diff options
| author | Jeff Garzik <jgarzik@pobox.com> | 2004-10-21 15:58:05 -0400 |
|---|---|---|
| committer | Jeff Garzik <jgarzik@pobox.com> | 2004-10-21 15:58:05 -0400 |
| commit | f5b8a851511cbbc1d9354258fc1840ff2c9eadc5 (patch) | |
| tree | 5400038e3a535107a8e20496d85afee696d8ce28 /include | |
| parent | 0d554d392aa7adce368f13d6068679c18b0fa50e (diff) | |
| parent | 77752839e8a15553eda7f2396f894eae80409a8d (diff) | |
Merge pobox.com:/garz/repo/libata-dev/export-simulator
into pobox.com:/garz/repo/libata-2.6
Diffstat (limited to 'include')
197 files changed, 2342 insertions, 61765 deletions
diff --git a/include/asm-alpha/io.h b/include/asm-alpha/io.h index 9e9de8e27a84..77b549de4a2e 100644 --- a/include/asm-alpha/io.h +++ b/include/asm-alpha/io.h @@ -658,6 +658,16 @@ isa_check_signature(unsigned long offset, const unsigned char *sig, long len) #define dma_cache_wback(_start,_size) do { } while (0) #define dma_cache_wback_inv(_start,_size) do { } while (0) +/* + * Some mucking forons use if[n]def writeq to check if platform has it. + * It's a bloody bad idea and we probably want ARCH_HAS_WRITEQ for them + * to play with; for now just use cpp anti-recursion logics and make sure + * that damn thing is defined and expands to itself. + */ + +#define writeq writeq +#define readq readq + #endif /* __KERNEL__ */ #endif /* __ALPHA_IO_H */ diff --git a/include/asm-alpha/pgtable.h b/include/asm-alpha/pgtable.h index 3f1ed39d25e4..eb388b7600e7 100644 --- a/include/asm-alpha/pgtable.h +++ b/include/asm-alpha/pgtable.h @@ -328,7 +328,7 @@ extern inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) #endif #define io_remap_page_range(vma, start, busaddr, size, prot) \ - remap_page_range(vma, start, virt_to_phys((void *)__ioremap(busaddr, size)), size, prot) + remap_pfn_range(vma, start, virt_to_phys(ioremap(busaddr, size)) >> PAGE_SHIFT, size, prot) #define pte_ERROR(e) \ printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e)) diff --git a/include/asm-arm/arch-integrator/platform.h b/include/asm-arm/arch-integrator/platform.h index 09ec7902f4bf..6b67e41669f4 100644 --- a/include/asm-arm/arch-integrator/platform.h +++ b/include/asm-arm/arch-integrator/platform.h @@ -457,10 +457,6 @@ #define mSEC_25 (mSEC_1 * 25) #define SEC_1 (mSEC_1 * 1000) -#ifndef __ASSEMBLY__ -extern void integrator_time_init(unsigned long, unsigned int); -#endif - #define INTEGRATOR_CSR_BASE 0x10000000 #define INTEGRATOR_CSR_SIZE 0x10000000 diff --git a/include/asm-arm/arch-integrator/time.h b/include/asm-arm/arch-integrator/time.h index 01729e4d0644..8b137891791f 100644 --- a/include/asm-arm/arch-integrator/time.h +++ b/include/asm-arm/arch-integrator/time.h @@ -1,159 +1 @@ -/* - * linux/include/asm-arm/arch-integrator/time.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#include <asm/system.h> -#include <asm/leds.h> -#include <asm/mach-types.h> -/* - * Where is the timer (VA)? - */ -#define TIMER0_VA_BASE (IO_ADDRESS(INTEGRATOR_CT_BASE)+0x00000000) -#define TIMER1_VA_BASE (IO_ADDRESS(INTEGRATOR_CT_BASE)+0x00000100) -#define TIMER2_VA_BASE (IO_ADDRESS(INTEGRATOR_CT_BASE)+0x00000200) -#define VA_IC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE) - -/* - * How long is the timer interval? - */ -#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10) -#if TIMER_INTERVAL >= 0x100000 -#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC) -#elif TIMER_INTERVAL >= 0x10000 -#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC) -#else -#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC) -#endif - -#define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable */ - -/* - * What does it look like? - */ -typedef struct TimerStruct { - unsigned long TimerLoad; - unsigned long TimerValue; - unsigned long TimerControl; - unsigned long TimerClear; -} TimerStruct_t; - -extern unsigned long (*gettimeoffset)(void); - -static unsigned long timer_reload; - -/* - * Returns number of ms since last clock interrupt. Note that interrupts - * will have been disabled by do_gettimeoffset() - */ -static unsigned long integrator_gettimeoffset(void) -{ - volatile TimerStruct_t *timer1 = (TimerStruct_t *)TIMER1_VA_BASE; - unsigned long ticks1, ticks2, status; - - /* - * Get the current number of ticks. Note that there is a race - * condition between us reading the timer and checking for - * an interrupt. We get around this by ensuring that the - * counter has not reloaded between our two reads. - */ - ticks2 = timer1->TimerValue & 0xffff; - do { - ticks1 = ticks2; - status = __raw_readl(VA_IC_BASE + IRQ_RAW_STATUS); - ticks2 = timer1->TimerValue & 0xffff; - } while (ticks2 > ticks1); - - /* - * Number of ticks since last interrupt. - */ - ticks1 = timer_reload - ticks2; - - /* - * Interrupt pending? If so, we've reloaded once already. - */ - if (status & (1 << IRQ_TIMERINT1)) - ticks1 += timer_reload; - - /* - * Convert the ticks to usecs - */ - return TICKS2USECS(ticks1); -} - -/* - * IRQ handler for the timer - */ -static irqreturn_t -integrator_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) -{ - volatile TimerStruct_t *timer1 = (volatile TimerStruct_t *)TIMER1_VA_BASE; - - // ...clear the interrupt - timer1->TimerClear = 1; - - do_leds(); - do_timer(regs); -#ifndef CONFIG_SMP - update_process_times(user_mode(regs)); -#endif - do_profile(regs); - - return IRQ_HANDLED; -} - -/* - * Set up timer interrupt, and return the current time in seconds. - */ -void __init time_init(void) -{ - volatile TimerStruct_t *timer0 = (volatile TimerStruct_t *)TIMER0_VA_BASE; - volatile TimerStruct_t *timer1 = (volatile TimerStruct_t *)TIMER1_VA_BASE; - volatile TimerStruct_t *timer2 = (volatile TimerStruct_t *)TIMER2_VA_BASE; - unsigned int timer_ctrl = 0x80 | 0x40; /* periodic */ - - if (machine_is_integrator()) { - timer_reload = 1000000 * TICKS_PER_uSEC / HZ; - } else if (machine_is_cintegrator()) { - timer_reload = 1000000 / HZ; - timer_ctrl |= TIMER_CTRL_IE; - } - if (timer_reload > 0x100000) { - timer_reload >>= 8; - timer_ctrl |= 0x08; /* /256 */ - } else if (timer_reload > 0x010000) { - timer_reload >>= 4; - timer_ctrl |= 0x04; /* /16 */ - } - - /* - * Initialise to a known state (all timers off) - */ - timer0->TimerControl = 0; - timer1->TimerControl = 0; - timer2->TimerControl = 0; - - timer1->TimerLoad = timer_reload; - timer1->TimerValue = timer_reload; - timer1->TimerControl = timer_ctrl; - - /* - * Make irqs happen for the system timer - */ - timer_irq.handler = integrator_timer_interrupt; - setup_irq(IRQ_TIMERINT1, &timer_irq); - gettimeoffset = integrator_gettimeoffset; -} diff --git a/include/asm-arm/arch-ixp2000/platform.h b/include/asm-arm/arch-ixp2000/platform.h index 9f4e315d5f1c..7a24461841b7 100644 --- a/include/asm-arm/arch-ixp2000/platform.h +++ b/include/asm-arm/arch-ixp2000/platform.h @@ -117,6 +117,7 @@ static inline unsigned int ixp2000_is_pcimaster(void) void ixp2000_map_io(void); void ixp2000_init_irq(void); void ixp2000_init_time(unsigned long); +unsigned long ixp2000_gettimeoffset(void); struct pci_sys_data; diff --git a/include/asm-arm/arch-ixp4xx/platform.h b/include/asm-arm/arch-ixp4xx/platform.h index b8ea57968d4a..fc9d710184f3 100644 --- a/include/asm-arm/arch-ixp4xx/platform.h +++ b/include/asm-arm/arch-ixp4xx/platform.h @@ -53,12 +53,14 @@ struct ixp4xx_i2c_pins { }; +struct sys_timer; + /* * Functions used by platform-level setup code */ extern void ixp4xx_map_io(void); extern void ixp4xx_init_irq(void); -extern void ixp4xx_init_time(void); +extern struct sys_timer ixp4xx_timer; extern void ixp4xx_pci_preinit(void); struct pci_sys_data; extern int ixp4xx_setup(int nr, struct pci_sys_data *sys); diff --git a/include/asm-arm/arch-s3c2410/regs-watchdog.h b/include/asm-arm/arch-s3c2410/regs-watchdog.h index f375d93c89d5..b09d5107a1eb 100644 --- a/include/asm-arm/arch-s3c2410/regs-watchdog.h +++ b/include/asm-arm/arch-s3c2410/regs-watchdog.h @@ -38,6 +38,7 @@ #define S3C2410_WTCON_DIV128 (3<<3) #define S3C2410_WTCON_PRESCALE(x) ((x) << 8) +#define S3C2410_WTCON_PRESCALE_MASK (0xff00) #endif /* __ASM_ARCH_REGS_WATCHDOG_H */ diff --git a/include/asm-arm/atomic.h b/include/asm-arm/atomic.h index 24208a2dabe8..dc96af6e9caa 100644 --- a/include/asm-arm/atomic.h +++ b/include/asm-arm/atomic.h @@ -149,6 +149,8 @@ static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) #define atomic_inc_and_test(v) (atomic_add_return(1, v) == 0) #define atomic_dec_and_test(v) (atomic_sub_return(1, v) == 0) +#define atomic_inc_return(v) (atomic_add_return(1, v)) +#define atomic_dec_return(v) (atomic_sub_return(1, v)) #define atomic_add_negative(i,v) (atomic_add_return(i, v) < 0) diff --git a/include/asm-arm/delay.h b/include/asm-arm/delay.h index 4ebcea03406d..1704360e9699 100644 --- a/include/asm-arm/delay.h +++ b/include/asm-arm/delay.h @@ -1,15 +1,23 @@ -#ifndef __ASM_ARM_DELAY_H -#define __ASM_ARM_DELAY_H - /* - * Copyright (C) 1995 Russell King + * Copyright (C) 1995-2004 Russell King * * Delay routines, using a pre-computed "loops_per_second" value. */ +#ifndef __ASM_ARM_DELAY_H +#define __ASM_ARM_DELAY_H extern void __delay(int loops); /* + * This function intentionally does not exist; if you see references to + * it, it means that you're calling udelay() with an out of range value. + * + * With currently imposed limits, this means that we support a max delay + * of 2000us and 671 bogomips + */ +extern void __bad_udelay(void); + +/* * division by multiplication: you don't have to worry about * loss of precision. * @@ -19,14 +27,16 @@ extern void __delay(int loops); * first constant multiplications gets optimized away if the delay is * a constant) */ -extern void udelay(unsigned long usecs); +extern void __udelay(unsigned long usecs); +extern void __const_udelay(unsigned long); -static inline unsigned long muldiv(unsigned long a, unsigned long b, unsigned long c) -{ - return a * b / c; -} +#define MAX_UDELAY_MS 2 - +#define udelay(n) \ + (__builtin_constant_p(n) ? \ + ((n) > (MAX_UDELAY_MS * 1000) ? __bad_udelay() : \ + __const_udelay((n) * 0x68dbul)) : \ + __udelay(n)) #endif /* defined(_ARM_DELAY_H) */ diff --git a/include/asm-arm/hardirq.h b/include/asm-arm/hardirq.h index 3f734c4de7f0..8cf189b44f33 100644 --- a/include/asm-arm/hardirq.h +++ b/include/asm-arm/hardirq.h @@ -8,10 +8,6 @@ typedef struct { unsigned int __softirq_pending; - unsigned int __local_irq_count; - unsigned int __local_bh_count; - unsigned int __syscall_count; - struct task_struct * __ksoftirqd_task; /* waitqueue is too large */ } ____cacheline_aligned irq_cpustat_t; #include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */ @@ -52,7 +48,6 @@ typedef struct { #define irq_enter() (preempt_count() += HARDIRQ_OFFSET) -#ifndef CONFIG_SMP extern asmlinkage void __do_softirq(void); #define irq_exit() \ @@ -62,6 +57,5 @@ extern asmlinkage void __do_softirq(void); __do_softirq(); \ preempt_enable_no_resched(); \ } while (0) -#endif #endif /* __ASM_HARDIRQ_H */ diff --git a/include/asm-arm/mach/arch.h b/include/asm-arm/mach/arch.h index 5c37b709fe9f..993467c37b5b 100644 --- a/include/asm-arm/mach/arch.h +++ b/include/asm-arm/mach/arch.h @@ -12,6 +12,7 @@ struct tag; struct meminfo; +struct sys_timer; struct machine_desc { /* @@ -39,7 +40,7 @@ struct machine_desc { struct meminfo *); void (*map_io)(void);/* IO mapping function */ void (*init_irq)(void); - void (*init_time)(void); + struct sys_timer *timer; /* system tick timer */ void (*init_machine)(void); }; @@ -82,9 +83,6 @@ const struct machine_desc __mach_desc_##_type \ #define INITIRQ(_func) \ .init_irq = _func, -#define INITTIME(_func) \ - .init_time = _func, - #define INIT_MACHINE(_func) \ .init_machine = _func, diff --git a/include/asm-arm/mach/time.h b/include/asm-arm/mach/time.h index 51728edf7ba4..5cf4fd659fd5 100644 --- a/include/asm-arm/mach/time.h +++ b/include/asm-arm/mach/time.h @@ -10,13 +10,44 @@ #ifndef __ASM_ARM_MACH_TIME_H #define __ASM_ARM_MACH_TIME_H -extern void (*init_arch_time)(void); +#include <linux/sysdev.h> -extern int (*set_rtc)(void); -extern unsigned long (*gettimeoffset)(void); +/* + * This is our kernel timer structure. + * + * - init + * Initialise the kernels jiffy timer source, claim interrupt + * using setup_irq. This is called early on during initialisation + * while interrupts are still disabled on the local CPU. + * - suspend + * Suspend the kernel jiffy timer source, if necessary. This + * is called with interrupts disabled, after all normal devices + * have been suspended. If no action is required, set this to + * NULL. + * - resume + * Resume the kernel jiffy timer source, if necessary. This + * is called with interrupts disabled before any normal devices + * are resumed. If no action is required, set this to NULL. + * - offset + * Return the timer offset in microseconds since the last timer + * interrupt. Note: this must take account of any unprocessed + * timer interrupt which may be pending. + */ +struct sys_timer { + struct sys_device dev; + void (*init)(void); + void (*suspend)(void); + void (*resume)(void); + unsigned long (*offset)(void); +}; +extern struct sys_timer *system_timer; extern void timer_tick(struct pt_regs *); +/* + * Kernel time keeping support. + */ +extern int (*set_rtc)(void); extern void save_time_delta(struct timespec *delta, struct timespec *rtc); extern void restore_time_delta(struct timespec *delta, struct timespec *rtc); diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h index 14ac954a1c52..c8247312ced3 100644 --- a/include/asm-arm/pgtable.h +++ b/include/asm-arm/pgtable.h @@ -412,7 +412,7 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; * into virtual address `from' */ #define io_remap_page_range(vma,from,phys,size,prot) \ - remap_page_range(vma,from,phys,size,prot) + remap_pfn_range(vma, from, (phys) >> PAGE_SHIFT, size, prot) #define pgtable_cache_init() do { } while (0) diff --git a/include/asm-arm/rtc.h b/include/asm-arm/rtc.h new file mode 100644 index 000000000000..c3e330ded860 --- /dev/null +++ b/include/asm-arm/rtc.h @@ -0,0 +1,45 @@ +/* + * linux/include/asm-arm/rtc.h + * + * Copyright (C) 2003 Deep Blue Solutions Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef ASMARM_RTC_H +#define ASMARM_RTC_H + +struct module; + +struct rtc_ops { + struct module *owner; + int (*open)(void); + void (*release)(void); + int (*ioctl)(unsigned int, unsigned long); + + void (*read_time)(struct rtc_time *); + int (*set_time)(struct rtc_time *); + void (*read_alarm)(struct rtc_wkalrm *); + int (*set_alarm)(struct rtc_wkalrm *); + int (*proc)(char *buf); +}; + +void rtc_time_to_tm(unsigned long, struct rtc_time *); +int rtc_tm_to_time(struct rtc_time *, unsigned long *); +void rtc_next_alarm_time(struct rtc_time *, struct rtc_time *, struct rtc_time *); +void rtc_update(unsigned long, unsigned long); +int register_rtc(struct rtc_ops *); +void unregister_rtc(struct rtc_ops *); + +static inline int rtc_periodic_alarm(struct rtc_time *tm) +{ + return (tm->tm_year == -1) || + ((unsigned)tm->tm_mon >= 12) || + ((unsigned)(tm->tm_mday - 1) >= 31) || + ((unsigned)tm->tm_hour > 23) || + ((unsigned)tm->tm_min > 59) || + ((unsigned)tm->tm_sec > 59); +} + +#endif diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h index 7572ac4ff5e5..e25c17ee6288 100644 --- a/include/asm-arm/system.h +++ b/include/asm-arm/system.h @@ -282,7 +282,7 @@ do { \ /* * Enable FIQs */ -#define __stf() \ +#define local_fiq_enable() \ ({ \ unsigned long temp; \ __asm__ __volatile__( \ @@ -297,7 +297,7 @@ do { \ /* * Disable FIQs */ -#define __clf() \ +#define local_fiq_disable() \ ({ \ unsigned long temp; \ __asm__ __volatile__( \ @@ -331,6 +331,13 @@ do { \ : "r" (x) \ : "memory", "cc") +#define irqs_disabled() \ +({ \ + unsigned long flags; \ + local_save_flags(flags); \ + flags & PSR_I_BIT; \ +}) + #ifdef CONFIG_SMP #error SMP not supported @@ -346,16 +353,6 @@ do { \ #define smp_wmb() barrier() #define smp_read_barrier_depends() do { } while(0) -#define clf() __clf() -#define stf() __stf() - -#define irqs_disabled() \ -({ \ - unsigned long flags; \ - local_save_flags(flags); \ - flags & PSR_I_BIT; \ -}) - #if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) /* * On the StrongARM, "swp" is terminally broken since it bypasses the diff --git a/include/asm-arm/thread_info.h b/include/asm-arm/thread_info.h index 1a362ca41476..1dff9bf3f021 100644 --- a/include/asm-arm/thread_info.h +++ b/include/asm-arm/thread_info.h @@ -76,6 +76,8 @@ struct thread_info { #define init_thread_info (init_thread_union.thread_info) #define init_stack (init_thread_union.stack) +#define THREAD_SIZE 8192 + /* * how to get the thread information struct from C */ @@ -84,11 +86,9 @@ static inline struct thread_info *current_thread_info(void) __attribute_const__; static inline struct thread_info *current_thread_info(void) { register unsigned long sp asm ("sp"); - return (struct thread_info *)(sp & ~0x1fff); + return (struct thread_info *)(sp & ~(THREAD_SIZE - 1)); } -#define THREAD_SIZE (8192) - extern struct thread_info *alloc_thread_info(struct task_struct *task); extern void free_thread_info(struct thread_info *); diff --git a/include/asm-arm26/atomic.h b/include/asm-arm26/atomic.h index 5697fc898593..56fa1a3038fa 100644 --- a/include/asm-arm26/atomic.h +++ b/include/asm-arm26/atomic.h @@ -105,6 +105,27 @@ static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) local_irq_restore(flags); } +static inline int atomic_add_return(int i, volatile atomic_t *v) +{ + unsigned long flags; + int val; + + local_irq_save(flags); + val = v->counter + i; + v->counter = val; + local_irq_restore(flags); + + return val; +} + +static inline int atomic_sub_return(int i, volatile atomic_t *v) +{ + return atomic_add_return(-i, v); +} + +#define atomic_inc_return(v) (atomic_add_return(1,v)) +#define atomic_dec_return(v) (atomic_sub_return(1,v)) + /* Atomic operations are already serializing on ARM */ #define smp_mb__before_atomic_dec() barrier() #define smp_mb__after_atomic_dec() barrier() diff --git a/include/asm-arm26/pgtable.h b/include/asm-arm26/pgtable.h index d8a0f65c6eca..a8647efc29ad 100644 --- a/include/asm-arm26/pgtable.h +++ b/include/asm-arm26/pgtable.h @@ -288,7 +288,7 @@ static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) * into virtual address `from' */ #define io_remap_page_range(vma,from,phys,size,prot) \ - remap_page_range(vma,from,phys,size,prot) + remap_pfn_range(vma, from, (phys) >> PAGE_SHIFT, size, prot) #endif /* !__ASSEMBLY__ */ diff --git a/include/asm-generic/dma-mapping-broken.h b/include/asm-generic/dma-mapping-broken.h index e3185b194c3e..fd9de9502dff 100644 --- a/include/asm-generic/dma-mapping-broken.h +++ b/include/asm-generic/dma-mapping-broken.h @@ -9,7 +9,7 @@ dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, int flag) { BUG(); - return 0; + return NULL; } static inline void diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h index bb340cb5cb03..da1b3ba89b3e 100644 --- a/include/asm-generic/vmlinux.lds.h +++ b/include/asm-generic/vmlinux.lds.h @@ -24,6 +24,9 @@ VMLINUX_SYMBOL(__start_pci_fixups_final) = .; \ *(.pci_fixup_final) \ VMLINUX_SYMBOL(__end_pci_fixups_final) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_enable) = .; \ + *(.pci_fixup_enable) \ + VMLINUX_SYMBOL(__end_pci_fixups_enable) = .; \ } \ \ /* Kernel symbol table: Normal symbols */ \ diff --git a/include/asm-h8300/pgtable.h b/include/asm-h8300/pgtable.h index 6c64b136cb2f..49d6c4a84764 100644 --- a/include/asm-h8300/pgtable.h +++ b/include/asm-h8300/pgtable.h @@ -50,7 +50,8 @@ extern int is_in_rom(unsigned long); * No page table caches to initialise */ #define pgtable_cache_init() do { } while (0) -#define io_remap_page_range remap_page_range +#define io_remap_page_range(vma, vaddr, paddr, size, prot) \ + remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot) /* * All 32bit addresses are effectively valid for vmalloc... diff --git a/include/asm-i386/atomic.h b/include/asm-i386/atomic.h index 4df45c5e4b16..509720be772a 100644 --- a/include/asm-i386/atomic.h +++ b/include/asm-i386/atomic.h @@ -2,6 +2,8 @@ #define __ARCH_I386_ATOMIC__ #include <linux/config.h> +#include <linux/compiler.h> +#include <asm/processor.h> /* * Atomic operations that C can't guarantee us. Useful for @@ -176,6 +178,46 @@ static __inline__ int atomic_add_negative(int i, atomic_t *v) return c; } +/** + * atomic_add_return - add and return + * @v: pointer of type atomic_t + * @i: integer value to add + * + * Atomically adds @i to @v and returns @i + @v + */ +static __inline__ int atomic_add_return(int i, atomic_t *v) +{ + int __i; +#ifdef CONFIG_M386 + if(unlikely(boot_cpu_data.x86==3)) + goto no_xadd; +#endif + /* Modern 486+ processor */ + __i = i; + __asm__ __volatile__( + LOCK "xaddl %0, %1;" + :"=r"(i) + :"m"(v->counter), "0"(i)); + return i + __i; + +#ifdef CONFIG_M386 +no_xadd: /* Legacy 386 processor */ + local_irq_disable(); + __i = atomic_read(v); + atomic_set(v, i + __i); + local_irq_enable(); + return i + __i; +#endif +} + +static __inline__ int atomic_sub_return(int i, atomic_t *v) +{ + return atomic_add_return(-i,v); +} + +#define atomic_inc_return(v) (atomic_add_return(1,v)) +#define atomic_dec_return(v) (atomic_sub_return(1,v)) + /* These are x86-specific, used by some header files */ #define atomic_clear_mask(mask, addr) \ __asm__ __volatile__(LOCK "andl %0,%1" \ diff --git a/include/asm-i386/module.h b/include/asm-i386/module.h index 8ec1dae638cb..14cacba9ccbb 100644 --- a/include/asm-i386/module.h +++ b/include/asm-i386/module.h @@ -40,6 +40,8 @@ struct mod_arch_specific #define MODULE_PROC_FAMILY "ELAN " #elif defined CONFIG_MCRUSOE #define MODULE_PROC_FAMILY "CRUSOE " +#elif defined CONFIG_MEFFICEON +#define MODULE_PROC_FAMILY "EFFICEON " #elif defined CONFIG_MWINCHIPC6 #define MODULE_PROC_FAMILY "WINCHIPC6 " #elif defined CONFIG_MWINCHIP2 diff --git a/include/asm-i386/pgtable.h b/include/asm-i386/pgtable.h index b4ba1fd6f99d..dea2125185d1 100644 --- a/include/asm-i386/pgtable.h +++ b/include/asm-i386/pgtable.h @@ -404,7 +404,8 @@ extern pte_t *lookup_address(unsigned long address); #define kern_addr_valid(addr) (1) #endif /* !CONFIG_DISCONTIGMEM */ -#define io_remap_page_range remap_page_range +#define io_remap_page_range(vma, vaddr, paddr, size, prot) \ + remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot) #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY diff --git a/include/asm-ia64/machvec.h b/include/asm-ia64/machvec.h index ff881e2bf9fe..c86afb81cd02 100644 --- a/include/asm-ia64/machvec.h +++ b/include/asm-ia64/machvec.h @@ -62,14 +62,14 @@ typedef unsigned int ia64_mv_inl_t (unsigned long); typedef void ia64_mv_outb_t (unsigned char, unsigned long); typedef void ia64_mv_outw_t (unsigned short, unsigned long); typedef void ia64_mv_outl_t (unsigned int, unsigned long); -typedef unsigned char ia64_mv_readb_t (void *); -typedef unsigned short ia64_mv_readw_t (void *); -typedef unsigned int ia64_mv_readl_t (void *); -typedef unsigned long ia64_mv_readq_t (void *); -typedef unsigned char ia64_mv_readb_relaxed_t (void *); -typedef unsigned short ia64_mv_readw_relaxed_t (void *); -typedef unsigned int ia64_mv_readl_relaxed_t (void *); -typedef unsigned long ia64_mv_readq_relaxed_t (void *); +typedef unsigned char ia64_mv_readb_t (const volatile void __iomem *); +typedef unsigned short ia64_mv_readw_t (const volatile void __iomem *); +typedef unsigned int ia64_mv_readl_t (const volatile void __iomem *); +typedef unsigned long ia64_mv_readq_t (const volatile void __iomem *); +typedef unsigned char ia64_mv_readb_relaxed_t (const volatile void __iomem *); +typedef unsigned short ia64_mv_readw_relaxed_t (const volatile void __iomem *); +typedef unsigned int ia64_mv_readl_relaxed_t (const volatile void __iomem *); +typedef unsigned long ia64_mv_readq_relaxed_t (const volatile void __iomem *); static inline void machvec_noop (void) diff --git a/include/asm-ia64/machvec_sn2.h b/include/asm-ia64/machvec_sn2.h index 9334851e1500..ff4cef0057a3 100644 --- a/include/asm-ia64/machvec_sn2.h +++ b/include/asm-ia64/machvec_sn2.h @@ -117,6 +117,6 @@ extern ia64_mv_dma_supported sn_dma_supported; #define platform_dma_mapping_error sn_dma_mapping_error #define platform_dma_supported sn_dma_supported -#include <asm/sn/sn2/io.h> +#include <asm/sn/io.h> #endif /* _ASM_IA64_MACHVEC_SN2_H */ diff --git a/include/asm-ia64/pci.h b/include/asm-ia64/pci.h index 86f7e8ee1399..dfd58c28c080 100644 --- a/include/asm-ia64/pci.h +++ b/include/asm-ia64/pci.h @@ -105,6 +105,8 @@ struct pci_controller { #define PCI_CONTROLLER(busdev) ((struct pci_controller *) busdev->sysdata) #define pci_domain_nr(busdev) (PCI_CONTROLLER(busdev)->segment) +extern struct pci_ops pci_root_ops; + static inline int pci_name_bus(char *name, struct pci_bus *bus) { if (pci_domain_nr(bus) == 0) { diff --git a/include/asm-ia64/pgtable.h b/include/asm-ia64/pgtable.h index 085ef89dfb7b..28c82ee3ac33 100644 --- a/include/asm-ia64/pgtable.h +++ b/include/asm-ia64/pgtable.h @@ -452,7 +452,9 @@ extern void paging_init (void); #define pte_to_pgoff(pte) ((pte_val(pte) << 1) >> 3) #define pgoff_to_pte(off) ((pte_t) { ((off) << 2) | _PAGE_FILE }) -#define io_remap_page_range remap_page_range /* XXX is this right? */ +/* XXX is this right? */ +#define io_remap_page_range(vma, vaddr, paddr, size, prot) \ + remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot) /* * ZERO_PAGE is a global shared page that is always zero: used diff --git a/include/asm-ia64/sn/addrs.h b/include/asm-ia64/sn/addrs.h index 550365c7f4ef..1220d1f122d1 100644 --- a/include/asm-ia64/sn/addrs.h +++ b/include/asm-ia64/sn/addrs.h @@ -3,20 +3,192 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 1992-1999,2001-2003 Silicon Graphics, Inc. All rights reserved. + * Copyright (c) 1992-1999,2001-2004 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_ADDRS_H #define _ASM_IA64_SN_ADDRS_H -#include <asm/sn/sn2/addrs.h> + +/* McKinley Address Format: + * + * 4 4 3 3 3 3 + * 9 8 8 7 6 5 0 + * +-+---------+----+--------------+ + * |0| Node ID | AS | Node Offset | + * +-+---------+----+--------------+ + * + * Node ID: If bit 38 = 1, is ICE, else is SHUB + * AS: Address Space Identifier. Used only if bit 38 = 0. + * b'00: Local Resources and MMR space + * bit 35 + * 0: Local resources space + * node id: + * 0: IA64/NT compatibility space + * 2: Local MMR Space + * 4: Local memory, regardless of local node id + * 1: Global MMR space + * b'01: GET space. + * b'10: AMO space. + * b'11: Cacheable memory space. + * + * NodeOffset: byte offset + */ + +/* TIO address format: + * 4 4 3 3 3 3 3 0 + * 9 8 8 7 6 5 4 + * +-+----------+-+---+--------------+ + * |0| Node ID |0|CID| Node offset | + * +-+----------+-+---+--------------+ + * + * Node ID: if bit 38 == 1, is ICE. + * Bit 37: Must be zero. + * CID: Chiplet ID: + * b'01: TIO LB (Indicates TIO MMR access.) + * b'11: TIO ICE (indicates coretalk space access.) + * Node offset: byte offest. + */ + +/* + * Note that in both of the above address formats, bit + * 35 set indicates that the reference is to the + * shub or tio MMRs. + */ #ifndef __ASSEMBLY__ -#include <asm/sn/types.h> -#endif +typedef union ia64_sn2_pa { + struct { + unsigned long off : 36; + unsigned long as : 2; + unsigned long nasid: 11; + unsigned long fill : 15; + } f; + unsigned long l; + void *p; +} ia64_sn2_pa_t; +#endif + +#define TO_PHYS_MASK 0x0001ffcfffffffffUL /* Note - clear AS bits */ + + +/* Regions determined by AS */ +#define LOCAL_MMR_SPACE 0xc000008000000000UL /* Local MMR space */ +#define LOCAL_PHYS_MMR_SPACE 0x8000008000000000UL /* Local PhysicalMMR space */ +#define LOCAL_MEM_SPACE 0xc000010000000000UL /* Local Memory space */ +/* It so happens that setting bit 35 indicates a reference to the SHUB or TIO + * MMR space. + */ +#define GLOBAL_MMR_SPACE 0xc000000800000000UL /* Global MMR space */ +#define TIO_MMR_SPACE 0xc000000800000000UL /* TIO MMR space */ +#define ICE_MMR_SPACE 0xc000000000000000UL /* ICE MMR space */ +#define GLOBAL_PHYS_MMR_SPACE 0x0000000800000000UL /* Global Physical MMR space */ +#define GET_SPACE 0xe000001000000000UL /* GET space */ +#define AMO_SPACE 0xc000002000000000UL /* AMO space */ +#define CACHEABLE_MEM_SPACE 0xe000003000000000UL /* Cacheable memory space */ +#define UNCACHED 0xc000000000000000UL /* UnCacheable memory space */ +#define UNCACHED_PHYS 0x8000000000000000UL /* UnCacheable physical memory space */ + +#define PHYS_MEM_SPACE 0x0000003000000000UL /* physical memory space */ + +/* SN2 address macros */ +/* NID_SHFT has the right value for both SHUB and TIO addresses.*/ +#define NID_SHFT 38 +#define LOCAL_MMR_ADDR(a) (UNCACHED | LOCAL_MMR_SPACE | (a)) +#define LOCAL_MMR_PHYS_ADDR(a) (UNCACHED_PHYS | LOCAL_PHYS_MMR_SPACE | (a)) +#define LOCAL_MEM_ADDR(a) (LOCAL_MEM_SPACE | (a)) +#define REMOTE_ADDR(n,a) ((((unsigned long)(n))<<NID_SHFT) | (a)) +#define GLOBAL_MMR_ADDR(n,a) (UNCACHED | GLOBAL_MMR_SPACE | REMOTE_ADDR(n,a)) +#define GLOBAL_MMR_PHYS_ADDR(n,a) (UNCACHED_PHYS | GLOBAL_PHYS_MMR_SPACE | REMOTE_ADDR(n,a)) +#define GET_ADDR(n,a) (GET_SPACE | REMOTE_ADDR(n,a)) +#define AMO_ADDR(n,a) (UNCACHED | AMO_SPACE | REMOTE_ADDR(n,a)) +#define GLOBAL_MEM_ADDR(n,a) (CACHEABLE_MEM_SPACE | REMOTE_ADDR(n,a)) + +/* non-II mmr's start at top of big window space (4G) */ +#define BWIN_TOP 0x0000000100000000UL + +/* + * general address defines - for code common to SN0/SN1/SN2 + */ +#define CAC_BASE CACHEABLE_MEM_SPACE /* cacheable memory space */ +#define IO_BASE (UNCACHED | GLOBAL_MMR_SPACE) /* lower 4G maps II's XIO space */ +#define TIO_BASE (UNCACHED | ICE_MMR_SPACE) /* lower 4G maps TIO space */ +#define AMO_BASE (UNCACHED | AMO_SPACE) /* fetch & op space */ +#define MSPEC_BASE AMO_BASE /* fetch & op space */ +#define UNCAC_BASE (UNCACHED | CACHEABLE_MEM_SPACE) /* uncached global memory */ +#define GET_BASE GET_SPACE /* momentarily coherent remote mem. */ +#define CALIAS_BASE LOCAL_CACHEABLE_BASE /* cached node-local memory */ +#define UALIAS_BASE (UNCACHED | LOCAL_CACHEABLE_BASE) /* uncached node-local memory */ + +#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) +#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) +#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) +#define TO_MSPEC(x) (MSPEC_BASE | ((x) & TO_PHYS_MASK)) +#define TO_GET(x) (GET_BASE | ((x) & TO_PHYS_MASK)) +#define TO_CALIAS(x) (CALIAS_BASE | TO_NODE_ADDRSPACE(x)) +#define TO_UALIAS(x) (UALIAS_BASE | TO_NODE_ADDRSPACE(x)) +#define NODE_SIZE_BITS 36 /* node offset : bits <35:0> */ +#define BWIN_SIZE_BITS 29 /* big window size: 512M */ +#define TIO_BWIN_SIZE_BITS 30 /* big window size: 1G */ +#define NASID_BITS 11 /* bits <48:38> */ +#define NASID_BITMASK (0x7ffULL) +#define NASID_SHFT NID_SHFT +#define NASID_META_BITS 0 /* ???? */ +#define NASID_LOCAL_BITS 7 /* same router as SN1 */ + +#define NODE_ADDRSPACE_SIZE (1UL << NODE_SIZE_BITS) +#define NASID_MASK ((uint64_t) NASID_BITMASK << NASID_SHFT) +#define NASID_GET(_pa) (int) (((uint64_t) (_pa) >> \ + NASID_SHFT) & NASID_BITMASK) +#define PHYS_TO_DMA(x) ( ((x & NASID_MASK) >> 2) | \ + (x & (NODE_ADDRSPACE_SIZE - 1)) ) + +/* + * This address requires a chiplet id in bits 38-39. For DMA to memory, + * the chiplet id is zero. If we implement TIO-TIO dma, we might need + * to insert a chiplet id into this macro. However, it is our belief + * right now that this chiplet id will be ICE, which is also zero. + */ +#define PHYS_TO_TIODMA(x) ( ((x & NASID_MASK) << 2) | \ + (x & (NODE_ADDRSPACE_SIZE - 1)) ) + +#define CHANGE_NASID(n,x) ({ia64_sn2_pa_t _v; _v.l = (long) (x); _v.f.nasid = n; _v.p;}) -#define HUBREG_CAST (volatile mmr_t *) +#ifndef __ASSEMBLY__ +#define NODE_SWIN_BASE(nasid, widget) \ + ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \ + : RAW_NODE_SWIN_BASE(nasid, widget)) +#else +#define NODE_SWIN_BASE(nasid, widget) \ + (NODE_IO_BASE(nasid) + ((uint64_t) (widget) << SWIN_SIZE_BITS)) +#define LOCAL_SWIN_BASE(widget) \ + (UNCACHED | LOCAL_MMR_SPACE | (((uint64_t) (widget) << SWIN_SIZE_BITS))) +#endif /* __ASSEMBLY__ */ + +/* + * The following definitions pertain to the IO special address + * space. They define the location of the big and little windows + * of any given node. + */ + +#define BWIN_SIZE (1UL << BWIN_SIZE_BITS) +#define BWIN_SIZEMASK (BWIN_SIZE - 1) +#define BWIN_WIDGET_MASK 0x7 +#define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE) +#define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \ + ((uint64_t) (bigwin) << BWIN_SIZE_BITS)) + +#define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK) +#define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK) + +#define TIO_BWIN_WINDOW_SELECT_MASK 0x7 +#define TIO_BWIN_WINDOWNUM(addr) (((addr) >> TIO_BWIN_SIZE_BITS) & TIO_BWIN_WINDOW_SELECT_MASK) + + +#ifndef __ASSEMBLY__ +#include <asm/sn/types.h> +#endif /* * The following macros are used to index to the beginning of a specific @@ -31,17 +203,11 @@ #define NODE_MSPEC_BASE(_n) (MSPEC_BASE + NODE_OFFSET(_n)) #define NODE_UNCAC_BASE(_n) (UNCAC_BASE + NODE_OFFSET(_n)) -#define TO_NODE(_n, _x) (NODE_OFFSET(_n) | ((_x) )) #define TO_NODE_CAC(_n, _x) (NODE_CAC_BASE(_n) | ((_x) & TO_PHYS_MASK)) -#define TO_NODE_UNCAC(_n, _x) (NODE_UNCAC_BASE(_n) | ((_x) & TO_PHYS_MASK)) -#define TO_NODE_MSPEC(_n, _x) (NODE_MSPEC_BASE(_n) | ((_x) & TO_PHYS_MASK)) -#define TO_NODE_HSPEC(_n, _x) (NODE_HSPEC_BASE(_n) | ((_x) & TO_PHYS_MASK)) - #define RAW_NODE_SWIN_BASE(nasid, widget) \ (NODE_IO_BASE(nasid) + ((uint64_t) (widget) << SWIN_SIZE_BITS)) -#define WIDGETID_GET(addr) ((unsigned char)((addr >> SWIN_SIZE_BITS) & 0xff)) /* * The following definitions pertain to the IO special address @@ -54,43 +220,20 @@ #define SWIN_SIZEMASK (SWIN_SIZE - 1) #define SWIN_WIDGET_MASK 0xF +#define TIO_SWIN_SIZE_BITS 28 +#define TIO_SWIN_SIZE (1UL << 28) +#define TIO_SWIN_SIZEMASK (SWIN_SIZE - 1) +#define TIO_SWIN_WIDGET_MASK 0x3 + /* * Convert smallwindow address to xtalk address. * * 'addr' can be physical or virtual address, but will be converted * to Xtalk address in the range 0 -> SWINZ_SIZEMASK */ -#define SWIN_WIDGETADDR(addr) ((addr) & SWIN_SIZEMASK) #define SWIN_WIDGETNUM(addr) (((addr) >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK) -/* - * Verify if addr belongs to small window address on node with "nasid" - * - * - * NOTE: "addr" is expected to be XKPHYS address, and NOT physical - * address - * - * - */ -#define NODE_SWIN_ADDR(nasid, addr) \ - (((addr) >= NODE_SWIN_BASE(nasid, 0)) && \ - ((addr) < (NODE_SWIN_BASE(nasid, HUB_NUM_WIDGET) + SWIN_SIZE)\ - )) -/* - * The following define the major position-independent aliases used - * in SN. - * LBOOT -- 256MB in size, reads in the LBOOT area result in - * uncached references to the local hub's boot prom and - * other directory-bus connected devices. - * IALIAS -- 8MB in size, reads in the IALIAS result in uncached - * references to the local hub's registers. - */ - -#define HUB_REGISTER_WIDGET 1 -#define IALIAS_BASE LOCAL_SWIN_BASE(HUB_REGISTER_WIDGET) -#define IALIAS_SIZE 0x800000 /* 8 Megabytes */ -#define IS_IALIAS(_a) (((_a) >= IALIAS_BASE) && \ - ((_a) < (IALIAS_BASE + IALIAS_SIZE))) +#define TIO_SWIN_WIDGETNUM(addr) (((addr) >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK) /* * The following macros produce the correct base virtual address for @@ -107,15 +250,13 @@ * As all other non-II mmr's located at the top of big window * space. */ -#define LOCAL_HUB_BASE(_x) (LOCAL_MMR_ADDR(_x) | (((~(_x)) & BWIN_TOP)>>8)) #define REMOTE_HUB_BASE(_x) \ (UNCACHED | GLOBAL_MMR_SPACE | \ (((~(_x)) & BWIN_TOP)>>8) | \ (((~(_x)) & BWIN_TOP)>>9) | (_x)) -#define LOCAL_HUB(_x) (HUBREG_CAST LOCAL_HUB_BASE(_x)) #define REMOTE_HUB(_n, _x) \ - (HUBREG_CAST (REMOTE_HUB_BASE(_x) | ((((long)(_n))<<NASID_SHFT)))) + ((uint64_t *)(REMOTE_HUB_BASE(_x) | ((((long)(_n))<<NASID_SHFT)))) /* @@ -126,12 +267,20 @@ * Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S(). * They're always safe. */ +/* + * LOCAL_HUB_ADDR doesn't need to be changed for TIO, since, by definition, + * there are no "local" TIOs. + */ #define LOCAL_HUB_ADDR(_x) \ - (((_x) & BWIN_TOP) ? (HUBREG_CAST (LOCAL_MMR_ADDR(_x))) \ - : (HUBREG_CAST (IALIAS_BASE + (_x)))) + (((_x) & BWIN_TOP) ? ((volatile uint64_t *)(LOCAL_MMR_ADDR(_x))) \ + : ((volatile uint64_t *)(IALIAS_BASE + (_x)))) #define REMOTE_HUB_ADDR(_n, _x) \ - (((_x) & BWIN_TOP) ? (HUBREG_CAST (GLOBAL_MMR_ADDR(_n, _x))) \ - : (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) + 0x800000 + (_x)))) + ((_n & 1) ? \ + /* TIO: */ \ + ((volatile uint64_t *)(GLOBAL_MMR_ADDR(_n, _x))) \ + : /* SHUB: */ \ + (((_x) & BWIN_TOP) ? ((volatile uint64_t *)(GLOBAL_MMR_ADDR(_n, _x))) \ + : ((volatile uint64_t *)(NODE_SWIN_BASE(_n, 1) + 0x800000 + (_x))))) #ifndef __ASSEMBLY__ @@ -152,7 +301,7 @@ * the base of the register space. */ #define HUB_REG_PTR(_base, _off) \ - (HUBREG_CAST ((unsigned long)(_base) + (__psunsigned_t)(_off))) + (volatile uint64_t *)((unsigned long)(_base) + (__psunsigned_t)(_off))) #define HUB_REG_PTR_L(_base, _off) \ HUB_L(HUB_REG_PTR((_base), (_off))) @@ -160,70 +309,4 @@ #define HUB_REG_PTR_S(_base, _off, _data) \ HUB_S(HUB_REG_PTR((_base), (_off)), (_data)) -/* - * Software structure locations -- permanently fixed - * See diagram in kldir.h - */ - -#define PHYS_RAMBASE 0x0 -#define K0_RAMBASE PHYS_TO_K0(PHYS_RAMBASE) - -#define ARCS_SPB_OFFSET 0x1000 -#define ARCS_SPB_ADDR(nasid) \ - PHYS_TO_K0(NODE_OFFSET(nasid) | ARCS_SPB_OFFSET) -#define ARCS_SPB_SIZE 0x0400 - -#define KLDIR_OFFSET 0x2000 -#define KLDIR_ADDR(nasid) \ - TO_NODE_CAC((nasid), KLDIR_OFFSET) -#define KLDIR_SIZE 0x0400 - - -/* - * Software structure locations -- indirected through KLDIR - * See diagram in kldir.h - * - * Important: All low memory structures must only be accessed - * uncached, except for the symmon stacks. - */ - -#define KLI_LAUNCH 0 /* Dir. entries */ -#define KLI_KLCONFIG 1 -#define KLI_NMI 2 -#define KLI_GDA 3 -#define KLI_FREEMEM 4 -#define KLI_SYMMON_STK 5 -#define KLI_PI_ERROR 6 -#define KLI_KERN_VARS 7 -#define KLI_KERN_XP 8 -#define KLI_KERN_PARTID 9 - -#ifndef __ASSEMBLY__ - -#define KLD_BASE(nasid) ((kldir_ent_t *) KLDIR_ADDR(nasid)) -#define KLD_LAUNCH(nasid) (KLD_BASE(nasid) + KLI_LAUNCH) -#define KLD_NMI(nasid) (KLD_BASE(nasid) + KLI_NMI) -#define KLD_KLCONFIG(nasid) (KLD_BASE(nasid) + KLI_KLCONFIG) -#define KLD_PI_ERROR(nasid) (KLD_BASE(nasid) + KLI_PI_ERROR) -#define KLD_GDA(nasid) (KLD_BASE(nasid) + KLI_GDA) -#define KLD_SYMMON_STK(nasid) (KLD_BASE(nasid) + KLI_SYMMON_STK) -#define KLD_FREEMEM(nasid) (KLD_BASE(nasid) + KLI_FREEMEM) -#define KLD_KERN_VARS(nasid) (KLD_BASE(nasid) + KLI_KERN_VARS) -#define KLD_KERN_XP(nasid) (KLD_BASE(nasid) + KLI_KERN_XP) -#define KLD_KERN_PARTID(nasid) (KLD_BASE(nasid) + KLI_KERN_PARTID) - -#define KLCONFIG_OFFSET(nasid) ia64_sn_get_klconfig_addr(nasid) - -#define KLCONFIG_ADDR(nasid) \ - TO_NODE_CAC((nasid), KLCONFIG_OFFSET(nasid)) -#define KLCONFIG_SIZE(nasid) KLD_KLCONFIG(nasid)->size - -#define GDA_ADDR(nasid) KLD_GDA(nasid)->pointer -#define GDA_SIZE(nasid) KLD_GDA(nasid)->size - -#define NODE_OFFSET_TO_K0(_nasid, _off) \ - (CACHEABLE_MEM_SPACE | NODE_OFFSET(_nasid) | (_off)) - -#endif /* __ASSEMBLY__ */ - #endif /* _ASM_IA64_SN_ADDRS_H */ diff --git a/include/asm-ia64/sn/arch.h b/include/asm-ia64/sn/arch.h index 0faf9d7dd9a8..0893ae2feb5c 100644 --- a/include/asm-ia64/sn/arch.h +++ b/include/asm-ia64/sn/arch.h @@ -5,7 +5,7 @@ * * SGI specific setup. * - * Copyright (C) 1995-1997,1999,2001-2003 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1995-1997,1999,2001-2004 Silicon Graphics, Inc. All rights reserved. * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org) */ #ifndef _ASM_IA64_SN_ARCH_H @@ -15,20 +15,24 @@ #include <asm/sn/types.h> #include <asm/sn/sn_cpuid.h> -typedef u64 shubreg_t; -typedef u64 hubreg_t; -typedef u64 mmr_t; +/* + * This is the maximum number of nodes that can be part of a kernel. + * Effectively, it's the maximum number of compact node ids (cnodeid_t). + * This is not necessarily the same as MAX_NASIDS. + */ +#define MAX_COMPACT_NODES 2048 + typedef u64 nic_t; +#define NASID_TO_COMPACT_NODEID(nasid) (nasid_to_cnodeid(nasid)) +#define COMPACT_TO_NASID_NODEID(cnode) (cnodeid_to_nasid(cnode)) + + #define INVALID_NASID ((nasid_t)-1) -#define INVALID_CNODEID ((cnodeid_t)-1) -#define INVALID_PNODEID ((pnodeid_t)-1) #define INVALID_SLAB (slabid_t)-1 #define INVALID_MODULE ((moduleid_t)-1) #define INVALID_PARTID ((partid_t)-1) -extern cpuid_t cnodetocpu(cnodeid_t); extern void sn_flush_all_caches(long addr, long bytes); -extern int is_fine_dirmode(void); #endif /* _ASM_IA64_SN_ARCH_H */ diff --git a/include/asm-ia64/sn/bte.h b/include/asm-ia64/sn/bte.h index 1b643d1e0820..0ec27f99c181 100644 --- a/include/asm-ia64/sn/bte.h +++ b/include/asm-ia64/sn/bte.h @@ -55,7 +55,9 @@ /* macro to force the IBCT0 value valid */ #define BTE_VALID_MODE(x) ((x) & (IBCT_NOTIFY | IBCT_ZFIL_MODE)) -#define BTE_ACTIVE (IBLS_BUSY | IBLS_ERROR) +#define BTE_ACTIVE (IBLS_BUSY | IBLS_ERROR) +#define BTE_WORD_AVAILABLE (IBLS_BUSY << 1) +#define BTE_WORD_BUSY (~BTE_WORD_AVAILABLE) /* * Some macros to simplify reading. diff --git a/include/asm-ia64/sn/cdl.h b/include/asm-ia64/sn/cdl.h deleted file mode 100644 index 0af675f6e14c..000000000000 --- a/include/asm-ia64/sn/cdl.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_CDL_H -#define _ASM_IA64_SN_CDL_H - -#ifdef __KERNEL__ -#include <asm/sn/sgi.h> -#endif - -struct cdl { - int part_num; /* Part part number */ - int mfg_num; /* Part MFG number */ - int (*attach)(vertex_hdl_t); /* Attach routine */ -}; - - -/* - * cdl: connection/driver list - * - * support code for bus infrastructure for busses - * that have self-identifying devices; initially - * constructed for xtalk, pciio and gioio modules. - */ -typedef struct cdl *cdl_p; - -/* - * cdl_add_connpt: add a connection point - * - * Calls the attach routines of all the drivers on - * the list that match this connection point, in - * the order that they were added to the list. - */ -extern int cdl_add_connpt(int key1, - int key2, - vertex_hdl_t conn, - int drv_flags); -#endif /* _ASM_IA64_SN_CDL_H */ diff --git a/include/asm-ia64/sn/clksupport.h b/include/asm-ia64/sn/clksupport.h index 2960e6ec1b61..d340c365a824 100644 --- a/include/asm-ia64/sn/clksupport.h +++ b/include/asm-ia64/sn/clksupport.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2000-2003 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved. */ /* @@ -14,39 +14,15 @@ * * RTC_COUNTER_ADDR - contains the address of the counter * - * GET_RTC_COUNTER() - macro to read the value of the clock - * - * RTC_CYCLES_PER_SEC - clock frequency in ticks per second - * */ #ifndef _ASM_IA64_SN_CLKSUPPORT_H #define _ASM_IA64_SN_CLKSUPPORT_H -#include <asm/sn/arch.h> -#include <asm/sn/addrs.h> -#include <asm/sn/sn2/addrs.h> -#include <asm/sn/sn2/shubio.h> -#include <asm/sn/sn2/shub_mmr.h> - -typedef long clkreg_t; - extern unsigned long sn_rtc_cycles_per_second; -extern unsigned long sn_rtc_per_itc; - -#define RTC_MASK SH_RTC_MASK -#define RTC_COUNTER_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) -#define RTC_COMPARE_A_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) -#define RTC_COMPARE_B_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) -#define RTC_INT_PENDING_A_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) -#define RTC_INT_PENDING_B_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) -#define RTC_INT_ENABLED_A_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) -#define RTC_INT_ENABLED_B_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) -#define SN_RTC_PER_ITC_SHIFT 34 -#define GET_RTC_COUNTER() (*RTC_COUNTER_ADDR) -#define rtc_time() GET_RTC_COUNTER() +#define RTC_COUNTER_ADDR ((long *)LOCAL_MMR_ADDR(SH_RTC)) -#define RTC_CYCLES_PER_SEC sn_rtc_cycles_per_second +#define rtc_time() (*RTC_COUNTER_ADDR) #endif /* _ASM_IA64_SN_CLKSUPPORT_H */ diff --git a/include/asm-ia64/sn/dmamap.h b/include/asm-ia64/sn/dmamap.h deleted file mode 100644 index cee47278386b..000000000000 --- a/include/asm-ia64/sn/dmamap.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_DMAMAP_H -#define _ASM_IA64_SN_DMAMAP_H - -/* - * Definitions for allocating, freeing, and using DMA maps - */ - -/* - * DMA map types - */ -#define DMA_SCSI 0 -#define DMA_A24VME 1 /* Challenge/Onyx only */ -#define DMA_A32VME 2 /* Challenge/Onyx only */ -#define DMA_A64VME 3 /* SN0/Racer */ - -#define DMA_EISA 4 - -#define DMA_PCI32 5 /* SN0/Racer */ -#define DMA_PCI64 6 /* SN0/Racer */ - -/* - * DMA map structure as returned by dma_mapalloc() - */ -typedef struct dmamap { - int dma_type; /* Map type (see above) */ - int dma_adap; /* I/O adapter */ - int dma_index; /* Beginning map register to use */ - int dma_size; /* Number of map registers to use */ - paddr_t dma_addr; /* Corresponding bus addr for A24/A32 */ - unsigned long dma_virtaddr; /* Beginning virtual address that is mapped */ -} dmamap_t; - -/* standard flags values for pio_map routines, - * including {xtalk,pciio}_dmamap calls. - * NOTE: try to keep these in step with PIOMAP flags. - */ -#define DMAMAP_FIXED 0x1 -#define DMAMAP_NOSLEEP 0x2 -#define DMAMAP_INPLACE 0x4 - -#define DMAMAP_FLAGS 0x7 - -#endif /* _ASM_IA64_SN_DMAMAP_H */ diff --git a/include/asm-ia64/sn/driver.h b/include/asm-ia64/sn/driver.h deleted file mode 100644 index 77bd34379319..000000000000 --- a/include/asm-ia64/sn/driver.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_DRIVER_H -#define _ASM_IA64_SN_DRIVER_H - -#include <asm/sn/sgi.h> -#include <asm/types.h> - -/* -** Interface for device driver handle management. -** -** These functions are mostly for use by the loadable driver code, and -** for use by I/O bus infrastructure code. -*/ - -typedef struct device_driver_s *device_driver_t; - -/* == Driver thread priority support == */ -typedef int ilvl_t; - -struct eframe_s; -struct piomap; -struct dmamap; - -typedef unsigned long iobush_t; - -/* interrupt function */ -typedef void *intr_arg_t; -typedef void intr_func_f(intr_arg_t); -typedef intr_func_f *intr_func_t; - -#define INTR_ARG(n) ((intr_arg_t)(__psunsigned_t)(n)) - -/* system interrupt resource handle -- returned from intr_alloc */ -typedef struct intr_s *intr_t; -#define INTR_HANDLE_NONE ((intr_t)0) - -/* - * restore interrupt level value, returned from intr_block_level - * for use with intr_unblock_level. - */ -typedef void *rlvl_t; - - -/* - * A basic, platform-independent description of I/O requirements for - * a device. This structure is usually formed by lboot based on information - * in configuration files. It contains information about PIO, DMA, and - * interrupt requirements for a specific instance of a device. - * - * The pio description is currently unused. - * - * The dma description describes bandwidth characteristics and bandwidth - * allocation requirements. (TBD) - * - * The Interrupt information describes the priority of interrupt, desired - * destination, policy (TBD), whether this is an error interrupt, etc. - * For now, interrupts are targeted to specific CPUs. - */ - -typedef struct device_desc_s { - /* pio description (currently none) */ - - /* dma description */ - /* TBD: allocated badwidth requirements */ - - /* interrupt description */ - vertex_hdl_t intr_target; /* Hardware locator string */ - int intr_policy; /* TBD */ - ilvl_t intr_swlevel; /* software level for blocking intr */ - char *intr_name; /* name of interrupt, if any */ - - int flags; -} *device_desc_t; - -/* flag values */ -#define D_INTR_ISERR 0x1 /* interrupt is for error handling */ -#define D_IS_ASSOC 0x2 /* descriptor is associated with a dev */ -#define D_INTR_NOTHREAD 0x4 /* Interrupt handler isn't threaded. */ - -#define INTR_SWLEVEL_NOTHREAD_DEFAULT 0 /* Default - * Interrupt level in case of - * non-threaded interrupt - * handlers - */ -#endif /* _ASM_IA64_SN_DRIVER_H */ diff --git a/include/asm-ia64/sn/fetchop.h b/include/asm-ia64/sn/fetchop.h index 2fb5cfc774b7..5f4ad8f4b5d2 100644 --- a/include/asm-ia64/sn/fetchop.h +++ b/include/asm-ia64/sn/fetchop.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 2001-2003 Silicon Graphics, Inc. All rights reserved. + * Copyright (c) 2001-2004 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_FETCHOP_H diff --git a/include/asm-ia64/sn/geo.h b/include/asm-ia64/sn/geo.h index f8060cd7e2dd..f566343d25f8 100644 --- a/include/asm-ia64/sn/geo.h +++ b/include/asm-ia64/sn/geo.h @@ -3,43 +3,122 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_GEO_H #define _ASM_IA64_SN_GEO_H -/* Include a platform-specific geo.h. It must define at least: - * geoid_t: Geographic identifier data type - * geo_type_t: Data type for the kind of geoid this is - * GEO_TYPE_xxx: Values for geo_type_t vars, eg. GEO_TYPE_NODE - * GEO_MAX_LEN: The maximum length of a geoid, formatted for printing - */ +/* The geoid_t implementation below is based loosely on the pcfg_t + implementation in sys/SN/promcfg.h. */ + +/* Type declaractions */ + +/* Size of a geoid_t structure (must be before decl. of geoid_u) */ +#define GEOID_SIZE 8 /* Would 16 be better? The size can + be different on different platforms. */ + +#define MAX_SLABS 0xe /* slabs per module */ + +typedef unsigned char geo_type_t; + +/* Fields common to all substructures */ +typedef struct geo_any_s { + moduleid_t module; /* The module (box) this h/w lives in */ + geo_type_t type; /* What type of h/w is named by this geoid_t */ + slabid_t slab; /* The logical assembly within the module */ +} geo_any_t; + +/* Additional fields for particular types of hardware */ +typedef struct geo_node_s { + geo_any_t any; /* No additional fields needed */ +} geo_node_t; + +typedef struct geo_rtr_s { + geo_any_t any; /* No additional fields needed */ +} geo_rtr_t; + +typedef struct geo_iocntl_s { + geo_any_t any; /* No additional fields needed */ +} geo_iocntl_t; + +typedef struct geo_pcicard_s { + geo_iocntl_t any; + char bus; /* Bus/widget number */ + char slot; /* PCI slot number */ +} geo_pcicard_t; + +/* Subcomponents of a node */ +typedef struct geo_cpu_s { + geo_node_t node; + char slice; /* Which CPU on the node */ +} geo_cpu_t; + +typedef struct geo_mem_s { + geo_node_t node; + char membus; /* The memory bus on the node */ + char memslot; /* The memory slot on the bus */ +} geo_mem_t; + + +typedef union geoid_u { + geo_any_t any; + geo_node_t node; + geo_iocntl_t iocntl; + geo_pcicard_t pcicard; + geo_rtr_t rtr; + geo_cpu_t cpu; + geo_mem_t mem; + char padsize[GEOID_SIZE]; +} geoid_t; + + +/* Preprocessor macros */ + +#define GEO_MAX_LEN 48 /* max. formatted length, plus some pad: + module/001c07/slab/5/node/memory/2/slot/4 */ -#include <asm/sn/sn2/geo.h> +/* Values for geo_type_t */ +#define GEO_TYPE_INVALID 0 +#define GEO_TYPE_MODULE 1 +#define GEO_TYPE_NODE 2 +#define GEO_TYPE_RTR 3 +#define GEO_TYPE_IOCNTL 4 +#define GEO_TYPE_IOCARD 5 +#define GEO_TYPE_CPU 6 +#define GEO_TYPE_MEM 7 +#define GEO_TYPE_MAX (GEO_TYPE_MEM+1) -/* Declarations applicable to all platforms */ +/* Parameter for hwcfg_format_geoid_compt() */ +#define GEO_COMPT_MODULE 1 +#define GEO_COMPT_SLAB 2 +#define GEO_COMPT_IOBUS 3 +#define GEO_COMPT_IOSLOT 4 +#define GEO_COMPT_CPU 5 +#define GEO_COMPT_MEMBUS 6 +#define GEO_COMPT_MEMSLOT 7 -/* parameter for hwcfg_format_geoid() */ -#define GEO_FORMAT_HWGRAPH 1 -#define GEO_FORMAT_BRIEF 2 +#define GEO_INVALID_STR "<invalid>" -/* (the parameter for hwcfg_format_geoid_compt() is defined in the - * platform-specific geo.h file) */ +#define INVALID_NASID ((nasid_t)-1) +#define INVALID_CNODEID ((cnodeid_t)-1) +#define INVALID_PNODEID ((pnodeid_t)-1) +#define INVALID_SLAB (slabid_t)-1 +#define INVALID_MODULE ((moduleid_t)-1) +#define INVALID_PARTID ((partid_t)-1) -/* Routines for manipulating geoid_t values */ +static inline slabid_t geo_slab(geoid_t g) +{ + return (g.any.type == GEO_TYPE_INVALID) ? + INVALID_SLAB : g.any.slab; +} -extern moduleid_t geo_module(geoid_t g); -extern slabid_t geo_slab(geoid_t g); -extern geo_type_t geo_type(geoid_t g); -extern int geo_valid(geoid_t g); -extern int geo_cmp(geoid_t g0, geoid_t g1); -extern geoid_t geo_new(geo_type_t type, ...); +static inline moduleid_t geo_module(geoid_t g) +{ + return (g.any.type == GEO_TYPE_INVALID) ? + INVALID_MODULE : g.any.module; +} -extern geoid_t hwcfg_parse_geoid(char *buffer); -extern void hwcfg_format_geoid(char *buffer, geoid_t m, int fmt); -extern void hwcfg_format_geoid_compt(char *buffer, geoid_t m, int compt); -extern geoid_t hwcfg_geo_get_self(geo_type_t type); -extern geoid_t hwcfg_geo_get_by_nasid(geo_type_t type, nasid_t nasid); +extern geoid_t cnodeid_get_geoid(cnodeid_t cnode); #endif /* _ASM_IA64_SN_GEO_H */ diff --git a/include/asm-ia64/sn/hcl.h b/include/asm-ia64/sn/hcl.h deleted file mode 100644 index c6d961e68073..000000000000 --- a/include/asm-ia64/sn/hcl.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_HCL_H -#define _ASM_IA64_SN_HCL_H - -#include <linux/fs.h> -#include <asm/sn/sgi.h> - -extern vertex_hdl_t hwgraph_root; -extern vertex_hdl_t linux_busnum; - -void hwgraph_debug(char *, const char *, int, vertex_hdl_t, vertex_hdl_t, char *, ...); - -#if 1 -#define HWGRAPH_DEBUG(args...) hwgraph_debug(args) -#else -#define HWGRAPH_DEBUG(args) -#endif - -typedef long labelcl_info_place_t; -typedef long arbitrary_info_t; -typedef long arb_info_desc_t; - - -/* - * Reserve room in every vertex for 2 pieces of fast access indexed information - * Note that we do not save a pointer to the bdevsw or cdevsw[] tables anymore. - */ -#define HWGRAPH_NUM_INDEX_INFO 2 /* MAX Entries */ -#define HWGRAPH_CONNECTPT 0 /* connect point (aprent) */ -#define HWGRAPH_FASTINFO 1 /* callee's private handle */ - -/* - * Reserved edge_place_t values, used as the "place" parameter to edge_get_next. - * Every vertex in the hwgraph has up to 2 *implicit* edges. There is an implicit - * edge called "." that points to the current vertex. There is an implicit edge - * called ".." that points to the vertex' connect point. - */ -#define EDGE_PLACE_WANT_CURRENT 0 /* "." */ -#define EDGE_PLACE_WANT_CONNECTPT 1 /* ".." */ -#define EDGE_PLACE_WANT_REAL_EDGES 2 /* Get the first real edge */ -#define HWGRAPH_RESERVED_PLACES 2 - - -/* - * Special pre-defined edge labels. - */ -#define HWGRAPH_EDGELBL_HW "hw" -#define HWGRAPH_EDGELBL_DOT "." -#define HWGRAPH_EDGELBL_DOTDOT ".." - -#include <asm/sn/labelcl.h> -#define hwgraph_fastinfo_set(a,b) labelcl_info_replace_IDX(a, HWGRAPH_FASTINFO, b, NULL) -#define hwgraph_connectpt_set labelcl_info_connectpt_set -#define hwgraph_generate_path hwgfs_generate_path -#define hwgraph_path_to_vertex(a) hwgfs_find_handle(NULL, a, 0, 0, 0, 1) -#define hwgraph_vertex_unref(a) - -/* - * External declarations of EXPORTED SYMBOLS in hcl.c - */ -extern vertex_hdl_t hwgraph_register(vertex_hdl_t, const char *, - unsigned int, unsigned int, unsigned int, unsigned int, - umode_t, uid_t, gid_t, struct file_operations *, void *); - -extern int hwgraph_mk_symlink(vertex_hdl_t, const char *, unsigned int, - unsigned int, const char *, unsigned int, vertex_hdl_t *, void *); - -extern int hwgraph_vertex_destroy(vertex_hdl_t); - -extern int hwgraph_edge_add(vertex_hdl_t, vertex_hdl_t, char *); -extern int hwgraph_edge_get(vertex_hdl_t, char *, vertex_hdl_t *); - -extern arbitrary_info_t hwgraph_fastinfo_get(vertex_hdl_t); -extern vertex_hdl_t hwgraph_mk_dir(vertex_hdl_t, const char *, unsigned int, void *); - -extern int hwgraph_connectpt_set(vertex_hdl_t, vertex_hdl_t); -extern vertex_hdl_t hwgraph_connectpt_get(vertex_hdl_t); -extern int hwgraph_edge_get_next(vertex_hdl_t, char *, vertex_hdl_t *, unsigned int *); - -extern graph_error_t hwgraph_traverse(vertex_hdl_t, char *, vertex_hdl_t *); - -extern int hwgraph_vertex_get_next(vertex_hdl_t *, vertex_hdl_t *); -extern int hwgraph_path_add(vertex_hdl_t, char *, vertex_hdl_t *); -extern vertex_hdl_t hwgraph_path_to_dev(char *); -extern vertex_hdl_t hwgraph_block_device_get(vertex_hdl_t); -extern vertex_hdl_t hwgraph_char_device_get(vertex_hdl_t); -extern graph_error_t hwgraph_char_device_add(vertex_hdl_t, char *, char *, vertex_hdl_t *); -extern int hwgraph_path_add(vertex_hdl_t, char *, vertex_hdl_t *); -extern int hwgraph_info_add_LBL(vertex_hdl_t, char *, arbitrary_info_t); -extern int hwgraph_info_get_LBL(vertex_hdl_t, char *, arbitrary_info_t *); -extern int hwgraph_info_replace_LBL(vertex_hdl_t, char *, arbitrary_info_t, - arbitrary_info_t *); -extern int hwgraph_info_get_exported_LBL(vertex_hdl_t, char *, int *, arbitrary_info_t *); -extern int hwgraph_info_get_next_LBL(vertex_hdl_t, char *, arbitrary_info_t *, - labelcl_info_place_t *); -extern int hwgraph_info_export_LBL(vertex_hdl_t, char *, int); -extern int hwgraph_info_unexport_LBL(vertex_hdl_t, char *); -extern int hwgraph_info_remove_LBL(vertex_hdl_t, char *, arbitrary_info_t *); -extern char *vertex_to_name(vertex_hdl_t, char *, unsigned int); - -#endif /* _ASM_IA64_SN_HCL_H */ diff --git a/include/asm-ia64/sn/hcl_util.h b/include/asm-ia64/sn/hcl_util.h deleted file mode 100644 index faa5aaec6fe0..000000000000 --- a/include/asm-ia64/sn/hcl_util.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. - */ - -#ifndef _ASM_IA64_SN_HCL_UTIL_H -#define _ASM_IA64_SN_HCL_UTIL_H - -#include <asm/sn/sgi.h> - -extern char * dev_to_name(vertex_hdl_t, char *, unsigned int); -extern int device_master_set(vertex_hdl_t, vertex_hdl_t); -extern vertex_hdl_t device_master_get(vertex_hdl_t); -extern cnodeid_t master_node_get(vertex_hdl_t); -extern cnodeid_t nodevertex_to_cnodeid(vertex_hdl_t); -extern void mark_nodevertex_as_node(vertex_hdl_t, cnodeid_t); - -#endif /* _ASM_IA64_SN_HCL_UTIL_H */ diff --git a/include/asm-ia64/sn/hwgfs.h b/include/asm-ia64/sn/hwgfs.h deleted file mode 100644 index bbdd433234c5..000000000000 --- a/include/asm-ia64/sn/hwgfs.h +++ /dev/null @@ -1,36 +0,0 @@ -#ifndef _ASM_IA64_SN_HWGFS_H -#define _ASM_IA64_SN_HWGFS_H - -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. - */ - -#include <asm/types.h> - -typedef struct dentry *hwgfs_handle_t; - -extern hwgfs_handle_t hwgfs_register(hwgfs_handle_t dir, const char *name, - unsigned int flags, - unsigned int major, unsigned int minor, - umode_t mode, void *ops, void *info); -extern int hwgfs_mk_symlink(hwgfs_handle_t dir, const char *name, - unsigned int flags, const char *link, - hwgfs_handle_t *handle, void *info); -extern hwgfs_handle_t hwgfs_mk_dir(hwgfs_handle_t dir, const char *name, - void *info); -extern void hwgfs_unregister(hwgfs_handle_t de); - -extern hwgfs_handle_t hwgfs_find_handle(hwgfs_handle_t dir, const char *name, - unsigned int major,unsigned int minor, - char type, int traverse_symlinks); -extern hwgfs_handle_t hwgfs_get_parent(hwgfs_handle_t de); -extern int hwgfs_generate_path(hwgfs_handle_t de, char *path, int buflen); - -extern void *hwgfs_get_info(hwgfs_handle_t de); -extern int hwgfs_set_info(hwgfs_handle_t de, void *info); - -#endif /* _ASM_IA64_SN_HWGFS_H */ diff --git a/include/asm-ia64/sn/ifconfig_net.h b/include/asm-ia64/sn/ifconfig_net.h deleted file mode 100644 index 183c93bfa004..000000000000 --- a/include/asm-ia64/sn/ifconfig_net.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000-2003 Silicon Graphics, Inc. All rights reserved. - */ - -#ifndef _ASM_IA64_SN_IFCONFIG_NET_H -#define _ASM_IA64_SN_IFCONFIG_NET_H - -#define NETCONFIG_FILE "/tmp/ifconfig_net" -#define POUND_CHAR '#' -#define MAX_LINE_LEN 128 -#define MAXPATHLEN 128 - -struct ifname_num { - long next_eth; - long next_fddi; - long next_hip; - long next_tr; - long next_fc; - long size; -}; - -struct ifname_MAC { - char name[16]; - unsigned char dev_addr[7]; - unsigned char addr_len; /* hardware address length */ -}; - -#endif /* _ASM_IA64_SN_IFCONFIG_NET_H */ diff --git a/include/asm-ia64/sn/intr.h b/include/asm-ia64/sn/intr.h index d2e8a0aa5e4f..c9c520983949 100644 --- a/include/asm-ia64/sn/intr.h +++ b/include/asm-ia64/sn/intr.h @@ -3,19 +3,48 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved. */ + #ifndef _ASM_IA64_SN_INTR_H #define _ASM_IA64_SN_INTR_H -#include <asm/sn/types.h> -#include <asm/sn/sn2/intr.h> +#define SGI_UART_VECTOR (0xe9) +#define SGI_PCIBR_ERROR (0x33) + +// These two IRQ's are used by partitioning. +#define SGI_XPC_ACTIVATE (0x30) +#define SGI_II_ERROR (0x31) +#define SGI_XBOW_ERROR (0x32) +#define SGI_PCIBR_ERROR (0x33) +#define SGI_ACPI_SCI_INT (0x34) +#define SGI_TIO_ERROR (0x36) +#define SGI_XPC_NOTIFY (0xe7) + +#define SN2_IRQ_RESERVED (0x1) +#define SN2_IRQ_CONNECTED (0x2) +#define SN2_IRQ_SHARED (0x4) + +// The SN PROM irq struct +struct sn_irq_info { + struct sn_irq_info *irq_next; /* sharing irq list */ + short irq_nasid; /* Nasid IRQ is assigned to */ + int irq_slice; /* slice IRQ is assigned to */ + int irq_cpuid; /* kernel logical cpuid */ + int irq_irq; /* the IRQ number */ + int irq_int_bit; /* Bridge interrupt pin */ + uint64_t irq_xtalkaddr; /* xtalkaddr IRQ is sent to */ + int irq_bridge_type;/* pciio asic type (pciio.h) */ + void *irq_bridge; /* bridge generating irq */ + void *irq_pciioinfo; /* associated pciio_info_t */ + int irq_last_intr; /* For Shub lb lost intr WAR */ + int irq_cookie; /* unique cookie */ + int irq_flags; /* flags */ + int irq_share_cnt; /* num devices sharing IRQ */ +}; extern void sn_send_IPI_phys(long, int, int); -extern void intr_init_vecblk(cnodeid_t node); #define CPU_VECTOR_TO_IRQ(cpuid,vector) (vector) -#define SN_CPU_FROM_IRQ(irq) (0) -#define SN_IVEC_FROM_IRQ(irq) (irq) #endif /* _ASM_IA64_SN_INTR_H */ diff --git a/include/asm-ia64/sn/io.h b/include/asm-ia64/sn/io.h index 4ca04bcbdb02..46d46842e3f0 100644 --- a/include/asm-ia64/sn/io.h +++ b/include/asm-ia64/sn/io.h @@ -1,65 +1,265 @@ -/* +/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2000-2003 Silicon Graphics, Inc. All Rights Reserved. - * Copyright (C) 2000 Ralf Baechle + * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_IA64_SN_IO_H -#define _ASM_IA64_SN_IO_H -#include <asm/sn/addrs.h> +#ifndef _ASM_SN_IO_H +#define _ASM_SN_IO_H +#include <linux/compiler.h> +#include <asm/intrinsics.h> + +extern void * sn_io_addr(unsigned long port) __attribute_const__; /* Forward definition */ +extern void sn_mmiob(void); /* Forward definition */ + +extern int numionodes; + +#define __sn_mf_a() ia64_mfa() + +extern void sn_dma_flush(unsigned long); + +#define __sn_inb ___sn_inb +#define __sn_inw ___sn_inw +#define __sn_inl ___sn_inl +#define __sn_outb ___sn_outb +#define __sn_outw ___sn_outw +#define __sn_outl ___sn_outl +#define __sn_readb ___sn_readb +#define __sn_readw ___sn_readw +#define __sn_readl ___sn_readl +#define __sn_readq ___sn_readq +#define __sn_readb_relaxed ___sn_readb_relaxed +#define __sn_readw_relaxed ___sn_readw_relaxed +#define __sn_readl_relaxed ___sn_readl_relaxed +#define __sn_readq_relaxed ___sn_readq_relaxed + +/* + * The following routines are SN Platform specific, called when + * a reference is made to inX/outX set macros. SN Platform + * inX set of macros ensures that Posted DMA writes on the + * Bridge is flushed. + * + * The routines should be self explainatory. + */ -/* Because we only have PCI I/O ports. */ -#define IIO_ITTE_BASE 0x400160 /* base of translation table entries */ -#define IIO_ITTE(bigwin) (IIO_ITTE_BASE + 8*(bigwin)) +static inline unsigned int +___sn_inb (unsigned long port) +{ + volatile unsigned char *addr; + unsigned char ret = -1; -#define IIO_ITTE_OFFSET_BITS 5 /* size of offset field */ -#define IIO_ITTE_OFFSET_MASK ((1<<IIO_ITTE_OFFSET_BITS)-1) -#define IIO_ITTE_OFFSET_SHIFT 0 + if ((addr = sn_io_addr(port))) { + ret = *addr; + __sn_mf_a(); + sn_dma_flush((unsigned long)addr); + } + return ret; +} -#define IIO_ITTE_WIDGET_BITS 4 /* size of widget field */ -#define IIO_ITTE_WIDGET_MASK ((1<<IIO_ITTE_WIDGET_BITS)-1) -#define IIO_ITTE_WIDGET_SHIFT 8 +static inline unsigned int +___sn_inw (unsigned long port) +{ + volatile unsigned short *addr; + unsigned short ret = -1; -#define IIO_ITTE_IOSP 1 /* I/O Space bit */ -#define IIO_ITTE_IOSP_MASK 1 -#define IIO_ITTE_IOSP_SHIFT 12 -#define HUB_PIO_MAP_TO_MEM 0 -#define HUB_PIO_MAP_TO_IO 1 + if ((addr = sn_io_addr(port))) { + ret = *addr; + __sn_mf_a(); + sn_dma_flush((unsigned long)addr); + } + return ret; +} -#define IIO_ITTE_INVALID_WIDGET 3 /* an invalid widget */ +static inline unsigned int +___sn_inl (unsigned long port) +{ + volatile unsigned int *addr; + unsigned int ret = -1; -#define IIO_ITTE_PUT(nasid, bigwin, io_or_mem, widget, addr) \ - REMOTE_HUB_S((nasid), IIO_ITTE(bigwin), \ - (((((addr) >> BWIN_SIZE_BITS) & \ - IIO_ITTE_OFFSET_MASK) << IIO_ITTE_OFFSET_SHIFT) | \ - (io_or_mem << IIO_ITTE_IOSP_SHIFT) | \ - (((widget) & IIO_ITTE_WIDGET_MASK) << IIO_ITTE_WIDGET_SHIFT))) + if ((addr = sn_io_addr(port))) { + ret = *addr; + __sn_mf_a(); + sn_dma_flush((unsigned long)addr); + } + return ret; +} -#define IIO_ITTE_DISABLE(nasid, bigwin) \ - IIO_ITTE_PUT((nasid), (bigwin), HUB_PIO_MAP_TO_MEM, \ - IIO_ITTE_INVALID_WIDGET, 0) +static inline void +___sn_outb (unsigned char val, unsigned long port) +{ + volatile unsigned char *addr; -#define IIO_ITTE_GET(nasid, bigwin) REMOTE_HUB_ADDR((nasid), IIO_ITTE(bigwin)) + if ((addr = sn_io_addr(port))) { + *addr = val; + sn_mmiob(); + } +} + +static inline void +___sn_outw (unsigned short val, unsigned long port) +{ + volatile unsigned short *addr; + + if ((addr = sn_io_addr(port))) { + *addr = val; + sn_mmiob(); + } +} + +static inline void +___sn_outl (unsigned int val, unsigned long port) +{ + volatile unsigned int *addr; + + if ((addr = sn_io_addr(port))) { + *addr = val; + sn_mmiob(); + } +} /* - * Macro which takes the widget number, and returns the - * IO PRB address of that widget. - * value _x is expected to be a widget number in the range - * 0, 8 - 0xF + * The following routines are SN Platform specific, called when + * a reference is made to readX/writeX set macros. SN Platform + * readX set of macros ensures that Posted DMA writes on the + * Bridge is flushed. + * + * The routines should be self explainatory. */ -#define IIO_IOPRB(_x) (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \ - (_x) : \ - (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) ) -#include <asm/sn/sn2/shub.h> -#include <asm/sn/sn2/shubio.h> +static inline unsigned char +___sn_readb (const volatile void __iomem *addr) +{ + unsigned char val; + + val = *(volatile unsigned char __force *)addr; + __sn_mf_a(); + sn_dma_flush((unsigned long)addr); + return val; +} + +static inline unsigned short +___sn_readw (const volatile void __iomem *addr) +{ + unsigned short val; + + val = *(volatile unsigned short __force *)addr; + __sn_mf_a(); + sn_dma_flush((unsigned long)addr); + return val; +} + +static inline unsigned int +___sn_readl (const volatile void __iomem *addr) +{ + unsigned int val; + + val = *(volatile unsigned int __force *)addr; + __sn_mf_a(); + sn_dma_flush((unsigned long)addr); + return val; +} + +static inline unsigned long +___sn_readq (const volatile void __iomem *addr) +{ + unsigned long val; + + val = *(volatile unsigned long __force *)addr; + __sn_mf_a(); + sn_dma_flush((unsigned long)addr); + return val; +} /* - * Used to ensure write ordering (like mb(), but for I/O space) + * For generic and SN2 kernels, we have a set of fast access + * PIO macros. These macros are provided on SN Platform + * because the normal inX and readX macros perform an + * additional task of flushing Post DMA request on the Bridge. + * + * These routines should be self explainatory. */ -extern void sn_mmiob(void); -#endif /* _ASM_IA64_SN_IO_H */ +static inline unsigned int +sn_inb_fast (unsigned long port) +{ + volatile unsigned char *addr = (unsigned char *)port; + unsigned char ret; + + ret = *addr; + __sn_mf_a(); + return ret; +} + +static inline unsigned int +sn_inw_fast (unsigned long port) +{ + volatile unsigned short *addr = (unsigned short *)port; + unsigned short ret; + + ret = *addr; + __sn_mf_a(); + return ret; +} + +static inline unsigned int +sn_inl_fast (unsigned long port) +{ + volatile unsigned int *addr = (unsigned int *)port; + unsigned int ret; + + ret = *addr; + __sn_mf_a(); + return ret; +} + +static inline unsigned char +___sn_readb_relaxed (const volatile void __iomem *addr) +{ + return *(volatile unsigned char __force *)addr; +} + +static inline unsigned short +___sn_readw_relaxed (const volatile void __iomem *addr) +{ + return *(volatile unsigned short __force *)addr; +} + +static inline unsigned int +___sn_readl_relaxed (const volatile void __iomem *addr) +{ + return *(volatile unsigned int __force *) addr; +} + +static inline unsigned long +___sn_readq_relaxed (const volatile void __iomem *addr) +{ + return *(volatile unsigned long __force *) addr; +} + +struct pci_dev; + +static inline int +sn_pci_set_vchan(struct pci_dev *pci_dev, unsigned long *addr, int vchan) +{ + + if (vchan > 1) { + return -1; + } + + if (!(*addr >> 32)) /* Using a mask here would be cleaner */ + return 0; /* but this generates better code */ + + if (vchan == 1) { + /* Set Bit 57 */ + *addr |= (1UL << 57); + } else { + /* Clear Bit 57 */ + *addr &= ~(1UL << 57); + } + + return 0; +} + +#endif /* _ASM_SN_IO_H */ diff --git a/include/asm-ia64/sn/ioc4.h b/include/asm-ia64/sn/ioc4.h deleted file mode 100644 index b83f29cb0809..000000000000 --- a/include/asm-ia64/sn/ioc4.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (c) 2002-2003 Silicon Graphics, Inc. All Rights Reserved. - */ - -#ifndef _ASM_IA64_SN_IOC4_H -#define _ASM_IA64_SN_IOC4_H - -/* - * Bytebus device space - */ -#define IOC4_BYTEBUS_DEV0 0x80000L /* Addressed using pci_bar0 */ -#define IOC4_BYTEBUS_DEV1 0xA0000L /* Addressed using pci_bar0 */ -#define IOC4_BYTEBUS_DEV2 0xC0000L /* Addressed using pci_bar0 */ -#define IOC4_BYTEBUS_DEV3 0xE0000L /* Addressed using pci_bar0 */ - -#endif /* _ASM_IA64_SN_IOC4_H */ diff --git a/include/asm-ia64/sn/ioconfig_bus.h b/include/asm-ia64/sn/ioconfig_bus.h deleted file mode 100644 index facdd6ccc549..000000000000 --- a/include/asm-ia64/sn/ioconfig_bus.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003 Silicon Graphics, Inc. All Rights Reserved. - */ - -#ifndef _ASM_IA64_SN_IOCONFIG_BUS_H -#define _ASM_IA64_SN_IOCONFIG_BUS_H - -#define IOCONFIG_PCIBUS "/boot/efi/ioconfig_pcibus" -#define POUND_CHAR '#' -#define MAX_LINE_LEN 128 -#define MAXPATHLEN 128 - -struct ioconfig_parm { - unsigned long ioconfig_activated; - unsigned long number; - void *buffer; -}; - -struct ascii_moduleid { - unsigned char io_moduleid[8]; /* pci path name */ -}; - -#endif /* _ASM_IA64_SN_IOCONFIG_BUS_H */ diff --git a/include/asm-ia64/sn/ioerror.h b/include/asm-ia64/sn/ioerror.h deleted file mode 100644 index 5467a25c650b..000000000000 --- a/include/asm-ia64/sn/ioerror.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_IOERROR_H -#define _ASM_IA64_SN_IOERROR_H - -#ifndef __ASSEMBLY__ - -#include <linux/types.h> -#include <asm/sn/types.h> - -/* - * Macros defining the various Errors to be handled as part of - * IO Error handling. - */ - -/* - * List of errors to be handled by each subsystem. - * "error_code" field will take one of these values. - * The error code is built up of single bits expressing - * our confidence that the error was that type; note - * that it is possible to have a PIO or DMA error where - * we don't know whether it was a READ or a WRITE, or - * even a READ or WRITE error that we're not sure whether - * to call a PIO or DMA. - * - * It is also possible to set both PIO and DMA, and possible - * to set both READ and WRITE; the first may be nonsensical - * but the second *could* be used to designate an access - * that is known to be a read-modify-write cycle. It is - * quite possible that nobody will ever use PIO|DMA or - * READ|WRITE ... but being flexible is good. - */ -#define IOECODE_UNSPEC 0 -#define IOECODE_READ 1 -#define IOECODE_WRITE 2 -#define IOECODE_PIO 4 -#define IOECODE_DMA 8 - -#define IOECODE_PIO_READ (IOECODE_PIO|IOECODE_READ) -#define IOECODE_PIO_WRITE (IOECODE_PIO|IOECODE_WRITE) -#define IOECODE_DMA_READ (IOECODE_DMA|IOECODE_READ) -#define IOECODE_DMA_WRITE (IOECODE_DMA|IOECODE_WRITE) - -/* support older names, but try to move everything - * to using new names that identify which package - * controls their values ... - */ -#define PIO_READ_ERROR IOECODE_PIO_READ -#define PIO_WRITE_ERROR IOECODE_PIO_WRITE -#define DMA_READ_ERROR IOECODE_DMA_READ -#define DMA_WRITE_ERROR IOECODE_DMA_WRITE - -/* - * List of error numbers returned by error handling sub-system. - */ - -#define IOERROR_HANDLED 0 /* Error Properly handled. */ -#define IOERROR_NODEV 0x1 /* No such device attached */ -#define IOERROR_BADHANDLE 0x2 /* Received bad handle */ -#define IOERROR_BADWIDGETNUM 0x3 /* Bad widget number */ -#define IOERROR_BADERRORCODE 0x4 /* Bad error code passed in */ -#define IOERROR_INVALIDADDR 0x5 /* Invalid address specified */ - -#define IOERROR_WIDGETLEVEL 0x6 /* Some failure at widget level */ -#define IOERROR_XTALKLEVEL 0x7 - -#define IOERROR_HWGRAPH_LOOKUP 0x8 /* hwgraph lookup failed for path */ -#define IOERROR_UNHANDLED 0x9 /* handler rejected error */ - -#define IOERROR_PANIC 0xA /* subsidiary handler has already - * started decode: continue error - * data dump, and panic from top - * caller in error chain. - */ - -/* - * IO errors at the bus/device driver level - */ - -#define IOERROR_DEV_NOTFOUND 0x10 /* Device matching bus addr not found */ -#define IOERROR_DEV_SHUTDOWN 0x11 /* Device has been shutdown */ - -/* - * Type of address. - * Indicates the direction of transfer that caused the error. - */ -#define IOERROR_ADDR_PIO 1 /* Error Address generated due to PIO */ -#define IOERROR_ADDR_DMA 2 /* Error address generated due to DMA */ - -/* - * IO error structure. - * - * This structure would expand to hold the information retrieved from - * all IO related error registers. - * - * This structure is defined to hold all system specific - * information related to a single error. - * - * This serves a couple of purpose. - * - Error handling often involves translating one form of address to other - * form. So, instead of having different data structures at each level, - * we have a single structure, and the appropriate fields get filled in - * at each layer. - * - This provides a way to dump all error related information in any layer - * of erorr handling (debugging aid). - * - * A second possibility is to allow each layer to define its own error - * data structure, and fill in the proper fields. This has the advantage - * of isolating the layers. - * A big concern is the potential stack usage (and overflow), if each layer - * defines these structures on stack (assuming we don't want to do kmalloc. - * - * Any layer wishing to pass extra information to a layer next to it in - * error handling hierarchy, can do so as a separate parameter. - */ - -typedef struct io_error_s { - /* Bit fields indicating which structure fields are valid */ - union { - struct { - unsigned ievb_errortype:1; - unsigned ievb_widgetnum:1; - unsigned ievb_widgetdev:1; - unsigned ievb_srccpu:1; - unsigned ievb_srcnode:1; - unsigned ievb_errnode:1; - unsigned ievb_sysioaddr:1; - unsigned ievb_xtalkaddr:1; - unsigned ievb_busspace:1; - unsigned ievb_busaddr:1; - unsigned ievb_vaddr:1; - unsigned ievb_memaddr:1; - unsigned ievb_epc:1; - unsigned ievb_ef:1; - unsigned ievb_tnum:1; - } iev_b; - unsigned iev_a; - } ie_v; - - short ie_errortype; /* error type: extra info about error */ - short ie_widgetnum; /* Widget number that's in error */ - short ie_widgetdev; /* Device within widget in error */ - cpuid_t ie_srccpu; /* CPU on srcnode generating error */ - cnodeid_t ie_srcnode; /* Node which caused the error */ - cnodeid_t ie_errnode; /* Node where error was noticed */ - iopaddr_t ie_sysioaddr; /* Sys specific IO address */ - iopaddr_t ie_xtalkaddr; /* Xtalk (48bit) addr of Error */ - iopaddr_t ie_busspace; /* Bus specific address space */ - iopaddr_t ie_busaddr; /* Bus specific address */ - caddr_t ie_vaddr; /* Virtual address of error */ - paddr_t ie_memaddr; /* Physical memory address */ - caddr_t ie_epc; /* pc when error reported */ - caddr_t ie_ef; /* eframe when error reported */ - short ie_tnum; /* Xtalk TNUM field */ -} ioerror_t; - -#define IOERROR_INIT(e) do { (e)->ie_v.iev_a = 0; } while (0) -#define IOERROR_SETVALUE(e,f,v) do { (e)->ie_ ## f = (v); (e)->ie_v.iev_b.ievb_ ## f = 1; } while (0) -#define IOERROR_FIELDVALID(e,f) ((unsigned long long)((e)->ie_v.iev_b.ievb_ ## f) != (unsigned long long) 0) -#define IOERROR_NOGETVALUE(e,f) (ASSERT(IOERROR_FIELDVALID(e,f)), ((e)->ie_ ## f)) -#define IOERROR_GETVALUE(p,e,f) ASSERT(IOERROR_FIELDVALID(e,f)); p=((e)->ie_ ## f) - -/* hub code likes to call the SysAD address "hubaddr" ... */ -#define ie_hubaddr ie_sysioaddr -#define ievb_hubaddr ievb_sysioaddr -#endif - -/* - * Error handling Modes. - */ -typedef enum { - MODE_DEVPROBE, /* Probing mode. Errors not fatal */ - MODE_DEVERROR, /* Error while system is running */ - MODE_DEVUSERERROR, /* Device Error created due to user mode access */ - MODE_DEVREENABLE /* Reenable pass */ -} ioerror_mode_t; - - -typedef int error_handler_f(void *, int, ioerror_mode_t, ioerror_t *); -typedef void *error_handler_arg_t; - -#ifdef ERROR_DEBUG -#define IOERR_PRINTF(x) (x) -#else -#define IOERR_PRINTF(x) -#endif /* ERROR_DEBUG */ - -#endif /* _ASM_IA64_SN_IOERROR_H */ diff --git a/include/asm-ia64/sn/ioerror_handling.h b/include/asm-ia64/sn/ioerror_handling.h deleted file mode 100644 index 6856779bd781..000000000000 --- a/include/asm-ia64/sn/ioerror_handling.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_IOERROR_HANDLING_H -#define _ASM_IA64_SN_IOERROR_HANDLING_H - -#include <linux/types.h> -#include <asm/sn/sgi.h> - -#ifdef __KERNEL__ - -/* - * Basic types required for io error handling interfaces. - */ - -/* - * Return code from the io error handling interfaces. - */ - -enum error_return_code_e { - /* Success */ - ERROR_RETURN_CODE_SUCCESS, - - /* Unknown failure */ - ERROR_RETURN_CODE_GENERAL_FAILURE, - - /* Nth error noticed while handling the first error */ - ERROR_RETURN_CODE_NESTED_CALL, - - /* State of the vertex is invalid */ - ERROR_RETURN_CODE_INVALID_STATE, - - /* Invalid action */ - ERROR_RETURN_CODE_INVALID_ACTION, - - /* Valid action but not cannot set it */ - ERROR_RETURN_CODE_CANNOT_SET_ACTION, - - /* Valid action but not possible for the current state */ - ERROR_RETURN_CODE_CANNOT_PERFORM_ACTION, - - /* Valid state but cannot change the state of the vertex to it */ - ERROR_RETURN_CODE_CANNOT_SET_STATE, - - /* ??? */ - ERROR_RETURN_CODE_DUPLICATE, - - /* Reached the root of the system critical graph */ - ERROR_RETURN_CODE_SYS_CRITICAL_GRAPH_BEGIN, - - /* Reached the leaf of the system critical graph */ - ERROR_RETURN_CODE_SYS_CRITICAL_GRAPH_ADD, - - /* Cannot shutdown the device in hw/sw */ - ERROR_RETURN_CODE_SHUTDOWN_FAILED, - - /* Cannot restart the device in hw/sw */ - ERROR_RETURN_CODE_RESET_FAILED, - - /* Cannot failover the io subsystem */ - ERROR_RETURN_CODE_FAILOVER_FAILED, - - /* No Jump Buffer exists */ - ERROR_RETURN_CODE_NO_JUMP_BUFFER -}; - -typedef uint64_t error_return_code_t; - -/* - * State of the vertex during error handling. - */ -enum error_state_e { - /* Ignore state */ - ERROR_STATE_IGNORE, - - /* Invalid state */ - ERROR_STATE_NONE, - - /* Trying to decipher the error bits */ - ERROR_STATE_LOOKUP, - - /* Trying to carryout the action decided upon after - * looking at the error bits - */ - ERROR_STATE_ACTION, - - /* Donot allow any other operations to this vertex from - * other parts of the kernel. This is also used to indicate - * that the device has been software shutdown. - */ - ERROR_STATE_SHUTDOWN, - - /* This is a transitory state when no new requests are accepted - * on behalf of the device. This is usually used when trying to - * quiesce all the outstanding operations and preparing the - * device for a failover / shutdown etc. - */ - ERROR_STATE_SHUTDOWN_IN_PROGRESS, - - /* This is the state when there is absolutely no activity going - * on wrt device. - */ - ERROR_STATE_SHUTDOWN_COMPLETE, - - /* This is the state when the device has issued a retry. */ - ERROR_STATE_RETRY, - - /* This is the normal state. This can also be used to indicate - * that the device has been software-enabled after software- - * shutting down previously. - */ - ERROR_STATE_NORMAL - -}; - -typedef uint64_t error_state_t; - -/* - * Generic error classes. This is used to classify errors after looking - * at the error bits and helpful in deciding on the action. - */ -enum error_class_e { - /* Unclassified error */ - ERROR_CLASS_UNKNOWN, - - /* LLP transmit error */ - ERROR_CLASS_LLP_XMIT, - - /* LLP receive error */ - ERROR_CLASS_LLP_RECV, - - /* Credit error */ - ERROR_CLASS_CREDIT, - - /* Timeout error */ - ERROR_CLASS_TIMEOUT, - - /* Access error */ - ERROR_CLASS_ACCESS, - - /* System coherency error */ - ERROR_CLASS_SYS_COHERENCY, - - /* Bad data error (ecc / parity etc) */ - ERROR_CLASS_BAD_DATA, - - /* Illegal request packet */ - ERROR_CLASS_BAD_REQ_PKT, - - /* Illegal response packet */ - ERROR_CLASS_BAD_RESP_PKT -}; - -#endif /* __KERNEL__ */ -#endif /* _ASM_IA64_SN_IOERROR_HANDLING_H */ diff --git a/include/asm-ia64/sn/iograph.h b/include/asm-ia64/sn/iograph.h deleted file mode 100644 index 735d2923d24a..000000000000 --- a/include/asm-ia64/sn/iograph.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_IOGRAPH_H -#define _ASM_IA64_SN_IOGRAPH_H - -#include <asm/sn/xtalk/xbow.h> /* For get MAX_PORT_NUM */ - -/* - * During initialization, platform-dependent kernel code establishes some - * basic elements of the hardware graph. This file contains edge and - * info labels that are used across various platforms -- it serves as an - * ad-hoc registry. - */ - -/* edges names */ -#define EDGE_LBL_BUS "bus" -#define EDGE_LBL_CONN ".connection" -#define EDGE_LBL_GUEST ".guest" /* For IOC3 */ -#define EDGE_LBL_HOST ".host" /* For IOC3 */ -#define EDGE_LBL_PERFMON "mon" -#define EDGE_LBL_USRPCI "usrpci" -#define EDGE_LBL_BLOCK "block" -#define EDGE_LBL_BOARD "board" -#define EDGE_LBL_CHAR "char" -#define EDGE_LBL_CONTROLLER "controller" -#define EDGE_LBL_CPU "cpu" -#define EDGE_LBL_CPUNUM "cpunum" -#define EDGE_LBL_DIRECT "direct" -#define EDGE_LBL_DISABLED "disabled" -#define EDGE_LBL_DISK "disk" -#define EDGE_LBL_HUB "hub" /* For SN0 */ -#define EDGE_LBL_HW "hw" -#define EDGE_LBL_INTERCONNECT "link" -#define EDGE_LBL_IO "io" -#define EDGE_LBL_LUN "lun" -#define EDGE_LBL_LINUX "linux" -#define EDGE_LBL_LINUX_BUS EDGE_LBL_LINUX "/bus/pci-x" -#define EDGE_LBL_MACHDEP "machdep" /* Platform depedent devices */ -#define EDGE_LBL_MASTER ".master" -#define EDGE_LBL_MEMORY "memory" -#define EDGE_LBL_META_ROUTER "metarouter" -#define EDGE_LBL_MIDPLANE "midplane" -#define EDGE_LBL_MODULE "module" -#define EDGE_LBL_NODE "node" -#define EDGE_LBL_NODENUM "nodenum" -#define EDGE_LBL_NVRAM "nvram" -#define EDGE_LBL_PARTITION "partition" -#define EDGE_LBL_PCI "pci" -#define EDGE_LBL_PCIX "pci-x" -#define EDGE_LBL_PCIX_0 EDGE_LBL_PCIX "/0" -#define EDGE_LBL_PCIX_1 EDGE_LBL_PCIX "/1" -#define EDGE_LBL_AGP "agp" -#define EDGE_LBL_AGP_0 EDGE_LBL_AGP "/0" -#define EDGE_LBL_AGP_1 EDGE_LBL_AGP "/1" -#define EDGE_LBL_PORT "port" -#define EDGE_LBL_PROM "prom" -#define EDGE_LBL_RACK "rack" -#define EDGE_LBL_RDISK "rdisk" -#define EDGE_LBL_REPEATER_ROUTER "repeaterrouter" -#define EDGE_LBL_ROUTER "router" -#define EDGE_LBL_RPOS "bay" /* Position in rack */ -#define EDGE_LBL_SCSI "scsi" -#define EDGE_LBL_SCSI_CTLR "scsi_ctlr" -#define EDGE_LBL_SLOT "slot" -#define EDGE_LBL_TARGET "target" -#define EDGE_LBL_UNKNOWN "unknown" -#define EDGE_LBL_XBOW "xbow" -#define EDGE_LBL_XIO "xio" -#define EDGE_LBL_XSWITCH ".xswitch" -#define EDGE_LBL_XTALK "xtalk" -#define EDGE_LBL_XWIDGET "xwidget" -#define EDGE_LBL_ELSC "elsc" -#define EDGE_LBL_L1 "L1" -#define EDGE_LBL_XPLINK "xplink" /* Cross partition */ -#define EDGE_LBL_XPLINK_NET "net" /* XP network devs */ -#define EDGE_LBL_XPLINK_RAW "raw" /* XP Raw devs */ -#define EDGE_LBL_SLAB "slab" /* Slab of a module */ -#define EDGE_LBL_XPLINK_KERNEL "kernel" /* XP kernel devs */ -#define EDGE_LBL_XPLINK_ADMIN "admin" /* Partition admin */ -#define EDGE_LBL_IOBRICK "iobrick" -#define EDGE_LBL_PXBRICK "PXbrick" -#define EDGE_LBL_OPUSBRICK "onboardio" -#define EDGE_LBL_IXBRICK "IXbrick" -#define EDGE_LBL_CGBRICK "CGbrick" -#define EDGE_LBL_CPUBUS "cpubus" /* CPU Interfaces (SysAd) */ - -/* vertex info labels in hwgraph */ -#define INFO_LBL_CNODEID "_cnodeid" -#define INFO_LBL_CONTROLLER_NAME "_controller_name" -#define INFO_LBL_CPUBUS "_cpubus" -#define INFO_LBL_CPUID "_cpuid" -#define INFO_LBL_CPU_INFO "_cpu" -#define INFO_LBL_DETAIL_INVENT "_detail_invent" /* inventory data*/ -#define INFO_LBL_DIAGVAL "_diag_reason" /* Reason disabled */ -#define INFO_LBL_DRIVER "_driver" /* points to attached device_driver_t */ -#define INFO_LBL_ELSC "_elsc" -#define INFO_LBL_SUBCH "_subch" /* system controller subchannel */ -#define INFO_LBL_HUB_INFO "_hubinfo" -#define INFO_LBL_HWGFSLIST "_hwgfs_list" -#define INFO_LBL_TRAVERSE "_hwg_traverse" /* hwgraph traverse function */ -#define INFO_LBL_MODULE_INFO "_module" /* module data ptr */ -#define INFO_LBL_MDPERF_DATA "_mdperf" /* mdperf monitoring*/ -#define INFO_LBL_NODE_INFO "_node" -#define INFO_LBL_PCIBR_HINTS "_pcibr_hints" -#define INFO_LBL_PCIIO "_pciio" -#define INFO_LBL_PFUNCS "_pciio_ops" /* ops vector for gio providers */ -#define INFO_LBL_PERMISSIONS "_permissions" /* owner, uid, gid */ -#define INFO_LBL_ROUTER_INFO "_router" -#define INFO_LBL_SUBDEVS "_subdevs" /* subdevice enable bits */ -#define INFO_LBL_XSWITCH "_xswitch" -#define INFO_LBL_XSWITCH_ID "_xswitch_id" -#define INFO_LBL_XSWITCH_VOL "_xswitch_volunteer" -#define INFO_LBL_XFUNCS "_xtalk_ops" /* ops vector for gio providers */ -#define INFO_LBL_XWIDGET "_xwidget" - - -#ifdef __KERNEL__ -void init_all_devices(void); -#endif /* __KERNEL__ */ - -int io_brick_map_widget(int, int); - -/* - * Map a brick's widget number to a meaningful int - */ - -struct io_brick_map_s { - int ibm_type; /* brick type */ - int ibm_map_wid[MAX_PORT_NUM]; /* wid to int map */ -}; - -#endif /* _ASM_IA64_SN_IOGRAPH_H */ diff --git a/include/asm-ia64/sn/klconfig.h b/include/asm-ia64/sn/klconfig.h index 781b0e00303a..37dd829bc0b9 100644 --- a/include/asm-ia64/sn/klconfig.h +++ b/include/asm-ia64/sn/klconfig.h @@ -5,7 +5,7 @@ * * Derived from IRIX <sys/SN/klconfig.h>. * - * Copyright (C) 1992-1997,1999,2001-2003 Silicon Graphics, Inc. All Rights Reserved. + * Copyright (C) 1992-1997,1999,2001-2004 Silicon Graphics, Inc. All Rights Reserved. * Copyright (C) 1999 by Ralf Baechle */ #ifndef _ASM_IA64_SN_KLCONFIG_H @@ -17,145 +17,20 @@ * components found on the BOARDs. */ -/* - * WARNING: - * Certain assembly language routines (notably xxxxx.s) in the IP27PROM - * will depend on the format of the data structures in this file. In - * most cases, rearranging the fields can seriously break things. - * Adding fields in the beginning or middle can also break things. - * Add fields if necessary, to the end of a struct in such a way - * that offsets of existing fields do not change. - */ - -#include <linux/types.h> -#include <asm/sn/types.h> -#include <asm/sn/slotnum.h> -#include <asm/sn/router.h> -#include <asm/sn/sgi.h> -#include <asm/sn/addrs.h> -#include <asm/sn/vector.h> -#include <asm/sn/xtalk/xbow.h> -#include <asm/sn/xtalk/xtalk.h> -#include <asm/sn/kldir.h> -#include <asm/sn/sn_fru.h> -#include <asm/sn/sn2/shub_md.h> -#include <asm/sn/geo.h> - -#define KLCFGINFO_MAGIC 0xbeedbabe - typedef s32 klconf_off_t; -#define MAX_MODULE_ID 255 -#define SIZE_PAD 4096 /* 4k padding for structures */ -/* - * 1 NODE brick, 3 Router bricks (1 local, 1 meta, 1 repeater), - * 6 XIO Widgets, 1 Xbow, 1 gfx - */ -#define MAX_SLOTS_PER_NODE (1 + 3 + 6 + 1 + 1) - -/* XXX if each node is guranteed to have some memory */ - -#define MAX_PCI_DEVS 8 - -/* lboard_t->brd_flags fields */ -/* All bits in this field are currently used. Try the pad fields if - you need more flag bits */ - -#define ENABLE_BOARD 0x01 -#define FAILED_BOARD 0x02 -#define DUPLICATE_BOARD 0x04 /* Boards like midplanes/routers which - are discovered twice. Use one of them */ -#define VISITED_BOARD 0x08 /* Used for compact hub numbering. */ -#define LOCAL_MASTER_IO6 0x10 /* master io6 for that node */ -#define KLTYPE_IOBRICK_XBOW (KLCLASS_MIDPLANE | 0x2) - -/* klinfo->flags fields */ - -#define KLINFO_ENABLE 0x01 /* This component is enabled */ -#define KLINFO_FAILED 0x02 /* This component failed */ -#define KLINFO_DEVICE 0x04 /* This component is a device */ -#define KLINFO_VISITED 0x08 /* This component has been visited */ -#define KLINFO_CONTROLLER 0x10 /* This component is a device controller */ -#define KLINFO_INSTALL 0x20 /* Install a driver */ -#define KLINFO_HEADLESS 0x40 /* Headless (or hubless) component */ - -/* Structures to manage various data storage areas */ -/* The numbers must be contiguous since the array index i - is used in the code to allocate various areas. -*/ - -#define BOARD_STRUCT 0 -#define COMPONENT_STRUCT 1 -#define ERRINFO_STRUCT 2 -#define KLMALLOC_TYPE_MAX (ERRINFO_STRUCT + 1) -#define DEVICE_STRUCT 3 - - -typedef struct console_s { - unsigned long uart_base; - unsigned long config_base; - unsigned long memory_base; - short baud; - short flag; - int type; - nasid_t nasid; - char wid; - char npci; - nic_t baseio_nic; -} console_t; - -typedef struct klc_malloc_hdr { - klconf_off_t km_base; - klconf_off_t km_limit; - klconf_off_t km_current; -} klc_malloc_hdr_t; /* Functions/macros needed to use this structure */ typedef struct kl_config_hdr { - u64 ch_magic; /* set this to KLCFGINFO_MAGIC */ - u32 ch_version; /* structure version number */ - klconf_off_t ch_malloc_hdr_off; /* offset of ch_malloc_hdr */ - klconf_off_t ch_cons_off; /* offset of ch_cons */ + char pad[20]; klconf_off_t ch_board_info; /* the link list of boards */ - console_t ch_cons_info; /* address info of the console */ - klc_malloc_hdr_t ch_malloc_hdr[KLMALLOC_TYPE_MAX]; - confidence_t ch_sw_belief; /* confidence that software is bad*/ - confidence_t ch_sn0net_belief; /* confidence that sn0net is bad */ + char pad0[88]; } kl_config_hdr_t; -#define KL_CONFIG_HDR(_nasid) ((kl_config_hdr_t *)(KLCONFIG_ADDR(_nasid))) - #define NODE_OFFSET_TO_LBOARD(nasid,off) (lboard_t*)(NODE_CAC_BASE(nasid) + (off)) -#define KL_CONFIG_INFO(_nasid) root_lboard[nasid_to_cnodeid(_nasid)] - -/* --- New Macros for the changed kl_config_hdr_t structure --- */ - -#define PTR_CH_CONS_INFO(_k) ((console_t *)\ - ((unsigned long)_k + (_k->ch_cons_off))) - -#define KL_CONFIG_CH_CONS_INFO(_n) PTR_CH_CONS_INFO(KL_CONFIG_HDR(_n)) - -/* ------------------------------------------------------------- */ - -#define KL_CONFIG_DUPLICATE_BOARD(_brd) ((_brd)->brd_flags & DUPLICATE_BOARD) - -#define XBOW_PORT_TYPE_HUB(_xbowp, _link) \ - ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_HUB) -#define XBOW_PORT_TYPE_IO(_xbowp, _link) \ - ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_IO) - -#define XBOW_PORT_IS_ENABLED(_xbowp, _link) \ - ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_ENABLE) -#define XBOW_PORT_NASID(_xbowp, _link) \ - ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_nasid) - -#define XBOW_PORT_IO 0x1 -#define XBOW_PORT_HUB 0x2 -#define XBOW_PORT_ENABLE 0x4 - /* * The KLCONFIG area is organized as a LINKED LIST of BOARDs. A BOARD * can be either 'LOCAL' or 'REMOTE'. LOCAL means it is attached to @@ -248,6 +123,7 @@ typedef struct kl_config_hdr { * The data structures below define the above concepts. */ + /* * BOARD classes */ @@ -261,54 +137,40 @@ typedef struct kl_config_hdr { #define KLCLASS_ROUTER 0x30 /* Router board */ #define KLCLASS_MIDPLANE 0x40 /* We need to treat this as a board so that we can record error info */ -#define KLCLASS_GFX 0x50 /* graphics boards */ - -#define KLCLASS_PSEUDO_GFX 0x60 /* HDTV type cards that use a gfx - * hw ifc to xtalk and are not gfx - * class for sw purposes */ - #define KLCLASS_IOBRICK 0x70 /* IP35 iobrick */ - #define KLCLASS_MAX 8 /* Bump this if a new CLASS is added */ -#define KLTYPE_MAX 11 /* Bump this if a new CLASS is added */ - -#define KLCLASS_UNKNOWN 0xf0 #define KLCLASS(_x) ((_x) & KLCLASS_MASK) + /* * board types */ #define KLTYPE_MASK 0x0f -#define KLTYPE_NONE 0x00 -#define KLTYPE_EMPTY 0x00 +#define KLTYPE(_x) ((_x) & KLTYPE_MASK) -#define KLTYPE_WEIRDCPU (KLCLASS_CPU | 0x0) #define KLTYPE_SNIA (KLCLASS_CPU | 0x1) +#define KLTYPE_TIO (KLCLASS_CPU | 0x2) #define KLTYPE_ROUTER (KLCLASS_ROUTER | 0x1) #define KLTYPE_META_ROUTER (KLCLASS_ROUTER | 0x3) #define KLTYPE_REPEATER_ROUTER (KLCLASS_ROUTER | 0x4) +#define KLTYPE_IOBRICK_XBOW (KLCLASS_MIDPLANE | 0x2) + #define KLTYPE_IOBRICK (KLCLASS_IOBRICK | 0x0) #define KLTYPE_NBRICK (KLCLASS_IOBRICK | 0x4) #define KLTYPE_PXBRICK (KLCLASS_IOBRICK | 0x6) #define KLTYPE_IXBRICK (KLCLASS_IOBRICK | 0x7) #define KLTYPE_CGBRICK (KLCLASS_IOBRICK | 0x8) #define KLTYPE_OPUSBRICK (KLCLASS_IOBRICK | 0x9) +#define KLTYPE_SABRICK (KLCLASS_IOBRICK | 0xa) +#define KLTYPE_IABRICK (KLCLASS_IOBRICK | 0xb) +#define KLTYPE_PABRICK (KLCLASS_IOBRICK | 0xc) +#define KLTYPE_GABRICK (KLCLASS_IOBRICK | 0xd) -/* The value of type should be more than 8 so that hinv prints - * out the board name from the NIC string. For values less than - * 8 the name of the board needs to be hard coded in a few places. - * When bringup started nic names had not standardized and so we - * had to hard code. (For people interested in history.) - */ -#define KLTYPE_UNKNOWN (KLCLASS_UNKNOWN | 0xf) - -#define KLTYPE(_x) ((_x) & KLTYPE_MASK) - /* * board structures */ @@ -337,7 +199,7 @@ typedef struct lboard_s { klconf_off_t brd_errinfo; /* Board's error information */ struct lboard_s *brd_parent; /* Logical parent for this brd */ char pad0[4]; - confidence_t brd_confidence; /* confidence that the board is bad */ + unsigned char brd_confidence; /* confidence that the board is bad */ nasid_t brd_owner; /* who owns this board */ unsigned char brd_nic_flags; /* To handle 8 more NICs */ char pad1[24]; /* future expansion */ @@ -346,18 +208,7 @@ typedef struct lboard_s { klconf_off_t brd_next_same; /* Next BOARD with same nasid */ } lboard_t; -/* - * Make sure we pass back the calias space address for local boards. - * klconfig board traversal and error structure extraction defines. - */ - -#define BOARD_SLOT(_brd) ((_brd)->brd_slot) - -#define KLCF_CLASS(_brd) KLCLASS((_brd)->brd_type) -#define KLCF_TYPE(_brd) KLTYPE((_brd)->brd_type) #define KLCF_NUM_COMPS(_brd) ((_brd)->brd_numcompts) -#define KLCF_MODULE_ID(_brd) ((_brd)->brd_module) - #define NODE_OFFSET_TO_KLINFO(n,off) ((klinfo_t*) TO_NODE_CAC(n,off)) #define KLCF_NEXT(_brd) \ ((_brd)->brd_next_same ? \ @@ -369,10 +220,6 @@ typedef struct lboard_s { ((((_brd)->brd_compts[(_ndx)]) == 0) ? 0 : \ (NODE_OFFSET_TO_KLINFO(NASID_GET(_brd), (_brd)->brd_compts[(_ndx)]))) -#define KLCF_COMP_TYPE(_comp) ((_comp)->struct_type) -#define KLCF_BRIDGE_W_ID(_comp) ((_comp)->physid) /* Widget ID */ - - /* * Generic info structure. This stores common info about a @@ -401,302 +248,25 @@ typedef struct klinfo_s { /* Generic info */ unsigned short pad4; /* klbri_t */ } klinfo_t ; -#define KLCONFIG_INFO_ENABLED(_i) ((_i)->flags & KLINFO_ENABLE) -/* - * Component structures. - * Following are the currently identified components: - * CPU, HUB, MEM_BANK, - * XBOW(consists of 16 WIDGETs, each of which can be HUB or GRAPHICS or BRIDGE) - * BRIDGE, IOC3, SuperIO, SCSI, FDDI - * ROUTER - * GRAPHICS - */ -#define KLSTRUCT_UNKNOWN 0 -#define KLSTRUCT_CPU 1 -#define KLSTRUCT_HUB 2 -#define KLSTRUCT_MEMBNK 3 -#define KLSTRUCT_XBOW 4 -#define KLSTRUCT_BRI 5 -#define KLSTRUCT_ROU 9 -#define KLSTRUCT_GFX 10 -#define KLSTRUCT_SCSI 11 -#define KLSTRUCT_DISK 14 -#define KLSTRUCT_CDROM 16 - -#define KLSTRUCT_FIBERCHANNEL 25 -#define KLSTRUCT_MOD_SERIAL_NUM 26 -#define KLSTRUCT_QLFIBRE 32 -#define KLSTRUCT_1394 33 -#define KLSTRUCT_USB 34 -#define KLSTRUCT_USBKBD 35 -#define KLSTRUCT_USBMS 36 -#define KLSTRUCT_SCSI_CTLR 37 -#define KLSTRUCT_PEBRICK 38 -#define KLSTRUCT_GIGE 39 -#define KLSTRUCT_IDE 40 -#define KLSTRUCT_IOC4 41 -#define KLSTRUCT_IOC4UART 42 -#define KLSTRUCT_IOC4_TTY 43 -#define KLSTRUCT_IOC4PCKM 44 -#define KLSTRUCT_IOC4MS 45 -#define KLSTRUCT_IOC4_ATA 46 -#define KLSTRUCT_PCIGFX 47 +static inline lboard_t *find_lboard_any(lboard_t * start, unsigned char brd_type) +{ + /* Search all boards stored on this node. */ -/* - * The port info in ip27_cfg area translates to a lboart_t in the - * KLCONFIG area. But since KLCONFIG does not use pointers, lboart_t - * is stored in terms of a nasid and a offset from start of KLCONFIG - * area on that nasid. - */ -typedef struct klport_s { - nasid_t port_nasid; - unsigned char port_flag; - klconf_off_t port_offset; - short port_num; -} klport_t; - -typedef struct klcpu_s { /* CPU */ - klinfo_t cpu_info; - unsigned short cpu_prid; /* Processor PRID value */ - unsigned short cpu_fpirr; /* FPU IRR value */ - unsigned short cpu_speed; /* Speed in MHZ */ - unsigned short cpu_scachesz; /* secondary cache size in MB */ - unsigned short cpu_scachespeed;/* secondary cache speed in MHz */ - unsigned long pad; -} klcpu_t ; - -#define CPU_STRUCT_VERSION 2 - -typedef struct klhub_s { /* HUB */ - klinfo_t hub_info; - unsigned int hub_flags; /* PCFG_HUB_xxx flags */ -#define MAX_NI_PORTS 2 - klport_t hub_port[MAX_NI_PORTS + 1];/* hub is connected to this */ - nic_t hub_box_nic; /* nic of containing box */ - klconf_off_t hub_mfg_nic; /* MFG NIC string */ - u64 hub_speed; /* Speed of hub in HZ */ - moduleid_t hub_io_module; /* attached io module */ - unsigned long pad; -} klhub_t ; - -typedef struct klhub_uart_s { /* HUB */ - klinfo_t hubuart_info; - unsigned int hubuart_flags; /* PCFG_HUB_xxx flags */ - nic_t hubuart_box_nic; /* nic of containing box */ - unsigned long pad; -} klhub_uart_t ; - -#define MEMORY_STRUCT_VERSION 2 - -typedef struct klmembnk_s { /* MEMORY BANK */ - klinfo_t membnk_info; - short membnk_memsz; /* Total memory in megabytes */ - short membnk_dimm_select; /* bank to physical addr mapping*/ - short membnk_bnksz[MD_MEM_BANKS]; /* Memory bank sizes */ - short membnk_attr; - unsigned long pad; -} klmembnk_t ; - -#define MAX_SERIAL_NUM_SIZE 10 - -typedef struct klmod_serial_num_s { - klinfo_t snum_info; - union { - char snum_str[MAX_SERIAL_NUM_SIZE]; - unsigned long long snum_int; - } snum; - unsigned long pad; -} klmod_serial_num_t; - -/* Macros needed to access serial number structure in lboard_t. - Hard coded values are necessary since we cannot treat - serial number struct as a component without losing compatibility - between prom versions. */ - -#define GET_SNUM_COMP(_l) ((klmod_serial_num_t *)\ - KLCF_COMP(_l, _l->brd_numcompts)) - -#define MAX_XBOW_LINKS 16 - -typedef struct klxbow_s { /* XBOW */ - klinfo_t xbow_info ; - klport_t xbow_port_info[MAX_XBOW_LINKS] ; /* Module number */ - int xbow_master_hub_link; - /* type of brd connected+component struct ptr+flags */ - unsigned long pad; -} klxbow_t ; - -#define MAX_PCI_SLOTS 8 - -typedef struct klpci_device_s { - s32 pci_device_id; /* 32 bits of vendor/device ID. */ - s32 pci_device_pad; /* 32 bits of padding. */ -} klpci_device_t; - -#define BRIDGE_STRUCT_VERSION 2 - -typedef struct klbri_s { /* BRIDGE */ - klinfo_t bri_info ; - unsigned char bri_eprominfo ; /* IO6prom connected to bridge */ - unsigned char bri_bustype ; /* PCI/VME BUS bridge/GIO */ - u64 *pci_specific ; /* PCI Board config info */ - klpci_device_t bri_devices[MAX_PCI_DEVS] ; /* PCI IDs */ - klconf_off_t bri_mfg_nic ; - unsigned long pad; -} klbri_t ; - -#define ROUTER_VECTOR_VERS 2 - -/* XXX - Don't we need the number of ports here?!? */ -typedef struct klrou_s { /* ROUTER */ - klinfo_t rou_info ; - unsigned int rou_flags ; /* PCFG_ROUTER_xxx flags */ - nic_t rou_box_nic ; /* nic of the containing module */ - klport_t rou_port[MAX_ROUTER_PORTS + 1] ; /* array index 1 to 6 */ - klconf_off_t rou_mfg_nic ; /* MFG NIC string */ - u64 rou_vector; /* vector from master node */ - unsigned long pad; -} klrou_t ; - -/* - * Graphics Controller/Device - * - * (IP27/IO6) Prom versions 6.13 (and 6.5.1 kernels) and earlier - * used a couple different structures to store graphics information. - * For compatibility reasons, the newer data structure preserves some - * of the layout so that fields that are used in the old versions remain - * in the same place (with the same info). Determination of what version - * of this structure we have is done by checking the cookie field. - */ -#define KLGFX_COOKIE 0x0c0de000 - -typedef struct klgfx_s { /* GRAPHICS Device */ - klinfo_t gfx_info; - klconf_off_t old_gndevs; /* for compatibility with older proms */ - klconf_off_t old_gdoff0; /* for compatibility with older proms */ - unsigned int cookie; /* for compatibility with older proms */ - unsigned int moduleslot; - struct klgfx_s *gfx_next_pipe; - u64 *gfx_specific; - klconf_off_t pad0; /* for compatibility with older proms */ - klconf_off_t gfx_mfg_nic; - unsigned long pad; -} klgfx_t; - -#define MAX_SCSI_DEVS 16 - -/* - * NOTE: THis is the max sized kl* structure and is used in klmalloc.c - * to allocate space of type COMPONENT. Make sure that if the size of - * any other component struct becomes more than this, then redefine - * that as the size to be klmalloced. - */ - -typedef struct klscsi_s { /* SCSI Bus */ - klinfo_t scsi_info ; - u64 *scsi_specific ; - unsigned char scsi_numdevs ; - klconf_off_t scsi_devinfo[MAX_SCSI_DEVS] ; - unsigned long pad; -} klscsi_t ; - -typedef struct klscctl_s { /* SCSI Controller */ - klinfo_t scsi_info ; - unsigned int type; - unsigned int scsi_buscnt; /* # busses this cntlr */ - void *scsi_bus[2]; /* Pointer to 2 klscsi_t's */ - unsigned long pad; -} klscctl_t ; - -typedef struct klscdev_s { /* SCSI device */ - klinfo_t scdev_info ; - struct scsidisk_data *scdev_cfg ; /* driver fills up this */ - unsigned long pad; -} klscdev_t ; - -typedef struct klttydev_s { /* TTY device */ - klinfo_t ttydev_info ; - struct terminal_data *ttydev_cfg ; /* driver fills up this */ - unsigned long pad; -} klttydev_t ; - -typedef struct klpcigfx_s { /* PCI GFX */ - klinfo_t gfx_info ; -} klpcigfx_t ; - -typedef struct klkbddev_s { /* KBD device */ - klinfo_t kbddev_info ; - struct keyboard_data *kbddev_cfg ; /* driver fills up this */ - unsigned long pad; -} klkbddev_t ; - -typedef struct klmsdev_s { /* mouse device */ - klinfo_t msdev_info ; - void *msdev_cfg ; - unsigned long pad; -} klmsdev_t ; - -/* - * USB info - */ + while (start) { + if (start->brd_type == brd_type) + return start; + start = KLCF_NEXT_ANY(start); + } + /* Didn't find it. */ + return (lboard_t *) NULL; +} -typedef struct klusb_s { - klinfo_t usb_info; /* controller info */ - void *usb_bus; /* handle to usb_bus_t */ - uint64_t usb_controller; /* ptr to controller info */ - unsigned long pad; -} klusb_t ; - -typedef union klcomp_s { - klcpu_t kc_cpu; - klhub_t kc_hub; - klmembnk_t kc_mem; - klxbow_t kc_xbow; - klbri_t kc_bri; - klrou_t kc_rou; - klgfx_t kc_gfx; - klscsi_t kc_scsi; - klscctl_t kc_scsi_ctl; - klscdev_t kc_scsi_dev; - klmod_serial_num_t kc_snum ; - klusb_t kc_usb; -} klcomp_t; - -typedef union kldev_s { /* for device structure allocation */ - klscdev_t kc_scsi_dev ; - klttydev_t kc_tty_dev ; - klkbddev_t kc_kbd_dev ; -} kldev_t ; /* external declarations of Linux kernel functions. */ extern lboard_t *root_lboard[]; -extern lboard_t *find_lboard_any(lboard_t *start, unsigned char type); -extern lboard_t *find_lboard_nasid(lboard_t *start, nasid_t, unsigned char type); extern klinfo_t *find_component(lboard_t *brd, klinfo_t *kli, unsigned char type); extern klinfo_t *find_first_component(lboard_t *brd, unsigned char type); -extern klcpu_t *nasid_slice_to_cpuinfo(nasid_t, int); - - -extern lboard_t *find_gfxpipe(int pipenum); -extern lboard_t *find_lboard_class_any(lboard_t *start, unsigned char brd_class); -extern lboard_t *find_lboard_class_nasid(lboard_t *start, nasid_t, unsigned char brd_class); -extern lboard_t *find_nic_lboard(lboard_t *, nic_t); -extern lboard_t *find_nic_type_lboard(nasid_t, unsigned char, nic_t); -extern lboard_t *find_lboard_modslot(lboard_t *start, geoid_t geoid); -extern int config_find_nic_router(nasid_t, nic_t, lboard_t **, klrou_t**); -extern int config_find_nic_hub(nasid_t, nic_t, lboard_t **, klhub_t**); -extern int config_find_xbow(nasid_t, lboard_t **, klxbow_t**); -extern int update_klcfg_cpuinfo(nasid_t, int); -extern void board_to_path(lboard_t *brd, char *path); -extern void nic_name_convert(char *old_name, char *new_name); -extern int module_brds(nasid_t nasid, lboard_t **module_brds, int n); -extern lboard_t *brd_from_key(uint64_t key); -extern void device_component_canonical_name_get(lboard_t *,klinfo_t *, - char *); -extern int board_serial_number_get(lboard_t *,char *); -extern nasid_t get_actual_nasid(lboard_t *brd) ; -extern net_vec_t klcfg_discover_route(lboard_t *, lboard_t *, int); #endif /* _ASM_IA64_SN_KLCONFIG_H */ diff --git a/include/asm-ia64/sn/kldir.h b/include/asm-ia64/sn/kldir.h deleted file mode 100644 index 685f110b9ec7..000000000000 --- a/include/asm-ia64/sn/kldir.h +++ /dev/null @@ -1,363 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Derived from IRIX <sys/SN/kldir.h>, revision 1.21. - * - * Copyright (C) 1992-1997,1999,2001-2003 Silicon Graphics, Inc. All Rights Reserved. - * Copyright (C) 1999 by Ralf Baechle - */ -#ifndef _ASM_IA64_SN_KLDIR_H -#define _ASM_IA64_SN_KLDIR_H - -#include <linux/types.h> - -/* - * The kldir memory area resides at a fixed place in each node's memory and - * provides pointers to most other IP27 memory areas. This allows us to - * resize and/or relocate memory areas at a later time without breaking all - * firmware and kernels that use them. Indices in the array are - * permanently dedicated to areas listed below. Some memory areas (marked - * below) reside at a permanently fixed location, but are included in the - * directory for completeness. - */ - -#define KLDIR_MAGIC 0x434d5f53505f5357 - -/* - * The upper portion of the memory map applies during boot - * only and is overwritten by IRIX/SYMMON. - * - * MEMORY MAP PER NODE - * - * 0x2000000 (32M) +-----------------------------------------+ - * | IO6 BUFFERS FOR FLASH ENET IOC3 | - * 0x1F80000 (31.5M) +-----------------------------------------+ - * | IO6 TEXT/DATA/BSS/stack | - * 0x1C00000 (30M) +-----------------------------------------+ - * | IO6 PROM DEBUG TEXT/DATA/BSS/stack | - * 0x0800000 (28M) +-----------------------------------------+ - * | IP27 PROM TEXT/DATA/BSS/stack | - * 0x1B00000 (27M) +-----------------------------------------+ - * | IP27 CFG | - * 0x1A00000 (26M) +-----------------------------------------+ - * | Graphics PROM | - * 0x1800000 (24M) +-----------------------------------------+ - * | 3rd Party PROM drivers | - * 0x1600000 (22M) +-----------------------------------------+ - * | | - * | Free | - * | | - * +-----------------------------------------+ - * | UNIX DEBUG Version | - * 0x190000 (2M--) +-----------------------------------------+ - * | SYMMON | - * | (For UNIX Debug only) | - * 0x34000 (208K) +-----------------------------------------+ - * | SYMMON STACK [NUM_CPU_PER_NODE] | - * | (For UNIX Debug only) | - * 0x25000 (148K) +-----------------------------------------+ - * | KLCONFIG - II (temp) | - * | | - * | ---------------------------- | - * | | - * | UNIX NON-DEBUG Version | - * 0x19000 (100K) +-----------------------------------------+ - * - * - * The lower portion of the memory map contains information that is - * permanent and is used by the IP27PROM, IO6PROM and IRIX. - * - * 0x19000 (100K) +-----------------------------------------+ - * | | - * | PI Error Spools (32K) | - * | | - * 0x12000 (72K) +-----------------------------------------+ - * | Unused | - * 0x11c00 (71K) +-----------------------------------------+ - * | CPU 1 NMI Eframe area | - * 0x11a00 (70.5K) +-----------------------------------------+ - * | CPU 0 NMI Eframe area | - * 0x11800 (70K) +-----------------------------------------+ - * | CPU 1 NMI Register save area | - * 0x11600 (69.5K) +-----------------------------------------+ - * | CPU 0 NMI Register save area | - * 0x11400 (69K) +-----------------------------------------+ - * | GDA (1k) | - * 0x11000 (68K) +-----------------------------------------+ - * | Early cache Exception stack | - * | and/or | - * | kernel/io6prom nmi registers | - * 0x10800 (66k) +-----------------------------------------+ - * | cache error eframe | - * 0x10400 (65K) +-----------------------------------------+ - * | Exception Handlers (UALIAS copy) | - * 0x10000 (64K) +-----------------------------------------+ - * | | - * | | - * | KLCONFIG - I (permanent) (48K) | - * | | - * | | - * | | - * 0x4000 (16K) +-----------------------------------------+ - * | NMI Handler (Protected Page) | - * 0x3000 (12K) +-----------------------------------------+ - * | ARCS PVECTORS (master node only) | - * 0x2c00 (11K) +-----------------------------------------+ - * | ARCS TVECTORS (master node only) | - * 0x2800 (10K) +-----------------------------------------+ - * | LAUNCH [NUM_CPU] | - * 0x2400 (9K) +-----------------------------------------+ - * | Low memory directory (KLDIR) | - * 0x2000 (8K) +-----------------------------------------+ - * | ARCS SPB (1K) | - * 0x1000 (4K) +-----------------------------------------+ - * | Early cache Exception stack | - * | and/or | - * | kernel/io6prom nmi registers | - * 0x800 (2k) +-----------------------------------------+ - * | cache error eframe | - * 0x400 (1K) +-----------------------------------------+ - * | Exception Handlers | - * 0x0 (0K) +-----------------------------------------+ - */ - -#ifdef __ASSEMBLY__ -#define KLDIR_OFF_MAGIC 0x00 -#define KLDIR_OFF_OFFSET 0x08 -#define KLDIR_OFF_POINTER 0x10 -#define KLDIR_OFF_SIZE 0x18 -#define KLDIR_OFF_COUNT 0x20 -#define KLDIR_OFF_STRIDE 0x28 -#endif /* __ASSEMBLY__ */ - -#ifndef __ASSEMBLY__ -typedef struct kldir_ent_s { - u64 magic; /* Indicates validity of entry */ - off_t offset; /* Offset from start of node space */ - unsigned long pointer; /* Pointer to area in some cases */ - size_t size; /* Size in bytes */ - u64 count; /* Repeat count if array, 1 if not */ - size_t stride; /* Stride if array, 0 if not */ - char rsvd[16]; /* Pad entry to 0x40 bytes */ - /* NOTE: These 16 bytes are used in the Partition KLDIR - entry to store partition info. Refer to klpart.h for this. */ -} kldir_ent_t; -#endif /* __ASSEMBLY__ */ - - -#define KLDIR_ENT_SIZE 0x40 -#define KLDIR_MAX_ENTRIES (0x400 / 0x40) - - - -/* - * The upper portion of the memory map applies during boot - * only and is overwritten by IRIX/SYMMON. The minimum memory bank - * size on IP35 is 64M, which provides a limit on the amount of space - * the PROM can assume it has available. - * - * Most of the addresses below are defined as macros in this file, or - * in SN/addrs.h or SN/SN1/addrs.h. - * - * MEMORY MAP PER NODE - * - * 0x4000000 (64M) +-----------------------------------------+ - * | | - * | | - * | IO7 TEXT/DATA/BSS/stack | - * 0x3000000 (48M) +-----------------------------------------+ - * | Free | - * 0x2102000 (>33M) +-----------------------------------------+ - * | IP35 Topology (PCFG) + misc data | - * 0x2000000 (32M) +-----------------------------------------+ - * | IO7 BUFFERS FOR FLASH ENET IOC3 | - * 0x1F80000 (31.5M) +-----------------------------------------+ - * | Free | - * 0x1C00000 (28M) +-----------------------------------------+ - * | IP35 PROM TEXT/DATA/BSS/stack | - * 0x1A00000 (26M) +-----------------------------------------+ - * | Routing temp. space | - * 0x1800000 (24M) +-----------------------------------------+ - * | Diagnostics temp. space | - * 0x1500000 (21M) +-----------------------------------------+ - * | Free | - * 0x1400000 (20M) +-----------------------------------------+ - * | IO7 PROM temporary copy | - * 0x1300000 (19M) +-----------------------------------------+ - * | | - * | Free | - * | (UNIX DATA starts above 0x1000000) | - * | | - * +-----------------------------------------+ - * | UNIX DEBUG Version | - * 0x0310000 (3.1M) +-----------------------------------------+ - * | SYMMON, loaded just below UNIX | - * | (For UNIX Debug only) | - * | | - * | | - * 0x006C000 (432K) +-----------------------------------------+ - * | SYMMON STACK [NUM_CPU_PER_NODE] | - * | (For UNIX Debug only) | - * 0x004C000 (304K) +-----------------------------------------+ - * | | - * | | - * | UNIX NON-DEBUG Version | - * 0x0040000 (256K) +-----------------------------------------+ - * - * - * The lower portion of the memory map contains information that is - * permanent and is used by the IP35PROM, IO7PROM and IRIX. - * - * 0x40000 (256K) +-----------------------------------------+ - * | | - * | KLCONFIG (64K) | - * | | - * 0x30000 (192K) +-----------------------------------------+ - * | | - * | PI Error Spools (64K) | - * | | - * 0x20000 (128K) +-----------------------------------------+ - * | | - * | Unused | - * | | - * 0x19000 (100K) +-----------------------------------------+ - * | Early cache Exception stack (CPU 3)| - * 0x18800 (98K) +-----------------------------------------+ - * | cache error eframe (CPU 3) | - * 0x18400 (97K) +-----------------------------------------+ - * | Exception Handlers (CPU 3) | - * 0x18000 (96K) +-----------------------------------------+ - * | | - * | Unused | - * | | - * 0x13c00 (79K) +-----------------------------------------+ - * | GPDA (8k) | - * 0x11c00 (71K) +-----------------------------------------+ - * | Early cache Exception stack (CPU 2)| - * 0x10800 (66k) +-----------------------------------------+ - * | cache error eframe (CPU 2) | - * 0x10400 (65K) +-----------------------------------------+ - * | Exception Handlers (CPU 2) | - * 0x10000 (64K) +-----------------------------------------+ - * | | - * | Unused | - * | | - * 0x0b400 (45K) +-----------------------------------------+ - * | GDA (1k) | - * 0x0b000 (44K) +-----------------------------------------+ - * | NMI Eframe areas (4) | - * 0x0a000 (40K) +-----------------------------------------+ - * | NMI Register save areas (4) | - * 0x09000 (36K) +-----------------------------------------+ - * | Early cache Exception stack (CPU 1)| - * 0x08800 (34K) +-----------------------------------------+ - * | cache error eframe (CPU 1) | - * 0x08400 (33K) +-----------------------------------------+ - * | Exception Handlers (CPU 1) | - * 0x08000 (32K) +-----------------------------------------+ - * | | - * | | - * | Unused | - * | | - * | | - * 0x04000 (16K) +-----------------------------------------+ - * | NMI Handler (Protected Page) | - * 0x03000 (12K) +-----------------------------------------+ - * | ARCS PVECTORS (master node only) | - * 0x02c00 (11K) +-----------------------------------------+ - * | ARCS TVECTORS (master node only) | - * 0x02800 (10K) +-----------------------------------------+ - * | LAUNCH [NUM_CPU] | - * 0x02400 (9K) +-----------------------------------------+ - * | Low memory directory (KLDIR) | - * 0x02000 (8K) +-----------------------------------------+ - * | ARCS SPB (1K) | - * 0x01000 (4K) +-----------------------------------------+ - * | Early cache Exception stack (CPU 0)| - * 0x00800 (2k) +-----------------------------------------+ - * | cache error eframe (CPU 0) | - * 0x00400 (1K) +-----------------------------------------+ - * | Exception Handlers (CPU 0) | - * 0x00000 (0K) +-----------------------------------------+ - */ - -/* - * NOTE: To change the kernel load address, you must update: - * - the appropriate elspec files in irix/kern/master.d - * - NODEBUGUNIX_ADDR in SN/SN1/addrs.h - * - IP27_FREEMEM_OFFSET below - * - KERNEL_START_OFFSET below (if supporting cells) - */ - - -/* - * This is defined here because IP27_SYMMON_STK_SIZE must be at least what - * we define here. Since it's set up in the prom. We can't redefine it later - * and expect more space to be allocated. The way to find out the true size - * of the symmon stacks is to divide SYMMON_STK_SIZE by SYMMON_STK_STRIDE - * for a particular node. - */ -#define SYMMON_STACK_SIZE 0x8000 - -#if defined (PROM) || defined (SABLE) - -/* - * These defines are prom version dependent. No code other than the IP35 - * prom should attempt to use these values. - */ -#define IP27_LAUNCH_OFFSET 0x2400 -#define IP27_LAUNCH_SIZE 0x400 -#define IP27_LAUNCH_COUNT 4 -#define IP27_LAUNCH_STRIDE 0x100 /* could be as small as 0x80 */ - -#define IP27_KLCONFIG_OFFSET 0x30000 -#define IP27_KLCONFIG_SIZE 0x10000 -#define IP27_KLCONFIG_COUNT 1 -#define IP27_KLCONFIG_STRIDE 0 - -#define IP27_NMI_OFFSET 0x3000 -#define IP27_NMI_SIZE 0x100 -#define IP27_NMI_COUNT 4 -#define IP27_NMI_STRIDE 0x40 - -#define IP27_PI_ERROR_OFFSET 0x20000 -#define IP27_PI_ERROR_SIZE 0x10000 -#define IP27_PI_ERROR_COUNT 1 -#define IP27_PI_ERROR_STRIDE 0 - -#define IP27_SYMMON_STK_OFFSET 0x4c000 -#define IP27_SYMMON_STK_SIZE 0x20000 -#define IP27_SYMMON_STK_COUNT 4 -/* IP27_SYMMON_STK_STRIDE must be >= SYMMON_STACK_SIZE */ -#define IP27_SYMMON_STK_STRIDE 0x8000 - -#define IP27_FREEMEM_OFFSET 0x40000 -#define IP27_FREEMEM_SIZE (-1) -#define IP27_FREEMEM_COUNT 1 -#define IP27_FREEMEM_STRIDE 0 - -#endif /* PROM || SABLE*/ -/* - * There will be only one of these in a partition so the IO7 must set it up. - */ -#define IO6_GDA_OFFSET 0xb000 -#define IO6_GDA_SIZE 0x400 -#define IO6_GDA_COUNT 1 -#define IO6_GDA_STRIDE 0 - -/* - * save area of kernel nmi regs in the prom format - */ -#define IP27_NMI_KREGS_OFFSET 0x9000 -#define IP27_NMI_KREGS_CPU_SIZE 0x400 -/* - * save area of kernel nmi regs in eframe format - */ -#define IP27_NMI_EFRAME_OFFSET 0xa000 -#define IP27_NMI_EFRAME_SIZE 0x400 - -#define GPDA_OFFSET 0x11c00 - -#endif /* _ASM_IA64_SN_KLDIR_H */ diff --git a/include/asm-ia64/sn/ksys/elsc.h b/include/asm-ia64/sn/ksys/elsc.h deleted file mode 100644 index 01bd746af95c..000000000000 --- a/include/asm-ia64/sn/ksys/elsc.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992-1997, 2000-2003 Silicon Graphics, Inc. All Rights Reserved. - */ -#ifndef _ASM_IA64_SN_KSYS_ELSC_H -#define _ASM_IA64_SN_KSYS_ELSC_H - -/* - * Error codes - * - * The possible ELSC error codes are a superset of the I2C error codes, - * so ELSC error codes begin at -100. - */ - -#define ELSC_ERROR_NONE 0 - -#define ELSC_ERROR_CMD_SEND (-100) /* Error sending command */ -#define ELSC_ERROR_CMD_CHECKSUM (-101) /* Command checksum bad */ -#define ELSC_ERROR_CMD_UNKNOWN (-102) /* Unknown command */ -#define ELSC_ERROR_CMD_ARGS (-103) /* Invalid argument(s) */ -#define ELSC_ERROR_CMD_PERM (-104) /* Permission denied */ -#define ELSC_ERROR_CMD_STATE (-105) /* not allowed in this state*/ - -#define ELSC_ERROR_RESP_TIMEOUT (-110) /* ELSC response timeout */ -#define ELSC_ERROR_RESP_CHECKSUM (-111) /* Response checksum bad */ -#define ELSC_ERROR_RESP_FORMAT (-112) /* Response format error */ -#define ELSC_ERROR_RESP_DIR (-113) /* Response direction error */ - -#define ELSC_ERROR_MSG_LOST (-120) /* Queue full; msg. lost */ -#define ELSC_ERROR_LOCK_TIMEOUT (-121) /* ELSC response timeout */ -#define ELSC_ERROR_DATA_SEND (-122) /* Error sending data */ -#define ELSC_ERROR_NIC (-123) /* NIC processing error */ -#define ELSC_ERROR_NVMAGIC (-124) /* Bad magic no. in NVRAM */ -#define ELSC_ERROR_MODULE (-125) /* Moduleid processing err */ - -#endif /* _ASM_IA64_SN_KSYS_ELSC_H */ diff --git a/include/asm-ia64/sn/ksys/l1.h b/include/asm-ia64/sn/ksys/l1.h deleted file mode 100644 index 19179db75fbc..000000000000 --- a/include/asm-ia64/sn/ksys/l1.h +++ /dev/null @@ -1,141 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All Rights Reserved. - */ - -#ifndef _ASM_IA64_SN_KSYS_L1_H -#define _ASM_IA64_SN_KSYS_L1_H - -#include <asm/sn/types.h> - -/* L1 Target Addresses */ -/* - * L1 commands and responses use source/target addresses that are - * 32 bits long. These are broken up into multiple bitfields that - * specify the type of the target controller (could actually be L2 - * L3, not just L1), the rack and bay of the target, and the task - * id (L1 functionality is divided into several independent "tasks" - * that can each receive command requests and transmit responses) - */ -#define L1_ADDR_TYPE_L1 0x00 /* L1 system controller */ -#define L1_ADDR_TYPE_L2 0x01 /* L2 system controller */ -#define L1_ADDR_TYPE_L3 0x02 /* L3 system controller */ -#define L1_ADDR_TYPE_CBRICK 0x03 /* attached C brick */ -#define L1_ADDR_TYPE_IOBRICK 0x04 /* attached I/O brick */ -#define L1_ADDR_TASK_SHFT 0 -#define L1_ADDR_TASK_MASK 0x0000001F -#define L1_ADDR_TASK_INVALID 0x00 /* invalid task */ -#define L1_ADDR_TASK_IROUTER 0x01 /* iRouter */ -#define L1_ADDR_TASK_SYS_MGMT 0x02 /* system management port */ -#define L1_ADDR_TASK_CMD 0x03 /* command interpreter */ -#define L1_ADDR_TASK_ENV 0x04 /* environmental monitor */ -#define L1_ADDR_TASK_BEDROCK 0x05 /* bedrock */ -#define L1_ADDR_TASK_GENERAL 0x06 /* general requests */ - -/* response argument types */ -#define L1_ARG_INT 0x00 /* 4-byte integer (big-endian) */ -#define L1_ARG_ASCII 0x01 /* null-terminated ASCII string */ -#define L1_ARG_UNKNOWN 0x80 /* unknown data type. The low - * 7 bits will contain the data - * length. */ - -/* response codes */ -#define L1_RESP_OK 0 /* no problems encountered */ -#define L1_RESP_IROUTER (- 1) /* iRouter error */ -#define L1_RESP_ARGC (-100) /* arg count mismatch */ -#define L1_RESP_REQC (-101) /* bad request code */ -#define L1_RESP_NAVAIL (-104) /* requested data not available */ -#define L1_RESP_ARGVAL (-105) /* arg value out of range */ -#define L1_RESP_INVAL (-107) /* requested data invalid */ - -/* L1 general requests */ - -/* request codes */ -#define L1_REQ_RDBG 0x0001 /* read debug switches */ -#define L1_REQ_RRACK 0x0002 /* read brick rack & bay */ -#define L1_REQ_RRBT 0x0003 /* read brick rack, bay & type */ -#define L1_REQ_SER_NUM 0x0004 /* read brick serial number */ -#define L1_REQ_FW_REV 0x0005 /* read L1 firmware revision */ -#define L1_REQ_EEPROM 0x0006 /* read EEPROM info */ -#define L1_REQ_EEPROM_FMT 0x0007 /* get EEPROM data format & size */ -#define L1_REQ_SYS_SERIAL 0x0008 /* read system serial number */ -#define L1_REQ_PARTITION_GET 0x0009 /* read partition id */ -#define L1_REQ_PORTSPEED 0x000a /* get ioport speed */ - -#define L1_REQ_CONS_SUBCH 0x1002 /* select this node's console - subchannel */ -#define L1_REQ_CONS_NODE 0x1003 /* volunteer to be the master - (console-hosting) node */ -#define L1_REQ_DISP1 0x1004 /* write line 1 of L1 display */ -#define L1_REQ_DISP2 0x1005 /* write line 2 of L1 display */ -#define L1_REQ_PARTITION_SET 0x1006 /* set partition id */ -#define L1_REQ_EVENT_SUBCH 0x1007 /* set the subchannel for system - controller event transmission */ - -#define L1_REQ_RESET 0x2000 /* request a full system reset */ -#define L1_REQ_PCI_UP 0x2001 /* power up pci slot or bus */ -#define L1_REQ_PCI_DOWN 0x2002 /* power down pci slot or bus */ -#define L1_REQ_PCI_RESET 0x2003 /* reset pci bus or slot */ - -/* L1 command interpreter requests */ - -/* request codes */ -#define L1_REQ_EXEC_CMD 0x0000 /* interpret and execute an ASCII - command string */ - -/* brick type response codes */ -#define L1_BRICKTYPE_PX 0x23 /* # */ -#define L1_BRICKTYPE_PE 0x25 /* % */ -#define L1_BRICKTYPE_N_p0 0x26 /* & */ -#define L1_BRICKTYPE_IP45 0x34 /* 4 */ -#define L1_BRICKTYPE_IP41 0x35 /* 5 */ -#define L1_BRICKTYPE_TWISTER 0x36 /* 6 */ /* IP53 & ROUTER */ -#define L1_BRICKTYPE_IX 0x3d /* = */ -#define L1_BRICKTYPE_IP34 0x61 /* a */ -#define L1_BRICKTYPE_C 0x63 /* c */ -#define L1_BRICKTYPE_I 0x69 /* i */ -#define L1_BRICKTYPE_N 0x6e /* n */ -#define L1_BRICKTYPE_OPUS 0x6f /* o */ -#define L1_BRICKTYPE_P 0x70 /* p */ -#define L1_BRICKTYPE_R 0x72 /* r */ -#define L1_BRICKTYPE_CHI_CG 0x76 /* v */ -#define L1_BRICKTYPE_X 0x78 /* x */ -#define L1_BRICKTYPE_X2 0x79 /* y */ - -/* EEPROM codes (for the "read EEPROM" request) */ -/* c brick */ -#define L1_EEP_NODE 0x00 /* node board */ -#define L1_EEP_PIMM0 0x01 -#define L1_EEP_PIMM(x) (L1_EEP_PIMM0+(x)) -#define L1_EEP_DIMM0 0x03 -#define L1_EEP_DIMM(x) (L1_EEP_DIMM0+(x)) - -/* other brick types */ -#define L1_EEP_POWER 0x00 /* power board */ -#define L1_EEP_LOGIC 0x01 /* logic board */ - -/* info area types */ -#define L1_EEP_CHASSIS 1 /* chassis info area */ -#define L1_EEP_BOARD 2 /* board info area */ -#define L1_EEP_IUSE 3 /* internal use area */ -#define L1_EEP_SPD 4 /* serial presence detect record */ - -#define L1_DISPLAY_LINE_LENGTH 12 /* L1 display characters/line */ - -#ifdef L1_DISP_2LINES -#define L1_DISPLAY_LINES 2 /* number of L1 display lines */ -#else -#define L1_DISPLAY_LINES 1 /* number of L1 display lines available - * to system software */ -#endif - -int elsc_display_line(nasid_t nasid, char *line, int lnum); -int iobrick_rack_bay_type_get( nasid_t nasid, unsigned int *rack, - unsigned int *bay, unsigned int *brick_type ); -int iomoduleid_get( nasid_t nasid ); - - -#endif /* _ASM_IA64_SN_KSYS_L1_H */ diff --git a/include/asm-ia64/sn/l1.h b/include/asm-ia64/sn/l1.h new file mode 100644 index 000000000000..d5dbd55e44b5 --- /dev/null +++ b/include/asm-ia64/sn/l1.h @@ -0,0 +1,36 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992-1997,2000-2004 Silicon Graphics, Inc. All Rights Reserved. + */ + +#ifndef _ASM_IA64_SN_L1_H +#define _ASM_IA64_SN_L1_H + +/* brick type response codes */ +#define L1_BRICKTYPE_PX 0x23 /* # */ +#define L1_BRICKTYPE_PE 0x25 /* % */ +#define L1_BRICKTYPE_N_p0 0x26 /* & */ +#define L1_BRICKTYPE_IP45 0x34 /* 4 */ +#define L1_BRICKTYPE_IP41 0x35 /* 5 */ +#define L1_BRICKTYPE_TWISTER 0x36 /* 6 */ /* IP53 & ROUTER */ +#define L1_BRICKTYPE_IX 0x3d /* = */ +#define L1_BRICKTYPE_IP34 0x61 /* a */ +#define L1_BRICKTYPE_GA 0x62 /* b */ +#define L1_BRICKTYPE_C 0x63 /* c */ +#define L1_BRICKTYPE_OPUS_TIO 0x66 /* f */ +#define L1_BRICKTYPE_I 0x69 /* i */ +#define L1_BRICKTYPE_N 0x6e /* n */ +#define L1_BRICKTYPE_OPUS 0x6f /* o */ +#define L1_BRICKTYPE_P 0x70 /* p */ +#define L1_BRICKTYPE_R 0x72 /* r */ +#define L1_BRICKTYPE_CHI_CG 0x76 /* v */ +#define L1_BRICKTYPE_X 0x78 /* x */ +#define L1_BRICKTYPE_X2 0x79 /* y */ +#define L1_BRICKTYPE_SA 0x5e /* ^ */ /* TIO bringup brick */ +#define L1_BRICKTYPE_PA 0x6a /* j */ +#define L1_BRICKTYPE_IA 0x6b /* k */ + +#endif /* _ASM_IA64_SN_L1_H */ diff --git a/include/asm-ia64/sn/labelcl.h b/include/asm-ia64/sn/labelcl.h deleted file mode 100644 index b5b9503f1908..000000000000 --- a/include/asm-ia64/sn/labelcl.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_LABELCL_H -#define _ASM_IA64_SN_LABELCL_H - -#define LABELCL_MAGIC 0x4857434c /* 'HWLC' */ -#define LABEL_LENGTH_MAX 256 /* Includes NULL char */ -#define INFO_DESC_PRIVATE (-1) /* default */ -#define INFO_DESC_EXPORT 0 /* export info itself */ - -/* - * Description of a label entry. - */ -typedef struct label_info_s { - char *name; - arb_info_desc_t desc; - arbitrary_info_t info; -} label_info_t; - -/* - * Definition of the data structure that provides the link to - * the hwgraph fastinfo and the label entries associated with a - * particular hwgraph entry. - */ -typedef struct labelcl_info_s { - unsigned long hwcl_magic; - unsigned long num_labels; - void *label_list; - arbitrary_info_t IDX_list[HWGRAPH_NUM_INDEX_INFO]; -} labelcl_info_t; - -/* - * Definitions for the string table that holds the actual names - * of the labels. - */ -struct string_table_item { - struct string_table_item *next; - char string[1]; -}; - -struct string_table { - struct string_table_item *string_table_head; - long string_table_generation; -}; - - -#define STRTBL_BASIC_SIZE ((size_t)(((struct string_table_item *)0)->string)) -#define STRTBL_ITEM_SIZE(str_length) (STRTBL_BASIC_SIZE + (str_length) + 1) - -#define STRTBL_ALLOC(str_length) \ - ((struct string_table_item *)kmalloc(STRTBL_ITEM_SIZE(str_length), GFP_KERNEL)) - -#define STRTBL_FREE(ptr) kfree(ptr) - - -extern labelcl_info_t *labelcl_info_create(void); -extern int labelcl_info_destroy(labelcl_info_t *); -extern int labelcl_info_add_LBL(vertex_hdl_t, char *, arb_info_desc_t, arbitrary_info_t); -extern int labelcl_info_remove_LBL(vertex_hdl_t, char *, arb_info_desc_t *, arbitrary_info_t *); -extern int labelcl_info_replace_LBL(vertex_hdl_t, char *, arb_info_desc_t, - arbitrary_info_t, arb_info_desc_t *, arbitrary_info_t *); -extern int labelcl_info_get_LBL(vertex_hdl_t, char *, arb_info_desc_t *, - arbitrary_info_t *); -extern int labelcl_info_get_next_LBL(vertex_hdl_t, char *, arb_info_desc_t *, - arbitrary_info_t *, labelcl_info_place_t *); -extern int labelcl_info_replace_IDX(vertex_hdl_t, int, arbitrary_info_t, - arbitrary_info_t *); -extern int labelcl_info_connectpt_set(vertex_hdl_t, vertex_hdl_t); -extern int labelcl_info_get_IDX(vertex_hdl_t, int, arbitrary_info_t *); - -#endif /* _ASM_IA64_SN_LABELCL_H */ diff --git a/include/asm-ia64/sn/leds.h b/include/asm-ia64/sn/leds.h index d2ee23449e9f..04fc929cb0fb 100644 --- a/include/asm-ia64/sn/leds.h +++ b/include/asm-ia64/sn/leds.h @@ -1,16 +1,14 @@ -#ifndef _ASM_IA64_SN_LEDS_H -#define _ASM_IA64_SN_LEDS_H - /* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. - * Copyright (C) 2000-2003 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved. */ +#ifndef _ASM_IA64_SN_LEDS_H +#define _ASM_IA64_SN_LEDS_H #include <asm/sn/addrs.h> #include <asm/sn/pda.h> -#include <asm/sn/sn2/shub.h> #define LED0 (LOCAL_MMR_ADDR(SH_REAL_JUNK_BUS_LED0)) #define LED_CPU_SHIFT 16 diff --git a/include/asm-ia64/sn/module.h b/include/asm-ia64/sn/module.h index 172f459fc01e..734e980ece2f 100644 --- a/include/asm-ia64/sn/module.h +++ b/include/asm-ia64/sn/module.h @@ -3,24 +3,11 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_MODULE_H #define _ASM_IA64_SN_MODULE_H -#include <asm/sn/klconfig.h> -#include <asm/sn/ksys/elsc.h> - -#define MODULE_MAX 128 -#define MODULE_MAX_NODES 2 -#define MODULE_HIST_CNT 16 -#define MAX_MODULE_LEN 16 - -/* Well-known module IDs */ -#define MODULE_UNKNOWN (-2) /* initial value of klconfig brd_module */ -/* #define INVALID_MODULE (-1) ** generic invalid moduleid_t (arch.h) */ -#define MODULE_NOT_SET 0 /* module ID not set in sys ctlrs. */ - /* parameter for format_module_id() */ #define MODULE_FORMAT_BRIEF 1 #define MODULE_FORMAT_LONG 2 @@ -59,13 +46,6 @@ #define MODULE_GET_BPOS(_m) (((_m) & MODULE_BPOS_MASK) >> MODULE_BPOS_SHFT) /* - * Macros for constructing moduleid_t's - */ -#define RBT_TO_MODULE(_r, _b, _t) ((_r) << MODULE_RACK_SHFT | \ - (_b) << MODULE_BPOS_SHFT | \ - (_t) << MODULE_BTYPE_SHFT) - -/* * Macros for encoding and decoding rack IDs * A rack number consists of three parts: * class (0==CPU/mixed, 1==I/O), group, number @@ -73,12 +53,12 @@ * Rack number is stored just as it is displayed on the screen: * a 3-decimal-digit number. */ -#define RACK_CLASS_DVDR 100 -#define RACK_GROUP_DVDR 10 -#define RACK_NUM_DVDR 1 +#define RACK_CLASS_DVDR 100 +#define RACK_GROUP_DVDR 10 +#define RACK_NUM_DVDR 1 -#define RACK_CREATE_RACKID(_c, _g, _n) ((_c) * RACK_CLASS_DVDR + \ - (_g) * RACK_GROUP_DVDR + (_n) * RACK_NUM_DVDR) +#define RACK_CREATE_RACKID(_c, _g, _n) ((_c) * RACK_CLASS_DVDR + \ + (_g) * RACK_GROUP_DVDR + (_n) * RACK_NUM_DVDR) #define RACK_GET_CLASS(_r) ((_r) / RACK_CLASS_DVDR) #define RACK_GET_GROUP(_r) (((_r) - RACK_GET_CLASS(_r) * \ @@ -90,29 +70,29 @@ /* * Macros for encoding and decoding rack IDs * A rack number consists of three parts: - * class 1 bit, 0==CPU/mixed, 1==I/O - * group 2 bits for CPU/mixed, 3 bits for I/O - * number 3 bits for CPU/mixed, 2 bits for I/O (1 based) + * class 1 bit, 0==CPU/mixed, 1==I/O + * group 2 bits for CPU/mixed, 3 bits for I/O + * number 3 bits for CPU/mixed, 2 bits for I/O (1 based) */ -#define RACK_GROUP_BITS(_r) (RACK_GET_CLASS(_r) ? 3 : 2) -#define RACK_NUM_BITS(_r) (RACK_GET_CLASS(_r) ? 2 : 3) +#define RACK_GROUP_BITS(_r) (RACK_GET_CLASS(_r) ? 3 : 2) +#define RACK_NUM_BITS(_r) (RACK_GET_CLASS(_r) ? 2 : 3) -#define RACK_CLASS_MASK(_r) 0x20 -#define RACK_CLASS_SHFT(_r) 5 -#define RACK_ADD_CLASS(_r, _c) \ - ((_r) |= (_c) << RACK_CLASS_SHFT(_r) & RACK_CLASS_MASK(_r)) +#define RACK_CLASS_MASK(_r) 0x20 +#define RACK_CLASS_SHFT(_r) 5 +#define RACK_ADD_CLASS(_r, _c) \ + ((_r) |= (_c) << RACK_CLASS_SHFT(_r) & RACK_CLASS_MASK(_r)) -#define RACK_GROUP_SHFT(_r) RACK_NUM_BITS(_r) -#define RACK_GROUP_MASK(_r) \ - ( (((unsigned)1<<RACK_GROUP_BITS(_r)) - 1) << RACK_GROUP_SHFT(_r) ) -#define RACK_ADD_GROUP(_r, _g) \ - ((_r) |= (_g) << RACK_GROUP_SHFT(_r) & RACK_GROUP_MASK(_r)) +#define RACK_GROUP_SHFT(_r) RACK_NUM_BITS(_r) +#define RACK_GROUP_MASK(_r) \ + ( (((unsigned)1<<RACK_GROUP_BITS(_r)) - 1) << RACK_GROUP_SHFT(_r) ) +#define RACK_ADD_GROUP(_r, _g) \ + ((_r) |= (_g) << RACK_GROUP_SHFT(_r) & RACK_GROUP_MASK(_r)) -#define RACK_NUM_SHFT(_r) 0 -#define RACK_NUM_MASK(_r) \ - ( (((unsigned)1<<RACK_NUM_BITS(_r)) - 1) << RACK_NUM_SHFT(_r) ) -#define RACK_ADD_NUM(_r, _n) \ - ((_r) |= ((_n) - 1) << RACK_NUM_SHFT(_r) & RACK_NUM_MASK(_r)) +#define RACK_NUM_SHFT(_r) 0 +#define RACK_NUM_MASK(_r) \ + ( (((unsigned)1<<RACK_NUM_BITS(_r)) - 1) << RACK_NUM_SHFT(_r) ) +#define RACK_ADD_NUM(_r, _n) \ + ((_r) |= ((_n) - 1) << RACK_NUM_SHFT(_r) & RACK_NUM_MASK(_r)) /* @@ -135,60 +115,13 @@ extern char brick_types[]; #define MODULE_IXBRICK 10 #define MODULE_CGBRICK 11 #define MODULE_OPUSBRICK 12 +#define MODULE_SABRICK 13 /* TIO BringUp Brick */ +#define MODULE_IABRICK 14 +#define MODULE_PABRICK 15 +#define MODULE_GABRICK 16 +#define MODULE_OPUS_TIO 17 /* OPUS TIO Riser */ -/* - * Moduleid_t comparison macros - */ -/* Don't compare the brick type: only the position is significant */ -#define MODULE_CMP(_m1, _m2) (((_m1)&(MODULE_RACK_MASK|MODULE_BPOS_MASK)) -\ - ((_m2)&(MODULE_RACK_MASK|MODULE_BPOS_MASK))) -#define MODULE_MATCH(_m1, _m2) (MODULE_CMP((_m1),(_m2)) == 0) - -typedef struct module_s module_t; - -struct module_s { - moduleid_t id; /* Module ID of this module */ - - spinlock_t lock; /* Lock for this structure */ - - /* List of nodes in this module */ - cnodeid_t nodes[MAX_SLABS + 1]; - geoid_t geoid[MAX_SLABS + 1]; - - /* Fields for Module System Controller */ - int mesgpend; /* Message pending */ - int shutdown; /* Shutdown in progress */ - time_t intrhist[MODULE_HIST_CNT]; - int histptr; - - int hbt_active; /* MSC heartbeat monitor active */ - uint64_t hbt_last; /* RTC when last heartbeat sent */ - - /* Module serial number info */ - union { - char snum_str[MAX_SERIAL_NUM_SIZE]; /* used by CONFIG_SGI_IP27 */ - uint64_t snum_int; /* used by speedo */ - } snum; - int snum_valid; - - int disable_alert; - int count_down; - - /* System serial number info (used by SN1) */ - char sys_snum[MAX_SERIAL_NUM_SIZE]; - int sys_snum_valid; -}; - -/* module.c */ -extern module_t *sn_modules[MODULE_MAX]; /* Indexed by cmoduleid_t */ -extern int nummodules; - -extern module_t *module_lookup(moduleid_t id); -extern void format_module_id(char *buffer, moduleid_t m, int fmt); -extern int parse_module_id(char *buffer); - -#ifdef __cplusplus -} -#endif +extern char brick_types[]; +extern void format_module_id(char *, moduleid_t, int); #endif /* _ASM_IA64_SN_MODULE_H */ diff --git a/include/asm-ia64/sn/nodepda.h b/include/asm-ia64/sn/nodepda.h index d76ef9ea99ff..e9510d82d7bd 100644 --- a/include/asm-ia64/sn/nodepda.h +++ b/include/asm-ia64/sn/nodepda.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_NODEPDA_H #define _ASM_IA64_SN_NODEPDA_H @@ -14,9 +14,7 @@ #include <asm/sn/intr.h> #include <asm/sn/router.h> #include <asm/sn/pda.h> -#include <asm/sn/module.h> #include <asm/sn/bte.h> -#include <asm/sn/sn2/arch.h> /* * NUMA Node-Specific Data structures are defined in this file. @@ -32,32 +30,8 @@ * This structure provides a convenient way of keeping together * all per-node data structures. */ - - - struct nodepda_s { - vertex_hdl_t xbow_vhdl; - nasid_t xbow_peer; /* NASID of our peer hub on xbow */ - struct semaphore xbow_sema; /* Sema for xbow synchronization */ - slotid_t slotdesc; - geoid_t geoid; - module_t *module; /* Pointer to containing module */ - xwidgetnum_t basew_id; - vertex_hdl_t basew_xc; - int hubticks; - int num_routers; /* XXX not setup! Total routers in the system */ - - - char *hwg_node_name; /* hwgraph node name */ - vertex_hdl_t node_vertex; /* Hwgraph vertex for this node */ - void *pdinfo; /* Platform-dependent per-node info */ - - - nodepda_router_info_t *npda_rip_first; - nodepda_router_info_t **npda_rip_last; - - spinlock_t bist_lock; /* @@ -76,17 +50,6 @@ struct nodepda_s { typedef struct nodepda_s nodepda_t; -struct irqpda_s { - int num_irq_used; - char irq_flags[NR_IRQS]; - struct pci_dev *device_dev[NR_IRQS]; - char share_count[NR_IRQS]; - struct pci_dev *curr; -}; - -typedef struct irqpda_s irqpda_t; - - /* * Access Functions for node PDA. * Since there is one nodepda for each node, we need a convenient mechanism @@ -104,32 +67,10 @@ typedef struct irqpda_s irqpda_t; #define nodepda pda->p_nodepda /* Ptr to this node's PDA */ #define NODEPDA(cnode) (nodepda->pernode_pdaindr[cnode]) - -/* - * Macros to access data structures inside nodepda - */ -#define NODE_MODULEID(cnode) geo_module((NODEPDA(cnode)->geoid)) -#define NODE_SLOTID(cnode) (NODEPDA(cnode)->slotdesc) - - -/* - * Quickly convert a compact node ID into a hwgraph vertex - */ -#define cnodeid_to_vertex(cnodeid) (NODEPDA(cnodeid)->node_vertex) - - /* * Check if given a compact node id the corresponding node has all the * cpus disabled. */ #define is_headless_node(cnode) (nr_cpus_node(cnode) == 0) -/* - * Check if given a node vertex handle the corresponding node has all the - * cpus disabled. - */ -#define is_headless_node_vertex(_nodevhdl) \ - is_headless_node(nodevertex_to_cnodeid(_nodevhdl)) - - #endif /* _ASM_IA64_SN_NODEPDA_H */ diff --git a/include/asm-ia64/sn/pci/bridge.h b/include/asm-ia64/sn/pci/bridge.h deleted file mode 100644 index 6b6d346ce1c9..000000000000 --- a/include/asm-ia64/sn/pci/bridge.h +++ /dev/null @@ -1,1895 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (c) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_SN_PCI_BRIDGE_H -#define _ASM_SN_PCI_BRIDGE_H - - -/* - * bridge.h - header file for bridge chip and bridge portion of xbridge chip - * - * Also including offsets for unique PIC registers. - * The PIC asic is a follow-on to Xbridge and most of its registers are - * identical to those of Xbridge. PIC is different than Xbridge in that - * it will accept 64 bit register access and that, in some cases, data - * is kept in bits 63:32. PIC registers that are identical to Xbridge - * may be accessed identically to the Xbridge registers, allowing for lots - * of code reuse. Here are the access rules as described in the PIC - * manual: - * - * o Read a word on a DW boundary returns D31:00 of reg. - * o Read a DW on a DW boundary returns D63:00 of reg. - * o Write a word on a DW boundary loads D31:00 of reg. - * o Write a DW on a DW boundary loads D63:00 of reg. - * o No support for word boundary access that is not double word - * aligned. - * - * So we can reuse a lot of bridge_s for PIC. In bridge_s are included - * #define tags and unions for 64 bit access to PIC registers. - * For a detailed PIC register layout see pic.h. - */ - -#include <linux/config.h> -#include <asm/sn/xtalk/xwidget.h> -#include <asm/sn/pci/pic.h> - -#define BRIDGE_REG_GET32(reg) \ - __swab32( *(volatile uint32_t *) (((uint64_t)reg)^4) ) - -#define BRIDGE_REG_SET32(reg) \ - *(volatile uint32_t *) (((uint64_t)reg)^4) - -/* I/O page size */ - -#if PAGE_SIZE == 4096 -#define IOPFNSHIFT 12 /* 4K per mapped page */ -#else -#define IOPFNSHIFT 14 /* 16K per mapped page */ -#endif /* PAGE_SIZE */ - -#define IOPGSIZE (1 << IOPFNSHIFT) -#define IOPG(x) ((x) >> IOPFNSHIFT) -#define IOPGOFF(x) ((x) & (IOPGSIZE-1)) - -/* Bridge RAM sizes */ - -#define BRIDGE_INTERNAL_ATES 128 -#define XBRIDGE_INTERNAL_ATES 1024 - -#define BRIDGE_ATE_RAM_SIZE (BRIDGE_INTERNAL_ATES<<3) /* 1kB ATE */ -#define XBRIDGE_ATE_RAM_SIZE (XBRIDGE_INTERNAL_ATES<<3) /* 8kB ATE */ - -#define PIC_WR_REQ_BUFSIZE 256 - -#define BRIDGE_CONFIG_BASE 0x20000 /* start of bridge's */ - /* map to each device's */ - /* config space */ -#define BRIDGE_CONFIG1_BASE 0x28000 /* type 1 device config space */ -#define BRIDGE_CONFIG_END 0x30000 -#define BRIDGE_CONFIG_SLOT_SIZE 0x1000 /* each map == 4k */ - -#define BRIDGE_SSRAM_512K 0x00080000 /* 512kB */ -#define BRIDGE_SSRAM_128K 0x00020000 /* 128kB */ -#define BRIDGE_SSRAM_64K 0x00010000 /* 64kB */ -#define BRIDGE_SSRAM_0K 0x00000000 /* 0kB */ - -/* ======================================================================== - * Bridge address map - */ - -#ifndef __ASSEMBLY__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * All accesses to bridge hardware registers must be done - * using 32-bit loads and stores. - */ -typedef uint32_t bridgereg_t; - -typedef uint64_t bridge_ate_t; - -/* pointers to bridge ATEs - * are always "pointer to volatile" - */ -typedef volatile bridge_ate_t *bridge_ate_p; - -/* - * It is generally preferred that hardware registers on the bridge - * are located from C code via this structure. - * - * Generated from Bridge spec dated 04oct95 - */ - - -/* - * pic_widget_cfg_s is a local definition of widget_cfg_t but with - * a union of 64bit & 32bit registers, since PIC has 64bit widget - * registers but BRIDGE and XBRIDGE have 32bit. PIC registers that - * have valid bits (ie. not just reserved) in the upper 32bits are - * defined as a union so we can access them as 64bit for PIC and - * as 32bit for BRIDGE and XBRIDGE. - */ -typedef volatile struct pic_widget_cfg_s { - bridgereg_t _b_wid_id; /* 0x000004 */ - bridgereg_t _pad_000000; - - union { - picreg_t _p_wid_stat; /* 0x000008 */ - struct { - bridgereg_t _b_wid_stat; /* 0x00000C */ - bridgereg_t _b_pad_000008; - } _b; - } u_wid_stat; - #define __p_wid_stat_64 u_wid_stat._p_wid_stat - #define __b_wid_stat u_wid_stat._b._b_wid_stat - - bridgereg_t _b_wid_err_upper; /* 0x000014 */ - bridgereg_t _pad_000010; - - union { - picreg_t _p_wid_err_lower; /* 0x000018 */ - struct { - bridgereg_t _b_wid_err_lower; /* 0x00001C */ - bridgereg_t _b_pad_000018; - } _b; - } u_wid_err_lower; - #define __p_wid_err_64 u_wid_err_lower._p_wid_err_lower - #define __b_wid_err_lower u_wid_err_lower._b._b_wid_err_lower - - union { - picreg_t _p_wid_control; /* 0x000020 */ - struct { - bridgereg_t _b_wid_control; /* 0x000024 */ - bridgereg_t _b_pad_000020; - } _b; - } u_wid_control; - #define __p_wid_control_64 u_wid_control._p_wid_control - #define __b_wid_control u_wid_control._b._b_wid_control - - bridgereg_t _b_wid_req_timeout; /* 0x00002C */ - bridgereg_t _pad_000028; - - bridgereg_t _b_wid_int_upper; /* 0x000034 */ - bridgereg_t _pad_000030; - - union { - picreg_t _p_wid_int_lower; /* 0x000038 */ - struct { - bridgereg_t _b_wid_int_lower; /* 0x00003C */ - bridgereg_t _b_pad_000038; - } _b; - } u_wid_int_lower; - #define __p_wid_int_64 u_wid_int_lower._p_wid_int_lower - #define __b_wid_int_lower u_wid_int_lower._b._b_wid_int_lower - - bridgereg_t _b_wid_err_cmdword; /* 0x000044 */ - bridgereg_t _pad_000040; - - bridgereg_t _b_wid_llp; /* 0x00004C */ - bridgereg_t _pad_000048; - - bridgereg_t _b_wid_tflush; /* 0x000054 */ - bridgereg_t _pad_000050; -} pic_widget_cfg_t; - -/* - * BRIDGE, XBRIDGE, PIC register definitions. NOTE: Prior to PIC, registers - * were a 32bit quantity and double word aligned (and only accessible as a - * 32bit word. PIC registers are 64bits and accessible as words or double - * words. PIC registers that have valid bits (ie. not just reserved) in the - * upper 32bits are defined as a union of one 64bit picreg_t and two 32bit - * bridgereg_t so we can access them both ways. - * - * It is generally preferred that hardware registers on the bridge are - * located from C code via this structure. - * - * Generated from Bridge spec dated 04oct95 - */ - -typedef volatile struct bridge_s { - - /* 0x000000-0x00FFFF -- Local Registers */ - - /* 0x000000-0x000057 -- Standard Widget Configuration */ - union { - widget_cfg_t xtalk_widget_def; /* 0x000000 */ - pic_widget_cfg_t local_widget_def; /* 0x000000 */ - } u_wid; - - /* 32bit widget register access via the widget_cfg_t */ - #define b_widget u_wid.xtalk_widget_def - - /* 32bit widget register access via the pic_widget_cfg_t */ - #define b_wid_id u_wid.local_widget_def._b_wid_id - #define b_wid_stat u_wid.local_widget_def.__b_wid_stat - #define b_wid_err_upper u_wid.local_widget_def._b_wid_err_upper - #define b_wid_err_lower u_wid.local_widget_def.__b_wid_err_lower - #define b_wid_control u_wid.local_widget_def.__b_wid_control - #define b_wid_req_timeout u_wid.local_widget_def._b_wid_req_timeout - #define b_wid_int_upper u_wid.local_widget_def._b_wid_int_upper - #define b_wid_int_lower u_wid.local_widget_def.__b_wid_int_lower - #define b_wid_err_cmdword u_wid.local_widget_def._b_wid_err_cmdword - #define b_wid_llp u_wid.local_widget_def._b_wid_llp - #define b_wid_tflush u_wid.local_widget_def._b_wid_tflush - - /* 64bit widget register access via the pic_widget_cfg_t */ - #define p_wid_stat_64 u_wid.local_widget_def.__p_wid_stat_64 - #define p_wid_err_64 u_wid.local_widget_def.__p_wid_err_64 - #define p_wid_control_64 u_wid.local_widget_def.__p_wid_control_64 - #define p_wid_int_64 u_wid.local_widget_def.__p_wid_int_64 - - /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */ - bridgereg_t b_wid_aux_err; /* 0x00005C */ - bridgereg_t _pad_000058; - - bridgereg_t b_wid_resp_upper; /* 0x000064 */ - bridgereg_t _pad_000060; - - union { - picreg_t _p_wid_resp_lower; /* 0x000068 */ - struct { - bridgereg_t _b_wid_resp_lower; /* 0x00006C */ - bridgereg_t _b_pad_000068; - } _b; - } u_wid_resp_lower; - #define p_wid_resp_64 u_wid_resp_lower._p_wid_resp_lower - #define b_wid_resp_lower u_wid_resp_lower._b._b_wid_resp_lower - - bridgereg_t b_wid_tst_pin_ctrl; /* 0x000074 */ - bridgereg_t _pad_000070; - - union { - picreg_t _p_addr_lkerr; /* 0x000078 */ - struct { - bridgereg_t _b_pad_00007C; - bridgereg_t _b_pad_000078; - } _b; - } u_addr_lkerr; - #define p_addr_lkerr_64 u_addr_lkerr._p_addr_lkerr - - /* 0x000080-0x00008F -- PMU */ - bridgereg_t b_dir_map; /* 0x000084 */ - bridgereg_t _pad_000080; - - bridgereg_t _pad_00008C; - bridgereg_t _pad_000088; - - /* 0x000090-0x00009F -- SSRAM */ - bridgereg_t b_ram_perr_or_map_fault;/* 0x000094 */ - bridgereg_t _pad_000090; - #define b_ram_perr b_ram_perr_or_map_fault /* Bridge */ - #define b_map_fault b_ram_perr_or_map_fault /* Xbridge & PIC */ - - bridgereg_t _pad_00009C; - bridgereg_t _pad_000098; - - /* 0x0000A0-0x0000AF -- Arbitration */ - bridgereg_t b_arb; /* 0x0000A4 */ - bridgereg_t _pad_0000A0; - - bridgereg_t _pad_0000AC; - bridgereg_t _pad_0000A8; - - /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */ - union { - picreg_t _p_ate_parity_err; /* 0x0000B0 */ - struct { - bridgereg_t _b_nic; /* 0x0000B4 */ - bridgereg_t _b_pad_0000B0; - } _b; - } u_ate_parity_err_or_nic; - #define p_ate_parity_err_64 u_ate_parity_err_or_nic._p_ate_parity_err - #define b_nic u_ate_parity_err_or_nic._b._b_nic - - bridgereg_t _pad_0000BC; - bridgereg_t _pad_0000B8; - - /* 0x0000C0-0x0000FF -- PCI/GIO */ - bridgereg_t b_bus_timeout; /* 0x0000C4 */ - bridgereg_t _pad_0000C0; - #define b_pci_bus_timeout b_bus_timeout - - bridgereg_t b_pci_cfg; /* 0x0000CC */ - bridgereg_t _pad_0000C8; - - bridgereg_t b_pci_err_upper; /* 0x0000D4 */ - bridgereg_t _pad_0000D0; - #define b_gio_err_upper b_pci_err_upper - - union { - picreg_t _p_pci_err_lower; /* 0x0000D8 */ - struct { - bridgereg_t _b_pci_err_lower; /* 0x0000DC */ - bridgereg_t _b_pad_0000D8; - } _b; - } u_pci_err_lower; - #define p_pci_err_64 u_pci_err_lower._p_pci_err_lower - #define b_pci_err_lower u_pci_err_lower._b._b_pci_err_lower - #define b_gio_err_lower b_pci_err_lower - - bridgereg_t _pad_0000E0[8]; - - /* 0x000100-0x0001FF -- Interrupt */ - union { - picreg_t _p_int_status; /* 0x000100 */ - struct { - bridgereg_t _b_int_status; /* 0x000104 */ - bridgereg_t _b_pad_000100; - } _b; - } u_int_status; - #define p_int_status_64 u_int_status._p_int_status - #define b_int_status u_int_status._b._b_int_status - - union { - picreg_t _p_int_enable; /* 0x000108 */ - struct { - bridgereg_t _b_int_enable; /* 0x00010C */ - bridgereg_t _b_pad_000108; - } _b; - } u_int_enable; - #define p_int_enable_64 u_int_enable._p_int_enable - #define b_int_enable u_int_enable._b._b_int_enable - - union { - picreg_t _p_int_rst_stat; /* 0x000110 */ - struct { - bridgereg_t _b_int_rst_stat; /* 0x000114 */ - bridgereg_t _b_pad_000110; - } _b; - } u_int_rst_stat; - #define p_int_rst_stat_64 u_int_rst_stat._p_int_rst_stat - #define b_int_rst_stat u_int_rst_stat._b._b_int_rst_stat - - bridgereg_t b_int_mode; /* 0x00011C */ - bridgereg_t _pad_000118; - - bridgereg_t b_int_device; /* 0x000124 */ - bridgereg_t _pad_000120; - - bridgereg_t b_int_host_err; /* 0x00012C */ - bridgereg_t _pad_000128; - - union { - picreg_t _p_int_addr[8]; /* 0x0001{30,,,68} */ - struct { - bridgereg_t addr; /* 0x0001{34,,,6C} */ - bridgereg_t _b_pad; - } _b[8]; - } u_int_addr; - #define p_int_addr_64 u_int_addr._p_int_addr - #define b_int_addr u_int_addr._b - - union { - picreg_t _p_err_int_view; /* 0x000170 */ - struct { - bridgereg_t _b_err_int_view; /* 0x000174 */ - bridgereg_t _b_pad_000170; - } _b; - } u_err_int_view; - #define p_err_int_view_64 u_err_int_view._p_err_int_view - #define b_err_int_view u_err_int_view._b._b_err_int_view - - union { - picreg_t _p_mult_int; /* 0x000178 */ - struct { - bridgereg_t _b_mult_int; /* 0x00017C */ - bridgereg_t _b_pad_000178; - } _b; - } u_mult_int; - #define p_mult_int_64 u_mult_int._p_mult_int - #define b_mult_int u_mult_int._b._b_mult_int - - struct { - bridgereg_t intr; /* 0x0001{84,,,BC} */ - bridgereg_t __pad; - } b_force_always[8]; - - struct { - bridgereg_t intr; /* 0x0001{C4,,,FC} */ - bridgereg_t __pad; - } b_force_pin[8]; - - /* 0x000200-0x0003FF -- Device */ - struct { - bridgereg_t reg; /* 0x0002{04,,,3C} */ - bridgereg_t __pad; - } b_device[8]; - - struct { - bridgereg_t reg; /* 0x0002{44,,,7C} */ - bridgereg_t __pad; - } b_wr_req_buf[8]; - - struct { - bridgereg_t reg; /* 0x0002{84,,,8C} */ - bridgereg_t __pad; - } b_rrb_map[2]; - #define b_even_resp b_rrb_map[0].reg /* 0x000284 */ - #define b_odd_resp b_rrb_map[1].reg /* 0x00028C */ - - bridgereg_t b_resp_status; /* 0x000294 */ - bridgereg_t _pad_000290; - - bridgereg_t b_resp_clear; /* 0x00029C */ - bridgereg_t _pad_000298; - - bridgereg_t _pad_0002A0[24]; - - /* Xbridge/PIC only */ - union { - struct { - picreg_t lower; /* 0x0003{08,,,F8} */ - picreg_t upper; /* 0x0003{00,,,F0} */ - } _p[16]; - struct { - bridgereg_t upper; /* 0x0003{04,,,F4} */ - bridgereg_t _b_pad1; - bridgereg_t lower; /* 0x0003{0C,,,FC} */ - bridgereg_t _b_pad2; - } _b[16]; - } u_buf_addr_match; - #define p_buf_addr_match_64 u_buf_addr_match._p - #define b_buf_addr_match u_buf_addr_match._b - - /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */ - struct { - bridgereg_t flush_w_touch; /* 0x000{404,,,5C4} */ - bridgereg_t __pad1; - bridgereg_t flush_wo_touch; /* 0x000{40C,,,5CC} */ - bridgereg_t __pad2; - bridgereg_t inflight; /* 0x000{414,,,5D4} */ - bridgereg_t __pad3; - bridgereg_t prefetch; /* 0x000{41C,,,5DC} */ - bridgereg_t __pad4; - bridgereg_t total_pci_retry; /* 0x000{424,,,5E4} */ - bridgereg_t __pad5; - bridgereg_t max_pci_retry; /* 0x000{42C,,,5EC} */ - bridgereg_t __pad6; - bridgereg_t max_latency; /* 0x000{434,,,5F4} */ - bridgereg_t __pad7; - bridgereg_t clear_all; /* 0x000{43C,,,5FC} */ - bridgereg_t __pad8; - } b_buf_count[8]; - - /* - * "PCI/X registers that are specific to PIC". See pic.h. - */ - - /* 0x000600-0x0009FF -- PCI/X registers */ - picreg_t p_pcix_bus_err_addr_64; /* 0x000600 */ - picreg_t p_pcix_bus_err_attr_64; /* 0x000608 */ - picreg_t p_pcix_bus_err_data_64; /* 0x000610 */ - picreg_t p_pcix_pio_split_addr_64; /* 0x000618 */ - picreg_t p_pcix_pio_split_attr_64; /* 0x000620 */ - picreg_t p_pcix_dma_req_err_attr_64; /* 0x000628 */ - picreg_t p_pcix_dma_req_err_addr_64; /* 0x000630 */ - picreg_t p_pcix_timeout_64; /* 0x000638 */ - - picreg_t _pad_000600[120]; - - /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */ - struct { - picreg_t p_buf_attr; /* 0X000{A08,,,AF8} */ - picreg_t p_buf_addr; /* 0x000{A00,,,AF0} */ - } p_pcix_read_buf_64[16]; - - struct { - picreg_t p_buf_attr; /* 0x000{B08,,,BE8} */ - picreg_t p_buf_addr; /* 0x000{B00,,,BE0} */ - picreg_t __pad1; /* 0x000{B18,,,BF8} */ - picreg_t p_buf_valid; /* 0x000{B10,,,BF0} */ - } p_pcix_write_buf_64[8]; - - /* - * end "PCI/X registers that are specific to PIC" - */ - - char _pad_000c00[0x010000 - 0x000c00]; - - /* 0x010000-0x011fff -- Internal Address Translation Entry RAM */ - /* - * Xbridge and PIC have 1024 internal ATE's and the Bridge has 128. - * Make enough room for the Xbridge/PIC ATE's and depend on runtime - * checks to limit access to bridge ATE's. - * - * In [X]bridge the internal ATE Ram is writen as double words only, - * but due to internal design issues it is read back as single words. - * i.e: - * b_int_ate_ram[index].hi.rd << 32 | xb_int_ate_ram_lo[index].rd - */ - union { - bridge_ate_t wr; /* write-only */ /* 0x01{0000,,,1FF8} */ - struct { - bridgereg_t rd; /* read-only */ /* 0x01{0004,,,1FFC} */ - bridgereg_t _p_pad; - } hi; - } b_int_ate_ram[XBRIDGE_INTERNAL_ATES]; - #define b_int_ate_ram_lo(idx) b_int_ate_ram[idx+512].hi.rd - - /* 0x012000-0x013fff -- Internal Address Translation Entry RAM LOW */ - struct { - bridgereg_t rd; /* read-only */ /* 0x01{2004,,,3FFC} */ - bridgereg_t _p_pad; - } xb_int_ate_ram_lo[XBRIDGE_INTERNAL_ATES]; - - char _pad_014000[0x18000 - 0x014000]; - - /* 0x18000-0x197F8 -- PIC Write Request Ram */ - /* 0x18000 - 0x187F8 */ - picreg_t p_wr_req_lower[PIC_WR_REQ_BUFSIZE]; - /* 0x18800 - 0x18FF8 */ - picreg_t p_wr_req_upper[PIC_WR_REQ_BUFSIZE]; - /* 0x19000 - 0x197F8 */ - picreg_t p_wr_req_parity[PIC_WR_REQ_BUFSIZE]; - - char _pad_019800[0x20000 - 0x019800]; - - /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */ - union { /* make all access sizes available. */ - unsigned char c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */ - uint16_t s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */ - uint32_t l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */ - uint64_t d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */ - union { - unsigned char c[0x100 / 1]; - uint16_t s[0x100 / 2]; - uint32_t l[0x100 / 4]; - uint64_t d[0x100 / 8]; - } f[8]; - } b_type0_cfg_dev[8]; /* 0x02{0000,,,7FFF} */ - - /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */ - union { /* make all access sizes available. */ - unsigned char c[0x1000 / 1]; - uint16_t s[0x1000 / 2]; - uint32_t l[0x1000 / 4]; - uint64_t d[0x1000 / 8]; - union { - unsigned char c[0x100 / 1]; - uint16_t s[0x100 / 2]; - uint32_t l[0x100 / 4]; - uint64_t d[0x100 / 8]; - } f[8]; - } b_type1_cfg; /* 0x028000-0x029000 */ - - char _pad_029000[0x007000]; /* 0x029000-0x030000 */ - - /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */ - union { - unsigned char c[8 / 1]; - uint16_t s[8 / 2]; - uint32_t l[8 / 4]; - uint64_t d[8 / 8]; - } b_pci_iack; /* 0x030000-0x030007 */ - - unsigned char _pad_030007[0x04fff8]; /* 0x030008-0x07FFFF */ - - /* 0x080000-0x0FFFFF -- External Address Translation Entry RAM */ - bridge_ate_t b_ext_ate_ram[0x10000]; - - /* 0x100000-0x1FFFFF -- Reserved */ - char _pad_100000[0x200000-0x100000]; - - /* 0x200000-0xBFFFFF -- PCI/GIO Device Spaces */ - union { /* make all access sizes available. */ - unsigned char c[0x100000 / 1]; - uint16_t s[0x100000 / 2]; - uint32_t l[0x100000 / 4]; - uint64_t d[0x100000 / 8]; - } b_devio_raw[10]; - - /* b_devio macro is a bit strange; it reflects the - * fact that the Bridge ASIC provides 2M for the - * first two DevIO windows and 1M for the other six. - */ - #define b_devio(n) b_devio_raw[((n)<2)?(n*2):(n+2)] - - /* 0xC00000-0xFFFFFF -- External Flash Proms 1,0 */ - union { /* make all access sizes available. */ - unsigned char c[0x400000 / 1]; /* read-only */ - uint16_t s[0x400000 / 2]; /* read-write */ - uint32_t l[0x400000 / 4]; /* read-only */ - uint64_t d[0x400000 / 8]; /* read-only */ - } b_external_flash; -} bridge_t; - -#define berr_field berr_un.berr_st -#endif /* __ASSEMBLY__ */ - -/* - * The values of these macros can and should be crosschecked - * regularly against the offsets of the like-named fields - * within the "bridge_t" structure above. - */ - -/* Byte offset macros for Bridge internal registers */ - -#define BRIDGE_WID_ID WIDGET_ID -#define BRIDGE_WID_STAT WIDGET_STATUS -#define BRIDGE_WID_ERR_UPPER WIDGET_ERR_UPPER_ADDR -#define BRIDGE_WID_ERR_LOWER WIDGET_ERR_LOWER_ADDR -#define BRIDGE_WID_CONTROL WIDGET_CONTROL -#define BRIDGE_WID_REQ_TIMEOUT WIDGET_REQ_TIMEOUT -#define BRIDGE_WID_INT_UPPER WIDGET_INTDEST_UPPER_ADDR -#define BRIDGE_WID_INT_LOWER WIDGET_INTDEST_LOWER_ADDR -#define BRIDGE_WID_ERR_CMDWORD WIDGET_ERR_CMD_WORD -#define BRIDGE_WID_LLP WIDGET_LLP_CFG -#define BRIDGE_WID_TFLUSH WIDGET_TFLUSH - -#define BRIDGE_WID_AUX_ERR 0x00005C /* Aux Error Command Word */ -#define BRIDGE_WID_RESP_UPPER 0x000064 /* Response Buf Upper Addr */ -#define BRIDGE_WID_RESP_LOWER 0x00006C /* Response Buf Lower Addr */ -#define BRIDGE_WID_TST_PIN_CTRL 0x000074 /* Test pin control */ - -#define BRIDGE_DIR_MAP 0x000084 /* Direct Map reg */ - -/* Bridge has SSRAM Parity Error and Xbridge has Map Fault here */ -#define BRIDGE_RAM_PERR 0x000094 /* SSRAM Parity Error */ -#define BRIDGE_MAP_FAULT 0x000094 /* Map Fault */ - -#define BRIDGE_ARB 0x0000A4 /* Arbitration Priority reg */ - -#define BRIDGE_NIC 0x0000B4 /* Number In A Can */ - -#define BRIDGE_BUS_TIMEOUT 0x0000C4 /* Bus Timeout Register */ -#define BRIDGE_PCI_BUS_TIMEOUT BRIDGE_BUS_TIMEOUT -#define BRIDGE_PCI_CFG 0x0000CC /* PCI Type 1 Config reg */ -#define BRIDGE_PCI_ERR_UPPER 0x0000D4 /* PCI error Upper Addr */ -#define BRIDGE_PCI_ERR_LOWER 0x0000DC /* PCI error Lower Addr */ - -#define BRIDGE_INT_STATUS 0x000104 /* Interrupt Status */ -#define BRIDGE_INT_ENABLE 0x00010C /* Interrupt Enables */ -#define BRIDGE_INT_RST_STAT 0x000114 /* Reset Intr Status */ -#define BRIDGE_INT_MODE 0x00011C /* Interrupt Mode */ -#define BRIDGE_INT_DEVICE 0x000124 /* Interrupt Device */ -#define BRIDGE_INT_HOST_ERR 0x00012C /* Host Error Field */ - -#define BRIDGE_INT_ADDR0 0x000134 /* Host Address Reg */ -#define BRIDGE_INT_ADDR_OFF 0x000008 /* Host Addr offset (1..7) */ -#define BRIDGE_INT_ADDR(x) (BRIDGE_INT_ADDR0+(x)*BRIDGE_INT_ADDR_OFF) - -#define BRIDGE_INT_VIEW 0x000174 /* Interrupt view */ -#define BRIDGE_MULTIPLE_INT 0x00017c /* Multiple interrupt occurred */ - -#define BRIDGE_FORCE_ALWAYS0 0x000184 /* Force an interrupt (always)*/ -#define BRIDGE_FORCE_ALWAYS_OFF 0x000008 /* Force Always offset */ -#define BRIDGE_FORCE_ALWAYS(x) (BRIDGE_FORCE_ALWAYS0+(x)*BRIDGE_FORCE_ALWAYS_OFF) - -#define BRIDGE_FORCE_PIN0 0x0001c4 /* Force an interrupt */ -#define BRIDGE_FORCE_PIN_OFF 0x000008 /* Force Pin offset */ -#define BRIDGE_FORCE_PIN(x) (BRIDGE_FORCE_PIN0+(x)*BRIDGE_FORCE_PIN_OFF) - -#define BRIDGE_DEVICE0 0x000204 /* Device 0 */ -#define BRIDGE_DEVICE_OFF 0x000008 /* Device offset (1..7) */ -#define BRIDGE_DEVICE(x) (BRIDGE_DEVICE0+(x)*BRIDGE_DEVICE_OFF) - -#define BRIDGE_WR_REQ_BUF0 0x000244 /* Write Request Buffer 0 */ -#define BRIDGE_WR_REQ_BUF_OFF 0x000008 /* Buffer Offset (1..7) */ -#define BRIDGE_WR_REQ_BUF(x) (BRIDGE_WR_REQ_BUF0+(x)*BRIDGE_WR_REQ_BUF_OFF) - -#define BRIDGE_EVEN_RESP 0x000284 /* Even Device Response Buf */ -#define BRIDGE_ODD_RESP 0x00028C /* Odd Device Response Buf */ - -#define BRIDGE_RESP_STATUS 0x000294 /* Read Response Status reg */ -#define BRIDGE_RESP_CLEAR 0x00029C /* Read Response Clear reg */ - -#define BRIDGE_BUF_ADDR_UPPER0 0x000304 -#define BRIDGE_BUF_ADDR_UPPER_OFF 0x000010 /* PCI Buffer Upper Offset */ -#define BRIDGE_BUF_ADDR_UPPER(x) (BRIDGE_BUF_ADDR_UPPER0+(x)*BRIDGE_BUF_ADDR_UPPER_OFF) - -#define BRIDGE_BUF_ADDR_LOWER0 0x00030c -#define BRIDGE_BUF_ADDR_LOWER_OFF 0x000010 /* PCI Buffer Upper Offset */ -#define BRIDGE_BUF_ADDR_LOWER(x) (BRIDGE_BUF_ADDR_LOWER0+(x)*BRIDGE_BUF_ADDR_LOWER_OFF) - -/* - * Performance Monitor Registers. - * - * The Performance registers are those registers which are associated with - * monitoring the performance of PCI generated reads to the host environ - * ment. Because of the size of the register file only the even registers - * were instrumented. - */ - -#define BRIDGE_BUF_OFF 0x40 -#define BRIDGE_BUF_NEXT(base, off) (base+((off)*BRIDGE_BUF_OFF)) - -/* - * Buffer (x) Flush Count with Data Touch Register. - * - * This counter is incremented each time the corresponding response buffer - * is flushed after at least a single data element in the buffer is used. - * A word write to this address clears the count. - */ - -#define BRIDGE_BUF_0_FLUSH_TOUCH 0x000404 -#define BRIDGE_BUF_2_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 1) -#define BRIDGE_BUF_4_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 2) -#define BRIDGE_BUF_6_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 3) -#define BRIDGE_BUF_8_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 4) -#define BRIDGE_BUF_10_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 5) -#define BRIDGE_BUF_12_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 6) -#define BRIDGE_BUF_14_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 7) - -/* - * Buffer (x) Flush Count w/o Data Touch Register - * - * This counter is incremented each time the corresponding response buffer - * is flushed without any data element in the buffer being used. A word - * write to this address clears the count. - */ - - -#define BRIDGE_BUF_0_FLUSH_NOTOUCH 0x00040c -#define BRIDGE_BUF_2_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 1) -#define BRIDGE_BUF_4_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 2) -#define BRIDGE_BUF_6_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 3) -#define BRIDGE_BUF_8_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 4) -#define BRIDGE_BUF_10_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 5) -#define BRIDGE_BUF_12_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 6) -#define BRIDGE_BUF_14_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 7) - -/* - * Buffer (x) Request in Flight Count Register - * - * This counter is incremented on each bus clock while the request is in - * flight. A word write to this address clears the count. - */ - -#define BRIDGE_BUF_0_INFLIGHT 0x000414 -#define BRIDGE_BUF_2_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 1) -#define BRIDGE_BUF_4_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 2) -#define BRIDGE_BUF_6_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 3) -#define BRIDGE_BUF_8_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 4) -#define BRIDGE_BUF_10_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 5) -#define BRIDGE_BUF_12_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 6) -#define BRIDGE_BUF_14_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 7) - -/* - * Buffer (x) Prefetch Request Count Register - * - * This counter is incremented each time the request using this buffer was - * generated from the prefetcher. A word write to this address clears the - * count. - */ - -#define BRIDGE_BUF_0_PREFETCH 0x00041C -#define BRIDGE_BUF_2_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 1) -#define BRIDGE_BUF_4_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 2) -#define BRIDGE_BUF_6_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 3) -#define BRIDGE_BUF_8_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 4) -#define BRIDGE_BUF_10_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 5) -#define BRIDGE_BUF_12_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 6) -#define BRIDGE_BUF_14_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 7) - -/* - * Buffer (x) Total PCI Retry Count Register - * - * This counter is incremented each time a PCI bus retry occurs and the ad - * dress matches the tag for the selected buffer. The buffer must also has - * this request in-flight. A word write to this address clears the count. - */ - -#define BRIDGE_BUF_0_PCI_RETRY 0x000424 -#define BRIDGE_BUF_2_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 1) -#define BRIDGE_BUF_4_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 2) -#define BRIDGE_BUF_6_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 3) -#define BRIDGE_BUF_8_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 4) -#define BRIDGE_BUF_10_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 5) -#define BRIDGE_BUF_12_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 6) -#define BRIDGE_BUF_14_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 7) - -/* - * Buffer (x) Max PCI Retry Count Register - * - * This counter is contains the maximum retry count for a single request - * which was in-flight for this buffer. A word write to this address - * clears the count. - */ - -#define BRIDGE_BUF_0_MAX_PCI_RETRY 0x00042C -#define BRIDGE_BUF_2_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 1) -#define BRIDGE_BUF_4_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 2) -#define BRIDGE_BUF_6_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 3) -#define BRIDGE_BUF_8_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 4) -#define BRIDGE_BUF_10_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 5) -#define BRIDGE_BUF_12_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 6) -#define BRIDGE_BUF_14_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 7) - -/* - * Buffer (x) Max Latency Count Register - * - * This counter is contains the maximum count (in bus clocks) for a single - * request which was in-flight for this buffer. A word write to this - * address clears the count. - */ - -#define BRIDGE_BUF_0_MAX_LATENCY 0x000434 -#define BRIDGE_BUF_2_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 1) -#define BRIDGE_BUF_4_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 2) -#define BRIDGE_BUF_6_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 3) -#define BRIDGE_BUF_8_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 4) -#define BRIDGE_BUF_10_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 5) -#define BRIDGE_BUF_12_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 6) -#define BRIDGE_BUF_14_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 7) - -/* - * Buffer (x) Clear All Register - * - * Any access to this register clears all the count values for the (x) - * registers. - */ - -#define BRIDGE_BUF_0_CLEAR_ALL 0x00043C -#define BRIDGE_BUF_2_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 1) -#define BRIDGE_BUF_4_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 2) -#define BRIDGE_BUF_6_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 3) -#define BRIDGE_BUF_8_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 4) -#define BRIDGE_BUF_10_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 5) -#define BRIDGE_BUF_12_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 6) -#define BRIDGE_BUF_14_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 7) - -/* end of Performance Monitor Registers */ - -/* Byte offset macros for Bridge I/O space. - * - * NOTE: Where applicable please use the PCIBR_xxx or PCIBRIDGE_xxx - * macros (below) as they will handle [X]Bridge and PIC. For example, - * PCIBRIDGE_TYPE0_CFG_DEV0() vs BRIDGE_TYPE0_CFG_DEV0 - */ - -#define BRIDGE_ATE_RAM 0x00010000 /* Internal Addr Xlat Ram */ - -#define BRIDGE_TYPE0_CFG_DEV0 0x00020000 /* Type 0 Cfg, Device 0 */ -#define BRIDGE_TYPE0_CFG_SLOT_OFF 0x00001000 /* Type 0 Cfg Slot Offset (1..7) */ -#define BRIDGE_TYPE0_CFG_FUNC_OFF 0x00000100 /* Type 0 Cfg Func Offset (1..7) */ -#define BRIDGE_TYPE0_CFG_DEV(s) (BRIDGE_TYPE0_CFG_DEV0+\ - (s)*BRIDGE_TYPE0_CFG_SLOT_OFF) -#define BRIDGE_TYPE0_CFG_DEVF(s,f) (BRIDGE_TYPE0_CFG_DEV0+\ - (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\ - (f)*BRIDGE_TYPE0_CFG_FUNC_OFF) - -#define BRIDGE_TYPE1_CFG 0x00028000 /* Type 1 Cfg space */ - -#define BRIDGE_PCI_IACK 0x00030000 /* PCI Interrupt Ack */ -#define BRIDGE_EXT_SSRAM 0x00080000 /* Extern SSRAM (ATE) */ - -/* Byte offset macros for Bridge device IO spaces */ - -#define BRIDGE_DEV_CNT 8 /* Up to 8 devices per bridge */ -#define BRIDGE_DEVIO0 0x00200000 /* Device IO 0 Addr */ -#define BRIDGE_DEVIO1 0x00400000 /* Device IO 1 Addr */ -#define BRIDGE_DEVIO2 0x00600000 /* Device IO 2 Addr */ -#define BRIDGE_DEVIO_OFF 0x00100000 /* Device IO Offset (3..7) */ - -#define BRIDGE_DEVIO_2MB 0x00200000 /* Device IO Offset (0..1) */ -#define BRIDGE_DEVIO_1MB 0x00100000 /* Device IO Offset (2..7) */ - -#ifndef __ASSEMBLY__ - -#define BRIDGE_DEVIO(x) ((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB) - -/* - * The device space macros for PIC are more complicated because the PIC has - * two PCI/X bridges under the same widget. For PIC bus 0, the addresses are - * basically the same as for the [X]Bridge. For PIC bus 1, the addresses are - * offset by 0x800000. Here are two sets of macros. They are - * "PCIBRIDGE_xxx" that return the address based on the supplied bus number - * and also equivalent "PCIBR_xxx" macros that may be used with a - * pcibr_soft_s structure. Both should work with all bridges. - */ -#define PIC_BUS1_OFFSET 0x800000 - -#define PCIBRIDGE_TYPE0_CFG_DEV0(busnum) \ - ((busnum) ? BRIDGE_TYPE0_CFG_DEV0 + PIC_BUS1_OFFSET : \ - BRIDGE_TYPE0_CFG_DEV0) -#define PCIBRIDGE_TYPE1_CFG(busnum) \ - ((busnum) ? BRIDGE_TYPE1_CFG + PIC_BUS1_OFFSET : BRIDGE_TYPE1_CFG) -#define PCIBRIDGE_TYPE0_CFG_DEV(busnum, s) \ - (PCIBRIDGE_TYPE0_CFG_DEV0(busnum)+\ - (s)*BRIDGE_TYPE0_CFG_SLOT_OFF) -#define PCIBRIDGE_TYPE0_CFG_DEVF(busnum, s, f) \ - (PCIBRIDGE_TYPE0_CFG_DEV0(busnum)+\ - (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\ - (f)*BRIDGE_TYPE0_CFG_FUNC_OFF) -#define PCIBRIDGE_DEVIO0(busnum) ((busnum) ? \ - (BRIDGE_DEVIO0 + PIC_BUS1_OFFSET) : BRIDGE_DEVIO0) -#define PCIBRIDGE_DEVIO1(busnum) ((busnum) ? \ - (BRIDGE_DEVIO1 + PIC_BUS1_OFFSET) : BRIDGE_DEVIO1) -#define PCIBRIDGE_DEVIO2(busnum) ((busnum) ? \ - (BRIDGE_DEVIO2 + PIC_BUS1_OFFSET) : BRIDGE_DEVIO2) -#define PCIBRIDGE_DEVIO(busnum, x) \ - ((x)<=1 ? PCIBRIDGE_DEVIO0(busnum)+(x)*BRIDGE_DEVIO_2MB : \ - PCIBRIDGE_DEVIO2(busnum)+((x)-2)*BRIDGE_DEVIO_1MB) - -#define PCIBR_BRIDGE_DEVIO0(ps) PCIBRIDGE_DEVIO0((ps)->bs_busnum) -#define PCIBR_BRIDGE_DEVIO1(ps) PCIBRIDGE_DEVIO1((ps)->bs_busnum) -#define PCIBR_BRIDGE_DEVIO2(ps) PCIBRIDGE_DEVIO2((ps)->bs_busnum) -#define PCIBR_BRIDGE_DEVIO(ps, s) PCIBRIDGE_DEVIO((ps)->bs_busnum, s) - -#define PCIBR_TYPE1_CFG(ps) PCIBRIDGE_TYPE1_CFG((ps)->bs_busnum) -#define PCIBR_BUS_TYPE0_CFG_DEV0(ps) PCIBR_TYPE0_CFG_DEV(ps, 0) -#define PCIBR_TYPE0_CFG_DEV(ps, s) PCIBRIDGE_TYPE0_CFG_DEV((ps)->bs_busnum, s+1) -#define PCIBR_BUS_TYPE0_CFG_DEVF(ps,s,f) PCIBRIDGE_TYPE0_CFG_DEVF((ps)->bs_busnum,(s+1),f) - -/* NOTE: 's' is the internal device number, not the external slot number */ -#define PCIBR_BUS_TYPE0_CFG_DEV(ps, s) \ - PCIBRIDGE_TYPE0_CFG_DEV((ps)->bs_busnum, s+1) - -#endif /* LANGUAGE_C */ - -#define BRIDGE_EXTERNAL_FLASH 0x00C00000 /* External Flash PROMS */ - -/* ======================================================================== - * Bridge register bit field definitions - */ - -/* Widget part number of bridge */ -#define BRIDGE_WIDGET_PART_NUM 0xc002 -#define XBRIDGE_WIDGET_PART_NUM 0xd002 - -/* Manufacturer of bridge */ -#define BRIDGE_WIDGET_MFGR_NUM 0x036 -#define XBRIDGE_WIDGET_MFGR_NUM 0x024 - -/* Revision numbers for known [X]Bridge revisions */ -#define BRIDGE_REV_A 0x1 -#define BRIDGE_REV_B 0x2 -#define BRIDGE_REV_C 0x3 -#define BRIDGE_REV_D 0x4 -#define XBRIDGE_REV_A 0x1 -#define XBRIDGE_REV_B 0x2 - -/* macros to determine bridge type. 'wid' == widget identification */ -#define IS_PIC_BUS0(wid) (XWIDGET_PART_NUM(wid) == PIC_WIDGET_PART_NUM_BUS0 && \ - XWIDGET_MFG_NUM(wid) == PIC_WIDGET_MFGR_NUM) -#define IS_PIC_BUS1(wid) (XWIDGET_PART_NUM(wid) == PIC_WIDGET_PART_NUM_BUS1 && \ - XWIDGET_MFG_NUM(wid) == PIC_WIDGET_MFGR_NUM) -#define IS_PIC_BRIDGE(wid) (IS_PIC_BUS0(wid) || IS_PIC_BUS1(wid)) - -/* Part + Rev numbers allows distinction and acscending sequence */ -#define BRIDGE_PART_REV_A (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_A) -#define BRIDGE_PART_REV_B (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_B) -#define BRIDGE_PART_REV_C (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_C) -#define BRIDGE_PART_REV_D (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_D) -#define XBRIDGE_PART_REV_A (XBRIDGE_WIDGET_PART_NUM << 4 | XBRIDGE_REV_A) -#define XBRIDGE_PART_REV_B (XBRIDGE_WIDGET_PART_NUM << 4 | XBRIDGE_REV_B) - -/* Bridge widget status register bits definition */ -#define PIC_STAT_PCIX_SPEED (0x3ull << 34) -#define PIC_STAT_PCIX_ACTIVE (0x1ull << 33) -#define BRIDGE_STAT_LLP_REC_CNT (0xFFu << 24) -#define BRIDGE_STAT_LLP_TX_CNT (0xFF << 16) -#define BRIDGE_STAT_FLASH_SELECT (0x1 << 6) -#define BRIDGE_STAT_PCI_GIO_N (0x1 << 5) -#define BRIDGE_STAT_PENDING (0x1F << 0) - -/* Bridge widget control register bits definition */ -#define PIC_CTRL_NO_SNOOP (0x1ull << 62) -#define PIC_CTRL_RELAX_ORDER (0x1ull << 61) -#define PIC_CTRL_BUS_NUM(x) ((unsigned long long)(x) << 48) -#define PIC_CTRL_BUS_NUM_MASK (PIC_CTRL_BUS_NUM(0xff)) -#define PIC_CTRL_DEV_NUM(x) ((unsigned long long)(x) << 43) -#define PIC_CTRL_DEV_NUM_MASK (PIC_CTRL_DEV_NUM(0x1f)) -#define PIC_CTRL_FUN_NUM(x) ((unsigned long long)(x) << 40) -#define PIC_CTRL_FUN_NUM_MASK (PIC_CTRL_FUN_NUM(0x7)) -#define PIC_CTRL_PAR_EN_REQ (0x1ull << 29) -#define PIC_CTRL_PAR_EN_RESP (0x1ull << 30) -#define PIC_CTRL_PAR_EN_ATE (0x1ull << 31) -#define BRIDGE_CTRL_FLASH_WR_EN (0x1ul << 31) /* bridge only */ -#define BRIDGE_CTRL_EN_CLK50 (0x1 << 30) -#define BRIDGE_CTRL_EN_CLK40 (0x1 << 29) -#define BRIDGE_CTRL_EN_CLK33 (0x1 << 28) -#define BRIDGE_CTRL_RST(n) ((n) << 24) -#define BRIDGE_CTRL_RST_MASK (BRIDGE_CTRL_RST(0xF)) -#define BRIDGE_CTRL_RST_PIN(x) (BRIDGE_CTRL_RST(0x1 << (x))) -#define BRIDGE_CTRL_IO_SWAP (0x1 << 23) -#define BRIDGE_CTRL_MEM_SWAP (0x1 << 22) -#define BRIDGE_CTRL_PAGE_SIZE (0x1 << 21) -#define BRIDGE_CTRL_SS_PAR_BAD (0x1 << 20) -#define BRIDGE_CTRL_SS_PAR_EN (0x1 << 19) -#define BRIDGE_CTRL_SSRAM_SIZE(n) ((n) << 17) -#define BRIDGE_CTRL_SSRAM_SIZE_MASK (BRIDGE_CTRL_SSRAM_SIZE(0x3)) -#define BRIDGE_CTRL_SSRAM_512K (BRIDGE_CTRL_SSRAM_SIZE(0x3)) -#define BRIDGE_CTRL_SSRAM_128K (BRIDGE_CTRL_SSRAM_SIZE(0x2)) -#define BRIDGE_CTRL_SSRAM_64K (BRIDGE_CTRL_SSRAM_SIZE(0x1)) -#define BRIDGE_CTRL_SSRAM_1K (BRIDGE_CTRL_SSRAM_SIZE(0x0)) -#define BRIDGE_CTRL_F_BAD_PKT (0x1 << 16) -#define BRIDGE_CTRL_LLP_XBAR_CRD(n) ((n) << 12) -#define BRIDGE_CTRL_LLP_XBAR_CRD_MASK (BRIDGE_CTRL_LLP_XBAR_CRD(0xf)) -#define BRIDGE_CTRL_CLR_RLLP_CNT (0x1 << 11) -#define BRIDGE_CTRL_CLR_TLLP_CNT (0x1 << 10) -#define BRIDGE_CTRL_SYS_END (0x1 << 9) -#define BRIDGE_CTRL_PCI_SPEED (0x3 << 4) - -#define BRIDGE_CTRL_BUS_SPEED(n) ((n) << 4) -#define BRIDGE_CTRL_BUS_SPEED_MASK (BRIDGE_CTRL_BUS_SPEED(0x3)) -#define BRIDGE_CTRL_BUS_SPEED_33 0x00 -#define BRIDGE_CTRL_BUS_SPEED_66 0x10 -#define BRIDGE_CTRL_MAX_TRANS(n) ((n) << 4) -#define BRIDGE_CTRL_MAX_TRANS_MASK (BRIDGE_CTRL_MAX_TRANS(0x1f)) -#define BRIDGE_CTRL_WIDGET_ID(n) ((n) << 0) -#define BRIDGE_CTRL_WIDGET_ID_MASK (BRIDGE_CTRL_WIDGET_ID(0xf)) - -/* Bridge Response buffer Error Upper Register bit fields definition */ -#define BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT (20) -#define BRIDGE_RESP_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT) -#define BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT (16) -#define BRIDGE_RESP_ERRUPPR_BUFNUM_MASK (0xF << BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT) -#define BRIDGE_RESP_ERRRUPPR_BUFMASK (0xFFFF) - -#define BRIDGE_RESP_ERRUPPR_BUFNUM(x) \ - (((x) & BRIDGE_RESP_ERRUPPR_BUFNUM_MASK) >> \ - BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT) - -#define BRIDGE_RESP_ERRUPPR_DEVICE(x) \ - (((x) & BRIDGE_RESP_ERRUPPR_DEVNUM_MASK) >> \ - BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT) - -/* Bridge direct mapping register bits definition */ -#define BRIDGE_DIRMAP_W_ID_SHFT 20 -#define BRIDGE_DIRMAP_W_ID (0xf << BRIDGE_DIRMAP_W_ID_SHFT) -#define BRIDGE_DIRMAP_RMF_64 (0x1 << 18) -#define BRIDGE_DIRMAP_ADD512 (0x1 << 17) -#define BRIDGE_DIRMAP_OFF (0x1ffff << 0) -#define BRIDGE_DIRMAP_OFF_ADDRSHFT (31) /* lsbit of DIRMAP_OFF is xtalk address bit 31 */ - -/* Bridge Arbitration register bits definition */ -#define BRIDGE_ARB_REQ_WAIT_TICK(x) ((x) << 16) -#define BRIDGE_ARB_REQ_WAIT_TICK_MASK BRIDGE_ARB_REQ_WAIT_TICK(0x3) -#define BRIDGE_ARB_REQ_WAIT_EN(x) ((x) << 8) -#define BRIDGE_ARB_REQ_WAIT_EN_MASK BRIDGE_ARB_REQ_WAIT_EN(0xff) -#define BRIDGE_ARB_FREEZE_GNT (1 << 6) -#define BRIDGE_ARB_HPRI_RING_B2 (1 << 5) -#define BRIDGE_ARB_HPRI_RING_B1 (1 << 4) -#define BRIDGE_ARB_HPRI_RING_B0 (1 << 3) -#define BRIDGE_ARB_LPRI_RING_B2 (1 << 2) -#define BRIDGE_ARB_LPRI_RING_B1 (1 << 1) -#define BRIDGE_ARB_LPRI_RING_B0 (1 << 0) - -/* Bridge Bus time-out register bits definition */ -#define BRIDGE_BUS_PCI_RETRY_HLD(x) ((x) << 16) -#define BRIDGE_BUS_PCI_RETRY_HLD_MASK BRIDGE_BUS_PCI_RETRY_HLD(0x1f) -#define BRIDGE_BUS_GIO_TIMEOUT (1 << 12) -#define BRIDGE_BUS_PCI_RETRY_CNT(x) ((x) << 0) -#define BRIDGE_BUS_PCI_RETRY_MASK BRIDGE_BUS_PCI_RETRY_CNT(0x3ff) - -/* Bridge interrupt status register bits definition */ -#define PIC_ISR_PCIX_SPLIT_MSG_PE (0x1ull << 45) -#define PIC_ISR_PCIX_SPLIT_EMSG (0x1ull << 44) -#define PIC_ISR_PCIX_SPLIT_TO (0x1ull << 43) -#define PIC_ISR_PCIX_UNEX_COMP (0x1ull << 42) -#define PIC_ISR_INT_RAM_PERR (0x1ull << 41) -#define PIC_ISR_PCIX_ARB_ERR (0x1ull << 40) -#define PIC_ISR_PCIX_REQ_TOUT (0x1ull << 39) -#define PIC_ISR_PCIX_TABORT (0x1ull << 38) -#define PIC_ISR_PCIX_PERR (0x1ull << 37) -#define PIC_ISR_PCIX_SERR (0x1ull << 36) -#define PIC_ISR_PCIX_MRETRY (0x1ull << 35) -#define PIC_ISR_PCIX_MTOUT (0x1ull << 34) -#define PIC_ISR_PCIX_DA_PARITY (0x1ull << 33) -#define PIC_ISR_PCIX_AD_PARITY (0x1ull << 32) -#define BRIDGE_ISR_MULTI_ERR (0x1u << 31) /* bridge only */ -#define BRIDGE_ISR_PMU_ESIZE_FAULT (0x1 << 30) /* bridge only */ -#define BRIDGE_ISR_PAGE_FAULT (0x1 << 30) /* xbridge only */ -#define BRIDGE_ISR_UNEXP_RESP (0x1 << 29) -#define BRIDGE_ISR_BAD_XRESP_PKT (0x1 << 28) -#define BRIDGE_ISR_BAD_XREQ_PKT (0x1 << 27) -#define BRIDGE_ISR_RESP_XTLK_ERR (0x1 << 26) -#define BRIDGE_ISR_REQ_XTLK_ERR (0x1 << 25) -#define BRIDGE_ISR_INVLD_ADDR (0x1 << 24) -#define BRIDGE_ISR_UNSUPPORTED_XOP (0x1 << 23) -#define BRIDGE_ISR_XREQ_FIFO_OFLOW (0x1 << 22) -#define BRIDGE_ISR_LLP_REC_SNERR (0x1 << 21) -#define BRIDGE_ISR_LLP_REC_CBERR (0x1 << 20) -#define BRIDGE_ISR_LLP_RCTY (0x1 << 19) -#define BRIDGE_ISR_LLP_TX_RETRY (0x1 << 18) -#define BRIDGE_ISR_LLP_TCTY (0x1 << 17) -#define BRIDGE_ISR_SSRAM_PERR (0x1 << 16) -#define BRIDGE_ISR_PCI_ABORT (0x1 << 15) -#define BRIDGE_ISR_PCI_PARITY (0x1 << 14) -#define BRIDGE_ISR_PCI_SERR (0x1 << 13) -#define BRIDGE_ISR_PCI_PERR (0x1 << 12) -#define BRIDGE_ISR_PCI_MST_TIMEOUT (0x1 << 11) -#define BRIDGE_ISR_GIO_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT -#define BRIDGE_ISR_PCI_RETRY_CNT (0x1 << 10) -#define BRIDGE_ISR_XREAD_REQ_TIMEOUT (0x1 << 9) -#define BRIDGE_ISR_GIO_B_ENBL_ERR (0x1 << 8) -#define BRIDGE_ISR_INT_MSK (0xff << 0) -#define BRIDGE_ISR_INT(x) (0x1 << (x)) - -#define BRIDGE_ISR_LINK_ERROR \ - (BRIDGE_ISR_LLP_REC_SNERR|BRIDGE_ISR_LLP_REC_CBERR| \ - BRIDGE_ISR_LLP_RCTY|BRIDGE_ISR_LLP_TX_RETRY| \ - BRIDGE_ISR_LLP_TCTY) - -#define BRIDGE_ISR_PCIBUS_PIOERR \ - (BRIDGE_ISR_PCI_MST_TIMEOUT|BRIDGE_ISR_PCI_ABORT| \ - PIC_ISR_PCIX_MTOUT|PIC_ISR_PCIX_TABORT) - -#define BRIDGE_ISR_PCIBUS_ERROR \ - (BRIDGE_ISR_PCIBUS_PIOERR|BRIDGE_ISR_PCI_PERR| \ - BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_RETRY_CNT| \ - BRIDGE_ISR_PCI_PARITY|PIC_ISR_PCIX_PERR| \ - PIC_ISR_PCIX_SERR|PIC_ISR_PCIX_MRETRY| \ - PIC_ISR_PCIX_AD_PARITY|PIC_ISR_PCIX_DA_PARITY| \ - PIC_ISR_PCIX_REQ_TOUT|PIC_ISR_PCIX_UNEX_COMP| \ - PIC_ISR_PCIX_SPLIT_TO|PIC_ISR_PCIX_SPLIT_EMSG| \ - PIC_ISR_PCIX_SPLIT_MSG_PE) - -#define BRIDGE_ISR_XTALK_ERROR \ - (BRIDGE_ISR_XREAD_REQ_TIMEOUT|BRIDGE_ISR_XREQ_FIFO_OFLOW|\ - BRIDGE_ISR_UNSUPPORTED_XOP|BRIDGE_ISR_INVLD_ADDR| \ - BRIDGE_ISR_REQ_XTLK_ERR|BRIDGE_ISR_RESP_XTLK_ERR| \ - BRIDGE_ISR_BAD_XREQ_PKT|BRIDGE_ISR_BAD_XRESP_PKT| \ - BRIDGE_ISR_UNEXP_RESP) - -#define BRIDGE_ISR_ERRORS \ - (BRIDGE_ISR_LINK_ERROR|BRIDGE_ISR_PCIBUS_ERROR| \ - BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR| \ - BRIDGE_ISR_PMU_ESIZE_FAULT|PIC_ISR_INT_RAM_PERR) - -/* - * List of Errors which are fatal and kill the sytem - */ -#define BRIDGE_ISR_ERROR_FATAL \ - ((BRIDGE_ISR_XTALK_ERROR & ~BRIDGE_ISR_XREAD_REQ_TIMEOUT)|\ - BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_PARITY| \ - PIC_ISR_PCIX_SERR|PIC_ISR_PCIX_AD_PARITY| \ - PIC_ISR_PCIX_DA_PARITY| \ - PIC_ISR_INT_RAM_PERR|PIC_ISR_PCIX_SPLIT_MSG_PE ) - -#define BRIDGE_ISR_ERROR_DUMP \ - (BRIDGE_ISR_PCIBUS_ERROR|BRIDGE_ISR_PMU_ESIZE_FAULT| \ - BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR| \ - PIC_ISR_PCIX_ARB_ERR|PIC_ISR_INT_RAM_PERR) - -/* Bridge interrupt enable register bits definition */ -#define PIC_IMR_PCIX_SPLIT_MSG_PE PIC_ISR_PCIX_SPLIT_MSG_PE -#define PIC_IMR_PCIX_SPLIT_EMSG PIC_ISR_PCIX_SPLIT_EMSG -#define PIC_IMR_PCIX_SPLIT_TO PIC_ISR_PCIX_SPLIT_TO -#define PIC_IMR_PCIX_UNEX_COMP PIC_ISR_PCIX_UNEX_COMP -#define PIC_IMR_INT_RAM_PERR PIC_ISR_INT_RAM_PERR -#define PIC_IMR_PCIX_ARB_ERR PIC_ISR_PCIX_ARB_ERR -#define PIC_IMR_PCIX_REQ_TOUR PIC_ISR_PCIX_REQ_TOUT -#define PIC_IMR_PCIX_TABORT PIC_ISR_PCIX_TABORT -#define PIC_IMR_PCIX_PERR PIC_ISR_PCIX_PERR -#define PIC_IMR_PCIX_SERR PIC_ISR_PCIX_SERR -#define PIC_IMR_PCIX_MRETRY PIC_ISR_PCIX_MRETRY -#define PIC_IMR_PCIX_MTOUT PIC_ISR_PCIX_MTOUT -#define PIC_IMR_PCIX_DA_PARITY PIC_ISR_PCIX_DA_PARITY -#define PIC_IMR_PCIX_AD_PARITY PIC_ISR_PCIX_AD_PARITY -#define BRIDGE_IMR_UNEXP_RESP BRIDGE_ISR_UNEXP_RESP -#define BRIDGE_IMR_PMU_ESIZE_FAULT BRIDGE_ISR_PMU_ESIZE_FAULT -#define BRIDGE_IMR_BAD_XRESP_PKT BRIDGE_ISR_BAD_XRESP_PKT -#define BRIDGE_IMR_BAD_XREQ_PKT BRIDGE_ISR_BAD_XREQ_PKT -#define BRIDGE_IMR_RESP_XTLK_ERR BRIDGE_ISR_RESP_XTLK_ERR -#define BRIDGE_IMR_REQ_XTLK_ERR BRIDGE_ISR_REQ_XTLK_ERR -#define BRIDGE_IMR_INVLD_ADDR BRIDGE_ISR_INVLD_ADDR -#define BRIDGE_IMR_UNSUPPORTED_XOP BRIDGE_ISR_UNSUPPORTED_XOP -#define BRIDGE_IMR_XREQ_FIFO_OFLOW BRIDGE_ISR_XREQ_FIFO_OFLOW -#define BRIDGE_IMR_LLP_REC_SNERR BRIDGE_ISR_LLP_REC_SNERR -#define BRIDGE_IMR_LLP_REC_CBERR BRIDGE_ISR_LLP_REC_CBERR -#define BRIDGE_IMR_LLP_RCTY BRIDGE_ISR_LLP_RCTY -#define BRIDGE_IMR_LLP_TX_RETRY BRIDGE_ISR_LLP_TX_RETRY -#define BRIDGE_IMR_LLP_TCTY BRIDGE_ISR_LLP_TCTY -#define BRIDGE_IMR_SSRAM_PERR BRIDGE_ISR_SSRAM_PERR -#define BRIDGE_IMR_PCI_ABORT BRIDGE_ISR_PCI_ABORT -#define BRIDGE_IMR_PCI_PARITY BRIDGE_ISR_PCI_PARITY -#define BRIDGE_IMR_PCI_SERR BRIDGE_ISR_PCI_SERR -#define BRIDGE_IMR_PCI_PERR BRIDGE_ISR_PCI_PERR -#define BRIDGE_IMR_PCI_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT -#define BRIDGE_IMR_GIO_MST_TIMEOUT BRIDGE_ISR_GIO_MST_TIMEOUT -#define BRIDGE_IMR_PCI_RETRY_CNT BRIDGE_ISR_PCI_RETRY_CNT -#define BRIDGE_IMR_XREAD_REQ_TIMEOUT BRIDGE_ISR_XREAD_REQ_TIMEOUT -#define BRIDGE_IMR_GIO_B_ENBL_ERR BRIDGE_ISR_GIO_B_ENBL_ERR -#define BRIDGE_IMR_INT_MSK BRIDGE_ISR_INT_MSK -#define BRIDGE_IMR_INT(x) BRIDGE_ISR_INT(x) - -/* - * Bridge interrupt reset register bits definition. Note, PIC can - * reset indiviual error interrupts, BRIDGE & XBRIDGE can only do - * groups of them. - */ -#define PIC_IRR_PCIX_SPLIT_MSG_PE PIC_ISR_PCIX_SPLIT_MSG_PE -#define PIC_IRR_PCIX_SPLIT_EMSG PIC_ISR_PCIX_SPLIT_EMSG -#define PIC_IRR_PCIX_SPLIT_TO PIC_ISR_PCIX_SPLIT_TO -#define PIC_IRR_PCIX_UNEX_COMP PIC_ISR_PCIX_UNEX_COMP -#define PIC_IRR_INT_RAM_PERR PIC_ISR_INT_RAM_PERR -#define PIC_IRR_PCIX_ARB_ERR PIC_ISR_PCIX_ARB_ERR -#define PIC_IRR_PCIX_REQ_TOUT PIC_ISR_PCIX_REQ_TOUT -#define PIC_IRR_PCIX_TABORT PIC_ISR_PCIX_TABORT -#define PIC_IRR_PCIX_PERR PIC_ISR_PCIX_PERR -#define PIC_IRR_PCIX_SERR PIC_ISR_PCIX_SERR -#define PIC_IRR_PCIX_MRETRY PIC_ISR_PCIX_MRETRY -#define PIC_IRR_PCIX_MTOUT PIC_ISR_PCIX_MTOUT -#define PIC_IRR_PCIX_DA_PARITY PIC_ISR_PCIX_DA_PARITY -#define PIC_IRR_PCIX_AD_PARITY PIC_ISR_PCIX_AD_PARITY -#define PIC_IRR_PAGE_FAULT BRIDGE_ISR_PAGE_FAULT -#define PIC_IRR_UNEXP_RESP BRIDGE_ISR_UNEXP_RESP -#define PIC_IRR_BAD_XRESP_PKT BRIDGE_ISR_BAD_XRESP_PKT -#define PIC_IRR_BAD_XREQ_PKT BRIDGE_ISR_BAD_XREQ_PKT -#define PIC_IRR_RESP_XTLK_ERR BRIDGE_ISR_RESP_XTLK_ERR -#define PIC_IRR_REQ_XTLK_ERR BRIDGE_ISR_REQ_XTLK_ERR -#define PIC_IRR_INVLD_ADDR BRIDGE_ISR_INVLD_ADDR -#define PIC_IRR_UNSUPPORTED_XOP BRIDGE_ISR_UNSUPPORTED_XOP -#define PIC_IRR_XREQ_FIFO_OFLOW BRIDGE_ISR_XREQ_FIFO_OFLOW -#define PIC_IRR_LLP_REC_SNERR BRIDGE_ISR_LLP_REC_SNERR -#define PIC_IRR_LLP_REC_CBERR BRIDGE_ISR_LLP_REC_CBERR -#define PIC_IRR_LLP_RCTY BRIDGE_ISR_LLP_RCTY -#define PIC_IRR_LLP_TX_RETRY BRIDGE_ISR_LLP_TX_RETRY -#define PIC_IRR_LLP_TCTY BRIDGE_ISR_LLP_TCTY -#define PIC_IRR_PCI_ABORT BRIDGE_ISR_PCI_ABORT -#define PIC_IRR_PCI_PARITY BRIDGE_ISR_PCI_PARITY -#define PIC_IRR_PCI_SERR BRIDGE_ISR_PCI_SERR -#define PIC_IRR_PCI_PERR BRIDGE_ISR_PCI_PERR -#define PIC_IRR_PCI_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT -#define PIC_IRR_PCI_RETRY_CNT BRIDGE_ISR_PCI_RETRY_CNT -#define PIC_IRR_XREAD_REQ_TIMEOUT BRIDGE_ISR_XREAD_REQ_TIMEOUT -#define BRIDGE_IRR_MULTI_CLR (0x1 << 6) -#define BRIDGE_IRR_CRP_GRP_CLR (0x1 << 5) -#define BRIDGE_IRR_RESP_BUF_GRP_CLR (0x1 << 4) -#define BRIDGE_IRR_REQ_DSP_GRP_CLR (0x1 << 3) -#define BRIDGE_IRR_LLP_GRP_CLR (0x1 << 2) -#define BRIDGE_IRR_SSRAM_GRP_CLR (0x1 << 1) -#define BRIDGE_IRR_PCI_GRP_CLR (0x1 << 0) -#define BRIDGE_IRR_GIO_GRP_CLR (0x1 << 0) -#define BRIDGE_IRR_ALL_CLR 0x7f - -#define BRIDGE_IRR_CRP_GRP (BRIDGE_ISR_UNEXP_RESP | \ - BRIDGE_ISR_XREQ_FIFO_OFLOW) -#define BRIDGE_IRR_RESP_BUF_GRP (BRIDGE_ISR_BAD_XRESP_PKT | \ - BRIDGE_ISR_RESP_XTLK_ERR | \ - BRIDGE_ISR_XREAD_REQ_TIMEOUT) -#define BRIDGE_IRR_REQ_DSP_GRP (BRIDGE_ISR_UNSUPPORTED_XOP | \ - BRIDGE_ISR_BAD_XREQ_PKT | \ - BRIDGE_ISR_REQ_XTLK_ERR | \ - BRIDGE_ISR_INVLD_ADDR) -#define BRIDGE_IRR_LLP_GRP (BRIDGE_ISR_LLP_REC_SNERR | \ - BRIDGE_ISR_LLP_REC_CBERR | \ - BRIDGE_ISR_LLP_RCTY | \ - BRIDGE_ISR_LLP_TX_RETRY | \ - BRIDGE_ISR_LLP_TCTY) -#define BRIDGE_IRR_SSRAM_GRP (BRIDGE_ISR_SSRAM_PERR | \ - BRIDGE_ISR_PMU_ESIZE_FAULT) -#define BRIDGE_IRR_PCI_GRP (BRIDGE_ISR_PCI_ABORT | \ - BRIDGE_ISR_PCI_PARITY | \ - BRIDGE_ISR_PCI_SERR | \ - BRIDGE_ISR_PCI_PERR | \ - BRIDGE_ISR_PCI_MST_TIMEOUT | \ - BRIDGE_ISR_PCI_RETRY_CNT) - -#define BRIDGE_IRR_GIO_GRP (BRIDGE_ISR_GIO_B_ENBL_ERR | \ - BRIDGE_ISR_GIO_MST_TIMEOUT) - -#define PIC_IRR_RAM_GRP PIC_ISR_INT_RAM_PERR - -#define PIC_PCIX_GRP_CLR (PIC_IRR_PCIX_AD_PARITY | \ - PIC_IRR_PCIX_DA_PARITY | \ - PIC_IRR_PCIX_MTOUT | \ - PIC_IRR_PCIX_MRETRY | \ - PIC_IRR_PCIX_SERR | \ - PIC_IRR_PCIX_PERR | \ - PIC_IRR_PCIX_TABORT | \ - PIC_ISR_PCIX_REQ_TOUT | \ - PIC_ISR_PCIX_UNEX_COMP | \ - PIC_ISR_PCIX_SPLIT_TO | \ - PIC_ISR_PCIX_SPLIT_EMSG | \ - PIC_ISR_PCIX_SPLIT_MSG_PE) - -/* Bridge INT_DEV register bits definition */ -#define BRIDGE_INT_DEV_SHFT(n) ((n)*3) -#define BRIDGE_INT_DEV_MASK(n) (0x7 << BRIDGE_INT_DEV_SHFT(n)) -#define BRIDGE_INT_DEV_SET(_dev, _line) (_dev << BRIDGE_INT_DEV_SHFT(_line)) - -/* Bridge interrupt(x) register bits definition */ -#define BRIDGE_INT_ADDR_HOST 0x0003FF00 -#define BRIDGE_INT_ADDR_FLD 0x000000FF - -/* PIC interrupt(x) register bits definition */ -#define PIC_INT_ADDR_FLD 0x00FF000000000000 -#define PIC_INT_ADDR_HOST 0x0000FFFFFFFFFFFF - -#define BRIDGE_TMO_PCI_RETRY_HLD_MASK 0x1f0000 -#define BRIDGE_TMO_GIO_TIMEOUT_MASK 0x001000 -#define BRIDGE_TMO_PCI_RETRY_CNT_MASK 0x0003ff - -#define BRIDGE_TMO_PCI_RETRY_CNT_MAX 0x3ff - -/* Bridge device(x) register bits definition */ -#define BRIDGE_DEV_ERR_LOCK_EN (1ull << 28) -#define BRIDGE_DEV_PAGE_CHK_DIS (1ull << 27) -#define BRIDGE_DEV_FORCE_PCI_PAR (1ull << 26) -#define BRIDGE_DEV_VIRTUAL_EN (1ull << 25) -#define BRIDGE_DEV_PMU_WRGA_EN (1ull << 24) -#define BRIDGE_DEV_DIR_WRGA_EN (1ull << 23) -#define BRIDGE_DEV_DEV_SIZE (1ull << 22) -#define BRIDGE_DEV_RT (1ull << 21) -#define BRIDGE_DEV_SWAP_PMU (1ull << 20) -#define BRIDGE_DEV_SWAP_DIR (1ull << 19) -#define BRIDGE_DEV_PREF (1ull << 18) -#define BRIDGE_DEV_PRECISE (1ull << 17) -#define BRIDGE_DEV_COH (1ull << 16) -#define BRIDGE_DEV_BARRIER (1ull << 15) -#define BRIDGE_DEV_GBR (1ull << 14) -#define BRIDGE_DEV_DEV_SWAP (1ull << 13) -#define BRIDGE_DEV_DEV_IO_MEM (1ull << 12) -#define BRIDGE_DEV_OFF_MASK 0x00000fff -#define BRIDGE_DEV_OFF_ADDR_SHFT 20 - -#define XBRIDGE_DEV_PMU_BITS BRIDGE_DEV_PMU_WRGA_EN -#define BRIDGE_DEV_PMU_BITS (BRIDGE_DEV_PMU_WRGA_EN | \ - BRIDGE_DEV_SWAP_PMU) -#define BRIDGE_DEV_D32_BITS (BRIDGE_DEV_DIR_WRGA_EN | \ - BRIDGE_DEV_SWAP_DIR | \ - BRIDGE_DEV_PREF | \ - BRIDGE_DEV_PRECISE | \ - BRIDGE_DEV_COH | \ - BRIDGE_DEV_BARRIER) -#define XBRIDGE_DEV_D64_BITS (BRIDGE_DEV_DIR_WRGA_EN | \ - BRIDGE_DEV_COH | \ - BRIDGE_DEV_BARRIER) -#define BRIDGE_DEV_D64_BITS (BRIDGE_DEV_DIR_WRGA_EN | \ - BRIDGE_DEV_SWAP_DIR | \ - BRIDGE_DEV_COH | \ - BRIDGE_DEV_BARRIER) - -/* Bridge Error Upper register bit field definition */ -#define BRIDGE_ERRUPPR_DEVMASTER (0x1 << 20) /* Device was master */ -#define BRIDGE_ERRUPPR_PCIVDEV (0x1 << 19) /* Virtual Req value */ -#define BRIDGE_ERRUPPR_DEVNUM_SHFT (16) -#define BRIDGE_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_ERRUPPR_DEVNUM_SHFT) -#define BRIDGE_ERRUPPR_DEVICE(err) (((err) >> BRIDGE_ERRUPPR_DEVNUM_SHFT) & 0x7) -#define BRIDGE_ERRUPPR_ADDRMASK (0xFFFF) - -/* Bridge interrupt mode register bits definition */ -#define BRIDGE_INTMODE_CLR_PKT_EN(x) (0x1 << (x)) - -/* this should be written to the xbow's link_control(x) register */ -#define BRIDGE_CREDIT 3 - -/* RRB assignment register */ -#define BRIDGE_RRB_EN 0x8 /* after shifting down */ -#define BRIDGE_RRB_DEV 0x7 /* after shifting down */ -#define BRIDGE_RRB_VDEV 0x4 /* after shifting down, 2 virtual channels */ -#define BRIDGE_RRB_PDEV 0x3 /* after shifting down, 8 devices */ - -#define PIC_RRB_EN 0x8 /* after shifting down */ -#define PIC_RRB_DEV 0x7 /* after shifting down */ -#define PIC_RRB_VDEV 0x6 /* after shifting down, 4 virtual channels */ -#define PIC_RRB_PDEV 0x1 /* after shifting down, 4 devices */ - -/* RRB status register */ -#define BRIDGE_RRB_VALID(r) (0x00010000<<(r)) -#define BRIDGE_RRB_INUSE(r) (0x00000001<<(r)) - -/* RRB clear register */ -#define BRIDGE_RRB_CLEAR(r) (0x00000001<<(r)) - -/* Defines for the virtual channels so we don't hardcode 0-3 within code */ -#define VCHAN0 0 /* virtual channel 0 (ie. the "normal" channel) */ -#define VCHAN1 1 /* virtual channel 1 */ -#define VCHAN2 2 /* virtual channel 2 - PIC only */ -#define VCHAN3 3 /* virtual channel 3 - PIC only */ - -/* PIC: PCI-X Read Buffer Attribute Register (RBAR) */ -#define NUM_RBAR 16 /* number of RBAR registers */ - -/* xbox system controller declarations */ -#define XBOX_BRIDGE_WID 8 -#define FLASH_PROM1_BASE 0xE00000 /* To read the xbox sysctlr status */ -#define XBOX_RPS_EXISTS 1 << 6 /* RPS bit in status register */ -#define XBOX_RPS_FAIL 1 << 4 /* RPS status bit in register */ - -/* ======================================================================== - */ -/* - * Macros for Xtalk to Bridge bus (PCI/GIO) PIO - * refer to section 4.2.1 of Bridge Spec for xtalk to PCI/GIO PIO mappings - */ -/* XTALK addresses that map into Bridge Bus addr space */ -#define BRIDGE_PIO32_XTALK_ALIAS_BASE 0x000040000000L -#define BRIDGE_PIO32_XTALK_ALIAS_LIMIT 0x00007FFFFFFFL -#define BRIDGE_PIO64_XTALK_ALIAS_BASE 0x000080000000L -#define BRIDGE_PIO64_XTALK_ALIAS_LIMIT 0x0000BFFFFFFFL -#define BRIDGE_PCIIO_XTALK_ALIAS_BASE 0x000100000000L -#define BRIDGE_PCIIO_XTALK_ALIAS_LIMIT 0x0001FFFFFFFFL - -/* Ranges of PCI bus space that can be accessed via PIO from xtalk */ -#define BRIDGE_MIN_PIO_ADDR_MEM 0x00000000 /* 1G PCI memory space */ -#define BRIDGE_MAX_PIO_ADDR_MEM 0x3fffffff -#define BRIDGE_MIN_PIO_ADDR_IO 0x00000000 /* 4G PCI IO space */ -#define BRIDGE_MAX_PIO_ADDR_IO 0xffffffff - -/* XTALK addresses that map into PCI addresses */ -#define BRIDGE_PCI_MEM32_BASE BRIDGE_PIO32_XTALK_ALIAS_BASE -#define BRIDGE_PCI_MEM32_LIMIT BRIDGE_PIO32_XTALK_ALIAS_LIMIT -#define BRIDGE_PCI_MEM64_BASE BRIDGE_PIO64_XTALK_ALIAS_BASE -#define BRIDGE_PCI_MEM64_LIMIT BRIDGE_PIO64_XTALK_ALIAS_LIMIT -#define BRIDGE_PCI_IO_BASE BRIDGE_PCIIO_XTALK_ALIAS_BASE -#define BRIDGE_PCI_IO_LIMIT BRIDGE_PCIIO_XTALK_ALIAS_LIMIT - -/* - * Macros for Xtalk to Bridge bus (PCI) PIO - * refer to section 5.2.1 Figure 4 of the "PCI Interface Chip (PIC) Volume II - * Programmer's Reference" (Revision 0.8 as of this writing). - * - * These are PIC bridge specific. A separate set of macros was defined - * because PIC deviates from Bridge/Xbridge by not supporting a big-window - * alias for PCI I/O space, and also redefines XTALK addresses - * 0x0000C0000000L and 0x000100000000L to be PCI MEM aliases for the second - * bus. - */ - -/* XTALK addresses that map into PIC Bridge Bus addr space */ -#define PICBRIDGE0_PIO32_XTALK_ALIAS_BASE 0x000040000000L -#define PICBRIDGE0_PIO32_XTALK_ALIAS_LIMIT 0x00007FFFFFFFL -#define PICBRIDGE0_PIO64_XTALK_ALIAS_BASE 0x000080000000L -#define PICBRIDGE0_PIO64_XTALK_ALIAS_LIMIT 0x0000BFFFFFFFL -#define PICBRIDGE1_PIO32_XTALK_ALIAS_BASE 0x0000C0000000L -#define PICBRIDGE1_PIO32_XTALK_ALIAS_LIMIT 0x0000FFFFFFFFL -#define PICBRIDGE1_PIO64_XTALK_ALIAS_BASE 0x000100000000L -#define PICBRIDGE1_PIO64_XTALK_ALIAS_LIMIT 0x00013FFFFFFFL - -/* XTALK addresses that map into PCI addresses */ -#define PICBRIDGE0_PCI_MEM32_BASE PICBRIDGE0_PIO32_XTALK_ALIAS_BASE -#define PICBRIDGE0_PCI_MEM32_LIMIT PICBRIDGE0_PIO32_XTALK_ALIAS_LIMIT -#define PICBRIDGE0_PCI_MEM64_BASE PICBRIDGE0_PIO64_XTALK_ALIAS_BASE -#define PICBRIDGE0_PCI_MEM64_LIMIT PICBRIDGE0_PIO64_XTALK_ALIAS_LIMIT -#define PICBRIDGE1_PCI_MEM32_BASE PICBRIDGE1_PIO32_XTALK_ALIAS_BASE -#define PICBRIDGE1_PCI_MEM32_LIMIT PICBRIDGE1_PIO32_XTALK_ALIAS_LIMIT -#define PICBRIDGE1_PCI_MEM64_BASE PICBRIDGE1_PIO64_XTALK_ALIAS_BASE -#define PICBRIDGE1_PCI_MEM64_LIMIT PICBRIDGE1_PIO64_XTALK_ALIAS_LIMIT - -/* - * Macros for Bridge bus (PCI/GIO) to Xtalk DMA - */ -/* Bridge Bus DMA addresses */ -#define BRIDGE_LOCAL_BASE 0 -#define BRIDGE_DMA_MAPPED_BASE 0x40000000 -#define BRIDGE_DMA_MAPPED_SIZE 0x40000000 /* 1G Bytes */ -#define BRIDGE_DMA_DIRECT_BASE 0x80000000 -#define BRIDGE_DMA_DIRECT_SIZE 0x80000000 /* 2G Bytes */ - -#define PCI32_LOCAL_BASE BRIDGE_LOCAL_BASE - -/* PCI addresses of regions decoded by Bridge for DMA */ -#define PCI32_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE -#define PCI32_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE - -#ifndef __ASSEMBLY__ - -#define IS_PCI32_LOCAL(x) ((uint64_t)(x) < PCI32_MAPPED_BASE) -#define IS_PCI32_MAPPED(x) ((uint64_t)(x) < PCI32_DIRECT_BASE && \ - (uint64_t)(x) >= PCI32_MAPPED_BASE) -#define IS_PCI32_DIRECT(x) ((uint64_t)(x) >= PCI32_MAPPED_BASE) -#define IS_PCI64(x) ((uint64_t)(x) >= PCI64_BASE) -#endif /* __ASSEMBLY__ */ - -/* - * The GIO address space. - */ -/* Xtalk to GIO PIO */ -#define BRIDGE_GIO_MEM32_BASE BRIDGE_PIO32_XTALK_ALIAS_BASE -#define BRIDGE_GIO_MEM32_LIMIT BRIDGE_PIO32_XTALK_ALIAS_LIMIT - -#define GIO_LOCAL_BASE BRIDGE_LOCAL_BASE - -/* GIO addresses of regions decoded by Bridge for DMA */ -#define GIO_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE -#define GIO_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE - -#ifndef __ASSEMBLY__ - -#define IS_GIO_LOCAL(x) ((uint64_t)(x) < GIO_MAPPED_BASE) -#define IS_GIO_MAPPED(x) ((uint64_t)(x) < GIO_DIRECT_BASE && \ - (uint64_t)(x) >= GIO_MAPPED_BASE) -#define IS_GIO_DIRECT(x) ((uint64_t)(x) >= GIO_MAPPED_BASE) -#endif /* __ASSEMBLY__ */ - -/* PCI to xtalk mapping */ - -/* given a DIR_OFF value and a pci/gio 32 bits direct address, determine - * which xtalk address is accessed - */ -#define BRIDGE_DIRECT_32_SEG_SIZE BRIDGE_DMA_DIRECT_SIZE -#define BRIDGE_DIRECT_32_TO_XTALK(dir_off,adr) \ - ((dir_off) * BRIDGE_DIRECT_32_SEG_SIZE + \ - ((adr) & (BRIDGE_DIRECT_32_SEG_SIZE - 1)) + PHYS_RAMBASE) - -/* 64-bit address attribute masks */ -#define PCI64_ATTR_TARG_MASK 0xf000000000000000 -#define PCI64_ATTR_TARG_SHFT 60 -#define PCI64_ATTR_PREF (1ull << 59) -#define PCI64_ATTR_PREC (1ull << 58) -#define PCI64_ATTR_VIRTUAL (1ull << 57) -#define PCI64_ATTR_BAR (1ull << 56) -#define PCI64_ATTR_SWAP (1ull << 55) -#define PCI64_ATTR_RMF_MASK 0x00ff000000000000 -#define PCI64_ATTR_RMF_SHFT 48 - -#ifndef __ASSEMBLY__ -/* Address translation entry for mapped pci32 accesses */ -typedef union ate_u { - uint64_t ent; - struct xb_ate_s { /* xbridge */ - uint64_t :16; - uint64_t addr:36; - uint64_t targ:4; - uint64_t reserved:2; - uint64_t swap:1; - uint64_t barrier:1; - uint64_t prefetch:1; - uint64_t precise:1; - uint64_t coherent:1; - uint64_t valid:1; - } xb_field; - struct ate_s { /* bridge */ - uint64_t rmf:16; - uint64_t addr:36; - uint64_t targ:4; - uint64_t reserved:3; - uint64_t barrier:1; - uint64_t prefetch:1; - uint64_t precise:1; - uint64_t coherent:1; - uint64_t valid:1; - } field; -} ate_t; -#endif /* __ASSEMBLY__ */ - -#define ATE_V (1 << 0) -#define ATE_CO (1 << 1) -#define ATE_PREC (1 << 2) -#define ATE_PREF (1 << 3) -#define ATE_BAR (1 << 4) -#define ATE_SWAP (1 << 5) - -#define ATE_PFNSHIFT 12 -#define ATE_TIDSHIFT 8 -#define ATE_RMFSHIFT 48 - -#define mkate(xaddr, xid, attr) ((xaddr) & 0x0000fffffffff000ULL) | \ - ((xid)<<ATE_TIDSHIFT) | \ - (attr) - -/* - * for xbridge, bit 29 of the pci address is the swap bit */ -#define ATE_SWAPSHIFT 29 -#define ATE_SWAP_ON(x) ((x) |= (1 << ATE_SWAPSHIFT)) -#define ATE_SWAP_OFF(x) ((x) &= ~(1 << ATE_SWAPSHIFT)) - -/* extern declarations */ - -#ifndef __ASSEMBLY__ - -/* ======================================================================== - */ - -#ifdef MACROFIELD_LINE -/* - * This table forms a relation between the byte offset macros normally - * used for ASM coding and the calculated byte offsets of the fields - * in the C structure. - * - * See bridge_check.c and bridge_html.c for further details. - */ -#ifndef MACROFIELD_LINE_BITFIELD -#define MACROFIELD_LINE_BITFIELD(m) /* ignored */ -#endif - -struct macrofield_s bridge_macrofield[] = -{ - - MACROFIELD_LINE(BRIDGE_WID_ID, b_wid_id) - MACROFIELD_LINE_BITFIELD(WIDGET_REV_NUM) - MACROFIELD_LINE_BITFIELD(WIDGET_PART_NUM) - MACROFIELD_LINE_BITFIELD(WIDGET_MFG_NUM) - MACROFIELD_LINE(BRIDGE_WID_STAT, b_wid_stat) - MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_LLP_REC_CNT) - MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_LLP_TX_CNT) - MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_FLASH_SELECT) - MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_PCI_GIO_N) - MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_PENDING) - MACROFIELD_LINE(BRIDGE_WID_ERR_UPPER, b_wid_err_upper) - MACROFIELD_LINE(BRIDGE_WID_ERR_LOWER, b_wid_err_lower) - MACROFIELD_LINE(BRIDGE_WID_CONTROL, b_wid_control) - MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_FLASH_WR_EN) - MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_EN_CLK50) - MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_EN_CLK40) - MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_EN_CLK33) - MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_RST_MASK) - MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_IO_SWAP) - MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_MEM_SWAP) - MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_PAGE_SIZE) - MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SS_PAR_BAD) - MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SS_PAR_EN) - MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SSRAM_SIZE_MASK) - MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_F_BAD_PKT) - MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_LLP_XBAR_CRD_MASK) - MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_CLR_RLLP_CNT) - MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_CLR_TLLP_CNT) - MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SYS_END) - MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_MAX_TRANS_MASK) - MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_WIDGET_ID_MASK) - MACROFIELD_LINE(BRIDGE_WID_REQ_TIMEOUT, b_wid_req_timeout) - MACROFIELD_LINE(BRIDGE_WID_INT_UPPER, b_wid_int_upper) - MACROFIELD_LINE_BITFIELD(WIDGET_INT_VECTOR) - MACROFIELD_LINE_BITFIELD(WIDGET_TARGET_ID) - MACROFIELD_LINE_BITFIELD(WIDGET_UPP_ADDR) - MACROFIELD_LINE(BRIDGE_WID_INT_LOWER, b_wid_int_lower) - MACROFIELD_LINE(BRIDGE_WID_ERR_CMDWORD, b_wid_err_cmdword) - MACROFIELD_LINE_BITFIELD(WIDGET_DIDN) - MACROFIELD_LINE_BITFIELD(WIDGET_SIDN) - MACROFIELD_LINE_BITFIELD(WIDGET_PACTYP) - MACROFIELD_LINE_BITFIELD(WIDGET_TNUM) - MACROFIELD_LINE_BITFIELD(WIDGET_COHERENT) - MACROFIELD_LINE_BITFIELD(WIDGET_DS) - MACROFIELD_LINE_BITFIELD(WIDGET_GBR) - MACROFIELD_LINE_BITFIELD(WIDGET_VBPM) - MACROFIELD_LINE_BITFIELD(WIDGET_ERROR) - MACROFIELD_LINE_BITFIELD(WIDGET_BARRIER) - MACROFIELD_LINE(BRIDGE_WID_LLP, b_wid_llp) - MACROFIELD_LINE_BITFIELD(WIDGET_LLP_MAXRETRY) - MACROFIELD_LINE_BITFIELD(WIDGET_LLP_NULLTIMEOUT) - MACROFIELD_LINE_BITFIELD(WIDGET_LLP_MAXBURST) - MACROFIELD_LINE(BRIDGE_WID_TFLUSH, b_wid_tflush) - MACROFIELD_LINE(BRIDGE_WID_AUX_ERR, b_wid_aux_err) - MACROFIELD_LINE(BRIDGE_WID_RESP_UPPER, b_wid_resp_upper) - MACROFIELD_LINE(BRIDGE_WID_RESP_LOWER, b_wid_resp_lower) - MACROFIELD_LINE(BRIDGE_WID_TST_PIN_CTRL, b_wid_tst_pin_ctrl) - MACROFIELD_LINE(BRIDGE_DIR_MAP, b_dir_map) - MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_W_ID) - MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_RMF_64) - MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_ADD512) - MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_OFF) - MACROFIELD_LINE(BRIDGE_RAM_PERR, b_ram_perr) - MACROFIELD_LINE(BRIDGE_ARB, b_arb) - MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_REQ_WAIT_TICK_MASK) - MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_REQ_WAIT_EN_MASK) - MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_FREEZE_GNT) - MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_HPRI_RING_B2) - MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_HPRI_RING_B1) - MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_HPRI_RING_B0) - MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_LPRI_RING_B2) - MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_LPRI_RING_B1) - MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_LPRI_RING_B0) - MACROFIELD_LINE(BRIDGE_NIC, b_nic) - MACROFIELD_LINE(BRIDGE_PCI_BUS_TIMEOUT, b_pci_bus_timeout) - MACROFIELD_LINE(BRIDGE_PCI_CFG, b_pci_cfg) - MACROFIELD_LINE(BRIDGE_PCI_ERR_UPPER, b_pci_err_upper) - MACROFIELD_LINE(BRIDGE_PCI_ERR_LOWER, b_pci_err_lower) - MACROFIELD_LINE(BRIDGE_INT_STATUS, b_int_status) - MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_MULTI_ERR) - MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PMU_ESIZE_FAULT) - MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_UNEXP_RESP) - MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_BAD_XRESP_PKT) - MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_BAD_XREQ_PKT) - MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_RESP_XTLK_ERR) - MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_REQ_XTLK_ERR) - MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_INVLD_ADDR) - MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_UNSUPPORTED_XOP) - MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_XREQ_FIFO_OFLOW) - MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_REC_SNERR) - MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_REC_CBERR) - MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_RCTY) - MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_TX_RETRY) - MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_TCTY) - MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_SSRAM_PERR) - MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_ABORT) - MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_PARITY) - MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_SERR) - MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_PERR) - MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_MST_TIMEOUT) - MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_RETRY_CNT) - MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_XREAD_REQ_TIMEOUT) - MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_GIO_B_ENBL_ERR) - MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_INT_MSK) - MACROFIELD_LINE(BRIDGE_INT_ENABLE, b_int_enable) - MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_UNEXP_RESP) - MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PMU_ESIZE_FAULT) - MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_BAD_XRESP_PKT) - MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_BAD_XREQ_PKT) - MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_RESP_XTLK_ERR) - MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_REQ_XTLK_ERR) - MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_INVLD_ADDR) - MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_UNSUPPORTED_XOP) - MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_XREQ_FIFO_OFLOW) - MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_REC_SNERR) - MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_REC_CBERR) - MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_RCTY) - MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_TX_RETRY) - MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_TCTY) - MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_SSRAM_PERR) - MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_ABORT) - MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_PARITY) - MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_SERR) - MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_PERR) - MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_MST_TIMEOUT) - MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_RETRY_CNT) - MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_XREAD_REQ_TIMEOUT) - MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_GIO_B_ENBL_ERR) - MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_INT_MSK) - MACROFIELD_LINE(BRIDGE_INT_RST_STAT, b_int_rst_stat) - MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_ALL_CLR) - MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_MULTI_CLR) - MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_CRP_GRP_CLR) - MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_RESP_BUF_GRP_CLR) - MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_REQ_DSP_GRP_CLR) - MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_LLP_GRP_CLR) - MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_SSRAM_GRP_CLR) - MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_PCI_GRP_CLR) - MACROFIELD_LINE(BRIDGE_INT_MODE, b_int_mode) - MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(7)) - MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(6)) - MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(5)) - MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(4)) - MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(3)) - MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(2)) - MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(1)) - MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(0)) - MACROFIELD_LINE(BRIDGE_INT_DEVICE, b_int_device) - MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(7)) - MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(6)) - MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(5)) - MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(4)) - MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(3)) - MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(2)) - MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(1)) - MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(0)) - MACROFIELD_LINE(BRIDGE_INT_HOST_ERR, b_int_host_err) - MACROFIELD_LINE_BITFIELD(BRIDGE_INT_ADDR_HOST) - MACROFIELD_LINE_BITFIELD(BRIDGE_INT_ADDR_FLD) - MACROFIELD_LINE(BRIDGE_INT_ADDR0, b_int_addr[0].addr) - MACROFIELD_LINE(BRIDGE_INT_ADDR(0), b_int_addr[0].addr) - MACROFIELD_LINE(BRIDGE_INT_ADDR(1), b_int_addr[1].addr) - MACROFIELD_LINE(BRIDGE_INT_ADDR(2), b_int_addr[2].addr) - MACROFIELD_LINE(BRIDGE_INT_ADDR(3), b_int_addr[3].addr) - MACROFIELD_LINE(BRIDGE_INT_ADDR(4), b_int_addr[4].addr) - MACROFIELD_LINE(BRIDGE_INT_ADDR(5), b_int_addr[5].addr) - MACROFIELD_LINE(BRIDGE_INT_ADDR(6), b_int_addr[6].addr) - MACROFIELD_LINE(BRIDGE_INT_ADDR(7), b_int_addr[7].addr) - MACROFIELD_LINE(BRIDGE_DEVICE0, b_device[0].reg) - MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_ERR_LOCK_EN) - MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PAGE_CHK_DIS) - MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_FORCE_PCI_PAR) - MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_VIRTUAL_EN) - MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PMU_WRGA_EN) - MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DIR_WRGA_EN) - MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DEV_SIZE) - MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_RT) - MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_SWAP_PMU) - MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_SWAP_DIR) - MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PREF) - MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PRECISE) - MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_COH) - MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_BARRIER) - MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_GBR) - MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DEV_SWAP) - MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DEV_IO_MEM) - MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_OFF_MASK) - MACROFIELD_LINE(BRIDGE_DEVICE(0), b_device[0].reg) - MACROFIELD_LINE(BRIDGE_DEVICE(1), b_device[1].reg) - MACROFIELD_LINE(BRIDGE_DEVICE(2), b_device[2].reg) - MACROFIELD_LINE(BRIDGE_DEVICE(3), b_device[3].reg) - MACROFIELD_LINE(BRIDGE_DEVICE(4), b_device[4].reg) - MACROFIELD_LINE(BRIDGE_DEVICE(5), b_device[5].reg) - MACROFIELD_LINE(BRIDGE_DEVICE(6), b_device[6].reg) - MACROFIELD_LINE(BRIDGE_DEVICE(7), b_device[7].reg) - MACROFIELD_LINE(BRIDGE_WR_REQ_BUF0, b_wr_req_buf[0].reg) - MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(0), b_wr_req_buf[0].reg) - MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(1), b_wr_req_buf[1].reg) - MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(2), b_wr_req_buf[2].reg) - MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(3), b_wr_req_buf[3].reg) - MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(4), b_wr_req_buf[4].reg) - MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(5), b_wr_req_buf[5].reg) - MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(6), b_wr_req_buf[6].reg) - MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(7), b_wr_req_buf[7].reg) - MACROFIELD_LINE(BRIDGE_EVEN_RESP, b_even_resp) - MACROFIELD_LINE(BRIDGE_ODD_RESP, b_odd_resp) - MACROFIELD_LINE(BRIDGE_RESP_STATUS, b_resp_status) - MACROFIELD_LINE(BRIDGE_RESP_CLEAR, b_resp_clear) - MACROFIELD_LINE(BRIDGE_ATE_RAM, b_int_ate_ram) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV0, b_type0_cfg_dev[0]) - - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(0), b_type0_cfg_dev[0]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,0), b_type0_cfg_dev[0].f[0]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,1), b_type0_cfg_dev[0].f[1]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,2), b_type0_cfg_dev[0].f[2]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,3), b_type0_cfg_dev[0].f[3]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,4), b_type0_cfg_dev[0].f[4]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,5), b_type0_cfg_dev[0].f[5]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,6), b_type0_cfg_dev[0].f[6]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,7), b_type0_cfg_dev[0].f[7]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(1), b_type0_cfg_dev[1]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,0), b_type0_cfg_dev[1].f[0]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,1), b_type0_cfg_dev[1].f[1]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,2), b_type0_cfg_dev[1].f[2]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,3), b_type0_cfg_dev[1].f[3]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,4), b_type0_cfg_dev[1].f[4]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,5), b_type0_cfg_dev[1].f[5]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,6), b_type0_cfg_dev[1].f[6]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,7), b_type0_cfg_dev[1].f[7]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(2), b_type0_cfg_dev[2]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,0), b_type0_cfg_dev[2].f[0]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,1), b_type0_cfg_dev[2].f[1]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,2), b_type0_cfg_dev[2].f[2]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,3), b_type0_cfg_dev[2].f[3]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,4), b_type0_cfg_dev[2].f[4]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,5), b_type0_cfg_dev[2].f[5]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,6), b_type0_cfg_dev[2].f[6]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,7), b_type0_cfg_dev[2].f[7]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(3), b_type0_cfg_dev[3]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,0), b_type0_cfg_dev[3].f[0]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,1), b_type0_cfg_dev[3].f[1]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,2), b_type0_cfg_dev[3].f[2]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,3), b_type0_cfg_dev[3].f[3]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,4), b_type0_cfg_dev[3].f[4]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,5), b_type0_cfg_dev[3].f[5]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,6), b_type0_cfg_dev[3].f[6]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,7), b_type0_cfg_dev[3].f[7]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(4), b_type0_cfg_dev[4]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,0), b_type0_cfg_dev[4].f[0]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,1), b_type0_cfg_dev[4].f[1]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,2), b_type0_cfg_dev[4].f[2]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,3), b_type0_cfg_dev[4].f[3]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,4), b_type0_cfg_dev[4].f[4]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,5), b_type0_cfg_dev[4].f[5]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,6), b_type0_cfg_dev[4].f[6]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,7), b_type0_cfg_dev[4].f[7]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(5), b_type0_cfg_dev[5]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,0), b_type0_cfg_dev[5].f[0]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,1), b_type0_cfg_dev[5].f[1]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,2), b_type0_cfg_dev[5].f[2]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,3), b_type0_cfg_dev[5].f[3]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,4), b_type0_cfg_dev[5].f[4]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,5), b_type0_cfg_dev[5].f[5]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,6), b_type0_cfg_dev[5].f[6]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,7), b_type0_cfg_dev[5].f[7]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(6), b_type0_cfg_dev[6]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,0), b_type0_cfg_dev[6].f[0]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,1), b_type0_cfg_dev[6].f[1]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,2), b_type0_cfg_dev[6].f[2]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,3), b_type0_cfg_dev[6].f[3]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,4), b_type0_cfg_dev[6].f[4]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,5), b_type0_cfg_dev[6].f[5]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,6), b_type0_cfg_dev[6].f[6]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,7), b_type0_cfg_dev[6].f[7]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(7), b_type0_cfg_dev[7]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,0), b_type0_cfg_dev[7].f[0]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,1), b_type0_cfg_dev[7].f[1]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,2), b_type0_cfg_dev[7].f[2]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,3), b_type0_cfg_dev[7].f[3]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,4), b_type0_cfg_dev[7].f[4]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,5), b_type0_cfg_dev[7].f[5]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,6), b_type0_cfg_dev[7].f[6]) - MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,7), b_type0_cfg_dev[7].f[7]) - - MACROFIELD_LINE(BRIDGE_TYPE1_CFG, b_type1_cfg) - MACROFIELD_LINE(BRIDGE_PCI_IACK, b_pci_iack) - MACROFIELD_LINE(BRIDGE_EXT_SSRAM, b_ext_ate_ram) - MACROFIELD_LINE(BRIDGE_DEVIO0, b_devio(0)) - MACROFIELD_LINE(BRIDGE_DEVIO(0), b_devio(0)) - MACROFIELD_LINE(BRIDGE_DEVIO(1), b_devio(1)) - MACROFIELD_LINE(BRIDGE_DEVIO(2), b_devio(2)) - MACROFIELD_LINE(BRIDGE_DEVIO(3), b_devio(3)) - MACROFIELD_LINE(BRIDGE_DEVIO(4), b_devio(4)) - MACROFIELD_LINE(BRIDGE_DEVIO(5), b_devio(5)) - MACROFIELD_LINE(BRIDGE_DEVIO(6), b_devio(6)) - MACROFIELD_LINE(BRIDGE_DEVIO(7), b_devio(7)) - MACROFIELD_LINE(BRIDGE_EXTERNAL_FLASH, b_external_flash) -}; -#endif - -#ifdef __cplusplus -}; -#endif -#endif /* C or C++ */ - -#endif /* _ASM_SN_PCI_BRIDGE_H */ diff --git a/include/asm-ia64/sn/pci/pci_bus_cvlink.h b/include/asm-ia64/sn/pci/pci_bus_cvlink.h deleted file mode 100644 index fedcccb2b64b..000000000000 --- a/include/asm-ia64/sn/pci/pci_bus_cvlink.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_PCI_CVLINK_H -#define _ASM_IA64_SN_PCI_CVLINK_H - -#include <asm/sn/types.h> -#include <asm/sn/sgi.h> -#include <asm/sn/driver.h> -#include <asm/sn/iograph.h> -#include <asm/param.h> -#include <asm/sn/pio.h> -#include <asm/sn/xtalk/xwidget.h> -#include <asm/sn/sn_private.h> -#include <asm/sn/addrs.h> -#include <asm/sn/hcl.h> -#include <asm/sn/hcl_util.h> -#include <asm/sn/intr.h> -#include <asm/sn/xtalk/xtalkaddrs.h> -#include <asm/sn/klconfig.h> -#include <asm/sn/io.h> - -#include <asm/sn/pci/pciio.h> -#include <asm/sn/pci/pcibr.h> -#include <asm/sn/pci/pcibr_private.h> - -#define MAX_PCI_XWIDGET 256 -#define MAX_ATE_MAPS 1024 - -#define SN_DEVICE_SYSDATA(dev) \ - ((struct sn_device_sysdata *) \ - (((struct pci_controller *) ((dev)->sysdata))->platform_data)) - -#define IS_PCI32G(dev) ((dev)->dma_mask >= 0xffffffff) -#define IS_PCI32L(dev) ((dev)->dma_mask < 0xffffffff) - -#define PCIDEV_VERTEX(pci_dev) \ - ((SN_DEVICE_SYSDATA(pci_dev))->vhdl) - -struct sn_widget_sysdata { - vertex_hdl_t vhdl; -}; - -struct sn_device_sysdata { - vertex_hdl_t vhdl; - pciio_provider_t *pci_provider; - pciio_intr_t intr_handle; - struct sn_flush_device_list *dma_flush_list; - pciio_piomap_t pio_map[PCI_ROM_RESOURCE]; -}; - -struct ioports_to_tlbs_s { - unsigned long p:1, - rv_1:1, - ma:3, - a:1, - d:1, - pl:2, - ar:3, - ppn:38, - rv_2:2, - ed:1, - ig:11; -}; - -#endif /* _ASM_IA64_SN_PCI_CVLINK_H */ diff --git a/include/asm-ia64/sn/pci/pci_defs.h b/include/asm-ia64/sn/pci/pci_defs.h deleted file mode 100644 index 3e64fd5bbdab..000000000000 --- a/include/asm-ia64/sn/pci/pci_defs.h +++ /dev/null @@ -1,414 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (c) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_PCI_PCI_DEFS_H -#define _ASM_IA64_SN_PCI_PCI_DEFS_H - -/* defines for the PCI bus architecture */ - -/* Bit layout of address fields for Type-1 - * Configuration Space cycles. - */ -#define PCI_TYPE0_SLOT_MASK 0xFFFFF800 -#define PCI_TYPE0_FUNC_MASK 0x00000700 -#define PCI_TYPE0_REG_MASK 0x000000FF - -#define PCI_TYPE0_SLOT_SHFT 11 -#define PCI_TYPE0_FUNC_SHFT 8 -#define PCI_TYPE0_REG_SHFT 0 - -#define PCI_TYPE0_FUNC(a) (((a) & PCI_TYPE0_FUNC_MASK) >> PCI_TYPE0_FUNC_SHFT) -#define PCI_TYPE0_REG(a) (((a) & PCI_TYPE0_REG_MASK) >> PCI_TYPE0_REG_SHFT) - -#define PCI_TYPE0(s,f,r) ((((1<<(s)) << PCI_TYPE0_SLOT_SHFT) & PCI_TYPE0_SLOT_MASK) |\ - (((f) << PCI_TYPE0_FUNC_SHFT) & PCI_TYPE0_FUNC_MASK) |\ - (((r) << PCI_TYPE0_REG_SHFT) & PCI_TYPE0_REG_MASK)) - -/* Bit layout of address fields for Type-1 - * Configuration Space cycles. - * NOTE: I'm including the byte offset within - * the 32-bit word as part of the register - * number as an extension of the layout in - * the PCI spec. - */ -#define PCI_TYPE1_BUS_MASK 0x00FF0000 -#define PCI_TYPE1_SLOT_MASK 0x0000F800 -#define PCI_TYPE1_FUNC_MASK 0x00000700 -#define PCI_TYPE1_REG_MASK 0x000000FF - -#define PCI_TYPE1_BUS_SHFT 16 -#define PCI_TYPE1_SLOT_SHFT 11 -#define PCI_TYPE1_FUNC_SHFT 8 -#define PCI_TYPE1_REG_SHFT 0 - -#define PCI_TYPE1_BUS(a) (((a) & PCI_TYPE1_BUS_MASK) >> PCI_TYPE1_BUS_SHFT) -#define PCI_TYPE1_SLOT(a) (((a) & PCI_TYPE1_SLOT_MASK) >> PCI_TYPE1_SLOT_SHFT) -#define PCI_TYPE1_FUNC(a) (((a) & PCI_TYPE1_FUNC_MASK) >> PCI_TYPE1_FUNC_SHFT) -#define PCI_TYPE1_REG(a) (((a) & PCI_TYPE1_REG_MASK) >> PCI_TYPE1_REG_SHFT) - -#define PCI_TYPE1(b,s,f,r) ((((b) << PCI_TYPE1_BUS_SHFT) & PCI_TYPE1_BUS_MASK) |\ - (((s) << PCI_TYPE1_SLOT_SHFT) & PCI_TYPE1_SLOT_MASK) |\ - (((f) << PCI_TYPE1_FUNC_SHFT) & PCI_TYPE1_FUNC_MASK) |\ - (((r) << PCI_TYPE1_REG_SHFT) & PCI_TYPE1_REG_MASK)) - -/* Byte offsets of registers in CFG space - */ -#define PCI_CFG_VENDOR_ID 0x00 /* Vendor ID (2 bytes) */ -#define PCI_CFG_DEVICE_ID 0x02 /* Device ID (2 bytes) */ - -#define PCI_CFG_COMMAND 0x04 /* Command (2 bytes) */ -#define PCI_CFG_STATUS 0x06 /* Status (2 bytes) */ - -/* NOTE: if you are using a C "switch" statement to - * differentiate between the Config space registers, be - * aware that PCI_CFG_CLASS_CODE and PCI_CFG_PROG_IF - * are the same offset. - */ -#define PCI_CFG_REV_ID 0x08 /* Revision Id (1 byte) */ -#define PCI_CFG_CLASS_CODE 0x09 /* Class Code (3 bytes) */ -#define PCI_CFG_PROG_IF 0x09 /* Prog Interface (1 byte) */ -#define PCI_CFG_SUB_CLASS 0x0A /* Sub Class (1 byte) */ -#define PCI_CFG_BASE_CLASS 0x0B /* Base Class (1 byte) */ - -#define PCI_CFG_CACHE_LINE 0x0C /* Cache line size (1 byte) */ -#define PCI_CFG_LATENCY_TIMER 0x0D /* Latency Timer (1 byte) */ -#define PCI_CFG_HEADER_TYPE 0x0E /* Header Type (1 byte) */ -#define PCI_CFG_BIST 0x0F /* Built In Self Test */ - -#define PCI_CFG_BASE_ADDR_0 0x10 /* Base Address (4 bytes) */ -#define PCI_CFG_BASE_ADDR_1 0x14 /* Base Address (4 bytes) */ -#define PCI_CFG_BASE_ADDR_2 0x18 /* Base Address (4 bytes) */ -#define PCI_CFG_BASE_ADDR_3 0x1C /* Base Address (4 bytes) */ -#define PCI_CFG_BASE_ADDR_4 0x20 /* Base Address (4 bytes) */ -#define PCI_CFG_BASE_ADDR_5 0x24 /* Base Address (4 bytes) */ - -#define PCI_CFG_BASE_ADDR_OFF 0x04 /* Base Address Offset (1..5)*/ -#define PCI_CFG_BASE_ADDR(n) (PCI_CFG_BASE_ADDR_0 + (n)*PCI_CFG_BASE_ADDR_OFF) -#define PCI_CFG_BASE_ADDRS 6 /* up to this many BASE regs */ - -#define PCI_CFG_CARDBUS_CIS 0x28 /* Cardbus CIS Pointer (4B) */ - -#define PCI_CFG_SUBSYS_VEND_ID 0x2C /* Subsystem Vendor ID (2B) */ -#define PCI_CFG_SUBSYS_ID 0x2E /* Subsystem ID */ - -#define PCI_EXPANSION_ROM 0x30 /* Expansion Rom Base (4B) */ -#define PCI_CAPABILITIES_PTR 0x34 /* Capabilities Pointer */ - -#define PCI_INTR_LINE 0x3C /* Interrupt Line (1B) */ -#define PCI_INTR_PIN 0x3D /* Interrupt Pin (1B) */ - -#define PCI_CFG_VEND_SPECIFIC 0x40 /* first vendor specific reg */ - -/* layout for Type 0x01 headers */ - -#define PCI_CFG_PPB_BUS_PRI 0x18 /* immediate upstream bus # */ -#define PCI_CFG_PPB_BUS_SEC 0x19 /* immediate downstream bus # */ -#define PCI_CFG_PPB_BUS_SUB 0x1A /* last downstream bus # */ -#define PCI_CFG_PPB_SEC_LAT 0x1B /* latency timer for SEC bus */ -#define PCI_CFG_PPB_IOBASE 0x1C /* IO Base Addr bits 12..15 */ -#define PCI_CFG_PPB_IOLIM 0x1D /* IO Limit Addr bits 12..15 */ -#define PCI_CFG_PPB_SEC_STAT 0x1E /* Secondary Status */ -#define PCI_CFG_PPB_MEMBASE 0x20 /* MEM Base Addr bits 16..31 */ -#define PCI_CFG_PPB_MEMLIM 0x22 /* MEM Limit Addr bits 16..31 */ -#define PCI_CFG_PPB_MEMPFBASE 0x24 /* PfMEM Base Addr bits 16..31 */ -#define PCI_CFG_PPB_MEMPFLIM 0x26 /* PfMEM Limit Addr bits 16..31 */ -#define PCI_CFG_PPB_MEMPFBASEHI 0x28 /* PfMEM Base Addr bits 32..63 */ -#define PCI_CFG_PPB_MEMPFLIMHI 0x2C /* PfMEM Limit Addr bits 32..63 */ -#define PCI_CFG_PPB_IOBASEHI 0x30 /* IO Base Addr bits 16..31 */ -#define PCI_CFG_PPB_IOLIMHI 0x32 /* IO Limit Addr bits 16..31 */ -#define PCI_CFG_PPB_SUB_VENDOR 0x34 /* Subsystem Vendor ID */ -#define PCI_CFG_PPB_SUB_DEVICE 0x36 /* Subsystem Device ID */ -#define PCI_CFG_PPB_ROM_BASE 0x38 /* ROM base address */ -#define PCI_CFG_PPB_INT_LINE 0x3C /* Interrupt Line */ -#define PCI_CFG_PPB_INT_PIN 0x3D /* Interrupt Pin */ -#define PCI_CFG_PPB_BRIDGE_CTRL 0x3E /* Bridge Control */ - /* XXX- these might be DEC 21152 specific */ -#define PCI_CFG_PPB_CHIP_CTRL 0x40 -#define PCI_CFG_PPB_DIAG_CTRL 0x41 -#define PCI_CFG_PPB_ARB_CTRL 0x42 -#define PCI_CFG_PPB_SERR_DISABLE 0x64 -#define PCI_CFG_PPB_CLK2_CTRL 0x68 -#define PCI_CFG_PPB_SERR_STATUS 0x6A - -/* Command Register layout (0x04) */ -#define PCI_CMD_IO_SPACE 0x001 /* I/O Space device */ -#define PCI_CMD_MEM_SPACE 0x002 /* Memory Space */ -#define PCI_CMD_BUS_MASTER 0x004 /* Bus Master */ -#define PCI_CMD_SPEC_CYCLES 0x008 /* Special Cycles */ -#define PCI_CMD_MEMW_INV_ENAB 0x010 /* Memory Write Inv Enable */ -#define PCI_CMD_VGA_PALETTE_SNP 0x020 /* VGA Palette Snoop */ -#define PCI_CMD_PAR_ERR_RESP 0x040 /* Parity Error Response */ -#define PCI_CMD_WAIT_CYCLE_CTL 0x080 /* Wait Cycle Control */ -#define PCI_CMD_SERR_ENABLE 0x100 /* SERR# Enable */ -#define PCI_CMD_F_BK_BK_ENABLE 0x200 /* Fast Back-to-Back Enable */ - -/* Status Register Layout (0x06) */ -#define PCI_STAT_PAR_ERR_DET 0x8000 /* Detected Parity Error */ -#define PCI_STAT_SYS_ERR 0x4000 /* Signaled System Error */ -#define PCI_STAT_RCVD_MSTR_ABT 0x2000 /* Received Master Abort */ -#define PCI_STAT_RCVD_TGT_ABT 0x1000 /* Received Target Abort */ -#define PCI_STAT_SGNL_TGT_ABT 0x0800 /* Signaled Target Abort */ - -#define PCI_STAT_DEVSEL_TIMING 0x0600 /* DEVSEL Timing Mask */ -#define DEVSEL_TIMING(_x) (((_x) >> 9) & 3) /* devsel tim macro */ -#define DEVSEL_FAST 0 /* Fast timing */ -#define DEVSEL_MEDIUM 1 /* Medium timing */ -#define DEVSEL_SLOW 2 /* Slow timing */ - -#define PCI_STAT_DATA_PAR_ERR 0x0100 /* Data Parity Err Detected */ -#define PCI_STAT_F_BK_BK_CAP 0x0080 /* Fast Back-to-Back Capable */ -#define PCI_STAT_UDF_SUPP 0x0040 /* UDF Supported */ -#define PCI_STAT_66MHZ_CAP 0x0020 /* 66 MHz Capable */ -#define PCI_STAT_CAP_LIST 0x0010 /* Capabilities List */ - -/* BIST Register Layout (0x0F) */ -#define PCI_BIST_BIST_CAP 0x80 /* BIST Capable */ -#define PCI_BIST_START_BIST 0x40 /* Start BIST */ -#define PCI_BIST_CMPLTION_MASK 0x0F /* COMPLETION MASK */ -#define PCI_BIST_CMPL_OK 0x00 /* 0 value is completion OK */ - -/* Base Address Register 0x10 */ -#define PCI_BA_IO_CODEMASK 0x3 /* bottom 2 bits encode I/O BAR type */ -#define PCI_BA_IO_SPACE 0x1 /* I/O Space Marker */ - -#define PCI_BA_MEM_CODEMASK 0xf /* bottom 4 bits encode MEM BAR type */ -#define PCI_BA_MEM_LOCATION 0x6 /* 2 bits for location avail */ -#define PCI_BA_MEM_32BIT 0x0 /* Anywhere in 32bit space */ -#define PCI_BA_MEM_1MEG 0x2 /* Locate below 1 Meg */ -#define PCI_BA_MEM_64BIT 0x4 /* Anywhere in 64bit space */ -#define PCI_BA_PREFETCH 0x8 /* Prefetchable, no side effect */ - -#define PCI_BA_ROM_CODEMASK 0x1 /* bottom bit control expansion ROM enable */ -#define PCI_BA_ROM_ENABLE 0x1 /* enable expansion ROM */ - -/* Bridge Control Register 0x3e */ -#define PCI_BCTRL_DTO_SERR 0x0800 /* Discard Timer timeout generates SERR on primary bus */ -#define PCI_BCTRL_DTO 0x0400 /* Discard Timer timeout status */ -#define PCI_BCTRL_DTO_SEC 0x0200 /* Secondary Discard Timer: 0 => 2^15 PCI clock cycles, 1 => 2^10 */ -#define PCI_BCTRL_DTO_PRI 0x0100 /* Primary Discard Timer: 0 => 2^15 PCI clock cycles, 1 => 2^10 */ -#define PCI_BCTRL_F_BK_BK_ENABLE 0x0080 /* Enable Fast Back-to-Back on secondary bus */ -#define PCI_BCTRL_RESET_SEC 0x0040 /* Reset Secondary bus */ -#define PCI_BCTRL_MSTR_ABT_MODE 0x0020 /* Master Abort Mode: 0 => do not report Master-Aborts */ -#define PCI_BCTRL_VGA_AF_ENABLE 0x0008 /* Enable VGA Address Forwarding */ -#define PCI_BCTRL_ISA_AF_ENABLE 0x0004 /* Enable ISA Address Forwarding */ -#define PCI_BCTRL_SERR_ENABLE 0x0002 /* Enable forwarding of SERR from secondary bus to primary bus */ -#define PCI_BCTRL_PAR_ERR_RESP 0x0001 /* Enable Parity Error Response reporting on secondary interface */ - -/* - * PCI 2.2 introduces the concept of ``capability lists.'' Capability lists - * provide a flexible mechanism for a device or bridge to advertise one or - * more standardized capabilities such as the presense of a power management - * interface, etc. The presense of a capability list is indicated by - * PCI_STAT_CAP_LIST being non-zero in the PCI_CFG_STATUS register. If - * PCI_STAT_CAP_LIST is set, then PCI_CFG_CAP_PTR is a ``pointer'' into the - * device-specific portion of the configuration header where the first - * capability block is stored. This ``pointer'' is a single byte which - * contains an offset from the beginning of the configuration header. The - * bottom two bits of the pointer are reserved and should be masked off to - * determine the offset. Each capability block contains a capability ID, a - * ``pointer'' to the next capability (another offset where a zero terminates - * the list) and capability-specific data. Each capability block starts with - * the capability ID and the ``next capability pointer.'' All data following - * this are capability-dependent. - */ -#define PCI_CAP_ID 0x00 /* Capability ID (1B) */ -#define PCI_CAP_PTR 0x01 /* Capability ``pointer'' (1B) */ - -/* PCI Capability IDs */ -#define PCI_CAP_PM 0x01 /* PCI Power Management */ -#define PCI_CAP_AGP 0x02 /* Accelerated Graphics Port */ -#define PCI_CAP_VPD 0x03 /* Vital Product Data (VPD) */ -#define PCI_CAP_SID 0x04 /* Slot Identification */ -#define PCI_CAP_MSI 0x05 /* Message Signaled Intr */ -#define PCI_CAP_HS 0x06 /* CompactPCI Hot Swap */ -#define PCI_CAP_PCIX 0x07 /* PCI-X */ -#define PCI_CAP_ID_HT 0x08 /* HyperTransport */ - - -/* PIO interface macros */ - -#ifndef IOC3_EMULATION - -#define PCI_INB(x) (*((volatile char*)x)) -#define PCI_INH(x) (*((volatile short*)x)) -#define PCI_INW(x) (*((volatile int*)x)) -#define PCI_OUTB(x,y) (*((volatile char*)x) = y) -#define PCI_OUTH(x,y) (*((volatile short*)x) = y) -#define PCI_OUTW(x,y) (*((volatile int*)x) = y) - -#else - -extern unsigned int pci_read(void * address, int type); -extern void pci_write(void * address, int data, int type); - -#define BYTE 1 -#define HALF 2 -#define WORD 4 - -#define PCI_INB(x) pci_read((void *)(x),BYTE) -#define PCI_INH(x) pci_read((void *)(x),HALF) -#define PCI_INW(x) pci_read((void *)(x),WORD) -#define PCI_OUTB(x,y) pci_write((void *)(x),(y),BYTE) -#define PCI_OUTH(x,y) pci_write((void *)(x),(y),HALF) -#define PCI_OUTW(x,y) pci_write((void *)(x),(y),WORD) - -#endif /* !IOC3_EMULATION */ - /* effects on reads, merges */ - -/* - * Definition of address layouts for PCI Config mechanism #1 - * XXX- These largely duplicate PCI_TYPE1 constants at the top - * of the file; the two groups should probably be combined. - */ - -#define CFG1_ADDR_REGISTER_MASK 0x000000fc -#define CFG1_ADDR_FUNCTION_MASK 0x00000700 -#define CFG1_ADDR_DEVICE_MASK 0x0000f800 -#define CFG1_ADDR_BUS_MASK 0x00ff0000 - -#define CFG1_REGISTER_SHIFT 2 -#define CFG1_FUNCTION_SHIFT 8 -#define CFG1_DEVICE_SHIFT 11 -#define CFG1_BUS_SHIFT 16 - -/* - * Class codes - */ -#define PCI_CFG_CLASS_PRE20 0x00 -#define PCI_CFG_CLASS_STORAGE 0x01 -#define PCI_CFG_CLASS_NETWORK 0x02 -#define PCI_CFG_CLASS_DISPLAY 0x03 -#define PCI_CFG_CLASS_MMEDIA 0x04 -#define PCI_CFG_CLASS_MEMORY 0x05 -#define PCI_CFG_CLASS_BRIDGE 0x06 -#define PCI_CFG_CLASS_COMM 0x07 -#define PCI_CFG_CLASS_BASE 0x08 -#define PCI_CFG_CLASS_INPUT 0x09 -#define PCI_CFG_CLASS_DOCK 0x0A -#define PCI_CFG_CLASS_PROC 0x0B -#define PCI_CFG_CLASS_SERIALBUS 0x0C -#define PCI_CFG_CLASS_OTHER 0xFF - -/* - * Important Subclasses - */ -#define PCI_CFG_SUBCLASS_BRIDGE_HOST 0x00 -#define PCI_CFG_SUBCLASS_BRIDGE_ISA 0x01 -#define PCI_CFG_SUBCLASS_BRIDGE_EISA 0x02 -#define PCI_CFG_SUBCLASS_BRIDGE_MC 0x03 -#define PCI_CFG_SUBCLASS_BRIDGE_PCI 0x04 -#define PCI_CFG_SUBCLASS_BRIDGE_PCMCIA 0x05 -#define PCI_CFG_SUBCLASS_BRIDGE_NUBUS 0x06 -#define PCI_CFG_SUBCLASS_BRIDGE_CARDBUS 0x07 -#define PCI_CFG_SUBCLASS_BRIDGE_OTHER 0x80 - -#ifndef __ASSEMBLY__ - -/* - * PCI config space definition - */ -typedef volatile struct pci_cfg_s { - uint16_t vendor_id; - uint16_t dev_id; - uint16_t cmd; - uint16_t status; - uint8_t rev; - uint8_t prog_if; - uint8_t sub_class; - uint8_t class; - uint8_t line_size; - uint8_t lt; - uint8_t hdr_type; - uint8_t bist; - uint32_t bar[6]; - uint32_t cardbus; - uint16_t subsys_vendor_id; - uint16_t subsys_dev_id; - uint32_t exp_rom; - uint32_t res[2]; - uint8_t int_line; - uint8_t int_pin; - uint8_t min_gnt; - uint8_t max_lat; -} pci_cfg_t; - -/* - * PCI Type 1 config space definition for PCI to PCI Bridges (PPBs) - */ -typedef volatile struct pci_cfg1_s { - uint16_t vendor_id; - uint16_t dev_id; - uint16_t cmd; - uint16_t status; - uint8_t rev; - uint8_t prog_if; - uint8_t sub_class; - uint8_t class; - uint8_t line_size; - uint8_t lt; - uint8_t hdr_type; - uint8_t bist; - uint32_t bar[2]; - uint8_t pri_bus_num; - uint8_t snd_bus_num; - uint8_t sub_bus_num; - uint8_t slt; - uint8_t io_base; - uint8_t io_limit; - uint16_t snd_status; - uint16_t mem_base; - uint16_t mem_limit; - uint16_t pmem_base; - uint16_t pmem_limit; - uint32_t pmem_base_upper; - uint32_t pmem_limit_upper; - uint16_t io_base_upper; - uint16_t io_limit_upper; - uint32_t res; - uint32_t exp_rom; - uint8_t int_line; - uint8_t int_pin; - uint16_t ppb_control; - -} pci_cfg1_t; - -/* - * PCI-X Capability - */ -typedef volatile struct cap_pcix_cmd_reg_s { - uint16_t data_parity_enable: 1, - enable_relaxed_order: 1, - max_mem_read_cnt: 2, - max_split: 3, - reserved1: 9; -} cap_pcix_cmd_reg_t; - -typedef volatile struct cap_pcix_stat_reg_s { - uint32_t func_num: 3, - dev_num: 5, - bus_num: 8, - bit64_device: 1, - mhz133_capable: 1, - split_complt_discard: 1, - unexpect_split_complt: 1, - device_complex: 1, - max_mem_read_cnt: 2, - max_out_split: 3, - max_cum_read: 3, - split_complt_err: 1, - reserved1: 2; -} cap_pcix_stat_reg_t; - -typedef volatile struct cap_pcix_type0_s { - uint8_t pcix_cap_id; - uint8_t pcix_cap_nxt; - cap_pcix_cmd_reg_t pcix_type0_command; - cap_pcix_stat_reg_t pcix_type0_status; -} cap_pcix_type0_t; - -#endif /* __ASSEMBLY__ */ -#endif /* _ASM_IA64_SN_PCI_PCI_DEFS_H */ diff --git a/include/asm-ia64/sn/pci/pcibr.h b/include/asm-ia64/sn/pci/pcibr.h deleted file mode 100644 index c46911ae6415..000000000000 --- a/include/asm-ia64/sn/pci/pcibr.h +++ /dev/null @@ -1,535 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_PCI_PCIBR_H -#define _ASM_IA64_SN_PCI_PCIBR_H - -#if defined(__KERNEL__) - -#include <linux/config.h> -#include <asm/sn/dmamap.h> -#include <asm/sn/driver.h> -#include <asm/sn/pio.h> - -#include <asm/sn/pci/pciio.h> -#include <asm/sn/pci/bridge.h> - -/* ===================================================================== - * symbolic constants used by pcibr's xtalk bus provider - */ - -#define PCIBR_PIOMAP_BUSY 0x80000000 - -#define PCIBR_DMAMAP_BUSY 0x80000000 -#define PCIBR_DMAMAP_SSRAM 0x40000000 - -#define PCIBR_INTR_BLOCKED 0x40000000 -#define PCIBR_INTR_BUSY 0x80000000 - -#ifndef __ASSEMBLY__ - -/* ===================================================================== - * opaque types used by pcibr's xtalk bus provider - */ - -typedef struct pcibr_piomap_s *pcibr_piomap_t; -typedef struct pcibr_dmamap_s *pcibr_dmamap_t; -typedef struct pcibr_intr_s *pcibr_intr_t; - -/* ===================================================================== - * bus provider function table - * - * Normally, this table is only handed off explicitly - * during provider initialization, and the PCI generic - * layer will stash a pointer to it in the vertex; however, - * exporting it explicitly enables a performance hack in - * the generic PCI provider where if we know at compile - * time that the only possible PCI provider is a - * pcibr, we can go directly to this ops table. - */ - -extern pciio_provider_t pci_pic_provider; - -/* ===================================================================== - * secondary entry points: pcibr PCI bus provider - * - * These functions are normally exported explicitly by - * a direct call from the pcibr initialization routine - * into the generic crosstalk provider; they are included - * here to enable a more aggressive performance hack in - * the generic crosstalk layer, where if we know that the - * only possible crosstalk provider is pcibr, and we can - * guarantee that all entry points are properly named, and - * we can deal with the implicit casting properly, then - * we can turn many of the generic provider routines into - * plain brances, or even eliminate them (given sufficient - * smarts on the part of the compilation system). - */ - -extern pcibr_piomap_t pcibr_piomap_alloc(vertex_hdl_t dev, - device_desc_t dev_desc, - pciio_space_t space, - iopaddr_t pci_addr, - size_t byte_count, - size_t byte_count_max, - unsigned flags); - -extern void pcibr_piomap_free(pcibr_piomap_t piomap); - -extern caddr_t pcibr_piomap_addr(pcibr_piomap_t piomap, - iopaddr_t xtalk_addr, - size_t byte_count); - -extern void pcibr_piomap_done(pcibr_piomap_t piomap); - -extern int pcibr_piomap_probe(pcibr_piomap_t piomap, - off_t offset, - int len, - void *valp); - -extern caddr_t pcibr_piotrans_addr(vertex_hdl_t dev, - device_desc_t dev_desc, - pciio_space_t space, - iopaddr_t pci_addr, - size_t byte_count, - unsigned flags); - -extern iopaddr_t pcibr_piospace_alloc(vertex_hdl_t dev, - device_desc_t dev_desc, - pciio_space_t space, - size_t byte_count, - size_t alignment); -extern void pcibr_piospace_free(vertex_hdl_t dev, - pciio_space_t space, - iopaddr_t pciaddr, - size_t byte_count); - -extern pcibr_dmamap_t pcibr_dmamap_alloc(vertex_hdl_t dev, - device_desc_t dev_desc, - size_t byte_count_max, - unsigned flags); - -extern void pcibr_dmamap_free(pcibr_dmamap_t dmamap); - -extern iopaddr_t pcibr_dmamap_addr(pcibr_dmamap_t dmamap, - paddr_t paddr, - size_t byte_count); - -extern void pcibr_dmamap_done(pcibr_dmamap_t dmamap); - -/* - * pcibr_get_dmatrans_node() will return the compact node id to which - * all 32-bit Direct Mapping memory accesses will be directed. - * (This node id can be different for each PCI bus.) - */ - -extern cnodeid_t pcibr_get_dmatrans_node(vertex_hdl_t pconn_vhdl); - -extern iopaddr_t pcibr_dmatrans_addr(vertex_hdl_t dev, - device_desc_t dev_desc, - paddr_t paddr, - size_t byte_count, - unsigned flags); - -extern void pcibr_dmamap_drain(pcibr_dmamap_t map); - -extern void pcibr_dmaaddr_drain(vertex_hdl_t vhdl, - paddr_t addr, - size_t bytes); - -typedef unsigned pcibr_intr_ibit_f(pciio_info_t info, - pciio_intr_line_t lines); - -extern void pcibr_intr_ibit_set(vertex_hdl_t, pcibr_intr_ibit_f *); - -extern pcibr_intr_t pcibr_intr_alloc(vertex_hdl_t dev, - device_desc_t dev_desc, - pciio_intr_line_t lines, - vertex_hdl_t owner_dev); - -extern void pcibr_intr_free(pcibr_intr_t intr); - -extern int pcibr_intr_connect(pcibr_intr_t intr, intr_func_t, intr_arg_t); - -extern void pcibr_intr_disconnect(pcibr_intr_t intr); - -extern vertex_hdl_t pcibr_intr_cpu_get(pcibr_intr_t intr); - -extern void pcibr_provider_startup(vertex_hdl_t pcibr); - -extern void pcibr_provider_shutdown(vertex_hdl_t pcibr); - -extern int pcibr_reset(vertex_hdl_t dev); - -extern pciio_endian_t pcibr_endian_set(vertex_hdl_t dev, - pciio_endian_t device_end, - pciio_endian_t desired_end); - -extern uint64_t pcibr_config_get(vertex_hdl_t conn, - unsigned reg, - unsigned size); - -extern void pcibr_config_set(vertex_hdl_t conn, - unsigned reg, - unsigned size, - uint64_t value); - -extern pciio_slot_t pcibr_error_extract(vertex_hdl_t pcibr_vhdl, - pciio_space_t *spacep, - iopaddr_t *addrp); - -extern int pcibr_wrb_flush(vertex_hdl_t pconn_vhdl); -extern int pcibr_rrb_check(vertex_hdl_t pconn_vhdl, - int *count_vchan0, - int *count_vchan1, - int *count_reserved, - int *count_pool); - -extern int pcibr_alloc_all_rrbs(vertex_hdl_t vhdl, int even_odd, - int dev_1_rrbs, int virt1, - int dev_2_rrbs, int virt2, - int dev_3_rrbs, int virt3, - int dev_4_rrbs, int virt4); - -typedef void -rrb_alloc_funct_f (vertex_hdl_t xconn_vhdl, - int *vendor_list); - -typedef rrb_alloc_funct_f *rrb_alloc_funct_t; - -void pcibr_set_rrb_callback(vertex_hdl_t xconn_vhdl, - rrb_alloc_funct_f *func); - -extern int pcibr_device_unregister(vertex_hdl_t); -extern void pcibr_driver_reg_callback(vertex_hdl_t, int, int, int); -extern void pcibr_driver_unreg_callback(vertex_hdl_t, - int, int, int); - - -extern void * pcibr_bridge_ptr_get(vertex_hdl_t, int); - -/* - * Bridge-specific flags that can be set via pcibr_device_flags_set - * and cleared via pcibr_device_flags_clear. Other flags are - * more generic and are maniuplated through PCI-generic interfaces. - * - * Note that all PCI implementation-specific flags (Bridge flags, in - * this case) are in bits 15-31. The lower 15 bits are reserved - * for PCI-generic flags. - * - * Some of these flags have been "promoted" to the - * generic layer, so they can be used without having - * to "know" that the PCI bus is hosted by a Bridge. - * - * PCIBR_NO_ATE_ROUNDUP: Request that no rounding up be done when - * allocating ATE's. ATE count computation will assume that the - * address to be mapped will start on a page boundary. - */ -#define PCIBR_NO_ATE_ROUNDUP 0x00008000 -#define PCIBR_WRITE_GATHER 0x00010000 /* please use PCIIO version */ -#define PCIBR_NOWRITE_GATHER 0x00020000 /* please use PCIIO version */ -#define PCIBR_PREFETCH 0x00040000 /* please use PCIIO version */ -#define PCIBR_NOPREFETCH 0x00080000 /* please use PCIIO version */ -#define PCIBR_PRECISE 0x00100000 -#define PCIBR_NOPRECISE 0x00200000 -#define PCIBR_BARRIER 0x00400000 -#define PCIBR_NOBARRIER 0x00800000 -#define PCIBR_VCHAN0 0x01000000 -#define PCIBR_VCHAN1 0x02000000 -#define PCIBR_64BIT 0x04000000 -#define PCIBR_NO64BIT 0x08000000 -#define PCIBR_SWAP 0x10000000 -#define PCIBR_NOSWAP 0x20000000 - -#define PCIBR_EXTERNAL_ATES 0x40000000 /* uses external ATEs */ -#define PCIBR_ACTIVE 0x80000000 /* need a "done" */ - -/* Flags that have meaning to pcibr_device_flags_{set,clear} */ -#define PCIBR_DEVICE_FLAGS ( \ - PCIBR_WRITE_GATHER |\ - PCIBR_NOWRITE_GATHER |\ - PCIBR_PREFETCH |\ - PCIBR_NOPREFETCH |\ - PCIBR_PRECISE |\ - PCIBR_NOPRECISE |\ - PCIBR_BARRIER |\ - PCIBR_NOBARRIER \ -) - -/* Flags that have meaning to *_dmamap_alloc, *_dmatrans_{addr,list} */ -#define PCIBR_DMA_FLAGS ( \ - PCIBR_PREFETCH |\ - PCIBR_NOPREFETCH |\ - PCIBR_PRECISE |\ - PCIBR_NOPRECISE |\ - PCIBR_BARRIER |\ - PCIBR_NOBARRIER |\ - PCIBR_VCHAN0 |\ - PCIBR_VCHAN1 \ -) - -typedef int pcibr_device_flags_t; - -#define MINIMAL_ATES_REQUIRED(addr, size) \ - (IOPG(IOPGOFF(addr) + (size) - 1) == IOPG((size) - 1)) - -#define MINIMAL_ATE_FLAG(addr, size) \ - (MINIMAL_ATES_REQUIRED((u_long)addr, size) ? PCIBR_NO_ATE_ROUNDUP : 0) - -/* - * Set bits in the Bridge Device(x) register for this device. - * "flags" are defined above. NOTE: this includes turning - * things *OFF* as well as turning them *ON* ... - */ -extern int pcibr_device_flags_set(vertex_hdl_t dev, - pcibr_device_flags_t flags); - -/* - * Allocate Read Response Buffers for use by the specified device. - * count_vchan0 is the total number of buffers desired for the - * "normal" channel. count_vchan1 is the total number of buffers - * desired for the "virtual" channel. Returns 0 on success, or - * <0 on failure, which occurs when we're unable to allocate any - * buffers to a channel that desires at least one buffer. - */ -extern int pcibr_rrb_alloc(vertex_hdl_t pconn_vhdl, - int *count_vchan0, - int *count_vchan1); - -/* - * Get the starting PCIbus address out of the given DMA map. - * This function is supposed to be used by a close friend of PCI bridge - * since it relies on the fact that the starting address of the map is fixed at - * the allocation time in the current implementation of PCI bridge. - */ -extern iopaddr_t pcibr_dmamap_pciaddr_get(pcibr_dmamap_t); -extern void pcibr_hints_fix_rrbs(vertex_hdl_t); -extern void pcibr_hints_dualslot(vertex_hdl_t, pciio_slot_t, pciio_slot_t); -extern void pcibr_hints_subdevs(vertex_hdl_t, pciio_slot_t, ulong); -extern void pcibr_hints_handsoff(vertex_hdl_t); - -typedef unsigned pcibr_intr_bits_f(pciio_info_t, pciio_intr_line_t, int); -extern void pcibr_hints_intr_bits(vertex_hdl_t, pcibr_intr_bits_f *); - -extern int pcibr_asic_rev(vertex_hdl_t); - -#endif /* __ASSEMBLY__ */ -#endif /* #if defined(__KERNEL__) */ -/* - * Some useful ioctls into the pcibr driver - */ -#define PCIBR 'p' -#define _PCIBR(x) ((PCIBR << 8) | (x)) - -/* - * Bit defintions for variable slot_status in struct - * pcibr_soft_slot_s. They are here so that the user - * hot-plug utility can interpret the slot's power - * status. - */ -#ifdef CONFIG_HOTPLUG_PCI_SGI -#define PCI_SLOT_ENABLE_CMPLT 0x01 -#define PCI_SLOT_ENABLE_INCMPLT 0x02 -#define PCI_SLOT_DISABLE_CMPLT 0x04 -#define PCI_SLOT_DISABLE_INCMPLT 0x08 -#define PCI_SLOT_POWER_ON 0x10 -#define PCI_SLOT_POWER_OFF 0x20 -#define PCI_SLOT_IS_SYS_CRITICAL 0x40 -#define PCI_SLOT_PCIBA_LOADED 0x80 - -#define PCI_SLOT_STATUS_MASK (PCI_SLOT_ENABLE_CMPLT | \ - PCI_SLOT_ENABLE_INCMPLT | \ - PCI_SLOT_DISABLE_CMPLT | \ - PCI_SLOT_DISABLE_INCMPLT) -#define PCI_SLOT_POWER_MASK (PCI_SLOT_POWER_ON | PCI_SLOT_POWER_OFF) - -/* - * Bit defintions for variable slot_status in struct - * pcibr_soft_slot_s. They are here so that both - * the pcibr driver and the pciconfig command can - * reference them. - */ -#define SLOT_STARTUP_CMPLT 0x01 -#define SLOT_STARTUP_INCMPLT 0x02 -#define SLOT_SHUTDOWN_CMPLT 0x04 -#define SLOT_SHUTDOWN_INCMPLT 0x08 -#define SLOT_POWER_UP 0x10 -#define SLOT_POWER_DOWN 0x20 -#define SLOT_IS_SYS_CRITICAL 0x40 - -#define SLOT_STATUS_MASK (SLOT_STARTUP_CMPLT | SLOT_STARTUP_INCMPLT | \ - SLOT_SHUTDOWN_CMPLT | SLOT_SHUTDOWN_INCMPLT) -#define SLOT_POWER_MASK (SLOT_POWER_UP | SLOT_POWER_DOWN) - -/* - * Bit definitions for variable resp_f_staus. - * They are here so that both the pcibr driver - * and the pciconfig command can reference them. - */ -#define FUNC_IS_VALID 0x01 -#define FUNC_IS_SYS_CRITICAL 0x02 - -/* - * L1 slot power operations for PCI hot-plug - */ -#define PCI_REQ_SLOT_POWER_ON 1 -#define PCI_L1_QSIZE 128 /* our L1 message buffer size */ - - -#define L1_QSIZE 128 /* our L1 message buffer size */ - -enum pcibr_slot_disable_action_e { - PCI_REQ_SLOT_ELIGIBLE, - PCI_REQ_SLOT_DISABLE -}; - - -struct pcibr_slot_up_resp_s { - int resp_sub_errno; - char resp_l1_msg[L1_QSIZE + 1]; -}; - -struct pcibr_slot_down_resp_s { - int resp_sub_errno; - char resp_l1_msg[L1_QSIZE + 1]; -}; - -struct pcibr_slot_info_resp_s { - short resp_bs_bridge_type; - short resp_bs_bridge_mode; - int resp_has_host; - char resp_host_slot; - vertex_hdl_t resp_slot_conn; - char resp_slot_conn_name[MAXDEVNAME]; - int resp_slot_status; - int resp_l1_bus_num; - int resp_bss_ninfo; - char resp_bss_devio_bssd_space[16]; - iopaddr_t resp_bss_devio_bssd_base; - uint64_t resp_bss_device; - int resp_bss_pmu_uctr; - int resp_bss_d32_uctr; - int resp_bss_d64_uctr; - iopaddr_t resp_bss_d64_base; - unsigned resp_bss_d64_flags; - iopaddr_t resp_bss_d32_base; - unsigned resp_bss_d32_flags; - volatile unsigned *resp_bss_cmd_pointer; - unsigned resp_bss_cmd_shadow; - int resp_bs_rrb_valid; - int resp_bs_rrb_valid_v1; - int resp_bs_rrb_valid_v2; - int resp_bs_rrb_valid_v3; - int resp_bs_rrb_res; - uint64_t resp_b_resp; - uint64_t resp_b_int_device; - uint64_t resp_b_int_enable; - uint64_t resp_b_int_host; - struct pcibr_slot_func_info_resp_s { - int resp_f_status; - char resp_f_slot_name[MAXDEVNAME]; - char resp_f_bus; - char resp_f_slot; - char resp_f_func; - char resp_f_master_name[MAXDEVNAME]; - void *resp_f_pops; - error_handler_f *resp_f_efunc; - error_handler_arg_t resp_f_einfo; - int resp_f_vendor; - int resp_f_device; - - struct { - char resp_w_space[16]; - iopaddr_t resp_w_base; - size_t resp_w_size; - } resp_f_window[6]; - - unsigned resp_f_rbase; - unsigned resp_f_rsize; - int resp_f_ibit[4]; - int resp_f_att_det_error; - - } resp_func[8]; -}; - -struct pcibr_slot_req_s { - int req_slot; - union { - enum pcibr_slot_disable_action_e up; - struct pcibr_slot_down_resp_s *down; - struct pcibr_slot_info_resp_s *query; - void *any; - } req_respp; - int req_size; -}; - -struct pcibr_slot_enable_resp_s { - int resp_sub_errno; - char resp_l1_msg[PCI_L1_QSIZE + 1]; -}; - -struct pcibr_slot_disable_resp_s { - int resp_sub_errno; - char resp_l1_msg[PCI_L1_QSIZE + 1]; -}; - -struct pcibr_slot_enable_req_s { - pciio_slot_t req_device; - struct pcibr_slot_enable_resp_s req_resp; -}; - -struct pcibr_slot_disable_req_s { - pciio_slot_t req_device; - enum pcibr_slot_disable_action_e req_action; - struct pcibr_slot_disable_resp_s req_resp; -}; - -struct pcibr_slot_info_req_s { - pciio_slot_t req_device; - struct pcibr_slot_info_resp_s req_resp; -}; - -#endif /* CONFIG_HOTPLUG_PCI_SGI */ - - -/* - * PCI specific errors, interpreted by pciconfig command - */ - -/* EPERM 1 */ -#define PCI_SLOT_ALREADY_UP 2 /* slot already up */ -#define PCI_SLOT_ALREADY_DOWN 3 /* slot already down */ -#define PCI_IS_SYS_CRITICAL 4 /* slot is system critical */ -/* EIO 5 */ -/* ENXIO 6 */ -#define PCI_L1_ERR 7 /* L1 console command error */ -#define PCI_NOT_A_BRIDGE 8 /* device is not a bridge */ -#define PCI_SLOT_IN_SHOEHORN 9 /* slot is in a shorhorn */ -#define PCI_NOT_A_SLOT 10 /* slot is invalid */ -#define PCI_RESP_AREA_TOO_SMALL 11 /* slot is invalid */ -/* ENOMEM 12 */ -#define PCI_NO_DRIVER 13 /* no driver for device */ -/* EFAULT 14 */ -#define PCI_EMPTY_33MHZ 15 /* empty 33 MHz bus */ -/* EBUSY 16 */ -#define PCI_SLOT_RESET_ERR 17 /* slot reset error */ -#define PCI_SLOT_INFO_INIT_ERR 18 /* slot info init error */ -/* ENODEV 19 */ -#define PCI_SLOT_ADDR_INIT_ERR 20 /* slot addr space init error */ -#define PCI_SLOT_DEV_INIT_ERR 21 /* slot device init error */ -/* EINVAL 22 */ -#define PCI_SLOT_GUEST_INIT_ERR 23 /* slot guest info init error */ -#define PCI_SLOT_RRB_ALLOC_ERR 24 /* slot initial rrb alloc error */ -#define PCI_SLOT_DRV_ATTACH_ERR 25 /* driver attach error */ -#define PCI_SLOT_DRV_DETACH_ERR 26 /* driver detach error */ -/* EFBIG 27 */ -#define PCI_MULTI_FUNC_ERR 28 /* multi-function card error */ -#define PCI_SLOT_RBAR_ALLOC_ERR 29 /* slot PCI-X RBAR alloc error */ -/* ERANGE 34 */ -/* EUNATCH 42 */ - -#endif /* _ASM_IA64_SN_PCI_PCIBR_H */ diff --git a/include/asm-ia64/sn/pci/pcibr_private.h b/include/asm-ia64/sn/pci/pcibr_private.h deleted file mode 100644 index bd9b395390ec..000000000000 --- a/include/asm-ia64/sn/pci/pcibr_private.h +++ /dev/null @@ -1,811 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_PCI_PCIBR_PRIVATE_H -#define _ASM_IA64_SN_PCI_PCIBR_PRIVATE_H - -/* - * pcibr_private.h -- private definitions for pcibr - * only the pcibr driver (and its closest friends) - * should ever peek into this file. - */ - -#include <linux/pci.h> -#include <asm/sn/pci/pcibr.h> -#include <asm/sn/pci/pciio_private.h> - -/* - * convenience typedefs - */ - -typedef uint64_t pcibr_DMattr_t; -typedef uint32_t pcibr_ATEattr_t; - -typedef struct pcibr_info_s *pcibr_info_t, **pcibr_info_h; -typedef struct pcibr_soft_s *pcibr_soft_t; -typedef struct pcibr_soft_slot_s *pcibr_soft_slot_t; -typedef struct pcibr_hints_s *pcibr_hints_t; -typedef struct pcibr_intr_list_s *pcibr_intr_list_t; -typedef struct pcibr_intr_wrap_s *pcibr_intr_wrap_t; -typedef struct pcibr_intr_cbuf_s *pcibr_intr_cbuf_t; - -typedef volatile unsigned int *cfg_p; -typedef volatile bridgereg_t *reg_p; - -/* - * extern functions - */ -cfg_p pcibr_slot_config_addr(pcibr_soft_t, pciio_slot_t, int); -cfg_p pcibr_func_config_addr(pcibr_soft_t, pciio_bus_t bus, pciio_slot_t, pciio_function_t, int); -void pcibr_debug(uint32_t, vertex_hdl_t, char *, ...); -void pcibr_func_config_set(pcibr_soft_t, pciio_slot_t, pciio_function_t, int, unsigned); -/* - * pcireg_ externs - */ - -extern uint64_t pcireg_id_get(pcibr_soft_t); -extern uint64_t pcireg_bridge_id_get(void *); -extern uint64_t pcireg_bus_err_get(pcibr_soft_t); -extern uint64_t pcireg_control_get(pcibr_soft_t); -extern uint64_t pcireg_bridge_control_get(void *); -extern void pcireg_control_set(pcibr_soft_t, uint64_t); -extern void pcireg_control_bit_clr(pcibr_soft_t, uint64_t); -extern void pcireg_control_bit_set(pcibr_soft_t, uint64_t); -extern void pcireg_req_timeout_set(pcibr_soft_t, uint64_t); -extern void pcireg_intr_dst_set(pcibr_soft_t, uint64_t); -extern uint64_t pcireg_intr_dst_target_id_get(pcibr_soft_t); -extern void pcireg_intr_dst_target_id_set(pcibr_soft_t, uint64_t); -extern uint64_t pcireg_intr_dst_addr_get(pcibr_soft_t); -extern void pcireg_intr_dst_addr_set(pcibr_soft_t, uint64_t); -extern uint64_t pcireg_cmdword_err_get(pcibr_soft_t); -extern uint64_t pcireg_llp_cfg_get(pcibr_soft_t); -extern void pcireg_llp_cfg_set(pcibr_soft_t, uint64_t); -extern uint64_t pcireg_tflush_get(pcibr_soft_t); -extern uint64_t pcireg_linkside_err_get(pcibr_soft_t); -extern uint64_t pcireg_resp_err_get(pcibr_soft_t); -extern uint64_t pcireg_resp_err_addr_get(pcibr_soft_t); -extern uint64_t pcireg_resp_err_buf_get(pcibr_soft_t); -extern uint64_t pcireg_resp_err_dev_get(pcibr_soft_t); -extern uint64_t pcireg_linkside_err_addr_get(pcibr_soft_t); -extern uint64_t pcireg_dirmap_get(pcibr_soft_t); -extern void pcireg_dirmap_set(pcibr_soft_t, uint64_t); -extern void pcireg_dirmap_wid_set(pcibr_soft_t, uint64_t); -extern void pcireg_dirmap_diroff_set(pcibr_soft_t, uint64_t); -extern void pcireg_dirmap_add512_set(pcibr_soft_t); -extern void pcireg_dirmap_add512_clr(pcibr_soft_t); -extern uint64_t pcireg_map_fault_get(pcibr_soft_t); -extern uint64_t pcireg_arbitration_get(pcibr_soft_t); -extern void pcireg_arbitration_set(pcibr_soft_t, uint64_t); -extern void pcireg_arbitration_bit_clr(pcibr_soft_t, uint64_t); -extern void pcireg_arbitration_bit_set(pcibr_soft_t, uint64_t); -extern uint64_t pcireg_parity_err_get(pcibr_soft_t); -extern uint64_t pcireg_type1_cntr_get(pcibr_soft_t); -extern void pcireg_type1_cntr_set(pcibr_soft_t, uint64_t); -extern uint64_t pcireg_timeout_get(pcibr_soft_t); -extern void pcireg_timeout_set(pcibr_soft_t, uint64_t); -extern void pcireg_timeout_bit_clr(pcibr_soft_t, uint64_t); -extern void pcireg_timeout_bit_set(pcibr_soft_t, uint64_t); -extern uint64_t pcireg_pci_bus_addr_get(pcibr_soft_t); -extern uint64_t pcireg_pci_bus_addr_addr_get(pcibr_soft_t); -extern uint64_t pcireg_intr_status_get(pcibr_soft_t); -extern uint64_t pcireg_intr_enable_get(pcibr_soft_t); -extern void pcireg_intr_enable_set(pcibr_soft_t, uint64_t); -extern void pcireg_intr_enable_bit_clr(pcibr_soft_t, uint64_t); -extern void pcireg_intr_enable_bit_set(pcibr_soft_t, uint64_t); -extern void pcireg_intr_reset_set(pcibr_soft_t, uint64_t); -extern void pcireg_intr_reset_bit_set(pcibr_soft_t, uint64_t); -extern uint64_t pcireg_intr_mode_get(pcibr_soft_t); -extern void pcireg_intr_mode_set(pcibr_soft_t, uint64_t); -extern void pcireg_intr_mode_bit_clr(pcibr_soft_t, uint64_t); -extern uint64_t pcireg_intr_device_get(pcibr_soft_t); -extern void pcireg_intr_device_set(pcibr_soft_t, uint64_t); -extern void pcireg_intr_device_bit_set(pcibr_soft_t, uint64_t); -extern void pcireg_bridge_intr_device_bit_set(void *, uint64_t); -extern void pcireg_intr_device_bit_clr(pcibr_soft_t, uint64_t); -extern uint64_t pcireg_intr_host_err_get(pcibr_soft_t); -extern void pcireg_intr_host_err_set(pcibr_soft_t, uint64_t); -extern uint64_t pcireg_intr_addr_get(pcibr_soft_t, int); -extern void pcireg_intr_addr_set(pcibr_soft_t, int, uint64_t); -extern void pcireg_bridge_intr_addr_set(void *, int, uint64_t); -extern void * pcireg_intr_addr_addr(pcibr_soft_t, int); -extern void pcireg_intr_addr_vect_set(pcibr_soft_t, int, uint64_t); -extern void pcireg_bridge_intr_addr_vect_set(void *, int, uint64_t); -extern uint64_t pcireg_intr_addr_addr_get(pcibr_soft_t, int); -extern void pcireg_intr_addr_addr_set(pcibr_soft_t, int, uint64_t); -extern void pcireg_bridge_intr_addr_addr_set(void *, int, uint64_t); -extern uint64_t pcireg_intr_view_get(pcibr_soft_t); -extern uint64_t pcireg_intr_multiple_get(pcibr_soft_t); -extern void pcireg_force_always_set(pcibr_soft_t, int); -extern void * pcireg_bridge_force_always_addr_get(void *, int); -extern void * pcireg_force_always_addr_get(pcibr_soft_t, int); -extern void pcireg_force_intr_set(pcibr_soft_t, int); -extern uint64_t pcireg_device_get(pcibr_soft_t, int); -extern void pcireg_device_set(pcibr_soft_t, int, uint64_t); -extern void pcireg_device_bit_set(pcibr_soft_t, int, uint64_t); -extern void pcireg_device_bit_clr(pcibr_soft_t, int, uint64_t); -extern uint64_t pcireg_rrb_get(pcibr_soft_t, int); -extern void pcireg_rrb_set(pcibr_soft_t, int, uint64_t); -extern void pcireg_rrb_bit_set(pcibr_soft_t, int, uint64_t); -extern void pcireg_rrb_bit_clr(pcibr_soft_t, int, uint64_t); -extern uint64_t pcireg_rrb_status_get(pcibr_soft_t); -extern void pcireg_rrb_clear_set(pcibr_soft_t, uint64_t); -extern uint64_t pcireg_wrb_flush_get(pcibr_soft_t, int); -extern uint64_t pcireg_pcix_bus_err_addr_get(pcibr_soft_t); -extern uint64_t pcireg_pcix_bus_err_attr_get(pcibr_soft_t); -extern uint64_t pcireg_pcix_bus_err_data_get(pcibr_soft_t); -extern uint64_t pcireg_pcix_req_err_attr_get(pcibr_soft_t); -extern uint64_t pcireg_pcix_req_err_addr_get(pcibr_soft_t); -extern uint64_t pcireg_pcix_pio_split_addr_get(pcibr_soft_t); -extern uint64_t pcireg_pcix_pio_split_attr_get(pcibr_soft_t); -extern cfg_p pcireg_type1_cfg_addr(pcibr_soft_t, pciio_function_t, - int); -extern cfg_p pcireg_type0_cfg_addr(pcibr_soft_t, pciio_slot_t, - pciio_function_t, int); -extern bridge_ate_t pcireg_int_ate_get(pcibr_soft_t, int); -extern void pcireg_int_ate_set(pcibr_soft_t, int, bridge_ate_t); -extern bridge_ate_p pcireg_int_ate_addr(pcibr_soft_t, int); - -extern uint64_t pcireg_speed_get(pcibr_soft_t); -extern uint64_t pcireg_mode_get(pcibr_soft_t); - -/* - * PCIBR_DEBUG() macro and debug bitmask defines - */ -/* low freqency debug events (ie. initialization, resource allocation,...) */ -#define PCIBR_DEBUG_INIT 0x00000001 /* bridge init */ -#define PCIBR_DEBUG_HINTS 0x00000002 /* bridge hints */ -#define PCIBR_DEBUG_ATTACH 0x00000004 /* bridge attach */ -#define PCIBR_DEBUG_DETACH 0x00000008 /* bridge detach */ -#define PCIBR_DEBUG_ATE 0x00000010 /* bridge ATE allocation */ -#define PCIBR_DEBUG_RRB 0x00000020 /* bridge RRB allocation */ -#define PCIBR_DEBUG_RBAR 0x00000040 /* bridge RBAR allocation */ -#define PCIBR_DEBUG_PROBE 0x00000080 /* bridge device probing */ -#define PCIBR_DEBUG_INTR_ERROR 0x00000100 /* bridge error interrupt */ -#define PCIBR_DEBUG_ERROR_HDLR 0x00000200 /* bridge error handler */ -#define PCIBR_DEBUG_CONFIG 0x00000400 /* device's config space */ -#define PCIBR_DEBUG_BAR 0x00000800 /* device's BAR allocations */ -#define PCIBR_DEBUG_INTR_ALLOC 0x00001000 /* device's intr allocation */ -#define PCIBR_DEBUG_DEV_ATTACH 0x00002000 /* device's attach */ -#define PCIBR_DEBUG_DEV_DETACH 0x00004000 /* device's detach */ -#define PCIBR_DEBUG_HOTPLUG 0x00008000 - -/* high freqency debug events (ie. map allocation, direct translation,...) */ -#define PCIBR_DEBUG_DEVREG 0x04000000 /* bridges device reg sets */ -#define PCIBR_DEBUG_PIOMAP 0x08000000 /* pcibr_piomap */ -#define PCIBR_DEBUG_PIODIR 0x10000000 /* pcibr_piotrans */ -#define PCIBR_DEBUG_DMAMAP 0x20000000 /* pcibr_dmamap */ -#define PCIBR_DEBUG_DMADIR 0x40000000 /* pcibr_dmatrans */ -#define PCIBR_DEBUG_INTR 0x80000000 /* interrupts */ - -extern char *pcibr_debug_module; -extern int pcibr_debug_widget; -extern int pcibr_debug_slot; -extern uint32_t pcibr_debug_mask; - -/* For low frequency events (ie. initialization, resource allocation,...) */ -#define PCIBR_DEBUG_ALWAYS(args) pcibr_debug args ; - -/* XXX: habeck: maybe make PCIBR_DEBUG() always available? Even in non- - * debug kernels? If tracing isn't enabled (i.e pcibr_debug_mask isn't - * set, then the overhead for this macro is just an extra 'if' check. - */ -/* For high frequency events (ie. map allocation, direct translation,...) */ -#if DEBUG -#define PCIBR_DEBUG(args) PCIBR_DEBUG_ALWAYS(args) -#else /* DEBUG */ -#define PCIBR_DEBUG(args) -#endif /* DEBUG */ - -/* - * Bridge sets up PIO using this information. - */ -struct pcibr_piomap_s { - struct pciio_piomap_s bp_pp; /* generic stuff */ - -#define bp_flags bp_pp.pp_flags /* PCIBR_PIOMAP flags */ -#define bp_dev bp_pp.pp_dev /* associated pci card */ -#define bp_slot bp_pp.pp_slot /* which slot the card is in */ -#define bp_space bp_pp.pp_space /* which address space */ -#define bp_pciaddr bp_pp.pp_pciaddr /* starting offset of mapping */ -#define bp_mapsz bp_pp.pp_mapsz /* size of this mapping */ -#define bp_kvaddr bp_pp.pp_kvaddr /* kernel virtual address to use */ - - iopaddr_t bp_xtalk_addr; /* corresponding xtalk address */ - xtalk_piomap_t bp_xtalk_pio; /* corresponding xtalk resource */ - pcibr_piomap_t bp_next; /* Next piomap on the list */ - pcibr_soft_t bp_soft; /* backpointer to bridge soft data */ - atomic_t bp_toc; /* PCI timeout counter */ - -}; - -/* - * Bridge sets up DMA using this information. - */ -struct pcibr_dmamap_s { - struct pciio_dmamap_s bd_pd; -#define bd_flags bd_pd.pd_flags /* PCIBR_DMAMAP flags */ -#define bd_dev bd_pd.pd_dev /* associated pci card */ -#define bd_slot bd_pd.pd_slot /* which slot the card is in */ - struct pcibr_soft_s *bd_soft; /* pcibr soft state backptr */ - xtalk_dmamap_t bd_xtalk; /* associated xtalk resources */ - - size_t bd_max_size; /* maximum size of mapping */ - xwidgetnum_t bd_xio_port; /* target XIO port */ - iopaddr_t bd_xio_addr; /* target XIO address */ - iopaddr_t bd_pci_addr; /* via PCI address */ - - int bd_ate_index; /* Address Translation Entry Index */ - int bd_ate_count; /* number of ATE's allocated */ - bridge_ate_p bd_ate_ptr; /* where to write first ATE */ - bridge_ate_t bd_ate_proto; /* prototype ATE (for xioaddr=0) */ - bridge_ate_t bd_ate_prime; /* value of 1st ATE written */ - dma_addr_t bd_dma_addr; /* Linux dma handle */ - struct resource resource; -}; - -#define IBUFSIZE 5 /* size of circular buffer (holds 4) */ - -/* - * Circular buffer used for interrupt processing - */ -struct pcibr_intr_cbuf_s { - spinlock_t ib_lock; /* cbuf 'put' lock */ - int ib_in; /* index of next free entry */ - int ib_out; /* index of next full entry */ - pcibr_intr_wrap_t ib_cbuf[IBUFSIZE]; /* circular buffer of wrap */ -}; - -/* - * Bridge sets up interrupts using this information. - */ - -struct pcibr_intr_s { - struct pciio_intr_s bi_pi; -#define bi_flags bi_pi.pi_flags /* PCIBR_INTR flags */ -#define bi_dev bi_pi.pi_dev /* associated pci card */ -#define bi_lines bi_pi.pi_lines /* which PCI interrupt line(s) */ -#define bi_func bi_pi.pi_func /* handler function (when connected) */ -#define bi_arg bi_pi.pi_arg /* handler parameter (when connected) */ -#define bi_mustruncpu bi_pi.pi_mustruncpu /* Where we must run. */ -#define bi_irq bi_pi.pi_irq /* IRQ assigned. */ -#define bi_cpu bi_pi.pi_cpu /* cpu assigned. */ - unsigned int bi_ibits; /* which Bridge interrupt bit(s) */ - pcibr_soft_t bi_soft; /* shortcut to soft info */ - struct pcibr_intr_cbuf_s bi_ibuf; /* circular buffer of wrap ptrs */ - unsigned bi_last_intr; /* For Shub lb lost intr. bug */ -}; - - -/* - * PCIBR_INFO_SLOT_GET_EXT returns the external slot number that the card - * resides in. (i.e the slot number silk screened on the back of the I/O - * brick). PCIBR_INFO_SLOT_GET_INT returns the internal slot (or device) - * number used by the pcibr code to represent that external slot (i.e to - * set bit patterns in BRIDGE/PIC registers to represent the device, or to - * offset into an array, or ...). - * - * In BRIDGE and XBRIDGE the external slot and internal device numbering - * are the same. (0->0, 1->1, 2->2,... 7->7) BUT in the PIC the external - * slot number is always 1 greater than the internal device number (1->0, - * 2->1, 3->2, 4->3). This is due to the fact that the PCI-X spec requires - * that the 'bridge' (i.e PIC) be designated as 'device 0', thus external - * slot numbering can't start at zero. - * - * PCIBR_DEVICE_TO_SLOT converts an internal device number to an external - * slot number. NOTE: PCIIO_SLOT_NONE stays as PCIIO_SLOT_NONE. - * - * PCIBR_SLOT_TO_DEVICE converts an external slot number to an internal - * device number. NOTE: PCIIO_SLOT_NONE stays as PCIIO_SLOT_NONE. - */ -#define PCIBR_INFO_SLOT_GET_EXT(info) (((pcibr_info_t)info)->f_slot) -#define PCIBR_INFO_SLOT_GET_INT(info) (((pcibr_info_t)info)->f_dev) - -#define PCIBR_DEVICE_TO_SLOT(pcibr_soft, dev_num) \ - (((dev_num) != PCIIO_SLOT_NONE) ? ((dev_num) + 1) : PCIIO_SLOT_NONE) - -#define PCIBR_SLOT_TO_DEVICE(pcibr_soft, slot) \ - (((slot) != PCIIO_SLOT_NONE) ? ((slot) - 1) : PCIIO_SLOT_NONE) - -/* - * per-connect point pcibr data, including standard pciio data in-line: - */ -struct pcibr_info_s { - struct pciio_info_s f_c; /* MUST BE FIRST. */ -#define f_vertex f_c.c_vertex /* back pointer to vertex */ -#define f_bus f_c.c_bus /* which bus the card is in */ -#define f_slot f_c.c_slot /* which slot the card is in */ -#define f_func f_c.c_func /* which func (on multi-func cards) */ -#define f_vendor f_c.c_vendor /* PCI card "vendor" code */ -#define f_device f_c.c_device /* PCI card "device" code */ -#define f_master f_c.c_master /* PCI bus provider */ -#define f_mfast f_c.c_mfast /* cached fastinfo from c_master */ -#define f_pops f_c.c_pops /* cached provider from c_master */ -#define f_efunc f_c.c_efunc /* error handling function */ -#define f_einfo f_c.c_einfo /* first parameter for efunc */ -#define f_window f_c.c_window /* state of BASE regs */ -#define f_rwindow f_c.c_rwindow /* expansion ROM BASE regs */ -#define f_rbase f_c.c_rbase /* expansion ROM base */ -#define f_rsize f_c.c_rsize /* expansion ROM size */ -#define f_piospace f_c.c_piospace /* additional I/O spaces allocated */ - - /* pcibr-specific connection state */ - int f_ibit[4]; /* Bridge bit for each INTx */ - pcibr_piomap_t f_piomap; - int f_att_det_error; - pciio_slot_t f_dev; /* which device the card represents */ - cap_pcix_type0_t *f_pcix_cap; /* pointer to the pcix capability */ -}; - -/* ===================================================================== - * Shared Interrupt Information - */ - -struct pcibr_intr_list_s { - pcibr_intr_list_t il_next; - pcibr_intr_t il_intr; - pcibr_soft_t il_soft; - pciio_slot_t il_slot; -}; - -/* ===================================================================== - * Interrupt Wrapper Data - */ -struct pcibr_intr_wrap_s { - pcibr_soft_t iw_soft; /* which bridge */ - volatile bridgereg_t *iw_stat; /* ptr to b_int_status */ - bridgereg_t iw_ibit; /* bit in b_int_status */ - pcibr_intr_list_t iw_list; /* ghostbusters! */ - int iw_hdlrcnt; /* running handler count */ - int iw_shared; /* if Bridge bit is shared */ - int iw_connected; /* if already connected */ -}; - -#define PCIBR_ISR_ERR_START 8 -#define PCIBR_ISR_MAX_ERRS_BRIDGE 32 -#define PCIBR_ISR_MAX_ERRS_PIC 45 -#define PCIBR_ISR_MAX_ERRS PCIBR_ISR_MAX_ERRS_PIC - -/* - * PCI Base Address Register window allocation constants. - * To reduce the size of the internal resource mapping structures, do - * not use the entire PCI bus I/O address space - */ -#define PCIBR_BUS_IO_BASE 0x200000 -#define PCIBR_BUS_IO_MAX 0x0FFFFFFF -#define PCIBR_BUS_IO_PAGE 0x100000 - -#define PCIBR_BUS_SWIN_BASE PAGE_SIZE -#define PCIBR_BUS_SWIN_MAX 0x000FFFFF -#define PCIBR_BUS_SWIN_PAGE PAGE_SIZE - -#define PCIBR_BUS_MEM_BASE 0x200000 -#define PCIBR_BUS_MEM_MAX 0x3FFFFFFF -#define PCIBR_BUS_MEM_PAGE 0x100000 - -/* defines for pcibr_soft_s->bs_bridge_type */ -#define PCIBR_BRIDGETYPE_PIC 2 -#define IS_PIC_BUSNUM_SOFT(ps, bus) ((ps)->bs_busnum == (bus)) - -/* - * Runtime checks for workarounds. - */ -#define PCIBR_WAR_ENABLED(pv, pcibr_soft) \ - ((1 << XWIDGET_PART_REV_NUM_REV(pcibr_soft->bs_rev_num)) & pv) - -/* defines for pcibr_soft_s->bs_bridge_mode */ -#define PCIBR_BRIDGEMODE_PCI_33 0x0 -#define PCIBR_BRIDGEMODE_PCI_66 0x2 -#define PCIBR_BRIDGEMODE_PCIX_66 0x3 -#define PCIBR_BRIDGEMODE_PCIX_100 0x5 -#define PCIBR_BRIDGEMODE_PCIX_133 0x7 -#define BUSSPEED_MASK 0x6 -#define BUSTYPE_MASK 0x1 - -#define IS_PCI(ps) (!IS_PCIX(ps)) -#define IS_PCIX(ps) ((ps)->bs_bridge_mode & BUSTYPE_MASK) - -#define IS_33MHZ(ps) ((ps)->bs_bridge_mode == PCIBR_BRIDGEMODE_PCI_33) -#define IS_66MHZ(ps) (((ps)->bs_bridge_mode == PCIBR_BRIDGEMODE_PCI_66) || \ - ((ps)->bs_bridge_mode == PCIBR_BRIDGEMODE_PCIX_66)) -#define IS_100MHZ(ps) ((ps)->bs_bridge_mode == PCIBR_BRIDGEMODE_PCIX_100) -#define IS_133MHZ(ps) ((ps)->bs_bridge_mode == PCIBR_BRIDGEMODE_PCIX_133) - - -/* Number of PCI slots. NOTE: this works as long as the first slot - * is zero. Otherwise use ((ps->bs_max_slot+1) - ps->bs_min_slot) - */ -#define PCIBR_NUM_SLOTS(ps) (ps->bs_max_slot+1) - -/* ===================================================================== - * Bridge Device State structure - * - * one instance of this structure is kept for each - * Bridge ASIC in the system. - */ - -struct pcibr_soft_s { - vertex_hdl_t bs_conn; /* xtalk connection point */ - vertex_hdl_t bs_vhdl; /* vertex owned by pcibr */ - uint64_t bs_int_enable; /* Mask of enabled intrs */ - void *bs_base; /* PIO pointer to Bridge chip */ - char *bs_name; /* hw graph name */ - char bs_asic_name[16]; /* ASIC name */ - xwidgetnum_t bs_xid; /* Bridge's xtalk ID number */ - vertex_hdl_t bs_master; /* xtalk master vertex */ - xwidgetnum_t bs_mxid; /* master's xtalk ID number */ - pciio_slot_t bs_first_slot; /* first existing slot */ - pciio_slot_t bs_last_slot; /* last existing slot */ - pciio_slot_t bs_last_reset; /* last slot to reset */ - uint32_t bs_unused_slot; /* unavailable slots bitmask */ - pciio_slot_t bs_min_slot; /* lowest possible slot */ - pciio_slot_t bs_max_slot; /* highest possible slot */ - pcibr_soft_t bs_peers_soft; /* PICs other bus's soft */ - int bs_busnum; /* PIC has two pci busses */ - - iopaddr_t bs_dir_xbase; /* xtalk address for 32-bit PCI direct map */ - xwidgetnum_t bs_dir_xport; /* xtalk port for 32-bit PCI direct map */ - - struct resource bs_int_ate_resource;/* root resource for internal ATEs */ - struct resource bs_ext_ate_resource;/* root resource for external ATEs */ - void *bs_allocated_ate_res;/* resource struct allocated */ - short bs_int_ate_size; /* number of internal ates */ - short bs_bridge_type; /* see defines above */ - short bs_bridge_mode; /* see defines above */ - - int bs_rev_num; /* revision number of Bridge */ - - /* bs_dma_flags are the forced dma flags used on all DMAs. Used for - * working around ASIC rev issues and protocol specific requirements - */ - unsigned int bs_dma_flags; /* forced DMA flags */ - - nasid_t bs_nasid; /* nasid this bus is on */ - moduleid_t bs_moduleid; /* io brick moduleid */ - short bs_bricktype; /* io brick type */ - - /* - * Lock used primarily to get mutual exclusion while managing any - * bridge resources.. - */ - spinlock_t bs_lock; - - vertex_hdl_t bs_noslot_conn; /* NO-SLOT connection point */ - pcibr_info_t bs_noslot_info; - -#ifdef CONFIG_HOTPLUG_PCI_SGI - /* Linux PCI bus structure pointer */ - struct pci_bus *bs_pci_bus; -#endif - - struct pcibr_soft_slot_s { - /* information we keep about each CFG slot */ - - /* some devices (ioc3 in non-slotted - * configurations, sometimes) make use - * of more than one REQ/GNT/INT* signal - * sets. The slot corresponding to the - * IDSEL that the device responds to is - * called the host slot; the slot - * numbers that the device is stealing - * REQ/GNT/INT bits from are known as - * the guest slots. - */ - int has_host; - pciio_slot_t host_slot; - vertex_hdl_t slot_conn; - -#ifdef CONFIG_HOTPLUG_PCI_SGI - /* PCI Hot-Plug status word */ - int slot_status; - - /* PCI Hot-Plug core structure pointer */ - struct hotplug_slot *bss_hotplug_slot; -#endif /* CONFIG_HOTPLUG_PCI_SGI */ - - /* Potentially several connection points - * for this slot. bss_ninfo is how many, - * and bss_infos is a pointer to - * an array pcibr_info_t values (which are - * pointers to pcibr_info structs, stored - * as device_info in connection ponts). - */ - int bss_ninfo; - pcibr_info_h bss_infos; - - /* Temporary Compatibility Macros, for - * stuff that has moved out of bs_slot - * and into the info structure. These - * will go away when their users have - * converted over to multifunction- - * friendly use of bss_{ninfo,infos}. - */ -#define bss_vendor_id bss_infos[0]->f_vendor -#define bss_device_id bss_infos[0]->f_device -#define bss_window bss_infos[0]->f_window -#define bssw_space w_space -#define bssw_base w_base -#define bssw_size w_size - - /* Where is DevIO(x) pointing? */ - /* bssd_space is NONE if it is not assigned. */ - struct { - pciio_space_t bssd_space; - iopaddr_t bssd_base; - int bssd_ref_cnt; - } bss_devio; - - /* Shadow value for Device(x) register, - * so we don't have to go to the chip. - */ - uint64_t bss_device; - - /* Number of sets on GBR/REALTIME bit outstanding - * Used by Priority I/O for tracking reservations - */ - int bss_pri_uctr; - - /* Number of "uses" of PMU, 32-bit direct, - * and 64-bit direct DMA (0:none, <0: trans, - * >0: how many dmamaps). Device(x) bits - * controlling attribute of each kind of - * channel can't be changed by dmamap_alloc - * or dmatrans if the controlling counter - * is nonzero. dmatrans is forever. - */ - int bss_pmu_uctr; - int bss_d32_uctr; - int bss_d64_uctr; - - /* When the contents of mapping configuration - * information is locked down by dmatrans, - * repeated checks of the same flags should - * be shortcircuited for efficiency. - */ - iopaddr_t bss_d64_base; - unsigned bss_d64_flags; - iopaddr_t bss_d32_base; - unsigned bss_d32_flags; - } bs_slot[8]; - - pcibr_intr_bits_f *bs_intr_bits; - - /* PIC PCI-X Read Buffer Management : - * bs_pcix_num_funcs: the total number of PCI-X functions - * on the bus - * bs_pcix_split_tot: total number of outstanding split - * transactions requested by all functions on the bus - * bs_pcix_rbar_percent_allowed: the percentage of the - * total number of buffers a function requested that are - * available to it, not including the 1 RBAR guaranteed - * to it. - * bs_pcix_rbar_inuse: number of RBARs in use. - * bs_pcix_rbar_avail: number of RBARs available. NOTE: - * this value can go negative if we oversubscribe the - * RBARs. (i.e. We have 16 RBARs but 17 functions). - */ - int bs_pcix_num_funcs; - int bs_pcix_split_tot; - int bs_pcix_rbar_percent_allowed; - - int bs_pcix_rbar_inuse; - int bs_pcix_rbar_avail; - - - /* RRB MANAGEMENT - * bs_rrb_fixed: bitmap of slots whose RRB - * allocations we should not "automatically" change - * bs_rrb_avail: number of RRBs that have not - * been allocated or reserved for {even,odd} slots - * bs_rrb_res: number of RRBs currently reserved for the - * use of the index slot number - * bs_rrb_res_dflt: number of RRBs reserved at boot - * time for the use of the index slot number - * bs_rrb_valid: number of RRBs currently marked valid - * for the indexed slot/vchan number; array[slot][vchan] - * bs_rrb_valid_dflt: number of RRBs marked valid at boot - * time for the indexed slot/vchan number; array[slot][vchan] - */ - int bs_rrb_fixed; - int bs_rrb_avail[2]; - int bs_rrb_res[8]; - int bs_rrb_res_dflt[8]; - int bs_rrb_valid[8][4]; - int bs_rrb_valid_dflt[8][4]; - struct { - /* Each Bridge interrupt bit has a single XIO - * interrupt channel allocated. - */ - xtalk_intr_t bsi_xtalk_intr; - /* - * A wrapper structure is associated with each - * Bridge interrupt bit. - */ - struct pcibr_intr_wrap_s bsi_pcibr_intr_wrap; - /* The bus and interrupt bit, used for pcibr_setpciint(). - * The pci busnum is bit3, int_bits bit2:0 - */ - uint32_t bsi_int_bit; - - } bs_intr[8]; - - xtalk_intr_t bsi_err_intr; - - /* - * We stash away some information in this structure on getting - * an error interrupt. This information is used during PIO read/ - * write error handling. - * - * As it stands now, we do not re-enable the error interrupt - * till the error is resolved. Error resolution happens either at - * bus error time for PIO Read errors (~100 microseconds), or at - * the scheduled timeout time for PIO write errors (~milliseconds). - * If this delay causes problems, we may need to move towards - * a different scheme.. - * - * Note that there is no locking while looking at this data structure. - * There should not be any race between bus error code and - * error interrupt code.. will look into this if needed. - * - * NOTE: The above discussion of error interrupt processing is - * no longer true. Whether it should again be true, is - * being looked into. - */ - struct br_errintr_info { - int bserr_toutcnt; - iopaddr_t bserr_addr; /* Address where error occured */ - uint64_t bserr_intstat; /* interrupts active at error dump */ - } bs_errinfo; - - /* - * PCI Bus Space allocation data structure. - * - * The resource mapping functions rmalloc() and rmfree() are used - * to manage the PCI bus I/O, small window, and memory address - * spaces. - * - * This info is used to assign PCI bus space addresses to cards - * via their BARs and to the callers of the pcibr_piospace_alloc() - * interface. - * - * Users of the pcibr_piospace_alloc() interface, such as the VME - * Universe chip, need PCI bus space that is not acquired by BARs. - * Most of these users need "large" amounts of PIO space (typically - * in Megabytes), and they generally tend to take once and never - * release. - */ - struct pciio_win_map_s bs_io_win_map; /* I/O addr space */ - struct pciio_win_map_s bs_swin_map; /* Small window addr space */ - struct pciio_win_map_s bs_mem_win_map; /* Memory addr space */ - - struct resource bs_io_win_root_resource; /* I/O addr space */ - struct resource bs_swin_root_resource; /* Small window addr space */ - struct resource bs_mem_win_root_resource; /* Memory addr space */ - - int bs_bus_addr_status; /* Bus space status */ - -#define PCIBR_BUS_ADDR_MEM_FREED 1 /* Reserved PROM mem addr freed */ -#define PCIBR_BUS_ADDR_IO_FREED 2 /* Reserved PROM I/O addr freed */ - - struct bs_errintr_stat_s { - uint32_t bs_errcount_total; - uint32_t bs_lasterr_timestamp; - uint32_t bs_lasterr_snapshot; - } bs_errintr_stat[PCIBR_ISR_MAX_ERRS]; - - /* - * Bridge-wide endianness control for - * large-window PIO mappings - * - * These fields are set to PCIIO_BYTE_SWAP - * or PCIIO_WORD_VALUES once the swapper - * has been configured, one way or the other, - * for the direct windows. If they are zero, - * nobody has a PIO mapping through that window, - * and the swapper can be set either way. - */ - unsigned bs_pio_end_io; - unsigned bs_pio_end_mem; -}; - -#define PCIBR_ERRTIME_THRESHOLD (100) -#define PCIBR_ERRRATE_THRESHOLD (100) - -/* - * pcibr will respond to hints dropped in its vertex - * using the following structure. - */ -struct pcibr_hints_s { - /* ph_host_slot is actually +1 so "0" means "no host" */ - pciio_slot_t ph_host_slot[8]; /* REQ/GNT/INT in use by ... */ - unsigned int ph_rrb_fixed; /* do not change RRB allocations */ - unsigned int ph_hands_off; /* prevent further pcibr operations */ - rrb_alloc_funct_t rrb_alloc_funct; /* do dynamic rrb allocation */ - pcibr_intr_bits_f *ph_intr_bits; /* map PCI INT[ABCD] to Bridge Int(n) */ -}; - -/* - * Number of bridge non-fatal error interrupts we can see before - * we decide to disable that interrupt. - */ -#define PCIBR_ERRINTR_DISABLE_LEVEL 10000 - -/* ===================================================================== - * Bridge (pcibr) state management functions - * - * pcibr_soft_get is here because we do it in a lot - * of places and I want to make sure they all stay - * in step with each other. - * - * pcibr_soft_set is here because I want it to be - * closely associated with pcibr_soft_get, even - * though it is only called in one place. - */ - -#define pcibr_soft_get(v) ((pcibr_soft_t)hwgraph_fastinfo_get((v))) -#define pcibr_soft_set(v,i) (hwgraph_fastinfo_set((v), (arbitrary_info_t)(i))) - -/* - * Additional PIO spaces per slot are - * recorded in this structure. - */ -struct pciio_piospace_s { - pciio_piospace_t next; /* another space for this device */ - char free; /* 1 if free, 0 if in use */ - pciio_space_t space; /* Which space is in use */ - iopaddr_t start; /* Starting address of the PIO space */ - size_t count; /* size of PIO space */ -}; - -/* - * pcibr_soft structure locking macros - */ -inline static unsigned long -pcibr_lock(pcibr_soft_t pcibr_soft) -{ - unsigned long flag; - spin_lock_irqsave(&pcibr_soft->bs_lock, flag); - return(flag); -} -#define pcibr_unlock(pcibr_soft, flag) spin_unlock_irqrestore(&pcibr_soft->bs_lock, flag) - -#define PCIBR_VALID_SLOT(ps, s) (s < PCIBR_NUM_SLOTS(ps)) -#define PCIBR_D64_BASE_UNSET (0xFFFFFFFFFFFFFFFF) -#define PCIBR_D32_BASE_UNSET (0xFFFFFFFF) -#define INFO_LBL_PCIBR_ASIC_REV "_pcibr_asic_rev" - -#define PCIBR_SOFT_LIST 1 -#if PCIBR_SOFT_LIST -typedef struct pcibr_list_s *pcibr_list_p; -struct pcibr_list_s { - pcibr_list_p bl_next; - pcibr_soft_t bl_soft; - vertex_hdl_t bl_vhdl; -}; -#endif /* PCIBR_SOFT_LIST */ - -/* Devices per widget: 2 buses, 2 slots per bus, 8 functions per slot. */ -#define DEV_PER_WIDGET (2*2*8) - -struct sn_flush_device_list { - int bus; - int slot; - int pin; - struct bar_list { - unsigned long start; - unsigned long end; - } bar_list[PCI_ROM_RESOURCE]; - unsigned long force_int_addr; - volatile unsigned long flush_addr; - spinlock_t flush_lock; -}; - -struct sn_flush_nasid_entry { - struct sn_flush_device_list **widget_p; - unsigned long iio_itte[8]; -}; - -#endif /* _ASM_SN_PCI_PCIBR_PRIVATE_H */ diff --git a/include/asm-ia64/sn/pci/pciio.h b/include/asm-ia64/sn/pci/pciio.h deleted file mode 100644 index 24c6ac97f735..000000000000 --- a/include/asm-ia64/sn/pci/pciio.h +++ /dev/null @@ -1,746 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_PCI_PCIIO_H -#define _ASM_IA64_SN_PCI_PCIIO_H - -/* - * pciio.h -- platform-independent PCI interface - */ - -#ifdef __KERNEL__ -#include <linux/ioport.h> -#include <asm/sn/ioerror.h> -#include <asm/sn/driver.h> -#include <asm/sn/hcl.h> -#else -#include <linux/ioport.h> -#include <ioerror.h> -#include <driver.h> -#include <hcl.h> -#endif - -#ifndef __ASSEMBLY__ - -#ifdef __KERNEL__ -#include <asm/sn/dmamap.h> -#else -#include <dmamap.h> -#endif - -typedef int pciio_vendor_id_t; - -#define PCIIO_VENDOR_ID_NONE (-1) - -typedef int pciio_device_id_t; - -#define PCIIO_DEVICE_ID_NONE (-1) - -typedef uint8_t pciio_bus_t; /* PCI bus number (0..255) */ -typedef uint8_t pciio_slot_t; /* PCI slot number (0..31, 255) */ -typedef uint8_t pciio_function_t; /* PCI func number (0..7, 255) */ - -#define PCIIO_SLOTS ((pciio_slot_t)32) -#define PCIIO_FUNCS ((pciio_function_t)8) - -#define PCIIO_SLOT_NONE ((pciio_slot_t)255) -#define PCIIO_FUNC_NONE ((pciio_function_t)255) - -typedef int pciio_intr_line_t; /* PCI interrupt line(s) */ - -#define PCIIO_INTR_LINE(n) (0x1 << (n)) -#define PCIIO_INTR_LINE_A (0x1) -#define PCIIO_INTR_LINE_B (0x2) -#define PCIIO_INTR_LINE_C (0x4) -#define PCIIO_INTR_LINE_D (0x8) - -typedef int pciio_space_t; /* PCI address space designation */ - -#define PCIIO_SPACE_NONE (0) -#define PCIIO_SPACE_ROM (1) -#define PCIIO_SPACE_IO (2) -/* PCIIO_SPACE_ (3) */ -#define PCIIO_SPACE_MEM (4) -#define PCIIO_SPACE_MEM32 (5) -#define PCIIO_SPACE_MEM64 (6) -#define PCIIO_SPACE_CFG (7) -#define PCIIO_SPACE_WIN0 (8) -#define PCIIO_SPACE_WIN(n) (PCIIO_SPACE_WIN0+(n)) /* 8..13 */ -/* PCIIO_SPACE_ (14) */ -#define PCIIO_SPACE_BAD (15) - -#if 1 /* does anyone really use these? */ -#define PCIIO_SPACE_USER0 (20) -#define PCIIO_SPACE_USER(n) (PCIIO_SPACE_USER0+(n)) /* 20 .. ? */ -#endif - -/* - * PCI_NOWHERE is the error value returned in - * place of a PCI address when there is no - * corresponding address. - */ -#define PCI_NOWHERE (0) - -/* - * Acceptable flag bits for pciio service calls - * - * PCIIO_FIXED: require that mappings be established - * using fixed sharable resources; address - * translation results will be permanently - * available. (PIOMAP_FIXED and DMAMAP_FIXED are - * the same numeric value and are acceptable). - * PCIIO_NOSLEEP: if any part of the operation would - * sleep waiting for resoruces, return an error - * instead. (PIOMAP_NOSLEEP and DMAMAP_NOSLEEP are - * the same numeric value and are acceptable). - * - * PCIIO_DMA_CMD: configure this stream as a - * generic "command" stream. Generally this - * means turn off prefetchers and write - * gatherers, and whatever else might be - * necessary to make command ring DMAs - * work as expected. - * PCIIO_DMA_DATA: configure this stream as a - * generic "data" stream. Generally, this - * means turning on prefetchers and write - * gatherers, and anything else that might - * increase the DMA throughput (short of - * using "high priority" or "real time" - * resources that may lower overall system - * performance). - * PCIIO_DMA_A64: this device is capable of - * using 64-bit DMA addresses. Unless this - * flag is specified, it is assumed that - * the DMA address must be in the low 4G - * of PCI space. - * PCIIO_PREFETCH: if there are prefetchers - * available, they can be turned on. - * PCIIO_NOPREFETCH: any prefetchers along - * the dma path should be turned off. - * PCIIO_WRITE_GATHER: if there are write gatherers - * available, they can be turned on. - * PCIIO_NOWRITE_GATHER: any write gatherers along - * the dma path should be turned off. - * - * PCIIO_BYTE_STREAM: the DMA stream represents a group - * of ordered bytes. Arrange all byte swapping - * hardware so that the bytes land in the correct - * order. This is a common setting for data - * channels, but is NOT implied by PCIIO_DMA_DATA. - * PCIIO_WORD_VALUES: the DMA stream is used to - * communicate quantities stored in multiple bytes, - * and the device doing the DMA is little-endian; - * arrange any swapping hardware so that - * 32-bit-wide values are maintained. This is a - * common setting for command rings that contain - * DMA addresses and counts, but is NOT implied by - * PCIIO_DMA_CMD. CPU Accesses to 16-bit fields - * must have their address xor-ed with 2, and - * accesses to individual bytes must have their - * addresses xor-ed with 3 relative to what the - * device expects. - * - * NOTE: any "provider specific" flags that - * conflict with the generic flags will - * override the generic flags, locally - * at that provider. - * - * Also, note that PCI-generic flags (PCIIO_) are - * in bits 0-14. The upper bits, 15-31, are reserved - * for PCI implementation-specific flags. - */ - -#define PCIIO_FIXED DMAMAP_FIXED -#define PCIIO_NOSLEEP DMAMAP_NOSLEEP - -#define PCIIO_DMA_CMD 0x0010 -#define PCIIO_DMA_DATA 0x0020 -#define PCIIO_DMA_A64 0x0040 - -#define PCIIO_WRITE_GATHER 0x0100 -#define PCIIO_NOWRITE_GATHER 0x0200 -#define PCIIO_PREFETCH 0x0400 -#define PCIIO_NOPREFETCH 0x0800 - -/* Requesting an endianness setting that the - * underlieing hardware can not support - * WILL result in a failure to allocate - * dmamaps or complete a dmatrans. - */ -#define PCIIO_BYTE_STREAM 0x1000 /* set BYTE SWAP for "byte stream" */ -#define PCIIO_WORD_VALUES 0x2000 /* set BYTE SWAP for "word values" */ - -/* - * Interface to deal with PCI endianness. - * The driver calls pciio_endian_set once, supplying the actual endianness of - * the device and the desired endianness. On SGI systems, only use LITTLE if - * dealing with a driver that does software swizzling. Most of the time, - * it's preferable to request BIG. The return value indicates the endianness - * that is actually achieved. On systems that support hardware swizzling, - * the achieved endianness will be the desired endianness. On systems without - * swizzle hardware, the achieved endianness will be the device's endianness. - */ -typedef enum pciio_endian_e { - PCIDMA_ENDIAN_BIG, - PCIDMA_ENDIAN_LITTLE -} pciio_endian_t; - -/* - * Generic PCI bus information - */ -typedef enum pciio_asic_type_e { - PCIIO_ASIC_TYPE_UNKNOWN, - PCIIO_ASIC_TYPE_MACE, - PCIIO_ASIC_TYPE_BRIDGE, - PCIIO_ASIC_TYPE_XBRIDGE, - PCIIO_ASIC_TYPE_PIC, -} pciio_asic_type_t; - -typedef enum pciio_bus_type_e { - PCIIO_BUS_TYPE_UNKNOWN, - PCIIO_BUS_TYPE_PCI, - PCIIO_BUS_TYPE_PCIX -} pciio_bus_type_t; - -typedef enum pciio_bus_speed_e { - PCIIO_BUS_SPEED_UNKNOWN, - PCIIO_BUS_SPEED_33, - PCIIO_BUS_SPEED_66, - PCIIO_BUS_SPEED_100, - PCIIO_BUS_SPEED_133 -} pciio_bus_speed_t; - -/* - * Interface to set PCI arbitration priority for devices that require - * realtime characteristics. pciio_priority_set is used to switch a - * device between the PCI high-priority arbitration ring and the low - * priority arbitration ring. - * - * (Note: this is strictly for the PCI arbitrary priority. It has - * no direct relationship to GBR.) - */ -typedef enum pciio_priority_e { - PCI_PRIO_LOW, - PCI_PRIO_HIGH -} pciio_priority_t; - -/* - * handles of various sorts - */ -typedef struct pciio_piomap_s *pciio_piomap_t; -typedef struct pciio_dmamap_s *pciio_dmamap_t; -typedef struct pciio_intr_s *pciio_intr_t; -typedef struct pciio_info_s *pciio_info_t; -typedef struct pciio_piospace_s *pciio_piospace_t; -typedef struct pciio_win_info_s *pciio_win_info_t; -typedef struct pciio_win_map_s *pciio_win_map_t; -typedef struct pciio_win_alloc_s *pciio_win_alloc_t; -typedef struct pciio_bus_map_s *pciio_bus_map_t; -typedef struct pciio_businfo_s *pciio_businfo_t; - - -/* PIO MANAGEMENT */ - -/* - * A NOTE ON PCI PIO ADDRESSES - * - * PCI supports three different address spaces: CFG - * space, MEM space and I/O space. Further, each - * card always accepts CFG accesses at an address - * based on which slot it is attached to, but can - * decode up to six address ranges. - * - * Assignment of the base address registers for all - * PCI devices is handled centrally; most commonly, - * device drivers will want to talk to offsets - * within one or another of the address ranges. In - * order to do this, which of these "address - * spaces" the PIO is directed into must be encoded - * in the flag word. - * - * We reserve the right to defer allocation of PCI - * address space for a device window until the - * driver makes a piomap_alloc or piotrans_addr - * request. - * - * If a device driver mucks with its device's base - * registers through a PIO mapping to CFG space, - * results of further PIO through the corresponding - * window are UNDEFINED. - * - * Windows are named by the index in the base - * address register set for the device of the - * desired register; IN THE CASE OF 64 BIT base - * registers, the index should be to the word of - * the register that contains the mapping type - * bits; since the PCI CFG space is natively - * organized little-endian fashion, this is the - * first of the two words. - * - * AT THE MOMENT, any required corrections for - * endianness are the responsibility of the device - * driver; not all platforms support control in - * hardware of byteswapping hardware. We anticipate - * providing flag bits to the PIO and DMA - * management interfaces to request different - * configurations of byteswapping hardware. - * - * PIO Accesses to CFG space via the "Bridge" ASIC - * used in IP30 platforms preserve the native byte - * significance within the 32-bit word; byte - * addresses for single byte accesses need to be - * XORed with 3, and addresses for 16-bit accesses - * need to be XORed with 2. - * - * The IOC3 used on IP30, and other SGI PCI devices - * as well, require use of 32-bit accesses to their - * configuration space registers. Any potential PCI - * bus providers need to be aware of this requirement. - */ - -#define PCIIO_PIOMAP_CFG (0x1) -#define PCIIO_PIOMAP_MEM (0x2) -#define PCIIO_PIOMAP_IO (0x4) -#define PCIIO_PIOMAP_WIN(n) (0x8+(n)) - -typedef pciio_piomap_t -pciio_piomap_alloc_f (vertex_hdl_t dev, /* set up mapping for this device */ - device_desc_t dev_desc, /* device descriptor */ - pciio_space_t space, /* which address space */ - iopaddr_t pcipio_addr, /* starting address */ - size_t byte_count, - size_t byte_count_max, /* maximum size of a mapping */ - unsigned int flags); /* defined in sys/pio.h */ - -typedef void -pciio_piomap_free_f (pciio_piomap_t pciio_piomap); - -typedef caddr_t -pciio_piomap_addr_f (pciio_piomap_t pciio_piomap, /* mapping resources */ - iopaddr_t pciio_addr, /* map for this pcipio address */ - size_t byte_count); /* map this many bytes */ - -typedef void -pciio_piomap_done_f (pciio_piomap_t pciio_piomap); - -typedef caddr_t -pciio_piotrans_addr_f (vertex_hdl_t dev, /* translate for this device */ - device_desc_t dev_desc, /* device descriptor */ - pciio_space_t space, /* which address space */ - iopaddr_t pciio_addr, /* starting address */ - size_t byte_count, /* map this many bytes */ - unsigned int flags); - -typedef caddr_t -pciio_pio_addr_f (vertex_hdl_t dev, /* translate for this device */ - device_desc_t dev_desc, /* device descriptor */ - pciio_space_t space, /* which address space */ - iopaddr_t pciio_addr, /* starting address */ - size_t byte_count, /* map this many bytes */ - pciio_piomap_t *mapp, /* in case a piomap was needed */ - unsigned int flags); - -typedef iopaddr_t -pciio_piospace_alloc_f (vertex_hdl_t dev, /* PIO space for this device */ - device_desc_t dev_desc, /* Device descriptor */ - pciio_space_t space, /* which address space */ - size_t byte_count, /* Number of bytes of space */ - size_t alignment); /* Alignment of allocation */ - -typedef void -pciio_piospace_free_f (vertex_hdl_t dev, /* Device freeing space */ - pciio_space_t space, /* Which space is freed */ - iopaddr_t pci_addr, /* Address being freed */ - size_t size); /* Size freed */ - -/* DMA MANAGEMENT */ - -typedef pciio_dmamap_t -pciio_dmamap_alloc_f (vertex_hdl_t dev, /* set up mappings for this device */ - device_desc_t dev_desc, /* device descriptor */ - size_t byte_count_max, /* max size of a mapping */ - unsigned int flags); /* defined in dma.h */ - -typedef void -pciio_dmamap_free_f (pciio_dmamap_t dmamap); - -typedef iopaddr_t -pciio_dmamap_addr_f (pciio_dmamap_t dmamap, /* use these mapping resources */ - paddr_t paddr, /* map for this address */ - size_t byte_count); /* map this many bytes */ - -typedef void -pciio_dmamap_done_f (pciio_dmamap_t dmamap); - -typedef iopaddr_t -pciio_dmatrans_addr_f (vertex_hdl_t dev, /* translate for this device */ - device_desc_t dev_desc, /* device descriptor */ - paddr_t paddr, /* system physical address */ - size_t byte_count, /* length */ - unsigned int flags); /* defined in dma.h */ - -typedef void -pciio_dmamap_drain_f (pciio_dmamap_t map); - -typedef void -pciio_dmaaddr_drain_f (vertex_hdl_t vhdl, - paddr_t addr, - size_t bytes); - - -/* INTERRUPT MANAGEMENT */ - -typedef pciio_intr_t -pciio_intr_alloc_f (vertex_hdl_t dev, /* which PCI device */ - device_desc_t dev_desc, /* device descriptor */ - pciio_intr_line_t lines, /* which line(s) will be used */ - vertex_hdl_t owner_dev); /* owner of this intr */ - -typedef void -pciio_intr_free_f (pciio_intr_t intr_hdl); - -typedef int -pciio_intr_connect_f (pciio_intr_t intr_hdl, intr_func_t intr_func, intr_arg_t intr_arg); /* pciio intr resource handle */ - -typedef void -pciio_intr_disconnect_f (pciio_intr_t intr_hdl); - -typedef vertex_hdl_t -pciio_intr_cpu_get_f (pciio_intr_t intr_hdl); /* pciio intr resource handle */ - -/* CONFIGURATION MANAGEMENT */ - -typedef void -pciio_provider_startup_f (vertex_hdl_t pciio_provider); - -typedef void -pciio_provider_shutdown_f (vertex_hdl_t pciio_provider); - -typedef int -pciio_reset_f (vertex_hdl_t conn); /* pci connection point */ - -typedef pciio_endian_t /* actual endianness */ -pciio_endian_set_f (vertex_hdl_t dev, /* specify endianness for this device */ - pciio_endian_t device_end, /* endianness of device */ - pciio_endian_t desired_end); /* desired endianness */ - -typedef uint64_t -pciio_config_get_f (vertex_hdl_t conn, /* pci connection point */ - unsigned int reg, /* register byte offset */ - unsigned int size); /* width in bytes (1..4) */ - -typedef void -pciio_config_set_f (vertex_hdl_t conn, /* pci connection point */ - unsigned int reg, /* register byte offset */ - unsigned int size, /* width in bytes (1..4) */ - uint64_t value); /* value to store */ - -typedef pciio_slot_t -pciio_error_extract_f (vertex_hdl_t vhdl, - pciio_space_t *spacep, - iopaddr_t *addrp); - -typedef void -pciio_driver_reg_callback_f (vertex_hdl_t conn, - int key1, - int key2, - int error); - -typedef void -pciio_driver_unreg_callback_f (vertex_hdl_t conn, /* pci connection point */ - int key1, - int key2, - int error); - -typedef int -pciio_device_unregister_f (vertex_hdl_t conn); - - -/* - * Adapters that provide a PCI interface adhere to this software interface. - */ -typedef struct pciio_provider_s { - /* ASIC PROVIDER ID */ - pciio_asic_type_t provider_asic; - - /* PIO MANAGEMENT */ - pciio_piomap_alloc_f *piomap_alloc; - pciio_piomap_free_f *piomap_free; - pciio_piomap_addr_f *piomap_addr; - pciio_piomap_done_f *piomap_done; - pciio_piotrans_addr_f *piotrans_addr; - pciio_piospace_alloc_f *piospace_alloc; - pciio_piospace_free_f *piospace_free; - - /* DMA MANAGEMENT */ - pciio_dmamap_alloc_f *dmamap_alloc; - pciio_dmamap_free_f *dmamap_free; - pciio_dmamap_addr_f *dmamap_addr; - pciio_dmamap_done_f *dmamap_done; - pciio_dmatrans_addr_f *dmatrans_addr; - pciio_dmamap_drain_f *dmamap_drain; - pciio_dmaaddr_drain_f *dmaaddr_drain; - - /* INTERRUPT MANAGEMENT */ - pciio_intr_alloc_f *intr_alloc; - pciio_intr_free_f *intr_free; - pciio_intr_connect_f *intr_connect; - pciio_intr_disconnect_f *intr_disconnect; - pciio_intr_cpu_get_f *intr_cpu_get; - - /* CONFIGURATION MANAGEMENT */ - pciio_provider_startup_f *provider_startup; - pciio_provider_shutdown_f *provider_shutdown; - pciio_reset_f *reset; - pciio_endian_set_f *endian_set; - pciio_config_get_f *config_get; - pciio_config_set_f *config_set; - - /* Error handling interface */ - pciio_error_extract_f *error_extract; - - /* Callback support */ - pciio_driver_reg_callback_f *driver_reg_callback; - pciio_driver_unreg_callback_f *driver_unreg_callback; - pciio_device_unregister_f *device_unregister; -} pciio_provider_t; - -/* PCI devices use these standard PCI provider interfaces */ -extern pciio_piomap_alloc_f pciio_piomap_alloc; -extern pciio_piomap_free_f pciio_piomap_free; -extern pciio_piomap_addr_f pciio_piomap_addr; -extern pciio_piomap_done_f pciio_piomap_done; -extern pciio_piotrans_addr_f pciio_piotrans_addr; -extern pciio_pio_addr_f pciio_pio_addr; -extern pciio_piospace_alloc_f pciio_piospace_alloc; -extern pciio_piospace_free_f pciio_piospace_free; -extern pciio_dmamap_alloc_f pciio_dmamap_alloc; -extern pciio_dmamap_free_f pciio_dmamap_free; -extern pciio_dmamap_addr_f pciio_dmamap_addr; -extern pciio_dmamap_done_f pciio_dmamap_done; -extern pciio_dmatrans_addr_f pciio_dmatrans_addr; -extern pciio_dmamap_drain_f pciio_dmamap_drain; -extern pciio_dmaaddr_drain_f pciio_dmaaddr_drain; -extern pciio_intr_alloc_f pciio_intr_alloc; -extern pciio_intr_free_f pciio_intr_free; -extern pciio_intr_connect_f pciio_intr_connect; -extern pciio_intr_disconnect_f pciio_intr_disconnect; -extern pciio_intr_cpu_get_f pciio_intr_cpu_get; -extern pciio_provider_startup_f pciio_provider_startup; -extern pciio_provider_shutdown_f pciio_provider_shutdown; -extern pciio_reset_f pciio_reset; -extern pciio_endian_set_f pciio_endian_set; -extern pciio_config_get_f pciio_config_get; -extern pciio_config_set_f pciio_config_set; - -/* Widgetdev in the IOERROR structure is encoded as follows. - * +---------------------------+ - * | slot (7:3) | function(2:0)| - * +---------------------------+ - * Following are the convenience interfaces to get at form - * a widgetdev or to break it into its constituents. - */ - -#define PCIIO_WIDGETDEV_SLOT_SHFT 3 -#define PCIIO_WIDGETDEV_SLOT_MASK 0x1f -#define PCIIO_WIDGETDEV_FUNC_MASK 0x7 - -#define pciio_widgetdev_create(slot,func) \ - (((slot) << PCIIO_WIDGETDEV_SLOT_SHFT) + (func)) - -#define pciio_widgetdev_slot_get(wdev) \ - (((wdev) >> PCIIO_WIDGETDEV_SLOT_SHFT) & PCIIO_WIDGETDEV_SLOT_MASK) - -#define pciio_widgetdev_func_get(wdev) \ - ((wdev) & PCIIO_WIDGETDEV_FUNC_MASK) - - -/* Generic PCI card initialization interface - */ - -extern int -pciio_driver_register (pciio_vendor_id_t vendor_id, /* card's vendor number */ - pciio_device_id_t device_id, /* card's device number */ - char *driver_prefix, /* driver prefix */ - unsigned int flags); - -extern void -pciio_error_register (vertex_hdl_t pconn, /* which slot */ - error_handler_f *efunc, /* function to call */ - error_handler_arg_t einfo); /* first parameter */ - -extern void pciio_driver_unregister(char *driver_prefix); - -typedef void pciio_iter_f(vertex_hdl_t pconn); /* a connect point */ - -/* Interfaces used by PCI Bus Providers to talk to - * the Generic PCI layer. - */ -extern vertex_hdl_t -pciio_device_register (vertex_hdl_t connectpt, /* vertex at center of bus */ - vertex_hdl_t master, /* card's master ASIC (pci provider) */ - pciio_slot_t slot, /* card's slot (0..?) */ - pciio_function_t func, /* card's func (0..?) */ - pciio_vendor_id_t vendor, /* card's vendor number */ - pciio_device_id_t device); /* card's device number */ - -extern void -pciio_device_unregister(vertex_hdl_t connectpt); - -extern pciio_info_t -pciio_device_info_new (pciio_info_t pciio_info, /* preallocated info struct */ - vertex_hdl_t master, /* card's master ASIC (pci provider) */ - pciio_slot_t slot, /* card's slot (0..?) */ - pciio_function_t func, /* card's func (0..?) */ - pciio_vendor_id_t vendor, /* card's vendor number */ - pciio_device_id_t device); /* card's device number */ - -extern void -pciio_device_info_free(pciio_info_t pciio_info); - -extern vertex_hdl_t -pciio_device_info_register( - vertex_hdl_t connectpt, /* vertex at center of bus */ - pciio_info_t pciio_info); /* details about conn point */ - -extern void -pciio_device_info_unregister( - vertex_hdl_t connectpt, /* vertex at center of bus */ - pciio_info_t pciio_info); /* details about conn point */ - - -extern int -pciio_device_attach( - vertex_hdl_t pcicard, /* vertex created by pciio_device_register */ - int drv_flags); -extern int -pciio_device_detach( - vertex_hdl_t pcicard, /* vertex created by pciio_device_register */ - int drv_flags); - - -/* create and initialize empty window mapping resource */ -extern pciio_win_map_t -pciio_device_win_map_new(pciio_win_map_t win_map, /* preallocated win map structure */ - size_t region_size, /* size of region to be tracked */ - size_t page_size); /* allocation page size */ - -/* destroy window mapping resource freeing up ancillary resources */ -extern void -pciio_device_win_map_free(pciio_win_map_t win_map); /* preallocated win map structure */ - -/* populate window mapping with free range of addresses */ -extern void -pciio_device_win_populate(pciio_win_map_t win_map, /* win map */ - iopaddr_t ioaddr, /* base address of free range */ - size_t size); /* size of free range */ - -/* allocate window from mapping resource */ -extern iopaddr_t -pciio_device_win_alloc(struct resource * res, - pciio_win_alloc_t win_alloc, /* opaque allocation cookie */ - size_t start, /* start unit, or 0 */ - size_t size, /* size of allocation */ - size_t align); /* alignment of allocation */ - -/* free previously allocated window */ -extern void -pciio_device_win_free(pciio_win_alloc_t win_alloc); /* opaque allocation cookie */ - - -/* - * Generic PCI interface, for use with all PCI providers - * and all PCI devices. - */ - -/* Generic PCI interrupt interfaces */ -extern vertex_hdl_t pciio_intr_dev_get(pciio_intr_t pciio_intr); -extern vertex_hdl_t pciio_intr_cpu_get(pciio_intr_t pciio_intr); - -/* Generic PCI pio interfaces */ -extern vertex_hdl_t pciio_pio_dev_get(pciio_piomap_t pciio_piomap); -extern pciio_slot_t pciio_pio_slot_get(pciio_piomap_t pciio_piomap); -extern pciio_space_t pciio_pio_space_get(pciio_piomap_t pciio_piomap); -extern iopaddr_t pciio_pio_pciaddr_get(pciio_piomap_t pciio_piomap); -extern ulong pciio_pio_mapsz_get(pciio_piomap_t pciio_piomap); -extern caddr_t pciio_pio_kvaddr_get(pciio_piomap_t pciio_piomap); - -/* Generic PCI dma interfaces */ -extern vertex_hdl_t pciio_dma_dev_get(pciio_dmamap_t pciio_dmamap); - -/* Register/unregister PCI providers and get implementation handle */ -extern void pciio_provider_register(vertex_hdl_t provider, pciio_provider_t *pciio_fns); -extern void pciio_provider_unregister(vertex_hdl_t provider); -extern pciio_provider_t *pciio_provider_fns_get(vertex_hdl_t provider); - -/* Generic pci slot information access interface */ -extern pciio_info_t pciio_info_chk(vertex_hdl_t vhdl); -extern pciio_info_t pciio_info_get(vertex_hdl_t vhdl); -extern void pciio_info_set(vertex_hdl_t vhdl, pciio_info_t widget_info); -extern vertex_hdl_t pciio_info_dev_get(pciio_info_t pciio_info); -extern pciio_bus_t pciio_info_bus_get(pciio_info_t pciio_info); -extern pciio_slot_t pciio_info_slot_get(pciio_info_t pciio_info); -extern pciio_function_t pciio_info_function_get(pciio_info_t pciio_info); -extern pciio_vendor_id_t pciio_info_vendor_id_get(pciio_info_t pciio_info); -extern pciio_device_id_t pciio_info_device_id_get(pciio_info_t pciio_info); -extern vertex_hdl_t pciio_info_master_get(pciio_info_t pciio_info); -extern arbitrary_info_t pciio_info_mfast_get(pciio_info_t pciio_info); -extern pciio_provider_t *pciio_info_pops_get(pciio_info_t pciio_info); -extern error_handler_f *pciio_info_efunc_get(pciio_info_t); -extern error_handler_arg_t *pciio_info_einfo_get(pciio_info_t); -extern pciio_space_t pciio_info_bar_space_get(pciio_info_t, int); -extern iopaddr_t pciio_info_bar_base_get(pciio_info_t, int); -extern size_t pciio_info_bar_size_get(pciio_info_t, int); -extern iopaddr_t pciio_info_rom_base_get(pciio_info_t); -extern size_t pciio_info_rom_size_get(pciio_info_t); -extern int pciio_info_type1_get(pciio_info_t); -extern int pciio_error_handler(vertex_hdl_t, int, ioerror_mode_t, ioerror_t *); - -/** - * sn_pci_set_vchan - Set the requested Virtual Channel bits into the mapped DMA - * address. - * @pci_dev: pci device pointer - * @addr: mapped dma address - * @vchan: Virtual Channel to use 0 or 1. - * - * Set the Virtual Channel bit in the mapped dma address. - */ - -static inline int -sn_pci_set_vchan(struct pci_dev *pci_dev, - dma_addr_t *addr, - int vchan) -{ - if (vchan > 1) { - return -1; - } - - if (!(*addr >> 32)) /* Using a mask here would be cleaner */ - return 0; /* but this generates better code */ - - if (vchan == 1) { - /* Set Bit 57 */ - *addr |= (1UL << 57); - } else { - /* Clear Bit 57 */ - *addr &= ~(1UL << 57); - } - - return 0; -} - -#endif /* C or C++ */ - - -/* - * Prototypes - */ - -int snia_badaddr_val(volatile void *addr, int len, volatile void *ptr); -nasid_t snia_get_console_nasid(void); -nasid_t snia_get_master_baseio_nasid(void); -#endif /* _ASM_IA64_SN_PCI_PCIIO_H */ diff --git a/include/asm-ia64/sn/pci/pciio_private.h b/include/asm-ia64/sn/pci/pciio_private.h deleted file mode 100644 index 862015890dc6..000000000000 --- a/include/asm-ia64/sn/pci/pciio_private.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_PCI_PCIIO_PRIVATE_H -#define _ASM_IA64_SN_PCI_PCIIO_PRIVATE_H - -#include <asm/sn/pci/pciio.h> -#include <asm/sn/pci/pci_defs.h> - -/* - * pciio_private.h -- private definitions for pciio - * PCI drivers should NOT include this file. - */ - -/* - * All PCI providers set up PIO using this information. - */ -struct pciio_piomap_s { - unsigned int pp_flags; /* PCIIO_PIOMAP flags */ - vertex_hdl_t pp_dev; /* associated pci card */ - pciio_slot_t pp_slot; /* which slot the card is in */ - pciio_space_t pp_space; /* which address space */ - iopaddr_t pp_pciaddr; /* starting offset of mapping */ - size_t pp_mapsz; /* size of this mapping */ - caddr_t pp_kvaddr; /* kernel virtual address to use */ -}; - -/* - * All PCI providers set up DMA using this information. - */ -struct pciio_dmamap_s { - unsigned int pd_flags; /* PCIIO_DMAMAP flags */ - vertex_hdl_t pd_dev; /* associated pci card */ - pciio_slot_t pd_slot; /* which slot the card is in */ -}; - -/* - * All PCI providers set up interrupts using this information. - */ - -struct pciio_intr_s { - unsigned int pi_flags; /* PCIIO_INTR flags */ - vertex_hdl_t pi_dev; /* associated pci card */ - device_desc_t pi_dev_desc; /* override device descriptor */ - pciio_intr_line_t pi_lines; /* which interrupt line(s) */ - intr_func_t pi_func; /* handler function (when connected) */ - intr_arg_t pi_arg; /* handler parameter (when connected) */ - cpuid_t pi_mustruncpu; /* Where we must run. */ - int pi_irq; /* IRQ assigned */ - int pi_cpu; /* cpu assigned */ -}; - -/* PCIIO_INTR (pi_flags) flags */ -#define PCIIO_INTR_CONNECTED 1 /* interrupt handler/thread has been connected */ -#define PCIIO_INTR_NOTHREAD 2 /* interrupt handler wants to be called at interrupt level */ - -/* - * Generic PCI bus information - */ -struct pciio_businfo_s { - int bi_multi_master;/* Bus provider supports multiple */ - /* dma masters behind a single slot. */ - /* Needed to work around a thrashing */ - /* issue in SGI Bridge ASIC and */ - /* its derivatives. */ - pciio_asic_type_t bi_asic_type; /* PCI ASIC type */ - pciio_bus_type_t bi_bus_type; /* PCI bus type */ - pciio_bus_speed_t bi_bus_speed; /* PCI bus speed */ -}; - -/* - * Some PCI provider implementations keep track of PCI window Base Address - * Register (BAR) address range assignment via the rmalloc()/rmfree() arena - * management routines. These implementations use the following data - * structure for each allocation address space (e.g. memory, I/O, small - * window, etc.). - * - * The ``page size'' encodes the minimum allocation unit and must be a power - * of 2. The main use of this allocation ``page size'' is to control the - * number of free address ranges that the mapping allocation software will - * need to track. Smaller values will allow more efficient use of the address - * ranges but will result in much larger allocation map structures ... For - * instance, if we want to manage allocations for a 256MB address range, - * choosing a 1MB allocation page size will result in up to 1MB being wasted - * for allocation requests smaller than 1MB. The worst case allocation - * pattern for the allocation software to track would be a pattern of 1MB - * allocated, 1MB free. This results in the need to track up to 128 free - * ranges. - */ -struct pciio_win_map_s { - struct map *wm_map; /* window address map */ - int wm_page_size; /* allocation ``page size'' */ -}; - -/* - * Opaque structure used to keep track of window allocation information. - */ -struct pciio_win_alloc_s { - struct resource *wa_resource; /* window map allocation resource */ - unsigned long wa_base; /* allocation starting page number */ - size_t wa_pages; /* number of pages in allocation */ -}; - -/* - * Each PCI Card has one of these. - */ - -struct pciio_info_s { - char *c_fingerprint; - vertex_hdl_t c_vertex; /* back pointer to vertex */ - vertex_hdl_t c_hostvertex;/* top most device in tree */ - pciio_bus_t c_bus; /* which bus the card is in */ - pciio_slot_t c_slot; /* which slot the card is in */ - pciio_function_t c_func; /* which func (on multi-func cards) */ - pciio_vendor_id_t c_vendor; /* PCI card "vendor" code */ - pciio_device_id_t c_device; /* PCI card "device" code */ - vertex_hdl_t c_master; /* PCI bus provider */ - arbitrary_info_t c_mfast; /* cached fastinfo from c_master */ - pciio_provider_t *c_pops; /* cached provider from c_master */ - error_handler_f *c_efunc; /* error handling function */ - error_handler_arg_t c_einfo; /* first parameter for efunc */ - - struct pciio_win_info_s { /* state of BASE regs */ - pciio_space_t w_space; - char w_code; /* low 4 bits of MEM BAR */ - /* low 2 bits of IO BAR */ - iopaddr_t w_base; - size_t w_size; - int w_devio_index; /* DevIO[] register used to - access this window */ - struct pciio_win_alloc_s w_win_alloc; /* window allocation cookie */ - } c_window[PCI_CFG_BASE_ADDRS + 1]; -#define c_rwindow c_window[PCI_CFG_BASE_ADDRS] /* EXPANSION ROM window */ -#define c_rbase c_rwindow.w_base /* EXPANSION ROM base addr */ -#define c_rsize c_rwindow.w_size /* EXPANSION ROM size (bytes) */ - pciio_piospace_t c_piospace; /* additional I/O spaces allocated */ - int c_type1; /* use type1 addressing */ -}; - -extern char pciio_info_fingerprint[]; -#endif /* _ASM_IA64_SN_PCI_PCIIO_PRIVATE_H */ diff --git a/include/asm-ia64/sn/pci/pic.h b/include/asm-ia64/sn/pci/pic.h deleted file mode 100644 index 143534986ea3..000000000000 --- a/include/asm-ia64/sn/pci/pic.h +++ /dev/null @@ -1,451 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_PCI_PIC_H -#define _ASM_IA64_SN_PCI_PIC_H - -/* - * PIC AS DEVICE ZERO - * ------------------ - * - * PIC handles PCI/X busses. PCI/X requires that the 'bridge' (i.e. PIC) - * be designated as 'device 0'. That is a departure from earlier SGI - * PCI bridges. Because of that we use config space 1 to access the - * config space of the first actual PCI device on the bus. - * Here's what the PIC manual says: - * - * The current PCI-X bus specification now defines that the parent - * hosts bus bridge (PIC for example) must be device 0 on bus 0. PIC - * reduced the total number of devices from 8 to 4 and removed the - * device registers and windows, now only supporting devices 0,1,2, and - * 3. PIC did leave all 8 configuration space windows. The reason was - * there was nothing to gain by removing them. Here in lies the problem. - * The device numbering we do using 0 through 3 is unrelated to the device - * numbering which PCI-X requires in configuration space. In the past we - * correlated Configs pace and our device space 0 <-> 0, 1 <-> 1, etc. - * PCI-X requires we start a 1, not 0 and currently the PX brick - * does associate our: - * - * device 0 with configuration space window 1, - * device 1 with configuration space window 2, - * device 2 with configuration space window 3, - * device 3 with configuration space window 4. - * - * The net effect is that all config space access are off-by-one with - * relation to other per-slot accesses on the PIC. - * Here is a table that shows some of that: - * - * Internal Slot# - * | - * | 0 1 2 3 - * ----------|--------------------------------------- - * config | 0x21000 0x22000 0x23000 0x24000 - * | - * even rrb | 0[0] n/a 1[0] n/a [] == implied even/odd - * | - * odd rrb | n/a 0[1] n/a 1[1] - * | - * int dev | 00 01 10 11 - * | - * ext slot# | 1 2 3 4 - * ----------|--------------------------------------- - */ - - -#ifdef __KERNEL__ -#include <linux/types.h> -#include <asm/sn/xtalk/xwidget.h> /* generic widget header */ -#else -#include <xtalk/xwidget.h> -#endif - -#include <asm/sn/pci/pciio.h> - - -/* - * bus provider function table - * - * Normally, this table is only handed off explicitly - * during provider initialization, and the PCI generic - * layer will stash a pointer to it in the vertex; however, - * exporting it explicitly enables a performance hack in - * the generic PCI provider where if we know at compile - * time that the only possible PCI provider is a - * pcibr, we can go directly to this ops table. - */ - -extern pciio_provider_t pci_pic_provider; - - -/* - * misc defines - * - */ - -#define PIC_WIDGET_PART_NUM_BUS0 0xd102 -#define PIC_WIDGET_PART_NUM_BUS1 0xd112 -#define PIC_WIDGET_MFGR_NUM 0x24 -#define PIC_WIDGET_REV_A 0x1 -#define PIC_WIDGET_REV_B 0x2 -#define PIC_WIDGET_REV_C 0x3 - -#define PIC_XTALK_ADDR_MASK 0x0000FFFFFFFFFFFF -#define PIC_INTERNAL_ATES 1024 - - -#define IS_PIC_PART_REV_A(rev) \ - ((rev == (PIC_WIDGET_PART_NUM_BUS0 << 4 | PIC_WIDGET_REV_A)) || \ - (rev == (PIC_WIDGET_PART_NUM_BUS1 << 4 | PIC_WIDGET_REV_A))) -#define IS_PIC_PART_REV_B(rev) \ - ((rev == (PIC_WIDGET_PART_NUM_BUS0 << 4 | PIC_WIDGET_REV_B)) || \ - (rev == (PIC_WIDGET_PART_NUM_BUS1 << 4 | PIC_WIDGET_REV_B))) -#define IS_PIC_PART_REV_C(rev) \ - ((rev == (PIC_WIDGET_PART_NUM_BUS0 << 4 | PIC_WIDGET_REV_C)) || \ - (rev == (PIC_WIDGET_PART_NUM_BUS1 << 4 | PIC_WIDGET_REV_C))) - - -/* - * misc typedefs - * - */ -typedef uint64_t picreg_t; -typedef uint64_t picate_t; - -/* - * PIC Bridge MMR defines - */ - -/* - * PIC STATUS register offset 0x00000008 - */ - -#define PIC_STAT_PCIX_ACTIVE_SHFT 33 - -/* - * PIC CONTROL register offset 0x00000020 - */ - -#define PIC_CTRL_PCI_SPEED_SHFT 4 -#define PIC_CTRL_PCI_SPEED (0x3 << PIC_CTRL_PCI_SPEED_SHFT) -#define PIC_CTRL_PAGE_SIZE_SHFT 21 -#define PIC_CTRL_PAGE_SIZE (0x1 << PIC_CTRL_PAGE_SIZE_SHFT) - - -/* - * PIC Intr Destination Addr offset 0x00000038 - */ - -#define PIC_INTR_DEST_ADDR 0x0000FFFFFFFFFFFF -#define PIC_INTR_DEST_TID_SHFT 48 -#define PIC_INTR_DEST_TID (0xFull << PIC_INTR_DEST_TID_SHFT) - -/* - * PIC PCI Responce Buffer offset 0x00000068 - */ -#define PIC_RSP_BUF_ADDR 0x0000FFFFFFFFFFFF -#define PIC_RSP_BUF_NUM_SHFT 48 -#define PIC_RSP_BUF_NUM (0xFull << PIC_RSP_BUF_NUM_SHFT) -#define PIC_RSP_BUF_DEV_NUM_SHFT 52 -#define PIC_RSP_BUF_DEV_NUM (0x3ull << PIC_RSP_BUF_DEV_NUM_SHFT) - -/* - * PIC PCI DIRECT MAP register offset 0x00000080 - */ -#define PIC_DIRMAP_DIROFF_SHFT 0 -#define PIC_DIRMAP_DIROFF (0x1FFFF << PIC_DIRMAP_DIROFF_SHFT) -#define PIC_DIRMAP_ADD512_SHFT 17 -#define PIC_DIRMAP_ADD512 (0x1 << PIC_DIRMAP_ADD512_SHFT) -#define PIC_DIRMAP_WID_SHFT 20 -#define PIC_DIRMAP_WID (0xF << PIC_DIRMAP_WID_SHFT) - -#define PIC_DIRMAP_OFF_ADDRSHFT 31 - -/* - * Interrupt Status register offset 0x00000100 - */ -#define PIC_ISR_PCIX_SPLIT_MSG_PE (0x1ull << 45) -#define PIC_ISR_PCIX_SPLIT_EMSG (0x1ull << 44) -#define PIC_ISR_PCIX_SPLIT_TO (0x1ull << 43) -#define PIC_ISR_PCIX_UNEX_COMP (0x1ull << 42) -#define PIC_ISR_INT_RAM_PERR (0x1ull << 41) -#define PIC_ISR_PCIX_ARB_ERR (0x1ull << 40) -#define PIC_ISR_PCIX_REQ_TOUT (0x1ull << 39) -#define PIC_ISR_PCIX_TABORT (0x1ull << 38) -#define PIC_ISR_PCIX_PERR (0x1ull << 37) -#define PIC_ISR_PCIX_SERR (0x1ull << 36) -#define PIC_ISR_PCIX_MRETRY (0x1ull << 35) -#define PIC_ISR_PCIX_MTOUT (0x1ull << 34) -#define PIC_ISR_PCIX_DA_PARITY (0x1ull << 33) -#define PIC_ISR_PCIX_AD_PARITY (0x1ull << 32) -#define PIC_ISR_PMU_PAGE_FAULT (0x1ull << 30) -#define PIC_ISR_UNEXP_RESP (0x1ull << 29) -#define PIC_ISR_BAD_XRESP_PKT (0x1ull << 28) -#define PIC_ISR_BAD_XREQ_PKT (0x1ull << 27) -#define PIC_ISR_RESP_XTLK_ERR (0x1ull << 26) -#define PIC_ISR_REQ_XTLK_ERR (0x1ull << 25) -#define PIC_ISR_INVLD_ADDR (0x1ull << 24) -#define PIC_ISR_UNSUPPORTED_XOP (0x1ull << 23) -#define PIC_ISR_XREQ_FIFO_OFLOW (0x1ull << 22) -#define PIC_ISR_LLP_REC_SNERR (0x1ull << 21) -#define PIC_ISR_LLP_REC_CBERR (0x1ull << 20) -#define PIC_ISR_LLP_RCTY (0x1ull << 19) -#define PIC_ISR_LLP_TX_RETRY (0x1ull << 18) -#define PIC_ISR_LLP_TCTY (0x1ull << 17) -#define PIC_ISR_PCI_ABORT (0x1ull << 15) -#define PIC_ISR_PCI_PARITY (0x1ull << 14) -#define PIC_ISR_PCI_SERR (0x1ull << 13) -#define PIC_ISR_PCI_PERR (0x1ull << 12) -#define PIC_ISR_PCI_MST_TIMEOUT (0x1ull << 11) -#define PIC_ISR_PCI_RETRY_CNT (0x1ull << 10) -#define PIC_ISR_XREAD_REQ_TIMEOUT (0x1ull << 9) -#define PIC_ISR_INT_MSK (0xffull << 0) -#define PIC_ISR_INT(x) (0x1ull << (x)) - -#define PIC_ISR_LINK_ERROR \ - (PIC_ISR_LLP_REC_SNERR|PIC_ISR_LLP_REC_CBERR| \ - PIC_ISR_LLP_RCTY|PIC_ISR_LLP_TX_RETRY| \ - PIC_ISR_LLP_TCTY) - -#define PIC_ISR_PCIBUS_PIOERR \ - (PIC_ISR_PCI_MST_TIMEOUT|PIC_ISR_PCI_ABORT| \ - PIC_ISR_PCIX_MTOUT|PIC_ISR_PCIX_TABORT) - -#define PIC_ISR_PCIBUS_ERROR \ - (PIC_ISR_PCIBUS_PIOERR|PIC_ISR_PCI_PERR| \ - PIC_ISR_PCI_SERR|PIC_ISR_PCI_RETRY_CNT| \ - PIC_ISR_PCI_PARITY|PIC_ISR_PCIX_PERR| \ - PIC_ISR_PCIX_SERR|PIC_ISR_PCIX_MRETRY| \ - PIC_ISR_PCIX_AD_PARITY|PIC_ISR_PCIX_DA_PARITY| \ - PIC_ISR_PCIX_REQ_TOUT|PIC_ISR_PCIX_UNEX_COMP| \ - PIC_ISR_PCIX_SPLIT_TO|PIC_ISR_PCIX_SPLIT_EMSG| \ - PIC_ISR_PCIX_SPLIT_MSG_PE) - -#define PIC_ISR_XTALK_ERROR \ - (PIC_ISR_XREAD_REQ_TIMEOUT|PIC_ISR_XREQ_FIFO_OFLOW| \ - PIC_ISR_UNSUPPORTED_XOP|PIC_ISR_INVLD_ADDR| \ - PIC_ISR_REQ_XTLK_ERR|PIC_ISR_RESP_XTLK_ERR| \ - PIC_ISR_BAD_XREQ_PKT|PIC_ISR_BAD_XRESP_PKT| \ - PIC_ISR_UNEXP_RESP) - -#define PIC_ISR_ERRORS \ - (PIC_ISR_LINK_ERROR|PIC_ISR_PCIBUS_ERROR| \ - PIC_ISR_XTALK_ERROR| \ - PIC_ISR_PMU_PAGE_FAULT|PIC_ISR_INT_RAM_PERR) - -/* - * PIC RESET INTR register offset 0x00000110 - */ - -#define PIC_IRR_ALL_CLR 0xffffffffffffffff - -/* - * PIC PCI Host Intr Addr offset 0x00000130 - 0x00000168 - */ -#define PIC_HOST_INTR_ADDR 0x0000FFFFFFFFFFFF -#define PIC_HOST_INTR_FLD_SHFT 48 -#define PIC_HOST_INTR_FLD (0xFFull << PIC_HOST_INTR_FLD_SHFT) - - -/* - * PIC MMR structure mapping - */ - -/* NOTE: PIC WAR. PV#854697. PIC does not allow writes just to [31:0] - * of a 64-bit register. When writing PIC registers, always write the - * entire 64 bits. - */ - -typedef volatile struct pic_s { - - /* 0x000000-0x00FFFF -- Local Registers */ - - /* 0x000000-0x000057 -- Standard Widget Configuration */ - picreg_t p_wid_id; /* 0x000000 */ - picreg_t p_wid_stat; /* 0x000008 */ - picreg_t p_wid_err_upper; /* 0x000010 */ - picreg_t p_wid_err_lower; /* 0x000018 */ - #define p_wid_err p_wid_err_lower - picreg_t p_wid_control; /* 0x000020 */ - picreg_t p_wid_req_timeout; /* 0x000028 */ - picreg_t p_wid_int_upper; /* 0x000030 */ - picreg_t p_wid_int_lower; /* 0x000038 */ - #define p_wid_int p_wid_int_lower - picreg_t p_wid_err_cmdword; /* 0x000040 */ - picreg_t p_wid_llp; /* 0x000048 */ - picreg_t p_wid_tflush; /* 0x000050 */ - - /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */ - picreg_t p_wid_aux_err; /* 0x000058 */ - picreg_t p_wid_resp_upper; /* 0x000060 */ - picreg_t p_wid_resp_lower; /* 0x000068 */ - #define p_wid_resp p_wid_resp_lower - picreg_t p_wid_tst_pin_ctrl; /* 0x000070 */ - picreg_t p_wid_addr_lkerr; /* 0x000078 */ - - /* 0x000080-0x00008F -- PMU & MAP */ - picreg_t p_dir_map; /* 0x000080 */ - picreg_t _pad_000088; /* 0x000088 */ - - /* 0x000090-0x00009F -- SSRAM */ - picreg_t p_map_fault; /* 0x000090 */ - picreg_t _pad_000098; /* 0x000098 */ - - /* 0x0000A0-0x0000AF -- Arbitration */ - picreg_t p_arb; /* 0x0000A0 */ - picreg_t _pad_0000A8; /* 0x0000A8 */ - - /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */ - picreg_t p_ate_parity_err; /* 0x0000B0 */ - picreg_t _pad_0000B8; /* 0x0000B8 */ - - /* 0x0000C0-0x0000FF -- PCI/GIO */ - picreg_t p_bus_timeout; /* 0x0000C0 */ - picreg_t p_pci_cfg; /* 0x0000C8 */ - picreg_t p_pci_err_upper; /* 0x0000D0 */ - picreg_t p_pci_err_lower; /* 0x0000D8 */ - #define p_pci_err p_pci_err_lower - picreg_t _pad_0000E0[4]; /* 0x0000{E0..F8} */ - - /* 0x000100-0x0001FF -- Interrupt */ - picreg_t p_int_status; /* 0x000100 */ - picreg_t p_int_enable; /* 0x000108 */ - picreg_t p_int_rst_stat; /* 0x000110 */ - picreg_t p_int_mode; /* 0x000118 */ - picreg_t p_int_device; /* 0x000120 */ - picreg_t p_int_host_err; /* 0x000128 */ - picreg_t p_int_addr[8]; /* 0x0001{30,,,68} */ - picreg_t p_err_int_view; /* 0x000170 */ - picreg_t p_mult_int; /* 0x000178 */ - picreg_t p_force_always[8]; /* 0x0001{80,,,B8} */ - picreg_t p_force_pin[8]; /* 0x0001{C0,,,F8} */ - - /* 0x000200-0x000298 -- Device */ - picreg_t p_device[4]; /* 0x0002{00,,,18} */ - picreg_t _pad_000220[4]; /* 0x0002{20,,,38} */ - picreg_t p_wr_req_buf[4]; /* 0x0002{40,,,58} */ - picreg_t _pad_000260[4]; /* 0x0002{60,,,78} */ - picreg_t p_rrb_map[2]; /* 0x0002{80,,,88} */ - #define p_even_resp p_rrb_map[0] /* 0x000280 */ - #define p_odd_resp p_rrb_map[1] /* 0x000288 */ - picreg_t p_resp_status; /* 0x000290 */ - picreg_t p_resp_clear; /* 0x000298 */ - - picreg_t _pad_0002A0[12]; /* 0x0002{A0..F8} */ - - /* 0x000300-0x0003F8 -- Buffer Address Match Registers */ - struct { - picreg_t upper; /* 0x0003{00,,,F0} */ - picreg_t lower; /* 0x0003{08,,,F8} */ - } p_buf_addr_match[16]; - - /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */ - struct { - picreg_t flush_w_touch; /* 0x000{400,,,5C0} */ - picreg_t flush_wo_touch; /* 0x000{408,,,5C8} */ - picreg_t inflight; /* 0x000{410,,,5D0} */ - picreg_t prefetch; /* 0x000{418,,,5D8} */ - picreg_t total_pci_retry; /* 0x000{420,,,5E0} */ - picreg_t max_pci_retry; /* 0x000{428,,,5E8} */ - picreg_t max_latency; /* 0x000{430,,,5F0} */ - picreg_t clear_all; /* 0x000{438,,,5F8} */ - } p_buf_count[8]; - - - /* 0x000600-0x0009FF -- PCI/X registers */ - picreg_t p_pcix_bus_err_addr; /* 0x000600 */ - picreg_t p_pcix_bus_err_attr; /* 0x000608 */ - picreg_t p_pcix_bus_err_data; /* 0x000610 */ - picreg_t p_pcix_pio_split_addr; /* 0x000618 */ - picreg_t p_pcix_pio_split_attr; /* 0x000620 */ - picreg_t p_pcix_dma_req_err_attr; /* 0x000628 */ - picreg_t p_pcix_dma_req_err_addr; /* 0x000630 */ - picreg_t p_pcix_timeout; /* 0x000638 */ - - picreg_t _pad_000640[120]; /* 0x000{640,,,9F8} */ - - /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */ - struct { - picreg_t p_buf_addr; /* 0x000{A00,,,AF0} */ - picreg_t p_buf_attr; /* 0X000{A08,,,AF8} */ - } p_pcix_read_buf_64[16]; - - struct { - picreg_t p_buf_addr; /* 0x000{B00,,,BE0} */ - picreg_t p_buf_attr; /* 0x000{B08,,,BE8} */ - picreg_t p_buf_valid; /* 0x000{B10,,,BF0} */ - picreg_t __pad1; /* 0x000{B18,,,BF8} */ - } p_pcix_write_buf_64[8]; - - /* End of Local Registers -- Start of Address Map space */ - - char _pad_000c00[0x010000 - 0x000c00]; - - /* 0x010000-0x011fff -- Internal ATE RAM (Auto Parity Generation) */ - picate_t p_int_ate_ram[1024]; /* 0x010000-0x011fff */ - - /* 0x012000-0x013fff -- Internal ATE RAM (Manual Parity Generation) */ - picate_t p_int_ate_ram_mp[1024]; /* 0x012000-0x013fff */ - - char _pad_014000[0x18000 - 0x014000]; - - /* 0x18000-0x197F8 -- PIC Write Request Ram */ - picreg_t p_wr_req_lower[256]; /* 0x18000 - 0x187F8 */ - picreg_t p_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */ - picreg_t p_wr_req_parity[256]; /* 0x19000 - 0x197F8 */ - - char _pad_019800[0x20000 - 0x019800]; - - /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */ - union { - uint8_t c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */ - uint16_t s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */ - uint32_t l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */ - uint64_t d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */ - union { - uint8_t c[0x100 / 1]; - uint16_t s[0x100 / 2]; - uint32_t l[0x100 / 4]; - uint64_t d[0x100 / 8]; - } f[8]; - } p_type0_cfg_dev[8]; /* 0x02{0000,,,7FFF} */ - - /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */ - union { - uint8_t c[0x1000 / 1]; /* 0x028000-0x029000 */ - uint16_t s[0x1000 / 2]; /* 0x028000-0x029000 */ - uint32_t l[0x1000 / 4]; /* 0x028000-0x029000 */ - uint64_t d[0x1000 / 8]; /* 0x028000-0x029000 */ - union { - uint8_t c[0x100 / 1]; - uint16_t s[0x100 / 2]; - uint32_t l[0x100 / 4]; - uint64_t d[0x100 / 8]; - } f[8]; - } p_type1_cfg; /* 0x028000-0x029000 */ - - char _pad_029000[0x030000-0x029000]; - - /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */ - union { - uint8_t c[8 / 1]; - uint16_t s[8 / 2]; - uint32_t l[8 / 4]; - uint64_t d[8 / 8]; - } p_pci_iack; /* 0x030000-0x030007 */ - - char _pad_030007[0x040000-0x030008]; - - /* 0x040000-0x030007 -- PCIX Special Cycle */ - union { - uint8_t c[8 / 1]; - uint16_t s[8 / 2]; - uint32_t l[8 / 4]; - uint64_t d[8 / 8]; - } p_pcix_cycle; /* 0x040000-0x040007 */ -} pic_t; - -#endif /* _ASM_IA64_SN_PCI_PIC_H */ diff --git a/include/asm-ia64/sn/pda.h b/include/asm-ia64/sn/pda.h index fa472c3f983e..9e61db871c67 100644 --- a/include/asm-ia64/sn/pda.h +++ b/include/asm-ia64/sn/pda.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_PDA_H #define _ASM_IA64_SN_PDA_H @@ -49,13 +49,14 @@ typedef struct pda_s { volatile unsigned long *pio_shub_war_cam_addr; volatile unsigned long *mem_write_status_addr; + struct bteinfo_s *cpu_bte_if[BTES_PER_NODE]; /* cpu interface order */ + unsigned long sn_soft_irr[4]; unsigned long sn_in_service_ivecs[4]; short cnodeid_to_nasid_table[MAX_NUMNODES]; int sn_lb_int_war_ticks; int sn_last_irq; int sn_first_irq; - int sn_num_irqs; /* number of irqs targeted for this cpu */ } pda_t; diff --git a/include/asm-ia64/sn/pio.h b/include/asm-ia64/sn/pio.h deleted file mode 100644 index da74b96905f4..000000000000 --- a/include/asm-ia64/sn/pio.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_PIO_H -#define _ASM_IA64_SN_PIO_H - -#include <asm/sn/types.h> - -/* - * pioaddr_t - The kernel virtual address that a PIO can be done upon. - * Should probably be (volatile void*) but EVEREST would do PIO - * to long mostly, just cast for other sizes. - */ - -typedef volatile unsigned long* pioaddr_t; - -/* - * iopaddr_t - the physical io space relative address (e.g. VME A16S 0x0800). - * iosapce_t - specifies the io address space to be mapped/accessed. - * piomap_t - the handle returned by pio_alloc() and used with all the pio - * access functions. - */ - - -typedef struct piomap { - unsigned int pio_bus; - unsigned int pio_adap; - int pio_flag; - int pio_reg; - char pio_name[7]; /* to identify the mapped device */ - struct piomap *pio_next; /* dlist to link active piomap's */ - struct piomap *pio_prev; /* for debug and error reporting */ - iopaddr_t pio_iopmask; /* valid iop address bit mask */ - iobush_t pio_bushandle; /* bus-level handle */ -} piomap_t; - -#define pio_type pio_iospace.ios_type -#define pio_iopaddr pio_iospace.ios_iopaddr -#define pio_size pio_iospace.ios_size -#define pio_vaddr pio_iospace.ios_vaddr - -/* Macro to get/set PIO error function */ -#define pio_seterrf(p,f) (p)->pio_errfunc = (f) -#define pio_geterrf(p) (p)->pio_errfunc - - -/* - * piomap_t type defines - */ - -#define PIOMAP_NTYPES 7 - -#define PIOMAP_A16N VME_A16NP -#define PIOMAP_A16S VME_A16S -#define PIOMAP_A24N VME_A24NP -#define PIOMAP_A24S VME_A24S -#define PIOMAP_A32N VME_A32NP -#define PIOMAP_A32S VME_A32S -#define PIOMAP_A64 6 - -#define PIOMAP_EISA_IO 0 -#define PIOMAP_EISA_MEM 1 - -#define PIOMAP_PCI_IO 0 -#define PIOMAP_PCI_MEM 1 -#define PIOMAP_PCI_CFG 2 -#define PIOMAP_PCI_ID 3 - -/* IBUS piomap types */ -#define PIOMAP_FCI 0 - -/* dang gio piomap types */ - -#define PIOMAP_GIO32 0 -#define PIOMAP_GIO64 1 - -#define ET_MEM 0 -#define ET_IO 1 -#define LAN_RAM 2 -#define LAN_IO 3 - -#define PIOREG_NULL (-1) - -/* standard flags values for pio_map routines, - * including {xtalk,pciio}_piomap calls. - * NOTE: try to keep these in step with DMAMAP flags. - */ -#define PIOMAP_UNFIXED 0x0 -#define PIOMAP_FIXED 0x1 -#define PIOMAP_NOSLEEP 0x2 -#define PIOMAP_INPLACE 0x4 - -#define PIOMAP_FLAGS 0x7 - -#endif /* _ASM_IA64_SN_PIO_H */ diff --git a/include/asm-ia64/sn/prio.h b/include/asm-ia64/sn/prio.h deleted file mode 100644 index 5df6a582b226..000000000000 --- a/include/asm-ia64/sn/prio.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_PRIO_H -#define _ASM_IA64_SN_PRIO_H - -#include <linux/types.h> - -/* - * Priority I/O function prototypes and macro definitions - */ - -typedef long long bandwidth_t; - -/* These should be the same as FREAD/FWRITE */ -#define PRIO_READ_ALLOCATE 0x1 -#define PRIO_WRITE_ALLOCATE 0x2 -#define PRIO_READWRITE_ALLOCATE (PRIO_READ_ALLOCATE | PRIO_WRITE_ALLOCATE) - -extern int prioSetBandwidth (int /* fd */, - int /* alloc_type */, - bandwidth_t /* bytes_per_sec */, - pid_t * /* pid */); -extern int prioGetBandwidth (int /* fd */, - bandwidth_t * /* read_bw */, - bandwidth_t * /* write_bw */); -extern int prioLock (pid_t *); -extern int prioUnlock (void); - -/* Error returns */ -#define PRIO_SUCCESS 0 -#define PRIO_FAIL (-1) - -#endif /* _ASM_IA64_SN_PRIO_H */ diff --git a/include/asm-ia64/sn/router.h b/include/asm-ia64/sn/router.h index 54667373d416..a28b36409b67 100644 --- a/include/asm-ia64/sn/router.h +++ b/include/asm-ia64/sn/router.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_ROUTER_H @@ -17,10 +17,7 @@ #ifndef __ASSEMBLY__ -#include <asm/sn/vector.h> -#include <asm/sn/slotnum.h> #include <asm/sn/arch.h> -#include <asm/sn/sgi.h> typedef uint64_t router_reg_t; @@ -411,7 +408,7 @@ typedef signed char port_no_t; /* Type for router port number */ typedef struct router_map_ent_s { uint64_t nic; moduleid_t module; - slotid_t slot; + char slot; } router_map_ent_t; struct rr_status_error_fmt { @@ -479,16 +476,16 @@ typedef struct router_info_s { char ri_leds; /* Current LED bitmap */ char ri_portmask; /* Active port bitmap */ router_reg_t ri_stat_rev_id; /* Status rev ID value */ - net_vec_t ri_vector; /* vector from guardian to router */ + uint64_t ri_vector; /* vector from guardian to router */ int ri_writeid; /* router's vector write ID */ int64_t ri_timebase; /* Time of first sample */ int64_t ri_timestamp; /* Time of last sample */ router_port_info_t ri_port[MAX_ROUTER_PORTS]; /* per port info */ moduleid_t ri_module; /* Which module are we in? */ - slotid_t ri_slotnum; /* Which slot are we in? */ + char ri_slotnum; /* Which slot are we in? */ router_reg_t ri_glbl_parms[GLBL_PARMS_REGS]; /* Global parms0&1 register contents*/ - vertex_hdl_t ri_vertex; /* hardware graph vertex */ + void * ri_vertex; /* hardware graph vertex */ router_reg_t ri_prot_conf; /* protection config. register */ int64_t ri_per_minute; /* Ticks per minute */ @@ -500,7 +497,7 @@ typedef struct router_info_s { * the bottom of the structure, below the user stuff. */ char ri_hist_type; /* histogram type */ - vertex_hdl_t ri_guardian; /* guardian node for the router */ + void * ri_guardian; /* guardian node for the router */ int64_t ri_last_print; /* When did we last print */ char ri_print; /* Should we print */ char ri_just_blink; /* Should we blink the LEDs */ @@ -509,7 +506,7 @@ typedef struct router_info_s { int64_t ri_deltatime; /* Time it took to sample */ #endif spinlock_t ri_lock; /* Lock for access to router info */ - net_vec_t *ri_vecarray; /* Pointer to array of vectors */ + uint64_t *ri_vecarray; /* Pointer to array of vectors */ struct lboard_s *ri_brd; /* Pointer to board structure */ char * ri_name; /* This board's hwg path */ unsigned char ri_port_maint[MAX_ROUTER_PORTS]; /* should we send a @@ -526,13 +523,13 @@ typedef struct router_info_s { * Router info hanging in the nodepda */ typedef struct nodepda_router_info_s { - vertex_hdl_t router_vhdl; /* vertex handle of the router */ + void * router_vhdl; /* vertex handle of the router */ short router_port; /* port thru which we entered */ short router_portmask; moduleid_t router_module; /* module in which router is there */ - slotid_t router_slot; /* router slot */ + char router_slot; /* router slot */ unsigned char router_type; /* kind of router */ - net_vec_t router_vector; /* vector from the guardian node */ + uint64_t router_vector; /* vector from the guardian node */ router_info_t *router_infop; /* info hanging off the hwg vertex */ struct nodepda_router_info_s *router_next; @@ -560,7 +557,7 @@ typedef struct router_elt_s { /* vector route from the master hub to * this router. */ - net_vec_t vec; + uint64_t vec; /* port status */ uint64_t status; char port_status[MAX_ROUTER_PORTS + 1]; @@ -570,11 +567,11 @@ typedef struct router_elt_s { */ struct { /* vertex handle for the router */ - vertex_hdl_t vhdl; + void * vhdl; /* guardian for this router */ - vertex_hdl_t guard; + void * guard; /* vector router from the guardian to the router */ - net_vec_t vec; + uint64_t vec; } k_elt; } u; /* easy to use port status interpretation */ @@ -618,24 +615,4 @@ typedef struct router_queue_s { #define RTABLE_SHFT(_L) (4 * ((_L) - 1)) #define RTABLE_MASK(_L) (0x7UL << RTABLE_SHFT(_L)) - -#define ROUTERINFO_STKSZ 4096 - -#ifndef __ASSEMBLY__ - -int router_reg_read(router_info_t *rip, int regno, router_reg_t *val); -int router_reg_write(router_info_t *rip, int regno, router_reg_t val); -int router_get_info(vertex_hdl_t routerv, router_info_t *, int); -int router_set_leds(router_info_t *rip); -void router_print_state(router_info_t *rip, int level, - void (*pf)(int, char *, ...),int print_where); -void capture_router_stats(router_info_t *rip); - - -int probe_routers(void); -void get_routername(unsigned char brd_type,char *rtrname); -void router_guardians_set(vertex_hdl_t hwgraph_root); -int router_hist_reselect(router_info_t *, int64_t); -#endif /* __ASSEMBLY__ */ - #endif /* _ASM_IA64_SN_ROUTER_H */ diff --git a/include/asm-ia64/sn/rw_mmr.h b/include/asm-ia64/sn/rw_mmr.h index 14309d4d88f3..f366bb5dcec2 100644 --- a/include/asm-ia64/sn/rw_mmr.h +++ b/include/asm-ia64/sn/rw_mmr.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2002-2003 Silicon Graphics, Inc. All Rights Reserved. + * Copyright (C) 2002-2004 Silicon Graphics, Inc. All Rights Reserved. */ #ifndef _ASM_IA64_SN_RW_MMR_H #define _ASM_IA64_SN_RW_MMR_H diff --git a/include/asm-ia64/sn/sgi.h b/include/asm-ia64/sn/sgi.h deleted file mode 100644 index 82772610ab6a..000000000000 --- a/include/asm-ia64/sn/sgi.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000-2003 Silicon Graphics, Inc. All rights reserved. - */ - - -#ifndef _ASM_IA64_SN_SGI_H -#define _ASM_IA64_SN_SGI_H - -#include <linux/config.h> - -#include <asm/sn/types.h> -#include <asm/sn/hwgfs.h> - -typedef hwgfs_handle_t vertex_hdl_t; - -/* Nice general name length that lots of people like to use */ -#ifndef MAXDEVNAME -#define MAXDEVNAME 256 -#endif - - -/* - * Possible return values from graph routines. - */ -typedef enum graph_error_e { - GRAPH_SUCCESS, /* 0 */ - GRAPH_DUP, /* 1 */ - GRAPH_NOT_FOUND, /* 2 */ - GRAPH_BAD_PARAM, /* 3 */ - GRAPH_HIT_LIMIT, /* 4 */ - GRAPH_CANNOT_ALLOC, /* 5 */ - GRAPH_ILLEGAL_REQUEST, /* 6 */ - GRAPH_IN_USE /* 7 */ -} graph_error_t; - -#define CNODEID_NONE ((cnodeid_t)-1) -#define CPU_NONE (-1) -#define GRAPH_VERTEX_NONE ((vertex_hdl_t)-1) - -/* - * Defines for individual WARs. Each is a bitmask of applicable - * part revision numbers. (1 << 1) == rev A, (1 << 2) == rev B, - * (3 << 1) == (rev A or rev B), etc - */ -#define PV854697 (~0) /* PIC: write 64bit regs as 64bits. permanent */ -#define PV854827 (~0UL) /* PIC: fake widget 0xf presence bit. permanent */ -#define PV855271 (1 << 1) /* PIC: use virt chan iff 64-bit device. */ -#define PV878674 (~0) /* PIC: Dont allow 64bit PIOs. permanent */ -#define PV855272 (1 << 1) /* PIC: runaway interrupt WAR */ -#define PV856155 (1 << 1) /* PIC: arbitration WAR */ -#define PV856864 (1 << 1) /* PIC: lower timeout to free TNUMs quicker */ -#define PV856866 (1 << 1) /* PIC: avoid rrb's 0/1/8/9. */ -#define PV862253 (1 << 1) /* PIC: don't enable write req RAM parity checking */ -#define PV867308 (3 << 1) /* PIC: make LLP error interrupts FATAL for PIC */ - -/* - * No code is complete without an Assertion macro - */ - -#if defined(DISABLE_ASSERT) -#define ASSERT(expr) -#define ASSERT_ALWAYS(expr) -#else -#define ASSERT(expr) do { \ - if(!(expr)) { \ - printk( "Assertion [%s] failed! %s:%s(line=%d)\n",\ - #expr,__FILE__,__FUNCTION__,__LINE__); \ - panic("Assertion panic\n"); \ - } } while(0) - -#define ASSERT_ALWAYS(expr) do {\ - if(!(expr)) { \ - printk( "Assertion [%s] failed! %s:%s(line=%d)\n",\ - #expr,__FILE__,__FUNCTION__,__LINE__); \ - panic("Assertion always panic\n"); \ - } } while(0) -#endif /* DISABLE_ASSERT */ - -#endif /* _ASM_IA64_SN_SGI_H */ diff --git a/include/asm-ia64/sn/shub_mmr.h b/include/asm-ia64/sn/shub_mmr.h new file mode 100644 index 000000000000..430c50fd1485 --- /dev/null +++ b/include/asm-ia64/sn/shub_mmr.h @@ -0,0 +1,199 @@ +/* + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 2001-2004 Silicon Graphics, Inc. All rights reserved. + */ + +#ifndef _ASM_IA64_SN_SHUB_MMR_H +#define _ASM_IA64_SN_SHUB_MMR_H + +/* ==================================================================== */ +/* Register "SH_IPI_INT" */ +/* SHub Inter-Processor Interrupt Registers */ +/* ==================================================================== */ +#define SH_IPI_INT 0x0000000110000380UL +#define SH_IPI_INT_MASK 0x8ff3ffffffefffffUL +#define SH_IPI_INT_INIT 0x0000000000000000UL + +/* SH_IPI_INT_TYPE */ +/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ +#define SH_IPI_INT_TYPE_SHFT 0 +#define SH_IPI_INT_TYPE_MASK 0x0000000000000007UL + +/* SH_IPI_INT_AGT */ +/* Description: Agent, must be 0 for SHub */ +#define SH_IPI_INT_AGT_SHFT 3 +#define SH_IPI_INT_AGT_MASK 0x0000000000000008UL + +/* SH_IPI_INT_PID */ +/* Description: Processor ID, same setting as on targeted McKinley */ +#define SH_IPI_INT_PID_SHFT 4 +#define SH_IPI_INT_PID_MASK 0x00000000000ffff0UL + +/* SH_IPI_INT_BASE */ +/* Description: Optional interrupt vector area, 2MB aligned */ +#define SH_IPI_INT_BASE_SHFT 21 +#define SH_IPI_INT_BASE_MASK 0x0003ffffffe00000UL + +/* SH_IPI_INT_IDX */ +/* Description: Targeted McKinley interrupt vector */ +#define SH_IPI_INT_IDX_SHFT 52 +#define SH_IPI_INT_IDX_MASK 0x0ff0000000000000UL + +/* SH_IPI_INT_SEND */ +/* Description: Send Interrupt Message to PI, This generates a puls */ +#define SH_IPI_INT_SEND_SHFT 63 +#define SH_IPI_INT_SEND_MASK 0x8000000000000000UL + +/* ==================================================================== */ +/* Register "SH_EVENT_OCCURRED" */ +/* SHub Interrupt Event Occurred */ +/* ==================================================================== */ +#define SH_EVENT_OCCURRED 0x0000000110010000UL +#define SH_EVENT_OCCURRED_ALIAS 0x0000000110010008UL + +/* ==================================================================== */ +/* Register "SH_PI_CAM_CONTROL" */ +/* CRB CAM MMR Access Control */ +/* ==================================================================== */ +#ifndef __ASSEMBLY__ +#define SH_PI_CAM_CONTROL 0x0000000120050300UL +#else +#define SH_PI_CAM_CONTROL 0x0000000120050300 +#endif + +/* ==================================================================== */ +/* Register "SH_SHUB_ID" */ +/* SHub ID Number */ +/* ==================================================================== */ +#define SH_SHUB_ID 0x0000000110060580UL +#define SH_SHUB_ID_REVISION_SHFT 28 +#define SH_SHUB_ID_REVISION_MASK 0x00000000f0000000 + +/* ==================================================================== */ +/* Register "SH_PTC_0" */ +/* Puge Translation Cache Message Configuration Information */ +/* ==================================================================== */ +#define SH_PTC_0 0x00000001101a0000UL +#define SH_PTC_1 0x00000001101a0080UL + +/* ==================================================================== */ +/* Register "SH_RTC" */ +/* Real-time Clock */ +/* ==================================================================== */ +#define SH_RTC 0x00000001101c0000UL +#define SH_RTC_MASK 0x007fffffffffffffUL + +/* ==================================================================== */ +/* Register "SH_MEMORY_WRITE_STATUS_0|1" */ +/* Memory Write Status for CPU 0 & 1 */ +/* ==================================================================== */ +#define SH_MEMORY_WRITE_STATUS_0 0x0000000120070000UL +#define SH_MEMORY_WRITE_STATUS_1 0x0000000120070080UL + +/* ==================================================================== */ +/* Register "SH_PIO_WRITE_STATUS_0|1" */ +/* PIO Write Status for CPU 0 & 1 */ +/* ==================================================================== */ +#ifndef __ASSEMBLY__ +#define SH_PIO_WRITE_STATUS_0 0x0000000120070200UL +#define SH_PIO_WRITE_STATUS_1 0x0000000120070280UL + +/* SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK */ +/* Description: Deadlock response detected */ +#define SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK_SHFT 1 +#define SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK_MASK 0x0000000000000002 + +/* SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT */ +/* Description: Count of currently pending PIO writes */ +#define SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_SHFT 56 +#define SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_MASK 0x3f00000000000000UL +#else +#define SH_PIO_WRITE_STATUS_0 0x0000000120070200 +#define SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_SHFT 56 +#define SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK_SHFT 1 +#endif + +/* ==================================================================== */ +/* Register "SH_PIO_WRITE_STATUS_0_ALIAS" */ +/* ==================================================================== */ +#ifndef __ASSEMBLY__ +#define SH_PIO_WRITE_STATUS_0_ALIAS 0x0000000120070208UL +#else +#define SH_PIO_WRITE_STATUS_0_ALIAS 0x0000000120070208 +#endif + +/* ==================================================================== */ +/* Register "SH_EVENT_OCCURRED" */ +/* SHub Interrupt Event Occurred */ +/* ==================================================================== */ +/* SH_EVENT_OCCURRED_UART_INT */ +/* Description: Pending Junk Bus UART Interrupt */ +#define SH_EVENT_OCCURRED_UART_INT_SHFT 20 +#define SH_EVENT_OCCURRED_UART_INT_MASK 0x0000000000100000 + +/* SH_EVENT_OCCURRED_IPI_INT */ +/* Description: Pending IPI Interrupt */ +#define SH_EVENT_OCCURRED_IPI_INT_SHFT 28 +#define SH_EVENT_OCCURRED_IPI_INT_MASK 0x0000000010000000 + +/* SH_EVENT_OCCURRED_II_INT0 */ +/* Description: Pending II 0 Interrupt */ +#define SH_EVENT_OCCURRED_II_INT0_SHFT 29 +#define SH_EVENT_OCCURRED_II_INT0_MASK 0x0000000020000000 + +/* SH_EVENT_OCCURRED_II_INT1 */ +/* Description: Pending II 1 Interrupt */ +#define SH_EVENT_OCCURRED_II_INT1_SHFT 30 +#define SH_EVENT_OCCURRED_II_INT1_MASK 0x0000000040000000 + +/* ==================================================================== */ +/* Register "SH_PTC_0" */ +/* Puge Translation Cache Message Configuration Information */ +/* ==================================================================== */ +#define SH_PTC_0 0x00000001101a0000UL +#define SH_PTC_0_MASK 0x80000000fffffffd +#define SH_PTC_0_INIT 0x0000000000000000 + +/* SH_PTC_0_A */ +/* Description: Type */ +#define SH_PTC_0_A_SHFT 0 +#define SH_PTC_0_A_MASK 0x0000000000000001 + +/* SH_PTC_0_PS */ +/* Description: Page Size */ +#define SH_PTC_0_PS_SHFT 2 +#define SH_PTC_0_PS_MASK 0x00000000000000fc + +/* SH_PTC_0_RID */ +/* Description: Region ID */ +#define SH_PTC_0_RID_SHFT 8 +#define SH_PTC_0_RID_MASK 0x00000000ffffff00 + +/* SH_PTC_0_START */ +/* Description: Start */ +#define SH_PTC_0_START_SHFT 63 +#define SH_PTC_0_START_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_PTC_1" */ +/* Puge Translation Cache Message Configuration Information */ +/* ==================================================================== */ +#define SH_PTC_1 0x00000001101a0080UL +#define SH_PTC_1_MASK 0x9ffffffffffff000 +#define SH_PTC_1_INIT 0x0000000000000000 + +/* SH_PTC_1_VPN */ +/* Description: Virtual page number */ +#define SH_PTC_1_VPN_SHFT 12 +#define SH_PTC_1_VPN_MASK 0x1ffffffffffff000 + +/* SH_PTC_1_START */ +/* Description: PTC_1 Start */ +#define SH_PTC_1_START_SHFT 63 +#define SH_PTC_1_START_MASK 0x8000000000000000 + +#endif /* _ASM_IA64_SN_SHUB_MMR_H */ diff --git a/include/asm-ia64/sn/simulator.h b/include/asm-ia64/sn/simulator.h index 82bc2cb20350..78eb4f869c8b 100644 --- a/include/asm-ia64/sn/simulator.h +++ b/include/asm-ia64/sn/simulator.h @@ -1,13 +1,13 @@ -#ifndef _ASM_IA64_SN_SIMULATOR_H -#define _ASM_IA64_SN_SIMULATOR_H - /* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. - * Copyright (C) 2000-2003 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved. */ +#ifndef _ASM_IA64_SN_SIMULATOR_H +#define _ASM_IA64_SN_SIMULATOR_H + #include <linux/config.h> #ifdef CONFIG_IA64_SGI_SN_SIM diff --git a/include/asm-ia64/sn/slotnum.h b/include/asm-ia64/sn/slotnum.h deleted file mode 100644 index 5e404ed48106..000000000000 --- a/include/asm-ia64/sn/slotnum.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_SLOTNUM_H -#define _ASM_IA64_SN_SLOTNUM_H - - -typedef unsigned char slotid_t; - -#include <asm/sn/sn2/slotnum.h> - -#endif /* _ASM_IA64_SN_SLOTNUM_H */ diff --git a/include/asm-ia64/sn/sn2/addrs.h b/include/asm-ia64/sn/sn2/addrs.h deleted file mode 100644 index b3f466fadc5f..000000000000 --- a/include/asm-ia64/sn/sn2/addrs.h +++ /dev/null @@ -1,169 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (c) 2001-2003 Silicon Graphics, Inc. All rights reserved. - */ - -#ifndef _ASM_IA64_SN_SN2_ADDRS_H -#define _ASM_IA64_SN_SN2_ADDRS_H - -/* McKinley Address Format: - * - * 4 4 3 3 3 3 - * 9 8 8 7 6 5 0 - * +-+---------+----+--------------+ - * |0| Node ID | AS | Node Offset | - * +-+---------+----+--------------+ - * - * Node ID: If bit 38 = 1, is ICE, else is SHUB - * AS: Address Space Identifier. Used only if bit 38 = 0. - * b'00: Local Resources and MMR space - * bit 35 - * 0: Local resources space - * node id: - * 0: IA64/NT compatibility space - * 2: Local MMR Space - * 4: Local memory, regardless of local node id - * 1: Global MMR space - * b'01: GET space. - * b'10: AMO space. - * b'11: Cacheable memory space. - * - * NodeOffset: byte offset - */ - -#ifndef __ASSEMBLY__ -typedef union ia64_sn2_pa { - struct { - unsigned long off : 36; - unsigned long as : 2; - unsigned long nasid: 11; - unsigned long fill : 15; - } f; - unsigned long l; - void *p; -} ia64_sn2_pa_t; -#endif - -#define TO_PHYS_MASK 0x0001ffcfffffffff /* Note - clear AS bits */ - - -/* Regions determined by AS */ -#define LOCAL_MMR_SPACE 0xc000008000000000 /* Local MMR space */ -#define LOCAL_PHYS_MMR_SPACE 0x8000008000000000 /* Local PhysicalMMR space */ -#define LOCAL_MEM_SPACE 0xc000010000000000 /* Local Memory space */ -#define GLOBAL_MMR_SPACE 0xc000000800000000 /* Global MMR space */ -#define GLOBAL_PHYS_MMR_SPACE 0x0000000800000000 /* Global Physical MMR space */ -#define GET_SPACE 0xe000001000000000 /* GET space */ -#define AMO_SPACE 0xc000002000000000 /* AMO space */ -#define CACHEABLE_MEM_SPACE 0xe000003000000000 /* Cacheable memory space */ -#define UNCACHED 0xc000000000000000 /* UnCacheable memory space */ -#define UNCACHED_PHYS 0x8000000000000000 /* UnCacheable physical memory space */ - -#define PHYS_MEM_SPACE 0x0000003000000000 /* physical memory space */ - -/* SN2 address macros */ -#define NID_SHFT 38 -#define LOCAL_MMR_ADDR(a) (UNCACHED | LOCAL_MMR_SPACE | (a)) -#define LOCAL_MMR_PHYS_ADDR(a) (UNCACHED_PHYS | LOCAL_PHYS_MMR_SPACE | (a)) -#define LOCAL_MEM_ADDR(a) (LOCAL_MEM_SPACE | (a)) -#define REMOTE_ADDR(n,a) ((((unsigned long)(n))<<NID_SHFT) | (a)) -#define GLOBAL_MMR_ADDR(n,a) (UNCACHED | GLOBAL_MMR_SPACE | REMOTE_ADDR(n,a)) -#define GLOBAL_MMR_PHYS_ADDR(n,a) (UNCACHED_PHYS | GLOBAL_PHYS_MMR_SPACE | REMOTE_ADDR(n,a)) -#define GET_ADDR(n,a) (GET_SPACE | REMOTE_ADDR(n,a)) -#define AMO_ADDR(n,a) (UNCACHED | AMO_SPACE | REMOTE_ADDR(n,a)) -#define GLOBAL_MEM_ADDR(n,a) (CACHEABLE_MEM_SPACE | REMOTE_ADDR(n,a)) - -/* non-II mmr's start at top of big window space (4G) */ -#define BWIN_TOP 0x0000000100000000 - -/* - * general address defines - for code common to SN0/SN1/SN2 - */ -#define CAC_BASE CACHEABLE_MEM_SPACE /* cacheable memory space */ -#define IO_BASE (UNCACHED | GLOBAL_MMR_SPACE) /* lower 4G maps II's XIO space */ -#define AMO_BASE (UNCACHED | AMO_SPACE) /* fetch & op space */ -#define MSPEC_BASE AMO_BASE /* fetch & op space */ -#define UNCAC_BASE (UNCACHED | CACHEABLE_MEM_SPACE) /* uncached global memory */ -#define GET_BASE GET_SPACE /* momentarily coherent remote mem. */ -#define CALIAS_BASE LOCAL_CACHEABLE_BASE /* cached node-local memory */ -#define UALIAS_BASE (UNCACHED | LOCAL_CACHEABLE_BASE) /* uncached node-local memory */ - -#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) -#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) -#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) -#define TO_MSPEC(x) (MSPEC_BASE | ((x) & TO_PHYS_MASK)) -#define TO_GET(x) (GET_BASE | ((x) & TO_PHYS_MASK)) -#define TO_CALIAS(x) (CALIAS_BASE | TO_NODE_ADDRSPACE(x)) -#define TO_UALIAS(x) (UALIAS_BASE | TO_NODE_ADDRSPACE(x)) -#define NODE_SIZE_BITS 36 /* node offset : bits <35:0> */ -#define BWIN_SIZE_BITS 29 /* big window size: 512M */ -#define NASID_BITS 11 /* bits <48:38> */ -#define NASID_BITMASK (0x7ffULL) -#define NASID_SHFT NID_SHFT -#define NASID_META_BITS 0 /* ???? */ -#define NASID_LOCAL_BITS 7 /* same router as SN1 */ - -#define NODE_ADDRSPACE_SIZE (1UL << NODE_SIZE_BITS) -#define NASID_MASK ((uint64_t) NASID_BITMASK << NASID_SHFT) -#define NASID_GET(_pa) (int) (((uint64_t) (_pa) >> \ - NASID_SHFT) & NASID_BITMASK) -#define PHYS_TO_DMA(x) ( ((x & NASID_MASK) >> 2) | \ - (x & (NODE_ADDRSPACE_SIZE - 1)) ) - -#define CHANGE_NASID(n,x) ({ia64_sn2_pa_t _v; _v.l = (long) (x); _v.f.nasid = n; _v.p;}) - -/* - * Determine if a physical address should be referenced as cached or uncached. - * For now, assume all memory is cached and everything else is noncached. - * (Later, we may need to special case areas of memory to be reference uncached). - */ -#define IS_CACHED_ADDRESS(x) (((x) & PHYS_MEM_SPACE) == PHYS_MEM_SPACE) - - -#ifndef __ASSEMBLY__ -#define NODE_SWIN_BASE(nasid, widget) \ - ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \ - : RAW_NODE_SWIN_BASE(nasid, widget)) -#else -#define NODE_SWIN_BASE(nasid, widget) \ - (NODE_IO_BASE(nasid) + ((uint64_t) (widget) << SWIN_SIZE_BITS)) -#define LOCAL_SWIN_BASE(widget) \ - (UNCACHED | LOCAL_MMR_SPACE | (((uint64_t) (widget) << SWIN_SIZE_BITS))) -#endif /* __ASSEMBLY__ */ - -/* - * The following definitions pertain to the IO special address - * space. They define the location of the big and little windows - * of any given node. - */ - -#define BWIN_INDEX_BITS 3 -#define BWIN_SIZE (1UL << BWIN_SIZE_BITS) -#define BWIN_SIZEMASK (BWIN_SIZE - 1) -#define BWIN_WIDGET_MASK 0x7 -#define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE) -#define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \ - ((uint64_t) (bigwin) << BWIN_SIZE_BITS)) - -#define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK) -#define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK) - -/* - * Verify if addr belongs to large window address of node with "nasid" - * - * - * NOTE: "addr" is expected to be XKPHYS address, and NOT physical - * address - * - * - */ - -#define NODE_BWIN_ADDR(nasid, addr) \ - (((addr) >= NODE_BWIN_BASE0(nasid)) && \ - ((addr) < (NODE_BWIN_BASE(nasid, HUB_NUM_BIG_WINDOW) + \ - BWIN_SIZE))) - -#endif /* _ASM_IA64_SN_SN2_ADDRS_H */ diff --git a/include/asm-ia64/sn/sn2/arch.h b/include/asm-ia64/sn/sn2/arch.h deleted file mode 100644 index f944f24cc6da..000000000000 --- a/include/asm-ia64/sn/sn2/arch.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_SN2_ARCH_H -#define _ASM_IA64_SN_SN2_ARCH_H - -#define CPUS_PER_NODE 4 /* CPUs on a single hub */ -#define CPUS_PER_SUBNODE 4 /* CPUs on a single hub PI */ - - -/* - * This is the maximum number of NASIDS that can be present in a system. - * (Highest NASID plus one.) - */ -#define MAX_NASIDS 2048 - - -/* - * This is the maximum number of nodes that can be part of a kernel. - * Effectively, it's the maximum number of compact node ids (cnodeid_t). - * This is not necessarily the same as MAX_NASIDS. - */ -#define MAX_COMPACT_NODES 2048 - -/* - * MAX_REGIONS refers to the maximum number of hardware partitioned regions. - */ -#define MAX_REGIONS 64 -#define MAX_NONPREMIUM_REGIONS 16 -#define MAX_PREMIUM_REGIONS MAX_REGIONS - - -/* - * MAX_PARITIONS refers to the maximum number of logically defined - * partitions the system can support. - */ -#define MAX_PARTITIONS MAX_REGIONS - - -#define NASID_MASK_BYTES ((MAX_NASIDS + 7) / 8) -#define CNASID_MASK_BYTES (NASID_MASK_BYTES / 2) - - -/* - * 1 FSB per SHUB, with up to 4 cpus per FSB. - */ -#define NUM_SUBNODES 1 -#define SUBNODE_SHFT 0 -#define SUBNODE_MASK (0x0 << SUBNODE_SHFT) -#define LOCALCPU_SHFT 0 -#define LOCALCPU_MASK (0x3 << LOCALCPU_SHFT) -#define SUBNODE(slice) (((slice) & SUBNODE_MASK) >> SUBNODE_SHFT) -#define LOCALCPU(slice) (((slice) & LOCALCPU_MASK) >> LOCALCPU_SHFT) -#define TO_SLICE(subn, local) (((subn) << SUBNODE_SHFT) | \ - ((local) << LOCALCPU_SHFT)) - -#endif /* _ASM_IA64_SN_SN2_ARCH_H */ diff --git a/include/asm-ia64/sn/sn2/geo.h b/include/asm-ia64/sn/sn2/geo.h deleted file mode 100644 index 599979c98478..000000000000 --- a/include/asm-ia64/sn/sn2/geo.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. - */ - -#ifndef _ASM_IA64_SN_SN2_GEO_H -#define _ASM_IA64_SN_SN2_GEO_H - -/* Headers required by declarations in this file */ - -#include <asm/sn/slotnum.h> - - -/* The geoid_t implementation below is based loosely on the pcfg_t - implementation in sys/SN/promcfg.h. */ - -/* Type declaractions */ - -/* Size of a geoid_t structure (must be before decl. of geoid_u) */ -#define GEOID_SIZE 8 /* Would 16 be better? The size can - be different on different platforms. */ - -#define MAX_SLABS 0xe /* slabs per module */ - -typedef unsigned char geo_type_t; - -/* Fields common to all substructures */ -typedef struct geo_any_s { - moduleid_t module; /* The module (box) this h/w lives in */ - geo_type_t type; /* What type of h/w is named by this geoid_t */ - slabid_t slab; /* The logical assembly within the module */ -} geo_any_t; - -/* Additional fields for particular types of hardware */ -typedef struct geo_node_s { - geo_any_t any; /* No additional fields needed */ -} geo_node_t; - -typedef struct geo_rtr_s { - geo_any_t any; /* No additional fields needed */ -} geo_rtr_t; - -typedef struct geo_iocntl_s { - geo_any_t any; /* No additional fields needed */ -} geo_iocntl_t; - -typedef struct geo_pcicard_s { - geo_iocntl_t any; - char bus; /* Bus/widget number */ - slotid_t slot; /* PCI slot number */ -} geo_pcicard_t; - -/* Subcomponents of a node */ -typedef struct geo_cpu_s { - geo_node_t node; - char slice; /* Which CPU on the node */ -} geo_cpu_t; - -typedef struct geo_mem_s { - geo_node_t node; - char membus; /* The memory bus on the node */ - char memslot; /* The memory slot on the bus */ -} geo_mem_t; - - -typedef union geoid_u { - geo_any_t any; - geo_node_t node; - geo_iocntl_t iocntl; - geo_pcicard_t pcicard; - geo_rtr_t rtr; - geo_cpu_t cpu; - geo_mem_t mem; - char padsize[GEOID_SIZE]; -} geoid_t; - - -/* Preprocessor macros */ - -#define GEO_MAX_LEN 48 /* max. formatted length, plus some pad: - module/001c07/slab/5/node/memory/2/slot/4 */ - -/* Values for geo_type_t */ -#define GEO_TYPE_INVALID 0 -#define GEO_TYPE_MODULE 1 -#define GEO_TYPE_NODE 2 -#define GEO_TYPE_RTR 3 -#define GEO_TYPE_IOCNTL 4 -#define GEO_TYPE_IOCARD 5 -#define GEO_TYPE_CPU 6 -#define GEO_TYPE_MEM 7 -#define GEO_TYPE_MAX (GEO_TYPE_MEM+1) - -/* Parameter for hwcfg_format_geoid_compt() */ -#define GEO_COMPT_MODULE 1 -#define GEO_COMPT_SLAB 2 -#define GEO_COMPT_IOBUS 3 -#define GEO_COMPT_IOSLOT 4 -#define GEO_COMPT_CPU 5 -#define GEO_COMPT_MEMBUS 6 -#define GEO_COMPT_MEMSLOT 7 - -#define GEO_INVALID_STR "<invalid>" - -#endif /* _ASM_IA64_SN_SN2_GEO_H */ diff --git a/include/asm-ia64/sn/sn2/intr.h b/include/asm-ia64/sn/sn2/intr.h deleted file mode 100644 index 2d3df0574b8c..000000000000 --- a/include/asm-ia64/sn/sn2/intr.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_SN2_INTR_H -#define _ASM_IA64_SN_SN2_INTR_H - -#define SGI_UART_VECTOR (0xe9) -#define SGI_SHUB_ERROR_VECTOR (0xea) - -// These two IRQ's are used by partitioning. -#define SGI_XPC_ACTIVATE (0x30) -#define SGI_II_ERROR (0x31) -#define SGI_XBOW_ERROR (0x32) -#define SGI_PCIBR_ERROR (0x33) -#define SGI_ACPI_SCI_INT (0x34) -#define SGI_XPC_NOTIFY (0xe7) - -#define IA64_SN2_FIRST_DEVICE_VECTOR (0x37) -#define IA64_SN2_LAST_DEVICE_VECTOR (0xe6) - -#define SN2_IRQ_RESERVED (0x1) -#define SN2_IRQ_CONNECTED (0x2) -#define SN2_IRQ_SHARED (0x4) - -#define SN2_IRQ_PER_HUB (2048) - -#endif /* _ASM_IA64_SN_SN2_INTR_H */ diff --git a/include/asm-ia64/sn/sn2/io.h b/include/asm-ia64/sn/sn2/io.h deleted file mode 100644 index 4cc94e9ad4eb..000000000000 --- a/include/asm-ia64/sn/sn2/io.h +++ /dev/null @@ -1,239 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000-2003 Silicon Graphics, Inc. All rights reserved. - */ - -#ifndef _ASM_SN_SN2_IO_H -#define _ASM_SN_SN2_IO_H -#include <linux/compiler.h> -#include <asm/intrinsics.h> - -extern void * sn_io_addr(unsigned long port) __attribute_const__; /* Forward definition */ -extern void sn_mmiob(void); /* Forward definition */ - -#define __sn_mf_a() ia64_mfa() - -extern void sn_dma_flush(unsigned long); - -#define __sn_inb ___sn_inb -#define __sn_inw ___sn_inw -#define __sn_inl ___sn_inl -#define __sn_outb ___sn_outb -#define __sn_outw ___sn_outw -#define __sn_outl ___sn_outl -#define __sn_readb ___sn_readb -#define __sn_readw ___sn_readw -#define __sn_readl ___sn_readl -#define __sn_readq ___sn_readq -#define __sn_readb_relaxed ___sn_readb_relaxed -#define __sn_readw_relaxed ___sn_readw_relaxed -#define __sn_readl_relaxed ___sn_readl_relaxed -#define __sn_readq_relaxed ___sn_readq_relaxed - -/* - * The following routines are SN Platform specific, called when - * a reference is made to inX/outX set macros. SN Platform - * inX set of macros ensures that Posted DMA writes on the - * Bridge is flushed. - * - * The routines should be self explainatory. - */ - -static inline unsigned int -___sn_inb (unsigned long port) -{ - volatile unsigned char *addr; - unsigned char ret = -1; - - if ((addr = sn_io_addr(port))) { - ret = *addr; - __sn_mf_a(); - sn_dma_flush((unsigned long)addr); - } - return ret; -} - -static inline unsigned int -___sn_inw (unsigned long port) -{ - volatile unsigned short *addr; - unsigned short ret = -1; - - if ((addr = sn_io_addr(port))) { - ret = *addr; - __sn_mf_a(); - sn_dma_flush((unsigned long)addr); - } - return ret; -} - -static inline unsigned int -___sn_inl (unsigned long port) -{ - volatile unsigned int *addr; - unsigned int ret = -1; - - if ((addr = sn_io_addr(port))) { - ret = *addr; - __sn_mf_a(); - sn_dma_flush((unsigned long)addr); - } - return ret; -} - -static inline void -___sn_outb (unsigned char val, unsigned long port) -{ - volatile unsigned char *addr; - - if ((addr = sn_io_addr(port))) { - *addr = val; - sn_mmiob(); - } -} - -static inline void -___sn_outw (unsigned short val, unsigned long port) -{ - volatile unsigned short *addr; - - if ((addr = sn_io_addr(port))) { - *addr = val; - sn_mmiob(); - } -} - -static inline void -___sn_outl (unsigned int val, unsigned long port) -{ - volatile unsigned int *addr; - - if ((addr = sn_io_addr(port))) { - *addr = val; - sn_mmiob(); - } -} - -/* - * The following routines are SN Platform specific, called when - * a reference is made to readX/writeX set macros. SN Platform - * readX set of macros ensures that Posted DMA writes on the - * Bridge is flushed. - * - * The routines should be self explainatory. - */ - -static inline unsigned char -___sn_readb (void *addr) -{ - unsigned char val; - - val = *(volatile unsigned char *)addr; - __sn_mf_a(); - sn_dma_flush((unsigned long)addr); - return val; -} - -static inline unsigned short -___sn_readw (void *addr) -{ - unsigned short val; - - val = *(volatile unsigned short *)addr; - __sn_mf_a(); - sn_dma_flush((unsigned long)addr); - return val; -} - -static inline unsigned int -___sn_readl (void *addr) -{ - unsigned int val; - - val = *(volatile unsigned int *) addr; - __sn_mf_a(); - sn_dma_flush((unsigned long)addr); - return val; -} - -static inline unsigned long -___sn_readq (void *addr) -{ - unsigned long val; - - val = *(volatile unsigned long *) addr; - __sn_mf_a(); - sn_dma_flush((unsigned long)addr); - return val; -} - -/* - * For generic and SN2 kernels, we have a set of fast access - * PIO macros. These macros are provided on SN Platform - * because the normal inX and readX macros perform an - * additional task of flushing Post DMA request on the Bridge. - * - * These routines should be self explainatory. - */ - -static inline unsigned int -sn_inb_fast (unsigned long port) -{ - volatile unsigned char *addr = (unsigned char *)port; - unsigned char ret; - - ret = *addr; - __sn_mf_a(); - return ret; -} - -static inline unsigned int -sn_inw_fast (unsigned long port) -{ - volatile unsigned short *addr = (unsigned short *)port; - unsigned short ret; - - ret = *addr; - __sn_mf_a(); - return ret; -} - -static inline unsigned int -sn_inl_fast (unsigned long port) -{ - volatile unsigned int *addr = (unsigned int *)port; - unsigned int ret; - - ret = *addr; - __sn_mf_a(); - return ret; -} - -static inline unsigned char -___sn_readb_relaxed (void *addr) -{ - return *(volatile unsigned char *)addr; -} - -static inline unsigned short -___sn_readw_relaxed (void *addr) -{ - return *(volatile unsigned short *)addr; -} - -static inline unsigned int -___sn_readl_relaxed (void *addr) -{ - return *(volatile unsigned int *) addr; -} - -static inline unsigned long -___sn_readq_relaxed (void *addr) -{ - return *(volatile unsigned long *) addr; -} - -#endif diff --git a/include/asm-ia64/sn/sn2/shub.h b/include/asm-ia64/sn/sn2/shub.h deleted file mode 100644 index edeeee0fbc47..000000000000 --- a/include/asm-ia64/sn/sn2/shub.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (c) 2001-2003 Silicon Graphics, Inc. All rights reserved. - */ - - -#ifndef _ASM_IA64_SN_SN2_SHUB_H -#define _ASM_IA64_SN_SN2_SHUB_H - -/* - * Junk Bus Address Space - * The junk bus is used to access the PROM, LED's, and UART. It's - * accessed through the local block MMR space. The data path is - * 16 bits wide. This space requires address bits 31-27 to be set, and - * is further divided by address bits 26:15. - * The LED addresses are write-only. To read the LEDs, you need to use - * SH_JUNK_BUS_LED0-3, defined in shub_mmr.h - * - */ -#define SH_REAL_JUNK_BUS_LED0 0x7fed00000 -#define SH_REAL_JUNK_BUS_LED1 0x7fed10000 -#define SH_REAL_JUNK_BUS_LED2 0x7fed20000 -#define SH_REAL_JUNK_BUS_LED3 0x7fed30000 -#define SH_JUNK_BUS_UART0 0x7fed40000 -#define SH_JUNK_BUS_UART1 0x7fed40008 -#define SH_JUNK_BUS_UART2 0x7fed40010 -#define SH_JUNK_BUS_UART3 0x7fed40018 -#define SH_JUNK_BUS_UART4 0x7fed40020 -#define SH_JUNK_BUS_UART5 0x7fed40028 -#define SH_JUNK_BUS_UART6 0x7fed40030 -#define SH_JUNK_BUS_UART7 0x7fed40038 - -#endif /* _ASM_IA64_SN_SN2_SHUB_H */ diff --git a/include/asm-ia64/sn/sn2/shub_md.h b/include/asm-ia64/sn/sn2/shub_md.h deleted file mode 100644 index 15b101446828..000000000000 --- a/include/asm-ia64/sn/sn2/shub_md.h +++ /dev/null @@ -1,275 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (c) 2001, 2002-2003 Silicon Graphics, Inc. All rights reserved. - */ - - -#ifndef _ASM_IA64_SN_SN2_SHUB_MD_H -#define _ASM_IA64_SN_SN2_SHUB_MD_H - -/* SN2 supports a mostly-flat address space with 4 CPU-visible, evenly spaced, - contiguous regions, or "software banks". On SN2, software bank n begins at - addresses n * 16GB, 0 <= n < 4. Each bank has a 16GB address space. If - the 4 dimms do not use up this space there will be holes between the - banks. Even with these holes the whole memory space within a bank is - not addressable address space. The top 1/32 of each bank is directory - memory space and is accessible through bist only. - - Physically a SN2 node board contains 2 daughter cards with 8 dimm sockets - each. A total of 16 dimm sockets arranged as 4 "DIMM banks" of 4 dimms - each. The data is stripped across the 4 memory busses so all dimms within - a dimm bank must have identical capacity dimms. Memory is increased or - decreased in sets of 4. Each dimm bank has 2 dimms on each side. - - Physical Dimm Bank layout. - DTR Card0 - ------------ - Dimm Bank 3 | MemYL3 | CS 3 - | MemXL3 | - |----------| - Dimm Bank 2 | MemYL2 | CS 2 - | MemXL2 | - |----------| - Dimm Bank 1 | MemYL1 | CS 1 - | MemXL1 | - |----------| - Dimm Bank 0 | MemYL0 | CS 0 - | MemXL0 | - ------------ - | | - BUS BUS - XL YL - | | - ------------ - | SHUB | - | MD | - ------------ - | | - BUS BUS - XR YR - | | - ------------ - Dimm Bank 0 | MemXR0 | CS 0 - | MemYR0 | - |----------| - Dimm Bank 1 | MemXR1 | CS 1 - | MemYR1 | - |----------| - Dimm Bank 2 | MemXR2 | CS 2 - | MemYR2 | - |----------| - Dimm Bank 3 | MemXR3 | CS 3 - | MemYR3 | - ------------ - DTR Card1 - - The dimms can be 1 or 2 sided dimms. The size and bankness is defined - separately for each dimm bank in the sh_[x,y,jnr]_dimm_cfg MMR register. - - Normally software bank 0 would map directly to physical dimm bank 0. The - software banks can map to the different physical dimm banks via the - DIMM[0-3]_CS field in SH_[x,y,jnr]_DIMM_CFG for each dimm slot. - - All the PROM's data structures (promlog variables, klconfig, etc.) - track memory by the physical dimm bank number. The kernel usually - tracks memory by the software bank number. - - */ - - -/* Preprocessor macros */ -#define MD_MEM_BANKS 4 -#define MD_PHYS_BANKS_PER_DIMM 2 /* dimms may be 2 sided. */ -#define MD_NUM_PHYS_BANKS (MD_MEM_BANKS * MD_PHYS_BANKS_PER_DIMM) -#define MD_DIMMS_IN_SLOT 4 /* 4 dimms in each dimm bank. aka slot */ - -/* Address bits 35,34 control dimm bank access. */ -#define MD_BANK_SHFT 34 -#define MD_BANK_MASK (UINT64_CAST 0x3 << MD_BANK_SHFT ) -#define MD_BANK_GET(addr) (((addr) & MD_BANK_MASK) >> MD_BANK_SHFT) -#define MD_BANK_SIZE (UINT64_CAST 0x1 << MD_BANK_SHFT ) /* 16 gb */ -#define MD_BANK_OFFSET(_b) (UINT64_CAST (_b) << MD_BANK_SHFT) - -/*Address bit 12 selects side of dimm if 2bnk dimms present. */ -#define MD_PHYS_BANK_SEL_SHFT 12 -#define MD_PHYS_BANK_SEL_MASK (UINT64_CAST 0x1 << MD_PHYS_BANK_SEL_SHFT) - -/* Address bit 7 determines if data resides on X or Y memory system. - * If addr Bit 7 is set the data resides on Y memory system and - * the corresponing directory entry reside on the X. - */ -#define MD_X_OR_Y_SEL_SHFT 7 -#define MD_X_OR_Y_SEL_MASK (1 << MD_X_OR_Y_SEL_SHFT) - -/* Address bit 8 determines which directory entry of the pair the address - * corresponds to. If addr Bit 8 is set DirB corresponds to the memory address. - */ -#define MD_DIRA_OR_DIRB_SEL_SHFT 8 -#define MD_DIRA_OR_DIRB_SEL_MASK (1 << MD_DIRA_OR_DIRB_SEL_SHFT) - -/* Address bit 11 determines if corresponding directory entry resides - * on Left or Right memory bus. If addr Bit 11 is set the corresponding - * directory entry resides on Right memory bus. - */ -#define MD_L_OR_R_SEL_SHFT 11 -#define MD_L_OR_R_SEL_MASK (1 << MD_L_OR_R_SEL_SHFT) - -/* DRAM sizes. */ -#define MD_SZ_64_Mb 0x0 -#define MD_SZ_128_Mb 0x1 -#define MD_SZ_256_Mb 0x2 -#define MD_SZ_512_Mb 0x3 -#define MD_SZ_1024_Mb 0x4 -#define MD_SZ_2048_Mb 0x5 -#define MD_SZ_UNUSED 0x7 - -#define MD_DIMM_SIZE_BYTES(_size, _2bk) ( \ - ( (_size) == 7 ? 0 : ( 0x4000000L << (_size)) << (_2bk)))\ - -#define MD_DIMM_SIZE_MBYTES(_size, _2bk) ( \ - ( (_size) == 7 ? 0 : ( 0x40L << (_size) ) << (_2bk))) \ - -/* The top 1/32 of each bank is directory memory, and not accessible - * via normal reads and writes */ -#define MD_DIMM_USER_SIZE(_size) ((_size) * 31 / 32) - -/* Minimum size of a populated bank is 64M (62M usable) */ -#define MIN_BANK_SIZE MD_DIMM_USER_SIZE((64 * 0x100000)) -#define MIN_BANK_STRING "62" - - -/*Possible values for FREQ field in sh_[x,y,jnr]_dimm_cfg regs */ -#define MD_DIMM_100_CL2_0 0x0 -#define MD_DIMM_133_CL2_0 0x1 -#define MD_DIMM_133_CL2_5 0x2 -#define MD_DIMM_160_CL2_0 0x3 -#define MD_DIMM_160_CL2_5 0x4 -#define MD_DIMM_160_CL3_0 0x5 -#define MD_DIMM_200_CL2_0 0x6 -#define MD_DIMM_200_CL2_5 0x7 -#define MD_DIMM_200_CL3_0 0x8 - -/* DIMM_CFG fields */ -#define MD_DIMM_SHFT(_dimm) ((_dimm) << 3) -#define MD_DIMM_SIZE_MASK(_dimm) \ - (SH_JNR_DIMM_CFG_DIMM0_SIZE_MASK << \ - (MD_DIMM_SHFT(_dimm))) - -#define MD_DIMM_2BK_MASK(_dimm) \ - (SH_JNR_DIMM_CFG_DIMM0_2BK_MASK << \ - MD_DIMM_SHFT(_dimm)) - -#define MD_DIMM_REV_MASK(_dimm) \ - (SH_JNR_DIMM_CFG_DIMM0_REV_MASK << \ - MD_DIMM_SHFT(_dimm)) - -#define MD_DIMM_CS_MASK(_dimm) \ - (SH_JNR_DIMM_CFG_DIMM0_CS_MASK << \ - MD_DIMM_SHFT(_dimm)) - -#define MD_DIMM_SIZE(_dimm, _cfg) \ - (((_cfg) & MD_DIMM_SIZE_MASK(_dimm)) \ - >> (MD_DIMM_SHFT(_dimm)+SH_JNR_DIMM_CFG_DIMM0_SIZE_SHFT)) - -#define MD_DIMM_TWO_SIDED(_dimm,_cfg) \ - ( ((_cfg) & MD_DIMM_2BK_MASK(_dimm)) \ - >> (MD_DIMM_SHFT(_dimm)+SH_JNR_DIMM_CFG_DIMM0_2BK_SHFT)) - -#define MD_DIMM_REVERSED(_dimm,_cfg) \ - (((_cfg) & MD_DIMM_REV_MASK(_dimm)) \ - >> (MD_DIMM_SHFT(_dimm)+SH_JNR_DIMM_CFG_DIMM0_REV_SHFT)) - -#define MD_DIMM_CS(_dimm,_cfg) \ - (((_cfg) & MD_DIMM_CS_MASK(_dimm)) \ - >> (MD_DIMM_SHFT(_dimm)+SH_JNR_DIMM_CFG_DIMM0_CS_SHFT)) - - - -/* Macros to set MMRs that must be set identically to others. */ -#define MD_SET_DIMM_CFG(_n, _value) { \ - REMOTE_HUB_S(_n, SH_X_DIMM_CFG,_value); \ - REMOTE_HUB_S(_n, SH_Y_DIMM_CFG, _value); \ - REMOTE_HUB_S(_n, SH_JNR_DIMM_CFG, _value);} - -#define MD_SET_DQCT_CFG(_n, _value) { \ - REMOTE_HUB_S(_n, SH_X_DQCT_CFG,_value); \ - REMOTE_HUB_S(_n, SH_Y_DQCT_CFG,_value); } - -#define MD_SET_CFG(_n, _value) { \ - REMOTE_HUB_S(_n, SH_X_CFG,_value); \ - REMOTE_HUB_S(_n, SH_Y_CFG,_value);} - -#define MD_SET_REFRESH_CONTROL(_n, _value) { \ - REMOTE_HUB_S(_n, SH_X_REFRESH_CONTROL, _value); \ - REMOTE_HUB_S(_n, SH_Y_REFRESH_CONTROL, _value);} - -#define MD_SET_DQ_MMR_DIR_COFIG(_n, _value) { \ - REMOTE_HUB_S(_n, SH_MD_DQLP_MMR_DIR_CONFIG, _value); \ - REMOTE_HUB_S(_n, SH_MD_DQRP_MMR_DIR_CONFIG, _value);} - -#define MD_SET_PIOWD_DIR_ENTRYS(_n, _value) { \ - REMOTE_HUB_S(_n, SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY, _value);\ - REMOTE_HUB_S(_n, SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY, _value);} - -/* - * There are 12 Node Presence MMRs, 4 in each primary DQ and 4 in the - * LB. The data in the left and right DQ MMRs and the LB must match. - */ -#define MD_SET_PRESENT_VEC(_n, _vec, _value) { \ - REMOTE_HUB_S(_n, SH_MD_DQLP_MMR_DIR_PRESVEC0+((_vec)*0x10),\ - _value); \ - REMOTE_HUB_S(_n, SH_MD_DQRP_MMR_DIR_PRESVEC0+((_vec)*0x10),\ - _value); \ - REMOTE_HUB_S(_n, SH_SHUBS_PRESENT0+((_vec)*0x80), _value);} -/* - * There are 16 Privilege Vector MMRs, 8 in each primary DQ. The data - * in the corresponding left and right DQ MMRs must match. Each MMR - * pair is used for a single partition. - */ -#define MD_SET_PRI_VEC(_n, _vec, _value) { \ - REMOTE_HUB_S(_n, SH_MD_DQLP_MMR_DIR_PRIVEC0+((_vec)*0x10),\ - _value); \ - REMOTE_HUB_S(_n, SH_MD_DQRP_MMR_DIR_PRIVEC0+((_vec)*0x10),\ - _value);} -/* - * There are 16 Local/Remote MMRs, 8 in each primary DQ. The data in - * the corresponding left and right DQ MMRs must match. Each MMR pair - * is used for a single partition. - */ -#define MD_SET_LOC_VEC(_n, _vec, _value) { \ - REMOTE_HUB_S(_n, SH_MD_DQLP_MMR_DIR_LOCVEC0+((_vec)*0x10),\ - _value); \ - REMOTE_HUB_S(_n, SH_MD_DQRP_MMR_DIR_LOCVEC0+((_vec)*0x10),\ - _value);} - -/* Memory BIST CMDS */ -#define MD_DIMM_INIT_MODE_SET 0x0 -#define MD_DIMM_INIT_REFRESH 0x1 -#define MD_DIMM_INIT_PRECHARGE 0x2 -#define MD_DIMM_INIT_BURST_TERM 0x6 -#define MD_DIMM_INIT_NOP 0x7 -#define MD_DIMM_BIST_READ 0x10 -#define MD_FILL_DIR 0x20 -#define MD_FILL_DATA 0x30 -#define MD_FILL_DIR_ACCESS 0X40 -#define MD_READ_DIR_PAIR 0x50 -#define MD_READ_DIR_TAG 0x60 - -/* SH_MMRBIST_CTL macros */ -#define MD_BIST_FAIL(_n) (REMOTE_HUB_L(_n, SH_MMRBIST_CTL) & \ - SH_MMRBIST_CTL_FAIL_MASK) - -#define MD_BIST_IN_PROGRESS(_n) (REMOTE_HUB_L(_n, SH_MMRBIST_CTL) & \ - SH_MMRBIST_CTL_IN_PROGRESS_MASK) - -#define MD_BIST_MEM_IDLE(_n); (REMOTE_HUB_L(_n, SH_MMRBIST_CTL) & \ - SH_MMRBIST_CTL_MEM_IDLE_MASK) - -/* SH_MMRBIST_ERR macros */ -#define MD_BIST_MISCOMPARE(_n) (REMOTE_HUB_L(_n, SH_MMRBIST_ERR) & \ - SH_MMRBIST_ERR_DETECTED_MASK) - -#endif /* _ASM_IA64_SN_SN2_SHUB_MD_H */ diff --git a/include/asm-ia64/sn/sn2/shub_mmr.h b/include/asm-ia64/sn/sn2/shub_mmr.h deleted file mode 100644 index 05ea7efaf453..000000000000 --- a/include/asm-ia64/sn/sn2/shub_mmr.h +++ /dev/null @@ -1,31597 +0,0 @@ -/* - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (c) 2001-2003 Silicon Graphics, Inc. All rights reserved. - */ - - -#ifndef _ASM_IA64_SN_SN2_SHUB_MMR_H -#define _ASM_IA64_SN_SN2_SHUB_MMR_H - -/* ==================================================================== */ -/* Register "SH_FSB_BINIT_CONTROL" */ -/* FSB BINIT# Control */ -/* ==================================================================== */ - -#define SH_FSB_BINIT_CONTROL 0x0000000120010000 -#define SH_FSB_BINIT_CONTROL_MASK 0x0000000000000001 -#define SH_FSB_BINIT_CONTROL_INIT 0x0000000000000000 - -/* SH_FSB_BINIT_CONTROL_BINIT */ -/* Description: Assert the FSB's BINIT# Signal */ -#define SH_FSB_BINIT_CONTROL_BINIT_SHFT 0 -#define SH_FSB_BINIT_CONTROL_BINIT_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_FSB_RESET_CONTROL" */ -/* FSB Reset Control */ -/* ==================================================================== */ - -#define SH_FSB_RESET_CONTROL 0x0000000120010080 -#define SH_FSB_RESET_CONTROL_MASK 0x0000000000000001 -#define SH_FSB_RESET_CONTROL_INIT 0x0000000000000000 - -/* SH_FSB_RESET_CONTROL_RESET */ -/* Description: Assert the FSB's RESET# Signal */ -#define SH_FSB_RESET_CONTROL_RESET_SHFT 0 -#define SH_FSB_RESET_CONTROL_RESET_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_FSB_SYSTEM_AGENT_CONFIG" */ -/* FSB System Agent Configuration */ -/* ==================================================================== */ - -#define SH_FSB_SYSTEM_AGENT_CONFIG 0x0000000120010100 -#define SH_FSB_SYSTEM_AGENT_CONFIG_MASK 0x00003fff0187fff9 -#define SH_FSB_SYSTEM_AGENT_CONFIG_INIT 0x0000000000000000 - -/* SH_FSB_SYSTEM_AGENT_CONFIG_RCNT_SCNT_EN */ -/* Description: RCNT/SCNT Assertion Enabled */ -#define SH_FSB_SYSTEM_AGENT_CONFIG_RCNT_SCNT_EN_SHFT 0 -#define SH_FSB_SYSTEM_AGENT_CONFIG_RCNT_SCNT_EN_MASK 0x0000000000000001 - -/* SH_FSB_SYSTEM_AGENT_CONFIG_BERR_ASSERT_EN */ -/* Description: BERR Assertion Enabled for Bus Errors */ -#define SH_FSB_SYSTEM_AGENT_CONFIG_BERR_ASSERT_EN_SHFT 3 -#define SH_FSB_SYSTEM_AGENT_CONFIG_BERR_ASSERT_EN_MASK 0x0000000000000008 - -/* SH_FSB_SYSTEM_AGENT_CONFIG_BERR_SAMPLING_EN */ -/* Description: BERR Sampling Enabled */ -#define SH_FSB_SYSTEM_AGENT_CONFIG_BERR_SAMPLING_EN_SHFT 4 -#define SH_FSB_SYSTEM_AGENT_CONFIG_BERR_SAMPLING_EN_MASK 0x0000000000000010 - -/* SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_ASSERT_EN */ -/* Description: BINIT Assertion Enabled */ -#define SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_ASSERT_EN_SHFT 5 -#define SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_ASSERT_EN_MASK 0x0000000000000020 - -/* SH_FSB_SYSTEM_AGENT_CONFIG_BNR_THROTTLING_EN */ -/* Description: stutter FSB request assertion */ -#define SH_FSB_SYSTEM_AGENT_CONFIG_BNR_THROTTLING_EN_SHFT 6 -#define SH_FSB_SYSTEM_AGENT_CONFIG_BNR_THROTTLING_EN_MASK 0x0000000000000040 - -/* SH_FSB_SYSTEM_AGENT_CONFIG_SHORT_HANG_EN */ -/* Description: use short duration hang timeout */ -#define SH_FSB_SYSTEM_AGENT_CONFIG_SHORT_HANG_EN_SHFT 7 -#define SH_FSB_SYSTEM_AGENT_CONFIG_SHORT_HANG_EN_MASK 0x0000000000000080 - -/* SH_FSB_SYSTEM_AGENT_CONFIG_INTA_RSP_DATA */ -/* Description: Interrupt Acknowledge Response Data */ -#define SH_FSB_SYSTEM_AGENT_CONFIG_INTA_RSP_DATA_SHFT 8 -#define SH_FSB_SYSTEM_AGENT_CONFIG_INTA_RSP_DATA_MASK 0x000000000000ff00 - -/* SH_FSB_SYSTEM_AGENT_CONFIG_IO_TRANS_RSP */ -/* Description: IO Transaction Response */ -#define SH_FSB_SYSTEM_AGENT_CONFIG_IO_TRANS_RSP_SHFT 16 -#define SH_FSB_SYSTEM_AGENT_CONFIG_IO_TRANS_RSP_MASK 0x0000000000010000 - -/* SH_FSB_SYSTEM_AGENT_CONFIG_XTPR_TRANS_RSP */ -/* Description: External Task Priority Register (xTPR) Transaction */ -/* Response */ -#define SH_FSB_SYSTEM_AGENT_CONFIG_XTPR_TRANS_RSP_SHFT 17 -#define SH_FSB_SYSTEM_AGENT_CONFIG_XTPR_TRANS_RSP_MASK 0x0000000000020000 - -/* SH_FSB_SYSTEM_AGENT_CONFIG_INTA_TRANS_RSP */ -/* Description: Interrupt Acknowledge Transaction Response */ -#define SH_FSB_SYSTEM_AGENT_CONFIG_INTA_TRANS_RSP_SHFT 18 -#define SH_FSB_SYSTEM_AGENT_CONFIG_INTA_TRANS_RSP_MASK 0x0000000000040000 - -/* SH_FSB_SYSTEM_AGENT_CONFIG_TDOT */ -/* Description: Throttle Data-bus Ownership Transitions */ -#define SH_FSB_SYSTEM_AGENT_CONFIG_TDOT_SHFT 23 -#define SH_FSB_SYSTEM_AGENT_CONFIG_TDOT_MASK 0x0000000000800000 - -/* SH_FSB_SYSTEM_AGENT_CONFIG_SERIALIZE_FSB_EN */ -/* Description: serialize processor transactions */ -#define SH_FSB_SYSTEM_AGENT_CONFIG_SERIALIZE_FSB_EN_SHFT 24 -#define SH_FSB_SYSTEM_AGENT_CONFIG_SERIALIZE_FSB_EN_MASK 0x0000000001000000 - -/* SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_EVENT_ENABLES */ -/* Description: FSB error binit enables */ -#define SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_EVENT_ENABLES_SHFT 32 -#define SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_EVENT_ENABLES_MASK 0x00003fff00000000 - -/* ==================================================================== */ -/* Register "SH_FSB_VGA_REMAP" */ -/* FSB VGA Address Space Remap */ -/* ==================================================================== */ - -#define SH_FSB_VGA_REMAP 0x0000000120010180 -#define SH_FSB_VGA_REMAP_MASK 0x4001fffffffe0000 -#define SH_FSB_VGA_REMAP_INIT 0x0000000000000000 - -/* SH_FSB_VGA_REMAP_OFFSET */ -/* Description: VGA Remap Node Offset */ -#define SH_FSB_VGA_REMAP_OFFSET_SHFT 17 -#define SH_FSB_VGA_REMAP_OFFSET_MASK 0x0000000ffffe0000 - -/* SH_FSB_VGA_REMAP_ASID */ -/* Description: VGA Remap Address Space ID */ -#define SH_FSB_VGA_REMAP_ASID_SHFT 36 -#define SH_FSB_VGA_REMAP_ASID_MASK 0x0000003000000000 - -/* SH_FSB_VGA_REMAP_NID */ -/* Description: VGA Remap Node ID */ -#define SH_FSB_VGA_REMAP_NID_SHFT 38 -#define SH_FSB_VGA_REMAP_NID_MASK 0x0001ffc000000000 - -/* SH_FSB_VGA_REMAP_VGA_REMAPPING_ENABLED */ -/* Description: VGA Remapping Enabled */ -#define SH_FSB_VGA_REMAP_VGA_REMAPPING_ENABLED_SHFT 62 -#define SH_FSB_VGA_REMAP_VGA_REMAPPING_ENABLED_MASK 0x4000000000000000 - -/* ==================================================================== */ -/* Register "SH_FSB_RESET_STATUS" */ -/* FSB Reset Status */ -/* ==================================================================== */ - -#define SH_FSB_RESET_STATUS 0x0000000120020000 -#define SH_FSB_RESET_STATUS_MASK 0x0000000000000001 -#define SH_FSB_RESET_STATUS_INIT 0x0000000000000000 - -/* SH_FSB_RESET_STATUS_RESET_IN_PROGRESS */ -/* Description: Reset in Progress */ -#define SH_FSB_RESET_STATUS_RESET_IN_PROGRESS_SHFT 0 -#define SH_FSB_RESET_STATUS_RESET_IN_PROGRESS_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_FSB_SYMMETRIC_AGENT_STATUS" */ -/* FSB Symmetric Agent Status */ -/* ==================================================================== */ - -#define SH_FSB_SYMMETRIC_AGENT_STATUS 0x0000000120020080 -#define SH_FSB_SYMMETRIC_AGENT_STATUS_MASK 0x0000000000000007 -#define SH_FSB_SYMMETRIC_AGENT_STATUS_INIT 0x0000000000000000 - -/* SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_0_ACTIVE */ -/* Description: CPU 0 Active. */ -#define SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_0_ACTIVE_SHFT 0 -#define SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_0_ACTIVE_MASK 0x0000000000000001 - -/* SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_1_ACTIVE */ -/* Description: CPU 1 Active. */ -#define SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_1_ACTIVE_SHFT 1 -#define SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_1_ACTIVE_MASK 0x0000000000000002 - -/* SH_FSB_SYMMETRIC_AGENT_STATUS_CPUS_READY */ -/* Description: The Processors are Ready */ -#define SH_FSB_SYMMETRIC_AGENT_STATUS_CPUS_READY_SHFT 2 -#define SH_FSB_SYMMETRIC_AGENT_STATUS_CPUS_READY_MASK 0x0000000000000004 - -/* ==================================================================== */ -/* Register "SH_GFX_CREDIT_COUNT_0" */ -/* Graphics-write Credit Count for CPU 0 */ -/* ==================================================================== */ - -#define SH_GFX_CREDIT_COUNT_0 0x0000000120030000 -#define SH_GFX_CREDIT_COUNT_0_MASK 0x80000000000fffff -#define SH_GFX_CREDIT_COUNT_0_INIT 0x000000000000003f - -/* SH_GFX_CREDIT_COUNT_0_COUNT */ -/* Description: Credit Count */ -#define SH_GFX_CREDIT_COUNT_0_COUNT_SHFT 0 -#define SH_GFX_CREDIT_COUNT_0_COUNT_MASK 0x00000000000fffff - -/* SH_GFX_CREDIT_COUNT_0_RESET_GFX_STATE */ -/* Description: Reset GFX state */ -#define SH_GFX_CREDIT_COUNT_0_RESET_GFX_STATE_SHFT 63 -#define SH_GFX_CREDIT_COUNT_0_RESET_GFX_STATE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_GFX_CREDIT_COUNT_1" */ -/* Graphics-write Credit Count for CPU 1 */ -/* ==================================================================== */ - -#define SH_GFX_CREDIT_COUNT_1 0x0000000120030080 -#define SH_GFX_CREDIT_COUNT_1_MASK 0x80000000000fffff -#define SH_GFX_CREDIT_COUNT_1_INIT 0x000000000000003f - -/* SH_GFX_CREDIT_COUNT_1_COUNT */ -/* Description: Credit Count */ -#define SH_GFX_CREDIT_COUNT_1_COUNT_SHFT 0 -#define SH_GFX_CREDIT_COUNT_1_COUNT_MASK 0x00000000000fffff - -/* SH_GFX_CREDIT_COUNT_1_RESET_GFX_STATE */ -/* Description: Reset GFX state */ -#define SH_GFX_CREDIT_COUNT_1_RESET_GFX_STATE_SHFT 63 -#define SH_GFX_CREDIT_COUNT_1_RESET_GFX_STATE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_GFX_MODE_CNTRL_0" */ -/* Graphics credit mode amd message ordering for CPU 0 */ -/* ==================================================================== */ - -#define SH_GFX_MODE_CNTRL_0 0x0000000120030100 -#define SH_GFX_MODE_CNTRL_0_MASK 0x0000000000000007 -#define SH_GFX_MODE_CNTRL_0_INIT 0x0000000000000003 - -/* SH_GFX_MODE_CNTRL_0_DWORD_CREDITS */ -/* Description: GFX credits are tracked by D-words */ -#define SH_GFX_MODE_CNTRL_0_DWORD_CREDITS_SHFT 0 -#define SH_GFX_MODE_CNTRL_0_DWORD_CREDITS_MASK 0x0000000000000001 - -/* SH_GFX_MODE_CNTRL_0_MIXED_MODE_CREDITS */ -/* Description: GFX credits are tracked by D-words and messages */ -#define SH_GFX_MODE_CNTRL_0_MIXED_MODE_CREDITS_SHFT 1 -#define SH_GFX_MODE_CNTRL_0_MIXED_MODE_CREDITS_MASK 0x0000000000000002 - -/* SH_GFX_MODE_CNTRL_0_RELAXED_ORDERING */ -/* Description: GFX message routing order */ -#define SH_GFX_MODE_CNTRL_0_RELAXED_ORDERING_SHFT 2 -#define SH_GFX_MODE_CNTRL_0_RELAXED_ORDERING_MASK 0x0000000000000004 - -/* ==================================================================== */ -/* Register "SH_GFX_MODE_CNTRL_1" */ -/* Graphics credit mode amd message ordering for CPU 1 */ -/* ==================================================================== */ - -#define SH_GFX_MODE_CNTRL_1 0x0000000120030180 -#define SH_GFX_MODE_CNTRL_1_MASK 0x0000000000000007 -#define SH_GFX_MODE_CNTRL_1_INIT 0x0000000000000003 - -/* SH_GFX_MODE_CNTRL_1_DWORD_CREDITS */ -/* Description: GFX credits are tracked by D-words */ -#define SH_GFX_MODE_CNTRL_1_DWORD_CREDITS_SHFT 0 -#define SH_GFX_MODE_CNTRL_1_DWORD_CREDITS_MASK 0x0000000000000001 - -/* SH_GFX_MODE_CNTRL_1_MIXED_MODE_CREDITS */ -/* Description: GFX credits are tracked by D-words and messages */ -#define SH_GFX_MODE_CNTRL_1_MIXED_MODE_CREDITS_SHFT 1 -#define SH_GFX_MODE_CNTRL_1_MIXED_MODE_CREDITS_MASK 0x0000000000000002 - -/* SH_GFX_MODE_CNTRL_1_RELAXED_ORDERING */ -/* Description: GFX message routing order */ -#define SH_GFX_MODE_CNTRL_1_RELAXED_ORDERING_SHFT 2 -#define SH_GFX_MODE_CNTRL_1_RELAXED_ORDERING_MASK 0x0000000000000004 - -/* ==================================================================== */ -/* Register "SH_GFX_SKID_CREDIT_COUNT_0" */ -/* Graphics-write Skid Credit Count for CPU 0 */ -/* ==================================================================== */ - -#define SH_GFX_SKID_CREDIT_COUNT_0 0x0000000120030200 -#define SH_GFX_SKID_CREDIT_COUNT_0_MASK 0x00000000000fffff -#define SH_GFX_SKID_CREDIT_COUNT_0_INIT 0x0000000000000030 - -/* SH_GFX_SKID_CREDIT_COUNT_0_SKID */ -/* Description: Skid Credit Count */ -#define SH_GFX_SKID_CREDIT_COUNT_0_SKID_SHFT 0 -#define SH_GFX_SKID_CREDIT_COUNT_0_SKID_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_GFX_SKID_CREDIT_COUNT_1" */ -/* Graphics-write Skid Credit Count for CPU 1 */ -/* ==================================================================== */ - -#define SH_GFX_SKID_CREDIT_COUNT_1 0x0000000120030280 -#define SH_GFX_SKID_CREDIT_COUNT_1_MASK 0x00000000000fffff -#define SH_GFX_SKID_CREDIT_COUNT_1_INIT 0x0000000000000030 - -/* SH_GFX_SKID_CREDIT_COUNT_1_SKID */ -/* Description: Skid Credit Count */ -#define SH_GFX_SKID_CREDIT_COUNT_1_SKID_SHFT 0 -#define SH_GFX_SKID_CREDIT_COUNT_1_SKID_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_GFX_STALL_LIMIT_0" */ -/* Graphics-write Stall Limit for CPU 0 */ -/* ==================================================================== */ - -#define SH_GFX_STALL_LIMIT_0 0x0000000120030300 -#define SH_GFX_STALL_LIMIT_0_MASK 0x0000000003ffffff -#define SH_GFX_STALL_LIMIT_0_INIT 0x0000000000010000 - -/* SH_GFX_STALL_LIMIT_0_LIMIT */ -/* Description: Graphics Stall Limit for CPU 0 */ -#define SH_GFX_STALL_LIMIT_0_LIMIT_SHFT 0 -#define SH_GFX_STALL_LIMIT_0_LIMIT_MASK 0x0000000003ffffff - -/* ==================================================================== */ -/* Register "SH_GFX_STALL_LIMIT_1" */ -/* Graphics-write Stall Limit for CPU 1 */ -/* ==================================================================== */ - -#define SH_GFX_STALL_LIMIT_1 0x0000000120030380 -#define SH_GFX_STALL_LIMIT_1_MASK 0x0000000003ffffff -#define SH_GFX_STALL_LIMIT_1_INIT 0x0000000000010000 - -/* SH_GFX_STALL_LIMIT_1_LIMIT */ -/* Description: Graphics Stall Limit for CPU 1 */ -#define SH_GFX_STALL_LIMIT_1_LIMIT_SHFT 0 -#define SH_GFX_STALL_LIMIT_1_LIMIT_MASK 0x0000000003ffffff - -/* ==================================================================== */ -/* Register "SH_GFX_STALL_TIMER_0" */ -/* Graphics-write Stall Timer for CPU 0 */ -/* ==================================================================== */ - -#define SH_GFX_STALL_TIMER_0 0x0000000120030400 -#define SH_GFX_STALL_TIMER_0_MASK 0x0000000003ffffff -#define SH_GFX_STALL_TIMER_0_INIT 0x0000000000000000 - -/* SH_GFX_STALL_TIMER_0_TIMER_VALUE */ -/* Description: Timer Value */ -#define SH_GFX_STALL_TIMER_0_TIMER_VALUE_SHFT 0 -#define SH_GFX_STALL_TIMER_0_TIMER_VALUE_MASK 0x0000000003ffffff - -/* ==================================================================== */ -/* Register "SH_GFX_STALL_TIMER_1" */ -/* Graphics-write Stall Timer for CPU 1 */ -/* ==================================================================== */ - -#define SH_GFX_STALL_TIMER_1 0x0000000120030480 -#define SH_GFX_STALL_TIMER_1_MASK 0x0000000003ffffff -#define SH_GFX_STALL_TIMER_1_INIT 0x0000000000000000 - -/* SH_GFX_STALL_TIMER_1_TIMER_VALUE */ -/* Description: Timer Value */ -#define SH_GFX_STALL_TIMER_1_TIMER_VALUE_SHFT 0 -#define SH_GFX_STALL_TIMER_1_TIMER_VALUE_MASK 0x0000000003ffffff - -/* ==================================================================== */ -/* Register "SH_GFX_WINDOW_0" */ -/* Graphics-write Window for CPU 0 */ -/* ==================================================================== */ - -#define SH_GFX_WINDOW_0 0x0000000120030500 -#define SH_GFX_WINDOW_0_MASK 0x8000000fff000000 -#define SH_GFX_WINDOW_0_INIT 0x0000000000000000 - -/* SH_GFX_WINDOW_0_BASE_ADDR */ -/* Description: Base Address for CPU 0's 16 MB Graphics Window */ -#define SH_GFX_WINDOW_0_BASE_ADDR_SHFT 24 -#define SH_GFX_WINDOW_0_BASE_ADDR_MASK 0x0000000fff000000 - -/* SH_GFX_WINDOW_0_GFX_WINDOW_EN */ -/* Description: Graphics Window Enabled */ -#define SH_GFX_WINDOW_0_GFX_WINDOW_EN_SHFT 63 -#define SH_GFX_WINDOW_0_GFX_WINDOW_EN_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_GFX_WINDOW_1" */ -/* Graphics-write Window for CPU 1 */ -/* ==================================================================== */ - -#define SH_GFX_WINDOW_1 0x0000000120030580 -#define SH_GFX_WINDOW_1_MASK 0x8000000fff000000 -#define SH_GFX_WINDOW_1_INIT 0x0000000000000000 - -/* SH_GFX_WINDOW_1_BASE_ADDR */ -/* Description: Base Address for CPU 1's 16 MB Graphics Window */ -#define SH_GFX_WINDOW_1_BASE_ADDR_SHFT 24 -#define SH_GFX_WINDOW_1_BASE_ADDR_MASK 0x0000000fff000000 - -/* SH_GFX_WINDOW_1_GFX_WINDOW_EN */ -/* Description: Graphics Window Enabled */ -#define SH_GFX_WINDOW_1_GFX_WINDOW_EN_SHFT 63 -#define SH_GFX_WINDOW_1_GFX_WINDOW_EN_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_GFX_INTERRUPT_TIMER_LIMIT_0" */ -/* Graphics-write Interrupt Limit for CPU 0 */ -/* ==================================================================== */ - -#define SH_GFX_INTERRUPT_TIMER_LIMIT_0 0x0000000120030600 -#define SH_GFX_INTERRUPT_TIMER_LIMIT_0_MASK 0x00000000000000ff -#define SH_GFX_INTERRUPT_TIMER_LIMIT_0_INIT 0x0000000000000040 - -/* SH_GFX_INTERRUPT_TIMER_LIMIT_0_INTERRUPT_TIMER_LIMIT */ -/* Description: GFX Interrupt Timer Limit */ -#define SH_GFX_INTERRUPT_TIMER_LIMIT_0_INTERRUPT_TIMER_LIMIT_SHFT 0 -#define SH_GFX_INTERRUPT_TIMER_LIMIT_0_INTERRUPT_TIMER_LIMIT_MASK 0x00000000000000ff - -/* ==================================================================== */ -/* Register "SH_GFX_INTERRUPT_TIMER_LIMIT_1" */ -/* Graphics-write Interrupt Limit for CPU 1 */ -/* ==================================================================== */ - -#define SH_GFX_INTERRUPT_TIMER_LIMIT_1 0x0000000120030680 -#define SH_GFX_INTERRUPT_TIMER_LIMIT_1_MASK 0x00000000000000ff -#define SH_GFX_INTERRUPT_TIMER_LIMIT_1_INIT 0x0000000000000040 - -/* SH_GFX_INTERRUPT_TIMER_LIMIT_1_INTERRUPT_TIMER_LIMIT */ -/* Description: GFX Interrupt Timer Limit */ -#define SH_GFX_INTERRUPT_TIMER_LIMIT_1_INTERRUPT_TIMER_LIMIT_SHFT 0 -#define SH_GFX_INTERRUPT_TIMER_LIMIT_1_INTERRUPT_TIMER_LIMIT_MASK 0x00000000000000ff - -/* ==================================================================== */ -/* Register "SH_GFX_WRITE_STATUS_0" */ -/* Graphics Write Status for CPU 0 */ -/* ==================================================================== */ - -#define SH_GFX_WRITE_STATUS_0 0x0000000120040000 -#define SH_GFX_WRITE_STATUS_0_MASK 0x8000000000000001 -#define SH_GFX_WRITE_STATUS_0_INIT 0x0000000000000000 - -/* SH_GFX_WRITE_STATUS_0_BUSY */ -/* Description: Busy */ -#define SH_GFX_WRITE_STATUS_0_BUSY_SHFT 0 -#define SH_GFX_WRITE_STATUS_0_BUSY_MASK 0x0000000000000001 - -/* SH_GFX_WRITE_STATUS_0_RE_ENABLE_GFX_STALL */ -/* Description: Re-enable GFX stall logic for this processor */ -#define SH_GFX_WRITE_STATUS_0_RE_ENABLE_GFX_STALL_SHFT 63 -#define SH_GFX_WRITE_STATUS_0_RE_ENABLE_GFX_STALL_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_GFX_WRITE_STATUS_1" */ -/* Graphics Write Status for CPU 1 */ -/* ==================================================================== */ - -#define SH_GFX_WRITE_STATUS_1 0x0000000120040080 -#define SH_GFX_WRITE_STATUS_1_MASK 0x8000000000000001 -#define SH_GFX_WRITE_STATUS_1_INIT 0x0000000000000000 - -/* SH_GFX_WRITE_STATUS_1_BUSY */ -/* Description: Busy */ -#define SH_GFX_WRITE_STATUS_1_BUSY_SHFT 0 -#define SH_GFX_WRITE_STATUS_1_BUSY_MASK 0x0000000000000001 - -/* SH_GFX_WRITE_STATUS_1_RE_ENABLE_GFX_STALL */ -/* Description: Re-enable GFX stall logic for this processor */ -#define SH_GFX_WRITE_STATUS_1_RE_ENABLE_GFX_STALL_SHFT 63 -#define SH_GFX_WRITE_STATUS_1_RE_ENABLE_GFX_STALL_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_II_INT0" */ -/* SHub II Interrupt 0 Registers */ -/* ==================================================================== */ - -#define SH_II_INT0 0x0000000110000000 -#define SH_II_INT0_MASK 0x00000000000001ff -#define SH_II_INT0_INIT 0x0000000000000000 - -/* SH_II_INT0_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_II_INT0_IDX_SHFT 0 -#define SH_II_INT0_IDX_MASK 0x00000000000000ff - -/* SH_II_INT0_SEND */ -/* Description: Send Interrupt Message to PI, This generates a puls */ -#define SH_II_INT0_SEND_SHFT 8 -#define SH_II_INT0_SEND_MASK 0x0000000000000100 - -/* ==================================================================== */ -/* Register "SH_II_INT0_CONFIG" */ -/* SHub II Interrupt 0 Config Registers */ -/* ==================================================================== */ - -#define SH_II_INT0_CONFIG 0x0000000110000080 -#define SH_II_INT0_CONFIG_MASK 0x0003ffffffefffff -#define SH_II_INT0_CONFIG_INIT 0x0000000000000000 - -/* SH_II_INT0_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_II_INT0_CONFIG_TYPE_SHFT 0 -#define SH_II_INT0_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_II_INT0_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_II_INT0_CONFIG_AGT_SHFT 3 -#define SH_II_INT0_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_II_INT0_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_II_INT0_CONFIG_PID_SHFT 4 -#define SH_II_INT0_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_II_INT0_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_II_INT0_CONFIG_BASE_SHFT 21 -#define SH_II_INT0_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* ==================================================================== */ -/* Register "SH_II_INT0_ENABLE" */ -/* SHub II Interrupt 0 Enable Registers */ -/* ==================================================================== */ - -#define SH_II_INT0_ENABLE 0x0000000110000200 -#define SH_II_INT0_ENABLE_MASK 0x0000000000000001 -#define SH_II_INT0_ENABLE_INIT 0x0000000000000000 - -/* SH_II_INT0_ENABLE_II_ENABLE */ -/* Description: Enable II Interrupt */ -#define SH_II_INT0_ENABLE_II_ENABLE_SHFT 0 -#define SH_II_INT0_ENABLE_II_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_II_INT1" */ -/* SHub II Interrupt 1 Registers */ -/* ==================================================================== */ - -#define SH_II_INT1 0x0000000110000100 -#define SH_II_INT1_MASK 0x00000000000001ff -#define SH_II_INT1_INIT 0x0000000000000000 - -/* SH_II_INT1_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_II_INT1_IDX_SHFT 0 -#define SH_II_INT1_IDX_MASK 0x00000000000000ff - -/* SH_II_INT1_SEND */ -/* Description: Send Interrupt Message to PI, This generates a puls */ -#define SH_II_INT1_SEND_SHFT 8 -#define SH_II_INT1_SEND_MASK 0x0000000000000100 - -/* ==================================================================== */ -/* Register "SH_II_INT1_CONFIG" */ -/* SHub II Interrupt 1 Config Registers */ -/* ==================================================================== */ - -#define SH_II_INT1_CONFIG 0x0000000110000180 -#define SH_II_INT1_CONFIG_MASK 0x0003ffffffefffff -#define SH_II_INT1_CONFIG_INIT 0x0000000000000000 - -/* SH_II_INT1_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_II_INT1_CONFIG_TYPE_SHFT 0 -#define SH_II_INT1_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_II_INT1_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_II_INT1_CONFIG_AGT_SHFT 3 -#define SH_II_INT1_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_II_INT1_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_II_INT1_CONFIG_PID_SHFT 4 -#define SH_II_INT1_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_II_INT1_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_II_INT1_CONFIG_BASE_SHFT 21 -#define SH_II_INT1_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* ==================================================================== */ -/* Register "SH_II_INT1_ENABLE" */ -/* SHub II Interrupt 1 Enable Registers */ -/* ==================================================================== */ - -#define SH_II_INT1_ENABLE 0x0000000110000280 -#define SH_II_INT1_ENABLE_MASK 0x0000000000000001 -#define SH_II_INT1_ENABLE_INIT 0x0000000000000000 - -/* SH_II_INT1_ENABLE_II_ENABLE */ -/* Description: Enable II 1 Interrupt */ -#define SH_II_INT1_ENABLE_II_ENABLE_SHFT 0 -#define SH_II_INT1_ENABLE_II_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_INT_NODE_ID_CONFIG" */ -/* SHub Interrupt Node ID Configuration */ -/* ==================================================================== */ - -#define SH_INT_NODE_ID_CONFIG 0x0000000110000300 -#define SH_INT_NODE_ID_CONFIG_MASK 0x0000000000000fff -#define SH_INT_NODE_ID_CONFIG_INIT 0x0000000000000000 - -/* SH_INT_NODE_ID_CONFIG_NODE_ID */ -/* Description: Node ID for interrupt messages */ -#define SH_INT_NODE_ID_CONFIG_NODE_ID_SHFT 0 -#define SH_INT_NODE_ID_CONFIG_NODE_ID_MASK 0x00000000000007ff - -/* SH_INT_NODE_ID_CONFIG_ID_SEL */ -/* Description: Select node id for interrupt messages */ -#define SH_INT_NODE_ID_CONFIG_ID_SEL_SHFT 11 -#define SH_INT_NODE_ID_CONFIG_ID_SEL_MASK 0x0000000000000800 - -/* ==================================================================== */ -/* Register "SH_IPI_INT" */ -/* SHub Inter-Processor Interrupt Registers */ -/* ==================================================================== */ - -#define SH_IPI_INT 0x0000000110000380 -#define SH_IPI_INT_MASK 0x8ff3ffffffefffff -#define SH_IPI_INT_INIT 0x0000000000000000 - -/* SH_IPI_INT_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_IPI_INT_TYPE_SHFT 0 -#define SH_IPI_INT_TYPE_MASK 0x0000000000000007 - -/* SH_IPI_INT_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_IPI_INT_AGT_SHFT 3 -#define SH_IPI_INT_AGT_MASK 0x0000000000000008 - -/* SH_IPI_INT_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_IPI_INT_PID_SHFT 4 -#define SH_IPI_INT_PID_MASK 0x00000000000ffff0 - -/* SH_IPI_INT_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_IPI_INT_BASE_SHFT 21 -#define SH_IPI_INT_BASE_MASK 0x0003ffffffe00000 - -/* SH_IPI_INT_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_IPI_INT_IDX_SHFT 52 -#define SH_IPI_INT_IDX_MASK 0x0ff0000000000000 - -/* SH_IPI_INT_SEND */ -/* Description: Send Interrupt Message to PI, This generates a puls */ -#define SH_IPI_INT_SEND_SHFT 63 -#define SH_IPI_INT_SEND_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_IPI_INT_ENABLE" */ -/* SHub Inter-Processor Interrupt Enable Registers */ -/* ==================================================================== */ - -#define SH_IPI_INT_ENABLE 0x0000000110000400 -#define SH_IPI_INT_ENABLE_MASK 0x0000000000000001 -#define SH_IPI_INT_ENABLE_INIT 0x0000000000000000 - -/* SH_IPI_INT_ENABLE_PIO_ENABLE */ -/* Description: Enable PIO Interrupt */ -#define SH_IPI_INT_ENABLE_PIO_ENABLE_SHFT 0 -#define SH_IPI_INT_ENABLE_PIO_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT0_CONFIG" */ -/* SHub Local Interrupt 0 Registers */ -/* ==================================================================== */ - -#define SH_LOCAL_INT0_CONFIG 0x0000000110000480 -#define SH_LOCAL_INT0_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_LOCAL_INT0_CONFIG_INIT 0x0000000000000000 - -/* SH_LOCAL_INT0_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_LOCAL_INT0_CONFIG_TYPE_SHFT 0 -#define SH_LOCAL_INT0_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_LOCAL_INT0_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_LOCAL_INT0_CONFIG_AGT_SHFT 3 -#define SH_LOCAL_INT0_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_LOCAL_INT0_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_LOCAL_INT0_CONFIG_PID_SHFT 4 -#define SH_LOCAL_INT0_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_LOCAL_INT0_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_LOCAL_INT0_CONFIG_BASE_SHFT 21 -#define SH_LOCAL_INT0_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_LOCAL_INT0_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_LOCAL_INT0_CONFIG_IDX_SHFT 52 -#define SH_LOCAL_INT0_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT0_ENABLE" */ -/* SHub Local Interrupt 0 Enable */ -/* ==================================================================== */ - -#define SH_LOCAL_INT0_ENABLE 0x0000000110000500 -#define SH_LOCAL_INT0_ENABLE_MASK 0x000000000000f7ff -#define SH_LOCAL_INT0_ENABLE_INIT 0x0000000000000000 - -/* SH_LOCAL_INT0_ENABLE_PI_HW_INT */ -/* Description: Enable PI Hardware interrupt */ -#define SH_LOCAL_INT0_ENABLE_PI_HW_INT_SHFT 0 -#define SH_LOCAL_INT0_ENABLE_PI_HW_INT_MASK 0x0000000000000001 - -/* SH_LOCAL_INT0_ENABLE_MD_HW_INT */ -/* Description: Enable MD Hardware interrupt */ -#define SH_LOCAL_INT0_ENABLE_MD_HW_INT_SHFT 1 -#define SH_LOCAL_INT0_ENABLE_MD_HW_INT_MASK 0x0000000000000002 - -/* SH_LOCAL_INT0_ENABLE_XN_HW_INT */ -/* Description: Enable XN Hardware interrupt */ -#define SH_LOCAL_INT0_ENABLE_XN_HW_INT_SHFT 2 -#define SH_LOCAL_INT0_ENABLE_XN_HW_INT_MASK 0x0000000000000004 - -/* SH_LOCAL_INT0_ENABLE_LB_HW_INT */ -/* Description: Enable LB Hardware interrupt */ -#define SH_LOCAL_INT0_ENABLE_LB_HW_INT_SHFT 3 -#define SH_LOCAL_INT0_ENABLE_LB_HW_INT_MASK 0x0000000000000008 - -/* SH_LOCAL_INT0_ENABLE_II_HW_INT */ -/* Description: Enable II wrapper Hardware interrupt */ -#define SH_LOCAL_INT0_ENABLE_II_HW_INT_SHFT 4 -#define SH_LOCAL_INT0_ENABLE_II_HW_INT_MASK 0x0000000000000010 - -/* SH_LOCAL_INT0_ENABLE_PI_CE_INT */ -/* Description: Enable PI Correctable Error Interrupt */ -#define SH_LOCAL_INT0_ENABLE_PI_CE_INT_SHFT 5 -#define SH_LOCAL_INT0_ENABLE_PI_CE_INT_MASK 0x0000000000000020 - -/* SH_LOCAL_INT0_ENABLE_MD_CE_INT */ -/* Description: Enable MD Correctable Error Interrupt */ -#define SH_LOCAL_INT0_ENABLE_MD_CE_INT_SHFT 6 -#define SH_LOCAL_INT0_ENABLE_MD_CE_INT_MASK 0x0000000000000040 - -/* SH_LOCAL_INT0_ENABLE_XN_CE_INT */ -/* Description: Enable XN Correctable Error Interrupt */ -#define SH_LOCAL_INT0_ENABLE_XN_CE_INT_SHFT 7 -#define SH_LOCAL_INT0_ENABLE_XN_CE_INT_MASK 0x0000000000000080 - -/* SH_LOCAL_INT0_ENABLE_PI_UCE_INT */ -/* Description: Enable PI Correctable Error Interrupt */ -#define SH_LOCAL_INT0_ENABLE_PI_UCE_INT_SHFT 8 -#define SH_LOCAL_INT0_ENABLE_PI_UCE_INT_MASK 0x0000000000000100 - -/* SH_LOCAL_INT0_ENABLE_MD_UCE_INT */ -/* Description: Enable MD Correctable Error Interrupt */ -#define SH_LOCAL_INT0_ENABLE_MD_UCE_INT_SHFT 9 -#define SH_LOCAL_INT0_ENABLE_MD_UCE_INT_MASK 0x0000000000000200 - -/* SH_LOCAL_INT0_ENABLE_XN_UCE_INT */ -/* Description: Enable XN Correctable Error Interrupt */ -#define SH_LOCAL_INT0_ENABLE_XN_UCE_INT_SHFT 10 -#define SH_LOCAL_INT0_ENABLE_XN_UCE_INT_MASK 0x0000000000000400 - -/* SH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT */ -/* Description: Enable System Shutdown Interrupt */ -#define SH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12 -#define SH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000 - -/* SH_LOCAL_INT0_ENABLE_UART_INT */ -/* Description: Enable Junk Bus UART Interrupt */ -#define SH_LOCAL_INT0_ENABLE_UART_INT_SHFT 13 -#define SH_LOCAL_INT0_ENABLE_UART_INT_MASK 0x0000000000002000 - -/* SH_LOCAL_INT0_ENABLE_L1_NMI_INT */ -/* Description: Enable L1 Controller NMI Interrupt */ -#define SH_LOCAL_INT0_ENABLE_L1_NMI_INT_SHFT 14 -#define SH_LOCAL_INT0_ENABLE_L1_NMI_INT_MASK 0x0000000000004000 - -/* SH_LOCAL_INT0_ENABLE_STOP_CLOCK */ -/* Description: Stop Clock Interrupt */ -#define SH_LOCAL_INT0_ENABLE_STOP_CLOCK_SHFT 15 -#define SH_LOCAL_INT0_ENABLE_STOP_CLOCK_MASK 0x0000000000008000 - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT1_CONFIG" */ -/* SHub Local Interrupt 1 Registers */ -/* ==================================================================== */ - -#define SH_LOCAL_INT1_CONFIG 0x0000000110000580 -#define SH_LOCAL_INT1_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_LOCAL_INT1_CONFIG_INIT 0x0000000000000000 - -/* SH_LOCAL_INT1_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_LOCAL_INT1_CONFIG_TYPE_SHFT 0 -#define SH_LOCAL_INT1_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_LOCAL_INT1_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_LOCAL_INT1_CONFIG_AGT_SHFT 3 -#define SH_LOCAL_INT1_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_LOCAL_INT1_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_LOCAL_INT1_CONFIG_PID_SHFT 4 -#define SH_LOCAL_INT1_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_LOCAL_INT1_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_LOCAL_INT1_CONFIG_BASE_SHFT 21 -#define SH_LOCAL_INT1_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_LOCAL_INT1_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_LOCAL_INT1_CONFIG_IDX_SHFT 52 -#define SH_LOCAL_INT1_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT1_ENABLE" */ -/* SHub Local Interrupt 1 Enable */ -/* ==================================================================== */ - -#define SH_LOCAL_INT1_ENABLE 0x0000000110000600 -#define SH_LOCAL_INT1_ENABLE_MASK 0x000000000000f7ff -#define SH_LOCAL_INT1_ENABLE_INIT 0x0000000000000000 - -/* SH_LOCAL_INT1_ENABLE_PI_HW_INT */ -/* Description: Enable PI Hardware interrupt */ -#define SH_LOCAL_INT1_ENABLE_PI_HW_INT_SHFT 0 -#define SH_LOCAL_INT1_ENABLE_PI_HW_INT_MASK 0x0000000000000001 - -/* SH_LOCAL_INT1_ENABLE_MD_HW_INT */ -/* Description: Enable MD Hardware interrupt */ -#define SH_LOCAL_INT1_ENABLE_MD_HW_INT_SHFT 1 -#define SH_LOCAL_INT1_ENABLE_MD_HW_INT_MASK 0x0000000000000002 - -/* SH_LOCAL_INT1_ENABLE_XN_HW_INT */ -/* Description: Enable XN Hardware interrupt */ -#define SH_LOCAL_INT1_ENABLE_XN_HW_INT_SHFT 2 -#define SH_LOCAL_INT1_ENABLE_XN_HW_INT_MASK 0x0000000000000004 - -/* SH_LOCAL_INT1_ENABLE_LB_HW_INT */ -/* Description: Enable LB Hardware interrupt */ -#define SH_LOCAL_INT1_ENABLE_LB_HW_INT_SHFT 3 -#define SH_LOCAL_INT1_ENABLE_LB_HW_INT_MASK 0x0000000000000008 - -/* SH_LOCAL_INT1_ENABLE_II_HW_INT */ -/* Description: Enable II wrapper Hardware interrupt */ -#define SH_LOCAL_INT1_ENABLE_II_HW_INT_SHFT 4 -#define SH_LOCAL_INT1_ENABLE_II_HW_INT_MASK 0x0000000000000010 - -/* SH_LOCAL_INT1_ENABLE_PI_CE_INT */ -/* Description: Enable PI Correctable Error Interrupt */ -#define SH_LOCAL_INT1_ENABLE_PI_CE_INT_SHFT 5 -#define SH_LOCAL_INT1_ENABLE_PI_CE_INT_MASK 0x0000000000000020 - -/* SH_LOCAL_INT1_ENABLE_MD_CE_INT */ -/* Description: Enable MD Correctable Error Interrupt */ -#define SH_LOCAL_INT1_ENABLE_MD_CE_INT_SHFT 6 -#define SH_LOCAL_INT1_ENABLE_MD_CE_INT_MASK 0x0000000000000040 - -/* SH_LOCAL_INT1_ENABLE_XN_CE_INT */ -/* Description: Enable XN Correctable Error Interrupt */ -#define SH_LOCAL_INT1_ENABLE_XN_CE_INT_SHFT 7 -#define SH_LOCAL_INT1_ENABLE_XN_CE_INT_MASK 0x0000000000000080 - -/* SH_LOCAL_INT1_ENABLE_PI_UCE_INT */ -/* Description: Enable PI Correctable Error Interrupt */ -#define SH_LOCAL_INT1_ENABLE_PI_UCE_INT_SHFT 8 -#define SH_LOCAL_INT1_ENABLE_PI_UCE_INT_MASK 0x0000000000000100 - -/* SH_LOCAL_INT1_ENABLE_MD_UCE_INT */ -/* Description: Enable MD Correctable Error Interrupt */ -#define SH_LOCAL_INT1_ENABLE_MD_UCE_INT_SHFT 9 -#define SH_LOCAL_INT1_ENABLE_MD_UCE_INT_MASK 0x0000000000000200 - -/* SH_LOCAL_INT1_ENABLE_XN_UCE_INT */ -/* Description: Enable XN Correctable Error Interrupt */ -#define SH_LOCAL_INT1_ENABLE_XN_UCE_INT_SHFT 10 -#define SH_LOCAL_INT1_ENABLE_XN_UCE_INT_MASK 0x0000000000000400 - -/* SH_LOCAL_INT1_ENABLE_SYSTEM_SHUTDOWN_INT */ -/* Description: Enable System Shutdown Interrupt */ -#define SH_LOCAL_INT1_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12 -#define SH_LOCAL_INT1_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000 - -/* SH_LOCAL_INT1_ENABLE_UART_INT */ -/* Description: Enable Junk Bus UART Interrupt */ -#define SH_LOCAL_INT1_ENABLE_UART_INT_SHFT 13 -#define SH_LOCAL_INT1_ENABLE_UART_INT_MASK 0x0000000000002000 - -/* SH_LOCAL_INT1_ENABLE_L1_NMI_INT */ -/* Description: Enable L1 Controller NMI Interrupt */ -#define SH_LOCAL_INT1_ENABLE_L1_NMI_INT_SHFT 14 -#define SH_LOCAL_INT1_ENABLE_L1_NMI_INT_MASK 0x0000000000004000 - -/* SH_LOCAL_INT1_ENABLE_STOP_CLOCK */ -/* Description: Stop Clock Interrupt */ -#define SH_LOCAL_INT1_ENABLE_STOP_CLOCK_SHFT 15 -#define SH_LOCAL_INT1_ENABLE_STOP_CLOCK_MASK 0x0000000000008000 - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT2_CONFIG" */ -/* SHub Local Interrupt 2 Registers */ -/* ==================================================================== */ - -#define SH_LOCAL_INT2_CONFIG 0x0000000110000680 -#define SH_LOCAL_INT2_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_LOCAL_INT2_CONFIG_INIT 0x0000000000000000 - -/* SH_LOCAL_INT2_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_LOCAL_INT2_CONFIG_TYPE_SHFT 0 -#define SH_LOCAL_INT2_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_LOCAL_INT2_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_LOCAL_INT2_CONFIG_AGT_SHFT 3 -#define SH_LOCAL_INT2_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_LOCAL_INT2_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_LOCAL_INT2_CONFIG_PID_SHFT 4 -#define SH_LOCAL_INT2_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_LOCAL_INT2_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_LOCAL_INT2_CONFIG_BASE_SHFT 21 -#define SH_LOCAL_INT2_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_LOCAL_INT2_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_LOCAL_INT2_CONFIG_IDX_SHFT 52 -#define SH_LOCAL_INT2_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT2_ENABLE" */ -/* SHub Local Interrupt 2 Enable */ -/* ==================================================================== */ - -#define SH_LOCAL_INT2_ENABLE 0x0000000110000700 -#define SH_LOCAL_INT2_ENABLE_MASK 0x000000000000f7ff -#define SH_LOCAL_INT2_ENABLE_INIT 0x0000000000000000 - -/* SH_LOCAL_INT2_ENABLE_PI_HW_INT */ -/* Description: Enable PI Hardware interrupt */ -#define SH_LOCAL_INT2_ENABLE_PI_HW_INT_SHFT 0 -#define SH_LOCAL_INT2_ENABLE_PI_HW_INT_MASK 0x0000000000000001 - -/* SH_LOCAL_INT2_ENABLE_MD_HW_INT */ -/* Description: Enable MD Hardware interrupt */ -#define SH_LOCAL_INT2_ENABLE_MD_HW_INT_SHFT 1 -#define SH_LOCAL_INT2_ENABLE_MD_HW_INT_MASK 0x0000000000000002 - -/* SH_LOCAL_INT2_ENABLE_XN_HW_INT */ -/* Description: Enable XN Hardware interrupt */ -#define SH_LOCAL_INT2_ENABLE_XN_HW_INT_SHFT 2 -#define SH_LOCAL_INT2_ENABLE_XN_HW_INT_MASK 0x0000000000000004 - -/* SH_LOCAL_INT2_ENABLE_LB_HW_INT */ -/* Description: Enable LB Hardware interrupt */ -#define SH_LOCAL_INT2_ENABLE_LB_HW_INT_SHFT 3 -#define SH_LOCAL_INT2_ENABLE_LB_HW_INT_MASK 0x0000000000000008 - -/* SH_LOCAL_INT2_ENABLE_II_HW_INT */ -/* Description: Enable II wrapper Hardware interrupt */ -#define SH_LOCAL_INT2_ENABLE_II_HW_INT_SHFT 4 -#define SH_LOCAL_INT2_ENABLE_II_HW_INT_MASK 0x0000000000000010 - -/* SH_LOCAL_INT2_ENABLE_PI_CE_INT */ -/* Description: Enable PI Correctable Error Interrupt */ -#define SH_LOCAL_INT2_ENABLE_PI_CE_INT_SHFT 5 -#define SH_LOCAL_INT2_ENABLE_PI_CE_INT_MASK 0x0000000000000020 - -/* SH_LOCAL_INT2_ENABLE_MD_CE_INT */ -/* Description: Enable MD Correctable Error Interrupt */ -#define SH_LOCAL_INT2_ENABLE_MD_CE_INT_SHFT 6 -#define SH_LOCAL_INT2_ENABLE_MD_CE_INT_MASK 0x0000000000000040 - -/* SH_LOCAL_INT2_ENABLE_XN_CE_INT */ -/* Description: Enable XN Correctable Error Interrupt */ -#define SH_LOCAL_INT2_ENABLE_XN_CE_INT_SHFT 7 -#define SH_LOCAL_INT2_ENABLE_XN_CE_INT_MASK 0x0000000000000080 - -/* SH_LOCAL_INT2_ENABLE_PI_UCE_INT */ -/* Description: Enable PI Correctable Error Interrupt */ -#define SH_LOCAL_INT2_ENABLE_PI_UCE_INT_SHFT 8 -#define SH_LOCAL_INT2_ENABLE_PI_UCE_INT_MASK 0x0000000000000100 - -/* SH_LOCAL_INT2_ENABLE_MD_UCE_INT */ -/* Description: Enable MD Correctable Error Interrupt */ -#define SH_LOCAL_INT2_ENABLE_MD_UCE_INT_SHFT 9 -#define SH_LOCAL_INT2_ENABLE_MD_UCE_INT_MASK 0x0000000000000200 - -/* SH_LOCAL_INT2_ENABLE_XN_UCE_INT */ -/* Description: Enable XN Correctable Error Interrupt */ -#define SH_LOCAL_INT2_ENABLE_XN_UCE_INT_SHFT 10 -#define SH_LOCAL_INT2_ENABLE_XN_UCE_INT_MASK 0x0000000000000400 - -/* SH_LOCAL_INT2_ENABLE_SYSTEM_SHUTDOWN_INT */ -/* Description: Enable System Shutdown Interrupt */ -#define SH_LOCAL_INT2_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12 -#define SH_LOCAL_INT2_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000 - -/* SH_LOCAL_INT2_ENABLE_UART_INT */ -/* Description: Enable Junk Bus UART Interrupt */ -#define SH_LOCAL_INT2_ENABLE_UART_INT_SHFT 13 -#define SH_LOCAL_INT2_ENABLE_UART_INT_MASK 0x0000000000002000 - -/* SH_LOCAL_INT2_ENABLE_L1_NMI_INT */ -/* Description: Enable L1 Controller NMI Interrupt */ -#define SH_LOCAL_INT2_ENABLE_L1_NMI_INT_SHFT 14 -#define SH_LOCAL_INT2_ENABLE_L1_NMI_INT_MASK 0x0000000000004000 - -/* SH_LOCAL_INT2_ENABLE_STOP_CLOCK */ -/* Description: Stop Clock Interrupt */ -#define SH_LOCAL_INT2_ENABLE_STOP_CLOCK_SHFT 15 -#define SH_LOCAL_INT2_ENABLE_STOP_CLOCK_MASK 0x0000000000008000 - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT3_CONFIG" */ -/* SHub Local Interrupt 3 Registers */ -/* ==================================================================== */ - -#define SH_LOCAL_INT3_CONFIG 0x0000000110000780 -#define SH_LOCAL_INT3_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_LOCAL_INT3_CONFIG_INIT 0x0000000000000000 - -/* SH_LOCAL_INT3_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_LOCAL_INT3_CONFIG_TYPE_SHFT 0 -#define SH_LOCAL_INT3_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_LOCAL_INT3_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_LOCAL_INT3_CONFIG_AGT_SHFT 3 -#define SH_LOCAL_INT3_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_LOCAL_INT3_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_LOCAL_INT3_CONFIG_PID_SHFT 4 -#define SH_LOCAL_INT3_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_LOCAL_INT3_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_LOCAL_INT3_CONFIG_BASE_SHFT 21 -#define SH_LOCAL_INT3_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_LOCAL_INT3_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_LOCAL_INT3_CONFIG_IDX_SHFT 52 -#define SH_LOCAL_INT3_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT3_ENABLE" */ -/* SHub Local Interrupt 3 Enable */ -/* ==================================================================== */ - -#define SH_LOCAL_INT3_ENABLE 0x0000000110000800 -#define SH_LOCAL_INT3_ENABLE_MASK 0x000000000000f7ff -#define SH_LOCAL_INT3_ENABLE_INIT 0x0000000000000000 - -/* SH_LOCAL_INT3_ENABLE_PI_HW_INT */ -/* Description: Enable PI Hardware interrupt */ -#define SH_LOCAL_INT3_ENABLE_PI_HW_INT_SHFT 0 -#define SH_LOCAL_INT3_ENABLE_PI_HW_INT_MASK 0x0000000000000001 - -/* SH_LOCAL_INT3_ENABLE_MD_HW_INT */ -/* Description: Enable MD Hardware interrupt */ -#define SH_LOCAL_INT3_ENABLE_MD_HW_INT_SHFT 1 -#define SH_LOCAL_INT3_ENABLE_MD_HW_INT_MASK 0x0000000000000002 - -/* SH_LOCAL_INT3_ENABLE_XN_HW_INT */ -/* Description: Enable XN Hardware interrupt */ -#define SH_LOCAL_INT3_ENABLE_XN_HW_INT_SHFT 2 -#define SH_LOCAL_INT3_ENABLE_XN_HW_INT_MASK 0x0000000000000004 - -/* SH_LOCAL_INT3_ENABLE_LB_HW_INT */ -/* Description: Enable LB Hardware interrupt */ -#define SH_LOCAL_INT3_ENABLE_LB_HW_INT_SHFT 3 -#define SH_LOCAL_INT3_ENABLE_LB_HW_INT_MASK 0x0000000000000008 - -/* SH_LOCAL_INT3_ENABLE_II_HW_INT */ -/* Description: Enable II wrapper Hardware interrupt */ -#define SH_LOCAL_INT3_ENABLE_II_HW_INT_SHFT 4 -#define SH_LOCAL_INT3_ENABLE_II_HW_INT_MASK 0x0000000000000010 - -/* SH_LOCAL_INT3_ENABLE_PI_CE_INT */ -/* Description: Enable PI Correctable Error Interrupt */ -#define SH_LOCAL_INT3_ENABLE_PI_CE_INT_SHFT 5 -#define SH_LOCAL_INT3_ENABLE_PI_CE_INT_MASK 0x0000000000000020 - -/* SH_LOCAL_INT3_ENABLE_MD_CE_INT */ -/* Description: Enable MD Correctable Error Interrupt */ -#define SH_LOCAL_INT3_ENABLE_MD_CE_INT_SHFT 6 -#define SH_LOCAL_INT3_ENABLE_MD_CE_INT_MASK 0x0000000000000040 - -/* SH_LOCAL_INT3_ENABLE_XN_CE_INT */ -/* Description: Enable XN Correctable Error Interrupt */ -#define SH_LOCAL_INT3_ENABLE_XN_CE_INT_SHFT 7 -#define SH_LOCAL_INT3_ENABLE_XN_CE_INT_MASK 0x0000000000000080 - -/* SH_LOCAL_INT3_ENABLE_PI_UCE_INT */ -/* Description: Enable PI Correctable Error Interrupt */ -#define SH_LOCAL_INT3_ENABLE_PI_UCE_INT_SHFT 8 -#define SH_LOCAL_INT3_ENABLE_PI_UCE_INT_MASK 0x0000000000000100 - -/* SH_LOCAL_INT3_ENABLE_MD_UCE_INT */ -/* Description: Enable MD Correctable Error Interrupt */ -#define SH_LOCAL_INT3_ENABLE_MD_UCE_INT_SHFT 9 -#define SH_LOCAL_INT3_ENABLE_MD_UCE_INT_MASK 0x0000000000000200 - -/* SH_LOCAL_INT3_ENABLE_XN_UCE_INT */ -/* Description: Enable XN Correctable Error Interrupt */ -#define SH_LOCAL_INT3_ENABLE_XN_UCE_INT_SHFT 10 -#define SH_LOCAL_INT3_ENABLE_XN_UCE_INT_MASK 0x0000000000000400 - -/* SH_LOCAL_INT3_ENABLE_SYSTEM_SHUTDOWN_INT */ -/* Description: Enable System Shutdown Interrupt */ -#define SH_LOCAL_INT3_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12 -#define SH_LOCAL_INT3_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000 - -/* SH_LOCAL_INT3_ENABLE_UART_INT */ -/* Description: Enable Junk Bus UART Interrupt */ -#define SH_LOCAL_INT3_ENABLE_UART_INT_SHFT 13 -#define SH_LOCAL_INT3_ENABLE_UART_INT_MASK 0x0000000000002000 - -/* SH_LOCAL_INT3_ENABLE_L1_NMI_INT */ -/* Description: Enable L1 Controller NMI Interrupt */ -#define SH_LOCAL_INT3_ENABLE_L1_NMI_INT_SHFT 14 -#define SH_LOCAL_INT3_ENABLE_L1_NMI_INT_MASK 0x0000000000004000 - -/* SH_LOCAL_INT3_ENABLE_STOP_CLOCK */ -/* Description: Stop Clock Interrupt */ -#define SH_LOCAL_INT3_ENABLE_STOP_CLOCK_SHFT 15 -#define SH_LOCAL_INT3_ENABLE_STOP_CLOCK_MASK 0x0000000000008000 - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT4_CONFIG" */ -/* SHub Local Interrupt 4 Registers */ -/* ==================================================================== */ - -#define SH_LOCAL_INT4_CONFIG 0x0000000110000880 -#define SH_LOCAL_INT4_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_LOCAL_INT4_CONFIG_INIT 0x0000000000000000 - -/* SH_LOCAL_INT4_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_LOCAL_INT4_CONFIG_TYPE_SHFT 0 -#define SH_LOCAL_INT4_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_LOCAL_INT4_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_LOCAL_INT4_CONFIG_AGT_SHFT 3 -#define SH_LOCAL_INT4_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_LOCAL_INT4_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_LOCAL_INT4_CONFIG_PID_SHFT 4 -#define SH_LOCAL_INT4_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_LOCAL_INT4_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_LOCAL_INT4_CONFIG_BASE_SHFT 21 -#define SH_LOCAL_INT4_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_LOCAL_INT4_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_LOCAL_INT4_CONFIG_IDX_SHFT 52 -#define SH_LOCAL_INT4_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT4_ENABLE" */ -/* SHub Local Interrupt 4 Enable */ -/* ==================================================================== */ - -#define SH_LOCAL_INT4_ENABLE 0x0000000110000900 -#define SH_LOCAL_INT4_ENABLE_MASK 0x000000000000f7ff -#define SH_LOCAL_INT4_ENABLE_INIT 0x0000000000000000 - -/* SH_LOCAL_INT4_ENABLE_PI_HW_INT */ -/* Description: Enable PI Hardware interrupt */ -#define SH_LOCAL_INT4_ENABLE_PI_HW_INT_SHFT 0 -#define SH_LOCAL_INT4_ENABLE_PI_HW_INT_MASK 0x0000000000000001 - -/* SH_LOCAL_INT4_ENABLE_MD_HW_INT */ -/* Description: Enable MD Hardware interrupt */ -#define SH_LOCAL_INT4_ENABLE_MD_HW_INT_SHFT 1 -#define SH_LOCAL_INT4_ENABLE_MD_HW_INT_MASK 0x0000000000000002 - -/* SH_LOCAL_INT4_ENABLE_XN_HW_INT */ -/* Description: Enable XN Hardware interrupt */ -#define SH_LOCAL_INT4_ENABLE_XN_HW_INT_SHFT 2 -#define SH_LOCAL_INT4_ENABLE_XN_HW_INT_MASK 0x0000000000000004 - -/* SH_LOCAL_INT4_ENABLE_LB_HW_INT */ -/* Description: Enable LB Hardware interrupt */ -#define SH_LOCAL_INT4_ENABLE_LB_HW_INT_SHFT 3 -#define SH_LOCAL_INT4_ENABLE_LB_HW_INT_MASK 0x0000000000000008 - -/* SH_LOCAL_INT4_ENABLE_II_HW_INT */ -/* Description: Enable II wrapper Hardware interrupt */ -#define SH_LOCAL_INT4_ENABLE_II_HW_INT_SHFT 4 -#define SH_LOCAL_INT4_ENABLE_II_HW_INT_MASK 0x0000000000000010 - -/* SH_LOCAL_INT4_ENABLE_PI_CE_INT */ -/* Description: Enable PI Correctable Error Interrupt */ -#define SH_LOCAL_INT4_ENABLE_PI_CE_INT_SHFT 5 -#define SH_LOCAL_INT4_ENABLE_PI_CE_INT_MASK 0x0000000000000020 - -/* SH_LOCAL_INT4_ENABLE_MD_CE_INT */ -/* Description: Enable MD Correctable Error Interrupt */ -#define SH_LOCAL_INT4_ENABLE_MD_CE_INT_SHFT 6 -#define SH_LOCAL_INT4_ENABLE_MD_CE_INT_MASK 0x0000000000000040 - -/* SH_LOCAL_INT4_ENABLE_XN_CE_INT */ -/* Description: Enable XN Correctable Error Interrupt */ -#define SH_LOCAL_INT4_ENABLE_XN_CE_INT_SHFT 7 -#define SH_LOCAL_INT4_ENABLE_XN_CE_INT_MASK 0x0000000000000080 - -/* SH_LOCAL_INT4_ENABLE_PI_UCE_INT */ -/* Description: Enable PI Correctable Error Interrupt */ -#define SH_LOCAL_INT4_ENABLE_PI_UCE_INT_SHFT 8 -#define SH_LOCAL_INT4_ENABLE_PI_UCE_INT_MASK 0x0000000000000100 - -/* SH_LOCAL_INT4_ENABLE_MD_UCE_INT */ -/* Description: Enable MD Correctable Error Interrupt */ -#define SH_LOCAL_INT4_ENABLE_MD_UCE_INT_SHFT 9 -#define SH_LOCAL_INT4_ENABLE_MD_UCE_INT_MASK 0x0000000000000200 - -/* SH_LOCAL_INT4_ENABLE_XN_UCE_INT */ -/* Description: Enable XN Correctable Error Interrupt */ -#define SH_LOCAL_INT4_ENABLE_XN_UCE_INT_SHFT 10 -#define SH_LOCAL_INT4_ENABLE_XN_UCE_INT_MASK 0x0000000000000400 - -/* SH_LOCAL_INT4_ENABLE_SYSTEM_SHUTDOWN_INT */ -/* Description: Enable System Shutdown Interrupt */ -#define SH_LOCAL_INT4_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12 -#define SH_LOCAL_INT4_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000 - -/* SH_LOCAL_INT4_ENABLE_UART_INT */ -/* Description: Enable Junk Bus UART Interrupt */ -#define SH_LOCAL_INT4_ENABLE_UART_INT_SHFT 13 -#define SH_LOCAL_INT4_ENABLE_UART_INT_MASK 0x0000000000002000 - -/* SH_LOCAL_INT4_ENABLE_L1_NMI_INT */ -/* Description: Enable L1 Controller NMI Interrupt */ -#define SH_LOCAL_INT4_ENABLE_L1_NMI_INT_SHFT 14 -#define SH_LOCAL_INT4_ENABLE_L1_NMI_INT_MASK 0x0000000000004000 - -/* SH_LOCAL_INT4_ENABLE_STOP_CLOCK */ -/* Description: Stop Clock Interrupt */ -#define SH_LOCAL_INT4_ENABLE_STOP_CLOCK_SHFT 15 -#define SH_LOCAL_INT4_ENABLE_STOP_CLOCK_MASK 0x0000000000008000 - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT5_CONFIG" */ -/* SHub Local Interrupt 5 Registers */ -/* ==================================================================== */ - -#define SH_LOCAL_INT5_CONFIG 0x0000000110000980 -#define SH_LOCAL_INT5_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_LOCAL_INT5_CONFIG_INIT 0x0000000000000000 - -/* SH_LOCAL_INT5_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_LOCAL_INT5_CONFIG_TYPE_SHFT 0 -#define SH_LOCAL_INT5_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_LOCAL_INT5_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_LOCAL_INT5_CONFIG_AGT_SHFT 3 -#define SH_LOCAL_INT5_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_LOCAL_INT5_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_LOCAL_INT5_CONFIG_PID_SHFT 4 -#define SH_LOCAL_INT5_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_LOCAL_INT5_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_LOCAL_INT5_CONFIG_BASE_SHFT 21 -#define SH_LOCAL_INT5_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_LOCAL_INT5_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_LOCAL_INT5_CONFIG_IDX_SHFT 52 -#define SH_LOCAL_INT5_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT5_ENABLE" */ -/* SHub Local Interrupt 5 Enable */ -/* ==================================================================== */ - -#define SH_LOCAL_INT5_ENABLE 0x0000000110000a00 -#define SH_LOCAL_INT5_ENABLE_MASK 0x000000000000f7ff -#define SH_LOCAL_INT5_ENABLE_INIT 0x0000000000000000 - -/* SH_LOCAL_INT5_ENABLE_PI_HW_INT */ -/* Description: Enable PI Hardware interrupt */ -#define SH_LOCAL_INT5_ENABLE_PI_HW_INT_SHFT 0 -#define SH_LOCAL_INT5_ENABLE_PI_HW_INT_MASK 0x0000000000000001 - -/* SH_LOCAL_INT5_ENABLE_MD_HW_INT */ -/* Description: Enable MD Hardware interrupt */ -#define SH_LOCAL_INT5_ENABLE_MD_HW_INT_SHFT 1 -#define SH_LOCAL_INT5_ENABLE_MD_HW_INT_MASK 0x0000000000000002 - -/* SH_LOCAL_INT5_ENABLE_XN_HW_INT */ -/* Description: Enable XN Hardware interrupt */ -#define SH_LOCAL_INT5_ENABLE_XN_HW_INT_SHFT 2 -#define SH_LOCAL_INT5_ENABLE_XN_HW_INT_MASK 0x0000000000000004 - -/* SH_LOCAL_INT5_ENABLE_LB_HW_INT */ -/* Description: Enable LB Hardware interrupt */ -#define SH_LOCAL_INT5_ENABLE_LB_HW_INT_SHFT 3 -#define SH_LOCAL_INT5_ENABLE_LB_HW_INT_MASK 0x0000000000000008 - -/* SH_LOCAL_INT5_ENABLE_II_HW_INT */ -/* Description: Enable II wrapper Hardware interrupt */ -#define SH_LOCAL_INT5_ENABLE_II_HW_INT_SHFT 4 -#define SH_LOCAL_INT5_ENABLE_II_HW_INT_MASK 0x0000000000000010 - -/* SH_LOCAL_INT5_ENABLE_PI_CE_INT */ -/* Description: Enable PI Correctable Error Interrupt */ -#define SH_LOCAL_INT5_ENABLE_PI_CE_INT_SHFT 5 -#define SH_LOCAL_INT5_ENABLE_PI_CE_INT_MASK 0x0000000000000020 - -/* SH_LOCAL_INT5_ENABLE_MD_CE_INT */ -/* Description: Enable MD Correctable Error Interrupt */ -#define SH_LOCAL_INT5_ENABLE_MD_CE_INT_SHFT 6 -#define SH_LOCAL_INT5_ENABLE_MD_CE_INT_MASK 0x0000000000000040 - -/* SH_LOCAL_INT5_ENABLE_XN_CE_INT */ -/* Description: Enable XN Correctable Error Interrupt */ -#define SH_LOCAL_INT5_ENABLE_XN_CE_INT_SHFT 7 -#define SH_LOCAL_INT5_ENABLE_XN_CE_INT_MASK 0x0000000000000080 - -/* SH_LOCAL_INT5_ENABLE_PI_UCE_INT */ -/* Description: Enable PI Correctable Error Interrupt */ -#define SH_LOCAL_INT5_ENABLE_PI_UCE_INT_SHFT 8 -#define SH_LOCAL_INT5_ENABLE_PI_UCE_INT_MASK 0x0000000000000100 - -/* SH_LOCAL_INT5_ENABLE_MD_UCE_INT */ -/* Description: Enable MD Correctable Error Interrupt */ -#define SH_LOCAL_INT5_ENABLE_MD_UCE_INT_SHFT 9 -#define SH_LOCAL_INT5_ENABLE_MD_UCE_INT_MASK 0x0000000000000200 - -/* SH_LOCAL_INT5_ENABLE_XN_UCE_INT */ -/* Description: Enable XN Correctable Error Interrupt */ -#define SH_LOCAL_INT5_ENABLE_XN_UCE_INT_SHFT 10 -#define SH_LOCAL_INT5_ENABLE_XN_UCE_INT_MASK 0x0000000000000400 - -/* SH_LOCAL_INT5_ENABLE_SYSTEM_SHUTDOWN_INT */ -/* Description: Enable System Shutdown Interrupt */ -#define SH_LOCAL_INT5_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12 -#define SH_LOCAL_INT5_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000 - -/* SH_LOCAL_INT5_ENABLE_UART_INT */ -/* Description: Enable Junk Bus UART Interrupt */ -#define SH_LOCAL_INT5_ENABLE_UART_INT_SHFT 13 -#define SH_LOCAL_INT5_ENABLE_UART_INT_MASK 0x0000000000002000 - -/* SH_LOCAL_INT5_ENABLE_L1_NMI_INT */ -/* Description: Enable L1 Controller NMI Interrupt */ -#define SH_LOCAL_INT5_ENABLE_L1_NMI_INT_SHFT 14 -#define SH_LOCAL_INT5_ENABLE_L1_NMI_INT_MASK 0x0000000000004000 - -/* SH_LOCAL_INT5_ENABLE_STOP_CLOCK */ -/* Description: Stop Clock Interrupt */ -#define SH_LOCAL_INT5_ENABLE_STOP_CLOCK_SHFT 15 -#define SH_LOCAL_INT5_ENABLE_STOP_CLOCK_MASK 0x0000000000008000 - -/* ==================================================================== */ -/* Register "SH_PROC0_ERR_INT_CONFIG" */ -/* SHub Processor 0 Error Interrupt Registers */ -/* ==================================================================== */ - -#define SH_PROC0_ERR_INT_CONFIG 0x0000000110000a80 -#define SH_PROC0_ERR_INT_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_PROC0_ERR_INT_CONFIG_INIT 0x0000000000000000 - -/* SH_PROC0_ERR_INT_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_PROC0_ERR_INT_CONFIG_TYPE_SHFT 0 -#define SH_PROC0_ERR_INT_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_PROC0_ERR_INT_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_PROC0_ERR_INT_CONFIG_AGT_SHFT 3 -#define SH_PROC0_ERR_INT_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_PROC0_ERR_INT_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_PROC0_ERR_INT_CONFIG_PID_SHFT 4 -#define SH_PROC0_ERR_INT_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_PROC0_ERR_INT_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_PROC0_ERR_INT_CONFIG_BASE_SHFT 21 -#define SH_PROC0_ERR_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_PROC0_ERR_INT_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_PROC0_ERR_INT_CONFIG_IDX_SHFT 52 -#define SH_PROC0_ERR_INT_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC1_ERR_INT_CONFIG" */ -/* SHub Processor 1 Error Interrupt Registers */ -/* ==================================================================== */ - -#define SH_PROC1_ERR_INT_CONFIG 0x0000000110000b00 -#define SH_PROC1_ERR_INT_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_PROC1_ERR_INT_CONFIG_INIT 0x0000000000000000 - -/* SH_PROC1_ERR_INT_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_PROC1_ERR_INT_CONFIG_TYPE_SHFT 0 -#define SH_PROC1_ERR_INT_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_PROC1_ERR_INT_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_PROC1_ERR_INT_CONFIG_AGT_SHFT 3 -#define SH_PROC1_ERR_INT_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_PROC1_ERR_INT_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_PROC1_ERR_INT_CONFIG_PID_SHFT 4 -#define SH_PROC1_ERR_INT_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_PROC1_ERR_INT_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_PROC1_ERR_INT_CONFIG_BASE_SHFT 21 -#define SH_PROC1_ERR_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_PROC1_ERR_INT_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_PROC1_ERR_INT_CONFIG_IDX_SHFT 52 -#define SH_PROC1_ERR_INT_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC2_ERR_INT_CONFIG" */ -/* SHub Processor 2 Error Interrupt Registers */ -/* ==================================================================== */ - -#define SH_PROC2_ERR_INT_CONFIG 0x0000000110000b80 -#define SH_PROC2_ERR_INT_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_PROC2_ERR_INT_CONFIG_INIT 0x0000000000000000 - -/* SH_PROC2_ERR_INT_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_PROC2_ERR_INT_CONFIG_TYPE_SHFT 0 -#define SH_PROC2_ERR_INT_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_PROC2_ERR_INT_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_PROC2_ERR_INT_CONFIG_AGT_SHFT 3 -#define SH_PROC2_ERR_INT_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_PROC2_ERR_INT_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_PROC2_ERR_INT_CONFIG_PID_SHFT 4 -#define SH_PROC2_ERR_INT_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_PROC2_ERR_INT_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_PROC2_ERR_INT_CONFIG_BASE_SHFT 21 -#define SH_PROC2_ERR_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_PROC2_ERR_INT_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_PROC2_ERR_INT_CONFIG_IDX_SHFT 52 -#define SH_PROC2_ERR_INT_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC3_ERR_INT_CONFIG" */ -/* SHub Processor 3 Error Interrupt Registers */ -/* ==================================================================== */ - -#define SH_PROC3_ERR_INT_CONFIG 0x0000000110000c00 -#define SH_PROC3_ERR_INT_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_PROC3_ERR_INT_CONFIG_INIT 0x0000000000000000 - -/* SH_PROC3_ERR_INT_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_PROC3_ERR_INT_CONFIG_TYPE_SHFT 0 -#define SH_PROC3_ERR_INT_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_PROC3_ERR_INT_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_PROC3_ERR_INT_CONFIG_AGT_SHFT 3 -#define SH_PROC3_ERR_INT_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_PROC3_ERR_INT_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_PROC3_ERR_INT_CONFIG_PID_SHFT 4 -#define SH_PROC3_ERR_INT_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_PROC3_ERR_INT_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_PROC3_ERR_INT_CONFIG_BASE_SHFT 21 -#define SH_PROC3_ERR_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_PROC3_ERR_INT_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_PROC3_ERR_INT_CONFIG_IDX_SHFT 52 -#define SH_PROC3_ERR_INT_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC0_ADV_INT_CONFIG" */ -/* SHub Processor 0 Advisory Interrupt Registers */ -/* ==================================================================== */ - -#define SH_PROC0_ADV_INT_CONFIG 0x0000000110000c80 -#define SH_PROC0_ADV_INT_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_PROC0_ADV_INT_CONFIG_INIT 0x0000000000000000 - -/* SH_PROC0_ADV_INT_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_PROC0_ADV_INT_CONFIG_TYPE_SHFT 0 -#define SH_PROC0_ADV_INT_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_PROC0_ADV_INT_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_PROC0_ADV_INT_CONFIG_AGT_SHFT 3 -#define SH_PROC0_ADV_INT_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_PROC0_ADV_INT_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_PROC0_ADV_INT_CONFIG_PID_SHFT 4 -#define SH_PROC0_ADV_INT_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_PROC0_ADV_INT_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_PROC0_ADV_INT_CONFIG_BASE_SHFT 21 -#define SH_PROC0_ADV_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_PROC0_ADV_INT_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_PROC0_ADV_INT_CONFIG_IDX_SHFT 52 -#define SH_PROC0_ADV_INT_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC1_ADV_INT_CONFIG" */ -/* SHub Processor 1 Advisory Interrupt Registers */ -/* ==================================================================== */ - -#define SH_PROC1_ADV_INT_CONFIG 0x0000000110000d00 -#define SH_PROC1_ADV_INT_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_PROC1_ADV_INT_CONFIG_INIT 0x0000000000000000 - -/* SH_PROC1_ADV_INT_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_PROC1_ADV_INT_CONFIG_TYPE_SHFT 0 -#define SH_PROC1_ADV_INT_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_PROC1_ADV_INT_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_PROC1_ADV_INT_CONFIG_AGT_SHFT 3 -#define SH_PROC1_ADV_INT_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_PROC1_ADV_INT_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_PROC1_ADV_INT_CONFIG_PID_SHFT 4 -#define SH_PROC1_ADV_INT_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_PROC1_ADV_INT_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_PROC1_ADV_INT_CONFIG_BASE_SHFT 21 -#define SH_PROC1_ADV_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_PROC1_ADV_INT_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_PROC1_ADV_INT_CONFIG_IDX_SHFT 52 -#define SH_PROC1_ADV_INT_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC2_ADV_INT_CONFIG" */ -/* SHub Processor 2 Advisory Interrupt Registers */ -/* ==================================================================== */ - -#define SH_PROC2_ADV_INT_CONFIG 0x0000000110000d80 -#define SH_PROC2_ADV_INT_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_PROC2_ADV_INT_CONFIG_INIT 0x0000000000000000 - -/* SH_PROC2_ADV_INT_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_PROC2_ADV_INT_CONFIG_TYPE_SHFT 0 -#define SH_PROC2_ADV_INT_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_PROC2_ADV_INT_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_PROC2_ADV_INT_CONFIG_AGT_SHFT 3 -#define SH_PROC2_ADV_INT_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_PROC2_ADV_INT_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_PROC2_ADV_INT_CONFIG_PID_SHFT 4 -#define SH_PROC2_ADV_INT_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_PROC2_ADV_INT_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_PROC2_ADV_INT_CONFIG_BASE_SHFT 21 -#define SH_PROC2_ADV_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_PROC2_ADV_INT_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_PROC2_ADV_INT_CONFIG_IDX_SHFT 52 -#define SH_PROC2_ADV_INT_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC3_ADV_INT_CONFIG" */ -/* SHub Processor 3 Advisory Interrupt Registers */ -/* ==================================================================== */ - -#define SH_PROC3_ADV_INT_CONFIG 0x0000000110000e00 -#define SH_PROC3_ADV_INT_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_PROC3_ADV_INT_CONFIG_INIT 0x0000000000000000 - -/* SH_PROC3_ADV_INT_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_PROC3_ADV_INT_CONFIG_TYPE_SHFT 0 -#define SH_PROC3_ADV_INT_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_PROC3_ADV_INT_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_PROC3_ADV_INT_CONFIG_AGT_SHFT 3 -#define SH_PROC3_ADV_INT_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_PROC3_ADV_INT_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_PROC3_ADV_INT_CONFIG_PID_SHFT 4 -#define SH_PROC3_ADV_INT_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_PROC3_ADV_INT_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_PROC3_ADV_INT_CONFIG_BASE_SHFT 21 -#define SH_PROC3_ADV_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_PROC3_ADV_INT_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_PROC3_ADV_INT_CONFIG_IDX_SHFT 52 -#define SH_PROC3_ADV_INT_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC0_ERR_INT_ENABLE" */ -/* SHub Processor 0 Error Interrupt Enable Registers */ -/* ==================================================================== */ - -#define SH_PROC0_ERR_INT_ENABLE 0x0000000110000e80 -#define SH_PROC0_ERR_INT_ENABLE_MASK 0x0000000000000001 -#define SH_PROC0_ERR_INT_ENABLE_INIT 0x0000000000000000 - -/* SH_PROC0_ERR_INT_ENABLE_PROC0_ERR_ENABLE */ -/* Description: Enable Processor 0 Error Interrupt */ -#define SH_PROC0_ERR_INT_ENABLE_PROC0_ERR_ENABLE_SHFT 0 -#define SH_PROC0_ERR_INT_ENABLE_PROC0_ERR_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_PROC1_ERR_INT_ENABLE" */ -/* SHub Processor 1 Error Interrupt Enable Registers */ -/* ==================================================================== */ - -#define SH_PROC1_ERR_INT_ENABLE 0x0000000110000f00 -#define SH_PROC1_ERR_INT_ENABLE_MASK 0x0000000000000001 -#define SH_PROC1_ERR_INT_ENABLE_INIT 0x0000000000000000 - -/* SH_PROC1_ERR_INT_ENABLE_PROC1_ERR_ENABLE */ -/* Description: Enable Processor 1 Error Interrupt */ -#define SH_PROC1_ERR_INT_ENABLE_PROC1_ERR_ENABLE_SHFT 0 -#define SH_PROC1_ERR_INT_ENABLE_PROC1_ERR_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_PROC2_ERR_INT_ENABLE" */ -/* SHub Processor 2 Error Interrupt Enable Registers */ -/* ==================================================================== */ - -#define SH_PROC2_ERR_INT_ENABLE 0x0000000110000f80 -#define SH_PROC2_ERR_INT_ENABLE_MASK 0x0000000000000001 -#define SH_PROC2_ERR_INT_ENABLE_INIT 0x0000000000000000 - -/* SH_PROC2_ERR_INT_ENABLE_PROC2_ERR_ENABLE */ -/* Description: Enable Processor 2 Error Interrupt */ -#define SH_PROC2_ERR_INT_ENABLE_PROC2_ERR_ENABLE_SHFT 0 -#define SH_PROC2_ERR_INT_ENABLE_PROC2_ERR_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_PROC3_ERR_INT_ENABLE" */ -/* SHub Processor 3 Error Interrupt Enable Registers */ -/* ==================================================================== */ - -#define SH_PROC3_ERR_INT_ENABLE 0x0000000110001000 -#define SH_PROC3_ERR_INT_ENABLE_MASK 0x0000000000000001 -#define SH_PROC3_ERR_INT_ENABLE_INIT 0x0000000000000000 - -/* SH_PROC3_ERR_INT_ENABLE_PROC3_ERR_ENABLE */ -/* Description: Enable Processor 3 Error Interrupt */ -#define SH_PROC3_ERR_INT_ENABLE_PROC3_ERR_ENABLE_SHFT 0 -#define SH_PROC3_ERR_INT_ENABLE_PROC3_ERR_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_PROC0_ADV_INT_ENABLE" */ -/* SHub Processor 0 Advisory Interrupt Enable Registers */ -/* ==================================================================== */ - -#define SH_PROC0_ADV_INT_ENABLE 0x0000000110001080 -#define SH_PROC0_ADV_INT_ENABLE_MASK 0x0000000000000001 -#define SH_PROC0_ADV_INT_ENABLE_INIT 0x0000000000000000 - -/* SH_PROC0_ADV_INT_ENABLE_PROC0_ADV_ENABLE */ -/* Description: Enable Processor 0 Advisory Interrupt */ -#define SH_PROC0_ADV_INT_ENABLE_PROC0_ADV_ENABLE_SHFT 0 -#define SH_PROC0_ADV_INT_ENABLE_PROC0_ADV_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_PROC1_ADV_INT_ENABLE" */ -/* SHub Processor 1 Advisory Interrupt Enable Registers */ -/* ==================================================================== */ - -#define SH_PROC1_ADV_INT_ENABLE 0x0000000110001100 -#define SH_PROC1_ADV_INT_ENABLE_MASK 0x0000000000000001 -#define SH_PROC1_ADV_INT_ENABLE_INIT 0x0000000000000000 - -/* SH_PROC1_ADV_INT_ENABLE_PROC1_ADV_ENABLE */ -/* Description: Enable Processor 1 Advisory Interrupt */ -#define SH_PROC1_ADV_INT_ENABLE_PROC1_ADV_ENABLE_SHFT 0 -#define SH_PROC1_ADV_INT_ENABLE_PROC1_ADV_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_PROC2_ADV_INT_ENABLE" */ -/* SHub Processor 2 Advisory Interrupt Enable Registers */ -/* ==================================================================== */ - -#define SH_PROC2_ADV_INT_ENABLE 0x0000000110001180 -#define SH_PROC2_ADV_INT_ENABLE_MASK 0x0000000000000001 -#define SH_PROC2_ADV_INT_ENABLE_INIT 0x0000000000000000 - -/* SH_PROC2_ADV_INT_ENABLE_PROC2_ADV_ENABLE */ -/* Description: Enable Processor 2 Advisory Interrupt */ -#define SH_PROC2_ADV_INT_ENABLE_PROC2_ADV_ENABLE_SHFT 0 -#define SH_PROC2_ADV_INT_ENABLE_PROC2_ADV_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_PROC3_ADV_INT_ENABLE" */ -/* SHub Processor 3 Advisory Interrupt Enable Registers */ -/* ==================================================================== */ - -#define SH_PROC3_ADV_INT_ENABLE 0x0000000110001200 -#define SH_PROC3_ADV_INT_ENABLE_MASK 0x0000000000000001 -#define SH_PROC3_ADV_INT_ENABLE_INIT 0x0000000000000000 - -/* SH_PROC3_ADV_INT_ENABLE_PROC3_ADV_ENABLE */ -/* Description: Enable Processor 3 Advisory Interrupt */ -#define SH_PROC3_ADV_INT_ENABLE_PROC3_ADV_ENABLE_SHFT 0 -#define SH_PROC3_ADV_INT_ENABLE_PROC3_ADV_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_PROFILE_INT_CONFIG" */ -/* SHub Profile Interrupt Configuration Registers */ -/* ==================================================================== */ - -#define SH_PROFILE_INT_CONFIG 0x0000000110001280 -#define SH_PROFILE_INT_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_PROFILE_INT_CONFIG_INIT 0x0000000000000000 - -/* SH_PROFILE_INT_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_PROFILE_INT_CONFIG_TYPE_SHFT 0 -#define SH_PROFILE_INT_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_PROFILE_INT_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_PROFILE_INT_CONFIG_AGT_SHFT 3 -#define SH_PROFILE_INT_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_PROFILE_INT_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_PROFILE_INT_CONFIG_PID_SHFT 4 -#define SH_PROFILE_INT_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_PROFILE_INT_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_PROFILE_INT_CONFIG_BASE_SHFT 21 -#define SH_PROFILE_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_PROFILE_INT_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_PROFILE_INT_CONFIG_IDX_SHFT 52 -#define SH_PROFILE_INT_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_PROFILE_INT_ENABLE" */ -/* SHub Profile Interrupt Enable Registers */ -/* ==================================================================== */ - -#define SH_PROFILE_INT_ENABLE 0x0000000110001300 -#define SH_PROFILE_INT_ENABLE_MASK 0x0000000000000001 -#define SH_PROFILE_INT_ENABLE_INIT 0x0000000000000000 - -/* SH_PROFILE_INT_ENABLE_PROFILE_ENABLE */ -/* Description: Enable Profile Interrupt */ -#define SH_PROFILE_INT_ENABLE_PROFILE_ENABLE_SHFT 0 -#define SH_PROFILE_INT_ENABLE_PROFILE_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_RTC0_INT_CONFIG" */ -/* SHub RTC 0 Interrupt Config Registers */ -/* ==================================================================== */ - -#define SH_RTC0_INT_CONFIG 0x0000000110001380 -#define SH_RTC0_INT_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_RTC0_INT_CONFIG_INIT 0x0000000000000000 - -/* SH_RTC0_INT_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_RTC0_INT_CONFIG_TYPE_SHFT 0 -#define SH_RTC0_INT_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_RTC0_INT_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_RTC0_INT_CONFIG_AGT_SHFT 3 -#define SH_RTC0_INT_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_RTC0_INT_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_RTC0_INT_CONFIG_PID_SHFT 4 -#define SH_RTC0_INT_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_RTC0_INT_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_RTC0_INT_CONFIG_BASE_SHFT 21 -#define SH_RTC0_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_RTC0_INT_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_RTC0_INT_CONFIG_IDX_SHFT 52 -#define SH_RTC0_INT_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_RTC0_INT_ENABLE" */ -/* SHub RTC 0 Interrupt Enable Registers */ -/* ==================================================================== */ - -#define SH_RTC0_INT_ENABLE 0x0000000110001400 -#define SH_RTC0_INT_ENABLE_MASK 0x0000000000000001 -#define SH_RTC0_INT_ENABLE_INIT 0x0000000000000000 - -/* SH_RTC0_INT_ENABLE_RTC0_ENABLE */ -/* Description: Enable RTC 0 Interrupt */ -#define SH_RTC0_INT_ENABLE_RTC0_ENABLE_SHFT 0 -#define SH_RTC0_INT_ENABLE_RTC0_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_RTC1_INT_CONFIG" */ -/* SHub RTC 1 Interrupt Config Registers */ -/* ==================================================================== */ - -#define SH_RTC1_INT_CONFIG 0x0000000110001480 -#define SH_RTC1_INT_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_RTC1_INT_CONFIG_INIT 0x0000000000000000 - -/* SH_RTC1_INT_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_RTC1_INT_CONFIG_TYPE_SHFT 0 -#define SH_RTC1_INT_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_RTC1_INT_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_RTC1_INT_CONFIG_AGT_SHFT 3 -#define SH_RTC1_INT_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_RTC1_INT_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_RTC1_INT_CONFIG_PID_SHFT 4 -#define SH_RTC1_INT_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_RTC1_INT_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_RTC1_INT_CONFIG_BASE_SHFT 21 -#define SH_RTC1_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_RTC1_INT_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_RTC1_INT_CONFIG_IDX_SHFT 52 -#define SH_RTC1_INT_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_RTC1_INT_ENABLE" */ -/* SHub RTC 1 Interrupt Enable Registers */ -/* ==================================================================== */ - -#define SH_RTC1_INT_ENABLE 0x0000000110001500 -#define SH_RTC1_INT_ENABLE_MASK 0x0000000000000001 -#define SH_RTC1_INT_ENABLE_INIT 0x0000000000000000 - -/* SH_RTC1_INT_ENABLE_RTC1_ENABLE */ -/* Description: Enable RTC 1 Interrupt */ -#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT 0 -#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_RTC2_INT_CONFIG" */ -/* SHub RTC 2 Interrupt Config Registers */ -/* ==================================================================== */ - -#define SH_RTC2_INT_CONFIG 0x0000000110001580 -#define SH_RTC2_INT_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_RTC2_INT_CONFIG_INIT 0x0000000000000000 - -/* SH_RTC2_INT_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_RTC2_INT_CONFIG_TYPE_SHFT 0 -#define SH_RTC2_INT_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_RTC2_INT_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_RTC2_INT_CONFIG_AGT_SHFT 3 -#define SH_RTC2_INT_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_RTC2_INT_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_RTC2_INT_CONFIG_PID_SHFT 4 -#define SH_RTC2_INT_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_RTC2_INT_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_RTC2_INT_CONFIG_BASE_SHFT 21 -#define SH_RTC2_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_RTC2_INT_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_RTC2_INT_CONFIG_IDX_SHFT 52 -#define SH_RTC2_INT_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_RTC2_INT_ENABLE" */ -/* SHub RTC 2 Interrupt Enable Registers */ -/* ==================================================================== */ - -#define SH_RTC2_INT_ENABLE 0x0000000110001600 -#define SH_RTC2_INT_ENABLE_MASK 0x0000000000000001 -#define SH_RTC2_INT_ENABLE_INIT 0x0000000000000000 - -/* SH_RTC2_INT_ENABLE_RTC2_ENABLE */ -/* Description: Enable RTC 2 Interrupt */ -#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT 0 -#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_RTC3_INT_CONFIG" */ -/* SHub RTC 3 Interrupt Config Registers */ -/* ==================================================================== */ - -#define SH_RTC3_INT_CONFIG 0x0000000110001680 -#define SH_RTC3_INT_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_RTC3_INT_CONFIG_INIT 0x0000000000000000 - -/* SH_RTC3_INT_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_RTC3_INT_CONFIG_TYPE_SHFT 0 -#define SH_RTC3_INT_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_RTC3_INT_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_RTC3_INT_CONFIG_AGT_SHFT 3 -#define SH_RTC3_INT_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_RTC3_INT_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_RTC3_INT_CONFIG_PID_SHFT 4 -#define SH_RTC3_INT_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_RTC3_INT_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_RTC3_INT_CONFIG_BASE_SHFT 21 -#define SH_RTC3_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_RTC3_INT_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_RTC3_INT_CONFIG_IDX_SHFT 52 -#define SH_RTC3_INT_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_RTC3_INT_ENABLE" */ -/* SHub RTC 3 Interrupt Enable Registers */ -/* ==================================================================== */ - -#define SH_RTC3_INT_ENABLE 0x0000000110001700 -#define SH_RTC3_INT_ENABLE_MASK 0x0000000000000001 -#define SH_RTC3_INT_ENABLE_INIT 0x0000000000000000 - -/* SH_RTC3_INT_ENABLE_RTC3_ENABLE */ -/* Description: Enable RTC 3 Interrupt */ -#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT 0 -#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_EVENT_OCCURRED" */ -/* SHub Interrupt Event Occurred */ -/* ==================================================================== */ - -#define SH_EVENT_OCCURRED 0x0000000110010000 -#define SH_EVENT_OCCURRED_MASK 0x000000007fffffff -#define SH_EVENT_OCCURRED_INIT 0x0000000000000000 - -/* SH_EVENT_OCCURRED_PI_HW_INT */ -/* Description: Pending PI Hardware interrupt */ -#define SH_EVENT_OCCURRED_PI_HW_INT_SHFT 0 -#define SH_EVENT_OCCURRED_PI_HW_INT_MASK 0x0000000000000001 - -/* SH_EVENT_OCCURRED_MD_HW_INT */ -/* Description: Pending MD Hardware interrupt */ -#define SH_EVENT_OCCURRED_MD_HW_INT_SHFT 1 -#define SH_EVENT_OCCURRED_MD_HW_INT_MASK 0x0000000000000002 - -/* SH_EVENT_OCCURRED_XN_HW_INT */ -/* Description: Pending XN Hardware interrupt */ -#define SH_EVENT_OCCURRED_XN_HW_INT_SHFT 2 -#define SH_EVENT_OCCURRED_XN_HW_INT_MASK 0x0000000000000004 - -/* SH_EVENT_OCCURRED_LB_HW_INT */ -/* Description: Pending LB Hardware interrupt */ -#define SH_EVENT_OCCURRED_LB_HW_INT_SHFT 3 -#define SH_EVENT_OCCURRED_LB_HW_INT_MASK 0x0000000000000008 - -/* SH_EVENT_OCCURRED_II_HW_INT */ -/* Description: Pending II wrapper Hardware interrupt */ -#define SH_EVENT_OCCURRED_II_HW_INT_SHFT 4 -#define SH_EVENT_OCCURRED_II_HW_INT_MASK 0x0000000000000010 - -/* SH_EVENT_OCCURRED_PI_CE_INT */ -/* Description: Pending PI Correctable Error Interrupt */ -#define SH_EVENT_OCCURRED_PI_CE_INT_SHFT 5 -#define SH_EVENT_OCCURRED_PI_CE_INT_MASK 0x0000000000000020 - -/* SH_EVENT_OCCURRED_MD_CE_INT */ -/* Description: Pending MD Correctable Error Interrupt */ -#define SH_EVENT_OCCURRED_MD_CE_INT_SHFT 6 -#define SH_EVENT_OCCURRED_MD_CE_INT_MASK 0x0000000000000040 - -/* SH_EVENT_OCCURRED_XN_CE_INT */ -/* Description: Pending XN Correctable Error Interrupt */ -#define SH_EVENT_OCCURRED_XN_CE_INT_SHFT 7 -#define SH_EVENT_OCCURRED_XN_CE_INT_MASK 0x0000000000000080 - -/* SH_EVENT_OCCURRED_PI_UCE_INT */ -/* Description: Pending PI Correctable Error Interrupt */ -#define SH_EVENT_OCCURRED_PI_UCE_INT_SHFT 8 -#define SH_EVENT_OCCURRED_PI_UCE_INT_MASK 0x0000000000000100 - -/* SH_EVENT_OCCURRED_MD_UCE_INT */ -/* Description: Pending MD Correctable Error Interrupt */ -#define SH_EVENT_OCCURRED_MD_UCE_INT_SHFT 9 -#define SH_EVENT_OCCURRED_MD_UCE_INT_MASK 0x0000000000000200 - -/* SH_EVENT_OCCURRED_XN_UCE_INT */ -/* Description: Pending XN Correctable Error Interrupt */ -#define SH_EVENT_OCCURRED_XN_UCE_INT_SHFT 10 -#define SH_EVENT_OCCURRED_XN_UCE_INT_MASK 0x0000000000000400 - -/* SH_EVENT_OCCURRED_PROC0_ADV_INT */ -/* Description: Pending Processor 0 Advisory Interrupt */ -#define SH_EVENT_OCCURRED_PROC0_ADV_INT_SHFT 11 -#define SH_EVENT_OCCURRED_PROC0_ADV_INT_MASK 0x0000000000000800 - -/* SH_EVENT_OCCURRED_PROC1_ADV_INT */ -/* Description: Pending Processor 1 Advisory Interrupt */ -#define SH_EVENT_OCCURRED_PROC1_ADV_INT_SHFT 12 -#define SH_EVENT_OCCURRED_PROC1_ADV_INT_MASK 0x0000000000001000 - -/* SH_EVENT_OCCURRED_PROC2_ADV_INT */ -/* Description: Pending Processor 2 Advisory Interrupt */ -#define SH_EVENT_OCCURRED_PROC2_ADV_INT_SHFT 13 -#define SH_EVENT_OCCURRED_PROC2_ADV_INT_MASK 0x0000000000002000 - -/* SH_EVENT_OCCURRED_PROC3_ADV_INT */ -/* Description: Pending Processor 3 Advisory Interrupt */ -#define SH_EVENT_OCCURRED_PROC3_ADV_INT_SHFT 14 -#define SH_EVENT_OCCURRED_PROC3_ADV_INT_MASK 0x0000000000004000 - -/* SH_EVENT_OCCURRED_PROC0_ERR_INT */ -/* Description: Pending Processor 0 Error Interrupt */ -#define SH_EVENT_OCCURRED_PROC0_ERR_INT_SHFT 15 -#define SH_EVENT_OCCURRED_PROC0_ERR_INT_MASK 0x0000000000008000 - -/* SH_EVENT_OCCURRED_PROC1_ERR_INT */ -/* Description: Pending Processor 1 Error Interrupt */ -#define SH_EVENT_OCCURRED_PROC1_ERR_INT_SHFT 16 -#define SH_EVENT_OCCURRED_PROC1_ERR_INT_MASK 0x0000000000010000 - -/* SH_EVENT_OCCURRED_PROC2_ERR_INT */ -/* Description: Pending Processor 2 Error Interrupt */ -#define SH_EVENT_OCCURRED_PROC2_ERR_INT_SHFT 17 -#define SH_EVENT_OCCURRED_PROC2_ERR_INT_MASK 0x0000000000020000 - -/* SH_EVENT_OCCURRED_PROC3_ERR_INT */ -/* Description: Pending Processor 3 Error Interrupt */ -#define SH_EVENT_OCCURRED_PROC3_ERR_INT_SHFT 18 -#define SH_EVENT_OCCURRED_PROC3_ERR_INT_MASK 0x0000000000040000 - -/* SH_EVENT_OCCURRED_SYSTEM_SHUTDOWN_INT */ -/* Description: Pending System Shutdown Interrupt */ -#define SH_EVENT_OCCURRED_SYSTEM_SHUTDOWN_INT_SHFT 19 -#define SH_EVENT_OCCURRED_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000080000 - -/* SH_EVENT_OCCURRED_UART_INT */ -/* Description: Pending Junk Bus UART Interrupt */ -#define SH_EVENT_OCCURRED_UART_INT_SHFT 20 -#define SH_EVENT_OCCURRED_UART_INT_MASK 0x0000000000100000 - -/* SH_EVENT_OCCURRED_L1_NMI_INT */ -/* Description: Pending L1 Controller NMI Interrupt */ -#define SH_EVENT_OCCURRED_L1_NMI_INT_SHFT 21 -#define SH_EVENT_OCCURRED_L1_NMI_INT_MASK 0x0000000000200000 - -/* SH_EVENT_OCCURRED_STOP_CLOCK */ -/* Description: Pending Stop Clock Interrupt */ -#define SH_EVENT_OCCURRED_STOP_CLOCK_SHFT 22 -#define SH_EVENT_OCCURRED_STOP_CLOCK_MASK 0x0000000000400000 - -/* SH_EVENT_OCCURRED_RTC0_INT */ -/* Description: Pending RTC 0 Interrupt */ -#define SH_EVENT_OCCURRED_RTC0_INT_SHFT 23 -#define SH_EVENT_OCCURRED_RTC0_INT_MASK 0x0000000000800000 - -/* SH_EVENT_OCCURRED_RTC1_INT */ -/* Description: Pending RTC 1 Interrupt */ -#define SH_EVENT_OCCURRED_RTC1_INT_SHFT 24 -#define SH_EVENT_OCCURRED_RTC1_INT_MASK 0x0000000001000000 - -/* SH_EVENT_OCCURRED_RTC2_INT */ -/* Description: Pending RTC 2 Interrupt */ -#define SH_EVENT_OCCURRED_RTC2_INT_SHFT 25 -#define SH_EVENT_OCCURRED_RTC2_INT_MASK 0x0000000002000000 - -/* SH_EVENT_OCCURRED_RTC3_INT */ -/* Description: Pending RTC 3 Interrupt */ -#define SH_EVENT_OCCURRED_RTC3_INT_SHFT 26 -#define SH_EVENT_OCCURRED_RTC3_INT_MASK 0x0000000004000000 - -/* SH_EVENT_OCCURRED_PROFILE_INT */ -/* Description: Pending Profile Interrupt */ -#define SH_EVENT_OCCURRED_PROFILE_INT_SHFT 27 -#define SH_EVENT_OCCURRED_PROFILE_INT_MASK 0x0000000008000000 - -/* SH_EVENT_OCCURRED_IPI_INT */ -/* Description: Pending IPI Interrupt */ -#define SH_EVENT_OCCURRED_IPI_INT_SHFT 28 -#define SH_EVENT_OCCURRED_IPI_INT_MASK 0x0000000010000000 - -/* SH_EVENT_OCCURRED_II_INT0 */ -/* Description: Pending II 0 Interrupt */ -#define SH_EVENT_OCCURRED_II_INT0_SHFT 29 -#define SH_EVENT_OCCURRED_II_INT0_MASK 0x0000000020000000 - -/* SH_EVENT_OCCURRED_II_INT1 */ -/* Description: Pending II 1 Interrupt */ -#define SH_EVENT_OCCURRED_II_INT1_SHFT 30 -#define SH_EVENT_OCCURRED_II_INT1_MASK 0x0000000040000000 - -/* ==================================================================== */ -/* Register "SH_EVENT_OCCURRED_ALIAS" */ -/* SHub Interrupt Event Occurred Alias */ -/* ==================================================================== */ - -#define SH_EVENT_OCCURRED_ALIAS 0x0000000110010008 - -/* ==================================================================== */ -/* Register "SH_EVENT_OVERFLOW" */ -/* SHub Interrupt Event Occurred Overflow */ -/* ==================================================================== */ - -#define SH_EVENT_OVERFLOW 0x0000000110010080 -#define SH_EVENT_OVERFLOW_MASK 0x000000000fffffff -#define SH_EVENT_OVERFLOW_INIT 0x0000000000000000 - -/* SH_EVENT_OVERFLOW_PI_HW_INT */ -/* Description: Pending PI Hardware interrupt */ -#define SH_EVENT_OVERFLOW_PI_HW_INT_SHFT 0 -#define SH_EVENT_OVERFLOW_PI_HW_INT_MASK 0x0000000000000001 - -/* SH_EVENT_OVERFLOW_MD_HW_INT */ -/* Description: Pending MD Hardware interrupt */ -#define SH_EVENT_OVERFLOW_MD_HW_INT_SHFT 1 -#define SH_EVENT_OVERFLOW_MD_HW_INT_MASK 0x0000000000000002 - -/* SH_EVENT_OVERFLOW_XN_HW_INT */ -/* Description: Pending XN Hardware interrupt */ -#define SH_EVENT_OVERFLOW_XN_HW_INT_SHFT 2 -#define SH_EVENT_OVERFLOW_XN_HW_INT_MASK 0x0000000000000004 - -/* SH_EVENT_OVERFLOW_LB_HW_INT */ -/* Description: Pending LB Hardware interrupt */ -#define SH_EVENT_OVERFLOW_LB_HW_INT_SHFT 3 -#define SH_EVENT_OVERFLOW_LB_HW_INT_MASK 0x0000000000000008 - -/* SH_EVENT_OVERFLOW_II_HW_INT */ -/* Description: Pending II wrapper Hardware interrupt */ -#define SH_EVENT_OVERFLOW_II_HW_INT_SHFT 4 -#define SH_EVENT_OVERFLOW_II_HW_INT_MASK 0x0000000000000010 - -/* SH_EVENT_OVERFLOW_PI_CE_INT */ -/* Description: Pending PI Correctable Error Interrupt */ -#define SH_EVENT_OVERFLOW_PI_CE_INT_SHFT 5 -#define SH_EVENT_OVERFLOW_PI_CE_INT_MASK 0x0000000000000020 - -/* SH_EVENT_OVERFLOW_MD_CE_INT */ -/* Description: Pending MD Correctable Error Interrupt */ -#define SH_EVENT_OVERFLOW_MD_CE_INT_SHFT 6 -#define SH_EVENT_OVERFLOW_MD_CE_INT_MASK 0x0000000000000040 - -/* SH_EVENT_OVERFLOW_XN_CE_INT */ -/* Description: Pending XN Correctable Error Interrupt */ -#define SH_EVENT_OVERFLOW_XN_CE_INT_SHFT 7 -#define SH_EVENT_OVERFLOW_XN_CE_INT_MASK 0x0000000000000080 - -/* SH_EVENT_OVERFLOW_PI_UCE_INT */ -/* Description: Pending PI Correctable Error Interrupt */ -#define SH_EVENT_OVERFLOW_PI_UCE_INT_SHFT 8 -#define SH_EVENT_OVERFLOW_PI_UCE_INT_MASK 0x0000000000000100 - -/* SH_EVENT_OVERFLOW_MD_UCE_INT */ -/* Description: Pending MD Correctable Error Interrupt */ -#define SH_EVENT_OVERFLOW_MD_UCE_INT_SHFT 9 -#define SH_EVENT_OVERFLOW_MD_UCE_INT_MASK 0x0000000000000200 - -/* SH_EVENT_OVERFLOW_XN_UCE_INT */ -/* Description: Pending XN Correctable Error Interrupt */ -#define SH_EVENT_OVERFLOW_XN_UCE_INT_SHFT 10 -#define SH_EVENT_OVERFLOW_XN_UCE_INT_MASK 0x0000000000000400 - -/* SH_EVENT_OVERFLOW_PROC0_ADV_INT */ -/* Description: Pending Processor 0 Advisory Interrupt */ -#define SH_EVENT_OVERFLOW_PROC0_ADV_INT_SHFT 11 -#define SH_EVENT_OVERFLOW_PROC0_ADV_INT_MASK 0x0000000000000800 - -/* SH_EVENT_OVERFLOW_PROC1_ADV_INT */ -/* Description: Pending Processor 1 Advisory Interrupt */ -#define SH_EVENT_OVERFLOW_PROC1_ADV_INT_SHFT 12 -#define SH_EVENT_OVERFLOW_PROC1_ADV_INT_MASK 0x0000000000001000 - -/* SH_EVENT_OVERFLOW_PROC2_ADV_INT */ -/* Description: Pending Processor 2 Advisory Interrupt */ -#define SH_EVENT_OVERFLOW_PROC2_ADV_INT_SHFT 13 -#define SH_EVENT_OVERFLOW_PROC2_ADV_INT_MASK 0x0000000000002000 - -/* SH_EVENT_OVERFLOW_PROC3_ADV_INT */ -/* Description: Pending Processor 3 Advisory Interrupt */ -#define SH_EVENT_OVERFLOW_PROC3_ADV_INT_SHFT 14 -#define SH_EVENT_OVERFLOW_PROC3_ADV_INT_MASK 0x0000000000004000 - -/* SH_EVENT_OVERFLOW_PROC0_ERR_INT */ -/* Description: Pending Processor 0 Error Interrupt */ -#define SH_EVENT_OVERFLOW_PROC0_ERR_INT_SHFT 15 -#define SH_EVENT_OVERFLOW_PROC0_ERR_INT_MASK 0x0000000000008000 - -/* SH_EVENT_OVERFLOW_PROC1_ERR_INT */ -/* Description: Pending Processor 1 Error Interrupt */ -#define SH_EVENT_OVERFLOW_PROC1_ERR_INT_SHFT 16 -#define SH_EVENT_OVERFLOW_PROC1_ERR_INT_MASK 0x0000000000010000 - -/* SH_EVENT_OVERFLOW_PROC2_ERR_INT */ -/* Description: Pending Processor 2 Error Interrupt */ -#define SH_EVENT_OVERFLOW_PROC2_ERR_INT_SHFT 17 -#define SH_EVENT_OVERFLOW_PROC2_ERR_INT_MASK 0x0000000000020000 - -/* SH_EVENT_OVERFLOW_PROC3_ERR_INT */ -/* Description: Pending Processor 3 Error Interrupt */ -#define SH_EVENT_OVERFLOW_PROC3_ERR_INT_SHFT 18 -#define SH_EVENT_OVERFLOW_PROC3_ERR_INT_MASK 0x0000000000040000 - -/* SH_EVENT_OVERFLOW_SYSTEM_SHUTDOWN_INT */ -/* Description: Pending System Shutdown Interrupt */ -#define SH_EVENT_OVERFLOW_SYSTEM_SHUTDOWN_INT_SHFT 19 -#define SH_EVENT_OVERFLOW_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000080000 - -/* SH_EVENT_OVERFLOW_UART_INT */ -/* Description: Pending Junk Bus UART Interrupt */ -#define SH_EVENT_OVERFLOW_UART_INT_SHFT 20 -#define SH_EVENT_OVERFLOW_UART_INT_MASK 0x0000000000100000 - -/* SH_EVENT_OVERFLOW_L1_NMI_INT */ -/* Description: Pending L1 Controller NMI Interrupt */ -#define SH_EVENT_OVERFLOW_L1_NMI_INT_SHFT 21 -#define SH_EVENT_OVERFLOW_L1_NMI_INT_MASK 0x0000000000200000 - -/* SH_EVENT_OVERFLOW_STOP_CLOCK */ -/* Description: Pending Stop Clock Interrupt */ -#define SH_EVENT_OVERFLOW_STOP_CLOCK_SHFT 22 -#define SH_EVENT_OVERFLOW_STOP_CLOCK_MASK 0x0000000000400000 - -/* SH_EVENT_OVERFLOW_RTC0_INT */ -/* Description: Pending RTC 0 Interrupt */ -#define SH_EVENT_OVERFLOW_RTC0_INT_SHFT 23 -#define SH_EVENT_OVERFLOW_RTC0_INT_MASK 0x0000000000800000 - -/* SH_EVENT_OVERFLOW_RTC1_INT */ -/* Description: Pending RTC 1 Interrupt */ -#define SH_EVENT_OVERFLOW_RTC1_INT_SHFT 24 -#define SH_EVENT_OVERFLOW_RTC1_INT_MASK 0x0000000001000000 - -/* SH_EVENT_OVERFLOW_RTC2_INT */ -/* Description: Pending RTC 2 Interrupt */ -#define SH_EVENT_OVERFLOW_RTC2_INT_SHFT 25 -#define SH_EVENT_OVERFLOW_RTC2_INT_MASK 0x0000000002000000 - -/* SH_EVENT_OVERFLOW_RTC3_INT */ -/* Description: Pending RTC 3 Interrupt */ -#define SH_EVENT_OVERFLOW_RTC3_INT_SHFT 26 -#define SH_EVENT_OVERFLOW_RTC3_INT_MASK 0x0000000004000000 - -/* SH_EVENT_OVERFLOW_PROFILE_INT */ -/* Description: Pending Profile Interrupt */ -#define SH_EVENT_OVERFLOW_PROFILE_INT_SHFT 27 -#define SH_EVENT_OVERFLOW_PROFILE_INT_MASK 0x0000000008000000 - -/* ==================================================================== */ -/* Register "SH_EVENT_OVERFLOW_ALIAS" */ -/* SHub Interrupt Event Occurred Overflow Alias */ -/* ==================================================================== */ - -#define SH_EVENT_OVERFLOW_ALIAS 0x0000000110010088 - -/* ==================================================================== */ -/* Register "SH_JUNK_BUS_TIME" */ -/* Junk Bus Timing */ -/* ==================================================================== */ - -#define SH_JUNK_BUS_TIME 0x0000000110020000 -#define SH_JUNK_BUS_TIME_MASK 0x00000000ffffffff -#define SH_JUNK_BUS_TIME_INIT 0x0000000040404040 - -/* SH_JUNK_BUS_TIME_FPROM_SETUP_HOLD */ -/* Description: Fprom_Setup_Hold */ -#define SH_JUNK_BUS_TIME_FPROM_SETUP_HOLD_SHFT 0 -#define SH_JUNK_BUS_TIME_FPROM_SETUP_HOLD_MASK 0x00000000000000ff - -/* SH_JUNK_BUS_TIME_FPROM_ENABLE */ -/* Description: Fprom_Enable */ -#define SH_JUNK_BUS_TIME_FPROM_ENABLE_SHFT 8 -#define SH_JUNK_BUS_TIME_FPROM_ENABLE_MASK 0x000000000000ff00 - -/* SH_JUNK_BUS_TIME_UART_SETUP_HOLD */ -/* Description: Uart_Setup_Hold */ -#define SH_JUNK_BUS_TIME_UART_SETUP_HOLD_SHFT 16 -#define SH_JUNK_BUS_TIME_UART_SETUP_HOLD_MASK 0x0000000000ff0000 - -/* SH_JUNK_BUS_TIME_UART_ENABLE */ -/* Description: Uart_Enable */ -#define SH_JUNK_BUS_TIME_UART_ENABLE_SHFT 24 -#define SH_JUNK_BUS_TIME_UART_ENABLE_MASK 0x00000000ff000000 - -/* ==================================================================== */ -/* Register "SH_JUNK_LATCH_TIME" */ -/* Junk Bus Latch Timing */ -/* ==================================================================== */ - -#define SH_JUNK_LATCH_TIME 0x0000000110020080 -#define SH_JUNK_LATCH_TIME_MASK 0x0000000000000007 -#define SH_JUNK_LATCH_TIME_INIT 0x0000000000000002 - -/* SH_JUNK_LATCH_TIME_SETUP_HOLD */ -/* Description: Setup and Hold Time */ -#define SH_JUNK_LATCH_TIME_SETUP_HOLD_SHFT 0 -#define SH_JUNK_LATCH_TIME_SETUP_HOLD_MASK 0x0000000000000007 - -/* ==================================================================== */ -/* Register "SH_JUNK_NACK_RESET" */ -/* Junk Bus Nack Counter Reset */ -/* ==================================================================== */ - -#define SH_JUNK_NACK_RESET 0x0000000110020100 -#define SH_JUNK_NACK_RESET_MASK 0x0000000000000001 -#define SH_JUNK_NACK_RESET_INIT 0x0000000000000000 - -/* SH_JUNK_NACK_RESET_PULSE */ -/* Description: Junk bus nack counter reset */ -#define SH_JUNK_NACK_RESET_PULSE_SHFT 0 -#define SH_JUNK_NACK_RESET_PULSE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_JUNK_BUS_LED0" */ -/* Junk Bus LED0 */ -/* ==================================================================== */ - -#define SH_JUNK_BUS_LED0 0x0000000110030000 -#define SH_JUNK_BUS_LED0_MASK 0x00000000000000ff -#define SH_JUNK_BUS_LED0_INIT 0x0000000000000000 - -/* SH_JUNK_BUS_LED0_LED0_DATA */ -/* Description: LED0_data */ -#define SH_JUNK_BUS_LED0_LED0_DATA_SHFT 0 -#define SH_JUNK_BUS_LED0_LED0_DATA_MASK 0x00000000000000ff - -/* ==================================================================== */ -/* Register "SH_JUNK_BUS_LED1" */ -/* Junk Bus LED1 */ -/* ==================================================================== */ - -#define SH_JUNK_BUS_LED1 0x0000000110030080 -#define SH_JUNK_BUS_LED1_MASK 0x00000000000000ff -#define SH_JUNK_BUS_LED1_INIT 0x0000000000000000 - -/* SH_JUNK_BUS_LED1_LED1_DATA */ -/* Description: LED1_data */ -#define SH_JUNK_BUS_LED1_LED1_DATA_SHFT 0 -#define SH_JUNK_BUS_LED1_LED1_DATA_MASK 0x00000000000000ff - -/* ==================================================================== */ -/* Register "SH_JUNK_BUS_LED2" */ -/* Junk Bus LED2 */ -/* ==================================================================== */ - -#define SH_JUNK_BUS_LED2 0x0000000110030100 -#define SH_JUNK_BUS_LED2_MASK 0x00000000000000ff -#define SH_JUNK_BUS_LED2_INIT 0x0000000000000000 - -/* SH_JUNK_BUS_LED2_LED2_DATA */ -/* Description: LED2_data */ -#define SH_JUNK_BUS_LED2_LED2_DATA_SHFT 0 -#define SH_JUNK_BUS_LED2_LED2_DATA_MASK 0x00000000000000ff - -/* ==================================================================== */ -/* Register "SH_JUNK_BUS_LED3" */ -/* Junk Bus LED3 */ -/* ==================================================================== */ - -#define SH_JUNK_BUS_LED3 0x0000000110030180 -#define SH_JUNK_BUS_LED3_MASK 0x00000000000000ff -#define SH_JUNK_BUS_LED3_INIT 0x0000000000000000 - -/* SH_JUNK_BUS_LED3_LED3_DATA */ -/* Description: LED3_data */ -#define SH_JUNK_BUS_LED3_LED3_DATA_SHFT 0 -#define SH_JUNK_BUS_LED3_LED3_DATA_MASK 0x00000000000000ff - -/* ==================================================================== */ -/* Register "SH_JUNK_ERROR_STATUS" */ -/* Junk Bus Error Status */ -/* ==================================================================== */ - -#define SH_JUNK_ERROR_STATUS 0x0000000110030200 -#define SH_JUNK_ERROR_STATUS_MASK 0x1fff7fffffffffff -#define SH_JUNK_ERROR_STATUS_INIT 0x0000000000000000 - -/* SH_JUNK_ERROR_STATUS_ADDRESS */ -/* Description: Failing junk bus address */ -#define SH_JUNK_ERROR_STATUS_ADDRESS_SHFT 0 -#define SH_JUNK_ERROR_STATUS_ADDRESS_MASK 0x00007fffffffffff - -/* SH_JUNK_ERROR_STATUS_CMD */ -/* Description: Junk bus command */ -#define SH_JUNK_ERROR_STATUS_CMD_SHFT 48 -#define SH_JUNK_ERROR_STATUS_CMD_MASK 0x00ff000000000000 - -/* SH_JUNK_ERROR_STATUS_MODE */ -/* Description: Mode */ -#define SH_JUNK_ERROR_STATUS_MODE_SHFT 56 -#define SH_JUNK_ERROR_STATUS_MODE_MASK 0x0100000000000000 - -/* SH_JUNK_ERROR_STATUS_STATUS */ -/* Description: Status */ -#define SH_JUNK_ERROR_STATUS_STATUS_SHFT 57 -#define SH_JUNK_ERROR_STATUS_STATUS_MASK 0x1e00000000000000 - -/* ==================================================================== */ -/* Register "SH_NI0_LLP_STAT" */ -/* This register describes the LLP status. */ -/* ==================================================================== */ - -#define SH_NI0_LLP_STAT 0x0000000150000000 -#define SH_NI0_LLP_STAT_MASK 0x000000000000000f -#define SH_NI0_LLP_STAT_INIT 0x0000000000000000 - -/* SH_NI0_LLP_STAT_LINK_RESET_STATE */ -/* Description: Status of LLP link. */ -#define SH_NI0_LLP_STAT_LINK_RESET_STATE_SHFT 0 -#define SH_NI0_LLP_STAT_LINK_RESET_STATE_MASK 0x000000000000000f - -/* ==================================================================== */ -/* Register "SH_NI0_LLP_RESET" */ -/* Writing issues a reset to the network interface */ -/* ==================================================================== */ - -#define SH_NI0_LLP_RESET 0x0000000150000008 -#define SH_NI0_LLP_RESET_MASK 0x0000000000000003 -#define SH_NI0_LLP_RESET_INIT 0x0000000000000000 - -/* SH_NI0_LLP_RESET_LINK */ -/* Description: Send Link Reset. Generates a pulse. */ -#define SH_NI0_LLP_RESET_LINK_SHFT 0 -#define SH_NI0_LLP_RESET_LINK_MASK 0x0000000000000001 - -/* SH_NI0_LLP_RESET_WARM */ -/* Description: Send Warm Reset. Generates a pulse. */ -#define SH_NI0_LLP_RESET_WARM_SHFT 1 -#define SH_NI0_LLP_RESET_WARM_MASK 0x0000000000000002 - -/* ==================================================================== */ -/* Register "SH_NI0_LLP_RESET_EN" */ -/* Controls LLP warm reset propagation */ -/* ==================================================================== */ - -#define SH_NI0_LLP_RESET_EN 0x0000000150000010 -#define SH_NI0_LLP_RESET_EN_MASK 0x0000000000000001 -#define SH_NI0_LLP_RESET_EN_INIT 0x0000000000000001 - -/* SH_NI0_LLP_RESET_EN_OK */ -/* Description: Allow LLP warm reset to reset SHUB */ -#define SH_NI0_LLP_RESET_EN_OK_SHFT 0 -#define SH_NI0_LLP_RESET_EN_OK_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_NI0_LLP_CHAN_MODE" */ -/* Sets the signaling mode of LLP and channel */ -/* ==================================================================== */ - -#define SH_NI0_LLP_CHAN_MODE 0x0000000150000018 -#define SH_NI0_LLP_CHAN_MODE_MASK 0x000000000000001f -#define SH_NI0_LLP_CHAN_MODE_INIT 0x0000000000000000 - -/* SH_NI0_LLP_CHAN_MODE_BITMODE32 */ -/* Description: Enables 32-bit (plus sideband) channel phits */ -#define SH_NI0_LLP_CHAN_MODE_BITMODE32_SHFT 0 -#define SH_NI0_LLP_CHAN_MODE_BITMODE32_MASK 0x0000000000000001 - -/* SH_NI0_LLP_CHAN_MODE_AC_ENCODE */ -/* Description: Enables nearly dc-free encoding for AC-coupling */ -#define SH_NI0_LLP_CHAN_MODE_AC_ENCODE_SHFT 1 -#define SH_NI0_LLP_CHAN_MODE_AC_ENCODE_MASK 0x0000000000000002 - -/* SH_NI0_LLP_CHAN_MODE_ENABLE_TUNING */ -/* Description: Enables automatic tuning of channel skew. */ -#define SH_NI0_LLP_CHAN_MODE_ENABLE_TUNING_SHFT 2 -#define SH_NI0_LLP_CHAN_MODE_ENABLE_TUNING_MASK 0x0000000000000004 - -/* SH_NI0_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD */ -/* Description: Enables remote fine tune updates */ -#define SH_NI0_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD_SHFT 3 -#define SH_NI0_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD_MASK 0x0000000000000008 - -/* SH_NI0_LLP_CHAN_MODE_ENABLE_CLKQUAD */ -/* Description: Enables quadrature clock in the pfssd */ -#define SH_NI0_LLP_CHAN_MODE_ENABLE_CLKQUAD_SHFT 4 -#define SH_NI0_LLP_CHAN_MODE_ENABLE_CLKQUAD_MASK 0x0000000000000010 - -/* ==================================================================== */ -/* Register "SH_NI0_LLP_CONFIG" */ -/* Sets the configuration of LLP and channel */ -/* ==================================================================== */ - -#define SH_NI0_LLP_CONFIG 0x0000000150000020 -#define SH_NI0_LLP_CONFIG_MASK 0x0000003fffffffff -#define SH_NI0_LLP_CONFIG_INIT 0x00000007fc6ffd00 - -/* SH_NI0_LLP_CONFIG_MAXBURST */ -#define SH_NI0_LLP_CONFIG_MAXBURST_SHFT 0 -#define SH_NI0_LLP_CONFIG_MAXBURST_MASK 0x00000000000003ff - -/* SH_NI0_LLP_CONFIG_MAXRETRY */ -#define SH_NI0_LLP_CONFIG_MAXRETRY_SHFT 10 -#define SH_NI0_LLP_CONFIG_MAXRETRY_MASK 0x00000000000ffc00 - -/* SH_NI0_LLP_CONFIG_NULLTIMEOUT */ -#define SH_NI0_LLP_CONFIG_NULLTIMEOUT_SHFT 20 -#define SH_NI0_LLP_CONFIG_NULLTIMEOUT_MASK 0x0000000003f00000 - -/* SH_NI0_LLP_CONFIG_FTU_TIME */ -#define SH_NI0_LLP_CONFIG_FTU_TIME_SHFT 26 -#define SH_NI0_LLP_CONFIG_FTU_TIME_MASK 0x0000003ffc000000 - -/* ==================================================================== */ -/* Register "SH_NI0_LLP_TEST_CTL" */ -/* ==================================================================== */ - -#define SH_NI0_LLP_TEST_CTL 0x0000000150000028 -#define SH_NI0_LLP_TEST_CTL_MASK 0x7ff3f3ffffffffff -#define SH_NI0_LLP_TEST_CTL_INIT 0x000000000a5fffff - -/* SH_NI0_LLP_TEST_CTL_PATTERN */ -/* Description: Send channel data pattern */ -#define SH_NI0_LLP_TEST_CTL_PATTERN_SHFT 0 -#define SH_NI0_LLP_TEST_CTL_PATTERN_MASK 0x000000ffffffffff - -/* SH_NI0_LLP_TEST_CTL_SEND_TEST_MODE */ -/* Description: Enables continuous send of data */ -#define SH_NI0_LLP_TEST_CTL_SEND_TEST_MODE_SHFT 40 -#define SH_NI0_LLP_TEST_CTL_SEND_TEST_MODE_MASK 0x0000030000000000 - -/* SH_NI0_LLP_TEST_CTL_WIRE_SEL */ -#define SH_NI0_LLP_TEST_CTL_WIRE_SEL_SHFT 44 -#define SH_NI0_LLP_TEST_CTL_WIRE_SEL_MASK 0x0003f00000000000 - -/* SH_NI0_LLP_TEST_CTL_LFSR_MODE */ -#define SH_NI0_LLP_TEST_CTL_LFSR_MODE_SHFT 52 -#define SH_NI0_LLP_TEST_CTL_LFSR_MODE_MASK 0x0030000000000000 - -/* SH_NI0_LLP_TEST_CTL_NOISE_MODE */ -#define SH_NI0_LLP_TEST_CTL_NOISE_MODE_SHFT 54 -#define SH_NI0_LLP_TEST_CTL_NOISE_MODE_MASK 0x00c0000000000000 - -/* SH_NI0_LLP_TEST_CTL_ARMCAPTURE */ -/* Description: Enable Capture of Next MicroPacket */ -#define SH_NI0_LLP_TEST_CTL_ARMCAPTURE_SHFT 56 -#define SH_NI0_LLP_TEST_CTL_ARMCAPTURE_MASK 0x0100000000000000 - -/* SH_NI0_LLP_TEST_CTL_CAPTURECBONLY */ -/* Description: Only capture a micropacket with a Check Byte error */ -#define SH_NI0_LLP_TEST_CTL_CAPTURECBONLY_SHFT 57 -#define SH_NI0_LLP_TEST_CTL_CAPTURECBONLY_MASK 0x0200000000000000 - -/* SH_NI0_LLP_TEST_CTL_SENDCBERROR */ -/* Description: Sends a single error */ -#define SH_NI0_LLP_TEST_CTL_SENDCBERROR_SHFT 58 -#define SH_NI0_LLP_TEST_CTL_SENDCBERROR_MASK 0x0400000000000000 - -/* SH_NI0_LLP_TEST_CTL_SENDSNERROR */ -/* Description: Sends a single sequence number error */ -#define SH_NI0_LLP_TEST_CTL_SENDSNERROR_SHFT 59 -#define SH_NI0_LLP_TEST_CTL_SENDSNERROR_MASK 0x0800000000000000 - -/* SH_NI0_LLP_TEST_CTL_FAKESNERROR */ -/* Description: Causes receiver to pretend it saw a sn error */ -#define SH_NI0_LLP_TEST_CTL_FAKESNERROR_SHFT 60 -#define SH_NI0_LLP_TEST_CTL_FAKESNERROR_MASK 0x1000000000000000 - -/* SH_NI0_LLP_TEST_CTL_CAPTURED */ -/* Description: Indicates a Valid Micropacket was captured */ -#define SH_NI0_LLP_TEST_CTL_CAPTURED_SHFT 61 -#define SH_NI0_LLP_TEST_CTL_CAPTURED_MASK 0x2000000000000000 - -/* SH_NI0_LLP_TEST_CTL_CBERROR */ -/* Description: Indicates a Micropacket with a CB error was capture */ -#define SH_NI0_LLP_TEST_CTL_CBERROR_SHFT 62 -#define SH_NI0_LLP_TEST_CTL_CBERROR_MASK 0x4000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI0_LLP_CAPT_WD1" */ -/* low order 64-bit captured word */ -/* ==================================================================== */ - -#define SH_NI0_LLP_CAPT_WD1 0x0000000150000030 -#define SH_NI0_LLP_CAPT_WD1_MASK 0xffffffffffffffff -#define SH_NI0_LLP_CAPT_WD1_INIT 0x0000000000000000 - -/* SH_NI0_LLP_CAPT_WD1_DATA */ -/* Description: low order 64-bit captured word */ -#define SH_NI0_LLP_CAPT_WD1_DATA_SHFT 0 -#define SH_NI0_LLP_CAPT_WD1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_NI0_LLP_CAPT_WD2" */ -/* high order 64-bit captured word */ -/* ==================================================================== */ - -#define SH_NI0_LLP_CAPT_WD2 0x0000000150000038 -#define SH_NI0_LLP_CAPT_WD2_MASK 0xffffffffffffffff -#define SH_NI0_LLP_CAPT_WD2_INIT 0x0000000000000000 - -/* SH_NI0_LLP_CAPT_WD2_DATA */ -/* Description: high order 64-bit captured word */ -#define SH_NI0_LLP_CAPT_WD2_DATA_SHFT 0 -#define SH_NI0_LLP_CAPT_WD2_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_NI0_LLP_CAPT_SBCB" */ -/* captured sideband, sequence, and CRC */ -/* ==================================================================== */ - -#define SH_NI0_LLP_CAPT_SBCB 0x0000000150000040 -#define SH_NI0_LLP_CAPT_SBCB_MASK 0x0000001fffffffff -#define SH_NI0_LLP_CAPT_SBCB_INIT 0x0000000000000000 - -/* SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVSBSN */ -/* Description: sideband and sequence */ -#define SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVSBSN_SHFT 0 -#define SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVSBSN_MASK 0x000000000000ffff - -/* SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVCRC */ -/* Description: CRC */ -#define SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVCRC_SHFT 16 -#define SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVCRC_MASK 0x00000000ffff0000 - -/* SH_NI0_LLP_CAPT_SBCB_SENTALLCBERRORS */ -/* Description: All CB errors have been sent */ -#define SH_NI0_LLP_CAPT_SBCB_SENTALLCBERRORS_SHFT 32 -#define SH_NI0_LLP_CAPT_SBCB_SENTALLCBERRORS_MASK 0x0000000100000000 - -/* SH_NI0_LLP_CAPT_SBCB_SENTALLSNERRORS */ -/* Description: All SN errors have been sent */ -#define SH_NI0_LLP_CAPT_SBCB_SENTALLSNERRORS_SHFT 33 -#define SH_NI0_LLP_CAPT_SBCB_SENTALLSNERRORS_MASK 0x0000000200000000 - -/* SH_NI0_LLP_CAPT_SBCB_FAKEDALLSNERRORS */ -/* Description: All faked SN errors have been sent */ -#define SH_NI0_LLP_CAPT_SBCB_FAKEDALLSNERRORS_SHFT 34 -#define SH_NI0_LLP_CAPT_SBCB_FAKEDALLSNERRORS_MASK 0x0000000400000000 - -/* SH_NI0_LLP_CAPT_SBCB_CHARGEOVERFLOW */ -/* Description: wire charge counter overflowed, valid if llp_mode e */ -#define SH_NI0_LLP_CAPT_SBCB_CHARGEOVERFLOW_SHFT 35 -#define SH_NI0_LLP_CAPT_SBCB_CHARGEOVERFLOW_MASK 0x0000000800000000 - -/* SH_NI0_LLP_CAPT_SBCB_CHARGEUNDERFLOW */ -/* Description: wire charge counter underflowed, valid if llp_mode */ -/* enabled */ -#define SH_NI0_LLP_CAPT_SBCB_CHARGEUNDERFLOW_SHFT 36 -#define SH_NI0_LLP_CAPT_SBCB_CHARGEUNDERFLOW_MASK 0x0000001000000000 - -/* ==================================================================== */ -/* Register "SH_NI0_LLP_ERR" */ -/* ==================================================================== */ - -#define SH_NI0_LLP_ERR 0x0000000150000048 -#define SH_NI0_LLP_ERR_MASK 0x001fffffffffffff -#define SH_NI0_LLP_ERR_INIT 0x0000000000000000 - -/* SH_NI0_LLP_ERR_RX_SN_ERR_COUNT */ -/* Description: Counts the sequence number errors received */ -#define SH_NI0_LLP_ERR_RX_SN_ERR_COUNT_SHFT 0 -#define SH_NI0_LLP_ERR_RX_SN_ERR_COUNT_MASK 0x00000000000000ff - -/* SH_NI0_LLP_ERR_RX_CB_ERR_COUNT */ -/* Description: Counts the check byte errors received */ -#define SH_NI0_LLP_ERR_RX_CB_ERR_COUNT_SHFT 8 -#define SH_NI0_LLP_ERR_RX_CB_ERR_COUNT_MASK 0x000000000000ff00 - -/* SH_NI0_LLP_ERR_RETRY_COUNT */ -/* Description: Counts the retries */ -#define SH_NI0_LLP_ERR_RETRY_COUNT_SHFT 16 -#define SH_NI0_LLP_ERR_RETRY_COUNT_MASK 0x0000000000ff0000 - -/* SH_NI0_LLP_ERR_RETRY_TIMEOUT */ -/* Description: Indicates a retry timeout has occurred */ -#define SH_NI0_LLP_ERR_RETRY_TIMEOUT_SHFT 24 -#define SH_NI0_LLP_ERR_RETRY_TIMEOUT_MASK 0x0000000001000000 - -/* SH_NI0_LLP_ERR_RCV_LINK_RESET */ -/* Description: Indicates a link reset has been received */ -#define SH_NI0_LLP_ERR_RCV_LINK_RESET_SHFT 25 -#define SH_NI0_LLP_ERR_RCV_LINK_RESET_MASK 0x0000000002000000 - -/* SH_NI0_LLP_ERR_SQUASH */ -/* Description: Indicates a micropacket was squashed */ -#define SH_NI0_LLP_ERR_SQUASH_SHFT 26 -#define SH_NI0_LLP_ERR_SQUASH_MASK 0x0000000004000000 - -/* SH_NI0_LLP_ERR_POWER_NOT_OK */ -/* Description: Detects and traps a loss of power_OK */ -#define SH_NI0_LLP_ERR_POWER_NOT_OK_SHFT 27 -#define SH_NI0_LLP_ERR_POWER_NOT_OK_MASK 0x0000000008000000 - -/* SH_NI0_LLP_ERR_WIRE_CNT */ -/* Description: counts the errors detected on a single wire test */ -#define SH_NI0_LLP_ERR_WIRE_CNT_SHFT 28 -#define SH_NI0_LLP_ERR_WIRE_CNT_MASK 0x000ffffff0000000 - -/* SH_NI0_LLP_ERR_WIRE_OVERFLOW */ -/* Description: wire_error_cnt has overflowed */ -#define SH_NI0_LLP_ERR_WIRE_OVERFLOW_SHFT 52 -#define SH_NI0_LLP_ERR_WIRE_OVERFLOW_MASK 0x0010000000000000 - -/* ==================================================================== */ -/* Register "SH_NI1_LLP_STAT" */ -/* This register describes the LLP status. */ -/* ==================================================================== */ - -#define SH_NI1_LLP_STAT 0x0000000150002000 -#define SH_NI1_LLP_STAT_MASK 0x000000000000000f -#define SH_NI1_LLP_STAT_INIT 0x0000000000000000 - -/* SH_NI1_LLP_STAT_LINK_RESET_STATE */ -/* Description: Status of LLP link. */ -#define SH_NI1_LLP_STAT_LINK_RESET_STATE_SHFT 0 -#define SH_NI1_LLP_STAT_LINK_RESET_STATE_MASK 0x000000000000000f - -/* ==================================================================== */ -/* Register "SH_NI1_LLP_RESET" */ -/* Writing issues a reset to the network interface */ -/* ==================================================================== */ - -#define SH_NI1_LLP_RESET 0x0000000150002008 -#define SH_NI1_LLP_RESET_MASK 0x0000000000000003 -#define SH_NI1_LLP_RESET_INIT 0x0000000000000000 - -/* SH_NI1_LLP_RESET_LINK */ -/* Description: Send Link Reset. Generates a pulse. */ -#define SH_NI1_LLP_RESET_LINK_SHFT 0 -#define SH_NI1_LLP_RESET_LINK_MASK 0x0000000000000001 - -/* SH_NI1_LLP_RESET_WARM */ -/* Description: Send Warm Reset. Generates a pulse. */ -#define SH_NI1_LLP_RESET_WARM_SHFT 1 -#define SH_NI1_LLP_RESET_WARM_MASK 0x0000000000000002 - -/* ==================================================================== */ -/* Register "SH_NI1_LLP_RESET_EN" */ -/* Controls LLP warm reset propagation */ -/* ==================================================================== */ - -#define SH_NI1_LLP_RESET_EN 0x0000000150002010 -#define SH_NI1_LLP_RESET_EN_MASK 0x0000000000000001 -#define SH_NI1_LLP_RESET_EN_INIT 0x0000000000000001 - -/* SH_NI1_LLP_RESET_EN_OK */ -/* Description: Allow LLP warm reset to reset SHUB */ -#define SH_NI1_LLP_RESET_EN_OK_SHFT 0 -#define SH_NI1_LLP_RESET_EN_OK_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_NI1_LLP_CHAN_MODE" */ -/* Sets the signaling mode of LLP and channel */ -/* ==================================================================== */ - -#define SH_NI1_LLP_CHAN_MODE 0x0000000150002018 -#define SH_NI1_LLP_CHAN_MODE_MASK 0x000000000000001f -#define SH_NI1_LLP_CHAN_MODE_INIT 0x0000000000000000 - -/* SH_NI1_LLP_CHAN_MODE_BITMODE32 */ -/* Description: Enables 32-bit (plus sideband) channel phits */ -#define SH_NI1_LLP_CHAN_MODE_BITMODE32_SHFT 0 -#define SH_NI1_LLP_CHAN_MODE_BITMODE32_MASK 0x0000000000000001 - -/* SH_NI1_LLP_CHAN_MODE_AC_ENCODE */ -/* Description: Enables nearly dc-free encoding for AC-coupling */ -#define SH_NI1_LLP_CHAN_MODE_AC_ENCODE_SHFT 1 -#define SH_NI1_LLP_CHAN_MODE_AC_ENCODE_MASK 0x0000000000000002 - -/* SH_NI1_LLP_CHAN_MODE_ENABLE_TUNING */ -/* Description: Enables automatic tuning of channel skew. */ -#define SH_NI1_LLP_CHAN_MODE_ENABLE_TUNING_SHFT 2 -#define SH_NI1_LLP_CHAN_MODE_ENABLE_TUNING_MASK 0x0000000000000004 - -/* SH_NI1_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD */ -/* Description: Enables remote fine tune updates */ -#define SH_NI1_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD_SHFT 3 -#define SH_NI1_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD_MASK 0x0000000000000008 - -/* SH_NI1_LLP_CHAN_MODE_ENABLE_CLKQUAD */ -/* Description: Enables quadrature clock in the pfssd */ -#define SH_NI1_LLP_CHAN_MODE_ENABLE_CLKQUAD_SHFT 4 -#define SH_NI1_LLP_CHAN_MODE_ENABLE_CLKQUAD_MASK 0x0000000000000010 - -/* ==================================================================== */ -/* Register "SH_NI1_LLP_CONFIG" */ -/* Sets the configuration of LLP and channel */ -/* ==================================================================== */ - -#define SH_NI1_LLP_CONFIG 0x0000000150002020 -#define SH_NI1_LLP_CONFIG_MASK 0x0000003fffffffff -#define SH_NI1_LLP_CONFIG_INIT 0x00000007fc6ffd00 - -/* SH_NI1_LLP_CONFIG_MAXBURST */ -#define SH_NI1_LLP_CONFIG_MAXBURST_SHFT 0 -#define SH_NI1_LLP_CONFIG_MAXBURST_MASK 0x00000000000003ff - -/* SH_NI1_LLP_CONFIG_MAXRETRY */ -#define SH_NI1_LLP_CONFIG_MAXRETRY_SHFT 10 -#define SH_NI1_LLP_CONFIG_MAXRETRY_MASK 0x00000000000ffc00 - -/* SH_NI1_LLP_CONFIG_NULLTIMEOUT */ -#define SH_NI1_LLP_CONFIG_NULLTIMEOUT_SHFT 20 -#define SH_NI1_LLP_CONFIG_NULLTIMEOUT_MASK 0x0000000003f00000 - -/* SH_NI1_LLP_CONFIG_FTU_TIME */ -#define SH_NI1_LLP_CONFIG_FTU_TIME_SHFT 26 -#define SH_NI1_LLP_CONFIG_FTU_TIME_MASK 0x0000003ffc000000 - -/* ==================================================================== */ -/* Register "SH_NI1_LLP_TEST_CTL" */ -/* ==================================================================== */ - -#define SH_NI1_LLP_TEST_CTL 0x0000000150002028 -#define SH_NI1_LLP_TEST_CTL_MASK 0x7ff3f3ffffffffff -#define SH_NI1_LLP_TEST_CTL_INIT 0x000000000a5fffff - -/* SH_NI1_LLP_TEST_CTL_PATTERN */ -/* Description: Send channel data pattern */ -#define SH_NI1_LLP_TEST_CTL_PATTERN_SHFT 0 -#define SH_NI1_LLP_TEST_CTL_PATTERN_MASK 0x000000ffffffffff - -/* SH_NI1_LLP_TEST_CTL_SEND_TEST_MODE */ -/* Description: Enables continuous send of data */ -#define SH_NI1_LLP_TEST_CTL_SEND_TEST_MODE_SHFT 40 -#define SH_NI1_LLP_TEST_CTL_SEND_TEST_MODE_MASK 0x0000030000000000 - -/* SH_NI1_LLP_TEST_CTL_WIRE_SEL */ -#define SH_NI1_LLP_TEST_CTL_WIRE_SEL_SHFT 44 -#define SH_NI1_LLP_TEST_CTL_WIRE_SEL_MASK 0x0003f00000000000 - -/* SH_NI1_LLP_TEST_CTL_LFSR_MODE */ -#define SH_NI1_LLP_TEST_CTL_LFSR_MODE_SHFT 52 -#define SH_NI1_LLP_TEST_CTL_LFSR_MODE_MASK 0x0030000000000000 - -/* SH_NI1_LLP_TEST_CTL_NOISE_MODE */ -#define SH_NI1_LLP_TEST_CTL_NOISE_MODE_SHFT 54 -#define SH_NI1_LLP_TEST_CTL_NOISE_MODE_MASK 0x00c0000000000000 - -/* SH_NI1_LLP_TEST_CTL_ARMCAPTURE */ -/* Description: Enable Capture of Next MicroPacket */ -#define SH_NI1_LLP_TEST_CTL_ARMCAPTURE_SHFT 56 -#define SH_NI1_LLP_TEST_CTL_ARMCAPTURE_MASK 0x0100000000000000 - -/* SH_NI1_LLP_TEST_CTL_CAPTURECBONLY */ -/* Description: Only capture a micropacket with a Check Byte error */ -#define SH_NI1_LLP_TEST_CTL_CAPTURECBONLY_SHFT 57 -#define SH_NI1_LLP_TEST_CTL_CAPTURECBONLY_MASK 0x0200000000000000 - -/* SH_NI1_LLP_TEST_CTL_SENDCBERROR */ -/* Description: Sends a single error */ -#define SH_NI1_LLP_TEST_CTL_SENDCBERROR_SHFT 58 -#define SH_NI1_LLP_TEST_CTL_SENDCBERROR_MASK 0x0400000000000000 - -/* SH_NI1_LLP_TEST_CTL_SENDSNERROR */ -/* Description: Sends a single sequence number error */ -#define SH_NI1_LLP_TEST_CTL_SENDSNERROR_SHFT 59 -#define SH_NI1_LLP_TEST_CTL_SENDSNERROR_MASK 0x0800000000000000 - -/* SH_NI1_LLP_TEST_CTL_FAKESNERROR */ -/* Description: Causes receiver to pretend it saw a sn error */ -#define SH_NI1_LLP_TEST_CTL_FAKESNERROR_SHFT 60 -#define SH_NI1_LLP_TEST_CTL_FAKESNERROR_MASK 0x1000000000000000 - -/* SH_NI1_LLP_TEST_CTL_CAPTURED */ -/* Description: Indicates a Valid Micropacket was captured */ -#define SH_NI1_LLP_TEST_CTL_CAPTURED_SHFT 61 -#define SH_NI1_LLP_TEST_CTL_CAPTURED_MASK 0x2000000000000000 - -/* SH_NI1_LLP_TEST_CTL_CBERROR */ -/* Description: Indicates a Micropacket with a CB error was capture */ -#define SH_NI1_LLP_TEST_CTL_CBERROR_SHFT 62 -#define SH_NI1_LLP_TEST_CTL_CBERROR_MASK 0x4000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI1_LLP_CAPT_WD1" */ -/* low order 64-bit captured word */ -/* ==================================================================== */ - -#define SH_NI1_LLP_CAPT_WD1 0x0000000150002030 -#define SH_NI1_LLP_CAPT_WD1_MASK 0xffffffffffffffff -#define SH_NI1_LLP_CAPT_WD1_INIT 0x0000000000000000 - -/* SH_NI1_LLP_CAPT_WD1_DATA */ -/* Description: low order 64-bit captured word */ -#define SH_NI1_LLP_CAPT_WD1_DATA_SHFT 0 -#define SH_NI1_LLP_CAPT_WD1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_NI1_LLP_CAPT_WD2" */ -/* high order 64-bit captured word */ -/* ==================================================================== */ - -#define SH_NI1_LLP_CAPT_WD2 0x0000000150002038 -#define SH_NI1_LLP_CAPT_WD2_MASK 0xffffffffffffffff -#define SH_NI1_LLP_CAPT_WD2_INIT 0x0000000000000000 - -/* SH_NI1_LLP_CAPT_WD2_DATA */ -/* Description: high order 64-bit captured word */ -#define SH_NI1_LLP_CAPT_WD2_DATA_SHFT 0 -#define SH_NI1_LLP_CAPT_WD2_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_NI1_LLP_CAPT_SBCB" */ -/* captured sideband, sequence, and CRC */ -/* ==================================================================== */ - -#define SH_NI1_LLP_CAPT_SBCB 0x0000000150002040 -#define SH_NI1_LLP_CAPT_SBCB_MASK 0x0000001fffffffff -#define SH_NI1_LLP_CAPT_SBCB_INIT 0x0000000000000000 - -/* SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVSBSN */ -/* Description: sideband and sequence */ -#define SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVSBSN_SHFT 0 -#define SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVSBSN_MASK 0x000000000000ffff - -/* SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVCRC */ -/* Description: CRC */ -#define SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVCRC_SHFT 16 -#define SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVCRC_MASK 0x00000000ffff0000 - -/* SH_NI1_LLP_CAPT_SBCB_SENTALLCBERRORS */ -/* Description: All CB errors have been sent */ -#define SH_NI1_LLP_CAPT_SBCB_SENTALLCBERRORS_SHFT 32 -#define SH_NI1_LLP_CAPT_SBCB_SENTALLCBERRORS_MASK 0x0000000100000000 - -/* SH_NI1_LLP_CAPT_SBCB_SENTALLSNERRORS */ -/* Description: All SN errors have been sent */ -#define SH_NI1_LLP_CAPT_SBCB_SENTALLSNERRORS_SHFT 33 -#define SH_NI1_LLP_CAPT_SBCB_SENTALLSNERRORS_MASK 0x0000000200000000 - -/* SH_NI1_LLP_CAPT_SBCB_FAKEDALLSNERRORS */ -/* Description: All faked SN errors have been sent */ -#define SH_NI1_LLP_CAPT_SBCB_FAKEDALLSNERRORS_SHFT 34 -#define SH_NI1_LLP_CAPT_SBCB_FAKEDALLSNERRORS_MASK 0x0000000400000000 - -/* SH_NI1_LLP_CAPT_SBCB_CHARGEOVERFLOW */ -/* Description: wire charge counter overflowed, valid if llp_mode e */ -#define SH_NI1_LLP_CAPT_SBCB_CHARGEOVERFLOW_SHFT 35 -#define SH_NI1_LLP_CAPT_SBCB_CHARGEOVERFLOW_MASK 0x0000000800000000 - -/* SH_NI1_LLP_CAPT_SBCB_CHARGEUNDERFLOW */ -/* Description: wire charge counter underflowed, valid if llp_mode */ -/* enabled */ -#define SH_NI1_LLP_CAPT_SBCB_CHARGEUNDERFLOW_SHFT 36 -#define SH_NI1_LLP_CAPT_SBCB_CHARGEUNDERFLOW_MASK 0x0000001000000000 - -/* ==================================================================== */ -/* Register "SH_NI1_LLP_ERR" */ -/* ==================================================================== */ - -#define SH_NI1_LLP_ERR 0x0000000150002048 -#define SH_NI1_LLP_ERR_MASK 0x001fffffffffffff -#define SH_NI1_LLP_ERR_INIT 0x0000000000000000 - -/* SH_NI1_LLP_ERR_RX_SN_ERR_COUNT */ -/* Description: Counts the sequence number errors received */ -#define SH_NI1_LLP_ERR_RX_SN_ERR_COUNT_SHFT 0 -#define SH_NI1_LLP_ERR_RX_SN_ERR_COUNT_MASK 0x00000000000000ff - -/* SH_NI1_LLP_ERR_RX_CB_ERR_COUNT */ -/* Description: Counts the check byte errors received */ -#define SH_NI1_LLP_ERR_RX_CB_ERR_COUNT_SHFT 8 -#define SH_NI1_LLP_ERR_RX_CB_ERR_COUNT_MASK 0x000000000000ff00 - -/* SH_NI1_LLP_ERR_RETRY_COUNT */ -/* Description: Counts the retries */ -#define SH_NI1_LLP_ERR_RETRY_COUNT_SHFT 16 -#define SH_NI1_LLP_ERR_RETRY_COUNT_MASK 0x0000000000ff0000 - -/* SH_NI1_LLP_ERR_RETRY_TIMEOUT */ -/* Description: Indicates a retry timeout has occurred */ -#define SH_NI1_LLP_ERR_RETRY_TIMEOUT_SHFT 24 -#define SH_NI1_LLP_ERR_RETRY_TIMEOUT_MASK 0x0000000001000000 - -/* SH_NI1_LLP_ERR_RCV_LINK_RESET */ -/* Description: Indicates a link reset has been received */ -#define SH_NI1_LLP_ERR_RCV_LINK_RESET_SHFT 25 -#define SH_NI1_LLP_ERR_RCV_LINK_RESET_MASK 0x0000000002000000 - -/* SH_NI1_LLP_ERR_SQUASH */ -/* Description: Indicates a micropacket was squashed */ -#define SH_NI1_LLP_ERR_SQUASH_SHFT 26 -#define SH_NI1_LLP_ERR_SQUASH_MASK 0x0000000004000000 - -/* SH_NI1_LLP_ERR_POWER_NOT_OK */ -/* Description: Detects and traps a loss of power_OK */ -#define SH_NI1_LLP_ERR_POWER_NOT_OK_SHFT 27 -#define SH_NI1_LLP_ERR_POWER_NOT_OK_MASK 0x0000000008000000 - -/* SH_NI1_LLP_ERR_WIRE_CNT */ -/* Description: counts the errors detected on a single wire test */ -#define SH_NI1_LLP_ERR_WIRE_CNT_SHFT 28 -#define SH_NI1_LLP_ERR_WIRE_CNT_MASK 0x000ffffff0000000 - -/* SH_NI1_LLP_ERR_WIRE_OVERFLOW */ -/* Description: wire_error_cnt has overflowed */ -#define SH_NI1_LLP_ERR_WIRE_OVERFLOW_SHFT 52 -#define SH_NI1_LLP_ERR_WIRE_OVERFLOW_MASK 0x0010000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_LLP_TO_FIFO02_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_LLP_TO_FIFO02_FLOW 0x0000000150001010 -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_MASK 0x3f3f003f3f00bfbf -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN_SHFT 24 -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000 - -/* SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP_SHFT 32 -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000 - -/* SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN_SHFT 48 -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000 - -/* SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP_SHFT 56 -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_LLP_TO_FIFO13_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_LLP_TO_FIFO13_FLOW 0x0000000150001020 -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_MASK 0x3f3f003f3f00bfbf -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN_SHFT 24 -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000 - -/* SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP_SHFT 32 -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000 - -/* SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN_SHFT 48 -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000 - -/* SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP_SHFT 56 -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_LLP_DEBIT_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_LLP_DEBIT_FLOW 0x0000000150001030 -#define SH_XNNI0_LLP_DEBIT_FLOW_MASK 0x1f1f1f1f1f1f1f1f -#define SH_XNNI0_LLP_DEBIT_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_DYN */ -/* Description: vc0 debit dynamic value */ -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_DYN_SHFT 0 -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_DYN_MASK 0x000000000000001f - -/* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_CAP */ -/* Description: vc0 debit captured value */ -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_CAP_SHFT 8 -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_CAP_MASK 0x0000000000001f00 - -/* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_DYN */ -/* Description: vc1 debit dynamic value */ -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_DYN_SHFT 16 -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_DYN_MASK 0x00000000001f0000 - -/* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_CAP */ -/* Description: vc1 debit captured value */ -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_CAP_SHFT 24 -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_CAP_MASK 0x000000001f000000 - -/* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_DYN */ -/* Description: vc2 debit dynamic value */ -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_DYN_SHFT 32 -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_DYN_MASK 0x0000001f00000000 - -/* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_CAP */ -/* Description: vc2 debit captured value */ -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_CAP_SHFT 40 -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_CAP_MASK 0x00001f0000000000 - -/* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_DYN */ -/* Description: vc3 debit dynamic value */ -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_DYN_SHFT 48 -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_DYN_MASK 0x001f000000000000 - -/* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_CAP */ -/* Description: vc3 debit captured value */ -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_CAP_SHFT 56 -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_CAP_MASK 0x1f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_LINK_0_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_LINK_0_FLOW 0x0000000150001040 -#define SH_XNNI0_LINK_0_FLOW_MASK 0x000000007f7f7fbf -#define SH_XNNI0_LINK_0_FLOW_INIT 0x0000000000001800 - -/* SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on vc0 from debit cntr */ -#define SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 Limit Test */ -#define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_TEST_SHFT 8 -#define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_TEST_MASK 0x0000000000007f00 - -/* SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_DYN */ -/* Description: Dynamic vc0 credit value */ -#define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_DYN_SHFT 16 -#define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_DYN_MASK 0x00000000007f0000 - -/* SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_CAP */ -/* Description: Captured vc0 credit */ -#define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_CAP_SHFT 24 -#define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_CAP_MASK 0x000000007f000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_LINK_1_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_LINK_1_FLOW 0x0000000150001050 -#define SH_XNNI0_LINK_1_FLOW_MASK 0x000000007f7f7fbf -#define SH_XNNI0_LINK_1_FLOW_INIT 0x0000000000001800 - -/* SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_WITHHOLD */ -/* Description: vc1 withhold */ -#define SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_WITHHOLD_SHFT 0 -#define SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED */ -/* Description: Force Credit on vc1 from debit cntr */ -#define SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED_SHFT 7 -#define SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_TEST */ -/* Description: vc1 Limit Test */ -#define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_TEST_SHFT 8 -#define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_TEST_MASK 0x0000000000007f00 - -/* SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_DYN */ -/* Description: Dynamic vc1 credit value */ -#define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_DYN_SHFT 16 -#define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_DYN_MASK 0x00000000007f0000 - -/* SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_CAP */ -/* Description: Captured vc1 credit */ -#define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_CAP_SHFT 24 -#define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_CAP_MASK 0x000000007f000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_LINK_2_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_LINK_2_FLOW 0x0000000150001060 -#define SH_XNNI0_LINK_2_FLOW_MASK 0x000000007f7f7fbf -#define SH_XNNI0_LINK_2_FLOW_INIT 0x0000000000001800 - -/* SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_WITHHOLD_SHFT 0 -#define SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on vc2 from debit cntr */ -#define SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 7 -#define SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 Limit Test */ -#define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_TEST_SHFT 8 -#define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_TEST_MASK 0x0000000000007f00 - -/* SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_DYN */ -/* Description: Dynamic vc2 credit value */ -#define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_DYN_SHFT 16 -#define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_DYN_MASK 0x00000000007f0000 - -/* SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_CAP */ -/* Description: Captured vc2 credit */ -#define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_CAP_SHFT 24 -#define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_CAP_MASK 0x000000007f000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_LINK_3_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_LINK_3_FLOW 0x0000000150001070 -#define SH_XNNI0_LINK_3_FLOW_MASK 0x000000007f7f7fbf -#define SH_XNNI0_LINK_3_FLOW_INIT 0x0000000000001800 - -/* SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_WITHHOLD */ -/* Description: vc3 withhold */ -#define SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_WITHHOLD_SHFT 0 -#define SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED */ -/* Description: Force Credit on vc3 from debit cntr */ -#define SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED_SHFT 7 -#define SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_TEST */ -/* Description: vc3 Limit Test */ -#define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_TEST_SHFT 8 -#define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_TEST_MASK 0x0000000000007f00 - -/* SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_DYN */ -/* Description: Dynamic vc3 credit value */ -#define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_DYN_SHFT 16 -#define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_DYN_MASK 0x00000000007f0000 - -/* SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_CAP */ -/* Description: Captured vc3 credit */ -#define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_CAP_SHFT 24 -#define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_CAP_MASK 0x000000007f000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_LLP_TO_FIFO02_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_LLP_TO_FIFO02_FLOW 0x0000000150003010 -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_MASK 0x3f3f003f3f00bfbf -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN_SHFT 24 -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000 - -/* SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP_SHFT 32 -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000 - -/* SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN_SHFT 48 -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000 - -/* SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP_SHFT 56 -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_LLP_TO_FIFO13_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_LLP_TO_FIFO13_FLOW 0x0000000150003020 -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_MASK 0x3f3f003f3f00bfbf -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN_SHFT 24 -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000 - -/* SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP_SHFT 32 -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000 - -/* SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN_SHFT 48 -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000 - -/* SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP_SHFT 56 -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_LLP_DEBIT_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_LLP_DEBIT_FLOW 0x0000000150003030 -#define SH_XNNI1_LLP_DEBIT_FLOW_MASK 0x1f1f1f1f1f1f1f1f -#define SH_XNNI1_LLP_DEBIT_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_DYN */ -/* Description: vc0 debit dynamic value */ -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_DYN_SHFT 0 -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_DYN_MASK 0x000000000000001f - -/* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_CAP */ -/* Description: vc0 debit captured value */ -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_CAP_SHFT 8 -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_CAP_MASK 0x0000000000001f00 - -/* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_DYN */ -/* Description: vc1 debit dynamic value */ -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_DYN_SHFT 16 -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_DYN_MASK 0x00000000001f0000 - -/* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_CAP */ -/* Description: vc1 debit captured value */ -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_CAP_SHFT 24 -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_CAP_MASK 0x000000001f000000 - -/* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_DYN */ -/* Description: vc2 debit dynamic value */ -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_DYN_SHFT 32 -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_DYN_MASK 0x0000001f00000000 - -/* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_CAP */ -/* Description: vc2 debit captured value */ -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_CAP_SHFT 40 -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_CAP_MASK 0x00001f0000000000 - -/* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_DYN */ -/* Description: vc3 debit dynamic value */ -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_DYN_SHFT 48 -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_DYN_MASK 0x001f000000000000 - -/* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_CAP */ -/* Description: vc3 debit captured value */ -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_CAP_SHFT 56 -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_CAP_MASK 0x1f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_LINK_0_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_LINK_0_FLOW 0x0000000150003040 -#define SH_XNNI1_LINK_0_FLOW_MASK 0x000000007f7f7fbf -#define SH_XNNI1_LINK_0_FLOW_INIT 0x0000000000001800 - -/* SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on vc0 from debit cntr */ -#define SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 Limit Test */ -#define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_TEST_SHFT 8 -#define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_TEST_MASK 0x0000000000007f00 - -/* SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_DYN */ -/* Description: Dynamic vc0 credit value */ -#define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_DYN_SHFT 16 -#define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_DYN_MASK 0x00000000007f0000 - -/* SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_CAP */ -/* Description: Captured vc0 credit */ -#define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_CAP_SHFT 24 -#define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_CAP_MASK 0x000000007f000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_LINK_1_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_LINK_1_FLOW 0x0000000150003050 -#define SH_XNNI1_LINK_1_FLOW_MASK 0x000000007f7f7fbf -#define SH_XNNI1_LINK_1_FLOW_INIT 0x0000000000001800 - -/* SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_WITHHOLD */ -/* Description: vc1 withhold */ -#define SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_WITHHOLD_SHFT 0 -#define SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED */ -/* Description: Force Credit on vc1 from debit cntr */ -#define SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED_SHFT 7 -#define SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_TEST */ -/* Description: vc1 Limit Test */ -#define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_TEST_SHFT 8 -#define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_TEST_MASK 0x0000000000007f00 - -/* SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_DYN */ -/* Description: Dynamic vc1 credit value */ -#define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_DYN_SHFT 16 -#define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_DYN_MASK 0x00000000007f0000 - -/* SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_CAP */ -/* Description: Captured vc1 credit */ -#define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_CAP_SHFT 24 -#define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_CAP_MASK 0x000000007f000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_LINK_2_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_LINK_2_FLOW 0x0000000150003060 -#define SH_XNNI1_LINK_2_FLOW_MASK 0x000000007f7f7fbf -#define SH_XNNI1_LINK_2_FLOW_INIT 0x0000000000001800 - -/* SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_WITHHOLD_SHFT 0 -#define SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on vc2 from debit cntr */ -#define SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 7 -#define SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 Limit Test */ -#define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_TEST_SHFT 8 -#define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_TEST_MASK 0x0000000000007f00 - -/* SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_DYN */ -/* Description: Dynamic vc2 credit value */ -#define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_DYN_SHFT 16 -#define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_DYN_MASK 0x00000000007f0000 - -/* SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_CAP */ -/* Description: Captured vc2 credit */ -#define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_CAP_SHFT 24 -#define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_CAP_MASK 0x000000007f000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_LINK_3_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_LINK_3_FLOW 0x0000000150003070 -#define SH_XNNI1_LINK_3_FLOW_MASK 0x000000007f7f7fbf -#define SH_XNNI1_LINK_3_FLOW_INIT 0x0000000000001800 - -/* SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_WITHHOLD */ -/* Description: vc3 withhold */ -#define SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_WITHHOLD_SHFT 0 -#define SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED */ -/* Description: Force Credit on vc3 from debit cntr */ -#define SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED_SHFT 7 -#define SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_TEST */ -/* Description: vc3 Limit Test */ -#define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_TEST_SHFT 8 -#define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_TEST_MASK 0x0000000000007f00 - -/* SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_DYN */ -/* Description: Dynamic vc3 credit value */ -#define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_DYN_SHFT 16 -#define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_DYN_MASK 0x00000000007f0000 - -/* SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_CAP */ -/* Description: Captured vc3 credit */ -#define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_CAP_SHFT 24 -#define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_CAP_MASK 0x000000007f000000 - -/* ==================================================================== */ -/* Register "SH_IILB_LOCAL_TABLE" */ -/* local lookup table */ -/* ==================================================================== */ - -#define SH_IILB_LOCAL_TABLE 0x0000000150020000 -#define SH_IILB_LOCAL_TABLE_MASK 0x800000000000003f -#define SH_IILB_LOCAL_TABLE_MEMDEPTH 128 -#define SH_IILB_LOCAL_TABLE_INIT 0x0000000000000000 - -/* SH_IILB_LOCAL_TABLE_DIR0 */ -/* Description: Direction field for next chip */ -#define SH_IILB_LOCAL_TABLE_DIR0_SHFT 0 -#define SH_IILB_LOCAL_TABLE_DIR0_MASK 0x000000000000000f - -/* SH_IILB_LOCAL_TABLE_V0 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_IILB_LOCAL_TABLE_V0_SHFT 4 -#define SH_IILB_LOCAL_TABLE_V0_MASK 0x0000000000000010 - -/* SH_IILB_LOCAL_TABLE_NI_SEL0 */ -/* Description: ni select for requests */ -#define SH_IILB_LOCAL_TABLE_NI_SEL0_SHFT 5 -#define SH_IILB_LOCAL_TABLE_NI_SEL0_MASK 0x0000000000000020 - -/* SH_IILB_LOCAL_TABLE_VALID */ -/* Description: Indicates that this entry is valid */ -#define SH_IILB_LOCAL_TABLE_VALID_SHFT 63 -#define SH_IILB_LOCAL_TABLE_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_IILB_GLOBAL_TABLE" */ -/* global lookup table */ -/* ==================================================================== */ - -#define SH_IILB_GLOBAL_TABLE 0x0000000150020400 -#define SH_IILB_GLOBAL_TABLE_MASK 0x800000000000003f -#define SH_IILB_GLOBAL_TABLE_MEMDEPTH 16 -#define SH_IILB_GLOBAL_TABLE_INIT 0x0000000000000000 - -/* SH_IILB_GLOBAL_TABLE_DIR0 */ -/* Description: Direction field for next chip */ -#define SH_IILB_GLOBAL_TABLE_DIR0_SHFT 0 -#define SH_IILB_GLOBAL_TABLE_DIR0_MASK 0x000000000000000f - -/* SH_IILB_GLOBAL_TABLE_V0 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_IILB_GLOBAL_TABLE_V0_SHFT 4 -#define SH_IILB_GLOBAL_TABLE_V0_MASK 0x0000000000000010 - -/* SH_IILB_GLOBAL_TABLE_NI_SEL0 */ -/* Description: ni select for requests */ -#define SH_IILB_GLOBAL_TABLE_NI_SEL0_SHFT 5 -#define SH_IILB_GLOBAL_TABLE_NI_SEL0_MASK 0x0000000000000020 - -/* SH_IILB_GLOBAL_TABLE_VALID */ -/* Description: Indicates that this entry is valid */ -#define SH_IILB_GLOBAL_TABLE_VALID_SHFT 63 -#define SH_IILB_GLOBAL_TABLE_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_IILB_OVER_RIDE_TABLE" */ -/* If enabled, bypass the Global/Local tables */ -/* ==================================================================== */ - -#define SH_IILB_OVER_RIDE_TABLE 0x0000000150020480 -#define SH_IILB_OVER_RIDE_TABLE_MASK 0x800000000000003f -#define SH_IILB_OVER_RIDE_TABLE_INIT 0x8000000000000000 - -/* SH_IILB_OVER_RIDE_TABLE_DIR0 */ -/* Description: Direction field for next chip */ -#define SH_IILB_OVER_RIDE_TABLE_DIR0_SHFT 0 -#define SH_IILB_OVER_RIDE_TABLE_DIR0_MASK 0x000000000000000f - -/* SH_IILB_OVER_RIDE_TABLE_V0 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_IILB_OVER_RIDE_TABLE_V0_SHFT 4 -#define SH_IILB_OVER_RIDE_TABLE_V0_MASK 0x0000000000000010 - -/* SH_IILB_OVER_RIDE_TABLE_NI_SEL0 */ -/* Description: ni select */ -#define SH_IILB_OVER_RIDE_TABLE_NI_SEL0_SHFT 5 -#define SH_IILB_OVER_RIDE_TABLE_NI_SEL0_MASK 0x0000000000000020 - -/* SH_IILB_OVER_RIDE_TABLE_ENABLE */ -/* Description: Indicates that this entry is enabled */ -#define SH_IILB_OVER_RIDE_TABLE_ENABLE_SHFT 63 -#define SH_IILB_OVER_RIDE_TABLE_ENABLE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_IILB_RSP_PLANE_HINT" */ -/* If enabled, invert incoming response only plane hint bit before lo */ -/* ==================================================================== */ - -#define SH_IILB_RSP_PLANE_HINT 0x0000000150020488 -#define SH_IILB_RSP_PLANE_HINT_MASK 0x0000000000000000 -#define SH_IILB_RSP_PLANE_HINT_INIT 0x0000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_LOCAL_TABLE" */ -/* local lookup table */ -/* ==================================================================== */ - -#define SH_PI_LOCAL_TABLE 0x0000000150021000 -#define SH_PI_LOCAL_TABLE_MASK 0x8000000000003f3f -#define SH_PI_LOCAL_TABLE_MEMDEPTH 128 -#define SH_PI_LOCAL_TABLE_INIT 0x0000000000000000 - -/* SH_PI_LOCAL_TABLE_DIR0 */ -/* Description: Direction field for next chip */ -#define SH_PI_LOCAL_TABLE_DIR0_SHFT 0 -#define SH_PI_LOCAL_TABLE_DIR0_MASK 0x000000000000000f - -/* SH_PI_LOCAL_TABLE_V0 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_PI_LOCAL_TABLE_V0_SHFT 4 -#define SH_PI_LOCAL_TABLE_V0_MASK 0x0000000000000010 - -/* SH_PI_LOCAL_TABLE_NI_SEL0 */ -/* Description: ni select for requests */ -#define SH_PI_LOCAL_TABLE_NI_SEL0_SHFT 5 -#define SH_PI_LOCAL_TABLE_NI_SEL0_MASK 0x0000000000000020 - -/* SH_PI_LOCAL_TABLE_DIR1 */ -#define SH_PI_LOCAL_TABLE_DIR1_SHFT 8 -#define SH_PI_LOCAL_TABLE_DIR1_MASK 0x0000000000000f00 - -/* SH_PI_LOCAL_TABLE_V1 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_PI_LOCAL_TABLE_V1_SHFT 12 -#define SH_PI_LOCAL_TABLE_V1_MASK 0x0000000000001000 - -/* SH_PI_LOCAL_TABLE_NI_SEL1 */ -/* Description: ni select for plane-hint 1 */ -#define SH_PI_LOCAL_TABLE_NI_SEL1_SHFT 13 -#define SH_PI_LOCAL_TABLE_NI_SEL1_MASK 0x0000000000002000 - -/* SH_PI_LOCAL_TABLE_VALID */ -/* Description: Indicates that this entry is valid */ -#define SH_PI_LOCAL_TABLE_VALID_SHFT 63 -#define SH_PI_LOCAL_TABLE_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_GLOBAL_TABLE" */ -/* global lookup table */ -/* ==================================================================== */ - -#define SH_PI_GLOBAL_TABLE 0x0000000150021400 -#define SH_PI_GLOBAL_TABLE_MASK 0x8000000000003f3f -#define SH_PI_GLOBAL_TABLE_MEMDEPTH 16 -#define SH_PI_GLOBAL_TABLE_INIT 0x0000000000000000 - -/* SH_PI_GLOBAL_TABLE_DIR0 */ -/* Description: Direction field for next chip */ -#define SH_PI_GLOBAL_TABLE_DIR0_SHFT 0 -#define SH_PI_GLOBAL_TABLE_DIR0_MASK 0x000000000000000f - -/* SH_PI_GLOBAL_TABLE_V0 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_PI_GLOBAL_TABLE_V0_SHFT 4 -#define SH_PI_GLOBAL_TABLE_V0_MASK 0x0000000000000010 - -/* SH_PI_GLOBAL_TABLE_NI_SEL0 */ -/* Description: ni select for requests */ -#define SH_PI_GLOBAL_TABLE_NI_SEL0_SHFT 5 -#define SH_PI_GLOBAL_TABLE_NI_SEL0_MASK 0x0000000000000020 - -/* SH_PI_GLOBAL_TABLE_DIR1 */ -#define SH_PI_GLOBAL_TABLE_DIR1_SHFT 8 -#define SH_PI_GLOBAL_TABLE_DIR1_MASK 0x0000000000000f00 - -/* SH_PI_GLOBAL_TABLE_V1 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_PI_GLOBAL_TABLE_V1_SHFT 12 -#define SH_PI_GLOBAL_TABLE_V1_MASK 0x0000000000001000 - -/* SH_PI_GLOBAL_TABLE_NI_SEL1 */ -/* Description: ni select for plane-hint 1 */ -#define SH_PI_GLOBAL_TABLE_NI_SEL1_SHFT 13 -#define SH_PI_GLOBAL_TABLE_NI_SEL1_MASK 0x0000000000002000 - -/* SH_PI_GLOBAL_TABLE_VALID */ -/* Description: Indicates that this entry is valid */ -#define SH_PI_GLOBAL_TABLE_VALID_SHFT 63 -#define SH_PI_GLOBAL_TABLE_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_OVER_RIDE_TABLE" */ -/* If enabled, bypass the Global/Local tables */ -/* ==================================================================== */ - -#define SH_PI_OVER_RIDE_TABLE 0x0000000150021480 -#define SH_PI_OVER_RIDE_TABLE_MASK 0x8000000000003f3f -#define SH_PI_OVER_RIDE_TABLE_INIT 0x8000000000002000 - -/* SH_PI_OVER_RIDE_TABLE_DIR0 */ -/* Description: Direction field for next chip */ -#define SH_PI_OVER_RIDE_TABLE_DIR0_SHFT 0 -#define SH_PI_OVER_RIDE_TABLE_DIR0_MASK 0x000000000000000f - -/* SH_PI_OVER_RIDE_TABLE_V0 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_PI_OVER_RIDE_TABLE_V0_SHFT 4 -#define SH_PI_OVER_RIDE_TABLE_V0_MASK 0x0000000000000010 - -/* SH_PI_OVER_RIDE_TABLE_NI_SEL0 */ -/* Description: ni select */ -#define SH_PI_OVER_RIDE_TABLE_NI_SEL0_SHFT 5 -#define SH_PI_OVER_RIDE_TABLE_NI_SEL0_MASK 0x0000000000000020 - -/* SH_PI_OVER_RIDE_TABLE_DIR1 */ -#define SH_PI_OVER_RIDE_TABLE_DIR1_SHFT 8 -#define SH_PI_OVER_RIDE_TABLE_DIR1_MASK 0x0000000000000f00 - -/* SH_PI_OVER_RIDE_TABLE_V1 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_PI_OVER_RIDE_TABLE_V1_SHFT 12 -#define SH_PI_OVER_RIDE_TABLE_V1_MASK 0x0000000000001000 - -/* SH_PI_OVER_RIDE_TABLE_NI_SEL1 */ -/* Description: ni select */ -#define SH_PI_OVER_RIDE_TABLE_NI_SEL1_SHFT 13 -#define SH_PI_OVER_RIDE_TABLE_NI_SEL1_MASK 0x0000000000002000 - -/* SH_PI_OVER_RIDE_TABLE_ENABLE */ -/* Description: Indicates that this entry is enabled */ -#define SH_PI_OVER_RIDE_TABLE_ENABLE_SHFT 63 -#define SH_PI_OVER_RIDE_TABLE_ENABLE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_RSP_PLANE_HINT" */ -/* If enabled, invert incoming response only plane hint bit before lo */ -/* ==================================================================== */ - -#define SH_PI_RSP_PLANE_HINT 0x0000000150021488 -#define SH_PI_RSP_PLANE_HINT_MASK 0x0000000000000001 -#define SH_PI_RSP_PLANE_HINT_INIT 0x0000000000000000 - -/* SH_PI_RSP_PLANE_HINT_INVERT */ -/* Description: Invert Response Plane Hint */ -#define SH_PI_RSP_PLANE_HINT_INVERT_SHFT 0 -#define SH_PI_RSP_PLANE_HINT_INVERT_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_NI0_LOCAL_TABLE" */ -/* local lookup table */ -/* ==================================================================== */ - -#define SH_NI0_LOCAL_TABLE 0x0000000150022000 -#define SH_NI0_LOCAL_TABLE_MASK 0x800000000000001f -#define SH_NI0_LOCAL_TABLE_MEMDEPTH 128 -#define SH_NI0_LOCAL_TABLE_INIT 0x0000000000000000 - -/* SH_NI0_LOCAL_TABLE_DIR0 */ -/* Description: Direction field for next chip */ -#define SH_NI0_LOCAL_TABLE_DIR0_SHFT 0 -#define SH_NI0_LOCAL_TABLE_DIR0_MASK 0x000000000000000f - -/* SH_NI0_LOCAL_TABLE_V0 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_NI0_LOCAL_TABLE_V0_SHFT 4 -#define SH_NI0_LOCAL_TABLE_V0_MASK 0x0000000000000010 - -/* SH_NI0_LOCAL_TABLE_VALID */ -/* Description: Indicates that this entry is valid */ -#define SH_NI0_LOCAL_TABLE_VALID_SHFT 63 -#define SH_NI0_LOCAL_TABLE_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI0_GLOBAL_TABLE" */ -/* global lookup table */ -/* ==================================================================== */ - -#define SH_NI0_GLOBAL_TABLE 0x0000000150022400 -#define SH_NI0_GLOBAL_TABLE_MASK 0x800000000000001f -#define SH_NI0_GLOBAL_TABLE_MEMDEPTH 16 -#define SH_NI0_GLOBAL_TABLE_INIT 0x0000000000000000 - -/* SH_NI0_GLOBAL_TABLE_DIR0 */ -/* Description: Direction field for next chip */ -#define SH_NI0_GLOBAL_TABLE_DIR0_SHFT 0 -#define SH_NI0_GLOBAL_TABLE_DIR0_MASK 0x000000000000000f - -/* SH_NI0_GLOBAL_TABLE_V0 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_NI0_GLOBAL_TABLE_V0_SHFT 4 -#define SH_NI0_GLOBAL_TABLE_V0_MASK 0x0000000000000010 - -/* SH_NI0_GLOBAL_TABLE_VALID */ -/* Description: Indicates that this entry is valid */ -#define SH_NI0_GLOBAL_TABLE_VALID_SHFT 63 -#define SH_NI0_GLOBAL_TABLE_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI0_OVER_RIDE_TABLE" */ -/* If enabled, bypass the Global/Local tables */ -/* ==================================================================== */ - -#define SH_NI0_OVER_RIDE_TABLE 0x0000000150022480 -#define SH_NI0_OVER_RIDE_TABLE_MASK 0x800000000000001f -#define SH_NI0_OVER_RIDE_TABLE_INIT 0x8000000000000000 - -/* SH_NI0_OVER_RIDE_TABLE_DIR0 */ -/* Description: Direction field for next chip */ -#define SH_NI0_OVER_RIDE_TABLE_DIR0_SHFT 0 -#define SH_NI0_OVER_RIDE_TABLE_DIR0_MASK 0x000000000000000f - -/* SH_NI0_OVER_RIDE_TABLE_V0 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_NI0_OVER_RIDE_TABLE_V0_SHFT 4 -#define SH_NI0_OVER_RIDE_TABLE_V0_MASK 0x0000000000000010 - -/* SH_NI0_OVER_RIDE_TABLE_ENABLE */ -/* Description: Indicates that this entry is enabled */ -#define SH_NI0_OVER_RIDE_TABLE_ENABLE_SHFT 63 -#define SH_NI0_OVER_RIDE_TABLE_ENABLE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI0_RSP_PLANE_HINT" */ -/* If enabled, invert incoming response only plane hint bit before lo */ -/* ==================================================================== */ - -#define SH_NI0_RSP_PLANE_HINT 0x0000000150022488 -#define SH_NI0_RSP_PLANE_HINT_MASK 0x0000000000000000 -#define SH_NI0_RSP_PLANE_HINT_INIT 0x0000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI1_LOCAL_TABLE" */ -/* local lookup table */ -/* ==================================================================== */ - -#define SH_NI1_LOCAL_TABLE 0x0000000150023000 -#define SH_NI1_LOCAL_TABLE_MASK 0x800000000000001f -#define SH_NI1_LOCAL_TABLE_MEMDEPTH 128 -#define SH_NI1_LOCAL_TABLE_INIT 0x0000000000000000 - -/* SH_NI1_LOCAL_TABLE_DIR0 */ -/* Description: Direction field for next chip */ -#define SH_NI1_LOCAL_TABLE_DIR0_SHFT 0 -#define SH_NI1_LOCAL_TABLE_DIR0_MASK 0x000000000000000f - -/* SH_NI1_LOCAL_TABLE_V0 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_NI1_LOCAL_TABLE_V0_SHFT 4 -#define SH_NI1_LOCAL_TABLE_V0_MASK 0x0000000000000010 - -/* SH_NI1_LOCAL_TABLE_VALID */ -/* Description: Indicates that this entry is valid */ -#define SH_NI1_LOCAL_TABLE_VALID_SHFT 63 -#define SH_NI1_LOCAL_TABLE_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI1_GLOBAL_TABLE" */ -/* global lookup table */ -/* ==================================================================== */ - -#define SH_NI1_GLOBAL_TABLE 0x0000000150023400 -#define SH_NI1_GLOBAL_TABLE_MASK 0x800000000000001f -#define SH_NI1_GLOBAL_TABLE_MEMDEPTH 16 -#define SH_NI1_GLOBAL_TABLE_INIT 0x0000000000000000 - -/* SH_NI1_GLOBAL_TABLE_DIR0 */ -/* Description: Direction field for next chip */ -#define SH_NI1_GLOBAL_TABLE_DIR0_SHFT 0 -#define SH_NI1_GLOBAL_TABLE_DIR0_MASK 0x000000000000000f - -/* SH_NI1_GLOBAL_TABLE_V0 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_NI1_GLOBAL_TABLE_V0_SHFT 4 -#define SH_NI1_GLOBAL_TABLE_V0_MASK 0x0000000000000010 - -/* SH_NI1_GLOBAL_TABLE_VALID */ -/* Description: Indicates that this entry is valid */ -#define SH_NI1_GLOBAL_TABLE_VALID_SHFT 63 -#define SH_NI1_GLOBAL_TABLE_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI1_OVER_RIDE_TABLE" */ -/* If enabled, bypass the Global/Local tables */ -/* ==================================================================== */ - -#define SH_NI1_OVER_RIDE_TABLE 0x0000000150023480 -#define SH_NI1_OVER_RIDE_TABLE_MASK 0x800000000000001f -#define SH_NI1_OVER_RIDE_TABLE_INIT 0x8000000000000000 - -/* SH_NI1_OVER_RIDE_TABLE_DIR0 */ -/* Description: Direction field for next chip */ -#define SH_NI1_OVER_RIDE_TABLE_DIR0_SHFT 0 -#define SH_NI1_OVER_RIDE_TABLE_DIR0_MASK 0x000000000000000f - -/* SH_NI1_OVER_RIDE_TABLE_V0 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_NI1_OVER_RIDE_TABLE_V0_SHFT 4 -#define SH_NI1_OVER_RIDE_TABLE_V0_MASK 0x0000000000000010 - -/* SH_NI1_OVER_RIDE_TABLE_ENABLE */ -/* Description: Indicates that this entry is enabled */ -#define SH_NI1_OVER_RIDE_TABLE_ENABLE_SHFT 63 -#define SH_NI1_OVER_RIDE_TABLE_ENABLE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI1_RSP_PLANE_HINT" */ -/* If enabled, invert incoming response only plane hint bit before lo */ -/* ==================================================================== */ - -#define SH_NI1_RSP_PLANE_HINT 0x0000000150023488 -#define SH_NI1_RSP_PLANE_HINT_MASK 0x0000000000000000 -#define SH_NI1_RSP_PLANE_HINT_INIT 0x0000000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_LOCAL_TABLE" */ -/* local lookup table */ -/* ==================================================================== */ - -#define SH_MD_LOCAL_TABLE 0x0000000150024000 -#define SH_MD_LOCAL_TABLE_MASK 0x8000000000003f3f -#define SH_MD_LOCAL_TABLE_MEMDEPTH 128 -#define SH_MD_LOCAL_TABLE_INIT 0x0000000000000000 - -/* SH_MD_LOCAL_TABLE_DIR0 */ -/* Description: Direction field for next chip */ -#define SH_MD_LOCAL_TABLE_DIR0_SHFT 0 -#define SH_MD_LOCAL_TABLE_DIR0_MASK 0x000000000000000f - -/* SH_MD_LOCAL_TABLE_V0 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_MD_LOCAL_TABLE_V0_SHFT 4 -#define SH_MD_LOCAL_TABLE_V0_MASK 0x0000000000000010 - -/* SH_MD_LOCAL_TABLE_NI_SEL0 */ -/* Description: ni select for requests */ -#define SH_MD_LOCAL_TABLE_NI_SEL0_SHFT 5 -#define SH_MD_LOCAL_TABLE_NI_SEL0_MASK 0x0000000000000020 - -/* SH_MD_LOCAL_TABLE_DIR1 */ -#define SH_MD_LOCAL_TABLE_DIR1_SHFT 8 -#define SH_MD_LOCAL_TABLE_DIR1_MASK 0x0000000000000f00 - -/* SH_MD_LOCAL_TABLE_V1 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_MD_LOCAL_TABLE_V1_SHFT 12 -#define SH_MD_LOCAL_TABLE_V1_MASK 0x0000000000001000 - -/* SH_MD_LOCAL_TABLE_NI_SEL1 */ -/* Description: ni select for plane-hint 1 */ -#define SH_MD_LOCAL_TABLE_NI_SEL1_SHFT 13 -#define SH_MD_LOCAL_TABLE_NI_SEL1_MASK 0x0000000000002000 - -/* SH_MD_LOCAL_TABLE_VALID */ -/* Description: Indicates that this entry is valid */ -#define SH_MD_LOCAL_TABLE_VALID_SHFT 63 -#define SH_MD_LOCAL_TABLE_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_GLOBAL_TABLE" */ -/* global lookup table */ -/* ==================================================================== */ - -#define SH_MD_GLOBAL_TABLE 0x0000000150024400 -#define SH_MD_GLOBAL_TABLE_MASK 0x8000000000003f3f -#define SH_MD_GLOBAL_TABLE_MEMDEPTH 16 -#define SH_MD_GLOBAL_TABLE_INIT 0x0000000000000000 - -/* SH_MD_GLOBAL_TABLE_DIR0 */ -/* Description: Direction field for next chip */ -#define SH_MD_GLOBAL_TABLE_DIR0_SHFT 0 -#define SH_MD_GLOBAL_TABLE_DIR0_MASK 0x000000000000000f - -/* SH_MD_GLOBAL_TABLE_V0 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_MD_GLOBAL_TABLE_V0_SHFT 4 -#define SH_MD_GLOBAL_TABLE_V0_MASK 0x0000000000000010 - -/* SH_MD_GLOBAL_TABLE_NI_SEL0 */ -/* Description: ni select for requests */ -#define SH_MD_GLOBAL_TABLE_NI_SEL0_SHFT 5 -#define SH_MD_GLOBAL_TABLE_NI_SEL0_MASK 0x0000000000000020 - -/* SH_MD_GLOBAL_TABLE_DIR1 */ -#define SH_MD_GLOBAL_TABLE_DIR1_SHFT 8 -#define SH_MD_GLOBAL_TABLE_DIR1_MASK 0x0000000000000f00 - -/* SH_MD_GLOBAL_TABLE_V1 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_MD_GLOBAL_TABLE_V1_SHFT 12 -#define SH_MD_GLOBAL_TABLE_V1_MASK 0x0000000000001000 - -/* SH_MD_GLOBAL_TABLE_NI_SEL1 */ -/* Description: ni select for plane-hint 1 */ -#define SH_MD_GLOBAL_TABLE_NI_SEL1_SHFT 13 -#define SH_MD_GLOBAL_TABLE_NI_SEL1_MASK 0x0000000000002000 - -/* SH_MD_GLOBAL_TABLE_VALID */ -/* Description: Indicates that this entry is valid */ -#define SH_MD_GLOBAL_TABLE_VALID_SHFT 63 -#define SH_MD_GLOBAL_TABLE_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_OVER_RIDE_TABLE" */ -/* If enabled, bypass the Global/Local tables */ -/* ==================================================================== */ - -#define SH_MD_OVER_RIDE_TABLE 0x0000000150024480 -#define SH_MD_OVER_RIDE_TABLE_MASK 0x8000000000003f3f -#define SH_MD_OVER_RIDE_TABLE_INIT 0x8000000000002000 - -/* SH_MD_OVER_RIDE_TABLE_DIR0 */ -/* Description: Direction field for next chip */ -#define SH_MD_OVER_RIDE_TABLE_DIR0_SHFT 0 -#define SH_MD_OVER_RIDE_TABLE_DIR0_MASK 0x000000000000000f - -/* SH_MD_OVER_RIDE_TABLE_V0 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_MD_OVER_RIDE_TABLE_V0_SHFT 4 -#define SH_MD_OVER_RIDE_TABLE_V0_MASK 0x0000000000000010 - -/* SH_MD_OVER_RIDE_TABLE_NI_SEL0 */ -/* Description: ni select */ -#define SH_MD_OVER_RIDE_TABLE_NI_SEL0_SHFT 5 -#define SH_MD_OVER_RIDE_TABLE_NI_SEL0_MASK 0x0000000000000020 - -/* SH_MD_OVER_RIDE_TABLE_DIR1 */ -#define SH_MD_OVER_RIDE_TABLE_DIR1_SHFT 8 -#define SH_MD_OVER_RIDE_TABLE_DIR1_MASK 0x0000000000000f00 - -/* SH_MD_OVER_RIDE_TABLE_V1 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_MD_OVER_RIDE_TABLE_V1_SHFT 12 -#define SH_MD_OVER_RIDE_TABLE_V1_MASK 0x0000000000001000 - -/* SH_MD_OVER_RIDE_TABLE_NI_SEL1 */ -/* Description: ni select */ -#define SH_MD_OVER_RIDE_TABLE_NI_SEL1_SHFT 13 -#define SH_MD_OVER_RIDE_TABLE_NI_SEL1_MASK 0x0000000000002000 - -/* SH_MD_OVER_RIDE_TABLE_ENABLE */ -/* Description: Indicates that this entry is enabled */ -#define SH_MD_OVER_RIDE_TABLE_ENABLE_SHFT 63 -#define SH_MD_OVER_RIDE_TABLE_ENABLE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_RSP_PLANE_HINT" */ -/* If enabled, invert incoming response only plane hint bit before lo */ -/* ==================================================================== */ - -#define SH_MD_RSP_PLANE_HINT 0x0000000150024488 -#define SH_MD_RSP_PLANE_HINT_MASK 0x0000000000000001 -#define SH_MD_RSP_PLANE_HINT_INIT 0x0000000000000000 - -/* SH_MD_RSP_PLANE_HINT_INVERT */ -/* Description: Invert Response Plane Hint */ -#define SH_MD_RSP_PLANE_HINT_INVERT_SHFT 0 -#define SH_MD_RSP_PLANE_HINT_INVERT_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_LB_LIQ_CTL" */ -/* Local Block LIQ Control */ -/* ==================================================================== */ - -#define SH_LB_LIQ_CTL 0x0000000110040000 -#define SH_LB_LIQ_CTL_MASK 0x0000000000070f1f -#define SH_LB_LIQ_CTL_INIT 0x0000000000000000 - -/* SH_LB_LIQ_CTL_LIQ_REQ_CTL */ -/* Description: LIQ Request Control */ -#define SH_LB_LIQ_CTL_LIQ_REQ_CTL_SHFT 0 -#define SH_LB_LIQ_CTL_LIQ_REQ_CTL_MASK 0x000000000000001f - -/* SH_LB_LIQ_CTL_LIQ_RPL_CTL */ -/* Description: LIQ Reply Control */ -#define SH_LB_LIQ_CTL_LIQ_RPL_CTL_SHFT 8 -#define SH_LB_LIQ_CTL_LIQ_RPL_CTL_MASK 0x0000000000000f00 - -/* SH_LB_LIQ_CTL_FORCE_RQ_CREDIT */ -/* Description: Force request credit */ -#define SH_LB_LIQ_CTL_FORCE_RQ_CREDIT_SHFT 16 -#define SH_LB_LIQ_CTL_FORCE_RQ_CREDIT_MASK 0x0000000000010000 - -/* SH_LB_LIQ_CTL_FORCE_RP_CREDIT */ -/* Description: Force reply credit */ -#define SH_LB_LIQ_CTL_FORCE_RP_CREDIT_SHFT 17 -#define SH_LB_LIQ_CTL_FORCE_RP_CREDIT_MASK 0x0000000000020000 - -/* SH_LB_LIQ_CTL_FORCE_LINVV_CREDIT */ -/* Description: Force linvv credit */ -#define SH_LB_LIQ_CTL_FORCE_LINVV_CREDIT_SHFT 18 -#define SH_LB_LIQ_CTL_FORCE_LINVV_CREDIT_MASK 0x0000000000040000 - -/* ==================================================================== */ -/* Register "SH_LB_LOQ_CTL" */ -/* Local Block LOQ Control */ -/* ==================================================================== */ - -#define SH_LB_LOQ_CTL 0x0000000110040080 -#define SH_LB_LOQ_CTL_MASK 0x0000000000000003 -#define SH_LB_LOQ_CTL_INIT 0x0000000000000000 - -/* SH_LB_LOQ_CTL_LOQ_REQ_CTL */ -/* Description: LOQ Request Control */ -#define SH_LB_LOQ_CTL_LOQ_REQ_CTL_SHFT 0 -#define SH_LB_LOQ_CTL_LOQ_REQ_CTL_MASK 0x0000000000000001 - -/* SH_LB_LOQ_CTL_LOQ_RPL_CTL */ -/* Description: LOQ Reply Control */ -#define SH_LB_LOQ_CTL_LOQ_RPL_CTL_SHFT 1 -#define SH_LB_LOQ_CTL_LOQ_RPL_CTL_MASK 0x0000000000000002 - -/* ==================================================================== */ -/* Register "SH_LB_MAX_REP_CREDIT_CNT" */ -/* Maximum number of reply credits from XN */ -/* ==================================================================== */ - -#define SH_LB_MAX_REP_CREDIT_CNT 0x0000000110040100 -#define SH_LB_MAX_REP_CREDIT_CNT_MASK 0x000000000000001f -#define SH_LB_MAX_REP_CREDIT_CNT_INIT 0x000000000000001f - -/* SH_LB_MAX_REP_CREDIT_CNT_MAX_CNT */ -/* Description: Max reply credits */ -#define SH_LB_MAX_REP_CREDIT_CNT_MAX_CNT_SHFT 0 -#define SH_LB_MAX_REP_CREDIT_CNT_MAX_CNT_MASK 0x000000000000001f - -/* ==================================================================== */ -/* Register "SH_LB_MAX_REQ_CREDIT_CNT" */ -/* Maximum number of request credits from XN */ -/* ==================================================================== */ - -#define SH_LB_MAX_REQ_CREDIT_CNT 0x0000000110040180 -#define SH_LB_MAX_REQ_CREDIT_CNT_MASK 0x000000000000001f -#define SH_LB_MAX_REQ_CREDIT_CNT_INIT 0x000000000000001f - -/* SH_LB_MAX_REQ_CREDIT_CNT_MAX_CNT */ -/* Description: Max request credits */ -#define SH_LB_MAX_REQ_CREDIT_CNT_MAX_CNT_SHFT 0 -#define SH_LB_MAX_REQ_CREDIT_CNT_MAX_CNT_MASK 0x000000000000001f - -/* ==================================================================== */ -/* Register "SH_PIO_TIME_OUT" */ -/* Local Block PIO time out value */ -/* ==================================================================== */ - -#define SH_PIO_TIME_OUT 0x0000000110040200 -#define SH_PIO_TIME_OUT_MASK 0x000000000000ffff -#define SH_PIO_TIME_OUT_INIT 0x0000000000000400 - -/* SH_PIO_TIME_OUT_VALUE */ -/* Description: PIO time out value */ -#define SH_PIO_TIME_OUT_VALUE_SHFT 0 -#define SH_PIO_TIME_OUT_VALUE_MASK 0x000000000000ffff - -/* ==================================================================== */ -/* Register "SH_PIO_NACK_RESET" */ -/* Local Block PIO Reset for nack counters */ -/* ==================================================================== */ - -#define SH_PIO_NACK_RESET 0x0000000110040280 -#define SH_PIO_NACK_RESET_MASK 0x0000000000000001 -#define SH_PIO_NACK_RESET_INIT 0x0000000000000000 - -/* SH_PIO_NACK_RESET_PULSE */ -/* Description: PIO nack counter reset */ -#define SH_PIO_NACK_RESET_PULSE_SHFT 0 -#define SH_PIO_NACK_RESET_PULSE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_CONVEYOR_BELT_TIME_OUT" */ -/* Local Block conveyor belt time out value */ -/* ==================================================================== */ - -#define SH_CONVEYOR_BELT_TIME_OUT 0x0000000110040300 -#define SH_CONVEYOR_BELT_TIME_OUT_MASK 0x0000000000000fff -#define SH_CONVEYOR_BELT_TIME_OUT_INIT 0x0000000000000000 - -/* SH_CONVEYOR_BELT_TIME_OUT_VALUE */ -/* Description: Conveyor belt time out value */ -#define SH_CONVEYOR_BELT_TIME_OUT_VALUE_SHFT 0 -#define SH_CONVEYOR_BELT_TIME_OUT_VALUE_MASK 0x0000000000000fff - -/* ==================================================================== */ -/* Register "SH_LB_CREDIT_STATUS" */ -/* Credit Counter Status Register */ -/* ==================================================================== */ - -#define SH_LB_CREDIT_STATUS 0x0000000110050000 -#define SH_LB_CREDIT_STATUS_MASK 0x000000000ffff3df -#define SH_LB_CREDIT_STATUS_INIT 0x0000000000000000 - -/* SH_LB_CREDIT_STATUS_LIQ_RQ_CREDIT */ -/* Description: LIQ request queue credit counter */ -#define SH_LB_CREDIT_STATUS_LIQ_RQ_CREDIT_SHFT 0 -#define SH_LB_CREDIT_STATUS_LIQ_RQ_CREDIT_MASK 0x000000000000001f - -/* SH_LB_CREDIT_STATUS_LIQ_RP_CREDIT */ -/* Description: LIQ reply queue credit counter */ -#define SH_LB_CREDIT_STATUS_LIQ_RP_CREDIT_SHFT 6 -#define SH_LB_CREDIT_STATUS_LIQ_RP_CREDIT_MASK 0x00000000000003c0 - -/* SH_LB_CREDIT_STATUS_LINVV_CREDIT */ -/* Description: LINVV credit counter */ -#define SH_LB_CREDIT_STATUS_LINVV_CREDIT_SHFT 12 -#define SH_LB_CREDIT_STATUS_LINVV_CREDIT_MASK 0x000000000003f000 - -/* SH_LB_CREDIT_STATUS_LOQ_RQ_CREDIT */ -/* Description: LOQ request queue credit counter */ -#define SH_LB_CREDIT_STATUS_LOQ_RQ_CREDIT_SHFT 18 -#define SH_LB_CREDIT_STATUS_LOQ_RQ_CREDIT_MASK 0x00000000007c0000 - -/* SH_LB_CREDIT_STATUS_LOQ_RP_CREDIT */ -/* Description: LOQ reply queue credit counter */ -#define SH_LB_CREDIT_STATUS_LOQ_RP_CREDIT_SHFT 23 -#define SH_LB_CREDIT_STATUS_LOQ_RP_CREDIT_MASK 0x000000000f800000 - -/* ==================================================================== */ -/* Register "SH_LB_DEBUG_LOCAL_SEL" */ -/* LB Debug Port Select */ -/* ==================================================================== */ - -#define SH_LB_DEBUG_LOCAL_SEL 0x0000000110050080 -#define SH_LB_DEBUG_LOCAL_SEL_MASK 0xf777777777777777 -#define SH_LB_DEBUG_LOCAL_SEL_INIT 0x0000000000000000 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_CHIPLET_SEL */ -/* Description: Nibble 0 Chiplet select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_CHIPLET_SEL_SHFT 0 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000007 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_CHIPLET_SEL */ -/* Description: Nibble 1 Chiplet select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_CHIPLET_SEL_SHFT 8 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000700 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_CHIPLET_SEL */ -/* Description: Nibble 2 Chiplet select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_CHIPLET_SEL_SHFT 16 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000070000 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_CHIPLET_SEL */ -/* Description: Nibble 3 Chiplet select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_CHIPLET_SEL_SHFT 24 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_CHIPLET_SEL_MASK 0x0000000007000000 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_CHIPLET_SEL */ -/* Description: Nibble 4 Chiplet select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_CHIPLET_SEL_SHFT 32 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_CHIPLET_SEL_MASK 0x0000000700000000 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_CHIPLET_SEL */ -/* Description: Nibble 5 Chiplet select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_CHIPLET_SEL_SHFT 40 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_CHIPLET_SEL_MASK 0x0000070000000000 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_CHIPLET_SEL */ -/* Description: Nibble 6 Chiplet select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_CHIPLET_SEL_SHFT 48 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_CHIPLET_SEL_MASK 0x0007000000000000 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_CHIPLET_SEL */ -/* Description: Nibble 7 Chiplet select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_CHIPLET_SEL_SHFT 56 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_CHIPLET_SEL_MASK 0x0700000000000000 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* SH_LB_DEBUG_LOCAL_SEL_TRIGGER_ENABLE */ -/* Description: Enable trigger on bit 32 of Analyzer data */ -#define SH_LB_DEBUG_LOCAL_SEL_TRIGGER_ENABLE_SHFT 63 -#define SH_LB_DEBUG_LOCAL_SEL_TRIGGER_ENABLE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_LB_DEBUG_PERF_SEL" */ -/* LB Debug Port Performance Select */ -/* ==================================================================== */ - -#define SH_LB_DEBUG_PERF_SEL 0x0000000110050100 -#define SH_LB_DEBUG_PERF_SEL_MASK 0x7777777777777777 -#define SH_LB_DEBUG_PERF_SEL_INIT 0x0000000000000000 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE0_CHIPLET_SEL */ -/* Description: Nibble 0 Chiplet select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE0_CHIPLET_SEL_SHFT 0 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000007 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE1_CHIPLET_SEL */ -/* Description: Nibble 1 Chiplet select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE1_CHIPLET_SEL_SHFT 8 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000700 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE2_CHIPLET_SEL */ -/* Description: Nibble 2 Chiplet select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE2_CHIPLET_SEL_SHFT 16 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000070000 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE3_CHIPLET_SEL */ -/* Description: Nibble 3 Chiplet select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE3_CHIPLET_SEL_SHFT 24 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE3_CHIPLET_SEL_MASK 0x0000000007000000 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE4_CHIPLET_SEL */ -/* Description: Nibble 4 Chiplet select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE4_CHIPLET_SEL_SHFT 32 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE4_CHIPLET_SEL_MASK 0x0000000700000000 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE5_CHIPLET_SEL */ -/* Description: Nibble 5 Chiplet select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE5_CHIPLET_SEL_SHFT 40 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE5_CHIPLET_SEL_MASK 0x0000070000000000 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE6_CHIPLET_SEL */ -/* Description: Nibble 6 Chiplet select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE6_CHIPLET_SEL_SHFT 48 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE6_CHIPLET_SEL_MASK 0x0007000000000000 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE7_CHIPLET_SEL */ -/* Description: Nibble 7 Chiplet select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE7_CHIPLET_SEL_SHFT 56 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE7_CHIPLET_SEL_MASK 0x0700000000000000 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* ==================================================================== */ -/* Register "SH_LB_DEBUG_TRIG_SEL" */ -/* LB Debug Trigger Select */ -/* ==================================================================== */ - -#define SH_LB_DEBUG_TRIG_SEL 0x0000000110050180 -#define SH_LB_DEBUG_TRIG_SEL_MASK 0x7777777777777777 -#define SH_LB_DEBUG_TRIG_SEL_INIT 0x0000000000000000 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER0_CHIPLET_SEL */ -/* Description: Nibble 0 Chiplet select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER0_CHIPLET_SEL_SHFT 0 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER0_CHIPLET_SEL_MASK 0x0000000000000007 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL_SHFT 4 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER1_CHIPLET_SEL */ -/* Description: Nibble 1 Chiplet select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER1_CHIPLET_SEL_SHFT 8 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER1_CHIPLET_SEL_MASK 0x0000000000000700 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL_SHFT 12 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER2_CHIPLET_SEL */ -/* Description: Nibble 2 Chiplet select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER2_CHIPLET_SEL_SHFT 16 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER2_CHIPLET_SEL_MASK 0x0000000000070000 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL_SHFT 20 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER3_CHIPLET_SEL */ -/* Description: Nibble 3 Chiplet select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER3_CHIPLET_SEL_SHFT 24 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER3_CHIPLET_SEL_MASK 0x0000000007000000 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL_SHFT 28 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER4_CHIPLET_SEL */ -/* Description: Nibble 4 Chiplet select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER4_CHIPLET_SEL_SHFT 32 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER4_CHIPLET_SEL_MASK 0x0000000700000000 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL_SHFT 36 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER5_CHIPLET_SEL */ -/* Description: Nibble 5 Chiplet select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER5_CHIPLET_SEL_SHFT 40 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER5_CHIPLET_SEL_MASK 0x0000070000000000 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL_SHFT 44 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER6_CHIPLET_SEL */ -/* Description: Nibble 6 Chiplet select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER6_CHIPLET_SEL_SHFT 48 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER6_CHIPLET_SEL_MASK 0x0007000000000000 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL_SHFT 52 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER7_CHIPLET_SEL */ -/* Description: Nibble 7 Chiplet select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER7_CHIPLET_SEL_SHFT 56 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER7_CHIPLET_SEL_MASK 0x0700000000000000 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL_SHFT 60 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* ==================================================================== */ -/* Register "SH_LB_ERROR_DETAIL_1" */ -/* LB Error capture information: HDR1 */ -/* ==================================================================== */ - -#define SH_LB_ERROR_DETAIL_1 0x0000000110050200 -#define SH_LB_ERROR_DETAIL_1_MASK 0x8003073fff3fffff -#define SH_LB_ERROR_DETAIL_1_INIT 0x0000000000000000 - -/* SH_LB_ERROR_DETAIL_1_COMMAND */ -/* Description: COMMAND */ -#define SH_LB_ERROR_DETAIL_1_COMMAND_SHFT 0 -#define SH_LB_ERROR_DETAIL_1_COMMAND_MASK 0x00000000000000ff - -/* SH_LB_ERROR_DETAIL_1_SUPPL */ -/* Description: SUPPLMENTAL */ -#define SH_LB_ERROR_DETAIL_1_SUPPL_SHFT 8 -#define SH_LB_ERROR_DETAIL_1_SUPPL_MASK 0x00000000003fff00 - -/* SH_LB_ERROR_DETAIL_1_SOURCE */ -/* Description: SOURCE */ -#define SH_LB_ERROR_DETAIL_1_SOURCE_SHFT 24 -#define SH_LB_ERROR_DETAIL_1_SOURCE_MASK 0x0000003fff000000 - -/* SH_LB_ERROR_DETAIL_1_DEST */ -/* Description: DEST */ -#define SH_LB_ERROR_DETAIL_1_DEST_SHFT 40 -#define SH_LB_ERROR_DETAIL_1_DEST_MASK 0x0000070000000000 - -/* SH_LB_ERROR_DETAIL_1_HDR_ERR */ -/* Description: HDR_ERR */ -#define SH_LB_ERROR_DETAIL_1_HDR_ERR_SHFT 48 -#define SH_LB_ERROR_DETAIL_1_HDR_ERR_MASK 0x0001000000000000 - -/* SH_LB_ERROR_DETAIL_1_DATA_ERR */ -/* Description: DATA_ERR */ -#define SH_LB_ERROR_DETAIL_1_DATA_ERR_SHFT 49 -#define SH_LB_ERROR_DETAIL_1_DATA_ERR_MASK 0x0002000000000000 - -/* SH_LB_ERROR_DETAIL_1_VALID */ -/* Description: VALID */ -#define SH_LB_ERROR_DETAIL_1_VALID_SHFT 63 -#define SH_LB_ERROR_DETAIL_1_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_LB_ERROR_DETAIL_2" */ -/* LB Error Bits */ -/* ==================================================================== */ - -#define SH_LB_ERROR_DETAIL_2 0x0000000110050280 -#define SH_LB_ERROR_DETAIL_2_MASK 0x00007fffffffffff -#define SH_LB_ERROR_DETAIL_2_INIT 0x0000000000000000 - -/* SH_LB_ERROR_DETAIL_2_ADDRESS */ -/* Description: ADDRESS */ -#define SH_LB_ERROR_DETAIL_2_ADDRESS_SHFT 0 -#define SH_LB_ERROR_DETAIL_2_ADDRESS_MASK 0x00007fffffffffff - -/* ==================================================================== */ -/* Register "SH_LB_ERROR_DETAIL_3" */ -/* LB Error Bits */ -/* ==================================================================== */ - -#define SH_LB_ERROR_DETAIL_3 0x0000000110050300 -#define SH_LB_ERROR_DETAIL_3_MASK 0xffffffffffffffff -#define SH_LB_ERROR_DETAIL_3_INIT 0x0000000000000000 - -/* SH_LB_ERROR_DETAIL_3_DATA */ -/* Description: DATA */ -#define SH_LB_ERROR_DETAIL_3_DATA_SHFT 0 -#define SH_LB_ERROR_DETAIL_3_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_LB_ERROR_DETAIL_4" */ -/* LB Error Bits */ -/* ==================================================================== */ - -#define SH_LB_ERROR_DETAIL_4 0x0000000110050380 -#define SH_LB_ERROR_DETAIL_4_MASK 0xffffffffffffffff -#define SH_LB_ERROR_DETAIL_4_INIT 0x0000000000000000 - -/* SH_LB_ERROR_DETAIL_4_ROUTE */ -/* Description: ROUTE */ -#define SH_LB_ERROR_DETAIL_4_ROUTE_SHFT 0 -#define SH_LB_ERROR_DETAIL_4_ROUTE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_LB_ERROR_DETAIL_5" */ -/* LB Error Bits */ -/* ==================================================================== */ - -#define SH_LB_ERROR_DETAIL_5 0x0000000110050400 -#define SH_LB_ERROR_DETAIL_5_MASK 0x000000000000007f -#define SH_LB_ERROR_DETAIL_5_INIT 0x0000000000000000 - -/* SH_LB_ERROR_DETAIL_5_READ_RETRY */ -/* Description: Read retry error */ -#define SH_LB_ERROR_DETAIL_5_READ_RETRY_SHFT 0 -#define SH_LB_ERROR_DETAIL_5_READ_RETRY_MASK 0x0000000000000001 - -/* SH_LB_ERROR_DETAIL_5_PTC1_WRITE */ -/* Description: PTC1 write error */ -#define SH_LB_ERROR_DETAIL_5_PTC1_WRITE_SHFT 1 -#define SH_LB_ERROR_DETAIL_5_PTC1_WRITE_MASK 0x0000000000000002 - -/* SH_LB_ERROR_DETAIL_5_WRITE_RETRY */ -/* Description: Write retry error */ -#define SH_LB_ERROR_DETAIL_5_WRITE_RETRY_SHFT 2 -#define SH_LB_ERROR_DETAIL_5_WRITE_RETRY_MASK 0x0000000000000004 - -/* SH_LB_ERROR_DETAIL_5_COUNT_A_OVERFLOW */ -/* Description: Nack A counter overflow error */ -#define SH_LB_ERROR_DETAIL_5_COUNT_A_OVERFLOW_SHFT 3 -#define SH_LB_ERROR_DETAIL_5_COUNT_A_OVERFLOW_MASK 0x0000000000000008 - -/* SH_LB_ERROR_DETAIL_5_COUNT_B_OVERFLOW */ -/* Description: Nack B counter overflow error */ -#define SH_LB_ERROR_DETAIL_5_COUNT_B_OVERFLOW_SHFT 4 -#define SH_LB_ERROR_DETAIL_5_COUNT_B_OVERFLOW_MASK 0x0000000000000010 - -/* SH_LB_ERROR_DETAIL_5_NACK_A_TIMEOUT */ -/* Description: Nack A counter timeout error */ -#define SH_LB_ERROR_DETAIL_5_NACK_A_TIMEOUT_SHFT 5 -#define SH_LB_ERROR_DETAIL_5_NACK_A_TIMEOUT_MASK 0x0000000000000020 - -/* SH_LB_ERROR_DETAIL_5_NACK_B_TIMEOUT */ -/* Description: Nack B counter timeout error */ -#define SH_LB_ERROR_DETAIL_5_NACK_B_TIMEOUT_SHFT 6 -#define SH_LB_ERROR_DETAIL_5_NACK_B_TIMEOUT_MASK 0x0000000000000040 - -/* ==================================================================== */ -/* Register "SH_LB_ERROR_MASK" */ -/* LB Error Mask */ -/* ==================================================================== */ - -#define SH_LB_ERROR_MASK 0x0000000110050480 -#define SH_LB_ERROR_MASK_MASK 0x00000000007fffff -#define SH_LB_ERROR_MASK_INIT 0x00000000007fffff - -/* SH_LB_ERROR_MASK_RQ_BAD_CMD */ -/* Description: RQ_BAD_CMD */ -#define SH_LB_ERROR_MASK_RQ_BAD_CMD_SHFT 0 -#define SH_LB_ERROR_MASK_RQ_BAD_CMD_MASK 0x0000000000000001 - -/* SH_LB_ERROR_MASK_RP_BAD_CMD */ -/* Description: RP_BAD_CMD */ -#define SH_LB_ERROR_MASK_RP_BAD_CMD_SHFT 1 -#define SH_LB_ERROR_MASK_RP_BAD_CMD_MASK 0x0000000000000002 - -/* SH_LB_ERROR_MASK_RQ_SHORT */ -/* Description: RQ_SHORT */ -#define SH_LB_ERROR_MASK_RQ_SHORT_SHFT 2 -#define SH_LB_ERROR_MASK_RQ_SHORT_MASK 0x0000000000000004 - -/* SH_LB_ERROR_MASK_RP_SHORT */ -/* Description: RP_SHORT */ -#define SH_LB_ERROR_MASK_RP_SHORT_SHFT 3 -#define SH_LB_ERROR_MASK_RP_SHORT_MASK 0x0000000000000008 - -/* SH_LB_ERROR_MASK_RQ_LONG */ -/* Description: RQ_LONG */ -#define SH_LB_ERROR_MASK_RQ_LONG_SHFT 4 -#define SH_LB_ERROR_MASK_RQ_LONG_MASK 0x0000000000000010 - -/* SH_LB_ERROR_MASK_RP_LONG */ -/* Description: RP_LONG */ -#define SH_LB_ERROR_MASK_RP_LONG_SHFT 5 -#define SH_LB_ERROR_MASK_RP_LONG_MASK 0x0000000000000020 - -/* SH_LB_ERROR_MASK_RQ_BAD_DATA */ -/* Description: RQ_BAD_DATA */ -#define SH_LB_ERROR_MASK_RQ_BAD_DATA_SHFT 6 -#define SH_LB_ERROR_MASK_RQ_BAD_DATA_MASK 0x0000000000000040 - -/* SH_LB_ERROR_MASK_RP_BAD_DATA */ -/* Description: RP_BAD_DATA */ -#define SH_LB_ERROR_MASK_RP_BAD_DATA_SHFT 7 -#define SH_LB_ERROR_MASK_RP_BAD_DATA_MASK 0x0000000000000080 - -/* SH_LB_ERROR_MASK_RQ_BAD_ADDR */ -/* Description: RQ_BAD_ADDR */ -#define SH_LB_ERROR_MASK_RQ_BAD_ADDR_SHFT 8 -#define SH_LB_ERROR_MASK_RQ_BAD_ADDR_MASK 0x0000000000000100 - -/* SH_LB_ERROR_MASK_RQ_TIME_OUT */ -/* Description: RQ_TIME_OUT */ -#define SH_LB_ERROR_MASK_RQ_TIME_OUT_SHFT 9 -#define SH_LB_ERROR_MASK_RQ_TIME_OUT_MASK 0x0000000000000200 - -/* SH_LB_ERROR_MASK_LINVV_OVERFLOW */ -/* Description: LINVV_OVERFLOW */ -#define SH_LB_ERROR_MASK_LINVV_OVERFLOW_SHFT 10 -#define SH_LB_ERROR_MASK_LINVV_OVERFLOW_MASK 0x0000000000000400 - -/* SH_LB_ERROR_MASK_UNEXPECTED_LINV */ -/* Description: UNEXPECTED_LINV */ -#define SH_LB_ERROR_MASK_UNEXPECTED_LINV_SHFT 11 -#define SH_LB_ERROR_MASK_UNEXPECTED_LINV_MASK 0x0000000000000800 - -/* SH_LB_ERROR_MASK_PTC_1_TIMEOUT */ -/* Description: PTC_1 Time out */ -#define SH_LB_ERROR_MASK_PTC_1_TIMEOUT_SHFT 12 -#define SH_LB_ERROR_MASK_PTC_1_TIMEOUT_MASK 0x0000000000001000 - -/* SH_LB_ERROR_MASK_JUNK_BUS_ERR */ -/* Description: Junk Bus error */ -#define SH_LB_ERROR_MASK_JUNK_BUS_ERR_SHFT 13 -#define SH_LB_ERROR_MASK_JUNK_BUS_ERR_MASK 0x0000000000002000 - -/* SH_LB_ERROR_MASK_PIO_CB_ERR */ -/* Description: PIO Conveyor Belt operation error */ -#define SH_LB_ERROR_MASK_PIO_CB_ERR_SHFT 14 -#define SH_LB_ERROR_MASK_PIO_CB_ERR_MASK 0x0000000000004000 - -/* SH_LB_ERROR_MASK_VECTOR_RQ_ROUTE_ERROR */ -/* Description: Vector request Route data was invalid */ -#define SH_LB_ERROR_MASK_VECTOR_RQ_ROUTE_ERROR_SHFT 15 -#define SH_LB_ERROR_MASK_VECTOR_RQ_ROUTE_ERROR_MASK 0x0000000000008000 - -/* SH_LB_ERROR_MASK_VECTOR_RP_ROUTE_ERROR */ -/* Description: Vector reply Route data was invalid */ -#define SH_LB_ERROR_MASK_VECTOR_RP_ROUTE_ERROR_SHFT 16 -#define SH_LB_ERROR_MASK_VECTOR_RP_ROUTE_ERROR_MASK 0x0000000000010000 - -/* SH_LB_ERROR_MASK_GCLK_DROP */ -/* Description: Gclk drop error */ -#define SH_LB_ERROR_MASK_GCLK_DROP_SHFT 17 -#define SH_LB_ERROR_MASK_GCLK_DROP_MASK 0x0000000000020000 - -/* SH_LB_ERROR_MASK_RQ_FIFO_ERROR */ -/* Description: Request queue FIFO error */ -#define SH_LB_ERROR_MASK_RQ_FIFO_ERROR_SHFT 18 -#define SH_LB_ERROR_MASK_RQ_FIFO_ERROR_MASK 0x0000000000040000 - -/* SH_LB_ERROR_MASK_RP_FIFO_ERROR */ -/* Description: Reply queue FIFO error */ -#define SH_LB_ERROR_MASK_RP_FIFO_ERROR_SHFT 19 -#define SH_LB_ERROR_MASK_RP_FIFO_ERROR_MASK 0x0000000000080000 - -/* SH_LB_ERROR_MASK_UNEXP_VALID */ -/* Description: Unexpected valid error */ -#define SH_LB_ERROR_MASK_UNEXP_VALID_SHFT 20 -#define SH_LB_ERROR_MASK_UNEXP_VALID_MASK 0x0000000000100000 - -/* SH_LB_ERROR_MASK_RQ_CREDIT_OVERFLOW */ -/* Description: Request queue credit overflow */ -#define SH_LB_ERROR_MASK_RQ_CREDIT_OVERFLOW_SHFT 21 -#define SH_LB_ERROR_MASK_RQ_CREDIT_OVERFLOW_MASK 0x0000000000200000 - -/* SH_LB_ERROR_MASK_RP_CREDIT_OVERFLOW */ -/* Description: Reply queue credit overflow */ -#define SH_LB_ERROR_MASK_RP_CREDIT_OVERFLOW_SHFT 22 -#define SH_LB_ERROR_MASK_RP_CREDIT_OVERFLOW_MASK 0x0000000000400000 - -/* ==================================================================== */ -/* Register "SH_LB_ERROR_OVERFLOW" */ -/* LB Error Overflow */ -/* ==================================================================== */ - -#define SH_LB_ERROR_OVERFLOW 0x0000000110050500 -#define SH_LB_ERROR_OVERFLOW_MASK 0x00000000007fffff -#define SH_LB_ERROR_OVERFLOW_INIT 0x0000000000000000 - -/* SH_LB_ERROR_OVERFLOW_RQ_BAD_CMD_OVRFL */ -/* Description: RQ_BAD_CMD_OVRFL */ -#define SH_LB_ERROR_OVERFLOW_RQ_BAD_CMD_OVRFL_SHFT 0 -#define SH_LB_ERROR_OVERFLOW_RQ_BAD_CMD_OVRFL_MASK 0x0000000000000001 - -/* SH_LB_ERROR_OVERFLOW_RP_BAD_CMD_OVRFL */ -/* Description: RP_BAD_CMD_OVRFL */ -#define SH_LB_ERROR_OVERFLOW_RP_BAD_CMD_OVRFL_SHFT 1 -#define SH_LB_ERROR_OVERFLOW_RP_BAD_CMD_OVRFL_MASK 0x0000000000000002 - -/* SH_LB_ERROR_OVERFLOW_RQ_SHORT_OVRFL */ -/* Description: RQ_SHORT_OVRFL */ -#define SH_LB_ERROR_OVERFLOW_RQ_SHORT_OVRFL_SHFT 2 -#define SH_LB_ERROR_OVERFLOW_RQ_SHORT_OVRFL_MASK 0x0000000000000004 - -/* SH_LB_ERROR_OVERFLOW_RP_SHORT_OVRFL */ -/* Description: RP_SHORT_OVRFL */ -#define SH_LB_ERROR_OVERFLOW_RP_SHORT_OVRFL_SHFT 3 -#define SH_LB_ERROR_OVERFLOW_RP_SHORT_OVRFL_MASK 0x0000000000000008 - -/* SH_LB_ERROR_OVERFLOW_RQ_LONG_OVRFL */ -/* Description: RQ_LONG_OVRFL */ -#define SH_LB_ERROR_OVERFLOW_RQ_LONG_OVRFL_SHFT 4 -#define SH_LB_ERROR_OVERFLOW_RQ_LONG_OVRFL_MASK 0x0000000000000010 - -/* SH_LB_ERROR_OVERFLOW_RP_LONG_OVRFL */ -/* Description: RP_LONG_OVRFL */ -#define SH_LB_ERROR_OVERFLOW_RP_LONG_OVRFL_SHFT 5 -#define SH_LB_ERROR_OVERFLOW_RP_LONG_OVRFL_MASK 0x0000000000000020 - -/* SH_LB_ERROR_OVERFLOW_RQ_BAD_DATA_OVRFL */ -/* Description: RQ_BAD_DATA_OVRFL */ -#define SH_LB_ERROR_OVERFLOW_RQ_BAD_DATA_OVRFL_SHFT 6 -#define SH_LB_ERROR_OVERFLOW_RQ_BAD_DATA_OVRFL_MASK 0x0000000000000040 - -/* SH_LB_ERROR_OVERFLOW_RP_BAD_DATA_OVRFL */ -/* Description: RP_BAD_DATA_OVRFL */ -#define SH_LB_ERROR_OVERFLOW_RP_BAD_DATA_OVRFL_SHFT 7 -#define SH_LB_ERROR_OVERFLOW_RP_BAD_DATA_OVRFL_MASK 0x0000000000000080 - -/* SH_LB_ERROR_OVERFLOW_RQ_BAD_ADDR_OVRFL */ -/* Description: RQ_BAD_ADDR_OVRFL */ -#define SH_LB_ERROR_OVERFLOW_RQ_BAD_ADDR_OVRFL_SHFT 8 -#define SH_LB_ERROR_OVERFLOW_RQ_BAD_ADDR_OVRFL_MASK 0x0000000000000100 - -/* SH_LB_ERROR_OVERFLOW_RQ_TIME_OUT_OVRFL */ -/* Description: RQ_TIME_OUT_OVRFL */ -#define SH_LB_ERROR_OVERFLOW_RQ_TIME_OUT_OVRFL_SHFT 9 -#define SH_LB_ERROR_OVERFLOW_RQ_TIME_OUT_OVRFL_MASK 0x0000000000000200 - -/* SH_LB_ERROR_OVERFLOW_LINVV_OVERFLOW_OVRFL */ -/* Description: LINVV_OVERFLOW_OVRFL */ -#define SH_LB_ERROR_OVERFLOW_LINVV_OVERFLOW_OVRFL_SHFT 10 -#define SH_LB_ERROR_OVERFLOW_LINVV_OVERFLOW_OVRFL_MASK 0x0000000000000400 - -/* SH_LB_ERROR_OVERFLOW_UNEXPECTED_LINV_OVRFL */ -/* Description: UNEXPECTED_LINV_OVRFL */ -#define SH_LB_ERROR_OVERFLOW_UNEXPECTED_LINV_OVRFL_SHFT 11 -#define SH_LB_ERROR_OVERFLOW_UNEXPECTED_LINV_OVRFL_MASK 0x0000000000000800 - -/* SH_LB_ERROR_OVERFLOW_PTC_1_TIMEOUT_OVRFL */ -/* Description: PTC_1 Time out overflow */ -#define SH_LB_ERROR_OVERFLOW_PTC_1_TIMEOUT_OVRFL_SHFT 12 -#define SH_LB_ERROR_OVERFLOW_PTC_1_TIMEOUT_OVRFL_MASK 0x0000000000001000 - -/* SH_LB_ERROR_OVERFLOW_JUNK_BUS_ERR_OVRFL */ -/* Description: Junk Bus error overflow */ -#define SH_LB_ERROR_OVERFLOW_JUNK_BUS_ERR_OVRFL_SHFT 13 -#define SH_LB_ERROR_OVERFLOW_JUNK_BUS_ERR_OVRFL_MASK 0x0000000000002000 - -/* SH_LB_ERROR_OVERFLOW_PIO_CB_ERR_OVRFL */ -/* Description: PIO Conveyor Belt operation error overflow */ -#define SH_LB_ERROR_OVERFLOW_PIO_CB_ERR_OVRFL_SHFT 14 -#define SH_LB_ERROR_OVERFLOW_PIO_CB_ERR_OVRFL_MASK 0x0000000000004000 - -/* SH_LB_ERROR_OVERFLOW_VECTOR_RQ_ROUTE_ERROR_OVRFL */ -/* Description: Vector request Route data was invalid overflow */ -#define SH_LB_ERROR_OVERFLOW_VECTOR_RQ_ROUTE_ERROR_OVRFL_SHFT 15 -#define SH_LB_ERROR_OVERFLOW_VECTOR_RQ_ROUTE_ERROR_OVRFL_MASK 0x0000000000008000 - -/* SH_LB_ERROR_OVERFLOW_VECTOR_RP_ROUTE_ERROR_OVRFL */ -/* Description: Vector reply Route data was invalid overflow */ -#define SH_LB_ERROR_OVERFLOW_VECTOR_RP_ROUTE_ERROR_OVRFL_SHFT 16 -#define SH_LB_ERROR_OVERFLOW_VECTOR_RP_ROUTE_ERROR_OVRFL_MASK 0x0000000000010000 - -/* SH_LB_ERROR_OVERFLOW_GCLK_DROP_OVRFL */ -/* Description: Gclk drop error overflow */ -#define SH_LB_ERROR_OVERFLOW_GCLK_DROP_OVRFL_SHFT 17 -#define SH_LB_ERROR_OVERFLOW_GCLK_DROP_OVRFL_MASK 0x0000000000020000 - -/* SH_LB_ERROR_OVERFLOW_RQ_FIFO_ERROR_OVRFL */ -/* Description: Request queue FIFO error overflow */ -#define SH_LB_ERROR_OVERFLOW_RQ_FIFO_ERROR_OVRFL_SHFT 18 -#define SH_LB_ERROR_OVERFLOW_RQ_FIFO_ERROR_OVRFL_MASK 0x0000000000040000 - -/* SH_LB_ERROR_OVERFLOW_RP_FIFO_ERROR_OVRFL */ -/* Description: Reply queue FIFO error overflow */ -#define SH_LB_ERROR_OVERFLOW_RP_FIFO_ERROR_OVRFL_SHFT 19 -#define SH_LB_ERROR_OVERFLOW_RP_FIFO_ERROR_OVRFL_MASK 0x0000000000080000 - -/* SH_LB_ERROR_OVERFLOW_UNEXP_VALID_OVRFL */ -/* Description: Unexpected valid error overflow */ -#define SH_LB_ERROR_OVERFLOW_UNEXP_VALID_OVRFL_SHFT 20 -#define SH_LB_ERROR_OVERFLOW_UNEXP_VALID_OVRFL_MASK 0x0000000000100000 - -/* SH_LB_ERROR_OVERFLOW_RQ_CREDIT_OVERFLOW_OVRFL */ -/* Description: Request queue credit overflow */ -#define SH_LB_ERROR_OVERFLOW_RQ_CREDIT_OVERFLOW_OVRFL_SHFT 21 -#define SH_LB_ERROR_OVERFLOW_RQ_CREDIT_OVERFLOW_OVRFL_MASK 0x0000000000200000 - -/* SH_LB_ERROR_OVERFLOW_RP_CREDIT_OVERFLOW_OVRFL */ -/* Description: Reply queue credit overflow */ -#define SH_LB_ERROR_OVERFLOW_RP_CREDIT_OVERFLOW_OVRFL_SHFT 22 -#define SH_LB_ERROR_OVERFLOW_RP_CREDIT_OVERFLOW_OVRFL_MASK 0x0000000000400000 - -/* ==================================================================== */ -/* Register "SH_LB_ERROR_OVERFLOW_ALIAS" */ -/* LB Error Overflow */ -/* ==================================================================== */ - -#define SH_LB_ERROR_OVERFLOW_ALIAS 0x0000000110050508 - -/* ==================================================================== */ -/* Register "SH_LB_ERROR_SUMMARY" */ -/* LB Error Bits */ -/* ==================================================================== */ - -#define SH_LB_ERROR_SUMMARY 0x0000000110050580 -#define SH_LB_ERROR_SUMMARY_MASK 0x00000000007fffff -#define SH_LB_ERROR_SUMMARY_INIT 0x0000000000000000 - -/* SH_LB_ERROR_SUMMARY_RQ_BAD_CMD */ -/* Description: RQ_BAD_CMD */ -#define SH_LB_ERROR_SUMMARY_RQ_BAD_CMD_SHFT 0 -#define SH_LB_ERROR_SUMMARY_RQ_BAD_CMD_MASK 0x0000000000000001 - -/* SH_LB_ERROR_SUMMARY_RP_BAD_CMD */ -/* Description: RP_BAD_CMD */ -#define SH_LB_ERROR_SUMMARY_RP_BAD_CMD_SHFT 1 -#define SH_LB_ERROR_SUMMARY_RP_BAD_CMD_MASK 0x0000000000000002 - -/* SH_LB_ERROR_SUMMARY_RQ_SHORT */ -/* Description: RQ_SHORT */ -#define SH_LB_ERROR_SUMMARY_RQ_SHORT_SHFT 2 -#define SH_LB_ERROR_SUMMARY_RQ_SHORT_MASK 0x0000000000000004 - -/* SH_LB_ERROR_SUMMARY_RP_SHORT */ -/* Description: RP_SHORT */ -#define SH_LB_ERROR_SUMMARY_RP_SHORT_SHFT 3 -#define SH_LB_ERROR_SUMMARY_RP_SHORT_MASK 0x0000000000000008 - -/* SH_LB_ERROR_SUMMARY_RQ_LONG */ -/* Description: RQ_LONG */ -#define SH_LB_ERROR_SUMMARY_RQ_LONG_SHFT 4 -#define SH_LB_ERROR_SUMMARY_RQ_LONG_MASK 0x0000000000000010 - -/* SH_LB_ERROR_SUMMARY_RP_LONG */ -/* Description: RP_LONG */ -#define SH_LB_ERROR_SUMMARY_RP_LONG_SHFT 5 -#define SH_LB_ERROR_SUMMARY_RP_LONG_MASK 0x0000000000000020 - -/* SH_LB_ERROR_SUMMARY_RQ_BAD_DATA */ -/* Description: RQ_BAD_DATA */ -#define SH_LB_ERROR_SUMMARY_RQ_BAD_DATA_SHFT 6 -#define SH_LB_ERROR_SUMMARY_RQ_BAD_DATA_MASK 0x0000000000000040 - -/* SH_LB_ERROR_SUMMARY_RP_BAD_DATA */ -/* Description: RP_BAD_DATA */ -#define SH_LB_ERROR_SUMMARY_RP_BAD_DATA_SHFT 7 -#define SH_LB_ERROR_SUMMARY_RP_BAD_DATA_MASK 0x0000000000000080 - -/* SH_LB_ERROR_SUMMARY_RQ_BAD_ADDR */ -/* Description: RQ_BAD_ADDR */ -#define SH_LB_ERROR_SUMMARY_RQ_BAD_ADDR_SHFT 8 -#define SH_LB_ERROR_SUMMARY_RQ_BAD_ADDR_MASK 0x0000000000000100 - -/* SH_LB_ERROR_SUMMARY_RQ_TIME_OUT */ -/* Description: RQ_TIME_OUT */ -#define SH_LB_ERROR_SUMMARY_RQ_TIME_OUT_SHFT 9 -#define SH_LB_ERROR_SUMMARY_RQ_TIME_OUT_MASK 0x0000000000000200 - -/* SH_LB_ERROR_SUMMARY_LINVV_OVERFLOW */ -/* Description: LINVV_OVERFLOW */ -#define SH_LB_ERROR_SUMMARY_LINVV_OVERFLOW_SHFT 10 -#define SH_LB_ERROR_SUMMARY_LINVV_OVERFLOW_MASK 0x0000000000000400 - -/* SH_LB_ERROR_SUMMARY_UNEXPECTED_LINV */ -/* Description: UNEXPECTED_LINV */ -#define SH_LB_ERROR_SUMMARY_UNEXPECTED_LINV_SHFT 11 -#define SH_LB_ERROR_SUMMARY_UNEXPECTED_LINV_MASK 0x0000000000000800 - -/* SH_LB_ERROR_SUMMARY_PTC_1_TIMEOUT */ -/* Description: PTC_1 Time out */ -#define SH_LB_ERROR_SUMMARY_PTC_1_TIMEOUT_SHFT 12 -#define SH_LB_ERROR_SUMMARY_PTC_1_TIMEOUT_MASK 0x0000000000001000 - -/* SH_LB_ERROR_SUMMARY_JUNK_BUS_ERR */ -/* Description: Junk Bus error */ -#define SH_LB_ERROR_SUMMARY_JUNK_BUS_ERR_SHFT 13 -#define SH_LB_ERROR_SUMMARY_JUNK_BUS_ERR_MASK 0x0000000000002000 - -/* SH_LB_ERROR_SUMMARY_PIO_CB_ERR */ -/* Description: PIO Conveyor Belt operation error */ -#define SH_LB_ERROR_SUMMARY_PIO_CB_ERR_SHFT 14 -#define SH_LB_ERROR_SUMMARY_PIO_CB_ERR_MASK 0x0000000000004000 - -/* SH_LB_ERROR_SUMMARY_VECTOR_RQ_ROUTE_ERROR */ -/* Description: Vector request Route data was invalid */ -#define SH_LB_ERROR_SUMMARY_VECTOR_RQ_ROUTE_ERROR_SHFT 15 -#define SH_LB_ERROR_SUMMARY_VECTOR_RQ_ROUTE_ERROR_MASK 0x0000000000008000 - -/* SH_LB_ERROR_SUMMARY_VECTOR_RP_ROUTE_ERROR */ -/* Description: Vector reply Route data was invalid */ -#define SH_LB_ERROR_SUMMARY_VECTOR_RP_ROUTE_ERROR_SHFT 16 -#define SH_LB_ERROR_SUMMARY_VECTOR_RP_ROUTE_ERROR_MASK 0x0000000000010000 - -/* SH_LB_ERROR_SUMMARY_GCLK_DROP */ -/* Description: Gclk drop error */ -#define SH_LB_ERROR_SUMMARY_GCLK_DROP_SHFT 17 -#define SH_LB_ERROR_SUMMARY_GCLK_DROP_MASK 0x0000000000020000 - -/* SH_LB_ERROR_SUMMARY_RQ_FIFO_ERROR */ -/* Description: Request queue FIFO error */ -#define SH_LB_ERROR_SUMMARY_RQ_FIFO_ERROR_SHFT 18 -#define SH_LB_ERROR_SUMMARY_RQ_FIFO_ERROR_MASK 0x0000000000040000 - -/* SH_LB_ERROR_SUMMARY_RP_FIFO_ERROR */ -/* Description: Reply queue FIFO error */ -#define SH_LB_ERROR_SUMMARY_RP_FIFO_ERROR_SHFT 19 -#define SH_LB_ERROR_SUMMARY_RP_FIFO_ERROR_MASK 0x0000000000080000 - -/* SH_LB_ERROR_SUMMARY_UNEXP_VALID */ -/* Description: Unexpected valid error */ -#define SH_LB_ERROR_SUMMARY_UNEXP_VALID_SHFT 20 -#define SH_LB_ERROR_SUMMARY_UNEXP_VALID_MASK 0x0000000000100000 - -/* SH_LB_ERROR_SUMMARY_RQ_CREDIT_OVERFLOW */ -/* Description: Request queue credit overflow */ -#define SH_LB_ERROR_SUMMARY_RQ_CREDIT_OVERFLOW_SHFT 21 -#define SH_LB_ERROR_SUMMARY_RQ_CREDIT_OVERFLOW_MASK 0x0000000000200000 - -/* SH_LB_ERROR_SUMMARY_RP_CREDIT_OVERFLOW */ -/* Description: Reply queue credit overflow */ -#define SH_LB_ERROR_SUMMARY_RP_CREDIT_OVERFLOW_SHFT 22 -#define SH_LB_ERROR_SUMMARY_RP_CREDIT_OVERFLOW_MASK 0x0000000000400000 - -/* ==================================================================== */ -/* Register "SH_LB_ERROR_SUMMARY_ALIAS" */ -/* LB Error Bits Alias */ -/* ==================================================================== */ - -#define SH_LB_ERROR_SUMMARY_ALIAS 0x0000000110050588 - -/* ==================================================================== */ -/* Register "SH_LB_FIRST_ERROR" */ -/* LB First Error */ -/* ==================================================================== */ - -#define SH_LB_FIRST_ERROR 0x0000000110050600 -#define SH_LB_FIRST_ERROR_MASK 0x00000000007fffff -#define SH_LB_FIRST_ERROR_INIT 0x0000000000000000 - -/* SH_LB_FIRST_ERROR_RQ_BAD_CMD */ -/* Description: RQ_BAD_CMD */ -#define SH_LB_FIRST_ERROR_RQ_BAD_CMD_SHFT 0 -#define SH_LB_FIRST_ERROR_RQ_BAD_CMD_MASK 0x0000000000000001 - -/* SH_LB_FIRST_ERROR_RP_BAD_CMD */ -/* Description: RP_BAD_CMD */ -#define SH_LB_FIRST_ERROR_RP_BAD_CMD_SHFT 1 -#define SH_LB_FIRST_ERROR_RP_BAD_CMD_MASK 0x0000000000000002 - -/* SH_LB_FIRST_ERROR_RQ_SHORT */ -/* Description: RQ_SHORT */ -#define SH_LB_FIRST_ERROR_RQ_SHORT_SHFT 2 -#define SH_LB_FIRST_ERROR_RQ_SHORT_MASK 0x0000000000000004 - -/* SH_LB_FIRST_ERROR_RP_SHORT */ -/* Description: RP_SHORT */ -#define SH_LB_FIRST_ERROR_RP_SHORT_SHFT 3 -#define SH_LB_FIRST_ERROR_RP_SHORT_MASK 0x0000000000000008 - -/* SH_LB_FIRST_ERROR_RQ_LONG */ -/* Description: RQ_LONG */ -#define SH_LB_FIRST_ERROR_RQ_LONG_SHFT 4 -#define SH_LB_FIRST_ERROR_RQ_LONG_MASK 0x0000000000000010 - -/* SH_LB_FIRST_ERROR_RP_LONG */ -/* Description: RP_LONG */ -#define SH_LB_FIRST_ERROR_RP_LONG_SHFT 5 -#define SH_LB_FIRST_ERROR_RP_LONG_MASK 0x0000000000000020 - -/* SH_LB_FIRST_ERROR_RQ_BAD_DATA */ -/* Description: RQ_BAD_DATA */ -#define SH_LB_FIRST_ERROR_RQ_BAD_DATA_SHFT 6 -#define SH_LB_FIRST_ERROR_RQ_BAD_DATA_MASK 0x0000000000000040 - -/* SH_LB_FIRST_ERROR_RP_BAD_DATA */ -/* Description: RP_BAD_DATA */ -#define SH_LB_FIRST_ERROR_RP_BAD_DATA_SHFT 7 -#define SH_LB_FIRST_ERROR_RP_BAD_DATA_MASK 0x0000000000000080 - -/* SH_LB_FIRST_ERROR_RQ_BAD_ADDR */ -/* Description: RQ_BAD_ADDR */ -#define SH_LB_FIRST_ERROR_RQ_BAD_ADDR_SHFT 8 -#define SH_LB_FIRST_ERROR_RQ_BAD_ADDR_MASK 0x0000000000000100 - -/* SH_LB_FIRST_ERROR_RQ_TIME_OUT */ -/* Description: RQ_TIME_OUT */ -#define SH_LB_FIRST_ERROR_RQ_TIME_OUT_SHFT 9 -#define SH_LB_FIRST_ERROR_RQ_TIME_OUT_MASK 0x0000000000000200 - -/* SH_LB_FIRST_ERROR_LINVV_OVERFLOW */ -/* Description: LINVV_OVERFLOW */ -#define SH_LB_FIRST_ERROR_LINVV_OVERFLOW_SHFT 10 -#define SH_LB_FIRST_ERROR_LINVV_OVERFLOW_MASK 0x0000000000000400 - -/* SH_LB_FIRST_ERROR_UNEXPECTED_LINV */ -/* Description: UNEXPECTED_LINV */ -#define SH_LB_FIRST_ERROR_UNEXPECTED_LINV_SHFT 11 -#define SH_LB_FIRST_ERROR_UNEXPECTED_LINV_MASK 0x0000000000000800 - -/* SH_LB_FIRST_ERROR_PTC_1_TIMEOUT */ -/* Description: PTC_1 Time out */ -#define SH_LB_FIRST_ERROR_PTC_1_TIMEOUT_SHFT 12 -#define SH_LB_FIRST_ERROR_PTC_1_TIMEOUT_MASK 0x0000000000001000 - -/* SH_LB_FIRST_ERROR_JUNK_BUS_ERR */ -/* Description: Junk Bus error */ -#define SH_LB_FIRST_ERROR_JUNK_BUS_ERR_SHFT 13 -#define SH_LB_FIRST_ERROR_JUNK_BUS_ERR_MASK 0x0000000000002000 - -/* SH_LB_FIRST_ERROR_PIO_CB_ERR */ -/* Description: PIO Conveyor Belt operation error */ -#define SH_LB_FIRST_ERROR_PIO_CB_ERR_SHFT 14 -#define SH_LB_FIRST_ERROR_PIO_CB_ERR_MASK 0x0000000000004000 - -/* SH_LB_FIRST_ERROR_VECTOR_RQ_ROUTE_ERROR */ -/* Description: Vector request Route data was invalid */ -#define SH_LB_FIRST_ERROR_VECTOR_RQ_ROUTE_ERROR_SHFT 15 -#define SH_LB_FIRST_ERROR_VECTOR_RQ_ROUTE_ERROR_MASK 0x0000000000008000 - -/* SH_LB_FIRST_ERROR_VECTOR_RP_ROUTE_ERROR */ -/* Description: Vector reply Route data was invalid */ -#define SH_LB_FIRST_ERROR_VECTOR_RP_ROUTE_ERROR_SHFT 16 -#define SH_LB_FIRST_ERROR_VECTOR_RP_ROUTE_ERROR_MASK 0x0000000000010000 - -/* SH_LB_FIRST_ERROR_GCLK_DROP */ -/* Description: Gclk drop error */ -#define SH_LB_FIRST_ERROR_GCLK_DROP_SHFT 17 -#define SH_LB_FIRST_ERROR_GCLK_DROP_MASK 0x0000000000020000 - -/* SH_LB_FIRST_ERROR_RQ_FIFO_ERROR */ -/* Description: Request queue FIFO error */ -#define SH_LB_FIRST_ERROR_RQ_FIFO_ERROR_SHFT 18 -#define SH_LB_FIRST_ERROR_RQ_FIFO_ERROR_MASK 0x0000000000040000 - -/* SH_LB_FIRST_ERROR_RP_FIFO_ERROR */ -/* Description: Reply queue FIFO error */ -#define SH_LB_FIRST_ERROR_RP_FIFO_ERROR_SHFT 19 -#define SH_LB_FIRST_ERROR_RP_FIFO_ERROR_MASK 0x0000000000080000 - -/* SH_LB_FIRST_ERROR_UNEXP_VALID */ -/* Description: Unexpected valid error */ -#define SH_LB_FIRST_ERROR_UNEXP_VALID_SHFT 20 -#define SH_LB_FIRST_ERROR_UNEXP_VALID_MASK 0x0000000000100000 - -/* SH_LB_FIRST_ERROR_RQ_CREDIT_OVERFLOW */ -/* Description: Request queue credit overflow */ -#define SH_LB_FIRST_ERROR_RQ_CREDIT_OVERFLOW_SHFT 21 -#define SH_LB_FIRST_ERROR_RQ_CREDIT_OVERFLOW_MASK 0x0000000000200000 - -/* SH_LB_FIRST_ERROR_RP_CREDIT_OVERFLOW */ -/* Description: Reply queue credit overflow */ -#define SH_LB_FIRST_ERROR_RP_CREDIT_OVERFLOW_SHFT 22 -#define SH_LB_FIRST_ERROR_RP_CREDIT_OVERFLOW_MASK 0x0000000000400000 - -/* ==================================================================== */ -/* Register "SH_LB_LAST_CREDIT" */ -/* Credit counter status register */ -/* ==================================================================== */ - -#define SH_LB_LAST_CREDIT 0x0000000110050680 -#define SH_LB_LAST_CREDIT_MASK 0x000000000ffff3df -#define SH_LB_LAST_CREDIT_INIT 0x0000000000000000 - -/* SH_LB_LAST_CREDIT_LIQ_RQ_CREDIT */ -/* Description: LIQ request queue credit counter */ -#define SH_LB_LAST_CREDIT_LIQ_RQ_CREDIT_SHFT 0 -#define SH_LB_LAST_CREDIT_LIQ_RQ_CREDIT_MASK 0x000000000000001f - -/* SH_LB_LAST_CREDIT_LIQ_RP_CREDIT */ -/* Description: LIQ reply queue credit counter */ -#define SH_LB_LAST_CREDIT_LIQ_RP_CREDIT_SHFT 6 -#define SH_LB_LAST_CREDIT_LIQ_RP_CREDIT_MASK 0x00000000000003c0 - -/* SH_LB_LAST_CREDIT_LINVV_CREDIT */ -/* Description: LINVV credit counter */ -#define SH_LB_LAST_CREDIT_LINVV_CREDIT_SHFT 12 -#define SH_LB_LAST_CREDIT_LINVV_CREDIT_MASK 0x000000000003f000 - -/* SH_LB_LAST_CREDIT_LOQ_RQ_CREDIT */ -/* Description: LOQ request queue credit counter */ -#define SH_LB_LAST_CREDIT_LOQ_RQ_CREDIT_SHFT 18 -#define SH_LB_LAST_CREDIT_LOQ_RQ_CREDIT_MASK 0x00000000007c0000 - -/* SH_LB_LAST_CREDIT_LOQ_RP_CREDIT */ -/* Description: LOQ reply queue credit counter */ -#define SH_LB_LAST_CREDIT_LOQ_RP_CREDIT_SHFT 23 -#define SH_LB_LAST_CREDIT_LOQ_RP_CREDIT_MASK 0x000000000f800000 - -/* ==================================================================== */ -/* Register "SH_LB_NACK_STATUS" */ -/* Nack Counter Status Register */ -/* ==================================================================== */ - -#define SH_LB_NACK_STATUS 0x0000000110050700 -#define SH_LB_NACK_STATUS_MASK 0x3fffffff0fff0fff -#define SH_LB_NACK_STATUS_INIT 0x0000000000000000 - -/* SH_LB_NACK_STATUS_PIO_NACK_A */ -/* Description: PIO nackA counter */ -#define SH_LB_NACK_STATUS_PIO_NACK_A_SHFT 0 -#define SH_LB_NACK_STATUS_PIO_NACK_A_MASK 0x0000000000000fff - -/* SH_LB_NACK_STATUS_PIO_NACK_B */ -/* Description: PIO nackA counter */ -#define SH_LB_NACK_STATUS_PIO_NACK_B_SHFT 16 -#define SH_LB_NACK_STATUS_PIO_NACK_B_MASK 0x000000000fff0000 - -/* SH_LB_NACK_STATUS_JUNK_NACK */ -/* Description: Junk bus nack counter */ -#define SH_LB_NACK_STATUS_JUNK_NACK_SHFT 32 -#define SH_LB_NACK_STATUS_JUNK_NACK_MASK 0x0000ffff00000000 - -/* SH_LB_NACK_STATUS_CB_TIMEOUT_COUNT */ -/* Description: Conveyor belt time out counter */ -#define SH_LB_NACK_STATUS_CB_TIMEOUT_COUNT_SHFT 48 -#define SH_LB_NACK_STATUS_CB_TIMEOUT_COUNT_MASK 0x0fff000000000000 - -/* SH_LB_NACK_STATUS_CB_STATE */ -/* Description: Conveyor belt state */ -#define SH_LB_NACK_STATUS_CB_STATE_SHFT 60 -#define SH_LB_NACK_STATUS_CB_STATE_MASK 0x3000000000000000 - -/* ==================================================================== */ -/* Register "SH_LB_TRIGGER_COMPARE" */ -/* LB Test-point Trigger Compare */ -/* ==================================================================== */ - -#define SH_LB_TRIGGER_COMPARE 0x0000000110050780 -#define SH_LB_TRIGGER_COMPARE_MASK 0x00000000ffffffff -#define SH_LB_TRIGGER_COMPARE_INIT 0x0000000000000000 - -/* SH_LB_TRIGGER_COMPARE_MASK */ -/* Description: Mask to select Debug bits for trigger generation */ -#define SH_LB_TRIGGER_COMPARE_MASK_SHFT 0 -#define SH_LB_TRIGGER_COMPARE_MASK_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_LB_TRIGGER_DATA" */ -/* LB Test-point Trigger Compare Data */ -/* ==================================================================== */ - -#define SH_LB_TRIGGER_DATA 0x0000000110050800 -#define SH_LB_TRIGGER_DATA_MASK 0x00000000ffffffff -#define SH_LB_TRIGGER_DATA_INIT 0x00000000ffffffff - -/* SH_LB_TRIGGER_DATA_COMPARE_PATTERN */ -/* Description: debug bit pattern for trigger generation */ -#define SH_LB_TRIGGER_DATA_COMPARE_PATTERN_SHFT 0 -#define SH_LB_TRIGGER_DATA_COMPARE_PATTERN_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_PI_AEC_CONFIG" */ -/* PI Adaptive Error Correction Configuration */ -/* ==================================================================== */ - -#define SH_PI_AEC_CONFIG 0x0000000120050000 -#define SH_PI_AEC_CONFIG_MASK 0x0000000000000007 -#define SH_PI_AEC_CONFIG_INIT 0x0000000000000000 - -/* SH_PI_AEC_CONFIG_MODE */ -/* Description: AEC Operation Mode */ -#define SH_PI_AEC_CONFIG_MODE_SHFT 0 -#define SH_PI_AEC_CONFIG_MODE_MASK 0x0000000000000007 - -/* ==================================================================== */ -/* Register "SH_PI_AFI_ERROR_MASK" */ -/* PI AFI Error Mask */ -/* ==================================================================== */ - -#define SH_PI_AFI_ERROR_MASK 0x0000000120050080 -#define SH_PI_AFI_ERROR_MASK_MASK 0x00000007ffe00000 -#define SH_PI_AFI_ERROR_MASK_INIT 0x00000007ffe00000 - -/* SH_PI_AFI_ERROR_MASK_HUNG_BUS */ -/* Description: FSB is hung */ -#define SH_PI_AFI_ERROR_MASK_HUNG_BUS_SHFT 21 -#define SH_PI_AFI_ERROR_MASK_HUNG_BUS_MASK 0x0000000000200000 - -/* SH_PI_AFI_ERROR_MASK_RSP_PARITY */ -/* Description: Parity error detecte during response phase */ -#define SH_PI_AFI_ERROR_MASK_RSP_PARITY_SHFT 22 -#define SH_PI_AFI_ERROR_MASK_RSP_PARITY_MASK 0x0000000000400000 - -/* SH_PI_AFI_ERROR_MASK_IOQ_OVERRUN */ -/* Description: Over run error detected on IOQ */ -#define SH_PI_AFI_ERROR_MASK_IOQ_OVERRUN_SHFT 23 -#define SH_PI_AFI_ERROR_MASK_IOQ_OVERRUN_MASK 0x0000000000800000 - -/* SH_PI_AFI_ERROR_MASK_REQ_FORMAT */ -/* Description: FSB request format not supported */ -#define SH_PI_AFI_ERROR_MASK_REQ_FORMAT_SHFT 24 -#define SH_PI_AFI_ERROR_MASK_REQ_FORMAT_MASK 0x0000000001000000 - -/* SH_PI_AFI_ERROR_MASK_ADDR_ACCESS */ -/* Description: Access to Address is not supported */ -#define SH_PI_AFI_ERROR_MASK_ADDR_ACCESS_SHFT 25 -#define SH_PI_AFI_ERROR_MASK_ADDR_ACCESS_MASK 0x0000000002000000 - -/* SH_PI_AFI_ERROR_MASK_REQ_PARITY */ -/* Description: Parity error detected during request phase */ -#define SH_PI_AFI_ERROR_MASK_REQ_PARITY_SHFT 26 -#define SH_PI_AFI_ERROR_MASK_REQ_PARITY_MASK 0x0000000004000000 - -/* SH_PI_AFI_ERROR_MASK_ADDR_PARITY */ -/* Description: Parity error detected on address */ -#define SH_PI_AFI_ERROR_MASK_ADDR_PARITY_SHFT 27 -#define SH_PI_AFI_ERROR_MASK_ADDR_PARITY_MASK 0x0000000008000000 - -/* SH_PI_AFI_ERROR_MASK_SHUB_FSB_DQE */ -/* Description: SHUB_FSB_DQE */ -#define SH_PI_AFI_ERROR_MASK_SHUB_FSB_DQE_SHFT 28 -#define SH_PI_AFI_ERROR_MASK_SHUB_FSB_DQE_MASK 0x0000000010000000 - -/* SH_PI_AFI_ERROR_MASK_SHUB_FSB_UCE */ -/* Description: An un-correctable ECC error was detected */ -#define SH_PI_AFI_ERROR_MASK_SHUB_FSB_UCE_SHFT 29 -#define SH_PI_AFI_ERROR_MASK_SHUB_FSB_UCE_MASK 0x0000000020000000 - -/* SH_PI_AFI_ERROR_MASK_SHUB_FSB_CE */ -/* Description: An correctable ECC error was detected */ -#define SH_PI_AFI_ERROR_MASK_SHUB_FSB_CE_SHFT 30 -#define SH_PI_AFI_ERROR_MASK_SHUB_FSB_CE_MASK 0x0000000040000000 - -/* SH_PI_AFI_ERROR_MASK_LIVELOCK */ -/* Description: AFI livelock error was detected */ -#define SH_PI_AFI_ERROR_MASK_LIVELOCK_SHFT 31 -#define SH_PI_AFI_ERROR_MASK_LIVELOCK_MASK 0x0000000080000000 - -/* SH_PI_AFI_ERROR_MASK_BAD_SNOOP */ -/* Description: AFI bad snoop error was detected */ -#define SH_PI_AFI_ERROR_MASK_BAD_SNOOP_SHFT 32 -#define SH_PI_AFI_ERROR_MASK_BAD_SNOOP_MASK 0x0000000100000000 - -/* SH_PI_AFI_ERROR_MASK_FSB_TBL_MISS */ -/* Description: AFI FSB request table miss error was detected */ -#define SH_PI_AFI_ERROR_MASK_FSB_TBL_MISS_SHFT 33 -#define SH_PI_AFI_ERROR_MASK_FSB_TBL_MISS_MASK 0x0000000200000000 - -/* SH_PI_AFI_ERROR_MASK_MSG_LEN */ -/* Description: Runt or Obese message received from SIC */ -#define SH_PI_AFI_ERROR_MASK_MSG_LEN_SHFT 34 -#define SH_PI_AFI_ERROR_MASK_MSG_LEN_MASK 0x0000000400000000 - -/* ==================================================================== */ -/* Register "SH_PI_AFI_TEST_POINT_COMPARE" */ -/* PI AFI Test Point Compare */ -/* ==================================================================== */ - -#define SH_PI_AFI_TEST_POINT_COMPARE 0x0000000120050100 -#define SH_PI_AFI_TEST_POINT_COMPARE_MASK 0xffffffffffffffff -#define SH_PI_AFI_TEST_POINT_COMPARE_INIT 0xffffffff00000000 - -/* SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_MASK */ -/* Description: Mask to select Debug bits for trigger generation */ -#define SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_MASK_SHFT 0 -#define SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_MASK_MASK 0x00000000ffffffff - -/* SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_PATTERN */ -/* Description: debug bit pattern for trigger generation */ -#define SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_PATTERN_SHFT 32 -#define SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_PATTERN_MASK 0xffffffff00000000 - -/* ==================================================================== */ -/* Register "SH_PI_AFI_TEST_POINT_SELECT" */ -/* PI AFI Test Point Select */ -/* ==================================================================== */ - -#define SH_PI_AFI_TEST_POINT_SELECT 0x0000000120050180 -#define SH_PI_AFI_TEST_POINT_SELECT_MASK 0xff7f7f7f7f7f7f7f -#define SH_PI_AFI_TEST_POINT_SELECT_INIT 0x0000000000000000 - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL */ -/* Description: Nibble 0: Word Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_SHFT 0 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_MASK 0x000000000000000f - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL */ -/* Description: Nibble 0: Nibble Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_SHFT 4 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL */ -/* Description: Nibble 1: Word Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_SHFT 8 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000f00 - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL */ -/* Description: Nibble 1: Nibble Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_SHFT 12 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL */ -/* Description: Nibble 2: Word Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_SHFT 16 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_MASK 0x00000000000f0000 - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL */ -/* Description: Nibble 2: Nibble Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_SHFT 20 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL */ -/* Description: Nibble 3: Word Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_SHFT 24 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_MASK 0x000000000f000000 - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL */ -/* Description: Nibble 3: Nibble Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_SHFT 28 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL */ -/* Description: Nibble 4: Word Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_SHFT 32 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_MASK 0x0000000f00000000 - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL */ -/* Description: Nibble 4: Nibble Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_SHFT 36 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL */ -/* Description: Nibble 5: Word Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_SHFT 40 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_MASK 0x00000f0000000000 - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL */ -/* Description: Nibble 5: Nibble Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_SHFT 44 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL */ -/* Description: Nibble 6: Word Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_SHFT 48 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_MASK 0x000f000000000000 - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL */ -/* Description: Nibble 6: Nibble Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_SHFT 52 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL */ -/* Description: Nibble 7: Word Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_SHFT 56 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_MASK 0x0f00000000000000 - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL */ -/* Description: Nibble 7: Nibble Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_SHFT 60 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* SH_PI_AFI_TEST_POINT_SELECT_TRIGGER_ENABLE */ -/* Description: Trigger Enabled */ -#define SH_PI_AFI_TEST_POINT_SELECT_TRIGGER_ENABLE_SHFT 63 -#define SH_PI_AFI_TEST_POINT_SELECT_TRIGGER_ENABLE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_AFI_TEST_POINT_TRIGGER_SELECT" */ -/* PI CRBC Test Point Trigger Select */ -/* ==================================================================== */ - -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT 0x0000000120050200 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_MASK 0x7f7f7f7f7f7f7f7f -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_INIT 0x0000000000000000 - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL */ -/* Description: Nibble 0 Chiplet select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_SHFT 0 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_MASK 0x000000000000000f - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_SHFT 4 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL */ -/* Description: Nibble 1 Chiplet select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_SHFT 8 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_MASK 0x0000000000000f00 - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_SHFT 12 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL */ -/* Description: Nibble 2 Chiplet select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_SHFT 16 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_MASK 0x00000000000f0000 - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_SHFT 20 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL */ -/* Description: Nibble 3 Chiplet select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_SHFT 24 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_MASK 0x000000000f000000 - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_SHFT 28 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL */ -/* Description: Nibble 4 Chiplet select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_SHFT 32 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_MASK 0x0000000f00000000 - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_SHFT 36 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL */ -/* Description: Nibble 5 Chiplet select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_SHFT 40 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_MASK 0x00000f0000000000 - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_SHFT 44 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL */ -/* Description: Nibble 6 Chiplet select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_SHFT 48 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_MASK 0x000f000000000000 - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_SHFT 52 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL */ -/* Description: Nibble 7 Chiplet select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_SHFT 56 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_MASK 0x0f00000000000000 - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_SHFT 60 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_AUTO_REPLY_ENABLE" */ -/* PI Auto Reply Enable */ -/* ==================================================================== */ - -#define SH_PI_AUTO_REPLY_ENABLE 0x0000000120050280 -#define SH_PI_AUTO_REPLY_ENABLE_MASK 0x0000000000000001 -#define SH_PI_AUTO_REPLY_ENABLE_INIT 0x0000000000000000 - -/* SH_PI_AUTO_REPLY_ENABLE_AUTO_REPLY_ENABLE */ -/* Description: Auto Reply Enabled */ -#define SH_PI_AUTO_REPLY_ENABLE_AUTO_REPLY_ENABLE_SHFT 0 -#define SH_PI_AUTO_REPLY_ENABLE_AUTO_REPLY_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_PI_CAM_CONTROL" */ -/* CRB CAM MMR Access Control */ -/* ==================================================================== */ - -#define SH_PI_CAM_CONTROL 0x0000000120050300 -#define SH_PI_CAM_CONTROL_MASK 0x800000000000037f -#define SH_PI_CAM_CONTROL_INIT 0x0000000000000000 - -/* SH_PI_CAM_CONTROL_CAM_INDX */ -/* Description: CRB CAM Index to perform read/write on. */ -#define SH_PI_CAM_CONTROL_CAM_INDX_SHFT 0 -#define SH_PI_CAM_CONTROL_CAM_INDX_MASK 0x000000000000007f - -/* SH_PI_CAM_CONTROL_CAM_WRITE */ -/* Description: Is CRB CAM MMR function a write. */ -#define SH_PI_CAM_CONTROL_CAM_WRITE_SHFT 8 -#define SH_PI_CAM_CONTROL_CAM_WRITE_MASK 0x0000000000000100 - -/* SH_PI_CAM_CONTROL_RRB_RD_XFER_CLEAR */ -/* Description: Clear RRB read tranfer pending. */ -#define SH_PI_CAM_CONTROL_RRB_RD_XFER_CLEAR_SHFT 9 -#define SH_PI_CAM_CONTROL_RRB_RD_XFER_CLEAR_MASK 0x0000000000000200 - -/* SH_PI_CAM_CONTROL_START */ -/* Description: Start CRB CAM read/write operation */ -#define SH_PI_CAM_CONTROL_START_SHFT 63 -#define SH_PI_CAM_CONTROL_START_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_CRBC_TEST_POINT_COMPARE" */ -/* PI CRBC Test Point Compare */ -/* ==================================================================== */ - -#define SH_PI_CRBC_TEST_POINT_COMPARE 0x0000000120050380 -#define SH_PI_CRBC_TEST_POINT_COMPARE_MASK 0xffffffffffffffff -#define SH_PI_CRBC_TEST_POINT_COMPARE_INIT 0xffffffff00000000 - -/* SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_MASK */ -/* Description: Mask to select Debug bits for trigger generation */ -#define SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_MASK_SHFT 0 -#define SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_MASK_MASK 0x00000000ffffffff - -/* SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_PATTERN */ -/* Description: debug bit pattern for trigger generation */ -#define SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_PATTERN_SHFT 32 -#define SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_PATTERN_MASK 0xffffffff00000000 - -/* ==================================================================== */ -/* Register "SH_PI_CRBC_TEST_POINT_SELECT" */ -/* PI CRBC Test Point Select */ -/* ==================================================================== */ - -#define SH_PI_CRBC_TEST_POINT_SELECT 0x0000000120050400 -#define SH_PI_CRBC_TEST_POINT_SELECT_MASK 0xf777777777777777 -#define SH_PI_CRBC_TEST_POINT_SELECT_INIT 0x0000000000000000 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL */ -/* Description: Nibble 0 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_SHFT 0 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000007 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_SHFT 4 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL */ -/* Description: Nibble 1 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_SHFT 8 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000700 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_SHFT 12 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL */ -/* Description: Nibble 2 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_SHFT 16 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000070000 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_SHFT 20 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL */ -/* Description: Nibble 3 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_SHFT 24 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_MASK 0x0000000007000000 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_SHFT 28 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL */ -/* Description: Nibble 4 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_SHFT 32 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_MASK 0x0000000700000000 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_SHFT 36 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL */ -/* Description: Nibble 5 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_SHFT 40 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_MASK 0x0000070000000000 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_SHFT 44 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL */ -/* Description: Nibble 6 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_SHFT 48 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_MASK 0x0007000000000000 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_SHFT 52 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL */ -/* Description: Nibble 7 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_SHFT 56 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_MASK 0x0700000000000000 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_SHFT 60 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* SH_PI_CRBC_TEST_POINT_SELECT_TRIGGER_ENABLE */ -/* Description: Enable trigger on bit 32 of Analyzer data */ -#define SH_PI_CRBC_TEST_POINT_SELECT_TRIGGER_ENABLE_SHFT 63 -#define SH_PI_CRBC_TEST_POINT_SELECT_TRIGGER_ENABLE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT" */ -/* PI CRBC Test Point Trigger Select */ -/* ==================================================================== */ - -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT 0x0000000120050480 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_MASK 0x7777777777777777 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_INIT 0x0000000000000000 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL */ -/* Description: Nibble 0 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_SHFT 0 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_MASK 0x0000000000000007 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_SHFT 4 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL */ -/* Description: Nibble 1 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_SHFT 8 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_MASK 0x0000000000000700 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_SHFT 12 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL */ -/* Description: Nibble 2 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_SHFT 16 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_MASK 0x0000000000070000 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_SHFT 20 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL */ -/* Description: Nibble 3 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_SHFT 24 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_MASK 0x0000000007000000 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_SHFT 28 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL */ -/* Description: Nibble 4 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_SHFT 32 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_MASK 0x0000000700000000 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_SHFT 36 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL */ -/* Description: Nibble 5 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_SHFT 40 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_MASK 0x0000070000000000 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_SHFT 44 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL */ -/* Description: Nibble 6 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_SHFT 48 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_MASK 0x0007000000000000 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_SHFT 52 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL */ -/* Description: Nibble 7 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_SHFT 56 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_MASK 0x0700000000000000 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_SHFT 60 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_ERROR_MASK" */ -/* PI CRBP Error Mask */ -/* ==================================================================== */ - -#define SH_PI_CRBP_ERROR_MASK 0x0000000120050500 -#define SH_PI_CRBP_ERROR_MASK_MASK 0x00000000001fffff -#define SH_PI_CRBP_ERROR_MASK_INIT 0x00000000001fffff - -/* SH_PI_CRBP_ERROR_MASK_FSB_PROTO_ERR */ -/* Description: Mask detection internal protocol table misses */ -#define SH_PI_CRBP_ERROR_MASK_FSB_PROTO_ERR_SHFT 0 -#define SH_PI_CRBP_ERROR_MASK_FSB_PROTO_ERR_MASK 0x0000000000000001 - -/* SH_PI_CRBP_ERROR_MASK_GFX_RP_ERR */ -/* Description: Mask graphic reply error detection */ -#define SH_PI_CRBP_ERROR_MASK_GFX_RP_ERR_SHFT 1 -#define SH_PI_CRBP_ERROR_MASK_GFX_RP_ERR_MASK 0x0000000000000002 - -/* SH_PI_CRBP_ERROR_MASK_XB_PROTO_ERR */ -/* Description: Mask detection of external protocol table misses */ -#define SH_PI_CRBP_ERROR_MASK_XB_PROTO_ERR_SHFT 2 -#define SH_PI_CRBP_ERROR_MASK_XB_PROTO_ERR_MASK 0x0000000000000004 - -/* SH_PI_CRBP_ERROR_MASK_MEM_RP_ERR */ -/* Description: Mask memory error reply message detection */ -#define SH_PI_CRBP_ERROR_MASK_MEM_RP_ERR_SHFT 3 -#define SH_PI_CRBP_ERROR_MASK_MEM_RP_ERR_MASK 0x0000000000000008 - -/* SH_PI_CRBP_ERROR_MASK_PIO_RP_ERR */ -/* Description: Mask PIO reply error message detection */ -#define SH_PI_CRBP_ERROR_MASK_PIO_RP_ERR_SHFT 4 -#define SH_PI_CRBP_ERROR_MASK_PIO_RP_ERR_MASK 0x0000000000000010 - -/* SH_PI_CRBP_ERROR_MASK_MEM_TO_ERR */ -/* Description: Mask memory time-out detection */ -#define SH_PI_CRBP_ERROR_MASK_MEM_TO_ERR_SHFT 5 -#define SH_PI_CRBP_ERROR_MASK_MEM_TO_ERR_MASK 0x0000000000000020 - -/* SH_PI_CRBP_ERROR_MASK_PIO_TO_ERR */ -/* Description: Mask PIO time-out detection */ -#define SH_PI_CRBP_ERROR_MASK_PIO_TO_ERR_SHFT 6 -#define SH_PI_CRBP_ERROR_MASK_PIO_TO_ERR_MASK 0x0000000000000040 - -/* SH_PI_CRBP_ERROR_MASK_FSB_SHUB_UCE */ -/* Description: Mask un-correctable ECC error detection */ -#define SH_PI_CRBP_ERROR_MASK_FSB_SHUB_UCE_SHFT 7 -#define SH_PI_CRBP_ERROR_MASK_FSB_SHUB_UCE_MASK 0x0000000000000080 - -/* SH_PI_CRBP_ERROR_MASK_FSB_SHUB_CE */ -/* Description: Mask correctable ECC error detection */ -#define SH_PI_CRBP_ERROR_MASK_FSB_SHUB_CE_SHFT 8 -#define SH_PI_CRBP_ERROR_MASK_FSB_SHUB_CE_MASK 0x0000000000000100 - -/* SH_PI_CRBP_ERROR_MASK_MSG_COLOR_ERR */ -/* Description: Mask detection of color errors */ -#define SH_PI_CRBP_ERROR_MASK_MSG_COLOR_ERR_SHFT 9 -#define SH_PI_CRBP_ERROR_MASK_MSG_COLOR_ERR_MASK 0x0000000000000200 - -/* SH_PI_CRBP_ERROR_MASK_MD_RQ_Q_OFLOW */ -/* Description: Mask MD Request input buffer over flow error */ -#define SH_PI_CRBP_ERROR_MASK_MD_RQ_Q_OFLOW_SHFT 10 -#define SH_PI_CRBP_ERROR_MASK_MD_RQ_Q_OFLOW_MASK 0x0000000000000400 - -/* SH_PI_CRBP_ERROR_MASK_MD_RP_Q_OFLOW */ -/* Description: Mask MD Reply input buffer over flow error */ -#define SH_PI_CRBP_ERROR_MASK_MD_RP_Q_OFLOW_SHFT 11 -#define SH_PI_CRBP_ERROR_MASK_MD_RP_Q_OFLOW_MASK 0x0000000000000800 - -/* SH_PI_CRBP_ERROR_MASK_XN_RQ_Q_OFLOW */ -/* Description: Mask XN Request input buffer over flow error */ -#define SH_PI_CRBP_ERROR_MASK_XN_RQ_Q_OFLOW_SHFT 12 -#define SH_PI_CRBP_ERROR_MASK_XN_RQ_Q_OFLOW_MASK 0x0000000000001000 - -/* SH_PI_CRBP_ERROR_MASK_XN_RP_Q_OFLOW */ -/* Description: Mask XN Reply input buffer over flow error */ -#define SH_PI_CRBP_ERROR_MASK_XN_RP_Q_OFLOW_SHFT 13 -#define SH_PI_CRBP_ERROR_MASK_XN_RP_Q_OFLOW_MASK 0x0000000000002000 - -/* SH_PI_CRBP_ERROR_MASK_NACK_OFLOW */ -/* Description: Mask NACK over flow error */ -#define SH_PI_CRBP_ERROR_MASK_NACK_OFLOW_SHFT 14 -#define SH_PI_CRBP_ERROR_MASK_NACK_OFLOW_MASK 0x0000000000004000 - -/* SH_PI_CRBP_ERROR_MASK_GFX_INT_0 */ -/* Description: Mask GFX transfer interrupt for CPU 0 */ -#define SH_PI_CRBP_ERROR_MASK_GFX_INT_0_SHFT 15 -#define SH_PI_CRBP_ERROR_MASK_GFX_INT_0_MASK 0x0000000000008000 - -/* SH_PI_CRBP_ERROR_MASK_GFX_INT_1 */ -/* Description: Mask GFX transfer interrupt for CPU 1 */ -#define SH_PI_CRBP_ERROR_MASK_GFX_INT_1_SHFT 16 -#define SH_PI_CRBP_ERROR_MASK_GFX_INT_1_MASK 0x0000000000010000 - -/* SH_PI_CRBP_ERROR_MASK_MD_RQ_CRD_OFLOW */ -/* Description: Mask MD Request Credit Overflow Error */ -#define SH_PI_CRBP_ERROR_MASK_MD_RQ_CRD_OFLOW_SHFT 17 -#define SH_PI_CRBP_ERROR_MASK_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000 - -/* SH_PI_CRBP_ERROR_MASK_MD_RP_CRD_OFLOW */ -/* Description: Mask MD Reply Credit Overflow Error */ -#define SH_PI_CRBP_ERROR_MASK_MD_RP_CRD_OFLOW_SHFT 18 -#define SH_PI_CRBP_ERROR_MASK_MD_RP_CRD_OFLOW_MASK 0x0000000000040000 - -/* SH_PI_CRBP_ERROR_MASK_XN_RQ_CRD_OFLOW */ -/* Description: Mask XN Request Credit Overflow Error */ -#define SH_PI_CRBP_ERROR_MASK_XN_RQ_CRD_OFLOW_SHFT 19 -#define SH_PI_CRBP_ERROR_MASK_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000 - -/* SH_PI_CRBP_ERROR_MASK_XN_RP_CRD_OFLOW */ -/* Description: Mask XN Reply Credit Overflow Error */ -#define SH_PI_CRBP_ERROR_MASK_XN_RP_CRD_OFLOW_SHFT 20 -#define SH_PI_CRBP_ERROR_MASK_XN_RP_CRD_OFLOW_MASK 0x0000000000100000 - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_FSB_PIPE_COMPARE" */ -/* CRBP FSB Pipe Compare */ -/* ==================================================================== */ - -#define SH_PI_CRBP_FSB_PIPE_COMPARE 0x0000000120050580 -#define SH_PI_CRBP_FSB_PIPE_COMPARE_MASK 0x001fffffffffffff -#define SH_PI_CRBP_FSB_PIPE_COMPARE_INIT 0x0000000000000000 - -/* SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_ADDRESS */ -/* Description: Address A or B to compare against */ -#define SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_ADDRESS_SHFT 0 -#define SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_ADDRESS_MASK 0x00007fffffffffff - -/* SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_REQ */ -/* Description: REQa or REQb value to compare against */ -#define SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_REQ_SHFT 47 -#define SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_REQ_MASK 0x001f800000000000 - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_FSB_PIPE_MASK" */ -/* CRBP Compare Mask */ -/* ==================================================================== */ - -#define SH_PI_CRBP_FSB_PIPE_MASK 0x0000000120050600 -#define SH_PI_CRBP_FSB_PIPE_MASK_MASK 0x001fffffffffffff -#define SH_PI_CRBP_FSB_PIPE_MASK_INIT 0x0000000000000000 - -/* SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_ADDRESS_MASK */ -/* Description: Address A or B mask values */ -#define SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_ADDRESS_MASK_SHFT 0 -#define SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_ADDRESS_MASK_MASK 0x00007fffffffffff - -/* SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_REQ_MASK */ -/* Description: REQa or REQb mask values */ -#define SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_REQ_MASK_SHFT 47 -#define SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_REQ_MASK_MASK 0x001f800000000000 - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_TEST_POINT_COMPARE" */ -/* PI CRBP Test Point Compare */ -/* ==================================================================== */ - -#define SH_PI_CRBP_TEST_POINT_COMPARE 0x0000000120050680 -#define SH_PI_CRBP_TEST_POINT_COMPARE_MASK 0xffffffffffffffff -#define SH_PI_CRBP_TEST_POINT_COMPARE_INIT 0xffffffff00000000 - -/* SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_MASK */ -/* Description: Mask to select Debug bits for trigger generation */ -#define SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_MASK_SHFT 0 -#define SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_MASK_MASK 0x00000000ffffffff - -/* SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_PATTERN */ -/* Description: debug bit pattern for trigger generation */ -#define SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_PATTERN_SHFT 32 -#define SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_PATTERN_MASK 0xffffffff00000000 - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_TEST_POINT_SELECT" */ -/* PI CRBP Test Point Select */ -/* ==================================================================== */ - -#define SH_PI_CRBP_TEST_POINT_SELECT 0x0000000120050700 -#define SH_PI_CRBP_TEST_POINT_SELECT_MASK 0xf777777777777777 -#define SH_PI_CRBP_TEST_POINT_SELECT_INIT 0x0000000000000000 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL */ -/* Description: Nibble 0 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_SHFT 0 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000007 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_SHFT 4 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL */ -/* Description: Nibble 1 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_SHFT 8 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000700 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_SHFT 12 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL */ -/* Description: Nibble 2 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_SHFT 16 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000070000 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_SHFT 20 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL */ -/* Description: Nibble 3 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_SHFT 24 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_MASK 0x0000000007000000 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_SHFT 28 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL */ -/* Description: Nibble 4 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_SHFT 32 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_MASK 0x0000000700000000 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_SHFT 36 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL */ -/* Description: Nibble 5 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_SHFT 40 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_MASK 0x0000070000000000 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_SHFT 44 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL */ -/* Description: Nibble 6 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_SHFT 48 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_MASK 0x0007000000000000 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_SHFT 52 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL */ -/* Description: Nibble 7 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_SHFT 56 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_MASK 0x0700000000000000 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_SHFT 60 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* SH_PI_CRBP_TEST_POINT_SELECT_TRIGGER_ENABLE */ -/* Description: Enable trigger on bit 32 of Analyzer data */ -#define SH_PI_CRBP_TEST_POINT_SELECT_TRIGGER_ENABLE_SHFT 63 -#define SH_PI_CRBP_TEST_POINT_SELECT_TRIGGER_ENABLE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT" */ -/* PI CRBP Test Point Trigger Select */ -/* ==================================================================== */ - -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT 0x0000000120050780 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_MASK 0x7777777777777777 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_INIT 0x0000000000000000 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL */ -/* Description: Nibble 0 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_SHFT 0 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_MASK 0x0000000000000007 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_SHFT 4 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL */ -/* Description: Nibble 1 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_SHFT 8 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_MASK 0x0000000000000700 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_SHFT 12 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL */ -/* Description: Nibble 2 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_SHFT 16 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_MASK 0x0000000000070000 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_SHFT 20 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL */ -/* Description: Nibble 3 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_SHFT 24 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_MASK 0x0000000007000000 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_SHFT 28 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL */ -/* Description: Nibble 4 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_SHFT 32 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_MASK 0x0000000700000000 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_SHFT 36 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL */ -/* Description: Nibble 5 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_SHFT 40 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_MASK 0x0000070000000000 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_SHFT 44 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL */ -/* Description: Nibble 6 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_SHFT 48 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_MASK 0x0007000000000000 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_SHFT 52 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL */ -/* Description: Nibble 7 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_SHFT 56 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_MASK 0x0700000000000000 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_SHFT 60 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_XB_PIPE_COMPARE_0" */ -/* CRBP XB Pipe Compare */ -/* ==================================================================== */ - -#define SH_PI_CRBP_XB_PIPE_COMPARE_0 0x0000000120050800 -#define SH_PI_CRBP_XB_PIPE_COMPARE_0_MASK 0x007fffffffffffff -#define SH_PI_CRBP_XB_PIPE_COMPARE_0_INIT 0x0000000000000000 - -/* SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_ADDRESS */ -/* Description: Address to compare against */ -#define SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_ADDRESS_SHFT 0 -#define SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_ADDRESS_MASK 0x00007fffffffffff - -/* SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_COMMAND */ -/* Description: SN2NET Command to compare against */ -#define SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_COMMAND_SHFT 47 -#define SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_COMMAND_MASK 0x007f800000000000 - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_XB_PIPE_COMPARE_1" */ -/* CRBP XB Pipe Compare */ -/* ==================================================================== */ - -#define SH_PI_CRBP_XB_PIPE_COMPARE_1 0x0000000120050880 -#define SH_PI_CRBP_XB_PIPE_COMPARE_1_MASK 0x000001ff3fff3fff -#define SH_PI_CRBP_XB_PIPE_COMPARE_1_INIT 0x0000000000000000 - -/* SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SOURCE */ -/* Description: Source to compare against */ -#define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SOURCE_SHFT 0 -#define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SOURCE_MASK 0x0000000000003fff - -/* SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SUPPLEMENTAL */ -/* Description: Supplemental to compare against */ -#define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SUPPLEMENTAL_SHFT 16 -#define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SUPPLEMENTAL_MASK 0x000000003fff0000 - -/* SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_ECHO */ -/* Description: Echo to compare against */ -#define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_ECHO_SHFT 32 -#define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_ECHO_MASK 0x000001ff00000000 - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_XB_PIPE_MASK_0" */ -/* CRBP Compare Mask Register 1 */ -/* ==================================================================== */ - -#define SH_PI_CRBP_XB_PIPE_MASK_0 0x0000000120050900 -#define SH_PI_CRBP_XB_PIPE_MASK_0_MASK 0x007fffffffffffff -#define SH_PI_CRBP_XB_PIPE_MASK_0_INIT 0x0000000000000000 - -/* SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_ADDRESS_MASK */ -/* Description: Address to compare against */ -#define SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_ADDRESS_MASK_SHFT 0 -#define SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_ADDRESS_MASK_MASK 0x00007fffffffffff - -/* SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_COMMAND_MASK */ -/* Description: SN2NET Command to compare against */ -#define SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_COMMAND_MASK_SHFT 47 -#define SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_COMMAND_MASK_MASK 0x007f800000000000 - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_XB_PIPE_MASK_1" */ -/* CRBP XB Pipe Compare Mask Register 1 */ -/* ==================================================================== */ - -#define SH_PI_CRBP_XB_PIPE_MASK_1 0x0000000120050980 -#define SH_PI_CRBP_XB_PIPE_MASK_1_MASK 0x000001ff3fff3fff -#define SH_PI_CRBP_XB_PIPE_MASK_1_INIT 0x0000000000000000 - -/* SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SOURCE_MASK */ -/* Description: Source to compare against */ -#define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SOURCE_MASK_SHFT 0 -#define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SOURCE_MASK_MASK 0x0000000000003fff - -/* SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SUPPLEMENTAL_MASK */ -/* Description: Supplemental to compare against */ -#define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SUPPLEMENTAL_MASK_SHFT 16 -#define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SUPPLEMENTAL_MASK_MASK 0x000000003fff0000 - -/* SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_ECHO_MASK */ -/* Description: Echo to compare against */ -#define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_ECHO_MASK_SHFT 32 -#define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_ECHO_MASK_MASK 0x000001ff00000000 - -/* ==================================================================== */ -/* Register "SH_PI_DPC_QUEUE_CONFIG" */ -/* DPC Queue Configuration */ -/* ==================================================================== */ - -#define SH_PI_DPC_QUEUE_CONFIG 0x0000000120050a00 -#define SH_PI_DPC_QUEUE_CONFIG_MASK 0x000000001f1f1f1f -#define SH_PI_DPC_QUEUE_CONFIG_INIT 0x000000000c010c01 - -/* SH_PI_DPC_QUEUE_CONFIG_DWCQ_AE_LEVEL */ -/* Description: DXB WTL Command Queue Almost Empty Level */ -#define SH_PI_DPC_QUEUE_CONFIG_DWCQ_AE_LEVEL_SHFT 0 -#define SH_PI_DPC_QUEUE_CONFIG_DWCQ_AE_LEVEL_MASK 0x000000000000001f - -/* SH_PI_DPC_QUEUE_CONFIG_DWCQ_AF_THRESH */ -/* Description: DXB WTL Command Queue Almost Full Threshold */ -#define SH_PI_DPC_QUEUE_CONFIG_DWCQ_AF_THRESH_SHFT 8 -#define SH_PI_DPC_QUEUE_CONFIG_DWCQ_AF_THRESH_MASK 0x0000000000001f00 - -/* SH_PI_DPC_QUEUE_CONFIG_FWCQ_AE_LEVEL */ -/* Description: FSB WTL Command Queue Almost Empty Level */ -#define SH_PI_DPC_QUEUE_CONFIG_FWCQ_AE_LEVEL_SHFT 16 -#define SH_PI_DPC_QUEUE_CONFIG_FWCQ_AE_LEVEL_MASK 0x00000000001f0000 - -/* SH_PI_DPC_QUEUE_CONFIG_FWCQ_AF_THRESH */ -/* Description: FSB WTL Command Queue Almost Full Threshold */ -#define SH_PI_DPC_QUEUE_CONFIG_FWCQ_AF_THRESH_SHFT 24 -#define SH_PI_DPC_QUEUE_CONFIG_FWCQ_AF_THRESH_MASK 0x000000001f000000 - -/* ==================================================================== */ -/* Register "SH_PI_ERROR_MASK" */ -/* PI Error Mask */ -/* ==================================================================== */ - -#define SH_PI_ERROR_MASK 0x0000000120050a80 -#define SH_PI_ERROR_MASK_MASK 0x00000007ffffffff -#define SH_PI_ERROR_MASK_INIT 0x00000007ffffffff - -/* SH_PI_ERROR_MASK_FSB_PROTO_ERR */ -/* Description: Mask detection of internal protocol table misses */ -#define SH_PI_ERROR_MASK_FSB_PROTO_ERR_SHFT 0 -#define SH_PI_ERROR_MASK_FSB_PROTO_ERR_MASK 0x0000000000000001 - -/* SH_PI_ERROR_MASK_GFX_RP_ERR */ -/* Description: Mask graphic reply error message error detection */ -#define SH_PI_ERROR_MASK_GFX_RP_ERR_SHFT 1 -#define SH_PI_ERROR_MASK_GFX_RP_ERR_MASK 0x0000000000000002 - -/* SH_PI_ERROR_MASK_XB_PROTO_ERR */ -/* Description: Mask detection of external protocol table misses */ -#define SH_PI_ERROR_MASK_XB_PROTO_ERR_SHFT 2 -#define SH_PI_ERROR_MASK_XB_PROTO_ERR_MASK 0x0000000000000004 - -/* SH_PI_ERROR_MASK_MEM_RP_ERR */ -/* Description: Mask memory reply error detection */ -#define SH_PI_ERROR_MASK_MEM_RP_ERR_SHFT 3 -#define SH_PI_ERROR_MASK_MEM_RP_ERR_MASK 0x0000000000000008 - -/* SH_PI_ERROR_MASK_PIO_RP_ERR */ -/* Description: Mask PIO reply error detection */ -#define SH_PI_ERROR_MASK_PIO_RP_ERR_SHFT 4 -#define SH_PI_ERROR_MASK_PIO_RP_ERR_MASK 0x0000000000000010 - -/* SH_PI_ERROR_MASK_MEM_TO_ERR */ -/* Description: Mask CRB time-out errors */ -#define SH_PI_ERROR_MASK_MEM_TO_ERR_SHFT 5 -#define SH_PI_ERROR_MASK_MEM_TO_ERR_MASK 0x0000000000000020 - -/* SH_PI_ERROR_MASK_PIO_TO_ERR */ -/* Description: Mask PIO time-out errors */ -#define SH_PI_ERROR_MASK_PIO_TO_ERR_SHFT 6 -#define SH_PI_ERROR_MASK_PIO_TO_ERR_MASK 0x0000000000000040 - -/* SH_PI_ERROR_MASK_FSB_SHUB_UCE */ -/* Description: Mask un-correctable ECC error detection */ -#define SH_PI_ERROR_MASK_FSB_SHUB_UCE_SHFT 7 -#define SH_PI_ERROR_MASK_FSB_SHUB_UCE_MASK 0x0000000000000080 - -/* SH_PI_ERROR_MASK_FSB_SHUB_CE */ -/* Description: Mask correctable ECC error detection */ -#define SH_PI_ERROR_MASK_FSB_SHUB_CE_SHFT 8 -#define SH_PI_ERROR_MASK_FSB_SHUB_CE_MASK 0x0000000000000100 - -/* SH_PI_ERROR_MASK_MSG_COLOR_ERR */ -/* Description: Mask message color error detection */ -#define SH_PI_ERROR_MASK_MSG_COLOR_ERR_SHFT 9 -#define SH_PI_ERROR_MASK_MSG_COLOR_ERR_MASK 0x0000000000000200 - -/* SH_PI_ERROR_MASK_MD_RQ_Q_OFLOW */ -/* Description: Mask MD Request input buffer over flow error */ -#define SH_PI_ERROR_MASK_MD_RQ_Q_OFLOW_SHFT 10 -#define SH_PI_ERROR_MASK_MD_RQ_Q_OFLOW_MASK 0x0000000000000400 - -/* SH_PI_ERROR_MASK_MD_RP_Q_OFLOW */ -/* Description: Mask MD Reply input buffer over flow error */ -#define SH_PI_ERROR_MASK_MD_RP_Q_OFLOW_SHFT 11 -#define SH_PI_ERROR_MASK_MD_RP_Q_OFLOW_MASK 0x0000000000000800 - -/* SH_PI_ERROR_MASK_XN_RQ_Q_OFLOW */ -/* Description: Mask XN Request input buffer over flow error */ -#define SH_PI_ERROR_MASK_XN_RQ_Q_OFLOW_SHFT 12 -#define SH_PI_ERROR_MASK_XN_RQ_Q_OFLOW_MASK 0x0000000000001000 - -/* SH_PI_ERROR_MASK_XN_RP_Q_OFLOW */ -/* Description: Mask XN Reply input buffer over flow error */ -#define SH_PI_ERROR_MASK_XN_RP_Q_OFLOW_SHFT 13 -#define SH_PI_ERROR_MASK_XN_RP_Q_OFLOW_MASK 0x0000000000002000 - -/* SH_PI_ERROR_MASK_NACK_OFLOW */ -/* Description: Mask NACK over flow error */ -#define SH_PI_ERROR_MASK_NACK_OFLOW_SHFT 14 -#define SH_PI_ERROR_MASK_NACK_OFLOW_MASK 0x0000000000004000 - -/* SH_PI_ERROR_MASK_GFX_INT_0 */ -/* Description: Mask GFX transfer interrupt for CPU 0 */ -#define SH_PI_ERROR_MASK_GFX_INT_0_SHFT 15 -#define SH_PI_ERROR_MASK_GFX_INT_0_MASK 0x0000000000008000 - -/* SH_PI_ERROR_MASK_GFX_INT_1 */ -/* Description: Mask GFX transfer interrupt for CPU 1 */ -#define SH_PI_ERROR_MASK_GFX_INT_1_SHFT 16 -#define SH_PI_ERROR_MASK_GFX_INT_1_MASK 0x0000000000010000 - -/* SH_PI_ERROR_MASK_MD_RQ_CRD_OFLOW */ -/* Description: Mask MD Request Credit Overflow Error */ -#define SH_PI_ERROR_MASK_MD_RQ_CRD_OFLOW_SHFT 17 -#define SH_PI_ERROR_MASK_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000 - -/* SH_PI_ERROR_MASK_MD_RP_CRD_OFLOW */ -/* Description: Mask MD Reply Credit Overflow Error */ -#define SH_PI_ERROR_MASK_MD_RP_CRD_OFLOW_SHFT 18 -#define SH_PI_ERROR_MASK_MD_RP_CRD_OFLOW_MASK 0x0000000000040000 - -/* SH_PI_ERROR_MASK_XN_RQ_CRD_OFLOW */ -/* Description: Mask XN Request Credit Overflow Error */ -#define SH_PI_ERROR_MASK_XN_RQ_CRD_OFLOW_SHFT 19 -#define SH_PI_ERROR_MASK_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000 - -/* SH_PI_ERROR_MASK_XN_RP_CRD_OFLOW */ -/* Description: Mask XN Reply Credit Overflow Error */ -#define SH_PI_ERROR_MASK_XN_RP_CRD_OFLOW_SHFT 20 -#define SH_PI_ERROR_MASK_XN_RP_CRD_OFLOW_MASK 0x0000000000100000 - -/* SH_PI_ERROR_MASK_HUNG_BUS */ -/* Description: Mask FSB hung error */ -#define SH_PI_ERROR_MASK_HUNG_BUS_SHFT 21 -#define SH_PI_ERROR_MASK_HUNG_BUS_MASK 0x0000000000200000 - -/* SH_PI_ERROR_MASK_RSP_PARITY */ -/* Description: Parity error detecte during response phase */ -#define SH_PI_ERROR_MASK_RSP_PARITY_SHFT 22 -#define SH_PI_ERROR_MASK_RSP_PARITY_MASK 0x0000000000400000 - -/* SH_PI_ERROR_MASK_IOQ_OVERRUN */ -/* Description: Over run error detected on IOQ */ -#define SH_PI_ERROR_MASK_IOQ_OVERRUN_SHFT 23 -#define SH_PI_ERROR_MASK_IOQ_OVERRUN_MASK 0x0000000000800000 - -/* SH_PI_ERROR_MASK_REQ_FORMAT */ -/* Description: FSB request format not supported */ -#define SH_PI_ERROR_MASK_REQ_FORMAT_SHFT 24 -#define SH_PI_ERROR_MASK_REQ_FORMAT_MASK 0x0000000001000000 - -/* SH_PI_ERROR_MASK_ADDR_ACCESS */ -/* Description: Access to Address is not supported */ -#define SH_PI_ERROR_MASK_ADDR_ACCESS_SHFT 25 -#define SH_PI_ERROR_MASK_ADDR_ACCESS_MASK 0x0000000002000000 - -/* SH_PI_ERROR_MASK_REQ_PARITY */ -/* Description: Parity error detected during request phase */ -#define SH_PI_ERROR_MASK_REQ_PARITY_SHFT 26 -#define SH_PI_ERROR_MASK_REQ_PARITY_MASK 0x0000000004000000 - -/* SH_PI_ERROR_MASK_ADDR_PARITY */ -/* Description: Parity error detected on address */ -#define SH_PI_ERROR_MASK_ADDR_PARITY_SHFT 27 -#define SH_PI_ERROR_MASK_ADDR_PARITY_MASK 0x0000000008000000 - -/* SH_PI_ERROR_MASK_SHUB_FSB_DQE */ -/* Description: SHUB_FSB_DQE */ -#define SH_PI_ERROR_MASK_SHUB_FSB_DQE_SHFT 28 -#define SH_PI_ERROR_MASK_SHUB_FSB_DQE_MASK 0x0000000010000000 - -/* SH_PI_ERROR_MASK_SHUB_FSB_UCE */ -/* Description: An un-correctable ECC error was detected */ -#define SH_PI_ERROR_MASK_SHUB_FSB_UCE_SHFT 29 -#define SH_PI_ERROR_MASK_SHUB_FSB_UCE_MASK 0x0000000020000000 - -/* SH_PI_ERROR_MASK_SHUB_FSB_CE */ -/* Description: An correctable ECC error was detected */ -#define SH_PI_ERROR_MASK_SHUB_FSB_CE_SHFT 30 -#define SH_PI_ERROR_MASK_SHUB_FSB_CE_MASK 0x0000000040000000 - -/* SH_PI_ERROR_MASK_LIVELOCK */ -/* Description: AFI livelock error was detected */ -#define SH_PI_ERROR_MASK_LIVELOCK_SHFT 31 -#define SH_PI_ERROR_MASK_LIVELOCK_MASK 0x0000000080000000 - -/* SH_PI_ERROR_MASK_BAD_SNOOP */ -/* Description: AFI bad snoop error was detected */ -#define SH_PI_ERROR_MASK_BAD_SNOOP_SHFT 32 -#define SH_PI_ERROR_MASK_BAD_SNOOP_MASK 0x0000000100000000 - -/* SH_PI_ERROR_MASK_FSB_TBL_MISS */ -/* Description: AFI FSB request table miss error was detected */ -#define SH_PI_ERROR_MASK_FSB_TBL_MISS_SHFT 33 -#define SH_PI_ERROR_MASK_FSB_TBL_MISS_MASK 0x0000000200000000 - -/* SH_PI_ERROR_MASK_MSG_LENGTH */ -/* Description: Message length error on received message from SIC */ -#define SH_PI_ERROR_MASK_MSG_LENGTH_SHFT 34 -#define SH_PI_ERROR_MASK_MSG_LENGTH_MASK 0x0000000400000000 - -/* ==================================================================== */ -/* Register "SH_PI_EXPRESS_REPLY_CONFIG" */ -/* PI Express Reply Configuration */ -/* ==================================================================== */ - -#define SH_PI_EXPRESS_REPLY_CONFIG 0x0000000120050b00 -#define SH_PI_EXPRESS_REPLY_CONFIG_MASK 0x0000000000000007 -#define SH_PI_EXPRESS_REPLY_CONFIG_INIT 0x0000000000000001 - -/* SH_PI_EXPRESS_REPLY_CONFIG_MODE */ -/* Description: Express Reply Mode */ -#define SH_PI_EXPRESS_REPLY_CONFIG_MODE_SHFT 0 -#define SH_PI_EXPRESS_REPLY_CONFIG_MODE_MASK 0x0000000000000007 - -/* ==================================================================== */ -/* Register "SH_PI_FSB_COMPARE_VALUE" */ -/* FSB Compare Value */ -/* ==================================================================== */ - -#define SH_PI_FSB_COMPARE_VALUE 0x0000000120050c00 -#define SH_PI_FSB_COMPARE_VALUE_MASK 0xffffffffffffffff -#define SH_PI_FSB_COMPARE_VALUE_INIT 0x0000000000000000 - -/* SH_PI_FSB_COMPARE_VALUE_COMPARE_VALUE */ -/* Description: Compare value */ -#define SH_PI_FSB_COMPARE_VALUE_COMPARE_VALUE_SHFT 0 -#define SH_PI_FSB_COMPARE_VALUE_COMPARE_VALUE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_PI_FSB_COMPARE_MASK" */ -/* FSB Compare Mask */ -/* ==================================================================== */ - -#define SH_PI_FSB_COMPARE_MASK 0x0000000120050b80 -#define SH_PI_FSB_COMPARE_MASK_MASK 0xffffffffffffffff -#define SH_PI_FSB_COMPARE_MASK_INIT 0x0000000000000000 - -/* SH_PI_FSB_COMPARE_MASK_MASK_VALUE */ -/* Description: Mask value */ -#define SH_PI_FSB_COMPARE_MASK_MASK_VALUE_SHFT 0 -#define SH_PI_FSB_COMPARE_MASK_MASK_VALUE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_PI_FSB_ERROR_INJECTION" */ -/* Inject an Error onto the FSB */ -/* ==================================================================== */ - -#define SH_PI_FSB_ERROR_INJECTION 0x0000000120050c80 -#define SH_PI_FSB_ERROR_INJECTION_MASK 0x000000070fff03ff -#define SH_PI_FSB_ERROR_INJECTION_INIT 0x0000000000000000 - -/* SH_PI_FSB_ERROR_INJECTION_RP_PE_TO_FSB */ -/* Description: Inject a RP# Parity Error onto the FSB */ -#define SH_PI_FSB_ERROR_INJECTION_RP_PE_TO_FSB_SHFT 0 -#define SH_PI_FSB_ERROR_INJECTION_RP_PE_TO_FSB_MASK 0x0000000000000001 - -/* SH_PI_FSB_ERROR_INJECTION_AP0_PE_TO_FSB */ -/* Description: Inject an AP[0]# Parity Error onto the FSB */ -#define SH_PI_FSB_ERROR_INJECTION_AP0_PE_TO_FSB_SHFT 1 -#define SH_PI_FSB_ERROR_INJECTION_AP0_PE_TO_FSB_MASK 0x0000000000000002 - -/* SH_PI_FSB_ERROR_INJECTION_AP1_PE_TO_FSB */ -/* Description: Inject an AP[1]# Parity Error onto the FSB */ -#define SH_PI_FSB_ERROR_INJECTION_AP1_PE_TO_FSB_SHFT 2 -#define SH_PI_FSB_ERROR_INJECTION_AP1_PE_TO_FSB_MASK 0x0000000000000004 - -/* SH_PI_FSB_ERROR_INJECTION_RSP_PE_TO_FSB */ -/* Description: Inject a RSP# Parity Error onto the FSB */ -#define SH_PI_FSB_ERROR_INJECTION_RSP_PE_TO_FSB_SHFT 3 -#define SH_PI_FSB_ERROR_INJECTION_RSP_PE_TO_FSB_MASK 0x0000000000000008 - -/* SH_PI_FSB_ERROR_INJECTION_DW0_CE_TO_FSB */ -/* Description: Inject a Correctable Error in Doubleword 0 onto the */ -#define SH_PI_FSB_ERROR_INJECTION_DW0_CE_TO_FSB_SHFT 4 -#define SH_PI_FSB_ERROR_INJECTION_DW0_CE_TO_FSB_MASK 0x0000000000000010 - -/* SH_PI_FSB_ERROR_INJECTION_DW0_UCE_TO_FSB */ -/* Description: Inject an Uncorrectable Error in Doubleword 0 onto */ -/* the FSB */ -#define SH_PI_FSB_ERROR_INJECTION_DW0_UCE_TO_FSB_SHFT 5 -#define SH_PI_FSB_ERROR_INJECTION_DW0_UCE_TO_FSB_MASK 0x0000000000000020 - -/* SH_PI_FSB_ERROR_INJECTION_DW1_CE_TO_FSB */ -/* Description: Inject a Correctable Error in Doubleword 1 onto the */ -#define SH_PI_FSB_ERROR_INJECTION_DW1_CE_TO_FSB_SHFT 6 -#define SH_PI_FSB_ERROR_INJECTION_DW1_CE_TO_FSB_MASK 0x0000000000000040 - -/* SH_PI_FSB_ERROR_INJECTION_DW1_UCE_TO_FSB */ -/* Description: Inject an Uncorrectable Error in Doubleword 1 onto */ -/* the FSB */ -#define SH_PI_FSB_ERROR_INJECTION_DW1_UCE_TO_FSB_SHFT 7 -#define SH_PI_FSB_ERROR_INJECTION_DW1_UCE_TO_FSB_MASK 0x0000000000000080 - -/* SH_PI_FSB_ERROR_INJECTION_IP0_PE_TO_FSB */ -/* Description: Inject an IP[0]# Parity Error onto the FSB */ -#define SH_PI_FSB_ERROR_INJECTION_IP0_PE_TO_FSB_SHFT 8 -#define SH_PI_FSB_ERROR_INJECTION_IP0_PE_TO_FSB_MASK 0x0000000000000100 - -/* SH_PI_FSB_ERROR_INJECTION_IP1_PE_TO_FSB */ -/* Description: Inject an IP[1]# Parity Error onto the FSB */ -#define SH_PI_FSB_ERROR_INJECTION_IP1_PE_TO_FSB_SHFT 9 -#define SH_PI_FSB_ERROR_INJECTION_IP1_PE_TO_FSB_MASK 0x0000000000000200 - -/* SH_PI_FSB_ERROR_INJECTION_RP_PE_FROM_FSB */ -/* Description: Inject a RP# Parity Error When Sampling the FSB */ -#define SH_PI_FSB_ERROR_INJECTION_RP_PE_FROM_FSB_SHFT 16 -#define SH_PI_FSB_ERROR_INJECTION_RP_PE_FROM_FSB_MASK 0x0000000000010000 - -/* SH_PI_FSB_ERROR_INJECTION_AP0_PE_FROM_FSB */ -/* Description: Inject an AP[0]# Parity Error When Sampling the FSB */ -#define SH_PI_FSB_ERROR_INJECTION_AP0_PE_FROM_FSB_SHFT 17 -#define SH_PI_FSB_ERROR_INJECTION_AP0_PE_FROM_FSB_MASK 0x0000000000020000 - -/* SH_PI_FSB_ERROR_INJECTION_AP1_PE_FROM_FSB */ -/* Description: Inject an AP[1]# Parity Error When Sampling the FSB */ -#define SH_PI_FSB_ERROR_INJECTION_AP1_PE_FROM_FSB_SHFT 18 -#define SH_PI_FSB_ERROR_INJECTION_AP1_PE_FROM_FSB_MASK 0x0000000000040000 - -/* SH_PI_FSB_ERROR_INJECTION_RSP_PE_FROM_FSB */ -/* Description: Inject a RSP# Parity Error When Sampling the FSB */ -#define SH_PI_FSB_ERROR_INJECTION_RSP_PE_FROM_FSB_SHFT 19 -#define SH_PI_FSB_ERROR_INJECTION_RSP_PE_FROM_FSB_MASK 0x0000000000080000 - -/* SH_PI_FSB_ERROR_INJECTION_DW0_CE_FROM_FSB */ -/* Description: Inject a Correctable Error in Doubleword 0 of SIC D */ -/* ata Packet 0 */ -#define SH_PI_FSB_ERROR_INJECTION_DW0_CE_FROM_FSB_SHFT 20 -#define SH_PI_FSB_ERROR_INJECTION_DW0_CE_FROM_FSB_MASK 0x0000000000100000 - -/* SH_PI_FSB_ERROR_INJECTION_DW0_UCE_FROM_FSB */ -/* Description: Inject a Uncorrectable Error in Doubleword 0 of SIC */ -/* Data Packet 0 */ -#define SH_PI_FSB_ERROR_INJECTION_DW0_UCE_FROM_FSB_SHFT 21 -#define SH_PI_FSB_ERROR_INJECTION_DW0_UCE_FROM_FSB_MASK 0x0000000000200000 - -/* SH_PI_FSB_ERROR_INJECTION_DW1_CE_FROM_FSB */ -/* Description: Inject a Correctable Error in Doubleword 0 of SIC D */ -/* ata Packet 0 */ -#define SH_PI_FSB_ERROR_INJECTION_DW1_CE_FROM_FSB_SHFT 22 -#define SH_PI_FSB_ERROR_INJECTION_DW1_CE_FROM_FSB_MASK 0x0000000000400000 - -/* SH_PI_FSB_ERROR_INJECTION_DW1_UCE_FROM_FSB */ -/* Description: Inject a Uncorrectable Error in Doubleword 0 of SIC */ -/* Data Packet 0 */ -#define SH_PI_FSB_ERROR_INJECTION_DW1_UCE_FROM_FSB_SHFT 23 -#define SH_PI_FSB_ERROR_INJECTION_DW1_UCE_FROM_FSB_MASK 0x0000000000800000 - -/* SH_PI_FSB_ERROR_INJECTION_DW2_CE_FROM_FSB */ -/* Description: Inject a Correctable Error in Doubleword 0 of SIC D */ -/* ata Packet 0 */ -#define SH_PI_FSB_ERROR_INJECTION_DW2_CE_FROM_FSB_SHFT 24 -#define SH_PI_FSB_ERROR_INJECTION_DW2_CE_FROM_FSB_MASK 0x0000000001000000 - -/* SH_PI_FSB_ERROR_INJECTION_DW2_UCE_FROM_FSB */ -/* Description: Inject a Uncorrectable Error in Doubleword 0 of SIC */ -/* Data Packet 0 */ -#define SH_PI_FSB_ERROR_INJECTION_DW2_UCE_FROM_FSB_SHFT 25 -#define SH_PI_FSB_ERROR_INJECTION_DW2_UCE_FROM_FSB_MASK 0x0000000002000000 - -/* SH_PI_FSB_ERROR_INJECTION_DW3_CE_FROM_FSB */ -/* Description: Inject a Correctable Error in Doubleword 0 of SIC D */ -/* ata Packet 0 */ -#define SH_PI_FSB_ERROR_INJECTION_DW3_CE_FROM_FSB_SHFT 26 -#define SH_PI_FSB_ERROR_INJECTION_DW3_CE_FROM_FSB_MASK 0x0000000004000000 - -/* SH_PI_FSB_ERROR_INJECTION_DW3_UCE_FROM_FSB */ -/* Description: Inject a Uncorrectable Error in Doubleword 0 of SIC */ -/* Data Packet 0 */ -#define SH_PI_FSB_ERROR_INJECTION_DW3_UCE_FROM_FSB_SHFT 27 -#define SH_PI_FSB_ERROR_INJECTION_DW3_UCE_FROM_FSB_MASK 0x0000000008000000 - -/* SH_PI_FSB_ERROR_INJECTION_IOQ_OVERRUN */ -/* Description: Inject an ioq overrun Error on the FSB */ -#define SH_PI_FSB_ERROR_INJECTION_IOQ_OVERRUN_SHFT 32 -#define SH_PI_FSB_ERROR_INJECTION_IOQ_OVERRUN_MASK 0x0000000100000000 - -/* SH_PI_FSB_ERROR_INJECTION_LIVELOCK */ -/* Description: Inject a livelock Error on the FSB */ -#define SH_PI_FSB_ERROR_INJECTION_LIVELOCK_SHFT 33 -#define SH_PI_FSB_ERROR_INJECTION_LIVELOCK_MASK 0x0000000200000000 - -/* SH_PI_FSB_ERROR_INJECTION_BUS_HANG */ -/* Description: Inject an bus hang on the FSB */ -#define SH_PI_FSB_ERROR_INJECTION_BUS_HANG_SHFT 34 -#define SH_PI_FSB_ERROR_INJECTION_BUS_HANG_MASK 0x0000000400000000 - -/* ==================================================================== */ -/* Register "SH_PI_MD2PI_REPLY_VC_CONFIG" */ -/* MD-to-PI Reply Virtual Channel Configuration */ -/* ==================================================================== */ - -#define SH_PI_MD2PI_REPLY_VC_CONFIG 0x0000000120050d00 -#define SH_PI_MD2PI_REPLY_VC_CONFIG_MASK 0xc000000000003fff -#define SH_PI_MD2PI_REPLY_VC_CONFIG_INIT 0x000000000000088c - -/* SH_PI_MD2PI_REPLY_VC_CONFIG_HDR_DEPTH */ -/* Description: Depth of header Buffer */ -#define SH_PI_MD2PI_REPLY_VC_CONFIG_HDR_DEPTH_SHFT 0 -#define SH_PI_MD2PI_REPLY_VC_CONFIG_HDR_DEPTH_MASK 0x000000000000000f - -/* SH_PI_MD2PI_REPLY_VC_CONFIG_DATA_DEPTH */ -/* Description: Number of data buffers Available */ -#define SH_PI_MD2PI_REPLY_VC_CONFIG_DATA_DEPTH_SHFT 4 -#define SH_PI_MD2PI_REPLY_VC_CONFIG_DATA_DEPTH_MASK 0x00000000000000f0 - -/* SH_PI_MD2PI_REPLY_VC_CONFIG_MAX_CREDITS */ -/* Description: Maximum credits from sender */ -#define SH_PI_MD2PI_REPLY_VC_CONFIG_MAX_CREDITS_SHFT 8 -#define SH_PI_MD2PI_REPLY_VC_CONFIG_MAX_CREDITS_MASK 0x0000000000003f00 - -/* SH_PI_MD2PI_REPLY_VC_CONFIG_FORCE_CREDIT */ -/* Description: Send an extra credit to sender */ -#define SH_PI_MD2PI_REPLY_VC_CONFIG_FORCE_CREDIT_SHFT 62 -#define SH_PI_MD2PI_REPLY_VC_CONFIG_FORCE_CREDIT_MASK 0x4000000000000000 - -/* SH_PI_MD2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS */ -/* Description: Capture credit and status information */ -#define SH_PI_MD2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS_SHFT 63 -#define SH_PI_MD2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_MD2PI_REQUEST_VC_CONFIG" */ -/* MD-to-PI Request Virtual Channel Configuration */ -/* ==================================================================== */ - -#define SH_PI_MD2PI_REQUEST_VC_CONFIG 0x0000000120050d80 -#define SH_PI_MD2PI_REQUEST_VC_CONFIG_MASK 0xc000000000003fff -#define SH_PI_MD2PI_REQUEST_VC_CONFIG_INIT 0x000000000000088c - -/* SH_PI_MD2PI_REQUEST_VC_CONFIG_HDR_DEPTH */ -/* Description: Depth of header Buffer */ -#define SH_PI_MD2PI_REQUEST_VC_CONFIG_HDR_DEPTH_SHFT 0 -#define SH_PI_MD2PI_REQUEST_VC_CONFIG_HDR_DEPTH_MASK 0x000000000000000f - -/* SH_PI_MD2PI_REQUEST_VC_CONFIG_DATA_DEPTH */ -/* Description: Number of data buffers Available */ -#define SH_PI_MD2PI_REQUEST_VC_CONFIG_DATA_DEPTH_SHFT 4 -#define SH_PI_MD2PI_REQUEST_VC_CONFIG_DATA_DEPTH_MASK 0x00000000000000f0 - -/* SH_PI_MD2PI_REQUEST_VC_CONFIG_MAX_CREDITS */ -/* Description: Maximum credits from sender */ -#define SH_PI_MD2PI_REQUEST_VC_CONFIG_MAX_CREDITS_SHFT 8 -#define SH_PI_MD2PI_REQUEST_VC_CONFIG_MAX_CREDITS_MASK 0x0000000000003f00 - -/* SH_PI_MD2PI_REQUEST_VC_CONFIG_FORCE_CREDIT */ -/* Description: Send an extra credit to sender */ -#define SH_PI_MD2PI_REQUEST_VC_CONFIG_FORCE_CREDIT_SHFT 62 -#define SH_PI_MD2PI_REQUEST_VC_CONFIG_FORCE_CREDIT_MASK 0x4000000000000000 - -/* SH_PI_MD2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS */ -/* Description: Capture credit and status information */ -#define SH_PI_MD2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS_SHFT 63 -#define SH_PI_MD2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_QUEUE_ERROR_INJECTION" */ -/* PI Queue Error Injection */ -/* ==================================================================== */ - -#define SH_PI_QUEUE_ERROR_INJECTION 0x0000000120050e00 -#define SH_PI_QUEUE_ERROR_INJECTION_MASK 0x00000000000000ff -#define SH_PI_QUEUE_ERROR_INJECTION_INIT 0x0000000000000000 - -/* SH_PI_QUEUE_ERROR_INJECTION_DAT_DFR_Q */ -#define SH_PI_QUEUE_ERROR_INJECTION_DAT_DFR_Q_SHFT 0 -#define SH_PI_QUEUE_ERROR_INJECTION_DAT_DFR_Q_MASK 0x0000000000000001 - -/* SH_PI_QUEUE_ERROR_INJECTION_DXB_WTL_CMND_Q */ -#define SH_PI_QUEUE_ERROR_INJECTION_DXB_WTL_CMND_Q_SHFT 1 -#define SH_PI_QUEUE_ERROR_INJECTION_DXB_WTL_CMND_Q_MASK 0x0000000000000002 - -/* SH_PI_QUEUE_ERROR_INJECTION_FSB_WTL_CMND_Q */ -#define SH_PI_QUEUE_ERROR_INJECTION_FSB_WTL_CMND_Q_SHFT 2 -#define SH_PI_QUEUE_ERROR_INJECTION_FSB_WTL_CMND_Q_MASK 0x0000000000000004 - -/* SH_PI_QUEUE_ERROR_INJECTION_MDPI_RPY_BFR */ -#define SH_PI_QUEUE_ERROR_INJECTION_MDPI_RPY_BFR_SHFT 3 -#define SH_PI_QUEUE_ERROR_INJECTION_MDPI_RPY_BFR_MASK 0x0000000000000008 - -/* SH_PI_QUEUE_ERROR_INJECTION_PTC_INTR */ -#define SH_PI_QUEUE_ERROR_INJECTION_PTC_INTR_SHFT 4 -#define SH_PI_QUEUE_ERROR_INJECTION_PTC_INTR_MASK 0x0000000000000010 - -/* SH_PI_QUEUE_ERROR_INJECTION_RXL_KILL_Q */ -#define SH_PI_QUEUE_ERROR_INJECTION_RXL_KILL_Q_SHFT 5 -#define SH_PI_QUEUE_ERROR_INJECTION_RXL_KILL_Q_MASK 0x0000000000000020 - -/* SH_PI_QUEUE_ERROR_INJECTION_RXL_RDY_Q */ -#define SH_PI_QUEUE_ERROR_INJECTION_RXL_RDY_Q_SHFT 6 -#define SH_PI_QUEUE_ERROR_INJECTION_RXL_RDY_Q_MASK 0x0000000000000040 - -/* SH_PI_QUEUE_ERROR_INJECTION_XNPI_RPY_BFR */ -#define SH_PI_QUEUE_ERROR_INJECTION_XNPI_RPY_BFR_SHFT 7 -#define SH_PI_QUEUE_ERROR_INJECTION_XNPI_RPY_BFR_MASK 0x0000000000000080 - -/* ==================================================================== */ -/* Register "SH_PI_TEST_POINT_COMPARE" */ -/* PI Test Point Compare */ -/* ==================================================================== */ - -#define SH_PI_TEST_POINT_COMPARE 0x0000000120050e80 -#define SH_PI_TEST_POINT_COMPARE_MASK 0xffffffffffffffff -#define SH_PI_TEST_POINT_COMPARE_INIT 0xffffffff00000000 - -/* SH_PI_TEST_POINT_COMPARE_COMPARE_MASK */ -/* Description: Mask to select test point data for trigger generati */ -#define SH_PI_TEST_POINT_COMPARE_COMPARE_MASK_SHFT 0 -#define SH_PI_TEST_POINT_COMPARE_COMPARE_MASK_MASK 0x00000000ffffffff - -/* SH_PI_TEST_POINT_COMPARE_COMPARE_PATTERN */ -/* Description: Pattern of test point data to cause trigger */ -#define SH_PI_TEST_POINT_COMPARE_COMPARE_PATTERN_SHFT 32 -#define SH_PI_TEST_POINT_COMPARE_COMPARE_PATTERN_MASK 0xffffffff00000000 - -/* ==================================================================== */ -/* Register "SH_PI_TEST_POINT_SELECT" */ -/* PI Test Point Select */ -/* ==================================================================== */ - -#define SH_PI_TEST_POINT_SELECT 0x0000000120050f00 -#define SH_PI_TEST_POINT_SELECT_MASK 0xf777777777777777 -#define SH_PI_TEST_POINT_SELECT_INIT 0x0000000000000000 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL */ -/* Description: Nibble 0 data is from Chiplet X */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_SHFT 0 -#define SH_PI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000007 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL */ -/* Description: Nibble X is routed to Nibble 0 */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_SHFT 4 -#define SH_PI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL */ -/* Description: Nibble 1 data is from Chiplet X */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_SHFT 8 -#define SH_PI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000700 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL */ -/* Description: Nibble X is routed to Nibble 1 */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_SHFT 12 -#define SH_PI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL */ -/* Description: Nibble 2 data is from Chiplet X */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_SHFT 16 -#define SH_PI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000070000 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL */ -/* Description: Nibble X is routed to Nibble 2 */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_SHFT 20 -#define SH_PI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL */ -/* Description: Nibble 3 data is from Chiplet X */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_SHFT 24 -#define SH_PI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_MASK 0x0000000007000000 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL */ -/* Description: Nibble X is routed to Nibble 3 */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_SHFT 28 -#define SH_PI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL */ -/* Description: Nibble 4 data is from Chiplet X */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_SHFT 32 -#define SH_PI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_MASK 0x0000000700000000 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL */ -/* Description: Nibble X is routed to Nibble 4 */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_SHFT 36 -#define SH_PI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL */ -/* Description: Nibble 5 data is from Chiplet X */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_SHFT 40 -#define SH_PI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_MASK 0x0000070000000000 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL */ -/* Description: Nibble X is routed to Nibble 5 */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_SHFT 44 -#define SH_PI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL */ -/* Description: Nibble 6 data is from Chiplet X */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_SHFT 48 -#define SH_PI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_MASK 0x0007000000000000 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL */ -/* Description: Nibble X is routed to Nibble 6 */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_SHFT 52 -#define SH_PI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL */ -/* Description: Nibble 7 data is from Chiplet X */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_SHFT 56 -#define SH_PI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_MASK 0x0700000000000000 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL */ -/* Description: Nibble X is routed to Nibble 7 */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_SHFT 60 -#define SH_PI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* SH_PI_TEST_POINT_SELECT_TRIGGER_ENABLE */ -/* Description: Enable trigger on bit 32 of Analyzer data */ -#define SH_PI_TEST_POINT_SELECT_TRIGGER_ENABLE_SHFT 63 -#define SH_PI_TEST_POINT_SELECT_TRIGGER_ENABLE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_TEST_POINT_TRIGGER_SELECT" */ -/* PI Test Point Trigger Select */ -/* ==================================================================== */ - -#define SH_PI_TEST_POINT_TRIGGER_SELECT 0x0000000120050f80 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_MASK 0x7777777777777777 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_INIT 0x0000000000000000 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL */ -/* Description: Nibble 0 Chiplet select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_SHFT 0 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_MASK 0x0000000000000007 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_SHFT 4 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL */ -/* Description: Nibble 1 Chiplet select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_SHFT 8 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_MASK 0x0000000000000700 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_SHFT 12 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL */ -/* Description: Nibble 2 Chiplet select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_SHFT 16 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_MASK 0x0000000000070000 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_SHFT 20 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL */ -/* Description: Nibble 3 Chiplet select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_SHFT 24 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_MASK 0x0000000007000000 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_SHFT 28 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL */ -/* Description: Nibble 4 Chiplet select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_SHFT 32 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_MASK 0x0000000700000000 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_SHFT 36 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL */ -/* Description: Nibble 5 Chiplet select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_SHFT 40 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_MASK 0x0000070000000000 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_SHFT 44 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL */ -/* Description: Nibble 6 Chiplet select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_SHFT 48 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_MASK 0x0007000000000000 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_SHFT 52 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL */ -/* Description: Nibble 7 Chiplet select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_SHFT 56 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_MASK 0x0700000000000000 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_SHFT 60 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_XN2PI_REPLY_VC_CONFIG" */ -/* XN-to-PI Reply Virtual Channel Configuration */ -/* ==================================================================== */ - -#define SH_PI_XN2PI_REPLY_VC_CONFIG 0x0000000120051000 -#define SH_PI_XN2PI_REPLY_VC_CONFIG_MASK 0xc000000000003fff -#define SH_PI_XN2PI_REPLY_VC_CONFIG_INIT 0x000000000000068c - -/* SH_PI_XN2PI_REPLY_VC_CONFIG_HDR_DEPTH */ -/* Description: Depth of header Buffer */ -#define SH_PI_XN2PI_REPLY_VC_CONFIG_HDR_DEPTH_SHFT 0 -#define SH_PI_XN2PI_REPLY_VC_CONFIG_HDR_DEPTH_MASK 0x000000000000000f - -/* SH_PI_XN2PI_REPLY_VC_CONFIG_DATA_DEPTH */ -/* Description: Number of data buffers Available */ -#define SH_PI_XN2PI_REPLY_VC_CONFIG_DATA_DEPTH_SHFT 4 -#define SH_PI_XN2PI_REPLY_VC_CONFIG_DATA_DEPTH_MASK 0x00000000000000f0 - -/* SH_PI_XN2PI_REPLY_VC_CONFIG_MAX_CREDITS */ -/* Description: Maximum credits from sender */ -#define SH_PI_XN2PI_REPLY_VC_CONFIG_MAX_CREDITS_SHFT 8 -#define SH_PI_XN2PI_REPLY_VC_CONFIG_MAX_CREDITS_MASK 0x0000000000003f00 - -/* SH_PI_XN2PI_REPLY_VC_CONFIG_FORCE_CREDIT */ -/* Description: Send an extra credit to sender */ -#define SH_PI_XN2PI_REPLY_VC_CONFIG_FORCE_CREDIT_SHFT 62 -#define SH_PI_XN2PI_REPLY_VC_CONFIG_FORCE_CREDIT_MASK 0x4000000000000000 - -/* SH_PI_XN2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS */ -/* Description: Capture credit and status information */ -#define SH_PI_XN2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS_SHFT 63 -#define SH_PI_XN2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_XN2PI_REQUEST_VC_CONFIG" */ -/* XN-to-PI Request Virtual Channel Configuration */ -/* ==================================================================== */ - -#define SH_PI_XN2PI_REQUEST_VC_CONFIG 0x0000000120051080 -#define SH_PI_XN2PI_REQUEST_VC_CONFIG_MASK 0xc000000000003fff -#define SH_PI_XN2PI_REQUEST_VC_CONFIG_INIT 0x000000000000068c - -/* SH_PI_XN2PI_REQUEST_VC_CONFIG_HDR_DEPTH */ -/* Description: Depth of header Buffer */ -#define SH_PI_XN2PI_REQUEST_VC_CONFIG_HDR_DEPTH_SHFT 0 -#define SH_PI_XN2PI_REQUEST_VC_CONFIG_HDR_DEPTH_MASK 0x000000000000000f - -/* SH_PI_XN2PI_REQUEST_VC_CONFIG_DATA_DEPTH */ -/* Description: Number of data buffers Available */ -#define SH_PI_XN2PI_REQUEST_VC_CONFIG_DATA_DEPTH_SHFT 4 -#define SH_PI_XN2PI_REQUEST_VC_CONFIG_DATA_DEPTH_MASK 0x00000000000000f0 - -/* SH_PI_XN2PI_REQUEST_VC_CONFIG_MAX_CREDITS */ -/* Description: Maximum credits from sender */ -#define SH_PI_XN2PI_REQUEST_VC_CONFIG_MAX_CREDITS_SHFT 8 -#define SH_PI_XN2PI_REQUEST_VC_CONFIG_MAX_CREDITS_MASK 0x0000000000003f00 - -/* SH_PI_XN2PI_REQUEST_VC_CONFIG_FORCE_CREDIT */ -/* Description: Send an extra credit to sender */ -#define SH_PI_XN2PI_REQUEST_VC_CONFIG_FORCE_CREDIT_SHFT 62 -#define SH_PI_XN2PI_REQUEST_VC_CONFIG_FORCE_CREDIT_MASK 0x4000000000000000 - -/* SH_PI_XN2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS */ -/* Description: Capture credit and status information */ -#define SH_PI_XN2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS_SHFT 63 -#define SH_PI_XN2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_AEC_STATUS" */ -/* PI Adaptive Error Correction Status */ -/* ==================================================================== */ - -#define SH_PI_AEC_STATUS 0x0000000120060000 -#define SH_PI_AEC_STATUS_MASK 0x0000000000000007 -#define SH_PI_AEC_STATUS_INIT 0x0000000000000000 - -/* SH_PI_AEC_STATUS_STATE */ -/* Description: AEC State */ -#define SH_PI_AEC_STATUS_STATE_SHFT 0 -#define SH_PI_AEC_STATUS_STATE_MASK 0x0000000000000007 - -/* ==================================================================== */ -/* Register "SH_PI_AFI_FIRST_ERROR" */ -/* PI AFI First Error */ -/* ==================================================================== */ - -#define SH_PI_AFI_FIRST_ERROR 0x0000000120060080 -#define SH_PI_AFI_FIRST_ERROR_MASK 0x00000007ffe00180 -#define SH_PI_AFI_FIRST_ERROR_INIT 0x0000000000000000 - -/* SH_PI_AFI_FIRST_ERROR_FSB_SHUB_UCE */ -/* Description: An un-correctable ECC error was detected */ -#define SH_PI_AFI_FIRST_ERROR_FSB_SHUB_UCE_SHFT 7 -#define SH_PI_AFI_FIRST_ERROR_FSB_SHUB_UCE_MASK 0x0000000000000080 - -/* SH_PI_AFI_FIRST_ERROR_FSB_SHUB_CE */ -/* Description: A correctable ECC error was detected */ -#define SH_PI_AFI_FIRST_ERROR_FSB_SHUB_CE_SHFT 8 -#define SH_PI_AFI_FIRST_ERROR_FSB_SHUB_CE_MASK 0x0000000000000100 - -/* SH_PI_AFI_FIRST_ERROR_HUNG_BUS */ -/* Description: FSB is hung */ -#define SH_PI_AFI_FIRST_ERROR_HUNG_BUS_SHFT 21 -#define SH_PI_AFI_FIRST_ERROR_HUNG_BUS_MASK 0x0000000000200000 - -/* SH_PI_AFI_FIRST_ERROR_RSP_PARITY */ -/* Description: Parity error detecte during response phase */ -#define SH_PI_AFI_FIRST_ERROR_RSP_PARITY_SHFT 22 -#define SH_PI_AFI_FIRST_ERROR_RSP_PARITY_MASK 0x0000000000400000 - -/* SH_PI_AFI_FIRST_ERROR_IOQ_OVERRUN */ -/* Description: Over run error detected on IOQ */ -#define SH_PI_AFI_FIRST_ERROR_IOQ_OVERRUN_SHFT 23 -#define SH_PI_AFI_FIRST_ERROR_IOQ_OVERRUN_MASK 0x0000000000800000 - -/* SH_PI_AFI_FIRST_ERROR_REQ_FORMAT */ -/* Description: FSB request format not supported */ -#define SH_PI_AFI_FIRST_ERROR_REQ_FORMAT_SHFT 24 -#define SH_PI_AFI_FIRST_ERROR_REQ_FORMAT_MASK 0x0000000001000000 - -/* SH_PI_AFI_FIRST_ERROR_ADDR_ACCESS */ -/* Description: Access to Address is not supported */ -#define SH_PI_AFI_FIRST_ERROR_ADDR_ACCESS_SHFT 25 -#define SH_PI_AFI_FIRST_ERROR_ADDR_ACCESS_MASK 0x0000000002000000 - -/* SH_PI_AFI_FIRST_ERROR_REQ_PARITY */ -/* Description: Parity error detected during request phase */ -#define SH_PI_AFI_FIRST_ERROR_REQ_PARITY_SHFT 26 -#define SH_PI_AFI_FIRST_ERROR_REQ_PARITY_MASK 0x0000000004000000 - -/* SH_PI_AFI_FIRST_ERROR_ADDR_PARITY */ -/* Description: Parity error detected on address */ -#define SH_PI_AFI_FIRST_ERROR_ADDR_PARITY_SHFT 27 -#define SH_PI_AFI_FIRST_ERROR_ADDR_PARITY_MASK 0x0000000008000000 - -/* SH_PI_AFI_FIRST_ERROR_SHUB_FSB_DQE */ -/* Description: SHUB_FSB_DQE */ -#define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_DQE_SHFT 28 -#define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_DQE_MASK 0x0000000010000000 - -/* SH_PI_AFI_FIRST_ERROR_SHUB_FSB_UCE */ -/* Description: An un-correctable ECC error was detected */ -#define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_UCE_SHFT 29 -#define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_UCE_MASK 0x0000000020000000 - -/* SH_PI_AFI_FIRST_ERROR_SHUB_FSB_CE */ -/* Description: An correctable ECC error was detected */ -#define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_CE_SHFT 30 -#define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_CE_MASK 0x0000000040000000 - -/* SH_PI_AFI_FIRST_ERROR_LIVELOCK */ -/* Description: AFI livelock error was detected */ -#define SH_PI_AFI_FIRST_ERROR_LIVELOCK_SHFT 31 -#define SH_PI_AFI_FIRST_ERROR_LIVELOCK_MASK 0x0000000080000000 - -/* SH_PI_AFI_FIRST_ERROR_BAD_SNOOP */ -/* Description: AFI bad snoop error was detected */ -#define SH_PI_AFI_FIRST_ERROR_BAD_SNOOP_SHFT 32 -#define SH_PI_AFI_FIRST_ERROR_BAD_SNOOP_MASK 0x0000000100000000 - -/* SH_PI_AFI_FIRST_ERROR_FSB_TBL_MISS */ -/* Description: AFI FSB request table miss error was detected */ -#define SH_PI_AFI_FIRST_ERROR_FSB_TBL_MISS_SHFT 33 -#define SH_PI_AFI_FIRST_ERROR_FSB_TBL_MISS_MASK 0x0000000200000000 - -/* SH_PI_AFI_FIRST_ERROR_MSG_LEN */ -/* Description: Runt or Obese message received from SIC */ -#define SH_PI_AFI_FIRST_ERROR_MSG_LEN_SHFT 34 -#define SH_PI_AFI_FIRST_ERROR_MSG_LEN_MASK 0x0000000400000000 - -/* ==================================================================== */ -/* Register "SH_PI_CAM_ADDRESS_READ_DATA" */ -/* CRB CAM MMR Address Read Data */ -/* ==================================================================== */ - -#define SH_PI_CAM_ADDRESS_READ_DATA 0x0000000120060100 -#define SH_PI_CAM_ADDRESS_READ_DATA_MASK 0x8000ffffffffffff -#define SH_PI_CAM_ADDRESS_READ_DATA_INIT 0x0000000000000000 - -/* SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR */ -/* Description: CRB CAM Address Read Data. */ -#define SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR_SHFT 0 -#define SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR_MASK 0x0000ffffffffffff - -/* SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR_VAL */ -/* Description: CRB CAM Address Read Data Valid. */ -#define SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR_VAL_SHFT 63 -#define SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR_VAL_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_CAM_LPRA_READ_DATA" */ -/* CRB CAM MMR LPRA Read Data */ -/* ==================================================================== */ - -#define SH_PI_CAM_LPRA_READ_DATA 0x0000000120060180 -#define SH_PI_CAM_LPRA_READ_DATA_MASK 0xffffffffffffffff -#define SH_PI_CAM_LPRA_READ_DATA_INIT 0x0000000000000000 - -/* SH_PI_CAM_LPRA_READ_DATA_CAM_LPRA */ -/* Description: CRB CAM LPRA read data. */ -#define SH_PI_CAM_LPRA_READ_DATA_CAM_LPRA_SHFT 0 -#define SH_PI_CAM_LPRA_READ_DATA_CAM_LPRA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_PI_CAM_STATE_READ_DATA" */ -/* CRB CAM MMR State Read Data */ -/* ==================================================================== */ - -#define SH_PI_CAM_STATE_READ_DATA 0x0000000120060200 -#define SH_PI_CAM_STATE_READ_DATA_MASK 0x8003ffff0000003f -#define SH_PI_CAM_STATE_READ_DATA_INIT 0x0000000000000000 - -/* SH_PI_CAM_STATE_READ_DATA_CAM_STATE */ -/* Description: CRB CAM State read data. */ -#define SH_PI_CAM_STATE_READ_DATA_CAM_STATE_SHFT 0 -#define SH_PI_CAM_STATE_READ_DATA_CAM_STATE_MASK 0x000000000000000f - -/* SH_PI_CAM_STATE_READ_DATA_CAM_TO */ -/* Description: CRB CAM Time-out Status. */ -#define SH_PI_CAM_STATE_READ_DATA_CAM_TO_SHFT 4 -#define SH_PI_CAM_STATE_READ_DATA_CAM_TO_MASK 0x0000000000000010 - -/* SH_PI_CAM_STATE_READ_DATA_CAM_STATE_RD_PEND */ -/* Description: CRB CAM State Read Pending. */ -#define SH_PI_CAM_STATE_READ_DATA_CAM_STATE_RD_PEND_SHFT 5 -#define SH_PI_CAM_STATE_READ_DATA_CAM_STATE_RD_PEND_MASK 0x0000000000000020 - -/* SH_PI_CAM_STATE_READ_DATA_CAM_LPRA */ -/* Description: CRB LPRA Overflow Data. */ -#define SH_PI_CAM_STATE_READ_DATA_CAM_LPRA_SHFT 32 -#define SH_PI_CAM_STATE_READ_DATA_CAM_LPRA_MASK 0x0003ffff00000000 - -/* SH_PI_CAM_STATE_READ_DATA_CAM_RD_DATA_VAL */ -/* Description: CRB CAM MMR read data is valid. */ -#define SH_PI_CAM_STATE_READ_DATA_CAM_RD_DATA_VAL_SHFT 63 -#define SH_PI_CAM_STATE_READ_DATA_CAM_RD_DATA_VAL_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_CORRECTED_DETAIL_1" */ -/* PI Corrected Error Detail */ -/* ==================================================================== */ - -#define SH_PI_CORRECTED_DETAIL_1 0x0000000120060280 -#define SH_PI_CORRECTED_DETAIL_1_MASK 0xffffffffffffffff -#define SH_PI_CORRECTED_DETAIL_1_INIT 0x0000000000000000 - -/* SH_PI_CORRECTED_DETAIL_1_ADDRESS */ -/* Description: Address of Message that logged Correctable Error */ -#define SH_PI_CORRECTED_DETAIL_1_ADDRESS_SHFT 0 -#define SH_PI_CORRECTED_DETAIL_1_ADDRESS_MASK 0x0000ffffffffffff - -/* SH_PI_CORRECTED_DETAIL_1_SYNDROME */ -/* Description: Syndrome for double word data with Correctable Erro */ -#define SH_PI_CORRECTED_DETAIL_1_SYNDROME_SHFT 48 -#define SH_PI_CORRECTED_DETAIL_1_SYNDROME_MASK 0x00ff000000000000 - -/* SH_PI_CORRECTED_DETAIL_1_DEP */ -/* Description: DEP code for Double word in error */ -#define SH_PI_CORRECTED_DETAIL_1_DEP_SHFT 56 -#define SH_PI_CORRECTED_DETAIL_1_DEP_MASK 0xff00000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_CORRECTED_DETAIL_2" */ -/* PI Corrected Error Detail 2 */ -/* ==================================================================== */ - -#define SH_PI_CORRECTED_DETAIL_2 0x0000000120060300 -#define SH_PI_CORRECTED_DETAIL_2_MASK 0xffffffffffffffff -#define SH_PI_CORRECTED_DETAIL_2_INIT 0x0000000000000000 - -/* SH_PI_CORRECTED_DETAIL_2_DATA */ -/* Description: Double word data in error */ -#define SH_PI_CORRECTED_DETAIL_2_DATA_SHFT 0 -#define SH_PI_CORRECTED_DETAIL_2_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_PI_CORRECTED_DETAIL_3" */ -/* PI Corrected Error Detail 3 */ -/* ==================================================================== */ - -#define SH_PI_CORRECTED_DETAIL_3 0x0000000120060380 -#define SH_PI_CORRECTED_DETAIL_3_MASK 0xffffffffffffffff -#define SH_PI_CORRECTED_DETAIL_3_INIT 0x0000000000000000 - -/* SH_PI_CORRECTED_DETAIL_3_ADDRESS */ -/* Description: Address of Message that logged Correctable Error */ -#define SH_PI_CORRECTED_DETAIL_3_ADDRESS_SHFT 0 -#define SH_PI_CORRECTED_DETAIL_3_ADDRESS_MASK 0x0000ffffffffffff - -/* SH_PI_CORRECTED_DETAIL_3_SYNDROME */ -/* Description: Syndrome for double word data with Correctable Erro */ -#define SH_PI_CORRECTED_DETAIL_3_SYNDROME_SHFT 48 -#define SH_PI_CORRECTED_DETAIL_3_SYNDROME_MASK 0x00ff000000000000 - -/* SH_PI_CORRECTED_DETAIL_3_DEP */ -/* Description: DEP code for Double word in error */ -#define SH_PI_CORRECTED_DETAIL_3_DEP_SHFT 56 -#define SH_PI_CORRECTED_DETAIL_3_DEP_MASK 0xff00000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_CORRECTED_DETAIL_4" */ -/* PI Corrected Error Detail 4 */ -/* ==================================================================== */ - -#define SH_PI_CORRECTED_DETAIL_4 0x0000000120060400 -#define SH_PI_CORRECTED_DETAIL_4_MASK 0xffffffffffffffff -#define SH_PI_CORRECTED_DETAIL_4_INIT 0x0000000000000000 - -/* SH_PI_CORRECTED_DETAIL_4_DATA */ -/* Description: Double word data in error */ -#define SH_PI_CORRECTED_DETAIL_4_DATA_SHFT 0 -#define SH_PI_CORRECTED_DETAIL_4_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_FIRST_ERROR" */ -/* PI CRBP First Error */ -/* ==================================================================== */ - -#define SH_PI_CRBP_FIRST_ERROR 0x0000000120060480 -#define SH_PI_CRBP_FIRST_ERROR_MASK 0x00000000001fffff -#define SH_PI_CRBP_FIRST_ERROR_INIT 0x0000000000000000 - -/* SH_PI_CRBP_FIRST_ERROR_FSB_PROTO_ERR */ -/* Description: CRB's FSB pipe detected protocol table miss */ -#define SH_PI_CRBP_FIRST_ERROR_FSB_PROTO_ERR_SHFT 0 -#define SH_PI_CRBP_FIRST_ERROR_FSB_PROTO_ERR_MASK 0x0000000000000001 - -/* SH_PI_CRBP_FIRST_ERROR_GFX_RP_ERR */ -/* Description: CRB's XB pipe received a GFX error reply */ -#define SH_PI_CRBP_FIRST_ERROR_GFX_RP_ERR_SHFT 1 -#define SH_PI_CRBP_FIRST_ERROR_GFX_RP_ERR_MASK 0x0000000000000002 - -/* SH_PI_CRBP_FIRST_ERROR_XB_PROTO_ERR */ -/* Description: CRB's XB pipe detected protocol table miss */ -#define SH_PI_CRBP_FIRST_ERROR_XB_PROTO_ERR_SHFT 2 -#define SH_PI_CRBP_FIRST_ERROR_XB_PROTO_ERR_MASK 0x0000000000000004 - -/* SH_PI_CRBP_FIRST_ERROR_MEM_RP_ERR */ -/* Description: CRB's XB pipe received a memory error reply message */ -#define SH_PI_CRBP_FIRST_ERROR_MEM_RP_ERR_SHFT 3 -#define SH_PI_CRBP_FIRST_ERROR_MEM_RP_ERR_MASK 0x0000000000000008 - -/* SH_PI_CRBP_FIRST_ERROR_PIO_RP_ERR */ -/* Description: CRB's XB pipe received a PIO error reply message */ -#define SH_PI_CRBP_FIRST_ERROR_PIO_RP_ERR_SHFT 4 -#define SH_PI_CRBP_FIRST_ERROR_PIO_RP_ERR_MASK 0x0000000000000010 - -/* SH_PI_CRBP_FIRST_ERROR_MEM_TO_ERR */ -/* Description: CRB's XB pipe detected a CRB time-out */ -#define SH_PI_CRBP_FIRST_ERROR_MEM_TO_ERR_SHFT 5 -#define SH_PI_CRBP_FIRST_ERROR_MEM_TO_ERR_MASK 0x0000000000000020 - -/* SH_PI_CRBP_FIRST_ERROR_PIO_TO_ERR */ -/* Description: CRB's XB pipe detected a PIO time-out */ -#define SH_PI_CRBP_FIRST_ERROR_PIO_TO_ERR_SHFT 6 -#define SH_PI_CRBP_FIRST_ERROR_PIO_TO_ERR_MASK 0x0000000000000040 - -/* SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_UCE */ -/* Description: An un-correctable ECC error was detected */ -#define SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_UCE_SHFT 7 -#define SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_UCE_MASK 0x0000000000000080 - -/* SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_CE */ -/* Description: A correctable ECC error was detected */ -#define SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_CE_SHFT 8 -#define SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_CE_MASK 0x0000000000000100 - -/* SH_PI_CRBP_FIRST_ERROR_MSG_COLOR_ERR */ -/* Description: Message color was wrong */ -#define SH_PI_CRBP_FIRST_ERROR_MSG_COLOR_ERR_SHFT 9 -#define SH_PI_CRBP_FIRST_ERROR_MSG_COLOR_ERR_MASK 0x0000000000000200 - -/* SH_PI_CRBP_FIRST_ERROR_MD_RQ_Q_OFLOW */ -/* Description: MD Request input buffer over flow error */ -#define SH_PI_CRBP_FIRST_ERROR_MD_RQ_Q_OFLOW_SHFT 10 -#define SH_PI_CRBP_FIRST_ERROR_MD_RQ_Q_OFLOW_MASK 0x0000000000000400 - -/* SH_PI_CRBP_FIRST_ERROR_MD_RP_Q_OFLOW */ -/* Description: MD Reply input buffer over flow error */ -#define SH_PI_CRBP_FIRST_ERROR_MD_RP_Q_OFLOW_SHFT 11 -#define SH_PI_CRBP_FIRST_ERROR_MD_RP_Q_OFLOW_MASK 0x0000000000000800 - -/* SH_PI_CRBP_FIRST_ERROR_XN_RQ_Q_OFLOW */ -/* Description: XN Request input buffer over flow error */ -#define SH_PI_CRBP_FIRST_ERROR_XN_RQ_Q_OFLOW_SHFT 12 -#define SH_PI_CRBP_FIRST_ERROR_XN_RQ_Q_OFLOW_MASK 0x0000000000001000 - -/* SH_PI_CRBP_FIRST_ERROR_XN_RP_Q_OFLOW */ -/* Description: XN Reply input buffer over flow error */ -#define SH_PI_CRBP_FIRST_ERROR_XN_RP_Q_OFLOW_SHFT 13 -#define SH_PI_CRBP_FIRST_ERROR_XN_RP_Q_OFLOW_MASK 0x0000000000002000 - -/* SH_PI_CRBP_FIRST_ERROR_NACK_OFLOW */ -/* Description: NACK over flow error */ -#define SH_PI_CRBP_FIRST_ERROR_NACK_OFLOW_SHFT 14 -#define SH_PI_CRBP_FIRST_ERROR_NACK_OFLOW_MASK 0x0000000000004000 - -/* SH_PI_CRBP_FIRST_ERROR_GFX_INT_0 */ -/* Description: GFX transfer interrupt for CPU 0 */ -#define SH_PI_CRBP_FIRST_ERROR_GFX_INT_0_SHFT 15 -#define SH_PI_CRBP_FIRST_ERROR_GFX_INT_0_MASK 0x0000000000008000 - -/* SH_PI_CRBP_FIRST_ERROR_GFX_INT_1 */ -/* Description: GFX transfer interrupt for CPU 1 */ -#define SH_PI_CRBP_FIRST_ERROR_GFX_INT_1_SHFT 16 -#define SH_PI_CRBP_FIRST_ERROR_GFX_INT_1_MASK 0x0000000000010000 - -/* SH_PI_CRBP_FIRST_ERROR_MD_RQ_CRD_OFLOW */ -/* Description: MD Request Credit Overflow Error */ -#define SH_PI_CRBP_FIRST_ERROR_MD_RQ_CRD_OFLOW_SHFT 17 -#define SH_PI_CRBP_FIRST_ERROR_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000 - -/* SH_PI_CRBP_FIRST_ERROR_MD_RP_CRD_OFLOW */ -/* Description: MD Reply Credit Overflow Error */ -#define SH_PI_CRBP_FIRST_ERROR_MD_RP_CRD_OFLOW_SHFT 18 -#define SH_PI_CRBP_FIRST_ERROR_MD_RP_CRD_OFLOW_MASK 0x0000000000040000 - -/* SH_PI_CRBP_FIRST_ERROR_XN_RQ_CRD_OFLOW */ -/* Description: XN Request Credit Overflow Error */ -#define SH_PI_CRBP_FIRST_ERROR_XN_RQ_CRD_OFLOW_SHFT 19 -#define SH_PI_CRBP_FIRST_ERROR_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000 - -/* SH_PI_CRBP_FIRST_ERROR_XN_RP_CRD_OFLOW */ -/* Description: XN Reply Credit Overflow Error */ -#define SH_PI_CRBP_FIRST_ERROR_XN_RP_CRD_OFLOW_SHFT 20 -#define SH_PI_CRBP_FIRST_ERROR_XN_RP_CRD_OFLOW_MASK 0x0000000000100000 - -/* ==================================================================== */ -/* Register "SH_PI_ERROR_DETAIL_1" */ -/* PI Error Detail 1 */ -/* ==================================================================== */ - -#define SH_PI_ERROR_DETAIL_1 0x0000000120060500 -#define SH_PI_ERROR_DETAIL_1_MASK 0xffffffffffffffff -#define SH_PI_ERROR_DETAIL_1_INIT 0x0000000000000000 - -/* SH_PI_ERROR_DETAIL_1_STATUS */ -/* Description: Error Detail 1 */ -#define SH_PI_ERROR_DETAIL_1_STATUS_SHFT 0 -#define SH_PI_ERROR_DETAIL_1_STATUS_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_PI_ERROR_DETAIL_2" */ -/* PI Error Detail 2 */ -/* ==================================================================== */ - -#define SH_PI_ERROR_DETAIL_2 0x0000000120060580 -#define SH_PI_ERROR_DETAIL_2_MASK 0xffffffffffffffff -#define SH_PI_ERROR_DETAIL_2_INIT 0x0000000000000000 - -/* SH_PI_ERROR_DETAIL_2_STATUS */ -/* Description: Error Status */ -#define SH_PI_ERROR_DETAIL_2_STATUS_SHFT 0 -#define SH_PI_ERROR_DETAIL_2_STATUS_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_PI_ERROR_OVERFLOW" */ -/* PI Error Overflow */ -/* ==================================================================== */ - -#define SH_PI_ERROR_OVERFLOW 0x0000000120060600 -#define SH_PI_ERROR_OVERFLOW_MASK 0x00000007ffffffff -#define SH_PI_ERROR_OVERFLOW_INIT 0x0000000000000000 - -/* SH_PI_ERROR_OVERFLOW_FSB_PROTO_ERR */ -/* Description: CRB's FSB pipe detected protocol table miss */ -#define SH_PI_ERROR_OVERFLOW_FSB_PROTO_ERR_SHFT 0 -#define SH_PI_ERROR_OVERFLOW_FSB_PROTO_ERR_MASK 0x0000000000000001 - -/* SH_PI_ERROR_OVERFLOW_GFX_RP_ERR */ -/* Description: CRB's XB pipe received another GFX reply error mess */ -#define SH_PI_ERROR_OVERFLOW_GFX_RP_ERR_SHFT 1 -#define SH_PI_ERROR_OVERFLOW_GFX_RP_ERR_MASK 0x0000000000000002 - -/* SH_PI_ERROR_OVERFLOW_XB_PROTO_ERR */ -/* Description: CRB's XB pipe detected another protocol table miss */ -#define SH_PI_ERROR_OVERFLOW_XB_PROTO_ERR_SHFT 2 -#define SH_PI_ERROR_OVERFLOW_XB_PROTO_ERR_MASK 0x0000000000000004 - -/* SH_PI_ERROR_OVERFLOW_MEM_RP_ERR */ -/* Description: CRB's XB pipe received another memory reply error m */ -#define SH_PI_ERROR_OVERFLOW_MEM_RP_ERR_SHFT 3 -#define SH_PI_ERROR_OVERFLOW_MEM_RP_ERR_MASK 0x0000000000000008 - -/* SH_PI_ERROR_OVERFLOW_PIO_RP_ERR */ -/* Description: CRB's XB pipe received another PIO reply error mess */ -#define SH_PI_ERROR_OVERFLOW_PIO_RP_ERR_SHFT 4 -#define SH_PI_ERROR_OVERFLOW_PIO_RP_ERR_MASK 0x0000000000000010 - -/* SH_PI_ERROR_OVERFLOW_MEM_TO_ERR */ -/* Description: CRB's XB pipe detected a CRB time-out */ -#define SH_PI_ERROR_OVERFLOW_MEM_TO_ERR_SHFT 5 -#define SH_PI_ERROR_OVERFLOW_MEM_TO_ERR_MASK 0x0000000000000020 - -/* SH_PI_ERROR_OVERFLOW_PIO_TO_ERR */ -/* Description: CRB's XB pipe detected a PIO time-out */ -#define SH_PI_ERROR_OVERFLOW_PIO_TO_ERR_SHFT 6 -#define SH_PI_ERROR_OVERFLOW_PIO_TO_ERR_MASK 0x0000000000000040 - -/* SH_PI_ERROR_OVERFLOW_FSB_SHUB_UCE */ -/* Description: An un-correctable ECC error was detected */ -#define SH_PI_ERROR_OVERFLOW_FSB_SHUB_UCE_SHFT 7 -#define SH_PI_ERROR_OVERFLOW_FSB_SHUB_UCE_MASK 0x0000000000000080 - -/* SH_PI_ERROR_OVERFLOW_FSB_SHUB_CE */ -/* Description: An correctable ECC error was detected */ -#define SH_PI_ERROR_OVERFLOW_FSB_SHUB_CE_SHFT 8 -#define SH_PI_ERROR_OVERFLOW_FSB_SHUB_CE_MASK 0x0000000000000100 - -/* SH_PI_ERROR_OVERFLOW_MSG_COLOR_ERR */ -/* Description: Message color was not correct */ -#define SH_PI_ERROR_OVERFLOW_MSG_COLOR_ERR_SHFT 9 -#define SH_PI_ERROR_OVERFLOW_MSG_COLOR_ERR_MASK 0x0000000000000200 - -/* SH_PI_ERROR_OVERFLOW_MD_RQ_Q_OFLOW */ -/* Description: MD Request input buffer over flow error */ -#define SH_PI_ERROR_OVERFLOW_MD_RQ_Q_OFLOW_SHFT 10 -#define SH_PI_ERROR_OVERFLOW_MD_RQ_Q_OFLOW_MASK 0x0000000000000400 - -/* SH_PI_ERROR_OVERFLOW_MD_RP_Q_OFLOW */ -/* Description: MD Reply input buffer over flow error */ -#define SH_PI_ERROR_OVERFLOW_MD_RP_Q_OFLOW_SHFT 11 -#define SH_PI_ERROR_OVERFLOW_MD_RP_Q_OFLOW_MASK 0x0000000000000800 - -/* SH_PI_ERROR_OVERFLOW_XN_RQ_Q_OFLOW */ -/* Description: XN Request input buffer over flow error */ -#define SH_PI_ERROR_OVERFLOW_XN_RQ_Q_OFLOW_SHFT 12 -#define SH_PI_ERROR_OVERFLOW_XN_RQ_Q_OFLOW_MASK 0x0000000000001000 - -/* SH_PI_ERROR_OVERFLOW_XN_RP_Q_OFLOW */ -/* Description: XN Reply input buffer over flow error */ -#define SH_PI_ERROR_OVERFLOW_XN_RP_Q_OFLOW_SHFT 13 -#define SH_PI_ERROR_OVERFLOW_XN_RP_Q_OFLOW_MASK 0x0000000000002000 - -/* SH_PI_ERROR_OVERFLOW_NACK_OFLOW */ -/* Description: NACK over flow error */ -#define SH_PI_ERROR_OVERFLOW_NACK_OFLOW_SHFT 14 -#define SH_PI_ERROR_OVERFLOW_NACK_OFLOW_MASK 0x0000000000004000 - -/* SH_PI_ERROR_OVERFLOW_GFX_INT_0 */ -/* Description: GFX transfer interrupt for CPU 0 */ -#define SH_PI_ERROR_OVERFLOW_GFX_INT_0_SHFT 15 -#define SH_PI_ERROR_OVERFLOW_GFX_INT_0_MASK 0x0000000000008000 - -/* SH_PI_ERROR_OVERFLOW_GFX_INT_1 */ -/* Description: GFX transfer interrupt for CPU 1 */ -#define SH_PI_ERROR_OVERFLOW_GFX_INT_1_SHFT 16 -#define SH_PI_ERROR_OVERFLOW_GFX_INT_1_MASK 0x0000000000010000 - -/* SH_PI_ERROR_OVERFLOW_MD_RQ_CRD_OFLOW */ -/* Description: MD Request Credit Overflow Error */ -#define SH_PI_ERROR_OVERFLOW_MD_RQ_CRD_OFLOW_SHFT 17 -#define SH_PI_ERROR_OVERFLOW_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000 - -/* SH_PI_ERROR_OVERFLOW_MD_RP_CRD_OFLOW */ -/* Description: MD Reply Credit Overflow Error */ -#define SH_PI_ERROR_OVERFLOW_MD_RP_CRD_OFLOW_SHFT 18 -#define SH_PI_ERROR_OVERFLOW_MD_RP_CRD_OFLOW_MASK 0x0000000000040000 - -/* SH_PI_ERROR_OVERFLOW_XN_RQ_CRD_OFLOW */ -/* Description: XN Request Credit Overflow Error */ -#define SH_PI_ERROR_OVERFLOW_XN_RQ_CRD_OFLOW_SHFT 19 -#define SH_PI_ERROR_OVERFLOW_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000 - -/* SH_PI_ERROR_OVERFLOW_XN_RP_CRD_OFLOW */ -/* Description: XN Reply Credit Overflow Error */ -#define SH_PI_ERROR_OVERFLOW_XN_RP_CRD_OFLOW_SHFT 20 -#define SH_PI_ERROR_OVERFLOW_XN_RP_CRD_OFLOW_MASK 0x0000000000100000 - -/* SH_PI_ERROR_OVERFLOW_HUNG_BUS */ -/* Description: FSB is hung */ -#define SH_PI_ERROR_OVERFLOW_HUNG_BUS_SHFT 21 -#define SH_PI_ERROR_OVERFLOW_HUNG_BUS_MASK 0x0000000000200000 - -/* SH_PI_ERROR_OVERFLOW_RSP_PARITY */ -/* Description: Parity error detecte during response phase */ -#define SH_PI_ERROR_OVERFLOW_RSP_PARITY_SHFT 22 -#define SH_PI_ERROR_OVERFLOW_RSP_PARITY_MASK 0x0000000000400000 - -/* SH_PI_ERROR_OVERFLOW_IOQ_OVERRUN */ -/* Description: Over run error detected on IOQ */ -#define SH_PI_ERROR_OVERFLOW_IOQ_OVERRUN_SHFT 23 -#define SH_PI_ERROR_OVERFLOW_IOQ_OVERRUN_MASK 0x0000000000800000 - -/* SH_PI_ERROR_OVERFLOW_REQ_FORMAT */ -/* Description: FSB request format not supported */ -#define SH_PI_ERROR_OVERFLOW_REQ_FORMAT_SHFT 24 -#define SH_PI_ERROR_OVERFLOW_REQ_FORMAT_MASK 0x0000000001000000 - -/* SH_PI_ERROR_OVERFLOW_ADDR_ACCESS */ -/* Description: Access to Address is not supported */ -#define SH_PI_ERROR_OVERFLOW_ADDR_ACCESS_SHFT 25 -#define SH_PI_ERROR_OVERFLOW_ADDR_ACCESS_MASK 0x0000000002000000 - -/* SH_PI_ERROR_OVERFLOW_REQ_PARITY */ -/* Description: Parity error detected during request phase */ -#define SH_PI_ERROR_OVERFLOW_REQ_PARITY_SHFT 26 -#define SH_PI_ERROR_OVERFLOW_REQ_PARITY_MASK 0x0000000004000000 - -/* SH_PI_ERROR_OVERFLOW_ADDR_PARITY */ -/* Description: Parity error detected on address */ -#define SH_PI_ERROR_OVERFLOW_ADDR_PARITY_SHFT 27 -#define SH_PI_ERROR_OVERFLOW_ADDR_PARITY_MASK 0x0000000008000000 - -/* SH_PI_ERROR_OVERFLOW_SHUB_FSB_DQE */ -/* Description: SHUB_FSB_DQE */ -#define SH_PI_ERROR_OVERFLOW_SHUB_FSB_DQE_SHFT 28 -#define SH_PI_ERROR_OVERFLOW_SHUB_FSB_DQE_MASK 0x0000000010000000 - -/* SH_PI_ERROR_OVERFLOW_SHUB_FSB_UCE */ -/* Description: An un-correctable ECC error was detected */ -#define SH_PI_ERROR_OVERFLOW_SHUB_FSB_UCE_SHFT 29 -#define SH_PI_ERROR_OVERFLOW_SHUB_FSB_UCE_MASK 0x0000000020000000 - -/* SH_PI_ERROR_OVERFLOW_SHUB_FSB_CE */ -/* Description: An correctable ECC error was detected */ -#define SH_PI_ERROR_OVERFLOW_SHUB_FSB_CE_SHFT 30 -#define SH_PI_ERROR_OVERFLOW_SHUB_FSB_CE_MASK 0x0000000040000000 - -/* SH_PI_ERROR_OVERFLOW_LIVELOCK */ -/* Description: AFI livelock error was detected */ -#define SH_PI_ERROR_OVERFLOW_LIVELOCK_SHFT 31 -#define SH_PI_ERROR_OVERFLOW_LIVELOCK_MASK 0x0000000080000000 - -/* SH_PI_ERROR_OVERFLOW_BAD_SNOOP */ -/* Description: AFI bad snoop error was detected */ -#define SH_PI_ERROR_OVERFLOW_BAD_SNOOP_SHFT 32 -#define SH_PI_ERROR_OVERFLOW_BAD_SNOOP_MASK 0x0000000100000000 - -/* SH_PI_ERROR_OVERFLOW_FSB_TBL_MISS */ -/* Description: AFI FSB request table miss error was detected */ -#define SH_PI_ERROR_OVERFLOW_FSB_TBL_MISS_SHFT 33 -#define SH_PI_ERROR_OVERFLOW_FSB_TBL_MISS_MASK 0x0000000200000000 - -/* SH_PI_ERROR_OVERFLOW_MSG_LENGTH */ -/* Description: Message length error on received message from SIC */ -#define SH_PI_ERROR_OVERFLOW_MSG_LENGTH_SHFT 34 -#define SH_PI_ERROR_OVERFLOW_MSG_LENGTH_MASK 0x0000000400000000 - -/* ==================================================================== */ -/* Register "SH_PI_ERROR_OVERFLOW_ALIAS" */ -/* PI Error Overflow Alias */ -/* ==================================================================== */ - -#define SH_PI_ERROR_OVERFLOW_ALIAS 0x0000000120060608 - -/* ==================================================================== */ -/* Register "SH_PI_ERROR_SUMMARY" */ -/* PI Error Summary */ -/* ==================================================================== */ - -#define SH_PI_ERROR_SUMMARY 0x0000000120060680 -#define SH_PI_ERROR_SUMMARY_MASK 0x00000007ffffffff -#define SH_PI_ERROR_SUMMARY_INIT 0x0000000000000000 - -/* SH_PI_ERROR_SUMMARY_FSB_PROTO_ERR */ -/* Description: CRB's FSB pipe detected protocol table miss */ -#define SH_PI_ERROR_SUMMARY_FSB_PROTO_ERR_SHFT 0 -#define SH_PI_ERROR_SUMMARY_FSB_PROTO_ERR_MASK 0x0000000000000001 - -/* SH_PI_ERROR_SUMMARY_GFX_RP_ERR */ -/* Description: Graphic reply error message received */ -#define SH_PI_ERROR_SUMMARY_GFX_RP_ERR_SHFT 1 -#define SH_PI_ERROR_SUMMARY_GFX_RP_ERR_MASK 0x0000000000000002 - -/* SH_PI_ERROR_SUMMARY_XB_PROTO_ERR */ -/* Description: CRB's XB pipe detected protocol table miss */ -#define SH_PI_ERROR_SUMMARY_XB_PROTO_ERR_SHFT 2 -#define SH_PI_ERROR_SUMMARY_XB_PROTO_ERR_MASK 0x0000000000000004 - -/* SH_PI_ERROR_SUMMARY_MEM_RP_ERR */ -/* Description: Memory reply error message received */ -#define SH_PI_ERROR_SUMMARY_MEM_RP_ERR_SHFT 3 -#define SH_PI_ERROR_SUMMARY_MEM_RP_ERR_MASK 0x0000000000000008 - -/* SH_PI_ERROR_SUMMARY_PIO_RP_ERR */ -/* Description: PIO error reply message received */ -#define SH_PI_ERROR_SUMMARY_PIO_RP_ERR_SHFT 4 -#define SH_PI_ERROR_SUMMARY_PIO_RP_ERR_MASK 0x0000000000000010 - -/* SH_PI_ERROR_SUMMARY_MEM_TO_ERR */ -/* Description: CRB's XB pipe detected a CRB time-out */ -#define SH_PI_ERROR_SUMMARY_MEM_TO_ERR_SHFT 5 -#define SH_PI_ERROR_SUMMARY_MEM_TO_ERR_MASK 0x0000000000000020 - -/* SH_PI_ERROR_SUMMARY_PIO_TO_ERR */ -/* Description: CRB's XB pipe detected a PIO time-out */ -#define SH_PI_ERROR_SUMMARY_PIO_TO_ERR_SHFT 6 -#define SH_PI_ERROR_SUMMARY_PIO_TO_ERR_MASK 0x0000000000000040 - -/* SH_PI_ERROR_SUMMARY_FSB_SHUB_UCE */ -/* Description: An un-correctable ECC error was detected */ -#define SH_PI_ERROR_SUMMARY_FSB_SHUB_UCE_SHFT 7 -#define SH_PI_ERROR_SUMMARY_FSB_SHUB_UCE_MASK 0x0000000000000080 - -/* SH_PI_ERROR_SUMMARY_FSB_SHUB_CE */ -/* Description: An correctable ECC error was detected */ -#define SH_PI_ERROR_SUMMARY_FSB_SHUB_CE_SHFT 8 -#define SH_PI_ERROR_SUMMARY_FSB_SHUB_CE_MASK 0x0000000000000100 - -/* SH_PI_ERROR_SUMMARY_MSG_COLOR_ERR */ -/* Description: Message color was wrong */ -#define SH_PI_ERROR_SUMMARY_MSG_COLOR_ERR_SHFT 9 -#define SH_PI_ERROR_SUMMARY_MSG_COLOR_ERR_MASK 0x0000000000000200 - -/* SH_PI_ERROR_SUMMARY_MD_RQ_Q_OFLOW */ -/* Description: MD Request input buffer over flow error */ -#define SH_PI_ERROR_SUMMARY_MD_RQ_Q_OFLOW_SHFT 10 -#define SH_PI_ERROR_SUMMARY_MD_RQ_Q_OFLOW_MASK 0x0000000000000400 - -/* SH_PI_ERROR_SUMMARY_MD_RP_Q_OFLOW */ -/* Description: MD Reply input buffer over flow error */ -#define SH_PI_ERROR_SUMMARY_MD_RP_Q_OFLOW_SHFT 11 -#define SH_PI_ERROR_SUMMARY_MD_RP_Q_OFLOW_MASK 0x0000000000000800 - -/* SH_PI_ERROR_SUMMARY_XN_RQ_Q_OFLOW */ -/* Description: XN Request input buffer over flow error */ -#define SH_PI_ERROR_SUMMARY_XN_RQ_Q_OFLOW_SHFT 12 -#define SH_PI_ERROR_SUMMARY_XN_RQ_Q_OFLOW_MASK 0x0000000000001000 - -/* SH_PI_ERROR_SUMMARY_XN_RP_Q_OFLOW */ -/* Description: XN Reply input buffer over flow error */ -#define SH_PI_ERROR_SUMMARY_XN_RP_Q_OFLOW_SHFT 13 -#define SH_PI_ERROR_SUMMARY_XN_RP_Q_OFLOW_MASK 0x0000000000002000 - -/* SH_PI_ERROR_SUMMARY_NACK_OFLOW */ -/* Description: NACK over flow error */ -#define SH_PI_ERROR_SUMMARY_NACK_OFLOW_SHFT 14 -#define SH_PI_ERROR_SUMMARY_NACK_OFLOW_MASK 0x0000000000004000 - -/* SH_PI_ERROR_SUMMARY_GFX_INT_0 */ -/* Description: GFX transfer interrupt for CPU 0 */ -#define SH_PI_ERROR_SUMMARY_GFX_INT_0_SHFT 15 -#define SH_PI_ERROR_SUMMARY_GFX_INT_0_MASK 0x0000000000008000 - -/* SH_PI_ERROR_SUMMARY_GFX_INT_1 */ -/* Description: GFX transfer interrupt for CPU 1 */ -#define SH_PI_ERROR_SUMMARY_GFX_INT_1_SHFT 16 -#define SH_PI_ERROR_SUMMARY_GFX_INT_1_MASK 0x0000000000010000 - -/* SH_PI_ERROR_SUMMARY_MD_RQ_CRD_OFLOW */ -/* Description: MD Request Credit Overflow Error */ -#define SH_PI_ERROR_SUMMARY_MD_RQ_CRD_OFLOW_SHFT 17 -#define SH_PI_ERROR_SUMMARY_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000 - -/* SH_PI_ERROR_SUMMARY_MD_RP_CRD_OFLOW */ -/* Description: MD Reply Credit Overflow Error */ -#define SH_PI_ERROR_SUMMARY_MD_RP_CRD_OFLOW_SHFT 18 -#define SH_PI_ERROR_SUMMARY_MD_RP_CRD_OFLOW_MASK 0x0000000000040000 - -/* SH_PI_ERROR_SUMMARY_XN_RQ_CRD_OFLOW */ -/* Description: XN Request Credit Overflow Error */ -#define SH_PI_ERROR_SUMMARY_XN_RQ_CRD_OFLOW_SHFT 19 -#define SH_PI_ERROR_SUMMARY_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000 - -/* SH_PI_ERROR_SUMMARY_XN_RP_CRD_OFLOW */ -/* Description: XN Reply Credit Overflow Error */ -#define SH_PI_ERROR_SUMMARY_XN_RP_CRD_OFLOW_SHFT 20 -#define SH_PI_ERROR_SUMMARY_XN_RP_CRD_OFLOW_MASK 0x0000000000100000 - -/* SH_PI_ERROR_SUMMARY_HUNG_BUS */ -/* Description: FSB is hung */ -#define SH_PI_ERROR_SUMMARY_HUNG_BUS_SHFT 21 -#define SH_PI_ERROR_SUMMARY_HUNG_BUS_MASK 0x0000000000200000 - -/* SH_PI_ERROR_SUMMARY_RSP_PARITY */ -/* Description: Parity error detecte during response phase */ -#define SH_PI_ERROR_SUMMARY_RSP_PARITY_SHFT 22 -#define SH_PI_ERROR_SUMMARY_RSP_PARITY_MASK 0x0000000000400000 - -/* SH_PI_ERROR_SUMMARY_IOQ_OVERRUN */ -/* Description: Over run error detected on IOQ */ -#define SH_PI_ERROR_SUMMARY_IOQ_OVERRUN_SHFT 23 -#define SH_PI_ERROR_SUMMARY_IOQ_OVERRUN_MASK 0x0000000000800000 - -/* SH_PI_ERROR_SUMMARY_REQ_FORMAT */ -/* Description: FSB request format not supported */ -#define SH_PI_ERROR_SUMMARY_REQ_FORMAT_SHFT 24 -#define SH_PI_ERROR_SUMMARY_REQ_FORMAT_MASK 0x0000000001000000 - -/* SH_PI_ERROR_SUMMARY_ADDR_ACCESS */ -/* Description: Access to Address is not supported */ -#define SH_PI_ERROR_SUMMARY_ADDR_ACCESS_SHFT 25 -#define SH_PI_ERROR_SUMMARY_ADDR_ACCESS_MASK 0x0000000002000000 - -/* SH_PI_ERROR_SUMMARY_REQ_PARITY */ -/* Description: Parity error detected during request phase */ -#define SH_PI_ERROR_SUMMARY_REQ_PARITY_SHFT 26 -#define SH_PI_ERROR_SUMMARY_REQ_PARITY_MASK 0x0000000004000000 - -/* SH_PI_ERROR_SUMMARY_ADDR_PARITY */ -/* Description: Parity error detected on address */ -#define SH_PI_ERROR_SUMMARY_ADDR_PARITY_SHFT 27 -#define SH_PI_ERROR_SUMMARY_ADDR_PARITY_MASK 0x0000000008000000 - -/* SH_PI_ERROR_SUMMARY_SHUB_FSB_DQE */ -/* Description: SHUB_FSB_DQE error */ -#define SH_PI_ERROR_SUMMARY_SHUB_FSB_DQE_SHFT 28 -#define SH_PI_ERROR_SUMMARY_SHUB_FSB_DQE_MASK 0x0000000010000000 - -/* SH_PI_ERROR_SUMMARY_SHUB_FSB_UCE */ -/* Description: An un-correctable ECC error was detected */ -#define SH_PI_ERROR_SUMMARY_SHUB_FSB_UCE_SHFT 29 -#define SH_PI_ERROR_SUMMARY_SHUB_FSB_UCE_MASK 0x0000000020000000 - -/* SH_PI_ERROR_SUMMARY_SHUB_FSB_CE */ -/* Description: An correctable ECC error was detected */ -#define SH_PI_ERROR_SUMMARY_SHUB_FSB_CE_SHFT 30 -#define SH_PI_ERROR_SUMMARY_SHUB_FSB_CE_MASK 0x0000000040000000 - -/* SH_PI_ERROR_SUMMARY_LIVELOCK */ -/* Description: AFI livelock error was detected */ -#define SH_PI_ERROR_SUMMARY_LIVELOCK_SHFT 31 -#define SH_PI_ERROR_SUMMARY_LIVELOCK_MASK 0x0000000080000000 - -/* SH_PI_ERROR_SUMMARY_BAD_SNOOP */ -/* Description: AFI bad snoop error was detected */ -#define SH_PI_ERROR_SUMMARY_BAD_SNOOP_SHFT 32 -#define SH_PI_ERROR_SUMMARY_BAD_SNOOP_MASK 0x0000000100000000 - -/* SH_PI_ERROR_SUMMARY_FSB_TBL_MISS */ -/* Description: AFI FSB request table miss error was detected */ -#define SH_PI_ERROR_SUMMARY_FSB_TBL_MISS_SHFT 33 -#define SH_PI_ERROR_SUMMARY_FSB_TBL_MISS_MASK 0x0000000200000000 - -/* SH_PI_ERROR_SUMMARY_MSG_LENGTH */ -/* Description: Message length error on received message from SIC */ -#define SH_PI_ERROR_SUMMARY_MSG_LENGTH_SHFT 34 -#define SH_PI_ERROR_SUMMARY_MSG_LENGTH_MASK 0x0000000400000000 - -/* ==================================================================== */ -/* Register "SH_PI_ERROR_SUMMARY_ALIAS" */ -/* PI Error Summary Alias */ -/* ==================================================================== */ - -#define SH_PI_ERROR_SUMMARY_ALIAS 0x0000000120060688 - -/* ==================================================================== */ -/* Register "SH_PI_EXPRESS_REPLY_STATUS" */ -/* PI Express Reply Status */ -/* ==================================================================== */ - -#define SH_PI_EXPRESS_REPLY_STATUS 0x0000000120060700 -#define SH_PI_EXPRESS_REPLY_STATUS_MASK 0x0000000000000007 -#define SH_PI_EXPRESS_REPLY_STATUS_INIT 0x0000000000000000 - -/* SH_PI_EXPRESS_REPLY_STATUS_STATE */ -/* Description: Express Reply State */ -#define SH_PI_EXPRESS_REPLY_STATUS_STATE_SHFT 0 -#define SH_PI_EXPRESS_REPLY_STATUS_STATE_MASK 0x0000000000000007 - -/* ==================================================================== */ -/* Register "SH_PI_FIRST_ERROR" */ -/* PI First Error */ -/* ==================================================================== */ - -#define SH_PI_FIRST_ERROR 0x0000000120060780 -#define SH_PI_FIRST_ERROR_MASK 0x00000007ffffffff -#define SH_PI_FIRST_ERROR_INIT 0x0000000000000000 - -/* SH_PI_FIRST_ERROR_FSB_PROTO_ERR */ -/* Description: CRB's FSB pipe detected protocol table miss */ -#define SH_PI_FIRST_ERROR_FSB_PROTO_ERR_SHFT 0 -#define SH_PI_FIRST_ERROR_FSB_PROTO_ERR_MASK 0x0000000000000001 - -/* SH_PI_FIRST_ERROR_GFX_RP_ERR */ -/* Description: Graphics error reply message received */ -#define SH_PI_FIRST_ERROR_GFX_RP_ERR_SHFT 1 -#define SH_PI_FIRST_ERROR_GFX_RP_ERR_MASK 0x0000000000000002 - -/* SH_PI_FIRST_ERROR_XB_PROTO_ERR */ -/* Description: CRB's XB pipe detected protocol table miss */ -#define SH_PI_FIRST_ERROR_XB_PROTO_ERR_SHFT 2 -#define SH_PI_FIRST_ERROR_XB_PROTO_ERR_MASK 0x0000000000000004 - -/* SH_PI_FIRST_ERROR_MEM_RP_ERR */ -/* Description: Memory reply error message received */ -#define SH_PI_FIRST_ERROR_MEM_RP_ERR_SHFT 3 -#define SH_PI_FIRST_ERROR_MEM_RP_ERR_MASK 0x0000000000000008 - -/* SH_PI_FIRST_ERROR_PIO_RP_ERR */ -/* Description: PIO reply error message received */ -#define SH_PI_FIRST_ERROR_PIO_RP_ERR_SHFT 4 -#define SH_PI_FIRST_ERROR_PIO_RP_ERR_MASK 0x0000000000000010 - -/* SH_PI_FIRST_ERROR_MEM_TO_ERR */ -/* Description: CRB's XB pipe detected a CRB time-out */ -#define SH_PI_FIRST_ERROR_MEM_TO_ERR_SHFT 5 -#define SH_PI_FIRST_ERROR_MEM_TO_ERR_MASK 0x0000000000000020 - -/* SH_PI_FIRST_ERROR_PIO_TO_ERR */ -/* Description: CRB's XB pipe detected a PIO time-out */ -#define SH_PI_FIRST_ERROR_PIO_TO_ERR_SHFT 6 -#define SH_PI_FIRST_ERROR_PIO_TO_ERR_MASK 0x0000000000000040 - -/* SH_PI_FIRST_ERROR_FSB_SHUB_UCE */ -/* Description: An un-correctable ECC error was detected */ -#define SH_PI_FIRST_ERROR_FSB_SHUB_UCE_SHFT 7 -#define SH_PI_FIRST_ERROR_FSB_SHUB_UCE_MASK 0x0000000000000080 - -/* SH_PI_FIRST_ERROR_FSB_SHUB_CE */ -/* Description: A correctable ECC error was detected */ -#define SH_PI_FIRST_ERROR_FSB_SHUB_CE_SHFT 8 -#define SH_PI_FIRST_ERROR_FSB_SHUB_CE_MASK 0x0000000000000100 - -/* SH_PI_FIRST_ERROR_MSG_COLOR_ERR */ -/* Description: Message color was wrong */ -#define SH_PI_FIRST_ERROR_MSG_COLOR_ERR_SHFT 9 -#define SH_PI_FIRST_ERROR_MSG_COLOR_ERR_MASK 0x0000000000000200 - -/* SH_PI_FIRST_ERROR_MD_RQ_Q_OFLOW */ -/* Description: MD Request input buffer over flow error */ -#define SH_PI_FIRST_ERROR_MD_RQ_Q_OFLOW_SHFT 10 -#define SH_PI_FIRST_ERROR_MD_RQ_Q_OFLOW_MASK 0x0000000000000400 - -/* SH_PI_FIRST_ERROR_MD_RP_Q_OFLOW */ -/* Description: MD Reply input buffer over flow error */ -#define SH_PI_FIRST_ERROR_MD_RP_Q_OFLOW_SHFT 11 -#define SH_PI_FIRST_ERROR_MD_RP_Q_OFLOW_MASK 0x0000000000000800 - -/* SH_PI_FIRST_ERROR_XN_RQ_Q_OFLOW */ -/* Description: XN Request input buffer over flow error */ -#define SH_PI_FIRST_ERROR_XN_RQ_Q_OFLOW_SHFT 12 -#define SH_PI_FIRST_ERROR_XN_RQ_Q_OFLOW_MASK 0x0000000000001000 - -/* SH_PI_FIRST_ERROR_XN_RP_Q_OFLOW */ -/* Description: XN Reply input buffer over flow error */ -#define SH_PI_FIRST_ERROR_XN_RP_Q_OFLOW_SHFT 13 -#define SH_PI_FIRST_ERROR_XN_RP_Q_OFLOW_MASK 0x0000000000002000 - -/* SH_PI_FIRST_ERROR_NACK_OFLOW */ -/* Description: NACK over flow error */ -#define SH_PI_FIRST_ERROR_NACK_OFLOW_SHFT 14 -#define SH_PI_FIRST_ERROR_NACK_OFLOW_MASK 0x0000000000004000 - -/* SH_PI_FIRST_ERROR_GFX_INT_0 */ -/* Description: GFX transfer interrupt for CPU 0 */ -#define SH_PI_FIRST_ERROR_GFX_INT_0_SHFT 15 -#define SH_PI_FIRST_ERROR_GFX_INT_0_MASK 0x0000000000008000 - -/* SH_PI_FIRST_ERROR_GFX_INT_1 */ -/* Description: GFX transfer interrupt for CPU 1 */ -#define SH_PI_FIRST_ERROR_GFX_INT_1_SHFT 16 -#define SH_PI_FIRST_ERROR_GFX_INT_1_MASK 0x0000000000010000 - -/* SH_PI_FIRST_ERROR_MD_RQ_CRD_OFLOW */ -/* Description: MD Request Credit Overflow Error */ -#define SH_PI_FIRST_ERROR_MD_RQ_CRD_OFLOW_SHFT 17 -#define SH_PI_FIRST_ERROR_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000 - -/* SH_PI_FIRST_ERROR_MD_RP_CRD_OFLOW */ -/* Description: MD Reply Credit Overflow Error */ -#define SH_PI_FIRST_ERROR_MD_RP_CRD_OFLOW_SHFT 18 -#define SH_PI_FIRST_ERROR_MD_RP_CRD_OFLOW_MASK 0x0000000000040000 - -/* SH_PI_FIRST_ERROR_XN_RQ_CRD_OFLOW */ -/* Description: XN Request Credit Overflow Error */ -#define SH_PI_FIRST_ERROR_XN_RQ_CRD_OFLOW_SHFT 19 -#define SH_PI_FIRST_ERROR_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000 - -/* SH_PI_FIRST_ERROR_XN_RP_CRD_OFLOW */ -/* Description: XN Reply Credit Overflow Error */ -#define SH_PI_FIRST_ERROR_XN_RP_CRD_OFLOW_SHFT 20 -#define SH_PI_FIRST_ERROR_XN_RP_CRD_OFLOW_MASK 0x0000000000100000 - -/* SH_PI_FIRST_ERROR_HUNG_BUS */ -/* Description: FSB is hung */ -#define SH_PI_FIRST_ERROR_HUNG_BUS_SHFT 21 -#define SH_PI_FIRST_ERROR_HUNG_BUS_MASK 0x0000000000200000 - -/* SH_PI_FIRST_ERROR_RSP_PARITY */ -/* Description: Parity error detecte during response phase */ -#define SH_PI_FIRST_ERROR_RSP_PARITY_SHFT 22 -#define SH_PI_FIRST_ERROR_RSP_PARITY_MASK 0x0000000000400000 - -/* SH_PI_FIRST_ERROR_IOQ_OVERRUN */ -/* Description: Over run error detected on IOQ */ -#define SH_PI_FIRST_ERROR_IOQ_OVERRUN_SHFT 23 -#define SH_PI_FIRST_ERROR_IOQ_OVERRUN_MASK 0x0000000000800000 - -/* SH_PI_FIRST_ERROR_REQ_FORMAT */ -/* Description: FSB request format not supported */ -#define SH_PI_FIRST_ERROR_REQ_FORMAT_SHFT 24 -#define SH_PI_FIRST_ERROR_REQ_FORMAT_MASK 0x0000000001000000 - -/* SH_PI_FIRST_ERROR_ADDR_ACCESS */ -/* Description: Access to Address is not supported */ -#define SH_PI_FIRST_ERROR_ADDR_ACCESS_SHFT 25 -#define SH_PI_FIRST_ERROR_ADDR_ACCESS_MASK 0x0000000002000000 - -/* SH_PI_FIRST_ERROR_REQ_PARITY */ -/* Description: Parity error detected during request phase */ -#define SH_PI_FIRST_ERROR_REQ_PARITY_SHFT 26 -#define SH_PI_FIRST_ERROR_REQ_PARITY_MASK 0x0000000004000000 - -/* SH_PI_FIRST_ERROR_ADDR_PARITY */ -/* Description: Parity error detected on address */ -#define SH_PI_FIRST_ERROR_ADDR_PARITY_SHFT 27 -#define SH_PI_FIRST_ERROR_ADDR_PARITY_MASK 0x0000000008000000 - -/* SH_PI_FIRST_ERROR_SHUB_FSB_DQE */ -/* Description: SHUB_FSB_DQE */ -#define SH_PI_FIRST_ERROR_SHUB_FSB_DQE_SHFT 28 -#define SH_PI_FIRST_ERROR_SHUB_FSB_DQE_MASK 0x0000000010000000 - -/* SH_PI_FIRST_ERROR_SHUB_FSB_UCE */ -/* Description: An un-correctable ECC error was detected */ -#define SH_PI_FIRST_ERROR_SHUB_FSB_UCE_SHFT 29 -#define SH_PI_FIRST_ERROR_SHUB_FSB_UCE_MASK 0x0000000020000000 - -/* SH_PI_FIRST_ERROR_SHUB_FSB_CE */ -/* Description: An correctable ECC error was detected */ -#define SH_PI_FIRST_ERROR_SHUB_FSB_CE_SHFT 30 -#define SH_PI_FIRST_ERROR_SHUB_FSB_CE_MASK 0x0000000040000000 - -/* SH_PI_FIRST_ERROR_LIVELOCK */ -/* Description: AFI livelock error was detected */ -#define SH_PI_FIRST_ERROR_LIVELOCK_SHFT 31 -#define SH_PI_FIRST_ERROR_LIVELOCK_MASK 0x0000000080000000 - -/* SH_PI_FIRST_ERROR_BAD_SNOOP */ -/* Description: AFI bad snoop error was detected */ -#define SH_PI_FIRST_ERROR_BAD_SNOOP_SHFT 32 -#define SH_PI_FIRST_ERROR_BAD_SNOOP_MASK 0x0000000100000000 - -/* SH_PI_FIRST_ERROR_FSB_TBL_MISS */ -/* Description: AFI FSB request table miss error was detected */ -#define SH_PI_FIRST_ERROR_FSB_TBL_MISS_SHFT 33 -#define SH_PI_FIRST_ERROR_FSB_TBL_MISS_MASK 0x0000000200000000 - -/* SH_PI_FIRST_ERROR_MSG_LENGTH */ -/* Description: Message length error on received message from SIC */ -#define SH_PI_FIRST_ERROR_MSG_LENGTH_SHFT 34 -#define SH_PI_FIRST_ERROR_MSG_LENGTH_MASK 0x0000000400000000 - -/* ==================================================================== */ -/* Register "SH_PI_FIRST_ERROR_ALIAS" */ -/* PI First Error Alias */ -/* ==================================================================== */ - -#define SH_PI_FIRST_ERROR_ALIAS 0x0000000120060788 - -/* ==================================================================== */ -/* Register "SH_PI_PI2MD_REPLY_VC_STATUS" */ -/* PI-to-MD Reply Virtual Channel Status */ -/* ==================================================================== */ - -#define SH_PI_PI2MD_REPLY_VC_STATUS 0x0000000120060900 -#define SH_PI_PI2MD_REPLY_VC_STATUS_MASK 0x000000000000003f -#define SH_PI_PI2MD_REPLY_VC_STATUS_INIT 0x0000000000000000 - -/* SH_PI_PI2MD_REPLY_VC_STATUS_OUTPUT_CRD_STAT */ -/* Description: Status of output credits */ -#define SH_PI_PI2MD_REPLY_VC_STATUS_OUTPUT_CRD_STAT_SHFT 0 -#define SH_PI_PI2MD_REPLY_VC_STATUS_OUTPUT_CRD_STAT_MASK 0x000000000000003f - -/* ==================================================================== */ -/* Register "SH_PI_PI2MD_REQUEST_VC_STATUS" */ -/* PI-to-MD Request Virtual Channel Status */ -/* ==================================================================== */ - -#define SH_PI_PI2MD_REQUEST_VC_STATUS 0x0000000120060980 -#define SH_PI_PI2MD_REQUEST_VC_STATUS_MASK 0x000000000000003f -#define SH_PI_PI2MD_REQUEST_VC_STATUS_INIT 0x0000000000000000 - -/* SH_PI_PI2MD_REQUEST_VC_STATUS_OUTPUT_CRD_STAT */ -/* Description: Status of output credits */ -#define SH_PI_PI2MD_REQUEST_VC_STATUS_OUTPUT_CRD_STAT_SHFT 0 -#define SH_PI_PI2MD_REQUEST_VC_STATUS_OUTPUT_CRD_STAT_MASK 0x000000000000003f - -/* ==================================================================== */ -/* Register "SH_PI_PI2XN_REPLY_VC_STATUS" */ -/* PI-to-XN Reply Virtual Channel Status */ -/* ==================================================================== */ - -#define SH_PI_PI2XN_REPLY_VC_STATUS 0x0000000120060a00 -#define SH_PI_PI2XN_REPLY_VC_STATUS_MASK 0x000000000000003f -#define SH_PI_PI2XN_REPLY_VC_STATUS_INIT 0x0000000000000000 - -/* SH_PI_PI2XN_REPLY_VC_STATUS_OUTPUT_CRD_STAT */ -/* Description: Status of output credits */ -#define SH_PI_PI2XN_REPLY_VC_STATUS_OUTPUT_CRD_STAT_SHFT 0 -#define SH_PI_PI2XN_REPLY_VC_STATUS_OUTPUT_CRD_STAT_MASK 0x000000000000003f - -/* ==================================================================== */ -/* Register "SH_PI_PI2XN_REQUEST_VC_STATUS" */ -/* PI-to-XN Request Virtual Channel Status */ -/* ==================================================================== */ - -#define SH_PI_PI2XN_REQUEST_VC_STATUS 0x0000000120060a80 -#define SH_PI_PI2XN_REQUEST_VC_STATUS_MASK 0x000000000000003f -#define SH_PI_PI2XN_REQUEST_VC_STATUS_INIT 0x0000000000000000 - -/* SH_PI_PI2XN_REQUEST_VC_STATUS_OUTPUT_CRD_STAT */ -/* Description: Status of output credits */ -#define SH_PI_PI2XN_REQUEST_VC_STATUS_OUTPUT_CRD_STAT_SHFT 0 -#define SH_PI_PI2XN_REQUEST_VC_STATUS_OUTPUT_CRD_STAT_MASK 0x000000000000003f - -/* ==================================================================== */ -/* Register "SH_PI_UNCORRECTED_DETAIL_1" */ -/* PI Uncorrected Error Detail 1 */ -/* ==================================================================== */ - -#define SH_PI_UNCORRECTED_DETAIL_1 0x0000000120060b00 -#define SH_PI_UNCORRECTED_DETAIL_1_MASK 0xffffffffffffffff -#define SH_PI_UNCORRECTED_DETAIL_1_INIT 0x0000000000000000 - -/* SH_PI_UNCORRECTED_DETAIL_1_ADDRESS */ -/* Description: Address of Message that logged Uncorrectable Error */ -#define SH_PI_UNCORRECTED_DETAIL_1_ADDRESS_SHFT 0 -#define SH_PI_UNCORRECTED_DETAIL_1_ADDRESS_MASK 0x0000ffffffffffff - -/* SH_PI_UNCORRECTED_DETAIL_1_SYNDROME */ -/* Description: Syndrome for double word data with Uncorrectable Er */ -#define SH_PI_UNCORRECTED_DETAIL_1_SYNDROME_SHFT 48 -#define SH_PI_UNCORRECTED_DETAIL_1_SYNDROME_MASK 0x00ff000000000000 - -/* SH_PI_UNCORRECTED_DETAIL_1_DEP */ -/* Description: DEP for Double word in error */ -#define SH_PI_UNCORRECTED_DETAIL_1_DEP_SHFT 56 -#define SH_PI_UNCORRECTED_DETAIL_1_DEP_MASK 0xff00000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_UNCORRECTED_DETAIL_2" */ -/* PI Uncorrected Error Detail 2 */ -/* ==================================================================== */ - -#define SH_PI_UNCORRECTED_DETAIL_2 0x0000000120060b80 -#define SH_PI_UNCORRECTED_DETAIL_2_MASK 0xffffffffffffffff -#define SH_PI_UNCORRECTED_DETAIL_2_INIT 0x0000000000000000 - -/* SH_PI_UNCORRECTED_DETAIL_2_DATA */ -/* Description: Double word data in error */ -#define SH_PI_UNCORRECTED_DETAIL_2_DATA_SHFT 0 -#define SH_PI_UNCORRECTED_DETAIL_2_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_PI_UNCORRECTED_DETAIL_3" */ -/* PI Uncorrected Error Detail 3 */ -/* ==================================================================== */ - -#define SH_PI_UNCORRECTED_DETAIL_3 0x0000000120060c00 -#define SH_PI_UNCORRECTED_DETAIL_3_MASK 0xffffffffffffffff -#define SH_PI_UNCORRECTED_DETAIL_3_INIT 0x0000000000000000 - -/* SH_PI_UNCORRECTED_DETAIL_3_ADDRESS */ -/* Description: Address of Message that logged Uncorrectable Error */ -#define SH_PI_UNCORRECTED_DETAIL_3_ADDRESS_SHFT 0 -#define SH_PI_UNCORRECTED_DETAIL_3_ADDRESS_MASK 0x0000ffffffffffff - -/* SH_PI_UNCORRECTED_DETAIL_3_SYNDROME */ -/* Description: Syndrome for double word data with Uncorrectable Er */ -#define SH_PI_UNCORRECTED_DETAIL_3_SYNDROME_SHFT 48 -#define SH_PI_UNCORRECTED_DETAIL_3_SYNDROME_MASK 0x00ff000000000000 - -/* SH_PI_UNCORRECTED_DETAIL_3_DEP */ -/* Description: DCP for Double word in error */ -#define SH_PI_UNCORRECTED_DETAIL_3_DEP_SHFT 56 -#define SH_PI_UNCORRECTED_DETAIL_3_DEP_MASK 0xff00000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_UNCORRECTED_DETAIL_4" */ -/* PI Uncorrected Error Detail 4 */ -/* ==================================================================== */ - -#define SH_PI_UNCORRECTED_DETAIL_4 0x0000000120060c80 -#define SH_PI_UNCORRECTED_DETAIL_4_MASK 0xffffffffffffffff -#define SH_PI_UNCORRECTED_DETAIL_4_INIT 0x0000000000000000 - -/* SH_PI_UNCORRECTED_DETAIL_4_DATA */ -/* Description: Double word data in error */ -#define SH_PI_UNCORRECTED_DETAIL_4_DATA_SHFT 0 -#define SH_PI_UNCORRECTED_DETAIL_4_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_PI_MD2PI_REPLY_VC_STATUS" */ -/* MD-to-PI Reply Virtual Channel Status */ -/* ==================================================================== */ - -#define SH_PI_MD2PI_REPLY_VC_STATUS 0x0000000120060800 -#define SH_PI_MD2PI_REPLY_VC_STATUS_MASK 0x0000000000000fff -#define SH_PI_MD2PI_REPLY_VC_STATUS_INIT 0x0000000000000000 - -/* SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT */ -/* Description: Status of input header credits */ -#define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT_SHFT 0 -#define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT_MASK 0x000000000000000f - -/* SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT */ -/* Description: Status of data credits */ -#define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT_SHFT 4 -#define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT_MASK 0x00000000000000f0 - -/* SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT */ -/* Description: Status of MD Reply Input Queue */ -#define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT_SHFT 8 -#define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT_MASK 0x0000000000000f00 - -/* ==================================================================== */ -/* Register "SH_PI_MD2PI_REQUEST_VC_STATUS" */ -/* MD-to-PI Request Virtual Channel Status */ -/* ==================================================================== */ - -#define SH_PI_MD2PI_REQUEST_VC_STATUS 0x0000000120060880 -#define SH_PI_MD2PI_REQUEST_VC_STATUS_MASK 0x0000000000000fff -#define SH_PI_MD2PI_REQUEST_VC_STATUS_INIT 0x0000000000000000 - -/* SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT */ -/* Description: Status of input header credits */ -#define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT_SHFT 0 -#define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT_MASK 0x000000000000000f - -/* SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT */ -/* Description: Status of input data credits */ -#define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT_SHFT 4 -#define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT_MASK 0x00000000000000f0 - -/* SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT */ -/* Description: Status of MD Request Input Queue */ -#define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT_SHFT 8 -#define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT_MASK 0x0000000000000f00 - -/* ==================================================================== */ -/* Register "SH_PI_XN2PI_REPLY_VC_STATUS" */ -/* XN-to-PI Reply Virtual Channel Status */ -/* ==================================================================== */ - -#define SH_PI_XN2PI_REPLY_VC_STATUS 0x0000000120060d00 -#define SH_PI_XN2PI_REPLY_VC_STATUS_MASK 0x0000000000000fff -#define SH_PI_XN2PI_REPLY_VC_STATUS_INIT 0x0000000000000000 - -/* SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT */ -/* Description: Status of input header credits */ -#define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT_SHFT 0 -#define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT_MASK 0x000000000000000f - -/* SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT */ -/* Description: Status of input data credits */ -#define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT_SHFT 4 -#define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT_MASK 0x00000000000000f0 - -/* SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT */ -/* Description: Status of XN Reply Input Queue */ -#define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT_SHFT 8 -#define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT_MASK 0x0000000000000f00 - -/* ==================================================================== */ -/* Register "SH_PI_XN2PI_REQUEST_VC_STATUS" */ -/* XN-to-PI Request Virtual Channel Status */ -/* ==================================================================== */ - -#define SH_PI_XN2PI_REQUEST_VC_STATUS 0x0000000120060d80 -#define SH_PI_XN2PI_REQUEST_VC_STATUS_MASK 0x0000000000000fff -#define SH_PI_XN2PI_REQUEST_VC_STATUS_INIT 0x0000000000000000 - -/* SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT */ -/* Description: Status of input header credits */ -#define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT_SHFT 0 -#define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT_MASK 0x000000000000000f - -/* SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT */ -/* Description: Status of input data credits */ -#define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT_SHFT 4 -#define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT_MASK 0x00000000000000f0 - -/* SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT */ -/* Description: Status of XN Request Input Queue */ -#define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT_SHFT 8 -#define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT_MASK 0x0000000000000f00 - -/* ==================================================================== */ -/* Register "SH_XNPI_SIC_FLOW" */ -/* ==================================================================== */ - -#define SH_XNPI_SIC_FLOW 0x0000000150030000 -#define SH_XNPI_SIC_FLOW_MASK 0x9f1f1f1f1f1f9f9f -#define SH_XNPI_SIC_FLOW_INIT 0x0000080000080000 - -/* SH_XNPI_SIC_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNPI_SIC_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNPI_SIC_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000001f - -/* SH_XNPI_SIC_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNPI_SIC_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNPI_SIC_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNPI_SIC_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNPI_SIC_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNPI_SIC_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000001f00 - -/* SH_XNPI_SIC_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNPI_SIC_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNPI_SIC_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNPI_SIC_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 credit_test */ -#define SH_XNPI_SIC_FLOW_CREDIT_VC0_TEST_SHFT 16 -#define SH_XNPI_SIC_FLOW_CREDIT_VC0_TEST_MASK 0x00000000001f0000 - -/* SH_XNPI_SIC_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNPI_SIC_FLOW_CREDIT_VC0_DYN_SHFT 24 -#define SH_XNPI_SIC_FLOW_CREDIT_VC0_DYN_MASK 0x000000001f000000 - -/* SH_XNPI_SIC_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNPI_SIC_FLOW_CREDIT_VC0_CAP_SHFT 32 -#define SH_XNPI_SIC_FLOW_CREDIT_VC0_CAP_MASK 0x0000001f00000000 - -/* SH_XNPI_SIC_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 credit_test */ -#define SH_XNPI_SIC_FLOW_CREDIT_VC2_TEST_SHFT 40 -#define SH_XNPI_SIC_FLOW_CREDIT_VC2_TEST_MASK 0x00001f0000000000 - -/* SH_XNPI_SIC_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNPI_SIC_FLOW_CREDIT_VC2_DYN_SHFT 48 -#define SH_XNPI_SIC_FLOW_CREDIT_VC2_DYN_MASK 0x001f000000000000 - -/* SH_XNPI_SIC_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNPI_SIC_FLOW_CREDIT_VC2_CAP_SHFT 56 -#define SH_XNPI_SIC_FLOW_CREDIT_VC2_CAP_MASK 0x1f00000000000000 - -/* SH_XNPI_SIC_FLOW_DISABLE_BYPASS_OUT */ -#define SH_XNPI_SIC_FLOW_DISABLE_BYPASS_OUT_SHFT 63 -#define SH_XNPI_SIC_FLOW_DISABLE_BYPASS_OUT_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_XNPI_TO_NI0_PORT_FLOW" */ -/* ==================================================================== */ - -#define SH_XNPI_TO_NI0_PORT_FLOW 0x0000000150030010 -#define SH_XNPI_TO_NI0_PORT_FLOW_MASK 0x3f3f003f3f00bfbf -#define SH_XNPI_TO_NI0_PORT_FLOW_INIT 0x0000000000000000 - -/* SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24 -#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000 - -/* SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32 -#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000 - -/* SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48 -#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000 - -/* SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56 -#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNPI_TO_NI1_PORT_FLOW" */ -/* ==================================================================== */ - -#define SH_XNPI_TO_NI1_PORT_FLOW 0x0000000150030020 -#define SH_XNPI_TO_NI1_PORT_FLOW_MASK 0x3f3f003f3f00bfbf -#define SH_XNPI_TO_NI1_PORT_FLOW_INIT 0x0000000000000000 - -/* SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24 -#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000 - -/* SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32 -#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000 - -/* SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48 -#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000 - -/* SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56 -#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNPI_TO_IILB_PORT_FLOW" */ -/* ==================================================================== */ - -#define SH_XNPI_TO_IILB_PORT_FLOW 0x0000000150030030 -#define SH_XNPI_TO_IILB_PORT_FLOW_MASK 0x3f3f003f3f00bfbf -#define SH_XNPI_TO_IILB_PORT_FLOW_INIT 0x0000000000000000 - -/* SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24 -#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000 - -/* SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32 -#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000 - -/* SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48 -#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000 - -/* SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56 -#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNPI_FR_NI0_PORT_FLOW_FIFO" */ -/* ==================================================================== */ - -#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO 0x0000000150030040 -#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_MASK 0x00001f1f3f3f3f3f -#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_INIT 0x00000c0c00000000 - -/* SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN */ -/* Description: vc0 fifo entry dynamic value */ -#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0 -#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f - -/* SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP */ -/* Description: vc0 fifo entry captured value */ -#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8 -#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00 - -/* SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN */ -/* Description: vc2 fifo entry dynamic value */ -#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16 -#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000 - -/* SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP */ -/* Description: vc2 fifo entry captured value */ -#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24 -#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000 - -/* SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST */ -/* Description: vc0 test credits limit */ -#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32 -#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000 - -/* SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST */ -/* Description: vc2 test credits limit */ -#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40 -#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNPI_FR_NI1_PORT_FLOW_FIFO" */ -/* ==================================================================== */ - -#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO 0x0000000150030050 -#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_MASK 0x00001f1f3f3f3f3f -#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_INIT 0x00000c0c00000000 - -/* SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN */ -/* Description: vc0 fifo entry dynamic value */ -#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0 -#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f - -/* SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP */ -/* Description: vc0 fifo entry captured value */ -#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8 -#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00 - -/* SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN */ -/* Description: vc2 fifo entry dynamic value */ -#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16 -#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000 - -/* SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP */ -/* Description: vc2 fifo entry captured value */ -#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24 -#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000 - -/* SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST */ -/* Description: vc0 test credits limit */ -#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32 -#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000 - -/* SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST */ -/* Description: vc2 test credits limit */ -#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40 -#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNPI_FR_IILB_PORT_FLOW_FIFO" */ -/* ==================================================================== */ - -#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO 0x0000000150030060 -#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_MASK 0x00001f1f3f3f3f3f -#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_INIT 0x00000c0c00000000 - -/* SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN */ -/* Description: vc0 fifo entry dynamic value */ -#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0 -#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f - -/* SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP */ -/* Description: vc0 fifo entry captured value */ -#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8 -#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00 - -/* SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN */ -/* Description: vc2 fifo entry dynamic value */ -#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16 -#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000 - -/* SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP */ -/* Description: vc2 fifo entry captured value */ -#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24 -#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000 - -/* SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST */ -/* Description: vc0 test credits limit */ -#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32 -#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000 - -/* SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST */ -/* Description: vc2 test credits limit */ -#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40 -#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNMD_SIC_FLOW" */ -/* ==================================================================== */ - -#define SH_XNMD_SIC_FLOW 0x0000000150030100 -#define SH_XNMD_SIC_FLOW_MASK 0x9f1f1f1f1f1f9f9f -#define SH_XNMD_SIC_FLOW_INIT 0x0000090000090000 - -/* SH_XNMD_SIC_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNMD_SIC_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNMD_SIC_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000001f - -/* SH_XNMD_SIC_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNMD_SIC_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNMD_SIC_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNMD_SIC_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNMD_SIC_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNMD_SIC_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000001f00 - -/* SH_XNMD_SIC_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNMD_SIC_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNMD_SIC_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNMD_SIC_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 credit_test */ -#define SH_XNMD_SIC_FLOW_CREDIT_VC0_TEST_SHFT 16 -#define SH_XNMD_SIC_FLOW_CREDIT_VC0_TEST_MASK 0x00000000001f0000 - -/* SH_XNMD_SIC_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNMD_SIC_FLOW_CREDIT_VC0_DYN_SHFT 24 -#define SH_XNMD_SIC_FLOW_CREDIT_VC0_DYN_MASK 0x000000001f000000 - -/* SH_XNMD_SIC_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNMD_SIC_FLOW_CREDIT_VC0_CAP_SHFT 32 -#define SH_XNMD_SIC_FLOW_CREDIT_VC0_CAP_MASK 0x0000001f00000000 - -/* SH_XNMD_SIC_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 credit_test */ -#define SH_XNMD_SIC_FLOW_CREDIT_VC2_TEST_SHFT 40 -#define SH_XNMD_SIC_FLOW_CREDIT_VC2_TEST_MASK 0x00001f0000000000 - -/* SH_XNMD_SIC_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNMD_SIC_FLOW_CREDIT_VC2_DYN_SHFT 48 -#define SH_XNMD_SIC_FLOW_CREDIT_VC2_DYN_MASK 0x001f000000000000 - -/* SH_XNMD_SIC_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNMD_SIC_FLOW_CREDIT_VC2_CAP_SHFT 56 -#define SH_XNMD_SIC_FLOW_CREDIT_VC2_CAP_MASK 0x1f00000000000000 - -/* SH_XNMD_SIC_FLOW_DISABLE_BYPASS_OUT */ -#define SH_XNMD_SIC_FLOW_DISABLE_BYPASS_OUT_SHFT 63 -#define SH_XNMD_SIC_FLOW_DISABLE_BYPASS_OUT_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_XNMD_TO_NI0_PORT_FLOW" */ -/* ==================================================================== */ - -#define SH_XNMD_TO_NI0_PORT_FLOW 0x0000000150030110 -#define SH_XNMD_TO_NI0_PORT_FLOW_MASK 0x3f3f003f3f00bfbf -#define SH_XNMD_TO_NI0_PORT_FLOW_INIT 0x0000000000000000 - -/* SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24 -#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000 - -/* SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32 -#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000 - -/* SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48 -#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000 - -/* SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56 -#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNMD_TO_NI1_PORT_FLOW" */ -/* ==================================================================== */ - -#define SH_XNMD_TO_NI1_PORT_FLOW 0x0000000150030120 -#define SH_XNMD_TO_NI1_PORT_FLOW_MASK 0x3f3f003f3f00bfbf -#define SH_XNMD_TO_NI1_PORT_FLOW_INIT 0x0000000000000000 - -/* SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24 -#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000 - -/* SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32 -#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000 - -/* SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48 -#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000 - -/* SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56 -#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNMD_TO_IILB_PORT_FLOW" */ -/* ==================================================================== */ - -#define SH_XNMD_TO_IILB_PORT_FLOW 0x0000000150030130 -#define SH_XNMD_TO_IILB_PORT_FLOW_MASK 0x3f3f003f3f00bfbf -#define SH_XNMD_TO_IILB_PORT_FLOW_INIT 0x0000000000000000 - -/* SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24 -#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000 - -/* SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32 -#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000 - -/* SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48 -#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000 - -/* SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56 -#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNMD_FR_NI0_PORT_FLOW_FIFO" */ -/* ==================================================================== */ - -#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO 0x0000000150030140 -#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_MASK 0x00001f1f3f3f3f3f -#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_INIT 0x00000c0c00000000 - -/* SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN */ -/* Description: vc0 fifo entry dynamic value */ -#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0 -#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f - -/* SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP */ -/* Description: vc0 fifo entry captured value */ -#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8 -#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00 - -/* SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN */ -/* Description: vc2 fifo entry dynamic value */ -#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16 -#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000 - -/* SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP */ -/* Description: vc2 fifo entry captured value */ -#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24 -#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000 - -/* SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST */ -/* Description: vc0 test credits limit */ -#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32 -#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000 - -/* SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST */ -/* Description: vc2 test credits limit */ -#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40 -#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNMD_FR_NI1_PORT_FLOW_FIFO" */ -/* ==================================================================== */ - -#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO 0x0000000150030150 -#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_MASK 0x00001f1f3f3f3f3f -#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_INIT 0x00000c0c00000000 - -/* SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN */ -/* Description: vc0 fifo entry dynamic value */ -#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0 -#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f - -/* SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP */ -/* Description: vc0 fifo entry captured value */ -#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8 -#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00 - -/* SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN */ -/* Description: vc2 fifo entry dynamic value */ -#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16 -#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000 - -/* SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP */ -/* Description: vc2 fifo entry captured value */ -#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24 -#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000 - -/* SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST */ -/* Description: vc0 test credits limit */ -#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32 -#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000 - -/* SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST */ -/* Description: vc2 test credits limit */ -#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40 -#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNMD_FR_IILB_PORT_FLOW_FIFO" */ -/* ==================================================================== */ - -#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO 0x0000000150030160 -#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_MASK 0x00001f1f3f3f3f3f -#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_INIT 0x00000c0c00000000 - -/* SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN */ -/* Description: vc0 fifo entry dynamic value */ -#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0 -#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f - -/* SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP */ -/* Description: vc0 fifo entry captured value */ -#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8 -#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00 - -/* SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN */ -/* Description: vc2 fifo entry dynamic value */ -#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16 -#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000 - -/* SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP */ -/* Description: vc2 fifo entry captured value */ -#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24 -#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000 - -/* SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST */ -/* Description: vc0 test credits limit */ -#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32 -#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000 - -/* SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST */ -/* Description: vc2 test credits limit */ -#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40 -#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNII_INTRA_FLOW" */ -/* ==================================================================== */ - -#define SH_XNII_INTRA_FLOW 0x0000000150030200 -#define SH_XNII_INTRA_FLOW_MASK 0x7f7f7f7f7f7fbfbf -#define SH_XNII_INTRA_FLOW_INIT 0x00003f00003f0000 - -/* SH_XNII_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNII_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNII_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNII_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNII_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNII_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNII_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNII_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNII_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNII_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNII_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNII_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNII_INTRA_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 credit_test */ -#define SH_XNII_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 16 -#define SH_XNII_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x00000000007f0000 - -/* SH_XNII_INTRA_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNII_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 24 -#define SH_XNII_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x000000007f000000 - -/* SH_XNII_INTRA_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNII_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 32 -#define SH_XNII_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x0000007f00000000 - -/* SH_XNII_INTRA_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 credit_test */ -#define SH_XNII_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 40 -#define SH_XNII_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x00007f0000000000 - -/* SH_XNII_INTRA_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNII_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 48 -#define SH_XNII_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x007f000000000000 - -/* SH_XNII_INTRA_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNII_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 56 -#define SH_XNII_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x7f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNLB_INTRA_FLOW" */ -/* ==================================================================== */ - -#define SH_XNLB_INTRA_FLOW 0x0000000150030210 -#define SH_XNLB_INTRA_FLOW_MASK 0xff7f7f7f7f7fbfbf -#define SH_XNLB_INTRA_FLOW_INIT 0x0000080000100000 - -/* SH_XNLB_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNLB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNLB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNLB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNLB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNLB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNLB_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNLB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNLB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNLB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNLB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNLB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNLB_INTRA_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 credit_test */ -#define SH_XNLB_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 16 -#define SH_XNLB_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x00000000007f0000 - -/* SH_XNLB_INTRA_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNLB_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 24 -#define SH_XNLB_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x000000007f000000 - -/* SH_XNLB_INTRA_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNLB_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 32 -#define SH_XNLB_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x0000007f00000000 - -/* SH_XNLB_INTRA_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 credit_test */ -#define SH_XNLB_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 40 -#define SH_XNLB_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x00007f0000000000 - -/* SH_XNLB_INTRA_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNLB_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 48 -#define SH_XNLB_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x007f000000000000 - -/* SH_XNLB_INTRA_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNLB_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 56 -#define SH_XNLB_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x7f00000000000000 - -/* SH_XNLB_INTRA_FLOW_DISABLE_BYPASS_IN */ -#define SH_XNLB_INTRA_FLOW_DISABLE_BYPASS_IN_SHFT 63 -#define SH_XNLB_INTRA_FLOW_DISABLE_BYPASS_IN_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT 0x0000000150030220 -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 - -/* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_DYN */ -/* Description: vc0 debit dynamic value */ -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 - -/* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_CAP */ -/* Description: vc0 debit captured value */ -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 - -/* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_DYN */ -/* Description: vc2 debit dynamic value */ -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 - -/* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_CAP */ -/* Description: vc2 debit captured value */ -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT 0x0000000150030230 -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 - -/* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_DYN */ -/* Description: vc0 debit dynamic value */ -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 - -/* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_CAP */ -/* Description: vc0 debit captured value */ -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 - -/* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_DYN */ -/* Description: vc2 debit dynamic value */ -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 - -/* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_CAP */ -/* Description: vc2 debit captured value */ -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT 0x0000000150030240 -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 - -/* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN */ -/* Description: vc0 debit dynamic value */ -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 - -/* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP */ -/* Description: vc0 debit captured value */ -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 - -/* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN */ -/* Description: vc2 debit dynamic value */ -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 - -/* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP */ -/* Description: vc2 debit captured value */ -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT 0x0000000150030250 -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 - -/* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN */ -/* Description: vc0 debit dynamic value */ -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 - -/* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP */ -/* Description: vc0 debit captured value */ -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 - -/* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN */ -/* Description: vc2 debit dynamic value */ -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 - -/* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP */ -/* Description: vc2 debit captured value */ -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT 0x0000000150030260 -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 - -/* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN */ -/* Description: vc0 debit dynamic value */ -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 - -/* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP */ -/* Description: vc0 debit captured value */ -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 - -/* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN */ -/* Description: vc2 debit dynamic value */ -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 - -/* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP */ -/* Description: vc2 debit captured value */ -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT 0x0000000150030270 -#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f -#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c - -/* SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 credit_test */ -#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 -#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f - -/* SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 -#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 - -/* SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 -#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 - -/* SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 credit_test */ -#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 -#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 - -/* SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 -#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 - -/* SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 -#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT 0x0000000150030280 -#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f -#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c - -/* SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 credit_test */ -#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 -#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f - -/* SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 -#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 - -/* SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 -#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 - -/* SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 credit_test */ -#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 -#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 - -/* SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 -#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 - -/* SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 -#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT 0x0000000150030290 -#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f -#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c - -/* SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 credit_test */ -#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 -#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f - -/* SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 -#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 - -/* SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 -#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 - -/* SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 credit_test */ -#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 -#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 - -/* SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 -#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 - -/* SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 -#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT 0x00000001500302a0 -#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f -#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c - -/* SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 credit_test */ -#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 -#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f - -/* SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 -#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 - -/* SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 -#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 - -/* SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 credit_test */ -#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 -#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 - -/* SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 -#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 - -/* SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 -#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT 0x00000001500302b0 -#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f -#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c - -/* SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 credit_test */ -#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 -#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f - -/* SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 -#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 - -/* SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 -#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 - -/* SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 credit_test */ -#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 -#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 - -/* SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 -#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 - -/* SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 -#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT 0x0000000150030300 -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 - -/* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN */ -/* Description: vc0 debit dynamic value */ -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 - -/* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP */ -/* Description: vc0 debit captured value */ -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 - -/* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN */ -/* Description: vc2 debit dynamic value */ -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 - -/* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP */ -/* Description: vc2 debit captured value */ -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT 0x0000000150030310 -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 - -/* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN */ -/* Description: vc0 debit dynamic value */ -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 - -/* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP */ -/* Description: vc0 debit captured value */ -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 - -/* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN */ -/* Description: vc2 debit dynamic value */ -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 - -/* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP */ -/* Description: vc2 debit captured value */ -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT 0x0000000150030320 -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 - -/* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN */ -/* Description: vc0 debit dynamic value */ -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 - -/* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP */ -/* Description: vc0 debit captured value */ -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 - -/* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN */ -/* Description: vc2 debit dynamic value */ -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 - -/* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP */ -/* Description: vc2 debit captured value */ -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT 0x0000000150030330 -#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f -#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c - -/* SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 credit_test */ -#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 -#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f - -/* SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 -#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 - -/* SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 -#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 - -/* SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 credit_test */ -#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 -#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 - -/* SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 -#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 - -/* SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 -#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT 0x0000000150030340 -#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f -#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c - -/* SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 credit_test */ -#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 -#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f - -/* SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 -#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 - -/* SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 -#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 - -/* SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 credit_test */ -#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 -#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 - -/* SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 -#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 - -/* SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 -#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT 0x0000000150030350 -#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f -#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c - -/* SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 credit_test */ -#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 -#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f - -/* SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 -#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 - -/* SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 -#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 - -/* SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 credit_test */ -#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 -#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 - -/* SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 -#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 - -/* SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 -#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_0_INTRANI_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_0_INTRANI_FLOW 0x0000000150030360 -#define SH_XNNI0_0_INTRANI_FLOW_MASK 0x00000000000000bf -#define SH_XNNI0_0_INTRANI_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* ==================================================================== */ -/* Register "SH_XNNI0_1_INTRANI_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_1_INTRANI_FLOW 0x0000000150030370 -#define SH_XNNI0_1_INTRANI_FLOW_MASK 0x00000000000000bf -#define SH_XNNI0_1_INTRANI_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD */ -/* Description: vc1 withhold */ -#define SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD_SHFT 0 -#define SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED */ -/* Description: Force Credit on VC1 from debit cntr */ -#define SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED_SHFT 7 -#define SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED_MASK 0x0000000000000080 - -/* ==================================================================== */ -/* Register "SH_XNNI0_2_INTRANI_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_2_INTRANI_FLOW 0x0000000150030380 -#define SH_XNNI0_2_INTRANI_FLOW_MASK 0x00000000000000bf -#define SH_XNNI0_2_INTRANI_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD_SHFT 0 -#define SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 7 -#define SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000000080 - -/* ==================================================================== */ -/* Register "SH_XNNI0_3_INTRANI_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_3_INTRANI_FLOW 0x0000000150030390 -#define SH_XNNI0_3_INTRANI_FLOW_MASK 0x00000000000000bf -#define SH_XNNI0_3_INTRANI_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD */ -/* Description: vc3 withhold */ -#define SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD_SHFT 0 -#define SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED */ -/* Description: Force Credit on VC3 from debit cntr */ -#define SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED_SHFT 7 -#define SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED_MASK 0x0000000000000080 - -/* ==================================================================== */ -/* Register "SH_XNNI0_VCSWITCH_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_VCSWITCH_FLOW 0x00000001500303a0 -#define SH_XNNI0_VCSWITCH_FLOW_MASK 0x0000000701010101 -#define SH_XNNI0_VCSWITCH_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI0_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH */ -/* Description: Swap VC0/2 with VC1/3 */ -#define SH_XNNI0_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH_SHFT 0 -#define SH_XNNI0_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH_MASK 0x0000000000000001 - -/* SH_XNNI0_VCSWITCH_FLOW_PI_VCFIFO_SWITCH */ -/* Description: Swap VC0/2 with VC1/3 */ -#define SH_XNNI0_VCSWITCH_FLOW_PI_VCFIFO_SWITCH_SHFT 8 -#define SH_XNNI0_VCSWITCH_FLOW_PI_VCFIFO_SWITCH_MASK 0x0000000000000100 - -/* SH_XNNI0_VCSWITCH_FLOW_MD_VCFIFO_SWITCH */ -/* Description: Swap VC0/2 with VC1/3 */ -#define SH_XNNI0_VCSWITCH_FLOW_MD_VCFIFO_SWITCH_SHFT 16 -#define SH_XNNI0_VCSWITCH_FLOW_MD_VCFIFO_SWITCH_MASK 0x0000000000010000 - -/* SH_XNNI0_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH */ -/* Description: Swap VC0/2 with VC1/3 */ -#define SH_XNNI0_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH_SHFT 24 -#define SH_XNNI0_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH_MASK 0x0000000001000000 - -/* SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN */ -#define SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN_SHFT 32 -#define SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN_MASK 0x0000000100000000 - -/* SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT */ -#define SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT_SHFT 33 -#define SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT_MASK 0x0000000200000000 - -/* SH_XNNI0_VCSWITCH_FLOW_ASYNC_FIFOES */ -#define SH_XNNI0_VCSWITCH_FLOW_ASYNC_FIFOES_SHFT 34 -#define SH_XNNI0_VCSWITCH_FLOW_ASYNC_FIFOES_MASK 0x0000000400000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_TIMER_REG" */ -/* ==================================================================== */ - -#define SH_XNNI0_TIMER_REG 0x00000001500303b0 -#define SH_XNNI0_TIMER_REG_MASK 0x0000000100ffffff -#define SH_XNNI0_TIMER_REG_INIT 0x0000000000ffffff - -/* SH_XNNI0_TIMER_REG_TIMEOUT_REG */ -/* Description: Master Timeout Counter */ -#define SH_XNNI0_TIMER_REG_TIMEOUT_REG_SHFT 0 -#define SH_XNNI0_TIMER_REG_TIMEOUT_REG_MASK 0x0000000000ffffff - -/* SH_XNNI0_TIMER_REG_LINKCLEANUP_REG */ -/* Description: Link Clean Up */ -#define SH_XNNI0_TIMER_REG_LINKCLEANUP_REG_SHFT 32 -#define SH_XNNI0_TIMER_REG_LINKCLEANUP_REG_MASK 0x0000000100000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_FIFO02_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_FIFO02_FLOW 0x00000001500303c0 -#define SH_XNNI0_FIFO02_FLOW_MASK 0x00000f0f0f0f0f0f -#define SH_XNNI0_FIFO02_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI0_FIFO02_FLOW_COUNT_VC0_LIMIT */ -/* Description: limit reg zero disables functionality */ -#define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_LIMIT_SHFT 0 -#define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_LIMIT_MASK 0x000000000000000f - -/* SH_XNNI0_FIFO02_FLOW_COUNT_VC0_DYN */ -/* Description: dynamic counter value */ -#define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_DYN_SHFT 8 -#define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_DYN_MASK 0x0000000000000f00 - -/* SH_XNNI0_FIFO02_FLOW_COUNT_VC0_CAP */ -/* Description: captured counter value */ -#define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_CAP_SHFT 16 -#define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_CAP_MASK 0x00000000000f0000 - -/* SH_XNNI0_FIFO02_FLOW_COUNT_VC2_LIMIT */ -/* Description: limit reg zero disables functionality */ -#define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_LIMIT_SHFT 24 -#define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_LIMIT_MASK 0x000000000f000000 - -/* SH_XNNI0_FIFO02_FLOW_COUNT_VC2_DYN */ -/* Description: counter dynamic value */ -#define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_DYN_SHFT 32 -#define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_DYN_MASK 0x0000000f00000000 - -/* SH_XNNI0_FIFO02_FLOW_COUNT_VC2_CAP */ -/* Description: captured counter value */ -#define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_CAP_SHFT 40 -#define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_CAP_MASK 0x00000f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_FIFO13_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_FIFO13_FLOW 0x00000001500303d0 -#define SH_XNNI0_FIFO13_FLOW_MASK 0x00000f0f0f0f0f0f -#define SH_XNNI0_FIFO13_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI0_FIFO13_FLOW_COUNT_VC1_LIMIT */ -/* Description: limit reg zero disables functionality */ -#define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_LIMIT_SHFT 0 -#define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_LIMIT_MASK 0x000000000000000f - -/* SH_XNNI0_FIFO13_FLOW_COUNT_VC1_DYN */ -/* Description: dynamic counter value */ -#define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_DYN_SHFT 8 -#define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_DYN_MASK 0x0000000000000f00 - -/* SH_XNNI0_FIFO13_FLOW_COUNT_VC1_CAP */ -/* Description: captured counter value */ -#define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_CAP_SHFT 16 -#define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_CAP_MASK 0x00000000000f0000 - -/* SH_XNNI0_FIFO13_FLOW_COUNT_VC3_LIMIT */ -/* Description: limit reg zero disables functionality */ -#define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_LIMIT_SHFT 24 -#define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_LIMIT_MASK 0x000000000f000000 - -/* SH_XNNI0_FIFO13_FLOW_COUNT_VC3_DYN */ -/* Description: counter dynamic value */ -#define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_DYN_SHFT 32 -#define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_DYN_MASK 0x0000000f00000000 - -/* SH_XNNI0_FIFO13_FLOW_COUNT_VC3_CAP */ -/* Description: captured counter value */ -#define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_CAP_SHFT 40 -#define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_CAP_MASK 0x00000f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_NI_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_NI_FLOW 0x00000001500303e0 -#define SH_XNNI0_NI_FLOW_MASK 0xff0fff0fff0fff0f -#define SH_XNNI0_NI_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI0_NI_FLOW_VC0_LIMIT */ -/* Description: vc0 limit reg, zero disables functionality */ -#define SH_XNNI0_NI_FLOW_VC0_LIMIT_SHFT 0 -#define SH_XNNI0_NI_FLOW_VC0_LIMIT_MASK 0x000000000000000f - -/* SH_XNNI0_NI_FLOW_VC0_DYN */ -/* Description: vc0 counter dynamic value */ -#define SH_XNNI0_NI_FLOW_VC0_DYN_SHFT 8 -#define SH_XNNI0_NI_FLOW_VC0_DYN_MASK 0x0000000000000f00 - -/* SH_XNNI0_NI_FLOW_VC0_CAP */ -/* Description: vc0 counter captured value */ -#define SH_XNNI0_NI_FLOW_VC0_CAP_SHFT 12 -#define SH_XNNI0_NI_FLOW_VC0_CAP_MASK 0x000000000000f000 - -/* SH_XNNI0_NI_FLOW_VC1_LIMIT */ -/* Description: vc1 limit reg, zero disables functionality */ -#define SH_XNNI0_NI_FLOW_VC1_LIMIT_SHFT 16 -#define SH_XNNI0_NI_FLOW_VC1_LIMIT_MASK 0x00000000000f0000 - -/* SH_XNNI0_NI_FLOW_VC1_DYN */ -/* Description: vc1 counter dynamic value */ -#define SH_XNNI0_NI_FLOW_VC1_DYN_SHFT 24 -#define SH_XNNI0_NI_FLOW_VC1_DYN_MASK 0x000000000f000000 - -/* SH_XNNI0_NI_FLOW_VC1_CAP */ -/* Description: vc1 counter captured value */ -#define SH_XNNI0_NI_FLOW_VC1_CAP_SHFT 28 -#define SH_XNNI0_NI_FLOW_VC1_CAP_MASK 0x00000000f0000000 - -/* SH_XNNI0_NI_FLOW_VC2_LIMIT */ -/* Description: vc2 limit reg, zero disables functionality */ -#define SH_XNNI0_NI_FLOW_VC2_LIMIT_SHFT 32 -#define SH_XNNI0_NI_FLOW_VC2_LIMIT_MASK 0x0000000f00000000 - -/* SH_XNNI0_NI_FLOW_VC2_DYN */ -/* Description: vc2 counter dynamic value */ -#define SH_XNNI0_NI_FLOW_VC2_DYN_SHFT 40 -#define SH_XNNI0_NI_FLOW_VC2_DYN_MASK 0x00000f0000000000 - -/* SH_XNNI0_NI_FLOW_VC2_CAP */ -/* Description: vc2 counter captured value */ -#define SH_XNNI0_NI_FLOW_VC2_CAP_SHFT 44 -#define SH_XNNI0_NI_FLOW_VC2_CAP_MASK 0x0000f00000000000 - -/* SH_XNNI0_NI_FLOW_VC3_LIMIT */ -/* Description: vc3 limit reg, zero disables functionality */ -#define SH_XNNI0_NI_FLOW_VC3_LIMIT_SHFT 48 -#define SH_XNNI0_NI_FLOW_VC3_LIMIT_MASK 0x000f000000000000 - -/* SH_XNNI0_NI_FLOW_VC3_DYN */ -/* Description: vc3 counter dynamic value */ -#define SH_XNNI0_NI_FLOW_VC3_DYN_SHFT 56 -#define SH_XNNI0_NI_FLOW_VC3_DYN_MASK 0x0f00000000000000 - -/* SH_XNNI0_NI_FLOW_VC3_CAP */ -/* Description: vc3 counter captured value */ -#define SH_XNNI0_NI_FLOW_VC3_CAP_SHFT 60 -#define SH_XNNI0_NI_FLOW_VC3_CAP_MASK 0xf000000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_DEAD_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_DEAD_FLOW 0x00000001500303f0 -#define SH_XNNI0_DEAD_FLOW_MASK 0xff0fff0fff0fff0f -#define SH_XNNI0_DEAD_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI0_DEAD_FLOW_VC0_LIMIT */ -/* Description: vc0 limit reg, zero disables functionality */ -#define SH_XNNI0_DEAD_FLOW_VC0_LIMIT_SHFT 0 -#define SH_XNNI0_DEAD_FLOW_VC0_LIMIT_MASK 0x000000000000000f - -/* SH_XNNI0_DEAD_FLOW_VC0_DYN */ -/* Description: vc0 counter dynamic value */ -#define SH_XNNI0_DEAD_FLOW_VC0_DYN_SHFT 8 -#define SH_XNNI0_DEAD_FLOW_VC0_DYN_MASK 0x0000000000000f00 - -/* SH_XNNI0_DEAD_FLOW_VC0_CAP */ -/* Description: vc0 counter captured value */ -#define SH_XNNI0_DEAD_FLOW_VC0_CAP_SHFT 12 -#define SH_XNNI0_DEAD_FLOW_VC0_CAP_MASK 0x000000000000f000 - -/* SH_XNNI0_DEAD_FLOW_VC1_LIMIT */ -/* Description: vc1 limit reg, zero disables functionality */ -#define SH_XNNI0_DEAD_FLOW_VC1_LIMIT_SHFT 16 -#define SH_XNNI0_DEAD_FLOW_VC1_LIMIT_MASK 0x00000000000f0000 - -/* SH_XNNI0_DEAD_FLOW_VC1_DYN */ -/* Description: vc1 counter dynamic value */ -#define SH_XNNI0_DEAD_FLOW_VC1_DYN_SHFT 24 -#define SH_XNNI0_DEAD_FLOW_VC1_DYN_MASK 0x000000000f000000 - -/* SH_XNNI0_DEAD_FLOW_VC1_CAP */ -/* Description: vc1 counter captured value */ -#define SH_XNNI0_DEAD_FLOW_VC1_CAP_SHFT 28 -#define SH_XNNI0_DEAD_FLOW_VC1_CAP_MASK 0x00000000f0000000 - -/* SH_XNNI0_DEAD_FLOW_VC2_LIMIT */ -/* Description: vc2 limit reg, zero disables functionality */ -#define SH_XNNI0_DEAD_FLOW_VC2_LIMIT_SHFT 32 -#define SH_XNNI0_DEAD_FLOW_VC2_LIMIT_MASK 0x0000000f00000000 - -/* SH_XNNI0_DEAD_FLOW_VC2_DYN */ -/* Description: vc2 counter dynamic value */ -#define SH_XNNI0_DEAD_FLOW_VC2_DYN_SHFT 40 -#define SH_XNNI0_DEAD_FLOW_VC2_DYN_MASK 0x00000f0000000000 - -/* SH_XNNI0_DEAD_FLOW_VC2_CAP */ -/* Description: vc2 counter captured value */ -#define SH_XNNI0_DEAD_FLOW_VC2_CAP_SHFT 44 -#define SH_XNNI0_DEAD_FLOW_VC2_CAP_MASK 0x0000f00000000000 - -/* SH_XNNI0_DEAD_FLOW_VC3_LIMIT */ -/* Description: vc3 limit reg, zero disables functionality */ -#define SH_XNNI0_DEAD_FLOW_VC3_LIMIT_SHFT 48 -#define SH_XNNI0_DEAD_FLOW_VC3_LIMIT_MASK 0x000f000000000000 - -/* SH_XNNI0_DEAD_FLOW_VC3_DYN */ -/* Description: vc3 counter dynamic value */ -#define SH_XNNI0_DEAD_FLOW_VC3_DYN_SHFT 56 -#define SH_XNNI0_DEAD_FLOW_VC3_DYN_MASK 0x0f00000000000000 - -/* SH_XNNI0_DEAD_FLOW_VC3_CAP */ -/* Description: vc3 counter captured value */ -#define SH_XNNI0_DEAD_FLOW_VC3_CAP_SHFT 60 -#define SH_XNNI0_DEAD_FLOW_VC3_CAP_MASK 0xf000000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_INJECT_AGE" */ -/* ==================================================================== */ - -#define SH_XNNI0_INJECT_AGE 0x0000000150030400 -#define SH_XNNI0_INJECT_AGE_MASK 0x000000000000ffff -#define SH_XNNI0_INJECT_AGE_INIT 0x0000000000000000 - -/* SH_XNNI0_INJECT_AGE_REQUEST_INJECT */ -/* Description: Value of AGE field for outgoing requests */ -#define SH_XNNI0_INJECT_AGE_REQUEST_INJECT_SHFT 0 -#define SH_XNNI0_INJECT_AGE_REQUEST_INJECT_MASK 0x00000000000000ff - -/* SH_XNNI0_INJECT_AGE_REPLY_INJECT */ -/* Description: Value of AGE field for outgoing replies */ -#define SH_XNNI0_INJECT_AGE_REPLY_INJECT_SHFT 8 -#define SH_XNNI0_INJECT_AGE_REPLY_INJECT_MASK 0x000000000000ff00 - -/* ==================================================================== */ -/* Register "SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT 0x0000000150030500 -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 - -/* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN */ -/* Description: vc0 debit dynamic value */ -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 - -/* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP */ -/* Description: vc0 debit captured value */ -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 - -/* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN */ -/* Description: vc2 debit dynamic value */ -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 - -/* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP */ -/* Description: vc2 debit captured value */ -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT 0x0000000150030510 -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 - -/* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN */ -/* Description: vc0 debit dynamic value */ -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 - -/* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP */ -/* Description: vc0 debit captured value */ -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 - -/* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN */ -/* Description: vc2 debit dynamic value */ -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 - -/* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP */ -/* Description: vc2 debit captured value */ -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT 0x0000000150030520 -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 - -/* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN */ -/* Description: vc0 debit dynamic value */ -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 - -/* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP */ -/* Description: vc0 debit captured value */ -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 - -/* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN */ -/* Description: vc2 debit dynamic value */ -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 - -/* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP */ -/* Description: vc2 debit captured value */ -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT 0x0000000150030530 -#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f -#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c - -/* SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 credit_test */ -#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 -#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f - -/* SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 -#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 - -/* SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 -#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 - -/* SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 credit_test */ -#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 -#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 - -/* SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 -#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 - -/* SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 -#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT 0x0000000150030540 -#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f -#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c - -/* SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 credit_test */ -#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 -#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f - -/* SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 -#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 - -/* SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 -#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 - -/* SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 credit_test */ -#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 -#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 - -/* SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 -#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 - -/* SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 -#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT 0x0000000150030550 -#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f -#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c - -/* SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 credit_test */ -#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 -#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f - -/* SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 -#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 - -/* SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 -#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 - -/* SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 credit_test */ -#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 -#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 - -/* SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 -#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 - -/* SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 -#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_0_INTRANI_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_0_INTRANI_FLOW 0x0000000150030560 -#define SH_XNNI1_0_INTRANI_FLOW_MASK 0x00000000000000bf -#define SH_XNNI1_0_INTRANI_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* ==================================================================== */ -/* Register "SH_XNNI1_1_INTRANI_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_1_INTRANI_FLOW 0x0000000150030570 -#define SH_XNNI1_1_INTRANI_FLOW_MASK 0x00000000000000bf -#define SH_XNNI1_1_INTRANI_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD */ -/* Description: vc1 withhold */ -#define SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD_SHFT 0 -#define SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED */ -/* Description: Force Credit on VC1 from debit cntr */ -#define SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED_SHFT 7 -#define SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED_MASK 0x0000000000000080 - -/* ==================================================================== */ -/* Register "SH_XNNI1_2_INTRANI_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_2_INTRANI_FLOW 0x0000000150030580 -#define SH_XNNI1_2_INTRANI_FLOW_MASK 0x00000000000000bf -#define SH_XNNI1_2_INTRANI_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD_SHFT 0 -#define SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 7 -#define SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000000080 - -/* ==================================================================== */ -/* Register "SH_XNNI1_3_INTRANI_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_3_INTRANI_FLOW 0x0000000150030590 -#define SH_XNNI1_3_INTRANI_FLOW_MASK 0x00000000000000bf -#define SH_XNNI1_3_INTRANI_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD */ -/* Description: vc3 withhold */ -#define SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD_SHFT 0 -#define SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED */ -/* Description: Force Credit on VC3 from debit cntr */ -#define SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED_SHFT 7 -#define SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED_MASK 0x0000000000000080 - -/* ==================================================================== */ -/* Register "SH_XNNI1_VCSWITCH_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_VCSWITCH_FLOW 0x00000001500305a0 -#define SH_XNNI1_VCSWITCH_FLOW_MASK 0x0000000701010101 -#define SH_XNNI1_VCSWITCH_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI1_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH */ -/* Description: Swap VC0/2 with VC1/3 */ -#define SH_XNNI1_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH_SHFT 0 -#define SH_XNNI1_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH_MASK 0x0000000000000001 - -/* SH_XNNI1_VCSWITCH_FLOW_PI_VCFIFO_SWITCH */ -/* Description: Swap VC0/2 with VC1/3 */ -#define SH_XNNI1_VCSWITCH_FLOW_PI_VCFIFO_SWITCH_SHFT 8 -#define SH_XNNI1_VCSWITCH_FLOW_PI_VCFIFO_SWITCH_MASK 0x0000000000000100 - -/* SH_XNNI1_VCSWITCH_FLOW_MD_VCFIFO_SWITCH */ -/* Description: Swap VC0/2 with VC1/3 */ -#define SH_XNNI1_VCSWITCH_FLOW_MD_VCFIFO_SWITCH_SHFT 16 -#define SH_XNNI1_VCSWITCH_FLOW_MD_VCFIFO_SWITCH_MASK 0x0000000000010000 - -/* SH_XNNI1_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH */ -/* Description: Swap VC0/2 with VC1/3 */ -#define SH_XNNI1_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH_SHFT 24 -#define SH_XNNI1_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH_MASK 0x0000000001000000 - -/* SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN */ -#define SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN_SHFT 32 -#define SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN_MASK 0x0000000100000000 - -/* SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT */ -#define SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT_SHFT 33 -#define SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT_MASK 0x0000000200000000 - -/* SH_XNNI1_VCSWITCH_FLOW_ASYNC_FIFOES */ -#define SH_XNNI1_VCSWITCH_FLOW_ASYNC_FIFOES_SHFT 34 -#define SH_XNNI1_VCSWITCH_FLOW_ASYNC_FIFOES_MASK 0x0000000400000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_TIMER_REG" */ -/* ==================================================================== */ - -#define SH_XNNI1_TIMER_REG 0x00000001500305b0 -#define SH_XNNI1_TIMER_REG_MASK 0x0000000100ffffff -#define SH_XNNI1_TIMER_REG_INIT 0x0000000000ffffff - -/* SH_XNNI1_TIMER_REG_TIMEOUT_REG */ -/* Description: Master Timeout Counter */ -#define SH_XNNI1_TIMER_REG_TIMEOUT_REG_SHFT 0 -#define SH_XNNI1_TIMER_REG_TIMEOUT_REG_MASK 0x0000000000ffffff - -/* SH_XNNI1_TIMER_REG_LINKCLEANUP_REG */ -/* Description: Link Clean Up */ -#define SH_XNNI1_TIMER_REG_LINKCLEANUP_REG_SHFT 32 -#define SH_XNNI1_TIMER_REG_LINKCLEANUP_REG_MASK 0x0000000100000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_FIFO02_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_FIFO02_FLOW 0x00000001500305c0 -#define SH_XNNI1_FIFO02_FLOW_MASK 0x00000f0f0f0f0f0f -#define SH_XNNI1_FIFO02_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI1_FIFO02_FLOW_COUNT_VC0_LIMIT */ -/* Description: limit reg zero disables functionality */ -#define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_LIMIT_SHFT 0 -#define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_LIMIT_MASK 0x000000000000000f - -/* SH_XNNI1_FIFO02_FLOW_COUNT_VC0_DYN */ -/* Description: dynamic counter value */ -#define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_DYN_SHFT 8 -#define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_DYN_MASK 0x0000000000000f00 - -/* SH_XNNI1_FIFO02_FLOW_COUNT_VC0_CAP */ -/* Description: captured counter value */ -#define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_CAP_SHFT 16 -#define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_CAP_MASK 0x00000000000f0000 - -/* SH_XNNI1_FIFO02_FLOW_COUNT_VC2_LIMIT */ -/* Description: limit reg zero disables functionality */ -#define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_LIMIT_SHFT 24 -#define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_LIMIT_MASK 0x000000000f000000 - -/* SH_XNNI1_FIFO02_FLOW_COUNT_VC2_DYN */ -/* Description: counter dynamic value */ -#define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_DYN_SHFT 32 -#define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_DYN_MASK 0x0000000f00000000 - -/* SH_XNNI1_FIFO02_FLOW_COUNT_VC2_CAP */ -/* Description: captured counter value */ -#define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_CAP_SHFT 40 -#define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_CAP_MASK 0x00000f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_FIFO13_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_FIFO13_FLOW 0x00000001500305d0 -#define SH_XNNI1_FIFO13_FLOW_MASK 0x00000f0f0f0f0f0f -#define SH_XNNI1_FIFO13_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI1_FIFO13_FLOW_COUNT_VC1_LIMIT */ -/* Description: limit reg zero disables functionality */ -#define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_LIMIT_SHFT 0 -#define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_LIMIT_MASK 0x000000000000000f - -/* SH_XNNI1_FIFO13_FLOW_COUNT_VC1_DYN */ -/* Description: dynamic counter value */ -#define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_DYN_SHFT 8 -#define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_DYN_MASK 0x0000000000000f00 - -/* SH_XNNI1_FIFO13_FLOW_COUNT_VC1_CAP */ -/* Description: captured counter value */ -#define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_CAP_SHFT 16 -#define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_CAP_MASK 0x00000000000f0000 - -/* SH_XNNI1_FIFO13_FLOW_COUNT_VC3_LIMIT */ -/* Description: limit reg zero disables functionality */ -#define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_LIMIT_SHFT 24 -#define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_LIMIT_MASK 0x000000000f000000 - -/* SH_XNNI1_FIFO13_FLOW_COUNT_VC3_DYN */ -/* Description: counter dynamic value */ -#define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_DYN_SHFT 32 -#define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_DYN_MASK 0x0000000f00000000 - -/* SH_XNNI1_FIFO13_FLOW_COUNT_VC3_CAP */ -/* Description: captured counter value */ -#define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_CAP_SHFT 40 -#define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_CAP_MASK 0x00000f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_NI_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_NI_FLOW 0x00000001500305e0 -#define SH_XNNI1_NI_FLOW_MASK 0xff0fff0fff0fff0f -#define SH_XNNI1_NI_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI1_NI_FLOW_VC0_LIMIT */ -/* Description: vc0 limit reg, zero disables functionality */ -#define SH_XNNI1_NI_FLOW_VC0_LIMIT_SHFT 0 -#define SH_XNNI1_NI_FLOW_VC0_LIMIT_MASK 0x000000000000000f - -/* SH_XNNI1_NI_FLOW_VC0_DYN */ -/* Description: vc0 counter dynamic value */ -#define SH_XNNI1_NI_FLOW_VC0_DYN_SHFT 8 -#define SH_XNNI1_NI_FLOW_VC0_DYN_MASK 0x0000000000000f00 - -/* SH_XNNI1_NI_FLOW_VC0_CAP */ -/* Description: vc0 counter captured value */ -#define SH_XNNI1_NI_FLOW_VC0_CAP_SHFT 12 -#define SH_XNNI1_NI_FLOW_VC0_CAP_MASK 0x000000000000f000 - -/* SH_XNNI1_NI_FLOW_VC1_LIMIT */ -/* Description: vc1 limit reg, zero disables functionality */ -#define SH_XNNI1_NI_FLOW_VC1_LIMIT_SHFT 16 -#define SH_XNNI1_NI_FLOW_VC1_LIMIT_MASK 0x00000000000f0000 - -/* SH_XNNI1_NI_FLOW_VC1_DYN */ -/* Description: vc1 counter dynamic value */ -#define SH_XNNI1_NI_FLOW_VC1_DYN_SHFT 24 -#define SH_XNNI1_NI_FLOW_VC1_DYN_MASK 0x000000000f000000 - -/* SH_XNNI1_NI_FLOW_VC1_CAP */ -/* Description: vc1 counter captured value */ -#define SH_XNNI1_NI_FLOW_VC1_CAP_SHFT 28 -#define SH_XNNI1_NI_FLOW_VC1_CAP_MASK 0x00000000f0000000 - -/* SH_XNNI1_NI_FLOW_VC2_LIMIT */ -/* Description: vc2 limit reg, zero disables functionality */ -#define SH_XNNI1_NI_FLOW_VC2_LIMIT_SHFT 32 -#define SH_XNNI1_NI_FLOW_VC2_LIMIT_MASK 0x0000000f00000000 - -/* SH_XNNI1_NI_FLOW_VC2_DYN */ -/* Description: vc2 counter dynamic value */ -#define SH_XNNI1_NI_FLOW_VC2_DYN_SHFT 40 -#define SH_XNNI1_NI_FLOW_VC2_DYN_MASK 0x00000f0000000000 - -/* SH_XNNI1_NI_FLOW_VC2_CAP */ -/* Description: vc2 counter captured value */ -#define SH_XNNI1_NI_FLOW_VC2_CAP_SHFT 44 -#define SH_XNNI1_NI_FLOW_VC2_CAP_MASK 0x0000f00000000000 - -/* SH_XNNI1_NI_FLOW_VC3_LIMIT */ -/* Description: vc3 limit reg, zero disables functionality */ -#define SH_XNNI1_NI_FLOW_VC3_LIMIT_SHFT 48 -#define SH_XNNI1_NI_FLOW_VC3_LIMIT_MASK 0x000f000000000000 - -/* SH_XNNI1_NI_FLOW_VC3_DYN */ -/* Description: vc3 counter dynamic value */ -#define SH_XNNI1_NI_FLOW_VC3_DYN_SHFT 56 -#define SH_XNNI1_NI_FLOW_VC3_DYN_MASK 0x0f00000000000000 - -/* SH_XNNI1_NI_FLOW_VC3_CAP */ -/* Description: vc3 counter captured value */ -#define SH_XNNI1_NI_FLOW_VC3_CAP_SHFT 60 -#define SH_XNNI1_NI_FLOW_VC3_CAP_MASK 0xf000000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_DEAD_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_DEAD_FLOW 0x00000001500305f0 -#define SH_XNNI1_DEAD_FLOW_MASK 0xff0fff0fff0fff0f -#define SH_XNNI1_DEAD_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI1_DEAD_FLOW_VC0_LIMIT */ -/* Description: vc0 limit reg, zero disables functionality */ -#define SH_XNNI1_DEAD_FLOW_VC0_LIMIT_SHFT 0 -#define SH_XNNI1_DEAD_FLOW_VC0_LIMIT_MASK 0x000000000000000f - -/* SH_XNNI1_DEAD_FLOW_VC0_DYN */ -/* Description: vc0 counter dynamic value */ -#define SH_XNNI1_DEAD_FLOW_VC0_DYN_SHFT 8 -#define SH_XNNI1_DEAD_FLOW_VC0_DYN_MASK 0x0000000000000f00 - -/* SH_XNNI1_DEAD_FLOW_VC0_CAP */ -/* Description: vc0 counter captured value */ -#define SH_XNNI1_DEAD_FLOW_VC0_CAP_SHFT 12 -#define SH_XNNI1_DEAD_FLOW_VC0_CAP_MASK 0x000000000000f000 - -/* SH_XNNI1_DEAD_FLOW_VC1_LIMIT */ -/* Description: vc1 limit reg, zero disables functionality */ -#define SH_XNNI1_DEAD_FLOW_VC1_LIMIT_SHFT 16 -#define SH_XNNI1_DEAD_FLOW_VC1_LIMIT_MASK 0x00000000000f0000 - -/* SH_XNNI1_DEAD_FLOW_VC1_DYN */ -/* Description: vc1 counter dynamic value */ -#define SH_XNNI1_DEAD_FLOW_VC1_DYN_SHFT 24 -#define SH_XNNI1_DEAD_FLOW_VC1_DYN_MASK 0x000000000f000000 - -/* SH_XNNI1_DEAD_FLOW_VC1_CAP */ -/* Description: vc1 counter captured value */ -#define SH_XNNI1_DEAD_FLOW_VC1_CAP_SHFT 28 -#define SH_XNNI1_DEAD_FLOW_VC1_CAP_MASK 0x00000000f0000000 - -/* SH_XNNI1_DEAD_FLOW_VC2_LIMIT */ -/* Description: vc2 limit reg, zero disables functionality */ -#define SH_XNNI1_DEAD_FLOW_VC2_LIMIT_SHFT 32 -#define SH_XNNI1_DEAD_FLOW_VC2_LIMIT_MASK 0x0000000f00000000 - -/* SH_XNNI1_DEAD_FLOW_VC2_DYN */ -/* Description: vc2 counter dynamic value */ -#define SH_XNNI1_DEAD_FLOW_VC2_DYN_SHFT 40 -#define SH_XNNI1_DEAD_FLOW_VC2_DYN_MASK 0x00000f0000000000 - -/* SH_XNNI1_DEAD_FLOW_VC2_CAP */ -/* Description: vc2 counter captured value */ -#define SH_XNNI1_DEAD_FLOW_VC2_CAP_SHFT 44 -#define SH_XNNI1_DEAD_FLOW_VC2_CAP_MASK 0x0000f00000000000 - -/* SH_XNNI1_DEAD_FLOW_VC3_LIMIT */ -/* Description: vc3 limit reg, zero disables functionality */ -#define SH_XNNI1_DEAD_FLOW_VC3_LIMIT_SHFT 48 -#define SH_XNNI1_DEAD_FLOW_VC3_LIMIT_MASK 0x000f000000000000 - -/* SH_XNNI1_DEAD_FLOW_VC3_DYN */ -/* Description: vc3 counter dynamic value */ -#define SH_XNNI1_DEAD_FLOW_VC3_DYN_SHFT 56 -#define SH_XNNI1_DEAD_FLOW_VC3_DYN_MASK 0x0f00000000000000 - -/* SH_XNNI1_DEAD_FLOW_VC3_CAP */ -/* Description: vc3 counter captured value */ -#define SH_XNNI1_DEAD_FLOW_VC3_CAP_SHFT 60 -#define SH_XNNI1_DEAD_FLOW_VC3_CAP_MASK 0xf000000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_INJECT_AGE" */ -/* ==================================================================== */ - -#define SH_XNNI1_INJECT_AGE 0x0000000150030600 -#define SH_XNNI1_INJECT_AGE_MASK 0x000000000000ffff -#define SH_XNNI1_INJECT_AGE_INIT 0x0000000000000000 - -/* SH_XNNI1_INJECT_AGE_REQUEST_INJECT */ -/* Description: Value of AGE field for outgoing requests */ -#define SH_XNNI1_INJECT_AGE_REQUEST_INJECT_SHFT 0 -#define SH_XNNI1_INJECT_AGE_REQUEST_INJECT_MASK 0x00000000000000ff - -/* SH_XNNI1_INJECT_AGE_REPLY_INJECT */ -/* Description: Value of AGE field for outgoing replies */ -#define SH_XNNI1_INJECT_AGE_REPLY_INJECT_SHFT 8 -#define SH_XNNI1_INJECT_AGE_REPLY_INJECT_MASK 0x000000000000ff00 - -/* ==================================================================== */ -/* Register "SH_XN_DEBUG_SEL" */ -/* XN Debug Port Select */ -/* ==================================================================== */ - -#define SH_XN_DEBUG_SEL 0x0000000150031000 -#define SH_XN_DEBUG_SEL_MASK 0xf777777777777777 -#define SH_XN_DEBUG_SEL_INIT 0x0000000000000000 - -/* SH_XN_DEBUG_SEL_NIBBLE0_RLM_SEL */ -/* Description: Nibble 0 RLM select */ -#define SH_XN_DEBUG_SEL_NIBBLE0_RLM_SEL_SHFT 0 -#define SH_XN_DEBUG_SEL_NIBBLE0_RLM_SEL_MASK 0x0000000000000007 - -/* SH_XN_DEBUG_SEL_NIBBLE0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_XN_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4 -#define SH_XN_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_XN_DEBUG_SEL_NIBBLE1_RLM_SEL */ -/* Description: Nibble 1 RLM select */ -#define SH_XN_DEBUG_SEL_NIBBLE1_RLM_SEL_SHFT 8 -#define SH_XN_DEBUG_SEL_NIBBLE1_RLM_SEL_MASK 0x0000000000000700 - -/* SH_XN_DEBUG_SEL_NIBBLE1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_XN_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12 -#define SH_XN_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_XN_DEBUG_SEL_NIBBLE2_RLM_SEL */ -/* Description: Nibble 2 RLM select */ -#define SH_XN_DEBUG_SEL_NIBBLE2_RLM_SEL_SHFT 16 -#define SH_XN_DEBUG_SEL_NIBBLE2_RLM_SEL_MASK 0x0000000000070000 - -/* SH_XN_DEBUG_SEL_NIBBLE2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_XN_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20 -#define SH_XN_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_XN_DEBUG_SEL_NIBBLE3_RLM_SEL */ -/* Description: Nibble 3 RLM select */ -#define SH_XN_DEBUG_SEL_NIBBLE3_RLM_SEL_SHFT 24 -#define SH_XN_DEBUG_SEL_NIBBLE3_RLM_SEL_MASK 0x0000000007000000 - -/* SH_XN_DEBUG_SEL_NIBBLE3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_XN_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28 -#define SH_XN_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_XN_DEBUG_SEL_NIBBLE4_RLM_SEL */ -/* Description: Nibble 4 RLM select */ -#define SH_XN_DEBUG_SEL_NIBBLE4_RLM_SEL_SHFT 32 -#define SH_XN_DEBUG_SEL_NIBBLE4_RLM_SEL_MASK 0x0000000700000000 - -/* SH_XN_DEBUG_SEL_NIBBLE4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_XN_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36 -#define SH_XN_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_XN_DEBUG_SEL_NIBBLE5_RLM_SEL */ -/* Description: Nibble 5 RLM select */ -#define SH_XN_DEBUG_SEL_NIBBLE5_RLM_SEL_SHFT 40 -#define SH_XN_DEBUG_SEL_NIBBLE5_RLM_SEL_MASK 0x0000070000000000 - -/* SH_XN_DEBUG_SEL_NIBBLE5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_XN_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44 -#define SH_XN_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_XN_DEBUG_SEL_NIBBLE6_RLM_SEL */ -/* Description: Nibble 6 RLM select */ -#define SH_XN_DEBUG_SEL_NIBBLE6_RLM_SEL_SHFT 48 -#define SH_XN_DEBUG_SEL_NIBBLE6_RLM_SEL_MASK 0x0007000000000000 - -/* SH_XN_DEBUG_SEL_NIBBLE6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_XN_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52 -#define SH_XN_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_XN_DEBUG_SEL_NIBBLE7_RLM_SEL */ -/* Description: Nibble 7 RLM select */ -#define SH_XN_DEBUG_SEL_NIBBLE7_RLM_SEL_SHFT 56 -#define SH_XN_DEBUG_SEL_NIBBLE7_RLM_SEL_MASK 0x0700000000000000 - -/* SH_XN_DEBUG_SEL_NIBBLE7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_XN_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60 -#define SH_XN_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* SH_XN_DEBUG_SEL_TRIGGER_ENABLE */ -/* Description: Enable trigger on bit 32 of Analyzer data */ -#define SH_XN_DEBUG_SEL_TRIGGER_ENABLE_SHFT 63 -#define SH_XN_DEBUG_SEL_TRIGGER_ENABLE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_XN_DEBUG_TRIG_SEL" */ -/* XN Debug trigger Select */ -/* ==================================================================== */ - -#define SH_XN_DEBUG_TRIG_SEL 0x0000000150031020 -#define SH_XN_DEBUG_TRIG_SEL_MASK 0x7777777777777777 -#define SH_XN_DEBUG_TRIG_SEL_INIT 0x0000000000000000 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER0_RLM_SEL */ -/* Description: Nibble 0 RLM select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER0_RLM_SEL_SHFT 0 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER0_RLM_SEL_MASK 0x0000000000000007 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL_SHFT 4 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER1_RLM_SEL */ -/* Description: Nibble 1 RLM select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER1_RLM_SEL_SHFT 8 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER1_RLM_SEL_MASK 0x0000000000000700 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL_SHFT 12 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER2_RLM_SEL */ -/* Description: Nibble 2 RLM select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER2_RLM_SEL_SHFT 16 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER2_RLM_SEL_MASK 0x0000000000070000 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL_SHFT 20 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER3_RLM_SEL */ -/* Description: Nibble 3 RLM select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER3_RLM_SEL_SHFT 24 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER3_RLM_SEL_MASK 0x0000000007000000 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL_SHFT 28 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER4_RLM_SEL */ -/* Description: Nibble 4 RLM select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER4_RLM_SEL_SHFT 32 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER4_RLM_SEL_MASK 0x0000000700000000 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL_SHFT 36 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER5_RLM_SEL */ -/* Description: Nibble 5 RLM select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER5_RLM_SEL_SHFT 40 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER5_RLM_SEL_MASK 0x0000070000000000 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL_SHFT 44 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER6_RLM_SEL */ -/* Description: Nibble 6 RLM select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER6_RLM_SEL_SHFT 48 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER6_RLM_SEL_MASK 0x0007000000000000 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL_SHFT 52 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER7_RLM_SEL */ -/* Description: Nibble 7 RLM select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER7_RLM_SEL_SHFT 56 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER7_RLM_SEL_MASK 0x0700000000000000 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL_SHFT 60 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* ==================================================================== */ -/* Register "SH_XN_TRIGGER_COMPARE" */ -/* XN Debug Compare */ -/* ==================================================================== */ - -#define SH_XN_TRIGGER_COMPARE 0x0000000150031040 -#define SH_XN_TRIGGER_COMPARE_MASK 0x00000000ffffffff -#define SH_XN_TRIGGER_COMPARE_INIT 0x0000000000000000 - -/* SH_XN_TRIGGER_COMPARE_MASK */ -/* Description: Mask to select Debug bits for trigger generation */ -#define SH_XN_TRIGGER_COMPARE_MASK_SHFT 0 -#define SH_XN_TRIGGER_COMPARE_MASK_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_XN_TRIGGER_DATA" */ -/* XN Debug Compare Data */ -/* ==================================================================== */ - -#define SH_XN_TRIGGER_DATA 0x0000000150031050 -#define SH_XN_TRIGGER_DATA_MASK 0x00000000ffffffff -#define SH_XN_TRIGGER_DATA_INIT 0x00000000ffffffff - -/* SH_XN_TRIGGER_DATA_COMPARE_PATTERN */ -/* Description: debug bit pattern for trigger generation */ -#define SH_XN_TRIGGER_DATA_COMPARE_PATTERN_SHFT 0 -#define SH_XN_TRIGGER_DATA_COMPARE_PATTERN_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_DEBUG_SEL" */ -/* XN IILB Debug Port Select */ -/* ==================================================================== */ - -#define SH_XN_IILB_DEBUG_SEL 0x0000000150031060 -#define SH_XN_IILB_DEBUG_SEL_MASK 0x7777777777777777 -#define SH_XN_IILB_DEBUG_SEL_INIT 0x0000000000000000 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE0_INPUT_SEL */ -/* Description: Nibble 0 input select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE0_INPUT_SEL_SHFT 0 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE1_INPUT_SEL */ -/* Description: Nibble 1 input select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE1_INPUT_SEL_SHFT 8 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE2_INPUT_SEL */ -/* Description: Nibble 2 input select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE2_INPUT_SEL_SHFT 16 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE3_INPUT_SEL */ -/* Description: Nibble 3 input select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE3_INPUT_SEL_SHFT 24 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE4_INPUT_SEL */ -/* Description: Nibble 4 input select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE4_INPUT_SEL_SHFT 32 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE5_INPUT_SEL */ -/* Description: Nibble 5 input select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE5_INPUT_SEL_SHFT 40 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE6_INPUT_SEL */ -/* Description: Nibble 6 input select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE6_INPUT_SEL_SHFT 48 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE7_INPUT_SEL */ -/* Description: Nibble 7 input select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE7_INPUT_SEL_SHFT 56 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* ==================================================================== */ -/* Register "SH_XN_PI_DEBUG_SEL" */ -/* XN PI Debug Port Select */ -/* ==================================================================== */ - -#define SH_XN_PI_DEBUG_SEL 0x00000001500310a0 -#define SH_XN_PI_DEBUG_SEL_MASK 0x7777777777777777 -#define SH_XN_PI_DEBUG_SEL_INIT 0x0000000000000000 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE0_INPUT_SEL */ -/* Description: Nibble 0 input select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE0_INPUT_SEL_SHFT 0 -#define SH_XN_PI_DEBUG_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4 -#define SH_XN_PI_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE1_INPUT_SEL */ -/* Description: Nibble 1 input select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE1_INPUT_SEL_SHFT 8 -#define SH_XN_PI_DEBUG_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12 -#define SH_XN_PI_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE2_INPUT_SEL */ -/* Description: Nibble 2 input select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE2_INPUT_SEL_SHFT 16 -#define SH_XN_PI_DEBUG_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20 -#define SH_XN_PI_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE3_INPUT_SEL */ -/* Description: Nibble 3 input select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE3_INPUT_SEL_SHFT 24 -#define SH_XN_PI_DEBUG_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28 -#define SH_XN_PI_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE4_INPUT_SEL */ -/* Description: Nibble 4 input select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE4_INPUT_SEL_SHFT 32 -#define SH_XN_PI_DEBUG_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36 -#define SH_XN_PI_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE5_INPUT_SEL */ -/* Description: Nibble 5 input select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE5_INPUT_SEL_SHFT 40 -#define SH_XN_PI_DEBUG_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44 -#define SH_XN_PI_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE6_INPUT_SEL */ -/* Description: Nibble 6 input select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE6_INPUT_SEL_SHFT 48 -#define SH_XN_PI_DEBUG_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52 -#define SH_XN_PI_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE7_INPUT_SEL */ -/* Description: Nibble 7 input select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE7_INPUT_SEL_SHFT 56 -#define SH_XN_PI_DEBUG_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60 -#define SH_XN_PI_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* ==================================================================== */ -/* Register "SH_XN_MD_DEBUG_SEL" */ -/* XN MD Debug Port Select */ -/* ==================================================================== */ - -#define SH_XN_MD_DEBUG_SEL 0x0000000150031080 -#define SH_XN_MD_DEBUG_SEL_MASK 0x7777777777777777 -#define SH_XN_MD_DEBUG_SEL_INIT 0x0000000000000000 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE0_INPUT_SEL */ -/* Description: Nibble 0 input select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE0_INPUT_SEL_SHFT 0 -#define SH_XN_MD_DEBUG_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4 -#define SH_XN_MD_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE1_INPUT_SEL */ -/* Description: Nibble 1 input select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE1_INPUT_SEL_SHFT 8 -#define SH_XN_MD_DEBUG_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12 -#define SH_XN_MD_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE2_INPUT_SEL */ -/* Description: Nibble 2 input select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE2_INPUT_SEL_SHFT 16 -#define SH_XN_MD_DEBUG_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20 -#define SH_XN_MD_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE3_INPUT_SEL */ -/* Description: Nibble 3 input select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE3_INPUT_SEL_SHFT 24 -#define SH_XN_MD_DEBUG_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28 -#define SH_XN_MD_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE4_INPUT_SEL */ -/* Description: Nibble 4 input select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE4_INPUT_SEL_SHFT 32 -#define SH_XN_MD_DEBUG_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36 -#define SH_XN_MD_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE5_INPUT_SEL */ -/* Description: Nibble 5 input select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE5_INPUT_SEL_SHFT 40 -#define SH_XN_MD_DEBUG_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44 -#define SH_XN_MD_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE6_INPUT_SEL */ -/* Description: Nibble 6 input select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE6_INPUT_SEL_SHFT 48 -#define SH_XN_MD_DEBUG_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52 -#define SH_XN_MD_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE7_INPUT_SEL */ -/* Description: Nibble 7 input select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE7_INPUT_SEL_SHFT 56 -#define SH_XN_MD_DEBUG_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60 -#define SH_XN_MD_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* ==================================================================== */ -/* Register "SH_XN_NI0_DEBUG_SEL" */ -/* XN NI0 Debug Port Select */ -/* ==================================================================== */ - -#define SH_XN_NI0_DEBUG_SEL 0x00000001500310c0 -#define SH_XN_NI0_DEBUG_SEL_MASK 0x7777777777777777 -#define SH_XN_NI0_DEBUG_SEL_INIT 0x0000000000000000 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE0_INPUT_SEL */ -/* Description: Nibble 0 input select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE0_INPUT_SEL_SHFT 0 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE1_INPUT_SEL */ -/* Description: Nibble 1 input select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE1_INPUT_SEL_SHFT 8 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE2_INPUT_SEL */ -/* Description: Nibble 2 input select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE2_INPUT_SEL_SHFT 16 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE3_INPUT_SEL */ -/* Description: Nibble 3 input select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE3_INPUT_SEL_SHFT 24 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE4_INPUT_SEL */ -/* Description: Nibble 4 input select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE4_INPUT_SEL_SHFT 32 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE5_INPUT_SEL */ -/* Description: Nibble 5 input select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE5_INPUT_SEL_SHFT 40 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE6_INPUT_SEL */ -/* Description: Nibble 6 input select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE6_INPUT_SEL_SHFT 48 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE7_INPUT_SEL */ -/* Description: Nibble 7 input select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE7_INPUT_SEL_SHFT 56 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* ==================================================================== */ -/* Register "SH_XN_NI1_DEBUG_SEL" */ -/* XN NI1 Debug Port Select */ -/* ==================================================================== */ - -#define SH_XN_NI1_DEBUG_SEL 0x00000001500310e0 -#define SH_XN_NI1_DEBUG_SEL_MASK 0x7777777777777777 -#define SH_XN_NI1_DEBUG_SEL_INIT 0x0000000000000000 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE0_INPUT_SEL */ -/* Description: Nibble 0 input select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE0_INPUT_SEL_SHFT 0 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE1_INPUT_SEL */ -/* Description: Nibble 1 input select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE1_INPUT_SEL_SHFT 8 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE2_INPUT_SEL */ -/* Description: Nibble 2 input select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE2_INPUT_SEL_SHFT 16 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE3_INPUT_SEL */ -/* Description: Nibble 3 input select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE3_INPUT_SEL_SHFT 24 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE4_INPUT_SEL */ -/* Description: Nibble 4 input select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE4_INPUT_SEL_SHFT 32 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE5_INPUT_SEL */ -/* Description: Nibble 5 input select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE5_INPUT_SEL_SHFT 40 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE6_INPUT_SEL */ -/* Description: Nibble 6 input select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE6_INPUT_SEL_SHFT 48 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE7_INPUT_SEL */ -/* Description: Nibble 7 input select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE7_INPUT_SEL_SHFT 56 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* ==================================================================== */ -/* Register "SH_XN_IILB_LB_CMP_EXP_DATA0" */ -/* IILB compare LB input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_IILB_LB_CMP_EXP_DATA0 0x0000000150031100 -#define SH_XN_IILB_LB_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_IILB_LB_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_IILB_LB_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_IILB_LB_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_IILB_LB_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_LB_CMP_EXP_DATA1" */ -/* IILB compare LB input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_IILB_LB_CMP_EXP_DATA1 0x0000000150031110 -#define SH_XN_IILB_LB_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_IILB_LB_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_IILB_LB_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_IILB_LB_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_IILB_LB_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_LB_CMP_ENABLE0" */ -/* IILB compare LB input enable0 */ -/* ==================================================================== */ - -#define SH_XN_IILB_LB_CMP_ENABLE0 0x0000000150031120 -#define SH_XN_IILB_LB_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_IILB_LB_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_IILB_LB_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_IILB_LB_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_IILB_LB_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_LB_CMP_ENABLE1" */ -/* IILB compare LB input enable1 */ -/* ==================================================================== */ - -#define SH_XN_IILB_LB_CMP_ENABLE1 0x0000000150031130 -#define SH_XN_IILB_LB_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_IILB_LB_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_IILB_LB_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_IILB_LB_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_IILB_LB_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_II_CMP_EXP_DATA0" */ -/* IILB compare II input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_IILB_II_CMP_EXP_DATA0 0x0000000150031140 -#define SH_XN_IILB_II_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_IILB_II_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_IILB_II_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_IILB_II_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_IILB_II_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_II_CMP_EXP_DATA1" */ -/* IILB compare II input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_IILB_II_CMP_EXP_DATA1 0x0000000150031150 -#define SH_XN_IILB_II_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_IILB_II_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_IILB_II_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_IILB_II_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_IILB_II_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_II_CMP_ENABLE0" */ -/* IILB compare II input enable0 */ -/* ==================================================================== */ - -#define SH_XN_IILB_II_CMP_ENABLE0 0x0000000150031160 -#define SH_XN_IILB_II_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_IILB_II_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_IILB_II_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_IILB_II_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_IILB_II_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_II_CMP_ENABLE1" */ -/* IILB compare II input enable1 */ -/* ==================================================================== */ - -#define SH_XN_IILB_II_CMP_ENABLE1 0x0000000150031170 -#define SH_XN_IILB_II_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_IILB_II_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_IILB_II_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_IILB_II_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_IILB_II_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_MD_CMP_EXP_DATA0" */ -/* IILB compare MD input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_IILB_MD_CMP_EXP_DATA0 0x0000000150031180 -#define SH_XN_IILB_MD_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_IILB_MD_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_IILB_MD_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_IILB_MD_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_IILB_MD_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_MD_CMP_EXP_DATA1" */ -/* IILB compare MD input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_IILB_MD_CMP_EXP_DATA1 0x0000000150031190 -#define SH_XN_IILB_MD_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_IILB_MD_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_IILB_MD_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_IILB_MD_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_IILB_MD_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_MD_CMP_ENABLE0" */ -/* IILB compare MD input enable0 */ -/* ==================================================================== */ - -#define SH_XN_IILB_MD_CMP_ENABLE0 0x00000001500311a0 -#define SH_XN_IILB_MD_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_IILB_MD_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_IILB_MD_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_IILB_MD_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_IILB_MD_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_MD_CMP_ENABLE1" */ -/* IILB compare MD input enable1 */ -/* ==================================================================== */ - -#define SH_XN_IILB_MD_CMP_ENABLE1 0x00000001500311b0 -#define SH_XN_IILB_MD_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_IILB_MD_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_IILB_MD_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_IILB_MD_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_IILB_MD_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_PI_CMP_EXP_DATA0" */ -/* IILB compare PI input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_IILB_PI_CMP_EXP_DATA0 0x00000001500311c0 -#define SH_XN_IILB_PI_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_IILB_PI_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_IILB_PI_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_IILB_PI_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_IILB_PI_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_PI_CMP_EXP_DATA1" */ -/* IILB compare PI input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_IILB_PI_CMP_EXP_DATA1 0x00000001500311d0 -#define SH_XN_IILB_PI_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_IILB_PI_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_IILB_PI_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_IILB_PI_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_IILB_PI_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_PI_CMP_ENABLE0" */ -/* IILB compare PI input enable0 */ -/* ==================================================================== */ - -#define SH_XN_IILB_PI_CMP_ENABLE0 0x00000001500311e0 -#define SH_XN_IILB_PI_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_IILB_PI_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_IILB_PI_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_IILB_PI_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_IILB_PI_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_PI_CMP_ENABLE1" */ -/* IILB compare PI input enable1 */ -/* ==================================================================== */ - -#define SH_XN_IILB_PI_CMP_ENABLE1 0x00000001500311f0 -#define SH_XN_IILB_PI_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_IILB_PI_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_IILB_PI_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_IILB_PI_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_IILB_PI_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_NI0_CMP_EXP_DATA0" */ -/* IILB compare NI0 input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_IILB_NI0_CMP_EXP_DATA0 0x0000000150031200 -#define SH_XN_IILB_NI0_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_IILB_NI0_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_IILB_NI0_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_IILB_NI0_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_IILB_NI0_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_NI0_CMP_EXP_DATA1" */ -/* IILB compare NI0 input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_IILB_NI0_CMP_EXP_DATA1 0x0000000150031210 -#define SH_XN_IILB_NI0_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_IILB_NI0_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_IILB_NI0_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_IILB_NI0_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_IILB_NI0_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_NI0_CMP_ENABLE0" */ -/* IILB compare NI0 input enable0 */ -/* ==================================================================== */ - -#define SH_XN_IILB_NI0_CMP_ENABLE0 0x0000000150031220 -#define SH_XN_IILB_NI0_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_IILB_NI0_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_IILB_NI0_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_IILB_NI0_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_IILB_NI0_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_NI0_CMP_ENABLE1" */ -/* IILB compare NI0 input enable1 */ -/* ==================================================================== */ - -#define SH_XN_IILB_NI0_CMP_ENABLE1 0x0000000150031230 -#define SH_XN_IILB_NI0_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_IILB_NI0_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_IILB_NI0_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_IILB_NI0_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_IILB_NI0_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_NI1_CMP_EXP_DATA0" */ -/* IILB compare NI1 input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_IILB_NI1_CMP_EXP_DATA0 0x0000000150031240 -#define SH_XN_IILB_NI1_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_IILB_NI1_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_IILB_NI1_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_IILB_NI1_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_IILB_NI1_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_NI1_CMP_EXP_DATA1" */ -/* IILB compare NI1 input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_IILB_NI1_CMP_EXP_DATA1 0x0000000150031250 -#define SH_XN_IILB_NI1_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_IILB_NI1_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_IILB_NI1_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_IILB_NI1_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_IILB_NI1_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_NI1_CMP_ENABLE0" */ -/* IILB compare NI1 input enable0 */ -/* ==================================================================== */ - -#define SH_XN_IILB_NI1_CMP_ENABLE0 0x0000000150031260 -#define SH_XN_IILB_NI1_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_IILB_NI1_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_IILB_NI1_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_IILB_NI1_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_IILB_NI1_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_NI1_CMP_ENABLE1" */ -/* IILB compare NI1 input enable1 */ -/* ==================================================================== */ - -#define SH_XN_IILB_NI1_CMP_ENABLE1 0x0000000150031270 -#define SH_XN_IILB_NI1_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_IILB_NI1_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_IILB_NI1_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_IILB_NI1_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_IILB_NI1_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_IILB_CMP_EXP_DATA0" */ -/* MD compare IILB input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_MD_IILB_CMP_EXP_DATA0 0x0000000150031500 -#define SH_XN_MD_IILB_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_MD_IILB_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_MD_IILB_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_MD_IILB_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_MD_IILB_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_IILB_CMP_EXP_DATA1" */ -/* MD compare IILB input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_MD_IILB_CMP_EXP_DATA1 0x0000000150031510 -#define SH_XN_MD_IILB_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_MD_IILB_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_MD_IILB_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_MD_IILB_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_MD_IILB_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_IILB_CMP_ENABLE0" */ -/* MD compare IILB input enable0 */ -/* ==================================================================== */ - -#define SH_XN_MD_IILB_CMP_ENABLE0 0x0000000150031520 -#define SH_XN_MD_IILB_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_MD_IILB_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_MD_IILB_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_MD_IILB_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_MD_IILB_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_IILB_CMP_ENABLE1" */ -/* MD compare IILB input enable1 */ -/* ==================================================================== */ - -#define SH_XN_MD_IILB_CMP_ENABLE1 0x0000000150031530 -#define SH_XN_MD_IILB_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_MD_IILB_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_MD_IILB_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_MD_IILB_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_MD_IILB_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_NI0_CMP_EXP_DATA0" */ -/* MD compare NI0 input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_MD_NI0_CMP_EXP_DATA0 0x0000000150031540 -#define SH_XN_MD_NI0_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_MD_NI0_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_MD_NI0_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_MD_NI0_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_MD_NI0_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_NI0_CMP_EXP_DATA1" */ -/* MD compare NI0 input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_MD_NI0_CMP_EXP_DATA1 0x0000000150031550 -#define SH_XN_MD_NI0_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_MD_NI0_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_MD_NI0_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_MD_NI0_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_MD_NI0_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_NI0_CMP_ENABLE0" */ -/* MD compare NI0 input enable0 */ -/* ==================================================================== */ - -#define SH_XN_MD_NI0_CMP_ENABLE0 0x0000000150031560 -#define SH_XN_MD_NI0_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_MD_NI0_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_MD_NI0_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_MD_NI0_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_MD_NI0_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_NI0_CMP_ENABLE1" */ -/* MD compare NI0 input enable1 */ -/* ==================================================================== */ - -#define SH_XN_MD_NI0_CMP_ENABLE1 0x0000000150031570 -#define SH_XN_MD_NI0_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_MD_NI0_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_MD_NI0_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_MD_NI0_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_MD_NI0_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_NI1_CMP_EXP_DATA0" */ -/* MD compare NI1 input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_MD_NI1_CMP_EXP_DATA0 0x0000000150031580 -#define SH_XN_MD_NI1_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_MD_NI1_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_MD_NI1_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_MD_NI1_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_MD_NI1_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_NI1_CMP_EXP_DATA1" */ -/* MD compare NI1 input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_MD_NI1_CMP_EXP_DATA1 0x0000000150031590 -#define SH_XN_MD_NI1_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_MD_NI1_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_MD_NI1_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_MD_NI1_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_MD_NI1_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_NI1_CMP_ENABLE0" */ -/* MD compare NI1 input enable0 */ -/* ==================================================================== */ - -#define SH_XN_MD_NI1_CMP_ENABLE0 0x00000001500315a0 -#define SH_XN_MD_NI1_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_MD_NI1_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_MD_NI1_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_MD_NI1_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_MD_NI1_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_NI1_CMP_ENABLE1" */ -/* MD compare NI1 input enable1 */ -/* ==================================================================== */ - -#define SH_XN_MD_NI1_CMP_ENABLE1 0x00000001500315b0 -#define SH_XN_MD_NI1_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_MD_NI1_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_MD_NI1_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_MD_NI1_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_MD_NI1_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_EXP_HDR0" */ -/* MD compare SIC input expected header0 */ -/* ==================================================================== */ - -#define SH_XN_MD_SIC_CMP_EXP_HDR0 0x00000001500315c0 -#define SH_XN_MD_SIC_CMP_EXP_HDR0_MASK 0xffffffffffffffff -#define SH_XN_MD_SIC_CMP_EXP_HDR0_INIT 0x0000000000000000 - -/* SH_XN_MD_SIC_CMP_EXP_HDR0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_MD_SIC_CMP_EXP_HDR0_DATA_SHFT 0 -#define SH_XN_MD_SIC_CMP_EXP_HDR0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_EXP_HDR1" */ -/* MD compare SIC input expected header1 */ -/* ==================================================================== */ - -#define SH_XN_MD_SIC_CMP_EXP_HDR1 0x00000001500315d0 -#define SH_XN_MD_SIC_CMP_EXP_HDR1_MASK 0x000003ffffffffff -#define SH_XN_MD_SIC_CMP_EXP_HDR1_INIT 0x0000000000000000 - -/* SH_XN_MD_SIC_CMP_EXP_HDR1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_MD_SIC_CMP_EXP_HDR1_DATA_SHFT 0 -#define SH_XN_MD_SIC_CMP_EXP_HDR1_DATA_MASK 0x000003ffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_HDR_ENABLE0" */ -/* MD compare SIC header enable0 */ -/* ==================================================================== */ - -#define SH_XN_MD_SIC_CMP_HDR_ENABLE0 0x00000001500315e0 -#define SH_XN_MD_SIC_CMP_HDR_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_MD_SIC_CMP_HDR_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_MD_SIC_CMP_HDR_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_MD_SIC_CMP_HDR_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_MD_SIC_CMP_HDR_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_HDR_ENABLE1" */ -/* MD compare SIC header enable1 */ -/* ==================================================================== */ - -#define SH_XN_MD_SIC_CMP_HDR_ENABLE1 0x00000001500315f0 -#define SH_XN_MD_SIC_CMP_HDR_ENABLE1_MASK 0x000003ffffffffff -#define SH_XN_MD_SIC_CMP_HDR_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_MD_SIC_CMP_HDR_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_MD_SIC_CMP_HDR_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_MD_SIC_CMP_HDR_ENABLE1_ENABLE_MASK 0x000003ffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_DATA0" */ -/* MD compare SIC data0 */ -/* ==================================================================== */ - -#define SH_XN_MD_SIC_CMP_DATA0 0x0000000150031600 -#define SH_XN_MD_SIC_CMP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_MD_SIC_CMP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_MD_SIC_CMP_DATA0_DATA0 */ -/* Description: Data0 */ -#define SH_XN_MD_SIC_CMP_DATA0_DATA0_SHFT 0 -#define SH_XN_MD_SIC_CMP_DATA0_DATA0_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_DATA1" */ -/* MD compare SIC data1 */ -/* ==================================================================== */ - -#define SH_XN_MD_SIC_CMP_DATA1 0x0000000150031610 -#define SH_XN_MD_SIC_CMP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_MD_SIC_CMP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_MD_SIC_CMP_DATA1_DATA1 */ -/* Description: Data1 */ -#define SH_XN_MD_SIC_CMP_DATA1_DATA1_SHFT 0 -#define SH_XN_MD_SIC_CMP_DATA1_DATA1_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_DATA2" */ -/* MD compare SIC data2 */ -/* ==================================================================== */ - -#define SH_XN_MD_SIC_CMP_DATA2 0x0000000150031620 -#define SH_XN_MD_SIC_CMP_DATA2_MASK 0xffffffffffffffff -#define SH_XN_MD_SIC_CMP_DATA2_INIT 0x0000000000000000 - -/* SH_XN_MD_SIC_CMP_DATA2_DATA2 */ -/* Description: Data2 */ -#define SH_XN_MD_SIC_CMP_DATA2_DATA2_SHFT 0 -#define SH_XN_MD_SIC_CMP_DATA2_DATA2_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_DATA3" */ -/* MD compare SIC data3 */ -/* ==================================================================== */ - -#define SH_XN_MD_SIC_CMP_DATA3 0x0000000150031630 -#define SH_XN_MD_SIC_CMP_DATA3_MASK 0xffffffffffffffff -#define SH_XN_MD_SIC_CMP_DATA3_INIT 0x0000000000000000 - -/* SH_XN_MD_SIC_CMP_DATA3_DATA3 */ -/* Description: Data3 */ -#define SH_XN_MD_SIC_CMP_DATA3_DATA3_SHFT 0 -#define SH_XN_MD_SIC_CMP_DATA3_DATA3_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE0" */ -/* MD enable compare SIC data0 */ -/* ==================================================================== */ - -#define SH_XN_MD_SIC_CMP_DATA_ENABLE0 0x0000000150031640 -#define SH_XN_MD_SIC_CMP_DATA_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_MD_SIC_CMP_DATA_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_MD_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0 */ -/* Description: Data0 */ -#define SH_XN_MD_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0_SHFT 0 -#define SH_XN_MD_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE1" */ -/* MD enable compare SIC data1 */ -/* ==================================================================== */ - -#define SH_XN_MD_SIC_CMP_DATA_ENABLE1 0x0000000150031650 -#define SH_XN_MD_SIC_CMP_DATA_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_MD_SIC_CMP_DATA_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_MD_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1 */ -/* Description: Data1 */ -#define SH_XN_MD_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1_SHFT 0 -#define SH_XN_MD_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE2" */ -/* MD enable compare SIC data2 */ -/* ==================================================================== */ - -#define SH_XN_MD_SIC_CMP_DATA_ENABLE2 0x0000000150031660 -#define SH_XN_MD_SIC_CMP_DATA_ENABLE2_MASK 0xffffffffffffffff -#define SH_XN_MD_SIC_CMP_DATA_ENABLE2_INIT 0x0000000000000000 - -/* SH_XN_MD_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2 */ -/* Description: Data2 */ -#define SH_XN_MD_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2_SHFT 0 -#define SH_XN_MD_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE3" */ -/* MD enable compare SIC data3 */ -/* ==================================================================== */ - -#define SH_XN_MD_SIC_CMP_DATA_ENABLE3 0x0000000150031670 -#define SH_XN_MD_SIC_CMP_DATA_ENABLE3_MASK 0xffffffffffffffff -#define SH_XN_MD_SIC_CMP_DATA_ENABLE3_INIT 0x0000000000000000 - -/* SH_XN_MD_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3 */ -/* Description: Data3 */ -#define SH_XN_MD_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3_SHFT 0 -#define SH_XN_MD_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_IILB_CMP_EXP_DATA0" */ -/* PI compare IILB input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_PI_IILB_CMP_EXP_DATA0 0x0000000150031300 -#define SH_XN_PI_IILB_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_PI_IILB_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_PI_IILB_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_PI_IILB_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_PI_IILB_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_IILB_CMP_EXP_DATA1" */ -/* PI compare IILB input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_PI_IILB_CMP_EXP_DATA1 0x0000000150031310 -#define SH_XN_PI_IILB_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_PI_IILB_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_PI_IILB_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_PI_IILB_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_PI_IILB_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_IILB_CMP_ENABLE0" */ -/* PI compare IILB input enable0 */ -/* ==================================================================== */ - -#define SH_XN_PI_IILB_CMP_ENABLE0 0x0000000150031320 -#define SH_XN_PI_IILB_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_PI_IILB_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_PI_IILB_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_PI_IILB_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_PI_IILB_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_IILB_CMP_ENABLE1" */ -/* PI compare IILB input enable1 */ -/* ==================================================================== */ - -#define SH_XN_PI_IILB_CMP_ENABLE1 0x0000000150031330 -#define SH_XN_PI_IILB_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_PI_IILB_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_PI_IILB_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_PI_IILB_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_PI_IILB_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_NI0_CMP_EXP_DATA0" */ -/* PI compare NI0 input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_PI_NI0_CMP_EXP_DATA0 0x0000000150031340 -#define SH_XN_PI_NI0_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_PI_NI0_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_PI_NI0_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_PI_NI0_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_PI_NI0_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_NI0_CMP_EXP_DATA1" */ -/* PI compare NI0 input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_PI_NI0_CMP_EXP_DATA1 0x0000000150031350 -#define SH_XN_PI_NI0_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_PI_NI0_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_PI_NI0_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_PI_NI0_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_PI_NI0_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_NI0_CMP_ENABLE0" */ -/* PI compare NI0 input enable0 */ -/* ==================================================================== */ - -#define SH_XN_PI_NI0_CMP_ENABLE0 0x0000000150031360 -#define SH_XN_PI_NI0_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_PI_NI0_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_PI_NI0_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_PI_NI0_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_PI_NI0_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_NI0_CMP_ENABLE1" */ -/* PI compare NI0 input enable1 */ -/* ==================================================================== */ - -#define SH_XN_PI_NI0_CMP_ENABLE1 0x0000000150031370 -#define SH_XN_PI_NI0_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_PI_NI0_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_PI_NI0_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_PI_NI0_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_PI_NI0_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_NI1_CMP_EXP_DATA0" */ -/* PI compare NI1 input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_PI_NI1_CMP_EXP_DATA0 0x0000000150031380 -#define SH_XN_PI_NI1_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_PI_NI1_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_PI_NI1_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_PI_NI1_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_PI_NI1_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_NI1_CMP_EXP_DATA1" */ -/* PI compare NI1 input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_PI_NI1_CMP_EXP_DATA1 0x0000000150031390 -#define SH_XN_PI_NI1_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_PI_NI1_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_PI_NI1_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_PI_NI1_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_PI_NI1_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_NI1_CMP_ENABLE0" */ -/* PI compare NI1 input enable0 */ -/* ==================================================================== */ - -#define SH_XN_PI_NI1_CMP_ENABLE0 0x00000001500313a0 -#define SH_XN_PI_NI1_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_PI_NI1_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_PI_NI1_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_PI_NI1_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_PI_NI1_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_NI1_CMP_ENABLE1" */ -/* PI compare NI1 input enable1 */ -/* ==================================================================== */ - -#define SH_XN_PI_NI1_CMP_ENABLE1 0x00000001500313b0 -#define SH_XN_PI_NI1_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_PI_NI1_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_PI_NI1_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_PI_NI1_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_PI_NI1_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_EXP_HDR0" */ -/* PI compare SIC input expected header0 */ -/* ==================================================================== */ - -#define SH_XN_PI_SIC_CMP_EXP_HDR0 0x00000001500313c0 -#define SH_XN_PI_SIC_CMP_EXP_HDR0_MASK 0xffffffffffffffff -#define SH_XN_PI_SIC_CMP_EXP_HDR0_INIT 0x0000000000000000 - -/* SH_XN_PI_SIC_CMP_EXP_HDR0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_PI_SIC_CMP_EXP_HDR0_DATA_SHFT 0 -#define SH_XN_PI_SIC_CMP_EXP_HDR0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_EXP_HDR1" */ -/* PI compare SIC input expected header1 */ -/* ==================================================================== */ - -#define SH_XN_PI_SIC_CMP_EXP_HDR1 0x00000001500313d0 -#define SH_XN_PI_SIC_CMP_EXP_HDR1_MASK 0x000003ffffffffff -#define SH_XN_PI_SIC_CMP_EXP_HDR1_INIT 0x0000000000000000 - -/* SH_XN_PI_SIC_CMP_EXP_HDR1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_PI_SIC_CMP_EXP_HDR1_DATA_SHFT 0 -#define SH_XN_PI_SIC_CMP_EXP_HDR1_DATA_MASK 0x000003ffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_HDR_ENABLE0" */ -/* PI compare SIC header enable0 */ -/* ==================================================================== */ - -#define SH_XN_PI_SIC_CMP_HDR_ENABLE0 0x00000001500313e0 -#define SH_XN_PI_SIC_CMP_HDR_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_PI_SIC_CMP_HDR_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_PI_SIC_CMP_HDR_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_PI_SIC_CMP_HDR_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_PI_SIC_CMP_HDR_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_HDR_ENABLE1" */ -/* PI compare SIC header enable1 */ -/* ==================================================================== */ - -#define SH_XN_PI_SIC_CMP_HDR_ENABLE1 0x00000001500313f0 -#define SH_XN_PI_SIC_CMP_HDR_ENABLE1_MASK 0x000003ffffffffff -#define SH_XN_PI_SIC_CMP_HDR_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_PI_SIC_CMP_HDR_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_PI_SIC_CMP_HDR_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_PI_SIC_CMP_HDR_ENABLE1_ENABLE_MASK 0x000003ffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_DATA0" */ -/* PI compare SIC data0 */ -/* ==================================================================== */ - -#define SH_XN_PI_SIC_CMP_DATA0 0x0000000150031400 -#define SH_XN_PI_SIC_CMP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_PI_SIC_CMP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_PI_SIC_CMP_DATA0_DATA0 */ -/* Description: Data0 */ -#define SH_XN_PI_SIC_CMP_DATA0_DATA0_SHFT 0 -#define SH_XN_PI_SIC_CMP_DATA0_DATA0_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_DATA1" */ -/* PI compare SIC data1 */ -/* ==================================================================== */ - -#define SH_XN_PI_SIC_CMP_DATA1 0x0000000150031410 -#define SH_XN_PI_SIC_CMP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_PI_SIC_CMP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_PI_SIC_CMP_DATA1_DATA1 */ -/* Description: Data1 */ -#define SH_XN_PI_SIC_CMP_DATA1_DATA1_SHFT 0 -#define SH_XN_PI_SIC_CMP_DATA1_DATA1_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_DATA2" */ -/* PI compare SIC data2 */ -/* ==================================================================== */ - -#define SH_XN_PI_SIC_CMP_DATA2 0x0000000150031420 -#define SH_XN_PI_SIC_CMP_DATA2_MASK 0xffffffffffffffff -#define SH_XN_PI_SIC_CMP_DATA2_INIT 0x0000000000000000 - -/* SH_XN_PI_SIC_CMP_DATA2_DATA2 */ -/* Description: Data2 */ -#define SH_XN_PI_SIC_CMP_DATA2_DATA2_SHFT 0 -#define SH_XN_PI_SIC_CMP_DATA2_DATA2_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_DATA3" */ -/* PI compare SIC data3 */ -/* ==================================================================== */ - -#define SH_XN_PI_SIC_CMP_DATA3 0x0000000150031430 -#define SH_XN_PI_SIC_CMP_DATA3_MASK 0xffffffffffffffff -#define SH_XN_PI_SIC_CMP_DATA3_INIT 0x0000000000000000 - -/* SH_XN_PI_SIC_CMP_DATA3_DATA3 */ -/* Description: Data3 */ -#define SH_XN_PI_SIC_CMP_DATA3_DATA3_SHFT 0 -#define SH_XN_PI_SIC_CMP_DATA3_DATA3_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE0" */ -/* PI enable compare SIC data0 */ -/* ==================================================================== */ - -#define SH_XN_PI_SIC_CMP_DATA_ENABLE0 0x0000000150031440 -#define SH_XN_PI_SIC_CMP_DATA_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_PI_SIC_CMP_DATA_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_PI_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0 */ -/* Description: Data0 */ -#define SH_XN_PI_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0_SHFT 0 -#define SH_XN_PI_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE1" */ -/* PI enable compare SIC data1 */ -/* ==================================================================== */ - -#define SH_XN_PI_SIC_CMP_DATA_ENABLE1 0x0000000150031450 -#define SH_XN_PI_SIC_CMP_DATA_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_PI_SIC_CMP_DATA_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_PI_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1 */ -/* Description: Data1 */ -#define SH_XN_PI_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1_SHFT 0 -#define SH_XN_PI_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE2" */ -/* PI enable compare SIC data2 */ -/* ==================================================================== */ - -#define SH_XN_PI_SIC_CMP_DATA_ENABLE2 0x0000000150031460 -#define SH_XN_PI_SIC_CMP_DATA_ENABLE2_MASK 0xffffffffffffffff -#define SH_XN_PI_SIC_CMP_DATA_ENABLE2_INIT 0x0000000000000000 - -/* SH_XN_PI_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2 */ -/* Description: Data2 */ -#define SH_XN_PI_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2_SHFT 0 -#define SH_XN_PI_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE3" */ -/* PI enable compare SIC data3 */ -/* ==================================================================== */ - -#define SH_XN_PI_SIC_CMP_DATA_ENABLE3 0x0000000150031470 -#define SH_XN_PI_SIC_CMP_DATA_ENABLE3_MASK 0xffffffffffffffff -#define SH_XN_PI_SIC_CMP_DATA_ENABLE3_INIT 0x0000000000000000 - -/* SH_XN_PI_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3 */ -/* Description: Data3 */ -#define SH_XN_PI_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3_SHFT 0 -#define SH_XN_PI_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_IILB_CMP_EXP_DATA0" */ -/* NI0 compare IILB input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_NI0_IILB_CMP_EXP_DATA0 0x0000000150031700 -#define SH_XN_NI0_IILB_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_NI0_IILB_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_NI0_IILB_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_NI0_IILB_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_NI0_IILB_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_IILB_CMP_EXP_DATA1" */ -/* NI0 compare IILB input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_NI0_IILB_CMP_EXP_DATA1 0x0000000150031710 -#define SH_XN_NI0_IILB_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_NI0_IILB_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_NI0_IILB_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_NI0_IILB_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_NI0_IILB_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_IILB_CMP_ENABLE0" */ -/* NI0 compare IILB input enable0 */ -/* ==================================================================== */ - -#define SH_XN_NI0_IILB_CMP_ENABLE0 0x0000000150031720 -#define SH_XN_NI0_IILB_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_NI0_IILB_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_NI0_IILB_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_NI0_IILB_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_NI0_IILB_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_IILB_CMP_ENABLE1" */ -/* NI0 compare IILB input enable1 */ -/* ==================================================================== */ - -#define SH_XN_NI0_IILB_CMP_ENABLE1 0x0000000150031730 -#define SH_XN_NI0_IILB_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_NI0_IILB_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_NI0_IILB_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_NI0_IILB_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_NI0_IILB_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_PI_CMP_EXP_DATA0" */ -/* NI0 compare PI input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_NI0_PI_CMP_EXP_DATA0 0x0000000150031740 -#define SH_XN_NI0_PI_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_NI0_PI_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_NI0_PI_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_NI0_PI_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_NI0_PI_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_PI_CMP_EXP_DATA1" */ -/* NI0 compare PI input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_NI0_PI_CMP_EXP_DATA1 0x0000000150031750 -#define SH_XN_NI0_PI_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_NI0_PI_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_NI0_PI_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_NI0_PI_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_NI0_PI_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_PI_CMP_ENABLE0" */ -/* NI0 compare PI input enable0 */ -/* ==================================================================== */ - -#define SH_XN_NI0_PI_CMP_ENABLE0 0x0000000150031760 -#define SH_XN_NI0_PI_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_NI0_PI_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_NI0_PI_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_NI0_PI_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_NI0_PI_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_PI_CMP_ENABLE1" */ -/* NI0 compare PI input enable1 */ -/* ==================================================================== */ - -#define SH_XN_NI0_PI_CMP_ENABLE1 0x0000000150031770 -#define SH_XN_NI0_PI_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_NI0_PI_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_NI0_PI_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_NI0_PI_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_NI0_PI_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_MD_CMP_EXP_DATA0" */ -/* NI0 compare MD input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_NI0_MD_CMP_EXP_DATA0 0x0000000150031780 -#define SH_XN_NI0_MD_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_NI0_MD_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_NI0_MD_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_NI0_MD_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_NI0_MD_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_MD_CMP_EXP_DATA1" */ -/* NI0 compare MD input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_NI0_MD_CMP_EXP_DATA1 0x0000000150031790 -#define SH_XN_NI0_MD_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_NI0_MD_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_NI0_MD_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_NI0_MD_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_NI0_MD_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_MD_CMP_ENABLE0" */ -/* NI0 compare MD input enable0 */ -/* ==================================================================== */ - -#define SH_XN_NI0_MD_CMP_ENABLE0 0x00000001500317a0 -#define SH_XN_NI0_MD_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_NI0_MD_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_NI0_MD_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_NI0_MD_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_NI0_MD_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_MD_CMP_ENABLE1" */ -/* NI0 compare MD input enable1 */ -/* ==================================================================== */ - -#define SH_XN_NI0_MD_CMP_ENABLE1 0x00000001500317b0 -#define SH_XN_NI0_MD_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_NI0_MD_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_NI0_MD_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_NI0_MD_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_NI0_MD_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_NI_CMP_EXP_DATA0" */ -/* NI0 compare NI input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_NI0_NI_CMP_EXP_DATA0 0x00000001500317c0 -#define SH_XN_NI0_NI_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_NI0_NI_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_NI0_NI_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_NI0_NI_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_NI0_NI_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_NI_CMP_EXP_DATA1" */ -/* NI0 compare NI input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_NI0_NI_CMP_EXP_DATA1 0x00000001500317d0 -#define SH_XN_NI0_NI_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_NI0_NI_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_NI0_NI_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_NI0_NI_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_NI0_NI_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_NI_CMP_ENABLE0" */ -/* NI0 compare NI input enable0 */ -/* ==================================================================== */ - -#define SH_XN_NI0_NI_CMP_ENABLE0 0x00000001500317e0 -#define SH_XN_NI0_NI_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_NI0_NI_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_NI0_NI_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_NI0_NI_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_NI0_NI_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_NI_CMP_ENABLE1" */ -/* NI0 compare NI input enable1 */ -/* ==================================================================== */ - -#define SH_XN_NI0_NI_CMP_ENABLE1 0x00000001500317f0 -#define SH_XN_NI0_NI_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_NI0_NI_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_NI0_NI_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_NI0_NI_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_NI0_NI_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_LLP_CMP_EXP_DATA0" */ -/* NI0 compare LLP input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_NI0_LLP_CMP_EXP_DATA0 0x0000000150031800 -#define SH_XN_NI0_LLP_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_NI0_LLP_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_NI0_LLP_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_NI0_LLP_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_NI0_LLP_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_LLP_CMP_EXP_DATA1" */ -/* NI0 compare LLP input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_NI0_LLP_CMP_EXP_DATA1 0x0000000150031810 -#define SH_XN_NI0_LLP_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_NI0_LLP_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_NI0_LLP_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_NI0_LLP_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_NI0_LLP_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_LLP_CMP_ENABLE0" */ -/* NI0 compare LLP input enable0 */ -/* ==================================================================== */ - -#define SH_XN_NI0_LLP_CMP_ENABLE0 0x0000000150031820 -#define SH_XN_NI0_LLP_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_NI0_LLP_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_NI0_LLP_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_NI0_LLP_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_NI0_LLP_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_LLP_CMP_ENABLE1" */ -/* NI0 compare LLP input enable1 */ -/* ==================================================================== */ - -#define SH_XN_NI0_LLP_CMP_ENABLE1 0x0000000150031830 -#define SH_XN_NI0_LLP_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_NI0_LLP_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_NI0_LLP_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_NI0_LLP_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_NI0_LLP_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_IILB_CMP_EXP_DATA0" */ -/* NI1 compare IILB input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_NI1_IILB_CMP_EXP_DATA0 0x0000000150031900 -#define SH_XN_NI1_IILB_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_NI1_IILB_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_NI1_IILB_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_NI1_IILB_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_NI1_IILB_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_IILB_CMP_EXP_DATA1" */ -/* NI1 compare IILB input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_NI1_IILB_CMP_EXP_DATA1 0x0000000150031910 -#define SH_XN_NI1_IILB_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_NI1_IILB_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_NI1_IILB_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_NI1_IILB_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_NI1_IILB_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_IILB_CMP_ENABLE0" */ -/* NI1 compare IILB input enable0 */ -/* ==================================================================== */ - -#define SH_XN_NI1_IILB_CMP_ENABLE0 0x0000000150031920 -#define SH_XN_NI1_IILB_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_NI1_IILB_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_NI1_IILB_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_NI1_IILB_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_NI1_IILB_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_IILB_CMP_ENABLE1" */ -/* NI1 compare IILB input enable1 */ -/* ==================================================================== */ - -#define SH_XN_NI1_IILB_CMP_ENABLE1 0x0000000150031930 -#define SH_XN_NI1_IILB_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_NI1_IILB_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_NI1_IILB_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_NI1_IILB_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_NI1_IILB_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_PI_CMP_EXP_DATA0" */ -/* NI1 compare PI input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_NI1_PI_CMP_EXP_DATA0 0x0000000150031940 -#define SH_XN_NI1_PI_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_NI1_PI_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_NI1_PI_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_NI1_PI_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_NI1_PI_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_PI_CMP_EXP_DATA1" */ -/* NI1 compare PI input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_NI1_PI_CMP_EXP_DATA1 0x0000000150031950 -#define SH_XN_NI1_PI_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_NI1_PI_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_NI1_PI_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_NI1_PI_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_NI1_PI_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_PI_CMP_ENABLE0" */ -/* NI1 compare PI input enable0 */ -/* ==================================================================== */ - -#define SH_XN_NI1_PI_CMP_ENABLE0 0x0000000150031960 -#define SH_XN_NI1_PI_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_NI1_PI_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_NI1_PI_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_NI1_PI_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_NI1_PI_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_PI_CMP_ENABLE1" */ -/* NI1 compare PI input enable1 */ -/* ==================================================================== */ - -#define SH_XN_NI1_PI_CMP_ENABLE1 0x0000000150031970 -#define SH_XN_NI1_PI_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_NI1_PI_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_NI1_PI_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_NI1_PI_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_NI1_PI_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_MD_CMP_EXP_DATA0" */ -/* NI1 compare MD input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_NI1_MD_CMP_EXP_DATA0 0x0000000150031980 -#define SH_XN_NI1_MD_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_NI1_MD_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_NI1_MD_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_NI1_MD_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_NI1_MD_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_MD_CMP_EXP_DATA1" */ -/* NI1 compare MD input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_NI1_MD_CMP_EXP_DATA1 0x0000000150031990 -#define SH_XN_NI1_MD_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_NI1_MD_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_NI1_MD_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_NI1_MD_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_NI1_MD_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_MD_CMP_ENABLE0" */ -/* NI1 compare MD input enable0 */ -/* ==================================================================== */ - -#define SH_XN_NI1_MD_CMP_ENABLE0 0x00000001500319a0 -#define SH_XN_NI1_MD_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_NI1_MD_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_NI1_MD_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_NI1_MD_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_NI1_MD_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_MD_CMP_ENABLE1" */ -/* NI1 compare MD input enable1 */ -/* ==================================================================== */ - -#define SH_XN_NI1_MD_CMP_ENABLE1 0x00000001500319b0 -#define SH_XN_NI1_MD_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_NI1_MD_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_NI1_MD_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_NI1_MD_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_NI1_MD_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_NI_CMP_EXP_DATA0" */ -/* NI1 compare NI input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_NI1_NI_CMP_EXP_DATA0 0x00000001500319c0 -#define SH_XN_NI1_NI_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_NI1_NI_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_NI1_NI_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_NI1_NI_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_NI1_NI_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_NI_CMP_EXP_DATA1" */ -/* NI1 compare NI input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_NI1_NI_CMP_EXP_DATA1 0x00000001500319d0 -#define SH_XN_NI1_NI_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_NI1_NI_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_NI1_NI_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_NI1_NI_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_NI1_NI_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_NI_CMP_ENABLE0" */ -/* NI1 compare NI input enable0 */ -/* ==================================================================== */ - -#define SH_XN_NI1_NI_CMP_ENABLE0 0x00000001500319e0 -#define SH_XN_NI1_NI_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_NI1_NI_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_NI1_NI_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_NI1_NI_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_NI1_NI_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_NI_CMP_ENABLE1" */ -/* NI1 compare NI input enable1 */ -/* ==================================================================== */ - -#define SH_XN_NI1_NI_CMP_ENABLE1 0x00000001500319f0 -#define SH_XN_NI1_NI_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_NI1_NI_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_NI1_NI_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_NI1_NI_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_NI1_NI_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_LLP_CMP_EXP_DATA0" */ -/* NI1 compare LLP input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_NI1_LLP_CMP_EXP_DATA0 0x0000000150031a00 -#define SH_XN_NI1_LLP_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_NI1_LLP_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_NI1_LLP_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_NI1_LLP_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_NI1_LLP_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_LLP_CMP_EXP_DATA1" */ -/* NI1 compare LLP input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_NI1_LLP_CMP_EXP_DATA1 0x0000000150031a10 -#define SH_XN_NI1_LLP_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_NI1_LLP_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_NI1_LLP_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_NI1_LLP_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_NI1_LLP_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_LLP_CMP_ENABLE0" */ -/* NI1 compare LLP input enable0 */ -/* ==================================================================== */ - -#define SH_XN_NI1_LLP_CMP_ENABLE0 0x0000000150031a20 -#define SH_XN_NI1_LLP_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_NI1_LLP_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_NI1_LLP_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_NI1_LLP_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_NI1_LLP_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_LLP_CMP_ENABLE1" */ -/* NI1 compare LLP input enable1 */ -/* ==================================================================== */ - -#define SH_XN_NI1_LLP_CMP_ENABLE1 0x0000000150031a30 -#define SH_XN_NI1_LLP_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_NI1_LLP_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_NI1_LLP_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_NI1_LLP_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_NI1_LLP_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XNPI_ECC_INJ_REG" */ -/* ==================================================================== */ - -#define SH_XNPI_ECC_INJ_REG 0x0000000150032000 -#define SH_XNPI_ECC_INJ_REG_MASK 0xf0fff0fff0fff0ff -#define SH_XNPI_ECC_INJ_REG_INIT 0x0000000000000000 - -/* SH_XNPI_ECC_INJ_REG_BYTE0 */ -/* Description: Replacement Checkbyte */ -#define SH_XNPI_ECC_INJ_REG_BYTE0_SHFT 0 -#define SH_XNPI_ECC_INJ_REG_BYTE0_MASK 0x00000000000000ff - -/* SH_XNPI_ECC_INJ_REG_DATA_1SHOT0 */ -/* Description: 1 shot mask data */ -#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT0_SHFT 12 -#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT0_MASK 0x0000000000001000 - -/* SH_XNPI_ECC_INJ_REG_DATA_CONT0 */ -/* Description: toggle mask data */ -#define SH_XNPI_ECC_INJ_REG_DATA_CONT0_SHFT 13 -#define SH_XNPI_ECC_INJ_REG_DATA_CONT0_MASK 0x0000000000002000 - -/* SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT0 */ -/* Description: Replace Checkbyte One Shot */ -#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT0_SHFT 14 -#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT0_MASK 0x0000000000004000 - -/* SH_XNPI_ECC_INJ_REG_DATA_CB_CONT0 */ -/* Description: Replace Checkbyte Continuous */ -#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT0_SHFT 15 -#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT0_MASK 0x0000000000008000 - -/* SH_XNPI_ECC_INJ_REG_BYTE1 */ -/* Description: Replacement Checkbyte */ -#define SH_XNPI_ECC_INJ_REG_BYTE1_SHFT 16 -#define SH_XNPI_ECC_INJ_REG_BYTE1_MASK 0x0000000000ff0000 - -/* SH_XNPI_ECC_INJ_REG_DATA_1SHOT1 */ -/* Description: 1 shot mask data */ -#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT1_SHFT 28 -#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT1_MASK 0x0000000010000000 - -/* SH_XNPI_ECC_INJ_REG_DATA_CONT1 */ -/* Description: toggle mask data */ -#define SH_XNPI_ECC_INJ_REG_DATA_CONT1_SHFT 29 -#define SH_XNPI_ECC_INJ_REG_DATA_CONT1_MASK 0x0000000020000000 - -/* SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT1 */ -/* Description: Replace Checkbyte One Shot */ -#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT1_SHFT 30 -#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT1_MASK 0x0000000040000000 - -/* SH_XNPI_ECC_INJ_REG_DATA_CB_CONT1 */ -/* Description: Replace Checkbyte Continous */ -#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT1_SHFT 31 -#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT1_MASK 0x0000000080000000 - -/* SH_XNPI_ECC_INJ_REG_BYTE2 */ -/* Description: Replacement Checkbyte */ -#define SH_XNPI_ECC_INJ_REG_BYTE2_SHFT 32 -#define SH_XNPI_ECC_INJ_REG_BYTE2_MASK 0x000000ff00000000 - -/* SH_XNPI_ECC_INJ_REG_DATA_1SHOT2 */ -/* Description: 1 shot mask data */ -#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT2_SHFT 44 -#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT2_MASK 0x0000100000000000 - -/* SH_XNPI_ECC_INJ_REG_DATA_CONT2 */ -/* Description: toggle mask data */ -#define SH_XNPI_ECC_INJ_REG_DATA_CONT2_SHFT 45 -#define SH_XNPI_ECC_INJ_REG_DATA_CONT2_MASK 0x0000200000000000 - -/* SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT2 */ -/* Description: Replace Checkbyte OneShot */ -#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT2_SHFT 46 -#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT2_MASK 0x0000400000000000 - -/* SH_XNPI_ECC_INJ_REG_DATA_CB_CONT2 */ -/* Description: Replace Checkbyte Continous */ -#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT2_SHFT 47 -#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT2_MASK 0x0000800000000000 - -/* SH_XNPI_ECC_INJ_REG_BYTE3 */ -/* Description: Replacement Checkbyte */ -#define SH_XNPI_ECC_INJ_REG_BYTE3_SHFT 48 -#define SH_XNPI_ECC_INJ_REG_BYTE3_MASK 0x00ff000000000000 - -/* SH_XNPI_ECC_INJ_REG_DATA_1SHOT3 */ -/* Description: 1 shot mask data */ -#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT3_SHFT 60 -#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT3_MASK 0x1000000000000000 - -/* SH_XNPI_ECC_INJ_REG_DATA_CONT3 */ -/* Description: toggle mask data */ -#define SH_XNPI_ECC_INJ_REG_DATA_CONT3_SHFT 61 -#define SH_XNPI_ECC_INJ_REG_DATA_CONT3_MASK 0x2000000000000000 - -/* SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT3 */ -/* Description: Replace Checkbyte One-Shot */ -#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT3_SHFT 62 -#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT3_MASK 0x4000000000000000 - -/* SH_XNPI_ECC_INJ_REG_DATA_CB_CONT3 */ -/* Description: Replace Checkbyte Continous */ -#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT3_SHFT 63 -#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT3_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_XNPI_ECC0_INJ_MASK_REG" */ -/* ==================================================================== */ - -#define SH_XNPI_ECC0_INJ_MASK_REG 0x0000000150032008 -#define SH_XNPI_ECC0_INJ_MASK_REG_MASK 0xffffffffffffffff -#define SH_XNPI_ECC0_INJ_MASK_REG_INIT 0x0000000000000000 - -/* SH_XNPI_ECC0_INJ_MASK_REG_MASK_ECC0 */ -/* Description: Replacement Data */ -#define SH_XNPI_ECC0_INJ_MASK_REG_MASK_ECC0_SHFT 0 -#define SH_XNPI_ECC0_INJ_MASK_REG_MASK_ECC0_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XNPI_ECC1_INJ_MASK_REG" */ -/* ==================================================================== */ - -#define SH_XNPI_ECC1_INJ_MASK_REG 0x0000000150032010 -#define SH_XNPI_ECC1_INJ_MASK_REG_MASK 0xffffffffffffffff -#define SH_XNPI_ECC1_INJ_MASK_REG_INIT 0x0000000000000000 - -/* SH_XNPI_ECC1_INJ_MASK_REG_MASK_ECC1 */ -/* Description: Replacement Data */ -#define SH_XNPI_ECC1_INJ_MASK_REG_MASK_ECC1_SHFT 0 -#define SH_XNPI_ECC1_INJ_MASK_REG_MASK_ECC1_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XNPI_ECC2_INJ_MASK_REG" */ -/* ==================================================================== */ - -#define SH_XNPI_ECC2_INJ_MASK_REG 0x0000000150032018 -#define SH_XNPI_ECC2_INJ_MASK_REG_MASK 0xffffffffffffffff -#define SH_XNPI_ECC2_INJ_MASK_REG_INIT 0x0000000000000000 - -/* SH_XNPI_ECC2_INJ_MASK_REG_MASK_ECC2 */ -/* Description: Replacement Data */ -#define SH_XNPI_ECC2_INJ_MASK_REG_MASK_ECC2_SHFT 0 -#define SH_XNPI_ECC2_INJ_MASK_REG_MASK_ECC2_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XNPI_ECC3_INJ_MASK_REG" */ -/* ==================================================================== */ - -#define SH_XNPI_ECC3_INJ_MASK_REG 0x0000000150032020 -#define SH_XNPI_ECC3_INJ_MASK_REG_MASK 0xffffffffffffffff -#define SH_XNPI_ECC3_INJ_MASK_REG_INIT 0x0000000000000000 - -/* SH_XNPI_ECC3_INJ_MASK_REG_MASK_ECC3 */ -/* Description: Replacement Data */ -#define SH_XNPI_ECC3_INJ_MASK_REG_MASK_ECC3_SHFT 0 -#define SH_XNPI_ECC3_INJ_MASK_REG_MASK_ECC3_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XNMD_ECC_INJ_REG" */ -/* ==================================================================== */ - -#define SH_XNMD_ECC_INJ_REG 0x0000000150032030 -#define SH_XNMD_ECC_INJ_REG_MASK 0xf0fff0fff0fff0ff -#define SH_XNMD_ECC_INJ_REG_INIT 0x0000000000000000 - -/* SH_XNMD_ECC_INJ_REG_BYTE0 */ -/* Description: Replacement Checkbyte */ -#define SH_XNMD_ECC_INJ_REG_BYTE0_SHFT 0 -#define SH_XNMD_ECC_INJ_REG_BYTE0_MASK 0x00000000000000ff - -/* SH_XNMD_ECC_INJ_REG_DATA_1SHOT0 */ -/* Description: 1 shot mask data */ -#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT0_SHFT 12 -#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT0_MASK 0x0000000000001000 - -/* SH_XNMD_ECC_INJ_REG_DATA_CONT0 */ -/* Description: toggle mask data */ -#define SH_XNMD_ECC_INJ_REG_DATA_CONT0_SHFT 13 -#define SH_XNMD_ECC_INJ_REG_DATA_CONT0_MASK 0x0000000000002000 - -/* SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT0 */ -/* Description: Replace Checkbyte One Shot */ -#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT0_SHFT 14 -#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT0_MASK 0x0000000000004000 - -/* SH_XNMD_ECC_INJ_REG_DATA_CB_CONT0 */ -/* Description: Replace Checkbyte Continuous */ -#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT0_SHFT 15 -#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT0_MASK 0x0000000000008000 - -/* SH_XNMD_ECC_INJ_REG_BYTE1 */ -/* Description: Replacement Checkbyte */ -#define SH_XNMD_ECC_INJ_REG_BYTE1_SHFT 16 -#define SH_XNMD_ECC_INJ_REG_BYTE1_MASK 0x0000000000ff0000 - -/* SH_XNMD_ECC_INJ_REG_DATA_1SHOT1 */ -/* Description: 1 shot mask data */ -#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT1_SHFT 28 -#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT1_MASK 0x0000000010000000 - -/* SH_XNMD_ECC_INJ_REG_DATA_CONT1 */ -/* Description: toggle mask data */ -#define SH_XNMD_ECC_INJ_REG_DATA_CONT1_SHFT 29 -#define SH_XNMD_ECC_INJ_REG_DATA_CONT1_MASK 0x0000000020000000 - -/* SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT1 */ -/* Description: Replace Checkbyte One Shot */ -#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT1_SHFT 30 -#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT1_MASK 0x0000000040000000 - -/* SH_XNMD_ECC_INJ_REG_DATA_CB_CONT1 */ -/* Description: Replace Checkbyte Continous */ -#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT1_SHFT 31 -#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT1_MASK 0x0000000080000000 - -/* SH_XNMD_ECC_INJ_REG_BYTE2 */ -/* Description: Replacement Checkbyte */ -#define SH_XNMD_ECC_INJ_REG_BYTE2_SHFT 32 -#define SH_XNMD_ECC_INJ_REG_BYTE2_MASK 0x000000ff00000000 - -/* SH_XNMD_ECC_INJ_REG_DATA_1SHOT2 */ -/* Description: 1 shot mask data */ -#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT2_SHFT 44 -#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT2_MASK 0x0000100000000000 - -/* SH_XNMD_ECC_INJ_REG_DATA_CONT2 */ -/* Description: toggle mask data */ -#define SH_XNMD_ECC_INJ_REG_DATA_CONT2_SHFT 45 -#define SH_XNMD_ECC_INJ_REG_DATA_CONT2_MASK 0x0000200000000000 - -/* SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT2 */ -/* Description: Replace Checkbyte OneShot */ -#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT2_SHFT 46 -#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT2_MASK 0x0000400000000000 - -/* SH_XNMD_ECC_INJ_REG_DATA_CB_CONT2 */ -/* Description: Replace Checkbyte Continous */ -#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT2_SHFT 47 -#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT2_MASK 0x0000800000000000 - -/* SH_XNMD_ECC_INJ_REG_BYTE3 */ -/* Description: Replacement Checkbyte */ -#define SH_XNMD_ECC_INJ_REG_BYTE3_SHFT 48 -#define SH_XNMD_ECC_INJ_REG_BYTE3_MASK 0x00ff000000000000 - -/* SH_XNMD_ECC_INJ_REG_DATA_1SHOT3 */ -/* Description: 1 shot mask data */ -#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT3_SHFT 60 -#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT3_MASK 0x1000000000000000 - -/* SH_XNMD_ECC_INJ_REG_DATA_CONT3 */ -/* Description: toggle mask data */ -#define SH_XNMD_ECC_INJ_REG_DATA_CONT3_SHFT 61 -#define SH_XNMD_ECC_INJ_REG_DATA_CONT3_MASK 0x2000000000000000 - -/* SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT3 */ -/* Description: Replace Checkbyte One-Shot */ -#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT3_SHFT 62 -#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT3_MASK 0x4000000000000000 - -/* SH_XNMD_ECC_INJ_REG_DATA_CB_CONT3 */ -/* Description: Replace Checkbyte Continous */ -#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT3_SHFT 63 -#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT3_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_XNMD_ECC0_INJ_MASK_REG" */ -/* ==================================================================== */ - -#define SH_XNMD_ECC0_INJ_MASK_REG 0x0000000150032038 -#define SH_XNMD_ECC0_INJ_MASK_REG_MASK 0xffffffffffffffff -#define SH_XNMD_ECC0_INJ_MASK_REG_INIT 0x0000000000000000 - -/* SH_XNMD_ECC0_INJ_MASK_REG_MASK_ECC0 */ -/* Description: Replacement Data */ -#define SH_XNMD_ECC0_INJ_MASK_REG_MASK_ECC0_SHFT 0 -#define SH_XNMD_ECC0_INJ_MASK_REG_MASK_ECC0_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XNMD_ECC1_INJ_MASK_REG" */ -/* ==================================================================== */ - -#define SH_XNMD_ECC1_INJ_MASK_REG 0x0000000150032040 -#define SH_XNMD_ECC1_INJ_MASK_REG_MASK 0xffffffffffffffff -#define SH_XNMD_ECC1_INJ_MASK_REG_INIT 0x0000000000000000 - -/* SH_XNMD_ECC1_INJ_MASK_REG_MASK_ECC1 */ -/* Description: Replacement Data */ -#define SH_XNMD_ECC1_INJ_MASK_REG_MASK_ECC1_SHFT 0 -#define SH_XNMD_ECC1_INJ_MASK_REG_MASK_ECC1_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XNMD_ECC2_INJ_MASK_REG" */ -/* ==================================================================== */ - -#define SH_XNMD_ECC2_INJ_MASK_REG 0x0000000150032048 -#define SH_XNMD_ECC2_INJ_MASK_REG_MASK 0xffffffffffffffff -#define SH_XNMD_ECC2_INJ_MASK_REG_INIT 0x0000000000000000 - -/* SH_XNMD_ECC2_INJ_MASK_REG_MASK_ECC2 */ -/* Description: Replacement Data */ -#define SH_XNMD_ECC2_INJ_MASK_REG_MASK_ECC2_SHFT 0 -#define SH_XNMD_ECC2_INJ_MASK_REG_MASK_ECC2_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XNMD_ECC3_INJ_MASK_REG" */ -/* ==================================================================== */ - -#define SH_XNMD_ECC3_INJ_MASK_REG 0x0000000150032050 -#define SH_XNMD_ECC3_INJ_MASK_REG_MASK 0xffffffffffffffff -#define SH_XNMD_ECC3_INJ_MASK_REG_INIT 0x0000000000000000 - -/* SH_XNMD_ECC3_INJ_MASK_REG_MASK_ECC3 */ -/* Description: Replacement Data */ -#define SH_XNMD_ECC3_INJ_MASK_REG_MASK_ECC3_SHFT 0 -#define SH_XNMD_ECC3_INJ_MASK_REG_MASK_ECC3_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XNMD_ECC_ERR_REPORT" */ -/* ==================================================================== */ - -#define SH_XNMD_ECC_ERR_REPORT 0x0000000150032058 -#define SH_XNMD_ECC_ERR_REPORT_MASK 0x0001000100010001 -#define SH_XNMD_ECC_ERR_REPORT_INIT 0x0000000000000000 - -/* SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE0 */ -/* Description: Disable Error Correction */ -#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE0_SHFT 0 -#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE0_MASK 0x0000000000000001 - -/* SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE1 */ -/* Description: Disable Error Correction */ -#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE1_SHFT 16 -#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE1_MASK 0x0000000000010000 - -/* SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE2 */ -/* Description: Disable Error Correction */ -#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE2_SHFT 32 -#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE2_MASK 0x0000000100000000 - -/* SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE3 */ -/* Description: Disable Error Correction */ -#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE3_SHFT 48 -#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE3_MASK 0x0001000000000000 - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_SUMMARY_1" */ -/* ni0 Error Summary Bits */ -/* ==================================================================== */ - -#define SH_NI0_ERROR_SUMMARY_1 0x0000000150040500 -#define SH_NI0_ERROR_SUMMARY_1_MASK 0xffffffffffffffff -#define SH_NI0_ERROR_SUMMARY_1_INIT 0xffffffffffffffff - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0 */ -/* Description: Fifo 02 debit0 overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2 */ -/* Description: Fifo 02 debit2 overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0 */ -/* Description: Fifo 13 debit0 overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2 */ -/* Description: Fifo 13 debit2 overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit overflow 0 */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit overflow 1 */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit overflow 2 */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit overflow 0 */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit overflow 1 */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit overflow 2 */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0 */ -/* Description: PI Fifo debit0 overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2 */ -/* Description: PI Fifo debit2 overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0 */ -/* Description: IILB Fifo debit0 overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2 */ -/* Description: IILB Fifo debit2 overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0 */ -/* Description: MD Fifo debit0 overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2 */ -/* Description: MD Fifo debit2 overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0 */ -/* Description: NI Fifo debit0 overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1 */ -/* Description: NI Fifo debit1 overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2 */ -/* Description: NI Fifo debit2 overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3 */ -/* Description: NI Fifo debit3 overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0 */ -/* Description: Fifo02 vc0 tail timeout */ -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56 -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000 - -/* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2 */ -/* Description: Fifo02 vc2 tail timeout */ -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57 -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000 - -/* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1 */ -/* Description: Fifo13 vc1 tail timeout */ -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58 -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000 - -/* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3 */ -/* Description: Fifo13 vc3 tail timeout */ -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59 -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000 - -/* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0 */ -/* Description: NI vc0 tail timeout */ -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0_SHFT 60 -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000 - -/* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1 */ -/* Description: NI vc1 tail timeout */ -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1_SHFT 61 -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000 - -/* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2 */ -/* Description: NI vc2 tail timeout */ -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2_SHFT 62 -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000 - -/* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3 */ -/* Description: NI vc3 tail timeout */ -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3_SHFT 63 -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_SUMMARY_1_ALIAS" */ -/* ni0 Error Summary Bits Alias */ -/* ==================================================================== */ - -#define SH_NI0_ERROR_SUMMARY_1_ALIAS 0x0000000150040508 - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_SUMMARY_2" */ -/* ni0 Error Summary Bits */ -/* ==================================================================== */ - -#define SH_NI0_ERROR_SUMMARY_2 0x0000000150040510 -#define SH_NI0_ERROR_SUMMARY_2_MASK 0x7fffffff003fffff -#define SH_NI0_ERROR_SUMMARY_2_INIT 0x7fffffff003fffff - -/* SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCNI */ -/* Description: Illegal VC NI */ -#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCNI_SHFT 0 -#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCNI_MASK 0x0000000000000001 - -/* SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCPI */ -/* Description: Illegal VC PI */ -#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCPI_SHFT 1 -#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCPI_MASK 0x0000000000000002 - -/* SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCMD */ -/* Description: Illegal VC MD */ -#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCMD_SHFT 2 -#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCMD_MASK 0x0000000000000004 - -/* SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCIILB */ -/* Description: Illegal VC IILB */ -#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCIILB_SHFT 3 -#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCIILB_MASK 0x0000000000000008 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit underflow 0 */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit underflow 1 */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit underflow 2 */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit underflow 0 */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit underflow 1 */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit underflow 2 */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0 */ -/* Description: llp deadlock vc0 */ -#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0_SHFT 56 -#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000 - -/* SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1 */ -/* Description: llp deadlock vc1 */ -#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1_SHFT 57 -#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000 - -/* SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2 */ -/* Description: llp deadlock vc2 */ -#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2_SHFT 58 -#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000 - -/* SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3 */ -/* Description: llp deadlock vc3 */ -#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3_SHFT 59 -#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000 - -/* SH_NI0_ERROR_SUMMARY_2_CHIPLET_NOMATCH */ -/* Description: chiplet nomatch */ -#define SH_NI0_ERROR_SUMMARY_2_CHIPLET_NOMATCH_SHFT 60 -#define SH_NI0_ERROR_SUMMARY_2_CHIPLET_NOMATCH_MASK 0x1000000000000000 - -/* SH_NI0_ERROR_SUMMARY_2_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_NI0_ERROR_SUMMARY_2_LUT_READ_ERROR_SHFT 61 -#define SH_NI0_ERROR_SUMMARY_2_LUT_READ_ERROR_MASK 0x2000000000000000 - -/* SH_NI0_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR */ -/* Description: Retry Timeout Error */ -#define SH_NI0_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR_SHFT 62 -#define SH_NI0_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_SUMMARY_2_ALIAS" */ -/* ni0 Error Summary Bits Alias */ -/* ==================================================================== */ - -#define SH_NI0_ERROR_SUMMARY_2_ALIAS 0x0000000150040518 - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_OVERFLOW_1" */ -/* ni0 Error Overflow Bits */ -/* ==================================================================== */ - -#define SH_NI0_ERROR_OVERFLOW_1 0x0000000150040520 -#define SH_NI0_ERROR_OVERFLOW_1_MASK 0xffffffffffffffff -#define SH_NI0_ERROR_OVERFLOW_1_INIT 0xffffffffffffffff - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0 */ -/* Description: Fifo 02 debit0 overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2 */ -/* Description: Fifo 02 debit2 overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0 */ -/* Description: Fifo 13 debit0 overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2 */ -/* Description: Fifo 13 debit2 overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit overflow 0 */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit overflow 1 */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit overflow 2 */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit overflow 0 */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit overflow 1 */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit overflow 2 */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0 */ -/* Description: PI Fifo debit0 overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2 */ -/* Description: PI Fifo debit2 overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0 */ -/* Description: IILB Fifo debit0 overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2 */ -/* Description: IILB Fifo debit2 overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0 */ -/* Description: MD Fifo debit0 overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2 */ -/* Description: MD Fifo debit2 overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0 */ -/* Description: NI Fifo debit0 overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1 */ -/* Description: NI Fifo debit1 overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2 */ -/* Description: NI Fifo debit2 overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3 */ -/* Description: NI Fifo debit3 overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0 */ -/* Description: Fifo02 vc0 tail timeout */ -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56 -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2 */ -/* Description: Fifo02 vc2 tail timeout */ -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57 -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1 */ -/* Description: Fifo13 vc1 tail timeout */ -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58 -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3 */ -/* Description: Fifo13 vc3 tail timeout */ -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59 -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0 */ -/* Description: NI vc0 tail timeout */ -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0_SHFT 60 -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1 */ -/* Description: NI vc1 tail timeout */ -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1_SHFT 61 -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2 */ -/* Description: NI vc2 tail timeout */ -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2_SHFT 62 -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3 */ -/* Description: NI vc3 tail timeout */ -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3_SHFT 63 -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_OVERFLOW_1_ALIAS" */ -/* ni0 Error Overflow Bits Alias */ -/* ==================================================================== */ - -#define SH_NI0_ERROR_OVERFLOW_1_ALIAS 0x0000000150040528 - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_OVERFLOW_2" */ -/* ni0 Error Overflow Bits */ -/* ==================================================================== */ - -#define SH_NI0_ERROR_OVERFLOW_2 0x0000000150040530 -#define SH_NI0_ERROR_OVERFLOW_2_MASK 0x7fffffff003fffff -#define SH_NI0_ERROR_OVERFLOW_2_INIT 0x7fffffff003fffff - -/* SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCNI */ -/* Description: Illegal VC NI */ -#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCNI_SHFT 0 -#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCNI_MASK 0x0000000000000001 - -/* SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCPI */ -/* Description: Illegal VC PI */ -#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCPI_SHFT 1 -#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCPI_MASK 0x0000000000000002 - -/* SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCMD */ -/* Description: Illegal VC MD */ -#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCMD_SHFT 2 -#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCMD_MASK 0x0000000000000004 - -/* SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCIILB */ -/* Description: Illegal VC IILB */ -#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCIILB_SHFT 3 -#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCIILB_MASK 0x0000000000000008 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit underflow 0 */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit underflow 1 */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit underflow 2 */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit underflow 0 */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit underflow 1 */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit underflow 2 */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0 */ -/* Description: llp deadlock vc0 */ -#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0_SHFT 56 -#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1 */ -/* Description: llp deadlock vc1 */ -#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1_SHFT 57 -#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2 */ -/* Description: llp deadlock vc2 */ -#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2_SHFT 58 -#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3 */ -/* Description: llp deadlock vc3 */ -#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3_SHFT 59 -#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_CHIPLET_NOMATCH */ -/* Description: chiplet nomatch */ -#define SH_NI0_ERROR_OVERFLOW_2_CHIPLET_NOMATCH_SHFT 60 -#define SH_NI0_ERROR_OVERFLOW_2_CHIPLET_NOMATCH_MASK 0x1000000000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_NI0_ERROR_OVERFLOW_2_LUT_READ_ERROR_SHFT 61 -#define SH_NI0_ERROR_OVERFLOW_2_LUT_READ_ERROR_MASK 0x2000000000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR */ -/* Description: Retry Timeout Error */ -#define SH_NI0_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR_SHFT 62 -#define SH_NI0_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_OVERFLOW_2_ALIAS" */ -/* ni0 Error Overflow Bits Alias */ -/* ==================================================================== */ - -#define SH_NI0_ERROR_OVERFLOW_2_ALIAS 0x0000000150040538 - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_MASK_1" */ -/* ni0 Error Mask Bits */ -/* ==================================================================== */ - -#define SH_NI0_ERROR_MASK_1 0x0000000150040540 -#define SH_NI0_ERROR_MASK_1_MASK 0xffffffffffffffff -#define SH_NI0_ERROR_MASK_1_INIT 0xffffffffffffffff - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0 */ -/* Description: Fifo 02 debit0 overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2 */ -/* Description: Fifo 02 debit2 overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0 */ -/* Description: Fifo 13 debit0 overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2 */ -/* Description: Fifo 13 debit2 overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit overflow 0 */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI0_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit overflow 1 */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI0_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit overflow 2 */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI0_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit overflow 0 */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI0_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit overflow 1 */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI0_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit overflow 2 */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI0_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0 */ -/* Description: PI Fifo debit0 overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2 */ -/* Description: PI Fifo debit2 overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0 */ -/* Description: IILB Fifo debit0 overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2 */ -/* Description: IILB Fifo debit2 overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0 */ -/* Description: MD Fifo debit0 overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2 */ -/* Description: MD Fifo debit2 overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0 */ -/* Description: NI Fifo debit0 overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1 */ -/* Description: NI Fifo debit1 overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2 */ -/* Description: NI Fifo debit2 overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3 */ -/* Description: NI Fifo debit3 overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0 */ -/* Description: Fifo02 vc0 tail timeout */ -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56 -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000 - -/* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2 */ -/* Description: Fifo02 vc2 tail timeout */ -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57 -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000 - -/* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1 */ -/* Description: Fifo13 vc1 tail timeout */ -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58 -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000 - -/* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3 */ -/* Description: Fifo13 vc3 tail timeout */ -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59 -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000 - -/* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0 */ -/* Description: NI vc0 tail timeout */ -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0_SHFT 60 -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000 - -/* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1 */ -/* Description: NI vc1 tail timeout */ -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1_SHFT 61 -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000 - -/* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2 */ -/* Description: NI vc2 tail timeout */ -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2_SHFT 62 -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000 - -/* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3 */ -/* Description: NI vc3 tail timeout */ -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3_SHFT 63 -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_MASK_2" */ -/* ni0 Error Mask Bits */ -/* ==================================================================== */ - -#define SH_NI0_ERROR_MASK_2 0x0000000150040550 -#define SH_NI0_ERROR_MASK_2_MASK 0x7fffffff003fffff -#define SH_NI0_ERROR_MASK_2_INIT 0x7fffffff003fffff - -/* SH_NI0_ERROR_MASK_2_ILLEGAL_VCNI */ -/* Description: Illegal VC NI */ -#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCNI_SHFT 0 -#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCNI_MASK 0x0000000000000001 - -/* SH_NI0_ERROR_MASK_2_ILLEGAL_VCPI */ -/* Description: Illegal VC PI */ -#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCPI_SHFT 1 -#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCPI_MASK 0x0000000000000002 - -/* SH_NI0_ERROR_MASK_2_ILLEGAL_VCMD */ -/* Description: Illegal VC MD */ -#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCMD_SHFT 2 -#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCMD_MASK 0x0000000000000004 - -/* SH_NI0_ERROR_MASK_2_ILLEGAL_VCIILB */ -/* Description: Illegal VC IILB */ -#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCIILB_SHFT 3 -#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCIILB_MASK 0x0000000000000008 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit underflow 0 */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit underflow 1 */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit underflow 2 */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit underflow 0 */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit underflow 1 */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit underflow 2 */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC0 */ -/* Description: llp deadlock vc0 */ -#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC0_SHFT 56 -#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000 - -/* SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC1 */ -/* Description: llp deadlock vc1 */ -#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC1_SHFT 57 -#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000 - -/* SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC2 */ -/* Description: llp deadlock vc2 */ -#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC2_SHFT 58 -#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000 - -/* SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC3 */ -/* Description: llp deadlock vc3 */ -#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC3_SHFT 59 -#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000 - -/* SH_NI0_ERROR_MASK_2_CHIPLET_NOMATCH */ -/* Description: chiplet nomatch */ -#define SH_NI0_ERROR_MASK_2_CHIPLET_NOMATCH_SHFT 60 -#define SH_NI0_ERROR_MASK_2_CHIPLET_NOMATCH_MASK 0x1000000000000000 - -/* SH_NI0_ERROR_MASK_2_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_NI0_ERROR_MASK_2_LUT_READ_ERROR_SHFT 61 -#define SH_NI0_ERROR_MASK_2_LUT_READ_ERROR_MASK 0x2000000000000000 - -/* SH_NI0_ERROR_MASK_2_RETRY_TIMEOUT_ERROR */ -/* Description: Retry Timeout Error */ -#define SH_NI0_ERROR_MASK_2_RETRY_TIMEOUT_ERROR_SHFT 62 -#define SH_NI0_ERROR_MASK_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI0_FIRST_ERROR_1" */ -/* ni0 First Error Bits */ -/* ==================================================================== */ - -#define SH_NI0_FIRST_ERROR_1 0x0000000150040560 -#define SH_NI0_FIRST_ERROR_1_MASK 0xffffffffffffffff -#define SH_NI0_FIRST_ERROR_1_INIT 0xffffffffffffffff - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0 */ -/* Description: Fifo 02 debit0 overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2 */ -/* Description: Fifo 02 debit2 overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0 */ -/* Description: Fifo 13 debit0 overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2 */ -/* Description: Fifo 13 debit2 overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit overflow 0 */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit overflow 1 */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit overflow 2 */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit overflow 0 */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit overflow 1 */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit overflow 2 */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0 */ -/* Description: PI Fifo debit0 overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2 */ -/* Description: PI Fifo debit2 overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0 */ -/* Description: IILB Fifo debit0 overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2 */ -/* Description: IILB Fifo debit2 overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0 */ -/* Description: MD Fifo debit0 overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2 */ -/* Description: MD Fifo debit2 overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0 */ -/* Description: NI Fifo debit0 overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1 */ -/* Description: NI Fifo debit1 overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2 */ -/* Description: NI Fifo debit2 overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3 */ -/* Description: NI Fifo debit3 overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0 */ -/* Description: Fifo02 vc0 tail timeout */ -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56 -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000 - -/* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2 */ -/* Description: Fifo02 vc2 tail timeout */ -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57 -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000 - -/* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1 */ -/* Description: Fifo13 vc1 tail timeout */ -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58 -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000 - -/* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3 */ -/* Description: Fifo13 vc3 tail timeout */ -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59 -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000 - -/* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0 */ -/* Description: NI vc0 tail timeout */ -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0_SHFT 60 -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000 - -/* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1 */ -/* Description: NI vc1 tail timeout */ -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1_SHFT 61 -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000 - -/* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2 */ -/* Description: NI vc2 tail timeout */ -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2_SHFT 62 -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000 - -/* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3 */ -/* Description: NI vc3 tail timeout */ -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3_SHFT 63 -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI0_FIRST_ERROR_2" */ -/* ni0 First Error Bits */ -/* ==================================================================== */ - -#define SH_NI0_FIRST_ERROR_2 0x0000000150040570 -#define SH_NI0_FIRST_ERROR_2_MASK 0x7fffffff003fffff -#define SH_NI0_FIRST_ERROR_2_INIT 0x7fffffff003fffff - -/* SH_NI0_FIRST_ERROR_2_ILLEGAL_VCNI */ -/* Description: Illegal VC NI */ -#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCNI_SHFT 0 -#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCNI_MASK 0x0000000000000001 - -/* SH_NI0_FIRST_ERROR_2_ILLEGAL_VCPI */ -/* Description: Illegal VC PI */ -#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCPI_SHFT 1 -#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCPI_MASK 0x0000000000000002 - -/* SH_NI0_FIRST_ERROR_2_ILLEGAL_VCMD */ -/* Description: Illegal VC MD */ -#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCMD_SHFT 2 -#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCMD_MASK 0x0000000000000004 - -/* SH_NI0_FIRST_ERROR_2_ILLEGAL_VCIILB */ -/* Description: Illegal VC IILB */ -#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCIILB_SHFT 3 -#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCIILB_MASK 0x0000000000000008 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit underflow 0 */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit underflow 1 */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit underflow 2 */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit underflow 0 */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit underflow 1 */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit underflow 2 */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC0 */ -/* Description: llp deadlock vc0 */ -#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC0_SHFT 56 -#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000 - -/* SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC1 */ -/* Description: llp deadlock vc1 */ -#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC1_SHFT 57 -#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000 - -/* SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC2 */ -/* Description: llp deadlock vc2 */ -#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC2_SHFT 58 -#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000 - -/* SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC3 */ -/* Description: llp deadlock vc3 */ -#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC3_SHFT 59 -#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000 - -/* SH_NI0_FIRST_ERROR_2_CHIPLET_NOMATCH */ -/* Description: chiplet nomatch */ -#define SH_NI0_FIRST_ERROR_2_CHIPLET_NOMATCH_SHFT 60 -#define SH_NI0_FIRST_ERROR_2_CHIPLET_NOMATCH_MASK 0x1000000000000000 - -/* SH_NI0_FIRST_ERROR_2_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_NI0_FIRST_ERROR_2_LUT_READ_ERROR_SHFT 61 -#define SH_NI0_FIRST_ERROR_2_LUT_READ_ERROR_MASK 0x2000000000000000 - -/* SH_NI0_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR */ -/* Description: Retry Timeout Error */ -#define SH_NI0_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR_SHFT 62 -#define SH_NI0_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_DETAIL_1" */ -/* ni0 Chiplet no match header bits 63:0 */ -/* ==================================================================== */ - -#define SH_NI0_ERROR_DETAIL_1 0x0000000150040580 -#define SH_NI0_ERROR_DETAIL_1_MASK 0xffffffffffffffff -#define SH_NI0_ERROR_DETAIL_1_INIT 0x0000000000000000 - -/* SH_NI0_ERROR_DETAIL_1_HEADER */ -/* Description: Header bits 63:0 */ -#define SH_NI0_ERROR_DETAIL_1_HEADER_SHFT 0 -#define SH_NI0_ERROR_DETAIL_1_HEADER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_DETAIL_2" */ -/* ni0 Chiplet no match header bits 127:64 */ -/* ==================================================================== */ - -#define SH_NI0_ERROR_DETAIL_2 0x0000000150040590 -#define SH_NI0_ERROR_DETAIL_2_MASK 0xffffffffffffffff -#define SH_NI0_ERROR_DETAIL_2_INIT 0x0000000000000000 - -/* SH_NI0_ERROR_DETAIL_2_HEADER */ -/* Description: Header bits 127:64 */ -#define SH_NI0_ERROR_DETAIL_2_HEADER_SHFT 0 -#define SH_NI0_ERROR_DETAIL_2_HEADER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_SUMMARY_1" */ -/* ni1 Error Summary Bits */ -/* ==================================================================== */ - -#define SH_NI1_ERROR_SUMMARY_1 0x0000000150040600 -#define SH_NI1_ERROR_SUMMARY_1_MASK 0xffffffffffffffff -#define SH_NI1_ERROR_SUMMARY_1_INIT 0xffffffffffffffff - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0 */ -/* Description: Fifo 02 debit0 overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2 */ -/* Description: Fifo 02 debit2 overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0 */ -/* Description: Fifo 13 debit0 overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2 */ -/* Description: Fifo 13 debit2 overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit overflow 0 */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit overflow 1 */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit overflow 2 */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit overflow 0 */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit overflow 1 */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit overflow 2 */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0 */ -/* Description: PI Fifo debit0 overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2 */ -/* Description: PI Fifo debit2 overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0 */ -/* Description: IILB Fifo debit0 overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2 */ -/* Description: IILB Fifo debit2 overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0 */ -/* Description: MD Fifo debit0 overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2 */ -/* Description: MD Fifo debit2 overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0 */ -/* Description: NI Fifo debit0 overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1 */ -/* Description: NI Fifo debit1 overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2 */ -/* Description: NI Fifo debit2 overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3 */ -/* Description: NI Fifo debit3 overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0 */ -/* Description: Fifo02 vc0 tail timeout */ -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56 -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000 - -/* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2 */ -/* Description: Fifo02 vc2 tail timeout */ -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57 -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000 - -/* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1 */ -/* Description: Fifo13 vc1 tail timeout */ -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58 -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000 - -/* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3 */ -/* Description: Fifo13 vc3 tail timeout */ -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59 -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000 - -/* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0 */ -/* Description: NI vc0 tail timeout */ -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0_SHFT 60 -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000 - -/* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1 */ -/* Description: NI vc1 tail timeout */ -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1_SHFT 61 -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000 - -/* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2 */ -/* Description: NI vc2 tail timeout */ -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2_SHFT 62 -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000 - -/* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3 */ -/* Description: NI vc3 tail timeout */ -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3_SHFT 63 -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_SUMMARY_1_ALIAS" */ -/* ni1 Error Summary Bits Alias */ -/* ==================================================================== */ - -#define SH_NI1_ERROR_SUMMARY_1_ALIAS 0x0000000150040608 - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_SUMMARY_2" */ -/* ni1 Error Summary Bits */ -/* ==================================================================== */ - -#define SH_NI1_ERROR_SUMMARY_2 0x0000000150040610 -#define SH_NI1_ERROR_SUMMARY_2_MASK 0x7fffffff003fffff -#define SH_NI1_ERROR_SUMMARY_2_INIT 0x7fffffff003fffff - -/* SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCNI */ -/* Description: Illegal VC NI */ -#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCNI_SHFT 0 -#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCNI_MASK 0x0000000000000001 - -/* SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCPI */ -/* Description: Illegal VC PI */ -#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCPI_SHFT 1 -#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCPI_MASK 0x0000000000000002 - -/* SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCMD */ -/* Description: Illegal VC MD */ -#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCMD_SHFT 2 -#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCMD_MASK 0x0000000000000004 - -/* SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCIILB */ -/* Description: Illegal VC IILB */ -#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCIILB_SHFT 3 -#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCIILB_MASK 0x0000000000000008 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit underflow 0 */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit underflow 1 */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit underflow 2 */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit underflow 0 */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit underflow 1 */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit underflow 2 */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0 */ -/* Description: llp deadlock vc0 */ -#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0_SHFT 56 -#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000 - -/* SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1 */ -/* Description: llp deadlock vc1 */ -#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1_SHFT 57 -#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000 - -/* SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2 */ -/* Description: llp deadlock vc2 */ -#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2_SHFT 58 -#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000 - -/* SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3 */ -/* Description: llp deadlock vc3 */ -#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3_SHFT 59 -#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000 - -/* SH_NI1_ERROR_SUMMARY_2_CHIPLET_NOMATCH */ -/* Description: chiplet nomatch */ -#define SH_NI1_ERROR_SUMMARY_2_CHIPLET_NOMATCH_SHFT 60 -#define SH_NI1_ERROR_SUMMARY_2_CHIPLET_NOMATCH_MASK 0x1000000000000000 - -/* SH_NI1_ERROR_SUMMARY_2_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_NI1_ERROR_SUMMARY_2_LUT_READ_ERROR_SHFT 61 -#define SH_NI1_ERROR_SUMMARY_2_LUT_READ_ERROR_MASK 0x2000000000000000 - -/* SH_NI1_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR */ -/* Description: Retry Timeout Error */ -#define SH_NI1_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR_SHFT 62 -#define SH_NI1_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_SUMMARY_2_ALIAS" */ -/* ni1 Error Summary Bits Alias */ -/* ==================================================================== */ - -#define SH_NI1_ERROR_SUMMARY_2_ALIAS 0x0000000150040618 - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_OVERFLOW_1" */ -/* ni1 Error Overflow Bits */ -/* ==================================================================== */ - -#define SH_NI1_ERROR_OVERFLOW_1 0x0000000150040620 -#define SH_NI1_ERROR_OVERFLOW_1_MASK 0xffffffffffffffff -#define SH_NI1_ERROR_OVERFLOW_1_INIT 0xffffffffffffffff - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0 */ -/* Description: Fifo 02 debit0 overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2 */ -/* Description: Fifo 02 debit2 overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0 */ -/* Description: Fifo 13 debit0 overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2 */ -/* Description: Fifo 13 debit2 overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit overflow 0 */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit overflow 1 */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit overflow 2 */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit overflow 0 */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit overflow 1 */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit overflow 2 */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0 */ -/* Description: PI Fifo debit0 overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2 */ -/* Description: PI Fifo debit2 overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0 */ -/* Description: IILB Fifo debit0 overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2 */ -/* Description: IILB Fifo debit2 overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0 */ -/* Description: MD Fifo debit0 overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2 */ -/* Description: MD Fifo debit2 overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0 */ -/* Description: NI Fifo debit0 overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1 */ -/* Description: NI Fifo debit1 overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2 */ -/* Description: NI Fifo debit2 overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3 */ -/* Description: NI Fifo debit3 overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0 */ -/* Description: Fifo02 vc0 tail timeout */ -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56 -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2 */ -/* Description: Fifo02 vc2 tail timeout */ -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57 -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1 */ -/* Description: Fifo13 vc1 tail timeout */ -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58 -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3 */ -/* Description: Fifo13 vc3 tail timeout */ -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59 -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0 */ -/* Description: NI vc0 tail timeout */ -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0_SHFT 60 -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1 */ -/* Description: NI vc1 tail timeout */ -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1_SHFT 61 -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2 */ -/* Description: NI vc2 tail timeout */ -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2_SHFT 62 -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3 */ -/* Description: NI vc3 tail timeout */ -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3_SHFT 63 -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_OVERFLOW_1_ALIAS" */ -/* ni1 Error Overflow Bits Alias */ -/* ==================================================================== */ - -#define SH_NI1_ERROR_OVERFLOW_1_ALIAS 0x0000000150040628 - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_OVERFLOW_2" */ -/* ni1 Error Overflow Bits */ -/* ==================================================================== */ - -#define SH_NI1_ERROR_OVERFLOW_2 0x0000000150040630 -#define SH_NI1_ERROR_OVERFLOW_2_MASK 0x7fffffff003fffff -#define SH_NI1_ERROR_OVERFLOW_2_INIT 0x7fffffff003fffff - -/* SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCNI */ -/* Description: Illegal VC NI */ -#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCNI_SHFT 0 -#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCNI_MASK 0x0000000000000001 - -/* SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCPI */ -/* Description: Illegal VC PI */ -#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCPI_SHFT 1 -#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCPI_MASK 0x0000000000000002 - -/* SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCMD */ -/* Description: Illegal VC MD */ -#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCMD_SHFT 2 -#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCMD_MASK 0x0000000000000004 - -/* SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCIILB */ -/* Description: Illegal VC IILB */ -#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCIILB_SHFT 3 -#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCIILB_MASK 0x0000000000000008 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit underflow 0 */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit underflow 1 */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit underflow 2 */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit underflow 0 */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit underflow 1 */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit underflow 2 */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0 */ -/* Description: llp deadlock vc0 */ -#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0_SHFT 56 -#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1 */ -/* Description: llp deadlock vc1 */ -#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1_SHFT 57 -#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2 */ -/* Description: llp deadlock vc2 */ -#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2_SHFT 58 -#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3 */ -/* Description: llp deadlock vc3 */ -#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3_SHFT 59 -#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_CHIPLET_NOMATCH */ -/* Description: chiplet nomatch */ -#define SH_NI1_ERROR_OVERFLOW_2_CHIPLET_NOMATCH_SHFT 60 -#define SH_NI1_ERROR_OVERFLOW_2_CHIPLET_NOMATCH_MASK 0x1000000000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_NI1_ERROR_OVERFLOW_2_LUT_READ_ERROR_SHFT 61 -#define SH_NI1_ERROR_OVERFLOW_2_LUT_READ_ERROR_MASK 0x2000000000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR */ -/* Description: Retry Timeout Error */ -#define SH_NI1_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR_SHFT 62 -#define SH_NI1_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_OVERFLOW_2_ALIAS" */ -/* ni1 Error Overflow Bits Alias */ -/* ==================================================================== */ - -#define SH_NI1_ERROR_OVERFLOW_2_ALIAS 0x0000000150040638 - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_MASK_1" */ -/* ni1 Error Mask Bits */ -/* ==================================================================== */ - -#define SH_NI1_ERROR_MASK_1 0x0000000150040640 -#define SH_NI1_ERROR_MASK_1_MASK 0xffffffffffffffff -#define SH_NI1_ERROR_MASK_1_INIT 0xffffffffffffffff - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0 */ -/* Description: Fifo 02 debit0 overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2 */ -/* Description: Fifo 02 debit2 overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0 */ -/* Description: Fifo 13 debit0 overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2 */ -/* Description: Fifo 13 debit2 overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit overflow 0 */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI1_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit overflow 1 */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI1_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit overflow 2 */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI1_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit overflow 0 */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI1_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit overflow 1 */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI1_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit overflow 2 */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI1_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0 */ -/* Description: PI Fifo debit0 overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2 */ -/* Description: PI Fifo debit2 overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0 */ -/* Description: IILB Fifo debit0 overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2 */ -/* Description: IILB Fifo debit2 overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0 */ -/* Description: MD Fifo debit0 overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2 */ -/* Description: MD Fifo debit2 overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0 */ -/* Description: NI Fifo debit0 overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1 */ -/* Description: NI Fifo debit1 overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2 */ -/* Description: NI Fifo debit2 overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3 */ -/* Description: NI Fifo debit3 overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0 */ -/* Description: Fifo02 vc0 tail timeout */ -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56 -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000 - -/* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2 */ -/* Description: Fifo02 vc2 tail timeout */ -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57 -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000 - -/* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1 */ -/* Description: Fifo13 vc1 tail timeout */ -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58 -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000 - -/* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3 */ -/* Description: Fifo13 vc3 tail timeout */ -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59 -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000 - -/* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0 */ -/* Description: NI vc0 tail timeout */ -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0_SHFT 60 -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000 - -/* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1 */ -/* Description: NI vc1 tail timeout */ -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1_SHFT 61 -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000 - -/* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2 */ -/* Description: NI vc2 tail timeout */ -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2_SHFT 62 -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000 - -/* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3 */ -/* Description: NI vc3 tail timeout */ -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3_SHFT 63 -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_MASK_2" */ -/* ni1 Error Mask Bits */ -/* ==================================================================== */ - -#define SH_NI1_ERROR_MASK_2 0x0000000150040650 -#define SH_NI1_ERROR_MASK_2_MASK 0x7fffffff003fffff -#define SH_NI1_ERROR_MASK_2_INIT 0x7fffffff003fffff - -/* SH_NI1_ERROR_MASK_2_ILLEGAL_VCNI */ -/* Description: Illegal VC NI */ -#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCNI_SHFT 0 -#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCNI_MASK 0x0000000000000001 - -/* SH_NI1_ERROR_MASK_2_ILLEGAL_VCPI */ -/* Description: Illegal VC PI */ -#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCPI_SHFT 1 -#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCPI_MASK 0x0000000000000002 - -/* SH_NI1_ERROR_MASK_2_ILLEGAL_VCMD */ -/* Description: Illegal VC MD */ -#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCMD_SHFT 2 -#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCMD_MASK 0x0000000000000004 - -/* SH_NI1_ERROR_MASK_2_ILLEGAL_VCIILB */ -/* Description: Illegal VC IILB */ -#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCIILB_SHFT 3 -#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCIILB_MASK 0x0000000000000008 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit underflow 0 */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit underflow 1 */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit underflow 2 */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit underflow 0 */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit underflow 1 */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit underflow 2 */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC0 */ -/* Description: llp deadlock vc0 */ -#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC0_SHFT 56 -#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000 - -/* SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC1 */ -/* Description: llp deadlock vc1 */ -#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC1_SHFT 57 -#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000 - -/* SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC2 */ -/* Description: llp deadlock vc2 */ -#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC2_SHFT 58 -#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000 - -/* SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC3 */ -/* Description: llp deadlock vc3 */ -#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC3_SHFT 59 -#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000 - -/* SH_NI1_ERROR_MASK_2_CHIPLET_NOMATCH */ -/* Description: chiplet nomatch */ -#define SH_NI1_ERROR_MASK_2_CHIPLET_NOMATCH_SHFT 60 -#define SH_NI1_ERROR_MASK_2_CHIPLET_NOMATCH_MASK 0x1000000000000000 - -/* SH_NI1_ERROR_MASK_2_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_NI1_ERROR_MASK_2_LUT_READ_ERROR_SHFT 61 -#define SH_NI1_ERROR_MASK_2_LUT_READ_ERROR_MASK 0x2000000000000000 - -/* SH_NI1_ERROR_MASK_2_RETRY_TIMEOUT_ERROR */ -/* Description: Retry Timeout Error */ -#define SH_NI1_ERROR_MASK_2_RETRY_TIMEOUT_ERROR_SHFT 62 -#define SH_NI1_ERROR_MASK_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI1_FIRST_ERROR_1" */ -/* ni1 First Error Bits */ -/* ==================================================================== */ - -#define SH_NI1_FIRST_ERROR_1 0x0000000150040660 -#define SH_NI1_FIRST_ERROR_1_MASK 0xffffffffffffffff -#define SH_NI1_FIRST_ERROR_1_INIT 0xffffffffffffffff - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0 */ -/* Description: Fifo 02 debit0 overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2 */ -/* Description: Fifo 02 debit2 overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0 */ -/* Description: Fifo 13 debit0 overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2 */ -/* Description: Fifo 13 debit2 overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit overflow 0 */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit overflow 1 */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit overflow 2 */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit overflow 0 */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit overflow 1 */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit overflow 2 */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0 */ -/* Description: PI Fifo debit0 overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2 */ -/* Description: PI Fifo debit2 overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0 */ -/* Description: IILB Fifo debit0 overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2 */ -/* Description: IILB Fifo debit2 overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0 */ -/* Description: MD Fifo debit0 overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2 */ -/* Description: MD Fifo debit2 overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0 */ -/* Description: NI Fifo debit0 overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1 */ -/* Description: NI Fifo debit1 overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2 */ -/* Description: NI Fifo debit2 overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3 */ -/* Description: NI Fifo debit3 overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0 */ -/* Description: Fifo02 vc0 tail timeout */ -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56 -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000 - -/* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2 */ -/* Description: Fifo02 vc2 tail timeout */ -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57 -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000 - -/* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1 */ -/* Description: Fifo13 vc1 tail timeout */ -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58 -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000 - -/* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3 */ -/* Description: Fifo13 vc3 tail timeout */ -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59 -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000 - -/* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0 */ -/* Description: NI vc0 tail timeout */ -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0_SHFT 60 -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000 - -/* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1 */ -/* Description: NI vc1 tail timeout */ -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1_SHFT 61 -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000 - -/* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2 */ -/* Description: NI vc2 tail timeout */ -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2_SHFT 62 -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000 - -/* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3 */ -/* Description: NI vc3 tail timeout */ -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3_SHFT 63 -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI1_FIRST_ERROR_2" */ -/* ni1 First Error Bits */ -/* ==================================================================== */ - -#define SH_NI1_FIRST_ERROR_2 0x0000000150040670 -#define SH_NI1_FIRST_ERROR_2_MASK 0x7fffffff003fffff -#define SH_NI1_FIRST_ERROR_2_INIT 0x7fffffff003fffff - -/* SH_NI1_FIRST_ERROR_2_ILLEGAL_VCNI */ -/* Description: Illegal VC NI */ -#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCNI_SHFT 0 -#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCNI_MASK 0x0000000000000001 - -/* SH_NI1_FIRST_ERROR_2_ILLEGAL_VCPI */ -/* Description: Illegal VC PI */ -#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCPI_SHFT 1 -#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCPI_MASK 0x0000000000000002 - -/* SH_NI1_FIRST_ERROR_2_ILLEGAL_VCMD */ -/* Description: Illegal VC MD */ -#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCMD_SHFT 2 -#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCMD_MASK 0x0000000000000004 - -/* SH_NI1_FIRST_ERROR_2_ILLEGAL_VCIILB */ -/* Description: Illegal VC IILB */ -#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCIILB_SHFT 3 -#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCIILB_MASK 0x0000000000000008 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit underflow 0 */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit underflow 1 */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit underflow 2 */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit underflow 0 */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit underflow 1 */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit underflow 2 */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC0 */ -/* Description: llp deadlock vc0 */ -#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC0_SHFT 56 -#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000 - -/* SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC1 */ -/* Description: llp deadlock vc1 */ -#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC1_SHFT 57 -#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000 - -/* SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC2 */ -/* Description: llp deadlock vc2 */ -#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC2_SHFT 58 -#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000 - -/* SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC3 */ -/* Description: llp deadlock vc3 */ -#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC3_SHFT 59 -#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000 - -/* SH_NI1_FIRST_ERROR_2_CHIPLET_NOMATCH */ -/* Description: chiplet nomatch */ -#define SH_NI1_FIRST_ERROR_2_CHIPLET_NOMATCH_SHFT 60 -#define SH_NI1_FIRST_ERROR_2_CHIPLET_NOMATCH_MASK 0x1000000000000000 - -/* SH_NI1_FIRST_ERROR_2_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_NI1_FIRST_ERROR_2_LUT_READ_ERROR_SHFT 61 -#define SH_NI1_FIRST_ERROR_2_LUT_READ_ERROR_MASK 0x2000000000000000 - -/* SH_NI1_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR */ -/* Description: Retry Timeout Error */ -#define SH_NI1_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR_SHFT 62 -#define SH_NI1_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_DETAIL_1" */ -/* ni1 Chiplet no match header bits 63:0 */ -/* ==================================================================== */ - -#define SH_NI1_ERROR_DETAIL_1 0x0000000150040680 -#define SH_NI1_ERROR_DETAIL_1_MASK 0xffffffffffffffff -#define SH_NI1_ERROR_DETAIL_1_INIT 0x0000000000000000 - -/* SH_NI1_ERROR_DETAIL_1_HEADER */ -/* Description: Header bits 63:0 */ -#define SH_NI1_ERROR_DETAIL_1_HEADER_SHFT 0 -#define SH_NI1_ERROR_DETAIL_1_HEADER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_DETAIL_2" */ -/* ni1 Chiplet no match header bits 127:64 */ -/* ==================================================================== */ - -#define SH_NI1_ERROR_DETAIL_2 0x0000000150040690 -#define SH_NI1_ERROR_DETAIL_2_MASK 0xffffffffffffffff -#define SH_NI1_ERROR_DETAIL_2_INIT 0x0000000000000000 - -/* SH_NI1_ERROR_DETAIL_2_HEADER */ -/* Description: Header bits 127:64 */ -#define SH_NI1_ERROR_DETAIL_2_HEADER_SHFT 0 -#define SH_NI1_ERROR_DETAIL_2_HEADER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_CORRECTED_DETAIL_1" */ -/* Corrected error details */ -/* ==================================================================== */ - -#define SH_XN_CORRECTED_DETAIL_1 0x0000000150040070 -#define SH_XN_CORRECTED_DETAIL_1_MASK 0x0fff0fff0fff0fff -#define SH_XN_CORRECTED_DETAIL_1_INIT 0x0000000000000000 - -/* SH_XN_CORRECTED_DETAIL_1_ECC0_SYNDROME */ -/* Description: ECC0 Syndrome */ -#define SH_XN_CORRECTED_DETAIL_1_ECC0_SYNDROME_SHFT 0 -#define SH_XN_CORRECTED_DETAIL_1_ECC0_SYNDROME_MASK 0x00000000000000ff - -/* SH_XN_CORRECTED_DETAIL_1_ECC0_WC */ -/* Description: ECC0 Word Count */ -#define SH_XN_CORRECTED_DETAIL_1_ECC0_WC_SHFT 8 -#define SH_XN_CORRECTED_DETAIL_1_ECC0_WC_MASK 0x0000000000000300 - -/* SH_XN_CORRECTED_DETAIL_1_ECC0_VC */ -/* Description: ECC0 Virtual Channel */ -#define SH_XN_CORRECTED_DETAIL_1_ECC0_VC_SHFT 10 -#define SH_XN_CORRECTED_DETAIL_1_ECC0_VC_MASK 0x0000000000000c00 - -/* SH_XN_CORRECTED_DETAIL_1_ECC1_SYNDROME */ -/* Description: ECC1 Syndrome */ -#define SH_XN_CORRECTED_DETAIL_1_ECC1_SYNDROME_SHFT 16 -#define SH_XN_CORRECTED_DETAIL_1_ECC1_SYNDROME_MASK 0x0000000000ff0000 - -/* SH_XN_CORRECTED_DETAIL_1_ECC1_WC */ -/* Description: ECC1 Word Count */ -#define SH_XN_CORRECTED_DETAIL_1_ECC1_WC_SHFT 24 -#define SH_XN_CORRECTED_DETAIL_1_ECC1_WC_MASK 0x0000000003000000 - -/* SH_XN_CORRECTED_DETAIL_1_ECC1_VC */ -/* Description: ECC1 Virtual Channel */ -#define SH_XN_CORRECTED_DETAIL_1_ECC1_VC_SHFT 26 -#define SH_XN_CORRECTED_DETAIL_1_ECC1_VC_MASK 0x000000000c000000 - -/* SH_XN_CORRECTED_DETAIL_1_ECC2_SYNDROME */ -/* Description: ECC2 Syndrome */ -#define SH_XN_CORRECTED_DETAIL_1_ECC2_SYNDROME_SHFT 32 -#define SH_XN_CORRECTED_DETAIL_1_ECC2_SYNDROME_MASK 0x000000ff00000000 - -/* SH_XN_CORRECTED_DETAIL_1_ECC2_WC */ -/* Description: ECC2 Word Count */ -#define SH_XN_CORRECTED_DETAIL_1_ECC2_WC_SHFT 40 -#define SH_XN_CORRECTED_DETAIL_1_ECC2_WC_MASK 0x0000030000000000 - -/* SH_XN_CORRECTED_DETAIL_1_ECC2_VC */ -/* Description: ECC2 Virtual Channel */ -#define SH_XN_CORRECTED_DETAIL_1_ECC2_VC_SHFT 42 -#define SH_XN_CORRECTED_DETAIL_1_ECC2_VC_MASK 0x00000c0000000000 - -/* SH_XN_CORRECTED_DETAIL_1_ECC3_SYNDROME */ -/* Description: ECC3 Syndrome */ -#define SH_XN_CORRECTED_DETAIL_1_ECC3_SYNDROME_SHFT 48 -#define SH_XN_CORRECTED_DETAIL_1_ECC3_SYNDROME_MASK 0x00ff000000000000 - -/* SH_XN_CORRECTED_DETAIL_1_ECC3_WC */ -/* Description: ECC3 Word Count */ -#define SH_XN_CORRECTED_DETAIL_1_ECC3_WC_SHFT 56 -#define SH_XN_CORRECTED_DETAIL_1_ECC3_WC_MASK 0x0300000000000000 - -/* SH_XN_CORRECTED_DETAIL_1_ECC3_VC */ -/* Description: ECC3 Virtual Channel */ -#define SH_XN_CORRECTED_DETAIL_1_ECC3_VC_SHFT 58 -#define SH_XN_CORRECTED_DETAIL_1_ECC3_VC_MASK 0x0c00000000000000 - -/* ==================================================================== */ -/* Register "SH_XN_CORRECTED_DETAIL_2" */ -/* Corrected error data */ -/* ==================================================================== */ - -#define SH_XN_CORRECTED_DETAIL_2 0x0000000150040080 -#define SH_XN_CORRECTED_DETAIL_2_MASK 0xffffffffffffffff -#define SH_XN_CORRECTED_DETAIL_2_INIT 0x0000000000000000 - -/* SH_XN_CORRECTED_DETAIL_2_DATA */ -/* Description: ECC data */ -#define SH_XN_CORRECTED_DETAIL_2_DATA_SHFT 0 -#define SH_XN_CORRECTED_DETAIL_2_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_CORRECTED_DETAIL_3" */ -/* Corrected error header0 */ -/* ==================================================================== */ - -#define SH_XN_CORRECTED_DETAIL_3 0x0000000150040090 -#define SH_XN_CORRECTED_DETAIL_3_MASK 0xffffffffffffffff -#define SH_XN_CORRECTED_DETAIL_3_INIT 0x0000000000000000 - -/* SH_XN_CORRECTED_DETAIL_3_HEADER0 */ -/* Description: ECC header0 (bits 63 - 0) */ -#define SH_XN_CORRECTED_DETAIL_3_HEADER0_SHFT 0 -#define SH_XN_CORRECTED_DETAIL_3_HEADER0_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_CORRECTED_DETAIL_4" */ -/* Corrected error header1 */ -/* ==================================================================== */ - -#define SH_XN_CORRECTED_DETAIL_4 0x00000001500400a0 -#define SH_XN_CORRECTED_DETAIL_4_MASK 0xc00003ffffffffff -#define SH_XN_CORRECTED_DETAIL_4_INIT 0x0000000000000000 - -/* SH_XN_CORRECTED_DETAIL_4_HEADER1 */ -/* Description: ECC header1 (bits 104 - 64) */ -#define SH_XN_CORRECTED_DETAIL_4_HEADER1_SHFT 0 -#define SH_XN_CORRECTED_DETAIL_4_HEADER1_MASK 0x000003ffffffffff - -/* SH_XN_CORRECTED_DETAIL_4_ERR_GROUP */ -/* Description: Error group */ -#define SH_XN_CORRECTED_DETAIL_4_ERR_GROUP_SHFT 62 -#define SH_XN_CORRECTED_DETAIL_4_ERR_GROUP_MASK 0xc000000000000000 - -/* ==================================================================== */ -/* Register "SH_XN_UNCORRECTED_DETAIL_1" */ -/* Uncorrected error details */ -/* ==================================================================== */ - -#define SH_XN_UNCORRECTED_DETAIL_1 0x00000001500400b0 -#define SH_XN_UNCORRECTED_DETAIL_1_MASK 0x0fff0fff0fff0fff -#define SH_XN_UNCORRECTED_DETAIL_1_INIT 0x0000000000000000 - -/* SH_XN_UNCORRECTED_DETAIL_1_ECC0_SYNDROME */ -/* Description: ECC0 Syndrome */ -#define SH_XN_UNCORRECTED_DETAIL_1_ECC0_SYNDROME_SHFT 0 -#define SH_XN_UNCORRECTED_DETAIL_1_ECC0_SYNDROME_MASK 0x00000000000000ff - -/* SH_XN_UNCORRECTED_DETAIL_1_ECC0_WC */ -/* Description: ECC0 Word Count */ -#define SH_XN_UNCORRECTED_DETAIL_1_ECC0_WC_SHFT 8 -#define SH_XN_UNCORRECTED_DETAIL_1_ECC0_WC_MASK 0x0000000000000300 - -/* SH_XN_UNCORRECTED_DETAIL_1_ECC0_VC */ -/* Description: ECC0 Virtual Channel */ -#define SH_XN_UNCORRECTED_DETAIL_1_ECC0_VC_SHFT 10 -#define SH_XN_UNCORRECTED_DETAIL_1_ECC0_VC_MASK 0x0000000000000c00 - -/* SH_XN_UNCORRECTED_DETAIL_1_ECC1_SYNDROME */ -/* Description: ECC1 Syndrome */ -#define SH_XN_UNCORRECTED_DETAIL_1_ECC1_SYNDROME_SHFT 16 -#define SH_XN_UNCORRECTED_DETAIL_1_ECC1_SYNDROME_MASK 0x0000000000ff0000 - -/* SH_XN_UNCORRECTED_DETAIL_1_ECC1_WC */ -/* Description: ECC1 Word Count */ -#define SH_XN_UNCORRECTED_DETAIL_1_ECC1_WC_SHFT 24 -#define SH_XN_UNCORRECTED_DETAIL_1_ECC1_WC_MASK 0x0000000003000000 - -/* SH_XN_UNCORRECTED_DETAIL_1_ECC1_VC */ -/* Description: ECC1 Virtual Channel */ -#define SH_XN_UNCORRECTED_DETAIL_1_ECC1_VC_SHFT 26 -#define SH_XN_UNCORRECTED_DETAIL_1_ECC1_VC_MASK 0x000000000c000000 - -/* SH_XN_UNCORRECTED_DETAIL_1_ECC2_SYNDROME */ -/* Description: ECC2 Syndrome */ -#define SH_XN_UNCORRECTED_DETAIL_1_ECC2_SYNDROME_SHFT 32 -#define SH_XN_UNCORRECTED_DETAIL_1_ECC2_SYNDROME_MASK 0x000000ff00000000 - -/* SH_XN_UNCORRECTED_DETAIL_1_ECC2_WC */ -/* Description: ECC2 Word Count */ -#define SH_XN_UNCORRECTED_DETAIL_1_ECC2_WC_SHFT 40 -#define SH_XN_UNCORRECTED_DETAIL_1_ECC2_WC_MASK 0x0000030000000000 - -/* SH_XN_UNCORRECTED_DETAIL_1_ECC2_VC */ -/* Description: ECC2 Virtual Channel */ -#define SH_XN_UNCORRECTED_DETAIL_1_ECC2_VC_SHFT 42 -#define SH_XN_UNCORRECTED_DETAIL_1_ECC2_VC_MASK 0x00000c0000000000 - -/* SH_XN_UNCORRECTED_DETAIL_1_ECC3_SYNDROME */ -/* Description: ECC3 Syndrome */ -#define SH_XN_UNCORRECTED_DETAIL_1_ECC3_SYNDROME_SHFT 48 -#define SH_XN_UNCORRECTED_DETAIL_1_ECC3_SYNDROME_MASK 0x00ff000000000000 - -/* SH_XN_UNCORRECTED_DETAIL_1_ECC3_WC */ -/* Description: ECC3 Word Count */ -#define SH_XN_UNCORRECTED_DETAIL_1_ECC3_WC_SHFT 56 -#define SH_XN_UNCORRECTED_DETAIL_1_ECC3_WC_MASK 0x0300000000000000 - -/* SH_XN_UNCORRECTED_DETAIL_1_ECC3_VC */ -/* Description: ECC3 Virtual Channel */ -#define SH_XN_UNCORRECTED_DETAIL_1_ECC3_VC_SHFT 58 -#define SH_XN_UNCORRECTED_DETAIL_1_ECC3_VC_MASK 0x0c00000000000000 - -/* ==================================================================== */ -/* Register "SH_XN_UNCORRECTED_DETAIL_2" */ -/* Uncorrected error data */ -/* ==================================================================== */ - -#define SH_XN_UNCORRECTED_DETAIL_2 0x00000001500400c0 -#define SH_XN_UNCORRECTED_DETAIL_2_MASK 0xffffffffffffffff -#define SH_XN_UNCORRECTED_DETAIL_2_INIT 0x0000000000000000 - -/* SH_XN_UNCORRECTED_DETAIL_2_DATA */ -/* Description: ECC data */ -#define SH_XN_UNCORRECTED_DETAIL_2_DATA_SHFT 0 -#define SH_XN_UNCORRECTED_DETAIL_2_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_UNCORRECTED_DETAIL_3" */ -/* Uncorrected error header0 */ -/* ==================================================================== */ - -#define SH_XN_UNCORRECTED_DETAIL_3 0x00000001500400d0 -#define SH_XN_UNCORRECTED_DETAIL_3_MASK 0xffffffffffffffff -#define SH_XN_UNCORRECTED_DETAIL_3_INIT 0x0000000000000000 - -/* SH_XN_UNCORRECTED_DETAIL_3_HEADER0 */ -/* Description: ECC header0 (bits 63 - 0) */ -#define SH_XN_UNCORRECTED_DETAIL_3_HEADER0_SHFT 0 -#define SH_XN_UNCORRECTED_DETAIL_3_HEADER0_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_UNCORRECTED_DETAIL_4" */ -/* Uncorrected error header1 */ -/* ==================================================================== */ - -#define SH_XN_UNCORRECTED_DETAIL_4 0x00000001500400e0 -#define SH_XN_UNCORRECTED_DETAIL_4_MASK 0xc00003ffffffffff -#define SH_XN_UNCORRECTED_DETAIL_4_INIT 0x0000000000000000 - -/* SH_XN_UNCORRECTED_DETAIL_4_HEADER1 */ -/* Description: ECC header1 (bits 104 - 64) */ -#define SH_XN_UNCORRECTED_DETAIL_4_HEADER1_SHFT 0 -#define SH_XN_UNCORRECTED_DETAIL_4_HEADER1_MASK 0x000003ffffffffff - -/* SH_XN_UNCORRECTED_DETAIL_4_ERR_GROUP */ -/* Description: Error group */ -#define SH_XN_UNCORRECTED_DETAIL_4_ERR_GROUP_SHFT 62 -#define SH_XN_UNCORRECTED_DETAIL_4_ERR_GROUP_MASK 0xc000000000000000 - -/* ==================================================================== */ -/* Register "SH_XNMD_ERROR_DETAIL_1" */ -/* Look Up Table Address (md) */ -/* ==================================================================== */ - -#define SH_XNMD_ERROR_DETAIL_1 0x00000001500400f0 -#define SH_XNMD_ERROR_DETAIL_1_MASK 0x00000000000007ff -#define SH_XNMD_ERROR_DETAIL_1_INIT 0x0000000000000000 - -/* SH_XNMD_ERROR_DETAIL_1_LUT_ADDR */ -/* Description: Look Up Table Read Address */ -#define SH_XNMD_ERROR_DETAIL_1_LUT_ADDR_SHFT 0 -#define SH_XNMD_ERROR_DETAIL_1_LUT_ADDR_MASK 0x00000000000007ff - -/* ==================================================================== */ -/* Register "SH_XNPI_ERROR_DETAIL_1" */ -/* Look Up Table Address (pi) */ -/* ==================================================================== */ - -#define SH_XNPI_ERROR_DETAIL_1 0x0000000150040100 -#define SH_XNPI_ERROR_DETAIL_1_MASK 0x00000000000007ff -#define SH_XNPI_ERROR_DETAIL_1_INIT 0x0000000000000000 - -/* SH_XNPI_ERROR_DETAIL_1_LUT_ADDR */ -/* Description: Look Up Table Read Address */ -#define SH_XNPI_ERROR_DETAIL_1_LUT_ADDR_SHFT 0 -#define SH_XNPI_ERROR_DETAIL_1_LUT_ADDR_MASK 0x00000000000007ff - -/* ==================================================================== */ -/* Register "SH_XNIILB_ERROR_DETAIL_1" */ -/* Chiplet NoMatch header [63:0] */ -/* ==================================================================== */ - -#define SH_XNIILB_ERROR_DETAIL_1 0x0000000150040110 -#define SH_XNIILB_ERROR_DETAIL_1_MASK 0xffffffffffffffff -#define SH_XNIILB_ERROR_DETAIL_1_INIT 0x0000000000000000 - -/* SH_XNIILB_ERROR_DETAIL_1_HEADER */ -/* Description: header bits [63:0] */ -#define SH_XNIILB_ERROR_DETAIL_1_HEADER_SHFT 0 -#define SH_XNIILB_ERROR_DETAIL_1_HEADER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XNIILB_ERROR_DETAIL_2" */ -/* Chiplet NoMatch header [127:64] */ -/* ==================================================================== */ - -#define SH_XNIILB_ERROR_DETAIL_2 0x0000000150040120 -#define SH_XNIILB_ERROR_DETAIL_2_MASK 0xffffffffffffffff -#define SH_XNIILB_ERROR_DETAIL_2_INIT 0x0000000000000000 - -/* SH_XNIILB_ERROR_DETAIL_2_HEADER */ -/* Description: header bits [127:64] */ -#define SH_XNIILB_ERROR_DETAIL_2_HEADER_SHFT 0 -#define SH_XNIILB_ERROR_DETAIL_2_HEADER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XNIILB_ERROR_DETAIL_3" */ -/* Look Up Table Address (iilb) */ -/* ==================================================================== */ - -#define SH_XNIILB_ERROR_DETAIL_3 0x0000000150040130 -#define SH_XNIILB_ERROR_DETAIL_3_MASK 0x00000000000007ff -#define SH_XNIILB_ERROR_DETAIL_3_INIT 0x0000000000000000 - -/* SH_XNIILB_ERROR_DETAIL_3_LUT_ADDR */ -/* Description: Look Up Table Read Address */ -#define SH_XNIILB_ERROR_DETAIL_3_LUT_ADDR_SHFT 0 -#define SH_XNIILB_ERROR_DETAIL_3_LUT_ADDR_MASK 0x00000000000007ff - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_DETAIL_3" */ -/* Look Up Table Address (ni0) */ -/* ==================================================================== */ - -#define SH_NI0_ERROR_DETAIL_3 0x0000000150040140 -#define SH_NI0_ERROR_DETAIL_3_MASK 0x00000000000007ff -#define SH_NI0_ERROR_DETAIL_3_INIT 0x0000000000000000 - -/* SH_NI0_ERROR_DETAIL_3_LUT_ADDR */ -/* Description: Look Up Table Read Address */ -#define SH_NI0_ERROR_DETAIL_3_LUT_ADDR_SHFT 0 -#define SH_NI0_ERROR_DETAIL_3_LUT_ADDR_MASK 0x00000000000007ff - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_DETAIL_3" */ -/* Look Up Table Address (ni1) */ -/* ==================================================================== */ - -#define SH_NI1_ERROR_DETAIL_3 0x0000000150040150 -#define SH_NI1_ERROR_DETAIL_3_MASK 0x00000000000007ff -#define SH_NI1_ERROR_DETAIL_3_INIT 0x0000000000000000 - -/* SH_NI1_ERROR_DETAIL_3_LUT_ADDR */ -/* Description: Look Up Table Read Address */ -#define SH_NI1_ERROR_DETAIL_3_LUT_ADDR_SHFT 0 -#define SH_NI1_ERROR_DETAIL_3_LUT_ADDR_MASK 0x00000000000007ff - -/* ==================================================================== */ -/* Register "SH_XN_ERROR_SUMMARY" */ -/* ==================================================================== */ - -#define SH_XN_ERROR_SUMMARY 0x0000000150040000 -#define SH_XN_ERROR_SUMMARY_MASK 0x0000003fffffffff -#define SH_XN_ERROR_SUMMARY_INIT 0x0000003fffffffff - -/* SH_XN_ERROR_SUMMARY_NI0_POP_OVERFLOW */ -/* Description: NI0 pop overflow */ -#define SH_XN_ERROR_SUMMARY_NI0_POP_OVERFLOW_SHFT 0 -#define SH_XN_ERROR_SUMMARY_NI0_POP_OVERFLOW_MASK 0x0000000000000001 - -/* SH_XN_ERROR_SUMMARY_NI0_PUSH_OVERFLOW */ -/* Description: NI0 push overflow */ -#define SH_XN_ERROR_SUMMARY_NI0_PUSH_OVERFLOW_SHFT 1 -#define SH_XN_ERROR_SUMMARY_NI0_PUSH_OVERFLOW_MASK 0x0000000000000002 - -/* SH_XN_ERROR_SUMMARY_NI0_CREDIT_OVERFLOW */ -/* Description: NI0 credit overflow */ -#define SH_XN_ERROR_SUMMARY_NI0_CREDIT_OVERFLOW_SHFT 2 -#define SH_XN_ERROR_SUMMARY_NI0_CREDIT_OVERFLOW_MASK 0x0000000000000004 - -/* SH_XN_ERROR_SUMMARY_NI0_DEBIT_OVERFLOW */ -/* Description: NI0 debit overflow */ -#define SH_XN_ERROR_SUMMARY_NI0_DEBIT_OVERFLOW_SHFT 3 -#define SH_XN_ERROR_SUMMARY_NI0_DEBIT_OVERFLOW_MASK 0x0000000000000008 - -/* SH_XN_ERROR_SUMMARY_NI0_POP_UNDERFLOW */ -/* Description: NI0 pop underflow */ -#define SH_XN_ERROR_SUMMARY_NI0_POP_UNDERFLOW_SHFT 4 -#define SH_XN_ERROR_SUMMARY_NI0_POP_UNDERFLOW_MASK 0x0000000000000010 - -/* SH_XN_ERROR_SUMMARY_NI0_PUSH_UNDERFLOW */ -/* Description: NI0 push underflow */ -#define SH_XN_ERROR_SUMMARY_NI0_PUSH_UNDERFLOW_SHFT 5 -#define SH_XN_ERROR_SUMMARY_NI0_PUSH_UNDERFLOW_MASK 0x0000000000000020 - -/* SH_XN_ERROR_SUMMARY_NI0_CREDIT_UNDERFLOW */ -/* Description: NI0 credit underflow */ -#define SH_XN_ERROR_SUMMARY_NI0_CREDIT_UNDERFLOW_SHFT 6 -#define SH_XN_ERROR_SUMMARY_NI0_CREDIT_UNDERFLOW_MASK 0x0000000000000040 - -/* SH_XN_ERROR_SUMMARY_NI0_LLP_ERROR */ -/* Description: NI0 llp error */ -#define SH_XN_ERROR_SUMMARY_NI0_LLP_ERROR_SHFT 7 -#define SH_XN_ERROR_SUMMARY_NI0_LLP_ERROR_MASK 0x0000000000000080 - -/* SH_XN_ERROR_SUMMARY_NI0_PIPE_ERROR */ -/* Description: NI0 Pipe in/out errors */ -#define SH_XN_ERROR_SUMMARY_NI0_PIPE_ERROR_SHFT 8 -#define SH_XN_ERROR_SUMMARY_NI0_PIPE_ERROR_MASK 0x0000000000000100 - -/* SH_XN_ERROR_SUMMARY_NI1_POP_OVERFLOW */ -/* Description: NI1 pop overflow */ -#define SH_XN_ERROR_SUMMARY_NI1_POP_OVERFLOW_SHFT 9 -#define SH_XN_ERROR_SUMMARY_NI1_POP_OVERFLOW_MASK 0x0000000000000200 - -/* SH_XN_ERROR_SUMMARY_NI1_PUSH_OVERFLOW */ -/* Description: NI1 push overflow */ -#define SH_XN_ERROR_SUMMARY_NI1_PUSH_OVERFLOW_SHFT 10 -#define SH_XN_ERROR_SUMMARY_NI1_PUSH_OVERFLOW_MASK 0x0000000000000400 - -/* SH_XN_ERROR_SUMMARY_NI1_CREDIT_OVERFLOW */ -/* Description: NI1 credit overflow */ -#define SH_XN_ERROR_SUMMARY_NI1_CREDIT_OVERFLOW_SHFT 11 -#define SH_XN_ERROR_SUMMARY_NI1_CREDIT_OVERFLOW_MASK 0x0000000000000800 - -/* SH_XN_ERROR_SUMMARY_NI1_DEBIT_OVERFLOW */ -/* Description: NI1 debit overflow */ -#define SH_XN_ERROR_SUMMARY_NI1_DEBIT_OVERFLOW_SHFT 12 -#define SH_XN_ERROR_SUMMARY_NI1_DEBIT_OVERFLOW_MASK 0x0000000000001000 - -/* SH_XN_ERROR_SUMMARY_NI1_POP_UNDERFLOW */ -/* Description: NI1 pop underflow */ -#define SH_XN_ERROR_SUMMARY_NI1_POP_UNDERFLOW_SHFT 13 -#define SH_XN_ERROR_SUMMARY_NI1_POP_UNDERFLOW_MASK 0x0000000000002000 - -/* SH_XN_ERROR_SUMMARY_NI1_PUSH_UNDERFLOW */ -/* Description: NI1 push underflow */ -#define SH_XN_ERROR_SUMMARY_NI1_PUSH_UNDERFLOW_SHFT 14 -#define SH_XN_ERROR_SUMMARY_NI1_PUSH_UNDERFLOW_MASK 0x0000000000004000 - -/* SH_XN_ERROR_SUMMARY_NI1_CREDIT_UNDERFLOW */ -/* Description: NI1 credit underflow */ -#define SH_XN_ERROR_SUMMARY_NI1_CREDIT_UNDERFLOW_SHFT 15 -#define SH_XN_ERROR_SUMMARY_NI1_CREDIT_UNDERFLOW_MASK 0x0000000000008000 - -/* SH_XN_ERROR_SUMMARY_NI1_LLP_ERROR */ -/* Description: NI1 llp error */ -#define SH_XN_ERROR_SUMMARY_NI1_LLP_ERROR_SHFT 16 -#define SH_XN_ERROR_SUMMARY_NI1_LLP_ERROR_MASK 0x0000000000010000 - -/* SH_XN_ERROR_SUMMARY_NI1_PIPE_ERROR */ -/* Description: NI1 pipe in/out error */ -#define SH_XN_ERROR_SUMMARY_NI1_PIPE_ERROR_SHFT 17 -#define SH_XN_ERROR_SUMMARY_NI1_PIPE_ERROR_MASK 0x0000000000020000 - -/* SH_XN_ERROR_SUMMARY_XNMD_CREDIT_OVERFLOW */ -/* Description: XNMD credit overflow */ -#define SH_XN_ERROR_SUMMARY_XNMD_CREDIT_OVERFLOW_SHFT 18 -#define SH_XN_ERROR_SUMMARY_XNMD_CREDIT_OVERFLOW_MASK 0x0000000000040000 - -/* SH_XN_ERROR_SUMMARY_XNMD_DEBIT_OVERFLOW */ -/* Description: XNMD debit overflow */ -#define SH_XN_ERROR_SUMMARY_XNMD_DEBIT_OVERFLOW_SHFT 19 -#define SH_XN_ERROR_SUMMARY_XNMD_DEBIT_OVERFLOW_MASK 0x0000000000080000 - -/* SH_XN_ERROR_SUMMARY_XNMD_DATA_BUFF_OVERFLOW */ -/* Description: XNMD data buffer overflow */ -#define SH_XN_ERROR_SUMMARY_XNMD_DATA_BUFF_OVERFLOW_SHFT 20 -#define SH_XN_ERROR_SUMMARY_XNMD_DATA_BUFF_OVERFLOW_MASK 0x0000000000100000 - -/* SH_XN_ERROR_SUMMARY_XNMD_CREDIT_UNDERFLOW */ -/* Description: XNMD credit underflow */ -#define SH_XN_ERROR_SUMMARY_XNMD_CREDIT_UNDERFLOW_SHFT 21 -#define SH_XN_ERROR_SUMMARY_XNMD_CREDIT_UNDERFLOW_MASK 0x0000000000200000 - -/* SH_XN_ERROR_SUMMARY_XNMD_SBE_ERROR */ -/* Description: XNMD single bit error */ -#define SH_XN_ERROR_SUMMARY_XNMD_SBE_ERROR_SHFT 22 -#define SH_XN_ERROR_SUMMARY_XNMD_SBE_ERROR_MASK 0x0000000000400000 - -/* SH_XN_ERROR_SUMMARY_XNMD_UCE_ERROR */ -/* Description: XNMD uncorrectable error */ -#define SH_XN_ERROR_SUMMARY_XNMD_UCE_ERROR_SHFT 23 -#define SH_XN_ERROR_SUMMARY_XNMD_UCE_ERROR_MASK 0x0000000000800000 - -/* SH_XN_ERROR_SUMMARY_XNMD_LUT_ERROR */ -/* Description: XNMD look up table error */ -#define SH_XN_ERROR_SUMMARY_XNMD_LUT_ERROR_SHFT 24 -#define SH_XN_ERROR_SUMMARY_XNMD_LUT_ERROR_MASK 0x0000000001000000 - -/* SH_XN_ERROR_SUMMARY_XNPI_CREDIT_OVERFLOW */ -/* Description: XNMD credit overflow */ -#define SH_XN_ERROR_SUMMARY_XNPI_CREDIT_OVERFLOW_SHFT 25 -#define SH_XN_ERROR_SUMMARY_XNPI_CREDIT_OVERFLOW_MASK 0x0000000002000000 - -/* SH_XN_ERROR_SUMMARY_XNPI_DEBIT_OVERFLOW */ -/* Description: XNPI debit overflow */ -#define SH_XN_ERROR_SUMMARY_XNPI_DEBIT_OVERFLOW_SHFT 26 -#define SH_XN_ERROR_SUMMARY_XNPI_DEBIT_OVERFLOW_MASK 0x0000000004000000 - -/* SH_XN_ERROR_SUMMARY_XNPI_DATA_BUFF_OVERFLOW */ -/* Description: XNPI data buffer overflow */ -#define SH_XN_ERROR_SUMMARY_XNPI_DATA_BUFF_OVERFLOW_SHFT 27 -#define SH_XN_ERROR_SUMMARY_XNPI_DATA_BUFF_OVERFLOW_MASK 0x0000000008000000 - -/* SH_XN_ERROR_SUMMARY_XNPI_CREDIT_UNDERFLOW */ -/* Description: XNPI credit underflow */ -#define SH_XN_ERROR_SUMMARY_XNPI_CREDIT_UNDERFLOW_SHFT 28 -#define SH_XN_ERROR_SUMMARY_XNPI_CREDIT_UNDERFLOW_MASK 0x0000000010000000 - -/* SH_XN_ERROR_SUMMARY_XNPI_SBE_ERROR */ -/* Description: XNPI single bit error */ -#define SH_XN_ERROR_SUMMARY_XNPI_SBE_ERROR_SHFT 29 -#define SH_XN_ERROR_SUMMARY_XNPI_SBE_ERROR_MASK 0x0000000020000000 - -/* SH_XN_ERROR_SUMMARY_XNPI_UCE_ERROR */ -/* Description: XNPI uncorrectable error */ -#define SH_XN_ERROR_SUMMARY_XNPI_UCE_ERROR_SHFT 30 -#define SH_XN_ERROR_SUMMARY_XNPI_UCE_ERROR_MASK 0x0000000040000000 - -/* SH_XN_ERROR_SUMMARY_XNPI_LUT_ERROR */ -/* Description: XNPI look up table error */ -#define SH_XN_ERROR_SUMMARY_XNPI_LUT_ERROR_SHFT 31 -#define SH_XN_ERROR_SUMMARY_XNPI_LUT_ERROR_MASK 0x0000000080000000 - -/* SH_XN_ERROR_SUMMARY_IILB_DEBIT_OVERFLOW */ -/* Description: IILB debit overflow */ -#define SH_XN_ERROR_SUMMARY_IILB_DEBIT_OVERFLOW_SHFT 32 -#define SH_XN_ERROR_SUMMARY_IILB_DEBIT_OVERFLOW_MASK 0x0000000100000000 - -/* SH_XN_ERROR_SUMMARY_IILB_CREDIT_OVERFLOW */ -/* Description: IILB credit overflow */ -#define SH_XN_ERROR_SUMMARY_IILB_CREDIT_OVERFLOW_SHFT 33 -#define SH_XN_ERROR_SUMMARY_IILB_CREDIT_OVERFLOW_MASK 0x0000000200000000 - -/* SH_XN_ERROR_SUMMARY_IILB_FIFO_OVERFLOW */ -/* Description: IILB fifo overflow */ -#define SH_XN_ERROR_SUMMARY_IILB_FIFO_OVERFLOW_SHFT 34 -#define SH_XN_ERROR_SUMMARY_IILB_FIFO_OVERFLOW_MASK 0x0000000400000000 - -/* SH_XN_ERROR_SUMMARY_IILB_CREDIT_UNDERFLOW */ -/* Description: IILB credit underflow */ -#define SH_XN_ERROR_SUMMARY_IILB_CREDIT_UNDERFLOW_SHFT 35 -#define SH_XN_ERROR_SUMMARY_IILB_CREDIT_UNDERFLOW_MASK 0x0000000800000000 - -/* SH_XN_ERROR_SUMMARY_IILB_FIFO_UNDERFLOW */ -/* Description: IILB fifo underflow */ -#define SH_XN_ERROR_SUMMARY_IILB_FIFO_UNDERFLOW_SHFT 36 -#define SH_XN_ERROR_SUMMARY_IILB_FIFO_UNDERFLOW_MASK 0x0000001000000000 - -/* SH_XN_ERROR_SUMMARY_IILB_CHIPLET_OR_LUT */ -/* Description: IILB chiplet nomatch or lut read error */ -#define SH_XN_ERROR_SUMMARY_IILB_CHIPLET_OR_LUT_SHFT 37 -#define SH_XN_ERROR_SUMMARY_IILB_CHIPLET_OR_LUT_MASK 0x0000002000000000 - -/* ==================================================================== */ -/* Register "SH_XN_ERRORS_ALIAS" */ -/* ==================================================================== */ - -#define SH_XN_ERRORS_ALIAS 0x0000000150040008 - -/* ==================================================================== */ -/* Register "SH_XN_ERROR_OVERFLOW" */ -/* ==================================================================== */ - -#define SH_XN_ERROR_OVERFLOW 0x0000000150040020 -#define SH_XN_ERROR_OVERFLOW_MASK 0x0000003fffffffff -#define SH_XN_ERROR_OVERFLOW_INIT 0x0000003fffffffff - -/* SH_XN_ERROR_OVERFLOW_NI0_POP_OVERFLOW */ -/* Description: NI0 pop overflow */ -#define SH_XN_ERROR_OVERFLOW_NI0_POP_OVERFLOW_SHFT 0 -#define SH_XN_ERROR_OVERFLOW_NI0_POP_OVERFLOW_MASK 0x0000000000000001 - -/* SH_XN_ERROR_OVERFLOW_NI0_PUSH_OVERFLOW */ -/* Description: NI0 push overflow */ -#define SH_XN_ERROR_OVERFLOW_NI0_PUSH_OVERFLOW_SHFT 1 -#define SH_XN_ERROR_OVERFLOW_NI0_PUSH_OVERFLOW_MASK 0x0000000000000002 - -/* SH_XN_ERROR_OVERFLOW_NI0_CREDIT_OVERFLOW */ -/* Description: NI0 credit overflow */ -#define SH_XN_ERROR_OVERFLOW_NI0_CREDIT_OVERFLOW_SHFT 2 -#define SH_XN_ERROR_OVERFLOW_NI0_CREDIT_OVERFLOW_MASK 0x0000000000000004 - -/* SH_XN_ERROR_OVERFLOW_NI0_DEBIT_OVERFLOW */ -/* Description: NI0 debit overflow */ -#define SH_XN_ERROR_OVERFLOW_NI0_DEBIT_OVERFLOW_SHFT 3 -#define SH_XN_ERROR_OVERFLOW_NI0_DEBIT_OVERFLOW_MASK 0x0000000000000008 - -/* SH_XN_ERROR_OVERFLOW_NI0_POP_UNDERFLOW */ -/* Description: NI0 pop underflow */ -#define SH_XN_ERROR_OVERFLOW_NI0_POP_UNDERFLOW_SHFT 4 -#define SH_XN_ERROR_OVERFLOW_NI0_POP_UNDERFLOW_MASK 0x0000000000000010 - -/* SH_XN_ERROR_OVERFLOW_NI0_PUSH_UNDERFLOW */ -/* Description: NI0 push underflow */ -#define SH_XN_ERROR_OVERFLOW_NI0_PUSH_UNDERFLOW_SHFT 5 -#define SH_XN_ERROR_OVERFLOW_NI0_PUSH_UNDERFLOW_MASK 0x0000000000000020 - -/* SH_XN_ERROR_OVERFLOW_NI0_CREDIT_UNDERFLOW */ -/* Description: NI0 credit underflow */ -#define SH_XN_ERROR_OVERFLOW_NI0_CREDIT_UNDERFLOW_SHFT 6 -#define SH_XN_ERROR_OVERFLOW_NI0_CREDIT_UNDERFLOW_MASK 0x0000000000000040 - -/* SH_XN_ERROR_OVERFLOW_NI0_LLP_ERROR */ -/* Description: NI0 llp error */ -#define SH_XN_ERROR_OVERFLOW_NI0_LLP_ERROR_SHFT 7 -#define SH_XN_ERROR_OVERFLOW_NI0_LLP_ERROR_MASK 0x0000000000000080 - -/* SH_XN_ERROR_OVERFLOW_NI0_PIPE_ERROR */ -/* Description: NI0 Pipe in/out errors */ -#define SH_XN_ERROR_OVERFLOW_NI0_PIPE_ERROR_SHFT 8 -#define SH_XN_ERROR_OVERFLOW_NI0_PIPE_ERROR_MASK 0x0000000000000100 - -/* SH_XN_ERROR_OVERFLOW_NI1_POP_OVERFLOW */ -/* Description: NI1 pop overflow */ -#define SH_XN_ERROR_OVERFLOW_NI1_POP_OVERFLOW_SHFT 9 -#define SH_XN_ERROR_OVERFLOW_NI1_POP_OVERFLOW_MASK 0x0000000000000200 - -/* SH_XN_ERROR_OVERFLOW_NI1_PUSH_OVERFLOW */ -/* Description: NI1 push overflow */ -#define SH_XN_ERROR_OVERFLOW_NI1_PUSH_OVERFLOW_SHFT 10 -#define SH_XN_ERROR_OVERFLOW_NI1_PUSH_OVERFLOW_MASK 0x0000000000000400 - -/* SH_XN_ERROR_OVERFLOW_NI1_CREDIT_OVERFLOW */ -/* Description: NI1 credit overflow */ -#define SH_XN_ERROR_OVERFLOW_NI1_CREDIT_OVERFLOW_SHFT 11 -#define SH_XN_ERROR_OVERFLOW_NI1_CREDIT_OVERFLOW_MASK 0x0000000000000800 - -/* SH_XN_ERROR_OVERFLOW_NI1_DEBIT_OVERFLOW */ -/* Description: NI1 debit overflow */ -#define SH_XN_ERROR_OVERFLOW_NI1_DEBIT_OVERFLOW_SHFT 12 -#define SH_XN_ERROR_OVERFLOW_NI1_DEBIT_OVERFLOW_MASK 0x0000000000001000 - -/* SH_XN_ERROR_OVERFLOW_NI1_POP_UNDERFLOW */ -/* Description: NI1 pop underflow */ -#define SH_XN_ERROR_OVERFLOW_NI1_POP_UNDERFLOW_SHFT 13 -#define SH_XN_ERROR_OVERFLOW_NI1_POP_UNDERFLOW_MASK 0x0000000000002000 - -/* SH_XN_ERROR_OVERFLOW_NI1_PUSH_UNDERFLOW */ -/* Description: NI1 push underflow */ -#define SH_XN_ERROR_OVERFLOW_NI1_PUSH_UNDERFLOW_SHFT 14 -#define SH_XN_ERROR_OVERFLOW_NI1_PUSH_UNDERFLOW_MASK 0x0000000000004000 - -/* SH_XN_ERROR_OVERFLOW_NI1_CREDIT_UNDERFLOW */ -/* Description: NI1 credit underflow */ -#define SH_XN_ERROR_OVERFLOW_NI1_CREDIT_UNDERFLOW_SHFT 15 -#define SH_XN_ERROR_OVERFLOW_NI1_CREDIT_UNDERFLOW_MASK 0x0000000000008000 - -/* SH_XN_ERROR_OVERFLOW_NI1_LLP_ERROR */ -/* Description: NI1 llp error */ -#define SH_XN_ERROR_OVERFLOW_NI1_LLP_ERROR_SHFT 16 -#define SH_XN_ERROR_OVERFLOW_NI1_LLP_ERROR_MASK 0x0000000000010000 - -/* SH_XN_ERROR_OVERFLOW_NI1_PIPE_ERROR */ -/* Description: NI1 pipe in/out error */ -#define SH_XN_ERROR_OVERFLOW_NI1_PIPE_ERROR_SHFT 17 -#define SH_XN_ERROR_OVERFLOW_NI1_PIPE_ERROR_MASK 0x0000000000020000 - -/* SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_OVERFLOW */ -/* Description: XNMD credit overflow */ -#define SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_OVERFLOW_SHFT 18 -#define SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_OVERFLOW_MASK 0x0000000000040000 - -/* SH_XN_ERROR_OVERFLOW_XNMD_DEBIT_OVERFLOW */ -/* Description: XNMD debit overflow */ -#define SH_XN_ERROR_OVERFLOW_XNMD_DEBIT_OVERFLOW_SHFT 19 -#define SH_XN_ERROR_OVERFLOW_XNMD_DEBIT_OVERFLOW_MASK 0x0000000000080000 - -/* SH_XN_ERROR_OVERFLOW_XNMD_DATA_BUFF_OVERFLOW */ -/* Description: XNMD data buffer overflow */ -#define SH_XN_ERROR_OVERFLOW_XNMD_DATA_BUFF_OVERFLOW_SHFT 20 -#define SH_XN_ERROR_OVERFLOW_XNMD_DATA_BUFF_OVERFLOW_MASK 0x0000000000100000 - -/* SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_UNDERFLOW */ -/* Description: XNMD credit underflow */ -#define SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_UNDERFLOW_SHFT 21 -#define SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_UNDERFLOW_MASK 0x0000000000200000 - -/* SH_XN_ERROR_OVERFLOW_XNMD_SBE_ERROR */ -/* Description: XNMD single bit error */ -#define SH_XN_ERROR_OVERFLOW_XNMD_SBE_ERROR_SHFT 22 -#define SH_XN_ERROR_OVERFLOW_XNMD_SBE_ERROR_MASK 0x0000000000400000 - -/* SH_XN_ERROR_OVERFLOW_XNMD_UCE_ERROR */ -/* Description: XNMD uncorrectable error */ -#define SH_XN_ERROR_OVERFLOW_XNMD_UCE_ERROR_SHFT 23 -#define SH_XN_ERROR_OVERFLOW_XNMD_UCE_ERROR_MASK 0x0000000000800000 - -/* SH_XN_ERROR_OVERFLOW_XNMD_LUT_ERROR */ -/* Description: XNMD look up table error */ -#define SH_XN_ERROR_OVERFLOW_XNMD_LUT_ERROR_SHFT 24 -#define SH_XN_ERROR_OVERFLOW_XNMD_LUT_ERROR_MASK 0x0000000001000000 - -/* SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_OVERFLOW */ -/* Description: XNMD credit overflow */ -#define SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_OVERFLOW_SHFT 25 -#define SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_OVERFLOW_MASK 0x0000000002000000 - -/* SH_XN_ERROR_OVERFLOW_XNPI_DEBIT_OVERFLOW */ -/* Description: XNPI debit overflow */ -#define SH_XN_ERROR_OVERFLOW_XNPI_DEBIT_OVERFLOW_SHFT 26 -#define SH_XN_ERROR_OVERFLOW_XNPI_DEBIT_OVERFLOW_MASK 0x0000000004000000 - -/* SH_XN_ERROR_OVERFLOW_XNPI_DATA_BUFF_OVERFLOW */ -/* Description: XNPI data buffer overflow */ -#define SH_XN_ERROR_OVERFLOW_XNPI_DATA_BUFF_OVERFLOW_SHFT 27 -#define SH_XN_ERROR_OVERFLOW_XNPI_DATA_BUFF_OVERFLOW_MASK 0x0000000008000000 - -/* SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_UNDERFLOW */ -/* Description: XNPI credit underflow */ -#define SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_UNDERFLOW_SHFT 28 -#define SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_UNDERFLOW_MASK 0x0000000010000000 - -/* SH_XN_ERROR_OVERFLOW_XNPI_SBE_ERROR */ -/* Description: XNPI single bit error */ -#define SH_XN_ERROR_OVERFLOW_XNPI_SBE_ERROR_SHFT 29 -#define SH_XN_ERROR_OVERFLOW_XNPI_SBE_ERROR_MASK 0x0000000020000000 - -/* SH_XN_ERROR_OVERFLOW_XNPI_UCE_ERROR */ -/* Description: XNPI uncorrectable error */ -#define SH_XN_ERROR_OVERFLOW_XNPI_UCE_ERROR_SHFT 30 -#define SH_XN_ERROR_OVERFLOW_XNPI_UCE_ERROR_MASK 0x0000000040000000 - -/* SH_XN_ERROR_OVERFLOW_XNPI_LUT_ERROR */ -/* Description: XNPI look up table error */ -#define SH_XN_ERROR_OVERFLOW_XNPI_LUT_ERROR_SHFT 31 -#define SH_XN_ERROR_OVERFLOW_XNPI_LUT_ERROR_MASK 0x0000000080000000 - -/* SH_XN_ERROR_OVERFLOW_IILB_DEBIT_OVERFLOW */ -/* Description: IILB debit overflow */ -#define SH_XN_ERROR_OVERFLOW_IILB_DEBIT_OVERFLOW_SHFT 32 -#define SH_XN_ERROR_OVERFLOW_IILB_DEBIT_OVERFLOW_MASK 0x0000000100000000 - -/* SH_XN_ERROR_OVERFLOW_IILB_CREDIT_OVERFLOW */ -/* Description: IILB credit overflow */ -#define SH_XN_ERROR_OVERFLOW_IILB_CREDIT_OVERFLOW_SHFT 33 -#define SH_XN_ERROR_OVERFLOW_IILB_CREDIT_OVERFLOW_MASK 0x0000000200000000 - -/* SH_XN_ERROR_OVERFLOW_IILB_FIFO_OVERFLOW */ -/* Description: IILB fifo overflow */ -#define SH_XN_ERROR_OVERFLOW_IILB_FIFO_OVERFLOW_SHFT 34 -#define SH_XN_ERROR_OVERFLOW_IILB_FIFO_OVERFLOW_MASK 0x0000000400000000 - -/* SH_XN_ERROR_OVERFLOW_IILB_CREDIT_UNDERFLOW */ -/* Description: IILB credit underflow */ -#define SH_XN_ERROR_OVERFLOW_IILB_CREDIT_UNDERFLOW_SHFT 35 -#define SH_XN_ERROR_OVERFLOW_IILB_CREDIT_UNDERFLOW_MASK 0x0000000800000000 - -/* SH_XN_ERROR_OVERFLOW_IILB_FIFO_UNDERFLOW */ -/* Description: IILB fifo underflow */ -#define SH_XN_ERROR_OVERFLOW_IILB_FIFO_UNDERFLOW_SHFT 36 -#define SH_XN_ERROR_OVERFLOW_IILB_FIFO_UNDERFLOW_MASK 0x0000001000000000 - -/* SH_XN_ERROR_OVERFLOW_IILB_CHIPLET_OR_LUT */ -/* Description: IILB chiplet nomatch or lut read error */ -#define SH_XN_ERROR_OVERFLOW_IILB_CHIPLET_OR_LUT_SHFT 37 -#define SH_XN_ERROR_OVERFLOW_IILB_CHIPLET_OR_LUT_MASK 0x0000002000000000 - -/* ==================================================================== */ -/* Register "SH_XN_ERROR_OVERFLOW_ALIAS" */ -/* ==================================================================== */ - -#define SH_XN_ERROR_OVERFLOW_ALIAS 0x0000000150040028 - -/* ==================================================================== */ -/* Register "SH_XN_ERROR_MASK" */ -/* ==================================================================== */ - -#define SH_XN_ERROR_MASK 0x0000000150040040 -#define SH_XN_ERROR_MASK_MASK 0x0000003fffffffff -#define SH_XN_ERROR_MASK_INIT 0x0000003fffffffff - -/* SH_XN_ERROR_MASK_NI0_POP_OVERFLOW */ -/* Description: NI0 pop overflow */ -#define SH_XN_ERROR_MASK_NI0_POP_OVERFLOW_SHFT 0 -#define SH_XN_ERROR_MASK_NI0_POP_OVERFLOW_MASK 0x0000000000000001 - -/* SH_XN_ERROR_MASK_NI0_PUSH_OVERFLOW */ -/* Description: NI0 push overflow */ -#define SH_XN_ERROR_MASK_NI0_PUSH_OVERFLOW_SHFT 1 -#define SH_XN_ERROR_MASK_NI0_PUSH_OVERFLOW_MASK 0x0000000000000002 - -/* SH_XN_ERROR_MASK_NI0_CREDIT_OVERFLOW */ -/* Description: NI0 credit overflow */ -#define SH_XN_ERROR_MASK_NI0_CREDIT_OVERFLOW_SHFT 2 -#define SH_XN_ERROR_MASK_NI0_CREDIT_OVERFLOW_MASK 0x0000000000000004 - -/* SH_XN_ERROR_MASK_NI0_DEBIT_OVERFLOW */ -/* Description: NI0 debit overflow */ -#define SH_XN_ERROR_MASK_NI0_DEBIT_OVERFLOW_SHFT 3 -#define SH_XN_ERROR_MASK_NI0_DEBIT_OVERFLOW_MASK 0x0000000000000008 - -/* SH_XN_ERROR_MASK_NI0_POP_UNDERFLOW */ -/* Description: NI0 pop underflow */ -#define SH_XN_ERROR_MASK_NI0_POP_UNDERFLOW_SHFT 4 -#define SH_XN_ERROR_MASK_NI0_POP_UNDERFLOW_MASK 0x0000000000000010 - -/* SH_XN_ERROR_MASK_NI0_PUSH_UNDERFLOW */ -/* Description: NI0 push underflow */ -#define SH_XN_ERROR_MASK_NI0_PUSH_UNDERFLOW_SHFT 5 -#define SH_XN_ERROR_MASK_NI0_PUSH_UNDERFLOW_MASK 0x0000000000000020 - -/* SH_XN_ERROR_MASK_NI0_CREDIT_UNDERFLOW */ -/* Description: NI0 credit underflow */ -#define SH_XN_ERROR_MASK_NI0_CREDIT_UNDERFLOW_SHFT 6 -#define SH_XN_ERROR_MASK_NI0_CREDIT_UNDERFLOW_MASK 0x0000000000000040 - -/* SH_XN_ERROR_MASK_NI0_LLP_ERROR */ -/* Description: NI0 llp error */ -#define SH_XN_ERROR_MASK_NI0_LLP_ERROR_SHFT 7 -#define SH_XN_ERROR_MASK_NI0_LLP_ERROR_MASK 0x0000000000000080 - -/* SH_XN_ERROR_MASK_NI0_PIPE_ERROR */ -/* Description: NI0 Pipe in/out errors */ -#define SH_XN_ERROR_MASK_NI0_PIPE_ERROR_SHFT 8 -#define SH_XN_ERROR_MASK_NI0_PIPE_ERROR_MASK 0x0000000000000100 - -/* SH_XN_ERROR_MASK_NI1_POP_OVERFLOW */ -/* Description: NI1 pop overflow */ -#define SH_XN_ERROR_MASK_NI1_POP_OVERFLOW_SHFT 9 -#define SH_XN_ERROR_MASK_NI1_POP_OVERFLOW_MASK 0x0000000000000200 - -/* SH_XN_ERROR_MASK_NI1_PUSH_OVERFLOW */ -/* Description: NI1 push overflow */ -#define SH_XN_ERROR_MASK_NI1_PUSH_OVERFLOW_SHFT 10 -#define SH_XN_ERROR_MASK_NI1_PUSH_OVERFLOW_MASK 0x0000000000000400 - -/* SH_XN_ERROR_MASK_NI1_CREDIT_OVERFLOW */ -/* Description: NI1 credit overflow */ -#define SH_XN_ERROR_MASK_NI1_CREDIT_OVERFLOW_SHFT 11 -#define SH_XN_ERROR_MASK_NI1_CREDIT_OVERFLOW_MASK 0x0000000000000800 - -/* SH_XN_ERROR_MASK_NI1_DEBIT_OVERFLOW */ -/* Description: NI1 debit overflow */ -#define SH_XN_ERROR_MASK_NI1_DEBIT_OVERFLOW_SHFT 12 -#define SH_XN_ERROR_MASK_NI1_DEBIT_OVERFLOW_MASK 0x0000000000001000 - -/* SH_XN_ERROR_MASK_NI1_POP_UNDERFLOW */ -/* Description: NI1 pop underflow */ -#define SH_XN_ERROR_MASK_NI1_POP_UNDERFLOW_SHFT 13 -#define SH_XN_ERROR_MASK_NI1_POP_UNDERFLOW_MASK 0x0000000000002000 - -/* SH_XN_ERROR_MASK_NI1_PUSH_UNDERFLOW */ -/* Description: NI1 push underflow */ -#define SH_XN_ERROR_MASK_NI1_PUSH_UNDERFLOW_SHFT 14 -#define SH_XN_ERROR_MASK_NI1_PUSH_UNDERFLOW_MASK 0x0000000000004000 - -/* SH_XN_ERROR_MASK_NI1_CREDIT_UNDERFLOW */ -/* Description: NI1 credit underflow */ -#define SH_XN_ERROR_MASK_NI1_CREDIT_UNDERFLOW_SHFT 15 -#define SH_XN_ERROR_MASK_NI1_CREDIT_UNDERFLOW_MASK 0x0000000000008000 - -/* SH_XN_ERROR_MASK_NI1_LLP_ERROR */ -/* Description: NI1 llp error */ -#define SH_XN_ERROR_MASK_NI1_LLP_ERROR_SHFT 16 -#define SH_XN_ERROR_MASK_NI1_LLP_ERROR_MASK 0x0000000000010000 - -/* SH_XN_ERROR_MASK_NI1_PIPE_ERROR */ -/* Description: NI1 pipe in/out error */ -#define SH_XN_ERROR_MASK_NI1_PIPE_ERROR_SHFT 17 -#define SH_XN_ERROR_MASK_NI1_PIPE_ERROR_MASK 0x0000000000020000 - -/* SH_XN_ERROR_MASK_XNMD_CREDIT_OVERFLOW */ -/* Description: XNMD credit overflow */ -#define SH_XN_ERROR_MASK_XNMD_CREDIT_OVERFLOW_SHFT 18 -#define SH_XN_ERROR_MASK_XNMD_CREDIT_OVERFLOW_MASK 0x0000000000040000 - -/* SH_XN_ERROR_MASK_XNMD_DEBIT_OVERFLOW */ -/* Description: XNMD debit overflow */ -#define SH_XN_ERROR_MASK_XNMD_DEBIT_OVERFLOW_SHFT 19 -#define SH_XN_ERROR_MASK_XNMD_DEBIT_OVERFLOW_MASK 0x0000000000080000 - -/* SH_XN_ERROR_MASK_XNMD_DATA_BUFF_OVERFLOW */ -/* Description: XNMD data buffer overflow */ -#define SH_XN_ERROR_MASK_XNMD_DATA_BUFF_OVERFLOW_SHFT 20 -#define SH_XN_ERROR_MASK_XNMD_DATA_BUFF_OVERFLOW_MASK 0x0000000000100000 - -/* SH_XN_ERROR_MASK_XNMD_CREDIT_UNDERFLOW */ -/* Description: XNMD credit underflow */ -#define SH_XN_ERROR_MASK_XNMD_CREDIT_UNDERFLOW_SHFT 21 -#define SH_XN_ERROR_MASK_XNMD_CREDIT_UNDERFLOW_MASK 0x0000000000200000 - -/* SH_XN_ERROR_MASK_XNMD_SBE_ERROR */ -/* Description: XNMD single bit error */ -#define SH_XN_ERROR_MASK_XNMD_SBE_ERROR_SHFT 22 -#define SH_XN_ERROR_MASK_XNMD_SBE_ERROR_MASK 0x0000000000400000 - -/* SH_XN_ERROR_MASK_XNMD_UCE_ERROR */ -/* Description: XNMD uncorrectable error */ -#define SH_XN_ERROR_MASK_XNMD_UCE_ERROR_SHFT 23 -#define SH_XN_ERROR_MASK_XNMD_UCE_ERROR_MASK 0x0000000000800000 - -/* SH_XN_ERROR_MASK_XNMD_LUT_ERROR */ -/* Description: XNMD look up table error */ -#define SH_XN_ERROR_MASK_XNMD_LUT_ERROR_SHFT 24 -#define SH_XN_ERROR_MASK_XNMD_LUT_ERROR_MASK 0x0000000001000000 - -/* SH_XN_ERROR_MASK_XNPI_CREDIT_OVERFLOW */ -/* Description: XNMD credit overflow */ -#define SH_XN_ERROR_MASK_XNPI_CREDIT_OVERFLOW_SHFT 25 -#define SH_XN_ERROR_MASK_XNPI_CREDIT_OVERFLOW_MASK 0x0000000002000000 - -/* SH_XN_ERROR_MASK_XNPI_DEBIT_OVERFLOW */ -/* Description: XNPI debit overflow */ -#define SH_XN_ERROR_MASK_XNPI_DEBIT_OVERFLOW_SHFT 26 -#define SH_XN_ERROR_MASK_XNPI_DEBIT_OVERFLOW_MASK 0x0000000004000000 - -/* SH_XN_ERROR_MASK_XNPI_DATA_BUFF_OVERFLOW */ -/* Description: XNPI data buffer overflow */ -#define SH_XN_ERROR_MASK_XNPI_DATA_BUFF_OVERFLOW_SHFT 27 -#define SH_XN_ERROR_MASK_XNPI_DATA_BUFF_OVERFLOW_MASK 0x0000000008000000 - -/* SH_XN_ERROR_MASK_XNPI_CREDIT_UNDERFLOW */ -/* Description: XNPI credit underflow */ -#define SH_XN_ERROR_MASK_XNPI_CREDIT_UNDERFLOW_SHFT 28 -#define SH_XN_ERROR_MASK_XNPI_CREDIT_UNDERFLOW_MASK 0x0000000010000000 - -/* SH_XN_ERROR_MASK_XNPI_SBE_ERROR */ -/* Description: XNPI single bit error */ -#define SH_XN_ERROR_MASK_XNPI_SBE_ERROR_SHFT 29 -#define SH_XN_ERROR_MASK_XNPI_SBE_ERROR_MASK 0x0000000020000000 - -/* SH_XN_ERROR_MASK_XNPI_UCE_ERROR */ -/* Description: XNPI uncorrectable error */ -#define SH_XN_ERROR_MASK_XNPI_UCE_ERROR_SHFT 30 -#define SH_XN_ERROR_MASK_XNPI_UCE_ERROR_MASK 0x0000000040000000 - -/* SH_XN_ERROR_MASK_XNPI_LUT_ERROR */ -/* Description: XNPI look up table error */ -#define SH_XN_ERROR_MASK_XNPI_LUT_ERROR_SHFT 31 -#define SH_XN_ERROR_MASK_XNPI_LUT_ERROR_MASK 0x0000000080000000 - -/* SH_XN_ERROR_MASK_IILB_DEBIT_OVERFLOW */ -/* Description: IILB debit overflow */ -#define SH_XN_ERROR_MASK_IILB_DEBIT_OVERFLOW_SHFT 32 -#define SH_XN_ERROR_MASK_IILB_DEBIT_OVERFLOW_MASK 0x0000000100000000 - -/* SH_XN_ERROR_MASK_IILB_CREDIT_OVERFLOW */ -/* Description: IILB credit overflow */ -#define SH_XN_ERROR_MASK_IILB_CREDIT_OVERFLOW_SHFT 33 -#define SH_XN_ERROR_MASK_IILB_CREDIT_OVERFLOW_MASK 0x0000000200000000 - -/* SH_XN_ERROR_MASK_IILB_FIFO_OVERFLOW */ -/* Description: IILB fifo overflow */ -#define SH_XN_ERROR_MASK_IILB_FIFO_OVERFLOW_SHFT 34 -#define SH_XN_ERROR_MASK_IILB_FIFO_OVERFLOW_MASK 0x0000000400000000 - -/* SH_XN_ERROR_MASK_IILB_CREDIT_UNDERFLOW */ -/* Description: IILB credit underflow */ -#define SH_XN_ERROR_MASK_IILB_CREDIT_UNDERFLOW_SHFT 35 -#define SH_XN_ERROR_MASK_IILB_CREDIT_UNDERFLOW_MASK 0x0000000800000000 - -/* SH_XN_ERROR_MASK_IILB_FIFO_UNDERFLOW */ -/* Description: IILB fifo underflow */ -#define SH_XN_ERROR_MASK_IILB_FIFO_UNDERFLOW_SHFT 36 -#define SH_XN_ERROR_MASK_IILB_FIFO_UNDERFLOW_MASK 0x0000001000000000 - -/* SH_XN_ERROR_MASK_IILB_CHIPLET_OR_LUT */ -/* Description: IILB chiplet nomatch or lut read error */ -#define SH_XN_ERROR_MASK_IILB_CHIPLET_OR_LUT_SHFT 37 -#define SH_XN_ERROR_MASK_IILB_CHIPLET_OR_LUT_MASK 0x0000002000000000 - -/* ==================================================================== */ -/* Register "SH_XN_FIRST_ERROR" */ -/* ==================================================================== */ - -#define SH_XN_FIRST_ERROR 0x0000000150040060 -#define SH_XN_FIRST_ERROR_MASK 0x0000003fffffffff -#define SH_XN_FIRST_ERROR_INIT 0x0000003fffffffff - -/* SH_XN_FIRST_ERROR_NI0_POP_OVERFLOW */ -/* Description: NI0 pop overflow */ -#define SH_XN_FIRST_ERROR_NI0_POP_OVERFLOW_SHFT 0 -#define SH_XN_FIRST_ERROR_NI0_POP_OVERFLOW_MASK 0x0000000000000001 - -/* SH_XN_FIRST_ERROR_NI0_PUSH_OVERFLOW */ -/* Description: NI0 push overflow */ -#define SH_XN_FIRST_ERROR_NI0_PUSH_OVERFLOW_SHFT 1 -#define SH_XN_FIRST_ERROR_NI0_PUSH_OVERFLOW_MASK 0x0000000000000002 - -/* SH_XN_FIRST_ERROR_NI0_CREDIT_OVERFLOW */ -/* Description: NI0 credit overflow */ -#define SH_XN_FIRST_ERROR_NI0_CREDIT_OVERFLOW_SHFT 2 -#define SH_XN_FIRST_ERROR_NI0_CREDIT_OVERFLOW_MASK 0x0000000000000004 - -/* SH_XN_FIRST_ERROR_NI0_DEBIT_OVERFLOW */ -/* Description: NI0 debit overflow */ -#define SH_XN_FIRST_ERROR_NI0_DEBIT_OVERFLOW_SHFT 3 -#define SH_XN_FIRST_ERROR_NI0_DEBIT_OVERFLOW_MASK 0x0000000000000008 - -/* SH_XN_FIRST_ERROR_NI0_POP_UNDERFLOW */ -/* Description: NI0 pop underflow */ -#define SH_XN_FIRST_ERROR_NI0_POP_UNDERFLOW_SHFT 4 -#define SH_XN_FIRST_ERROR_NI0_POP_UNDERFLOW_MASK 0x0000000000000010 - -/* SH_XN_FIRST_ERROR_NI0_PUSH_UNDERFLOW */ -/* Description: NI0 push underflow */ -#define SH_XN_FIRST_ERROR_NI0_PUSH_UNDERFLOW_SHFT 5 -#define SH_XN_FIRST_ERROR_NI0_PUSH_UNDERFLOW_MASK 0x0000000000000020 - -/* SH_XN_FIRST_ERROR_NI0_CREDIT_UNDERFLOW */ -/* Description: NI0 credit underflow */ -#define SH_XN_FIRST_ERROR_NI0_CREDIT_UNDERFLOW_SHFT 6 -#define SH_XN_FIRST_ERROR_NI0_CREDIT_UNDERFLOW_MASK 0x0000000000000040 - -/* SH_XN_FIRST_ERROR_NI0_LLP_ERROR */ -/* Description: NI0 llp error */ -#define SH_XN_FIRST_ERROR_NI0_LLP_ERROR_SHFT 7 -#define SH_XN_FIRST_ERROR_NI0_LLP_ERROR_MASK 0x0000000000000080 - -/* SH_XN_FIRST_ERROR_NI0_PIPE_ERROR */ -/* Description: NI0 Pipe in/out errors */ -#define SH_XN_FIRST_ERROR_NI0_PIPE_ERROR_SHFT 8 -#define SH_XN_FIRST_ERROR_NI0_PIPE_ERROR_MASK 0x0000000000000100 - -/* SH_XN_FIRST_ERROR_NI1_POP_OVERFLOW */ -/* Description: NI1 pop overflow */ -#define SH_XN_FIRST_ERROR_NI1_POP_OVERFLOW_SHFT 9 -#define SH_XN_FIRST_ERROR_NI1_POP_OVERFLOW_MASK 0x0000000000000200 - -/* SH_XN_FIRST_ERROR_NI1_PUSH_OVERFLOW */ -/* Description: NI1 push overflow */ -#define SH_XN_FIRST_ERROR_NI1_PUSH_OVERFLOW_SHFT 10 -#define SH_XN_FIRST_ERROR_NI1_PUSH_OVERFLOW_MASK 0x0000000000000400 - -/* SH_XN_FIRST_ERROR_NI1_CREDIT_OVERFLOW */ -/* Description: NI1 credit overflow */ -#define SH_XN_FIRST_ERROR_NI1_CREDIT_OVERFLOW_SHFT 11 -#define SH_XN_FIRST_ERROR_NI1_CREDIT_OVERFLOW_MASK 0x0000000000000800 - -/* SH_XN_FIRST_ERROR_NI1_DEBIT_OVERFLOW */ -/* Description: NI1 debit overflow */ -#define SH_XN_FIRST_ERROR_NI1_DEBIT_OVERFLOW_SHFT 12 -#define SH_XN_FIRST_ERROR_NI1_DEBIT_OVERFLOW_MASK 0x0000000000001000 - -/* SH_XN_FIRST_ERROR_NI1_POP_UNDERFLOW */ -/* Description: NI1 pop underflow */ -#define SH_XN_FIRST_ERROR_NI1_POP_UNDERFLOW_SHFT 13 -#define SH_XN_FIRST_ERROR_NI1_POP_UNDERFLOW_MASK 0x0000000000002000 - -/* SH_XN_FIRST_ERROR_NI1_PUSH_UNDERFLOW */ -/* Description: NI1 push underflow */ -#define SH_XN_FIRST_ERROR_NI1_PUSH_UNDERFLOW_SHFT 14 -#define SH_XN_FIRST_ERROR_NI1_PUSH_UNDERFLOW_MASK 0x0000000000004000 - -/* SH_XN_FIRST_ERROR_NI1_CREDIT_UNDERFLOW */ -/* Description: NI1 credit underflow */ -#define SH_XN_FIRST_ERROR_NI1_CREDIT_UNDERFLOW_SHFT 15 -#define SH_XN_FIRST_ERROR_NI1_CREDIT_UNDERFLOW_MASK 0x0000000000008000 - -/* SH_XN_FIRST_ERROR_NI1_LLP_ERROR */ -/* Description: NI1 llp error */ -#define SH_XN_FIRST_ERROR_NI1_LLP_ERROR_SHFT 16 -#define SH_XN_FIRST_ERROR_NI1_LLP_ERROR_MASK 0x0000000000010000 - -/* SH_XN_FIRST_ERROR_NI1_PIPE_ERROR */ -/* Description: NI1 pipe in/out error */ -#define SH_XN_FIRST_ERROR_NI1_PIPE_ERROR_SHFT 17 -#define SH_XN_FIRST_ERROR_NI1_PIPE_ERROR_MASK 0x0000000000020000 - -/* SH_XN_FIRST_ERROR_XNMD_CREDIT_OVERFLOW */ -/* Description: XNMD credit overflow */ -#define SH_XN_FIRST_ERROR_XNMD_CREDIT_OVERFLOW_SHFT 18 -#define SH_XN_FIRST_ERROR_XNMD_CREDIT_OVERFLOW_MASK 0x0000000000040000 - -/* SH_XN_FIRST_ERROR_XNMD_DEBIT_OVERFLOW */ -/* Description: XNMD debit overflow */ -#define SH_XN_FIRST_ERROR_XNMD_DEBIT_OVERFLOW_SHFT 19 -#define SH_XN_FIRST_ERROR_XNMD_DEBIT_OVERFLOW_MASK 0x0000000000080000 - -/* SH_XN_FIRST_ERROR_XNMD_DATA_BUFF_OVERFLOW */ -/* Description: XNMD data buffer overflow */ -#define SH_XN_FIRST_ERROR_XNMD_DATA_BUFF_OVERFLOW_SHFT 20 -#define SH_XN_FIRST_ERROR_XNMD_DATA_BUFF_OVERFLOW_MASK 0x0000000000100000 - -/* SH_XN_FIRST_ERROR_XNMD_CREDIT_UNDERFLOW */ -/* Description: XNMD credit underflow */ -#define SH_XN_FIRST_ERROR_XNMD_CREDIT_UNDERFLOW_SHFT 21 -#define SH_XN_FIRST_ERROR_XNMD_CREDIT_UNDERFLOW_MASK 0x0000000000200000 - -/* SH_XN_FIRST_ERROR_XNMD_SBE_ERROR */ -/* Description: XNMD single bit error */ -#define SH_XN_FIRST_ERROR_XNMD_SBE_ERROR_SHFT 22 -#define SH_XN_FIRST_ERROR_XNMD_SBE_ERROR_MASK 0x0000000000400000 - -/* SH_XN_FIRST_ERROR_XNMD_UCE_ERROR */ -/* Description: XNMD uncorrectable error */ -#define SH_XN_FIRST_ERROR_XNMD_UCE_ERROR_SHFT 23 -#define SH_XN_FIRST_ERROR_XNMD_UCE_ERROR_MASK 0x0000000000800000 - -/* SH_XN_FIRST_ERROR_XNMD_LUT_ERROR */ -/* Description: XNMD look up table error */ -#define SH_XN_FIRST_ERROR_XNMD_LUT_ERROR_SHFT 24 -#define SH_XN_FIRST_ERROR_XNMD_LUT_ERROR_MASK 0x0000000001000000 - -/* SH_XN_FIRST_ERROR_XNPI_CREDIT_OVERFLOW */ -/* Description: XNMD credit overflow */ -#define SH_XN_FIRST_ERROR_XNPI_CREDIT_OVERFLOW_SHFT 25 -#define SH_XN_FIRST_ERROR_XNPI_CREDIT_OVERFLOW_MASK 0x0000000002000000 - -/* SH_XN_FIRST_ERROR_XNPI_DEBIT_OVERFLOW */ -/* Description: XNPI debit overflow */ -#define SH_XN_FIRST_ERROR_XNPI_DEBIT_OVERFLOW_SHFT 26 -#define SH_XN_FIRST_ERROR_XNPI_DEBIT_OVERFLOW_MASK 0x0000000004000000 - -/* SH_XN_FIRST_ERROR_XNPI_DATA_BUFF_OVERFLOW */ -/* Description: XNPI data buffer overflow */ -#define SH_XN_FIRST_ERROR_XNPI_DATA_BUFF_OVERFLOW_SHFT 27 -#define SH_XN_FIRST_ERROR_XNPI_DATA_BUFF_OVERFLOW_MASK 0x0000000008000000 - -/* SH_XN_FIRST_ERROR_XNPI_CREDIT_UNDERFLOW */ -/* Description: XNPI credit underflow */ -#define SH_XN_FIRST_ERROR_XNPI_CREDIT_UNDERFLOW_SHFT 28 -#define SH_XN_FIRST_ERROR_XNPI_CREDIT_UNDERFLOW_MASK 0x0000000010000000 - -/* SH_XN_FIRST_ERROR_XNPI_SBE_ERROR */ -/* Description: XNPI single bit error */ -#define SH_XN_FIRST_ERROR_XNPI_SBE_ERROR_SHFT 29 -#define SH_XN_FIRST_ERROR_XNPI_SBE_ERROR_MASK 0x0000000020000000 - -/* SH_XN_FIRST_ERROR_XNPI_UCE_ERROR */ -/* Description: XNPI uncorrectable error */ -#define SH_XN_FIRST_ERROR_XNPI_UCE_ERROR_SHFT 30 -#define SH_XN_FIRST_ERROR_XNPI_UCE_ERROR_MASK 0x0000000040000000 - -/* SH_XN_FIRST_ERROR_XNPI_LUT_ERROR */ -/* Description: XNPI look up table error */ -#define SH_XN_FIRST_ERROR_XNPI_LUT_ERROR_SHFT 31 -#define SH_XN_FIRST_ERROR_XNPI_LUT_ERROR_MASK 0x0000000080000000 - -/* SH_XN_FIRST_ERROR_IILB_DEBIT_OVERFLOW */ -/* Description: IILB debit overflow */ -#define SH_XN_FIRST_ERROR_IILB_DEBIT_OVERFLOW_SHFT 32 -#define SH_XN_FIRST_ERROR_IILB_DEBIT_OVERFLOW_MASK 0x0000000100000000 - -/* SH_XN_FIRST_ERROR_IILB_CREDIT_OVERFLOW */ -/* Description: IILB credit overflow */ -#define SH_XN_FIRST_ERROR_IILB_CREDIT_OVERFLOW_SHFT 33 -#define SH_XN_FIRST_ERROR_IILB_CREDIT_OVERFLOW_MASK 0x0000000200000000 - -/* SH_XN_FIRST_ERROR_IILB_FIFO_OVERFLOW */ -/* Description: IILB fifo overflow */ -#define SH_XN_FIRST_ERROR_IILB_FIFO_OVERFLOW_SHFT 34 -#define SH_XN_FIRST_ERROR_IILB_FIFO_OVERFLOW_MASK 0x0000000400000000 - -/* SH_XN_FIRST_ERROR_IILB_CREDIT_UNDERFLOW */ -/* Description: IILB credit underflow */ -#define SH_XN_FIRST_ERROR_IILB_CREDIT_UNDERFLOW_SHFT 35 -#define SH_XN_FIRST_ERROR_IILB_CREDIT_UNDERFLOW_MASK 0x0000000800000000 - -/* SH_XN_FIRST_ERROR_IILB_FIFO_UNDERFLOW */ -/* Description: IILB fifo underflow */ -#define SH_XN_FIRST_ERROR_IILB_FIFO_UNDERFLOW_SHFT 36 -#define SH_XN_FIRST_ERROR_IILB_FIFO_UNDERFLOW_MASK 0x0000001000000000 - -/* SH_XN_FIRST_ERROR_IILB_CHIPLET_OR_LUT */ -/* Description: IILB chiplet nomatch or lut read error */ -#define SH_XN_FIRST_ERROR_IILB_CHIPLET_OR_LUT_SHFT 37 -#define SH_XN_FIRST_ERROR_IILB_CHIPLET_OR_LUT_MASK 0x0000002000000000 - -/* ==================================================================== */ -/* Register "SH_XNIILB_ERROR_SUMMARY" */ -/* ==================================================================== */ - -#define SH_XNIILB_ERROR_SUMMARY 0x0000000150040200 -#define SH_XNIILB_ERROR_SUMMARY_MASK 0xffffffffffffffff -#define SH_XNIILB_ERROR_SUMMARY_INIT 0xffffffffffffffff - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT0 */ -/* Description: II debit0 overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT0_SHFT 0 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT0_MASK 0x0000000000000001 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT2 */ -/* Description: II debit2 overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT2_SHFT 1 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT2_MASK 0x0000000000000002 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT0 */ -/* Description: LB debit0 overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT0_SHFT 2 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT0_MASK 0x0000000000000004 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT2 */ -/* Description: LB debit2 overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT2_SHFT 3 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT2_MASK 0x0000000000000008 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC0 */ -/* Description: II VC0 fifo overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC0_SHFT 4 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC0_MASK 0x0000000000000010 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC2 */ -/* Description: II VC2 fifo overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC2_SHFT 5 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC2_MASK 0x0000000000000020 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC0 */ -/* Description: II VC0 fifo underflow */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC0_SHFT 6 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC0_MASK 0x0000000000000040 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC2 */ -/* Description: II VC2 fifo underflow */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC2_SHFT 7 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC2_MASK 0x0000000000000080 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC0 */ -/* Description: LB VC0 fifo overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC0_SHFT 8 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC0_MASK 0x0000000000000100 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC2 */ -/* Description: LB VC2 fifo overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC2_SHFT 9 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC2_MASK 0x0000000000000200 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC0 */ -/* Description: LB VC0 fifo underflow */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC0_SHFT 10 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC0_MASK 0x0000000000000400 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC2 */ -/* Description: LB VC2 fifo underflow */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC2_SHFT 11 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC2_MASK 0x0000000000000800 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_IN */ -/* Description: PI VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_IN_SHFT 12 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000001000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_IN */ -/* Description: IILB VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_IN_SHFT 13 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000002000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_IN */ -/* Description: MD VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_IN_SHFT 14 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000000004000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_IN */ -/* Description: NI0 VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_IN_SHFT 15 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000000008000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_IN */ -/* Description: NI1 VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_IN_SHFT 16 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000000010000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_IN */ -/* Description: PI VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_IN_SHFT 17 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000000020000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_IN */ -/* Description: IILB VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_IN_SHFT 18 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000000040000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_IN */ -/* Description: MD VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_IN_SHFT 19 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000000080000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_IN */ -/* Description: NI0 VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_IN_SHFT 20 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000000100000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_IN */ -/* Description: NI1 VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_IN_SHFT 21 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000000200000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_IN */ -/* Description: PI VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_IN_SHFT 22 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000400000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_IN */ -/* Description: IILB VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_IN_SHFT 23 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000800000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_IN */ -/* Description: MD VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_IN_SHFT 24 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000001000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_IN */ -/* Description: NI0 VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_IN_SHFT 25 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000002000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_IN */ -/* Description: NI1 VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_IN_SHFT 26 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000004000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_IN */ -/* Description: PI VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_IN_SHFT 27 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000008000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_IN */ -/* Description: IILB VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_IN_SHFT 28 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000010000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_IN */ -/* Description: MD VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_IN_SHFT 29 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000020000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_IN */ -/* Description: NI0 VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_IN_SHFT 30 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000040000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_IN */ -/* Description: NI1 VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_IN_SHFT 31 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000080000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT0 */ -/* Description: PI Fifo Debit0 overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT0_SHFT 32 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT0_MASK 0x0000000100000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT2 */ -/* Description: PI Fifo Debit2 overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT2_SHFT 33 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT2_MASK 0x0000000200000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0 */ -/* Description: IILB Fifo Debit0 overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_SHFT 34 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_MASK 0x0000000400000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2 */ -/* Description: IILB Fifo Debit2 overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_SHFT 35 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_MASK 0x0000000800000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT0 */ -/* Description: MD Fifo Debit0 overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT0_SHFT 36 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT0_MASK 0x0000001000000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT2 */ -/* Description: MD Fifo Debit2 overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT2_SHFT 37 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT2_MASK 0x0000002000000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0 */ -/* Description: NI0 Fifo Debit0 overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_SHFT 38 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_MASK 0x0000004000000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2 */ -/* Description: NI0 Fifo Debit2 overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_SHFT 39 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_MASK 0x0000008000000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0 */ -/* Description: NI1 Fifo Debit0 overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_SHFT 40 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_MASK 0x0000010000000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2 */ -/* Description: NI1 Fifo Debit2 overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_SHFT 41 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_MASK 0x0000020000000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_OUT_SHFT 42 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0000040000000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_OUT_SHFT 43 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0000080000000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_OUT_SHFT 44 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0000100000000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_OUT_SHFT 45 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0000200000000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_OUT_SHFT 46 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0000400000000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_OUT_SHFT 47 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0000800000000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_OUT_SHFT 48 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0001000000000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_OUT_SHFT 49 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0002000000000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_OUT_SHFT 50 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x0004000000000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_OUT_SHFT 51 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x0008000000000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_OUT_SHFT 52 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0010000000000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_OUT_SHFT 53 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0020000000000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_OUT_SHFT 54 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0040000000000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_OUT_SHFT 55 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0080000000000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_OUT_SHFT 56 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0100000000000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_OUT_SHFT 57 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0200000000000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_OUT_SHFT 58 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0400000000000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_OUT_SHFT 59 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0800000000000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_OUT_SHFT 60 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x1000000000000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_OUT_SHFT 61 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x2000000000000000 - -/* SH_XNIILB_ERROR_SUMMARY_CHIPLET_NOMATCH */ -/* Description: chiplet nomatch */ -#define SH_XNIILB_ERROR_SUMMARY_CHIPLET_NOMATCH_SHFT 62 -#define SH_XNIILB_ERROR_SUMMARY_CHIPLET_NOMATCH_MASK 0x4000000000000000 - -/* SH_XNIILB_ERROR_SUMMARY_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_XNIILB_ERROR_SUMMARY_LUT_READ_ERROR_SHFT 63 -#define SH_XNIILB_ERROR_SUMMARY_LUT_READ_ERROR_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_XNIILB_ERRORS_ALIAS" */ -/* ==================================================================== */ - -#define SH_XNIILB_ERRORS_ALIAS 0x0000000150040208 - -/* ==================================================================== */ -/* Register "SH_XNIILB_ERROR_OVERFLOW" */ -/* ==================================================================== */ - -#define SH_XNIILB_ERROR_OVERFLOW 0x0000000150040220 -#define SH_XNIILB_ERROR_OVERFLOW_MASK 0xffffffffffffffff -#define SH_XNIILB_ERROR_OVERFLOW_INIT 0xffffffffffffffff - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT0 */ -/* Description: II debit0 overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT0_SHFT 0 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT0_MASK 0x0000000000000001 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT2 */ -/* Description: II debit2 overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT2_SHFT 1 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT2_MASK 0x0000000000000002 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT0 */ -/* Description: LB debit0 overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT0_SHFT 2 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT0_MASK 0x0000000000000004 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT2 */ -/* Description: LB debit2 overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT2_SHFT 3 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT2_MASK 0x0000000000000008 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC0 */ -/* Description: II VC0 fifo overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC0_SHFT 4 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC0_MASK 0x0000000000000010 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC2 */ -/* Description: II VC2 fifo overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC2_SHFT 5 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC2_MASK 0x0000000000000020 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC0 */ -/* Description: II VC0 fifo underflow */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC0_SHFT 6 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC0_MASK 0x0000000000000040 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC2 */ -/* Description: II VC2 fifo underflow */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC2_SHFT 7 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC2_MASK 0x0000000000000080 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC0 */ -/* Description: LB VC0 fifo overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC0_SHFT 8 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC0_MASK 0x0000000000000100 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC2 */ -/* Description: LB VC2 fifo overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC2_SHFT 9 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC2_MASK 0x0000000000000200 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC0 */ -/* Description: LB VC0 fifo underflow */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC0_SHFT 10 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC0_MASK 0x0000000000000400 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC2 */ -/* Description: LB VC2 fifo underflow */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC2_SHFT 11 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC2_MASK 0x0000000000000800 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_IN */ -/* Description: PI VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_IN_SHFT 12 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000001000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_IN */ -/* Description: IILB VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_IN_SHFT 13 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000002000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_IN */ -/* Description: MD VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_IN_SHFT 14 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000000004000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_IN */ -/* Description: NI0 VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_IN_SHFT 15 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000000008000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_IN */ -/* Description: NI1 VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_IN_SHFT 16 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000000010000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_IN */ -/* Description: PI VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_IN_SHFT 17 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000000020000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_IN */ -/* Description: IILB VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_IN_SHFT 18 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000000040000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_IN */ -/* Description: MD VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_IN_SHFT 19 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000000080000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_IN */ -/* Description: NI0 VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_IN_SHFT 20 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000000100000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_IN */ -/* Description: NI1 VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_IN_SHFT 21 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000000200000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_IN */ -/* Description: PI VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_IN_SHFT 22 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000400000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_IN */ -/* Description: IILB VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_IN_SHFT 23 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000800000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_IN */ -/* Description: MD VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_IN_SHFT 24 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000001000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_IN */ -/* Description: NI0 VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_IN_SHFT 25 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000002000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_IN */ -/* Description: NI1 VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_IN_SHFT 26 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000004000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_IN */ -/* Description: PI VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_IN_SHFT 27 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000008000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_IN */ -/* Description: IILB VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_IN_SHFT 28 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000010000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_IN */ -/* Description: MD VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_IN_SHFT 29 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000020000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_IN */ -/* Description: NI0 VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_IN_SHFT 30 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000040000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_IN */ -/* Description: NI1 VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_IN_SHFT 31 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000080000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT0 */ -/* Description: PI Fifo Debit0 overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT0_SHFT 32 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT0_MASK 0x0000000100000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT2 */ -/* Description: PI Fifo Debit2 overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT2_SHFT 33 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT2_MASK 0x0000000200000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0 */ -/* Description: IILB Fifo Debit0 overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_SHFT 34 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_MASK 0x0000000400000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2 */ -/* Description: IILB Fifo Debit2 overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_SHFT 35 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_MASK 0x0000000800000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT0 */ -/* Description: MD Fifo Debit0 overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT0_SHFT 36 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT0_MASK 0x0000001000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT2 */ -/* Description: MD Fifo Debit2 overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT2_SHFT 37 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT2_MASK 0x0000002000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0 */ -/* Description: NI0 Fifo Debit0 overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_SHFT 38 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_MASK 0x0000004000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2 */ -/* Description: NI0 Fifo Debit2 overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_SHFT 39 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_MASK 0x0000008000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0 */ -/* Description: NI1 Fifo Debit0 overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_SHFT 40 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_MASK 0x0000010000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2 */ -/* Description: NI1 Fifo Debit2 overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_SHFT 41 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_MASK 0x0000020000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_OUT_SHFT 42 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0000040000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_OUT_SHFT 43 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0000080000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_OUT_SHFT 44 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0000100000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_OUT_SHFT 45 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0000200000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_OUT_SHFT 46 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0000400000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_OUT_SHFT 47 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0000800000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_OUT_SHFT 48 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0001000000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_OUT_SHFT 49 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0002000000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_OUT_SHFT 50 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x0004000000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_OUT_SHFT 51 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x0008000000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_OUT_SHFT 52 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0010000000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_OUT_SHFT 53 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0020000000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_OUT_SHFT 54 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0040000000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_OUT_SHFT 55 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0080000000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_OUT_SHFT 56 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0100000000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_OUT_SHFT 57 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0200000000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_OUT_SHFT 58 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0400000000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_OUT_SHFT 59 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0800000000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_OUT_SHFT 60 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x1000000000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_OUT_SHFT 61 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x2000000000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_CHIPLET_NOMATCH */ -/* Description: chiplet nomatch */ -#define SH_XNIILB_ERROR_OVERFLOW_CHIPLET_NOMATCH_SHFT 62 -#define SH_XNIILB_ERROR_OVERFLOW_CHIPLET_NOMATCH_MASK 0x4000000000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_XNIILB_ERROR_OVERFLOW_LUT_READ_ERROR_SHFT 63 -#define SH_XNIILB_ERROR_OVERFLOW_LUT_READ_ERROR_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_XNIILB_ERROR_OVERFLOW_ALIAS" */ -/* ==================================================================== */ - -#define SH_XNIILB_ERROR_OVERFLOW_ALIAS 0x0000000150040228 - -/* ==================================================================== */ -/* Register "SH_XNIILB_ERROR_MASK" */ -/* ==================================================================== */ - -#define SH_XNIILB_ERROR_MASK 0x0000000150040240 -#define SH_XNIILB_ERROR_MASK_MASK 0xffffffffffffffff -#define SH_XNIILB_ERROR_MASK_INIT 0xffffffffffffffff - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT0 */ -/* Description: II debit0 overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT0_SHFT 0 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT0_MASK 0x0000000000000001 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT2 */ -/* Description: II debit2 overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT2_SHFT 1 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT2_MASK 0x0000000000000002 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT0 */ -/* Description: LB debit0 overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT0_SHFT 2 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT0_MASK 0x0000000000000004 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT2 */ -/* Description: LB debit2 overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT2_SHFT 3 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT2_MASK 0x0000000000000008 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC0 */ -/* Description: II VC0 fifo overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC0_SHFT 4 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC0_MASK 0x0000000000000010 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC2 */ -/* Description: II VC2 fifo overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC2_SHFT 5 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC2_MASK 0x0000000000000020 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC0 */ -/* Description: II VC0 fifo underflow */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC0_SHFT 6 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC0_MASK 0x0000000000000040 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC2 */ -/* Description: II VC2 fifo underflow */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC2_SHFT 7 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC2_MASK 0x0000000000000080 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC0 */ -/* Description: LB VC0 fifo overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC0_SHFT 8 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC0_MASK 0x0000000000000100 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC2 */ -/* Description: LB VC2 fifo overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC2_SHFT 9 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC2_MASK 0x0000000000000200 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC0 */ -/* Description: LB VC0 fifo underflow */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC0_SHFT 10 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC0_MASK 0x0000000000000400 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC2 */ -/* Description: LB VC2 fifo underflow */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC2_SHFT 11 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC2_MASK 0x0000000000000800 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_IN */ -/* Description: PI VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_IN_SHFT 12 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000001000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_IN */ -/* Description: IILB VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_IN_SHFT 13 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000002000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_IN */ -/* Description: MD VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_IN_SHFT 14 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000000004000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_IN */ -/* Description: NI0 VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_IN_SHFT 15 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000000008000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_IN */ -/* Description: NI1 VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_IN_SHFT 16 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000000010000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_IN */ -/* Description: PI VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_IN_SHFT 17 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000000020000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_IN */ -/* Description: IILB VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_IN_SHFT 18 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000000040000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_IN */ -/* Description: MD VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_IN_SHFT 19 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000000080000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_IN */ -/* Description: NI0 VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_IN_SHFT 20 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000000100000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_IN */ -/* Description: NI1 VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_IN_SHFT 21 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000000200000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_IN */ -/* Description: PI VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_IN_SHFT 22 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000400000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_IN */ -/* Description: IILB VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_IN_SHFT 23 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000800000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_IN */ -/* Description: MD VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_IN_SHFT 24 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000001000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_IN */ -/* Description: NI0 VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_IN_SHFT 25 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000002000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_IN */ -/* Description: NI1 VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_IN_SHFT 26 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000004000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_IN */ -/* Description: PI VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_IN_SHFT 27 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000008000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_IN */ -/* Description: IILB VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_IN_SHFT 28 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000010000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_IN */ -/* Description: MD VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_IN_SHFT 29 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000020000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_IN */ -/* Description: NI0 VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_IN_SHFT 30 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000040000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_IN */ -/* Description: NI1 VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_IN_SHFT 31 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000080000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT0 */ -/* Description: PI Fifo Debit0 overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT0_SHFT 32 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT0_MASK 0x0000000100000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT2 */ -/* Description: PI Fifo Debit2 overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT2_SHFT 33 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT2_MASK 0x0000000200000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT0 */ -/* Description: IILB Fifo Debit0 overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT0_SHFT 34 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT0_MASK 0x0000000400000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT2 */ -/* Description: IILB Fifo Debit2 overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT2_SHFT 35 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT2_MASK 0x0000000800000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT0 */ -/* Description: MD Fifo Debit0 overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT0_SHFT 36 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT0_MASK 0x0000001000000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT2 */ -/* Description: MD Fifo Debit2 overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT2_SHFT 37 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT2_MASK 0x0000002000000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT0 */ -/* Description: NI0 Fifo Debit0 overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT0_SHFT 38 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT0_MASK 0x0000004000000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT2 */ -/* Description: NI0 Fifo Debit2 overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT2_SHFT 39 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT2_MASK 0x0000008000000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT0 */ -/* Description: NI1 Fifo Debit0 overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT0_SHFT 40 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT0_MASK 0x0000010000000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT2 */ -/* Description: NI1 Fifo Debit2 overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT2_SHFT 41 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT2_MASK 0x0000020000000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_OUT_SHFT 42 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0000040000000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_OUT_SHFT 43 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0000080000000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_OUT_SHFT 44 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0000100000000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_OUT_SHFT 45 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0000200000000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_OUT_SHFT 46 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0000400000000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_OUT_SHFT 47 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0000800000000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_OUT_SHFT 48 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0001000000000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_OUT_SHFT 49 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0002000000000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_OUT_SHFT 50 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x0004000000000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_OUT_SHFT 51 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x0008000000000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_OUT_SHFT 52 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0010000000000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_OUT_SHFT 53 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0020000000000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_OUT_SHFT 54 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0040000000000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_OUT_SHFT 55 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0080000000000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_OUT_SHFT 56 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0100000000000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_OUT_SHFT 57 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0200000000000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_OUT_SHFT 58 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0400000000000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_OUT_SHFT 59 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0800000000000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_OUT_SHFT 60 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x1000000000000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_OUT_SHFT 61 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x2000000000000000 - -/* SH_XNIILB_ERROR_MASK_CHIPLET_NOMATCH */ -/* Description: chiplet nomatch */ -#define SH_XNIILB_ERROR_MASK_CHIPLET_NOMATCH_SHFT 62 -#define SH_XNIILB_ERROR_MASK_CHIPLET_NOMATCH_MASK 0x4000000000000000 - -/* SH_XNIILB_ERROR_MASK_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_XNIILB_ERROR_MASK_LUT_READ_ERROR_SHFT 63 -#define SH_XNIILB_ERROR_MASK_LUT_READ_ERROR_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_XNIILB_FIRST_ERROR" */ -/* ==================================================================== */ - -#define SH_XNIILB_FIRST_ERROR 0x0000000150040260 -#define SH_XNIILB_FIRST_ERROR_MASK 0xffffffffffffffff -#define SH_XNIILB_FIRST_ERROR_INIT 0xffffffffffffffff - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT0 */ -/* Description: II debit0 overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT0_SHFT 0 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT0_MASK 0x0000000000000001 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT2 */ -/* Description: II debit2 overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT2_SHFT 1 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT2_MASK 0x0000000000000002 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT0 */ -/* Description: LB debit0 overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT0_SHFT 2 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT0_MASK 0x0000000000000004 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT2 */ -/* Description: LB debit2 overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT2_SHFT 3 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT2_MASK 0x0000000000000008 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC0 */ -/* Description: II VC0 fifo overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC0_SHFT 4 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC0_MASK 0x0000000000000010 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC2 */ -/* Description: II VC2 fifo overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC2_SHFT 5 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC2_MASK 0x0000000000000020 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC0 */ -/* Description: II VC0 fifo underflow */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC0_SHFT 6 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC0_MASK 0x0000000000000040 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC2 */ -/* Description: II VC2 fifo underflow */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC2_SHFT 7 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC2_MASK 0x0000000000000080 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC0 */ -/* Description: LB VC0 fifo overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC0_SHFT 8 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC0_MASK 0x0000000000000100 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC2 */ -/* Description: LB VC2 fifo overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC2_SHFT 9 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC2_MASK 0x0000000000000200 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC0 */ -/* Description: LB VC0 fifo underflow */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC0_SHFT 10 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC0_MASK 0x0000000000000400 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC2 */ -/* Description: LB VC2 fifo underflow */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC2_SHFT 11 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC2_MASK 0x0000000000000800 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_IN */ -/* Description: PI VC0 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_IN_SHFT 12 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000001000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_IN */ -/* Description: IILB VC0 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_IN_SHFT 13 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000002000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_IN */ -/* Description: MD VC0 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_IN_SHFT 14 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000000004000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_IN */ -/* Description: NI0 VC0 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_IN_SHFT 15 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000000008000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_IN */ -/* Description: NI1 VC0 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_IN_SHFT 16 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000000010000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_IN */ -/* Description: PI VC2 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_IN_SHFT 17 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000000020000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_IN */ -/* Description: IILB VC2 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_IN_SHFT 18 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000000040000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_IN */ -/* Description: MD VC2 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_IN_SHFT 19 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000000080000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_IN */ -/* Description: NI0 VC2 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_IN_SHFT 20 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000000100000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_IN */ -/* Description: NI1 VC2 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_IN_SHFT 21 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000000200000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_IN */ -/* Description: PI VC0 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_IN_SHFT 22 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000400000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_IN */ -/* Description: IILB VC0 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_IN_SHFT 23 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000800000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_IN */ -/* Description: MD VC0 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_IN_SHFT 24 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000001000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_IN */ -/* Description: NI0 VC0 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_IN_SHFT 25 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000002000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_IN */ -/* Description: NI1 VC0 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_IN_SHFT 26 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000004000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_IN */ -/* Description: PI VC2 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_IN_SHFT 27 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000008000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_IN */ -/* Description: IILB VC2 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_IN_SHFT 28 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000010000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_IN */ -/* Description: MD VC2 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_IN_SHFT 29 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000020000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_IN */ -/* Description: NI0 VC2 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_IN_SHFT 30 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000040000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_IN */ -/* Description: NI1 VC2 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_IN_SHFT 31 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000080000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT0 */ -/* Description: PI Fifo Debit0 overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT0_SHFT 32 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT0_MASK 0x0000000100000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT2 */ -/* Description: PI Fifo Debit2 overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT2_SHFT 33 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT2_MASK 0x0000000200000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT0 */ -/* Description: IILB Fifo Debit0 overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_SHFT 34 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_MASK 0x0000000400000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT2 */ -/* Description: IILB Fifo Debit2 overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_SHFT 35 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_MASK 0x0000000800000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT0 */ -/* Description: MD Fifo Debit0 overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT0_SHFT 36 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT0_MASK 0x0000001000000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT2 */ -/* Description: MD Fifo Debit2 overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT2_SHFT 37 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT2_MASK 0x0000002000000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT0 */ -/* Description: NI0 Fifo Debit0 overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_SHFT 38 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_MASK 0x0000004000000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT2 */ -/* Description: NI0 Fifo Debit2 overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_SHFT 39 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_MASK 0x0000008000000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT0 */ -/* Description: NI1 Fifo Debit0 overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_SHFT 40 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_MASK 0x0000010000000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT2 */ -/* Description: NI1 Fifo Debit2 overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_SHFT 41 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_MASK 0x0000020000000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_OUT_SHFT 42 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0000040000000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_OUT_SHFT 43 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0000080000000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_OUT_SHFT 44 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0000100000000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_OUT_SHFT 45 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0000200000000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_OUT_SHFT 46 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0000400000000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_OUT_SHFT 47 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0000800000000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_OUT_SHFT 48 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0001000000000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_OUT_SHFT 49 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0002000000000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_OUT_SHFT 50 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x0004000000000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_OUT_SHFT 51 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x0008000000000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_OUT_SHFT 52 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0010000000000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_OUT_SHFT 53 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0020000000000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_OUT_SHFT 54 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0040000000000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_OUT_SHFT 55 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0080000000000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_OUT_SHFT 56 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0100000000000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_OUT_SHFT 57 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0200000000000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_OUT_SHFT 58 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0400000000000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_OUT_SHFT 59 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0800000000000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_OUT_SHFT 60 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x1000000000000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_OUT_SHFT 61 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x2000000000000000 - -/* SH_XNIILB_FIRST_ERROR_CHIPLET_NOMATCH */ -/* Description: chiplet nomatch */ -#define SH_XNIILB_FIRST_ERROR_CHIPLET_NOMATCH_SHFT 62 -#define SH_XNIILB_FIRST_ERROR_CHIPLET_NOMATCH_MASK 0x4000000000000000 - -/* SH_XNIILB_FIRST_ERROR_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_XNIILB_FIRST_ERROR_LUT_READ_ERROR_SHFT 63 -#define SH_XNIILB_FIRST_ERROR_LUT_READ_ERROR_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_XNPI_ERROR_SUMMARY" */ -/* ==================================================================== */ - -#define SH_XNPI_ERROR_SUMMARY 0x0000000150040300 -#define SH_XNPI_ERROR_SUMMARY_MASK 0x0003ffffffffffff -#define SH_XNPI_ERROR_SUMMARY_INIT 0x0003ffffffffffff - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_SHFT 0 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0_SHFT 1 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0_MASK 0x0000000000000002 - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_SHFT 2 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2_SHFT 3 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2_MASK 0x0000000000000008 - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_SHFT 4 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0_SHFT 5 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0_MASK 0x0000000000000020 - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_SHFT 6 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2_SHFT 7 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2_MASK 0x0000000000000080 - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_SHFT 8 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0_SHFT 9 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0_MASK 0x0000000000000200 - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_SHFT 10 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2_SHFT 11 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2_MASK 0x0000000000000800 - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT_SHFT 12 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT_SHFT 13 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000 - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT_SHFT 14 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT_SHFT 15 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0 */ -/* Description: VC0 Data Buffer overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0_SHFT 16 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2 */ -/* Description: VC2 Data Buffer overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2_SHFT 17 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000 - -/* SH_XNPI_ERROR_SUMMARY_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_XNPI_ERROR_SUMMARY_LUT_READ_ERROR_SHFT 18 -#define SH_XNPI_ERROR_SUMMARY_LUT_READ_ERROR_MASK 0x0000000000040000 - -/* SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR0 */ -/* Description: Single Bit Error in Bits 63:0 */ -#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR0_SHFT 19 -#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR0_MASK 0x0000000000080000 - -/* SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR1 */ -/* Description: Single Bit Error in Bits 127:64 */ -#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR1_SHFT 20 -#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR1_MASK 0x0000000000100000 - -/* SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR2 */ -/* Description: Single Bit Error in Bits 191:128 */ -#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR2_SHFT 21 -#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR2_MASK 0x0000000000200000 - -/* SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR3 */ -/* Description: Single Bit Error in Bits 255:192 */ -#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR3_SHFT 22 -#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR3_MASK 0x0000000000400000 - -/* SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR0 */ -/* Description: Uncorrectable Error in Bits 63:0 */ -#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR0_SHFT 23 -#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR0_MASK 0x0000000000800000 - -/* SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR1 */ -/* Description: Uncorrectable Error in Bits 127:64 */ -#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR1_SHFT 24 -#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR1_MASK 0x0000000001000000 - -/* SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR2 */ -/* Description: Uncorrectable Error in Bits 191:128 */ -#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR2_SHFT 25 -#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR2_MASK 0x0000000002000000 - -/* SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR3 */ -/* Description: Uncorrectable Error in Bits 255:192 */ -#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR3_SHFT 26 -#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR3_MASK 0x0000000004000000 - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0_SHFT 27 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0_SHFT 28 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000 - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2_SHFT 29 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2_SHFT 30 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0 */ -/* Description: NI0 Debit 0 Overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_SHFT 31 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2 */ -/* Description: NI0 Debit 2 Overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_SHFT 32 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0 */ -/* Description: NI1 Debit 0 Overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_SHFT 33 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2 */ -/* Description: NI1 Debit 2 Overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_SHFT 34 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0 */ -/* Description: IILB Debit 0 Overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_SHFT 35 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2 */ -/* Description: IILB Debit 2 Overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_SHFT 36 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000 - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_SHFT 38 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000 - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_SHFT 40 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000 - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_SHFT 42 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000 - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_SHFT 44 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000 - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_SHFT 46 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_SHFT 48 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO */ -/* Description: Header Cancel Fifo Overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000 - -/* ==================================================================== */ -/* Register "SH_XNPI_ERRORS_ALIAS" */ -/* ==================================================================== */ - -#define SH_XNPI_ERRORS_ALIAS 0x0000000150040308 - -/* ==================================================================== */ -/* Register "SH_XNPI_ERROR_OVERFLOW" */ -/* ==================================================================== */ - -#define SH_XNPI_ERROR_OVERFLOW 0x0000000150040320 -#define SH_XNPI_ERROR_OVERFLOW_MASK 0x0003ffffffffffff -#define SH_XNPI_ERROR_OVERFLOW_INIT 0x0003ffffffffffff - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_SHFT 0 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_SHFT 1 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_MASK 0x0000000000000002 - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_SHFT 2 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_SHFT 3 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_MASK 0x0000000000000008 - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_SHFT 4 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_SHFT 5 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_MASK 0x0000000000000020 - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_SHFT 6 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_SHFT 7 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_MASK 0x0000000000000080 - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_SHFT 8 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_SHFT 9 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_MASK 0x0000000000000200 - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_SHFT 10 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_SHFT 11 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_MASK 0x0000000000000800 - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT_SHFT 12 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT_SHFT 13 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000 - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT_SHFT 14 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT_SHFT 15 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0 */ -/* Description: VC0 Data Buffer overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0_SHFT 16 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2 */ -/* Description: VC2 Data Buffer overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2_SHFT 17 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000 - -/* SH_XNPI_ERROR_OVERFLOW_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_XNPI_ERROR_OVERFLOW_LUT_READ_ERROR_SHFT 18 -#define SH_XNPI_ERROR_OVERFLOW_LUT_READ_ERROR_MASK 0x0000000000040000 - -/* SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR0 */ -/* Description: Single Bit Error in Bits 63:0 */ -#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR0_SHFT 19 -#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR0_MASK 0x0000000000080000 - -/* SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR1 */ -/* Description: Single Bit Error in Bits 127:64 */ -#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR1_SHFT 20 -#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR1_MASK 0x0000000000100000 - -/* SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR2 */ -/* Description: Single Bit Error in Bits 191:128 */ -#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR2_SHFT 21 -#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR2_MASK 0x0000000000200000 - -/* SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR3 */ -/* Description: Single Bit Error in Bits 255:192 */ -#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR3_SHFT 22 -#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR3_MASK 0x0000000000400000 - -/* SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR0 */ -/* Description: Uncorrectable Error in Bits 63:0 */ -#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR0_SHFT 23 -#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR0_MASK 0x0000000000800000 - -/* SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR1 */ -/* Description: Uncorrectable Error in Bits 127:64 */ -#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR1_SHFT 24 -#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR1_MASK 0x0000000001000000 - -/* SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR2 */ -/* Description: Uncorrectable Error in Bits 191:128 */ -#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR2_SHFT 25 -#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR2_MASK 0x0000000002000000 - -/* SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR3 */ -/* Description: Uncorrectable Error in Bits 255:192 */ -#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR3_SHFT 26 -#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR3_MASK 0x0000000004000000 - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0_SHFT 27 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0_SHFT 28 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000 - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2_SHFT 29 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2_SHFT 30 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0 */ -/* Description: NI0 Debit 0 Overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_SHFT 31 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2 */ -/* Description: NI0 Debit 2 Overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_SHFT 32 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0 */ -/* Description: NI1 Debit 0 Overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_SHFT 33 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2 */ -/* Description: NI1 Debit 2 Overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_SHFT 34 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0 */ -/* Description: IILB Debit 0 Overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_SHFT 35 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2 */ -/* Description: IILB Debit 2 Overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_SHFT 36 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000 - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_SHFT 38 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000 - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_SHFT 40 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000 - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_SHFT 42 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000 - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_SHFT 44 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000 - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_SHFT 46 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_SHFT 48 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO */ -/* Description: Header Cancel Fifo Overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000 - -/* ==================================================================== */ -/* Register "SH_XNPI_ERROR_OVERFLOW_ALIAS" */ -/* ==================================================================== */ - -#define SH_XNPI_ERROR_OVERFLOW_ALIAS 0x0000000150040328 - -/* ==================================================================== */ -/* Register "SH_XNPI_ERROR_MASK" */ -/* ==================================================================== */ - -#define SH_XNPI_ERROR_MASK 0x0000000150040340 -#define SH_XNPI_ERROR_MASK_MASK 0x0003ffffffffffff -#define SH_XNPI_ERROR_MASK_INIT 0x0003ffffffffffff - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0_SHFT 0 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0_SHFT 1 -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0_MASK 0x0000000000000002 - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2_SHFT 2 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2_SHFT 3 -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2_MASK 0x0000000000000008 - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0_SHFT 4 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0_SHFT 5 -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0_MASK 0x0000000000000020 - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2_SHFT 6 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2_SHFT 7 -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2_MASK 0x0000000000000080 - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0_SHFT 8 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0_SHFT 9 -#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0_MASK 0x0000000000000200 - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2_SHFT 10 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2_SHFT 11 -#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2_MASK 0x0000000000000800 - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_VC0_CREDIT_SHFT 12 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_VC0_CREDIT_SHFT 13 -#define SH_XNPI_ERROR_MASK_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000 - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_VC2_CREDIT_SHFT 14 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_VC2_CREDIT_SHFT 15 -#define SH_XNPI_ERROR_MASK_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC0 */ -/* Description: VC0 Data Buffer overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC0_SHFT 16 -#define SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC2 */ -/* Description: VC2 Data Buffer overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC2_SHFT 17 -#define SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000 - -/* SH_XNPI_ERROR_MASK_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_XNPI_ERROR_MASK_LUT_READ_ERROR_SHFT 18 -#define SH_XNPI_ERROR_MASK_LUT_READ_ERROR_MASK 0x0000000000040000 - -/* SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR0 */ -/* Description: Single Bit Error in Bits 63:0 */ -#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR0_SHFT 19 -#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR0_MASK 0x0000000000080000 - -/* SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR1 */ -/* Description: Single Bit Error in Bits 127:64 */ -#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR1_SHFT 20 -#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR1_MASK 0x0000000000100000 - -/* SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR2 */ -/* Description: Single Bit Error in Bits 191:128 */ -#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR2_SHFT 21 -#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR2_MASK 0x0000000000200000 - -/* SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR3 */ -/* Description: Single Bit Error in Bits 255:192 */ -#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR3_SHFT 22 -#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR3_MASK 0x0000000000400000 - -/* SH_XNPI_ERROR_MASK_UNCOR_ERROR0 */ -/* Description: Uncorrectable Error in Bits 63:0 */ -#define SH_XNPI_ERROR_MASK_UNCOR_ERROR0_SHFT 23 -#define SH_XNPI_ERROR_MASK_UNCOR_ERROR0_MASK 0x0000000000800000 - -/* SH_XNPI_ERROR_MASK_UNCOR_ERROR1 */ -/* Description: Uncorrectable Error in Bits 127:64 */ -#define SH_XNPI_ERROR_MASK_UNCOR_ERROR1_SHFT 24 -#define SH_XNPI_ERROR_MASK_UNCOR_ERROR1_MASK 0x0000000001000000 - -/* SH_XNPI_ERROR_MASK_UNCOR_ERROR2 */ -/* Description: Uncorrectable Error in Bits 191:128 */ -#define SH_XNPI_ERROR_MASK_UNCOR_ERROR2_SHFT 25 -#define SH_XNPI_ERROR_MASK_UNCOR_ERROR2_MASK 0x0000000002000000 - -/* SH_XNPI_ERROR_MASK_UNCOR_ERROR3 */ -/* Description: Uncorrectable Error in Bits 255:192 */ -#define SH_XNPI_ERROR_MASK_UNCOR_ERROR3_SHFT 26 -#define SH_XNPI_ERROR_MASK_UNCOR_ERROR3_MASK 0x0000000004000000 - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR0_SHFT 27 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR0_SHFT 28 -#define SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000 - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR2_SHFT 29 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR2_SHFT 30 -#define SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT0 */ -/* Description: NI0 Debit 0 Overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT0_SHFT 31 -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT2 */ -/* Description: NI0 Debit 2 Overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT2_SHFT 32 -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT0 */ -/* Description: NI1 Debit 0 Overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT0_SHFT 33 -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT2 */ -/* Description: NI1 Debit 2 Overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT2_SHFT 34 -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT0 */ -/* Description: IILB Debit 0 Overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT0_SHFT 35 -#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT2 */ -/* Description: IILB Debit 2 Overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT2_SHFT 36 -#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000 - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_SHFT 38 -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000 - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_SHFT 40 -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000 - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_SHFT 42 -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000 - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_SHFT 44 -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000 - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_SHFT 46 -#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_SHFT 48 -#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO */ -/* Description: Header Cancel Fifo Overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49 -#define SH_XNPI_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000 - -/* ==================================================================== */ -/* Register "SH_XNPI_FIRST_ERROR" */ -/* ==================================================================== */ - -#define SH_XNPI_FIRST_ERROR 0x0000000150040360 -#define SH_XNPI_FIRST_ERROR_MASK 0x0003ffffffffffff -#define SH_XNPI_FIRST_ERROR_INIT 0x0003ffffffffffff - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0_SHFT 0 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0_SHFT 1 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0_MASK 0x0000000000000002 - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2_SHFT 2 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2_SHFT 3 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2_MASK 0x0000000000000008 - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0_SHFT 4 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0_SHFT 5 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0_MASK 0x0000000000000020 - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2_SHFT 6 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2_SHFT 7 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2_MASK 0x0000000000000080 - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0_SHFT 8 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0_SHFT 9 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0_MASK 0x0000000000000200 - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2_SHFT 10 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2_SHFT 11 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2_MASK 0x0000000000000800 - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_VC0_CREDIT_SHFT 12 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_VC0_CREDIT_SHFT 13 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000 - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_VC2_CREDIT_SHFT 14 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_VC2_CREDIT_SHFT 15 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC0 */ -/* Description: VC0 Data Buffer overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC0_SHFT 16 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC2 */ -/* Description: VC2 Data Buffer overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC2_SHFT 17 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000 - -/* SH_XNPI_FIRST_ERROR_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_XNPI_FIRST_ERROR_LUT_READ_ERROR_SHFT 18 -#define SH_XNPI_FIRST_ERROR_LUT_READ_ERROR_MASK 0x0000000000040000 - -/* SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR0 */ -/* Description: Single Bit Error in Bits 63:0 */ -#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR0_SHFT 19 -#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR0_MASK 0x0000000000080000 - -/* SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR1 */ -/* Description: Single Bit Error in Bits 127:64 */ -#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR1_SHFT 20 -#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR1_MASK 0x0000000000100000 - -/* SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR2 */ -/* Description: Single Bit Error in Bits 191:128 */ -#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR2_SHFT 21 -#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR2_MASK 0x0000000000200000 - -/* SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR3 */ -/* Description: Single Bit Error in Bits 255:192 */ -#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR3_SHFT 22 -#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR3_MASK 0x0000000000400000 - -/* SH_XNPI_FIRST_ERROR_UNCOR_ERROR0 */ -/* Description: Uncorrectable Error in Bits 63:0 */ -#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR0_SHFT 23 -#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR0_MASK 0x0000000000800000 - -/* SH_XNPI_FIRST_ERROR_UNCOR_ERROR1 */ -/* Description: Uncorrectable Error in Bits 127:64 */ -#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR1_SHFT 24 -#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR1_MASK 0x0000000001000000 - -/* SH_XNPI_FIRST_ERROR_UNCOR_ERROR2 */ -/* Description: Uncorrectable Error in Bits 191:128 */ -#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR2_SHFT 25 -#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR2_MASK 0x0000000002000000 - -/* SH_XNPI_FIRST_ERROR_UNCOR_ERROR3 */ -/* Description: Uncorrectable Error in Bits 255:192 */ -#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR3_SHFT 26 -#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR3_MASK 0x0000000004000000 - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR0_SHFT 27 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR0_SHFT 28 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000 - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR2_SHFT 29 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR2_SHFT 30 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT0 */ -/* Description: NI0 Debit 0 Overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_SHFT 31 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT2 */ -/* Description: NI0 Debit 2 Overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_SHFT 32 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT0 */ -/* Description: NI1 Debit 0 Overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_SHFT 33 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT2 */ -/* Description: NI1 Debit 2 Overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_SHFT 34 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT0 */ -/* Description: IILB Debit 0 Overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_SHFT 35 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT2 */ -/* Description: IILB Debit 2 Overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_SHFT 36 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000 - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_SHFT 38 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000 - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_SHFT 40 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000 - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_SHFT 42 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000 - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_SHFT 44 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000 - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_SHFT 46 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_SHFT 48 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO */ -/* Description: Header Cancel Fifo Overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000 - -/* ==================================================================== */ -/* Register "SH_XNMD_ERROR_SUMMARY" */ -/* ==================================================================== */ - -#define SH_XNMD_ERROR_SUMMARY 0x0000000150040400 -#define SH_XNMD_ERROR_SUMMARY_MASK 0x0003ffffffffffff -#define SH_XNMD_ERROR_SUMMARY_INIT 0x0003ffffffffffff - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_SHFT 0 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0_SHFT 1 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0_MASK 0x0000000000000002 - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_SHFT 2 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2_SHFT 3 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2_MASK 0x0000000000000008 - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_SHFT 4 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0_SHFT 5 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0_MASK 0x0000000000000020 - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_SHFT 6 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2_SHFT 7 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2_MASK 0x0000000000000080 - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_SHFT 8 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0_SHFT 9 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0_MASK 0x0000000000000200 - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_SHFT 10 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2_SHFT 11 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2_MASK 0x0000000000000800 - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT_SHFT 12 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT_SHFT 13 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000 - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT_SHFT 14 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT_SHFT 15 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0 */ -/* Description: VC0 Data Buffer overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0_SHFT 16 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2 */ -/* Description: VC2 Data Buffer overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2_SHFT 17 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000 - -/* SH_XNMD_ERROR_SUMMARY_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_XNMD_ERROR_SUMMARY_LUT_READ_ERROR_SHFT 18 -#define SH_XNMD_ERROR_SUMMARY_LUT_READ_ERROR_MASK 0x0000000000040000 - -/* SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR0 */ -/* Description: Single Bit Error in Bits 63:0 */ -#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR0_SHFT 19 -#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR0_MASK 0x0000000000080000 - -/* SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR1 */ -/* Description: Single Bit Error in Bits 127:64 */ -#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR1_SHFT 20 -#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR1_MASK 0x0000000000100000 - -/* SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR2 */ -/* Description: Single Bit Error in Bits 191:128 */ -#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR2_SHFT 21 -#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR2_MASK 0x0000000000200000 - -/* SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR3 */ -/* Description: Single Bit Error in Bits 255:192 */ -#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR3_SHFT 22 -#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR3_MASK 0x0000000000400000 - -/* SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR0 */ -/* Description: Uncorrectable Error in Bits 63:0 */ -#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR0_SHFT 23 -#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR0_MASK 0x0000000000800000 - -/* SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR1 */ -/* Description: Uncorrectable Error in Bits 127:64 */ -#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR1_SHFT 24 -#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR1_MASK 0x0000000001000000 - -/* SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR2 */ -/* Description: Uncorrectable Error in Bits 191:128 */ -#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR2_SHFT 25 -#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR2_MASK 0x0000000002000000 - -/* SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR3 */ -/* Description: Uncorrectable Error in Bits 255:192 */ -#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR3_SHFT 26 -#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR3_MASK 0x0000000004000000 - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0_SHFT 27 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0_SHFT 28 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000 - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2_SHFT 29 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2_SHFT 30 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0 */ -/* Description: NI0 Debit 0 Overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_SHFT 31 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2 */ -/* Description: NI0 Debit 2 Overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_SHFT 32 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0 */ -/* Description: NI1 Debit 0 Overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_SHFT 33 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2 */ -/* Description: NI1 Debit 2 Overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_SHFT 34 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0 */ -/* Description: IILB Debit 0 Overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_SHFT 35 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2 */ -/* Description: IILB Debit 2 Overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_SHFT 36 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000 - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_SHFT 38 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000 - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_SHFT 40 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000 - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_SHFT 42 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000 - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_SHFT 44 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000 - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_SHFT 46 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_SHFT 48 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO */ -/* Description: Header Cancel Fifo Overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000 - -/* ==================================================================== */ -/* Register "SH_XNMD_ERRORS_ALIAS" */ -/* ==================================================================== */ - -#define SH_XNMD_ERRORS_ALIAS 0x0000000150040408 - -/* ==================================================================== */ -/* Register "SH_XNMD_ERROR_OVERFLOW" */ -/* ==================================================================== */ - -#define SH_XNMD_ERROR_OVERFLOW 0x0000000150040420 -#define SH_XNMD_ERROR_OVERFLOW_MASK 0x0003ffffffffffff -#define SH_XNMD_ERROR_OVERFLOW_INIT 0x0003ffffffffffff - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_SHFT 0 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_SHFT 1 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_MASK 0x0000000000000002 - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_SHFT 2 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_SHFT 3 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_MASK 0x0000000000000008 - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_SHFT 4 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_SHFT 5 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_MASK 0x0000000000000020 - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_SHFT 6 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_SHFT 7 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_MASK 0x0000000000000080 - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_SHFT 8 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_SHFT 9 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_MASK 0x0000000000000200 - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_SHFT 10 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_SHFT 11 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_MASK 0x0000000000000800 - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT_SHFT 12 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT_SHFT 13 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000 - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT_SHFT 14 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT_SHFT 15 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0 */ -/* Description: VC0 Data Buffer overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0_SHFT 16 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2 */ -/* Description: VC2 Data Buffer overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2_SHFT 17 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000 - -/* SH_XNMD_ERROR_OVERFLOW_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_XNMD_ERROR_OVERFLOW_LUT_READ_ERROR_SHFT 18 -#define SH_XNMD_ERROR_OVERFLOW_LUT_READ_ERROR_MASK 0x0000000000040000 - -/* SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR0 */ -/* Description: Single Bit Error in Bits 63:0 */ -#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR0_SHFT 19 -#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR0_MASK 0x0000000000080000 - -/* SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR1 */ -/* Description: Single Bit Error in Bits 127:64 */ -#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR1_SHFT 20 -#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR1_MASK 0x0000000000100000 - -/* SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR2 */ -/* Description: Single Bit Error in Bits 191:128 */ -#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR2_SHFT 21 -#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR2_MASK 0x0000000000200000 - -/* SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR3 */ -/* Description: Single Bit Error in Bits 255:192 */ -#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR3_SHFT 22 -#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR3_MASK 0x0000000000400000 - -/* SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR0 */ -/* Description: Uncorrectable Error in Bits 63:0 */ -#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR0_SHFT 23 -#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR0_MASK 0x0000000000800000 - -/* SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR1 */ -/* Description: Uncorrectable Error in Bits 127:64 */ -#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR1_SHFT 24 -#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR1_MASK 0x0000000001000000 - -/* SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR2 */ -/* Description: Uncorrectable Error in Bits 191:128 */ -#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR2_SHFT 25 -#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR2_MASK 0x0000000002000000 - -/* SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR3 */ -/* Description: Uncorrectable Error in Bits 255:192 */ -#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR3_SHFT 26 -#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR3_MASK 0x0000000004000000 - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0_SHFT 27 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0_SHFT 28 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000 - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2_SHFT 29 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2_SHFT 30 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0 */ -/* Description: NI0 Debit 0 Overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_SHFT 31 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2 */ -/* Description: NI0 Debit 2 Overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_SHFT 32 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0 */ -/* Description: NI1 Debit 0 Overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_SHFT 33 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2 */ -/* Description: NI1 Debit 2 Overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_SHFT 34 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0 */ -/* Description: IILB Debit 0 Overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_SHFT 35 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2 */ -/* Description: IILB Debit 2 Overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_SHFT 36 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000 - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_SHFT 38 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000 - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_SHFT 40 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000 - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_SHFT 42 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000 - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_SHFT 44 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000 - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_SHFT 46 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_SHFT 48 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO */ -/* Description: Header Cancel Fifo Overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000 - -/* ==================================================================== */ -/* Register "SH_XNMD_ERROR_OVERFLOW_ALIAS" */ -/* ==================================================================== */ - -#define SH_XNMD_ERROR_OVERFLOW_ALIAS 0x0000000150040428 - -/* ==================================================================== */ -/* Register "SH_XNMD_ERROR_MASK" */ -/* ==================================================================== */ - -#define SH_XNMD_ERROR_MASK 0x0000000150040440 -#define SH_XNMD_ERROR_MASK_MASK 0x0003ffffffffffff -#define SH_XNMD_ERROR_MASK_INIT 0x0003ffffffffffff - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0_SHFT 0 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0_SHFT 1 -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0_MASK 0x0000000000000002 - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2_SHFT 2 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2_SHFT 3 -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2_MASK 0x0000000000000008 - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0_SHFT 4 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0_SHFT 5 -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0_MASK 0x0000000000000020 - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2_SHFT 6 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2_SHFT 7 -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2_MASK 0x0000000000000080 - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0_SHFT 8 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0_SHFT 9 -#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0_MASK 0x0000000000000200 - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2_SHFT 10 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2_SHFT 11 -#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2_MASK 0x0000000000000800 - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_VC0_CREDIT_SHFT 12 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_VC0_CREDIT_SHFT 13 -#define SH_XNMD_ERROR_MASK_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000 - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_VC2_CREDIT_SHFT 14 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_VC2_CREDIT_SHFT 15 -#define SH_XNMD_ERROR_MASK_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC0 */ -/* Description: VC0 Data Buffer overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC0_SHFT 16 -#define SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC2 */ -/* Description: VC2 Data Buffer overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC2_SHFT 17 -#define SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000 - -/* SH_XNMD_ERROR_MASK_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_XNMD_ERROR_MASK_LUT_READ_ERROR_SHFT 18 -#define SH_XNMD_ERROR_MASK_LUT_READ_ERROR_MASK 0x0000000000040000 - -/* SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR0 */ -/* Description: Single Bit Error in Bits 63:0 */ -#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR0_SHFT 19 -#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR0_MASK 0x0000000000080000 - -/* SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR1 */ -/* Description: Single Bit Error in Bits 127:64 */ -#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR1_SHFT 20 -#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR1_MASK 0x0000000000100000 - -/* SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR2 */ -/* Description: Single Bit Error in Bits 191:128 */ -#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR2_SHFT 21 -#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR2_MASK 0x0000000000200000 - -/* SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR3 */ -/* Description: Single Bit Error in Bits 255:192 */ -#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR3_SHFT 22 -#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR3_MASK 0x0000000000400000 - -/* SH_XNMD_ERROR_MASK_UNCOR_ERROR0 */ -/* Description: Uncorrectable Error in Bits 63:0 */ -#define SH_XNMD_ERROR_MASK_UNCOR_ERROR0_SHFT 23 -#define SH_XNMD_ERROR_MASK_UNCOR_ERROR0_MASK 0x0000000000800000 - -/* SH_XNMD_ERROR_MASK_UNCOR_ERROR1 */ -/* Description: Uncorrectable Error in Bits 127:64 */ -#define SH_XNMD_ERROR_MASK_UNCOR_ERROR1_SHFT 24 -#define SH_XNMD_ERROR_MASK_UNCOR_ERROR1_MASK 0x0000000001000000 - -/* SH_XNMD_ERROR_MASK_UNCOR_ERROR2 */ -/* Description: Uncorrectable Error in Bits 191:128 */ -#define SH_XNMD_ERROR_MASK_UNCOR_ERROR2_SHFT 25 -#define SH_XNMD_ERROR_MASK_UNCOR_ERROR2_MASK 0x0000000002000000 - -/* SH_XNMD_ERROR_MASK_UNCOR_ERROR3 */ -/* Description: Uncorrectable Error in Bits 255:192 */ -#define SH_XNMD_ERROR_MASK_UNCOR_ERROR3_SHFT 26 -#define SH_XNMD_ERROR_MASK_UNCOR_ERROR3_MASK 0x0000000004000000 - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR0_SHFT 27 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR0_SHFT 28 -#define SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000 - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR2_SHFT 29 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR2_SHFT 30 -#define SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT0 */ -/* Description: NI0 Debit 0 Overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT0_SHFT 31 -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT2 */ -/* Description: NI0 Debit 2 Overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT2_SHFT 32 -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT0 */ -/* Description: NI1 Debit 0 Overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT0_SHFT 33 -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT2 */ -/* Description: NI1 Debit 2 Overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT2_SHFT 34 -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT0 */ -/* Description: IILB Debit 0 Overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT0_SHFT 35 -#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT2 */ -/* Description: IILB Debit 2 Overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT2_SHFT 36 -#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000 - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_SHFT 38 -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000 - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_SHFT 40 -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000 - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_SHFT 42 -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000 - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_SHFT 44 -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000 - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_SHFT 46 -#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_SHFT 48 -#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO */ -/* Description: Header Cancel Fifo Overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49 -#define SH_XNMD_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000 - -/* ==================================================================== */ -/* Register "SH_XNMD_FIRST_ERROR" */ -/* ==================================================================== */ - -#define SH_XNMD_FIRST_ERROR 0x0000000150040460 -#define SH_XNMD_FIRST_ERROR_MASK 0x0003ffffffffffff -#define SH_XNMD_FIRST_ERROR_INIT 0x0003ffffffffffff - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0_SHFT 0 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0_SHFT 1 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0_MASK 0x0000000000000002 - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2_SHFT 2 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2_SHFT 3 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2_MASK 0x0000000000000008 - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0_SHFT 4 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0_SHFT 5 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0_MASK 0x0000000000000020 - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2_SHFT 6 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2_SHFT 7 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2_MASK 0x0000000000000080 - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0_SHFT 8 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0_SHFT 9 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0_MASK 0x0000000000000200 - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2_SHFT 10 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2_SHFT 11 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2_MASK 0x0000000000000800 - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_VC0_CREDIT_SHFT 12 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_VC0_CREDIT_SHFT 13 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000 - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_VC2_CREDIT_SHFT 14 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_VC2_CREDIT_SHFT 15 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC0 */ -/* Description: VC0 Data Buffer overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC0_SHFT 16 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC2 */ -/* Description: VC2 Data Buffer overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC2_SHFT 17 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000 - -/* SH_XNMD_FIRST_ERROR_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_XNMD_FIRST_ERROR_LUT_READ_ERROR_SHFT 18 -#define SH_XNMD_FIRST_ERROR_LUT_READ_ERROR_MASK 0x0000000000040000 - -/* SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR0 */ -/* Description: Single Bit Error in Bits 63:0 */ -#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR0_SHFT 19 -#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR0_MASK 0x0000000000080000 - -/* SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR1 */ -/* Description: Single Bit Error in Bits 127:64 */ -#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR1_SHFT 20 -#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR1_MASK 0x0000000000100000 - -/* SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR2 */ -/* Description: Single Bit Error in Bits 191:128 */ -#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR2_SHFT 21 -#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR2_MASK 0x0000000000200000 - -/* SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR3 */ -/* Description: Single Bit Error in Bits 255:192 */ -#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR3_SHFT 22 -#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR3_MASK 0x0000000000400000 - -/* SH_XNMD_FIRST_ERROR_UNCOR_ERROR0 */ -/* Description: Uncorrectable Error in Bits 63:0 */ -#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR0_SHFT 23 -#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR0_MASK 0x0000000000800000 - -/* SH_XNMD_FIRST_ERROR_UNCOR_ERROR1 */ -/* Description: Uncorrectable Error in Bits 127:64 */ -#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR1_SHFT 24 -#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR1_MASK 0x0000000001000000 - -/* SH_XNMD_FIRST_ERROR_UNCOR_ERROR2 */ -/* Description: Uncorrectable Error in Bits 191:128 */ -#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR2_SHFT 25 -#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR2_MASK 0x0000000002000000 - -/* SH_XNMD_FIRST_ERROR_UNCOR_ERROR3 */ -/* Description: Uncorrectable Error in Bits 255:192 */ -#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR3_SHFT 26 -#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR3_MASK 0x0000000004000000 - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR0_SHFT 27 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR0_SHFT 28 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000 - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR2_SHFT 29 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR2_SHFT 30 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT0 */ -/* Description: NI0 Debit 0 Overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_SHFT 31 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT2 */ -/* Description: NI0 Debit 2 Overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_SHFT 32 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT0 */ -/* Description: NI1 Debit 0 Overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_SHFT 33 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT2 */ -/* Description: NI1 Debit 2 Overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_SHFT 34 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT0 */ -/* Description: IILB Debit 0 Overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_SHFT 35 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT2 */ -/* Description: IILB Debit 2 Overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_SHFT 36 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000 - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_SHFT 38 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000 - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_SHFT 40 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000 - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_SHFT 42 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000 - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_SHFT 44 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000 - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_SHFT 46 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_SHFT 48 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO */ -/* Description: Header Cancel Fifo Overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000 - -/* ==================================================================== */ -/* Register "SH_AUTO_REPLY_ENABLE0" */ -/* Automatic Maintenance Reply Enable 0 */ -/* ==================================================================== */ - -#define SH_AUTO_REPLY_ENABLE0 0x0000000110061000 -#define SH_AUTO_REPLY_ENABLE0_MASK 0xffffffffffffffff -#define SH_AUTO_REPLY_ENABLE0_INIT 0x0000000000000000 - -/* SH_AUTO_REPLY_ENABLE0_ENABLE0 */ -/* Description: Enable 0 */ -#define SH_AUTO_REPLY_ENABLE0_ENABLE0_SHFT 0 -#define SH_AUTO_REPLY_ENABLE0_ENABLE0_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_AUTO_REPLY_ENABLE1" */ -/* Automatic Maintenance Reply Enable 1 */ -/* ==================================================================== */ - -#define SH_AUTO_REPLY_ENABLE1 0x0000000110061080 -#define SH_AUTO_REPLY_ENABLE1_MASK 0xffffffffffffffff -#define SH_AUTO_REPLY_ENABLE1_INIT 0x0000000000000000 - -/* SH_AUTO_REPLY_ENABLE1_ENABLE1 */ -/* Description: Enable 1 */ -#define SH_AUTO_REPLY_ENABLE1_ENABLE1_SHFT 0 -#define SH_AUTO_REPLY_ENABLE1_ENABLE1_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_AUTO_REPLY_HEADER0" */ -/* Automatic Maintenance Reply Header 0 */ -/* ==================================================================== */ - -#define SH_AUTO_REPLY_HEADER0 0x0000000110061100 -#define SH_AUTO_REPLY_HEADER0_MASK 0xffffffffffffffff -#define SH_AUTO_REPLY_HEADER0_INIT 0x0000000000000000 - -/* SH_AUTO_REPLY_HEADER0_HEADER0 */ -/* Description: Header 0 */ -#define SH_AUTO_REPLY_HEADER0_HEADER0_SHFT 0 -#define SH_AUTO_REPLY_HEADER0_HEADER0_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_AUTO_REPLY_HEADER1" */ -/* Automatic Maintenance Reply Header 1 */ -/* ==================================================================== */ - -#define SH_AUTO_REPLY_HEADER1 0x0000000110061180 -#define SH_AUTO_REPLY_HEADER1_MASK 0xffffffffffffffff -#define SH_AUTO_REPLY_HEADER1_INIT 0x0000000000000000 - -/* SH_AUTO_REPLY_HEADER1_HEADER1 */ -/* Description: Header 1 */ -#define SH_AUTO_REPLY_HEADER1_HEADER1_SHFT 0 -#define SH_AUTO_REPLY_HEADER1_HEADER1_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_ENABLE_RP_AUTO_REPLY" */ -/* Enable Automatic Maintenance Reply From Reply Queue */ -/* ==================================================================== */ - -#define SH_ENABLE_RP_AUTO_REPLY 0x0000000110061200 -#define SH_ENABLE_RP_AUTO_REPLY_MASK 0x0000000000000001 -#define SH_ENABLE_RP_AUTO_REPLY_INIT 0x0000000000000000 - -/* SH_ENABLE_RP_AUTO_REPLY_ENABLE */ -/* Description: Enable Reply Auto Reply */ -#define SH_ENABLE_RP_AUTO_REPLY_ENABLE_SHFT 0 -#define SH_ENABLE_RP_AUTO_REPLY_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_ENABLE_RQ_AUTO_REPLY" */ -/* Enable Automatic Maintenance Reply From Request Queue */ -/* ==================================================================== */ - -#define SH_ENABLE_RQ_AUTO_REPLY 0x0000000110061280 -#define SH_ENABLE_RQ_AUTO_REPLY_MASK 0x0000000000000001 -#define SH_ENABLE_RQ_AUTO_REPLY_INIT 0x0000000000000000 - -/* SH_ENABLE_RQ_AUTO_REPLY_ENABLE */ -/* Description: Enable Request Auto Reply */ -#define SH_ENABLE_RQ_AUTO_REPLY_ENABLE_SHFT 0 -#define SH_ENABLE_RQ_AUTO_REPLY_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_REDIRECT_INVAL" */ -/* Redirect invalidate to LB instead of PI */ -/* ==================================================================== */ - -#define SH_REDIRECT_INVAL 0x0000000110061300 -#define SH_REDIRECT_INVAL_MASK 0x0000000000000001 -#define SH_REDIRECT_INVAL_INIT 0x0000000000000000 - -/* SH_REDIRECT_INVAL_REDIRECT */ -/* Description: Redirect invalidates to LB instead of PI */ -#define SH_REDIRECT_INVAL_REDIRECT_SHFT 0 -#define SH_REDIRECT_INVAL_REDIRECT_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_CNTRL" */ -/* Diagnostic Message Control Register */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_CNTRL 0x0000000110062000 -#define SH_DIAG_MSG_CNTRL_MASK 0xc000000000003fff -#define SH_DIAG_MSG_CNTRL_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_CNTRL_MSG_LENGTH */ -/* Description: Message data payload length, 0 - 63 */ -#define SH_DIAG_MSG_CNTRL_MSG_LENGTH_SHFT 0 -#define SH_DIAG_MSG_CNTRL_MSG_LENGTH_MASK 0x000000000000003f - -/* SH_DIAG_MSG_CNTRL_ERROR_INJECT_POINT */ -/* Description: Point message that the error bit would be activated */ -#define SH_DIAG_MSG_CNTRL_ERROR_INJECT_POINT_SHFT 6 -#define SH_DIAG_MSG_CNTRL_ERROR_INJECT_POINT_MASK 0x0000000000000fc0 - -/* SH_DIAG_MSG_CNTRL_ERROR_INJECT_ENABLE */ -/* Description: Enable ERROR_INJECT_POINT field */ -#define SH_DIAG_MSG_CNTRL_ERROR_INJECT_ENABLE_SHFT 12 -#define SH_DIAG_MSG_CNTRL_ERROR_INJECT_ENABLE_MASK 0x0000000000001000 - -/* SH_DIAG_MSG_CNTRL_PORT */ -/* Description: 0 = request port, 1 = reply port */ -#define SH_DIAG_MSG_CNTRL_PORT_SHFT 13 -#define SH_DIAG_MSG_CNTRL_PORT_MASK 0x0000000000002000 - -/* SH_DIAG_MSG_CNTRL_START */ -/* Description: Start */ -#define SH_DIAG_MSG_CNTRL_START_SHFT 62 -#define SH_DIAG_MSG_CNTRL_START_MASK 0x4000000000000000 - -/* SH_DIAG_MSG_CNTRL_BUSY */ -/* Description: Busy */ -#define SH_DIAG_MSG_CNTRL_BUSY_SHFT 63 -#define SH_DIAG_MSG_CNTRL_BUSY_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA0L" */ -/* Diagnostic Data, lower 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA0L 0x0000000110062080 -#define SH_DIAG_MSG_DATA0L_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA0L_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA0L_DATA_LOWER */ -/* Description: Lower 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA0L_DATA_LOWER_SHFT 0 -#define SH_DIAG_MSG_DATA0L_DATA_LOWER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA0U" */ -/* Diagnostice Data, upper 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA0U 0x0000000110062100 -#define SH_DIAG_MSG_DATA0U_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA0U_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA0U_DATA_UPPER */ -/* Description: Upper 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA0U_DATA_UPPER_SHFT 0 -#define SH_DIAG_MSG_DATA0U_DATA_UPPER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA1L" */ -/* Diagnostic Data, lower 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA1L 0x0000000110062180 -#define SH_DIAG_MSG_DATA1L_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA1L_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA1L_DATA_LOWER */ -/* Description: Lower 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA1L_DATA_LOWER_SHFT 0 -#define SH_DIAG_MSG_DATA1L_DATA_LOWER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA1U" */ -/* Diagnostice Data, upper 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA1U 0x0000000110062200 -#define SH_DIAG_MSG_DATA1U_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA1U_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA1U_DATA_UPPER */ -/* Description: Upper 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA1U_DATA_UPPER_SHFT 0 -#define SH_DIAG_MSG_DATA1U_DATA_UPPER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA2L" */ -/* Diagnostic Data, lower 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA2L 0x0000000110062280 -#define SH_DIAG_MSG_DATA2L_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA2L_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA2L_DATA_LOWER */ -/* Description: Lower 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA2L_DATA_LOWER_SHFT 0 -#define SH_DIAG_MSG_DATA2L_DATA_LOWER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA2U" */ -/* Diagnostice Data, upper 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA2U 0x0000000110062300 -#define SH_DIAG_MSG_DATA2U_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA2U_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA2U_DATA_UPPER */ -/* Description: Upper 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA2U_DATA_UPPER_SHFT 0 -#define SH_DIAG_MSG_DATA2U_DATA_UPPER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA3L" */ -/* Diagnostic Data, lower 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA3L 0x0000000110062380 -#define SH_DIAG_MSG_DATA3L_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA3L_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA3L_DATA_LOWER */ -/* Description: Lower 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA3L_DATA_LOWER_SHFT 0 -#define SH_DIAG_MSG_DATA3L_DATA_LOWER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA3U" */ -/* Diagnostice Data, upper 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA3U 0x0000000110062400 -#define SH_DIAG_MSG_DATA3U_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA3U_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA3U_DATA_UPPER */ -/* Description: Upper 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA3U_DATA_UPPER_SHFT 0 -#define SH_DIAG_MSG_DATA3U_DATA_UPPER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA4L" */ -/* Diagnostic Data, lower 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA4L 0x0000000110062480 -#define SH_DIAG_MSG_DATA4L_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA4L_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA4L_DATA_LOWER */ -/* Description: Lower 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA4L_DATA_LOWER_SHFT 0 -#define SH_DIAG_MSG_DATA4L_DATA_LOWER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA4U" */ -/* Diagnostice Data, upper 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA4U 0x0000000110062500 -#define SH_DIAG_MSG_DATA4U_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA4U_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA4U_DATA_UPPER */ -/* Description: Upper 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA4U_DATA_UPPER_SHFT 0 -#define SH_DIAG_MSG_DATA4U_DATA_UPPER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA5L" */ -/* Diagnostic Data, lower 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA5L 0x0000000110062580 -#define SH_DIAG_MSG_DATA5L_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA5L_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA5L_DATA_LOWER */ -/* Description: Lower 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA5L_DATA_LOWER_SHFT 0 -#define SH_DIAG_MSG_DATA5L_DATA_LOWER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA5U" */ -/* Diagnostice Data, upper 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA5U 0x0000000110062600 -#define SH_DIAG_MSG_DATA5U_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA5U_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA5U_DATA_UPPER */ -/* Description: Upper 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA5U_DATA_UPPER_SHFT 0 -#define SH_DIAG_MSG_DATA5U_DATA_UPPER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA6L" */ -/* Diagnostic Data, lower 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA6L 0x0000000110062680 -#define SH_DIAG_MSG_DATA6L_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA6L_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA6L_DATA_LOWER */ -/* Description: Lower 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA6L_DATA_LOWER_SHFT 0 -#define SH_DIAG_MSG_DATA6L_DATA_LOWER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA6U" */ -/* Diagnostice Data, upper 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA6U 0x0000000110062700 -#define SH_DIAG_MSG_DATA6U_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA6U_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA6U_DATA_UPPER */ -/* Description: Upper 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA6U_DATA_UPPER_SHFT 0 -#define SH_DIAG_MSG_DATA6U_DATA_UPPER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA7L" */ -/* Diagnostic Data, lower 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA7L 0x0000000110062780 -#define SH_DIAG_MSG_DATA7L_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA7L_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA7L_DATA_LOWER */ -/* Description: Lower 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA7L_DATA_LOWER_SHFT 0 -#define SH_DIAG_MSG_DATA7L_DATA_LOWER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA7U" */ -/* Diagnostice Data, upper 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA7U 0x0000000110062800 -#define SH_DIAG_MSG_DATA7U_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA7U_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA7U_DATA_UPPER */ -/* Description: Upper 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA7U_DATA_UPPER_SHFT 0 -#define SH_DIAG_MSG_DATA7U_DATA_UPPER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA8L" */ -/* Diagnostic Data, lower 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA8L 0x0000000110062880 -#define SH_DIAG_MSG_DATA8L_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA8L_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA8L_DATA_LOWER */ -/* Description: Lower 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA8L_DATA_LOWER_SHFT 0 -#define SH_DIAG_MSG_DATA8L_DATA_LOWER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA8U" */ -/* Diagnostice Data, upper 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA8U 0x0000000110062900 -#define SH_DIAG_MSG_DATA8U_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA8U_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA8U_DATA_UPPER */ -/* Description: Upper 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA8U_DATA_UPPER_SHFT 0 -#define SH_DIAG_MSG_DATA8U_DATA_UPPER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_HDR0" */ -/* Diagnostice Data, lower 64 bits of header */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_HDR0 0x0000000110062980 -#define SH_DIAG_MSG_HDR0_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_HDR0_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_HDR0_HEADER0 */ -/* Description: Lower 64 bits of Diagnositic Message Header */ -#define SH_DIAG_MSG_HDR0_HEADER0_SHFT 0 -#define SH_DIAG_MSG_HDR0_HEADER0_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_HDR1" */ -/* Diagnostice Data, upper 64 bits of header */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_HDR1 0x0000000110062a00 -#define SH_DIAG_MSG_HDR1_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_HDR1_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_HDR1_HEADER1 */ -/* Description: Upper 64 bits of Diagnositic Message Header */ -#define SH_DIAG_MSG_HDR1_HEADER1_SHFT 0 -#define SH_DIAG_MSG_HDR1_HEADER1_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DEBUG_SELECT" */ -/* SHub Debug Port Select */ -/* ==================================================================== */ - -#define SH_DEBUG_SELECT 0x0000000110063000 -#define SH_DEBUG_SELECT_MASK 0x8fffffffffffffff -#define SH_DEBUG_SELECT_INIT 0x0000e38e38e38e38 - -/* SH_DEBUG_SELECT_NIBBLE0_NIBBLE_SEL */ -/* Description: Nibble0_nibble_select */ -#define SH_DEBUG_SELECT_NIBBLE0_NIBBLE_SEL_SHFT 0 -#define SH_DEBUG_SELECT_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000007 - -/* SH_DEBUG_SELECT_NIBBLE0_CHIPLET_SEL */ -/* Description: Nibble0_chiplet_select */ -#define SH_DEBUG_SELECT_NIBBLE0_CHIPLET_SEL_SHFT 3 -#define SH_DEBUG_SELECT_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000038 - -/* SH_DEBUG_SELECT_NIBBLE1_NIBBLE_SEL */ -/* Description: Nibble1_nibble_select */ -#define SH_DEBUG_SELECT_NIBBLE1_NIBBLE_SEL_SHFT 6 -#define SH_DEBUG_SELECT_NIBBLE1_NIBBLE_SEL_MASK 0x00000000000001c0 - -/* SH_DEBUG_SELECT_NIBBLE1_CHIPLET_SEL */ -/* Description: Nibble1_chiplet_select */ -#define SH_DEBUG_SELECT_NIBBLE1_CHIPLET_SEL_SHFT 9 -#define SH_DEBUG_SELECT_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000e00 - -/* SH_DEBUG_SELECT_NIBBLE2_NIBBLE_SEL */ -/* Description: Nibble2_nibble_select */ -#define SH_DEBUG_SELECT_NIBBLE2_NIBBLE_SEL_SHFT 12 -#define SH_DEBUG_SELECT_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_DEBUG_SELECT_NIBBLE2_CHIPLET_SEL */ -/* Description: Nibble2_chiplet_select */ -#define SH_DEBUG_SELECT_NIBBLE2_CHIPLET_SEL_SHFT 15 -#define SH_DEBUG_SELECT_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000038000 - -/* SH_DEBUG_SELECT_NIBBLE3_NIBBLE_SEL */ -/* Description: Nibble3_nibble_select */ -#define SH_DEBUG_SELECT_NIBBLE3_NIBBLE_SEL_SHFT 18 -#define SH_DEBUG_SELECT_NIBBLE3_NIBBLE_SEL_MASK 0x00000000001c0000 - -/* SH_DEBUG_SELECT_NIBBLE3_CHIPLET_SEL */ -/* Description: Nibble3_chiplet_select */ -#define SH_DEBUG_SELECT_NIBBLE3_CHIPLET_SEL_SHFT 21 -#define SH_DEBUG_SELECT_NIBBLE3_CHIPLET_SEL_MASK 0x0000000000e00000 - -/* SH_DEBUG_SELECT_NIBBLE4_NIBBLE_SEL */ -/* Description: Nibble4_nibble_select */ -#define SH_DEBUG_SELECT_NIBBLE4_NIBBLE_SEL_SHFT 24 -#define SH_DEBUG_SELECT_NIBBLE4_NIBBLE_SEL_MASK 0x0000000007000000 - -/* SH_DEBUG_SELECT_NIBBLE4_CHIPLET_SEL */ -/* Description: Nibble4_chiplet_select */ -#define SH_DEBUG_SELECT_NIBBLE4_CHIPLET_SEL_SHFT 27 -#define SH_DEBUG_SELECT_NIBBLE4_CHIPLET_SEL_MASK 0x0000000038000000 - -/* SH_DEBUG_SELECT_NIBBLE5_NIBBLE_SEL */ -/* Description: Nibble5_nibble_select */ -#define SH_DEBUG_SELECT_NIBBLE5_NIBBLE_SEL_SHFT 30 -#define SH_DEBUG_SELECT_NIBBLE5_NIBBLE_SEL_MASK 0x00000001c0000000 - -/* SH_DEBUG_SELECT_NIBBLE5_CHIPLET_SEL */ -/* Description: Nibble5_chiplet_select */ -#define SH_DEBUG_SELECT_NIBBLE5_CHIPLET_SEL_SHFT 33 -#define SH_DEBUG_SELECT_NIBBLE5_CHIPLET_SEL_MASK 0x0000000e00000000 - -/* SH_DEBUG_SELECT_NIBBLE6_NIBBLE_SEL */ -/* Description: Nibble6_nibble_select */ -#define SH_DEBUG_SELECT_NIBBLE6_NIBBLE_SEL_SHFT 36 -#define SH_DEBUG_SELECT_NIBBLE6_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_DEBUG_SELECT_NIBBLE6_CHIPLET_SEL */ -/* Description: Nibble6_chiplet_select */ -#define SH_DEBUG_SELECT_NIBBLE6_CHIPLET_SEL_SHFT 39 -#define SH_DEBUG_SELECT_NIBBLE6_CHIPLET_SEL_MASK 0x0000038000000000 - -/* SH_DEBUG_SELECT_NIBBLE7_NIBBLE_SEL */ -/* Description: Nibble7_nibble_select */ -#define SH_DEBUG_SELECT_NIBBLE7_NIBBLE_SEL_SHFT 42 -#define SH_DEBUG_SELECT_NIBBLE7_NIBBLE_SEL_MASK 0x00001c0000000000 - -/* SH_DEBUG_SELECT_NIBBLE7_CHIPLET_SEL */ -/* Description: Nibble7_chiplet_select */ -#define SH_DEBUG_SELECT_NIBBLE7_CHIPLET_SEL_SHFT 45 -#define SH_DEBUG_SELECT_NIBBLE7_CHIPLET_SEL_MASK 0x0000e00000000000 - -/* SH_DEBUG_SELECT_DEBUG_II_SEL */ -/* Description: Select bits to II port */ -#define SH_DEBUG_SELECT_DEBUG_II_SEL_SHFT 48 -#define SH_DEBUG_SELECT_DEBUG_II_SEL_MASK 0x0007000000000000 - -/* SH_DEBUG_SELECT_SEL_II */ -/* Description: Select II to debug port */ -#define SH_DEBUG_SELECT_SEL_II_SHFT 51 -#define SH_DEBUG_SELECT_SEL_II_MASK 0x0ff8000000000000 - -/* SH_DEBUG_SELECT_TRIGGER_ENABLE */ -/* Description: Enable trigger on bit 32 of Analyzer data */ -#define SH_DEBUG_SELECT_TRIGGER_ENABLE_SHFT 63 -#define SH_DEBUG_SELECT_TRIGGER_ENABLE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_TRIGGER_COMPARE_MASK" */ -/* SHub Trigger Compare Mask */ -/* ==================================================================== */ - -#define SH_TRIGGER_COMPARE_MASK 0x0000000110063080 -#define SH_TRIGGER_COMPARE_MASK_MASK 0x00000000ffffffff -#define SH_TRIGGER_COMPARE_MASK_INIT 0x0000000000000000 - -/* SH_TRIGGER_COMPARE_MASK_MASK */ -/* Description: SHub Trigger Compare Mask */ -#define SH_TRIGGER_COMPARE_MASK_MASK_SHFT 0 -#define SH_TRIGGER_COMPARE_MASK_MASK_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_TRIGGER_COMPARE_PATTERN" */ -/* SHub Trigger Compare Pattern */ -/* ==================================================================== */ - -#define SH_TRIGGER_COMPARE_PATTERN 0x0000000110063100 -#define SH_TRIGGER_COMPARE_PATTERN_MASK 0x00000000ffffffff -#define SH_TRIGGER_COMPARE_PATTERN_INIT 0x0000000000000000 - -/* SH_TRIGGER_COMPARE_PATTERN_DATA */ -/* Description: SHub Trigger Compare Pattern */ -#define SH_TRIGGER_COMPARE_PATTERN_DATA_SHFT 0 -#define SH_TRIGGER_COMPARE_PATTERN_DATA_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_TRIGGER_SEL" */ -/* Trigger select for SHUB debug port */ -/* ==================================================================== */ - -#define SH_TRIGGER_SEL 0x0000000110063180 -#define SH_TRIGGER_SEL_MASK 0x7777777777777777 -#define SH_TRIGGER_SEL_INIT 0x0000000000000000 - -/* SH_TRIGGER_SEL_NIBBLE0_INPUT_SEL */ -/* Description: Nibble 0 input select */ -#define SH_TRIGGER_SEL_NIBBLE0_INPUT_SEL_SHFT 0 -#define SH_TRIGGER_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007 - -/* SH_TRIGGER_SEL_NIBBLE0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_TRIGGER_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4 -#define SH_TRIGGER_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_TRIGGER_SEL_NIBBLE1_INPUT_SEL */ -/* Description: Nibble 1 input select */ -#define SH_TRIGGER_SEL_NIBBLE1_INPUT_SEL_SHFT 8 -#define SH_TRIGGER_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700 - -/* SH_TRIGGER_SEL_NIBBLE1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_TRIGGER_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12 -#define SH_TRIGGER_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_TRIGGER_SEL_NIBBLE2_INPUT_SEL */ -/* Description: Nibble 2 input select */ -#define SH_TRIGGER_SEL_NIBBLE2_INPUT_SEL_SHFT 16 -#define SH_TRIGGER_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000 - -/* SH_TRIGGER_SEL_NIBBLE2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_TRIGGER_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20 -#define SH_TRIGGER_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_TRIGGER_SEL_NIBBLE3_INPUT_SEL */ -/* Description: Nibble 3 input select */ -#define SH_TRIGGER_SEL_NIBBLE3_INPUT_SEL_SHFT 24 -#define SH_TRIGGER_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000 - -/* SH_TRIGGER_SEL_NIBBLE3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_TRIGGER_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28 -#define SH_TRIGGER_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_TRIGGER_SEL_NIBBLE4_INPUT_SEL */ -/* Description: Nibble 4 input select */ -#define SH_TRIGGER_SEL_NIBBLE4_INPUT_SEL_SHFT 32 -#define SH_TRIGGER_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000 - -/* SH_TRIGGER_SEL_NIBBLE4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_TRIGGER_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36 -#define SH_TRIGGER_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_TRIGGER_SEL_NIBBLE5_INPUT_SEL */ -/* Description: Nibble 5 input select */ -#define SH_TRIGGER_SEL_NIBBLE5_INPUT_SEL_SHFT 40 -#define SH_TRIGGER_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000 - -/* SH_TRIGGER_SEL_NIBBLE5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_TRIGGER_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44 -#define SH_TRIGGER_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_TRIGGER_SEL_NIBBLE6_INPUT_SEL */ -/* Description: Nibble 6 input select */ -#define SH_TRIGGER_SEL_NIBBLE6_INPUT_SEL_SHFT 48 -#define SH_TRIGGER_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000 - -/* SH_TRIGGER_SEL_NIBBLE6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_TRIGGER_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52 -#define SH_TRIGGER_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_TRIGGER_SEL_NIBBLE7_INPUT_SEL */ -/* Description: Nibble 7 input select */ -#define SH_TRIGGER_SEL_NIBBLE7_INPUT_SEL_SHFT 56 -#define SH_TRIGGER_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000 - -/* SH_TRIGGER_SEL_NIBBLE7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_TRIGGER_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60 -#define SH_TRIGGER_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* ==================================================================== */ -/* Register "SH_STOP_CLK_CONTROL" */ -/* Stop Clock Control */ -/* ==================================================================== */ - -#define SH_STOP_CLK_CONTROL 0x0000000110064000 -#define SH_STOP_CLK_CONTROL_MASK 0x00000000000000ff -#define SH_STOP_CLK_CONTROL_INIT 0x00000000000000e0 - -/* SH_STOP_CLK_CONTROL_STIMULUS */ -/* Description: Counter stimulus */ -#define SH_STOP_CLK_CONTROL_STIMULUS_SHFT 0 -#define SH_STOP_CLK_CONTROL_STIMULUS_MASK 0x000000000000001f - -/* SH_STOP_CLK_CONTROL_EVENT */ -/* Description: Counter event select (0-greater than, 1-equal) */ -#define SH_STOP_CLK_CONTROL_EVENT_SHFT 5 -#define SH_STOP_CLK_CONTROL_EVENT_MASK 0x0000000000000020 - -/* SH_STOP_CLK_CONTROL_POLARITY */ -/* Description: Counter polarity select (0-negative edge, 1-positiv */ -/* e edge) */ -#define SH_STOP_CLK_CONTROL_POLARITY_SHFT 6 -#define SH_STOP_CLK_CONTROL_POLARITY_MASK 0x0000000000000040 - -/* SH_STOP_CLK_CONTROL_MODE */ -/* Description: Counter mode select (0-internal, 1-external) */ -#define SH_STOP_CLK_CONTROL_MODE_SHFT 7 -#define SH_STOP_CLK_CONTROL_MODE_MASK 0x0000000000000080 - -/* ==================================================================== */ -/* Register "SH_STOP_CLK_DELAY_PHASE" */ -/* Stop Clock Delay Phase */ -/* ==================================================================== */ - -#define SH_STOP_CLK_DELAY_PHASE 0x0000000110064080 -#define SH_STOP_CLK_DELAY_PHASE_MASK 0x00000000000000ff -#define SH_STOP_CLK_DELAY_PHASE_INIT 0x0000000000000000 - -/* SH_STOP_CLK_DELAY_PHASE_DELAY */ -/* Description: Delay phase */ -#define SH_STOP_CLK_DELAY_PHASE_DELAY_SHFT 0 -#define SH_STOP_CLK_DELAY_PHASE_DELAY_MASK 0x00000000000000ff - -/* ==================================================================== */ -/* Register "SH_TSF_ARM_MASK" */ -/* Trigger sequencing facility arm mask */ -/* ==================================================================== */ - -#define SH_TSF_ARM_MASK 0x0000000110065000 -#define SH_TSF_ARM_MASK_MASK 0xffffffffffffffff -#define SH_TSF_ARM_MASK_INIT 0x0000000000000000 - -/* SH_TSF_ARM_MASK_MASK */ -/* Description: Trigger sequencing facility arm mask */ -#define SH_TSF_ARM_MASK_MASK_SHFT 0 -#define SH_TSF_ARM_MASK_MASK_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_TSF_COUNTER_PRESETS" */ -/* Trigger sequencing facility counter presets */ -/* ==================================================================== */ - -#define SH_TSF_COUNTER_PRESETS 0x0000000110065080 -#define SH_TSF_COUNTER_PRESETS_MASK 0xffffffffffffffff -#define SH_TSF_COUNTER_PRESETS_INIT 0x0000000000000000 - -/* SH_TSF_COUNTER_PRESETS_COUNT_32 */ -/* Description: Trigger sequencing facility counter 32 */ -#define SH_TSF_COUNTER_PRESETS_COUNT_32_SHFT 0 -#define SH_TSF_COUNTER_PRESETS_COUNT_32_MASK 0x00000000ffffffff - -/* SH_TSF_COUNTER_PRESETS_COUNT_16 */ -/* Description: Trigger sequencing facility counter 16 */ -#define SH_TSF_COUNTER_PRESETS_COUNT_16_SHFT 32 -#define SH_TSF_COUNTER_PRESETS_COUNT_16_MASK 0x0000ffff00000000 - -/* SH_TSF_COUNTER_PRESETS_COUNT_8B */ -/* Description: Trigger sequencing facility counter 8b */ -#define SH_TSF_COUNTER_PRESETS_COUNT_8B_SHFT 48 -#define SH_TSF_COUNTER_PRESETS_COUNT_8B_MASK 0x00ff000000000000 - -/* SH_TSF_COUNTER_PRESETS_COUNT_8A */ -/* Description: Trigger sequencing facility counter 8a */ -#define SH_TSF_COUNTER_PRESETS_COUNT_8A_SHFT 56 -#define SH_TSF_COUNTER_PRESETS_COUNT_8A_MASK 0xff00000000000000 - -/* ==================================================================== */ -/* Register "SH_TSF_DECREMENT_CTL" */ -/* Trigger sequencing facility counter decrement control */ -/* ==================================================================== */ - -#define SH_TSF_DECREMENT_CTL 0x0000000110065100 -#define SH_TSF_DECREMENT_CTL_MASK 0x000000000000ffff -#define SH_TSF_DECREMENT_CTL_INIT 0x0000000000000000 - -/* SH_TSF_DECREMENT_CTL_CTL */ -/* Description: Trigger sequencing facility counter decrement contr */ -#define SH_TSF_DECREMENT_CTL_CTL_SHFT 0 -#define SH_TSF_DECREMENT_CTL_CTL_MASK 0x000000000000ffff - -/* ==================================================================== */ -/* Register "SH_TSF_DIAG_MSG_CTL" */ -/* Trigger sequencing facility diagnostic message control */ -/* ==================================================================== */ - -#define SH_TSF_DIAG_MSG_CTL 0x0000000110065180 -#define SH_TSF_DIAG_MSG_CTL_MASK 0x00000000000000ff -#define SH_TSF_DIAG_MSG_CTL_INIT 0x0000000000000000 - -/* SH_TSF_DIAG_MSG_CTL_ENABLE */ -/* Description: Trigger sequencing facility diagnostic message cont */ -#define SH_TSF_DIAG_MSG_CTL_ENABLE_SHFT 0 -#define SH_TSF_DIAG_MSG_CTL_ENABLE_MASK 0x00000000000000ff - -/* ==================================================================== */ -/* Register "SH_TSF_DISARM_MASK" */ -/* Trigger sequencing facility disarm mask */ -/* ==================================================================== */ - -#define SH_TSF_DISARM_MASK 0x0000000110065200 -#define SH_TSF_DISARM_MASK_MASK 0xffffffffffffffff -#define SH_TSF_DISARM_MASK_INIT 0x0000000000000000 - -/* SH_TSF_DISARM_MASK_MASK */ -/* Description: Trigger sequencing facility disarm mask */ -#define SH_TSF_DISARM_MASK_MASK_SHFT 0 -#define SH_TSF_DISARM_MASK_MASK_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_TSF_ENABLE_CTL" */ -/* Trigger sequencing facility counter enable control */ -/* ==================================================================== */ - -#define SH_TSF_ENABLE_CTL 0x0000000110065280 -#define SH_TSF_ENABLE_CTL_MASK 0x000000000000ffff -#define SH_TSF_ENABLE_CTL_INIT 0x0000000000000000 - -/* SH_TSF_ENABLE_CTL_CTL */ -/* Description: Trigger sequencing facility counter enable control */ -#define SH_TSF_ENABLE_CTL_CTL_SHFT 0 -#define SH_TSF_ENABLE_CTL_CTL_MASK 0x000000000000ffff - -/* ==================================================================== */ -/* Register "SH_TSF_SOFTWARE_ARM" */ -/* Trigger sequencing facility software arm */ -/* ==================================================================== */ - -#define SH_TSF_SOFTWARE_ARM 0x0000000110065300 -#define SH_TSF_SOFTWARE_ARM_MASK 0x00000000000000ff -#define SH_TSF_SOFTWARE_ARM_INIT 0x0000000000000000 - -/* SH_TSF_SOFTWARE_ARM_BIT0 */ -/* Description: Trigger sequencing facility software arm bit 0 */ -#define SH_TSF_SOFTWARE_ARM_BIT0_SHFT 0 -#define SH_TSF_SOFTWARE_ARM_BIT0_MASK 0x0000000000000001 - -/* SH_TSF_SOFTWARE_ARM_BIT1 */ -/* Description: Trigger sequencing facility software arm bit 1 */ -#define SH_TSF_SOFTWARE_ARM_BIT1_SHFT 1 -#define SH_TSF_SOFTWARE_ARM_BIT1_MASK 0x0000000000000002 - -/* SH_TSF_SOFTWARE_ARM_BIT2 */ -/* Description: Trigger sequencing facility software arm bit 2 */ -#define SH_TSF_SOFTWARE_ARM_BIT2_SHFT 2 -#define SH_TSF_SOFTWARE_ARM_BIT2_MASK 0x0000000000000004 - -/* SH_TSF_SOFTWARE_ARM_BIT3 */ -/* Description: Trigger sequencing facility software arm bit 3 */ -#define SH_TSF_SOFTWARE_ARM_BIT3_SHFT 3 -#define SH_TSF_SOFTWARE_ARM_BIT3_MASK 0x0000000000000008 - -/* SH_TSF_SOFTWARE_ARM_BIT4 */ -/* Description: Trigger sequencing facility software arm bit 4 */ -#define SH_TSF_SOFTWARE_ARM_BIT4_SHFT 4 -#define SH_TSF_SOFTWARE_ARM_BIT4_MASK 0x0000000000000010 - -/* SH_TSF_SOFTWARE_ARM_BIT5 */ -/* Description: Trigger sequencing facility software arm bit 5 */ -#define SH_TSF_SOFTWARE_ARM_BIT5_SHFT 5 -#define SH_TSF_SOFTWARE_ARM_BIT5_MASK 0x0000000000000020 - -/* SH_TSF_SOFTWARE_ARM_BIT6 */ -/* Description: Trigger sequencing facility software arm bit 6 */ -#define SH_TSF_SOFTWARE_ARM_BIT6_SHFT 6 -#define SH_TSF_SOFTWARE_ARM_BIT6_MASK 0x0000000000000040 - -/* SH_TSF_SOFTWARE_ARM_BIT7 */ -/* Description: Trigger sequencing facility software arm bit 7 */ -#define SH_TSF_SOFTWARE_ARM_BIT7_SHFT 7 -#define SH_TSF_SOFTWARE_ARM_BIT7_MASK 0x0000000000000080 - -/* ==================================================================== */ -/* Register "SH_TSF_SOFTWARE_DISARM" */ -/* Trigger sequencing facility software disarm */ -/* ==================================================================== */ - -#define SH_TSF_SOFTWARE_DISARM 0x0000000110065380 -#define SH_TSF_SOFTWARE_DISARM_MASK 0x00000000000000ff -#define SH_TSF_SOFTWARE_DISARM_INIT 0x0000000000000000 - -/* SH_TSF_SOFTWARE_DISARM_BIT0 */ -/* Description: Trigger sequencing facility software disarm bit 0 */ -#define SH_TSF_SOFTWARE_DISARM_BIT0_SHFT 0 -#define SH_TSF_SOFTWARE_DISARM_BIT0_MASK 0x0000000000000001 - -/* SH_TSF_SOFTWARE_DISARM_BIT1 */ -/* Description: Trigger sequencing facility software disarm bit 1 */ -#define SH_TSF_SOFTWARE_DISARM_BIT1_SHFT 1 -#define SH_TSF_SOFTWARE_DISARM_BIT1_MASK 0x0000000000000002 - -/* SH_TSF_SOFTWARE_DISARM_BIT2 */ -/* Description: Trigger sequencing facility software disarm bit 2 */ -#define SH_TSF_SOFTWARE_DISARM_BIT2_SHFT 2 -#define SH_TSF_SOFTWARE_DISARM_BIT2_MASK 0x0000000000000004 - -/* SH_TSF_SOFTWARE_DISARM_BIT3 */ -/* Description: Trigger sequencing facility software disarm bit 3 */ -#define SH_TSF_SOFTWARE_DISARM_BIT3_SHFT 3 -#define SH_TSF_SOFTWARE_DISARM_BIT3_MASK 0x0000000000000008 - -/* SH_TSF_SOFTWARE_DISARM_BIT4 */ -/* Description: Trigger sequencing facility software disarm bit 4 */ -#define SH_TSF_SOFTWARE_DISARM_BIT4_SHFT 4 -#define SH_TSF_SOFTWARE_DISARM_BIT4_MASK 0x0000000000000010 - -/* SH_TSF_SOFTWARE_DISARM_BIT5 */ -/* Description: Trigger sequencing facility software disarm bit 5 */ -#define SH_TSF_SOFTWARE_DISARM_BIT5_SHFT 5 -#define SH_TSF_SOFTWARE_DISARM_BIT5_MASK 0x0000000000000020 - -/* SH_TSF_SOFTWARE_DISARM_BIT6 */ -/* Description: Trigger sequencing facility software disarm bit 6 */ -#define SH_TSF_SOFTWARE_DISARM_BIT6_SHFT 6 -#define SH_TSF_SOFTWARE_DISARM_BIT6_MASK 0x0000000000000040 - -/* SH_TSF_SOFTWARE_DISARM_BIT7 */ -/* Description: Trigger sequencing facility software disarm bit 7 */ -#define SH_TSF_SOFTWARE_DISARM_BIT7_SHFT 7 -#define SH_TSF_SOFTWARE_DISARM_BIT7_MASK 0x0000000000000080 - -/* ==================================================================== */ -/* Register "SH_TSF_SOFTWARE_TRIGGERED" */ -/* Trigger sequencing facility software triggered */ -/* ==================================================================== */ - -#define SH_TSF_SOFTWARE_TRIGGERED 0x0000000110065400 -#define SH_TSF_SOFTWARE_TRIGGERED_MASK 0x00000000000000ff -#define SH_TSF_SOFTWARE_TRIGGERED_INIT 0x0000000000000000 - -/* SH_TSF_SOFTWARE_TRIGGERED_BIT0 */ -/* Description: Trigger sequencing facility software triggered bit */ -#define SH_TSF_SOFTWARE_TRIGGERED_BIT0_SHFT 0 -#define SH_TSF_SOFTWARE_TRIGGERED_BIT0_MASK 0x0000000000000001 - -/* SH_TSF_SOFTWARE_TRIGGERED_BIT1 */ -/* Description: Trigger sequencing facility software triggered bit */ -#define SH_TSF_SOFTWARE_TRIGGERED_BIT1_SHFT 1 -#define SH_TSF_SOFTWARE_TRIGGERED_BIT1_MASK 0x0000000000000002 - -/* SH_TSF_SOFTWARE_TRIGGERED_BIT2 */ -/* Description: Trigger sequencing facility software triggered bit */ -#define SH_TSF_SOFTWARE_TRIGGERED_BIT2_SHFT 2 -#define SH_TSF_SOFTWARE_TRIGGERED_BIT2_MASK 0x0000000000000004 - -/* SH_TSF_SOFTWARE_TRIGGERED_BIT3 */ -/* Description: Trigger sequencing facility software triggered bit */ -#define SH_TSF_SOFTWARE_TRIGGERED_BIT3_SHFT 3 -#define SH_TSF_SOFTWARE_TRIGGERED_BIT3_MASK 0x0000000000000008 - -/* SH_TSF_SOFTWARE_TRIGGERED_BIT4 */ -/* Description: Trigger sequencing facility software triggered bit */ -#define SH_TSF_SOFTWARE_TRIGGERED_BIT4_SHFT 4 -#define SH_TSF_SOFTWARE_TRIGGERED_BIT4_MASK 0x0000000000000010 - -/* SH_TSF_SOFTWARE_TRIGGERED_BIT5 */ -/* Description: Trigger sequencing facility software triggered bit */ -#define SH_TSF_SOFTWARE_TRIGGERED_BIT5_SHFT 5 -#define SH_TSF_SOFTWARE_TRIGGERED_BIT5_MASK 0x0000000000000020 - -/* SH_TSF_SOFTWARE_TRIGGERED_BIT6 */ -/* Description: Trigger sequencing facility software triggered bit */ -#define SH_TSF_SOFTWARE_TRIGGERED_BIT6_SHFT 6 -#define SH_TSF_SOFTWARE_TRIGGERED_BIT6_MASK 0x0000000000000040 - -/* SH_TSF_SOFTWARE_TRIGGERED_BIT7 */ -/* Description: Trigger sequencing facility software triggered bit */ -#define SH_TSF_SOFTWARE_TRIGGERED_BIT7_SHFT 7 -#define SH_TSF_SOFTWARE_TRIGGERED_BIT7_MASK 0x0000000000000080 - -/* ==================================================================== */ -/* Register "SH_TSF_TRIGGER_MASK" */ -/* Trigger sequencing facility trigger mask */ -/* ==================================================================== */ - -#define SH_TSF_TRIGGER_MASK 0x0000000110065480 -#define SH_TSF_TRIGGER_MASK_MASK 0xffffffffffffffff -#define SH_TSF_TRIGGER_MASK_INIT 0x0000000000000000 - -/* SH_TSF_TRIGGER_MASK_MASK */ -/* Description: Trigger sequencing facility trigger mask */ -#define SH_TSF_TRIGGER_MASK_MASK_SHFT 0 -#define SH_TSF_TRIGGER_MASK_MASK_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_VEC_DATA" */ -/* Vector Write Request Message Data */ -/* ==================================================================== */ - -#define SH_VEC_DATA 0x0000000110066000 -#define SH_VEC_DATA_MASK 0xffffffffffffffff -#define SH_VEC_DATA_INIT 0x0000000000000000 - -/* SH_VEC_DATA_DATA */ -/* Description: Data */ -#define SH_VEC_DATA_DATA_SHFT 0 -#define SH_VEC_DATA_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_VEC_PARMS" */ -/* Vector Message Parameters Register */ -/* ==================================================================== */ - -#define SH_VEC_PARMS 0x0000000110066080 -#define SH_VEC_PARMS_MASK 0xc0003ffffffffffb -#define SH_VEC_PARMS_INIT 0x0000000000000000 - -/* SH_VEC_PARMS_TYPE */ -/* Description: Vector Request Message Type */ -#define SH_VEC_PARMS_TYPE_SHFT 0 -#define SH_VEC_PARMS_TYPE_MASK 0x0000000000000001 - -/* SH_VEC_PARMS_NI_PORT */ -/* Description: Network Interface Port Select */ -#define SH_VEC_PARMS_NI_PORT_SHFT 1 -#define SH_VEC_PARMS_NI_PORT_MASK 0x0000000000000002 - -/* SH_VEC_PARMS_ADDRESS */ -/* Description: Address[37:6] */ -#define SH_VEC_PARMS_ADDRESS_SHFT 3 -#define SH_VEC_PARMS_ADDRESS_MASK 0x00000007fffffff8 - -/* SH_VEC_PARMS_PIO_ID */ -/* Description: PIO ID */ -#define SH_VEC_PARMS_PIO_ID_SHFT 35 -#define SH_VEC_PARMS_PIO_ID_MASK 0x00003ff800000000 - -/* SH_VEC_PARMS_START */ -/* Description: Start */ -#define SH_VEC_PARMS_START_SHFT 62 -#define SH_VEC_PARMS_START_MASK 0x4000000000000000 - -/* SH_VEC_PARMS_BUSY */ -/* Description: Busy */ -#define SH_VEC_PARMS_BUSY_SHFT 63 -#define SH_VEC_PARMS_BUSY_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_VEC_ROUTE" */ -/* Vector Request Message Route */ -/* ==================================================================== */ - -#define SH_VEC_ROUTE 0x0000000110066100 -#define SH_VEC_ROUTE_MASK 0xffffffffffffffff -#define SH_VEC_ROUTE_INIT 0x0000000000000000 - -/* SH_VEC_ROUTE_ROUTE */ -/* Description: Route */ -#define SH_VEC_ROUTE_ROUTE_SHFT 0 -#define SH_VEC_ROUTE_ROUTE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_CPU_PERM" */ -/* CPU MMR Access Permission Bits */ -/* ==================================================================== */ - -#define SH_CPU_PERM 0x0000000110060000 -#define SH_CPU_PERM_MASK 0xffffffffffffffff -#define SH_CPU_PERM_INIT 0xffffffffffffffff - -/* SH_CPU_PERM_ACCESS_BITS */ -/* Description: Access Bits */ -#define SH_CPU_PERM_ACCESS_BITS_SHFT 0 -#define SH_CPU_PERM_ACCESS_BITS_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_CPU_PERM_OVR" */ -/* CPU MMR Access Permission Override */ -/* ==================================================================== */ - -#define SH_CPU_PERM_OVR 0x0000000110060080 -#define SH_CPU_PERM_OVR_MASK 0xffffffffffffffff -#define SH_CPU_PERM_OVR_INIT 0x0000000000000000 - -/* SH_CPU_PERM_OVR_OVERRIDE */ -/* Description: Override */ -#define SH_CPU_PERM_OVR_OVERRIDE_SHFT 0 -#define SH_CPU_PERM_OVR_OVERRIDE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_EXT_IO_PERM" */ -/* External IO MMR Access Permission Bits */ -/* ==================================================================== */ - -#define SH_EXT_IO_PERM 0x0000000110060100 -#define SH_EXT_IO_PERM_MASK 0xffffffffffffffff -#define SH_EXT_IO_PERM_INIT 0x0000000000000000 - -/* SH_EXT_IO_PERM_ACCESS_BITS */ -/* Description: Access Bits */ -#define SH_EXT_IO_PERM_ACCESS_BITS_SHFT 0 -#define SH_EXT_IO_PERM_ACCESS_BITS_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_EXT_IOI_ACCESS" */ -/* External IO Interrupt Access Permission Bits */ -/* ==================================================================== */ - -#define SH_EXT_IOI_ACCESS 0x0000000110060180 -#define SH_EXT_IOI_ACCESS_MASK 0xffffffffffffffff -#define SH_EXT_IOI_ACCESS_INIT 0xffffffffffffffff - -/* SH_EXT_IOI_ACCESS_ACCESS_BITS */ -/* Description: Access Bits */ -#define SH_EXT_IOI_ACCESS_ACCESS_BITS_SHFT 0 -#define SH_EXT_IOI_ACCESS_ACCESS_BITS_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_GC_FIL_CTRL" */ -/* SHub Global Clock Filter Control */ -/* ==================================================================== */ - -#define SH_GC_FIL_CTRL 0x0000000110060200 -#define SH_GC_FIL_CTRL_MASK 0x03ff3ff3ff1fff1f -#define SH_GC_FIL_CTRL_INIT 0x0000000000000000 - -/* SH_GC_FIL_CTRL_OFFSET */ -/* Description: Offset */ -#define SH_GC_FIL_CTRL_OFFSET_SHFT 0 -#define SH_GC_FIL_CTRL_OFFSET_MASK 0x000000000000001f - -/* SH_GC_FIL_CTRL_MASK_COUNTER */ -/* Description: Mask Counter */ -#define SH_GC_FIL_CTRL_MASK_COUNTER_SHFT 8 -#define SH_GC_FIL_CTRL_MASK_COUNTER_MASK 0x00000000000fff00 - -/* SH_GC_FIL_CTRL_MASK_ENABLE */ -/* Description: Mask Enable */ -#define SH_GC_FIL_CTRL_MASK_ENABLE_SHFT 20 -#define SH_GC_FIL_CTRL_MASK_ENABLE_MASK 0x0000000000100000 - -/* SH_GC_FIL_CTRL_DROPOUT_COUNTER */ -/* Description: Dropout Counter */ -#define SH_GC_FIL_CTRL_DROPOUT_COUNTER_SHFT 24 -#define SH_GC_FIL_CTRL_DROPOUT_COUNTER_MASK 0x00000003ff000000 - -/* SH_GC_FIL_CTRL_DROPOUT_THRESH */ -/* Description: Dropout threshold */ -#define SH_GC_FIL_CTRL_DROPOUT_THRESH_SHFT 36 -#define SH_GC_FIL_CTRL_DROPOUT_THRESH_MASK 0x00003ff000000000 - -/* SH_GC_FIL_CTRL_ERROR_COUNTER */ -/* Description: Error counter */ -#define SH_GC_FIL_CTRL_ERROR_COUNTER_SHFT 48 -#define SH_GC_FIL_CTRL_ERROR_COUNTER_MASK 0x03ff000000000000 - -/* ==================================================================== */ -/* Register "SH_GC_SRC_CTRL" */ -/* SHub Global Clock Control */ -/* ==================================================================== */ - -#define SH_GC_SRC_CTRL 0x0000000110060280 -#define SH_GC_SRC_CTRL_MASK 0x0000000313ff3ff1 -#define SH_GC_SRC_CTRL_INIT 0x0000000100000000 - -/* SH_GC_SRC_CTRL_ENABLE_COUNTER */ -/* Description: Enable Counter */ -#define SH_GC_SRC_CTRL_ENABLE_COUNTER_SHFT 0 -#define SH_GC_SRC_CTRL_ENABLE_COUNTER_MASK 0x0000000000000001 - -/* SH_GC_SRC_CTRL_MAX_COUNT */ -/* Description: Max Count */ -#define SH_GC_SRC_CTRL_MAX_COUNT_SHFT 4 -#define SH_GC_SRC_CTRL_MAX_COUNT_MASK 0x0000000000003ff0 - -/* SH_GC_SRC_CTRL_COUNTER */ -/* Description: Counter */ -#define SH_GC_SRC_CTRL_COUNTER_SHFT 16 -#define SH_GC_SRC_CTRL_COUNTER_MASK 0x0000000003ff0000 - -/* SH_GC_SRC_CTRL_TOGGLE_BIT */ -/* Description: Toggle bit */ -#define SH_GC_SRC_CTRL_TOGGLE_BIT_SHFT 28 -#define SH_GC_SRC_CTRL_TOGGLE_BIT_MASK 0x0000000010000000 - -/* SH_GC_SRC_CTRL_SOURCE_SEL */ -/* Description: Source select (0=ext., 1=Int., 2=SHUB) */ -#define SH_GC_SRC_CTRL_SOURCE_SEL_SHFT 32 -#define SH_GC_SRC_CTRL_SOURCE_SEL_MASK 0x0000000300000000 - -/* ==================================================================== */ -/* Register "SH_HARD_RESET" */ -/* SHub Hard Reset */ -/* ==================================================================== */ - -#define SH_HARD_RESET 0x0000000110060300 -#define SH_HARD_RESET_MASK 0x0000000000000001 -#define SH_HARD_RESET_INIT 0x0000000000000000 - -/* SH_HARD_RESET_HARD_RESET */ -/* Description: Hard Reset */ -#define SH_HARD_RESET_HARD_RESET_SHFT 0 -#define SH_HARD_RESET_HARD_RESET_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_IO_PERM" */ -/* II MMR Access Permission Bits */ -/* ==================================================================== */ - -#define SH_IO_PERM 0x0000000110060380 -#define SH_IO_PERM_MASK 0xffffffffffffffff -#define SH_IO_PERM_INIT 0x0000000000000000 - -/* SH_IO_PERM_ACCESS_BITS */ -/* Description: Access Bits */ -#define SH_IO_PERM_ACCESS_BITS_SHFT 0 -#define SH_IO_PERM_ACCESS_BITS_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_IOI_ACCESS" */ -/* II Interrupt Access Permission Bits */ -/* ==================================================================== */ - -#define SH_IOI_ACCESS 0x0000000110060400 -#define SH_IOI_ACCESS_MASK 0xffffffffffffffff -#define SH_IOI_ACCESS_INIT 0xffffffffffffffff - -/* SH_IOI_ACCESS_ACCESS_BITS */ -/* Description: Access Bits */ -#define SH_IOI_ACCESS_ACCESS_BITS_SHFT 0 -#define SH_IOI_ACCESS_ACCESS_BITS_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_IPI_ACCESS" */ -/* CPU interrupt Access Permission Bits */ -/* ==================================================================== */ - -#define SH_IPI_ACCESS 0x0000000110060480 -#define SH_IPI_ACCESS_MASK 0xffffffffffffffff -#define SH_IPI_ACCESS_INIT 0xffffffffffffffff - -/* SH_IPI_ACCESS_ACCESS_BITS */ -/* Description: Access Bits */ -#define SH_IPI_ACCESS_ACCESS_BITS_SHFT 0 -#define SH_IPI_ACCESS_ACCESS_BITS_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_JTAG_CONFIG" */ -/* SHub JTAG configuration */ -/* ==================================================================== */ - -#define SH_JTAG_CONFIG 0x0000000110060500 -#define SH_JTAG_CONFIG_MASK 0x00ffffffffffffff -#define SH_JTAG_CONFIG_INIT 0x0000000000000000 - -/* SH_JTAG_CONFIG_MD_CLK_SEL */ -/* Description: Select divide freq of DRAMCLK */ -#define SH_JTAG_CONFIG_MD_CLK_SEL_SHFT 0 -#define SH_JTAG_CONFIG_MD_CLK_SEL_MASK 0x0000000000000003 - -/* SH_JTAG_CONFIG_NI_CLK_SEL */ -/* Description: Selects clock source for NICLK domain */ -#define SH_JTAG_CONFIG_NI_CLK_SEL_SHFT 2 -#define SH_JTAG_CONFIG_NI_CLK_SEL_MASK 0x0000000000000004 - -/* SH_JTAG_CONFIG_II_CLK_SEL */ -/* Description: Selects clock source for IOCLK domain */ -#define SH_JTAG_CONFIG_II_CLK_SEL_SHFT 3 -#define SH_JTAG_CONFIG_II_CLK_SEL_MASK 0x0000000000000018 - -/* SH_JTAG_CONFIG_WRT90_TARGET */ -/* Description: wrt90_target */ -#define SH_JTAG_CONFIG_WRT90_TARGET_SHFT 5 -#define SH_JTAG_CONFIG_WRT90_TARGET_MASK 0x000000000007ffe0 - -/* SH_JTAG_CONFIG_WRT90_OVERRIDER */ -/* Description: wrt90_overrideR */ -#define SH_JTAG_CONFIG_WRT90_OVERRIDER_SHFT 19 -#define SH_JTAG_CONFIG_WRT90_OVERRIDER_MASK 0x0000000000080000 - -/* SH_JTAG_CONFIG_WRT90_OVERRIDE */ -/* Description: wrt90_override */ -#define SH_JTAG_CONFIG_WRT90_OVERRIDE_SHFT 20 -#define SH_JTAG_CONFIG_WRT90_OVERRIDE_MASK 0x0000000000100000 - -/* SH_JTAG_CONFIG_JTAG_MCI_RESET_DELAY */ -/* Description: jtag_mci_reset_delay */ -#define SH_JTAG_CONFIG_JTAG_MCI_RESET_DELAY_SHFT 21 -#define SH_JTAG_CONFIG_JTAG_MCI_RESET_DELAY_MASK 0x0000000001e00000 - -/* SH_JTAG_CONFIG_JTAG_MCI_TARGET */ -/* Description: jtag_mci_target */ -#define SH_JTAG_CONFIG_JTAG_MCI_TARGET_SHFT 25 -#define SH_JTAG_CONFIG_JTAG_MCI_TARGET_MASK 0x0000007ffe000000 - -/* SH_JTAG_CONFIG_JTAG_MCI_OVERRIDE */ -/* Description: jtag_mci_override */ -#define SH_JTAG_CONFIG_JTAG_MCI_OVERRIDE_SHFT 39 -#define SH_JTAG_CONFIG_JTAG_MCI_OVERRIDE_MASK 0x0000008000000000 - -/* SH_JTAG_CONFIG_FSB_CONFIG_IOQ_DEPTH */ -/* Description: 0=depth 8, 1=depth1 */ -#define SH_JTAG_CONFIG_FSB_CONFIG_IOQ_DEPTH_SHFT 40 -#define SH_JTAG_CONFIG_FSB_CONFIG_IOQ_DEPTH_MASK 0x0000010000000000 - -/* SH_JTAG_CONFIG_FSB_CONFIG_SAMPLE_BINIT */ -/* Description: Enable sampling of BINIT */ -#define SH_JTAG_CONFIG_FSB_CONFIG_SAMPLE_BINIT_SHFT 41 -#define SH_JTAG_CONFIG_FSB_CONFIG_SAMPLE_BINIT_MASK 0x0000020000000000 - -/* SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BUS_PARKING */ -#define SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BUS_PARKING_SHFT 42 -#define SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BUS_PARKING_MASK 0x0000040000000000 - -/* SH_JTAG_CONFIG_FSB_CONFIG_CLOCK_RATIO */ -#define SH_JTAG_CONFIG_FSB_CONFIG_CLOCK_RATIO_SHFT 43 -#define SH_JTAG_CONFIG_FSB_CONFIG_CLOCK_RATIO_MASK 0x0000f80000000000 - -/* SH_JTAG_CONFIG_FSB_CONFIG_OUTPUT_TRISTATE */ -/* Description: Output tristate control */ -#define SH_JTAG_CONFIG_FSB_CONFIG_OUTPUT_TRISTATE_SHFT 48 -#define SH_JTAG_CONFIG_FSB_CONFIG_OUTPUT_TRISTATE_MASK 0x000f000000000000 - -/* SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BIST */ -/* Description: Enables BIST */ -#define SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BIST_SHFT 52 -#define SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BIST_MASK 0x0010000000000000 - -/* SH_JTAG_CONFIG_FSB_CONFIG_AUX */ -/* Description: Enables BIST */ -#define SH_JTAG_CONFIG_FSB_CONFIG_AUX_SHFT 53 -#define SH_JTAG_CONFIG_FSB_CONFIG_AUX_MASK 0x0060000000000000 - -/* SH_JTAG_CONFIG_GTL_CONFIG_RE */ -/* Description: Reference Enable selection for GTL io */ -#define SH_JTAG_CONFIG_GTL_CONFIG_RE_SHFT 55 -#define SH_JTAG_CONFIG_GTL_CONFIG_RE_MASK 0x0080000000000000 - -/* ==================================================================== */ -/* Register "SH_SHUB_ID" */ -/* SHub ID Number */ -/* ==================================================================== */ - -#define SH_SHUB_ID 0x0000000110060580 -#define SH_SHUB_ID_MASK 0x011f37ffffffffff -#define SH_SHUB_ID_INIT 0x0010300000000000 - -/* SH_SHUB_ID_FORCE1 */ -/* Description: Must be 1 */ -#define SH_SHUB_ID_FORCE1_SHFT 0 -#define SH_SHUB_ID_FORCE1_MASK 0x0000000000000001 - -/* SH_SHUB_ID_MANUFACTURER */ -/* Description: Manufacturer */ -#define SH_SHUB_ID_MANUFACTURER_SHFT 1 -#define SH_SHUB_ID_MANUFACTURER_MASK 0x0000000000000ffe - -/* SH_SHUB_ID_PART_NUMBER */ -/* Description: Part Number */ -#define SH_SHUB_ID_PART_NUMBER_SHFT 12 -#define SH_SHUB_ID_PART_NUMBER_MASK 0x000000000ffff000 - -/* SH_SHUB_ID_REVISION */ -/* Description: Revision */ -#define SH_SHUB_ID_REVISION_SHFT 28 -#define SH_SHUB_ID_REVISION_MASK 0x00000000f0000000 - -/* SH_SHUB_ID_NODE_ID */ -/* Description: Node Identification */ -#define SH_SHUB_ID_NODE_ID_SHFT 32 -#define SH_SHUB_ID_NODE_ID_MASK 0x000007ff00000000 - -/* SH_SHUB_ID_SHARING_MODE */ -/* Description: Sharing mode (Coherency Domain Size) */ -#define SH_SHUB_ID_SHARING_MODE_SHFT 44 -#define SH_SHUB_ID_SHARING_MODE_MASK 0x0000300000000000 - -/* SH_SHUB_ID_NODES_PER_BIT */ -/* Description: Nodes per bit definition for MMR access */ -#define SH_SHUB_ID_NODES_PER_BIT_SHFT 48 -#define SH_SHUB_ID_NODES_PER_BIT_MASK 0x001f000000000000 - -/* SH_SHUB_ID_NI_PORT */ -/* Description: NI port of vector reference, 0 = NI0, 1 = NI1 */ -#define SH_SHUB_ID_NI_PORT_SHFT 56 -#define SH_SHUB_ID_NI_PORT_MASK 0x0100000000000000 - -/* ==================================================================== */ -/* Register "SH_SHUBS_PRESENT0" */ -/* Shubs 0 - 63 Present. Used for invalidate generation */ -/* ==================================================================== */ - -#define SH_SHUBS_PRESENT0 0x0000000110060600 -#define SH_SHUBS_PRESENT0_MASK 0xffffffffffffffff -#define SH_SHUBS_PRESENT0_INIT 0xffffffffffffffff - -/* SH_SHUBS_PRESENT0_SHUBS_PRESENT0 */ -/* Description: Shubs 0 - 63 Present configuration */ -#define SH_SHUBS_PRESENT0_SHUBS_PRESENT0_SHFT 0 -#define SH_SHUBS_PRESENT0_SHUBS_PRESENT0_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_SHUBS_PRESENT1" */ -/* Shubs 64 - 127 Present. Used for invalidate generation */ -/* ==================================================================== */ - -#define SH_SHUBS_PRESENT1 0x0000000110060680 -#define SH_SHUBS_PRESENT1_MASK 0xffffffffffffffff -#define SH_SHUBS_PRESENT1_INIT 0xffffffffffffffff - -/* SH_SHUBS_PRESENT1_SHUBS_PRESENT1 */ -/* Description: Shubs 64 - 127 Present configuration */ -#define SH_SHUBS_PRESENT1_SHUBS_PRESENT1_SHFT 0 -#define SH_SHUBS_PRESENT1_SHUBS_PRESENT1_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_SHUBS_PRESENT2" */ -/* Shubs 128 - 191 Present. Used for invalidate generation */ -/* ==================================================================== */ - -#define SH_SHUBS_PRESENT2 0x0000000110060700 -#define SH_SHUBS_PRESENT2_MASK 0xffffffffffffffff -#define SH_SHUBS_PRESENT2_INIT 0xffffffffffffffff - -/* SH_SHUBS_PRESENT2_SHUBS_PRESENT2 */ -/* Description: Shubs 128 - 191 Present configuration */ -#define SH_SHUBS_PRESENT2_SHUBS_PRESENT2_SHFT 0 -#define SH_SHUBS_PRESENT2_SHUBS_PRESENT2_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_SHUBS_PRESENT3" */ -/* Shubs 192 - 255 Present. Used for invalidate generation */ -/* ==================================================================== */ - -#define SH_SHUBS_PRESENT3 0x0000000110060780 -#define SH_SHUBS_PRESENT3_MASK 0xffffffffffffffff -#define SH_SHUBS_PRESENT3_INIT 0xffffffffffffffff - -/* SH_SHUBS_PRESENT3_SHUBS_PRESENT3 */ -/* Description: Shubs 192 - 255 Present configuration */ -#define SH_SHUBS_PRESENT3_SHUBS_PRESENT3_SHFT 0 -#define SH_SHUBS_PRESENT3_SHUBS_PRESENT3_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_SOFT_RESET" */ -/* SHub Soft Reset */ -/* ==================================================================== */ - -#define SH_SOFT_RESET 0x0000000110060800 -#define SH_SOFT_RESET_MASK 0x0000000000000001 -#define SH_SOFT_RESET_INIT 0x0000000000000000 - -/* SH_SOFT_RESET_SOFT_RESET */ -/* Description: Soft Reset */ -#define SH_SOFT_RESET_SOFT_RESET_SHFT 0 -#define SH_SOFT_RESET_SOFT_RESET_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_FIRST_ERROR" */ -/* Shub Global First Error Flags */ -/* ==================================================================== */ - -#define SH_FIRST_ERROR 0x0000000110071000 -#define SH_FIRST_ERROR_MASK 0x000000000007ffff -#define SH_FIRST_ERROR_INIT 0x0000000000000000 - -/* SH_FIRST_ERROR_FIRST_ERROR */ -/* Description: Chiplet with first error */ -#define SH_FIRST_ERROR_FIRST_ERROR_SHFT 0 -#define SH_FIRST_ERROR_FIRST_ERROR_MASK 0x000000000007ffff - -/* ==================================================================== */ -/* Register "SH_II_HW_TIME_STAMP" */ -/* II hardware error time stamp */ -/* ==================================================================== */ - -#define SH_II_HW_TIME_STAMP 0x0000000110071080 -#define SH_II_HW_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_II_HW_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_II_HW_TIME_STAMP_TIME */ -/* Description: II hardware error time stamp */ -#define SH_II_HW_TIME_STAMP_TIME_SHFT 0 -#define SH_II_HW_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_II_HW_TIME_STAMP_VALID */ -/* Description: II hardware error time stamp valid */ -#define SH_II_HW_TIME_STAMP_VALID_SHFT 63 -#define SH_II_HW_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_LB_HW_TIME_STAMP" */ -/* LB hardware error time stamp */ -/* ==================================================================== */ - -#define SH_LB_HW_TIME_STAMP 0x0000000110071100 -#define SH_LB_HW_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_LB_HW_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_LB_HW_TIME_STAMP_TIME */ -/* Description: LB hardware error time stamp */ -#define SH_LB_HW_TIME_STAMP_TIME_SHFT 0 -#define SH_LB_HW_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_LB_HW_TIME_STAMP_VALID */ -/* Description: LB hardware error time stamp valid */ -#define SH_LB_HW_TIME_STAMP_VALID_SHFT 63 -#define SH_LB_HW_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_COR_TIME_STAMP" */ -/* MD correctable error time stamp */ -/* ==================================================================== */ - -#define SH_MD_COR_TIME_STAMP 0x0000000110071180 -#define SH_MD_COR_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_MD_COR_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_MD_COR_TIME_STAMP_TIME */ -/* Description: MD correctable error time stamp */ -#define SH_MD_COR_TIME_STAMP_TIME_SHFT 0 -#define SH_MD_COR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_MD_COR_TIME_STAMP_VALID */ -/* Description: MD correctable error time stamp valid */ -#define SH_MD_COR_TIME_STAMP_VALID_SHFT 63 -#define SH_MD_COR_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_HW_TIME_STAMP" */ -/* MD hardware error time stamp */ -/* ==================================================================== */ - -#define SH_MD_HW_TIME_STAMP 0x0000000110071200 -#define SH_MD_HW_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_MD_HW_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_MD_HW_TIME_STAMP_TIME */ -/* Description: MD hardware error time stamp */ -#define SH_MD_HW_TIME_STAMP_TIME_SHFT 0 -#define SH_MD_HW_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_MD_HW_TIME_STAMP_VALID */ -/* Description: MD hardware error time stamp valid */ -#define SH_MD_HW_TIME_STAMP_VALID_SHFT 63 -#define SH_MD_HW_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_UNCOR_TIME_STAMP" */ -/* MD uncorrectable error time stamp */ -/* ==================================================================== */ - -#define SH_MD_UNCOR_TIME_STAMP 0x0000000110071280 -#define SH_MD_UNCOR_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_MD_UNCOR_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_MD_UNCOR_TIME_STAMP_TIME */ -/* Description: MD uncorrectable error time stamp */ -#define SH_MD_UNCOR_TIME_STAMP_TIME_SHFT 0 -#define SH_MD_UNCOR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_MD_UNCOR_TIME_STAMP_VALID */ -/* Description: MD uncorrectable error time stamp valid */ -#define SH_MD_UNCOR_TIME_STAMP_VALID_SHFT 63 -#define SH_MD_UNCOR_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_COR_TIME_STAMP" */ -/* PI correctable error time stamp */ -/* ==================================================================== */ - -#define SH_PI_COR_TIME_STAMP 0x0000000110071300 -#define SH_PI_COR_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_PI_COR_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_PI_COR_TIME_STAMP_TIME */ -/* Description: PI correctable error time stamp */ -#define SH_PI_COR_TIME_STAMP_TIME_SHFT 0 -#define SH_PI_COR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_PI_COR_TIME_STAMP_VALID */ -/* Description: PI correctable error time stamp valid */ -#define SH_PI_COR_TIME_STAMP_VALID_SHFT 63 -#define SH_PI_COR_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_HW_TIME_STAMP" */ -/* PI hardware error time stamp */ -/* ==================================================================== */ - -#define SH_PI_HW_TIME_STAMP 0x0000000110071380 -#define SH_PI_HW_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_PI_HW_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_PI_HW_TIME_STAMP_TIME */ -/* Description: PI hardware error time stamp */ -#define SH_PI_HW_TIME_STAMP_TIME_SHFT 0 -#define SH_PI_HW_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_PI_HW_TIME_STAMP_VALID */ -/* Description: PI hardware error time stamp valid */ -#define SH_PI_HW_TIME_STAMP_VALID_SHFT 63 -#define SH_PI_HW_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_UNCOR_TIME_STAMP" */ -/* PI uncorrectable error time stamp */ -/* ==================================================================== */ - -#define SH_PI_UNCOR_TIME_STAMP 0x0000000110071400 -#define SH_PI_UNCOR_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_PI_UNCOR_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_PI_UNCOR_TIME_STAMP_TIME */ -/* Description: PI uncorrectable error time stamp */ -#define SH_PI_UNCOR_TIME_STAMP_TIME_SHFT 0 -#define SH_PI_UNCOR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_PI_UNCOR_TIME_STAMP_VALID */ -/* Description: PI uncorrectable error time stamp valid */ -#define SH_PI_UNCOR_TIME_STAMP_VALID_SHFT 63 -#define SH_PI_UNCOR_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC0_ADV_TIME_STAMP" */ -/* Proc 0 advisory time stamp */ -/* ==================================================================== */ - -#define SH_PROC0_ADV_TIME_STAMP 0x0000000110071480 -#define SH_PROC0_ADV_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_PROC0_ADV_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_PROC0_ADV_TIME_STAMP_TIME */ -/* Description: Processor 0 advisory time stamp */ -#define SH_PROC0_ADV_TIME_STAMP_TIME_SHFT 0 -#define SH_PROC0_ADV_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_PROC0_ADV_TIME_STAMP_VALID */ -/* Description: Processor 0 advisory time stamp valid */ -#define SH_PROC0_ADV_TIME_STAMP_VALID_SHFT 63 -#define SH_PROC0_ADV_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC0_ERR_TIME_STAMP" */ -/* Proc 0 error time stamp */ -/* ==================================================================== */ - -#define SH_PROC0_ERR_TIME_STAMP 0x0000000110071500 -#define SH_PROC0_ERR_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_PROC0_ERR_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_PROC0_ERR_TIME_STAMP_TIME */ -/* Description: Processor 0 error time stamp */ -#define SH_PROC0_ERR_TIME_STAMP_TIME_SHFT 0 -#define SH_PROC0_ERR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_PROC0_ERR_TIME_STAMP_VALID */ -/* Description: Processor 0 error time stamp valid */ -#define SH_PROC0_ERR_TIME_STAMP_VALID_SHFT 63 -#define SH_PROC0_ERR_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC1_ADV_TIME_STAMP" */ -/* Proc 1 advisory time stamp */ -/* ==================================================================== */ - -#define SH_PROC1_ADV_TIME_STAMP 0x0000000110071580 -#define SH_PROC1_ADV_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_PROC1_ADV_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_PROC1_ADV_TIME_STAMP_TIME */ -/* Description: Processor 1 advisory time stamp */ -#define SH_PROC1_ADV_TIME_STAMP_TIME_SHFT 0 -#define SH_PROC1_ADV_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_PROC1_ADV_TIME_STAMP_VALID */ -/* Description: Processor 1 advisory time stamp valid */ -#define SH_PROC1_ADV_TIME_STAMP_VALID_SHFT 63 -#define SH_PROC1_ADV_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC1_ERR_TIME_STAMP" */ -/* Proc 1 error time stamp */ -/* ==================================================================== */ - -#define SH_PROC1_ERR_TIME_STAMP 0x0000000110071600 -#define SH_PROC1_ERR_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_PROC1_ERR_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_PROC1_ERR_TIME_STAMP_TIME */ -/* Description: Processor 1 error time stamp */ -#define SH_PROC1_ERR_TIME_STAMP_TIME_SHFT 0 -#define SH_PROC1_ERR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_PROC1_ERR_TIME_STAMP_VALID */ -/* Description: Processor 1 error time stamp valid */ -#define SH_PROC1_ERR_TIME_STAMP_VALID_SHFT 63 -#define SH_PROC1_ERR_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC2_ADV_TIME_STAMP" */ -/* Proc 2 advisory time stamp */ -/* ==================================================================== */ - -#define SH_PROC2_ADV_TIME_STAMP 0x0000000110071680 -#define SH_PROC2_ADV_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_PROC2_ADV_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_PROC2_ADV_TIME_STAMP_TIME */ -/* Description: Processor 2 advisory time stamp */ -#define SH_PROC2_ADV_TIME_STAMP_TIME_SHFT 0 -#define SH_PROC2_ADV_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_PROC2_ADV_TIME_STAMP_VALID */ -/* Description: Processor 2 advisory time stamp valid */ -#define SH_PROC2_ADV_TIME_STAMP_VALID_SHFT 63 -#define SH_PROC2_ADV_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC2_ERR_TIME_STAMP" */ -/* Proc 2 error time stamp */ -/* ==================================================================== */ - -#define SH_PROC2_ERR_TIME_STAMP 0x0000000110071700 -#define SH_PROC2_ERR_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_PROC2_ERR_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_PROC2_ERR_TIME_STAMP_TIME */ -/* Description: Processor 2 error time stamp */ -#define SH_PROC2_ERR_TIME_STAMP_TIME_SHFT 0 -#define SH_PROC2_ERR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_PROC2_ERR_TIME_STAMP_VALID */ -/* Description: Processor 2 error time stamp valid */ -#define SH_PROC2_ERR_TIME_STAMP_VALID_SHFT 63 -#define SH_PROC2_ERR_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC3_ADV_TIME_STAMP" */ -/* Proc 3 advisory time stamp */ -/* ==================================================================== */ - -#define SH_PROC3_ADV_TIME_STAMP 0x0000000110071780 -#define SH_PROC3_ADV_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_PROC3_ADV_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_PROC3_ADV_TIME_STAMP_TIME */ -/* Description: Processor 3 advisory time stamp */ -#define SH_PROC3_ADV_TIME_STAMP_TIME_SHFT 0 -#define SH_PROC3_ADV_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_PROC3_ADV_TIME_STAMP_VALID */ -/* Description: Processor 3 advisory time stamp valid */ -#define SH_PROC3_ADV_TIME_STAMP_VALID_SHFT 63 -#define SH_PROC3_ADV_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC3_ERR_TIME_STAMP" */ -/* Proc 3 error time stamp */ -/* ==================================================================== */ - -#define SH_PROC3_ERR_TIME_STAMP 0x0000000110071800 -#define SH_PROC3_ERR_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_PROC3_ERR_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_PROC3_ERR_TIME_STAMP_TIME */ -/* Description: Processor 3 error time stamp */ -#define SH_PROC3_ERR_TIME_STAMP_TIME_SHFT 0 -#define SH_PROC3_ERR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_PROC3_ERR_TIME_STAMP_VALID */ -/* Description: Processor 3 error time stamp valid */ -#define SH_PROC3_ERR_TIME_STAMP_VALID_SHFT 63 -#define SH_PROC3_ERR_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_XN_COR_TIME_STAMP" */ -/* XN correctable error time stamp */ -/* ==================================================================== */ - -#define SH_XN_COR_TIME_STAMP 0x0000000110071880 -#define SH_XN_COR_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_XN_COR_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_XN_COR_TIME_STAMP_TIME */ -/* Description: XN correctable error time stamp */ -#define SH_XN_COR_TIME_STAMP_TIME_SHFT 0 -#define SH_XN_COR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_XN_COR_TIME_STAMP_VALID */ -/* Description: XN correctable error time stamp valid */ -#define SH_XN_COR_TIME_STAMP_VALID_SHFT 63 -#define SH_XN_COR_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_XN_HW_TIME_STAMP" */ -/* XN hardware error time stamp */ -/* ==================================================================== */ - -#define SH_XN_HW_TIME_STAMP 0x0000000110071900 -#define SH_XN_HW_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_XN_HW_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_XN_HW_TIME_STAMP_TIME */ -/* Description: XN hardware error time stamp */ -#define SH_XN_HW_TIME_STAMP_TIME_SHFT 0 -#define SH_XN_HW_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_XN_HW_TIME_STAMP_VALID */ -/* Description: XN hardware error time stamp valid */ -#define SH_XN_HW_TIME_STAMP_VALID_SHFT 63 -#define SH_XN_HW_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_XN_UNCOR_TIME_STAMP" */ -/* XN uncorrectable error time stamp */ -/* ==================================================================== */ - -#define SH_XN_UNCOR_TIME_STAMP 0x0000000110071980 -#define SH_XN_UNCOR_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_XN_UNCOR_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_XN_UNCOR_TIME_STAMP_TIME */ -/* Description: XN uncorrectable error time stamp */ -#define SH_XN_UNCOR_TIME_STAMP_TIME_SHFT 0 -#define SH_XN_UNCOR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_XN_UNCOR_TIME_STAMP_VALID */ -/* Description: XN uncorrectable error time stamp valid */ -#define SH_XN_UNCOR_TIME_STAMP_VALID_SHFT 63 -#define SH_XN_UNCOR_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_DEBUG_PORT" */ -/* SHub Debug Port */ -/* ==================================================================== */ - -#define SH_DEBUG_PORT 0x0000000110072000 -#define SH_DEBUG_PORT_MASK 0x00000000ffffffff -#define SH_DEBUG_PORT_INIT 0x0000000000000000 - -/* SH_DEBUG_PORT_DEBUG_NIBBLE0 */ -/* Description: Debug port nibble 0 */ -#define SH_DEBUG_PORT_DEBUG_NIBBLE0_SHFT 0 -#define SH_DEBUG_PORT_DEBUG_NIBBLE0_MASK 0x000000000000000f - -/* SH_DEBUG_PORT_DEBUG_NIBBLE1 */ -/* Description: Debug port nibble 1 */ -#define SH_DEBUG_PORT_DEBUG_NIBBLE1_SHFT 4 -#define SH_DEBUG_PORT_DEBUG_NIBBLE1_MASK 0x00000000000000f0 - -/* SH_DEBUG_PORT_DEBUG_NIBBLE2 */ -/* Description: Debug port nibble 2 */ -#define SH_DEBUG_PORT_DEBUG_NIBBLE2_SHFT 8 -#define SH_DEBUG_PORT_DEBUG_NIBBLE2_MASK 0x0000000000000f00 - -/* SH_DEBUG_PORT_DEBUG_NIBBLE3 */ -/* Description: Debug port nibble 3 */ -#define SH_DEBUG_PORT_DEBUG_NIBBLE3_SHFT 12 -#define SH_DEBUG_PORT_DEBUG_NIBBLE3_MASK 0x000000000000f000 - -/* SH_DEBUG_PORT_DEBUG_NIBBLE4 */ -/* Description: Debug port nibble 4 */ -#define SH_DEBUG_PORT_DEBUG_NIBBLE4_SHFT 16 -#define SH_DEBUG_PORT_DEBUG_NIBBLE4_MASK 0x00000000000f0000 - -/* SH_DEBUG_PORT_DEBUG_NIBBLE5 */ -/* Description: Debug port nibble 5 */ -#define SH_DEBUG_PORT_DEBUG_NIBBLE5_SHFT 20 -#define SH_DEBUG_PORT_DEBUG_NIBBLE5_MASK 0x0000000000f00000 - -/* SH_DEBUG_PORT_DEBUG_NIBBLE6 */ -/* Description: Debug port nibble 6 */ -#define SH_DEBUG_PORT_DEBUG_NIBBLE6_SHFT 24 -#define SH_DEBUG_PORT_DEBUG_NIBBLE6_MASK 0x000000000f000000 - -/* SH_DEBUG_PORT_DEBUG_NIBBLE7 */ -/* Description: Debug port nibble 7 */ -#define SH_DEBUG_PORT_DEBUG_NIBBLE7_SHFT 28 -#define SH_DEBUG_PORT_DEBUG_NIBBLE7_MASK 0x00000000f0000000 - -/* ==================================================================== */ -/* Register "SH_II_DEBUG_DATA" */ -/* II Debug Data */ -/* ==================================================================== */ - -#define SH_II_DEBUG_DATA 0x0000000110072080 -#define SH_II_DEBUG_DATA_MASK 0x00000000ffffffff -#define SH_II_DEBUG_DATA_INIT 0x0000000000000000 - -/* SH_II_DEBUG_DATA_II_DATA */ -/* Description: II debug data */ -#define SH_II_DEBUG_DATA_II_DATA_SHFT 0 -#define SH_II_DEBUG_DATA_II_DATA_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_II_WRAP_DEBUG_DATA" */ -/* SHub II Wrapper Debug Data */ -/* ==================================================================== */ - -#define SH_II_WRAP_DEBUG_DATA 0x0000000110072100 -#define SH_II_WRAP_DEBUG_DATA_MASK 0x00000000ffffffff -#define SH_II_WRAP_DEBUG_DATA_INIT 0x0000000000000000 - -/* SH_II_WRAP_DEBUG_DATA_II_WRAP_DATA */ -/* Description: II wrapper debug data */ -#define SH_II_WRAP_DEBUG_DATA_II_WRAP_DATA_SHFT 0 -#define SH_II_WRAP_DEBUG_DATA_II_WRAP_DATA_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_LB_DEBUG_DATA" */ -/* SHub LB Debug Data */ -/* ==================================================================== */ - -#define SH_LB_DEBUG_DATA 0x0000000110072180 -#define SH_LB_DEBUG_DATA_MASK 0x00000000ffffffff -#define SH_LB_DEBUG_DATA_INIT 0x0000000000000000 - -/* SH_LB_DEBUG_DATA_LB_DATA */ -/* Description: LB debug data */ -#define SH_LB_DEBUG_DATA_LB_DATA_SHFT 0 -#define SH_LB_DEBUG_DATA_LB_DATA_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DEBUG_DATA" */ -/* SHub MD Debug Data */ -/* ==================================================================== */ - -#define SH_MD_DEBUG_DATA 0x0000000110072200 -#define SH_MD_DEBUG_DATA_MASK 0x00000000ffffffff -#define SH_MD_DEBUG_DATA_INIT 0x0000000000000000 - -/* SH_MD_DEBUG_DATA_MD_DATA */ -/* Description: MD debug data */ -#define SH_MD_DEBUG_DATA_MD_DATA_SHFT 0 -#define SH_MD_DEBUG_DATA_MD_DATA_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_PI_DEBUG_DATA" */ -/* SHub PI Debug Data */ -/* ==================================================================== */ - -#define SH_PI_DEBUG_DATA 0x0000000110072280 -#define SH_PI_DEBUG_DATA_MASK 0x00000000ffffffff -#define SH_PI_DEBUG_DATA_INIT 0x0000000000000000 - -/* SH_PI_DEBUG_DATA_PI_DATA */ -/* Description: PI Debug Data */ -#define SH_PI_DEBUG_DATA_PI_DATA_SHFT 0 -#define SH_PI_DEBUG_DATA_PI_DATA_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_XN_DEBUG_DATA" */ -/* SHub XN Debug Data */ -/* ==================================================================== */ - -#define SH_XN_DEBUG_DATA 0x0000000110072300 -#define SH_XN_DEBUG_DATA_MASK 0x00000000ffffffff -#define SH_XN_DEBUG_DATA_INIT 0x0000000000000000 - -/* SH_XN_DEBUG_DATA_XN_DATA */ -/* Description: XN debug data */ -#define SH_XN_DEBUG_DATA_XN_DATA_SHFT 0 -#define SH_XN_DEBUG_DATA_XN_DATA_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_TSF_ARMED_STATE" */ -/* Trigger sequencing facility arm state */ -/* ==================================================================== */ - -#define SH_TSF_ARMED_STATE 0x0000000110073000 -#define SH_TSF_ARMED_STATE_MASK 0x00000000000000ff -#define SH_TSF_ARMED_STATE_INIT 0x0000000000000000 - -/* SH_TSF_ARMED_STATE_STATE */ -/* Description: Trigger sequencing facility armed state */ -#define SH_TSF_ARMED_STATE_STATE_SHFT 0 -#define SH_TSF_ARMED_STATE_STATE_MASK 0x00000000000000ff - -/* ==================================================================== */ -/* Register "SH_TSF_COUNTER_VALUE" */ -/* Trigger sequencing facility counter value */ -/* ==================================================================== */ - -#define SH_TSF_COUNTER_VALUE 0x0000000110073080 -#define SH_TSF_COUNTER_VALUE_MASK 0xffffffffffffffff -#define SH_TSF_COUNTER_VALUE_INIT 0x0000000000000000 - -/* SH_TSF_COUNTER_VALUE_COUNT_32 */ -/* Description: Trigger sequencing facility counter 32 */ -#define SH_TSF_COUNTER_VALUE_COUNT_32_SHFT 0 -#define SH_TSF_COUNTER_VALUE_COUNT_32_MASK 0x00000000ffffffff - -/* SH_TSF_COUNTER_VALUE_COUNT_16 */ -/* Description: Trigger sequencing facility counter 16 */ -#define SH_TSF_COUNTER_VALUE_COUNT_16_SHFT 32 -#define SH_TSF_COUNTER_VALUE_COUNT_16_MASK 0x0000ffff00000000 - -/* SH_TSF_COUNTER_VALUE_COUNT_8B */ -/* Description: Trigger sequencing facility counter 8b */ -#define SH_TSF_COUNTER_VALUE_COUNT_8B_SHFT 48 -#define SH_TSF_COUNTER_VALUE_COUNT_8B_MASK 0x00ff000000000000 - -/* SH_TSF_COUNTER_VALUE_COUNT_8A */ -/* Description: Trigger sequencing facility counter 8a */ -#define SH_TSF_COUNTER_VALUE_COUNT_8A_SHFT 56 -#define SH_TSF_COUNTER_VALUE_COUNT_8A_MASK 0xff00000000000000 - -/* ==================================================================== */ -/* Register "SH_TSF_TRIGGERED_STATE" */ -/* Trigger sequencing facility triggered state */ -/* ==================================================================== */ - -#define SH_TSF_TRIGGERED_STATE 0x0000000110073100 -#define SH_TSF_TRIGGERED_STATE_MASK 0x00000000000000ff -#define SH_TSF_TRIGGERED_STATE_INIT 0x0000000000000000 - -/* SH_TSF_TRIGGERED_STATE_STATE */ -/* Description: Trigger sequencing facility triggered state */ -#define SH_TSF_TRIGGERED_STATE_STATE_SHFT 0 -#define SH_TSF_TRIGGERED_STATE_STATE_MASK 0x00000000000000ff - -/* ==================================================================== */ -/* Register "SH_VEC_RDDATA" */ -/* Vector Reply Message Data */ -/* ==================================================================== */ - -#define SH_VEC_RDDATA 0x0000000110074000 -#define SH_VEC_RDDATA_MASK 0xffffffffffffffff -#define SH_VEC_RDDATA_INIT 0x0000000000000000 - -/* SH_VEC_RDDATA_DATA */ -/* Description: Data */ -#define SH_VEC_RDDATA_DATA_SHFT 0 -#define SH_VEC_RDDATA_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_VEC_RETURN" */ -/* Vector Reply Message Return Route */ -/* ==================================================================== */ - -#define SH_VEC_RETURN 0x0000000110074080 -#define SH_VEC_RETURN_MASK 0xffffffffffffffff -#define SH_VEC_RETURN_INIT 0x0000000000000000 - -/* SH_VEC_RETURN_ROUTE */ -/* Description: Route */ -#define SH_VEC_RETURN_ROUTE_SHFT 0 -#define SH_VEC_RETURN_ROUTE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_VEC_STATUS" */ -/* Vector Reply Message Status */ -/* ==================================================================== */ - -#define SH_VEC_STATUS 0x0000000110074100 -#define SH_VEC_STATUS_MASK 0xcfffffffffffffff -#define SH_VEC_STATUS_INIT 0x0000000000000000 - -/* SH_VEC_STATUS_TYPE */ -/* Description: Type */ -#define SH_VEC_STATUS_TYPE_SHFT 0 -#define SH_VEC_STATUS_TYPE_MASK 0x0000000000000007 - -/* SH_VEC_STATUS_ADDRESS */ -/* Description: Address */ -#define SH_VEC_STATUS_ADDRESS_SHFT 3 -#define SH_VEC_STATUS_ADDRESS_MASK 0x00000007fffffff8 - -/* SH_VEC_STATUS_PIO_ID */ -/* Description: PIO ID */ -#define SH_VEC_STATUS_PIO_ID_SHFT 35 -#define SH_VEC_STATUS_PIO_ID_MASK 0x00003ff800000000 - -/* SH_VEC_STATUS_SOURCE */ -/* Description: Source */ -#define SH_VEC_STATUS_SOURCE_SHFT 46 -#define SH_VEC_STATUS_SOURCE_MASK 0x0fffc00000000000 - -/* SH_VEC_STATUS_OVERRUN */ -/* Description: Overrun */ -#define SH_VEC_STATUS_OVERRUN_SHFT 62 -#define SH_VEC_STATUS_OVERRUN_MASK 0x4000000000000000 - -/* SH_VEC_STATUS_STATUS_VALID */ -/* Description: Status_Valid */ -#define SH_VEC_STATUS_STATUS_VALID_SHFT 63 -#define SH_VEC_STATUS_STATUS_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_VEC_STATUS_ALIAS" */ -/* Vector Reply Message Status Alias */ -/* ==================================================================== */ - -#define SH_VEC_STATUS_ALIAS 0x0000000110074108 - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNT0_CONTROL" */ -/* Performance Counter 0 Control */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNT0_CONTROL 0x0000000110080000 -#define SH_PERFORMANCE_COUNT0_CONTROL_MASK 0x000000000007ffff -#define SH_PERFORMANCE_COUNT0_CONTROL_INIT 0x000000000000b8b8 - -/* SH_PERFORMANCE_COUNT0_CONTROL_UP_STIMULUS */ -/* Description: Counter 0 up stimulus */ -#define SH_PERFORMANCE_COUNT0_CONTROL_UP_STIMULUS_SHFT 0 -#define SH_PERFORMANCE_COUNT0_CONTROL_UP_STIMULUS_MASK 0x000000000000001f - -/* SH_PERFORMANCE_COUNT0_CONTROL_UP_EVENT */ -/* Description: Counter 0 up event select (1-greater than, 0-equal) */ -#define SH_PERFORMANCE_COUNT0_CONTROL_UP_EVENT_SHFT 5 -#define SH_PERFORMANCE_COUNT0_CONTROL_UP_EVENT_MASK 0x0000000000000020 - -/* SH_PERFORMANCE_COUNT0_CONTROL_UP_POLARITY */ -/* Description: Counter 0 up polarity select (1-negative edge, 0-po */ -/* sitive edge) */ -#define SH_PERFORMANCE_COUNT0_CONTROL_UP_POLARITY_SHFT 6 -#define SH_PERFORMANCE_COUNT0_CONTROL_UP_POLARITY_MASK 0x0000000000000040 - -/* SH_PERFORMANCE_COUNT0_CONTROL_UP_MODE */ -/* Description: Counter 0 up mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT0_CONTROL_UP_MODE_SHFT 7 -#define SH_PERFORMANCE_COUNT0_CONTROL_UP_MODE_MASK 0x0000000000000080 - -/* SH_PERFORMANCE_COUNT0_CONTROL_DN_STIMULUS */ -/* Description: Counter 0 down stimulus */ -#define SH_PERFORMANCE_COUNT0_CONTROL_DN_STIMULUS_SHFT 8 -#define SH_PERFORMANCE_COUNT0_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00 - -/* SH_PERFORMANCE_COUNT0_CONTROL_DN_EVENT */ -/* Description: Counter 0 down event select (1-greater than, 0-equa */ -#define SH_PERFORMANCE_COUNT0_CONTROL_DN_EVENT_SHFT 13 -#define SH_PERFORMANCE_COUNT0_CONTROL_DN_EVENT_MASK 0x0000000000002000 - -/* SH_PERFORMANCE_COUNT0_CONTROL_DN_POLARITY */ -/* Description: Counter 0 down polarity select (1-negative edge, 0- */ -/* positive edge) */ -#define SH_PERFORMANCE_COUNT0_CONTROL_DN_POLARITY_SHFT 14 -#define SH_PERFORMANCE_COUNT0_CONTROL_DN_POLARITY_MASK 0x0000000000004000 - -/* SH_PERFORMANCE_COUNT0_CONTROL_DN_MODE */ -/* Description: Counter 0 down mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT0_CONTROL_DN_MODE_SHFT 15 -#define SH_PERFORMANCE_COUNT0_CONTROL_DN_MODE_MASK 0x0000000000008000 - -/* SH_PERFORMANCE_COUNT0_CONTROL_INC_ENABLE */ -/* Description: Counter 0 enable increment */ -#define SH_PERFORMANCE_COUNT0_CONTROL_INC_ENABLE_SHFT 16 -#define SH_PERFORMANCE_COUNT0_CONTROL_INC_ENABLE_MASK 0x0000000000010000 - -/* SH_PERFORMANCE_COUNT0_CONTROL_DEC_ENABLE */ -/* Description: Counter 0 enable decrement */ -#define SH_PERFORMANCE_COUNT0_CONTROL_DEC_ENABLE_SHFT 17 -#define SH_PERFORMANCE_COUNT0_CONTROL_DEC_ENABLE_MASK 0x0000000000020000 - -/* SH_PERFORMANCE_COUNT0_CONTROL_PEAK_DET_ENABLE */ -/* Description: Counter 0 enable peak detection */ -#define SH_PERFORMANCE_COUNT0_CONTROL_PEAK_DET_ENABLE_SHFT 18 -#define SH_PERFORMANCE_COUNT0_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000 - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNT1_CONTROL" */ -/* Performance Counter 1 Control */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNT1_CONTROL 0x0000000110090000 -#define SH_PERFORMANCE_COUNT1_CONTROL_MASK 0x000000000007ffff -#define SH_PERFORMANCE_COUNT1_CONTROL_INIT 0x000000000000b8b8 - -/* SH_PERFORMANCE_COUNT1_CONTROL_UP_STIMULUS */ -/* Description: Counter 1 up stimulus */ -#define SH_PERFORMANCE_COUNT1_CONTROL_UP_STIMULUS_SHFT 0 -#define SH_PERFORMANCE_COUNT1_CONTROL_UP_STIMULUS_MASK 0x000000000000001f - -/* SH_PERFORMANCE_COUNT1_CONTROL_UP_EVENT */ -/* Description: Counter 1 up event select (1-greater than, 0-equal) */ -#define SH_PERFORMANCE_COUNT1_CONTROL_UP_EVENT_SHFT 5 -#define SH_PERFORMANCE_COUNT1_CONTROL_UP_EVENT_MASK 0x0000000000000020 - -/* SH_PERFORMANCE_COUNT1_CONTROL_UP_POLARITY */ -/* Description: Counter 1 up polarity select (1-negative edge, 0-po */ -/* sitive edge) */ -#define SH_PERFORMANCE_COUNT1_CONTROL_UP_POLARITY_SHFT 6 -#define SH_PERFORMANCE_COUNT1_CONTROL_UP_POLARITY_MASK 0x0000000000000040 - -/* SH_PERFORMANCE_COUNT1_CONTROL_UP_MODE */ -/* Description: Counter 1 up mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT1_CONTROL_UP_MODE_SHFT 7 -#define SH_PERFORMANCE_COUNT1_CONTROL_UP_MODE_MASK 0x0000000000000080 - -/* SH_PERFORMANCE_COUNT1_CONTROL_DN_STIMULUS */ -/* Description: Counter 1 down stimulus */ -#define SH_PERFORMANCE_COUNT1_CONTROL_DN_STIMULUS_SHFT 8 -#define SH_PERFORMANCE_COUNT1_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00 - -/* SH_PERFORMANCE_COUNT1_CONTROL_DN_EVENT */ -/* Description: Counter 1 down event select (1-greater than, 0-equa */ -#define SH_PERFORMANCE_COUNT1_CONTROL_DN_EVENT_SHFT 13 -#define SH_PERFORMANCE_COUNT1_CONTROL_DN_EVENT_MASK 0x0000000000002000 - -/* SH_PERFORMANCE_COUNT1_CONTROL_DN_POLARITY */ -/* Description: Counter 1 down polarity select (1-negative edge, 0- */ -/* positive edge) */ -#define SH_PERFORMANCE_COUNT1_CONTROL_DN_POLARITY_SHFT 14 -#define SH_PERFORMANCE_COUNT1_CONTROL_DN_POLARITY_MASK 0x0000000000004000 - -/* SH_PERFORMANCE_COUNT1_CONTROL_DN_MODE */ -/* Description: Counter 1 down mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT1_CONTROL_DN_MODE_SHFT 15 -#define SH_PERFORMANCE_COUNT1_CONTROL_DN_MODE_MASK 0x0000000000008000 - -/* SH_PERFORMANCE_COUNT1_CONTROL_INC_ENABLE */ -/* Description: Counter 1 enable increment */ -#define SH_PERFORMANCE_COUNT1_CONTROL_INC_ENABLE_SHFT 16 -#define SH_PERFORMANCE_COUNT1_CONTROL_INC_ENABLE_MASK 0x0000000000010000 - -/* SH_PERFORMANCE_COUNT1_CONTROL_DEC_ENABLE */ -/* Description: Counter 1 enable decrement */ -#define SH_PERFORMANCE_COUNT1_CONTROL_DEC_ENABLE_SHFT 17 -#define SH_PERFORMANCE_COUNT1_CONTROL_DEC_ENABLE_MASK 0x0000000000020000 - -/* SH_PERFORMANCE_COUNT1_CONTROL_PEAK_DET_ENABLE */ -/* Description: Counter 1 enable peak detection */ -#define SH_PERFORMANCE_COUNT1_CONTROL_PEAK_DET_ENABLE_SHFT 18 -#define SH_PERFORMANCE_COUNT1_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000 - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNT2_CONTROL" */ -/* Performance Counter 2 Control */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNT2_CONTROL 0x00000001100a0000 -#define SH_PERFORMANCE_COUNT2_CONTROL_MASK 0x000000000007ffff -#define SH_PERFORMANCE_COUNT2_CONTROL_INIT 0x000000000000b8b8 - -/* SH_PERFORMANCE_COUNT2_CONTROL_UP_STIMULUS */ -/* Description: Counter 2 up stimulus */ -#define SH_PERFORMANCE_COUNT2_CONTROL_UP_STIMULUS_SHFT 0 -#define SH_PERFORMANCE_COUNT2_CONTROL_UP_STIMULUS_MASK 0x000000000000001f - -/* SH_PERFORMANCE_COUNT2_CONTROL_UP_EVENT */ -/* Description: Counter 2 up event select (1-greater than, 0-equal) */ -#define SH_PERFORMANCE_COUNT2_CONTROL_UP_EVENT_SHFT 5 -#define SH_PERFORMANCE_COUNT2_CONTROL_UP_EVENT_MASK 0x0000000000000020 - -/* SH_PERFORMANCE_COUNT2_CONTROL_UP_POLARITY */ -/* Description: Counter 2 up polarity select (1-negative edge, 0-po */ -/* sitive edge) */ -#define SH_PERFORMANCE_COUNT2_CONTROL_UP_POLARITY_SHFT 6 -#define SH_PERFORMANCE_COUNT2_CONTROL_UP_POLARITY_MASK 0x0000000000000040 - -/* SH_PERFORMANCE_COUNT2_CONTROL_UP_MODE */ -/* Description: Counter 2 up mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT2_CONTROL_UP_MODE_SHFT 7 -#define SH_PERFORMANCE_COUNT2_CONTROL_UP_MODE_MASK 0x0000000000000080 - -/* SH_PERFORMANCE_COUNT2_CONTROL_DN_STIMULUS */ -/* Description: Counter 2 down stimulus */ -#define SH_PERFORMANCE_COUNT2_CONTROL_DN_STIMULUS_SHFT 8 -#define SH_PERFORMANCE_COUNT2_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00 - -/* SH_PERFORMANCE_COUNT2_CONTROL_DN_EVENT */ -/* Description: Counter 2 down event select (1-greater than, 0-equa */ -#define SH_PERFORMANCE_COUNT2_CONTROL_DN_EVENT_SHFT 13 -#define SH_PERFORMANCE_COUNT2_CONTROL_DN_EVENT_MASK 0x0000000000002000 - -/* SH_PERFORMANCE_COUNT2_CONTROL_DN_POLARITY */ -/* Description: Counter 2 down polarity select (1-negative edge, 0- */ -/* positive edge) */ -#define SH_PERFORMANCE_COUNT2_CONTROL_DN_POLARITY_SHFT 14 -#define SH_PERFORMANCE_COUNT2_CONTROL_DN_POLARITY_MASK 0x0000000000004000 - -/* SH_PERFORMANCE_COUNT2_CONTROL_DN_MODE */ -/* Description: Counter 2 down mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT2_CONTROL_DN_MODE_SHFT 15 -#define SH_PERFORMANCE_COUNT2_CONTROL_DN_MODE_MASK 0x0000000000008000 - -/* SH_PERFORMANCE_COUNT2_CONTROL_INC_ENABLE */ -/* Description: Counter 2 enable increment */ -#define SH_PERFORMANCE_COUNT2_CONTROL_INC_ENABLE_SHFT 16 -#define SH_PERFORMANCE_COUNT2_CONTROL_INC_ENABLE_MASK 0x0000000000010000 - -/* SH_PERFORMANCE_COUNT2_CONTROL_DEC_ENABLE */ -/* Description: Counter 2 enable decrement */ -#define SH_PERFORMANCE_COUNT2_CONTROL_DEC_ENABLE_SHFT 17 -#define SH_PERFORMANCE_COUNT2_CONTROL_DEC_ENABLE_MASK 0x0000000000020000 - -/* SH_PERFORMANCE_COUNT2_CONTROL_PEAK_DET_ENABLE */ -/* Description: Counter 2 enable peak detection */ -#define SH_PERFORMANCE_COUNT2_CONTROL_PEAK_DET_ENABLE_SHFT 18 -#define SH_PERFORMANCE_COUNT2_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000 - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNT3_CONTROL" */ -/* Performance Counter 3 Control */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNT3_CONTROL 0x00000001100b0000 -#define SH_PERFORMANCE_COUNT3_CONTROL_MASK 0x000000000007ffff -#define SH_PERFORMANCE_COUNT3_CONTROL_INIT 0x000000000000b8b8 - -/* SH_PERFORMANCE_COUNT3_CONTROL_UP_STIMULUS */ -/* Description: Counter 3 up stimulus */ -#define SH_PERFORMANCE_COUNT3_CONTROL_UP_STIMULUS_SHFT 0 -#define SH_PERFORMANCE_COUNT3_CONTROL_UP_STIMULUS_MASK 0x000000000000001f - -/* SH_PERFORMANCE_COUNT3_CONTROL_UP_EVENT */ -/* Description: Counter 3 up event select (1-greater than, 0-equal) */ -#define SH_PERFORMANCE_COUNT3_CONTROL_UP_EVENT_SHFT 5 -#define SH_PERFORMANCE_COUNT3_CONTROL_UP_EVENT_MASK 0x0000000000000020 - -/* SH_PERFORMANCE_COUNT3_CONTROL_UP_POLARITY */ -/* Description: Counter 3 up polarity select (1-negative edge, 0-po */ -/* sitive edge) */ -#define SH_PERFORMANCE_COUNT3_CONTROL_UP_POLARITY_SHFT 6 -#define SH_PERFORMANCE_COUNT3_CONTROL_UP_POLARITY_MASK 0x0000000000000040 - -/* SH_PERFORMANCE_COUNT3_CONTROL_UP_MODE */ -/* Description: Counter 3 up mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT3_CONTROL_UP_MODE_SHFT 7 -#define SH_PERFORMANCE_COUNT3_CONTROL_UP_MODE_MASK 0x0000000000000080 - -/* SH_PERFORMANCE_COUNT3_CONTROL_DN_STIMULUS */ -/* Description: Counter 3 down stimulus */ -#define SH_PERFORMANCE_COUNT3_CONTROL_DN_STIMULUS_SHFT 8 -#define SH_PERFORMANCE_COUNT3_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00 - -/* SH_PERFORMANCE_COUNT3_CONTROL_DN_EVENT */ -/* Description: Counter 3 down event select (1-greater than, 0-equa */ -#define SH_PERFORMANCE_COUNT3_CONTROL_DN_EVENT_SHFT 13 -#define SH_PERFORMANCE_COUNT3_CONTROL_DN_EVENT_MASK 0x0000000000002000 - -/* SH_PERFORMANCE_COUNT3_CONTROL_DN_POLARITY */ -/* Description: Counter 3 down polarity select (1-negative edge, 0- */ -/* positive edge) */ -#define SH_PERFORMANCE_COUNT3_CONTROL_DN_POLARITY_SHFT 14 -#define SH_PERFORMANCE_COUNT3_CONTROL_DN_POLARITY_MASK 0x0000000000004000 - -/* SH_PERFORMANCE_COUNT3_CONTROL_DN_MODE */ -/* Description: Counter 3 down mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT3_CONTROL_DN_MODE_SHFT 15 -#define SH_PERFORMANCE_COUNT3_CONTROL_DN_MODE_MASK 0x0000000000008000 - -/* SH_PERFORMANCE_COUNT3_CONTROL_INC_ENABLE */ -/* Description: Counter 3 enable increment */ -#define SH_PERFORMANCE_COUNT3_CONTROL_INC_ENABLE_SHFT 16 -#define SH_PERFORMANCE_COUNT3_CONTROL_INC_ENABLE_MASK 0x0000000000010000 - -/* SH_PERFORMANCE_COUNT3_CONTROL_DEC_ENABLE */ -/* Description: Counter 3 enable decrement */ -#define SH_PERFORMANCE_COUNT3_CONTROL_DEC_ENABLE_SHFT 17 -#define SH_PERFORMANCE_COUNT3_CONTROL_DEC_ENABLE_MASK 0x0000000000020000 - -/* SH_PERFORMANCE_COUNT3_CONTROL_PEAK_DET_ENABLE */ -/* Description: Counter 3 enable peak detection */ -#define SH_PERFORMANCE_COUNT3_CONTROL_PEAK_DET_ENABLE_SHFT 18 -#define SH_PERFORMANCE_COUNT3_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000 - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNT4_CONTROL" */ -/* Performance Counter 4 Control */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNT4_CONTROL 0x00000001100c0000 -#define SH_PERFORMANCE_COUNT4_CONTROL_MASK 0x000000000007ffff -#define SH_PERFORMANCE_COUNT4_CONTROL_INIT 0x000000000000b8b8 - -/* SH_PERFORMANCE_COUNT4_CONTROL_UP_STIMULUS */ -/* Description: Counter 4 up stimulus */ -#define SH_PERFORMANCE_COUNT4_CONTROL_UP_STIMULUS_SHFT 0 -#define SH_PERFORMANCE_COUNT4_CONTROL_UP_STIMULUS_MASK 0x000000000000001f - -/* SH_PERFORMANCE_COUNT4_CONTROL_UP_EVENT */ -/* Description: Counter 4 up event select (1-greater than, 0-equal) */ -#define SH_PERFORMANCE_COUNT4_CONTROL_UP_EVENT_SHFT 5 -#define SH_PERFORMANCE_COUNT4_CONTROL_UP_EVENT_MASK 0x0000000000000020 - -/* SH_PERFORMANCE_COUNT4_CONTROL_UP_POLARITY */ -/* Description: Counter 4 up polarity select (1-negative edge, 0-po */ -/* sitive edge) */ -#define SH_PERFORMANCE_COUNT4_CONTROL_UP_POLARITY_SHFT 6 -#define SH_PERFORMANCE_COUNT4_CONTROL_UP_POLARITY_MASK 0x0000000000000040 - -/* SH_PERFORMANCE_COUNT4_CONTROL_UP_MODE */ -/* Description: Counter 4 up mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT4_CONTROL_UP_MODE_SHFT 7 -#define SH_PERFORMANCE_COUNT4_CONTROL_UP_MODE_MASK 0x0000000000000080 - -/* SH_PERFORMANCE_COUNT4_CONTROL_DN_STIMULUS */ -/* Description: Counter 4 down stimulus */ -#define SH_PERFORMANCE_COUNT4_CONTROL_DN_STIMULUS_SHFT 8 -#define SH_PERFORMANCE_COUNT4_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00 - -/* SH_PERFORMANCE_COUNT4_CONTROL_DN_EVENT */ -/* Description: Counter 4 down event select (1-greater than, 0-equa */ -#define SH_PERFORMANCE_COUNT4_CONTROL_DN_EVENT_SHFT 13 -#define SH_PERFORMANCE_COUNT4_CONTROL_DN_EVENT_MASK 0x0000000000002000 - -/* SH_PERFORMANCE_COUNT4_CONTROL_DN_POLARITY */ -/* Description: Counter 4 down polarity select (1-negative edge, 0- */ -/* positive edge) */ -#define SH_PERFORMANCE_COUNT4_CONTROL_DN_POLARITY_SHFT 14 -#define SH_PERFORMANCE_COUNT4_CONTROL_DN_POLARITY_MASK 0x0000000000004000 - -/* SH_PERFORMANCE_COUNT4_CONTROL_DN_MODE */ -/* Description: Counter 4 down mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT4_CONTROL_DN_MODE_SHFT 15 -#define SH_PERFORMANCE_COUNT4_CONTROL_DN_MODE_MASK 0x0000000000008000 - -/* SH_PERFORMANCE_COUNT4_CONTROL_INC_ENABLE */ -/* Description: Counter 4 enable increment */ -#define SH_PERFORMANCE_COUNT4_CONTROL_INC_ENABLE_SHFT 16 -#define SH_PERFORMANCE_COUNT4_CONTROL_INC_ENABLE_MASK 0x0000000000010000 - -/* SH_PERFORMANCE_COUNT4_CONTROL_DEC_ENABLE */ -/* Description: Counter 4 enable decrement */ -#define SH_PERFORMANCE_COUNT4_CONTROL_DEC_ENABLE_SHFT 17 -#define SH_PERFORMANCE_COUNT4_CONTROL_DEC_ENABLE_MASK 0x0000000000020000 - -/* SH_PERFORMANCE_COUNT4_CONTROL_PEAK_DET_ENABLE */ -/* Description: Counter 4 enable peak detection */ -#define SH_PERFORMANCE_COUNT4_CONTROL_PEAK_DET_ENABLE_SHFT 18 -#define SH_PERFORMANCE_COUNT4_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000 - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNT5_CONTROL" */ -/* Performance Counter 5 Control */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNT5_CONTROL 0x00000001100d0000 -#define SH_PERFORMANCE_COUNT5_CONTROL_MASK 0x000000000007ffff -#define SH_PERFORMANCE_COUNT5_CONTROL_INIT 0x000000000000b8b8 - -/* SH_PERFORMANCE_COUNT5_CONTROL_UP_STIMULUS */ -/* Description: Counter 5 up stimulus */ -#define SH_PERFORMANCE_COUNT5_CONTROL_UP_STIMULUS_SHFT 0 -#define SH_PERFORMANCE_COUNT5_CONTROL_UP_STIMULUS_MASK 0x000000000000001f - -/* SH_PERFORMANCE_COUNT5_CONTROL_UP_EVENT */ -/* Description: Counter 5 up event select (1-greater than, 0-equal) */ -#define SH_PERFORMANCE_COUNT5_CONTROL_UP_EVENT_SHFT 5 -#define SH_PERFORMANCE_COUNT5_CONTROL_UP_EVENT_MASK 0x0000000000000020 - -/* SH_PERFORMANCE_COUNT5_CONTROL_UP_POLARITY */ -/* Description: Counter 5 up polarity select (1-negative edge, 0-po */ -/* sitive edge) */ -#define SH_PERFORMANCE_COUNT5_CONTROL_UP_POLARITY_SHFT 6 -#define SH_PERFORMANCE_COUNT5_CONTROL_UP_POLARITY_MASK 0x0000000000000040 - -/* SH_PERFORMANCE_COUNT5_CONTROL_UP_MODE */ -/* Description: Counter 5 up mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT5_CONTROL_UP_MODE_SHFT 7 -#define SH_PERFORMANCE_COUNT5_CONTROL_UP_MODE_MASK 0x0000000000000080 - -/* SH_PERFORMANCE_COUNT5_CONTROL_DN_STIMULUS */ -/* Description: Counter 5 down stimulus */ -#define SH_PERFORMANCE_COUNT5_CONTROL_DN_STIMULUS_SHFT 8 -#define SH_PERFORMANCE_COUNT5_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00 - -/* SH_PERFORMANCE_COUNT5_CONTROL_DN_EVENT */ -/* Description: Counter 5 down event select (1-greater than, 0-equa */ -#define SH_PERFORMANCE_COUNT5_CONTROL_DN_EVENT_SHFT 13 -#define SH_PERFORMANCE_COUNT5_CONTROL_DN_EVENT_MASK 0x0000000000002000 - -/* SH_PERFORMANCE_COUNT5_CONTROL_DN_POLARITY */ -/* Description: Counter 5 down polarity select (1-negative edge, 0- */ -/* positive edge) */ -#define SH_PERFORMANCE_COUNT5_CONTROL_DN_POLARITY_SHFT 14 -#define SH_PERFORMANCE_COUNT5_CONTROL_DN_POLARITY_MASK 0x0000000000004000 - -/* SH_PERFORMANCE_COUNT5_CONTROL_DN_MODE */ -/* Description: Counter 5 down mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT5_CONTROL_DN_MODE_SHFT 15 -#define SH_PERFORMANCE_COUNT5_CONTROL_DN_MODE_MASK 0x0000000000008000 - -/* SH_PERFORMANCE_COUNT5_CONTROL_INC_ENABLE */ -/* Description: Counter 5 enable increment */ -#define SH_PERFORMANCE_COUNT5_CONTROL_INC_ENABLE_SHFT 16 -#define SH_PERFORMANCE_COUNT5_CONTROL_INC_ENABLE_MASK 0x0000000000010000 - -/* SH_PERFORMANCE_COUNT5_CONTROL_DEC_ENABLE */ -/* Description: Counter 5 enable decrement */ -#define SH_PERFORMANCE_COUNT5_CONTROL_DEC_ENABLE_SHFT 17 -#define SH_PERFORMANCE_COUNT5_CONTROL_DEC_ENABLE_MASK 0x0000000000020000 - -/* SH_PERFORMANCE_COUNT5_CONTROL_PEAK_DET_ENABLE */ -/* Description: Counter 5 enable peak detection */ -#define SH_PERFORMANCE_COUNT5_CONTROL_PEAK_DET_ENABLE_SHFT 18 -#define SH_PERFORMANCE_COUNT5_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000 - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNT6_CONTROL" */ -/* Performance Counter 6 Control */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNT6_CONTROL 0x00000001100e0000 -#define SH_PERFORMANCE_COUNT6_CONTROL_MASK 0x000000000007ffff -#define SH_PERFORMANCE_COUNT6_CONTROL_INIT 0x000000000000b8b8 - -/* SH_PERFORMANCE_COUNT6_CONTROL_UP_STIMULUS */ -/* Description: Counter 6 up stimulus */ -#define SH_PERFORMANCE_COUNT6_CONTROL_UP_STIMULUS_SHFT 0 -#define SH_PERFORMANCE_COUNT6_CONTROL_UP_STIMULUS_MASK 0x000000000000001f - -/* SH_PERFORMANCE_COUNT6_CONTROL_UP_EVENT */ -/* Description: Counter 6 up event select (1-greater than, 0-equal) */ -#define SH_PERFORMANCE_COUNT6_CONTROL_UP_EVENT_SHFT 5 -#define SH_PERFORMANCE_COUNT6_CONTROL_UP_EVENT_MASK 0x0000000000000020 - -/* SH_PERFORMANCE_COUNT6_CONTROL_UP_POLARITY */ -/* Description: Counter 6 up polarity select (1-negative edge, 0-po */ -/* sitive edge) */ -#define SH_PERFORMANCE_COUNT6_CONTROL_UP_POLARITY_SHFT 6 -#define SH_PERFORMANCE_COUNT6_CONTROL_UP_POLARITY_MASK 0x0000000000000040 - -/* SH_PERFORMANCE_COUNT6_CONTROL_UP_MODE */ -/* Description: Counter 6 up mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT6_CONTROL_UP_MODE_SHFT 7 -#define SH_PERFORMANCE_COUNT6_CONTROL_UP_MODE_MASK 0x0000000000000080 - -/* SH_PERFORMANCE_COUNT6_CONTROL_DN_STIMULUS */ -/* Description: Counter 6 down stimulus */ -#define SH_PERFORMANCE_COUNT6_CONTROL_DN_STIMULUS_SHFT 8 -#define SH_PERFORMANCE_COUNT6_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00 - -/* SH_PERFORMANCE_COUNT6_CONTROL_DN_EVENT */ -/* Description: Counter 6 down event select (1-greater than, 0-equa */ -#define SH_PERFORMANCE_COUNT6_CONTROL_DN_EVENT_SHFT 13 -#define SH_PERFORMANCE_COUNT6_CONTROL_DN_EVENT_MASK 0x0000000000002000 - -/* SH_PERFORMANCE_COUNT6_CONTROL_DN_POLARITY */ -/* Description: Counter 6 down polarity select (1-negative edge, 0- */ -/* positive edge) */ -#define SH_PERFORMANCE_COUNT6_CONTROL_DN_POLARITY_SHFT 14 -#define SH_PERFORMANCE_COUNT6_CONTROL_DN_POLARITY_MASK 0x0000000000004000 - -/* SH_PERFORMANCE_COUNT6_CONTROL_DN_MODE */ -/* Description: Counter 6 down mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT6_CONTROL_DN_MODE_SHFT 15 -#define SH_PERFORMANCE_COUNT6_CONTROL_DN_MODE_MASK 0x0000000000008000 - -/* SH_PERFORMANCE_COUNT6_CONTROL_INC_ENABLE */ -/* Description: Counter 6 enable increment */ -#define SH_PERFORMANCE_COUNT6_CONTROL_INC_ENABLE_SHFT 16 -#define SH_PERFORMANCE_COUNT6_CONTROL_INC_ENABLE_MASK 0x0000000000010000 - -/* SH_PERFORMANCE_COUNT6_CONTROL_DEC_ENABLE */ -/* Description: Counter 6 enable decrement */ -#define SH_PERFORMANCE_COUNT6_CONTROL_DEC_ENABLE_SHFT 17 -#define SH_PERFORMANCE_COUNT6_CONTROL_DEC_ENABLE_MASK 0x0000000000020000 - -/* SH_PERFORMANCE_COUNT6_CONTROL_PEAK_DET_ENABLE */ -/* Description: Counter 6 enable peak detection */ -#define SH_PERFORMANCE_COUNT6_CONTROL_PEAK_DET_ENABLE_SHFT 18 -#define SH_PERFORMANCE_COUNT6_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000 - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNT7_CONTROL" */ -/* Performance Counter 7 Control */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNT7_CONTROL 0x00000001100f0000 -#define SH_PERFORMANCE_COUNT7_CONTROL_MASK 0x000000000007ffff -#define SH_PERFORMANCE_COUNT7_CONTROL_INIT 0x000000000000b8b8 - -/* SH_PERFORMANCE_COUNT7_CONTROL_UP_STIMULUS */ -/* Description: Counter 7 up stimulus */ -#define SH_PERFORMANCE_COUNT7_CONTROL_UP_STIMULUS_SHFT 0 -#define SH_PERFORMANCE_COUNT7_CONTROL_UP_STIMULUS_MASK 0x000000000000001f - -/* SH_PERFORMANCE_COUNT7_CONTROL_UP_EVENT */ -/* Description: Counter 7 up event select (1-greater than, 0-equal) */ -#define SH_PERFORMANCE_COUNT7_CONTROL_UP_EVENT_SHFT 5 -#define SH_PERFORMANCE_COUNT7_CONTROL_UP_EVENT_MASK 0x0000000000000020 - -/* SH_PERFORMANCE_COUNT7_CONTROL_UP_POLARITY */ -/* Description: Counter 7 up polarity select (1-negative edge, 0-po */ -/* sitive edge) */ -#define SH_PERFORMANCE_COUNT7_CONTROL_UP_POLARITY_SHFT 6 -#define SH_PERFORMANCE_COUNT7_CONTROL_UP_POLARITY_MASK 0x0000000000000040 - -/* SH_PERFORMANCE_COUNT7_CONTROL_UP_MODE */ -/* Description: Counter 7 up mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT7_CONTROL_UP_MODE_SHFT 7 -#define SH_PERFORMANCE_COUNT7_CONTROL_UP_MODE_MASK 0x0000000000000080 - -/* SH_PERFORMANCE_COUNT7_CONTROL_DN_STIMULUS */ -/* Description: Counter 7 down stimulus */ -#define SH_PERFORMANCE_COUNT7_CONTROL_DN_STIMULUS_SHFT 8 -#define SH_PERFORMANCE_COUNT7_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00 - -/* SH_PERFORMANCE_COUNT7_CONTROL_DN_EVENT */ -/* Description: Counter 7 down event select (1-greater than, 0-equa */ -#define SH_PERFORMANCE_COUNT7_CONTROL_DN_EVENT_SHFT 13 -#define SH_PERFORMANCE_COUNT7_CONTROL_DN_EVENT_MASK 0x0000000000002000 - -/* SH_PERFORMANCE_COUNT7_CONTROL_DN_POLARITY */ -/* Description: Counter 7 down polarity select (1-negative edge, 0- */ -/* positive edge) */ -#define SH_PERFORMANCE_COUNT7_CONTROL_DN_POLARITY_SHFT 14 -#define SH_PERFORMANCE_COUNT7_CONTROL_DN_POLARITY_MASK 0x0000000000004000 - -/* SH_PERFORMANCE_COUNT7_CONTROL_DN_MODE */ -/* Description: Counter 7 down mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT7_CONTROL_DN_MODE_SHFT 15 -#define SH_PERFORMANCE_COUNT7_CONTROL_DN_MODE_MASK 0x0000000000008000 - -/* SH_PERFORMANCE_COUNT7_CONTROL_INC_ENABLE */ -/* Description: Counter 7 enable increment */ -#define SH_PERFORMANCE_COUNT7_CONTROL_INC_ENABLE_SHFT 16 -#define SH_PERFORMANCE_COUNT7_CONTROL_INC_ENABLE_MASK 0x0000000000010000 - -/* SH_PERFORMANCE_COUNT7_CONTROL_DEC_ENABLE */ -/* Description: Counter 7 enable decrement */ -#define SH_PERFORMANCE_COUNT7_CONTROL_DEC_ENABLE_SHFT 17 -#define SH_PERFORMANCE_COUNT7_CONTROL_DEC_ENABLE_MASK 0x0000000000020000 - -/* SH_PERFORMANCE_COUNT7_CONTROL_PEAK_DET_ENABLE */ -/* Description: Counter 7 enable peak detection */ -#define SH_PERFORMANCE_COUNT7_CONTROL_PEAK_DET_ENABLE_SHFT 18 -#define SH_PERFORMANCE_COUNT7_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000 - -/* ==================================================================== */ -/* Register "SH_PROFILE_DN_CONTROL" */ -/* Profile Counter Down Control */ -/* ==================================================================== */ - -#define SH_PROFILE_DN_CONTROL 0x0000000110100000 -#define SH_PROFILE_DN_CONTROL_MASK 0x00000000000000ff -#define SH_PROFILE_DN_CONTROL_INIT 0x00000000000000b8 - -/* SH_PROFILE_DN_CONTROL_STIMULUS */ -/* Description: Counter stimulus */ -#define SH_PROFILE_DN_CONTROL_STIMULUS_SHFT 0 -#define SH_PROFILE_DN_CONTROL_STIMULUS_MASK 0x000000000000001f - -/* SH_PROFILE_DN_CONTROL_EVENT */ -/* Description: Counter event select (1-greater than, 0-equal) */ -#define SH_PROFILE_DN_CONTROL_EVENT_SHFT 5 -#define SH_PROFILE_DN_CONTROL_EVENT_MASK 0x0000000000000020 - -/* SH_PROFILE_DN_CONTROL_POLARITY */ -/* Description: Counter polarity select (1-negative edge, 0-positiv */ -/* e edge) */ -#define SH_PROFILE_DN_CONTROL_POLARITY_SHFT 6 -#define SH_PROFILE_DN_CONTROL_POLARITY_MASK 0x0000000000000040 - -/* SH_PROFILE_DN_CONTROL_MODE */ -/* Description: Counter mode select (1-internal, 0-external) */ -#define SH_PROFILE_DN_CONTROL_MODE_SHFT 7 -#define SH_PROFILE_DN_CONTROL_MODE_MASK 0x0000000000000080 - -/* ==================================================================== */ -/* Register "SH_PROFILE_PEAK_CONTROL" */ -/* Profile Counter Peak Control */ -/* ==================================================================== */ - -#define SH_PROFILE_PEAK_CONTROL 0x0000000110100080 -#define SH_PROFILE_PEAK_CONTROL_MASK 0x0000000000000068 -#define SH_PROFILE_PEAK_CONTROL_INIT 0x0000000000000060 - -/* SH_PROFILE_PEAK_CONTROL_STIMULUS */ -/* Description: Counter stimulus */ -#define SH_PROFILE_PEAK_CONTROL_STIMULUS_SHFT 3 -#define SH_PROFILE_PEAK_CONTROL_STIMULUS_MASK 0x0000000000000008 - -/* SH_PROFILE_PEAK_CONTROL_EVENT */ -/* Description: Counter event select (0-greater than, 1-equal) */ -#define SH_PROFILE_PEAK_CONTROL_EVENT_SHFT 5 -#define SH_PROFILE_PEAK_CONTROL_EVENT_MASK 0x0000000000000020 - -/* SH_PROFILE_PEAK_CONTROL_POLARITY */ -/* Description: Counter polarity select (0-negative edge, 1-positiv */ -/* e edge) */ -#define SH_PROFILE_PEAK_CONTROL_POLARITY_SHFT 6 -#define SH_PROFILE_PEAK_CONTROL_POLARITY_MASK 0x0000000000000040 - -/* ==================================================================== */ -/* Register "SH_PROFILE_RANGE" */ -/* Profile Counter Range */ -/* ==================================================================== */ - -#define SH_PROFILE_RANGE 0x0000000110100100 -#define SH_PROFILE_RANGE_MASK 0xffffffffffffffff -#define SH_PROFILE_RANGE_INIT 0x0000000000000000 - -/* SH_PROFILE_RANGE_RANGE0 */ -/* Description: Profiling range 0 */ -#define SH_PROFILE_RANGE_RANGE0_SHFT 0 -#define SH_PROFILE_RANGE_RANGE0_MASK 0x00000000000000ff - -/* SH_PROFILE_RANGE_RANGE1 */ -/* Description: Profiling range 1 */ -#define SH_PROFILE_RANGE_RANGE1_SHFT 8 -#define SH_PROFILE_RANGE_RANGE1_MASK 0x000000000000ff00 - -/* SH_PROFILE_RANGE_RANGE2 */ -/* Description: Profiling range 2 */ -#define SH_PROFILE_RANGE_RANGE2_SHFT 16 -#define SH_PROFILE_RANGE_RANGE2_MASK 0x0000000000ff0000 - -/* SH_PROFILE_RANGE_RANGE3 */ -/* Description: Profiling range 3 */ -#define SH_PROFILE_RANGE_RANGE3_SHFT 24 -#define SH_PROFILE_RANGE_RANGE3_MASK 0x00000000ff000000 - -/* SH_PROFILE_RANGE_RANGE4 */ -/* Description: Profiling range 4 */ -#define SH_PROFILE_RANGE_RANGE4_SHFT 32 -#define SH_PROFILE_RANGE_RANGE4_MASK 0x000000ff00000000 - -/* SH_PROFILE_RANGE_RANGE5 */ -/* Description: Profiling range 5 */ -#define SH_PROFILE_RANGE_RANGE5_SHFT 40 -#define SH_PROFILE_RANGE_RANGE5_MASK 0x0000ff0000000000 - -/* SH_PROFILE_RANGE_RANGE6 */ -/* Description: Profiling range 6 */ -#define SH_PROFILE_RANGE_RANGE6_SHFT 48 -#define SH_PROFILE_RANGE_RANGE6_MASK 0x00ff000000000000 - -/* SH_PROFILE_RANGE_RANGE7 */ -/* Description: Profiling range 7 */ -#define SH_PROFILE_RANGE_RANGE7_SHFT 56 -#define SH_PROFILE_RANGE_RANGE7_MASK 0xff00000000000000 - -/* ==================================================================== */ -/* Register "SH_PROFILE_UP_CONTROL" */ -/* Profile Counter Up Control */ -/* ==================================================================== */ - -#define SH_PROFILE_UP_CONTROL 0x0000000110100180 -#define SH_PROFILE_UP_CONTROL_MASK 0x00000000000000ff -#define SH_PROFILE_UP_CONTROL_INIT 0x00000000000000b8 - -/* SH_PROFILE_UP_CONTROL_STIMULUS */ -/* Description: Counter stimulus */ -#define SH_PROFILE_UP_CONTROL_STIMULUS_SHFT 0 -#define SH_PROFILE_UP_CONTROL_STIMULUS_MASK 0x000000000000001f - -/* SH_PROFILE_UP_CONTROL_EVENT */ -/* Description: Counter event select (1-greater than, 0-equal) */ -#define SH_PROFILE_UP_CONTROL_EVENT_SHFT 5 -#define SH_PROFILE_UP_CONTROL_EVENT_MASK 0x0000000000000020 - -/* SH_PROFILE_UP_CONTROL_POLARITY */ -/* Description: Counter polarity select (1-negative edge, 0-positiv */ -/* e edge) */ -#define SH_PROFILE_UP_CONTROL_POLARITY_SHFT 6 -#define SH_PROFILE_UP_CONTROL_POLARITY_MASK 0x0000000000000040 - -/* SH_PROFILE_UP_CONTROL_MODE */ -/* Description: Counter mode select (1-internal, 0-external) */ -#define SH_PROFILE_UP_CONTROL_MODE_SHFT 7 -#define SH_PROFILE_UP_CONTROL_MODE_MASK 0x0000000000000080 - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNTER0" */ -/* Performance Counter 0 */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNTER0 0x0000000110110000 -#define SH_PERFORMANCE_COUNTER0_MASK 0x00000000ffffffff -#define SH_PERFORMANCE_COUNTER0_INIT 0x0000000000000000 - -/* SH_PERFORMANCE_COUNTER0_COUNT */ -/* Description: Counter 0 */ -#define SH_PERFORMANCE_COUNTER0_COUNT_SHFT 0 -#define SH_PERFORMANCE_COUNTER0_COUNT_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNTER1" */ -/* Performance Counter 1 */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNTER1 0x0000000110120000 -#define SH_PERFORMANCE_COUNTER1_MASK 0x00000000ffffffff -#define SH_PERFORMANCE_COUNTER1_INIT 0x0000000000000000 - -/* SH_PERFORMANCE_COUNTER1_COUNT */ -/* Description: Counter 1 */ -#define SH_PERFORMANCE_COUNTER1_COUNT_SHFT 0 -#define SH_PERFORMANCE_COUNTER1_COUNT_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNTER2" */ -/* Performance Counter 2 */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNTER2 0x0000000110130000 -#define SH_PERFORMANCE_COUNTER2_MASK 0x00000000ffffffff -#define SH_PERFORMANCE_COUNTER2_INIT 0x0000000000000000 - -/* SH_PERFORMANCE_COUNTER2_COUNT */ -/* Description: Counter 2 */ -#define SH_PERFORMANCE_COUNTER2_COUNT_SHFT 0 -#define SH_PERFORMANCE_COUNTER2_COUNT_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNTER3" */ -/* Performance Counter 3 */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNTER3 0x0000000110140000 -#define SH_PERFORMANCE_COUNTER3_MASK 0x00000000ffffffff -#define SH_PERFORMANCE_COUNTER3_INIT 0x0000000000000000 - -/* SH_PERFORMANCE_COUNTER3_COUNT */ -/* Description: Counter 3 */ -#define SH_PERFORMANCE_COUNTER3_COUNT_SHFT 0 -#define SH_PERFORMANCE_COUNTER3_COUNT_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNTER4" */ -/* Performance Counter 4 */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNTER4 0x0000000110150000 -#define SH_PERFORMANCE_COUNTER4_MASK 0x00000000ffffffff -#define SH_PERFORMANCE_COUNTER4_INIT 0x0000000000000000 - -/* SH_PERFORMANCE_COUNTER4_COUNT */ -/* Description: Counter 4 */ -#define SH_PERFORMANCE_COUNTER4_COUNT_SHFT 0 -#define SH_PERFORMANCE_COUNTER4_COUNT_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNTER5" */ -/* Performance Counter 5 */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNTER5 0x0000000110160000 -#define SH_PERFORMANCE_COUNTER5_MASK 0x00000000ffffffff -#define SH_PERFORMANCE_COUNTER5_INIT 0x0000000000000000 - -/* SH_PERFORMANCE_COUNTER5_COUNT */ -/* Description: Counter 5 */ -#define SH_PERFORMANCE_COUNTER5_COUNT_SHFT 0 -#define SH_PERFORMANCE_COUNTER5_COUNT_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNTER6" */ -/* Performance Counter 6 */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNTER6 0x0000000110170000 -#define SH_PERFORMANCE_COUNTER6_MASK 0x00000000ffffffff -#define SH_PERFORMANCE_COUNTER6_INIT 0x0000000000000000 - -/* SH_PERFORMANCE_COUNTER6_COUNT */ -/* Description: Counter 6 */ -#define SH_PERFORMANCE_COUNTER6_COUNT_SHFT 0 -#define SH_PERFORMANCE_COUNTER6_COUNT_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNTER7" */ -/* Performance Counter 7 */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNTER7 0x0000000110180000 -#define SH_PERFORMANCE_COUNTER7_MASK 0x00000000ffffffff -#define SH_PERFORMANCE_COUNTER7_INIT 0x0000000000000000 - -/* SH_PERFORMANCE_COUNTER7_COUNT */ -/* Description: Counter 7 */ -#define SH_PERFORMANCE_COUNTER7_COUNT_SHFT 0 -#define SH_PERFORMANCE_COUNTER7_COUNT_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_PROFILE_COUNTER" */ -/* Profile Counter */ -/* ==================================================================== */ - -#define SH_PROFILE_COUNTER 0x0000000110190000 -#define SH_PROFILE_COUNTER_MASK 0x00000000000000ff -#define SH_PROFILE_COUNTER_INIT 0x0000000000000000 - -/* SH_PROFILE_COUNTER_COUNTER */ -/* Description: Counter Value */ -#define SH_PROFILE_COUNTER_COUNTER_SHFT 0 -#define SH_PROFILE_COUNTER_COUNTER_MASK 0x00000000000000ff - -/* ==================================================================== */ -/* Register "SH_PROFILE_PEAK" */ -/* Profile Peak Counter */ -/* ==================================================================== */ - -#define SH_PROFILE_PEAK 0x0000000110190080 -#define SH_PROFILE_PEAK_MASK 0x00000000000000ff -#define SH_PROFILE_PEAK_INIT 0x0000000000000000 - -/* SH_PROFILE_PEAK_COUNTER */ -/* Description: Counter Value */ -#define SH_PROFILE_PEAK_COUNTER_SHFT 0 -#define SH_PROFILE_PEAK_COUNTER_MASK 0x00000000000000ff - -/* ==================================================================== */ -/* Register "SH_PTC_0" */ -/* Puge Translation Cache Message Configuration Information */ -/* ==================================================================== */ - -#define SH_PTC_0 0x00000001101a0000 -#define SH_PTC_0_MASK 0x80000000fffffffd -#define SH_PTC_0_INIT 0x0000000000000000 - -/* SH_PTC_0_A */ -/* Description: Type */ -#define SH_PTC_0_A_SHFT 0 -#define SH_PTC_0_A_MASK 0x0000000000000001 - -/* SH_PTC_0_PS */ -/* Description: Page Size */ -#define SH_PTC_0_PS_SHFT 2 -#define SH_PTC_0_PS_MASK 0x00000000000000fc - -/* SH_PTC_0_RID */ -/* Description: Region ID */ -#define SH_PTC_0_RID_SHFT 8 -#define SH_PTC_0_RID_MASK 0x00000000ffffff00 - -/* SH_PTC_0_START */ -/* Description: Start */ -#define SH_PTC_0_START_SHFT 63 -#define SH_PTC_0_START_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PTC_1" */ -/* Puge Translation Cache Message Configuration Information */ -/* ==================================================================== */ - -#define SH_PTC_1 0x00000001101a0080 -#define SH_PTC_1_MASK 0x9ffffffffffff000 -#define SH_PTC_1_INIT 0x0000000000000000 - -/* SH_PTC_1_VPN */ -/* Description: Virtual page number */ -#define SH_PTC_1_VPN_SHFT 12 -#define SH_PTC_1_VPN_MASK 0x1ffffffffffff000 - -/* SH_PTC_1_START */ -/* Description: PTC_1 Start */ -#define SH_PTC_1_START_SHFT 63 -#define SH_PTC_1_START_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PTC_PARMS" */ -/* PTC Time-out parmaeters */ -/* ==================================================================== */ - -#define SH_PTC_PARMS 0x00000001101a0100 -#define SH_PTC_PARMS_MASK 0x0000000fffffffff -#define SH_PTC_PARMS_INIT 0x00000007ffffffff - -/* SH_PTC_PARMS_PTC_TO_WRAP */ -/* Description: PTC time-out period */ -#define SH_PTC_PARMS_PTC_TO_WRAP_SHFT 0 -#define SH_PTC_PARMS_PTC_TO_WRAP_MASK 0x0000000000ffffff - -/* SH_PTC_PARMS_PTC_TO_VAL */ -/* Description: PTC time-out valid */ -#define SH_PTC_PARMS_PTC_TO_VAL_SHFT 24 -#define SH_PTC_PARMS_PTC_TO_VAL_MASK 0x0000000fff000000 - -/* ==================================================================== */ -/* Register "SH_INT_CMPA" */ -/* RTC Compare Value for Processor A */ -/* ==================================================================== */ - -#define SH_INT_CMPA 0x00000001101b0000 -#define SH_INT_CMPA_MASK 0x007fffffffffffff -#define SH_INT_CMPA_INIT 0x0000000000000000 - -/* SH_INT_CMPA_REAL_TIME_CMPA */ -/* Description: Real Time Clock Compare */ -#define SH_INT_CMPA_REAL_TIME_CMPA_SHFT 0 -#define SH_INT_CMPA_REAL_TIME_CMPA_MASK 0x007fffffffffffff - -/* ==================================================================== */ -/* Register "SH_INT_CMPB" */ -/* RTC Compare Value for Processor B */ -/* ==================================================================== */ - -#define SH_INT_CMPB 0x00000001101b0080 -#define SH_INT_CMPB_MASK 0x007fffffffffffff -#define SH_INT_CMPB_INIT 0x0000000000000000 - -/* SH_INT_CMPB_REAL_TIME_CMPB */ -/* Description: Real Time Clock Compare */ -#define SH_INT_CMPB_REAL_TIME_CMPB_SHFT 0 -#define SH_INT_CMPB_REAL_TIME_CMPB_MASK 0x007fffffffffffff - -/* ==================================================================== */ -/* Register "SH_INT_CMPC" */ -/* RTC Compare Value for Processor C */ -/* ==================================================================== */ - -#define SH_INT_CMPC 0x00000001101b0100 -#define SH_INT_CMPC_MASK 0x007fffffffffffff -#define SH_INT_CMPC_INIT 0x0000000000000000 - -/* SH_INT_CMPC_REAL_TIME_CMPC */ -/* Description: Real Time Clock Compare */ -#define SH_INT_CMPC_REAL_TIME_CMPC_SHFT 0 -#define SH_INT_CMPC_REAL_TIME_CMPC_MASK 0x007fffffffffffff - -/* ==================================================================== */ -/* Register "SH_INT_CMPD" */ -/* RTC Compare Value for Processor D */ -/* ==================================================================== */ - -#define SH_INT_CMPD 0x00000001101b0180 -#define SH_INT_CMPD_MASK 0x007fffffffffffff -#define SH_INT_CMPD_INIT 0x0000000000000000 - -/* SH_INT_CMPD_REAL_TIME_CMPD */ -/* Description: Real Time Clock Compare */ -#define SH_INT_CMPD_REAL_TIME_CMPD_SHFT 0 -#define SH_INT_CMPD_REAL_TIME_CMPD_MASK 0x007fffffffffffff - -/* ==================================================================== */ -/* Register "SH_INT_PROF" */ -/* Profile Compare Registers */ -/* ==================================================================== */ - -#define SH_INT_PROF 0x00000001101b0200 -#define SH_INT_PROF_MASK 0x00000000ffffffff -#define SH_INT_PROF_INIT 0x0000000000000000 - -/* SH_INT_PROF_PROFILE_COMPARE */ -/* Description: Profile Compare */ -#define SH_INT_PROF_PROFILE_COMPARE_SHFT 0 -#define SH_INT_PROF_PROFILE_COMPARE_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_RTC" */ -/* Real-time Clock */ -/* ==================================================================== */ - -#define SH_RTC 0x00000001101c0000UL -#define SH_RTC_MASK 0x007fffffffffffffUL -#define SH_RTC_INIT 0x0000000000000000 - -/* SH_RTC_REAL_TIME_CLOCK */ -/* Description: Real-time Clock */ -#define SH_RTC_REAL_TIME_CLOCK_SHFT 0 -#define SH_RTC_REAL_TIME_CLOCK_MASK 0x007fffffffffffffUL - -/* ==================================================================== */ -/* Register "SH_SCRATCH0" */ -/* Scratch Register 0 */ -/* ==================================================================== */ - -#define SH_SCRATCH0 0x00000001101d0000 -#define SH_SCRATCH0_MASK 0xffffffffffffffff -#define SH_SCRATCH0_INIT 0x0000000000000000 - -/* SH_SCRATCH0_SCRATCH0 */ -/* Description: Scratch register 0 */ -#define SH_SCRATCH0_SCRATCH0_SHFT 0 -#define SH_SCRATCH0_SCRATCH0_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_SCRATCH0_ALIAS" */ -/* Scratch Register 0 Alias Address */ -/* ==================================================================== */ - -#define SH_SCRATCH0_ALIAS 0x00000001101d0008 - -/* ==================================================================== */ -/* Register "SH_SCRATCH1" */ -/* Scratch Register 1 */ -/* ==================================================================== */ - -#define SH_SCRATCH1 0x00000001101d0080 -#define SH_SCRATCH1_MASK 0xffffffffffffffff -#define SH_SCRATCH1_INIT 0x0000000000000000 - -/* SH_SCRATCH1_SCRATCH1 */ -/* Description: Scratch register 1 */ -#define SH_SCRATCH1_SCRATCH1_SHFT 0 -#define SH_SCRATCH1_SCRATCH1_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_SCRATCH1_ALIAS" */ -/* Scratch Register 1 Alias Address */ -/* ==================================================================== */ - -#define SH_SCRATCH1_ALIAS 0x00000001101d0088 - -/* ==================================================================== */ -/* Register "SH_SCRATCH2" */ -/* Scratch Register 2 */ -/* ==================================================================== */ - -#define SH_SCRATCH2 0x00000001101d0100 -#define SH_SCRATCH2_MASK 0xffffffffffffffff -#define SH_SCRATCH2_INIT 0x0000000000000000 - -/* SH_SCRATCH2_SCRATCH2 */ -/* Description: Scratch register 2 */ -#define SH_SCRATCH2_SCRATCH2_SHFT 0 -#define SH_SCRATCH2_SCRATCH2_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_SCRATCH2_ALIAS" */ -/* Scratch Register 2 Alias Address */ -/* ==================================================================== */ - -#define SH_SCRATCH2_ALIAS 0x00000001101d0108 - -/* ==================================================================== */ -/* Register "SH_SCRATCH3" */ -/* Scratch Register 3 */ -/* ==================================================================== */ - -#define SH_SCRATCH3 0x00000001101d0180 -#define SH_SCRATCH3_MASK 0x0000000000000001 -#define SH_SCRATCH3_INIT 0x0000000000000000 - -/* SH_SCRATCH3_SCRATCH3 */ -/* Description: Scratch register 3 */ -#define SH_SCRATCH3_SCRATCH3_SHFT 0 -#define SH_SCRATCH3_SCRATCH3_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_SCRATCH3_ALIAS" */ -/* Scratch Register 3 Alias Address */ -/* ==================================================================== */ - -#define SH_SCRATCH3_ALIAS 0x00000001101d0188 - -/* ==================================================================== */ -/* Register "SH_SCRATCH4" */ -/* Scratch Register 4 */ -/* ==================================================================== */ - -#define SH_SCRATCH4 0x00000001101d0200 -#define SH_SCRATCH4_MASK 0x0000000000000001 -#define SH_SCRATCH4_INIT 0x0000000000000000 - -/* SH_SCRATCH4_SCRATCH4 */ -/* Description: Scratch register 4 */ -#define SH_SCRATCH4_SCRATCH4_SHFT 0 -#define SH_SCRATCH4_SCRATCH4_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_SCRATCH4_ALIAS" */ -/* Scratch Register 4 Alias Address */ -/* ==================================================================== */ - -#define SH_SCRATCH4_ALIAS 0x00000001101d0208 - -/* ==================================================================== */ -/* Register "SH_CRB_MESSAGE_CONTROL" */ -/* Coherent Request Buffer Message Control */ -/* ==================================================================== */ - -#define SH_CRB_MESSAGE_CONTROL 0x0000000120000000 -#define SH_CRB_MESSAGE_CONTROL_MASK 0xffffffff00000fff -#define SH_CRB_MESSAGE_CONTROL_INIT 0x0000000000000006 - -/* SH_CRB_MESSAGE_CONTROL_SYSTEM_COHERENCE_ENABLE */ -/* Description: System Coherence Enabled */ -#define SH_CRB_MESSAGE_CONTROL_SYSTEM_COHERENCE_ENABLE_SHFT 0 -#define SH_CRB_MESSAGE_CONTROL_SYSTEM_COHERENCE_ENABLE_MASK 0x0000000000000001 - -/* SH_CRB_MESSAGE_CONTROL_LOCAL_SPECULATIVE_MESSAGE_ENABLE */ -/* Description: Speculative Read Requests to Local Memory Enabled */ -#define SH_CRB_MESSAGE_CONTROL_LOCAL_SPECULATIVE_MESSAGE_ENABLE_SHFT 1 -#define SH_CRB_MESSAGE_CONTROL_LOCAL_SPECULATIVE_MESSAGE_ENABLE_MASK 0x0000000000000002 - -/* SH_CRB_MESSAGE_CONTROL_REMOTE_SPECULATIVE_MESSAGE_ENABLE */ -/* Description: Speculative Read Requests to Remote Memory Enabled */ -#define SH_CRB_MESSAGE_CONTROL_REMOTE_SPECULATIVE_MESSAGE_ENABLE_SHFT 2 -#define SH_CRB_MESSAGE_CONTROL_REMOTE_SPECULATIVE_MESSAGE_ENABLE_MASK 0x0000000000000004 - -/* SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR */ -/* Description: Define color of message */ -#define SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR_SHFT 3 -#define SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR_MASK 0x0000000000000008 - -/* SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR_ENABLE */ -/* Description: Enable color message processing */ -#define SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR_ENABLE_SHFT 4 -#define SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR_ENABLE_MASK 0x0000000000000010 - -/* SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_FSB_ENABLE */ -/* Description: Enable FSB RRB Mismatch check */ -#define SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_SHFT 5 -#define SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_MASK 0x0000000000000020 - -/* SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_FSB_ENABLE */ -/* Description: Enable FSB WRB Mismatch check */ -#define SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_SHFT 6 -#define SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_MASK 0x0000000000000040 - -/* SH_CRB_MESSAGE_CONTROL_IRB_ATTRIBUTE_MISMATCH_FSB_ENABLE */ -/* Description: Enable FSB IRB Mismatch check */ -#define SH_CRB_MESSAGE_CONTROL_IRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_SHFT 7 -#define SH_CRB_MESSAGE_CONTROL_IRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_MASK 0x0000000000000080 - -/* SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_XB_ENABLE */ -/* Description: Enable XB RRB Mismatch check */ -#define SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_XB_ENABLE_SHFT 8 -#define SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_XB_ENABLE_MASK 0x0000000000000100 - -/* SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_XB_ENABLE */ -/* Description: Enable XB WRB Mismatch check */ -#define SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_XB_ENABLE_SHFT 9 -#define SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_XB_ENABLE_MASK 0x0000000000000200 - -/* SH_CRB_MESSAGE_CONTROL_SUPPRESS_BOGUS_WRITES */ -/* Description: ignor residual write data */ -#define SH_CRB_MESSAGE_CONTROL_SUPPRESS_BOGUS_WRITES_SHFT 10 -#define SH_CRB_MESSAGE_CONTROL_SUPPRESS_BOGUS_WRITES_MASK 0x0000000000000400 - -/* SH_CRB_MESSAGE_CONTROL_ENABLE_IVACK_CONSOLIDATION */ -/* Description: enable IVACK reply consolidation */ -#define SH_CRB_MESSAGE_CONTROL_ENABLE_IVACK_CONSOLIDATION_SHFT 11 -#define SH_CRB_MESSAGE_CONTROL_ENABLE_IVACK_CONSOLIDATION_MASK 0x0000000000000800 - -/* SH_CRB_MESSAGE_CONTROL_IVACK_STALL_COUNT */ -/* Description: IVACK stall counter */ -#define SH_CRB_MESSAGE_CONTROL_IVACK_STALL_COUNT_SHFT 32 -#define SH_CRB_MESSAGE_CONTROL_IVACK_STALL_COUNT_MASK 0x0000ffff00000000 - -/* SH_CRB_MESSAGE_CONTROL_IVACK_THROTTLE_CONTROL */ -/* Description: IVACK throttling limit/timer control */ -#define SH_CRB_MESSAGE_CONTROL_IVACK_THROTTLE_CONTROL_SHFT 48 -#define SH_CRB_MESSAGE_CONTROL_IVACK_THROTTLE_CONTROL_MASK 0xffff000000000000 - -/* ==================================================================== */ -/* Register "SH_CRB_NACK_LIMIT" */ -/* CRB Nack Limit */ -/* ==================================================================== */ - -#define SH_CRB_NACK_LIMIT 0x0000000120000080 -#define SH_CRB_NACK_LIMIT_MASK 0x800000000000ffff -#define SH_CRB_NACK_LIMIT_INIT 0x0000000000000000 - -/* SH_CRB_NACK_LIMIT_LIMIT */ -/* Description: Nack Count Limit */ -#define SH_CRB_NACK_LIMIT_LIMIT_SHFT 0 -#define SH_CRB_NACK_LIMIT_LIMIT_MASK 0x0000000000000fff - -/* SH_CRB_NACK_LIMIT_PRI_FREQ */ -/* Description: Frequency at which priority count is incremented */ -#define SH_CRB_NACK_LIMIT_PRI_FREQ_SHFT 12 -#define SH_CRB_NACK_LIMIT_PRI_FREQ_MASK 0x000000000000f000 - -/* SH_CRB_NACK_LIMIT_ENABLE */ -/* Description: Enable NACK limit detection */ -#define SH_CRB_NACK_LIMIT_ENABLE_SHFT 63 -#define SH_CRB_NACK_LIMIT_ENABLE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_CRB_TIMEOUT_PRESCALE" */ -/* Coherent Request Buffer Timeout Prescale */ -/* ==================================================================== */ - -#define SH_CRB_TIMEOUT_PRESCALE 0x0000000120000100 -#define SH_CRB_TIMEOUT_PRESCALE_MASK 0x00000000ffffffff -#define SH_CRB_TIMEOUT_PRESCALE_INIT 0x0000000000000000 - -/* SH_CRB_TIMEOUT_PRESCALE_SCALING_FACTOR */ -/* Description: CRB Time-out Prescale Factor */ -#define SH_CRB_TIMEOUT_PRESCALE_SCALING_FACTOR_SHFT 0 -#define SH_CRB_TIMEOUT_PRESCALE_SCALING_FACTOR_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_CRB_TIMEOUT_SKID" */ -/* Coherent Request Buffer Timeout Skid Limit */ -/* ==================================================================== */ - -#define SH_CRB_TIMEOUT_SKID 0x0000000120000180 -#define SH_CRB_TIMEOUT_SKID_MASK 0x800000000000003f -#define SH_CRB_TIMEOUT_SKID_INIT 0x0000000000000007 - -/* SH_CRB_TIMEOUT_SKID_SKID */ -/* Description: CRB Time-out Skid */ -#define SH_CRB_TIMEOUT_SKID_SKID_SHFT 0 -#define SH_CRB_TIMEOUT_SKID_SKID_MASK 0x000000000000003f - -/* SH_CRB_TIMEOUT_SKID_RESET_SKID_COUNT */ -/* Description: Reset Skid counter */ -#define SH_CRB_TIMEOUT_SKID_RESET_SKID_COUNT_SHFT 63 -#define SH_CRB_TIMEOUT_SKID_RESET_SKID_COUNT_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_MEMORY_WRITE_STATUS_0" */ -/* Memory Write Status for CPU 0 */ -/* ==================================================================== */ - -#define SH_MEMORY_WRITE_STATUS_0 0x0000000120070000 -#define SH_MEMORY_WRITE_STATUS_0_MASK 0x000000000000003f -#define SH_MEMORY_WRITE_STATUS_0_INIT 0x0000000000000000 - -/* SH_MEMORY_WRITE_STATUS_0_PENDING_WRITE_COUNT */ -/* Description: Pending Write Count */ -#define SH_MEMORY_WRITE_STATUS_0_PENDING_WRITE_COUNT_SHFT 0 -#define SH_MEMORY_WRITE_STATUS_0_PENDING_WRITE_COUNT_MASK 0x000000000000003f - -/* ==================================================================== */ -/* Register "SH_MEMORY_WRITE_STATUS_1" */ -/* Memory Write Status for CPU 1 */ -/* ==================================================================== */ - -#define SH_MEMORY_WRITE_STATUS_1 0x0000000120070080 -#define SH_MEMORY_WRITE_STATUS_1_MASK 0x000000000000003f -#define SH_MEMORY_WRITE_STATUS_1_INIT 0x0000000000000000 - -/* SH_MEMORY_WRITE_STATUS_1_PENDING_WRITE_COUNT */ -/* Description: Pending Write Count */ -#define SH_MEMORY_WRITE_STATUS_1_PENDING_WRITE_COUNT_SHFT 0 -#define SH_MEMORY_WRITE_STATUS_1_PENDING_WRITE_COUNT_MASK 0x000000000000003f - -/* ==================================================================== */ -/* Register "SH_PIO_WRITE_STATUS_0" */ -/* PIO Write Status for CPU 0 */ -/* ==================================================================== */ - -#define SH_PIO_WRITE_STATUS_0 0x0000000120070200 -#define SH_PIO_WRITE_STATUS_0_MASK 0xbf03ffffffffffff -#define SH_PIO_WRITE_STATUS_0_INIT 0x8000000000000000 - -/* SH_PIO_WRITE_STATUS_0_MULTI_WRITE_ERROR */ -/* Description: More than one PIO write error occurred */ -#define SH_PIO_WRITE_STATUS_0_MULTI_WRITE_ERROR_SHFT 0 -#define SH_PIO_WRITE_STATUS_0_MULTI_WRITE_ERROR_MASK 0x0000000000000001 - -/* SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK */ -/* Description: Deaklock response detected */ -#define SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK_SHFT 1 -#define SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK_MASK 0x0000000000000002 - -/* SH_PIO_WRITE_STATUS_0_WRITE_ERROR */ -/* Description: Error response detected */ -#define SH_PIO_WRITE_STATUS_0_WRITE_ERROR_SHFT 2 -#define SH_PIO_WRITE_STATUS_0_WRITE_ERROR_MASK 0x0000000000000004 - -/* SH_PIO_WRITE_STATUS_0_WRITE_ERROR_ADDRESS */ -/* Description: Address associated with error response */ -#define SH_PIO_WRITE_STATUS_0_WRITE_ERROR_ADDRESS_SHFT 3 -#define SH_PIO_WRITE_STATUS_0_WRITE_ERROR_ADDRESS_MASK 0x0003fffffffffff8 - -/* SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT */ -/* Description: Count of currently pending PIO writes */ -#define SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_SHFT 56 -#define SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_MASK 0x3f00000000000000 - -/* SH_PIO_WRITE_STATUS_0_WRITES_OK */ -/* Description: No pending writes or errors */ -#define SH_PIO_WRITE_STATUS_0_WRITES_OK_SHFT 63 -#define SH_PIO_WRITE_STATUS_0_WRITES_OK_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PIO_WRITE_STATUS_1" */ -/* PIO Write Status for CPU 1 */ -/* ==================================================================== */ - -#define SH_PIO_WRITE_STATUS_1 0x0000000120070280 -#define SH_PIO_WRITE_STATUS_1_MASK 0xbf03ffffffffffff -#define SH_PIO_WRITE_STATUS_1_INIT 0x8000000000000000 - -/* SH_PIO_WRITE_STATUS_1_MULTI_WRITE_ERROR */ -/* Description: More than one PIO write error occurred */ -#define SH_PIO_WRITE_STATUS_1_MULTI_WRITE_ERROR_SHFT 0 -#define SH_PIO_WRITE_STATUS_1_MULTI_WRITE_ERROR_MASK 0x0000000000000001 - -/* SH_PIO_WRITE_STATUS_1_WRITE_DEADLOCK */ -/* Description: Deaklock response detected */ -#define SH_PIO_WRITE_STATUS_1_WRITE_DEADLOCK_SHFT 1 -#define SH_PIO_WRITE_STATUS_1_WRITE_DEADLOCK_MASK 0x0000000000000002 - -/* SH_PIO_WRITE_STATUS_1_WRITE_ERROR */ -/* Description: Error response detected */ -#define SH_PIO_WRITE_STATUS_1_WRITE_ERROR_SHFT 2 -#define SH_PIO_WRITE_STATUS_1_WRITE_ERROR_MASK 0x0000000000000004 - -/* SH_PIO_WRITE_STATUS_1_WRITE_ERROR_ADDRESS */ -/* Description: Address associated with error response */ -#define SH_PIO_WRITE_STATUS_1_WRITE_ERROR_ADDRESS_SHFT 3 -#define SH_PIO_WRITE_STATUS_1_WRITE_ERROR_ADDRESS_MASK 0x0003fffffffffff8 - -/* SH_PIO_WRITE_STATUS_1_PENDING_WRITE_COUNT */ -/* Description: Count of currently pending PIO writes */ -#define SH_PIO_WRITE_STATUS_1_PENDING_WRITE_COUNT_SHFT 56 -#define SH_PIO_WRITE_STATUS_1_PENDING_WRITE_COUNT_MASK 0x3f00000000000000 - -/* SH_PIO_WRITE_STATUS_1_WRITES_OK */ -/* Description: No pending writes or errors */ -#define SH_PIO_WRITE_STATUS_1_WRITES_OK_SHFT 63 -#define SH_PIO_WRITE_STATUS_1_WRITES_OK_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PIO_WRITE_STATUS_0_ALIAS" */ -/* ==================================================================== */ - -#define SH_PIO_WRITE_STATUS_0_ALIAS 0x0000000120070208 - -/* ==================================================================== */ -/* Register "SH_PIO_WRITE_STATUS_1_ALIAS" */ -/* ==================================================================== */ - -#define SH_PIO_WRITE_STATUS_1_ALIAS 0x0000000120070288 - -/* ==================================================================== */ -/* Register "SH_MEMORY_WRITE_STATUS_NON_USER_0" */ -/* Memory Write Status for CPU 0. OS access only */ -/* ==================================================================== */ - -#define SH_MEMORY_WRITE_STATUS_NON_USER_0 0x0000000120070400 -#define SH_MEMORY_WRITE_STATUS_NON_USER_0_MASK 0x800000000000003f -#define SH_MEMORY_WRITE_STATUS_NON_USER_0_INIT 0x0000000000000000 - -/* SH_MEMORY_WRITE_STATUS_NON_USER_0_PENDING_WRITE_COUNT */ -/* Description: Pending Write Count */ -#define SH_MEMORY_WRITE_STATUS_NON_USER_0_PENDING_WRITE_COUNT_SHFT 0 -#define SH_MEMORY_WRITE_STATUS_NON_USER_0_PENDING_WRITE_COUNT_MASK 0x000000000000003f - -/* SH_MEMORY_WRITE_STATUS_NON_USER_0_CLEAR */ -/* Description: Clear pending write count */ -#define SH_MEMORY_WRITE_STATUS_NON_USER_0_CLEAR_SHFT 63 -#define SH_MEMORY_WRITE_STATUS_NON_USER_0_CLEAR_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_MEMORY_WRITE_STATUS_NON_USER_1" */ -/* Memory Write Status for CPU 1. OS access only */ -/* ==================================================================== */ - -#define SH_MEMORY_WRITE_STATUS_NON_USER_1 0x0000000120070480 -#define SH_MEMORY_WRITE_STATUS_NON_USER_1_MASK 0x800000000000003f -#define SH_MEMORY_WRITE_STATUS_NON_USER_1_INIT 0x0000000000000000 - -/* SH_MEMORY_WRITE_STATUS_NON_USER_1_PENDING_WRITE_COUNT */ -/* Description: Pending Write Count */ -#define SH_MEMORY_WRITE_STATUS_NON_USER_1_PENDING_WRITE_COUNT_SHFT 0 -#define SH_MEMORY_WRITE_STATUS_NON_USER_1_PENDING_WRITE_COUNT_MASK 0x000000000000003f - -/* SH_MEMORY_WRITE_STATUS_NON_USER_1_CLEAR */ -/* Description: Clear pending write count */ -#define SH_MEMORY_WRITE_STATUS_NON_USER_1_CLEAR_SHFT 63 -#define SH_MEMORY_WRITE_STATUS_NON_USER_1_CLEAR_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_MMRBIST_ERR" */ -/* Error capture for bist read errors */ -/* ==================================================================== */ - -#define SH_MMRBIST_ERR 0x0000000100000080 -#define SH_MMRBIST_ERR_MASK 0x00000071ffffffff -#define SH_MMRBIST_ERR_INIT 0x0000000000000000 - -/* SH_MMRBIST_ERR_ADDR */ -/* Description: dword address of bist error */ -#define SH_MMRBIST_ERR_ADDR_SHFT 0 -#define SH_MMRBIST_ERR_ADDR_MASK 0x00000001ffffffff - -/* SH_MMRBIST_ERR_DETECTED */ -/* Description: error detected flag */ -#define SH_MMRBIST_ERR_DETECTED_SHFT 36 -#define SH_MMRBIST_ERR_DETECTED_MASK 0x0000001000000000 - -/* SH_MMRBIST_ERR_MULTIPLE_DETECTED */ -/* Description: multiple errors detected flag */ -#define SH_MMRBIST_ERR_MULTIPLE_DETECTED_SHFT 37 -#define SH_MMRBIST_ERR_MULTIPLE_DETECTED_MASK 0x0000002000000000 - -/* SH_MMRBIST_ERR_CANCELLED */ -/* Description: mmr/bist was cancelled */ -#define SH_MMRBIST_ERR_CANCELLED_SHFT 38 -#define SH_MMRBIST_ERR_CANCELLED_MASK 0x0000004000000000 - -/* ==================================================================== */ -/* Register "SH_MISC_ERR_HDR_LOWER" */ -/* Header capture register */ -/* ==================================================================== */ - -#define SH_MISC_ERR_HDR_LOWER 0x0000000100000088 -#define SH_MISC_ERR_HDR_LOWER_MASK 0x93fffffffffffff8 -#define SH_MISC_ERR_HDR_LOWER_INIT 0x0000000000000000 - -/* SH_MISC_ERR_HDR_LOWER_ADDR */ -/* Description: upper bits of reference address */ -#define SH_MISC_ERR_HDR_LOWER_ADDR_SHFT 3 -#define SH_MISC_ERR_HDR_LOWER_ADDR_MASK 0x0000000ffffffff8 - -/* SH_MISC_ERR_HDR_LOWER_CMD */ -/* Description: command of reference */ -#define SH_MISC_ERR_HDR_LOWER_CMD_SHFT 36 -#define SH_MISC_ERR_HDR_LOWER_CMD_MASK 0x00000ff000000000 - -/* SH_MISC_ERR_HDR_LOWER_SRC */ -/* Description: source node of reference */ -#define SH_MISC_ERR_HDR_LOWER_SRC_SHFT 44 -#define SH_MISC_ERR_HDR_LOWER_SRC_MASK 0x03fff00000000000 - -/* SH_MISC_ERR_HDR_LOWER_WRITE */ -/* Description: reference is a write */ -#define SH_MISC_ERR_HDR_LOWER_WRITE_SHFT 60 -#define SH_MISC_ERR_HDR_LOWER_WRITE_MASK 0x1000000000000000 - -/* SH_MISC_ERR_HDR_LOWER_VALID */ -/* Description: set when capture occurs */ -#define SH_MISC_ERR_HDR_LOWER_VALID_SHFT 63 -#define SH_MISC_ERR_HDR_LOWER_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_MISC_ERR_HDR_UPPER" */ -/* Error header capture packet and protocol errors */ -/* ==================================================================== */ - -#define SH_MISC_ERR_HDR_UPPER 0x0000000100000090 -#define SH_MISC_ERR_HDR_UPPER_MASK 0x000000001ff000ff -#define SH_MISC_ERR_HDR_UPPER_INIT 0x0000000000000000 - -/* SH_MISC_ERR_HDR_UPPER_DIR_PROTOCOL */ -/* Description: indicates a directory protocol error captured */ -#define SH_MISC_ERR_HDR_UPPER_DIR_PROTOCOL_SHFT 0 -#define SH_MISC_ERR_HDR_UPPER_DIR_PROTOCOL_MASK 0x0000000000000001 - -/* SH_MISC_ERR_HDR_UPPER_ILLEGAL_CMD */ -/* Description: indicates an illegal command error captured */ -#define SH_MISC_ERR_HDR_UPPER_ILLEGAL_CMD_SHFT 1 -#define SH_MISC_ERR_HDR_UPPER_ILLEGAL_CMD_MASK 0x0000000000000002 - -/* SH_MISC_ERR_HDR_UPPER_NONEXIST_ADDR */ -/* Description: indicates a non-existent memory error captured */ -#define SH_MISC_ERR_HDR_UPPER_NONEXIST_ADDR_SHFT 2 -#define SH_MISC_ERR_HDR_UPPER_NONEXIST_ADDR_MASK 0x0000000000000004 - -/* SH_MISC_ERR_HDR_UPPER_RMW_UC */ -/* Description: indicates an uncorrectable store rmw */ -#define SH_MISC_ERR_HDR_UPPER_RMW_UC_SHFT 3 -#define SH_MISC_ERR_HDR_UPPER_RMW_UC_MASK 0x0000000000000008 - -/* SH_MISC_ERR_HDR_UPPER_RMW_COR */ -/* Description: indicates a correctable store rmw */ -#define SH_MISC_ERR_HDR_UPPER_RMW_COR_SHFT 4 -#define SH_MISC_ERR_HDR_UPPER_RMW_COR_MASK 0x0000000000000010 - -/* SH_MISC_ERR_HDR_UPPER_DIR_ACC */ -/* Description: indicates a data request to directory memory error */ -/* captured */ -#define SH_MISC_ERR_HDR_UPPER_DIR_ACC_SHFT 5 -#define SH_MISC_ERR_HDR_UPPER_DIR_ACC_MASK 0x0000000000000020 - -/* SH_MISC_ERR_HDR_UPPER_PI_PKT_SIZE */ -/* Description: indicates a pkt size error from pi */ -#define SH_MISC_ERR_HDR_UPPER_PI_PKT_SIZE_SHFT 6 -#define SH_MISC_ERR_HDR_UPPER_PI_PKT_SIZE_MASK 0x0000000000000040 - -/* SH_MISC_ERR_HDR_UPPER_XN_PKT_SIZE */ -/* Description: indicates a pkt size error from xn */ -#define SH_MISC_ERR_HDR_UPPER_XN_PKT_SIZE_SHFT 7 -#define SH_MISC_ERR_HDR_UPPER_XN_PKT_SIZE_MASK 0x0000000000000080 - -/* SH_MISC_ERR_HDR_UPPER_ECHO */ -#define SH_MISC_ERR_HDR_UPPER_ECHO_SHFT 20 -#define SH_MISC_ERR_HDR_UPPER_ECHO_MASK 0x000000001ff00000 - -/* ==================================================================== */ -/* Register "SH_DIR_UC_ERR_HDR_LOWER" */ -/* Header capture register */ -/* ==================================================================== */ - -#define SH_DIR_UC_ERR_HDR_LOWER 0x0000000100000098 -#define SH_DIR_UC_ERR_HDR_LOWER_MASK 0x93fffffffffffff8 -#define SH_DIR_UC_ERR_HDR_LOWER_INIT 0x0000000000000000 - -/* SH_DIR_UC_ERR_HDR_LOWER_ADDR */ -/* Description: upper bits of reference address */ -#define SH_DIR_UC_ERR_HDR_LOWER_ADDR_SHFT 3 -#define SH_DIR_UC_ERR_HDR_LOWER_ADDR_MASK 0x0000000ffffffff8 - -/* SH_DIR_UC_ERR_HDR_LOWER_CMD */ -/* Description: command of reference */ -#define SH_DIR_UC_ERR_HDR_LOWER_CMD_SHFT 36 -#define SH_DIR_UC_ERR_HDR_LOWER_CMD_MASK 0x00000ff000000000 - -/* SH_DIR_UC_ERR_HDR_LOWER_SRC */ -/* Description: source node of reference */ -#define SH_DIR_UC_ERR_HDR_LOWER_SRC_SHFT 44 -#define SH_DIR_UC_ERR_HDR_LOWER_SRC_MASK 0x03fff00000000000 - -/* SH_DIR_UC_ERR_HDR_LOWER_WRITE */ -/* Description: reference is a write */ -#define SH_DIR_UC_ERR_HDR_LOWER_WRITE_SHFT 60 -#define SH_DIR_UC_ERR_HDR_LOWER_WRITE_MASK 0x1000000000000000 - -/* SH_DIR_UC_ERR_HDR_LOWER_VALID */ -/* Description: set when capture occurs */ -#define SH_DIR_UC_ERR_HDR_LOWER_VALID_SHFT 63 -#define SH_DIR_UC_ERR_HDR_LOWER_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_DIR_UC_ERR_HDR_UPPER" */ -/* Error header capture packet and protocol errors */ -/* ==================================================================== */ - -#define SH_DIR_UC_ERR_HDR_UPPER 0x00000001000000a0 -#define SH_DIR_UC_ERR_HDR_UPPER_MASK 0x000000001ff00008 -#define SH_DIR_UC_ERR_HDR_UPPER_INIT 0x0000000000000000 - -/* SH_DIR_UC_ERR_HDR_UPPER_DIR_UC */ -/* Description: indicates uncorrectable directory error captured */ -#define SH_DIR_UC_ERR_HDR_UPPER_DIR_UC_SHFT 3 -#define SH_DIR_UC_ERR_HDR_UPPER_DIR_UC_MASK 0x0000000000000008 - -/* SH_DIR_UC_ERR_HDR_UPPER_ECHO */ -#define SH_DIR_UC_ERR_HDR_UPPER_ECHO_SHFT 20 -#define SH_DIR_UC_ERR_HDR_UPPER_ECHO_MASK 0x000000001ff00000 - -/* ==================================================================== */ -/* Register "SH_DIR_COR_ERR_HDR_LOWER" */ -/* Header capture register */ -/* ==================================================================== */ - -#define SH_DIR_COR_ERR_HDR_LOWER 0x00000001000000a8 -#define SH_DIR_COR_ERR_HDR_LOWER_MASK 0x93fffffffffffff8 -#define SH_DIR_COR_ERR_HDR_LOWER_INIT 0x0000000000000000 - -/* SH_DIR_COR_ERR_HDR_LOWER_ADDR */ -/* Description: upper bits of reference address */ -#define SH_DIR_COR_ERR_HDR_LOWER_ADDR_SHFT 3 -#define SH_DIR_COR_ERR_HDR_LOWER_ADDR_MASK 0x0000000ffffffff8 - -/* SH_DIR_COR_ERR_HDR_LOWER_CMD */ -/* Description: command of reference */ -#define SH_DIR_COR_ERR_HDR_LOWER_CMD_SHFT 36 -#define SH_DIR_COR_ERR_HDR_LOWER_CMD_MASK 0x00000ff000000000 - -/* SH_DIR_COR_ERR_HDR_LOWER_SRC */ -/* Description: source node of reference */ -#define SH_DIR_COR_ERR_HDR_LOWER_SRC_SHFT 44 -#define SH_DIR_COR_ERR_HDR_LOWER_SRC_MASK 0x03fff00000000000 - -/* SH_DIR_COR_ERR_HDR_LOWER_WRITE */ -/* Description: reference is a write */ -#define SH_DIR_COR_ERR_HDR_LOWER_WRITE_SHFT 60 -#define SH_DIR_COR_ERR_HDR_LOWER_WRITE_MASK 0x1000000000000000 - -/* SH_DIR_COR_ERR_HDR_LOWER_VALID */ -/* Description: set when capture occurs */ -#define SH_DIR_COR_ERR_HDR_LOWER_VALID_SHFT 63 -#define SH_DIR_COR_ERR_HDR_LOWER_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_DIR_COR_ERR_HDR_UPPER" */ -/* Error header capture packet and protocol errors */ -/* ==================================================================== */ - -#define SH_DIR_COR_ERR_HDR_UPPER 0x00000001000000b0 -#define SH_DIR_COR_ERR_HDR_UPPER_MASK 0x000000001ff00100 -#define SH_DIR_COR_ERR_HDR_UPPER_INIT 0x0000000000000000 - -/* SH_DIR_COR_ERR_HDR_UPPER_DIR_COR */ -/* Description: indicates correctable directory error captured */ -#define SH_DIR_COR_ERR_HDR_UPPER_DIR_COR_SHFT 8 -#define SH_DIR_COR_ERR_HDR_UPPER_DIR_COR_MASK 0x0000000000000100 - -/* SH_DIR_COR_ERR_HDR_UPPER_ECHO */ -#define SH_DIR_COR_ERR_HDR_UPPER_ECHO_SHFT 20 -#define SH_DIR_COR_ERR_HDR_UPPER_ECHO_MASK 0x000000001ff00000 - -/* ==================================================================== */ -/* Register "SH_MEM_ERROR_SUMMARY" */ -/* Memory error flags */ -/* ==================================================================== */ - -#define SH_MEM_ERROR_SUMMARY 0x00000001000000b8 -#define SH_MEM_ERROR_SUMMARY_MASK 0x00000007f77777ff -#define SH_MEM_ERROR_SUMMARY_INIT 0x0000000000000000 - -/* SH_MEM_ERROR_SUMMARY_ILLEGAL_CMD */ -/* Description: illegal command error */ -#define SH_MEM_ERROR_SUMMARY_ILLEGAL_CMD_SHFT 0 -#define SH_MEM_ERROR_SUMMARY_ILLEGAL_CMD_MASK 0x0000000000000001 - -/* SH_MEM_ERROR_SUMMARY_NONEXIST_ADDR */ -/* Description: non-existent memory error */ -#define SH_MEM_ERROR_SUMMARY_NONEXIST_ADDR_SHFT 1 -#define SH_MEM_ERROR_SUMMARY_NONEXIST_ADDR_MASK 0x0000000000000002 - -/* SH_MEM_ERROR_SUMMARY_DQLP_DIR_PERR */ -/* Description: directory protocol error in dqlp */ -#define SH_MEM_ERROR_SUMMARY_DQLP_DIR_PERR_SHFT 2 -#define SH_MEM_ERROR_SUMMARY_DQLP_DIR_PERR_MASK 0x0000000000000004 - -/* SH_MEM_ERROR_SUMMARY_DQRP_DIR_PERR */ -/* Description: directory protocol error in dqrp */ -#define SH_MEM_ERROR_SUMMARY_DQRP_DIR_PERR_SHFT 3 -#define SH_MEM_ERROR_SUMMARY_DQRP_DIR_PERR_MASK 0x0000000000000008 - -/* SH_MEM_ERROR_SUMMARY_DQLP_DIR_UC */ -/* Description: uncorrectable directory error in dqlp */ -#define SH_MEM_ERROR_SUMMARY_DQLP_DIR_UC_SHFT 4 -#define SH_MEM_ERROR_SUMMARY_DQLP_DIR_UC_MASK 0x0000000000000010 - -/* SH_MEM_ERROR_SUMMARY_DQLP_DIR_COR */ -/* Description: correctable directory error in dqlp */ -#define SH_MEM_ERROR_SUMMARY_DQLP_DIR_COR_SHFT 5 -#define SH_MEM_ERROR_SUMMARY_DQLP_DIR_COR_MASK 0x0000000000000020 - -/* SH_MEM_ERROR_SUMMARY_DQRP_DIR_UC */ -/* Description: uncorrectable directory error in dqrp */ -#define SH_MEM_ERROR_SUMMARY_DQRP_DIR_UC_SHFT 6 -#define SH_MEM_ERROR_SUMMARY_DQRP_DIR_UC_MASK 0x0000000000000040 - -/* SH_MEM_ERROR_SUMMARY_DQRP_DIR_COR */ -/* Description: correctable directory error in dqrp */ -#define SH_MEM_ERROR_SUMMARY_DQRP_DIR_COR_SHFT 7 -#define SH_MEM_ERROR_SUMMARY_DQRP_DIR_COR_MASK 0x0000000000000080 - -/* SH_MEM_ERROR_SUMMARY_ACX_INT_HW */ -/* Description: hardware interrupt from acx */ -#define SH_MEM_ERROR_SUMMARY_ACX_INT_HW_SHFT 8 -#define SH_MEM_ERROR_SUMMARY_ACX_INT_HW_MASK 0x0000000000000100 - -/* SH_MEM_ERROR_SUMMARY_ACY_INT_HW */ -/* Description: hardware interrupt from acy */ -#define SH_MEM_ERROR_SUMMARY_ACY_INT_HW_SHFT 9 -#define SH_MEM_ERROR_SUMMARY_ACY_INT_HW_MASK 0x0000000000000200 - -/* SH_MEM_ERROR_SUMMARY_DIR_ACC */ -/* Description: directory memory access error */ -#define SH_MEM_ERROR_SUMMARY_DIR_ACC_SHFT 10 -#define SH_MEM_ERROR_SUMMARY_DIR_ACC_MASK 0x0000000000000400 - -/* SH_MEM_ERROR_SUMMARY_DQLP_INT_UC */ -/* Description: uncorrectable interrupt from dqlp */ -#define SH_MEM_ERROR_SUMMARY_DQLP_INT_UC_SHFT 12 -#define SH_MEM_ERROR_SUMMARY_DQLP_INT_UC_MASK 0x0000000000001000 - -/* SH_MEM_ERROR_SUMMARY_DQLP_INT_COR */ -/* Description: correctable interrupt from dqlp */ -#define SH_MEM_ERROR_SUMMARY_DQLP_INT_COR_SHFT 13 -#define SH_MEM_ERROR_SUMMARY_DQLP_INT_COR_MASK 0x0000000000002000 - -/* SH_MEM_ERROR_SUMMARY_DQLP_INT_HW */ -/* Description: hardware interrupt from dqlp */ -#define SH_MEM_ERROR_SUMMARY_DQLP_INT_HW_SHFT 14 -#define SH_MEM_ERROR_SUMMARY_DQLP_INT_HW_MASK 0x0000000000004000 - -/* SH_MEM_ERROR_SUMMARY_DQLS_INT_UC */ -/* Description: uncorrectable interrupt from dqls */ -#define SH_MEM_ERROR_SUMMARY_DQLS_INT_UC_SHFT 16 -#define SH_MEM_ERROR_SUMMARY_DQLS_INT_UC_MASK 0x0000000000010000 - -/* SH_MEM_ERROR_SUMMARY_DQLS_INT_COR */ -/* Description: correctable interrupt from dqls */ -#define SH_MEM_ERROR_SUMMARY_DQLS_INT_COR_SHFT 17 -#define SH_MEM_ERROR_SUMMARY_DQLS_INT_COR_MASK 0x0000000000020000 - -/* SH_MEM_ERROR_SUMMARY_DQLS_INT_HW */ -/* Description: hardware interrupt from dqls */ -#define SH_MEM_ERROR_SUMMARY_DQLS_INT_HW_SHFT 18 -#define SH_MEM_ERROR_SUMMARY_DQLS_INT_HW_MASK 0x0000000000040000 - -/* SH_MEM_ERROR_SUMMARY_DQRP_INT_UC */ -/* Description: uncorrectable interrupt from dqrp */ -#define SH_MEM_ERROR_SUMMARY_DQRP_INT_UC_SHFT 20 -#define SH_MEM_ERROR_SUMMARY_DQRP_INT_UC_MASK 0x0000000000100000 - -/* SH_MEM_ERROR_SUMMARY_DQRP_INT_COR */ -/* Description: correctable interrupt from dqrp */ -#define SH_MEM_ERROR_SUMMARY_DQRP_INT_COR_SHFT 21 -#define SH_MEM_ERROR_SUMMARY_DQRP_INT_COR_MASK 0x0000000000200000 - -/* SH_MEM_ERROR_SUMMARY_DQRP_INT_HW */ -/* Description: hardware interrupt from dqrp */ -#define SH_MEM_ERROR_SUMMARY_DQRP_INT_HW_SHFT 22 -#define SH_MEM_ERROR_SUMMARY_DQRP_INT_HW_MASK 0x0000000000400000 - -/* SH_MEM_ERROR_SUMMARY_DQRS_INT_UC */ -/* Description: uncorrectable interrupt from dqrs */ -#define SH_MEM_ERROR_SUMMARY_DQRS_INT_UC_SHFT 24 -#define SH_MEM_ERROR_SUMMARY_DQRS_INT_UC_MASK 0x0000000001000000 - -/* SH_MEM_ERROR_SUMMARY_DQRS_INT_COR */ -/* Description: correctable interrupt from dqrs */ -#define SH_MEM_ERROR_SUMMARY_DQRS_INT_COR_SHFT 25 -#define SH_MEM_ERROR_SUMMARY_DQRS_INT_COR_MASK 0x0000000002000000 - -/* SH_MEM_ERROR_SUMMARY_DQRS_INT_HW */ -/* Description: hardware interrupt from dqrs */ -#define SH_MEM_ERROR_SUMMARY_DQRS_INT_HW_SHFT 26 -#define SH_MEM_ERROR_SUMMARY_DQRS_INT_HW_MASK 0x0000000004000000 - -/* SH_MEM_ERROR_SUMMARY_PI_REPLY_OVERFLOW */ -/* Description: too many reply packets came from pi */ -#define SH_MEM_ERROR_SUMMARY_PI_REPLY_OVERFLOW_SHFT 28 -#define SH_MEM_ERROR_SUMMARY_PI_REPLY_OVERFLOW_MASK 0x0000000010000000 - -/* SH_MEM_ERROR_SUMMARY_XN_REPLY_OVERFLOW */ -/* Description: too many reply packets came from xn */ -#define SH_MEM_ERROR_SUMMARY_XN_REPLY_OVERFLOW_SHFT 29 -#define SH_MEM_ERROR_SUMMARY_XN_REPLY_OVERFLOW_MASK 0x0000000020000000 - -/* SH_MEM_ERROR_SUMMARY_PI_REQUEST_OVERFLOW */ -/* Description: too many request packets came from pi */ -#define SH_MEM_ERROR_SUMMARY_PI_REQUEST_OVERFLOW_SHFT 30 -#define SH_MEM_ERROR_SUMMARY_PI_REQUEST_OVERFLOW_MASK 0x0000000040000000 - -/* SH_MEM_ERROR_SUMMARY_XN_REQUEST_OVERFLOW */ -/* Description: too many request packets came from xn */ -#define SH_MEM_ERROR_SUMMARY_XN_REQUEST_OVERFLOW_SHFT 31 -#define SH_MEM_ERROR_SUMMARY_XN_REQUEST_OVERFLOW_MASK 0x0000000080000000 - -/* SH_MEM_ERROR_SUMMARY_RED_BLACK_ERR_TIMEOUT */ -/* Description: red black scheme did not clean up soon enough */ -#define SH_MEM_ERROR_SUMMARY_RED_BLACK_ERR_TIMEOUT_SHFT 32 -#define SH_MEM_ERROR_SUMMARY_RED_BLACK_ERR_TIMEOUT_MASK 0x0000000100000000 - -/* SH_MEM_ERROR_SUMMARY_PI_PKT_SIZE */ -/* Description: received data bearing packet from pi with wrong siz */ -#define SH_MEM_ERROR_SUMMARY_PI_PKT_SIZE_SHFT 33 -#define SH_MEM_ERROR_SUMMARY_PI_PKT_SIZE_MASK 0x0000000200000000 - -/* SH_MEM_ERROR_SUMMARY_XN_PKT_SIZE */ -/* Description: received data bearing packet from xn with wrong siz */ -#define SH_MEM_ERROR_SUMMARY_XN_PKT_SIZE_SHFT 34 -#define SH_MEM_ERROR_SUMMARY_XN_PKT_SIZE_MASK 0x0000000400000000 - -/* ==================================================================== */ -/* Register "SH_MEM_ERROR_SUMMARY_ALIAS" */ -/* Memory error flags clear alias */ -/* ==================================================================== */ - -#define SH_MEM_ERROR_SUMMARY_ALIAS 0x00000001000000c0 - -/* ==================================================================== */ -/* Register "SH_MEM_ERROR_OVERFLOW" */ -/* Memory error flags */ -/* ==================================================================== */ - -#define SH_MEM_ERROR_OVERFLOW 0x00000001000000c8 -#define SH_MEM_ERROR_OVERFLOW_MASK 0x00000007f77777ff -#define SH_MEM_ERROR_OVERFLOW_INIT 0x0000000000000000 - -/* SH_MEM_ERROR_OVERFLOW_ILLEGAL_CMD */ -/* Description: illegal command error */ -#define SH_MEM_ERROR_OVERFLOW_ILLEGAL_CMD_SHFT 0 -#define SH_MEM_ERROR_OVERFLOW_ILLEGAL_CMD_MASK 0x0000000000000001 - -/* SH_MEM_ERROR_OVERFLOW_NONEXIST_ADDR */ -/* Description: non-existent memory error */ -#define SH_MEM_ERROR_OVERFLOW_NONEXIST_ADDR_SHFT 1 -#define SH_MEM_ERROR_OVERFLOW_NONEXIST_ADDR_MASK 0x0000000000000002 - -/* SH_MEM_ERROR_OVERFLOW_DQLP_DIR_PERR */ -/* Description: directory protocol error in dqlp */ -#define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_PERR_SHFT 2 -#define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_PERR_MASK 0x0000000000000004 - -/* SH_MEM_ERROR_OVERFLOW_DQRP_DIR_PERR */ -/* Description: directory protocol error in dqrp */ -#define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_PERR_SHFT 3 -#define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_PERR_MASK 0x0000000000000008 - -/* SH_MEM_ERROR_OVERFLOW_DQLP_DIR_UC */ -/* Description: uncorrectable directory error in dqlp */ -#define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_UC_SHFT 4 -#define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_UC_MASK 0x0000000000000010 - -/* SH_MEM_ERROR_OVERFLOW_DQLP_DIR_COR */ -/* Description: correctable directory error in dqlp */ -#define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_COR_SHFT 5 -#define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_COR_MASK 0x0000000000000020 - -/* SH_MEM_ERROR_OVERFLOW_DQRP_DIR_UC */ -/* Description: uncorrectable directory error in dqrp */ -#define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_UC_SHFT 6 -#define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_UC_MASK 0x0000000000000040 - -/* SH_MEM_ERROR_OVERFLOW_DQRP_DIR_COR */ -/* Description: correctable directory error in dqrp */ -#define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_COR_SHFT 7 -#define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_COR_MASK 0x0000000000000080 - -/* SH_MEM_ERROR_OVERFLOW_ACX_INT_HW */ -/* Description: hardware interrupt from acx */ -#define SH_MEM_ERROR_OVERFLOW_ACX_INT_HW_SHFT 8 -#define SH_MEM_ERROR_OVERFLOW_ACX_INT_HW_MASK 0x0000000000000100 - -/* SH_MEM_ERROR_OVERFLOW_ACY_INT_HW */ -/* Description: hardware interrupt from acy */ -#define SH_MEM_ERROR_OVERFLOW_ACY_INT_HW_SHFT 9 -#define SH_MEM_ERROR_OVERFLOW_ACY_INT_HW_MASK 0x0000000000000200 - -/* SH_MEM_ERROR_OVERFLOW_DIR_ACC */ -/* Description: directory memory access error */ -#define SH_MEM_ERROR_OVERFLOW_DIR_ACC_SHFT 10 -#define SH_MEM_ERROR_OVERFLOW_DIR_ACC_MASK 0x0000000000000400 - -/* SH_MEM_ERROR_OVERFLOW_DQLP_INT_UC */ -/* Description: uncorrectable interrupt from dqlp */ -#define SH_MEM_ERROR_OVERFLOW_DQLP_INT_UC_SHFT 12 -#define SH_MEM_ERROR_OVERFLOW_DQLP_INT_UC_MASK 0x0000000000001000 - -/* SH_MEM_ERROR_OVERFLOW_DQLP_INT_COR */ -/* Description: correctable interrupt from dqlp */ -#define SH_MEM_ERROR_OVERFLOW_DQLP_INT_COR_SHFT 13 -#define SH_MEM_ERROR_OVERFLOW_DQLP_INT_COR_MASK 0x0000000000002000 - -/* SH_MEM_ERROR_OVERFLOW_DQLP_INT_HW */ -/* Description: hardware interrupt from dqlp */ -#define SH_MEM_ERROR_OVERFLOW_DQLP_INT_HW_SHFT 14 -#define SH_MEM_ERROR_OVERFLOW_DQLP_INT_HW_MASK 0x0000000000004000 - -/* SH_MEM_ERROR_OVERFLOW_DQLS_INT_UC */ -/* Description: uncorrectable interrupt from dqls */ -#define SH_MEM_ERROR_OVERFLOW_DQLS_INT_UC_SHFT 16 -#define SH_MEM_ERROR_OVERFLOW_DQLS_INT_UC_MASK 0x0000000000010000 - -/* SH_MEM_ERROR_OVERFLOW_DQLS_INT_COR */ -/* Description: correctable interrupt from dqls */ -#define SH_MEM_ERROR_OVERFLOW_DQLS_INT_COR_SHFT 17 -#define SH_MEM_ERROR_OVERFLOW_DQLS_INT_COR_MASK 0x0000000000020000 - -/* SH_MEM_ERROR_OVERFLOW_DQLS_INT_HW */ -/* Description: hardware interrupt from dqls */ -#define SH_MEM_ERROR_OVERFLOW_DQLS_INT_HW_SHFT 18 -#define SH_MEM_ERROR_OVERFLOW_DQLS_INT_HW_MASK 0x0000000000040000 - -/* SH_MEM_ERROR_OVERFLOW_DQRP_INT_UC */ -/* Description: uncorrectable interrupt from dqrp */ -#define SH_MEM_ERROR_OVERFLOW_DQRP_INT_UC_SHFT 20 -#define SH_MEM_ERROR_OVERFLOW_DQRP_INT_UC_MASK 0x0000000000100000 - -/* SH_MEM_ERROR_OVERFLOW_DQRP_INT_COR */ -/* Description: correctable interrupt from dqrp */ -#define SH_MEM_ERROR_OVERFLOW_DQRP_INT_COR_SHFT 21 -#define SH_MEM_ERROR_OVERFLOW_DQRP_INT_COR_MASK 0x0000000000200000 - -/* SH_MEM_ERROR_OVERFLOW_DQRP_INT_HW */ -/* Description: hardware interrupt from dqrp */ -#define SH_MEM_ERROR_OVERFLOW_DQRP_INT_HW_SHFT 22 -#define SH_MEM_ERROR_OVERFLOW_DQRP_INT_HW_MASK 0x0000000000400000 - -/* SH_MEM_ERROR_OVERFLOW_DQRS_INT_UC */ -/* Description: uncorrectable interrupt from dqrs */ -#define SH_MEM_ERROR_OVERFLOW_DQRS_INT_UC_SHFT 24 -#define SH_MEM_ERROR_OVERFLOW_DQRS_INT_UC_MASK 0x0000000001000000 - -/* SH_MEM_ERROR_OVERFLOW_DQRS_INT_COR */ -/* Description: correctable interrupt from dqrs */ -#define SH_MEM_ERROR_OVERFLOW_DQRS_INT_COR_SHFT 25 -#define SH_MEM_ERROR_OVERFLOW_DQRS_INT_COR_MASK 0x0000000002000000 - -/* SH_MEM_ERROR_OVERFLOW_DQRS_INT_HW */ -/* Description: hardware interrupt from dqrs */ -#define SH_MEM_ERROR_OVERFLOW_DQRS_INT_HW_SHFT 26 -#define SH_MEM_ERROR_OVERFLOW_DQRS_INT_HW_MASK 0x0000000004000000 - -/* SH_MEM_ERROR_OVERFLOW_PI_REPLY_OVERFLOW */ -/* Description: too many reply packets came from pi */ -#define SH_MEM_ERROR_OVERFLOW_PI_REPLY_OVERFLOW_SHFT 28 -#define SH_MEM_ERROR_OVERFLOW_PI_REPLY_OVERFLOW_MASK 0x0000000010000000 - -/* SH_MEM_ERROR_OVERFLOW_XN_REPLY_OVERFLOW */ -/* Description: too many reply packets came from xn */ -#define SH_MEM_ERROR_OVERFLOW_XN_REPLY_OVERFLOW_SHFT 29 -#define SH_MEM_ERROR_OVERFLOW_XN_REPLY_OVERFLOW_MASK 0x0000000020000000 - -/* SH_MEM_ERROR_OVERFLOW_PI_REQUEST_OVERFLOW */ -/* Description: too many request packets came from pi */ -#define SH_MEM_ERROR_OVERFLOW_PI_REQUEST_OVERFLOW_SHFT 30 -#define SH_MEM_ERROR_OVERFLOW_PI_REQUEST_OVERFLOW_MASK 0x0000000040000000 - -/* SH_MEM_ERROR_OVERFLOW_XN_REQUEST_OVERFLOW */ -/* Description: too many request packets came from xn */ -#define SH_MEM_ERROR_OVERFLOW_XN_REQUEST_OVERFLOW_SHFT 31 -#define SH_MEM_ERROR_OVERFLOW_XN_REQUEST_OVERFLOW_MASK 0x0000000080000000 - -/* SH_MEM_ERROR_OVERFLOW_RED_BLACK_ERR_TIMEOUT */ -/* Description: red black scheme did not clean up soon enough */ -#define SH_MEM_ERROR_OVERFLOW_RED_BLACK_ERR_TIMEOUT_SHFT 32 -#define SH_MEM_ERROR_OVERFLOW_RED_BLACK_ERR_TIMEOUT_MASK 0x0000000100000000 - -/* SH_MEM_ERROR_OVERFLOW_PI_PKT_SIZE */ -/* Description: received data bearing packet from pi with wrong siz */ -#define SH_MEM_ERROR_OVERFLOW_PI_PKT_SIZE_SHFT 33 -#define SH_MEM_ERROR_OVERFLOW_PI_PKT_SIZE_MASK 0x0000000200000000 - -/* SH_MEM_ERROR_OVERFLOW_XN_PKT_SIZE */ -/* Description: received data bearing packet from xn with wrong siz */ -#define SH_MEM_ERROR_OVERFLOW_XN_PKT_SIZE_SHFT 34 -#define SH_MEM_ERROR_OVERFLOW_XN_PKT_SIZE_MASK 0x0000000400000000 - -/* ==================================================================== */ -/* Register "SH_MEM_ERROR_OVERFLOW_ALIAS" */ -/* Memory error flags clear alias */ -/* ==================================================================== */ - -#define SH_MEM_ERROR_OVERFLOW_ALIAS 0x00000001000000d0 - -/* ==================================================================== */ -/* Register "SH_MEM_ERROR_MASK" */ -/* Memory error flags */ -/* ==================================================================== */ - -#define SH_MEM_ERROR_MASK 0x00000001000000d8 -#define SH_MEM_ERROR_MASK_MASK 0x00000007f77777ff -#define SH_MEM_ERROR_MASK_INIT 0x00000007f77773ff - -/* SH_MEM_ERROR_MASK_ILLEGAL_CMD */ -/* Description: illegal command error */ -#define SH_MEM_ERROR_MASK_ILLEGAL_CMD_SHFT 0 -#define SH_MEM_ERROR_MASK_ILLEGAL_CMD_MASK 0x0000000000000001 - -/* SH_MEM_ERROR_MASK_NONEXIST_ADDR */ -/* Description: non-existent memory error */ -#define SH_MEM_ERROR_MASK_NONEXIST_ADDR_SHFT 1 -#define SH_MEM_ERROR_MASK_NONEXIST_ADDR_MASK 0x0000000000000002 - -/* SH_MEM_ERROR_MASK_DQLP_DIR_PERR */ -/* Description: directory protocol error in dqlp */ -#define SH_MEM_ERROR_MASK_DQLP_DIR_PERR_SHFT 2 -#define SH_MEM_ERROR_MASK_DQLP_DIR_PERR_MASK 0x0000000000000004 - -/* SH_MEM_ERROR_MASK_DQRP_DIR_PERR */ -/* Description: directory protocol error in dqrp */ -#define SH_MEM_ERROR_MASK_DQRP_DIR_PERR_SHFT 3 -#define SH_MEM_ERROR_MASK_DQRP_DIR_PERR_MASK 0x0000000000000008 - -/* SH_MEM_ERROR_MASK_DQLP_DIR_UC */ -/* Description: uncorrectable directory error in dqlp */ -#define SH_MEM_ERROR_MASK_DQLP_DIR_UC_SHFT 4 -#define SH_MEM_ERROR_MASK_DQLP_DIR_UC_MASK 0x0000000000000010 - -/* SH_MEM_ERROR_MASK_DQLP_DIR_COR */ -/* Description: correctable directory error in dqlp */ -#define SH_MEM_ERROR_MASK_DQLP_DIR_COR_SHFT 5 -#define SH_MEM_ERROR_MASK_DQLP_DIR_COR_MASK 0x0000000000000020 - -/* SH_MEM_ERROR_MASK_DQRP_DIR_UC */ -/* Description: uncorrectable directory error in dqrp */ -#define SH_MEM_ERROR_MASK_DQRP_DIR_UC_SHFT 6 -#define SH_MEM_ERROR_MASK_DQRP_DIR_UC_MASK 0x0000000000000040 - -/* SH_MEM_ERROR_MASK_DQRP_DIR_COR */ -/* Description: correctable directory error in dqrp */ -#define SH_MEM_ERROR_MASK_DQRP_DIR_COR_SHFT 7 -#define SH_MEM_ERROR_MASK_DQRP_DIR_COR_MASK 0x0000000000000080 - -/* SH_MEM_ERROR_MASK_ACX_INT_HW */ -/* Description: hardware interrupt from acx */ -#define SH_MEM_ERROR_MASK_ACX_INT_HW_SHFT 8 -#define SH_MEM_ERROR_MASK_ACX_INT_HW_MASK 0x0000000000000100 - -/* SH_MEM_ERROR_MASK_ACY_INT_HW */ -/* Description: hardware interrupt from acy */ -#define SH_MEM_ERROR_MASK_ACY_INT_HW_SHFT 9 -#define SH_MEM_ERROR_MASK_ACY_INT_HW_MASK 0x0000000000000200 - -/* SH_MEM_ERROR_MASK_DIR_ACC */ -/* Description: directory memory access error */ -#define SH_MEM_ERROR_MASK_DIR_ACC_SHFT 10 -#define SH_MEM_ERROR_MASK_DIR_ACC_MASK 0x0000000000000400 - -/* SH_MEM_ERROR_MASK_DQLP_INT_UC */ -/* Description: uncorrectable interrupt from dqlp */ -#define SH_MEM_ERROR_MASK_DQLP_INT_UC_SHFT 12 -#define SH_MEM_ERROR_MASK_DQLP_INT_UC_MASK 0x0000000000001000 - -/* SH_MEM_ERROR_MASK_DQLP_INT_COR */ -/* Description: correctable interrupt from dqlp */ -#define SH_MEM_ERROR_MASK_DQLP_INT_COR_SHFT 13 -#define SH_MEM_ERROR_MASK_DQLP_INT_COR_MASK 0x0000000000002000 - -/* SH_MEM_ERROR_MASK_DQLP_INT_HW */ -/* Description: hardware interrupt from dqlp */ -#define SH_MEM_ERROR_MASK_DQLP_INT_HW_SHFT 14 -#define SH_MEM_ERROR_MASK_DQLP_INT_HW_MASK 0x0000000000004000 - -/* SH_MEM_ERROR_MASK_DQLS_INT_UC */ -/* Description: uncorrectable interrupt from dqls */ -#define SH_MEM_ERROR_MASK_DQLS_INT_UC_SHFT 16 -#define SH_MEM_ERROR_MASK_DQLS_INT_UC_MASK 0x0000000000010000 - -/* SH_MEM_ERROR_MASK_DQLS_INT_COR */ -/* Description: correctable interrupt from dqls */ -#define SH_MEM_ERROR_MASK_DQLS_INT_COR_SHFT 17 -#define SH_MEM_ERROR_MASK_DQLS_INT_COR_MASK 0x0000000000020000 - -/* SH_MEM_ERROR_MASK_DQLS_INT_HW */ -/* Description: hardware interrupt from dqls */ -#define SH_MEM_ERROR_MASK_DQLS_INT_HW_SHFT 18 -#define SH_MEM_ERROR_MASK_DQLS_INT_HW_MASK 0x0000000000040000 - -/* SH_MEM_ERROR_MASK_DQRP_INT_UC */ -/* Description: uncorrectable interrupt from dqrp */ -#define SH_MEM_ERROR_MASK_DQRP_INT_UC_SHFT 20 -#define SH_MEM_ERROR_MASK_DQRP_INT_UC_MASK 0x0000000000100000 - -/* SH_MEM_ERROR_MASK_DQRP_INT_COR */ -/* Description: correctable interrupt from dqrp */ -#define SH_MEM_ERROR_MASK_DQRP_INT_COR_SHFT 21 -#define SH_MEM_ERROR_MASK_DQRP_INT_COR_MASK 0x0000000000200000 - -/* SH_MEM_ERROR_MASK_DQRP_INT_HW */ -/* Description: hardware interrupt from dqrp */ -#define SH_MEM_ERROR_MASK_DQRP_INT_HW_SHFT 22 -#define SH_MEM_ERROR_MASK_DQRP_INT_HW_MASK 0x0000000000400000 - -/* SH_MEM_ERROR_MASK_DQRS_INT_UC */ -/* Description: uncorrectable interrupt from dqrs */ -#define SH_MEM_ERROR_MASK_DQRS_INT_UC_SHFT 24 -#define SH_MEM_ERROR_MASK_DQRS_INT_UC_MASK 0x0000000001000000 - -/* SH_MEM_ERROR_MASK_DQRS_INT_COR */ -/* Description: correctable interrupt from dqrs */ -#define SH_MEM_ERROR_MASK_DQRS_INT_COR_SHFT 25 -#define SH_MEM_ERROR_MASK_DQRS_INT_COR_MASK 0x0000000002000000 - -/* SH_MEM_ERROR_MASK_DQRS_INT_HW */ -/* Description: hardware interrupt from dqrs */ -#define SH_MEM_ERROR_MASK_DQRS_INT_HW_SHFT 26 -#define SH_MEM_ERROR_MASK_DQRS_INT_HW_MASK 0x0000000004000000 - -/* SH_MEM_ERROR_MASK_PI_REPLY_OVERFLOW */ -/* Description: too many reply packets came from pi */ -#define SH_MEM_ERROR_MASK_PI_REPLY_OVERFLOW_SHFT 28 -#define SH_MEM_ERROR_MASK_PI_REPLY_OVERFLOW_MASK 0x0000000010000000 - -/* SH_MEM_ERROR_MASK_XN_REPLY_OVERFLOW */ -/* Description: too many reply packets came from xn */ -#define SH_MEM_ERROR_MASK_XN_REPLY_OVERFLOW_SHFT 29 -#define SH_MEM_ERROR_MASK_XN_REPLY_OVERFLOW_MASK 0x0000000020000000 - -/* SH_MEM_ERROR_MASK_PI_REQUEST_OVERFLOW */ -/* Description: too many request packets came from pi */ -#define SH_MEM_ERROR_MASK_PI_REQUEST_OVERFLOW_SHFT 30 -#define SH_MEM_ERROR_MASK_PI_REQUEST_OVERFLOW_MASK 0x0000000040000000 - -/* SH_MEM_ERROR_MASK_XN_REQUEST_OVERFLOW */ -/* Description: too many request packets came from xn */ -#define SH_MEM_ERROR_MASK_XN_REQUEST_OVERFLOW_SHFT 31 -#define SH_MEM_ERROR_MASK_XN_REQUEST_OVERFLOW_MASK 0x0000000080000000 - -/* SH_MEM_ERROR_MASK_RED_BLACK_ERR_TIMEOUT */ -/* Description: red black scheme did not clean up soon enough */ -#define SH_MEM_ERROR_MASK_RED_BLACK_ERR_TIMEOUT_SHFT 32 -#define SH_MEM_ERROR_MASK_RED_BLACK_ERR_TIMEOUT_MASK 0x0000000100000000 - -/* SH_MEM_ERROR_MASK_PI_PKT_SIZE */ -/* Description: received data bearing packet from pi with wrong siz */ -#define SH_MEM_ERROR_MASK_PI_PKT_SIZE_SHFT 33 -#define SH_MEM_ERROR_MASK_PI_PKT_SIZE_MASK 0x0000000200000000 - -/* SH_MEM_ERROR_MASK_XN_PKT_SIZE */ -/* Description: received data bearing packet from xn with wrong siz */ -#define SH_MEM_ERROR_MASK_XN_PKT_SIZE_SHFT 34 -#define SH_MEM_ERROR_MASK_XN_PKT_SIZE_MASK 0x0000000400000000 - -/* ==================================================================== */ -/* Register "SH_X_DIMM_CFG" */ -/* AC Mem Config Registers */ -/* ==================================================================== */ - -#define SH_X_DIMM_CFG 0x0000000100010000 -#define SH_X_DIMM_CFG_MASK 0x0000000f7f7f7f7f -#define SH_X_DIMM_CFG_INIT 0x000000026f4f2f0f - -/* SH_X_DIMM_CFG_DIMM0_SIZE */ -/* Description: DIMM 0 DRAM size */ -#define SH_X_DIMM_CFG_DIMM0_SIZE_SHFT 0 -#define SH_X_DIMM_CFG_DIMM0_SIZE_MASK 0x0000000000000007 - -/* SH_X_DIMM_CFG_DIMM0_2BK */ -/* Description: DIMM 0 has two physical banks */ -#define SH_X_DIMM_CFG_DIMM0_2BK_SHFT 3 -#define SH_X_DIMM_CFG_DIMM0_2BK_MASK 0x0000000000000008 - -/* SH_X_DIMM_CFG_DIMM0_REV */ -/* Description: DIMM 0 physical banks reversed */ -#define SH_X_DIMM_CFG_DIMM0_REV_SHFT 4 -#define SH_X_DIMM_CFG_DIMM0_REV_MASK 0x0000000000000010 - -/* SH_X_DIMM_CFG_DIMM0_CS */ -/* Description: DIMM 0 chip select, addr[35:34] match */ -#define SH_X_DIMM_CFG_DIMM0_CS_SHFT 5 -#define SH_X_DIMM_CFG_DIMM0_CS_MASK 0x0000000000000060 - -/* SH_X_DIMM_CFG_DIMM1_SIZE */ -/* Description: DIMM 1 DRAM size */ -#define SH_X_DIMM_CFG_DIMM1_SIZE_SHFT 8 -#define SH_X_DIMM_CFG_DIMM1_SIZE_MASK 0x0000000000000700 - -/* SH_X_DIMM_CFG_DIMM1_2BK */ -/* Description: DIMM 1 has two physical banks */ -#define SH_X_DIMM_CFG_DIMM1_2BK_SHFT 11 -#define SH_X_DIMM_CFG_DIMM1_2BK_MASK 0x0000000000000800 - -/* SH_X_DIMM_CFG_DIMM1_REV */ -/* Description: DIMM 1 physical banks reversed */ -#define SH_X_DIMM_CFG_DIMM1_REV_SHFT 12 -#define SH_X_DIMM_CFG_DIMM1_REV_MASK 0x0000000000001000 - -/* SH_X_DIMM_CFG_DIMM1_CS */ -/* Description: DIMM 1 chip select, addr[35:34] match */ -#define SH_X_DIMM_CFG_DIMM1_CS_SHFT 13 -#define SH_X_DIMM_CFG_DIMM1_CS_MASK 0x0000000000006000 - -/* SH_X_DIMM_CFG_DIMM2_SIZE */ -/* Description: DIMM 2 DRAM size */ -#define SH_X_DIMM_CFG_DIMM2_SIZE_SHFT 16 -#define SH_X_DIMM_CFG_DIMM2_SIZE_MASK 0x0000000000070000 - -/* SH_X_DIMM_CFG_DIMM2_2BK */ -/* Description: DIMM 2 has two physical banks */ -#define SH_X_DIMM_CFG_DIMM2_2BK_SHFT 19 -#define SH_X_DIMM_CFG_DIMM2_2BK_MASK 0x0000000000080000 - -/* SH_X_DIMM_CFG_DIMM2_REV */ -/* Description: DIMM 2 physical banks reversed */ -#define SH_X_DIMM_CFG_DIMM2_REV_SHFT 20 -#define SH_X_DIMM_CFG_DIMM2_REV_MASK 0x0000000000100000 - -/* SH_X_DIMM_CFG_DIMM2_CS */ -/* Description: DIMM 2 chip select, addr[35:34] match */ -#define SH_X_DIMM_CFG_DIMM2_CS_SHFT 21 -#define SH_X_DIMM_CFG_DIMM2_CS_MASK 0x0000000000600000 - -/* SH_X_DIMM_CFG_DIMM3_SIZE */ -/* Description: DIMM 3 DRAM size */ -#define SH_X_DIMM_CFG_DIMM3_SIZE_SHFT 24 -#define SH_X_DIMM_CFG_DIMM3_SIZE_MASK 0x0000000007000000 - -/* SH_X_DIMM_CFG_DIMM3_2BK */ -/* Description: DIMM 3 has two physical banks */ -#define SH_X_DIMM_CFG_DIMM3_2BK_SHFT 27 -#define SH_X_DIMM_CFG_DIMM3_2BK_MASK 0x0000000008000000 - -/* SH_X_DIMM_CFG_DIMM3_REV */ -/* Description: DIMM 3 physical banks reversed */ -#define SH_X_DIMM_CFG_DIMM3_REV_SHFT 28 -#define SH_X_DIMM_CFG_DIMM3_REV_MASK 0x0000000010000000 - -/* SH_X_DIMM_CFG_DIMM3_CS */ -/* Description: DIMM 3 chip select, addr[35:34] match */ -#define SH_X_DIMM_CFG_DIMM3_CS_SHFT 29 -#define SH_X_DIMM_CFG_DIMM3_CS_MASK 0x0000000060000000 - -/* SH_X_DIMM_CFG_FREQ */ -/* Description: DIMM frequency select */ -#define SH_X_DIMM_CFG_FREQ_SHFT 32 -#define SH_X_DIMM_CFG_FREQ_MASK 0x0000000f00000000 - -/* ==================================================================== */ -/* Register "SH_Y_DIMM_CFG" */ -/* AC Mem Config Registers */ -/* ==================================================================== */ - -#define SH_Y_DIMM_CFG 0x0000000100010008 -#define SH_Y_DIMM_CFG_MASK 0x0000000f7f7f7f7f -#define SH_Y_DIMM_CFG_INIT 0x000000026f4f2f0f - -/* SH_Y_DIMM_CFG_DIMM0_SIZE */ -/* Description: DIMM 0 DRAM size */ -#define SH_Y_DIMM_CFG_DIMM0_SIZE_SHFT 0 -#define SH_Y_DIMM_CFG_DIMM0_SIZE_MASK 0x0000000000000007 - -/* SH_Y_DIMM_CFG_DIMM0_2BK */ -/* Description: DIMM 0 has two physical banks */ -#define SH_Y_DIMM_CFG_DIMM0_2BK_SHFT 3 -#define SH_Y_DIMM_CFG_DIMM0_2BK_MASK 0x0000000000000008 - -/* SH_Y_DIMM_CFG_DIMM0_REV */ -/* Description: DIMM 0 physical banks reversed */ -#define SH_Y_DIMM_CFG_DIMM0_REV_SHFT 4 -#define SH_Y_DIMM_CFG_DIMM0_REV_MASK 0x0000000000000010 - -/* SH_Y_DIMM_CFG_DIMM0_CS */ -/* Description: DIMM 0 chip select, addr[35:34] match */ -#define SH_Y_DIMM_CFG_DIMM0_CS_SHFT 5 -#define SH_Y_DIMM_CFG_DIMM0_CS_MASK 0x0000000000000060 - -/* SH_Y_DIMM_CFG_DIMM1_SIZE */ -/* Description: DIMM 1 DRAM size */ -#define SH_Y_DIMM_CFG_DIMM1_SIZE_SHFT 8 -#define SH_Y_DIMM_CFG_DIMM1_SIZE_MASK 0x0000000000000700 - -/* SH_Y_DIMM_CFG_DIMM1_2BK */ -/* Description: DIMM 1 has two physical banks */ -#define SH_Y_DIMM_CFG_DIMM1_2BK_SHFT 11 -#define SH_Y_DIMM_CFG_DIMM1_2BK_MASK 0x0000000000000800 - -/* SH_Y_DIMM_CFG_DIMM1_REV */ -/* Description: DIMM 1 physical banks reversed */ -#define SH_Y_DIMM_CFG_DIMM1_REV_SHFT 12 -#define SH_Y_DIMM_CFG_DIMM1_REV_MASK 0x0000000000001000 - -/* SH_Y_DIMM_CFG_DIMM1_CS */ -/* Description: DIMM 1 chip select, addr[35:34] match */ -#define SH_Y_DIMM_CFG_DIMM1_CS_SHFT 13 -#define SH_Y_DIMM_CFG_DIMM1_CS_MASK 0x0000000000006000 - -/* SH_Y_DIMM_CFG_DIMM2_SIZE */ -/* Description: DIMM 2 DRAM size */ -#define SH_Y_DIMM_CFG_DIMM2_SIZE_SHFT 16 -#define SH_Y_DIMM_CFG_DIMM2_SIZE_MASK 0x0000000000070000 - -/* SH_Y_DIMM_CFG_DIMM2_2BK */ -/* Description: DIMM 2 has two physical banks */ -#define SH_Y_DIMM_CFG_DIMM2_2BK_SHFT 19 -#define SH_Y_DIMM_CFG_DIMM2_2BK_MASK 0x0000000000080000 - -/* SH_Y_DIMM_CFG_DIMM2_REV */ -/* Description: DIMM 2 physical banks reversed */ -#define SH_Y_DIMM_CFG_DIMM2_REV_SHFT 20 -#define SH_Y_DIMM_CFG_DIMM2_REV_MASK 0x0000000000100000 - -/* SH_Y_DIMM_CFG_DIMM2_CS */ -/* Description: DIMM 2 chip select, addr[35:34] match */ -#define SH_Y_DIMM_CFG_DIMM2_CS_SHFT 21 -#define SH_Y_DIMM_CFG_DIMM2_CS_MASK 0x0000000000600000 - -/* SH_Y_DIMM_CFG_DIMM3_SIZE */ -/* Description: DIMM 3 DRAM size */ -#define SH_Y_DIMM_CFG_DIMM3_SIZE_SHFT 24 -#define SH_Y_DIMM_CFG_DIMM3_SIZE_MASK 0x0000000007000000 - -/* SH_Y_DIMM_CFG_DIMM3_2BK */ -/* Description: DIMM 3 has two physical banks */ -#define SH_Y_DIMM_CFG_DIMM3_2BK_SHFT 27 -#define SH_Y_DIMM_CFG_DIMM3_2BK_MASK 0x0000000008000000 - -/* SH_Y_DIMM_CFG_DIMM3_REV */ -/* Description: DIMM 3 physical banks reversed */ -#define SH_Y_DIMM_CFG_DIMM3_REV_SHFT 28 -#define SH_Y_DIMM_CFG_DIMM3_REV_MASK 0x0000000010000000 - -/* SH_Y_DIMM_CFG_DIMM3_CS */ -/* Description: DIMM 3 chip select, addr[35:34] match */ -#define SH_Y_DIMM_CFG_DIMM3_CS_SHFT 29 -#define SH_Y_DIMM_CFG_DIMM3_CS_MASK 0x0000000060000000 - -/* SH_Y_DIMM_CFG_FREQ */ -/* Description: DIMM frequency select */ -#define SH_Y_DIMM_CFG_FREQ_SHFT 32 -#define SH_Y_DIMM_CFG_FREQ_MASK 0x0000000f00000000 - -/* ==================================================================== */ -/* Register "SH_JNR_DIMM_CFG" */ -/* AC Mem Config Registers */ -/* ==================================================================== */ - -#define SH_JNR_DIMM_CFG 0x0000000100010010 -#define SH_JNR_DIMM_CFG_MASK 0x0000000f7f7f7f7f -#define SH_JNR_DIMM_CFG_INIT 0x000000026f4f2f0f - -/* SH_JNR_DIMM_CFG_DIMM0_SIZE */ -/* Description: DIMM 0 DRAM size */ -#define SH_JNR_DIMM_CFG_DIMM0_SIZE_SHFT 0 -#define SH_JNR_DIMM_CFG_DIMM0_SIZE_MASK 0x0000000000000007 - -/* SH_JNR_DIMM_CFG_DIMM0_2BK */ -/* Description: DIMM 0 has two physical banks */ -#define SH_JNR_DIMM_CFG_DIMM0_2BK_SHFT 3 -#define SH_JNR_DIMM_CFG_DIMM0_2BK_MASK 0x0000000000000008 - -/* SH_JNR_DIMM_CFG_DIMM0_REV */ -/* Description: DIMM 0 physical banks reversed */ -#define SH_JNR_DIMM_CFG_DIMM0_REV_SHFT 4 -#define SH_JNR_DIMM_CFG_DIMM0_REV_MASK 0x0000000000000010 - -/* SH_JNR_DIMM_CFG_DIMM0_CS */ -/* Description: DIMM 0 chip select, addr[35:34] match */ -#define SH_JNR_DIMM_CFG_DIMM0_CS_SHFT 5 -#define SH_JNR_DIMM_CFG_DIMM0_CS_MASK 0x0000000000000060 - -/* SH_JNR_DIMM_CFG_DIMM1_SIZE */ -/* Description: DIMM 1 DRAM size */ -#define SH_JNR_DIMM_CFG_DIMM1_SIZE_SHFT 8 -#define SH_JNR_DIMM_CFG_DIMM1_SIZE_MASK 0x0000000000000700 - -/* SH_JNR_DIMM_CFG_DIMM1_2BK */ -/* Description: DIMM 1 has two physical banks */ -#define SH_JNR_DIMM_CFG_DIMM1_2BK_SHFT 11 -#define SH_JNR_DIMM_CFG_DIMM1_2BK_MASK 0x0000000000000800 - -/* SH_JNR_DIMM_CFG_DIMM1_REV */ -/* Description: DIMM 1 physical banks reversed */ -#define SH_JNR_DIMM_CFG_DIMM1_REV_SHFT 12 -#define SH_JNR_DIMM_CFG_DIMM1_REV_MASK 0x0000000000001000 - -/* SH_JNR_DIMM_CFG_DIMM1_CS */ -/* Description: DIMM 1 chip select, addr[35:34] match */ -#define SH_JNR_DIMM_CFG_DIMM1_CS_SHFT 13 -#define SH_JNR_DIMM_CFG_DIMM1_CS_MASK 0x0000000000006000 - -/* SH_JNR_DIMM_CFG_DIMM2_SIZE */ -/* Description: DIMM 2 DRAM size */ -#define SH_JNR_DIMM_CFG_DIMM2_SIZE_SHFT 16 -#define SH_JNR_DIMM_CFG_DIMM2_SIZE_MASK 0x0000000000070000 - -/* SH_JNR_DIMM_CFG_DIMM2_2BK */ -/* Description: DIMM 2 has two physical banks */ -#define SH_JNR_DIMM_CFG_DIMM2_2BK_SHFT 19 -#define SH_JNR_DIMM_CFG_DIMM2_2BK_MASK 0x0000000000080000 - -/* SH_JNR_DIMM_CFG_DIMM2_REV */ -/* Description: DIMM 2 physical banks reversed */ -#define SH_JNR_DIMM_CFG_DIMM2_REV_SHFT 20 -#define SH_JNR_DIMM_CFG_DIMM2_REV_MASK 0x0000000000100000 - -/* SH_JNR_DIMM_CFG_DIMM2_CS */ -/* Description: DIMM 2 chip select, addr[35:34] match */ -#define SH_JNR_DIMM_CFG_DIMM2_CS_SHFT 21 -#define SH_JNR_DIMM_CFG_DIMM2_CS_MASK 0x0000000000600000 - -/* SH_JNR_DIMM_CFG_DIMM3_SIZE */ -/* Description: DIMM 3 DRAM size */ -#define SH_JNR_DIMM_CFG_DIMM3_SIZE_SHFT 24 -#define SH_JNR_DIMM_CFG_DIMM3_SIZE_MASK 0x0000000007000000 - -/* SH_JNR_DIMM_CFG_DIMM3_2BK */ -/* Description: DIMM 3 has two physical banks */ -#define SH_JNR_DIMM_CFG_DIMM3_2BK_SHFT 27 -#define SH_JNR_DIMM_CFG_DIMM3_2BK_MASK 0x0000000008000000 - -/* SH_JNR_DIMM_CFG_DIMM3_REV */ -/* Description: DIMM 3 physical banks reversed */ -#define SH_JNR_DIMM_CFG_DIMM3_REV_SHFT 28 -#define SH_JNR_DIMM_CFG_DIMM3_REV_MASK 0x0000000010000000 - -/* SH_JNR_DIMM_CFG_DIMM3_CS */ -/* Description: DIMM 3 chip select, addr[35:34] match */ -#define SH_JNR_DIMM_CFG_DIMM3_CS_SHFT 29 -#define SH_JNR_DIMM_CFG_DIMM3_CS_MASK 0x0000000060000000 - -/* SH_JNR_DIMM_CFG_FREQ */ -/* Description: DIMM frequency select */ -#define SH_JNR_DIMM_CFG_FREQ_SHFT 32 -#define SH_JNR_DIMM_CFG_FREQ_MASK 0x0000000f00000000 - -/* ==================================================================== */ -/* Register "SH_X_PHASE_CFG" */ -/* AC Phase Config Registers */ -/* ==================================================================== */ - -#define SH_X_PHASE_CFG 0x0000000100010018 -#define SH_X_PHASE_CFG_MASK 0x7fffffffffffffff -#define SH_X_PHASE_CFG_INIT 0x0000000000000000 - -/* SH_X_PHASE_CFG_LD_A */ -/* Description: Address, control load core clock A latch */ -#define SH_X_PHASE_CFG_LD_A_SHFT 0 -#define SH_X_PHASE_CFG_LD_A_MASK 0x000000000000001f - -/* SH_X_PHASE_CFG_LD_B */ -/* Description: Address, control load core clock B latch */ -#define SH_X_PHASE_CFG_LD_B_SHFT 5 -#define SH_X_PHASE_CFG_LD_B_MASK 0x00000000000003e0 - -/* SH_X_PHASE_CFG_DQ_LD_A */ -/* Description: DATA MCI load core clock A latch */ -#define SH_X_PHASE_CFG_DQ_LD_A_SHFT 10 -#define SH_X_PHASE_CFG_DQ_LD_A_MASK 0x0000000000007c00 - -/* SH_X_PHASE_CFG_DQ_LD_B */ -/* Description: DATA MCI load core clock B latch */ -#define SH_X_PHASE_CFG_DQ_LD_B_SHFT 15 -#define SH_X_PHASE_CFG_DQ_LD_B_MASK 0x00000000000f8000 - -/* SH_X_PHASE_CFG_HOLD */ -/* Description: Hold request on core clock phase */ -#define SH_X_PHASE_CFG_HOLD_SHFT 20 -#define SH_X_PHASE_CFG_HOLD_MASK 0x0000000001f00000 - -/* SH_X_PHASE_CFG_HOLD_REQ */ -/* Description: Hold next request on core clock phase */ -#define SH_X_PHASE_CFG_HOLD_REQ_SHFT 25 -#define SH_X_PHASE_CFG_HOLD_REQ_MASK 0x000000003e000000 - -/* SH_X_PHASE_CFG_ADD_CP */ -/* Description: add delay clock period to dqct delay chain on phase */ -#define SH_X_PHASE_CFG_ADD_CP_SHFT 30 -#define SH_X_PHASE_CFG_ADD_CP_MASK 0x00000007c0000000 - -/* SH_X_PHASE_CFG_BUBBLE_EN */ -/* Description: bubble, idle core clock to wait for memory clock */ -#define SH_X_PHASE_CFG_BUBBLE_EN_SHFT 35 -#define SH_X_PHASE_CFG_BUBBLE_EN_MASK 0x000000f800000000 - -/* SH_X_PHASE_CFG_PHA_BUBBLE */ -/* Description: MMR phaseA bubble value */ -#define SH_X_PHASE_CFG_PHA_BUBBLE_SHFT 40 -#define SH_X_PHASE_CFG_PHA_BUBBLE_MASK 0x0000070000000000 - -/* SH_X_PHASE_CFG_PHB_BUBBLE */ -/* Description: MMR phaseB bubble value */ -#define SH_X_PHASE_CFG_PHB_BUBBLE_SHFT 43 -#define SH_X_PHASE_CFG_PHB_BUBBLE_MASK 0x0000380000000000 - -/* SH_X_PHASE_CFG_PHC_BUBBLE */ -/* Description: MMR phaseC bubble value */ -#define SH_X_PHASE_CFG_PHC_BUBBLE_SHFT 46 -#define SH_X_PHASE_CFG_PHC_BUBBLE_MASK 0x0001c00000000000 - -/* SH_X_PHASE_CFG_PHD_BUBBLE */ -/* Description: MMR phaseD bubble value */ -#define SH_X_PHASE_CFG_PHD_BUBBLE_SHFT 49 -#define SH_X_PHASE_CFG_PHD_BUBBLE_MASK 0x000e000000000000 - -/* SH_X_PHASE_CFG_PHE_BUBBLE */ -/* Description: MMR phaseE bubble value */ -#define SH_X_PHASE_CFG_PHE_BUBBLE_SHFT 52 -#define SH_X_PHASE_CFG_PHE_BUBBLE_MASK 0x0070000000000000 - -/* SH_X_PHASE_CFG_SEL_A */ -/* Description: address,control select A memory clock latch */ -#define SH_X_PHASE_CFG_SEL_A_SHFT 55 -#define SH_X_PHASE_CFG_SEL_A_MASK 0x0780000000000000 - -/* SH_X_PHASE_CFG_DQ_SEL_A */ -/* Description: DATA MCI select A memory clock latch */ -#define SH_X_PHASE_CFG_DQ_SEL_A_SHFT 59 -#define SH_X_PHASE_CFG_DQ_SEL_A_MASK 0x7800000000000000 - -/* ==================================================================== */ -/* Register "SH_X_CFG" */ -/* AC Config Registers */ -/* ==================================================================== */ - -#define SH_X_CFG 0x0000000100010020 -#define SH_X_CFG_MASK 0xffffffffffffffff -#define SH_X_CFG_INIT 0x108443103322100c - -/* SH_X_CFG_MODE_SERIAL */ -/* Description: Arbque arbitration in serial mode */ -#define SH_X_CFG_MODE_SERIAL_SHFT 0 -#define SH_X_CFG_MODE_SERIAL_MASK 0x0000000000000001 - -/* SH_X_CFG_DIRC_RANDOM_REPLACEMENT */ -/* Description: Directory cache random replacement */ -#define SH_X_CFG_DIRC_RANDOM_REPLACEMENT_SHFT 1 -#define SH_X_CFG_DIRC_RANDOM_REPLACEMENT_MASK 0x0000000000000002 - -/* SH_X_CFG_DIR_COUNTER_INIT */ -/* Description: Dir counter initial value */ -#define SH_X_CFG_DIR_COUNTER_INIT_SHFT 2 -#define SH_X_CFG_DIR_COUNTER_INIT_MASK 0x00000000000000fc - -/* SH_X_CFG_TA_DLYS */ -/* Description: Turn around delays */ -#define SH_X_CFG_TA_DLYS_SHFT 8 -#define SH_X_CFG_TA_DLYS_MASK 0x000000ffffffff00 - -/* SH_X_CFG_DA_BB_CLR */ -/* Description: Bank busy CPs for a data read request */ -#define SH_X_CFG_DA_BB_CLR_SHFT 40 -#define SH_X_CFG_DA_BB_CLR_MASK 0x00000f0000000000 - -/* SH_X_CFG_DC_BB_CLR */ -/* Description: Bank busy CPs for a directory cache read request */ -#define SH_X_CFG_DC_BB_CLR_SHFT 44 -#define SH_X_CFG_DC_BB_CLR_MASK 0x0000f00000000000 - -/* SH_X_CFG_WT_BB_CLR */ -/* Description: Bank busy CPs for all write request */ -#define SH_X_CFG_WT_BB_CLR_SHFT 48 -#define SH_X_CFG_WT_BB_CLR_MASK 0x000f000000000000 - -/* SH_X_CFG_SSO_WT_EN */ -/* Description: Simultaneous switching enabled on output data pins */ -#define SH_X_CFG_SSO_WT_EN_SHFT 52 -#define SH_X_CFG_SSO_WT_EN_MASK 0x0010000000000000 - -/* SH_X_CFG_TRCD2_EN */ -/* Description: Trcd, ras to cas delay of 2 CPs enabled */ -#define SH_X_CFG_TRCD2_EN_SHFT 53 -#define SH_X_CFG_TRCD2_EN_MASK 0x0020000000000000 - -/* SH_X_CFG_TRCD4_EN */ -/* Description: Trcd, ras to case delay of 4 CPs enabled */ -#define SH_X_CFG_TRCD4_EN_SHFT 54 -#define SH_X_CFG_TRCD4_EN_MASK 0x0040000000000000 - -/* SH_X_CFG_REQ_CNTR_DIS */ -/* Description: Request delay counter disabled */ -#define SH_X_CFG_REQ_CNTR_DIS_SHFT 55 -#define SH_X_CFG_REQ_CNTR_DIS_MASK 0x0080000000000000 - -/* SH_X_CFG_REQ_CNTR_VAL */ -/* Description: Request counter delay value in CPs */ -#define SH_X_CFG_REQ_CNTR_VAL_SHFT 56 -#define SH_X_CFG_REQ_CNTR_VAL_MASK 0x3f00000000000000 - -/* SH_X_CFG_INV_CAS_ADDR */ -/* Description: Invert cas address bits 3 to 7 */ -#define SH_X_CFG_INV_CAS_ADDR_SHFT 62 -#define SH_X_CFG_INV_CAS_ADDR_MASK 0x4000000000000000 - -/* SH_X_CFG_CLR_DIR_CACHE */ -/* Description: Clear directory cache tags */ -#define SH_X_CFG_CLR_DIR_CACHE_SHFT 63 -#define SH_X_CFG_CLR_DIR_CACHE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_X_DQCT_CFG" */ -/* AC Config Registers */ -/* ==================================================================== */ - -#define SH_X_DQCT_CFG 0x0000000100010028 -#define SH_X_DQCT_CFG_MASK 0x0000000000ffffff -#define SH_X_DQCT_CFG_INIT 0x0000000000585418 - -/* SH_X_DQCT_CFG_RD_SEL */ -/* Description: Read data select */ -#define SH_X_DQCT_CFG_RD_SEL_SHFT 0 -#define SH_X_DQCT_CFG_RD_SEL_MASK 0x000000000000000f - -/* SH_X_DQCT_CFG_WT_SEL */ -/* Description: Write data select */ -#define SH_X_DQCT_CFG_WT_SEL_SHFT 4 -#define SH_X_DQCT_CFG_WT_SEL_MASK 0x00000000000000f0 - -/* SH_X_DQCT_CFG_DTA_RD_SEL */ -/* Description: Data ready read select */ -#define SH_X_DQCT_CFG_DTA_RD_SEL_SHFT 8 -#define SH_X_DQCT_CFG_DTA_RD_SEL_MASK 0x0000000000000f00 - -/* SH_X_DQCT_CFG_DTA_WT_SEL */ -/* Description: Data ready write select */ -#define SH_X_DQCT_CFG_DTA_WT_SEL_SHFT 12 -#define SH_X_DQCT_CFG_DTA_WT_SEL_MASK 0x000000000000f000 - -/* SH_X_DQCT_CFG_DIR_RD_SEL */ -/* Description: Dir ready read select */ -#define SH_X_DQCT_CFG_DIR_RD_SEL_SHFT 16 -#define SH_X_DQCT_CFG_DIR_RD_SEL_MASK 0x00000000000f0000 - -/* SH_X_DQCT_CFG_MDIR_RD_SEL */ -/* Description: Dir ready read select */ -#define SH_X_DQCT_CFG_MDIR_RD_SEL_SHFT 20 -#define SH_X_DQCT_CFG_MDIR_RD_SEL_MASK 0x0000000000f00000 - -/* ==================================================================== */ -/* Register "SH_X_REFRESH_CONTROL" */ -/* Refresh Control Register */ -/* ==================================================================== */ - -#define SH_X_REFRESH_CONTROL 0x0000000100010030 -#define SH_X_REFRESH_CONTROL_MASK 0x000000000fffffff -#define SH_X_REFRESH_CONTROL_INIT 0x00000000009cc300 - -/* SH_X_REFRESH_CONTROL_ENABLE */ -/* Description: Refresh enable */ -#define SH_X_REFRESH_CONTROL_ENABLE_SHFT 0 -#define SH_X_REFRESH_CONTROL_ENABLE_MASK 0x00000000000000ff - -/* SH_X_REFRESH_CONTROL_INTERVAL */ -/* Description: Refresh interval in core CPs */ -#define SH_X_REFRESH_CONTROL_INTERVAL_SHFT 8 -#define SH_X_REFRESH_CONTROL_INTERVAL_MASK 0x000000000001ff00 - -/* SH_X_REFRESH_CONTROL_HOLD */ -/* Description: Refresh hold */ -#define SH_X_REFRESH_CONTROL_HOLD_SHFT 17 -#define SH_X_REFRESH_CONTROL_HOLD_MASK 0x00000000007e0000 - -/* SH_X_REFRESH_CONTROL_INTERLEAVE */ -/* Description: Refresh interleave */ -#define SH_X_REFRESH_CONTROL_INTERLEAVE_SHFT 23 -#define SH_X_REFRESH_CONTROL_INTERLEAVE_MASK 0x0000000000800000 - -/* SH_X_REFRESH_CONTROL_HALF_RATE */ -/* Description: Refresh half rate */ -#define SH_X_REFRESH_CONTROL_HALF_RATE_SHFT 24 -#define SH_X_REFRESH_CONTROL_HALF_RATE_MASK 0x000000000f000000 - -/* ==================================================================== */ -/* Register "SH_Y_PHASE_CFG" */ -/* AC Phase Config Registers */ -/* ==================================================================== */ - -#define SH_Y_PHASE_CFG 0x0000000100010038 -#define SH_Y_PHASE_CFG_MASK 0x7fffffffffffffff -#define SH_Y_PHASE_CFG_INIT 0x0000000000000000 - -/* SH_Y_PHASE_CFG_LD_A */ -/* Description: Address, control load core clock A latch */ -#define SH_Y_PHASE_CFG_LD_A_SHFT 0 -#define SH_Y_PHASE_CFG_LD_A_MASK 0x000000000000001f - -/* SH_Y_PHASE_CFG_LD_B */ -/* Description: Address, control load core clock B latch */ -#define SH_Y_PHASE_CFG_LD_B_SHFT 5 -#define SH_Y_PHASE_CFG_LD_B_MASK 0x00000000000003e0 - -/* SH_Y_PHASE_CFG_DQ_LD_A */ -/* Description: DATA MCI load core clock A latch */ -#define SH_Y_PHASE_CFG_DQ_LD_A_SHFT 10 -#define SH_Y_PHASE_CFG_DQ_LD_A_MASK 0x0000000000007c00 - -/* SH_Y_PHASE_CFG_DQ_LD_B */ -/* Description: DATA MCI load core clock B latch */ -#define SH_Y_PHASE_CFG_DQ_LD_B_SHFT 15 -#define SH_Y_PHASE_CFG_DQ_LD_B_MASK 0x00000000000f8000 - -/* SH_Y_PHASE_CFG_HOLD */ -/* Description: Hold request on core clock phase */ -#define SH_Y_PHASE_CFG_HOLD_SHFT 20 -#define SH_Y_PHASE_CFG_HOLD_MASK 0x0000000001f00000 - -/* SH_Y_PHASE_CFG_HOLD_REQ */ -/* Description: Hold next request on core clock phase */ -#define SH_Y_PHASE_CFG_HOLD_REQ_SHFT 25 -#define SH_Y_PHASE_CFG_HOLD_REQ_MASK 0x000000003e000000 - -/* SH_Y_PHASE_CFG_ADD_CP */ -/* Description: add delay clock period to dqct delay chain on phase */ -#define SH_Y_PHASE_CFG_ADD_CP_SHFT 30 -#define SH_Y_PHASE_CFG_ADD_CP_MASK 0x00000007c0000000 - -/* SH_Y_PHASE_CFG_BUBBLE_EN */ -/* Description: bubble, idle core clock to wait for memory clock */ -#define SH_Y_PHASE_CFG_BUBBLE_EN_SHFT 35 -#define SH_Y_PHASE_CFG_BUBBLE_EN_MASK 0x000000f800000000 - -/* SH_Y_PHASE_CFG_PHA_BUBBLE */ -/* Description: MMR phaseA bubble value */ -#define SH_Y_PHASE_CFG_PHA_BUBBLE_SHFT 40 -#define SH_Y_PHASE_CFG_PHA_BUBBLE_MASK 0x0000070000000000 - -/* SH_Y_PHASE_CFG_PHB_BUBBLE */ -/* Description: MMR phaseB bubble value */ -#define SH_Y_PHASE_CFG_PHB_BUBBLE_SHFT 43 -#define SH_Y_PHASE_CFG_PHB_BUBBLE_MASK 0x0000380000000000 - -/* SH_Y_PHASE_CFG_PHC_BUBBLE */ -/* Description: MMR phaseC bubble value */ -#define SH_Y_PHASE_CFG_PHC_BUBBLE_SHFT 46 -#define SH_Y_PHASE_CFG_PHC_BUBBLE_MASK 0x0001c00000000000 - -/* SH_Y_PHASE_CFG_PHD_BUBBLE */ -/* Description: MMR phaseD bubble value */ -#define SH_Y_PHASE_CFG_PHD_BUBBLE_SHFT 49 -#define SH_Y_PHASE_CFG_PHD_BUBBLE_MASK 0x000e000000000000 - -/* SH_Y_PHASE_CFG_PHE_BUBBLE */ -/* Description: MMR phaseE bubble value */ -#define SH_Y_PHASE_CFG_PHE_BUBBLE_SHFT 52 -#define SH_Y_PHASE_CFG_PHE_BUBBLE_MASK 0x0070000000000000 - -/* SH_Y_PHASE_CFG_SEL_A */ -/* Description: address,control select A memory clock latch */ -#define SH_Y_PHASE_CFG_SEL_A_SHFT 55 -#define SH_Y_PHASE_CFG_SEL_A_MASK 0x0780000000000000 - -/* SH_Y_PHASE_CFG_DQ_SEL_A */ -/* Description: DATA MCI select A memory clock latch */ -#define SH_Y_PHASE_CFG_DQ_SEL_A_SHFT 59 -#define SH_Y_PHASE_CFG_DQ_SEL_A_MASK 0x7800000000000000 - -/* ==================================================================== */ -/* Register "SH_Y_CFG" */ -/* AC Config Registers */ -/* ==================================================================== */ - -#define SH_Y_CFG 0x0000000100010040 -#define SH_Y_CFG_MASK 0xffffffffffffffff -#define SH_Y_CFG_INIT 0x108443103322100c - -/* SH_Y_CFG_MODE_SERIAL */ -/* Description: Arbque arbitration in serial mode */ -#define SH_Y_CFG_MODE_SERIAL_SHFT 0 -#define SH_Y_CFG_MODE_SERIAL_MASK 0x0000000000000001 - -/* SH_Y_CFG_DIRC_RANDOM_REPLACEMENT */ -/* Description: Directory cache random replacement */ -#define SH_Y_CFG_DIRC_RANDOM_REPLACEMENT_SHFT 1 -#define SH_Y_CFG_DIRC_RANDOM_REPLACEMENT_MASK 0x0000000000000002 - -/* SH_Y_CFG_DIR_COUNTER_INIT */ -/* Description: Dir counter initial value */ -#define SH_Y_CFG_DIR_COUNTER_INIT_SHFT 2 -#define SH_Y_CFG_DIR_COUNTER_INIT_MASK 0x00000000000000fc - -/* SH_Y_CFG_TA_DLYS */ -/* Description: Turn around delays */ -#define SH_Y_CFG_TA_DLYS_SHFT 8 -#define SH_Y_CFG_TA_DLYS_MASK 0x000000ffffffff00 - -/* SH_Y_CFG_DA_BB_CLR */ -/* Description: Bank busy CPs for a data read request */ -#define SH_Y_CFG_DA_BB_CLR_SHFT 40 -#define SH_Y_CFG_DA_BB_CLR_MASK 0x00000f0000000000 - -/* SH_Y_CFG_DC_BB_CLR */ -/* Description: Bank busy CPs for a directory cache read request */ -#define SH_Y_CFG_DC_BB_CLR_SHFT 44 -#define SH_Y_CFG_DC_BB_CLR_MASK 0x0000f00000000000 - -/* SH_Y_CFG_WT_BB_CLR */ -/* Description: Bank busy CPs for all write request */ -#define SH_Y_CFG_WT_BB_CLR_SHFT 48 -#define SH_Y_CFG_WT_BB_CLR_MASK 0x000f000000000000 - -/* SH_Y_CFG_SSO_WT_EN */ -/* Description: Simultaneous switching enabled on output data pins */ -#define SH_Y_CFG_SSO_WT_EN_SHFT 52 -#define SH_Y_CFG_SSO_WT_EN_MASK 0x0010000000000000 - -/* SH_Y_CFG_TRCD2_EN */ -/* Description: Trcd, ras to cas delay of 2 CPs enabled */ -#define SH_Y_CFG_TRCD2_EN_SHFT 53 -#define SH_Y_CFG_TRCD2_EN_MASK 0x0020000000000000 - -/* SH_Y_CFG_TRCD4_EN */ -/* Description: Trcd, ras to case delay of 4 CPs enabled */ -#define SH_Y_CFG_TRCD4_EN_SHFT 54 -#define SH_Y_CFG_TRCD4_EN_MASK 0x0040000000000000 - -/* SH_Y_CFG_REQ_CNTR_DIS */ -/* Description: Request delay counter disabled */ -#define SH_Y_CFG_REQ_CNTR_DIS_SHFT 55 -#define SH_Y_CFG_REQ_CNTR_DIS_MASK 0x0080000000000000 - -/* SH_Y_CFG_REQ_CNTR_VAL */ -/* Description: Request counter delay value in CPs */ -#define SH_Y_CFG_REQ_CNTR_VAL_SHFT 56 -#define SH_Y_CFG_REQ_CNTR_VAL_MASK 0x3f00000000000000 - -/* SH_Y_CFG_INV_CAS_ADDR */ -/* Description: Invert cas address bits 3 to 7 */ -#define SH_Y_CFG_INV_CAS_ADDR_SHFT 62 -#define SH_Y_CFG_INV_CAS_ADDR_MASK 0x4000000000000000 - -/* SH_Y_CFG_CLR_DIR_CACHE */ -/* Description: Clear directory cache tags */ -#define SH_Y_CFG_CLR_DIR_CACHE_SHFT 63 -#define SH_Y_CFG_CLR_DIR_CACHE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_Y_DQCT_CFG" */ -/* AC Config Registers */ -/* ==================================================================== */ - -#define SH_Y_DQCT_CFG 0x0000000100010048 -#define SH_Y_DQCT_CFG_MASK 0x0000000000ffffff -#define SH_Y_DQCT_CFG_INIT 0x0000000000585418 - -/* SH_Y_DQCT_CFG_RD_SEL */ -/* Description: Read data select */ -#define SH_Y_DQCT_CFG_RD_SEL_SHFT 0 -#define SH_Y_DQCT_CFG_RD_SEL_MASK 0x000000000000000f - -/* SH_Y_DQCT_CFG_WT_SEL */ -/* Description: Write data select */ -#define SH_Y_DQCT_CFG_WT_SEL_SHFT 4 -#define SH_Y_DQCT_CFG_WT_SEL_MASK 0x00000000000000f0 - -/* SH_Y_DQCT_CFG_DTA_RD_SEL */ -/* Description: Data ready read select */ -#define SH_Y_DQCT_CFG_DTA_RD_SEL_SHFT 8 -#define SH_Y_DQCT_CFG_DTA_RD_SEL_MASK 0x0000000000000f00 - -/* SH_Y_DQCT_CFG_DTA_WT_SEL */ -/* Description: Data ready write select */ -#define SH_Y_DQCT_CFG_DTA_WT_SEL_SHFT 12 -#define SH_Y_DQCT_CFG_DTA_WT_SEL_MASK 0x000000000000f000 - -/* SH_Y_DQCT_CFG_DIR_RD_SEL */ -/* Description: Dir ready read select */ -#define SH_Y_DQCT_CFG_DIR_RD_SEL_SHFT 16 -#define SH_Y_DQCT_CFG_DIR_RD_SEL_MASK 0x00000000000f0000 - -/* SH_Y_DQCT_CFG_MDIR_RD_SEL */ -/* Description: Dir ready read select */ -#define SH_Y_DQCT_CFG_MDIR_RD_SEL_SHFT 20 -#define SH_Y_DQCT_CFG_MDIR_RD_SEL_MASK 0x0000000000f00000 - -/* ==================================================================== */ -/* Register "SH_Y_REFRESH_CONTROL" */ -/* Refresh Control Register */ -/* ==================================================================== */ - -#define SH_Y_REFRESH_CONTROL 0x0000000100010050 -#define SH_Y_REFRESH_CONTROL_MASK 0x000000000fffffff -#define SH_Y_REFRESH_CONTROL_INIT 0x00000000009cc300 - -/* SH_Y_REFRESH_CONTROL_ENABLE */ -/* Description: Refresh enable */ -#define SH_Y_REFRESH_CONTROL_ENABLE_SHFT 0 -#define SH_Y_REFRESH_CONTROL_ENABLE_MASK 0x00000000000000ff - -/* SH_Y_REFRESH_CONTROL_INTERVAL */ -/* Description: Refresh interval in core CPs */ -#define SH_Y_REFRESH_CONTROL_INTERVAL_SHFT 8 -#define SH_Y_REFRESH_CONTROL_INTERVAL_MASK 0x000000000001ff00 - -/* SH_Y_REFRESH_CONTROL_HOLD */ -/* Description: Refresh hold */ -#define SH_Y_REFRESH_CONTROL_HOLD_SHFT 17 -#define SH_Y_REFRESH_CONTROL_HOLD_MASK 0x00000000007e0000 - -/* SH_Y_REFRESH_CONTROL_INTERLEAVE */ -/* Description: Refresh interleave */ -#define SH_Y_REFRESH_CONTROL_INTERLEAVE_SHFT 23 -#define SH_Y_REFRESH_CONTROL_INTERLEAVE_MASK 0x0000000000800000 - -/* SH_Y_REFRESH_CONTROL_HALF_RATE */ -/* Description: Refresh half rate */ -#define SH_Y_REFRESH_CONTROL_HALF_RATE_SHFT 24 -#define SH_Y_REFRESH_CONTROL_HALF_RATE_MASK 0x000000000f000000 - -/* ==================================================================== */ -/* Register "SH_MEM_RED_BLACK" */ -/* MD fairness watchdog timers */ -/* ==================================================================== */ - -#define SH_MEM_RED_BLACK 0x0000000100010058 -#define SH_MEM_RED_BLACK_MASK 0x000fffffffffffff -#define SH_MEM_RED_BLACK_INIT 0x0000000040000400 - -/* SH_MEM_RED_BLACK_TIME */ -/* Description: Clocks to tag references with a given color */ -#define SH_MEM_RED_BLACK_TIME_SHFT 0 -#define SH_MEM_RED_BLACK_TIME_MASK 0x000000000000ffff - -/* SH_MEM_RED_BLACK_ERR_TIME */ -/* Description: Max clocks to wait after red/black change for old c */ -/* olor to clear. */ -#define SH_MEM_RED_BLACK_ERR_TIME_SHFT 16 -#define SH_MEM_RED_BLACK_ERR_TIME_MASK 0x000fffffffff0000 - -/* ==================================================================== */ -/* Register "SH_MISC_MEM_CFG" */ -/* ==================================================================== */ - -#define SH_MISC_MEM_CFG 0x0000000100010060 -#define SH_MISC_MEM_CFG_MASK 0x0013f1f1fff3f3ff -#define SH_MISC_MEM_CFG_INIT 0x0000000000010107 - -/* SH_MISC_MEM_CFG_EXPRESS_HEADER_ENABLE */ -/* Description: enables the use of express headers from md to pi */ -#define SH_MISC_MEM_CFG_EXPRESS_HEADER_ENABLE_SHFT 0 -#define SH_MISC_MEM_CFG_EXPRESS_HEADER_ENABLE_MASK 0x0000000000000001 - -/* SH_MISC_MEM_CFG_SPEC_HEADER_ENABLE */ -/* Description: enables the use of speculative headers from md to p */ -#define SH_MISC_MEM_CFG_SPEC_HEADER_ENABLE_SHFT 1 -#define SH_MISC_MEM_CFG_SPEC_HEADER_ENABLE_MASK 0x0000000000000002 - -/* SH_MISC_MEM_CFG_JNR_BYPASS_ENABLE */ -/* Description: enables bypass path for requests going through ac */ -#define SH_MISC_MEM_CFG_JNR_BYPASS_ENABLE_SHFT 2 -#define SH_MISC_MEM_CFG_JNR_BYPASS_ENABLE_MASK 0x0000000000000004 - -/* SH_MISC_MEM_CFG_XN_RD_SAME_AS_PI */ -/* Description: disables a one clock delay of XN read data */ -#define SH_MISC_MEM_CFG_XN_RD_SAME_AS_PI_SHFT 3 -#define SH_MISC_MEM_CFG_XN_RD_SAME_AS_PI_MASK 0x0000000000000008 - -/* SH_MISC_MEM_CFG_LOW_WRITE_BUFFER_THRESHOLD */ -/* Description: point at which data writes get higher priority */ -#define SH_MISC_MEM_CFG_LOW_WRITE_BUFFER_THRESHOLD_SHFT 4 -#define SH_MISC_MEM_CFG_LOW_WRITE_BUFFER_THRESHOLD_MASK 0x00000000000003f0 - -/* SH_MISC_MEM_CFG_LOW_VICTIM_BUFFER_THRESHOLD */ -/* Description: point at which dir cache writes get higher priority */ -#define SH_MISC_MEM_CFG_LOW_VICTIM_BUFFER_THRESHOLD_SHFT 12 -#define SH_MISC_MEM_CFG_LOW_VICTIM_BUFFER_THRESHOLD_MASK 0x000000000003f000 - -/* SH_MISC_MEM_CFG_THROTTLE_CNT */ -/* Description: number of clocks between accepting references */ -#define SH_MISC_MEM_CFG_THROTTLE_CNT_SHFT 20 -#define SH_MISC_MEM_CFG_THROTTLE_CNT_MASK 0x000000000ff00000 - -/* SH_MISC_MEM_CFG_DISABLED_READ_TNUMS */ -/* Description: number of read tnums to take out of circulation */ -#define SH_MISC_MEM_CFG_DISABLED_READ_TNUMS_SHFT 28 -#define SH_MISC_MEM_CFG_DISABLED_READ_TNUMS_MASK 0x00000001f0000000 - -/* SH_MISC_MEM_CFG_DISABLED_WRITE_TNUMS */ -/* Description: number of write tnums to take out of circulation */ -#define SH_MISC_MEM_CFG_DISABLED_WRITE_TNUMS_SHFT 36 -#define SH_MISC_MEM_CFG_DISABLED_WRITE_TNUMS_MASK 0x000001f000000000 - -/* SH_MISC_MEM_CFG_DISABLED_VICTIMS */ -/* Description: number of dir cache victim buffers to take out of c */ -/* irculation in each quadrant of the MD */ -#define SH_MISC_MEM_CFG_DISABLED_VICTIMS_SHFT 44 -#define SH_MISC_MEM_CFG_DISABLED_VICTIMS_MASK 0x0003f00000000000 - -/* SH_MISC_MEM_CFG_ALTERNATE_XN_RP_PLANE */ -/* Description: enables plane alternating for replies to XN */ -#define SH_MISC_MEM_CFG_ALTERNATE_XN_RP_PLANE_SHFT 52 -#define SH_MISC_MEM_CFG_ALTERNATE_XN_RP_PLANE_MASK 0x0010000000000000 - -/* ==================================================================== */ -/* Register "SH_PIO_RQ_CRD_CTL" */ -/* pio_rq Credit Circulation Control */ -/* ==================================================================== */ - -#define SH_PIO_RQ_CRD_CTL 0x0000000100010068 -#define SH_PIO_RQ_CRD_CTL_MASK 0x000000000000003f -#define SH_PIO_RQ_CRD_CTL_INIT 0x0000000000000002 - -/* SH_PIO_RQ_CRD_CTL_DEPTH */ -/* Description: Total depth of buffering (in sic packets) */ -#define SH_PIO_RQ_CRD_CTL_DEPTH_SHFT 0 -#define SH_PIO_RQ_CRD_CTL_DEPTH_MASK 0x000000000000003f - -/* ==================================================================== */ -/* Register "SH_PI_MD_RQ_CRD_CTL" */ -/* pi_md_rq Credit Circulation Control */ -/* ==================================================================== */ - -#define SH_PI_MD_RQ_CRD_CTL 0x0000000100010070 -#define SH_PI_MD_RQ_CRD_CTL_MASK 0x000000000000003f -#define SH_PI_MD_RQ_CRD_CTL_INIT 0x0000000000000008 - -/* SH_PI_MD_RQ_CRD_CTL_DEPTH */ -/* Description: Total depth of buffering (in sic packets) */ -#define SH_PI_MD_RQ_CRD_CTL_DEPTH_SHFT 0 -#define SH_PI_MD_RQ_CRD_CTL_DEPTH_MASK 0x000000000000003f - -/* ==================================================================== */ -/* Register "SH_PI_MD_RP_CRD_CTL" */ -/* pi_md_rp Credit Circulation Control */ -/* ==================================================================== */ - -#define SH_PI_MD_RP_CRD_CTL 0x0000000100010078 -#define SH_PI_MD_RP_CRD_CTL_MASK 0x000000000000003f -#define SH_PI_MD_RP_CRD_CTL_INIT 0x0000000000000004 - -/* SH_PI_MD_RP_CRD_CTL_DEPTH */ -/* Description: Total depth of buffering (in sic packets) */ -#define SH_PI_MD_RP_CRD_CTL_DEPTH_SHFT 0 -#define SH_PI_MD_RP_CRD_CTL_DEPTH_MASK 0x000000000000003f - -/* ==================================================================== */ -/* Register "SH_XN_MD_RQ_CRD_CTL" */ -/* xn_md_rq Credit Circulation Control */ -/* ==================================================================== */ - -#define SH_XN_MD_RQ_CRD_CTL 0x0000000100010080 -#define SH_XN_MD_RQ_CRD_CTL_MASK 0x000000000000003f -#define SH_XN_MD_RQ_CRD_CTL_INIT 0x0000000000000008 - -/* SH_XN_MD_RQ_CRD_CTL_DEPTH */ -/* Description: Total depth of buffering (in sic packets) */ -#define SH_XN_MD_RQ_CRD_CTL_DEPTH_SHFT 0 -#define SH_XN_MD_RQ_CRD_CTL_DEPTH_MASK 0x000000000000003f - -/* ==================================================================== */ -/* Register "SH_XN_MD_RP_CRD_CTL" */ -/* xn_md_rp Credit Circulation Control */ -/* ==================================================================== */ - -#define SH_XN_MD_RP_CRD_CTL 0x0000000100010088 -#define SH_XN_MD_RP_CRD_CTL_MASK 0x000000000000003f -#define SH_XN_MD_RP_CRD_CTL_INIT 0x0000000000000004 - -/* SH_XN_MD_RP_CRD_CTL_DEPTH */ -/* Description: Total depth of buffering (in sic packets) */ -#define SH_XN_MD_RP_CRD_CTL_DEPTH_SHFT 0 -#define SH_XN_MD_RP_CRD_CTL_DEPTH_MASK 0x000000000000003f - -/* ==================================================================== */ -/* Register "SH_X_TAG0" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_X_TAG0 0x0000000100020000 -#define SH_X_TAG0_MASK 0x00000000000fffff -#define SH_X_TAG0_INIT 0x0000000000000000 - -/* SH_X_TAG0_TAG */ -/* Description: Valid + Tag Address */ -#define SH_X_TAG0_TAG_SHFT 0 -#define SH_X_TAG0_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_X_TAG1" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_X_TAG1 0x0000000100020008 -#define SH_X_TAG1_MASK 0x00000000000fffff -#define SH_X_TAG1_INIT 0x0000000000000000 - -/* SH_X_TAG1_TAG */ -/* Description: Valid + Tag Address */ -#define SH_X_TAG1_TAG_SHFT 0 -#define SH_X_TAG1_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_X_TAG2" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_X_TAG2 0x0000000100020010 -#define SH_X_TAG2_MASK 0x00000000000fffff -#define SH_X_TAG2_INIT 0x0000000000000000 - -/* SH_X_TAG2_TAG */ -/* Description: Valid + Tag Address */ -#define SH_X_TAG2_TAG_SHFT 0 -#define SH_X_TAG2_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_X_TAG3" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_X_TAG3 0x0000000100020018 -#define SH_X_TAG3_MASK 0x00000000000fffff -#define SH_X_TAG3_INIT 0x0000000000000000 - -/* SH_X_TAG3_TAG */ -/* Description: Valid + Tag Address */ -#define SH_X_TAG3_TAG_SHFT 0 -#define SH_X_TAG3_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_X_TAG4" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_X_TAG4 0x0000000100020020 -#define SH_X_TAG4_MASK 0x00000000000fffff -#define SH_X_TAG4_INIT 0x0000000000000000 - -/* SH_X_TAG4_TAG */ -/* Description: Valid + Tag Address */ -#define SH_X_TAG4_TAG_SHFT 0 -#define SH_X_TAG4_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_X_TAG5" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_X_TAG5 0x0000000100020028 -#define SH_X_TAG5_MASK 0x00000000000fffff -#define SH_X_TAG5_INIT 0x0000000000000000 - -/* SH_X_TAG5_TAG */ -/* Description: Valid + Tag Address */ -#define SH_X_TAG5_TAG_SHFT 0 -#define SH_X_TAG5_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_X_TAG6" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_X_TAG6 0x0000000100020030 -#define SH_X_TAG6_MASK 0x00000000000fffff -#define SH_X_TAG6_INIT 0x0000000000000000 - -/* SH_X_TAG6_TAG */ -/* Description: Valid + Tag Address */ -#define SH_X_TAG6_TAG_SHFT 0 -#define SH_X_TAG6_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_X_TAG7" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_X_TAG7 0x0000000100020038 -#define SH_X_TAG7_MASK 0x00000000000fffff -#define SH_X_TAG7_INIT 0x0000000000000000 - -/* SH_X_TAG7_TAG */ -/* Description: Valid + Tag Address */ -#define SH_X_TAG7_TAG_SHFT 0 -#define SH_X_TAG7_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_Y_TAG0" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_Y_TAG0 0x0000000100020040 -#define SH_Y_TAG0_MASK 0x00000000000fffff -#define SH_Y_TAG0_INIT 0x0000000000000000 - -/* SH_Y_TAG0_TAG */ -/* Description: Valid + Tag Address */ -#define SH_Y_TAG0_TAG_SHFT 0 -#define SH_Y_TAG0_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_Y_TAG1" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_Y_TAG1 0x0000000100020048 -#define SH_Y_TAG1_MASK 0x00000000000fffff -#define SH_Y_TAG1_INIT 0x0000000000000000 - -/* SH_Y_TAG1_TAG */ -/* Description: Valid + Tag Address */ -#define SH_Y_TAG1_TAG_SHFT 0 -#define SH_Y_TAG1_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_Y_TAG2" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_Y_TAG2 0x0000000100020050 -#define SH_Y_TAG2_MASK 0x00000000000fffff -#define SH_Y_TAG2_INIT 0x0000000000000000 - -/* SH_Y_TAG2_TAG */ -/* Description: Valid + Tag Address */ -#define SH_Y_TAG2_TAG_SHFT 0 -#define SH_Y_TAG2_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_Y_TAG3" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_Y_TAG3 0x0000000100020058 -#define SH_Y_TAG3_MASK 0x00000000000fffff -#define SH_Y_TAG3_INIT 0x0000000000000000 - -/* SH_Y_TAG3_TAG */ -/* Description: Valid + Tag Address */ -#define SH_Y_TAG3_TAG_SHFT 0 -#define SH_Y_TAG3_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_Y_TAG4" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_Y_TAG4 0x0000000100020060 -#define SH_Y_TAG4_MASK 0x00000000000fffff -#define SH_Y_TAG4_INIT 0x0000000000000000 - -/* SH_Y_TAG4_TAG */ -/* Description: Valid + Tag Address */ -#define SH_Y_TAG4_TAG_SHFT 0 -#define SH_Y_TAG4_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_Y_TAG5" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_Y_TAG5 0x0000000100020068 -#define SH_Y_TAG5_MASK 0x00000000000fffff -#define SH_Y_TAG5_INIT 0x0000000000000000 - -/* SH_Y_TAG5_TAG */ -/* Description: Valid + Tag Address */ -#define SH_Y_TAG5_TAG_SHFT 0 -#define SH_Y_TAG5_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_Y_TAG6" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_Y_TAG6 0x0000000100020070 -#define SH_Y_TAG6_MASK 0x00000000000fffff -#define SH_Y_TAG6_INIT 0x0000000000000000 - -/* SH_Y_TAG6_TAG */ -/* Description: Valid + Tag Address */ -#define SH_Y_TAG6_TAG_SHFT 0 -#define SH_Y_TAG6_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_Y_TAG7" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_Y_TAG7 0x0000000100020078 -#define SH_Y_TAG7_MASK 0x00000000000fffff -#define SH_Y_TAG7_INIT 0x0000000000000000 - -/* SH_Y_TAG7_TAG */ -/* Description: Valid + Tag Address */ -#define SH_Y_TAG7_TAG_SHFT 0 -#define SH_Y_TAG7_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_MMRBIST_BASE" */ -/* mmr/bist base address */ -/* ==================================================================== */ - -#define SH_MMRBIST_BASE 0x0000000100020080 -#define SH_MMRBIST_BASE_MASK 0x0003fffffffffff8 -#define SH_MMRBIST_BASE_INIT 0x0000000000000000 - -/* SH_MMRBIST_BASE_DWORD_ADDR */ -/* Description: bits 49:3 of the memory address */ -#define SH_MMRBIST_BASE_DWORD_ADDR_SHFT 3 -#define SH_MMRBIST_BASE_DWORD_ADDR_MASK 0x0003fffffffffff8 - -/* ==================================================================== */ -/* Register "SH_MMRBIST_CTL" */ -/* Bist base address */ -/* ==================================================================== */ - -#define SH_MMRBIST_CTL 0x0000000100020088 -#define SH_MMRBIST_CTL_MASK 0x0000177f7fffffff -#define SH_MMRBIST_CTL_INIT 0x0000000000000000 - -/* SH_MMRBIST_CTL_BLOCK_LENGTH */ -/* Description: number of dwords in operation */ -#define SH_MMRBIST_CTL_BLOCK_LENGTH_SHFT 0 -#define SH_MMRBIST_CTL_BLOCK_LENGTH_MASK 0x000000007fffffff - -/* SH_MMRBIST_CTL_CMD */ -/* Description: mmr/bist function */ -#define SH_MMRBIST_CTL_CMD_SHFT 32 -#define SH_MMRBIST_CTL_CMD_MASK 0x0000007f00000000 - -/* SH_MMRBIST_CTL_IN_PROGRESS */ -/* Description: writing a 1 starts operation, hardware clears on co */ -/* mpletion */ -#define SH_MMRBIST_CTL_IN_PROGRESS_SHFT 40 -#define SH_MMRBIST_CTL_IN_PROGRESS_MASK 0x0000010000000000 - -/* SH_MMRBIST_CTL_FAIL */ -/* Description: mmr/bist had a data or address error */ -#define SH_MMRBIST_CTL_FAIL_SHFT 41 -#define SH_MMRBIST_CTL_FAIL_MASK 0x0000020000000000 - -/* SH_MMRBIST_CTL_MEM_IDLE */ -/* Description: all memory activity is complete */ -#define SH_MMRBIST_CTL_MEM_IDLE_SHFT 42 -#define SH_MMRBIST_CTL_MEM_IDLE_MASK 0x0000040000000000 - -/* SH_MMRBIST_CTL_RESET_STATE */ -/* Description: writing a 1 resets mmrbist hardware, hardware clear */ -/* s on completion */ -#define SH_MMRBIST_CTL_RESET_STATE_SHFT 44 -#define SH_MMRBIST_CTL_RESET_STATE_MASK 0x0000100000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DBUG_DATA_CFG" */ -/* configuration for md debug data muxes */ -/* ==================================================================== */ - -#define SH_MD_DBUG_DATA_CFG 0x0000000100020100 -#define SH_MD_DBUG_DATA_CFG_MASK 0x7777777777777777 -#define SH_MD_DBUG_DATA_CFG_INIT 0x0000000000000000 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE0_CHIPLET */ -/* Description: selects which md chiplet drives nibble0 */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE0_CHIPLET_SHFT 0 -#define SH_MD_DBUG_DATA_CFG_NIBBLE0_CHIPLET_MASK 0x0000000000000007 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE0_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE0_NIBBLE_SHFT 4 -#define SH_MD_DBUG_DATA_CFG_NIBBLE0_NIBBLE_MASK 0x0000000000000070 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE1_CHIPLET */ -/* Description: selects which md chiplet drives nibble1 */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE1_CHIPLET_SHFT 8 -#define SH_MD_DBUG_DATA_CFG_NIBBLE1_CHIPLET_MASK 0x0000000000000700 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE1_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE1_NIBBLE_SHFT 12 -#define SH_MD_DBUG_DATA_CFG_NIBBLE1_NIBBLE_MASK 0x0000000000007000 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE2_CHIPLET */ -/* Description: selects which md chiplet drives nibble2 */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE2_CHIPLET_SHFT 16 -#define SH_MD_DBUG_DATA_CFG_NIBBLE2_CHIPLET_MASK 0x0000000000070000 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE2_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE2_NIBBLE_SHFT 20 -#define SH_MD_DBUG_DATA_CFG_NIBBLE2_NIBBLE_MASK 0x0000000000700000 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE3_CHIPLET */ -/* Description: selects which md chiplet drives nibble3 */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE3_CHIPLET_SHFT 24 -#define SH_MD_DBUG_DATA_CFG_NIBBLE3_CHIPLET_MASK 0x0000000007000000 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE3_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE3_NIBBLE_SHFT 28 -#define SH_MD_DBUG_DATA_CFG_NIBBLE3_NIBBLE_MASK 0x0000000070000000 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE4_CHIPLET */ -/* Description: selects which md chiplet drives nibble4 */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE4_CHIPLET_SHFT 32 -#define SH_MD_DBUG_DATA_CFG_NIBBLE4_CHIPLET_MASK 0x0000000700000000 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE4_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE4_NIBBLE_SHFT 36 -#define SH_MD_DBUG_DATA_CFG_NIBBLE4_NIBBLE_MASK 0x0000007000000000 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE5_CHIPLET */ -/* Description: selects which md chiplet drives nibble5 */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE5_CHIPLET_SHFT 40 -#define SH_MD_DBUG_DATA_CFG_NIBBLE5_CHIPLET_MASK 0x0000070000000000 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE5_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE5_NIBBLE_SHFT 44 -#define SH_MD_DBUG_DATA_CFG_NIBBLE5_NIBBLE_MASK 0x0000700000000000 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE6_CHIPLET */ -/* Description: selects which md chiplet drives nibble6 */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE6_CHIPLET_SHFT 48 -#define SH_MD_DBUG_DATA_CFG_NIBBLE6_CHIPLET_MASK 0x0007000000000000 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE6_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE6_NIBBLE_SHFT 52 -#define SH_MD_DBUG_DATA_CFG_NIBBLE6_NIBBLE_MASK 0x0070000000000000 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE7_CHIPLET */ -/* Description: selects which md chiplet drives nibble7 */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE7_CHIPLET_SHFT 56 -#define SH_MD_DBUG_DATA_CFG_NIBBLE7_CHIPLET_MASK 0x0700000000000000 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE7_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE7_NIBBLE_SHFT 60 -#define SH_MD_DBUG_DATA_CFG_NIBBLE7_NIBBLE_MASK 0x7000000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DBUG_TRIGGER_CFG" */ -/* configuration for md debug triggers */ -/* ==================================================================== */ - -#define SH_MD_DBUG_TRIGGER_CFG 0x0000000100020108 -#define SH_MD_DBUG_TRIGGER_CFG_MASK 0xf777777777777777 -#define SH_MD_DBUG_TRIGGER_CFG_INIT 0x0000000000000000 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_CHIPLET */ -/* Description: selects which md chiplet drives nibble0 */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_CHIPLET_SHFT 0 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_CHIPLET_MASK 0x0000000000000007 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_NIBBLE_SHFT 4 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_NIBBLE_MASK 0x0000000000000070 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_CHIPLET */ -/* Description: selects which md chiplet drives nibble1 */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_CHIPLET_SHFT 8 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_CHIPLET_MASK 0x0000000000000700 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_NIBBLE_SHFT 12 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_NIBBLE_MASK 0x0000000000007000 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_CHIPLET */ -/* Description: selects which md chiplet drives nibble2 */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_CHIPLET_SHFT 16 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_CHIPLET_MASK 0x0000000000070000 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_NIBBLE_SHFT 20 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_NIBBLE_MASK 0x0000000000700000 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_CHIPLET */ -/* Description: selects which md chiplet drives nibble3 */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_CHIPLET_SHFT 24 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_CHIPLET_MASK 0x0000000007000000 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_NIBBLE_SHFT 28 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_NIBBLE_MASK 0x0000000070000000 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_CHIPLET */ -/* Description: selects which md chiplet drives nibble4 */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_CHIPLET_SHFT 32 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_CHIPLET_MASK 0x0000000700000000 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_NIBBLE_SHFT 36 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_NIBBLE_MASK 0x0000007000000000 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_CHIPLET */ -/* Description: selects which md chiplet drives nibble5 */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_CHIPLET_SHFT 40 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_CHIPLET_MASK 0x0000070000000000 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_NIBBLE_SHFT 44 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_NIBBLE_MASK 0x0000700000000000 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_CHIPLET */ -/* Description: selects which md chiplet drives nibble6 */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_CHIPLET_SHFT 48 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_CHIPLET_MASK 0x0007000000000000 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_NIBBLE_SHFT 52 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_NIBBLE_MASK 0x0070000000000000 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_CHIPLET */ -/* Description: selects which md chiplet drives nibble7 */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_CHIPLET_SHFT 56 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_CHIPLET_MASK 0x0700000000000000 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_NIBBLE_SHFT 60 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_NIBBLE_MASK 0x7000000000000000 - -/* SH_MD_DBUG_TRIGGER_CFG_ENABLE */ -/* Description: enables triggering on pattern match */ -#define SH_MD_DBUG_TRIGGER_CFG_ENABLE_SHFT 63 -#define SH_MD_DBUG_TRIGGER_CFG_ENABLE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DBUG_COMPARE" */ -/* md debug compare pattern and mask */ -/* ==================================================================== */ - -#define SH_MD_DBUG_COMPARE 0x0000000100020110 -#define SH_MD_DBUG_COMPARE_MASK 0xffffffffffffffff -#define SH_MD_DBUG_COMPARE_INIT 0x0000000000000000 - -/* SH_MD_DBUG_COMPARE_PATTERN */ -/* Description: pattern against which to compare dbug data for trig */ -#define SH_MD_DBUG_COMPARE_PATTERN_SHFT 0 -#define SH_MD_DBUG_COMPARE_PATTERN_MASK 0x00000000ffffffff - -/* SH_MD_DBUG_COMPARE_MASK */ -/* Description: bits to include in compare of dbug data for trigger */ -#define SH_MD_DBUG_COMPARE_MASK_SHFT 32 -#define SH_MD_DBUG_COMPARE_MASK_MASK 0xffffffff00000000 - -/* ==================================================================== */ -/* Register "SH_X_MOD_DBUG_SEL" */ -/* MD acx debug select */ -/* ==================================================================== */ - -#define SH_X_MOD_DBUG_SEL 0x0000000100020118 -#define SH_X_MOD_DBUG_SEL_MASK 0x03ffffffffffffff -#define SH_X_MOD_DBUG_SEL_INIT 0x0000000000000000 - -/* SH_X_MOD_DBUG_SEL_TAG_SEL */ -/* Description: tagmgr select */ -#define SH_X_MOD_DBUG_SEL_TAG_SEL_SHFT 0 -#define SH_X_MOD_DBUG_SEL_TAG_SEL_MASK 0x00000000000000ff - -/* SH_X_MOD_DBUG_SEL_WBQ_SEL */ -/* Description: wbqtg select */ -#define SH_X_MOD_DBUG_SEL_WBQ_SEL_SHFT 8 -#define SH_X_MOD_DBUG_SEL_WBQ_SEL_MASK 0x000000000000ff00 - -/* SH_X_MOD_DBUG_SEL_ARB_SEL */ -/* Description: arbque select */ -#define SH_X_MOD_DBUG_SEL_ARB_SEL_SHFT 16 -#define SH_X_MOD_DBUG_SEL_ARB_SEL_MASK 0x0000000000ff0000 - -/* SH_X_MOD_DBUG_SEL_ATL_SEL */ -/* Description: aintl select */ -#define SH_X_MOD_DBUG_SEL_ATL_SEL_SHFT 24 -#define SH_X_MOD_DBUG_SEL_ATL_SEL_MASK 0x00000007ff000000 - -/* SH_X_MOD_DBUG_SEL_ATR_SEL */ -/* Description: aintr select */ -#define SH_X_MOD_DBUG_SEL_ATR_SEL_SHFT 35 -#define SH_X_MOD_DBUG_SEL_ATR_SEL_MASK 0x00003ff800000000 - -/* SH_X_MOD_DBUG_SEL_DQL_SEL */ -/* Description: dqctr select */ -#define SH_X_MOD_DBUG_SEL_DQL_SEL_SHFT 46 -#define SH_X_MOD_DBUG_SEL_DQL_SEL_MASK 0x000fc00000000000 - -/* SH_X_MOD_DBUG_SEL_DQR_SEL */ -/* Description: dqctl select */ -#define SH_X_MOD_DBUG_SEL_DQR_SEL_SHFT 52 -#define SH_X_MOD_DBUG_SEL_DQR_SEL_MASK 0x03f0000000000000 - -/* ==================================================================== */ -/* Register "SH_X_DBUG_SEL" */ -/* MD acx debug select */ -/* ==================================================================== */ - -#define SH_X_DBUG_SEL 0x0000000100020120 -#define SH_X_DBUG_SEL_MASK 0x0000000000ffffff -#define SH_X_DBUG_SEL_INIT 0x0000000000000000 - -/* SH_X_DBUG_SEL_DBG_SEL */ -/* Description: debug select */ -#define SH_X_DBUG_SEL_DBG_SEL_SHFT 0 -#define SH_X_DBUG_SEL_DBG_SEL_MASK 0x0000000000ffffff - -/* ==================================================================== */ -/* Register "SH_X_LADDR_CMP" */ -/* MD acx address compare */ -/* ==================================================================== */ - -#define SH_X_LADDR_CMP 0x0000000100020128 -#define SH_X_LADDR_CMP_MASK 0x0fffffff0fffffff -#define SH_X_LADDR_CMP_INIT 0x0000000000000000 - -/* SH_X_LADDR_CMP_CMP_VAL */ -/* Description: Compare value */ -#define SH_X_LADDR_CMP_CMP_VAL_SHFT 0 -#define SH_X_LADDR_CMP_CMP_VAL_MASK 0x000000000fffffff - -/* SH_X_LADDR_CMP_MASK_VAL */ -/* Description: Mask value */ -#define SH_X_LADDR_CMP_MASK_VAL_SHFT 32 -#define SH_X_LADDR_CMP_MASK_VAL_MASK 0x0fffffff00000000 - -/* ==================================================================== */ -/* Register "SH_X_RADDR_CMP" */ -/* MD acx address compare */ -/* ==================================================================== */ - -#define SH_X_RADDR_CMP 0x0000000100020130 -#define SH_X_RADDR_CMP_MASK 0x0fffffff0fffffff -#define SH_X_RADDR_CMP_INIT 0x0000000000000000 - -/* SH_X_RADDR_CMP_CMP_VAL */ -/* Description: Compare value */ -#define SH_X_RADDR_CMP_CMP_VAL_SHFT 0 -#define SH_X_RADDR_CMP_CMP_VAL_MASK 0x000000000fffffff - -/* SH_X_RADDR_CMP_MASK_VAL */ -/* Description: Mask value */ -#define SH_X_RADDR_CMP_MASK_VAL_SHFT 32 -#define SH_X_RADDR_CMP_MASK_VAL_MASK 0x0fffffff00000000 - -/* ==================================================================== */ -/* Register "SH_X_TAG_CMP" */ -/* MD acx tagmgr compare */ -/* ==================================================================== */ - -#define SH_X_TAG_CMP 0x0000000100020138 -#define SH_X_TAG_CMP_MASK 0x007fffffffffffff -#define SH_X_TAG_CMP_INIT 0x0000000000000000 - -/* SH_X_TAG_CMP_CMD */ -/* Description: Command compare value */ -#define SH_X_TAG_CMP_CMD_SHFT 0 -#define SH_X_TAG_CMP_CMD_MASK 0x00000000000000ff - -/* SH_X_TAG_CMP_ADDR */ -/* Description: Address compare value */ -#define SH_X_TAG_CMP_ADDR_SHFT 8 -#define SH_X_TAG_CMP_ADDR_MASK 0x000001ffffffff00 - -/* SH_X_TAG_CMP_SRC */ -/* Description: Source compare value */ -#define SH_X_TAG_CMP_SRC_SHFT 41 -#define SH_X_TAG_CMP_SRC_MASK 0x007ffe0000000000 - -/* ==================================================================== */ -/* Register "SH_X_TAG_MASK" */ -/* MD acx tagmgr mask */ -/* ==================================================================== */ - -#define SH_X_TAG_MASK 0x0000000100020140 -#define SH_X_TAG_MASK_MASK 0x007fffffffffffff -#define SH_X_TAG_MASK_INIT 0x0000000000000000 - -/* SH_X_TAG_MASK_CMD */ -/* Description: Command compare value */ -#define SH_X_TAG_MASK_CMD_SHFT 0 -#define SH_X_TAG_MASK_CMD_MASK 0x00000000000000ff - -/* SH_X_TAG_MASK_ADDR */ -/* Description: Address compare value */ -#define SH_X_TAG_MASK_ADDR_SHFT 8 -#define SH_X_TAG_MASK_ADDR_MASK 0x000001ffffffff00 - -/* SH_X_TAG_MASK_SRC */ -/* Description: Source compare value */ -#define SH_X_TAG_MASK_SRC_SHFT 41 -#define SH_X_TAG_MASK_SRC_MASK 0x007ffe0000000000 - -/* ==================================================================== */ -/* Register "SH_Y_MOD_DBUG_SEL" */ -/* MD acy debug select */ -/* ==================================================================== */ - -#define SH_Y_MOD_DBUG_SEL 0x0000000100020148 -#define SH_Y_MOD_DBUG_SEL_MASK 0x03ffffffffffffff -#define SH_Y_MOD_DBUG_SEL_INIT 0x0000000000000000 - -/* SH_Y_MOD_DBUG_SEL_TAG_SEL */ -/* Description: tagmgr select */ -#define SH_Y_MOD_DBUG_SEL_TAG_SEL_SHFT 0 -#define SH_Y_MOD_DBUG_SEL_TAG_SEL_MASK 0x00000000000000ff - -/* SH_Y_MOD_DBUG_SEL_WBQ_SEL */ -/* Description: wbqtg select */ -#define SH_Y_MOD_DBUG_SEL_WBQ_SEL_SHFT 8 -#define SH_Y_MOD_DBUG_SEL_WBQ_SEL_MASK 0x000000000000ff00 - -/* SH_Y_MOD_DBUG_SEL_ARB_SEL */ -/* Description: arbque select */ -#define SH_Y_MOD_DBUG_SEL_ARB_SEL_SHFT 16 -#define SH_Y_MOD_DBUG_SEL_ARB_SEL_MASK 0x0000000000ff0000 - -/* SH_Y_MOD_DBUG_SEL_ATL_SEL */ -/* Description: aintl select */ -#define SH_Y_MOD_DBUG_SEL_ATL_SEL_SHFT 24 -#define SH_Y_MOD_DBUG_SEL_ATL_SEL_MASK 0x00000007ff000000 - -/* SH_Y_MOD_DBUG_SEL_ATR_SEL */ -/* Description: aintr select */ -#define SH_Y_MOD_DBUG_SEL_ATR_SEL_SHFT 35 -#define SH_Y_MOD_DBUG_SEL_ATR_SEL_MASK 0x00003ff800000000 - -/* SH_Y_MOD_DBUG_SEL_DQL_SEL */ -/* Description: dqctr select */ -#define SH_Y_MOD_DBUG_SEL_DQL_SEL_SHFT 46 -#define SH_Y_MOD_DBUG_SEL_DQL_SEL_MASK 0x000fc00000000000 - -/* SH_Y_MOD_DBUG_SEL_DQR_SEL */ -/* Description: dqctl select */ -#define SH_Y_MOD_DBUG_SEL_DQR_SEL_SHFT 52 -#define SH_Y_MOD_DBUG_SEL_DQR_SEL_MASK 0x03f0000000000000 - -/* ==================================================================== */ -/* Register "SH_Y_DBUG_SEL" */ -/* MD acy debug select */ -/* ==================================================================== */ - -#define SH_Y_DBUG_SEL 0x0000000100020150 -#define SH_Y_DBUG_SEL_MASK 0x0000000000ffffff -#define SH_Y_DBUG_SEL_INIT 0x0000000000000000 - -/* SH_Y_DBUG_SEL_DBG_SEL */ -/* Description: debug select */ -#define SH_Y_DBUG_SEL_DBG_SEL_SHFT 0 -#define SH_Y_DBUG_SEL_DBG_SEL_MASK 0x0000000000ffffff - -/* ==================================================================== */ -/* Register "SH_Y_LADDR_CMP" */ -/* MD acy address compare */ -/* ==================================================================== */ - -#define SH_Y_LADDR_CMP 0x0000000100020158 -#define SH_Y_LADDR_CMP_MASK 0x0fffffff0fffffff -#define SH_Y_LADDR_CMP_INIT 0x0000000000000000 - -/* SH_Y_LADDR_CMP_CMP_VAL */ -/* Description: Compare value */ -#define SH_Y_LADDR_CMP_CMP_VAL_SHFT 0 -#define SH_Y_LADDR_CMP_CMP_VAL_MASK 0x000000000fffffff - -/* SH_Y_LADDR_CMP_MASK_VAL */ -/* Description: Mask value */ -#define SH_Y_LADDR_CMP_MASK_VAL_SHFT 32 -#define SH_Y_LADDR_CMP_MASK_VAL_MASK 0x0fffffff00000000 - -/* ==================================================================== */ -/* Register "SH_Y_RADDR_CMP" */ -/* MD acy address compare */ -/* ==================================================================== */ - -#define SH_Y_RADDR_CMP 0x0000000100020160 -#define SH_Y_RADDR_CMP_MASK 0x0fffffff0fffffff -#define SH_Y_RADDR_CMP_INIT 0x0000000000000000 - -/* SH_Y_RADDR_CMP_CMP_VAL */ -/* Description: Compare value */ -#define SH_Y_RADDR_CMP_CMP_VAL_SHFT 0 -#define SH_Y_RADDR_CMP_CMP_VAL_MASK 0x000000000fffffff - -/* SH_Y_RADDR_CMP_MASK_VAL */ -/* Description: Mask value */ -#define SH_Y_RADDR_CMP_MASK_VAL_SHFT 32 -#define SH_Y_RADDR_CMP_MASK_VAL_MASK 0x0fffffff00000000 - -/* ==================================================================== */ -/* Register "SH_Y_TAG_CMP" */ -/* MD acy tagmgr compare */ -/* ==================================================================== */ - -#define SH_Y_TAG_CMP 0x0000000100020168 -#define SH_Y_TAG_CMP_MASK 0x007fffffffffffff -#define SH_Y_TAG_CMP_INIT 0x0000000000000000 - -/* SH_Y_TAG_CMP_CMD */ -/* Description: Command compare value */ -#define SH_Y_TAG_CMP_CMD_SHFT 0 -#define SH_Y_TAG_CMP_CMD_MASK 0x00000000000000ff - -/* SH_Y_TAG_CMP_ADDR */ -/* Description: Address compare value */ -#define SH_Y_TAG_CMP_ADDR_SHFT 8 -#define SH_Y_TAG_CMP_ADDR_MASK 0x000001ffffffff00 - -/* SH_Y_TAG_CMP_SRC */ -/* Description: Source compare value */ -#define SH_Y_TAG_CMP_SRC_SHFT 41 -#define SH_Y_TAG_CMP_SRC_MASK 0x007ffe0000000000 - -/* ==================================================================== */ -/* Register "SH_Y_TAG_MASK" */ -/* MD acy tagmgr mask */ -/* ==================================================================== */ - -#define SH_Y_TAG_MASK 0x0000000100020170 -#define SH_Y_TAG_MASK_MASK 0x007fffffffffffff -#define SH_Y_TAG_MASK_INIT 0x0000000000000000 - -/* SH_Y_TAG_MASK_CMD */ -/* Description: Command compare value */ -#define SH_Y_TAG_MASK_CMD_SHFT 0 -#define SH_Y_TAG_MASK_CMD_MASK 0x00000000000000ff - -/* SH_Y_TAG_MASK_ADDR */ -/* Description: Address compare value */ -#define SH_Y_TAG_MASK_ADDR_SHFT 8 -#define SH_Y_TAG_MASK_ADDR_MASK 0x000001ffffffff00 - -/* SH_Y_TAG_MASK_SRC */ -/* Description: Source compare value */ -#define SH_Y_TAG_MASK_SRC_SHFT 41 -#define SH_Y_TAG_MASK_SRC_MASK 0x007ffe0000000000 - -/* ==================================================================== */ -/* Register "SH_MD_JNR_DBUG_DATA_CFG" */ -/* configuration for md jnr debug data muxes */ -/* ==================================================================== */ - -#define SH_MD_JNR_DBUG_DATA_CFG 0x0000000100020178 -#define SH_MD_JNR_DBUG_DATA_CFG_MASK 0x0000000077777777 -#define SH_MD_JNR_DBUG_DATA_CFG_INIT 0x0000000000000000 - -/* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE0_SEL */ -/* Description: selects which nibble drives nibble0 */ -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE0_SEL_SHFT 0 -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE0_SEL_MASK 0x0000000000000007 - -/* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE1_SEL */ -/* Description: selects which nibble drives nibble1 */ -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE1_SEL_SHFT 4 -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE1_SEL_MASK 0x0000000000000070 - -/* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE2_SEL */ -/* Description: selects which nibble drives nibble2 */ -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE2_SEL_SHFT 8 -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE2_SEL_MASK 0x0000000000000700 - -/* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE3_SEL */ -/* Description: selects which nibble drives nibble3 */ -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE3_SEL_SHFT 12 -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE3_SEL_MASK 0x0000000000007000 - -/* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE4_SEL */ -/* Description: selects which nibble drives nibble4 */ -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE4_SEL_SHFT 16 -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE4_SEL_MASK 0x0000000000070000 - -/* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE5_SEL */ -/* Description: selects which nibble drives nibble5 */ -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE5_SEL_SHFT 20 -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE5_SEL_MASK 0x0000000000700000 - -/* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE6_SEL */ -/* Description: selects which nibble drives nibble6 */ -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE6_SEL_SHFT 24 -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE6_SEL_MASK 0x0000000007000000 - -/* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE7_SEL */ -/* Description: selects which nibble drives nibble7 */ -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE7_SEL_SHFT 28 -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE7_SEL_MASK 0x0000000070000000 - -/* ==================================================================== */ -/* Register "SH_MD_LAST_CREDIT" */ -/* captures last credit values on reset */ -/* ==================================================================== */ - -#define SH_MD_LAST_CREDIT 0x0000000100020180 -#define SH_MD_LAST_CREDIT_MASK 0x0000003f3f3f3f3f -#define SH_MD_LAST_CREDIT_INIT 0x0000000000000000 - -/* SH_MD_LAST_CREDIT_RQ_TO_PI */ -/* Description: capture of request credits to pi */ -#define SH_MD_LAST_CREDIT_RQ_TO_PI_SHFT 0 -#define SH_MD_LAST_CREDIT_RQ_TO_PI_MASK 0x000000000000003f - -/* SH_MD_LAST_CREDIT_RP_TO_PI */ -/* Description: capture of reply credits to pi */ -#define SH_MD_LAST_CREDIT_RP_TO_PI_SHFT 8 -#define SH_MD_LAST_CREDIT_RP_TO_PI_MASK 0x0000000000003f00 - -/* SH_MD_LAST_CREDIT_RQ_TO_XN */ -/* Description: capture of request credits to xn */ -#define SH_MD_LAST_CREDIT_RQ_TO_XN_SHFT 16 -#define SH_MD_LAST_CREDIT_RQ_TO_XN_MASK 0x00000000003f0000 - -/* SH_MD_LAST_CREDIT_RP_TO_XN */ -/* Description: capture of reply credits to xn */ -#define SH_MD_LAST_CREDIT_RP_TO_XN_SHFT 24 -#define SH_MD_LAST_CREDIT_RP_TO_XN_MASK 0x000000003f000000 - -/* SH_MD_LAST_CREDIT_TO_LB */ -/* Description: capture of credits to pi */ -#define SH_MD_LAST_CREDIT_TO_LB_SHFT 32 -#define SH_MD_LAST_CREDIT_TO_LB_MASK 0x0000003f00000000 - -/* ==================================================================== */ -/* Register "SH_MEM_CAPTURE_ADDR" */ -/* Address capture address register */ -/* ==================================================================== */ - -#define SH_MEM_CAPTURE_ADDR 0x0000000100020300 -#define SH_MEM_CAPTURE_ADDR_MASK 0x00000ffffffffff8 -#define SH_MEM_CAPTURE_ADDR_INIT 0x0000000000000000 - -/* SH_MEM_CAPTURE_ADDR_ADDR */ -/* Description: upper bits of address */ -#define SH_MEM_CAPTURE_ADDR_ADDR_SHFT 3 -#define SH_MEM_CAPTURE_ADDR_ADDR_MASK 0x0000000ffffffff8 - -/* SH_MEM_CAPTURE_ADDR_CMD */ -/* Description: command of reference */ -#define SH_MEM_CAPTURE_ADDR_CMD_SHFT 36 -#define SH_MEM_CAPTURE_ADDR_CMD_MASK 0x00000ff000000000 - -/* ==================================================================== */ -/* Register "SH_MEM_CAPTURE_MASK" */ -/* Address capture mask register */ -/* ==================================================================== */ - -#define SH_MEM_CAPTURE_MASK 0x0000000100020308 -#define SH_MEM_CAPTURE_MASK_MASK 0x00003ffffffffff8 -#define SH_MEM_CAPTURE_MASK_INIT 0x0000000000000000 - -/* SH_MEM_CAPTURE_MASK_ADDR */ -/* Description: upper bits of address */ -#define SH_MEM_CAPTURE_MASK_ADDR_SHFT 3 -#define SH_MEM_CAPTURE_MASK_ADDR_MASK 0x0000000ffffffff8 - -/* SH_MEM_CAPTURE_MASK_CMD */ -/* Description: command of reference */ -#define SH_MEM_CAPTURE_MASK_CMD_SHFT 36 -#define SH_MEM_CAPTURE_MASK_CMD_MASK 0x00000ff000000000 - -/* SH_MEM_CAPTURE_MASK_ENABLE_LOCAL */ -/* Description: capture references originating locally */ -#define SH_MEM_CAPTURE_MASK_ENABLE_LOCAL_SHFT 44 -#define SH_MEM_CAPTURE_MASK_ENABLE_LOCAL_MASK 0x0000100000000000 - -/* SH_MEM_CAPTURE_MASK_ENABLE_REMOTE */ -/* Description: capture references originating remotely */ -#define SH_MEM_CAPTURE_MASK_ENABLE_REMOTE_SHFT 45 -#define SH_MEM_CAPTURE_MASK_ENABLE_REMOTE_MASK 0x0000200000000000 - -/* ==================================================================== */ -/* Register "SH_MEM_CAPTURE_HDR" */ -/* Address capture header register */ -/* ==================================================================== */ - -#define SH_MEM_CAPTURE_HDR 0x0000000100020310 -#define SH_MEM_CAPTURE_HDR_MASK 0xfffffffffffffff8 -#define SH_MEM_CAPTURE_HDR_INIT 0x0000000000000000 - -/* SH_MEM_CAPTURE_HDR_ADDR */ -/* Description: upper bits of reference address */ -#define SH_MEM_CAPTURE_HDR_ADDR_SHFT 3 -#define SH_MEM_CAPTURE_HDR_ADDR_MASK 0x0000000ffffffff8 - -/* SH_MEM_CAPTURE_HDR_CMD */ -/* Description: command of reference */ -#define SH_MEM_CAPTURE_HDR_CMD_SHFT 36 -#define SH_MEM_CAPTURE_HDR_CMD_MASK 0x00000ff000000000 - -/* SH_MEM_CAPTURE_HDR_SRC */ -/* Description: source node of reference */ -#define SH_MEM_CAPTURE_HDR_SRC_SHFT 44 -#define SH_MEM_CAPTURE_HDR_SRC_MASK 0x03fff00000000000 - -/* SH_MEM_CAPTURE_HDR_CNTR */ -/* Description: increments on every capture */ -#define SH_MEM_CAPTURE_HDR_CNTR_SHFT 58 -#define SH_MEM_CAPTURE_HDR_CNTR_MASK 0xfc00000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_CONFIG" */ -/* DQ directory config register */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_CONFIG 0x0000000100030000 -#define SH_MD_DQLP_MMR_DIR_CONFIG_MASK 0x000000000000001f -#define SH_MD_DQLP_MMR_DIR_CONFIG_INIT 0x0000000000000010 - -/* SH_MD_DQLP_MMR_DIR_CONFIG_SYS_SIZE */ -/* Description: system size code */ -#define SH_MD_DQLP_MMR_DIR_CONFIG_SYS_SIZE_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_CONFIG_SYS_SIZE_MASK 0x0000000000000007 - -/* SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRECC */ -/* Description: enable directory ecc correction */ -#define SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRECC_SHFT 3 -#define SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRECC_MASK 0x0000000000000008 - -/* SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRPOIS */ -/* Description: enable local poisoning for dir table fall-through */ -#define SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRPOIS_SHFT 4 -#define SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRPOIS_MASK 0x0000000000000010 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRESVEC0" */ -/* node [63:0] presence bits */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_PRESVEC0 0x0000000100030100 -#define SH_MD_DQLP_MMR_DIR_PRESVEC0_MASK 0xffffffffffffffff -#define SH_MD_DQLP_MMR_DIR_PRESVEC0_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_PRESVEC0_VEC */ -/* Description: node presence bits, 1=present */ -#define SH_MD_DQLP_MMR_DIR_PRESVEC0_VEC_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_PRESVEC0_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRESVEC1" */ -/* node [127:64] presence bits */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_PRESVEC1 0x0000000100030110 -#define SH_MD_DQLP_MMR_DIR_PRESVEC1_MASK 0xffffffffffffffff -#define SH_MD_DQLP_MMR_DIR_PRESVEC1_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_PRESVEC1_VEC */ -/* Description: node presence bits, 1=present */ -#define SH_MD_DQLP_MMR_DIR_PRESVEC1_VEC_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_PRESVEC1_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRESVEC2" */ -/* node [191:128] presence bits */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_PRESVEC2 0x0000000100030120 -#define SH_MD_DQLP_MMR_DIR_PRESVEC2_MASK 0xffffffffffffffff -#define SH_MD_DQLP_MMR_DIR_PRESVEC2_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_PRESVEC2_VEC */ -/* Description: node presence bits, 1=present */ -#define SH_MD_DQLP_MMR_DIR_PRESVEC2_VEC_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_PRESVEC2_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRESVEC3" */ -/* node [255:192] presence bits */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_PRESVEC3 0x0000000100030130 -#define SH_MD_DQLP_MMR_DIR_PRESVEC3_MASK 0xffffffffffffffff -#define SH_MD_DQLP_MMR_DIR_PRESVEC3_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_PRESVEC3_VEC */ -/* Description: node presence bits, 1=present */ -#define SH_MD_DQLP_MMR_DIR_PRESVEC3_VEC_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_PRESVEC3_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC0" */ -/* local vector for acc=0 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_LOCVEC0 0x0000000100030200 -#define SH_MD_DQLP_MMR_DIR_LOCVEC0_MASK 0xffffffffffffffff -#define SH_MD_DQLP_MMR_DIR_LOCVEC0_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_LOCVEC0_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQLP_MMR_DIR_LOCVEC0_VEC_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_LOCVEC0_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC1" */ -/* local vector for acc=1 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_LOCVEC1 0x0000000100030210 -#define SH_MD_DQLP_MMR_DIR_LOCVEC1_MASK 0xffffffffffffffff -#define SH_MD_DQLP_MMR_DIR_LOCVEC1_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_LOCVEC1_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQLP_MMR_DIR_LOCVEC1_VEC_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_LOCVEC1_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC2" */ -/* local vector for acc=2 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_LOCVEC2 0x0000000100030220 -#define SH_MD_DQLP_MMR_DIR_LOCVEC2_MASK 0xffffffffffffffff -#define SH_MD_DQLP_MMR_DIR_LOCVEC2_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_LOCVEC2_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQLP_MMR_DIR_LOCVEC2_VEC_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_LOCVEC2_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC3" */ -/* local vector for acc=3 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_LOCVEC3 0x0000000100030230 -#define SH_MD_DQLP_MMR_DIR_LOCVEC3_MASK 0xffffffffffffffff -#define SH_MD_DQLP_MMR_DIR_LOCVEC3_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_LOCVEC3_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQLP_MMR_DIR_LOCVEC3_VEC_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_LOCVEC3_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC4" */ -/* local vector for acc=4 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_LOCVEC4 0x0000000100030240 -#define SH_MD_DQLP_MMR_DIR_LOCVEC4_MASK 0xffffffffffffffff -#define SH_MD_DQLP_MMR_DIR_LOCVEC4_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_LOCVEC4_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQLP_MMR_DIR_LOCVEC4_VEC_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_LOCVEC4_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC5" */ -/* local vector for acc=5 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_LOCVEC5 0x0000000100030250 -#define SH_MD_DQLP_MMR_DIR_LOCVEC5_MASK 0xffffffffffffffff -#define SH_MD_DQLP_MMR_DIR_LOCVEC5_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_LOCVEC5_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQLP_MMR_DIR_LOCVEC5_VEC_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_LOCVEC5_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC6" */ -/* local vector for acc=6 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_LOCVEC6 0x0000000100030260 -#define SH_MD_DQLP_MMR_DIR_LOCVEC6_MASK 0xffffffffffffffff -#define SH_MD_DQLP_MMR_DIR_LOCVEC6_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_LOCVEC6_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQLP_MMR_DIR_LOCVEC6_VEC_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_LOCVEC6_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC7" */ -/* local vector for acc=7 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_LOCVEC7 0x0000000100030270 -#define SH_MD_DQLP_MMR_DIR_LOCVEC7_MASK 0xffffffffffffffff -#define SH_MD_DQLP_MMR_DIR_LOCVEC7_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_LOCVEC7_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQLP_MMR_DIR_LOCVEC7_VEC_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_LOCVEC7_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC0" */ -/* privilege vector for acc=0 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_PRIVEC0 0x0000000100030300 -#define SH_MD_DQLP_MMR_DIR_PRIVEC0_MASK 0x000000000fffffff -#define SH_MD_DQLP_MMR_DIR_PRIVEC0_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_PRIVEC0_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC0_IN_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_PRIVEC0_IN_MASK 0x0000000000003fff - -/* SH_MD_DQLP_MMR_DIR_PRIVEC0_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC0_OUT_SHFT 14 -#define SH_MD_DQLP_MMR_DIR_PRIVEC0_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC1" */ -/* privilege vector for acc=1 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_PRIVEC1 0x0000000100030310 -#define SH_MD_DQLP_MMR_DIR_PRIVEC1_MASK 0x000000000fffffff -#define SH_MD_DQLP_MMR_DIR_PRIVEC1_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_PRIVEC1_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC1_IN_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_PRIVEC1_IN_MASK 0x0000000000003fff - -/* SH_MD_DQLP_MMR_DIR_PRIVEC1_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC1_OUT_SHFT 14 -#define SH_MD_DQLP_MMR_DIR_PRIVEC1_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC2" */ -/* privilege vector for acc=2 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_PRIVEC2 0x0000000100030320 -#define SH_MD_DQLP_MMR_DIR_PRIVEC2_MASK 0x000000000fffffff -#define SH_MD_DQLP_MMR_DIR_PRIVEC2_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_PRIVEC2_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC2_IN_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_PRIVEC2_IN_MASK 0x0000000000003fff - -/* SH_MD_DQLP_MMR_DIR_PRIVEC2_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC2_OUT_SHFT 14 -#define SH_MD_DQLP_MMR_DIR_PRIVEC2_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC3" */ -/* privilege vector for acc=3 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_PRIVEC3 0x0000000100030330 -#define SH_MD_DQLP_MMR_DIR_PRIVEC3_MASK 0x000000000fffffff -#define SH_MD_DQLP_MMR_DIR_PRIVEC3_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_PRIVEC3_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC3_IN_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_PRIVEC3_IN_MASK 0x0000000000003fff - -/* SH_MD_DQLP_MMR_DIR_PRIVEC3_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC3_OUT_SHFT 14 -#define SH_MD_DQLP_MMR_DIR_PRIVEC3_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC4" */ -/* privilege vector for acc=4 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_PRIVEC4 0x0000000100030340 -#define SH_MD_DQLP_MMR_DIR_PRIVEC4_MASK 0x000000000fffffff -#define SH_MD_DQLP_MMR_DIR_PRIVEC4_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_PRIVEC4_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC4_IN_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_PRIVEC4_IN_MASK 0x0000000000003fff - -/* SH_MD_DQLP_MMR_DIR_PRIVEC4_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC4_OUT_SHFT 14 -#define SH_MD_DQLP_MMR_DIR_PRIVEC4_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC5" */ -/* privilege vector for acc=5 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_PRIVEC5 0x0000000100030350 -#define SH_MD_DQLP_MMR_DIR_PRIVEC5_MASK 0x000000000fffffff -#define SH_MD_DQLP_MMR_DIR_PRIVEC5_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_PRIVEC5_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC5_IN_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_PRIVEC5_IN_MASK 0x0000000000003fff - -/* SH_MD_DQLP_MMR_DIR_PRIVEC5_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC5_OUT_SHFT 14 -#define SH_MD_DQLP_MMR_DIR_PRIVEC5_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC6" */ -/* privilege vector for acc=6 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_PRIVEC6 0x0000000100030360 -#define SH_MD_DQLP_MMR_DIR_PRIVEC6_MASK 0x000000000fffffff -#define SH_MD_DQLP_MMR_DIR_PRIVEC6_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_PRIVEC6_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC6_IN_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_PRIVEC6_IN_MASK 0x0000000000003fff - -/* SH_MD_DQLP_MMR_DIR_PRIVEC6_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC6_OUT_SHFT 14 -#define SH_MD_DQLP_MMR_DIR_PRIVEC6_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC7" */ -/* privilege vector for acc=7 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_PRIVEC7 0x0000000100030370 -#define SH_MD_DQLP_MMR_DIR_PRIVEC7_MASK 0x000000000fffffff -#define SH_MD_DQLP_MMR_DIR_PRIVEC7_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_PRIVEC7_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC7_IN_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_PRIVEC7_IN_MASK 0x0000000000003fff - -/* SH_MD_DQLP_MMR_DIR_PRIVEC7_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC7_OUT_SHFT 14 -#define SH_MD_DQLP_MMR_DIR_PRIVEC7_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_TIMER" */ -/* MD SXRO timer */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_TIMER 0x0000000100030400 -#define SH_MD_DQLP_MMR_DIR_TIMER_MASK 0x00000000003fffff -#define SH_MD_DQLP_MMR_DIR_TIMER_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_TIMER_TIMER_DIV */ -/* Description: timer divide register */ -#define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_DIV_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_DIV_MASK 0x0000000000000fff - -/* SH_MD_DQLP_MMR_DIR_TIMER_TIMER_EN */ -/* Description: timer enable */ -#define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_EN_SHFT 12 -#define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_EN_MASK 0x0000000000001000 - -/* SH_MD_DQLP_MMR_DIR_TIMER_TIMER_CUR */ -/* Description: value of current timer */ -#define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_CUR_SHFT 13 -#define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_CUR_MASK 0x00000000003fe000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY" */ -/* directory pio write data */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY 0x0000000100031000 -#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_MASK 0x03ffffffffffffff -#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRA */ -/* Description: directory entry A */ -#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRA_SHFT 0 -#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRA_MASK 0x0000000003ffffff - -/* SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRB */ -/* Description: directory entry B */ -#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRB_SHFT 26 -#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRB_MASK 0x000ffffffc000000 - -/* SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_PRI */ -/* Description: directory priority */ -#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_PRI_SHFT 52 -#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_PRI_MASK 0x0070000000000000 - -/* SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_ACC */ -/* Description: directory access bits */ -#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_ACC_SHFT 55 -#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_ACC_MASK 0x0380000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_PIOWD_DIR_ECC" */ -/* directory ecc register */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC 0x0000000100031010 -#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_MASK 0x0000000000003fff -#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCA */ -/* Description: XOR bits for directory ECC group 1 */ -#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCA_SHFT 0 -#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCA_MASK 0x000000000000007f - -/* SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCB */ -/* Description: XOR bits for directory ECC group 2 */ -#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCB_SHFT 7 -#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCB_MASK 0x0000000000003f80 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY" */ -/* x directory pio read data */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY 0x0000000100032000 -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_MASK 0x0fffffffffffffff -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRA */ -/* Description: directory entry A */ -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRA_SHFT 0 -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRA_MASK 0x0000000003ffffff - -/* SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRB */ -/* Description: directory entry B */ -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRB_SHFT 26 -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRB_MASK 0x000ffffffc000000 - -/* SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_PRI */ -/* Description: directory priority */ -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_PRI_SHFT 52 -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_PRI_MASK 0x0070000000000000 - -/* SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_ACC */ -/* Description: directory access bits */ -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_ACC_SHFT 55 -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_ACC_MASK 0x0380000000000000 - -/* SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_COR */ -/* Description: correctable ecc error */ -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_COR_SHFT 58 -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_COR_MASK 0x0400000000000000 - -/* SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_UNC */ -/* Description: uncorrectable ecc error */ -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_UNC_SHFT 59 -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_UNC_MASK 0x0800000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XPIORD_XDIR_ECC" */ -/* x directory ecc */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC 0x0000000100032010 -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_MASK 0x0000000000003fff -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCA */ -/* Description: group 1 ecc */ -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCA_SHFT 0 -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCA_MASK 0x000000000000007f - -/* SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCB */ -/* Description: group 2 ecc */ -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCB_SHFT 7 -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCB_MASK 0x0000000000003f80 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY" */ -/* y directory pio read data */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY 0x0000000100032800 -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_MASK 0x0fffffffffffffff -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRA */ -/* Description: directory entry A */ -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRA_SHFT 0 -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRA_MASK 0x0000000003ffffff - -/* SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRB */ -/* Description: directory entry B */ -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRB_SHFT 26 -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRB_MASK 0x000ffffffc000000 - -/* SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_PRI */ -/* Description: directory priority */ -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_PRI_SHFT 52 -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_PRI_MASK 0x0070000000000000 - -/* SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_ACC */ -/* Description: directory access bits */ -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_ACC_SHFT 55 -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_ACC_MASK 0x0380000000000000 - -/* SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_COR */ -/* Description: correctable ecc error */ -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_COR_SHFT 58 -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_COR_MASK 0x0400000000000000 - -/* SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_UNC */ -/* Description: uncorrectable ecc error */ -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_UNC_SHFT 59 -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_UNC_MASK 0x0800000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YPIORD_YDIR_ECC" */ -/* y directory ecc */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC 0x0000000100032810 -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_MASK 0x0000000000003fff -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCA */ -/* Description: group 1 ecc */ -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCA_SHFT 0 -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCA_MASK 0x000000000000007f - -/* SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCB */ -/* Description: group 2 ecc */ -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCB_SHFT 7 -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCB_MASK 0x0000000000003f80 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XCERR1" */ -/* correctable dir ecc group 1 error register */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_XCERR1 0x0000000100033000 -#define SH_MD_DQLP_MMR_XCERR1_MASK 0x0000007fffffffff -#define SH_MD_DQLP_MMR_XCERR1_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_XCERR1_GRP1 */ -/* Description: ecc group 1 bits */ -#define SH_MD_DQLP_MMR_XCERR1_GRP1_SHFT 0 -#define SH_MD_DQLP_MMR_XCERR1_GRP1_MASK 0x0000000fffffffff - -/* SH_MD_DQLP_MMR_XCERR1_VAL */ -/* Description: correctable ecc error in group 1 bits */ -#define SH_MD_DQLP_MMR_XCERR1_VAL_SHFT 36 -#define SH_MD_DQLP_MMR_XCERR1_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQLP_MMR_XCERR1_MORE */ -/* Description: more than one correctable ecc error in group 1 */ -#define SH_MD_DQLP_MMR_XCERR1_MORE_SHFT 37 -#define SH_MD_DQLP_MMR_XCERR1_MORE_MASK 0x0000002000000000 - -/* SH_MD_DQLP_MMR_XCERR1_ARM */ -/* Description: writing 1 arms uncorrectable ecc error capture */ -#define SH_MD_DQLP_MMR_XCERR1_ARM_SHFT 38 -#define SH_MD_DQLP_MMR_XCERR1_ARM_MASK 0x0000004000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XCERR2" */ -/* correctable dir ecc group 2 error register */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_XCERR2 0x0000000100033010 -#define SH_MD_DQLP_MMR_XCERR2_MASK 0x0000003fffffffff -#define SH_MD_DQLP_MMR_XCERR2_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_XCERR2_GRP2 */ -/* Description: ecc group 2 bits */ -#define SH_MD_DQLP_MMR_XCERR2_GRP2_SHFT 0 -#define SH_MD_DQLP_MMR_XCERR2_GRP2_MASK 0x0000000fffffffff - -/* SH_MD_DQLP_MMR_XCERR2_VAL */ -/* Description: correctable ecc error in group 2 bits */ -#define SH_MD_DQLP_MMR_XCERR2_VAL_SHFT 36 -#define SH_MD_DQLP_MMR_XCERR2_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQLP_MMR_XCERR2_MORE */ -/* Description: more than one correctable ecc error in group 2 */ -#define SH_MD_DQLP_MMR_XCERR2_MORE_SHFT 37 -#define SH_MD_DQLP_MMR_XCERR2_MORE_MASK 0x0000002000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XUERR1" */ -/* uncorrectable dir ecc group 1 error register */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_XUERR1 0x0000000100033020 -#define SH_MD_DQLP_MMR_XUERR1_MASK 0x0000007fffffffff -#define SH_MD_DQLP_MMR_XUERR1_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_XUERR1_GRP1 */ -/* Description: ecc group 1 bits */ -#define SH_MD_DQLP_MMR_XUERR1_GRP1_SHFT 0 -#define SH_MD_DQLP_MMR_XUERR1_GRP1_MASK 0x0000000fffffffff - -/* SH_MD_DQLP_MMR_XUERR1_VAL */ -/* Description: uncorrectable ecc error in group 1 bits */ -#define SH_MD_DQLP_MMR_XUERR1_VAL_SHFT 36 -#define SH_MD_DQLP_MMR_XUERR1_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQLP_MMR_XUERR1_MORE */ -/* Description: more than one uncorrectable ecc error in group 1 */ -#define SH_MD_DQLP_MMR_XUERR1_MORE_SHFT 37 -#define SH_MD_DQLP_MMR_XUERR1_MORE_MASK 0x0000002000000000 - -/* SH_MD_DQLP_MMR_XUERR1_ARM */ -/* Description: writing 1 arms uncorrectable ecc error capture */ -#define SH_MD_DQLP_MMR_XUERR1_ARM_SHFT 38 -#define SH_MD_DQLP_MMR_XUERR1_ARM_MASK 0x0000004000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XUERR2" */ -/* uncorrectable dir ecc group 2 error register */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_XUERR2 0x0000000100033030 -#define SH_MD_DQLP_MMR_XUERR2_MASK 0x0000003fffffffff -#define SH_MD_DQLP_MMR_XUERR2_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_XUERR2_GRP2 */ -/* Description: ecc group 2 bits */ -#define SH_MD_DQLP_MMR_XUERR2_GRP2_SHFT 0 -#define SH_MD_DQLP_MMR_XUERR2_GRP2_MASK 0x0000000fffffffff - -/* SH_MD_DQLP_MMR_XUERR2_VAL */ -/* Description: uncorrectable ecc error in group 2 bits */ -#define SH_MD_DQLP_MMR_XUERR2_VAL_SHFT 36 -#define SH_MD_DQLP_MMR_XUERR2_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQLP_MMR_XUERR2_MORE */ -/* Description: more than one uncorrectable ecc error in group 2 */ -#define SH_MD_DQLP_MMR_XUERR2_MORE_SHFT 37 -#define SH_MD_DQLP_MMR_XUERR2_MORE_MASK 0x0000002000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XPERR" */ -/* protocol error register */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_XPERR 0x0000000100033040 -#define SH_MD_DQLP_MMR_XPERR_MASK 0x7fffffffffffffff -#define SH_MD_DQLP_MMR_XPERR_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_XPERR_DIR */ -/* Description: directory entry */ -#define SH_MD_DQLP_MMR_XPERR_DIR_SHFT 0 -#define SH_MD_DQLP_MMR_XPERR_DIR_MASK 0x0000000003ffffff - -/* SH_MD_DQLP_MMR_XPERR_CMD */ -/* Description: incoming command */ -#define SH_MD_DQLP_MMR_XPERR_CMD_SHFT 26 -#define SH_MD_DQLP_MMR_XPERR_CMD_MASK 0x00000003fc000000 - -/* SH_MD_DQLP_MMR_XPERR_SRC */ -/* Description: source node of dir operation */ -#define SH_MD_DQLP_MMR_XPERR_SRC_SHFT 34 -#define SH_MD_DQLP_MMR_XPERR_SRC_MASK 0x0000fffc00000000 - -/* SH_MD_DQLP_MMR_XPERR_PRIGE */ -/* Description: priority was greater-equal */ -#define SH_MD_DQLP_MMR_XPERR_PRIGE_SHFT 48 -#define SH_MD_DQLP_MMR_XPERR_PRIGE_MASK 0x0001000000000000 - -/* SH_MD_DQLP_MMR_XPERR_PRIV */ -/* Description: access privilege bit */ -#define SH_MD_DQLP_MMR_XPERR_PRIV_SHFT 49 -#define SH_MD_DQLP_MMR_XPERR_PRIV_MASK 0x0002000000000000 - -/* SH_MD_DQLP_MMR_XPERR_COR */ -/* Description: correctable ecc error */ -#define SH_MD_DQLP_MMR_XPERR_COR_SHFT 50 -#define SH_MD_DQLP_MMR_XPERR_COR_MASK 0x0004000000000000 - -/* SH_MD_DQLP_MMR_XPERR_UNC */ -/* Description: uncorrectable ecc error */ -#define SH_MD_DQLP_MMR_XPERR_UNC_SHFT 51 -#define SH_MD_DQLP_MMR_XPERR_UNC_MASK 0x0008000000000000 - -/* SH_MD_DQLP_MMR_XPERR_MYBIT */ -/* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */ -#define SH_MD_DQLP_MMR_XPERR_MYBIT_SHFT 52 -#define SH_MD_DQLP_MMR_XPERR_MYBIT_MASK 0x0ff0000000000000 - -/* SH_MD_DQLP_MMR_XPERR_VAL */ -/* Description: protocol error info valid */ -#define SH_MD_DQLP_MMR_XPERR_VAL_SHFT 60 -#define SH_MD_DQLP_MMR_XPERR_VAL_MASK 0x1000000000000000 - -/* SH_MD_DQLP_MMR_XPERR_MORE */ -/* Description: more than one protocol error */ -#define SH_MD_DQLP_MMR_XPERR_MORE_SHFT 61 -#define SH_MD_DQLP_MMR_XPERR_MORE_MASK 0x2000000000000000 - -/* SH_MD_DQLP_MMR_XPERR_ARM */ -/* Description: writing 1 arms error capture */ -#define SH_MD_DQLP_MMR_XPERR_ARM_SHFT 62 -#define SH_MD_DQLP_MMR_XPERR_ARM_MASK 0x4000000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YCERR1" */ -/* correctable dir ecc group 1 error register */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_YCERR1 0x0000000100033800 -#define SH_MD_DQLP_MMR_YCERR1_MASK 0x0000007fffffffff -#define SH_MD_DQLP_MMR_YCERR1_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_YCERR1_GRP1 */ -/* Description: ecc group 1 bits */ -#define SH_MD_DQLP_MMR_YCERR1_GRP1_SHFT 0 -#define SH_MD_DQLP_MMR_YCERR1_GRP1_MASK 0x0000000fffffffff - -/* SH_MD_DQLP_MMR_YCERR1_VAL */ -/* Description: correctable ecc error in group 1 bits */ -#define SH_MD_DQLP_MMR_YCERR1_VAL_SHFT 36 -#define SH_MD_DQLP_MMR_YCERR1_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQLP_MMR_YCERR1_MORE */ -/* Description: more than one correctable ecc error in group 1 */ -#define SH_MD_DQLP_MMR_YCERR1_MORE_SHFT 37 -#define SH_MD_DQLP_MMR_YCERR1_MORE_MASK 0x0000002000000000 - -/* SH_MD_DQLP_MMR_YCERR1_ARM */ -/* Description: writing 1 arms uncorrectable ecc error capture */ -#define SH_MD_DQLP_MMR_YCERR1_ARM_SHFT 38 -#define SH_MD_DQLP_MMR_YCERR1_ARM_MASK 0x0000004000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YCERR2" */ -/* correctable dir ecc group 2 error register */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_YCERR2 0x0000000100033810 -#define SH_MD_DQLP_MMR_YCERR2_MASK 0x0000003fffffffff -#define SH_MD_DQLP_MMR_YCERR2_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_YCERR2_GRP2 */ -/* Description: ecc group 2 bits */ -#define SH_MD_DQLP_MMR_YCERR2_GRP2_SHFT 0 -#define SH_MD_DQLP_MMR_YCERR2_GRP2_MASK 0x0000000fffffffff - -/* SH_MD_DQLP_MMR_YCERR2_VAL */ -/* Description: correctable ecc error in group 2 bits */ -#define SH_MD_DQLP_MMR_YCERR2_VAL_SHFT 36 -#define SH_MD_DQLP_MMR_YCERR2_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQLP_MMR_YCERR2_MORE */ -/* Description: more than one correctable ecc error in group 2 */ -#define SH_MD_DQLP_MMR_YCERR2_MORE_SHFT 37 -#define SH_MD_DQLP_MMR_YCERR2_MORE_MASK 0x0000002000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YUERR1" */ -/* uncorrectable dir ecc group 1 error register */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_YUERR1 0x0000000100033820 -#define SH_MD_DQLP_MMR_YUERR1_MASK 0x0000007fffffffff -#define SH_MD_DQLP_MMR_YUERR1_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_YUERR1_GRP1 */ -/* Description: ecc group 1 bits */ -#define SH_MD_DQLP_MMR_YUERR1_GRP1_SHFT 0 -#define SH_MD_DQLP_MMR_YUERR1_GRP1_MASK 0x0000000fffffffff - -/* SH_MD_DQLP_MMR_YUERR1_VAL */ -/* Description: uncorrectable ecc error in group 1 bits */ -#define SH_MD_DQLP_MMR_YUERR1_VAL_SHFT 36 -#define SH_MD_DQLP_MMR_YUERR1_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQLP_MMR_YUERR1_MORE */ -/* Description: more than one uncorrectable ecc error in group 1 */ -#define SH_MD_DQLP_MMR_YUERR1_MORE_SHFT 37 -#define SH_MD_DQLP_MMR_YUERR1_MORE_MASK 0x0000002000000000 - -/* SH_MD_DQLP_MMR_YUERR1_ARM */ -/* Description: writing 1 arms uncorrectable ecc error capture */ -#define SH_MD_DQLP_MMR_YUERR1_ARM_SHFT 38 -#define SH_MD_DQLP_MMR_YUERR1_ARM_MASK 0x0000004000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YUERR2" */ -/* uncorrectable dir ecc group 2 error register */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_YUERR2 0x0000000100033830 -#define SH_MD_DQLP_MMR_YUERR2_MASK 0x0000003fffffffff -#define SH_MD_DQLP_MMR_YUERR2_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_YUERR2_GRP2 */ -/* Description: ecc group 2 bits */ -#define SH_MD_DQLP_MMR_YUERR2_GRP2_SHFT 0 -#define SH_MD_DQLP_MMR_YUERR2_GRP2_MASK 0x0000000fffffffff - -/* SH_MD_DQLP_MMR_YUERR2_VAL */ -/* Description: uncorrectable ecc error in group 2 bits */ -#define SH_MD_DQLP_MMR_YUERR2_VAL_SHFT 36 -#define SH_MD_DQLP_MMR_YUERR2_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQLP_MMR_YUERR2_MORE */ -/* Description: more than one uncorrectable ecc error in group 2 */ -#define SH_MD_DQLP_MMR_YUERR2_MORE_SHFT 37 -#define SH_MD_DQLP_MMR_YUERR2_MORE_MASK 0x0000002000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YPERR" */ -/* protocol error register */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_YPERR 0x0000000100033840 -#define SH_MD_DQLP_MMR_YPERR_MASK 0x7fffffffffffffff -#define SH_MD_DQLP_MMR_YPERR_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_YPERR_DIR */ -/* Description: directory entry */ -#define SH_MD_DQLP_MMR_YPERR_DIR_SHFT 0 -#define SH_MD_DQLP_MMR_YPERR_DIR_MASK 0x0000000003ffffff - -/* SH_MD_DQLP_MMR_YPERR_CMD */ -/* Description: incoming command */ -#define SH_MD_DQLP_MMR_YPERR_CMD_SHFT 26 -#define SH_MD_DQLP_MMR_YPERR_CMD_MASK 0x00000003fc000000 - -/* SH_MD_DQLP_MMR_YPERR_SRC */ -/* Description: source node of dir operation */ -#define SH_MD_DQLP_MMR_YPERR_SRC_SHFT 34 -#define SH_MD_DQLP_MMR_YPERR_SRC_MASK 0x0000fffc00000000 - -/* SH_MD_DQLP_MMR_YPERR_PRIGE */ -/* Description: priority was greater-equal */ -#define SH_MD_DQLP_MMR_YPERR_PRIGE_SHFT 48 -#define SH_MD_DQLP_MMR_YPERR_PRIGE_MASK 0x0001000000000000 - -/* SH_MD_DQLP_MMR_YPERR_PRIV */ -/* Description: access privilege bit */ -#define SH_MD_DQLP_MMR_YPERR_PRIV_SHFT 49 -#define SH_MD_DQLP_MMR_YPERR_PRIV_MASK 0x0002000000000000 - -/* SH_MD_DQLP_MMR_YPERR_COR */ -/* Description: correctable ecc error */ -#define SH_MD_DQLP_MMR_YPERR_COR_SHFT 50 -#define SH_MD_DQLP_MMR_YPERR_COR_MASK 0x0004000000000000 - -/* SH_MD_DQLP_MMR_YPERR_UNC */ -/* Description: uncorrectable ecc error */ -#define SH_MD_DQLP_MMR_YPERR_UNC_SHFT 51 -#define SH_MD_DQLP_MMR_YPERR_UNC_MASK 0x0008000000000000 - -/* SH_MD_DQLP_MMR_YPERR_MYBIT */ -/* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */ -#define SH_MD_DQLP_MMR_YPERR_MYBIT_SHFT 52 -#define SH_MD_DQLP_MMR_YPERR_MYBIT_MASK 0x0ff0000000000000 - -/* SH_MD_DQLP_MMR_YPERR_VAL */ -/* Description: protocol error info valid */ -#define SH_MD_DQLP_MMR_YPERR_VAL_SHFT 60 -#define SH_MD_DQLP_MMR_YPERR_VAL_MASK 0x1000000000000000 - -/* SH_MD_DQLP_MMR_YPERR_MORE */ -/* Description: more than one protocol error */ -#define SH_MD_DQLP_MMR_YPERR_MORE_SHFT 61 -#define SH_MD_DQLP_MMR_YPERR_MORE_MASK 0x2000000000000000 - -/* SH_MD_DQLP_MMR_YPERR_ARM */ -/* Description: writing 1 arms error capture */ -#define SH_MD_DQLP_MMR_YPERR_ARM_SHFT 62 -#define SH_MD_DQLP_MMR_YPERR_ARM_MASK 0x4000000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_CMDTRIG" */ -/* cmd triggers */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_CMDTRIG 0x0000000100034000 -#define SH_MD_DQLP_MMR_DIR_CMDTRIG_MASK 0x00000000ffffffff -#define SH_MD_DQLP_MMR_DIR_CMDTRIG_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD0 */ -/* Description: command trigger 0 */ -#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD0_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD0_MASK 0x00000000000000ff - -/* SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD1 */ -/* Description: command trigger 1 */ -#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD1_SHFT 8 -#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD1_MASK 0x000000000000ff00 - -/* SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD2 */ -/* Description: command trigger 2 */ -#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD2_SHFT 16 -#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD2_MASK 0x0000000000ff0000 - -/* SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD3 */ -/* Description: command trigger 3 */ -#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD3_SHFT 24 -#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD3_MASK 0x00000000ff000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_TBLTRIG" */ -/* dir table trigger */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_TBLTRIG 0x0000000100034010 -#define SH_MD_DQLP_MMR_DIR_TBLTRIG_MASK 0x000003ffffffffff -#define SH_MD_DQLP_MMR_DIR_TBLTRIG_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_TBLTRIG_SRC */ -/* Description: source of request */ -#define SH_MD_DQLP_MMR_DIR_TBLTRIG_SRC_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_TBLTRIG_SRC_MASK 0x0000000000003fff - -/* SH_MD_DQLP_MMR_DIR_TBLTRIG_CMD */ -/* Description: incoming request */ -#define SH_MD_DQLP_MMR_DIR_TBLTRIG_CMD_SHFT 14 -#define SH_MD_DQLP_MMR_DIR_TBLTRIG_CMD_MASK 0x00000000003fc000 - -/* SH_MD_DQLP_MMR_DIR_TBLTRIG_ACC */ -/* Description: uncorrectable error, privilege bit */ -#define SH_MD_DQLP_MMR_DIR_TBLTRIG_ACC_SHFT 22 -#define SH_MD_DQLP_MMR_DIR_TBLTRIG_ACC_MASK 0x0000000000c00000 - -/* SH_MD_DQLP_MMR_DIR_TBLTRIG_PRIGE */ -/* Description: priority greater-equal */ -#define SH_MD_DQLP_MMR_DIR_TBLTRIG_PRIGE_SHFT 24 -#define SH_MD_DQLP_MMR_DIR_TBLTRIG_PRIGE_MASK 0x0000000001000000 - -/* SH_MD_DQLP_MMR_DIR_TBLTRIG_DIRST */ -/* Description: shrd,sxro,sub-state */ -#define SH_MD_DQLP_MMR_DIR_TBLTRIG_DIRST_SHFT 25 -#define SH_MD_DQLP_MMR_DIR_TBLTRIG_DIRST_MASK 0x00000003fe000000 - -/* SH_MD_DQLP_MMR_DIR_TBLTRIG_MYBIT */ -/* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */ -#define SH_MD_DQLP_MMR_DIR_TBLTRIG_MYBIT_SHFT 34 -#define SH_MD_DQLP_MMR_DIR_TBLTRIG_MYBIT_MASK 0x000003fc00000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_TBLMASK" */ -/* dir table trigger mask */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_TBLMASK 0x0000000100034020 -#define SH_MD_DQLP_MMR_DIR_TBLMASK_MASK 0x000003ffffffffff -#define SH_MD_DQLP_MMR_DIR_TBLMASK_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_TBLMASK_SRC */ -/* Description: source of request */ -#define SH_MD_DQLP_MMR_DIR_TBLMASK_SRC_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_TBLMASK_SRC_MASK 0x0000000000003fff - -/* SH_MD_DQLP_MMR_DIR_TBLMASK_CMD */ -/* Description: incoming request */ -#define SH_MD_DQLP_MMR_DIR_TBLMASK_CMD_SHFT 14 -#define SH_MD_DQLP_MMR_DIR_TBLMASK_CMD_MASK 0x00000000003fc000 - -/* SH_MD_DQLP_MMR_DIR_TBLMASK_ACC */ -/* Description: uncorrectable error, privilege bit */ -#define SH_MD_DQLP_MMR_DIR_TBLMASK_ACC_SHFT 22 -#define SH_MD_DQLP_MMR_DIR_TBLMASK_ACC_MASK 0x0000000000c00000 - -/* SH_MD_DQLP_MMR_DIR_TBLMASK_PRIGE */ -/* Description: priority greater-equal */ -#define SH_MD_DQLP_MMR_DIR_TBLMASK_PRIGE_SHFT 24 -#define SH_MD_DQLP_MMR_DIR_TBLMASK_PRIGE_MASK 0x0000000001000000 - -/* SH_MD_DQLP_MMR_DIR_TBLMASK_DIRST */ -/* Description: shrd,sxro,sub-state */ -#define SH_MD_DQLP_MMR_DIR_TBLMASK_DIRST_SHFT 25 -#define SH_MD_DQLP_MMR_DIR_TBLMASK_DIRST_MASK 0x00000003fe000000 - -/* SH_MD_DQLP_MMR_DIR_TBLMASK_MYBIT */ -/* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */ -#define SH_MD_DQLP_MMR_DIR_TBLMASK_MYBIT_SHFT 34 -#define SH_MD_DQLP_MMR_DIR_TBLMASK_MYBIT_MASK 0x000003fc00000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XBIST_H" */ -/* rising edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_XBIST_H 0x0000000100038000 -#define SH_MD_DQLP_MMR_XBIST_H_MASK 0x00000700ffffffff -#define SH_MD_DQLP_MMR_XBIST_H_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_XBIST_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLP_MMR_XBIST_H_PAT_SHFT 0 -#define SH_MD_DQLP_MMR_XBIST_H_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQLP_MMR_XBIST_H_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQLP_MMR_XBIST_H_INV_SHFT 40 -#define SH_MD_DQLP_MMR_XBIST_H_INV_MASK 0x0000010000000000 - -/* SH_MD_DQLP_MMR_XBIST_H_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQLP_MMR_XBIST_H_ROT_SHFT 41 -#define SH_MD_DQLP_MMR_XBIST_H_ROT_MASK 0x0000020000000000 - -/* SH_MD_DQLP_MMR_XBIST_H_ARM */ -/* Description: writing 1 arms data miscompare capture */ -#define SH_MD_DQLP_MMR_XBIST_H_ARM_SHFT 42 -#define SH_MD_DQLP_MMR_XBIST_H_ARM_MASK 0x0000040000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XBIST_L" */ -/* falling edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_XBIST_L 0x0000000100038010 -#define SH_MD_DQLP_MMR_XBIST_L_MASK 0x00000300ffffffff -#define SH_MD_DQLP_MMR_XBIST_L_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_XBIST_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLP_MMR_XBIST_L_PAT_SHFT 0 -#define SH_MD_DQLP_MMR_XBIST_L_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQLP_MMR_XBIST_L_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQLP_MMR_XBIST_L_INV_SHFT 40 -#define SH_MD_DQLP_MMR_XBIST_L_INV_MASK 0x0000010000000000 - -/* SH_MD_DQLP_MMR_XBIST_L_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQLP_MMR_XBIST_L_ROT_SHFT 41 -#define SH_MD_DQLP_MMR_XBIST_L_ROT_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XBIST_ERR_H" */ -/* rising edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_XBIST_ERR_H 0x0000000100038020 -#define SH_MD_DQLP_MMR_XBIST_ERR_H_MASK 0x00000300ffffffff -#define SH_MD_DQLP_MMR_XBIST_ERR_H_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_XBIST_ERR_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLP_MMR_XBIST_ERR_H_PAT_SHFT 0 -#define SH_MD_DQLP_MMR_XBIST_ERR_H_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQLP_MMR_XBIST_ERR_H_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQLP_MMR_XBIST_ERR_H_VAL_SHFT 40 -#define SH_MD_DQLP_MMR_XBIST_ERR_H_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQLP_MMR_XBIST_ERR_H_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQLP_MMR_XBIST_ERR_H_MORE_SHFT 41 -#define SH_MD_DQLP_MMR_XBIST_ERR_H_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XBIST_ERR_L" */ -/* falling edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_XBIST_ERR_L 0x0000000100038030 -#define SH_MD_DQLP_MMR_XBIST_ERR_L_MASK 0x00000300ffffffff -#define SH_MD_DQLP_MMR_XBIST_ERR_L_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_XBIST_ERR_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLP_MMR_XBIST_ERR_L_PAT_SHFT 0 -#define SH_MD_DQLP_MMR_XBIST_ERR_L_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQLP_MMR_XBIST_ERR_L_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQLP_MMR_XBIST_ERR_L_VAL_SHFT 40 -#define SH_MD_DQLP_MMR_XBIST_ERR_L_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQLP_MMR_XBIST_ERR_L_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQLP_MMR_XBIST_ERR_L_MORE_SHFT 41 -#define SH_MD_DQLP_MMR_XBIST_ERR_L_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YBIST_H" */ -/* rising edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_YBIST_H 0x0000000100038800 -#define SH_MD_DQLP_MMR_YBIST_H_MASK 0x00000700ffffffff -#define SH_MD_DQLP_MMR_YBIST_H_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_YBIST_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLP_MMR_YBIST_H_PAT_SHFT 0 -#define SH_MD_DQLP_MMR_YBIST_H_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQLP_MMR_YBIST_H_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQLP_MMR_YBIST_H_INV_SHFT 40 -#define SH_MD_DQLP_MMR_YBIST_H_INV_MASK 0x0000010000000000 - -/* SH_MD_DQLP_MMR_YBIST_H_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQLP_MMR_YBIST_H_ROT_SHFT 41 -#define SH_MD_DQLP_MMR_YBIST_H_ROT_MASK 0x0000020000000000 - -/* SH_MD_DQLP_MMR_YBIST_H_ARM */ -/* Description: writing 1 arms data miscompare capture */ -#define SH_MD_DQLP_MMR_YBIST_H_ARM_SHFT 42 -#define SH_MD_DQLP_MMR_YBIST_H_ARM_MASK 0x0000040000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YBIST_L" */ -/* falling edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_YBIST_L 0x0000000100038810 -#define SH_MD_DQLP_MMR_YBIST_L_MASK 0x00000300ffffffff -#define SH_MD_DQLP_MMR_YBIST_L_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_YBIST_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLP_MMR_YBIST_L_PAT_SHFT 0 -#define SH_MD_DQLP_MMR_YBIST_L_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQLP_MMR_YBIST_L_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQLP_MMR_YBIST_L_INV_SHFT 40 -#define SH_MD_DQLP_MMR_YBIST_L_INV_MASK 0x0000010000000000 - -/* SH_MD_DQLP_MMR_YBIST_L_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQLP_MMR_YBIST_L_ROT_SHFT 41 -#define SH_MD_DQLP_MMR_YBIST_L_ROT_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YBIST_ERR_H" */ -/* rising edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_YBIST_ERR_H 0x0000000100038820 -#define SH_MD_DQLP_MMR_YBIST_ERR_H_MASK 0x00000300ffffffff -#define SH_MD_DQLP_MMR_YBIST_ERR_H_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_YBIST_ERR_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLP_MMR_YBIST_ERR_H_PAT_SHFT 0 -#define SH_MD_DQLP_MMR_YBIST_ERR_H_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQLP_MMR_YBIST_ERR_H_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQLP_MMR_YBIST_ERR_H_VAL_SHFT 40 -#define SH_MD_DQLP_MMR_YBIST_ERR_H_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQLP_MMR_YBIST_ERR_H_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQLP_MMR_YBIST_ERR_H_MORE_SHFT 41 -#define SH_MD_DQLP_MMR_YBIST_ERR_H_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YBIST_ERR_L" */ -/* falling edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_YBIST_ERR_L 0x0000000100038830 -#define SH_MD_DQLP_MMR_YBIST_ERR_L_MASK 0x00000300ffffffff -#define SH_MD_DQLP_MMR_YBIST_ERR_L_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_YBIST_ERR_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLP_MMR_YBIST_ERR_L_PAT_SHFT 0 -#define SH_MD_DQLP_MMR_YBIST_ERR_L_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQLP_MMR_YBIST_ERR_L_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQLP_MMR_YBIST_ERR_L_VAL_SHFT 40 -#define SH_MD_DQLP_MMR_YBIST_ERR_L_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQLP_MMR_YBIST_ERR_L_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQLP_MMR_YBIST_ERR_L_MORE_SHFT 41 -#define SH_MD_DQLP_MMR_YBIST_ERR_L_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLS_MMR_XBIST_H" */ -/* rising edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLS_MMR_XBIST_H 0x0000000100048000 -#define SH_MD_DQLS_MMR_XBIST_H_MASK 0x000007ffffffffff -#define SH_MD_DQLS_MMR_XBIST_H_INIT 0x0000000000000000 - -/* SH_MD_DQLS_MMR_XBIST_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLS_MMR_XBIST_H_PAT_SHFT 0 -#define SH_MD_DQLS_MMR_XBIST_H_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQLS_MMR_XBIST_H_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQLS_MMR_XBIST_H_INV_SHFT 40 -#define SH_MD_DQLS_MMR_XBIST_H_INV_MASK 0x0000010000000000 - -/* SH_MD_DQLS_MMR_XBIST_H_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQLS_MMR_XBIST_H_ROT_SHFT 41 -#define SH_MD_DQLS_MMR_XBIST_H_ROT_MASK 0x0000020000000000 - -/* SH_MD_DQLS_MMR_XBIST_H_ARM */ -/* Description: writing 1 arms data miscompare capture */ -#define SH_MD_DQLS_MMR_XBIST_H_ARM_SHFT 42 -#define SH_MD_DQLS_MMR_XBIST_H_ARM_MASK 0x0000040000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLS_MMR_XBIST_L" */ -/* falling edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLS_MMR_XBIST_L 0x0000000100048010 -#define SH_MD_DQLS_MMR_XBIST_L_MASK 0x000003ffffffffff -#define SH_MD_DQLS_MMR_XBIST_L_INIT 0x0000000000000000 - -/* SH_MD_DQLS_MMR_XBIST_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLS_MMR_XBIST_L_PAT_SHFT 0 -#define SH_MD_DQLS_MMR_XBIST_L_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQLS_MMR_XBIST_L_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQLS_MMR_XBIST_L_INV_SHFT 40 -#define SH_MD_DQLS_MMR_XBIST_L_INV_MASK 0x0000010000000000 - -/* SH_MD_DQLS_MMR_XBIST_L_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQLS_MMR_XBIST_L_ROT_SHFT 41 -#define SH_MD_DQLS_MMR_XBIST_L_ROT_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLS_MMR_XBIST_ERR_H" */ -/* rising edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLS_MMR_XBIST_ERR_H 0x0000000100048020 -#define SH_MD_DQLS_MMR_XBIST_ERR_H_MASK 0x000003ffffffffff -#define SH_MD_DQLS_MMR_XBIST_ERR_H_INIT 0x0000000000000000 - -/* SH_MD_DQLS_MMR_XBIST_ERR_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLS_MMR_XBIST_ERR_H_PAT_SHFT 0 -#define SH_MD_DQLS_MMR_XBIST_ERR_H_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQLS_MMR_XBIST_ERR_H_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQLS_MMR_XBIST_ERR_H_VAL_SHFT 40 -#define SH_MD_DQLS_MMR_XBIST_ERR_H_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQLS_MMR_XBIST_ERR_H_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQLS_MMR_XBIST_ERR_H_MORE_SHFT 41 -#define SH_MD_DQLS_MMR_XBIST_ERR_H_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLS_MMR_XBIST_ERR_L" */ -/* falling edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLS_MMR_XBIST_ERR_L 0x0000000100048030 -#define SH_MD_DQLS_MMR_XBIST_ERR_L_MASK 0x000003ffffffffff -#define SH_MD_DQLS_MMR_XBIST_ERR_L_INIT 0x0000000000000000 - -/* SH_MD_DQLS_MMR_XBIST_ERR_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLS_MMR_XBIST_ERR_L_PAT_SHFT 0 -#define SH_MD_DQLS_MMR_XBIST_ERR_L_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQLS_MMR_XBIST_ERR_L_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQLS_MMR_XBIST_ERR_L_VAL_SHFT 40 -#define SH_MD_DQLS_MMR_XBIST_ERR_L_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQLS_MMR_XBIST_ERR_L_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQLS_MMR_XBIST_ERR_L_MORE_SHFT 41 -#define SH_MD_DQLS_MMR_XBIST_ERR_L_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLS_MMR_YBIST_H" */ -/* rising edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLS_MMR_YBIST_H 0x0000000100048800 -#define SH_MD_DQLS_MMR_YBIST_H_MASK 0x000007ffffffffff -#define SH_MD_DQLS_MMR_YBIST_H_INIT 0x0000000000000000 - -/* SH_MD_DQLS_MMR_YBIST_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLS_MMR_YBIST_H_PAT_SHFT 0 -#define SH_MD_DQLS_MMR_YBIST_H_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQLS_MMR_YBIST_H_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQLS_MMR_YBIST_H_INV_SHFT 40 -#define SH_MD_DQLS_MMR_YBIST_H_INV_MASK 0x0000010000000000 - -/* SH_MD_DQLS_MMR_YBIST_H_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQLS_MMR_YBIST_H_ROT_SHFT 41 -#define SH_MD_DQLS_MMR_YBIST_H_ROT_MASK 0x0000020000000000 - -/* SH_MD_DQLS_MMR_YBIST_H_ARM */ -/* Description: writing 1 arms data miscompare capture */ -#define SH_MD_DQLS_MMR_YBIST_H_ARM_SHFT 42 -#define SH_MD_DQLS_MMR_YBIST_H_ARM_MASK 0x0000040000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLS_MMR_YBIST_L" */ -/* falling edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLS_MMR_YBIST_L 0x0000000100048810 -#define SH_MD_DQLS_MMR_YBIST_L_MASK 0x000003ffffffffff -#define SH_MD_DQLS_MMR_YBIST_L_INIT 0x0000000000000000 - -/* SH_MD_DQLS_MMR_YBIST_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLS_MMR_YBIST_L_PAT_SHFT 0 -#define SH_MD_DQLS_MMR_YBIST_L_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQLS_MMR_YBIST_L_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQLS_MMR_YBIST_L_INV_SHFT 40 -#define SH_MD_DQLS_MMR_YBIST_L_INV_MASK 0x0000010000000000 - -/* SH_MD_DQLS_MMR_YBIST_L_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQLS_MMR_YBIST_L_ROT_SHFT 41 -#define SH_MD_DQLS_MMR_YBIST_L_ROT_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLS_MMR_YBIST_ERR_H" */ -/* rising edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLS_MMR_YBIST_ERR_H 0x0000000100048820 -#define SH_MD_DQLS_MMR_YBIST_ERR_H_MASK 0x000003ffffffffff -#define SH_MD_DQLS_MMR_YBIST_ERR_H_INIT 0x0000000000000000 - -/* SH_MD_DQLS_MMR_YBIST_ERR_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLS_MMR_YBIST_ERR_H_PAT_SHFT 0 -#define SH_MD_DQLS_MMR_YBIST_ERR_H_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQLS_MMR_YBIST_ERR_H_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQLS_MMR_YBIST_ERR_H_VAL_SHFT 40 -#define SH_MD_DQLS_MMR_YBIST_ERR_H_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQLS_MMR_YBIST_ERR_H_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQLS_MMR_YBIST_ERR_H_MORE_SHFT 41 -#define SH_MD_DQLS_MMR_YBIST_ERR_H_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLS_MMR_YBIST_ERR_L" */ -/* falling edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLS_MMR_YBIST_ERR_L 0x0000000100048830 -#define SH_MD_DQLS_MMR_YBIST_ERR_L_MASK 0x000003ffffffffff -#define SH_MD_DQLS_MMR_YBIST_ERR_L_INIT 0x0000000000000000 - -/* SH_MD_DQLS_MMR_YBIST_ERR_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLS_MMR_YBIST_ERR_L_PAT_SHFT 0 -#define SH_MD_DQLS_MMR_YBIST_ERR_L_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQLS_MMR_YBIST_ERR_L_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQLS_MMR_YBIST_ERR_L_VAL_SHFT 40 -#define SH_MD_DQLS_MMR_YBIST_ERR_L_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQLS_MMR_YBIST_ERR_L_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQLS_MMR_YBIST_ERR_L_MORE_SHFT 41 -#define SH_MD_DQLS_MMR_YBIST_ERR_L_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLS_MMR_JNR_DEBUG" */ -/* joiner/fct debug configuration */ -/* ==================================================================== */ - -#define SH_MD_DQLS_MMR_JNR_DEBUG 0x0000000100049000 -#define SH_MD_DQLS_MMR_JNR_DEBUG_MASK 0x0000000000000003 -#define SH_MD_DQLS_MMR_JNR_DEBUG_INIT 0x0000000000000000 - -/* SH_MD_DQLS_MMR_JNR_DEBUG_PX */ -/* Description: select 0=pi 1=xn side */ -#define SH_MD_DQLS_MMR_JNR_DEBUG_PX_SHFT 0 -#define SH_MD_DQLS_MMR_JNR_DEBUG_PX_MASK 0x0000000000000001 - -/* SH_MD_DQLS_MMR_JNR_DEBUG_RW */ -/* Description: select 0=read 1=write side */ -#define SH_MD_DQLS_MMR_JNR_DEBUG_RW_SHFT 1 -#define SH_MD_DQLS_MMR_JNR_DEBUG_RW_MASK 0x0000000000000002 - -/* ==================================================================== */ -/* Register "SH_MD_DQLS_MMR_XAMOPW_ERR" */ -/* amo/partial rmw ecc error register */ -/* ==================================================================== */ - -#define SH_MD_DQLS_MMR_XAMOPW_ERR 0x000000010004a000 -#define SH_MD_DQLS_MMR_XAMOPW_ERR_MASK 0x0000000103ff03ff -#define SH_MD_DQLS_MMR_XAMOPW_ERR_INIT 0x0000000000000000 - -/* SH_MD_DQLS_MMR_XAMOPW_ERR_SSYN */ -/* Description: store data syndrome */ -#define SH_MD_DQLS_MMR_XAMOPW_ERR_SSYN_SHFT 0 -#define SH_MD_DQLS_MMR_XAMOPW_ERR_SSYN_MASK 0x00000000000000ff - -/* SH_MD_DQLS_MMR_XAMOPW_ERR_SCOR */ -/* Description: correctable ecc errror on store data */ -#define SH_MD_DQLS_MMR_XAMOPW_ERR_SCOR_SHFT 8 -#define SH_MD_DQLS_MMR_XAMOPW_ERR_SCOR_MASK 0x0000000000000100 - -/* SH_MD_DQLS_MMR_XAMOPW_ERR_SUNC */ -/* Description: uncorrectable ecc errror on store data */ -#define SH_MD_DQLS_MMR_XAMOPW_ERR_SUNC_SHFT 9 -#define SH_MD_DQLS_MMR_XAMOPW_ERR_SUNC_MASK 0x0000000000000200 - -/* SH_MD_DQLS_MMR_XAMOPW_ERR_RSYN */ -/* Description: memory read data syndrome */ -#define SH_MD_DQLS_MMR_XAMOPW_ERR_RSYN_SHFT 16 -#define SH_MD_DQLS_MMR_XAMOPW_ERR_RSYN_MASK 0x0000000000ff0000 - -/* SH_MD_DQLS_MMR_XAMOPW_ERR_RCOR */ -/* Description: correctable ecc errror on read data */ -#define SH_MD_DQLS_MMR_XAMOPW_ERR_RCOR_SHFT 24 -#define SH_MD_DQLS_MMR_XAMOPW_ERR_RCOR_MASK 0x0000000001000000 - -/* SH_MD_DQLS_MMR_XAMOPW_ERR_RUNC */ -/* Description: uncorrectable ecc errror on read data */ -#define SH_MD_DQLS_MMR_XAMOPW_ERR_RUNC_SHFT 25 -#define SH_MD_DQLS_MMR_XAMOPW_ERR_RUNC_MASK 0x0000000002000000 - -/* SH_MD_DQLS_MMR_XAMOPW_ERR_ARM */ -/* Description: writing 1 arms ecc error capture */ -#define SH_MD_DQLS_MMR_XAMOPW_ERR_ARM_SHFT 32 -#define SH_MD_DQLS_MMR_XAMOPW_ERR_ARM_MASK 0x0000000100000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_CONFIG" */ -/* DQ directory config register */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_CONFIG 0x0000000100050000 -#define SH_MD_DQRP_MMR_DIR_CONFIG_MASK 0x000000000000001f -#define SH_MD_DQRP_MMR_DIR_CONFIG_INIT 0x0000000000000010 - -/* SH_MD_DQRP_MMR_DIR_CONFIG_SYS_SIZE */ -/* Description: system size code */ -#define SH_MD_DQRP_MMR_DIR_CONFIG_SYS_SIZE_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_CONFIG_SYS_SIZE_MASK 0x0000000000000007 - -/* SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRECC */ -/* Description: enable directory ecc correction */ -#define SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRECC_SHFT 3 -#define SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRECC_MASK 0x0000000000000008 - -/* SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRPOIS */ -/* Description: enable local poisoning for dir table fall-through */ -#define SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRPOIS_SHFT 4 -#define SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRPOIS_MASK 0x0000000000000010 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRESVEC0" */ -/* node [63:0] presence bits */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_PRESVEC0 0x0000000100050100 -#define SH_MD_DQRP_MMR_DIR_PRESVEC0_MASK 0xffffffffffffffff -#define SH_MD_DQRP_MMR_DIR_PRESVEC0_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_PRESVEC0_VEC */ -/* Description: node presence bits, 1=present */ -#define SH_MD_DQRP_MMR_DIR_PRESVEC0_VEC_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_PRESVEC0_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRESVEC1" */ -/* node [127:64] presence bits */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_PRESVEC1 0x0000000100050110 -#define SH_MD_DQRP_MMR_DIR_PRESVEC1_MASK 0xffffffffffffffff -#define SH_MD_DQRP_MMR_DIR_PRESVEC1_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_PRESVEC1_VEC */ -/* Description: node presence bits, 1=present */ -#define SH_MD_DQRP_MMR_DIR_PRESVEC1_VEC_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_PRESVEC1_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRESVEC2" */ -/* node [191:128] presence bits */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_PRESVEC2 0x0000000100050120 -#define SH_MD_DQRP_MMR_DIR_PRESVEC2_MASK 0xffffffffffffffff -#define SH_MD_DQRP_MMR_DIR_PRESVEC2_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_PRESVEC2_VEC */ -/* Description: node presence bits, 1=present */ -#define SH_MD_DQRP_MMR_DIR_PRESVEC2_VEC_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_PRESVEC2_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRESVEC3" */ -/* node [255:192] presence bits */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_PRESVEC3 0x0000000100050130 -#define SH_MD_DQRP_MMR_DIR_PRESVEC3_MASK 0xffffffffffffffff -#define SH_MD_DQRP_MMR_DIR_PRESVEC3_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_PRESVEC3_VEC */ -/* Description: node presence bits, 1=present */ -#define SH_MD_DQRP_MMR_DIR_PRESVEC3_VEC_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_PRESVEC3_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC0" */ -/* local vector for acc=0 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_LOCVEC0 0x0000000100050200 -#define SH_MD_DQRP_MMR_DIR_LOCVEC0_MASK 0xffffffffffffffff -#define SH_MD_DQRP_MMR_DIR_LOCVEC0_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_LOCVEC0_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQRP_MMR_DIR_LOCVEC0_VEC_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_LOCVEC0_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC1" */ -/* local vector for acc=1 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_LOCVEC1 0x0000000100050210 -#define SH_MD_DQRP_MMR_DIR_LOCVEC1_MASK 0xffffffffffffffff -#define SH_MD_DQRP_MMR_DIR_LOCVEC1_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_LOCVEC1_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQRP_MMR_DIR_LOCVEC1_VEC_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_LOCVEC1_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC2" */ -/* local vector for acc=2 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_LOCVEC2 0x0000000100050220 -#define SH_MD_DQRP_MMR_DIR_LOCVEC2_MASK 0xffffffffffffffff -#define SH_MD_DQRP_MMR_DIR_LOCVEC2_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_LOCVEC2_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQRP_MMR_DIR_LOCVEC2_VEC_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_LOCVEC2_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC3" */ -/* local vector for acc=3 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_LOCVEC3 0x0000000100050230 -#define SH_MD_DQRP_MMR_DIR_LOCVEC3_MASK 0xffffffffffffffff -#define SH_MD_DQRP_MMR_DIR_LOCVEC3_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_LOCVEC3_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQRP_MMR_DIR_LOCVEC3_VEC_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_LOCVEC3_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC4" */ -/* local vector for acc=4 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_LOCVEC4 0x0000000100050240 -#define SH_MD_DQRP_MMR_DIR_LOCVEC4_MASK 0xffffffffffffffff -#define SH_MD_DQRP_MMR_DIR_LOCVEC4_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_LOCVEC4_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQRP_MMR_DIR_LOCVEC4_VEC_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_LOCVEC4_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC5" */ -/* local vector for acc=5 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_LOCVEC5 0x0000000100050250 -#define SH_MD_DQRP_MMR_DIR_LOCVEC5_MASK 0xffffffffffffffff -#define SH_MD_DQRP_MMR_DIR_LOCVEC5_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_LOCVEC5_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQRP_MMR_DIR_LOCVEC5_VEC_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_LOCVEC5_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC6" */ -/* local vector for acc=6 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_LOCVEC6 0x0000000100050260 -#define SH_MD_DQRP_MMR_DIR_LOCVEC6_MASK 0xffffffffffffffff -#define SH_MD_DQRP_MMR_DIR_LOCVEC6_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_LOCVEC6_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQRP_MMR_DIR_LOCVEC6_VEC_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_LOCVEC6_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC7" */ -/* local vector for acc=7 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_LOCVEC7 0x0000000100050270 -#define SH_MD_DQRP_MMR_DIR_LOCVEC7_MASK 0xffffffffffffffff -#define SH_MD_DQRP_MMR_DIR_LOCVEC7_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_LOCVEC7_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQRP_MMR_DIR_LOCVEC7_VEC_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_LOCVEC7_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC0" */ -/* privilege vector for acc=0 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_PRIVEC0 0x0000000100050300 -#define SH_MD_DQRP_MMR_DIR_PRIVEC0_MASK 0x000000000fffffff -#define SH_MD_DQRP_MMR_DIR_PRIVEC0_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_PRIVEC0_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC0_IN_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_PRIVEC0_IN_MASK 0x0000000000003fff - -/* SH_MD_DQRP_MMR_DIR_PRIVEC0_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC0_OUT_SHFT 14 -#define SH_MD_DQRP_MMR_DIR_PRIVEC0_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC1" */ -/* privilege vector for acc=1 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_PRIVEC1 0x0000000100050310 -#define SH_MD_DQRP_MMR_DIR_PRIVEC1_MASK 0x000000000fffffff -#define SH_MD_DQRP_MMR_DIR_PRIVEC1_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_PRIVEC1_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC1_IN_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_PRIVEC1_IN_MASK 0x0000000000003fff - -/* SH_MD_DQRP_MMR_DIR_PRIVEC1_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC1_OUT_SHFT 14 -#define SH_MD_DQRP_MMR_DIR_PRIVEC1_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC2" */ -/* privilege vector for acc=2 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_PRIVEC2 0x0000000100050320 -#define SH_MD_DQRP_MMR_DIR_PRIVEC2_MASK 0x000000000fffffff -#define SH_MD_DQRP_MMR_DIR_PRIVEC2_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_PRIVEC2_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC2_IN_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_PRIVEC2_IN_MASK 0x0000000000003fff - -/* SH_MD_DQRP_MMR_DIR_PRIVEC2_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC2_OUT_SHFT 14 -#define SH_MD_DQRP_MMR_DIR_PRIVEC2_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC3" */ -/* privilege vector for acc=3 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_PRIVEC3 0x0000000100050330 -#define SH_MD_DQRP_MMR_DIR_PRIVEC3_MASK 0x000000000fffffff -#define SH_MD_DQRP_MMR_DIR_PRIVEC3_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_PRIVEC3_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC3_IN_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_PRIVEC3_IN_MASK 0x0000000000003fff - -/* SH_MD_DQRP_MMR_DIR_PRIVEC3_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC3_OUT_SHFT 14 -#define SH_MD_DQRP_MMR_DIR_PRIVEC3_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC4" */ -/* privilege vector for acc=4 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_PRIVEC4 0x0000000100050340 -#define SH_MD_DQRP_MMR_DIR_PRIVEC4_MASK 0x000000000fffffff -#define SH_MD_DQRP_MMR_DIR_PRIVEC4_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_PRIVEC4_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC4_IN_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_PRIVEC4_IN_MASK 0x0000000000003fff - -/* SH_MD_DQRP_MMR_DIR_PRIVEC4_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC4_OUT_SHFT 14 -#define SH_MD_DQRP_MMR_DIR_PRIVEC4_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC5" */ -/* privilege vector for acc=5 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_PRIVEC5 0x0000000100050350 -#define SH_MD_DQRP_MMR_DIR_PRIVEC5_MASK 0x000000000fffffff -#define SH_MD_DQRP_MMR_DIR_PRIVEC5_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_PRIVEC5_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC5_IN_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_PRIVEC5_IN_MASK 0x0000000000003fff - -/* SH_MD_DQRP_MMR_DIR_PRIVEC5_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC5_OUT_SHFT 14 -#define SH_MD_DQRP_MMR_DIR_PRIVEC5_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC6" */ -/* privilege vector for acc=6 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_PRIVEC6 0x0000000100050360 -#define SH_MD_DQRP_MMR_DIR_PRIVEC6_MASK 0x000000000fffffff -#define SH_MD_DQRP_MMR_DIR_PRIVEC6_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_PRIVEC6_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC6_IN_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_PRIVEC6_IN_MASK 0x0000000000003fff - -/* SH_MD_DQRP_MMR_DIR_PRIVEC6_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC6_OUT_SHFT 14 -#define SH_MD_DQRP_MMR_DIR_PRIVEC6_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC7" */ -/* privilege vector for acc=7 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_PRIVEC7 0x0000000100050370 -#define SH_MD_DQRP_MMR_DIR_PRIVEC7_MASK 0x000000000fffffff -#define SH_MD_DQRP_MMR_DIR_PRIVEC7_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_PRIVEC7_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC7_IN_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_PRIVEC7_IN_MASK 0x0000000000003fff - -/* SH_MD_DQRP_MMR_DIR_PRIVEC7_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC7_OUT_SHFT 14 -#define SH_MD_DQRP_MMR_DIR_PRIVEC7_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_TIMER" */ -/* MD SXRO timer */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_TIMER 0x0000000100050400 -#define SH_MD_DQRP_MMR_DIR_TIMER_MASK 0x00000000003fffff -#define SH_MD_DQRP_MMR_DIR_TIMER_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_TIMER_TIMER_DIV */ -/* Description: timer divide register */ -#define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_DIV_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_DIV_MASK 0x0000000000000fff - -/* SH_MD_DQRP_MMR_DIR_TIMER_TIMER_EN */ -/* Description: timer enable */ -#define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_EN_SHFT 12 -#define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_EN_MASK 0x0000000000001000 - -/* SH_MD_DQRP_MMR_DIR_TIMER_TIMER_CUR */ -/* Description: value of current timer */ -#define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_CUR_SHFT 13 -#define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_CUR_MASK 0x00000000003fe000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY" */ -/* directory pio write data */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY 0x0000000100051000 -#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_MASK 0x03ffffffffffffff -#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRA */ -/* Description: directory entry A */ -#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRA_SHFT 0 -#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRA_MASK 0x0000000003ffffff - -/* SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRB */ -/* Description: directory entry B */ -#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRB_SHFT 26 -#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRB_MASK 0x000ffffffc000000 - -/* SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_PRI */ -/* Description: directory priority */ -#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_PRI_SHFT 52 -#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_PRI_MASK 0x0070000000000000 - -/* SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_ACC */ -/* Description: directory access bits */ -#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_ACC_SHFT 55 -#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_ACC_MASK 0x0380000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_PIOWD_DIR_ECC" */ -/* directory ecc register */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC 0x0000000100051010 -#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_MASK 0x0000000000003fff -#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCA */ -/* Description: XOR bits for directory ECC group 1 */ -#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCA_SHFT 0 -#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCA_MASK 0x000000000000007f - -/* SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCB */ -/* Description: XOR bits for directory ECC group 2 */ -#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCB_SHFT 7 -#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCB_MASK 0x0000000000003f80 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY" */ -/* x directory pio read data */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY 0x0000000100052000 -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_MASK 0x0fffffffffffffff -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRA */ -/* Description: directory entry A */ -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRA_SHFT 0 -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRA_MASK 0x0000000003ffffff - -/* SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRB */ -/* Description: directory entry B */ -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRB_SHFT 26 -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRB_MASK 0x000ffffffc000000 - -/* SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_PRI */ -/* Description: directory priority */ -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_PRI_SHFT 52 -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_PRI_MASK 0x0070000000000000 - -/* SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_ACC */ -/* Description: directory access bits */ -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_ACC_SHFT 55 -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_ACC_MASK 0x0380000000000000 - -/* SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_COR */ -/* Description: correctable ecc error */ -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_COR_SHFT 58 -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_COR_MASK 0x0400000000000000 - -/* SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_UNC */ -/* Description: uncorrectable ecc error */ -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_UNC_SHFT 59 -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_UNC_MASK 0x0800000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XPIORD_XDIR_ECC" */ -/* x directory ecc */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC 0x0000000100052010 -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_MASK 0x0000000000003fff -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCA */ -/* Description: group 1 ecc */ -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCA_SHFT 0 -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCA_MASK 0x000000000000007f - -/* SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCB */ -/* Description: group 2 ecc */ -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCB_SHFT 7 -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCB_MASK 0x0000000000003f80 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY" */ -/* y directory pio read data */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY 0x0000000100052800 -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_MASK 0x0fffffffffffffff -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRA */ -/* Description: directory entry A */ -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRA_SHFT 0 -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRA_MASK 0x0000000003ffffff - -/* SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRB */ -/* Description: directory entry B */ -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRB_SHFT 26 -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRB_MASK 0x000ffffffc000000 - -/* SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_PRI */ -/* Description: directory priority */ -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_PRI_SHFT 52 -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_PRI_MASK 0x0070000000000000 - -/* SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_ACC */ -/* Description: directory access bits */ -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_ACC_SHFT 55 -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_ACC_MASK 0x0380000000000000 - -/* SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_COR */ -/* Description: correctable ecc error */ -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_COR_SHFT 58 -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_COR_MASK 0x0400000000000000 - -/* SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_UNC */ -/* Description: uncorrectable ecc error */ -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_UNC_SHFT 59 -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_UNC_MASK 0x0800000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YPIORD_YDIR_ECC" */ -/* y directory ecc */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC 0x0000000100052810 -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_MASK 0x0000000000003fff -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCA */ -/* Description: group 1 ecc */ -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCA_SHFT 0 -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCA_MASK 0x000000000000007f - -/* SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCB */ -/* Description: group 2 ecc */ -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCB_SHFT 7 -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCB_MASK 0x0000000000003f80 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XCERR1" */ -/* correctable dir ecc group 1 error register */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_XCERR1 0x0000000100053000 -#define SH_MD_DQRP_MMR_XCERR1_MASK 0x0000007fffffffff -#define SH_MD_DQRP_MMR_XCERR1_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_XCERR1_GRP1 */ -/* Description: ecc group 1 bits */ -#define SH_MD_DQRP_MMR_XCERR1_GRP1_SHFT 0 -#define SH_MD_DQRP_MMR_XCERR1_GRP1_MASK 0x0000000fffffffff - -/* SH_MD_DQRP_MMR_XCERR1_VAL */ -/* Description: correctable ecc error in group 1 bits */ -#define SH_MD_DQRP_MMR_XCERR1_VAL_SHFT 36 -#define SH_MD_DQRP_MMR_XCERR1_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQRP_MMR_XCERR1_MORE */ -/* Description: more than one correctable ecc error in group 1 */ -#define SH_MD_DQRP_MMR_XCERR1_MORE_SHFT 37 -#define SH_MD_DQRP_MMR_XCERR1_MORE_MASK 0x0000002000000000 - -/* SH_MD_DQRP_MMR_XCERR1_ARM */ -/* Description: writing 1 arms uncorrectable ecc error capture */ -#define SH_MD_DQRP_MMR_XCERR1_ARM_SHFT 38 -#define SH_MD_DQRP_MMR_XCERR1_ARM_MASK 0x0000004000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XCERR2" */ -/* correctable dir ecc group 2 error register */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_XCERR2 0x0000000100053010 -#define SH_MD_DQRP_MMR_XCERR2_MASK 0x0000003fffffffff -#define SH_MD_DQRP_MMR_XCERR2_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_XCERR2_GRP2 */ -/* Description: ecc group 2 bits */ -#define SH_MD_DQRP_MMR_XCERR2_GRP2_SHFT 0 -#define SH_MD_DQRP_MMR_XCERR2_GRP2_MASK 0x0000000fffffffff - -/* SH_MD_DQRP_MMR_XCERR2_VAL */ -/* Description: correctable ecc error in group 2 bits */ -#define SH_MD_DQRP_MMR_XCERR2_VAL_SHFT 36 -#define SH_MD_DQRP_MMR_XCERR2_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQRP_MMR_XCERR2_MORE */ -/* Description: more than one correctable ecc error in group 2 */ -#define SH_MD_DQRP_MMR_XCERR2_MORE_SHFT 37 -#define SH_MD_DQRP_MMR_XCERR2_MORE_MASK 0x0000002000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XUERR1" */ -/* uncorrectable dir ecc group 1 error register */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_XUERR1 0x0000000100053020 -#define SH_MD_DQRP_MMR_XUERR1_MASK 0x0000007fffffffff -#define SH_MD_DQRP_MMR_XUERR1_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_XUERR1_GRP1 */ -/* Description: ecc group 1 bits */ -#define SH_MD_DQRP_MMR_XUERR1_GRP1_SHFT 0 -#define SH_MD_DQRP_MMR_XUERR1_GRP1_MASK 0x0000000fffffffff - -/* SH_MD_DQRP_MMR_XUERR1_VAL */ -/* Description: uncorrectable ecc error in group 1 bits */ -#define SH_MD_DQRP_MMR_XUERR1_VAL_SHFT 36 -#define SH_MD_DQRP_MMR_XUERR1_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQRP_MMR_XUERR1_MORE */ -/* Description: more than one uncorrectable ecc error in group 1 */ -#define SH_MD_DQRP_MMR_XUERR1_MORE_SHFT 37 -#define SH_MD_DQRP_MMR_XUERR1_MORE_MASK 0x0000002000000000 - -/* SH_MD_DQRP_MMR_XUERR1_ARM */ -/* Description: writing 1 arms uncorrectable ecc error capture */ -#define SH_MD_DQRP_MMR_XUERR1_ARM_SHFT 38 -#define SH_MD_DQRP_MMR_XUERR1_ARM_MASK 0x0000004000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XUERR2" */ -/* uncorrectable dir ecc group 2 error register */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_XUERR2 0x0000000100053030 -#define SH_MD_DQRP_MMR_XUERR2_MASK 0x0000003fffffffff -#define SH_MD_DQRP_MMR_XUERR2_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_XUERR2_GRP2 */ -/* Description: ecc group 2 bits */ -#define SH_MD_DQRP_MMR_XUERR2_GRP2_SHFT 0 -#define SH_MD_DQRP_MMR_XUERR2_GRP2_MASK 0x0000000fffffffff - -/* SH_MD_DQRP_MMR_XUERR2_VAL */ -/* Description: uncorrectable ecc error in group 2 bits */ -#define SH_MD_DQRP_MMR_XUERR2_VAL_SHFT 36 -#define SH_MD_DQRP_MMR_XUERR2_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQRP_MMR_XUERR2_MORE */ -/* Description: more than one uncorrectable ecc error in group 2 */ -#define SH_MD_DQRP_MMR_XUERR2_MORE_SHFT 37 -#define SH_MD_DQRP_MMR_XUERR2_MORE_MASK 0x0000002000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XPERR" */ -/* protocol error register */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_XPERR 0x0000000100053040 -#define SH_MD_DQRP_MMR_XPERR_MASK 0x7fffffffffffffff -#define SH_MD_DQRP_MMR_XPERR_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_XPERR_DIR */ -/* Description: directory entry */ -#define SH_MD_DQRP_MMR_XPERR_DIR_SHFT 0 -#define SH_MD_DQRP_MMR_XPERR_DIR_MASK 0x0000000003ffffff - -/* SH_MD_DQRP_MMR_XPERR_CMD */ -/* Description: incoming command */ -#define SH_MD_DQRP_MMR_XPERR_CMD_SHFT 26 -#define SH_MD_DQRP_MMR_XPERR_CMD_MASK 0x00000003fc000000 - -/* SH_MD_DQRP_MMR_XPERR_SRC */ -/* Description: source node of dir operation */ -#define SH_MD_DQRP_MMR_XPERR_SRC_SHFT 34 -#define SH_MD_DQRP_MMR_XPERR_SRC_MASK 0x0000fffc00000000 - -/* SH_MD_DQRP_MMR_XPERR_PRIGE */ -/* Description: priority was greater-equal */ -#define SH_MD_DQRP_MMR_XPERR_PRIGE_SHFT 48 -#define SH_MD_DQRP_MMR_XPERR_PRIGE_MASK 0x0001000000000000 - -/* SH_MD_DQRP_MMR_XPERR_PRIV */ -/* Description: access privilege bit */ -#define SH_MD_DQRP_MMR_XPERR_PRIV_SHFT 49 -#define SH_MD_DQRP_MMR_XPERR_PRIV_MASK 0x0002000000000000 - -/* SH_MD_DQRP_MMR_XPERR_COR */ -/* Description: correctable ecc error */ -#define SH_MD_DQRP_MMR_XPERR_COR_SHFT 50 -#define SH_MD_DQRP_MMR_XPERR_COR_MASK 0x0004000000000000 - -/* SH_MD_DQRP_MMR_XPERR_UNC */ -/* Description: uncorrectable ecc error */ -#define SH_MD_DQRP_MMR_XPERR_UNC_SHFT 51 -#define SH_MD_DQRP_MMR_XPERR_UNC_MASK 0x0008000000000000 - -/* SH_MD_DQRP_MMR_XPERR_MYBIT */ -/* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */ -#define SH_MD_DQRP_MMR_XPERR_MYBIT_SHFT 52 -#define SH_MD_DQRP_MMR_XPERR_MYBIT_MASK 0x0ff0000000000000 - -/* SH_MD_DQRP_MMR_XPERR_VAL */ -/* Description: protocol error info valid */ -#define SH_MD_DQRP_MMR_XPERR_VAL_SHFT 60 -#define SH_MD_DQRP_MMR_XPERR_VAL_MASK 0x1000000000000000 - -/* SH_MD_DQRP_MMR_XPERR_MORE */ -/* Description: more than one protocol error */ -#define SH_MD_DQRP_MMR_XPERR_MORE_SHFT 61 -#define SH_MD_DQRP_MMR_XPERR_MORE_MASK 0x2000000000000000 - -/* SH_MD_DQRP_MMR_XPERR_ARM */ -/* Description: writing 1 arms error capture */ -#define SH_MD_DQRP_MMR_XPERR_ARM_SHFT 62 -#define SH_MD_DQRP_MMR_XPERR_ARM_MASK 0x4000000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YCERR1" */ -/* correctable dir ecc group 1 error register */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_YCERR1 0x0000000100053800 -#define SH_MD_DQRP_MMR_YCERR1_MASK 0x0000007fffffffff -#define SH_MD_DQRP_MMR_YCERR1_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_YCERR1_GRP1 */ -/* Description: ecc group 1 bits */ -#define SH_MD_DQRP_MMR_YCERR1_GRP1_SHFT 0 -#define SH_MD_DQRP_MMR_YCERR1_GRP1_MASK 0x0000000fffffffff - -/* SH_MD_DQRP_MMR_YCERR1_VAL */ -/* Description: correctable ecc error in group 1 bits */ -#define SH_MD_DQRP_MMR_YCERR1_VAL_SHFT 36 -#define SH_MD_DQRP_MMR_YCERR1_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQRP_MMR_YCERR1_MORE */ -/* Description: more than one correctable ecc error in group 1 */ -#define SH_MD_DQRP_MMR_YCERR1_MORE_SHFT 37 -#define SH_MD_DQRP_MMR_YCERR1_MORE_MASK 0x0000002000000000 - -/* SH_MD_DQRP_MMR_YCERR1_ARM */ -/* Description: writing 1 arms uncorrectable ecc error capture */ -#define SH_MD_DQRP_MMR_YCERR1_ARM_SHFT 38 -#define SH_MD_DQRP_MMR_YCERR1_ARM_MASK 0x0000004000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YCERR2" */ -/* correctable dir ecc group 2 error register */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_YCERR2 0x0000000100053810 -#define SH_MD_DQRP_MMR_YCERR2_MASK 0x0000003fffffffff -#define SH_MD_DQRP_MMR_YCERR2_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_YCERR2_GRP2 */ -/* Description: ecc group 2 bits */ -#define SH_MD_DQRP_MMR_YCERR2_GRP2_SHFT 0 -#define SH_MD_DQRP_MMR_YCERR2_GRP2_MASK 0x0000000fffffffff - -/* SH_MD_DQRP_MMR_YCERR2_VAL */ -/* Description: correctable ecc error in group 2 bits */ -#define SH_MD_DQRP_MMR_YCERR2_VAL_SHFT 36 -#define SH_MD_DQRP_MMR_YCERR2_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQRP_MMR_YCERR2_MORE */ -/* Description: more than one correctable ecc error in group 2 */ -#define SH_MD_DQRP_MMR_YCERR2_MORE_SHFT 37 -#define SH_MD_DQRP_MMR_YCERR2_MORE_MASK 0x0000002000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YUERR1" */ -/* uncorrectable dir ecc group 1 error register */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_YUERR1 0x0000000100053820 -#define SH_MD_DQRP_MMR_YUERR1_MASK 0x0000007fffffffff -#define SH_MD_DQRP_MMR_YUERR1_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_YUERR1_GRP1 */ -/* Description: ecc group 1 bits */ -#define SH_MD_DQRP_MMR_YUERR1_GRP1_SHFT 0 -#define SH_MD_DQRP_MMR_YUERR1_GRP1_MASK 0x0000000fffffffff - -/* SH_MD_DQRP_MMR_YUERR1_VAL */ -/* Description: uncorrectable ecc error in group 1 bits */ -#define SH_MD_DQRP_MMR_YUERR1_VAL_SHFT 36 -#define SH_MD_DQRP_MMR_YUERR1_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQRP_MMR_YUERR1_MORE */ -/* Description: more than one uncorrectable ecc error in group 1 */ -#define SH_MD_DQRP_MMR_YUERR1_MORE_SHFT 37 -#define SH_MD_DQRP_MMR_YUERR1_MORE_MASK 0x0000002000000000 - -/* SH_MD_DQRP_MMR_YUERR1_ARM */ -/* Description: writing 1 arms uncorrectable ecc error capture */ -#define SH_MD_DQRP_MMR_YUERR1_ARM_SHFT 38 -#define SH_MD_DQRP_MMR_YUERR1_ARM_MASK 0x0000004000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YUERR2" */ -/* uncorrectable dir ecc group 2 error register */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_YUERR2 0x0000000100053830 -#define SH_MD_DQRP_MMR_YUERR2_MASK 0x0000003fffffffff -#define SH_MD_DQRP_MMR_YUERR2_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_YUERR2_GRP2 */ -/* Description: ecc group 2 bits */ -#define SH_MD_DQRP_MMR_YUERR2_GRP2_SHFT 0 -#define SH_MD_DQRP_MMR_YUERR2_GRP2_MASK 0x0000000fffffffff - -/* SH_MD_DQRP_MMR_YUERR2_VAL */ -/* Description: uncorrectable ecc error in group 2 bits */ -#define SH_MD_DQRP_MMR_YUERR2_VAL_SHFT 36 -#define SH_MD_DQRP_MMR_YUERR2_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQRP_MMR_YUERR2_MORE */ -/* Description: more than one uncorrectable ecc error in group 2 */ -#define SH_MD_DQRP_MMR_YUERR2_MORE_SHFT 37 -#define SH_MD_DQRP_MMR_YUERR2_MORE_MASK 0x0000002000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YPERR" */ -/* protocol error register */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_YPERR 0x0000000100053840 -#define SH_MD_DQRP_MMR_YPERR_MASK 0x7fffffffffffffff -#define SH_MD_DQRP_MMR_YPERR_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_YPERR_DIR */ -/* Description: directory entry */ -#define SH_MD_DQRP_MMR_YPERR_DIR_SHFT 0 -#define SH_MD_DQRP_MMR_YPERR_DIR_MASK 0x0000000003ffffff - -/* SH_MD_DQRP_MMR_YPERR_CMD */ -/* Description: incoming command */ -#define SH_MD_DQRP_MMR_YPERR_CMD_SHFT 26 -#define SH_MD_DQRP_MMR_YPERR_CMD_MASK 0x00000003fc000000 - -/* SH_MD_DQRP_MMR_YPERR_SRC */ -/* Description: source node of dir operation */ -#define SH_MD_DQRP_MMR_YPERR_SRC_SHFT 34 -#define SH_MD_DQRP_MMR_YPERR_SRC_MASK 0x0000fffc00000000 - -/* SH_MD_DQRP_MMR_YPERR_PRIGE */ -/* Description: priority was greater-equal */ -#define SH_MD_DQRP_MMR_YPERR_PRIGE_SHFT 48 -#define SH_MD_DQRP_MMR_YPERR_PRIGE_MASK 0x0001000000000000 - -/* SH_MD_DQRP_MMR_YPERR_PRIV */ -/* Description: access privilege bit */ -#define SH_MD_DQRP_MMR_YPERR_PRIV_SHFT 49 -#define SH_MD_DQRP_MMR_YPERR_PRIV_MASK 0x0002000000000000 - -/* SH_MD_DQRP_MMR_YPERR_COR */ -/* Description: correctable ecc error */ -#define SH_MD_DQRP_MMR_YPERR_COR_SHFT 50 -#define SH_MD_DQRP_MMR_YPERR_COR_MASK 0x0004000000000000 - -/* SH_MD_DQRP_MMR_YPERR_UNC */ -/* Description: uncorrectable ecc error */ -#define SH_MD_DQRP_MMR_YPERR_UNC_SHFT 51 -#define SH_MD_DQRP_MMR_YPERR_UNC_MASK 0x0008000000000000 - -/* SH_MD_DQRP_MMR_YPERR_MYBIT */ -/* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */ -#define SH_MD_DQRP_MMR_YPERR_MYBIT_SHFT 52 -#define SH_MD_DQRP_MMR_YPERR_MYBIT_MASK 0x0ff0000000000000 - -/* SH_MD_DQRP_MMR_YPERR_VAL */ -/* Description: protocol error info valid */ -#define SH_MD_DQRP_MMR_YPERR_VAL_SHFT 60 -#define SH_MD_DQRP_MMR_YPERR_VAL_MASK 0x1000000000000000 - -/* SH_MD_DQRP_MMR_YPERR_MORE */ -/* Description: more than one protocol error */ -#define SH_MD_DQRP_MMR_YPERR_MORE_SHFT 61 -#define SH_MD_DQRP_MMR_YPERR_MORE_MASK 0x2000000000000000 - -/* SH_MD_DQRP_MMR_YPERR_ARM */ -/* Description: writing 1 arms error capture */ -#define SH_MD_DQRP_MMR_YPERR_ARM_SHFT 62 -#define SH_MD_DQRP_MMR_YPERR_ARM_MASK 0x4000000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_CMDTRIG" */ -/* cmd triggers */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_CMDTRIG 0x0000000100054000 -#define SH_MD_DQRP_MMR_DIR_CMDTRIG_MASK 0x00000000ffffffff -#define SH_MD_DQRP_MMR_DIR_CMDTRIG_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD0 */ -/* Description: command trigger 0 */ -#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD0_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD0_MASK 0x00000000000000ff - -/* SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD1 */ -/* Description: command trigger 1 */ -#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD1_SHFT 8 -#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD1_MASK 0x000000000000ff00 - -/* SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD2 */ -/* Description: command trigger 2 */ -#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD2_SHFT 16 -#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD2_MASK 0x0000000000ff0000 - -/* SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD3 */ -/* Description: command trigger 3 */ -#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD3_SHFT 24 -#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD3_MASK 0x00000000ff000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_TBLTRIG" */ -/* dir table trigger */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_TBLTRIG 0x0000000100054010 -#define SH_MD_DQRP_MMR_DIR_TBLTRIG_MASK 0x000003ffffffffff -#define SH_MD_DQRP_MMR_DIR_TBLTRIG_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_TBLTRIG_SRC */ -/* Description: source of request */ -#define SH_MD_DQRP_MMR_DIR_TBLTRIG_SRC_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_TBLTRIG_SRC_MASK 0x0000000000003fff - -/* SH_MD_DQRP_MMR_DIR_TBLTRIG_CMD */ -/* Description: incoming request */ -#define SH_MD_DQRP_MMR_DIR_TBLTRIG_CMD_SHFT 14 -#define SH_MD_DQRP_MMR_DIR_TBLTRIG_CMD_MASK 0x00000000003fc000 - -/* SH_MD_DQRP_MMR_DIR_TBLTRIG_ACC */ -/* Description: uncorrectable error, privilege bit */ -#define SH_MD_DQRP_MMR_DIR_TBLTRIG_ACC_SHFT 22 -#define SH_MD_DQRP_MMR_DIR_TBLTRIG_ACC_MASK 0x0000000000c00000 - -/* SH_MD_DQRP_MMR_DIR_TBLTRIG_PRIGE */ -/* Description: priority greater-equal */ -#define SH_MD_DQRP_MMR_DIR_TBLTRIG_PRIGE_SHFT 24 -#define SH_MD_DQRP_MMR_DIR_TBLTRIG_PRIGE_MASK 0x0000000001000000 - -/* SH_MD_DQRP_MMR_DIR_TBLTRIG_DIRST */ -/* Description: shrd,sxro,sub-state */ -#define SH_MD_DQRP_MMR_DIR_TBLTRIG_DIRST_SHFT 25 -#define SH_MD_DQRP_MMR_DIR_TBLTRIG_DIRST_MASK 0x00000003fe000000 - -/* SH_MD_DQRP_MMR_DIR_TBLTRIG_MYBIT */ -/* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */ -#define SH_MD_DQRP_MMR_DIR_TBLTRIG_MYBIT_SHFT 34 -#define SH_MD_DQRP_MMR_DIR_TBLTRIG_MYBIT_MASK 0x000003fc00000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_TBLMASK" */ -/* dir table trigger mask */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_TBLMASK 0x0000000100054020 -#define SH_MD_DQRP_MMR_DIR_TBLMASK_MASK 0x000003ffffffffff -#define SH_MD_DQRP_MMR_DIR_TBLMASK_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_TBLMASK_SRC */ -/* Description: source of request */ -#define SH_MD_DQRP_MMR_DIR_TBLMASK_SRC_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_TBLMASK_SRC_MASK 0x0000000000003fff - -/* SH_MD_DQRP_MMR_DIR_TBLMASK_CMD */ -/* Description: incoming request */ -#define SH_MD_DQRP_MMR_DIR_TBLMASK_CMD_SHFT 14 -#define SH_MD_DQRP_MMR_DIR_TBLMASK_CMD_MASK 0x00000000003fc000 - -/* SH_MD_DQRP_MMR_DIR_TBLMASK_ACC */ -/* Description: uncorrectable error, privilege bit */ -#define SH_MD_DQRP_MMR_DIR_TBLMASK_ACC_SHFT 22 -#define SH_MD_DQRP_MMR_DIR_TBLMASK_ACC_MASK 0x0000000000c00000 - -/* SH_MD_DQRP_MMR_DIR_TBLMASK_PRIGE */ -/* Description: priority greater-equal */ -#define SH_MD_DQRP_MMR_DIR_TBLMASK_PRIGE_SHFT 24 -#define SH_MD_DQRP_MMR_DIR_TBLMASK_PRIGE_MASK 0x0000000001000000 - -/* SH_MD_DQRP_MMR_DIR_TBLMASK_DIRST */ -/* Description: shrd,sxro,sub-state */ -#define SH_MD_DQRP_MMR_DIR_TBLMASK_DIRST_SHFT 25 -#define SH_MD_DQRP_MMR_DIR_TBLMASK_DIRST_MASK 0x00000003fe000000 - -/* SH_MD_DQRP_MMR_DIR_TBLMASK_MYBIT */ -/* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */ -#define SH_MD_DQRP_MMR_DIR_TBLMASK_MYBIT_SHFT 34 -#define SH_MD_DQRP_MMR_DIR_TBLMASK_MYBIT_MASK 0x000003fc00000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XBIST_H" */ -/* rising edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_XBIST_H 0x0000000100058000 -#define SH_MD_DQRP_MMR_XBIST_H_MASK 0x00000700ffffffff -#define SH_MD_DQRP_MMR_XBIST_H_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_XBIST_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRP_MMR_XBIST_H_PAT_SHFT 0 -#define SH_MD_DQRP_MMR_XBIST_H_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQRP_MMR_XBIST_H_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQRP_MMR_XBIST_H_INV_SHFT 40 -#define SH_MD_DQRP_MMR_XBIST_H_INV_MASK 0x0000010000000000 - -/* SH_MD_DQRP_MMR_XBIST_H_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQRP_MMR_XBIST_H_ROT_SHFT 41 -#define SH_MD_DQRP_MMR_XBIST_H_ROT_MASK 0x0000020000000000 - -/* SH_MD_DQRP_MMR_XBIST_H_ARM */ -/* Description: writing 1 arms data miscompare capture */ -#define SH_MD_DQRP_MMR_XBIST_H_ARM_SHFT 42 -#define SH_MD_DQRP_MMR_XBIST_H_ARM_MASK 0x0000040000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XBIST_L" */ -/* falling edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_XBIST_L 0x0000000100058010 -#define SH_MD_DQRP_MMR_XBIST_L_MASK 0x00000300ffffffff -#define SH_MD_DQRP_MMR_XBIST_L_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_XBIST_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRP_MMR_XBIST_L_PAT_SHFT 0 -#define SH_MD_DQRP_MMR_XBIST_L_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQRP_MMR_XBIST_L_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQRP_MMR_XBIST_L_INV_SHFT 40 -#define SH_MD_DQRP_MMR_XBIST_L_INV_MASK 0x0000010000000000 - -/* SH_MD_DQRP_MMR_XBIST_L_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQRP_MMR_XBIST_L_ROT_SHFT 41 -#define SH_MD_DQRP_MMR_XBIST_L_ROT_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XBIST_ERR_H" */ -/* rising edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_XBIST_ERR_H 0x0000000100058020 -#define SH_MD_DQRP_MMR_XBIST_ERR_H_MASK 0x00000300ffffffff -#define SH_MD_DQRP_MMR_XBIST_ERR_H_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_XBIST_ERR_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRP_MMR_XBIST_ERR_H_PAT_SHFT 0 -#define SH_MD_DQRP_MMR_XBIST_ERR_H_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQRP_MMR_XBIST_ERR_H_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQRP_MMR_XBIST_ERR_H_VAL_SHFT 40 -#define SH_MD_DQRP_MMR_XBIST_ERR_H_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQRP_MMR_XBIST_ERR_H_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQRP_MMR_XBIST_ERR_H_MORE_SHFT 41 -#define SH_MD_DQRP_MMR_XBIST_ERR_H_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XBIST_ERR_L" */ -/* falling edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_XBIST_ERR_L 0x0000000100058030 -#define SH_MD_DQRP_MMR_XBIST_ERR_L_MASK 0x00000300ffffffff -#define SH_MD_DQRP_MMR_XBIST_ERR_L_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_XBIST_ERR_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRP_MMR_XBIST_ERR_L_PAT_SHFT 0 -#define SH_MD_DQRP_MMR_XBIST_ERR_L_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQRP_MMR_XBIST_ERR_L_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQRP_MMR_XBIST_ERR_L_VAL_SHFT 40 -#define SH_MD_DQRP_MMR_XBIST_ERR_L_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQRP_MMR_XBIST_ERR_L_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQRP_MMR_XBIST_ERR_L_MORE_SHFT 41 -#define SH_MD_DQRP_MMR_XBIST_ERR_L_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YBIST_H" */ -/* rising edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_YBIST_H 0x0000000100058800 -#define SH_MD_DQRP_MMR_YBIST_H_MASK 0x00000700ffffffff -#define SH_MD_DQRP_MMR_YBIST_H_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_YBIST_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRP_MMR_YBIST_H_PAT_SHFT 0 -#define SH_MD_DQRP_MMR_YBIST_H_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQRP_MMR_YBIST_H_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQRP_MMR_YBIST_H_INV_SHFT 40 -#define SH_MD_DQRP_MMR_YBIST_H_INV_MASK 0x0000010000000000 - -/* SH_MD_DQRP_MMR_YBIST_H_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQRP_MMR_YBIST_H_ROT_SHFT 41 -#define SH_MD_DQRP_MMR_YBIST_H_ROT_MASK 0x0000020000000000 - -/* SH_MD_DQRP_MMR_YBIST_H_ARM */ -/* Description: writing 1 arms data miscompare capture */ -#define SH_MD_DQRP_MMR_YBIST_H_ARM_SHFT 42 -#define SH_MD_DQRP_MMR_YBIST_H_ARM_MASK 0x0000040000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YBIST_L" */ -/* falling edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_YBIST_L 0x0000000100058810 -#define SH_MD_DQRP_MMR_YBIST_L_MASK 0x00000300ffffffff -#define SH_MD_DQRP_MMR_YBIST_L_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_YBIST_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRP_MMR_YBIST_L_PAT_SHFT 0 -#define SH_MD_DQRP_MMR_YBIST_L_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQRP_MMR_YBIST_L_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQRP_MMR_YBIST_L_INV_SHFT 40 -#define SH_MD_DQRP_MMR_YBIST_L_INV_MASK 0x0000010000000000 - -/* SH_MD_DQRP_MMR_YBIST_L_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQRP_MMR_YBIST_L_ROT_SHFT 41 -#define SH_MD_DQRP_MMR_YBIST_L_ROT_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YBIST_ERR_H" */ -/* rising edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_YBIST_ERR_H 0x0000000100058820 -#define SH_MD_DQRP_MMR_YBIST_ERR_H_MASK 0x00000300ffffffff -#define SH_MD_DQRP_MMR_YBIST_ERR_H_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_YBIST_ERR_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRP_MMR_YBIST_ERR_H_PAT_SHFT 0 -#define SH_MD_DQRP_MMR_YBIST_ERR_H_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQRP_MMR_YBIST_ERR_H_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQRP_MMR_YBIST_ERR_H_VAL_SHFT 40 -#define SH_MD_DQRP_MMR_YBIST_ERR_H_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQRP_MMR_YBIST_ERR_H_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQRP_MMR_YBIST_ERR_H_MORE_SHFT 41 -#define SH_MD_DQRP_MMR_YBIST_ERR_H_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YBIST_ERR_L" */ -/* falling edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_YBIST_ERR_L 0x0000000100058830 -#define SH_MD_DQRP_MMR_YBIST_ERR_L_MASK 0x00000300ffffffff -#define SH_MD_DQRP_MMR_YBIST_ERR_L_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_YBIST_ERR_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRP_MMR_YBIST_ERR_L_PAT_SHFT 0 -#define SH_MD_DQRP_MMR_YBIST_ERR_L_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQRP_MMR_YBIST_ERR_L_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQRP_MMR_YBIST_ERR_L_VAL_SHFT 40 -#define SH_MD_DQRP_MMR_YBIST_ERR_L_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQRP_MMR_YBIST_ERR_L_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQRP_MMR_YBIST_ERR_L_MORE_SHFT 41 -#define SH_MD_DQRP_MMR_YBIST_ERR_L_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRS_MMR_XBIST_H" */ -/* rising edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRS_MMR_XBIST_H 0x0000000100068000 -#define SH_MD_DQRS_MMR_XBIST_H_MASK 0x000007ffffffffff -#define SH_MD_DQRS_MMR_XBIST_H_INIT 0x0000000000000000 - -/* SH_MD_DQRS_MMR_XBIST_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRS_MMR_XBIST_H_PAT_SHFT 0 -#define SH_MD_DQRS_MMR_XBIST_H_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQRS_MMR_XBIST_H_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQRS_MMR_XBIST_H_INV_SHFT 40 -#define SH_MD_DQRS_MMR_XBIST_H_INV_MASK 0x0000010000000000 - -/* SH_MD_DQRS_MMR_XBIST_H_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQRS_MMR_XBIST_H_ROT_SHFT 41 -#define SH_MD_DQRS_MMR_XBIST_H_ROT_MASK 0x0000020000000000 - -/* SH_MD_DQRS_MMR_XBIST_H_ARM */ -/* Description: writing 1 arms data miscompare capture */ -#define SH_MD_DQRS_MMR_XBIST_H_ARM_SHFT 42 -#define SH_MD_DQRS_MMR_XBIST_H_ARM_MASK 0x0000040000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRS_MMR_XBIST_L" */ -/* falling edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRS_MMR_XBIST_L 0x0000000100068010 -#define SH_MD_DQRS_MMR_XBIST_L_MASK 0x000003ffffffffff -#define SH_MD_DQRS_MMR_XBIST_L_INIT 0x0000000000000000 - -/* SH_MD_DQRS_MMR_XBIST_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRS_MMR_XBIST_L_PAT_SHFT 0 -#define SH_MD_DQRS_MMR_XBIST_L_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQRS_MMR_XBIST_L_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQRS_MMR_XBIST_L_INV_SHFT 40 -#define SH_MD_DQRS_MMR_XBIST_L_INV_MASK 0x0000010000000000 - -/* SH_MD_DQRS_MMR_XBIST_L_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQRS_MMR_XBIST_L_ROT_SHFT 41 -#define SH_MD_DQRS_MMR_XBIST_L_ROT_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRS_MMR_XBIST_ERR_H" */ -/* rising edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRS_MMR_XBIST_ERR_H 0x0000000100068020 -#define SH_MD_DQRS_MMR_XBIST_ERR_H_MASK 0x000003ffffffffff -#define SH_MD_DQRS_MMR_XBIST_ERR_H_INIT 0x0000000000000000 - -/* SH_MD_DQRS_MMR_XBIST_ERR_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRS_MMR_XBIST_ERR_H_PAT_SHFT 0 -#define SH_MD_DQRS_MMR_XBIST_ERR_H_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQRS_MMR_XBIST_ERR_H_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQRS_MMR_XBIST_ERR_H_VAL_SHFT 40 -#define SH_MD_DQRS_MMR_XBIST_ERR_H_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQRS_MMR_XBIST_ERR_H_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQRS_MMR_XBIST_ERR_H_MORE_SHFT 41 -#define SH_MD_DQRS_MMR_XBIST_ERR_H_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRS_MMR_XBIST_ERR_L" */ -/* falling edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRS_MMR_XBIST_ERR_L 0x0000000100068030 -#define SH_MD_DQRS_MMR_XBIST_ERR_L_MASK 0x000003ffffffffff -#define SH_MD_DQRS_MMR_XBIST_ERR_L_INIT 0x0000000000000000 - -/* SH_MD_DQRS_MMR_XBIST_ERR_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRS_MMR_XBIST_ERR_L_PAT_SHFT 0 -#define SH_MD_DQRS_MMR_XBIST_ERR_L_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQRS_MMR_XBIST_ERR_L_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQRS_MMR_XBIST_ERR_L_VAL_SHFT 40 -#define SH_MD_DQRS_MMR_XBIST_ERR_L_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQRS_MMR_XBIST_ERR_L_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQRS_MMR_XBIST_ERR_L_MORE_SHFT 41 -#define SH_MD_DQRS_MMR_XBIST_ERR_L_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRS_MMR_YBIST_H" */ -/* rising edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRS_MMR_YBIST_H 0x0000000100068800 -#define SH_MD_DQRS_MMR_YBIST_H_MASK 0x000007ffffffffff -#define SH_MD_DQRS_MMR_YBIST_H_INIT 0x0000000000000000 - -/* SH_MD_DQRS_MMR_YBIST_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRS_MMR_YBIST_H_PAT_SHFT 0 -#define SH_MD_DQRS_MMR_YBIST_H_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQRS_MMR_YBIST_H_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQRS_MMR_YBIST_H_INV_SHFT 40 -#define SH_MD_DQRS_MMR_YBIST_H_INV_MASK 0x0000010000000000 - -/* SH_MD_DQRS_MMR_YBIST_H_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQRS_MMR_YBIST_H_ROT_SHFT 41 -#define SH_MD_DQRS_MMR_YBIST_H_ROT_MASK 0x0000020000000000 - -/* SH_MD_DQRS_MMR_YBIST_H_ARM */ -/* Description: writing 1 arms data miscompare capture */ -#define SH_MD_DQRS_MMR_YBIST_H_ARM_SHFT 42 -#define SH_MD_DQRS_MMR_YBIST_H_ARM_MASK 0x0000040000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRS_MMR_YBIST_L" */ -/* falling edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRS_MMR_YBIST_L 0x0000000100068810 -#define SH_MD_DQRS_MMR_YBIST_L_MASK 0x000003ffffffffff -#define SH_MD_DQRS_MMR_YBIST_L_INIT 0x0000000000000000 - -/* SH_MD_DQRS_MMR_YBIST_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRS_MMR_YBIST_L_PAT_SHFT 0 -#define SH_MD_DQRS_MMR_YBIST_L_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQRS_MMR_YBIST_L_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQRS_MMR_YBIST_L_INV_SHFT 40 -#define SH_MD_DQRS_MMR_YBIST_L_INV_MASK 0x0000010000000000 - -/* SH_MD_DQRS_MMR_YBIST_L_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQRS_MMR_YBIST_L_ROT_SHFT 41 -#define SH_MD_DQRS_MMR_YBIST_L_ROT_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRS_MMR_YBIST_ERR_H" */ -/* rising edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRS_MMR_YBIST_ERR_H 0x0000000100068820 -#define SH_MD_DQRS_MMR_YBIST_ERR_H_MASK 0x000003ffffffffff -#define SH_MD_DQRS_MMR_YBIST_ERR_H_INIT 0x0000000000000000 - -/* SH_MD_DQRS_MMR_YBIST_ERR_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRS_MMR_YBIST_ERR_H_PAT_SHFT 0 -#define SH_MD_DQRS_MMR_YBIST_ERR_H_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQRS_MMR_YBIST_ERR_H_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQRS_MMR_YBIST_ERR_H_VAL_SHFT 40 -#define SH_MD_DQRS_MMR_YBIST_ERR_H_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQRS_MMR_YBIST_ERR_H_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQRS_MMR_YBIST_ERR_H_MORE_SHFT 41 -#define SH_MD_DQRS_MMR_YBIST_ERR_H_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRS_MMR_YBIST_ERR_L" */ -/* falling edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRS_MMR_YBIST_ERR_L 0x0000000100068830 -#define SH_MD_DQRS_MMR_YBIST_ERR_L_MASK 0x000003ffffffffff -#define SH_MD_DQRS_MMR_YBIST_ERR_L_INIT 0x0000000000000000 - -/* SH_MD_DQRS_MMR_YBIST_ERR_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRS_MMR_YBIST_ERR_L_PAT_SHFT 0 -#define SH_MD_DQRS_MMR_YBIST_ERR_L_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQRS_MMR_YBIST_ERR_L_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQRS_MMR_YBIST_ERR_L_VAL_SHFT 40 -#define SH_MD_DQRS_MMR_YBIST_ERR_L_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQRS_MMR_YBIST_ERR_L_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQRS_MMR_YBIST_ERR_L_MORE_SHFT 41 -#define SH_MD_DQRS_MMR_YBIST_ERR_L_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRS_MMR_JNR_DEBUG" */ -/* joiner/fct debug configuration */ -/* ==================================================================== */ - -#define SH_MD_DQRS_MMR_JNR_DEBUG 0x0000000100069000 -#define SH_MD_DQRS_MMR_JNR_DEBUG_MASK 0x0000000000000003 -#define SH_MD_DQRS_MMR_JNR_DEBUG_INIT 0x0000000000000000 - -/* SH_MD_DQRS_MMR_JNR_DEBUG_PX */ -/* Description: select 0=pi 1=xn side */ -#define SH_MD_DQRS_MMR_JNR_DEBUG_PX_SHFT 0 -#define SH_MD_DQRS_MMR_JNR_DEBUG_PX_MASK 0x0000000000000001 - -/* SH_MD_DQRS_MMR_JNR_DEBUG_RW */ -/* Description: select 0=read 1=write side */ -#define SH_MD_DQRS_MMR_JNR_DEBUG_RW_SHFT 1 -#define SH_MD_DQRS_MMR_JNR_DEBUG_RW_MASK 0x0000000000000002 - -/* ==================================================================== */ -/* Register "SH_MD_DQRS_MMR_YAMOPW_ERR" */ -/* amo/partial rmw ecc error register */ -/* ==================================================================== */ - -#define SH_MD_DQRS_MMR_YAMOPW_ERR 0x000000010006a000 -#define SH_MD_DQRS_MMR_YAMOPW_ERR_MASK 0x0000000103ff03ff -#define SH_MD_DQRS_MMR_YAMOPW_ERR_INIT 0x0000000000000000 - -/* SH_MD_DQRS_MMR_YAMOPW_ERR_SSYN */ -/* Description: store data syndrome */ -#define SH_MD_DQRS_MMR_YAMOPW_ERR_SSYN_SHFT 0 -#define SH_MD_DQRS_MMR_YAMOPW_ERR_SSYN_MASK 0x00000000000000ff - -/* SH_MD_DQRS_MMR_YAMOPW_ERR_SCOR */ -/* Description: correctable ecc errror on store data */ -#define SH_MD_DQRS_MMR_YAMOPW_ERR_SCOR_SHFT 8 -#define SH_MD_DQRS_MMR_YAMOPW_ERR_SCOR_MASK 0x0000000000000100 - -/* SH_MD_DQRS_MMR_YAMOPW_ERR_SUNC */ -/* Description: uncorrectable ecc errror on store data */ -#define SH_MD_DQRS_MMR_YAMOPW_ERR_SUNC_SHFT 9 -#define SH_MD_DQRS_MMR_YAMOPW_ERR_SUNC_MASK 0x0000000000000200 - -/* SH_MD_DQRS_MMR_YAMOPW_ERR_RSYN */ -/* Description: memory read data syndrome */ -#define SH_MD_DQRS_MMR_YAMOPW_ERR_RSYN_SHFT 16 -#define SH_MD_DQRS_MMR_YAMOPW_ERR_RSYN_MASK 0x0000000000ff0000 - -/* SH_MD_DQRS_MMR_YAMOPW_ERR_RCOR */ -/* Description: correctable ecc errror on read data */ -#define SH_MD_DQRS_MMR_YAMOPW_ERR_RCOR_SHFT 24 -#define SH_MD_DQRS_MMR_YAMOPW_ERR_RCOR_MASK 0x0000000001000000 - -/* SH_MD_DQRS_MMR_YAMOPW_ERR_RUNC */ -/* Description: uncorrectable ecc errror on read data */ -#define SH_MD_DQRS_MMR_YAMOPW_ERR_RUNC_SHFT 25 -#define SH_MD_DQRS_MMR_YAMOPW_ERR_RUNC_MASK 0x0000000002000000 - -/* SH_MD_DQRS_MMR_YAMOPW_ERR_ARM */ -/* Description: writing 1 arms ecc error capture */ -#define SH_MD_DQRS_MMR_YAMOPW_ERR_ARM_SHFT 32 -#define SH_MD_DQRS_MMR_YAMOPW_ERR_ARM_MASK 0x0000000100000000 - - -#endif /* _ASM_IA64_SN_SN2_SHUB_MMR_H */ diff --git a/include/asm-ia64/sn/sn2/shub_mmr_t.h b/include/asm-ia64/sn/sn2/shub_mmr_t.h deleted file mode 100644 index 5e74a7e1c8b5..000000000000 --- a/include/asm-ia64/sn/sn2/shub_mmr_t.h +++ /dev/null @@ -1,14829 +0,0 @@ -/* - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (c) 2001-2003 Silicon Graphics, Inc. All rights reserved. - */ - -#ifndef _ASM_IA64_SN_SN2_SHUB_MMR_T_H -#define _ASM_IA64_SN_SN2_SHUB_MMR_T_H - -#include <asm/sn/arch.h> - -/* ==================================================================== */ -/* Register "SH_FSB_BINIT_CONTROL" */ -/* FSB BINIT# Control */ -/* ==================================================================== */ - -typedef union sh_fsb_binit_control_u { - mmr_t sh_fsb_binit_control_regval; - struct { - mmr_t binit : 1; - mmr_t reserved_0 : 63; - } sh_fsb_binit_control_s; -} sh_fsb_binit_control_u_t; - -/* ==================================================================== */ -/* Register "SH_FSB_RESET_CONTROL" */ -/* FSB Reset Control */ -/* ==================================================================== */ - -typedef union sh_fsb_reset_control_u { - mmr_t sh_fsb_reset_control_regval; - struct { - mmr_t reset : 1; - mmr_t reserved_0 : 63; - } sh_fsb_reset_control_s; -} sh_fsb_reset_control_u_t; - -/* ==================================================================== */ -/* Register "SH_FSB_SYSTEM_AGENT_CONFIG" */ -/* FSB System Agent Configuration */ -/* ==================================================================== */ - -typedef union sh_fsb_system_agent_config_u { - mmr_t sh_fsb_system_agent_config_regval; - struct { - mmr_t rcnt_scnt_en : 1; - mmr_t reserved_0 : 2; - mmr_t berr_assert_en : 1; - mmr_t berr_sampling_en : 1; - mmr_t binit_assert_en : 1; - mmr_t bnr_throttling_en : 1; - mmr_t short_hang_en : 1; - mmr_t inta_rsp_data : 8; - mmr_t io_trans_rsp : 1; - mmr_t xtpr_trans_rsp : 1; - mmr_t inta_trans_rsp : 1; - mmr_t reserved_1 : 4; - mmr_t tdot : 1; - mmr_t serialize_fsb_en : 1; - mmr_t reserved_2 : 7; - mmr_t binit_event_enables : 14; - mmr_t reserved_3 : 18; - } sh_fsb_system_agent_config_s; -} sh_fsb_system_agent_config_u_t; - -/* ==================================================================== */ -/* Register "SH_FSB_VGA_REMAP" */ -/* FSB VGA Address Space Remap */ -/* ==================================================================== */ - -typedef union sh_fsb_vga_remap_u { - mmr_t sh_fsb_vga_remap_regval; - struct { - mmr_t reserved_0 : 17; - mmr_t offset : 19; - mmr_t asid : 2; - mmr_t nid : 11; - mmr_t reserved_1 : 13; - mmr_t vga_remapping_enabled : 1; - mmr_t reserved_2 : 1; - } sh_fsb_vga_remap_s; -} sh_fsb_vga_remap_u_t; - -/* ==================================================================== */ -/* Register "SH_FSB_RESET_STATUS" */ -/* FSB Reset Status */ -/* ==================================================================== */ - -typedef union sh_fsb_reset_status_u { - mmr_t sh_fsb_reset_status_regval; - struct { - mmr_t reset_in_progress : 1; - mmr_t reserved_0 : 63; - } sh_fsb_reset_status_s; -} sh_fsb_reset_status_u_t; - -/* ==================================================================== */ -/* Register "SH_FSB_SYMMETRIC_AGENT_STATUS" */ -/* FSB Symmetric Agent Status */ -/* ==================================================================== */ - -typedef union sh_fsb_symmetric_agent_status_u { - mmr_t sh_fsb_symmetric_agent_status_regval; - struct { - mmr_t cpu_0_active : 1; - mmr_t cpu_1_active : 1; - mmr_t cpus_ready : 1; - mmr_t reserved_0 : 61; - } sh_fsb_symmetric_agent_status_s; -} sh_fsb_symmetric_agent_status_u_t; - -/* ==================================================================== */ -/* Register "SH_GFX_CREDIT_COUNT_0" */ -/* Graphics-write Credit Count for CPU 0 */ -/* ==================================================================== */ - -typedef union sh_gfx_credit_count_0_u { - mmr_t sh_gfx_credit_count_0_regval; - struct { - mmr_t count : 20; - mmr_t reserved_0 : 43; - mmr_t reset_gfx_state : 1; - } sh_gfx_credit_count_0_s; -} sh_gfx_credit_count_0_u_t; - -/* ==================================================================== */ -/* Register "SH_GFX_CREDIT_COUNT_1" */ -/* Graphics-write Credit Count for CPU 1 */ -/* ==================================================================== */ - -typedef union sh_gfx_credit_count_1_u { - mmr_t sh_gfx_credit_count_1_regval; - struct { - mmr_t count : 20; - mmr_t reserved_0 : 43; - mmr_t reset_gfx_state : 1; - } sh_gfx_credit_count_1_s; -} sh_gfx_credit_count_1_u_t; - -/* ==================================================================== */ -/* Register "SH_GFX_MODE_CNTRL_0" */ -/* Graphics credit mode amd message ordering for CPU 0 */ -/* ==================================================================== */ - -typedef union sh_gfx_mode_cntrl_0_u { - mmr_t sh_gfx_mode_cntrl_0_regval; - struct { - mmr_t dword_credits : 1; - mmr_t mixed_mode_credits : 1; - mmr_t relaxed_ordering : 1; - mmr_t reserved_0 : 61; - } sh_gfx_mode_cntrl_0_s; -} sh_gfx_mode_cntrl_0_u_t; - -/* ==================================================================== */ -/* Register "SH_GFX_MODE_CNTRL_1" */ -/* Graphics credit mode amd message ordering for CPU 1 */ -/* ==================================================================== */ - -typedef union sh_gfx_mode_cntrl_1_u { - mmr_t sh_gfx_mode_cntrl_1_regval; - struct { - mmr_t dword_credits : 1; - mmr_t mixed_mode_credits : 1; - mmr_t relaxed_ordering : 1; - mmr_t reserved_0 : 61; - } sh_gfx_mode_cntrl_1_s; -} sh_gfx_mode_cntrl_1_u_t; - -/* ==================================================================== */ -/* Register "SH_GFX_SKID_CREDIT_COUNT_0" */ -/* Graphics-write Skid Credit Count for CPU 0 */ -/* ==================================================================== */ - -typedef union sh_gfx_skid_credit_count_0_u { - mmr_t sh_gfx_skid_credit_count_0_regval; - struct { - mmr_t skid : 20; - mmr_t reserved_0 : 44; - } sh_gfx_skid_credit_count_0_s; -} sh_gfx_skid_credit_count_0_u_t; - -/* ==================================================================== */ -/* Register "SH_GFX_SKID_CREDIT_COUNT_1" */ -/* Graphics-write Skid Credit Count for CPU 1 */ -/* ==================================================================== */ - -typedef union sh_gfx_skid_credit_count_1_u { - mmr_t sh_gfx_skid_credit_count_1_regval; - struct { - mmr_t skid : 20; - mmr_t reserved_0 : 44; - } sh_gfx_skid_credit_count_1_s; -} sh_gfx_skid_credit_count_1_u_t; - -/* ==================================================================== */ -/* Register "SH_GFX_STALL_LIMIT_0" */ -/* Graphics-write Stall Limit for CPU 0 */ -/* ==================================================================== */ - -typedef union sh_gfx_stall_limit_0_u { - mmr_t sh_gfx_stall_limit_0_regval; - struct { - mmr_t limit : 26; - mmr_t reserved_0 : 38; - } sh_gfx_stall_limit_0_s; -} sh_gfx_stall_limit_0_u_t; - -/* ==================================================================== */ -/* Register "SH_GFX_STALL_LIMIT_1" */ -/* Graphics-write Stall Limit for CPU 1 */ -/* ==================================================================== */ - -typedef union sh_gfx_stall_limit_1_u { - mmr_t sh_gfx_stall_limit_1_regval; - struct { - mmr_t limit : 26; - mmr_t reserved_0 : 38; - } sh_gfx_stall_limit_1_s; -} sh_gfx_stall_limit_1_u_t; - -/* ==================================================================== */ -/* Register "SH_GFX_STALL_TIMER_0" */ -/* Graphics-write Stall Timer for CPU 0 */ -/* ==================================================================== */ - -typedef union sh_gfx_stall_timer_0_u { - mmr_t sh_gfx_stall_timer_0_regval; - struct { - mmr_t timer_value : 26; - mmr_t reserved_0 : 38; - } sh_gfx_stall_timer_0_s; -} sh_gfx_stall_timer_0_u_t; - -/* ==================================================================== */ -/* Register "SH_GFX_STALL_TIMER_1" */ -/* Graphics-write Stall Timer for CPU 1 */ -/* ==================================================================== */ - -typedef union sh_gfx_stall_timer_1_u { - mmr_t sh_gfx_stall_timer_1_regval; - struct { - mmr_t timer_value : 26; - mmr_t reserved_0 : 38; - } sh_gfx_stall_timer_1_s; -} sh_gfx_stall_timer_1_u_t; - -/* ==================================================================== */ -/* Register "SH_GFX_WINDOW_0" */ -/* Graphics-write Window for CPU 0 */ -/* ==================================================================== */ - -typedef union sh_gfx_window_0_u { - mmr_t sh_gfx_window_0_regval; - struct { - mmr_t reserved_0 : 24; - mmr_t base_addr : 12; - mmr_t reserved_1 : 27; - mmr_t gfx_window_en : 1; - } sh_gfx_window_0_s; -} sh_gfx_window_0_u_t; - -/* ==================================================================== */ -/* Register "SH_GFX_WINDOW_1" */ -/* Graphics-write Window for CPU 1 */ -/* ==================================================================== */ - -typedef union sh_gfx_window_1_u { - mmr_t sh_gfx_window_1_regval; - struct { - mmr_t reserved_0 : 24; - mmr_t base_addr : 12; - mmr_t reserved_1 : 27; - mmr_t gfx_window_en : 1; - } sh_gfx_window_1_s; -} sh_gfx_window_1_u_t; - -/* ==================================================================== */ -/* Register "SH_GFX_INTERRUPT_TIMER_LIMIT_0" */ -/* Graphics-write Interrupt Limit for CPU 0 */ -/* ==================================================================== */ - -typedef union sh_gfx_interrupt_timer_limit_0_u { - mmr_t sh_gfx_interrupt_timer_limit_0_regval; - struct { - mmr_t interrupt_timer_limit : 8; - mmr_t reserved_0 : 56; - } sh_gfx_interrupt_timer_limit_0_s; -} sh_gfx_interrupt_timer_limit_0_u_t; - -/* ==================================================================== */ -/* Register "SH_GFX_INTERRUPT_TIMER_LIMIT_1" */ -/* Graphics-write Interrupt Limit for CPU 1 */ -/* ==================================================================== */ - -typedef union sh_gfx_interrupt_timer_limit_1_u { - mmr_t sh_gfx_interrupt_timer_limit_1_regval; - struct { - mmr_t interrupt_timer_limit : 8; - mmr_t reserved_0 : 56; - } sh_gfx_interrupt_timer_limit_1_s; -} sh_gfx_interrupt_timer_limit_1_u_t; - -/* ==================================================================== */ -/* Register "SH_GFX_WRITE_STATUS_0" */ -/* Graphics Write Status for CPU 0 */ -/* ==================================================================== */ - -typedef union sh_gfx_write_status_0_u { - mmr_t sh_gfx_write_status_0_regval; - struct { - mmr_t busy : 1; - mmr_t reserved_0 : 62; - mmr_t re_enable_gfx_stall : 1; - } sh_gfx_write_status_0_s; -} sh_gfx_write_status_0_u_t; - -/* ==================================================================== */ -/* Register "SH_GFX_WRITE_STATUS_1" */ -/* Graphics Write Status for CPU 1 */ -/* ==================================================================== */ - -typedef union sh_gfx_write_status_1_u { - mmr_t sh_gfx_write_status_1_regval; - struct { - mmr_t busy : 1; - mmr_t reserved_0 : 62; - mmr_t re_enable_gfx_stall : 1; - } sh_gfx_write_status_1_s; -} sh_gfx_write_status_1_u_t; - -/* ==================================================================== */ -/* Register "SH_II_INT0" */ -/* SHub II Interrupt 0 Registers */ -/* ==================================================================== */ - -typedef union sh_ii_int0_u { - mmr_t sh_ii_int0_regval; - struct { - mmr_t idx : 8; - mmr_t send : 1; - mmr_t reserved_0 : 55; - } sh_ii_int0_s; -} sh_ii_int0_u_t; - -/* ==================================================================== */ -/* Register "SH_II_INT0_CONFIG" */ -/* SHub II Interrupt 0 Config Registers */ -/* ==================================================================== */ - -typedef union sh_ii_int0_config_u { - mmr_t sh_ii_int0_config_regval; - struct { - mmr_t type : 3; - mmr_t agt : 1; - mmr_t pid : 16; - mmr_t reserved_0 : 1; - mmr_t base : 29; - mmr_t reserved_1 : 14; - } sh_ii_int0_config_s; -} sh_ii_int0_config_u_t; - -/* ==================================================================== */ -/* Register "SH_II_INT0_ENABLE" */ -/* SHub II Interrupt 0 Enable Registers */ -/* ==================================================================== */ - -typedef union sh_ii_int0_enable_u { - mmr_t sh_ii_int0_enable_regval; - struct { - mmr_t ii_enable : 1; - mmr_t reserved_0 : 63; - } sh_ii_int0_enable_s; -} sh_ii_int0_enable_u_t; - -/* ==================================================================== */ -/* Register "SH_II_INT1" */ -/* SHub II Interrupt 1 Registers */ -/* ==================================================================== */ - -typedef union sh_ii_int1_u { - mmr_t sh_ii_int1_regval; - struct { - mmr_t idx : 8; - mmr_t send : 1; - mmr_t reserved_0 : 55; - } sh_ii_int1_s; -} sh_ii_int1_u_t; - -/* ==================================================================== */ -/* Register "SH_II_INT1_CONFIG" */ -/* SHub II Interrupt 1 Config Registers */ -/* ==================================================================== */ - -typedef union sh_ii_int1_config_u { - mmr_t sh_ii_int1_config_regval; - struct { - mmr_t type : 3; - mmr_t agt : 1; - mmr_t pid : 16; - mmr_t reserved_0 : 1; - mmr_t base : 29; - mmr_t reserved_1 : 14; - } sh_ii_int1_config_s; -} sh_ii_int1_config_u_t; - -/* ==================================================================== */ -/* Register "SH_II_INT1_ENABLE" */ -/* SHub II Interrupt 1 Enable Registers */ -/* ==================================================================== */ - -typedef union sh_ii_int1_enable_u { - mmr_t sh_ii_int1_enable_regval; - struct { - mmr_t ii_enable : 1; - mmr_t reserved_0 : 63; - } sh_ii_int1_enable_s; -} sh_ii_int1_enable_u_t; - -/* ==================================================================== */ -/* Register "SH_INT_NODE_ID_CONFIG" */ -/* SHub Interrupt Node ID Configuration */ -/* ==================================================================== */ - -typedef union sh_int_node_id_config_u { - mmr_t sh_int_node_id_config_regval; - struct { - mmr_t node_id : 11; - mmr_t id_sel : 1; - mmr_t reserved_0 : 52; - } sh_int_node_id_config_s; -} sh_int_node_id_config_u_t; - -/* ==================================================================== */ -/* Register "SH_IPI_INT" */ -/* SHub Inter-Processor Interrupt Registers */ -/* ==================================================================== */ - -typedef union sh_ipi_int_u { - mmr_t sh_ipi_int_regval; - struct { - mmr_t type : 3; - mmr_t agt : 1; - mmr_t pid : 16; - mmr_t reserved_0 : 1; - mmr_t base : 29; - mmr_t reserved_1 : 2; - mmr_t idx : 8; - mmr_t reserved_2 : 3; - mmr_t send : 1; - } sh_ipi_int_s; -} sh_ipi_int_u_t; - -/* ==================================================================== */ -/* Register "SH_IPI_INT_ENABLE" */ -/* SHub Inter-Processor Interrupt Enable Registers */ -/* ==================================================================== */ - -typedef union sh_ipi_int_enable_u { - mmr_t sh_ipi_int_enable_regval; - struct { - mmr_t pio_enable : 1; - mmr_t reserved_0 : 63; - } sh_ipi_int_enable_s; -} sh_ipi_int_enable_u_t; - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT0_CONFIG" */ -/* SHub Local Interrupt 0 Registers */ -/* ==================================================================== */ - -typedef union sh_local_int0_config_u { - mmr_t sh_local_int0_config_regval; - struct { - mmr_t type : 3; - mmr_t agt : 1; - mmr_t pid : 16; - mmr_t reserved_0 : 1; - mmr_t base : 29; - mmr_t reserved_1 : 2; - mmr_t idx : 8; - mmr_t reserved_2 : 4; - } sh_local_int0_config_s; -} sh_local_int0_config_u_t; - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT0_ENABLE" */ -/* SHub Local Interrupt 0 Enable */ -/* ==================================================================== */ - -typedef union sh_local_int0_enable_u { - mmr_t sh_local_int0_enable_regval; - struct { - mmr_t pi_hw_int : 1; - mmr_t md_hw_int : 1; - mmr_t xn_hw_int : 1; - mmr_t lb_hw_int : 1; - mmr_t ii_hw_int : 1; - mmr_t pi_ce_int : 1; - mmr_t md_ce_int : 1; - mmr_t xn_ce_int : 1; - mmr_t pi_uce_int : 1; - mmr_t md_uce_int : 1; - mmr_t xn_uce_int : 1; - mmr_t reserved_0 : 1; - mmr_t system_shutdown_int : 1; - mmr_t uart_int : 1; - mmr_t l1_nmi_int : 1; - mmr_t stop_clock : 1; - mmr_t reserved_1 : 48; - } sh_local_int0_enable_s; -} sh_local_int0_enable_u_t; - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT1_CONFIG" */ -/* SHub Local Interrupt 1 Registers */ -/* ==================================================================== */ - -typedef union sh_local_int1_config_u { - mmr_t sh_local_int1_config_regval; - struct { - mmr_t type : 3; - mmr_t agt : 1; - mmr_t pid : 16; - mmr_t reserved_0 : 1; - mmr_t base : 29; - mmr_t reserved_1 : 2; - mmr_t idx : 8; - mmr_t reserved_2 : 4; - } sh_local_int1_config_s; -} sh_local_int1_config_u_t; - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT1_ENABLE" */ -/* SHub Local Interrupt 1 Enable */ -/* ==================================================================== */ - -typedef union sh_local_int1_enable_u { - mmr_t sh_local_int1_enable_regval; - struct { - mmr_t pi_hw_int : 1; - mmr_t md_hw_int : 1; - mmr_t xn_hw_int : 1; - mmr_t lb_hw_int : 1; - mmr_t ii_hw_int : 1; - mmr_t pi_ce_int : 1; - mmr_t md_ce_int : 1; - mmr_t xn_ce_int : 1; - mmr_t pi_uce_int : 1; - mmr_t md_uce_int : 1; - mmr_t xn_uce_int : 1; - mmr_t reserved_0 : 1; - mmr_t system_shutdown_int : 1; - mmr_t uart_int : 1; - mmr_t l1_nmi_int : 1; - mmr_t stop_clock : 1; - mmr_t reserved_1 : 48; - } sh_local_int1_enable_s; -} sh_local_int1_enable_u_t; - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT2_CONFIG" */ -/* SHub Local Interrupt 2 Registers */ -/* ==================================================================== */ - -typedef union sh_local_int2_config_u { - mmr_t sh_local_int2_config_regval; - struct { - mmr_t type : 3; - mmr_t agt : 1; - mmr_t pid : 16; - mmr_t reserved_0 : 1; - mmr_t base : 29; - mmr_t reserved_1 : 2; - mmr_t idx : 8; - mmr_t reserved_2 : 4; - } sh_local_int2_config_s; -} sh_local_int2_config_u_t; - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT2_ENABLE" */ -/* SHub Local Interrupt 2 Enable */ -/* ==================================================================== */ - -typedef union sh_local_int2_enable_u { - mmr_t sh_local_int2_enable_regval; - struct { - mmr_t pi_hw_int : 1; - mmr_t md_hw_int : 1; - mmr_t xn_hw_int : 1; - mmr_t lb_hw_int : 1; - mmr_t ii_hw_int : 1; - mmr_t pi_ce_int : 1; - mmr_t md_ce_int : 1; - mmr_t xn_ce_int : 1; - mmr_t pi_uce_int : 1; - mmr_t md_uce_int : 1; - mmr_t xn_uce_int : 1; - mmr_t reserved_0 : 1; - mmr_t system_shutdown_int : 1; - mmr_t uart_int : 1; - mmr_t l1_nmi_int : 1; - mmr_t stop_clock : 1; - mmr_t reserved_1 : 48; - } sh_local_int2_enable_s; -} sh_local_int2_enable_u_t; - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT3_CONFIG" */ -/* SHub Local Interrupt 3 Registers */ -/* ==================================================================== */ - -typedef union sh_local_int3_config_u { - mmr_t sh_local_int3_config_regval; - struct { - mmr_t type : 3; - mmr_t agt : 1; - mmr_t pid : 16; - mmr_t reserved_0 : 1; - mmr_t base : 29; - mmr_t reserved_1 : 2; - mmr_t idx : 8; - mmr_t reserved_2 : 4; - } sh_local_int3_config_s; -} sh_local_int3_config_u_t; - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT3_ENABLE" */ -/* SHub Local Interrupt 3 Enable */ -/* ==================================================================== */ - -typedef union sh_local_int3_enable_u { - mmr_t sh_local_int3_enable_regval; - struct { - mmr_t pi_hw_int : 1; - mmr_t md_hw_int : 1; - mmr_t xn_hw_int : 1; - mmr_t lb_hw_int : 1; - mmr_t ii_hw_int : 1; - mmr_t pi_ce_int : 1; - mmr_t md_ce_int : 1; - mmr_t xn_ce_int : 1; - mmr_t pi_uce_int : 1; - mmr_t md_uce_int : 1; - mmr_t xn_uce_int : 1; - mmr_t reserved_0 : 1; - mmr_t system_shutdown_int : 1; - mmr_t uart_int : 1; - mmr_t l1_nmi_int : 1; - mmr_t stop_clock : 1; - mmr_t reserved_1 : 48; - } sh_local_int3_enable_s; -} sh_local_int3_enable_u_t; - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT4_CONFIG" */ -/* SHub Local Interrupt 4 Registers */ -/* ==================================================================== */ - -typedef union sh_local_int4_config_u { - mmr_t sh_local_int4_config_regval; - struct { - mmr_t type : 3; - mmr_t agt : 1; - mmr_t pid : 16; - mmr_t reserved_0 : 1; - mmr_t base : 29; - mmr_t reserved_1 : 2; - mmr_t idx : 8; - mmr_t reserved_2 : 4; - } sh_local_int4_config_s; -} sh_local_int4_config_u_t; - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT4_ENABLE" */ -/* SHub Local Interrupt 4 Enable */ -/* ==================================================================== */ - -typedef union sh_local_int4_enable_u { - mmr_t sh_local_int4_enable_regval; - struct { - mmr_t pi_hw_int : 1; - mmr_t md_hw_int : 1; - mmr_t xn_hw_int : 1; - mmr_t lb_hw_int : 1; - mmr_t ii_hw_int : 1; - mmr_t pi_ce_int : 1; - mmr_t md_ce_int : 1; - mmr_t xn_ce_int : 1; - mmr_t pi_uce_int : 1; - mmr_t md_uce_int : 1; - mmr_t xn_uce_int : 1; - mmr_t reserved_0 : 1; - mmr_t system_shutdown_int : 1; - mmr_t uart_int : 1; - mmr_t l1_nmi_int : 1; - mmr_t stop_clock : 1; - mmr_t reserved_1 : 48; - } sh_local_int4_enable_s; -} sh_local_int4_enable_u_t; - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT5_CONFIG" */ -/* SHub Local Interrupt 5 Registers */ -/* ==================================================================== */ - -typedef union sh_local_int5_config_u { - mmr_t sh_local_int5_config_regval; - struct { - mmr_t type : 3; - mmr_t agt : 1; - mmr_t pid : 16; - mmr_t reserved_0 : 1; - mmr_t base : 29; - mmr_t reserved_1 : 2; - mmr_t idx : 8; - mmr_t reserved_2 : 4; - } sh_local_int5_config_s; -} sh_local_int5_config_u_t; - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT5_ENABLE" */ -/* SHub Local Interrupt 5 Enable */ -/* ==================================================================== */ - -typedef union sh_local_int5_enable_u { - mmr_t sh_local_int5_enable_regval; - struct { - mmr_t pi_hw_int : 1; - mmr_t md_hw_int : 1; - mmr_t xn_hw_int : 1; - mmr_t lb_hw_int : 1; - mmr_t ii_hw_int : 1; - mmr_t pi_ce_int : 1; - mmr_t md_ce_int : 1; - mmr_t xn_ce_int : 1; - mmr_t pi_uce_int : 1; - mmr_t md_uce_int : 1; - mmr_t xn_uce_int : 1; - mmr_t reserved_0 : 1; - mmr_t system_shutdown_int : 1; - mmr_t uart_int : 1; - mmr_t l1_nmi_int : 1; - mmr_t stop_clock : 1; - mmr_t reserved_1 : 48; - } sh_local_int5_enable_s; -} sh_local_int5_enable_u_t; - -/* ==================================================================== */ -/* Register "SH_PROC0_ERR_INT_CONFIG" */ -/* SHub Processor 0 Error Interrupt Registers */ -/* ==================================================================== */ - -typedef union sh_proc0_err_int_config_u { - mmr_t sh_proc0_err_int_config_regval; - struct { - mmr_t type : 3; - mmr_t agt : 1; - mmr_t pid : 16; - mmr_t reserved_0 : 1; - mmr_t base : 29; - mmr_t reserved_1 : 2; - mmr_t idx : 8; - mmr_t reserved_2 : 4; - } sh_proc0_err_int_config_s; -} sh_proc0_err_int_config_u_t; - -/* ==================================================================== */ -/* Register "SH_PROC1_ERR_INT_CONFIG" */ -/* SHub Processor 1 Error Interrupt Registers */ -/* ==================================================================== */ - -typedef union sh_proc1_err_int_config_u { - mmr_t sh_proc1_err_int_config_regval; - struct { - mmr_t type : 3; - mmr_t agt : 1; - mmr_t pid : 16; - mmr_t reserved_0 : 1; - mmr_t base : 29; - mmr_t reserved_1 : 2; - mmr_t idx : 8; - mmr_t reserved_2 : 4; - } sh_proc1_err_int_config_s; -} sh_proc1_err_int_config_u_t; - -/* ==================================================================== */ -/* Register "SH_PROC2_ERR_INT_CONFIG" */ -/* SHub Processor 2 Error Interrupt Registers */ -/* ==================================================================== */ - -typedef union sh_proc2_err_int_config_u { - mmr_t sh_proc2_err_int_config_regval; - struct { - mmr_t type : 3; - mmr_t agt : 1; - mmr_t pid : 16; - mmr_t reserved_0 : 1; - mmr_t base : 29; - mmr_t reserved_1 : 2; - mmr_t idx : 8; - mmr_t reserved_2 : 4; - } sh_proc2_err_int_config_s; -} sh_proc2_err_int_config_u_t; - -/* ==================================================================== */ -/* Register "SH_PROC3_ERR_INT_CONFIG" */ -/* SHub Processor 3 Error Interrupt Registers */ -/* ==================================================================== */ - -typedef union sh_proc3_err_int_config_u { - mmr_t sh_proc3_err_int_config_regval; - struct { - mmr_t type : 3; - mmr_t agt : 1; - mmr_t pid : 16; - mmr_t reserved_0 : 1; - mmr_t base : 29; - mmr_t reserved_1 : 2; - mmr_t idx : 8; - mmr_t reserved_2 : 4; - } sh_proc3_err_int_config_s; -} sh_proc3_err_int_config_u_t; - -/* ==================================================================== */ -/* Register "SH_PROC0_ADV_INT_CONFIG" */ -/* SHub Processor 0 Advisory Interrupt Registers */ -/* ==================================================================== */ - -typedef union sh_proc0_adv_int_config_u { - mmr_t sh_proc0_adv_int_config_regval; - struct { - mmr_t type : 3; - mmr_t agt : 1; - mmr_t pid : 16; - mmr_t reserved_0 : 1; - mmr_t base : 29; - mmr_t reserved_1 : 2; - mmr_t idx : 8; - mmr_t reserved_2 : 4; - } sh_proc0_adv_int_config_s; -} sh_proc0_adv_int_config_u_t; - -/* ==================================================================== */ -/* Register "SH_PROC1_ADV_INT_CONFIG" */ -/* SHub Processor 1 Advisory Interrupt Registers */ -/* ==================================================================== */ - -typedef union sh_proc1_adv_int_config_u { - mmr_t sh_proc1_adv_int_config_regval; - struct { - mmr_t type : 3; - mmr_t agt : 1; - mmr_t pid : 16; - mmr_t reserved_0 : 1; - mmr_t base : 29; - mmr_t reserved_1 : 2; - mmr_t idx : 8; - mmr_t reserved_2 : 4; - } sh_proc1_adv_int_config_s; -} sh_proc1_adv_int_config_u_t; - -/* ==================================================================== */ -/* Register "SH_PROC2_ADV_INT_CONFIG" */ -/* SHub Processor 2 Advisory Interrupt Registers */ -/* ==================================================================== */ - -typedef union sh_proc2_adv_int_config_u { - mmr_t sh_proc2_adv_int_config_regval; - struct { - mmr_t type : 3; - mmr_t agt : 1; - mmr_t pid : 16; - mmr_t reserved_0 : 1; - mmr_t base : 29; - mmr_t reserved_1 : 2; - mmr_t idx : 8; - mmr_t reserved_2 : 4; - } sh_proc2_adv_int_config_s; -} sh_proc2_adv_int_config_u_t; - -/* ==================================================================== */ -/* Register "SH_PROC3_ADV_INT_CONFIG" */ -/* SHub Processor 3 Advisory Interrupt Registers */ -/* ==================================================================== */ - -typedef union sh_proc3_adv_int_config_u { - mmr_t sh_proc3_adv_int_config_regval; - struct { - mmr_t type : 3; - mmr_t agt : 1; - mmr_t pid : 16; - mmr_t reserved_0 : 1; - mmr_t base : 29; - mmr_t reserved_1 : 2; - mmr_t idx : 8; - mmr_t reserved_2 : 4; - } sh_proc3_adv_int_config_s; -} sh_proc3_adv_int_config_u_t; - -/* ==================================================================== */ -/* Register "SH_PROC0_ERR_INT_ENABLE" */ -/* SHub Processor 0 Error Interrupt Enable Registers */ -/* ==================================================================== */ - -typedef union sh_proc0_err_int_enable_u { - mmr_t sh_proc0_err_int_enable_regval; - struct { - mmr_t proc0_err_enable : 1; - mmr_t reserved_0 : 63; - } sh_proc0_err_int_enable_s; -} sh_proc0_err_int_enable_u_t; - -/* ==================================================================== */ -/* Register "SH_PROC1_ERR_INT_ENABLE" */ -/* SHub Processor 1 Error Interrupt Enable Registers */ -/* ==================================================================== */ - -typedef union sh_proc1_err_int_enable_u { - mmr_t sh_proc1_err_int_enable_regval; - struct { - mmr_t proc1_err_enable : 1; - mmr_t reserved_0 : 63; - } sh_proc1_err_int_enable_s; -} sh_proc1_err_int_enable_u_t; - -/* ==================================================================== */ -/* Register "SH_PROC2_ERR_INT_ENABLE" */ -/* SHub Processor 2 Error Interrupt Enable Registers */ -/* ==================================================================== */ - -typedef union sh_proc2_err_int_enable_u { - mmr_t sh_proc2_err_int_enable_regval; - struct { - mmr_t proc2_err_enable : 1; - mmr_t reserved_0 : 63; - } sh_proc2_err_int_enable_s; -} sh_proc2_err_int_enable_u_t; - -/* ==================================================================== */ -/* Register "SH_PROC3_ERR_INT_ENABLE" */ -/* SHub Processor 3 Error Interrupt Enable Registers */ -/* ==================================================================== */ - -typedef union sh_proc3_err_int_enable_u { - mmr_t sh_proc3_err_int_enable_regval; - struct { - mmr_t proc3_err_enable : 1; - mmr_t reserved_0 : 63; - } sh_proc3_err_int_enable_s; -} sh_proc3_err_int_enable_u_t; - -/* ==================================================================== */ -/* Register "SH_PROC0_ADV_INT_ENABLE" */ -/* SHub Processor 0 Advisory Interrupt Enable Registers */ -/* ==================================================================== */ - -typedef union sh_proc0_adv_int_enable_u { - mmr_t sh_proc0_adv_int_enable_regval; - struct { - mmr_t proc0_adv_enable : 1; - mmr_t reserved_0 : 63; - } sh_proc0_adv_int_enable_s; -} sh_proc0_adv_int_enable_u_t; - -/* ==================================================================== */ -/* Register "SH_PROC1_ADV_INT_ENABLE" */ -/* SHub Processor 1 Advisory Interrupt Enable Registers */ -/* ==================================================================== */ - -typedef union sh_proc1_adv_int_enable_u { - mmr_t sh_proc1_adv_int_enable_regval; - struct { - mmr_t proc1_adv_enable : 1; - mmr_t reserved_0 : 63; - } sh_proc1_adv_int_enable_s; -} sh_proc1_adv_int_enable_u_t; - -/* ==================================================================== */ -/* Register "SH_PROC2_ADV_INT_ENABLE" */ -/* SHub Processor 2 Advisory Interrupt Enable Registers */ -/* ==================================================================== */ - -typedef union sh_proc2_adv_int_enable_u { - mmr_t sh_proc2_adv_int_enable_regval; - struct { - mmr_t proc2_adv_enable : 1; - mmr_t reserved_0 : 63; - } sh_proc2_adv_int_enable_s; -} sh_proc2_adv_int_enable_u_t; - -/* ==================================================================== */ -/* Register "SH_PROC3_ADV_INT_ENABLE" */ -/* SHub Processor 3 Advisory Interrupt Enable Registers */ -/* ==================================================================== */ - -typedef union sh_proc3_adv_int_enable_u { - mmr_t sh_proc3_adv_int_enable_regval; - struct { - mmr_t proc3_adv_enable : 1; - mmr_t reserved_0 : 63; - } sh_proc3_adv_int_enable_s; -} sh_proc3_adv_int_enable_u_t; - -/* ==================================================================== */ -/* Register "SH_PROFILE_INT_CONFIG" */ -/* SHub Profile Interrupt Configuration Registers */ -/* ==================================================================== */ - -typedef union sh_profile_int_config_u { - mmr_t sh_profile_int_config_regval; - struct { - mmr_t type : 3; - mmr_t agt : 1; - mmr_t pid : 16; - mmr_t reserved_0 : 1; - mmr_t base : 29; - mmr_t reserved_1 : 2; - mmr_t idx : 8; - mmr_t reserved_2 : 4; - } sh_profile_int_config_s; -} sh_profile_int_config_u_t; - -/* ==================================================================== */ -/* Register "SH_PROFILE_INT_ENABLE" */ -/* SHub Profile Interrupt Enable Registers */ -/* ==================================================================== */ - -typedef union sh_profile_int_enable_u { - mmr_t sh_profile_int_enable_regval; - struct { - mmr_t profile_enable : 1; - mmr_t reserved_0 : 63; - } sh_profile_int_enable_s; -} sh_profile_int_enable_u_t; - -/* ==================================================================== */ -/* Register "SH_RTC0_INT_CONFIG" */ -/* SHub RTC 0 Interrupt Config Registers */ -/* ==================================================================== */ - -typedef union sh_rtc0_int_config_u { - mmr_t sh_rtc0_int_config_regval; - struct { - mmr_t type : 3; - mmr_t agt : 1; - mmr_t pid : 16; - mmr_t reserved_0 : 1; - mmr_t base : 29; - mmr_t reserved_1 : 2; - mmr_t idx : 8; - mmr_t reserved_2 : 4; - } sh_rtc0_int_config_s; -} sh_rtc0_int_config_u_t; - -/* ==================================================================== */ -/* Register "SH_RTC0_INT_ENABLE" */ -/* SHub RTC 0 Interrupt Enable Registers */ -/* ==================================================================== */ - -typedef union sh_rtc0_int_enable_u { - mmr_t sh_rtc0_int_enable_regval; - struct { - mmr_t rtc0_enable : 1; - mmr_t reserved_0 : 63; - } sh_rtc0_int_enable_s; -} sh_rtc0_int_enable_u_t; - -/* ==================================================================== */ -/* Register "SH_RTC1_INT_CONFIG" */ -/* SHub RTC 1 Interrupt Config Registers */ -/* ==================================================================== */ - -typedef union sh_rtc1_int_config_u { - mmr_t sh_rtc1_int_config_regval; - struct { - mmr_t type : 3; - mmr_t agt : 1; - mmr_t pid : 16; - mmr_t reserved_0 : 1; - mmr_t base : 29; - mmr_t reserved_1 : 2; - mmr_t idx : 8; - mmr_t reserved_2 : 4; - } sh_rtc1_int_config_s; -} sh_rtc1_int_config_u_t; - -/* ==================================================================== */ -/* Register "SH_RTC1_INT_ENABLE" */ -/* SHub RTC 1 Interrupt Enable Registers */ -/* ==================================================================== */ - -typedef union sh_rtc1_int_enable_u { - mmr_t sh_rtc1_int_enable_regval; - struct { - mmr_t rtc1_enable : 1; - mmr_t reserved_0 : 63; - } sh_rtc1_int_enable_s; -} sh_rtc1_int_enable_u_t; - -/* ==================================================================== */ -/* Register "SH_RTC2_INT_CONFIG" */ -/* SHub RTC 2 Interrupt Config Registers */ -/* ==================================================================== */ - -typedef union sh_rtc2_int_config_u { - mmr_t sh_rtc2_int_config_regval; - struct { - mmr_t type : 3; - mmr_t agt : 1; - mmr_t pid : 16; - mmr_t reserved_0 : 1; - mmr_t base : 29; - mmr_t reserved_1 : 2; - mmr_t idx : 8; - mmr_t reserved_2 : 4; - } sh_rtc2_int_config_s; -} sh_rtc2_int_config_u_t; - -/* ==================================================================== */ -/* Register "SH_RTC2_INT_ENABLE" */ -/* SHub RTC 2 Interrupt Enable Registers */ -/* ==================================================================== */ - -typedef union sh_rtc2_int_enable_u { - mmr_t sh_rtc2_int_enable_regval; - struct { - mmr_t rtc2_enable : 1; - mmr_t reserved_0 : 63; - } sh_rtc2_int_enable_s; -} sh_rtc2_int_enable_u_t; - -/* ==================================================================== */ -/* Register "SH_RTC3_INT_CONFIG" */ -/* SHub RTC 3 Interrupt Config Registers */ -/* ==================================================================== */ - -typedef union sh_rtc3_int_config_u { - mmr_t sh_rtc3_int_config_regval; - struct { - mmr_t type : 3; - mmr_t agt : 1; - mmr_t pid : 16; - mmr_t reserved_0 : 1; - mmr_t base : 29; - mmr_t reserved_1 : 2; - mmr_t idx : 8; - mmr_t reserved_2 : 4; - } sh_rtc3_int_config_s; -} sh_rtc3_int_config_u_t; - -/* ==================================================================== */ -/* Register "SH_RTC3_INT_ENABLE" */ -/* SHub RTC 3 Interrupt Enable Registers */ -/* ==================================================================== */ - -typedef union sh_rtc3_int_enable_u { - mmr_t sh_rtc3_int_enable_regval; - struct { - mmr_t rtc3_enable : 1; - mmr_t reserved_0 : 63; - } sh_rtc3_int_enable_s; -} sh_rtc3_int_enable_u_t; - -/* ==================================================================== */ -/* Register "SH_EVENT_OCCURRED" */ -/* SHub Interrupt Event Occurred */ -/* ==================================================================== */ - -typedef union sh_event_occurred_u { - mmr_t sh_event_occurred_regval; - struct { - mmr_t pi_hw_int : 1; - mmr_t md_hw_int : 1; - mmr_t xn_hw_int : 1; - mmr_t lb_hw_int : 1; - mmr_t ii_hw_int : 1; - mmr_t pi_ce_int : 1; - mmr_t md_ce_int : 1; - mmr_t xn_ce_int : 1; - mmr_t pi_uce_int : 1; - mmr_t md_uce_int : 1; - mmr_t xn_uce_int : 1; - mmr_t proc0_adv_int : 1; - mmr_t proc1_adv_int : 1; - mmr_t proc2_adv_int : 1; - mmr_t proc3_adv_int : 1; - mmr_t proc0_err_int : 1; - mmr_t proc1_err_int : 1; - mmr_t proc2_err_int : 1; - mmr_t proc3_err_int : 1; - mmr_t system_shutdown_int : 1; - mmr_t uart_int : 1; - mmr_t l1_nmi_int : 1; - mmr_t stop_clock : 1; - mmr_t rtc0_int : 1; - mmr_t rtc1_int : 1; - mmr_t rtc2_int : 1; - mmr_t rtc3_int : 1; - mmr_t profile_int : 1; - mmr_t ipi_int : 1; - mmr_t ii_int0 : 1; - mmr_t ii_int1 : 1; - mmr_t reserved_0 : 33; - } sh_event_occurred_s; -} sh_event_occurred_u_t; - -/* ==================================================================== */ -/* Register "SH_EVENT_OVERFLOW" */ -/* SHub Interrupt Event Occurred Overflow */ -/* ==================================================================== */ - -typedef union sh_event_overflow_u { - mmr_t sh_event_overflow_regval; - struct { - mmr_t pi_hw_int : 1; - mmr_t md_hw_int : 1; - mmr_t xn_hw_int : 1; - mmr_t lb_hw_int : 1; - mmr_t ii_hw_int : 1; - mmr_t pi_ce_int : 1; - mmr_t md_ce_int : 1; - mmr_t xn_ce_int : 1; - mmr_t pi_uce_int : 1; - mmr_t md_uce_int : 1; - mmr_t xn_uce_int : 1; - mmr_t proc0_adv_int : 1; - mmr_t proc1_adv_int : 1; - mmr_t proc2_adv_int : 1; - mmr_t proc3_adv_int : 1; - mmr_t proc0_err_int : 1; - mmr_t proc1_err_int : 1; - mmr_t proc2_err_int : 1; - mmr_t proc3_err_int : 1; - mmr_t system_shutdown_int : 1; - mmr_t uart_int : 1; - mmr_t l1_nmi_int : 1; - mmr_t stop_clock : 1; - mmr_t rtc0_int : 1; - mmr_t rtc1_int : 1; - mmr_t rtc2_int : 1; - mmr_t rtc3_int : 1; - mmr_t profile_int : 1; - mmr_t reserved_0 : 36; - } sh_event_overflow_s; -} sh_event_overflow_u_t; - -/* ==================================================================== */ -/* Register "SH_JUNK_BUS_TIME" */ -/* Junk Bus Timing */ -/* ==================================================================== */ - -typedef union sh_junk_bus_time_u { - mmr_t sh_junk_bus_time_regval; - struct { - mmr_t fprom_setup_hold : 8; - mmr_t fprom_enable : 8; - mmr_t uart_setup_hold : 8; - mmr_t uart_enable : 8; - mmr_t reserved_0 : 32; - } sh_junk_bus_time_s; -} sh_junk_bus_time_u_t; - -/* ==================================================================== */ -/* Register "SH_JUNK_LATCH_TIME" */ -/* Junk Bus Latch Timing */ -/* ==================================================================== */ - -typedef union sh_junk_latch_time_u { - mmr_t sh_junk_latch_time_regval; - struct { - mmr_t setup_hold : 3; - mmr_t reserved_0 : 61; - } sh_junk_latch_time_s; -} sh_junk_latch_time_u_t; - -/* ==================================================================== */ -/* Register "SH_JUNK_NACK_RESET" */ -/* Junk Bus Nack Counter Reset */ -/* ==================================================================== */ - -typedef union sh_junk_nack_reset_u { - mmr_t sh_junk_nack_reset_regval; - struct { - mmr_t pulse : 1; - mmr_t reserved_0 : 63; - } sh_junk_nack_reset_s; -} sh_junk_nack_reset_u_t; - -/* ==================================================================== */ -/* Register "SH_JUNK_BUS_LED0" */ -/* Junk Bus LED0 */ -/* ==================================================================== */ - -typedef union sh_junk_bus_led0_u { - mmr_t sh_junk_bus_led0_regval; - struct { - mmr_t led0_data : 8; - mmr_t reserved_0 : 56; - } sh_junk_bus_led0_s; -} sh_junk_bus_led0_u_t; - -/* ==================================================================== */ -/* Register "SH_JUNK_BUS_LED1" */ -/* Junk Bus LED1 */ -/* ==================================================================== */ - -typedef union sh_junk_bus_led1_u { - mmr_t sh_junk_bus_led1_regval; - struct { - mmr_t led1_data : 8; - mmr_t reserved_0 : 56; - } sh_junk_bus_led1_s; -} sh_junk_bus_led1_u_t; - -/* ==================================================================== */ -/* Register "SH_JUNK_BUS_LED2" */ -/* Junk Bus LED2 */ -/* ==================================================================== */ - -typedef union sh_junk_bus_led2_u { - mmr_t sh_junk_bus_led2_regval; - struct { - mmr_t led2_data : 8; - mmr_t reserved_0 : 56; - } sh_junk_bus_led2_s; -} sh_junk_bus_led2_u_t; - -/* ==================================================================== */ -/* Register "SH_JUNK_BUS_LED3" */ -/* Junk Bus LED3 */ -/* ==================================================================== */ - -typedef union sh_junk_bus_led3_u { - mmr_t sh_junk_bus_led3_regval; - struct { - mmr_t led3_data : 8; - mmr_t reserved_0 : 56; - } sh_junk_bus_led3_s; -} sh_junk_bus_led3_u_t; - -/* ==================================================================== */ -/* Register "SH_JUNK_ERROR_STATUS" */ -/* Junk Bus Error Status */ -/* ==================================================================== */ - -typedef union sh_junk_error_status_u { - mmr_t sh_junk_error_status_regval; - struct { - mmr_t address : 47; - mmr_t reserved_0 : 1; - mmr_t cmd : 8; - mmr_t mode : 1; - mmr_t status : 4; - mmr_t reserved_1 : 3; - } sh_junk_error_status_s; -} sh_junk_error_status_u_t; - -/* ==================================================================== */ -/* Register "SH_NI0_LLP_STAT" */ -/* This register describes the LLP status. */ -/* ==================================================================== */ - -typedef union sh_ni0_llp_stat_u { - mmr_t sh_ni0_llp_stat_regval; - struct { - mmr_t link_reset_state : 4; - mmr_t reserved_0 : 60; - } sh_ni0_llp_stat_s; -} sh_ni0_llp_stat_u_t; - -/* ==================================================================== */ -/* Register "SH_NI0_LLP_RESET" */ -/* Writing issues a reset to the network interface */ -/* ==================================================================== */ - -typedef union sh_ni0_llp_reset_u { - mmr_t sh_ni0_llp_reset_regval; - struct { - mmr_t link : 1; - mmr_t warm : 1; - mmr_t reserved_0 : 62; - } sh_ni0_llp_reset_s; -} sh_ni0_llp_reset_u_t; - -/* ==================================================================== */ -/* Register "SH_NI0_LLP_RESET_EN" */ -/* Controls LLP warm reset propagation */ -/* ==================================================================== */ - -typedef union sh_ni0_llp_reset_en_u { - mmr_t sh_ni0_llp_reset_en_regval; - struct { - mmr_t ok : 1; - mmr_t reserved_0 : 63; - } sh_ni0_llp_reset_en_s; -} sh_ni0_llp_reset_en_u_t; - -/* ==================================================================== */ -/* Register "SH_NI0_LLP_CHAN_MODE" */ -/* Sets the signaling mode of LLP and channel */ -/* ==================================================================== */ - -typedef union sh_ni0_llp_chan_mode_u { - mmr_t sh_ni0_llp_chan_mode_regval; - struct { - mmr_t bitmode32 : 1; - mmr_t ac_encode : 1; - mmr_t enable_tuning : 1; - mmr_t enable_rmt_ft_upd : 1; - mmr_t enable_clkquad : 1; - mmr_t reserved_0 : 59; - } sh_ni0_llp_chan_mode_s; -} sh_ni0_llp_chan_mode_u_t; - -/* ==================================================================== */ -/* Register "SH_NI0_LLP_CONFIG" */ -/* Sets the configuration of LLP and channel */ -/* ==================================================================== */ - -typedef union sh_ni0_llp_config_u { - mmr_t sh_ni0_llp_config_regval; - struct { - mmr_t maxburst : 10; - mmr_t maxretry : 10; - mmr_t nulltimeout : 6; - mmr_t ftu_time : 12; - mmr_t reserved_0 : 26; - } sh_ni0_llp_config_s; -} sh_ni0_llp_config_u_t; - -/* ==================================================================== */ -/* Register "SH_NI0_LLP_TEST_CTL" */ -/* ==================================================================== */ - -typedef union sh_ni0_llp_test_ctl_u { - mmr_t sh_ni0_llp_test_ctl_regval; - struct { - mmr_t pattern : 40; - mmr_t send_test_mode : 2; - mmr_t reserved_0 : 2; - mmr_t wire_sel : 6; - mmr_t reserved_1 : 2; - mmr_t lfsr_mode : 2; - mmr_t noise_mode : 2; - mmr_t armcapture : 1; - mmr_t capturecbonly : 1; - mmr_t sendcberror : 1; - mmr_t sendsnerror : 1; - mmr_t fakesnerror : 1; - mmr_t captured : 1; - mmr_t cberror : 1; - mmr_t reserved_2 : 1; - } sh_ni0_llp_test_ctl_s; -} sh_ni0_llp_test_ctl_u_t; - -/* ==================================================================== */ -/* Register "SH_NI0_LLP_CAPT_WD1" */ -/* low order 64-bit captured word */ -/* ==================================================================== */ - -typedef union sh_ni0_llp_capt_wd1_u { - mmr_t sh_ni0_llp_capt_wd1_regval; - struct { - mmr_t data : 64; - } sh_ni0_llp_capt_wd1_s; -} sh_ni0_llp_capt_wd1_u_t; - -/* ==================================================================== */ -/* Register "SH_NI0_LLP_CAPT_WD2" */ -/* high order 64-bit captured word */ -/* ==================================================================== */ - -typedef union sh_ni0_llp_capt_wd2_u { - mmr_t sh_ni0_llp_capt_wd2_regval; - struct { - mmr_t data : 64; - } sh_ni0_llp_capt_wd2_s; -} sh_ni0_llp_capt_wd2_u_t; - -/* ==================================================================== */ -/* Register "SH_NI0_LLP_CAPT_SBCB" */ -/* captured sideband, sequence, and CRC */ -/* ==================================================================== */ - -typedef union sh_ni0_llp_capt_sbcb_u { - mmr_t sh_ni0_llp_capt_sbcb_regval; - struct { - mmr_t capturedrcvsbsn : 16; - mmr_t capturedrcvcrc : 16; - mmr_t sentallcberrors : 1; - mmr_t sentallsnerrors : 1; - mmr_t fakedallsnerrors : 1; - mmr_t chargeoverflow : 1; - mmr_t chargeunderflow : 1; - mmr_t reserved_0 : 27; - } sh_ni0_llp_capt_sbcb_s; -} sh_ni0_llp_capt_sbcb_u_t; - -/* ==================================================================== */ -/* Register "SH_NI0_LLP_ERR" */ -/* ==================================================================== */ - -typedef union sh_ni0_llp_err_u { - mmr_t sh_ni0_llp_err_regval; - struct { - mmr_t rx_sn_err_count : 8; - mmr_t rx_cb_err_count : 8; - mmr_t retry_count : 8; - mmr_t retry_timeout : 1; - mmr_t rcv_link_reset : 1; - mmr_t squash : 1; - mmr_t power_not_ok : 1; - mmr_t wire_cnt : 24; - mmr_t wire_overflow : 1; - mmr_t reserved_0 : 11; - } sh_ni0_llp_err_s; -} sh_ni0_llp_err_u_t; - -/* ==================================================================== */ -/* Register "SH_NI1_LLP_STAT" */ -/* This register describes the LLP status. */ -/* ==================================================================== */ - -typedef union sh_ni1_llp_stat_u { - mmr_t sh_ni1_llp_stat_regval; - struct { - mmr_t link_reset_state : 4; - mmr_t reserved_0 : 60; - } sh_ni1_llp_stat_s; -} sh_ni1_llp_stat_u_t; - -/* ==================================================================== */ -/* Register "SH_NI1_LLP_RESET" */ -/* Writing issues a reset to the network interface */ -/* ==================================================================== */ - -typedef union sh_ni1_llp_reset_u { - mmr_t sh_ni1_llp_reset_regval; - struct { - mmr_t link : 1; - mmr_t warm : 1; - mmr_t reserved_0 : 62; - } sh_ni1_llp_reset_s; -} sh_ni1_llp_reset_u_t; - -/* ==================================================================== */ -/* Register "SH_NI1_LLP_RESET_EN" */ -/* Controls LLP warm reset propagation */ -/* ==================================================================== */ - -typedef union sh_ni1_llp_reset_en_u { - mmr_t sh_ni1_llp_reset_en_regval; - struct { - mmr_t ok : 1; - mmr_t reserved_0 : 63; - } sh_ni1_llp_reset_en_s; -} sh_ni1_llp_reset_en_u_t; - -/* ==================================================================== */ -/* Register "SH_NI1_LLP_CHAN_MODE" */ -/* Sets the signaling mode of LLP and channel */ -/* ==================================================================== */ - -typedef union sh_ni1_llp_chan_mode_u { - mmr_t sh_ni1_llp_chan_mode_regval; - struct { - mmr_t bitmode32 : 1; - mmr_t ac_encode : 1; - mmr_t enable_tuning : 1; - mmr_t enable_rmt_ft_upd : 1; - mmr_t enable_clkquad : 1; - mmr_t reserved_0 : 59; - } sh_ni1_llp_chan_mode_s; -} sh_ni1_llp_chan_mode_u_t; - -/* ==================================================================== */ -/* Register "SH_NI1_LLP_CONFIG" */ -/* Sets the configuration of LLP and channel */ -/* ==================================================================== */ - -typedef union sh_ni1_llp_config_u { - mmr_t sh_ni1_llp_config_regval; - struct { - mmr_t maxburst : 10; - mmr_t maxretry : 10; - mmr_t nulltimeout : 6; - mmr_t ftu_time : 12; - mmr_t reserved_0 : 26; - } sh_ni1_llp_config_s; -} sh_ni1_llp_config_u_t; - -/* ==================================================================== */ -/* Register "SH_NI1_LLP_TEST_CTL" */ -/* ==================================================================== */ - -typedef union sh_ni1_llp_test_ctl_u { - mmr_t sh_ni1_llp_test_ctl_regval; - struct { - mmr_t pattern : 40; - mmr_t send_test_mode : 2; - mmr_t reserved_0 : 2; - mmr_t wire_sel : 6; - mmr_t reserved_1 : 2; - mmr_t lfsr_mode : 2; - mmr_t noise_mode : 2; - mmr_t armcapture : 1; - mmr_t capturecbonly : 1; - mmr_t sendcberror : 1; - mmr_t sendsnerror : 1; - mmr_t fakesnerror : 1; - mmr_t captured : 1; - mmr_t cberror : 1; - mmr_t reserved_2 : 1; - } sh_ni1_llp_test_ctl_s; -} sh_ni1_llp_test_ctl_u_t; - -/* ==================================================================== */ -/* Register "SH_NI1_LLP_CAPT_WD1" */ -/* low order 64-bit captured word */ -/* ==================================================================== */ - -typedef union sh_ni1_llp_capt_wd1_u { - mmr_t sh_ni1_llp_capt_wd1_regval; - struct { - mmr_t data : 64; - } sh_ni1_llp_capt_wd1_s; -} sh_ni1_llp_capt_wd1_u_t; - -/* ==================================================================== */ -/* Register "SH_NI1_LLP_CAPT_WD2" */ -/* high order 64-bit captured word */ -/* ==================================================================== */ - -typedef union sh_ni1_llp_capt_wd2_u { - mmr_t sh_ni1_llp_capt_wd2_regval; - struct { - mmr_t data : 64; - } sh_ni1_llp_capt_wd2_s; -} sh_ni1_llp_capt_wd2_u_t; - -/* ==================================================================== */ -/* Register "SH_NI1_LLP_CAPT_SBCB" */ -/* captured sideband, sequence, and CRC */ -/* ==================================================================== */ - -typedef union sh_ni1_llp_capt_sbcb_u { - mmr_t sh_ni1_llp_capt_sbcb_regval; - struct { - mmr_t capturedrcvsbsn : 16; - mmr_t capturedrcvcrc : 16; - mmr_t sentallcberrors : 1; - mmr_t sentallsnerrors : 1; - mmr_t fakedallsnerrors : 1; - mmr_t chargeoverflow : 1; - mmr_t chargeunderflow : 1; - mmr_t reserved_0 : 27; - } sh_ni1_llp_capt_sbcb_s; -} sh_ni1_llp_capt_sbcb_u_t; - -/* ==================================================================== */ -/* Register "SH_NI1_LLP_ERR" */ -/* ==================================================================== */ - -typedef union sh_ni1_llp_err_u { - mmr_t sh_ni1_llp_err_regval; - struct { - mmr_t rx_sn_err_count : 8; - mmr_t rx_cb_err_count : 8; - mmr_t retry_count : 8; - mmr_t retry_timeout : 1; - mmr_t rcv_link_reset : 1; - mmr_t squash : 1; - mmr_t power_not_ok : 1; - mmr_t wire_cnt : 24; - mmr_t wire_overflow : 1; - mmr_t reserved_0 : 11; - } sh_ni1_llp_err_s; -} sh_ni1_llp_err_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI0_LLP_TO_FIFO02_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni0_llp_to_fifo02_flow_u { - mmr_t sh_xnni0_llp_to_fifo02_flow_regval; - struct { - mmr_t debit_vc0_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_force_cred : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_2 : 8; - mmr_t credit_vc0_dyn : 6; - mmr_t reserved_3 : 2; - mmr_t credit_vc0_cap : 6; - mmr_t reserved_4 : 10; - mmr_t credit_vc2_dyn : 6; - mmr_t reserved_5 : 2; - mmr_t credit_vc2_cap : 6; - mmr_t reserved_6 : 2; - } sh_xnni0_llp_to_fifo02_flow_s; -} sh_xnni0_llp_to_fifo02_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI0_LLP_TO_FIFO13_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni0_llp_to_fifo13_flow_u { - mmr_t sh_xnni0_llp_to_fifo13_flow_regval; - struct { - mmr_t debit_vc0_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_force_cred : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_2 : 8; - mmr_t credit_vc0_dyn : 6; - mmr_t reserved_3 : 2; - mmr_t credit_vc0_cap : 6; - mmr_t reserved_4 : 10; - mmr_t credit_vc2_dyn : 6; - mmr_t reserved_5 : 2; - mmr_t credit_vc2_cap : 6; - mmr_t reserved_6 : 2; - } sh_xnni0_llp_to_fifo13_flow_s; -} sh_xnni0_llp_to_fifo13_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI0_LLP_DEBIT_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni0_llp_debit_flow_u { - mmr_t sh_xnni0_llp_debit_flow_regval; - struct { - mmr_t debit_vc0_dyn : 5; - mmr_t reserved_0 : 3; - mmr_t debit_vc0_cap : 5; - mmr_t reserved_1 : 3; - mmr_t debit_vc1_dyn : 5; - mmr_t reserved_2 : 3; - mmr_t debit_vc1_cap : 5; - mmr_t reserved_3 : 3; - mmr_t debit_vc2_dyn : 5; - mmr_t reserved_4 : 3; - mmr_t debit_vc2_cap : 5; - mmr_t reserved_5 : 3; - mmr_t debit_vc3_dyn : 5; - mmr_t reserved_6 : 3; - mmr_t debit_vc3_cap : 5; - mmr_t reserved_7 : 3; - } sh_xnni0_llp_debit_flow_s; -} sh_xnni0_llp_debit_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI0_LINK_0_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni0_link_0_flow_u { - mmr_t sh_xnni0_link_0_flow_regval; - struct { - mmr_t debit_vc0_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_force_cred : 1; - mmr_t credit_vc0_test : 7; - mmr_t reserved_1 : 1; - mmr_t credit_vc0_dyn : 7; - mmr_t reserved_2 : 1; - mmr_t credit_vc0_cap : 7; - mmr_t reserved_3 : 33; - } sh_xnni0_link_0_flow_s; -} sh_xnni0_link_0_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI0_LINK_1_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni0_link_1_flow_u { - mmr_t sh_xnni0_link_1_flow_regval; - struct { - mmr_t debit_vc1_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t debit_vc1_force_cred : 1; - mmr_t credit_vc1_test : 7; - mmr_t reserved_1 : 1; - mmr_t credit_vc1_dyn : 7; - mmr_t reserved_2 : 1; - mmr_t credit_vc1_cap : 7; - mmr_t reserved_3 : 33; - } sh_xnni0_link_1_flow_s; -} sh_xnni0_link_1_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI0_LINK_2_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni0_link_2_flow_u { - mmr_t sh_xnni0_link_2_flow_regval; - struct { - mmr_t debit_vc2_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t debit_vc2_force_cred : 1; - mmr_t credit_vc2_test : 7; - mmr_t reserved_1 : 1; - mmr_t credit_vc2_dyn : 7; - mmr_t reserved_2 : 1; - mmr_t credit_vc2_cap : 7; - mmr_t reserved_3 : 33; - } sh_xnni0_link_2_flow_s; -} sh_xnni0_link_2_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI0_LINK_3_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni0_link_3_flow_u { - mmr_t sh_xnni0_link_3_flow_regval; - struct { - mmr_t debit_vc3_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t debit_vc3_force_cred : 1; - mmr_t credit_vc3_test : 7; - mmr_t reserved_1 : 1; - mmr_t credit_vc3_dyn : 7; - mmr_t reserved_2 : 1; - mmr_t credit_vc3_cap : 7; - mmr_t reserved_3 : 33; - } sh_xnni0_link_3_flow_s; -} sh_xnni0_link_3_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI1_LLP_TO_FIFO02_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni1_llp_to_fifo02_flow_u { - mmr_t sh_xnni1_llp_to_fifo02_flow_regval; - struct { - mmr_t debit_vc0_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_force_cred : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_2 : 8; - mmr_t credit_vc0_dyn : 6; - mmr_t reserved_3 : 2; - mmr_t credit_vc0_cap : 6; - mmr_t reserved_4 : 10; - mmr_t credit_vc2_dyn : 6; - mmr_t reserved_5 : 2; - mmr_t credit_vc2_cap : 6; - mmr_t reserved_6 : 2; - } sh_xnni1_llp_to_fifo02_flow_s; -} sh_xnni1_llp_to_fifo02_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI1_LLP_TO_FIFO13_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni1_llp_to_fifo13_flow_u { - mmr_t sh_xnni1_llp_to_fifo13_flow_regval; - struct { - mmr_t debit_vc0_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_force_cred : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_2 : 8; - mmr_t credit_vc0_dyn : 6; - mmr_t reserved_3 : 2; - mmr_t credit_vc0_cap : 6; - mmr_t reserved_4 : 10; - mmr_t credit_vc2_dyn : 6; - mmr_t reserved_5 : 2; - mmr_t credit_vc2_cap : 6; - mmr_t reserved_6 : 2; - } sh_xnni1_llp_to_fifo13_flow_s; -} sh_xnni1_llp_to_fifo13_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI1_LLP_DEBIT_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni1_llp_debit_flow_u { - mmr_t sh_xnni1_llp_debit_flow_regval; - struct { - mmr_t debit_vc0_dyn : 5; - mmr_t reserved_0 : 3; - mmr_t debit_vc0_cap : 5; - mmr_t reserved_1 : 3; - mmr_t debit_vc1_dyn : 5; - mmr_t reserved_2 : 3; - mmr_t debit_vc1_cap : 5; - mmr_t reserved_3 : 3; - mmr_t debit_vc2_dyn : 5; - mmr_t reserved_4 : 3; - mmr_t debit_vc2_cap : 5; - mmr_t reserved_5 : 3; - mmr_t debit_vc3_dyn : 5; - mmr_t reserved_6 : 3; - mmr_t debit_vc3_cap : 5; - mmr_t reserved_7 : 3; - } sh_xnni1_llp_debit_flow_s; -} sh_xnni1_llp_debit_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI1_LINK_0_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni1_link_0_flow_u { - mmr_t sh_xnni1_link_0_flow_regval; - struct { - mmr_t debit_vc0_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_force_cred : 1; - mmr_t credit_vc0_test : 7; - mmr_t reserved_1 : 1; - mmr_t credit_vc0_dyn : 7; - mmr_t reserved_2 : 1; - mmr_t credit_vc0_cap : 7; - mmr_t reserved_3 : 33; - } sh_xnni1_link_0_flow_s; -} sh_xnni1_link_0_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI1_LINK_1_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni1_link_1_flow_u { - mmr_t sh_xnni1_link_1_flow_regval; - struct { - mmr_t debit_vc1_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t debit_vc1_force_cred : 1; - mmr_t credit_vc1_test : 7; - mmr_t reserved_1 : 1; - mmr_t credit_vc1_dyn : 7; - mmr_t reserved_2 : 1; - mmr_t credit_vc1_cap : 7; - mmr_t reserved_3 : 33; - } sh_xnni1_link_1_flow_s; -} sh_xnni1_link_1_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI1_LINK_2_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni1_link_2_flow_u { - mmr_t sh_xnni1_link_2_flow_regval; - struct { - mmr_t debit_vc2_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t debit_vc2_force_cred : 1; - mmr_t credit_vc2_test : 7; - mmr_t reserved_1 : 1; - mmr_t credit_vc2_dyn : 7; - mmr_t reserved_2 : 1; - mmr_t credit_vc2_cap : 7; - mmr_t reserved_3 : 33; - } sh_xnni1_link_2_flow_s; -} sh_xnni1_link_2_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI1_LINK_3_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni1_link_3_flow_u { - mmr_t sh_xnni1_link_3_flow_regval; - struct { - mmr_t debit_vc3_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t debit_vc3_force_cred : 1; - mmr_t credit_vc3_test : 7; - mmr_t reserved_1 : 1; - mmr_t credit_vc3_dyn : 7; - mmr_t reserved_2 : 1; - mmr_t credit_vc3_cap : 7; - mmr_t reserved_3 : 33; - } sh_xnni1_link_3_flow_s; -} sh_xnni1_link_3_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_IILB_LOCAL_TABLE" */ -/* local lookup table */ -/* ==================================================================== */ - -typedef union sh_iilb_local_table_u { - mmr_t sh_iilb_local_table_regval; - struct { - mmr_t dir0 : 4; - mmr_t v0 : 1; - mmr_t ni_sel0 : 1; - mmr_t reserved_0 : 57; - mmr_t valid : 1; - } sh_iilb_local_table_s; -} sh_iilb_local_table_u_t; - -/* ==================================================================== */ -/* Register "SH_IILB_GLOBAL_TABLE" */ -/* global lookup table */ -/* ==================================================================== */ - -typedef union sh_iilb_global_table_u { - mmr_t sh_iilb_global_table_regval; - struct { - mmr_t dir0 : 4; - mmr_t v0 : 1; - mmr_t ni_sel0 : 1; - mmr_t reserved_0 : 57; - mmr_t valid : 1; - } sh_iilb_global_table_s; -} sh_iilb_global_table_u_t; - -/* ==================================================================== */ -/* Register "SH_IILB_OVER_RIDE_TABLE" */ -/* If enabled, bypass the Global/Local tables */ -/* ==================================================================== */ - -typedef union sh_iilb_over_ride_table_u { - mmr_t sh_iilb_over_ride_table_regval; - struct { - mmr_t dir0 : 4; - mmr_t v0 : 1; - mmr_t ni_sel0 : 1; - mmr_t reserved_0 : 57; - mmr_t enable : 1; - } sh_iilb_over_ride_table_s; -} sh_iilb_over_ride_table_u_t; - -/* ==================================================================== */ -/* Register "SH_IILB_RSP_PLANE_HINT" */ -/* If enabled, invert incoming response only plane hint bit before lo */ -/* ==================================================================== */ - -typedef union sh_iilb_rsp_plane_hint_u { - mmr_t sh_iilb_rsp_plane_hint_regval; - struct { - mmr_t reserved_0 : 64; - } sh_iilb_rsp_plane_hint_s; -} sh_iilb_rsp_plane_hint_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_LOCAL_TABLE" */ -/* local lookup table */ -/* ==================================================================== */ - -typedef union sh_pi_local_table_u { - mmr_t sh_pi_local_table_regval; - struct { - mmr_t dir0 : 4; - mmr_t v0 : 1; - mmr_t ni_sel0 : 1; - mmr_t reserved_0 : 2; - mmr_t dir1 : 4; - mmr_t v1 : 1; - mmr_t ni_sel1 : 1; - mmr_t reserved_1 : 49; - mmr_t valid : 1; - } sh_pi_local_table_s; -} sh_pi_local_table_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_GLOBAL_TABLE" */ -/* global lookup table */ -/* ==================================================================== */ - -typedef union sh_pi_global_table_u { - mmr_t sh_pi_global_table_regval; - struct { - mmr_t dir0 : 4; - mmr_t v0 : 1; - mmr_t ni_sel0 : 1; - mmr_t reserved_0 : 2; - mmr_t dir1 : 4; - mmr_t v1 : 1; - mmr_t ni_sel1 : 1; - mmr_t reserved_1 : 49; - mmr_t valid : 1; - } sh_pi_global_table_s; -} sh_pi_global_table_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_OVER_RIDE_TABLE" */ -/* If enabled, bypass the Global/Local tables */ -/* ==================================================================== */ - -typedef union sh_pi_over_ride_table_u { - mmr_t sh_pi_over_ride_table_regval; - struct { - mmr_t dir0 : 4; - mmr_t v0 : 1; - mmr_t ni_sel0 : 1; - mmr_t reserved_0 : 2; - mmr_t dir1 : 4; - mmr_t v1 : 1; - mmr_t ni_sel1 : 1; - mmr_t reserved_1 : 49; - mmr_t enable : 1; - } sh_pi_over_ride_table_s; -} sh_pi_over_ride_table_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_RSP_PLANE_HINT" */ -/* If enabled, invert incoming response only plane hint bit before lo */ -/* ==================================================================== */ - -typedef union sh_pi_rsp_plane_hint_u { - mmr_t sh_pi_rsp_plane_hint_regval; - struct { - mmr_t invert : 1; - mmr_t reserved_0 : 63; - } sh_pi_rsp_plane_hint_s; -} sh_pi_rsp_plane_hint_u_t; - -/* ==================================================================== */ -/* Register "SH_NI0_LOCAL_TABLE" */ -/* local lookup table */ -/* ==================================================================== */ - -typedef union sh_ni0_local_table_u { - mmr_t sh_ni0_local_table_regval; - struct { - mmr_t dir0 : 4; - mmr_t v0 : 1; - mmr_t reserved_0 : 58; - mmr_t valid : 1; - } sh_ni0_local_table_s; -} sh_ni0_local_table_u_t; - -/* ==================================================================== */ -/* Register "SH_NI0_GLOBAL_TABLE" */ -/* global lookup table */ -/* ==================================================================== */ - -typedef union sh_ni0_global_table_u { - mmr_t sh_ni0_global_table_regval; - struct { - mmr_t dir0 : 4; - mmr_t v0 : 1; - mmr_t reserved_0 : 58; - mmr_t valid : 1; - } sh_ni0_global_table_s; -} sh_ni0_global_table_u_t; - -/* ==================================================================== */ -/* Register "SH_NI0_OVER_RIDE_TABLE" */ -/* If enabled, bypass the Global/Local tables */ -/* ==================================================================== */ - -typedef union sh_ni0_over_ride_table_u { - mmr_t sh_ni0_over_ride_table_regval; - struct { - mmr_t dir0 : 4; - mmr_t v0 : 1; - mmr_t reserved_0 : 58; - mmr_t enable : 1; - } sh_ni0_over_ride_table_s; -} sh_ni0_over_ride_table_u_t; - -/* ==================================================================== */ -/* Register "SH_NI0_RSP_PLANE_HINT" */ -/* If enabled, invert incoming response only plane hint bit before lo */ -/* ==================================================================== */ - -typedef union sh_ni0_rsp_plane_hint_u { - mmr_t sh_ni0_rsp_plane_hint_regval; - struct { - mmr_t reserved_0 : 64; - } sh_ni0_rsp_plane_hint_s; -} sh_ni0_rsp_plane_hint_u_t; - -/* ==================================================================== */ -/* Register "SH_NI1_LOCAL_TABLE" */ -/* local lookup table */ -/* ==================================================================== */ - -typedef union sh_ni1_local_table_u { - mmr_t sh_ni1_local_table_regval; - struct { - mmr_t dir0 : 4; - mmr_t v0 : 1; - mmr_t reserved_0 : 58; - mmr_t valid : 1; - } sh_ni1_local_table_s; -} sh_ni1_local_table_u_t; - -/* ==================================================================== */ -/* Register "SH_NI1_GLOBAL_TABLE" */ -/* global lookup table */ -/* ==================================================================== */ - -typedef union sh_ni1_global_table_u { - mmr_t sh_ni1_global_table_regval; - struct { - mmr_t dir0 : 4; - mmr_t v0 : 1; - mmr_t reserved_0 : 58; - mmr_t valid : 1; - } sh_ni1_global_table_s; -} sh_ni1_global_table_u_t; - -/* ==================================================================== */ -/* Register "SH_NI1_OVER_RIDE_TABLE" */ -/* If enabled, bypass the Global/Local tables */ -/* ==================================================================== */ - -typedef union sh_ni1_over_ride_table_u { - mmr_t sh_ni1_over_ride_table_regval; - struct { - mmr_t dir0 : 4; - mmr_t v0 : 1; - mmr_t reserved_0 : 58; - mmr_t enable : 1; - } sh_ni1_over_ride_table_s; -} sh_ni1_over_ride_table_u_t; - -/* ==================================================================== */ -/* Register "SH_NI1_RSP_PLANE_HINT" */ -/* If enabled, invert incoming response only plane hint bit before lo */ -/* ==================================================================== */ - -typedef union sh_ni1_rsp_plane_hint_u { - mmr_t sh_ni1_rsp_plane_hint_regval; - struct { - mmr_t reserved_0 : 64; - } sh_ni1_rsp_plane_hint_s; -} sh_ni1_rsp_plane_hint_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_LOCAL_TABLE" */ -/* local lookup table */ -/* ==================================================================== */ - -typedef union sh_md_local_table_u { - mmr_t sh_md_local_table_regval; - struct { - mmr_t dir0 : 4; - mmr_t v0 : 1; - mmr_t ni_sel0 : 1; - mmr_t reserved_0 : 2; - mmr_t dir1 : 4; - mmr_t v1 : 1; - mmr_t ni_sel1 : 1; - mmr_t reserved_1 : 49; - mmr_t valid : 1; - } sh_md_local_table_s; -} sh_md_local_table_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_GLOBAL_TABLE" */ -/* global lookup table */ -/* ==================================================================== */ - -typedef union sh_md_global_table_u { - mmr_t sh_md_global_table_regval; - struct { - mmr_t dir0 : 4; - mmr_t v0 : 1; - mmr_t ni_sel0 : 1; - mmr_t reserved_0 : 2; - mmr_t dir1 : 4; - mmr_t v1 : 1; - mmr_t ni_sel1 : 1; - mmr_t reserved_1 : 49; - mmr_t valid : 1; - } sh_md_global_table_s; -} sh_md_global_table_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_OVER_RIDE_TABLE" */ -/* If enabled, bypass the Global/Local tables */ -/* ==================================================================== */ - -typedef union sh_md_over_ride_table_u { - mmr_t sh_md_over_ride_table_regval; - struct { - mmr_t dir0 : 4; - mmr_t v0 : 1; - mmr_t ni_sel0 : 1; - mmr_t reserved_0 : 2; - mmr_t dir1 : 4; - mmr_t v1 : 1; - mmr_t ni_sel1 : 1; - mmr_t reserved_1 : 49; - mmr_t enable : 1; - } sh_md_over_ride_table_s; -} sh_md_over_ride_table_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_RSP_PLANE_HINT" */ -/* If enabled, invert incoming response only plane hint bit before lo */ -/* ==================================================================== */ - -typedef union sh_md_rsp_plane_hint_u { - mmr_t sh_md_rsp_plane_hint_regval; - struct { - mmr_t invert : 1; - mmr_t reserved_0 : 63; - } sh_md_rsp_plane_hint_s; -} sh_md_rsp_plane_hint_u_t; - -/* ==================================================================== */ -/* Register "SH_LB_LIQ_CTL" */ -/* Local Block LIQ Control */ -/* ==================================================================== */ - -typedef union sh_lb_liq_ctl_u { - mmr_t sh_lb_liq_ctl_regval; - struct { - mmr_t liq_req_ctl : 5; - mmr_t reserved_0 : 3; - mmr_t liq_rpl_ctl : 4; - mmr_t reserved_1 : 4; - mmr_t force_rq_credit : 1; - mmr_t force_rp_credit : 1; - mmr_t force_linvv_credit : 1; - mmr_t reserved_2 : 45; - } sh_lb_liq_ctl_s; -} sh_lb_liq_ctl_u_t; - -/* ==================================================================== */ -/* Register "SH_LB_LOQ_CTL" */ -/* Local Block LOQ Control */ -/* ==================================================================== */ - -typedef union sh_lb_loq_ctl_u { - mmr_t sh_lb_loq_ctl_regval; - struct { - mmr_t loq_req_ctl : 1; - mmr_t loq_rpl_ctl : 1; - mmr_t reserved_0 : 62; - } sh_lb_loq_ctl_s; -} sh_lb_loq_ctl_u_t; - -/* ==================================================================== */ -/* Register "SH_LB_MAX_REP_CREDIT_CNT" */ -/* Maximum number of reply credits from XN */ -/* ==================================================================== */ - -typedef union sh_lb_max_rep_credit_cnt_u { - mmr_t sh_lb_max_rep_credit_cnt_regval; - struct { - mmr_t max_cnt : 5; - mmr_t reserved_0 : 59; - } sh_lb_max_rep_credit_cnt_s; -} sh_lb_max_rep_credit_cnt_u_t; - -/* ==================================================================== */ -/* Register "SH_LB_MAX_REQ_CREDIT_CNT" */ -/* Maximum number of request credits from XN */ -/* ==================================================================== */ - -typedef union sh_lb_max_req_credit_cnt_u { - mmr_t sh_lb_max_req_credit_cnt_regval; - struct { - mmr_t max_cnt : 5; - mmr_t reserved_0 : 59; - } sh_lb_max_req_credit_cnt_s; -} sh_lb_max_req_credit_cnt_u_t; - -/* ==================================================================== */ -/* Register "SH_PIO_TIME_OUT" */ -/* Local Block PIO time out value */ -/* ==================================================================== */ - -typedef union sh_pio_time_out_u { - mmr_t sh_pio_time_out_regval; - struct { - mmr_t value : 16; - mmr_t reserved_0 : 48; - } sh_pio_time_out_s; -} sh_pio_time_out_u_t; - -/* ==================================================================== */ -/* Register "SH_PIO_NACK_RESET" */ -/* Local Block PIO Reset for nack counters */ -/* ==================================================================== */ - -typedef union sh_pio_nack_reset_u { - mmr_t sh_pio_nack_reset_regval; - struct { - mmr_t pulse : 1; - mmr_t reserved_0 : 63; - } sh_pio_nack_reset_s; -} sh_pio_nack_reset_u_t; - -/* ==================================================================== */ -/* Register "SH_CONVEYOR_BELT_TIME_OUT" */ -/* Local Block conveyor belt time out value */ -/* ==================================================================== */ - -typedef union sh_conveyor_belt_time_out_u { - mmr_t sh_conveyor_belt_time_out_regval; - struct { - mmr_t value : 12; - mmr_t reserved_0 : 52; - } sh_conveyor_belt_time_out_s; -} sh_conveyor_belt_time_out_u_t; - -/* ==================================================================== */ -/* Register "SH_LB_CREDIT_STATUS" */ -/* Credit Counter Status Register */ -/* ==================================================================== */ - -typedef union sh_lb_credit_status_u { - mmr_t sh_lb_credit_status_regval; - struct { - mmr_t liq_rq_credit : 5; - mmr_t reserved_0 : 1; - mmr_t liq_rp_credit : 4; - mmr_t reserved_1 : 2; - mmr_t linvv_credit : 6; - mmr_t loq_rq_credit : 5; - mmr_t loq_rp_credit : 5; - mmr_t reserved_2 : 36; - } sh_lb_credit_status_s; -} sh_lb_credit_status_u_t; - -/* ==================================================================== */ -/* Register "SH_LB_DEBUG_LOCAL_SEL" */ -/* LB Debug Port Select */ -/* ==================================================================== */ - -typedef union sh_lb_debug_local_sel_u { - mmr_t sh_lb_debug_local_sel_regval; - struct { - mmr_t nibble0_chiplet_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble1_chiplet_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble2_chiplet_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble3_chiplet_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble4_chiplet_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble5_chiplet_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble6_chiplet_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble7_chiplet_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t trigger_enable : 1; - } sh_lb_debug_local_sel_s; -} sh_lb_debug_local_sel_u_t; - -/* ==================================================================== */ -/* Register "SH_LB_DEBUG_PERF_SEL" */ -/* LB Debug Port Performance Select */ -/* ==================================================================== */ - -typedef union sh_lb_debug_perf_sel_u { - mmr_t sh_lb_debug_perf_sel_regval; - struct { - mmr_t nibble0_chiplet_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble1_chiplet_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble2_chiplet_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble3_chiplet_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble4_chiplet_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble5_chiplet_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble6_chiplet_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble7_chiplet_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t reserved_15 : 1; - } sh_lb_debug_perf_sel_s; -} sh_lb_debug_perf_sel_u_t; - -/* ==================================================================== */ -/* Register "SH_LB_DEBUG_TRIG_SEL" */ -/* LB Debug Trigger Select */ -/* ==================================================================== */ - -typedef union sh_lb_debug_trig_sel_u { - mmr_t sh_lb_debug_trig_sel_regval; - struct { - mmr_t trigger0_chiplet_sel : 3; - mmr_t reserved_0 : 1; - mmr_t trigger0_nibble_sel : 3; - mmr_t reserved_1 : 1; - mmr_t trigger1_chiplet_sel : 3; - mmr_t reserved_2 : 1; - mmr_t trigger1_nibble_sel : 3; - mmr_t reserved_3 : 1; - mmr_t trigger2_chiplet_sel : 3; - mmr_t reserved_4 : 1; - mmr_t trigger2_nibble_sel : 3; - mmr_t reserved_5 : 1; - mmr_t trigger3_chiplet_sel : 3; - mmr_t reserved_6 : 1; - mmr_t trigger3_nibble_sel : 3; - mmr_t reserved_7 : 1; - mmr_t trigger4_chiplet_sel : 3; - mmr_t reserved_8 : 1; - mmr_t trigger4_nibble_sel : 3; - mmr_t reserved_9 : 1; - mmr_t trigger5_chiplet_sel : 3; - mmr_t reserved_10 : 1; - mmr_t trigger5_nibble_sel : 3; - mmr_t reserved_11 : 1; - mmr_t trigger6_chiplet_sel : 3; - mmr_t reserved_12 : 1; - mmr_t trigger6_nibble_sel : 3; - mmr_t reserved_13 : 1; - mmr_t trigger7_chiplet_sel : 3; - mmr_t reserved_14 : 1; - mmr_t trigger7_nibble_sel : 3; - mmr_t reserved_15 : 1; - } sh_lb_debug_trig_sel_s; -} sh_lb_debug_trig_sel_u_t; - -/* ==================================================================== */ -/* Register "SH_LB_ERROR_DETAIL_1" */ -/* LB Error capture information: HDR1 */ -/* ==================================================================== */ - -typedef union sh_lb_error_detail_1_u { - mmr_t sh_lb_error_detail_1_regval; - struct { - mmr_t command : 8; - mmr_t suppl : 14; - mmr_t reserved_0 : 2; - mmr_t source : 14; - mmr_t reserved_1 : 2; - mmr_t dest : 3; - mmr_t reserved_2 : 5; - mmr_t hdr_err : 1; - mmr_t data_err : 1; - mmr_t reserved_3 : 13; - mmr_t valid : 1; - } sh_lb_error_detail_1_s; -} sh_lb_error_detail_1_u_t; - -/* ==================================================================== */ -/* Register "SH_LB_ERROR_DETAIL_2" */ -/* LB Error Bits */ -/* ==================================================================== */ - -typedef union sh_lb_error_detail_2_u { - mmr_t sh_lb_error_detail_2_regval; - struct { - mmr_t address : 47; - mmr_t reserved_0 : 17; - } sh_lb_error_detail_2_s; -} sh_lb_error_detail_2_u_t; - -/* ==================================================================== */ -/* Register "SH_LB_ERROR_DETAIL_3" */ -/* LB Error Bits */ -/* ==================================================================== */ - -typedef union sh_lb_error_detail_3_u { - mmr_t sh_lb_error_detail_3_regval; - struct { - mmr_t data : 64; - } sh_lb_error_detail_3_s; -} sh_lb_error_detail_3_u_t; - -/* ==================================================================== */ -/* Register "SH_LB_ERROR_DETAIL_4" */ -/* LB Error Bits */ -/* ==================================================================== */ - -typedef union sh_lb_error_detail_4_u { - mmr_t sh_lb_error_detail_4_regval; - struct { - mmr_t route : 64; - } sh_lb_error_detail_4_s; -} sh_lb_error_detail_4_u_t; - -/* ==================================================================== */ -/* Register "SH_LB_ERROR_DETAIL_5" */ -/* LB Error Bits */ -/* ==================================================================== */ - -typedef union sh_lb_error_detail_5_u { - mmr_t sh_lb_error_detail_5_regval; - struct { - mmr_t read_retry : 1; - mmr_t ptc1_write : 1; - mmr_t write_retry : 1; - mmr_t count_a_overflow : 1; - mmr_t count_b_overflow : 1; - mmr_t nack_a_timeout : 1; - mmr_t nack_b_timeout : 1; - mmr_t reserved_0 : 57; - } sh_lb_error_detail_5_s; -} sh_lb_error_detail_5_u_t; - -/* ==================================================================== */ -/* Register "SH_LB_ERROR_MASK" */ -/* LB Error Mask */ -/* ==================================================================== */ - -typedef union sh_lb_error_mask_u { - mmr_t sh_lb_error_mask_regval; - struct { - mmr_t rq_bad_cmd : 1; - mmr_t rp_bad_cmd : 1; - mmr_t rq_short : 1; - mmr_t rp_short : 1; - mmr_t rq_long : 1; - mmr_t rp_long : 1; - mmr_t rq_bad_data : 1; - mmr_t rp_bad_data : 1; - mmr_t rq_bad_addr : 1; - mmr_t rq_time_out : 1; - mmr_t linvv_overflow : 1; - mmr_t unexpected_linv : 1; - mmr_t ptc_1_timeout : 1; - mmr_t junk_bus_err : 1; - mmr_t pio_cb_err : 1; - mmr_t vector_rq_route_error : 1; - mmr_t vector_rp_route_error : 1; - mmr_t gclk_drop : 1; - mmr_t rq_fifo_error : 1; - mmr_t rp_fifo_error : 1; - mmr_t unexp_valid : 1; - mmr_t rq_credit_overflow : 1; - mmr_t rp_credit_overflow : 1; - mmr_t reserved_0 : 41; - } sh_lb_error_mask_s; -} sh_lb_error_mask_u_t; - -/* ==================================================================== */ -/* Register "SH_LB_ERROR_OVERFLOW" */ -/* LB Error Overflow */ -/* ==================================================================== */ - -typedef union sh_lb_error_overflow_u { - mmr_t sh_lb_error_overflow_regval; - struct { - mmr_t rq_bad_cmd_ovrfl : 1; - mmr_t rp_bad_cmd_ovrfl : 1; - mmr_t rq_short_ovrfl : 1; - mmr_t rp_short_ovrfl : 1; - mmr_t rq_long_ovrfl : 1; - mmr_t rp_long_ovrfl : 1; - mmr_t rq_bad_data_ovrfl : 1; - mmr_t rp_bad_data_ovrfl : 1; - mmr_t rq_bad_addr_ovrfl : 1; - mmr_t rq_time_out_ovrfl : 1; - mmr_t linvv_overflow_ovrfl : 1; - mmr_t unexpected_linv_ovrfl : 1; - mmr_t ptc_1_timeout_ovrfl : 1; - mmr_t junk_bus_err_ovrfl : 1; - mmr_t pio_cb_err_ovrfl : 1; - mmr_t vector_rq_route_error_ovrfl : 1; - mmr_t vector_rp_route_error_ovrfl : 1; - mmr_t gclk_drop_ovrfl : 1; - mmr_t rq_fifo_error_ovrfl : 1; - mmr_t rp_fifo_error_ovrfl : 1; - mmr_t unexp_valid_ovrfl : 1; - mmr_t rq_credit_overflow_ovrfl : 1; - mmr_t rp_credit_overflow_ovrfl : 1; - mmr_t reserved_0 : 41; - } sh_lb_error_overflow_s; -} sh_lb_error_overflow_u_t; - -/* ==================================================================== */ -/* Register "SH_LB_ERROR_SUMMARY" */ -/* LB Error Bits */ -/* ==================================================================== */ - -typedef union sh_lb_error_summary_u { - mmr_t sh_lb_error_summary_regval; - struct { - mmr_t rq_bad_cmd : 1; - mmr_t rp_bad_cmd : 1; - mmr_t rq_short : 1; - mmr_t rp_short : 1; - mmr_t rq_long : 1; - mmr_t rp_long : 1; - mmr_t rq_bad_data : 1; - mmr_t rp_bad_data : 1; - mmr_t rq_bad_addr : 1; - mmr_t rq_time_out : 1; - mmr_t linvv_overflow : 1; - mmr_t unexpected_linv : 1; - mmr_t ptc_1_timeout : 1; - mmr_t junk_bus_err : 1; - mmr_t pio_cb_err : 1; - mmr_t vector_rq_route_error : 1; - mmr_t vector_rp_route_error : 1; - mmr_t gclk_drop : 1; - mmr_t rq_fifo_error : 1; - mmr_t rp_fifo_error : 1; - mmr_t unexp_valid : 1; - mmr_t rq_credit_overflow : 1; - mmr_t rp_credit_overflow : 1; - mmr_t reserved_0 : 41; - } sh_lb_error_summary_s; -} sh_lb_error_summary_u_t; - -/* ==================================================================== */ -/* Register "SH_LB_FIRST_ERROR" */ -/* LB First Error */ -/* ==================================================================== */ - -typedef union sh_lb_first_error_u { - mmr_t sh_lb_first_error_regval; - struct { - mmr_t rq_bad_cmd : 1; - mmr_t rp_bad_cmd : 1; - mmr_t rq_short : 1; - mmr_t rp_short : 1; - mmr_t rq_long : 1; - mmr_t rp_long : 1; - mmr_t rq_bad_data : 1; - mmr_t rp_bad_data : 1; - mmr_t rq_bad_addr : 1; - mmr_t rq_time_out : 1; - mmr_t linvv_overflow : 1; - mmr_t unexpected_linv : 1; - mmr_t ptc_1_timeout : 1; - mmr_t junk_bus_err : 1; - mmr_t pio_cb_err : 1; - mmr_t vector_rq_route_error : 1; - mmr_t vector_rp_route_error : 1; - mmr_t gclk_drop : 1; - mmr_t rq_fifo_error : 1; - mmr_t rp_fifo_error : 1; - mmr_t unexp_valid : 1; - mmr_t rq_credit_overflow : 1; - mmr_t rp_credit_overflow : 1; - mmr_t reserved_0 : 41; - } sh_lb_first_error_s; -} sh_lb_first_error_u_t; - -/* ==================================================================== */ -/* Register "SH_LB_LAST_CREDIT" */ -/* Credit counter status register */ -/* ==================================================================== */ - -typedef union sh_lb_last_credit_u { - mmr_t sh_lb_last_credit_regval; - struct { - mmr_t liq_rq_credit : 5; - mmr_t reserved_0 : 1; - mmr_t liq_rp_credit : 4; - mmr_t reserved_1 : 2; - mmr_t linvv_credit : 6; - mmr_t loq_rq_credit : 5; - mmr_t loq_rp_credit : 5; - mmr_t reserved_2 : 36; - } sh_lb_last_credit_s; -} sh_lb_last_credit_u_t; - -/* ==================================================================== */ -/* Register "SH_LB_NACK_STATUS" */ -/* Nack Counter Status Register */ -/* ==================================================================== */ - -typedef union sh_lb_nack_status_u { - mmr_t sh_lb_nack_status_regval; - struct { - mmr_t pio_nack_a : 12; - mmr_t reserved_0 : 4; - mmr_t pio_nack_b : 12; - mmr_t reserved_1 : 4; - mmr_t junk_nack : 16; - mmr_t cb_timeout_count : 12; - mmr_t cb_state : 2; - mmr_t reserved_2 : 2; - } sh_lb_nack_status_s; -} sh_lb_nack_status_u_t; - -/* ==================================================================== */ -/* Register "SH_LB_TRIGGER_COMPARE" */ -/* LB Test-point Trigger Compare */ -/* ==================================================================== */ - -typedef union sh_lb_trigger_compare_u { - mmr_t sh_lb_trigger_compare_regval; - struct { - mmr_t mask : 32; - mmr_t reserved_0 : 32; - } sh_lb_trigger_compare_s; -} sh_lb_trigger_compare_u_t; - -/* ==================================================================== */ -/* Register "SH_LB_TRIGGER_DATA" */ -/* LB Test-point Trigger Compare Data */ -/* ==================================================================== */ - -typedef union sh_lb_trigger_data_u { - mmr_t sh_lb_trigger_data_regval; - struct { - mmr_t compare_pattern : 32; - mmr_t reserved_0 : 32; - } sh_lb_trigger_data_s; -} sh_lb_trigger_data_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_AEC_CONFIG" */ -/* PI Adaptive Error Correction Configuration */ -/* ==================================================================== */ - -typedef union sh_pi_aec_config_u { - mmr_t sh_pi_aec_config_regval; - struct { - mmr_t mode : 3; - mmr_t reserved_0 : 61; - } sh_pi_aec_config_s; -} sh_pi_aec_config_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_AFI_ERROR_MASK" */ -/* PI AFI Error Mask */ -/* ==================================================================== */ - -typedef union sh_pi_afi_error_mask_u { - mmr_t sh_pi_afi_error_mask_regval; - struct { - mmr_t reserved_0 : 21; - mmr_t hung_bus : 1; - mmr_t rsp_parity : 1; - mmr_t ioq_overrun : 1; - mmr_t req_format : 1; - mmr_t addr_access : 1; - mmr_t req_parity : 1; - mmr_t addr_parity : 1; - mmr_t shub_fsb_dqe : 1; - mmr_t shub_fsb_uce : 1; - mmr_t shub_fsb_ce : 1; - mmr_t livelock : 1; - mmr_t bad_snoop : 1; - mmr_t fsb_tbl_miss : 1; - mmr_t msg_len : 1; - mmr_t reserved_1 : 29; - } sh_pi_afi_error_mask_s; -} sh_pi_afi_error_mask_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_AFI_TEST_POINT_COMPARE" */ -/* PI AFI Test Point Compare */ -/* ==================================================================== */ - -typedef union sh_pi_afi_test_point_compare_u { - mmr_t sh_pi_afi_test_point_compare_regval; - struct { - mmr_t compare_mask : 32; - mmr_t compare_pattern : 32; - } sh_pi_afi_test_point_compare_s; -} sh_pi_afi_test_point_compare_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_AFI_TEST_POINT_SELECT" */ -/* PI AFI Test Point Select */ -/* ==================================================================== */ - -typedef union sh_pi_afi_test_point_select_u { - mmr_t sh_pi_afi_test_point_select_regval; - struct { - mmr_t nibble0_chiplet_sel : 4; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble1_chiplet_sel : 4; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble2_chiplet_sel : 4; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble3_chiplet_sel : 4; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble4_chiplet_sel : 4; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble5_chiplet_sel : 4; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble6_chiplet_sel : 4; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble7_chiplet_sel : 4; - mmr_t nibble7_nibble_sel : 3; - mmr_t trigger_enable : 1; - } sh_pi_afi_test_point_select_s; -} sh_pi_afi_test_point_select_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_AFI_TEST_POINT_TRIGGER_SELECT" */ -/* PI CRBC Test Point Trigger Select */ -/* ==================================================================== */ - -typedef union sh_pi_afi_test_point_trigger_select_u { - mmr_t sh_pi_afi_test_point_trigger_select_regval; - struct { - mmr_t trigger0_chiplet_sel : 4; - mmr_t trigger0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t trigger1_chiplet_sel : 4; - mmr_t trigger1_nibble_sel : 3; - mmr_t reserved_1 : 1; - mmr_t trigger2_chiplet_sel : 4; - mmr_t trigger2_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t trigger3_chiplet_sel : 4; - mmr_t trigger3_nibble_sel : 3; - mmr_t reserved_3 : 1; - mmr_t trigger4_chiplet_sel : 4; - mmr_t trigger4_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t trigger5_chiplet_sel : 4; - mmr_t trigger5_nibble_sel : 3; - mmr_t reserved_5 : 1; - mmr_t trigger6_chiplet_sel : 4; - mmr_t trigger6_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t trigger7_chiplet_sel : 4; - mmr_t trigger7_nibble_sel : 3; - mmr_t reserved_7 : 1; - } sh_pi_afi_test_point_trigger_select_s; -} sh_pi_afi_test_point_trigger_select_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_AUTO_REPLY_ENABLE" */ -/* PI Auto Reply Enable */ -/* ==================================================================== */ - -typedef union sh_pi_auto_reply_enable_u { - mmr_t sh_pi_auto_reply_enable_regval; - struct { - mmr_t auto_reply_enable : 1; - mmr_t reserved_0 : 63; - } sh_pi_auto_reply_enable_s; -} sh_pi_auto_reply_enable_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_CAM_CONTROL" */ -/* CRB CAM MMR Access Control */ -/* ==================================================================== */ - -typedef union sh_pi_cam_control_u { - mmr_t sh_pi_cam_control_regval; - struct { - mmr_t cam_indx : 7; - mmr_t reserved_0 : 1; - mmr_t cam_write : 1; - mmr_t rrb_rd_xfer_clear : 1; - mmr_t reserved_1 : 53; - mmr_t start : 1; - } sh_pi_cam_control_s; -} sh_pi_cam_control_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_CRBC_TEST_POINT_COMPARE" */ -/* PI CRBC Test Point Compare */ -/* ==================================================================== */ - -typedef union sh_pi_crbc_test_point_compare_u { - mmr_t sh_pi_crbc_test_point_compare_regval; - struct { - mmr_t compare_mask : 32; - mmr_t compare_pattern : 32; - } sh_pi_crbc_test_point_compare_s; -} sh_pi_crbc_test_point_compare_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_CRBC_TEST_POINT_SELECT" */ -/* PI CRBC Test Point Select */ -/* ==================================================================== */ - -typedef union sh_pi_crbc_test_point_select_u { - mmr_t sh_pi_crbc_test_point_select_regval; - struct { - mmr_t nibble0_chiplet_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble1_chiplet_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble2_chiplet_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble3_chiplet_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble4_chiplet_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble5_chiplet_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble6_chiplet_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble7_chiplet_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t trigger_enable : 1; - } sh_pi_crbc_test_point_select_s; -} sh_pi_crbc_test_point_select_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT" */ -/* PI CRBC Test Point Trigger Select */ -/* ==================================================================== */ - -typedef union sh_pi_crbc_test_point_trigger_select_u { - mmr_t sh_pi_crbc_test_point_trigger_select_regval; - struct { - mmr_t trigger0_chiplet_sel : 3; - mmr_t reserved_0 : 1; - mmr_t trigger0_nibble_sel : 3; - mmr_t reserved_1 : 1; - mmr_t trigger1_chiplet_sel : 3; - mmr_t reserved_2 : 1; - mmr_t trigger1_nibble_sel : 3; - mmr_t reserved_3 : 1; - mmr_t trigger2_chiplet_sel : 3; - mmr_t reserved_4 : 1; - mmr_t trigger2_nibble_sel : 3; - mmr_t reserved_5 : 1; - mmr_t trigger3_chiplet_sel : 3; - mmr_t reserved_6 : 1; - mmr_t trigger3_nibble_sel : 3; - mmr_t reserved_7 : 1; - mmr_t trigger4_chiplet_sel : 3; - mmr_t reserved_8 : 1; - mmr_t trigger4_nibble_sel : 3; - mmr_t reserved_9 : 1; - mmr_t trigger5_chiplet_sel : 3; - mmr_t reserved_10 : 1; - mmr_t trigger5_nibble_sel : 3; - mmr_t reserved_11 : 1; - mmr_t trigger6_chiplet_sel : 3; - mmr_t reserved_12 : 1; - mmr_t trigger6_nibble_sel : 3; - mmr_t reserved_13 : 1; - mmr_t trigger7_chiplet_sel : 3; - mmr_t reserved_14 : 1; - mmr_t trigger7_nibble_sel : 3; - mmr_t reserved_15 : 1; - } sh_pi_crbc_test_point_trigger_select_s; -} sh_pi_crbc_test_point_trigger_select_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_ERROR_MASK" */ -/* PI CRBP Error Mask */ -/* ==================================================================== */ - -typedef union sh_pi_crbp_error_mask_u { - mmr_t sh_pi_crbp_error_mask_regval; - struct { - mmr_t fsb_proto_err : 1; - mmr_t gfx_rp_err : 1; - mmr_t xb_proto_err : 1; - mmr_t mem_rp_err : 1; - mmr_t pio_rp_err : 1; - mmr_t mem_to_err : 1; - mmr_t pio_to_err : 1; - mmr_t fsb_shub_uce : 1; - mmr_t fsb_shub_ce : 1; - mmr_t msg_color_err : 1; - mmr_t md_rq_q_oflow : 1; - mmr_t md_rp_q_oflow : 1; - mmr_t xn_rq_q_oflow : 1; - mmr_t xn_rp_q_oflow : 1; - mmr_t nack_oflow : 1; - mmr_t gfx_int_0 : 1; - mmr_t gfx_int_1 : 1; - mmr_t md_rq_crd_oflow : 1; - mmr_t md_rp_crd_oflow : 1; - mmr_t xn_rq_crd_oflow : 1; - mmr_t xn_rp_crd_oflow : 1; - mmr_t reserved_0 : 43; - } sh_pi_crbp_error_mask_s; -} sh_pi_crbp_error_mask_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_FSB_PIPE_COMPARE" */ -/* CRBP FSB Pipe Compare */ -/* ==================================================================== */ - -typedef union sh_pi_crbp_fsb_pipe_compare_u { - mmr_t sh_pi_crbp_fsb_pipe_compare_regval; - struct { - mmr_t compare_address : 47; - mmr_t compare_req : 6; - mmr_t reserved_0 : 11; - } sh_pi_crbp_fsb_pipe_compare_s; -} sh_pi_crbp_fsb_pipe_compare_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_FSB_PIPE_MASK" */ -/* CRBP Compare Mask */ -/* ==================================================================== */ - -typedef union sh_pi_crbp_fsb_pipe_mask_u { - mmr_t sh_pi_crbp_fsb_pipe_mask_regval; - struct { - mmr_t compare_address_mask : 47; - mmr_t compare_req_mask : 6; - mmr_t reserved_0 : 11; - } sh_pi_crbp_fsb_pipe_mask_s; -} sh_pi_crbp_fsb_pipe_mask_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_TEST_POINT_COMPARE" */ -/* PI CRBP Test Point Compare */ -/* ==================================================================== */ - -typedef union sh_pi_crbp_test_point_compare_u { - mmr_t sh_pi_crbp_test_point_compare_regval; - struct { - mmr_t compare_mask : 32; - mmr_t compare_pattern : 32; - } sh_pi_crbp_test_point_compare_s; -} sh_pi_crbp_test_point_compare_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_TEST_POINT_SELECT" */ -/* PI CRBP Test Point Select */ -/* ==================================================================== */ - -typedef union sh_pi_crbp_test_point_select_u { - mmr_t sh_pi_crbp_test_point_select_regval; - struct { - mmr_t nibble0_chiplet_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble1_chiplet_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble2_chiplet_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble3_chiplet_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble4_chiplet_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble5_chiplet_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble6_chiplet_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble7_chiplet_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t trigger_enable : 1; - } sh_pi_crbp_test_point_select_s; -} sh_pi_crbp_test_point_select_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT" */ -/* PI CRBP Test Point Trigger Select */ -/* ==================================================================== */ - -typedef union sh_pi_crbp_test_point_trigger_select_u { - mmr_t sh_pi_crbp_test_point_trigger_select_regval; - struct { - mmr_t trigger0_chiplet_sel : 3; - mmr_t reserved_0 : 1; - mmr_t trigger0_nibble_sel : 3; - mmr_t reserved_1 : 1; - mmr_t trigger1_chiplet_sel : 3; - mmr_t reserved_2 : 1; - mmr_t trigger1_nibble_sel : 3; - mmr_t reserved_3 : 1; - mmr_t trigger2_chiplet_sel : 3; - mmr_t reserved_4 : 1; - mmr_t trigger2_nibble_sel : 3; - mmr_t reserved_5 : 1; - mmr_t trigger3_chiplet_sel : 3; - mmr_t reserved_6 : 1; - mmr_t trigger3_nibble_sel : 3; - mmr_t reserved_7 : 1; - mmr_t trigger4_chiplet_sel : 3; - mmr_t reserved_8 : 1; - mmr_t trigger4_nibble_sel : 3; - mmr_t reserved_9 : 1; - mmr_t trigger5_chiplet_sel : 3; - mmr_t reserved_10 : 1; - mmr_t trigger5_nibble_sel : 3; - mmr_t reserved_11 : 1; - mmr_t trigger6_chiplet_sel : 3; - mmr_t reserved_12 : 1; - mmr_t trigger6_nibble_sel : 3; - mmr_t reserved_13 : 1; - mmr_t trigger7_chiplet_sel : 3; - mmr_t reserved_14 : 1; - mmr_t trigger7_nibble_sel : 3; - mmr_t reserved_15 : 1; - } sh_pi_crbp_test_point_trigger_select_s; -} sh_pi_crbp_test_point_trigger_select_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_XB_PIPE_COMPARE_0" */ -/* CRBP XB Pipe Compare */ -/* ==================================================================== */ - -typedef union sh_pi_crbp_xb_pipe_compare_0_u { - mmr_t sh_pi_crbp_xb_pipe_compare_0_regval; - struct { - mmr_t compare_address : 47; - mmr_t compare_command : 8; - mmr_t reserved_0 : 9; - } sh_pi_crbp_xb_pipe_compare_0_s; -} sh_pi_crbp_xb_pipe_compare_0_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_XB_PIPE_COMPARE_1" */ -/* CRBP XB Pipe Compare */ -/* ==================================================================== */ - -typedef union sh_pi_crbp_xb_pipe_compare_1_u { - mmr_t sh_pi_crbp_xb_pipe_compare_1_regval; - struct { - mmr_t compare_source : 14; - mmr_t reserved_0 : 2; - mmr_t compare_supplemental : 14; - mmr_t reserved_1 : 2; - mmr_t compare_echo : 9; - mmr_t reserved_2 : 23; - } sh_pi_crbp_xb_pipe_compare_1_s; -} sh_pi_crbp_xb_pipe_compare_1_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_XB_PIPE_MASK_0" */ -/* CRBP Compare Mask Register 1 */ -/* ==================================================================== */ - -typedef union sh_pi_crbp_xb_pipe_mask_0_u { - mmr_t sh_pi_crbp_xb_pipe_mask_0_regval; - struct { - mmr_t compare_address_mask : 47; - mmr_t compare_command_mask : 8; - mmr_t reserved_0 : 9; - } sh_pi_crbp_xb_pipe_mask_0_s; -} sh_pi_crbp_xb_pipe_mask_0_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_XB_PIPE_MASK_1" */ -/* CRBP XB Pipe Compare Mask Register 1 */ -/* ==================================================================== */ - -typedef union sh_pi_crbp_xb_pipe_mask_1_u { - mmr_t sh_pi_crbp_xb_pipe_mask_1_regval; - struct { - mmr_t compare_source_mask : 14; - mmr_t reserved_0 : 2; - mmr_t compare_supplemental_mask : 14; - mmr_t reserved_1 : 2; - mmr_t compare_echo_mask : 9; - mmr_t reserved_2 : 23; - } sh_pi_crbp_xb_pipe_mask_1_s; -} sh_pi_crbp_xb_pipe_mask_1_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_DPC_QUEUE_CONFIG" */ -/* DPC Queue Configuration */ -/* ==================================================================== */ - -typedef union sh_pi_dpc_queue_config_u { - mmr_t sh_pi_dpc_queue_config_regval; - struct { - mmr_t dwcq_ae_level : 5; - mmr_t reserved_0 : 3; - mmr_t dwcq_af_thresh : 5; - mmr_t reserved_1 : 3; - mmr_t fwcq_ae_level : 5; - mmr_t reserved_2 : 3; - mmr_t fwcq_af_thresh : 5; - mmr_t reserved_3 : 35; - } sh_pi_dpc_queue_config_s; -} sh_pi_dpc_queue_config_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_ERROR_MASK" */ -/* PI Error Mask */ -/* ==================================================================== */ - -typedef union sh_pi_error_mask_u { - mmr_t sh_pi_error_mask_regval; - struct { - mmr_t fsb_proto_err : 1; - mmr_t gfx_rp_err : 1; - mmr_t xb_proto_err : 1; - mmr_t mem_rp_err : 1; - mmr_t pio_rp_err : 1; - mmr_t mem_to_err : 1; - mmr_t pio_to_err : 1; - mmr_t fsb_shub_uce : 1; - mmr_t fsb_shub_ce : 1; - mmr_t msg_color_err : 1; - mmr_t md_rq_q_oflow : 1; - mmr_t md_rp_q_oflow : 1; - mmr_t xn_rq_q_oflow : 1; - mmr_t xn_rp_q_oflow : 1; - mmr_t nack_oflow : 1; - mmr_t gfx_int_0 : 1; - mmr_t gfx_int_1 : 1; - mmr_t md_rq_crd_oflow : 1; - mmr_t md_rp_crd_oflow : 1; - mmr_t xn_rq_crd_oflow : 1; - mmr_t xn_rp_crd_oflow : 1; - mmr_t hung_bus : 1; - mmr_t rsp_parity : 1; - mmr_t ioq_overrun : 1; - mmr_t req_format : 1; - mmr_t addr_access : 1; - mmr_t req_parity : 1; - mmr_t addr_parity : 1; - mmr_t shub_fsb_dqe : 1; - mmr_t shub_fsb_uce : 1; - mmr_t shub_fsb_ce : 1; - mmr_t livelock : 1; - mmr_t bad_snoop : 1; - mmr_t fsb_tbl_miss : 1; - mmr_t msg_length : 1; - mmr_t reserved_0 : 29; - } sh_pi_error_mask_s; -} sh_pi_error_mask_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_EXPRESS_REPLY_CONFIG" */ -/* PI Express Reply Configuration */ -/* ==================================================================== */ - -typedef union sh_pi_express_reply_config_u { - mmr_t sh_pi_express_reply_config_regval; - struct { - mmr_t mode : 3; - mmr_t reserved_0 : 61; - } sh_pi_express_reply_config_s; -} sh_pi_express_reply_config_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_FSB_COMPARE_VALUE" */ -/* FSB Compare Value */ -/* ==================================================================== */ - -typedef union sh_pi_fsb_compare_value_u { - mmr_t sh_pi_fsb_compare_value_regval; - struct { - mmr_t compare_value : 64; - } sh_pi_fsb_compare_value_s; -} sh_pi_fsb_compare_value_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_FSB_COMPARE_MASK" */ -/* FSB Compare Mask */ -/* ==================================================================== */ - -typedef union sh_pi_fsb_compare_mask_u { - mmr_t sh_pi_fsb_compare_mask_regval; - struct { - mmr_t mask_value : 64; - } sh_pi_fsb_compare_mask_s; -} sh_pi_fsb_compare_mask_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_FSB_ERROR_INJECTION" */ -/* Inject an Error onto the FSB */ -/* ==================================================================== */ - -typedef union sh_pi_fsb_error_injection_u { - mmr_t sh_pi_fsb_error_injection_regval; - struct { - mmr_t rp_pe_to_fsb : 1; - mmr_t ap0_pe_to_fsb : 1; - mmr_t ap1_pe_to_fsb : 1; - mmr_t rsp_pe_to_fsb : 1; - mmr_t dw0_ce_to_fsb : 1; - mmr_t dw0_uce_to_fsb : 1; - mmr_t dw1_ce_to_fsb : 1; - mmr_t dw1_uce_to_fsb : 1; - mmr_t ip0_pe_to_fsb : 1; - mmr_t ip1_pe_to_fsb : 1; - mmr_t reserved_0 : 6; - mmr_t rp_pe_from_fsb : 1; - mmr_t ap0_pe_from_fsb : 1; - mmr_t ap1_pe_from_fsb : 1; - mmr_t rsp_pe_from_fsb : 1; - mmr_t dw0_ce_from_fsb : 1; - mmr_t dw0_uce_from_fsb : 1; - mmr_t dw1_ce_from_fsb : 1; - mmr_t dw1_uce_from_fsb : 1; - mmr_t dw2_ce_from_fsb : 1; - mmr_t dw2_uce_from_fsb : 1; - mmr_t dw3_ce_from_fsb : 1; - mmr_t dw3_uce_from_fsb : 1; - mmr_t reserved_1 : 4; - mmr_t ioq_overrun : 1; - mmr_t livelock : 1; - mmr_t bus_hang : 1; - mmr_t reserved_2 : 29; - } sh_pi_fsb_error_injection_s; -} sh_pi_fsb_error_injection_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_MD2PI_REPLY_VC_CONFIG" */ -/* MD-to-PI Reply Virtual Channel Configuration */ -/* ==================================================================== */ - -typedef union sh_pi_md2pi_reply_vc_config_u { - mmr_t sh_pi_md2pi_reply_vc_config_regval; - struct { - mmr_t hdr_depth : 4; - mmr_t data_depth : 4; - mmr_t max_credits : 6; - mmr_t reserved_0 : 48; - mmr_t force_credit : 1; - mmr_t capture_credit_status : 1; - } sh_pi_md2pi_reply_vc_config_s; -} sh_pi_md2pi_reply_vc_config_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_MD2PI_REQUEST_VC_CONFIG" */ -/* MD-to-PI Request Virtual Channel Configuration */ -/* ==================================================================== */ - -typedef union sh_pi_md2pi_request_vc_config_u { - mmr_t sh_pi_md2pi_request_vc_config_regval; - struct { - mmr_t hdr_depth : 4; - mmr_t data_depth : 4; - mmr_t max_credits : 6; - mmr_t reserved_0 : 48; - mmr_t force_credit : 1; - mmr_t capture_credit_status : 1; - } sh_pi_md2pi_request_vc_config_s; -} sh_pi_md2pi_request_vc_config_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_QUEUE_ERROR_INJECTION" */ -/* PI Queue Error Injection */ -/* ==================================================================== */ - -typedef union sh_pi_queue_error_injection_u { - mmr_t sh_pi_queue_error_injection_regval; - struct { - mmr_t dat_dfr_q : 1; - mmr_t dxb_wtl_cmnd_q : 1; - mmr_t fsb_wtl_cmnd_q : 1; - mmr_t mdpi_rpy_bfr : 1; - mmr_t ptc_intr : 1; - mmr_t rxl_kill_q : 1; - mmr_t rxl_rdy_q : 1; - mmr_t xnpi_rpy_bfr : 1; - mmr_t reserved_0 : 56; - } sh_pi_queue_error_injection_s; -} sh_pi_queue_error_injection_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_TEST_POINT_COMPARE" */ -/* PI Test Point Compare */ -/* ==================================================================== */ - -typedef union sh_pi_test_point_compare_u { - mmr_t sh_pi_test_point_compare_regval; - struct { - mmr_t compare_mask : 32; - mmr_t compare_pattern : 32; - } sh_pi_test_point_compare_s; -} sh_pi_test_point_compare_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_TEST_POINT_SELECT" */ -/* PI Test Point Select */ -/* ==================================================================== */ - -typedef union sh_pi_test_point_select_u { - mmr_t sh_pi_test_point_select_regval; - struct { - mmr_t nibble0_chiplet_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble1_chiplet_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble2_chiplet_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble3_chiplet_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble4_chiplet_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble5_chiplet_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble6_chiplet_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble7_chiplet_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t trigger_enable : 1; - } sh_pi_test_point_select_s; -} sh_pi_test_point_select_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_TEST_POINT_TRIGGER_SELECT" */ -/* PI Test Point Trigger Select */ -/* ==================================================================== */ - -typedef union sh_pi_test_point_trigger_select_u { - mmr_t sh_pi_test_point_trigger_select_regval; - struct { - mmr_t trigger0_chiplet_sel : 3; - mmr_t reserved_0 : 1; - mmr_t trigger0_nibble_sel : 3; - mmr_t reserved_1 : 1; - mmr_t trigger1_chiplet_sel : 3; - mmr_t reserved_2 : 1; - mmr_t trigger1_nibble_sel : 3; - mmr_t reserved_3 : 1; - mmr_t trigger2_chiplet_sel : 3; - mmr_t reserved_4 : 1; - mmr_t trigger2_nibble_sel : 3; - mmr_t reserved_5 : 1; - mmr_t trigger3_chiplet_sel : 3; - mmr_t reserved_6 : 1; - mmr_t trigger3_nibble_sel : 3; - mmr_t reserved_7 : 1; - mmr_t trigger4_chiplet_sel : 3; - mmr_t reserved_8 : 1; - mmr_t trigger4_nibble_sel : 3; - mmr_t reserved_9 : 1; - mmr_t trigger5_chiplet_sel : 3; - mmr_t reserved_10 : 1; - mmr_t trigger5_nibble_sel : 3; - mmr_t reserved_11 : 1; - mmr_t trigger6_chiplet_sel : 3; - mmr_t reserved_12 : 1; - mmr_t trigger6_nibble_sel : 3; - mmr_t reserved_13 : 1; - mmr_t trigger7_chiplet_sel : 3; - mmr_t reserved_14 : 1; - mmr_t trigger7_nibble_sel : 3; - mmr_t reserved_15 : 1; - } sh_pi_test_point_trigger_select_s; -} sh_pi_test_point_trigger_select_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_XN2PI_REPLY_VC_CONFIG" */ -/* XN-to-PI Reply Virtual Channel Configuration */ -/* ==================================================================== */ - -typedef union sh_pi_xn2pi_reply_vc_config_u { - mmr_t sh_pi_xn2pi_reply_vc_config_regval; - struct { - mmr_t hdr_depth : 4; - mmr_t data_depth : 4; - mmr_t max_credits : 6; - mmr_t reserved_0 : 48; - mmr_t force_credit : 1; - mmr_t capture_credit_status : 1; - } sh_pi_xn2pi_reply_vc_config_s; -} sh_pi_xn2pi_reply_vc_config_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_XN2PI_REQUEST_VC_CONFIG" */ -/* XN-to-PI Request Virtual Channel Configuration */ -/* ==================================================================== */ - -typedef union sh_pi_xn2pi_request_vc_config_u { - mmr_t sh_pi_xn2pi_request_vc_config_regval; - struct { - mmr_t hdr_depth : 4; - mmr_t data_depth : 4; - mmr_t max_credits : 6; - mmr_t reserved_0 : 48; - mmr_t force_credit : 1; - mmr_t capture_credit_status : 1; - } sh_pi_xn2pi_request_vc_config_s; -} sh_pi_xn2pi_request_vc_config_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_AEC_STATUS" */ -/* PI Adaptive Error Correction Status */ -/* ==================================================================== */ - -typedef union sh_pi_aec_status_u { - mmr_t sh_pi_aec_status_regval; - struct { - mmr_t state : 3; - mmr_t reserved_0 : 61; - } sh_pi_aec_status_s; -} sh_pi_aec_status_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_AFI_FIRST_ERROR" */ -/* PI AFI First Error */ -/* ==================================================================== */ - -typedef union sh_pi_afi_first_error_u { - mmr_t sh_pi_afi_first_error_regval; - struct { - mmr_t reserved_0 : 7; - mmr_t fsb_shub_uce : 1; - mmr_t fsb_shub_ce : 1; - mmr_t reserved_1 : 12; - mmr_t hung_bus : 1; - mmr_t rsp_parity : 1; - mmr_t ioq_overrun : 1; - mmr_t req_format : 1; - mmr_t addr_access : 1; - mmr_t req_parity : 1; - mmr_t addr_parity : 1; - mmr_t shub_fsb_dqe : 1; - mmr_t shub_fsb_uce : 1; - mmr_t shub_fsb_ce : 1; - mmr_t livelock : 1; - mmr_t bad_snoop : 1; - mmr_t fsb_tbl_miss : 1; - mmr_t msg_len : 1; - mmr_t reserved_2 : 29; - } sh_pi_afi_first_error_s; -} sh_pi_afi_first_error_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_CAM_ADDRESS_READ_DATA" */ -/* CRB CAM MMR Address Read Data */ -/* ==================================================================== */ - -typedef union sh_pi_cam_address_read_data_u { - mmr_t sh_pi_cam_address_read_data_regval; - struct { - mmr_t cam_addr : 48; - mmr_t reserved_0 : 15; - mmr_t cam_addr_val : 1; - } sh_pi_cam_address_read_data_s; -} sh_pi_cam_address_read_data_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_CAM_LPRA_READ_DATA" */ -/* CRB CAM MMR LPRA Read Data */ -/* ==================================================================== */ - -typedef union sh_pi_cam_lpra_read_data_u { - mmr_t sh_pi_cam_lpra_read_data_regval; - struct { - mmr_t cam_lpra : 64; - } sh_pi_cam_lpra_read_data_s; -} sh_pi_cam_lpra_read_data_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_CAM_STATE_READ_DATA" */ -/* CRB CAM MMR State Read Data */ -/* ==================================================================== */ - -typedef union sh_pi_cam_state_read_data_u { - mmr_t sh_pi_cam_state_read_data_regval; - struct { - mmr_t cam_state : 4; - mmr_t cam_to : 1; - mmr_t cam_state_rd_pend : 1; - mmr_t reserved_0 : 26; - mmr_t cam_lpra : 18; - mmr_t reserved_1 : 13; - mmr_t cam_rd_data_val : 1; - } sh_pi_cam_state_read_data_s; -} sh_pi_cam_state_read_data_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_CORRECTED_DETAIL_1" */ -/* PI Corrected Error Detail */ -/* ==================================================================== */ - -typedef union sh_pi_corrected_detail_1_u { - mmr_t sh_pi_corrected_detail_1_regval; - struct { - mmr_t address : 48; - mmr_t syndrome : 8; - mmr_t dep : 8; - } sh_pi_corrected_detail_1_s; -} sh_pi_corrected_detail_1_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_CORRECTED_DETAIL_2" */ -/* PI Corrected Error Detail 2 */ -/* ==================================================================== */ - -typedef union sh_pi_corrected_detail_2_u { - mmr_t sh_pi_corrected_detail_2_regval; - struct { - mmr_t data : 64; - } sh_pi_corrected_detail_2_s; -} sh_pi_corrected_detail_2_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_CORRECTED_DETAIL_3" */ -/* PI Corrected Error Detail 3 */ -/* ==================================================================== */ - -typedef union sh_pi_corrected_detail_3_u { - mmr_t sh_pi_corrected_detail_3_regval; - struct { - mmr_t address : 48; - mmr_t syndrome : 8; - mmr_t dep : 8; - } sh_pi_corrected_detail_3_s; -} sh_pi_corrected_detail_3_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_CORRECTED_DETAIL_4" */ -/* PI Corrected Error Detail 4 */ -/* ==================================================================== */ - -typedef union sh_pi_corrected_detail_4_u { - mmr_t sh_pi_corrected_detail_4_regval; - struct { - mmr_t data : 64; - } sh_pi_corrected_detail_4_s; -} sh_pi_corrected_detail_4_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_FIRST_ERROR" */ -/* PI CRBP First Error */ -/* ==================================================================== */ - -typedef union sh_pi_crbp_first_error_u { - mmr_t sh_pi_crbp_first_error_regval; - struct { - mmr_t fsb_proto_err : 1; - mmr_t gfx_rp_err : 1; - mmr_t xb_proto_err : 1; - mmr_t mem_rp_err : 1; - mmr_t pio_rp_err : 1; - mmr_t mem_to_err : 1; - mmr_t pio_to_err : 1; - mmr_t fsb_shub_uce : 1; - mmr_t fsb_shub_ce : 1; - mmr_t msg_color_err : 1; - mmr_t md_rq_q_oflow : 1; - mmr_t md_rp_q_oflow : 1; - mmr_t xn_rq_q_oflow : 1; - mmr_t xn_rp_q_oflow : 1; - mmr_t nack_oflow : 1; - mmr_t gfx_int_0 : 1; - mmr_t gfx_int_1 : 1; - mmr_t md_rq_crd_oflow : 1; - mmr_t md_rp_crd_oflow : 1; - mmr_t xn_rq_crd_oflow : 1; - mmr_t xn_rp_crd_oflow : 1; - mmr_t reserved_0 : 43; - } sh_pi_crbp_first_error_s; -} sh_pi_crbp_first_error_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_ERROR_DETAIL_1" */ -/* PI Error Detail 1 */ -/* ==================================================================== */ - -typedef union sh_pi_error_detail_1_u { - mmr_t sh_pi_error_detail_1_regval; - struct { - mmr_t status : 64; - } sh_pi_error_detail_1_s; -} sh_pi_error_detail_1_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_ERROR_DETAIL_2" */ -/* PI Error Detail 2 */ -/* ==================================================================== */ - -typedef union sh_pi_error_detail_2_u { - mmr_t sh_pi_error_detail_2_regval; - struct { - mmr_t status : 64; - } sh_pi_error_detail_2_s; -} sh_pi_error_detail_2_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_ERROR_OVERFLOW" */ -/* PI Error Overflow */ -/* ==================================================================== */ - -typedef union sh_pi_error_overflow_u { - mmr_t sh_pi_error_overflow_regval; - struct { - mmr_t fsb_proto_err : 1; - mmr_t gfx_rp_err : 1; - mmr_t xb_proto_err : 1; - mmr_t mem_rp_err : 1; - mmr_t pio_rp_err : 1; - mmr_t mem_to_err : 1; - mmr_t pio_to_err : 1; - mmr_t fsb_shub_uce : 1; - mmr_t fsb_shub_ce : 1; - mmr_t msg_color_err : 1; - mmr_t md_rq_q_oflow : 1; - mmr_t md_rp_q_oflow : 1; - mmr_t xn_rq_q_oflow : 1; - mmr_t xn_rp_q_oflow : 1; - mmr_t nack_oflow : 1; - mmr_t gfx_int_0 : 1; - mmr_t gfx_int_1 : 1; - mmr_t md_rq_crd_oflow : 1; - mmr_t md_rp_crd_oflow : 1; - mmr_t xn_rq_crd_oflow : 1; - mmr_t xn_rp_crd_oflow : 1; - mmr_t hung_bus : 1; - mmr_t rsp_parity : 1; - mmr_t ioq_overrun : 1; - mmr_t req_format : 1; - mmr_t addr_access : 1; - mmr_t req_parity : 1; - mmr_t addr_parity : 1; - mmr_t shub_fsb_dqe : 1; - mmr_t shub_fsb_uce : 1; - mmr_t shub_fsb_ce : 1; - mmr_t livelock : 1; - mmr_t bad_snoop : 1; - mmr_t fsb_tbl_miss : 1; - mmr_t msg_length : 1; - mmr_t reserved_0 : 29; - } sh_pi_error_overflow_s; -} sh_pi_error_overflow_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_ERROR_SUMMARY" */ -/* PI Error Summary */ -/* ==================================================================== */ - -typedef union sh_pi_error_summary_u { - mmr_t sh_pi_error_summary_regval; - struct { - mmr_t fsb_proto_err : 1; - mmr_t gfx_rp_err : 1; - mmr_t xb_proto_err : 1; - mmr_t mem_rp_err : 1; - mmr_t pio_rp_err : 1; - mmr_t mem_to_err : 1; - mmr_t pio_to_err : 1; - mmr_t fsb_shub_uce : 1; - mmr_t fsb_shub_ce : 1; - mmr_t msg_color_err : 1; - mmr_t md_rq_q_oflow : 1; - mmr_t md_rp_q_oflow : 1; - mmr_t xn_rq_q_oflow : 1; - mmr_t xn_rp_q_oflow : 1; - mmr_t nack_oflow : 1; - mmr_t gfx_int_0 : 1; - mmr_t gfx_int_1 : 1; - mmr_t md_rq_crd_oflow : 1; - mmr_t md_rp_crd_oflow : 1; - mmr_t xn_rq_crd_oflow : 1; - mmr_t xn_rp_crd_oflow : 1; - mmr_t hung_bus : 1; - mmr_t rsp_parity : 1; - mmr_t ioq_overrun : 1; - mmr_t req_format : 1; - mmr_t addr_access : 1; - mmr_t req_parity : 1; - mmr_t addr_parity : 1; - mmr_t shub_fsb_dqe : 1; - mmr_t shub_fsb_uce : 1; - mmr_t shub_fsb_ce : 1; - mmr_t livelock : 1; - mmr_t bad_snoop : 1; - mmr_t fsb_tbl_miss : 1; - mmr_t msg_length : 1; - mmr_t reserved_0 : 29; - } sh_pi_error_summary_s; -} sh_pi_error_summary_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_EXPRESS_REPLY_STATUS" */ -/* PI Express Reply Status */ -/* ==================================================================== */ - -typedef union sh_pi_express_reply_status_u { - mmr_t sh_pi_express_reply_status_regval; - struct { - mmr_t state : 3; - mmr_t reserved_0 : 61; - } sh_pi_express_reply_status_s; -} sh_pi_express_reply_status_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_FIRST_ERROR" */ -/* PI First Error */ -/* ==================================================================== */ - -typedef union sh_pi_first_error_u { - mmr_t sh_pi_first_error_regval; - struct { - mmr_t fsb_proto_err : 1; - mmr_t gfx_rp_err : 1; - mmr_t xb_proto_err : 1; - mmr_t mem_rp_err : 1; - mmr_t pio_rp_err : 1; - mmr_t mem_to_err : 1; - mmr_t pio_to_err : 1; - mmr_t fsb_shub_uce : 1; - mmr_t fsb_shub_ce : 1; - mmr_t msg_color_err : 1; - mmr_t md_rq_q_oflow : 1; - mmr_t md_rp_q_oflow : 1; - mmr_t xn_rq_q_oflow : 1; - mmr_t xn_rp_q_oflow : 1; - mmr_t nack_oflow : 1; - mmr_t gfx_int_0 : 1; - mmr_t gfx_int_1 : 1; - mmr_t md_rq_crd_oflow : 1; - mmr_t md_rp_crd_oflow : 1; - mmr_t xn_rq_crd_oflow : 1; - mmr_t xn_rp_crd_oflow : 1; - mmr_t hung_bus : 1; - mmr_t rsp_parity : 1; - mmr_t ioq_overrun : 1; - mmr_t req_format : 1; - mmr_t addr_access : 1; - mmr_t req_parity : 1; - mmr_t addr_parity : 1; - mmr_t shub_fsb_dqe : 1; - mmr_t shub_fsb_uce : 1; - mmr_t shub_fsb_ce : 1; - mmr_t livelock : 1; - mmr_t bad_snoop : 1; - mmr_t fsb_tbl_miss : 1; - mmr_t msg_length : 1; - mmr_t reserved_0 : 29; - } sh_pi_first_error_s; -} sh_pi_first_error_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_PI2MD_REPLY_VC_STATUS" */ -/* PI-to-MD Reply Virtual Channel Status */ -/* ==================================================================== */ - -typedef union sh_pi_pi2md_reply_vc_status_u { - mmr_t sh_pi_pi2md_reply_vc_status_regval; - struct { - mmr_t output_crd_stat : 6; - mmr_t reserved_0 : 58; - } sh_pi_pi2md_reply_vc_status_s; -} sh_pi_pi2md_reply_vc_status_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_PI2MD_REQUEST_VC_STATUS" */ -/* PI-to-MD Request Virtual Channel Status */ -/* ==================================================================== */ - -typedef union sh_pi_pi2md_request_vc_status_u { - mmr_t sh_pi_pi2md_request_vc_status_regval; - struct { - mmr_t output_crd_stat : 6; - mmr_t reserved_0 : 58; - } sh_pi_pi2md_request_vc_status_s; -} sh_pi_pi2md_request_vc_status_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_PI2XN_REPLY_VC_STATUS" */ -/* PI-to-XN Reply Virtual Channel Status */ -/* ==================================================================== */ - -typedef union sh_pi_pi2xn_reply_vc_status_u { - mmr_t sh_pi_pi2xn_reply_vc_status_regval; - struct { - mmr_t output_crd_stat : 6; - mmr_t reserved_0 : 58; - } sh_pi_pi2xn_reply_vc_status_s; -} sh_pi_pi2xn_reply_vc_status_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_PI2XN_REQUEST_VC_STATUS" */ -/* PI-to-XN Request Virtual Channel Status */ -/* ==================================================================== */ - -typedef union sh_pi_pi2xn_request_vc_status_u { - mmr_t sh_pi_pi2xn_request_vc_status_regval; - struct { - mmr_t output_crd_stat : 6; - mmr_t reserved_0 : 58; - } sh_pi_pi2xn_request_vc_status_s; -} sh_pi_pi2xn_request_vc_status_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_UNCORRECTED_DETAIL_1" */ -/* PI Uncorrected Error Detail 1 */ -/* ==================================================================== */ - -typedef union sh_pi_uncorrected_detail_1_u { - mmr_t sh_pi_uncorrected_detail_1_regval; - struct { - mmr_t address : 48; - mmr_t syndrome : 8; - mmr_t dep : 8; - } sh_pi_uncorrected_detail_1_s; -} sh_pi_uncorrected_detail_1_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_UNCORRECTED_DETAIL_2" */ -/* PI Uncorrected Error Detail 2 */ -/* ==================================================================== */ - -typedef union sh_pi_uncorrected_detail_2_u { - mmr_t sh_pi_uncorrected_detail_2_regval; - struct { - mmr_t data : 64; - } sh_pi_uncorrected_detail_2_s; -} sh_pi_uncorrected_detail_2_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_UNCORRECTED_DETAIL_3" */ -/* PI Uncorrected Error Detail 3 */ -/* ==================================================================== */ - -typedef union sh_pi_uncorrected_detail_3_u { - mmr_t sh_pi_uncorrected_detail_3_regval; - struct { - mmr_t address : 48; - mmr_t syndrome : 8; - mmr_t dep : 8; - } sh_pi_uncorrected_detail_3_s; -} sh_pi_uncorrected_detail_3_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_UNCORRECTED_DETAIL_4" */ -/* PI Uncorrected Error Detail 4 */ -/* ==================================================================== */ - -typedef union sh_pi_uncorrected_detail_4_u { - mmr_t sh_pi_uncorrected_detail_4_regval; - struct { - mmr_t data : 64; - } sh_pi_uncorrected_detail_4_s; -} sh_pi_uncorrected_detail_4_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_MD2PI_REPLY_VC_STATUS" */ -/* MD-to-PI Reply Virtual Channel Status */ -/* ==================================================================== */ - -typedef union sh_pi_md2pi_reply_vc_status_u { - mmr_t sh_pi_md2pi_reply_vc_status_regval; - struct { - mmr_t input_hdr_crd_stat : 4; - mmr_t input_dat_crd_stat : 4; - mmr_t input_queue_stat : 4; - mmr_t reserved_0 : 52; - } sh_pi_md2pi_reply_vc_status_s; -} sh_pi_md2pi_reply_vc_status_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_MD2PI_REQUEST_VC_STATUS" */ -/* MD-to-PI Request Virtual Channel Status */ -/* ==================================================================== */ - -typedef union sh_pi_md2pi_request_vc_status_u { - mmr_t sh_pi_md2pi_request_vc_status_regval; - struct { - mmr_t input_hdr_crd_stat : 4; - mmr_t input_dat_crd_stat : 4; - mmr_t input_queue_stat : 4; - mmr_t reserved_0 : 52; - } sh_pi_md2pi_request_vc_status_s; -} sh_pi_md2pi_request_vc_status_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_XN2PI_REPLY_VC_STATUS" */ -/* XN-to-PI Reply Virtual Channel Status */ -/* ==================================================================== */ - -typedef union sh_pi_xn2pi_reply_vc_status_u { - mmr_t sh_pi_xn2pi_reply_vc_status_regval; - struct { - mmr_t input_hdr_crd_stat : 4; - mmr_t input_dat_crd_stat : 4; - mmr_t input_queue_stat : 4; - mmr_t reserved_0 : 52; - } sh_pi_xn2pi_reply_vc_status_s; -} sh_pi_xn2pi_reply_vc_status_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_XN2PI_REQUEST_VC_STATUS" */ -/* XN-to-PI Request Virtual Channel Status */ -/* ==================================================================== */ - -typedef union sh_pi_xn2pi_request_vc_status_u { - mmr_t sh_pi_xn2pi_request_vc_status_regval; - struct { - mmr_t input_hdr_crd_stat : 4; - mmr_t input_dat_crd_stat : 4; - mmr_t input_queue_stat : 4; - mmr_t reserved_0 : 52; - } sh_pi_xn2pi_request_vc_status_s; -} sh_pi_xn2pi_request_vc_status_u_t; - -/* ==================================================================== */ -/* Register "SH_XNPI_SIC_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnpi_sic_flow_u { - mmr_t sh_xnpi_sic_flow_regval; - struct { - mmr_t debit_vc0_withhold : 5; - mmr_t reserved_0 : 2; - mmr_t debit_vc0_force_cred : 1; - mmr_t debit_vc2_withhold : 5; - mmr_t reserved_1 : 2; - mmr_t debit_vc2_force_cred : 1; - mmr_t credit_vc0_test : 5; - mmr_t reserved_2 : 3; - mmr_t credit_vc0_dyn : 5; - mmr_t reserved_3 : 3; - mmr_t credit_vc0_cap : 5; - mmr_t reserved_4 : 3; - mmr_t credit_vc2_test : 5; - mmr_t reserved_5 : 3; - mmr_t credit_vc2_dyn : 5; - mmr_t reserved_6 : 3; - mmr_t credit_vc2_cap : 5; - mmr_t reserved_7 : 2; - mmr_t disable_bypass_out : 1; - } sh_xnpi_sic_flow_s; -} sh_xnpi_sic_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNPI_TO_NI0_PORT_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnpi_to_ni0_port_flow_u { - mmr_t sh_xnpi_to_ni0_port_flow_regval; - struct { - mmr_t debit_vc0_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_force_cred : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_2 : 8; - mmr_t credit_vc0_dyn : 6; - mmr_t reserved_3 : 2; - mmr_t credit_vc0_cap : 6; - mmr_t reserved_4 : 10; - mmr_t credit_vc2_dyn : 6; - mmr_t reserved_5 : 2; - mmr_t credit_vc2_cap : 6; - mmr_t reserved_6 : 2; - } sh_xnpi_to_ni0_port_flow_s; -} sh_xnpi_to_ni0_port_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNPI_TO_NI1_PORT_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnpi_to_ni1_port_flow_u { - mmr_t sh_xnpi_to_ni1_port_flow_regval; - struct { - mmr_t debit_vc0_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_force_cred : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_2 : 8; - mmr_t credit_vc0_dyn : 6; - mmr_t reserved_3 : 2; - mmr_t credit_vc0_cap : 6; - mmr_t reserved_4 : 10; - mmr_t credit_vc2_dyn : 6; - mmr_t reserved_5 : 2; - mmr_t credit_vc2_cap : 6; - mmr_t reserved_6 : 2; - } sh_xnpi_to_ni1_port_flow_s; -} sh_xnpi_to_ni1_port_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNPI_TO_IILB_PORT_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnpi_to_iilb_port_flow_u { - mmr_t sh_xnpi_to_iilb_port_flow_regval; - struct { - mmr_t debit_vc0_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_force_cred : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_2 : 8; - mmr_t credit_vc0_dyn : 6; - mmr_t reserved_3 : 2; - mmr_t credit_vc0_cap : 6; - mmr_t reserved_4 : 10; - mmr_t credit_vc2_dyn : 6; - mmr_t reserved_5 : 2; - mmr_t credit_vc2_cap : 6; - mmr_t reserved_6 : 2; - } sh_xnpi_to_iilb_port_flow_s; -} sh_xnpi_to_iilb_port_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNPI_FR_NI0_PORT_FLOW_FIFO" */ -/* ==================================================================== */ - -typedef union sh_xnpi_fr_ni0_port_flow_fifo_u { - mmr_t sh_xnpi_fr_ni0_port_flow_fifo_regval; - struct { - mmr_t entry_vc0_dyn : 6; - mmr_t reserved_0 : 2; - mmr_t entry_vc0_cap : 6; - mmr_t reserved_1 : 2; - mmr_t entry_vc2_dyn : 6; - mmr_t reserved_2 : 2; - mmr_t entry_vc2_cap : 6; - mmr_t reserved_3 : 2; - mmr_t entry_vc0_test : 5; - mmr_t reserved_4 : 3; - mmr_t entry_vc2_test : 5; - mmr_t reserved_5 : 19; - } sh_xnpi_fr_ni0_port_flow_fifo_s; -} sh_xnpi_fr_ni0_port_flow_fifo_u_t; - -/* ==================================================================== */ -/* Register "SH_XNPI_FR_NI1_PORT_FLOW_FIFO" */ -/* ==================================================================== */ - -typedef union sh_xnpi_fr_ni1_port_flow_fifo_u { - mmr_t sh_xnpi_fr_ni1_port_flow_fifo_regval; - struct { - mmr_t entry_vc0_dyn : 6; - mmr_t reserved_0 : 2; - mmr_t entry_vc0_cap : 6; - mmr_t reserved_1 : 2; - mmr_t entry_vc2_dyn : 6; - mmr_t reserved_2 : 2; - mmr_t entry_vc2_cap : 6; - mmr_t reserved_3 : 2; - mmr_t entry_vc0_test : 5; - mmr_t reserved_4 : 3; - mmr_t entry_vc2_test : 5; - mmr_t reserved_5 : 19; - } sh_xnpi_fr_ni1_port_flow_fifo_s; -} sh_xnpi_fr_ni1_port_flow_fifo_u_t; - -/* ==================================================================== */ -/* Register "SH_XNPI_FR_IILB_PORT_FLOW_FIFO" */ -/* ==================================================================== */ - -typedef union sh_xnpi_fr_iilb_port_flow_fifo_u { - mmr_t sh_xnpi_fr_iilb_port_flow_fifo_regval; - struct { - mmr_t entry_vc0_dyn : 6; - mmr_t reserved_0 : 2; - mmr_t entry_vc0_cap : 6; - mmr_t reserved_1 : 2; - mmr_t entry_vc2_dyn : 6; - mmr_t reserved_2 : 2; - mmr_t entry_vc2_cap : 6; - mmr_t reserved_3 : 2; - mmr_t entry_vc0_test : 5; - mmr_t reserved_4 : 3; - mmr_t entry_vc2_test : 5; - mmr_t reserved_5 : 19; - } sh_xnpi_fr_iilb_port_flow_fifo_s; -} sh_xnpi_fr_iilb_port_flow_fifo_u_t; - -/* ==================================================================== */ -/* Register "SH_XNMD_SIC_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnmd_sic_flow_u { - mmr_t sh_xnmd_sic_flow_regval; - struct { - mmr_t debit_vc0_withhold : 5; - mmr_t reserved_0 : 2; - mmr_t debit_vc0_force_cred : 1; - mmr_t debit_vc2_withhold : 5; - mmr_t reserved_1 : 2; - mmr_t debit_vc2_force_cred : 1; - mmr_t credit_vc0_test : 5; - mmr_t reserved_2 : 3; - mmr_t credit_vc0_dyn : 5; - mmr_t reserved_3 : 3; - mmr_t credit_vc0_cap : 5; - mmr_t reserved_4 : 3; - mmr_t credit_vc2_test : 5; - mmr_t reserved_5 : 3; - mmr_t credit_vc2_dyn : 5; - mmr_t reserved_6 : 3; - mmr_t credit_vc2_cap : 5; - mmr_t reserved_7 : 2; - mmr_t disable_bypass_out : 1; - } sh_xnmd_sic_flow_s; -} sh_xnmd_sic_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNMD_TO_NI0_PORT_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnmd_to_ni0_port_flow_u { - mmr_t sh_xnmd_to_ni0_port_flow_regval; - struct { - mmr_t debit_vc0_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_force_cred : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_2 : 8; - mmr_t credit_vc0_dyn : 6; - mmr_t reserved_3 : 2; - mmr_t credit_vc0_cap : 6; - mmr_t reserved_4 : 10; - mmr_t credit_vc2_dyn : 6; - mmr_t reserved_5 : 2; - mmr_t credit_vc2_cap : 6; - mmr_t reserved_6 : 2; - } sh_xnmd_to_ni0_port_flow_s; -} sh_xnmd_to_ni0_port_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNMD_TO_NI1_PORT_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnmd_to_ni1_port_flow_u { - mmr_t sh_xnmd_to_ni1_port_flow_regval; - struct { - mmr_t debit_vc0_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_force_cred : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_2 : 8; - mmr_t credit_vc0_dyn : 6; - mmr_t reserved_3 : 2; - mmr_t credit_vc0_cap : 6; - mmr_t reserved_4 : 10; - mmr_t credit_vc2_dyn : 6; - mmr_t reserved_5 : 2; - mmr_t credit_vc2_cap : 6; - mmr_t reserved_6 : 2; - } sh_xnmd_to_ni1_port_flow_s; -} sh_xnmd_to_ni1_port_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNMD_TO_IILB_PORT_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnmd_to_iilb_port_flow_u { - mmr_t sh_xnmd_to_iilb_port_flow_regval; - struct { - mmr_t debit_vc0_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_force_cred : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_2 : 8; - mmr_t credit_vc0_dyn : 6; - mmr_t reserved_3 : 2; - mmr_t credit_vc0_cap : 6; - mmr_t reserved_4 : 10; - mmr_t credit_vc2_dyn : 6; - mmr_t reserved_5 : 2; - mmr_t credit_vc2_cap : 6; - mmr_t reserved_6 : 2; - } sh_xnmd_to_iilb_port_flow_s; -} sh_xnmd_to_iilb_port_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNMD_FR_NI0_PORT_FLOW_FIFO" */ -/* ==================================================================== */ - -typedef union sh_xnmd_fr_ni0_port_flow_fifo_u { - mmr_t sh_xnmd_fr_ni0_port_flow_fifo_regval; - struct { - mmr_t entry_vc0_dyn : 6; - mmr_t reserved_0 : 2; - mmr_t entry_vc0_cap : 6; - mmr_t reserved_1 : 2; - mmr_t entry_vc2_dyn : 6; - mmr_t reserved_2 : 2; - mmr_t entry_vc2_cap : 6; - mmr_t reserved_3 : 2; - mmr_t entry_vc0_test : 5; - mmr_t reserved_4 : 3; - mmr_t entry_vc2_test : 5; - mmr_t reserved_5 : 19; - } sh_xnmd_fr_ni0_port_flow_fifo_s; -} sh_xnmd_fr_ni0_port_flow_fifo_u_t; - -/* ==================================================================== */ -/* Register "SH_XNMD_FR_NI1_PORT_FLOW_FIFO" */ -/* ==================================================================== */ - -typedef union sh_xnmd_fr_ni1_port_flow_fifo_u { - mmr_t sh_xnmd_fr_ni1_port_flow_fifo_regval; - struct { - mmr_t entry_vc0_dyn : 6; - mmr_t reserved_0 : 2; - mmr_t entry_vc0_cap : 6; - mmr_t reserved_1 : 2; - mmr_t entry_vc2_dyn : 6; - mmr_t reserved_2 : 2; - mmr_t entry_vc2_cap : 6; - mmr_t reserved_3 : 2; - mmr_t entry_vc0_test : 5; - mmr_t reserved_4 : 3; - mmr_t entry_vc2_test : 5; - mmr_t reserved_5 : 19; - } sh_xnmd_fr_ni1_port_flow_fifo_s; -} sh_xnmd_fr_ni1_port_flow_fifo_u_t; - -/* ==================================================================== */ -/* Register "SH_XNMD_FR_IILB_PORT_FLOW_FIFO" */ -/* ==================================================================== */ - -typedef union sh_xnmd_fr_iilb_port_flow_fifo_u { - mmr_t sh_xnmd_fr_iilb_port_flow_fifo_regval; - struct { - mmr_t entry_vc0_dyn : 6; - mmr_t reserved_0 : 2; - mmr_t entry_vc0_cap : 6; - mmr_t reserved_1 : 2; - mmr_t entry_vc2_dyn : 6; - mmr_t reserved_2 : 2; - mmr_t entry_vc2_cap : 6; - mmr_t reserved_3 : 2; - mmr_t entry_vc0_test : 5; - mmr_t reserved_4 : 3; - mmr_t entry_vc2_test : 5; - mmr_t reserved_5 : 19; - } sh_xnmd_fr_iilb_port_flow_fifo_s; -} sh_xnmd_fr_iilb_port_flow_fifo_u_t; - -/* ==================================================================== */ -/* Register "SH_XNII_INTRA_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnii_intra_flow_u { - mmr_t sh_xnii_intra_flow_regval; - struct { - mmr_t debit_vc0_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_force_cred : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_force_cred : 1; - mmr_t credit_vc0_test : 7; - mmr_t reserved_2 : 1; - mmr_t credit_vc0_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t credit_vc0_cap : 7; - mmr_t reserved_4 : 1; - mmr_t credit_vc2_test : 7; - mmr_t reserved_5 : 1; - mmr_t credit_vc2_dyn : 7; - mmr_t reserved_6 : 1; - mmr_t credit_vc2_cap : 7; - mmr_t reserved_7 : 1; - } sh_xnii_intra_flow_s; -} sh_xnii_intra_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNLB_INTRA_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnlb_intra_flow_u { - mmr_t sh_xnlb_intra_flow_regval; - struct { - mmr_t debit_vc0_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_force_cred : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_force_cred : 1; - mmr_t credit_vc0_test : 7; - mmr_t reserved_2 : 1; - mmr_t credit_vc0_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t credit_vc0_cap : 7; - mmr_t reserved_4 : 1; - mmr_t credit_vc2_test : 7; - mmr_t reserved_5 : 1; - mmr_t credit_vc2_dyn : 7; - mmr_t reserved_6 : 1; - mmr_t credit_vc2_cap : 7; - mmr_t disable_bypass_in : 1; - } sh_xnlb_intra_flow_s; -} sh_xnlb_intra_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -typedef union sh_xniilb_to_ni0_intra_flow_debit_u { - mmr_t sh_xniilb_to_ni0_intra_flow_debit_regval; - struct { - mmr_t vc0_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t vc0_force_cred : 1; - mmr_t vc2_withhold : 6; - mmr_t reserved_1 : 1; - mmr_t vc2_force_cred : 1; - mmr_t reserved_2 : 8; - mmr_t vc0_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_4 : 9; - mmr_t vc2_dyn : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_6 : 1; - } sh_xniilb_to_ni0_intra_flow_debit_s; -} sh_xniilb_to_ni0_intra_flow_debit_u_t; - -/* ==================================================================== */ -/* Register "SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -typedef union sh_xniilb_to_ni1_intra_flow_debit_u { - mmr_t sh_xniilb_to_ni1_intra_flow_debit_regval; - struct { - mmr_t vc0_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t vc0_force_cred : 1; - mmr_t vc2_withhold : 6; - mmr_t reserved_1 : 1; - mmr_t vc2_force_cred : 1; - mmr_t reserved_2 : 8; - mmr_t vc0_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_4 : 9; - mmr_t vc2_dyn : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_6 : 1; - } sh_xniilb_to_ni1_intra_flow_debit_s; -} sh_xniilb_to_ni1_intra_flow_debit_u_t; - -/* ==================================================================== */ -/* Register "SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -typedef union sh_xniilb_to_md_intra_flow_debit_u { - mmr_t sh_xniilb_to_md_intra_flow_debit_regval; - struct { - mmr_t vc0_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t vc0_force_cred : 1; - mmr_t vc2_withhold : 6; - mmr_t reserved_1 : 1; - mmr_t vc2_force_cred : 1; - mmr_t reserved_2 : 8; - mmr_t vc0_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_4 : 9; - mmr_t vc2_dyn : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_6 : 1; - } sh_xniilb_to_md_intra_flow_debit_s; -} sh_xniilb_to_md_intra_flow_debit_u_t; - -/* ==================================================================== */ -/* Register "SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -typedef union sh_xniilb_to_iilb_intra_flow_debit_u { - mmr_t sh_xniilb_to_iilb_intra_flow_debit_regval; - struct { - mmr_t vc0_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t vc0_force_cred : 1; - mmr_t vc2_withhold : 6; - mmr_t reserved_1 : 1; - mmr_t vc2_force_cred : 1; - mmr_t reserved_2 : 8; - mmr_t vc0_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_4 : 9; - mmr_t vc2_dyn : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_6 : 1; - } sh_xniilb_to_iilb_intra_flow_debit_s; -} sh_xniilb_to_iilb_intra_flow_debit_u_t; - -/* ==================================================================== */ -/* Register "SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -typedef union sh_xniilb_to_pi_intra_flow_debit_u { - mmr_t sh_xniilb_to_pi_intra_flow_debit_regval; - struct { - mmr_t vc0_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t vc0_force_cred : 1; - mmr_t vc2_withhold : 6; - mmr_t reserved_1 : 1; - mmr_t vc2_force_cred : 1; - mmr_t reserved_2 : 8; - mmr_t vc0_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_4 : 9; - mmr_t vc2_dyn : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_6 : 1; - } sh_xniilb_to_pi_intra_flow_debit_s; -} sh_xniilb_to_pi_intra_flow_debit_u_t; - -/* ==================================================================== */ -/* Register "SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -typedef union sh_xniilb_fr_ni0_intra_flow_credit_u { - mmr_t sh_xniilb_fr_ni0_intra_flow_credit_regval; - struct { - mmr_t vc0_test : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_2 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 17; - } sh_xniilb_fr_ni0_intra_flow_credit_s; -} sh_xniilb_fr_ni0_intra_flow_credit_u_t; - -/* ==================================================================== */ -/* Register "SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -typedef union sh_xniilb_fr_ni1_intra_flow_credit_u { - mmr_t sh_xniilb_fr_ni1_intra_flow_credit_regval; - struct { - mmr_t vc0_test : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_2 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 17; - } sh_xniilb_fr_ni1_intra_flow_credit_s; -} sh_xniilb_fr_ni1_intra_flow_credit_u_t; - -/* ==================================================================== */ -/* Register "SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -typedef union sh_xniilb_fr_md_intra_flow_credit_u { - mmr_t sh_xniilb_fr_md_intra_flow_credit_regval; - struct { - mmr_t vc0_test : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_2 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 17; - } sh_xniilb_fr_md_intra_flow_credit_s; -} sh_xniilb_fr_md_intra_flow_credit_u_t; - -/* ==================================================================== */ -/* Register "SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -typedef union sh_xniilb_fr_iilb_intra_flow_credit_u { - mmr_t sh_xniilb_fr_iilb_intra_flow_credit_regval; - struct { - mmr_t vc0_test : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_2 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 17; - } sh_xniilb_fr_iilb_intra_flow_credit_s; -} sh_xniilb_fr_iilb_intra_flow_credit_u_t; - -/* ==================================================================== */ -/* Register "SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -typedef union sh_xniilb_fr_pi_intra_flow_credit_u { - mmr_t sh_xniilb_fr_pi_intra_flow_credit_regval; - struct { - mmr_t vc0_test : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_2 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 17; - } sh_xniilb_fr_pi_intra_flow_credit_s; -} sh_xniilb_fr_pi_intra_flow_credit_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -typedef union sh_xnni0_to_pi_intra_flow_debit_u { - mmr_t sh_xnni0_to_pi_intra_flow_debit_regval; - struct { - mmr_t vc0_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t vc0_force_cred : 1; - mmr_t vc2_withhold : 6; - mmr_t reserved_1 : 1; - mmr_t vc2_force_cred : 1; - mmr_t reserved_2 : 8; - mmr_t vc0_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_4 : 9; - mmr_t vc2_dyn : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_6 : 1; - } sh_xnni0_to_pi_intra_flow_debit_s; -} sh_xnni0_to_pi_intra_flow_debit_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -typedef union sh_xnni0_to_md_intra_flow_debit_u { - mmr_t sh_xnni0_to_md_intra_flow_debit_regval; - struct { - mmr_t vc0_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t vc0_force_cred : 1; - mmr_t vc2_withhold : 6; - mmr_t reserved_1 : 1; - mmr_t vc2_force_cred : 1; - mmr_t reserved_2 : 8; - mmr_t vc0_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_4 : 9; - mmr_t vc2_dyn : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_6 : 1; - } sh_xnni0_to_md_intra_flow_debit_s; -} sh_xnni0_to_md_intra_flow_debit_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -typedef union sh_xnni0_to_iilb_intra_flow_debit_u { - mmr_t sh_xnni0_to_iilb_intra_flow_debit_regval; - struct { - mmr_t vc0_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t vc0_force_cred : 1; - mmr_t vc2_withhold : 6; - mmr_t reserved_1 : 1; - mmr_t vc2_force_cred : 1; - mmr_t reserved_2 : 8; - mmr_t vc0_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_4 : 9; - mmr_t vc2_dyn : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_6 : 1; - } sh_xnni0_to_iilb_intra_flow_debit_s; -} sh_xnni0_to_iilb_intra_flow_debit_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -typedef union sh_xnni0_fr_pi_intra_flow_credit_u { - mmr_t sh_xnni0_fr_pi_intra_flow_credit_regval; - struct { - mmr_t vc0_test : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_2 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 17; - } sh_xnni0_fr_pi_intra_flow_credit_s; -} sh_xnni0_fr_pi_intra_flow_credit_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -typedef union sh_xnni0_fr_md_intra_flow_credit_u { - mmr_t sh_xnni0_fr_md_intra_flow_credit_regval; - struct { - mmr_t vc0_test : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_2 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 17; - } sh_xnni0_fr_md_intra_flow_credit_s; -} sh_xnni0_fr_md_intra_flow_credit_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -typedef union sh_xnni0_fr_iilb_intra_flow_credit_u { - mmr_t sh_xnni0_fr_iilb_intra_flow_credit_regval; - struct { - mmr_t vc0_test : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_2 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 17; - } sh_xnni0_fr_iilb_intra_flow_credit_s; -} sh_xnni0_fr_iilb_intra_flow_credit_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI0_0_INTRANI_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni0_0_intrani_flow_u { - mmr_t sh_xnni0_0_intrani_flow_regval; - struct { - mmr_t debit_vc0_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_1 : 56; - } sh_xnni0_0_intrani_flow_s; -} sh_xnni0_0_intrani_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI0_1_INTRANI_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni0_1_intrani_flow_u { - mmr_t sh_xnni0_1_intrani_flow_regval; - struct { - mmr_t debit_vc1_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t debit_vc1_force_cred : 1; - mmr_t reserved_1 : 56; - } sh_xnni0_1_intrani_flow_s; -} sh_xnni0_1_intrani_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI0_2_INTRANI_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni0_2_intrani_flow_u { - mmr_t sh_xnni0_2_intrani_flow_regval; - struct { - mmr_t debit_vc2_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_1 : 56; - } sh_xnni0_2_intrani_flow_s; -} sh_xnni0_2_intrani_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI0_3_INTRANI_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni0_3_intrani_flow_u { - mmr_t sh_xnni0_3_intrani_flow_regval; - struct { - mmr_t debit_vc3_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t debit_vc3_force_cred : 1; - mmr_t reserved_1 : 56; - } sh_xnni0_3_intrani_flow_s; -} sh_xnni0_3_intrani_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI0_VCSWITCH_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni0_vcswitch_flow_u { - mmr_t sh_xnni0_vcswitch_flow_regval; - struct { - mmr_t ni_vcfifo_dateline_switch : 1; - mmr_t reserved_0 : 7; - mmr_t pi_vcfifo_switch : 1; - mmr_t reserved_1 : 7; - mmr_t md_vcfifo_switch : 1; - mmr_t reserved_2 : 7; - mmr_t iilb_vcfifo_switch : 1; - mmr_t reserved_3 : 7; - mmr_t disable_sync_bypass_in : 1; - mmr_t disable_sync_bypass_out : 1; - mmr_t async_fifoes : 1; - mmr_t reserved_4 : 29; - } sh_xnni0_vcswitch_flow_s; -} sh_xnni0_vcswitch_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI0_TIMER_REG" */ -/* ==================================================================== */ - -typedef union sh_xnni0_timer_reg_u { - mmr_t sh_xnni0_timer_reg_regval; - struct { - mmr_t timeout_reg : 24; - mmr_t reserved_0 : 8; - mmr_t linkcleanup_reg : 1; - mmr_t reserved_1 : 31; - } sh_xnni0_timer_reg_s; -} sh_xnni0_timer_reg_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI0_FIFO02_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni0_fifo02_flow_u { - mmr_t sh_xnni0_fifo02_flow_regval; - struct { - mmr_t count_vc0_limit : 4; - mmr_t reserved_0 : 4; - mmr_t count_vc0_dyn : 4; - mmr_t reserved_1 : 4; - mmr_t count_vc0_cap : 4; - mmr_t reserved_2 : 4; - mmr_t count_vc2_limit : 4; - mmr_t reserved_3 : 4; - mmr_t count_vc2_dyn : 4; - mmr_t reserved_4 : 4; - mmr_t count_vc2_cap : 4; - mmr_t reserved_5 : 20; - } sh_xnni0_fifo02_flow_s; -} sh_xnni0_fifo02_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI0_FIFO13_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni0_fifo13_flow_u { - mmr_t sh_xnni0_fifo13_flow_regval; - struct { - mmr_t count_vc1_limit : 4; - mmr_t reserved_0 : 4; - mmr_t count_vc1_dyn : 4; - mmr_t reserved_1 : 4; - mmr_t count_vc1_cap : 4; - mmr_t reserved_2 : 4; - mmr_t count_vc3_limit : 4; - mmr_t reserved_3 : 4; - mmr_t count_vc3_dyn : 4; - mmr_t reserved_4 : 4; - mmr_t count_vc3_cap : 4; - mmr_t reserved_5 : 20; - } sh_xnni0_fifo13_flow_s; -} sh_xnni0_fifo13_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI0_NI_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni0_ni_flow_u { - mmr_t sh_xnni0_ni_flow_regval; - struct { - mmr_t vc0_limit : 4; - mmr_t reserved_0 : 4; - mmr_t vc0_dyn : 4; - mmr_t vc0_cap : 4; - mmr_t vc1_limit : 4; - mmr_t reserved_1 : 4; - mmr_t vc1_dyn : 4; - mmr_t vc1_cap : 4; - mmr_t vc2_limit : 4; - mmr_t reserved_2 : 4; - mmr_t vc2_dyn : 4; - mmr_t vc2_cap : 4; - mmr_t vc3_limit : 4; - mmr_t reserved_3 : 4; - mmr_t vc3_dyn : 4; - mmr_t vc3_cap : 4; - } sh_xnni0_ni_flow_s; -} sh_xnni0_ni_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI0_DEAD_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni0_dead_flow_u { - mmr_t sh_xnni0_dead_flow_regval; - struct { - mmr_t vc0_limit : 4; - mmr_t reserved_0 : 4; - mmr_t vc0_dyn : 4; - mmr_t vc0_cap : 4; - mmr_t vc1_limit : 4; - mmr_t reserved_1 : 4; - mmr_t vc1_dyn : 4; - mmr_t vc1_cap : 4; - mmr_t vc2_limit : 4; - mmr_t reserved_2 : 4; - mmr_t vc2_dyn : 4; - mmr_t vc2_cap : 4; - mmr_t vc3_limit : 4; - mmr_t reserved_3 : 4; - mmr_t vc3_dyn : 4; - mmr_t vc3_cap : 4; - } sh_xnni0_dead_flow_s; -} sh_xnni0_dead_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI0_INJECT_AGE" */ -/* ==================================================================== */ - -typedef union sh_xnni0_inject_age_u { - mmr_t sh_xnni0_inject_age_regval; - struct { - mmr_t request_inject : 8; - mmr_t reply_inject : 8; - mmr_t reserved_0 : 48; - } sh_xnni0_inject_age_s; -} sh_xnni0_inject_age_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -typedef union sh_xnni1_to_pi_intra_flow_debit_u { - mmr_t sh_xnni1_to_pi_intra_flow_debit_regval; - struct { - mmr_t vc0_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t vc0_force_cred : 1; - mmr_t vc2_withhold : 6; - mmr_t reserved_1 : 1; - mmr_t vc2_force_cred : 1; - mmr_t reserved_2 : 8; - mmr_t vc0_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_4 : 9; - mmr_t vc2_dyn : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_6 : 1; - } sh_xnni1_to_pi_intra_flow_debit_s; -} sh_xnni1_to_pi_intra_flow_debit_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -typedef union sh_xnni1_to_md_intra_flow_debit_u { - mmr_t sh_xnni1_to_md_intra_flow_debit_regval; - struct { - mmr_t vc0_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t vc0_force_cred : 1; - mmr_t vc2_withhold : 6; - mmr_t reserved_1 : 1; - mmr_t vc2_force_cred : 1; - mmr_t reserved_2 : 8; - mmr_t vc0_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_4 : 9; - mmr_t vc2_dyn : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_6 : 1; - } sh_xnni1_to_md_intra_flow_debit_s; -} sh_xnni1_to_md_intra_flow_debit_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -typedef union sh_xnni1_to_iilb_intra_flow_debit_u { - mmr_t sh_xnni1_to_iilb_intra_flow_debit_regval; - struct { - mmr_t vc0_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t vc0_force_cred : 1; - mmr_t vc2_withhold : 6; - mmr_t reserved_1 : 1; - mmr_t vc2_force_cred : 1; - mmr_t reserved_2 : 8; - mmr_t vc0_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_4 : 9; - mmr_t vc2_dyn : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_6 : 1; - } sh_xnni1_to_iilb_intra_flow_debit_s; -} sh_xnni1_to_iilb_intra_flow_debit_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -typedef union sh_xnni1_fr_pi_intra_flow_credit_u { - mmr_t sh_xnni1_fr_pi_intra_flow_credit_regval; - struct { - mmr_t vc0_test : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_2 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 17; - } sh_xnni1_fr_pi_intra_flow_credit_s; -} sh_xnni1_fr_pi_intra_flow_credit_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -typedef union sh_xnni1_fr_md_intra_flow_credit_u { - mmr_t sh_xnni1_fr_md_intra_flow_credit_regval; - struct { - mmr_t vc0_test : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_2 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 17; - } sh_xnni1_fr_md_intra_flow_credit_s; -} sh_xnni1_fr_md_intra_flow_credit_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -typedef union sh_xnni1_fr_iilb_intra_flow_credit_u { - mmr_t sh_xnni1_fr_iilb_intra_flow_credit_regval; - struct { - mmr_t vc0_test : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_2 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 17; - } sh_xnni1_fr_iilb_intra_flow_credit_s; -} sh_xnni1_fr_iilb_intra_flow_credit_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI1_0_INTRANI_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni1_0_intrani_flow_u { - mmr_t sh_xnni1_0_intrani_flow_regval; - struct { - mmr_t debit_vc0_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_1 : 56; - } sh_xnni1_0_intrani_flow_s; -} sh_xnni1_0_intrani_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI1_1_INTRANI_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni1_1_intrani_flow_u { - mmr_t sh_xnni1_1_intrani_flow_regval; - struct { - mmr_t debit_vc1_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t debit_vc1_force_cred : 1; - mmr_t reserved_1 : 56; - } sh_xnni1_1_intrani_flow_s; -} sh_xnni1_1_intrani_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI1_2_INTRANI_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni1_2_intrani_flow_u { - mmr_t sh_xnni1_2_intrani_flow_regval; - struct { - mmr_t debit_vc2_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_1 : 56; - } sh_xnni1_2_intrani_flow_s; -} sh_xnni1_2_intrani_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI1_3_INTRANI_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni1_3_intrani_flow_u { - mmr_t sh_xnni1_3_intrani_flow_regval; - struct { - mmr_t debit_vc3_withhold : 6; - mmr_t reserved_0 : 1; - mmr_t debit_vc3_force_cred : 1; - mmr_t reserved_1 : 56; - } sh_xnni1_3_intrani_flow_s; -} sh_xnni1_3_intrani_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI1_VCSWITCH_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni1_vcswitch_flow_u { - mmr_t sh_xnni1_vcswitch_flow_regval; - struct { - mmr_t ni_vcfifo_dateline_switch : 1; - mmr_t reserved_0 : 7; - mmr_t pi_vcfifo_switch : 1; - mmr_t reserved_1 : 7; - mmr_t md_vcfifo_switch : 1; - mmr_t reserved_2 : 7; - mmr_t iilb_vcfifo_switch : 1; - mmr_t reserved_3 : 7; - mmr_t disable_sync_bypass_in : 1; - mmr_t disable_sync_bypass_out : 1; - mmr_t async_fifoes : 1; - mmr_t reserved_4 : 29; - } sh_xnni1_vcswitch_flow_s; -} sh_xnni1_vcswitch_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI1_TIMER_REG" */ -/* ==================================================================== */ - -typedef union sh_xnni1_timer_reg_u { - mmr_t sh_xnni1_timer_reg_regval; - struct { - mmr_t timeout_reg : 24; - mmr_t reserved_0 : 8; - mmr_t linkcleanup_reg : 1; - mmr_t reserved_1 : 31; - } sh_xnni1_timer_reg_s; -} sh_xnni1_timer_reg_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI1_FIFO02_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni1_fifo02_flow_u { - mmr_t sh_xnni1_fifo02_flow_regval; - struct { - mmr_t count_vc0_limit : 4; - mmr_t reserved_0 : 4; - mmr_t count_vc0_dyn : 4; - mmr_t reserved_1 : 4; - mmr_t count_vc0_cap : 4; - mmr_t reserved_2 : 4; - mmr_t count_vc2_limit : 4; - mmr_t reserved_3 : 4; - mmr_t count_vc2_dyn : 4; - mmr_t reserved_4 : 4; - mmr_t count_vc2_cap : 4; - mmr_t reserved_5 : 20; - } sh_xnni1_fifo02_flow_s; -} sh_xnni1_fifo02_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI1_FIFO13_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni1_fifo13_flow_u { - mmr_t sh_xnni1_fifo13_flow_regval; - struct { - mmr_t count_vc1_limit : 4; - mmr_t reserved_0 : 4; - mmr_t count_vc1_dyn : 4; - mmr_t reserved_1 : 4; - mmr_t count_vc1_cap : 4; - mmr_t reserved_2 : 4; - mmr_t count_vc3_limit : 4; - mmr_t reserved_3 : 4; - mmr_t count_vc3_dyn : 4; - mmr_t reserved_4 : 4; - mmr_t count_vc3_cap : 4; - mmr_t reserved_5 : 20; - } sh_xnni1_fifo13_flow_s; -} sh_xnni1_fifo13_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI1_NI_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni1_ni_flow_u { - mmr_t sh_xnni1_ni_flow_regval; - struct { - mmr_t vc0_limit : 4; - mmr_t reserved_0 : 4; - mmr_t vc0_dyn : 4; - mmr_t vc0_cap : 4; - mmr_t vc1_limit : 4; - mmr_t reserved_1 : 4; - mmr_t vc1_dyn : 4; - mmr_t vc1_cap : 4; - mmr_t vc2_limit : 4; - mmr_t reserved_2 : 4; - mmr_t vc2_dyn : 4; - mmr_t vc2_cap : 4; - mmr_t vc3_limit : 4; - mmr_t reserved_3 : 4; - mmr_t vc3_dyn : 4; - mmr_t vc3_cap : 4; - } sh_xnni1_ni_flow_s; -} sh_xnni1_ni_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI1_DEAD_FLOW" */ -/* ==================================================================== */ - -typedef union sh_xnni1_dead_flow_u { - mmr_t sh_xnni1_dead_flow_regval; - struct { - mmr_t vc0_limit : 4; - mmr_t reserved_0 : 4; - mmr_t vc0_dyn : 4; - mmr_t vc0_cap : 4; - mmr_t vc1_limit : 4; - mmr_t reserved_1 : 4; - mmr_t vc1_dyn : 4; - mmr_t vc1_cap : 4; - mmr_t vc2_limit : 4; - mmr_t reserved_2 : 4; - mmr_t vc2_dyn : 4; - mmr_t vc2_cap : 4; - mmr_t vc3_limit : 4; - mmr_t reserved_3 : 4; - mmr_t vc3_dyn : 4; - mmr_t vc3_cap : 4; - } sh_xnni1_dead_flow_s; -} sh_xnni1_dead_flow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNNI1_INJECT_AGE" */ -/* ==================================================================== */ - -typedef union sh_xnni1_inject_age_u { - mmr_t sh_xnni1_inject_age_regval; - struct { - mmr_t request_inject : 8; - mmr_t reply_inject : 8; - mmr_t reserved_0 : 48; - } sh_xnni1_inject_age_s; -} sh_xnni1_inject_age_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_DEBUG_SEL" */ -/* XN Debug Port Select */ -/* ==================================================================== */ - -typedef union sh_xn_debug_sel_u { - mmr_t sh_xn_debug_sel_regval; - struct { - mmr_t nibble0_rlm_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble1_rlm_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble2_rlm_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble3_rlm_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble4_rlm_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble5_rlm_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble6_rlm_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble7_rlm_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t trigger_enable : 1; - } sh_xn_debug_sel_s; -} sh_xn_debug_sel_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_DEBUG_TRIG_SEL" */ -/* XN Debug trigger Select */ -/* ==================================================================== */ - -typedef union sh_xn_debug_trig_sel_u { - mmr_t sh_xn_debug_trig_sel_regval; - struct { - mmr_t trigger0_rlm_sel : 3; - mmr_t reserved_0 : 1; - mmr_t trigger0_nibble_sel : 3; - mmr_t reserved_1 : 1; - mmr_t trigger1_rlm_sel : 3; - mmr_t reserved_2 : 1; - mmr_t trigger1_nibble_sel : 3; - mmr_t reserved_3 : 1; - mmr_t trigger2_rlm_sel : 3; - mmr_t reserved_4 : 1; - mmr_t trigger2_nibble_sel : 3; - mmr_t reserved_5 : 1; - mmr_t trigger3_rlm_sel : 3; - mmr_t reserved_6 : 1; - mmr_t trigger3_nibble_sel : 3; - mmr_t reserved_7 : 1; - mmr_t trigger4_rlm_sel : 3; - mmr_t reserved_8 : 1; - mmr_t trigger4_nibble_sel : 3; - mmr_t reserved_9 : 1; - mmr_t trigger5_rlm_sel : 3; - mmr_t reserved_10 : 1; - mmr_t trigger5_nibble_sel : 3; - mmr_t reserved_11 : 1; - mmr_t trigger6_rlm_sel : 3; - mmr_t reserved_12 : 1; - mmr_t trigger6_nibble_sel : 3; - mmr_t reserved_13 : 1; - mmr_t trigger7_rlm_sel : 3; - mmr_t reserved_14 : 1; - mmr_t trigger7_nibble_sel : 3; - mmr_t reserved_15 : 1; - } sh_xn_debug_trig_sel_s; -} sh_xn_debug_trig_sel_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_TRIGGER_COMPARE" */ -/* XN Debug Compare */ -/* ==================================================================== */ - -typedef union sh_xn_trigger_compare_u { - mmr_t sh_xn_trigger_compare_regval; - struct { - mmr_t mask : 32; - mmr_t reserved_0 : 32; - } sh_xn_trigger_compare_s; -} sh_xn_trigger_compare_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_TRIGGER_DATA" */ -/* XN Debug Compare Data */ -/* ==================================================================== */ - -typedef union sh_xn_trigger_data_u { - mmr_t sh_xn_trigger_data_regval; - struct { - mmr_t compare_pattern : 32; - mmr_t reserved_0 : 32; - } sh_xn_trigger_data_s; -} sh_xn_trigger_data_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_IILB_DEBUG_SEL" */ -/* XN IILB Debug Port Select */ -/* ==================================================================== */ - -typedef union sh_xn_iilb_debug_sel_u { - mmr_t sh_xn_iilb_debug_sel_regval; - struct { - mmr_t nibble0_input_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble1_input_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble2_input_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble3_input_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble4_input_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble5_input_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble6_input_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble7_input_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t reserved_15 : 1; - } sh_xn_iilb_debug_sel_s; -} sh_xn_iilb_debug_sel_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_PI_DEBUG_SEL" */ -/* XN PI Debug Port Select */ -/* ==================================================================== */ - -typedef union sh_xn_pi_debug_sel_u { - mmr_t sh_xn_pi_debug_sel_regval; - struct { - mmr_t nibble0_input_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble1_input_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble2_input_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble3_input_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble4_input_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble5_input_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble6_input_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble7_input_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t reserved_15 : 1; - } sh_xn_pi_debug_sel_s; -} sh_xn_pi_debug_sel_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_MD_DEBUG_SEL" */ -/* XN MD Debug Port Select */ -/* ==================================================================== */ - -typedef union sh_xn_md_debug_sel_u { - mmr_t sh_xn_md_debug_sel_regval; - struct { - mmr_t nibble0_input_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble1_input_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble2_input_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble3_input_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble4_input_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble5_input_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble6_input_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble7_input_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t reserved_15 : 1; - } sh_xn_md_debug_sel_s; -} sh_xn_md_debug_sel_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI0_DEBUG_SEL" */ -/* XN NI0 Debug Port Select */ -/* ==================================================================== */ - -typedef union sh_xn_ni0_debug_sel_u { - mmr_t sh_xn_ni0_debug_sel_regval; - struct { - mmr_t nibble0_input_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble1_input_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble2_input_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble3_input_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble4_input_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble5_input_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble6_input_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble7_input_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t reserved_15 : 1; - } sh_xn_ni0_debug_sel_s; -} sh_xn_ni0_debug_sel_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI1_DEBUG_SEL" */ -/* XN NI1 Debug Port Select */ -/* ==================================================================== */ - -typedef union sh_xn_ni1_debug_sel_u { - mmr_t sh_xn_ni1_debug_sel_regval; - struct { - mmr_t nibble0_input_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble1_input_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble2_input_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble3_input_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble4_input_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble5_input_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble6_input_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble7_input_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t reserved_15 : 1; - } sh_xn_ni1_debug_sel_s; -} sh_xn_ni1_debug_sel_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_IILB_LB_CMP_EXP_DATA0" */ -/* IILB compare LB input expected data0 */ -/* ==================================================================== */ - -typedef union sh_xn_iilb_lb_cmp_exp_data0_u { - mmr_t sh_xn_iilb_lb_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_lb_cmp_exp_data0_s; -} sh_xn_iilb_lb_cmp_exp_data0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_IILB_LB_CMP_EXP_DATA1" */ -/* IILB compare LB input expected data1 */ -/* ==================================================================== */ - -typedef union sh_xn_iilb_lb_cmp_exp_data1_u { - mmr_t sh_xn_iilb_lb_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_lb_cmp_exp_data1_s; -} sh_xn_iilb_lb_cmp_exp_data1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_IILB_LB_CMP_ENABLE0" */ -/* IILB compare LB input enable0 */ -/* ==================================================================== */ - -typedef union sh_xn_iilb_lb_cmp_enable0_u { - mmr_t sh_xn_iilb_lb_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_lb_cmp_enable0_s; -} sh_xn_iilb_lb_cmp_enable0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_IILB_LB_CMP_ENABLE1" */ -/* IILB compare LB input enable1 */ -/* ==================================================================== */ - -typedef union sh_xn_iilb_lb_cmp_enable1_u { - mmr_t sh_xn_iilb_lb_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_lb_cmp_enable1_s; -} sh_xn_iilb_lb_cmp_enable1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_IILB_II_CMP_EXP_DATA0" */ -/* IILB compare II input expected data0 */ -/* ==================================================================== */ - -typedef union sh_xn_iilb_ii_cmp_exp_data0_u { - mmr_t sh_xn_iilb_ii_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_ii_cmp_exp_data0_s; -} sh_xn_iilb_ii_cmp_exp_data0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_IILB_II_CMP_EXP_DATA1" */ -/* IILB compare II input expected data1 */ -/* ==================================================================== */ - -typedef union sh_xn_iilb_ii_cmp_exp_data1_u { - mmr_t sh_xn_iilb_ii_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_ii_cmp_exp_data1_s; -} sh_xn_iilb_ii_cmp_exp_data1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_IILB_II_CMP_ENABLE0" */ -/* IILB compare II input enable0 */ -/* ==================================================================== */ - -typedef union sh_xn_iilb_ii_cmp_enable0_u { - mmr_t sh_xn_iilb_ii_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_ii_cmp_enable0_s; -} sh_xn_iilb_ii_cmp_enable0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_IILB_II_CMP_ENABLE1" */ -/* IILB compare II input enable1 */ -/* ==================================================================== */ - -typedef union sh_xn_iilb_ii_cmp_enable1_u { - mmr_t sh_xn_iilb_ii_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_ii_cmp_enable1_s; -} sh_xn_iilb_ii_cmp_enable1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_IILB_MD_CMP_EXP_DATA0" */ -/* IILB compare MD input expected data0 */ -/* ==================================================================== */ - -typedef union sh_xn_iilb_md_cmp_exp_data0_u { - mmr_t sh_xn_iilb_md_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_md_cmp_exp_data0_s; -} sh_xn_iilb_md_cmp_exp_data0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_IILB_MD_CMP_EXP_DATA1" */ -/* IILB compare MD input expected data1 */ -/* ==================================================================== */ - -typedef union sh_xn_iilb_md_cmp_exp_data1_u { - mmr_t sh_xn_iilb_md_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_md_cmp_exp_data1_s; -} sh_xn_iilb_md_cmp_exp_data1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_IILB_MD_CMP_ENABLE0" */ -/* IILB compare MD input enable0 */ -/* ==================================================================== */ - -typedef union sh_xn_iilb_md_cmp_enable0_u { - mmr_t sh_xn_iilb_md_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_md_cmp_enable0_s; -} sh_xn_iilb_md_cmp_enable0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_IILB_MD_CMP_ENABLE1" */ -/* IILB compare MD input enable1 */ -/* ==================================================================== */ - -typedef union sh_xn_iilb_md_cmp_enable1_u { - mmr_t sh_xn_iilb_md_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_md_cmp_enable1_s; -} sh_xn_iilb_md_cmp_enable1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_IILB_PI_CMP_EXP_DATA0" */ -/* IILB compare PI input expected data0 */ -/* ==================================================================== */ - -typedef union sh_xn_iilb_pi_cmp_exp_data0_u { - mmr_t sh_xn_iilb_pi_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_pi_cmp_exp_data0_s; -} sh_xn_iilb_pi_cmp_exp_data0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_IILB_PI_CMP_EXP_DATA1" */ -/* IILB compare PI input expected data1 */ -/* ==================================================================== */ - -typedef union sh_xn_iilb_pi_cmp_exp_data1_u { - mmr_t sh_xn_iilb_pi_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_pi_cmp_exp_data1_s; -} sh_xn_iilb_pi_cmp_exp_data1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_IILB_PI_CMP_ENABLE0" */ -/* IILB compare PI input enable0 */ -/* ==================================================================== */ - -typedef union sh_xn_iilb_pi_cmp_enable0_u { - mmr_t sh_xn_iilb_pi_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_pi_cmp_enable0_s; -} sh_xn_iilb_pi_cmp_enable0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_IILB_PI_CMP_ENABLE1" */ -/* IILB compare PI input enable1 */ -/* ==================================================================== */ - -typedef union sh_xn_iilb_pi_cmp_enable1_u { - mmr_t sh_xn_iilb_pi_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_pi_cmp_enable1_s; -} sh_xn_iilb_pi_cmp_enable1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_IILB_NI0_CMP_EXP_DATA0" */ -/* IILB compare NI0 input expected data0 */ -/* ==================================================================== */ - -typedef union sh_xn_iilb_ni0_cmp_exp_data0_u { - mmr_t sh_xn_iilb_ni0_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_ni0_cmp_exp_data0_s; -} sh_xn_iilb_ni0_cmp_exp_data0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_IILB_NI0_CMP_EXP_DATA1" */ -/* IILB compare NI0 input expected data1 */ -/* ==================================================================== */ - -typedef union sh_xn_iilb_ni0_cmp_exp_data1_u { - mmr_t sh_xn_iilb_ni0_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_ni0_cmp_exp_data1_s; -} sh_xn_iilb_ni0_cmp_exp_data1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_IILB_NI0_CMP_ENABLE0" */ -/* IILB compare NI0 input enable0 */ -/* ==================================================================== */ - -typedef union sh_xn_iilb_ni0_cmp_enable0_u { - mmr_t sh_xn_iilb_ni0_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_ni0_cmp_enable0_s; -} sh_xn_iilb_ni0_cmp_enable0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_IILB_NI0_CMP_ENABLE1" */ -/* IILB compare NI0 input enable1 */ -/* ==================================================================== */ - -typedef union sh_xn_iilb_ni0_cmp_enable1_u { - mmr_t sh_xn_iilb_ni0_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_ni0_cmp_enable1_s; -} sh_xn_iilb_ni0_cmp_enable1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_IILB_NI1_CMP_EXP_DATA0" */ -/* IILB compare NI1 input expected data0 */ -/* ==================================================================== */ - -typedef union sh_xn_iilb_ni1_cmp_exp_data0_u { - mmr_t sh_xn_iilb_ni1_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_ni1_cmp_exp_data0_s; -} sh_xn_iilb_ni1_cmp_exp_data0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_IILB_NI1_CMP_EXP_DATA1" */ -/* IILB compare NI1 input expected data1 */ -/* ==================================================================== */ - -typedef union sh_xn_iilb_ni1_cmp_exp_data1_u { - mmr_t sh_xn_iilb_ni1_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_ni1_cmp_exp_data1_s; -} sh_xn_iilb_ni1_cmp_exp_data1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_IILB_NI1_CMP_ENABLE0" */ -/* IILB compare NI1 input enable0 */ -/* ==================================================================== */ - -typedef union sh_xn_iilb_ni1_cmp_enable0_u { - mmr_t sh_xn_iilb_ni1_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_ni1_cmp_enable0_s; -} sh_xn_iilb_ni1_cmp_enable0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_IILB_NI1_CMP_ENABLE1" */ -/* IILB compare NI1 input enable1 */ -/* ==================================================================== */ - -typedef union sh_xn_iilb_ni1_cmp_enable1_u { - mmr_t sh_xn_iilb_ni1_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_ni1_cmp_enable1_s; -} sh_xn_iilb_ni1_cmp_enable1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_MD_IILB_CMP_EXP_DATA0" */ -/* MD compare IILB input expected data0 */ -/* ==================================================================== */ - -typedef union sh_xn_md_iilb_cmp_exp_data0_u { - mmr_t sh_xn_md_iilb_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_md_iilb_cmp_exp_data0_s; -} sh_xn_md_iilb_cmp_exp_data0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_MD_IILB_CMP_EXP_DATA1" */ -/* MD compare IILB input expected data1 */ -/* ==================================================================== */ - -typedef union sh_xn_md_iilb_cmp_exp_data1_u { - mmr_t sh_xn_md_iilb_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_md_iilb_cmp_exp_data1_s; -} sh_xn_md_iilb_cmp_exp_data1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_MD_IILB_CMP_ENABLE0" */ -/* MD compare IILB input enable0 */ -/* ==================================================================== */ - -typedef union sh_xn_md_iilb_cmp_enable0_u { - mmr_t sh_xn_md_iilb_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_md_iilb_cmp_enable0_s; -} sh_xn_md_iilb_cmp_enable0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_MD_IILB_CMP_ENABLE1" */ -/* MD compare IILB input enable1 */ -/* ==================================================================== */ - -typedef union sh_xn_md_iilb_cmp_enable1_u { - mmr_t sh_xn_md_iilb_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_md_iilb_cmp_enable1_s; -} sh_xn_md_iilb_cmp_enable1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_MD_NI0_CMP_EXP_DATA0" */ -/* MD compare NI0 input expected data0 */ -/* ==================================================================== */ - -typedef union sh_xn_md_ni0_cmp_exp_data0_u { - mmr_t sh_xn_md_ni0_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_md_ni0_cmp_exp_data0_s; -} sh_xn_md_ni0_cmp_exp_data0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_MD_NI0_CMP_EXP_DATA1" */ -/* MD compare NI0 input expected data1 */ -/* ==================================================================== */ - -typedef union sh_xn_md_ni0_cmp_exp_data1_u { - mmr_t sh_xn_md_ni0_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_md_ni0_cmp_exp_data1_s; -} sh_xn_md_ni0_cmp_exp_data1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_MD_NI0_CMP_ENABLE0" */ -/* MD compare NI0 input enable0 */ -/* ==================================================================== */ - -typedef union sh_xn_md_ni0_cmp_enable0_u { - mmr_t sh_xn_md_ni0_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_md_ni0_cmp_enable0_s; -} sh_xn_md_ni0_cmp_enable0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_MD_NI0_CMP_ENABLE1" */ -/* MD compare NI0 input enable1 */ -/* ==================================================================== */ - -typedef union sh_xn_md_ni0_cmp_enable1_u { - mmr_t sh_xn_md_ni0_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_md_ni0_cmp_enable1_s; -} sh_xn_md_ni0_cmp_enable1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_MD_NI1_CMP_EXP_DATA0" */ -/* MD compare NI1 input expected data0 */ -/* ==================================================================== */ - -typedef union sh_xn_md_ni1_cmp_exp_data0_u { - mmr_t sh_xn_md_ni1_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_md_ni1_cmp_exp_data0_s; -} sh_xn_md_ni1_cmp_exp_data0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_MD_NI1_CMP_EXP_DATA1" */ -/* MD compare NI1 input expected data1 */ -/* ==================================================================== */ - -typedef union sh_xn_md_ni1_cmp_exp_data1_u { - mmr_t sh_xn_md_ni1_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_md_ni1_cmp_exp_data1_s; -} sh_xn_md_ni1_cmp_exp_data1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_MD_NI1_CMP_ENABLE0" */ -/* MD compare NI1 input enable0 */ -/* ==================================================================== */ - -typedef union sh_xn_md_ni1_cmp_enable0_u { - mmr_t sh_xn_md_ni1_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_md_ni1_cmp_enable0_s; -} sh_xn_md_ni1_cmp_enable0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_MD_NI1_CMP_ENABLE1" */ -/* MD compare NI1 input enable1 */ -/* ==================================================================== */ - -typedef union sh_xn_md_ni1_cmp_enable1_u { - mmr_t sh_xn_md_ni1_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_md_ni1_cmp_enable1_s; -} sh_xn_md_ni1_cmp_enable1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_EXP_HDR0" */ -/* MD compare SIC input expected header0 */ -/* ==================================================================== */ - -typedef union sh_xn_md_sic_cmp_exp_hdr0_u { - mmr_t sh_xn_md_sic_cmp_exp_hdr0_regval; - struct { - mmr_t data : 64; - } sh_xn_md_sic_cmp_exp_hdr0_s; -} sh_xn_md_sic_cmp_exp_hdr0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_EXP_HDR1" */ -/* MD compare SIC input expected header1 */ -/* ==================================================================== */ - -typedef union sh_xn_md_sic_cmp_exp_hdr1_u { - mmr_t sh_xn_md_sic_cmp_exp_hdr1_regval; - struct { - mmr_t data : 42; - mmr_t reserved_0 : 22; - } sh_xn_md_sic_cmp_exp_hdr1_s; -} sh_xn_md_sic_cmp_exp_hdr1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_HDR_ENABLE0" */ -/* MD compare SIC header enable0 */ -/* ==================================================================== */ - -typedef union sh_xn_md_sic_cmp_hdr_enable0_u { - mmr_t sh_xn_md_sic_cmp_hdr_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_md_sic_cmp_hdr_enable0_s; -} sh_xn_md_sic_cmp_hdr_enable0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_HDR_ENABLE1" */ -/* MD compare SIC header enable1 */ -/* ==================================================================== */ - -typedef union sh_xn_md_sic_cmp_hdr_enable1_u { - mmr_t sh_xn_md_sic_cmp_hdr_enable1_regval; - struct { - mmr_t enable : 42; - mmr_t reserved_0 : 22; - } sh_xn_md_sic_cmp_hdr_enable1_s; -} sh_xn_md_sic_cmp_hdr_enable1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_DATA0" */ -/* MD compare SIC data0 */ -/* ==================================================================== */ - -typedef union sh_xn_md_sic_cmp_data0_u { - mmr_t sh_xn_md_sic_cmp_data0_regval; - struct { - mmr_t data0 : 64; - } sh_xn_md_sic_cmp_data0_s; -} sh_xn_md_sic_cmp_data0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_DATA1" */ -/* MD compare SIC data1 */ -/* ==================================================================== */ - -typedef union sh_xn_md_sic_cmp_data1_u { - mmr_t sh_xn_md_sic_cmp_data1_regval; - struct { - mmr_t data1 : 64; - } sh_xn_md_sic_cmp_data1_s; -} sh_xn_md_sic_cmp_data1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_DATA2" */ -/* MD compare SIC data2 */ -/* ==================================================================== */ - -typedef union sh_xn_md_sic_cmp_data2_u { - mmr_t sh_xn_md_sic_cmp_data2_regval; - struct { - mmr_t data2 : 64; - } sh_xn_md_sic_cmp_data2_s; -} sh_xn_md_sic_cmp_data2_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_DATA3" */ -/* MD compare SIC data3 */ -/* ==================================================================== */ - -typedef union sh_xn_md_sic_cmp_data3_u { - mmr_t sh_xn_md_sic_cmp_data3_regval; - struct { - mmr_t data3 : 64; - } sh_xn_md_sic_cmp_data3_s; -} sh_xn_md_sic_cmp_data3_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE0" */ -/* MD enable compare SIC data0 */ -/* ==================================================================== */ - -typedef union sh_xn_md_sic_cmp_data_enable0_u { - mmr_t sh_xn_md_sic_cmp_data_enable0_regval; - struct { - mmr_t data_enable0 : 64; - } sh_xn_md_sic_cmp_data_enable0_s; -} sh_xn_md_sic_cmp_data_enable0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE1" */ -/* MD enable compare SIC data1 */ -/* ==================================================================== */ - -typedef union sh_xn_md_sic_cmp_data_enable1_u { - mmr_t sh_xn_md_sic_cmp_data_enable1_regval; - struct { - mmr_t data_enable1 : 64; - } sh_xn_md_sic_cmp_data_enable1_s; -} sh_xn_md_sic_cmp_data_enable1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE2" */ -/* MD enable compare SIC data2 */ -/* ==================================================================== */ - -typedef union sh_xn_md_sic_cmp_data_enable2_u { - mmr_t sh_xn_md_sic_cmp_data_enable2_regval; - struct { - mmr_t data_enable2 : 64; - } sh_xn_md_sic_cmp_data_enable2_s; -} sh_xn_md_sic_cmp_data_enable2_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE3" */ -/* MD enable compare SIC data3 */ -/* ==================================================================== */ - -typedef union sh_xn_md_sic_cmp_data_enable3_u { - mmr_t sh_xn_md_sic_cmp_data_enable3_regval; - struct { - mmr_t data_enable3 : 64; - } sh_xn_md_sic_cmp_data_enable3_s; -} sh_xn_md_sic_cmp_data_enable3_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_PI_IILB_CMP_EXP_DATA0" */ -/* PI compare IILB input expected data0 */ -/* ==================================================================== */ - -typedef union sh_xn_pi_iilb_cmp_exp_data0_u { - mmr_t sh_xn_pi_iilb_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_pi_iilb_cmp_exp_data0_s; -} sh_xn_pi_iilb_cmp_exp_data0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_PI_IILB_CMP_EXP_DATA1" */ -/* PI compare IILB input expected data1 */ -/* ==================================================================== */ - -typedef union sh_xn_pi_iilb_cmp_exp_data1_u { - mmr_t sh_xn_pi_iilb_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_pi_iilb_cmp_exp_data1_s; -} sh_xn_pi_iilb_cmp_exp_data1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_PI_IILB_CMP_ENABLE0" */ -/* PI compare IILB input enable0 */ -/* ==================================================================== */ - -typedef union sh_xn_pi_iilb_cmp_enable0_u { - mmr_t sh_xn_pi_iilb_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_pi_iilb_cmp_enable0_s; -} sh_xn_pi_iilb_cmp_enable0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_PI_IILB_CMP_ENABLE1" */ -/* PI compare IILB input enable1 */ -/* ==================================================================== */ - -typedef union sh_xn_pi_iilb_cmp_enable1_u { - mmr_t sh_xn_pi_iilb_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_pi_iilb_cmp_enable1_s; -} sh_xn_pi_iilb_cmp_enable1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_PI_NI0_CMP_EXP_DATA0" */ -/* PI compare NI0 input expected data0 */ -/* ==================================================================== */ - -typedef union sh_xn_pi_ni0_cmp_exp_data0_u { - mmr_t sh_xn_pi_ni0_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_pi_ni0_cmp_exp_data0_s; -} sh_xn_pi_ni0_cmp_exp_data0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_PI_NI0_CMP_EXP_DATA1" */ -/* PI compare NI0 input expected data1 */ -/* ==================================================================== */ - -typedef union sh_xn_pi_ni0_cmp_exp_data1_u { - mmr_t sh_xn_pi_ni0_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_pi_ni0_cmp_exp_data1_s; -} sh_xn_pi_ni0_cmp_exp_data1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_PI_NI0_CMP_ENABLE0" */ -/* PI compare NI0 input enable0 */ -/* ==================================================================== */ - -typedef union sh_xn_pi_ni0_cmp_enable0_u { - mmr_t sh_xn_pi_ni0_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_pi_ni0_cmp_enable0_s; -} sh_xn_pi_ni0_cmp_enable0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_PI_NI0_CMP_ENABLE1" */ -/* PI compare NI0 input enable1 */ -/* ==================================================================== */ - -typedef union sh_xn_pi_ni0_cmp_enable1_u { - mmr_t sh_xn_pi_ni0_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_pi_ni0_cmp_enable1_s; -} sh_xn_pi_ni0_cmp_enable1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_PI_NI1_CMP_EXP_DATA0" */ -/* PI compare NI1 input expected data0 */ -/* ==================================================================== */ - -typedef union sh_xn_pi_ni1_cmp_exp_data0_u { - mmr_t sh_xn_pi_ni1_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_pi_ni1_cmp_exp_data0_s; -} sh_xn_pi_ni1_cmp_exp_data0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_PI_NI1_CMP_EXP_DATA1" */ -/* PI compare NI1 input expected data1 */ -/* ==================================================================== */ - -typedef union sh_xn_pi_ni1_cmp_exp_data1_u { - mmr_t sh_xn_pi_ni1_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_pi_ni1_cmp_exp_data1_s; -} sh_xn_pi_ni1_cmp_exp_data1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_PI_NI1_CMP_ENABLE0" */ -/* PI compare NI1 input enable0 */ -/* ==================================================================== */ - -typedef union sh_xn_pi_ni1_cmp_enable0_u { - mmr_t sh_xn_pi_ni1_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_pi_ni1_cmp_enable0_s; -} sh_xn_pi_ni1_cmp_enable0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_PI_NI1_CMP_ENABLE1" */ -/* PI compare NI1 input enable1 */ -/* ==================================================================== */ - -typedef union sh_xn_pi_ni1_cmp_enable1_u { - mmr_t sh_xn_pi_ni1_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_pi_ni1_cmp_enable1_s; -} sh_xn_pi_ni1_cmp_enable1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_EXP_HDR0" */ -/* PI compare SIC input expected header0 */ -/* ==================================================================== */ - -typedef union sh_xn_pi_sic_cmp_exp_hdr0_u { - mmr_t sh_xn_pi_sic_cmp_exp_hdr0_regval; - struct { - mmr_t data : 64; - } sh_xn_pi_sic_cmp_exp_hdr0_s; -} sh_xn_pi_sic_cmp_exp_hdr0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_EXP_HDR1" */ -/* PI compare SIC input expected header1 */ -/* ==================================================================== */ - -typedef union sh_xn_pi_sic_cmp_exp_hdr1_u { - mmr_t sh_xn_pi_sic_cmp_exp_hdr1_regval; - struct { - mmr_t data : 42; - mmr_t reserved_0 : 22; - } sh_xn_pi_sic_cmp_exp_hdr1_s; -} sh_xn_pi_sic_cmp_exp_hdr1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_HDR_ENABLE0" */ -/* PI compare SIC header enable0 */ -/* ==================================================================== */ - -typedef union sh_xn_pi_sic_cmp_hdr_enable0_u { - mmr_t sh_xn_pi_sic_cmp_hdr_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_pi_sic_cmp_hdr_enable0_s; -} sh_xn_pi_sic_cmp_hdr_enable0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_HDR_ENABLE1" */ -/* PI compare SIC header enable1 */ -/* ==================================================================== */ - -typedef union sh_xn_pi_sic_cmp_hdr_enable1_u { - mmr_t sh_xn_pi_sic_cmp_hdr_enable1_regval; - struct { - mmr_t enable : 42; - mmr_t reserved_0 : 22; - } sh_xn_pi_sic_cmp_hdr_enable1_s; -} sh_xn_pi_sic_cmp_hdr_enable1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_DATA0" */ -/* PI compare SIC data0 */ -/* ==================================================================== */ - -typedef union sh_xn_pi_sic_cmp_data0_u { - mmr_t sh_xn_pi_sic_cmp_data0_regval; - struct { - mmr_t data0 : 64; - } sh_xn_pi_sic_cmp_data0_s; -} sh_xn_pi_sic_cmp_data0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_DATA1" */ -/* PI compare SIC data1 */ -/* ==================================================================== */ - -typedef union sh_xn_pi_sic_cmp_data1_u { - mmr_t sh_xn_pi_sic_cmp_data1_regval; - struct { - mmr_t data1 : 64; - } sh_xn_pi_sic_cmp_data1_s; -} sh_xn_pi_sic_cmp_data1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_DATA2" */ -/* PI compare SIC data2 */ -/* ==================================================================== */ - -typedef union sh_xn_pi_sic_cmp_data2_u { - mmr_t sh_xn_pi_sic_cmp_data2_regval; - struct { - mmr_t data2 : 64; - } sh_xn_pi_sic_cmp_data2_s; -} sh_xn_pi_sic_cmp_data2_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_DATA3" */ -/* PI compare SIC data3 */ -/* ==================================================================== */ - -typedef union sh_xn_pi_sic_cmp_data3_u { - mmr_t sh_xn_pi_sic_cmp_data3_regval; - struct { - mmr_t data3 : 64; - } sh_xn_pi_sic_cmp_data3_s; -} sh_xn_pi_sic_cmp_data3_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE0" */ -/* PI enable compare SIC data0 */ -/* ==================================================================== */ - -typedef union sh_xn_pi_sic_cmp_data_enable0_u { - mmr_t sh_xn_pi_sic_cmp_data_enable0_regval; - struct { - mmr_t data_enable0 : 64; - } sh_xn_pi_sic_cmp_data_enable0_s; -} sh_xn_pi_sic_cmp_data_enable0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE1" */ -/* PI enable compare SIC data1 */ -/* ==================================================================== */ - -typedef union sh_xn_pi_sic_cmp_data_enable1_u { - mmr_t sh_xn_pi_sic_cmp_data_enable1_regval; - struct { - mmr_t data_enable1 : 64; - } sh_xn_pi_sic_cmp_data_enable1_s; -} sh_xn_pi_sic_cmp_data_enable1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE2" */ -/* PI enable compare SIC data2 */ -/* ==================================================================== */ - -typedef union sh_xn_pi_sic_cmp_data_enable2_u { - mmr_t sh_xn_pi_sic_cmp_data_enable2_regval; - struct { - mmr_t data_enable2 : 64; - } sh_xn_pi_sic_cmp_data_enable2_s; -} sh_xn_pi_sic_cmp_data_enable2_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE3" */ -/* PI enable compare SIC data3 */ -/* ==================================================================== */ - -typedef union sh_xn_pi_sic_cmp_data_enable3_u { - mmr_t sh_xn_pi_sic_cmp_data_enable3_regval; - struct { - mmr_t data_enable3 : 64; - } sh_xn_pi_sic_cmp_data_enable3_s; -} sh_xn_pi_sic_cmp_data_enable3_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI0_IILB_CMP_EXP_DATA0" */ -/* NI0 compare IILB input expected data0 */ -/* ==================================================================== */ - -typedef union sh_xn_ni0_iilb_cmp_exp_data0_u { - mmr_t sh_xn_ni0_iilb_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_ni0_iilb_cmp_exp_data0_s; -} sh_xn_ni0_iilb_cmp_exp_data0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI0_IILB_CMP_EXP_DATA1" */ -/* NI0 compare IILB input expected data1 */ -/* ==================================================================== */ - -typedef union sh_xn_ni0_iilb_cmp_exp_data1_u { - mmr_t sh_xn_ni0_iilb_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_ni0_iilb_cmp_exp_data1_s; -} sh_xn_ni0_iilb_cmp_exp_data1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI0_IILB_CMP_ENABLE0" */ -/* NI0 compare IILB input enable0 */ -/* ==================================================================== */ - -typedef union sh_xn_ni0_iilb_cmp_enable0_u { - mmr_t sh_xn_ni0_iilb_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni0_iilb_cmp_enable0_s; -} sh_xn_ni0_iilb_cmp_enable0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI0_IILB_CMP_ENABLE1" */ -/* NI0 compare IILB input enable1 */ -/* ==================================================================== */ - -typedef union sh_xn_ni0_iilb_cmp_enable1_u { - mmr_t sh_xn_ni0_iilb_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni0_iilb_cmp_enable1_s; -} sh_xn_ni0_iilb_cmp_enable1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI0_PI_CMP_EXP_DATA0" */ -/* NI0 compare PI input expected data0 */ -/* ==================================================================== */ - -typedef union sh_xn_ni0_pi_cmp_exp_data0_u { - mmr_t sh_xn_ni0_pi_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_ni0_pi_cmp_exp_data0_s; -} sh_xn_ni0_pi_cmp_exp_data0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI0_PI_CMP_EXP_DATA1" */ -/* NI0 compare PI input expected data1 */ -/* ==================================================================== */ - -typedef union sh_xn_ni0_pi_cmp_exp_data1_u { - mmr_t sh_xn_ni0_pi_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_ni0_pi_cmp_exp_data1_s; -} sh_xn_ni0_pi_cmp_exp_data1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI0_PI_CMP_ENABLE0" */ -/* NI0 compare PI input enable0 */ -/* ==================================================================== */ - -typedef union sh_xn_ni0_pi_cmp_enable0_u { - mmr_t sh_xn_ni0_pi_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni0_pi_cmp_enable0_s; -} sh_xn_ni0_pi_cmp_enable0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI0_PI_CMP_ENABLE1" */ -/* NI0 compare PI input enable1 */ -/* ==================================================================== */ - -typedef union sh_xn_ni0_pi_cmp_enable1_u { - mmr_t sh_xn_ni0_pi_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni0_pi_cmp_enable1_s; -} sh_xn_ni0_pi_cmp_enable1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI0_MD_CMP_EXP_DATA0" */ -/* NI0 compare MD input expected data0 */ -/* ==================================================================== */ - -typedef union sh_xn_ni0_md_cmp_exp_data0_u { - mmr_t sh_xn_ni0_md_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_ni0_md_cmp_exp_data0_s; -} sh_xn_ni0_md_cmp_exp_data0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI0_MD_CMP_EXP_DATA1" */ -/* NI0 compare MD input expected data1 */ -/* ==================================================================== */ - -typedef union sh_xn_ni0_md_cmp_exp_data1_u { - mmr_t sh_xn_ni0_md_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_ni0_md_cmp_exp_data1_s; -} sh_xn_ni0_md_cmp_exp_data1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI0_MD_CMP_ENABLE0" */ -/* NI0 compare MD input enable0 */ -/* ==================================================================== */ - -typedef union sh_xn_ni0_md_cmp_enable0_u { - mmr_t sh_xn_ni0_md_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni0_md_cmp_enable0_s; -} sh_xn_ni0_md_cmp_enable0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI0_MD_CMP_ENABLE1" */ -/* NI0 compare MD input enable1 */ -/* ==================================================================== */ - -typedef union sh_xn_ni0_md_cmp_enable1_u { - mmr_t sh_xn_ni0_md_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni0_md_cmp_enable1_s; -} sh_xn_ni0_md_cmp_enable1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI0_NI_CMP_EXP_DATA0" */ -/* NI0 compare NI input expected data0 */ -/* ==================================================================== */ - -typedef union sh_xn_ni0_ni_cmp_exp_data0_u { - mmr_t sh_xn_ni0_ni_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_ni0_ni_cmp_exp_data0_s; -} sh_xn_ni0_ni_cmp_exp_data0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI0_NI_CMP_EXP_DATA1" */ -/* NI0 compare NI input expected data1 */ -/* ==================================================================== */ - -typedef union sh_xn_ni0_ni_cmp_exp_data1_u { - mmr_t sh_xn_ni0_ni_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_ni0_ni_cmp_exp_data1_s; -} sh_xn_ni0_ni_cmp_exp_data1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI0_NI_CMP_ENABLE0" */ -/* NI0 compare NI input enable0 */ -/* ==================================================================== */ - -typedef union sh_xn_ni0_ni_cmp_enable0_u { - mmr_t sh_xn_ni0_ni_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni0_ni_cmp_enable0_s; -} sh_xn_ni0_ni_cmp_enable0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI0_NI_CMP_ENABLE1" */ -/* NI0 compare NI input enable1 */ -/* ==================================================================== */ - -typedef union sh_xn_ni0_ni_cmp_enable1_u { - mmr_t sh_xn_ni0_ni_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni0_ni_cmp_enable1_s; -} sh_xn_ni0_ni_cmp_enable1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI0_LLP_CMP_EXP_DATA0" */ -/* NI0 compare LLP input expected data0 */ -/* ==================================================================== */ - -typedef union sh_xn_ni0_llp_cmp_exp_data0_u { - mmr_t sh_xn_ni0_llp_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_ni0_llp_cmp_exp_data0_s; -} sh_xn_ni0_llp_cmp_exp_data0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI0_LLP_CMP_EXP_DATA1" */ -/* NI0 compare LLP input expected data1 */ -/* ==================================================================== */ - -typedef union sh_xn_ni0_llp_cmp_exp_data1_u { - mmr_t sh_xn_ni0_llp_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_ni0_llp_cmp_exp_data1_s; -} sh_xn_ni0_llp_cmp_exp_data1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI0_LLP_CMP_ENABLE0" */ -/* NI0 compare LLP input enable0 */ -/* ==================================================================== */ - -typedef union sh_xn_ni0_llp_cmp_enable0_u { - mmr_t sh_xn_ni0_llp_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni0_llp_cmp_enable0_s; -} sh_xn_ni0_llp_cmp_enable0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI0_LLP_CMP_ENABLE1" */ -/* NI0 compare LLP input enable1 */ -/* ==================================================================== */ - -typedef union sh_xn_ni0_llp_cmp_enable1_u { - mmr_t sh_xn_ni0_llp_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni0_llp_cmp_enable1_s; -} sh_xn_ni0_llp_cmp_enable1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI1_IILB_CMP_EXP_DATA0" */ -/* NI1 compare IILB input expected data0 */ -/* ==================================================================== */ - -typedef union sh_xn_ni1_iilb_cmp_exp_data0_u { - mmr_t sh_xn_ni1_iilb_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_ni1_iilb_cmp_exp_data0_s; -} sh_xn_ni1_iilb_cmp_exp_data0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI1_IILB_CMP_EXP_DATA1" */ -/* NI1 compare IILB input expected data1 */ -/* ==================================================================== */ - -typedef union sh_xn_ni1_iilb_cmp_exp_data1_u { - mmr_t sh_xn_ni1_iilb_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_ni1_iilb_cmp_exp_data1_s; -} sh_xn_ni1_iilb_cmp_exp_data1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI1_IILB_CMP_ENABLE0" */ -/* NI1 compare IILB input enable0 */ -/* ==================================================================== */ - -typedef union sh_xn_ni1_iilb_cmp_enable0_u { - mmr_t sh_xn_ni1_iilb_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni1_iilb_cmp_enable0_s; -} sh_xn_ni1_iilb_cmp_enable0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI1_IILB_CMP_ENABLE1" */ -/* NI1 compare IILB input enable1 */ -/* ==================================================================== */ - -typedef union sh_xn_ni1_iilb_cmp_enable1_u { - mmr_t sh_xn_ni1_iilb_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni1_iilb_cmp_enable1_s; -} sh_xn_ni1_iilb_cmp_enable1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI1_PI_CMP_EXP_DATA0" */ -/* NI1 compare PI input expected data0 */ -/* ==================================================================== */ - -typedef union sh_xn_ni1_pi_cmp_exp_data0_u { - mmr_t sh_xn_ni1_pi_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_ni1_pi_cmp_exp_data0_s; -} sh_xn_ni1_pi_cmp_exp_data0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI1_PI_CMP_EXP_DATA1" */ -/* NI1 compare PI input expected data1 */ -/* ==================================================================== */ - -typedef union sh_xn_ni1_pi_cmp_exp_data1_u { - mmr_t sh_xn_ni1_pi_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_ni1_pi_cmp_exp_data1_s; -} sh_xn_ni1_pi_cmp_exp_data1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI1_PI_CMP_ENABLE0" */ -/* NI1 compare PI input enable0 */ -/* ==================================================================== */ - -typedef union sh_xn_ni1_pi_cmp_enable0_u { - mmr_t sh_xn_ni1_pi_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni1_pi_cmp_enable0_s; -} sh_xn_ni1_pi_cmp_enable0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI1_PI_CMP_ENABLE1" */ -/* NI1 compare PI input enable1 */ -/* ==================================================================== */ - -typedef union sh_xn_ni1_pi_cmp_enable1_u { - mmr_t sh_xn_ni1_pi_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni1_pi_cmp_enable1_s; -} sh_xn_ni1_pi_cmp_enable1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI1_MD_CMP_EXP_DATA0" */ -/* NI1 compare MD input expected data0 */ -/* ==================================================================== */ - -typedef union sh_xn_ni1_md_cmp_exp_data0_u { - mmr_t sh_xn_ni1_md_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_ni1_md_cmp_exp_data0_s; -} sh_xn_ni1_md_cmp_exp_data0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI1_MD_CMP_EXP_DATA1" */ -/* NI1 compare MD input expected data1 */ -/* ==================================================================== */ - -typedef union sh_xn_ni1_md_cmp_exp_data1_u { - mmr_t sh_xn_ni1_md_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_ni1_md_cmp_exp_data1_s; -} sh_xn_ni1_md_cmp_exp_data1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI1_MD_CMP_ENABLE0" */ -/* NI1 compare MD input enable0 */ -/* ==================================================================== */ - -typedef union sh_xn_ni1_md_cmp_enable0_u { - mmr_t sh_xn_ni1_md_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni1_md_cmp_enable0_s; -} sh_xn_ni1_md_cmp_enable0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI1_MD_CMP_ENABLE1" */ -/* NI1 compare MD input enable1 */ -/* ==================================================================== */ - -typedef union sh_xn_ni1_md_cmp_enable1_u { - mmr_t sh_xn_ni1_md_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni1_md_cmp_enable1_s; -} sh_xn_ni1_md_cmp_enable1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI1_NI_CMP_EXP_DATA0" */ -/* NI1 compare NI input expected data0 */ -/* ==================================================================== */ - -typedef union sh_xn_ni1_ni_cmp_exp_data0_u { - mmr_t sh_xn_ni1_ni_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_ni1_ni_cmp_exp_data0_s; -} sh_xn_ni1_ni_cmp_exp_data0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI1_NI_CMP_EXP_DATA1" */ -/* NI1 compare NI input expected data1 */ -/* ==================================================================== */ - -typedef union sh_xn_ni1_ni_cmp_exp_data1_u { - mmr_t sh_xn_ni1_ni_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_ni1_ni_cmp_exp_data1_s; -} sh_xn_ni1_ni_cmp_exp_data1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI1_NI_CMP_ENABLE0" */ -/* NI1 compare NI input enable0 */ -/* ==================================================================== */ - -typedef union sh_xn_ni1_ni_cmp_enable0_u { - mmr_t sh_xn_ni1_ni_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni1_ni_cmp_enable0_s; -} sh_xn_ni1_ni_cmp_enable0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI1_NI_CMP_ENABLE1" */ -/* NI1 compare NI input enable1 */ -/* ==================================================================== */ - -typedef union sh_xn_ni1_ni_cmp_enable1_u { - mmr_t sh_xn_ni1_ni_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni1_ni_cmp_enable1_s; -} sh_xn_ni1_ni_cmp_enable1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI1_LLP_CMP_EXP_DATA0" */ -/* NI1 compare LLP input expected data0 */ -/* ==================================================================== */ - -typedef union sh_xn_ni1_llp_cmp_exp_data0_u { - mmr_t sh_xn_ni1_llp_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_ni1_llp_cmp_exp_data0_s; -} sh_xn_ni1_llp_cmp_exp_data0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI1_LLP_CMP_EXP_DATA1" */ -/* NI1 compare LLP input expected data1 */ -/* ==================================================================== */ - -typedef union sh_xn_ni1_llp_cmp_exp_data1_u { - mmr_t sh_xn_ni1_llp_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_ni1_llp_cmp_exp_data1_s; -} sh_xn_ni1_llp_cmp_exp_data1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI1_LLP_CMP_ENABLE0" */ -/* NI1 compare LLP input enable0 */ -/* ==================================================================== */ - -typedef union sh_xn_ni1_llp_cmp_enable0_u { - mmr_t sh_xn_ni1_llp_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni1_llp_cmp_enable0_s; -} sh_xn_ni1_llp_cmp_enable0_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_NI1_LLP_CMP_ENABLE1" */ -/* NI1 compare LLP input enable1 */ -/* ==================================================================== */ - -typedef union sh_xn_ni1_llp_cmp_enable1_u { - mmr_t sh_xn_ni1_llp_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni1_llp_cmp_enable1_s; -} sh_xn_ni1_llp_cmp_enable1_u_t; - -/* ==================================================================== */ -/* Register "SH_XNPI_ECC_INJ_REG" */ -/* ==================================================================== */ - -typedef union sh_xnpi_ecc_inj_reg_u { - mmr_t sh_xnpi_ecc_inj_reg_regval; - struct { - mmr_t byte0 : 8; - mmr_t reserved_0 : 4; - mmr_t data_1shot0 : 1; - mmr_t data_cont0 : 1; - mmr_t data_cb_1shot0 : 1; - mmr_t data_cb_cont0 : 1; - mmr_t byte1 : 8; - mmr_t reserved_1 : 4; - mmr_t data_1shot1 : 1; - mmr_t data_cont1 : 1; - mmr_t data_cb_1shot1 : 1; - mmr_t data_cb_cont1 : 1; - mmr_t byte2 : 8; - mmr_t reserved_2 : 4; - mmr_t data_1shot2 : 1; - mmr_t data_cont2 : 1; - mmr_t data_cb_1shot2 : 1; - mmr_t data_cb_cont2 : 1; - mmr_t byte3 : 8; - mmr_t reserved_3 : 4; - mmr_t data_1shot3 : 1; - mmr_t data_cont3 : 1; - mmr_t data_cb_1shot3 : 1; - mmr_t data_cb_cont3 : 1; - } sh_xnpi_ecc_inj_reg_s; -} sh_xnpi_ecc_inj_reg_u_t; - -/* ==================================================================== */ -/* Register "SH_XNPI_ECC0_INJ_MASK_REG" */ -/* ==================================================================== */ - -typedef union sh_xnpi_ecc0_inj_mask_reg_u { - mmr_t sh_xnpi_ecc0_inj_mask_reg_regval; - struct { - mmr_t mask_ecc0 : 64; - } sh_xnpi_ecc0_inj_mask_reg_s; -} sh_xnpi_ecc0_inj_mask_reg_u_t; - -/* ==================================================================== */ -/* Register "SH_XNPI_ECC1_INJ_MASK_REG" */ -/* ==================================================================== */ - -typedef union sh_xnpi_ecc1_inj_mask_reg_u { - mmr_t sh_xnpi_ecc1_inj_mask_reg_regval; - struct { - mmr_t mask_ecc1 : 64; - } sh_xnpi_ecc1_inj_mask_reg_s; -} sh_xnpi_ecc1_inj_mask_reg_u_t; - -/* ==================================================================== */ -/* Register "SH_XNPI_ECC2_INJ_MASK_REG" */ -/* ==================================================================== */ - -typedef union sh_xnpi_ecc2_inj_mask_reg_u { - mmr_t sh_xnpi_ecc2_inj_mask_reg_regval; - struct { - mmr_t mask_ecc2 : 64; - } sh_xnpi_ecc2_inj_mask_reg_s; -} sh_xnpi_ecc2_inj_mask_reg_u_t; - -/* ==================================================================== */ -/* Register "SH_XNPI_ECC3_INJ_MASK_REG" */ -/* ==================================================================== */ - -typedef union sh_xnpi_ecc3_inj_mask_reg_u { - mmr_t sh_xnpi_ecc3_inj_mask_reg_regval; - struct { - mmr_t mask_ecc3 : 64; - } sh_xnpi_ecc3_inj_mask_reg_s; -} sh_xnpi_ecc3_inj_mask_reg_u_t; - -/* ==================================================================== */ -/* Register "SH_XNMD_ECC_INJ_REG" */ -/* ==================================================================== */ - -typedef union sh_xnmd_ecc_inj_reg_u { - mmr_t sh_xnmd_ecc_inj_reg_regval; - struct { - mmr_t byte0 : 8; - mmr_t reserved_0 : 4; - mmr_t data_1shot0 : 1; - mmr_t data_cont0 : 1; - mmr_t data_cb_1shot0 : 1; - mmr_t data_cb_cont0 : 1; - mmr_t byte1 : 8; - mmr_t reserved_1 : 4; - mmr_t data_1shot1 : 1; - mmr_t data_cont1 : 1; - mmr_t data_cb_1shot1 : 1; - mmr_t data_cb_cont1 : 1; - mmr_t byte2 : 8; - mmr_t reserved_2 : 4; - mmr_t data_1shot2 : 1; - mmr_t data_cont2 : 1; - mmr_t data_cb_1shot2 : 1; - mmr_t data_cb_cont2 : 1; - mmr_t byte3 : 8; - mmr_t reserved_3 : 4; - mmr_t data_1shot3 : 1; - mmr_t data_cont3 : 1; - mmr_t data_cb_1shot3 : 1; - mmr_t data_cb_cont3 : 1; - } sh_xnmd_ecc_inj_reg_s; -} sh_xnmd_ecc_inj_reg_u_t; - -/* ==================================================================== */ -/* Register "SH_XNMD_ECC0_INJ_MASK_REG" */ -/* ==================================================================== */ - -typedef union sh_xnmd_ecc0_inj_mask_reg_u { - mmr_t sh_xnmd_ecc0_inj_mask_reg_regval; - struct { - mmr_t mask_ecc0 : 64; - } sh_xnmd_ecc0_inj_mask_reg_s; -} sh_xnmd_ecc0_inj_mask_reg_u_t; - -/* ==================================================================== */ -/* Register "SH_XNMD_ECC1_INJ_MASK_REG" */ -/* ==================================================================== */ - -typedef union sh_xnmd_ecc1_inj_mask_reg_u { - mmr_t sh_xnmd_ecc1_inj_mask_reg_regval; - struct { - mmr_t mask_ecc1 : 64; - } sh_xnmd_ecc1_inj_mask_reg_s; -} sh_xnmd_ecc1_inj_mask_reg_u_t; - -/* ==================================================================== */ -/* Register "SH_XNMD_ECC2_INJ_MASK_REG" */ -/* ==================================================================== */ - -typedef union sh_xnmd_ecc2_inj_mask_reg_u { - mmr_t sh_xnmd_ecc2_inj_mask_reg_regval; - struct { - mmr_t mask_ecc2 : 64; - } sh_xnmd_ecc2_inj_mask_reg_s; -} sh_xnmd_ecc2_inj_mask_reg_u_t; - -/* ==================================================================== */ -/* Register "SH_XNMD_ECC3_INJ_MASK_REG" */ -/* ==================================================================== */ - -typedef union sh_xnmd_ecc3_inj_mask_reg_u { - mmr_t sh_xnmd_ecc3_inj_mask_reg_regval; - struct { - mmr_t mask_ecc3 : 64; - } sh_xnmd_ecc3_inj_mask_reg_s; -} sh_xnmd_ecc3_inj_mask_reg_u_t; - -/* ==================================================================== */ -/* Register "SH_XNMD_ECC_ERR_REPORT" */ -/* ==================================================================== */ - -typedef union sh_xnmd_ecc_err_report_u { - mmr_t sh_xnmd_ecc_err_report_regval; - struct { - mmr_t ecc_disable0 : 1; - mmr_t reserved_0 : 15; - mmr_t ecc_disable1 : 1; - mmr_t reserved_1 : 15; - mmr_t ecc_disable2 : 1; - mmr_t reserved_2 : 15; - mmr_t ecc_disable3 : 1; - mmr_t reserved_3 : 15; - } sh_xnmd_ecc_err_report_s; -} sh_xnmd_ecc_err_report_u_t; - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_SUMMARY_1" */ -/* ni0 Error Summary Bits */ -/* ==================================================================== */ - -typedef union sh_ni0_error_summary_1_u { - mmr_t sh_ni0_error_summary_1_regval; - struct { - mmr_t overflow_fifo02_debit0 : 1; - mmr_t overflow_fifo02_debit2 : 1; - mmr_t overflow_fifo13_debit0 : 1; - mmr_t overflow_fifo13_debit2 : 1; - mmr_t overflow_fifo02_vc0_pop : 1; - mmr_t overflow_fifo02_vc2_pop : 1; - mmr_t overflow_fifo13_vc1_pop : 1; - mmr_t overflow_fifo13_vc3_pop : 1; - mmr_t overflow_fifo02_vc0_push : 1; - mmr_t overflow_fifo02_vc2_push : 1; - mmr_t overflow_fifo13_vc1_push : 1; - mmr_t overflow_fifo13_vc3_push : 1; - mmr_t overflow_fifo02_vc0_credit : 1; - mmr_t overflow_fifo02_vc2_credit : 1; - mmr_t overflow_fifo13_vc0_credit : 1; - mmr_t overflow_fifo13_vc2_credit : 1; - mmr_t overflow0_vc0_credit : 1; - mmr_t overflow1_vc0_credit : 1; - mmr_t overflow2_vc0_credit : 1; - mmr_t overflow0_vc2_credit : 1; - mmr_t overflow1_vc2_credit : 1; - mmr_t overflow2_vc2_credit : 1; - mmr_t overflow_pi_fifo_debit0 : 1; - mmr_t overflow_pi_fifo_debit2 : 1; - mmr_t overflow_iilb_fifo_debit0 : 1; - mmr_t overflow_iilb_fifo_debit2 : 1; - mmr_t overflow_md_fifo_debit0 : 1; - mmr_t overflow_md_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit0 : 1; - mmr_t overflow_ni_fifo_debit1 : 1; - mmr_t overflow_ni_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit3 : 1; - mmr_t overflow_pi_fifo_vc0_pop : 1; - mmr_t overflow_pi_fifo_vc2_pop : 1; - mmr_t overflow_iilb_fifo_vc0_pop : 1; - mmr_t overflow_iilb_fifo_vc2_pop : 1; - mmr_t overflow_md_fifo_vc0_pop : 1; - mmr_t overflow_md_fifo_vc2_pop : 1; - mmr_t overflow_ni_fifo_vc0_pop : 1; - mmr_t overflow_ni_fifo_vc2_pop : 1; - mmr_t overflow_pi_fifo_vc0_push : 1; - mmr_t overflow_pi_fifo_vc2_push : 1; - mmr_t overflow_iilb_fifo_vc0_push : 1; - mmr_t overflow_iilb_fifo_vc2_push : 1; - mmr_t overflow_md_fifo_vc0_push : 1; - mmr_t overflow_md_fifo_vc2_push : 1; - mmr_t overflow_pi_fifo_vc0_credit : 1; - mmr_t overflow_pi_fifo_vc2_credit : 1; - mmr_t overflow_iilb_fifo_vc0_credit : 1; - mmr_t overflow_iilb_fifo_vc2_credit : 1; - mmr_t overflow_md_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc0_credit : 1; - mmr_t overflow_ni_fifo_vc1_credit : 1; - mmr_t overflow_ni_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc3_credit : 1; - mmr_t tail_timeout_fifo02_vc0 : 1; - mmr_t tail_timeout_fifo02_vc2 : 1; - mmr_t tail_timeout_fifo13_vc1 : 1; - mmr_t tail_timeout_fifo13_vc3 : 1; - mmr_t tail_timeout_ni_vc0 : 1; - mmr_t tail_timeout_ni_vc1 : 1; - mmr_t tail_timeout_ni_vc2 : 1; - mmr_t tail_timeout_ni_vc3 : 1; - } sh_ni0_error_summary_1_s; -} sh_ni0_error_summary_1_u_t; - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_SUMMARY_2" */ -/* ni0 Error Summary Bits */ -/* ==================================================================== */ - -typedef union sh_ni0_error_summary_2_u { - mmr_t sh_ni0_error_summary_2_regval; - struct { - mmr_t illegal_vcni : 1; - mmr_t illegal_vcpi : 1; - mmr_t illegal_vcmd : 1; - mmr_t illegal_vciilb : 1; - mmr_t underflow_fifo02_vc0_pop : 1; - mmr_t underflow_fifo02_vc2_pop : 1; - mmr_t underflow_fifo13_vc1_pop : 1; - mmr_t underflow_fifo13_vc3_pop : 1; - mmr_t underflow_fifo02_vc0_push : 1; - mmr_t underflow_fifo02_vc2_push : 1; - mmr_t underflow_fifo13_vc1_push : 1; - mmr_t underflow_fifo13_vc3_push : 1; - mmr_t underflow_fifo02_vc0_credit : 1; - mmr_t underflow_fifo02_vc2_credit : 1; - mmr_t underflow_fifo13_vc0_credit : 1; - mmr_t underflow_fifo13_vc2_credit : 1; - mmr_t underflow0_vc0_credit : 1; - mmr_t underflow1_vc0_credit : 1; - mmr_t underflow2_vc0_credit : 1; - mmr_t underflow0_vc2_credit : 1; - mmr_t underflow1_vc2_credit : 1; - mmr_t underflow2_vc2_credit : 1; - mmr_t reserved_0 : 10; - mmr_t underflow_pi_fifo_vc0_pop : 1; - mmr_t underflow_pi_fifo_vc2_pop : 1; - mmr_t underflow_iilb_fifo_vc0_pop : 1; - mmr_t underflow_iilb_fifo_vc2_pop : 1; - mmr_t underflow_md_fifo_vc0_pop : 1; - mmr_t underflow_md_fifo_vc2_pop : 1; - mmr_t underflow_ni_fifo_vc0_pop : 1; - mmr_t underflow_ni_fifo_vc2_pop : 1; - mmr_t underflow_pi_fifo_vc0_push : 1; - mmr_t underflow_pi_fifo_vc2_push : 1; - mmr_t underflow_iilb_fifo_vc0_push : 1; - mmr_t underflow_iilb_fifo_vc2_push : 1; - mmr_t underflow_md_fifo_vc0_push : 1; - mmr_t underflow_md_fifo_vc2_push : 1; - mmr_t underflow_pi_fifo_vc0_credit : 1; - mmr_t underflow_pi_fifo_vc2_credit : 1; - mmr_t underflow_iilb_fifo_vc0_credit : 1; - mmr_t underflow_iilb_fifo_vc2_credit : 1; - mmr_t underflow_md_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc0_credit : 1; - mmr_t underflow_ni_fifo_vc1_credit : 1; - mmr_t underflow_ni_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc3_credit : 1; - mmr_t llp_deadlock_vc0 : 1; - mmr_t llp_deadlock_vc1 : 1; - mmr_t llp_deadlock_vc2 : 1; - mmr_t llp_deadlock_vc3 : 1; - mmr_t chiplet_nomatch : 1; - mmr_t lut_read_error : 1; - mmr_t retry_timeout_error : 1; - mmr_t reserved_1 : 1; - } sh_ni0_error_summary_2_s; -} sh_ni0_error_summary_2_u_t; - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_OVERFLOW_1" */ -/* ni0 Error Overflow Bits */ -/* ==================================================================== */ - -typedef union sh_ni0_error_overflow_1_u { - mmr_t sh_ni0_error_overflow_1_regval; - struct { - mmr_t overflow_fifo02_debit0 : 1; - mmr_t overflow_fifo02_debit2 : 1; - mmr_t overflow_fifo13_debit0 : 1; - mmr_t overflow_fifo13_debit2 : 1; - mmr_t overflow_fifo02_vc0_pop : 1; - mmr_t overflow_fifo02_vc2_pop : 1; - mmr_t overflow_fifo13_vc1_pop : 1; - mmr_t overflow_fifo13_vc3_pop : 1; - mmr_t overflow_fifo02_vc0_push : 1; - mmr_t overflow_fifo02_vc2_push : 1; - mmr_t overflow_fifo13_vc1_push : 1; - mmr_t overflow_fifo13_vc3_push : 1; - mmr_t overflow_fifo02_vc0_credit : 1; - mmr_t overflow_fifo02_vc2_credit : 1; - mmr_t overflow_fifo13_vc0_credit : 1; - mmr_t overflow_fifo13_vc2_credit : 1; - mmr_t overflow0_vc0_credit : 1; - mmr_t overflow1_vc0_credit : 1; - mmr_t overflow2_vc0_credit : 1; - mmr_t overflow0_vc2_credit : 1; - mmr_t overflow1_vc2_credit : 1; - mmr_t overflow2_vc2_credit : 1; - mmr_t overflow_pi_fifo_debit0 : 1; - mmr_t overflow_pi_fifo_debit2 : 1; - mmr_t overflow_iilb_fifo_debit0 : 1; - mmr_t overflow_iilb_fifo_debit2 : 1; - mmr_t overflow_md_fifo_debit0 : 1; - mmr_t overflow_md_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit0 : 1; - mmr_t overflow_ni_fifo_debit1 : 1; - mmr_t overflow_ni_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit3 : 1; - mmr_t overflow_pi_fifo_vc0_pop : 1; - mmr_t overflow_pi_fifo_vc2_pop : 1; - mmr_t overflow_iilb_fifo_vc0_pop : 1; - mmr_t overflow_iilb_fifo_vc2_pop : 1; - mmr_t overflow_md_fifo_vc0_pop : 1; - mmr_t overflow_md_fifo_vc2_pop : 1; - mmr_t overflow_ni_fifo_vc0_pop : 1; - mmr_t overflow_ni_fifo_vc2_pop : 1; - mmr_t overflow_pi_fifo_vc0_push : 1; - mmr_t overflow_pi_fifo_vc2_push : 1; - mmr_t overflow_iilb_fifo_vc0_push : 1; - mmr_t overflow_iilb_fifo_vc2_push : 1; - mmr_t overflow_md_fifo_vc0_push : 1; - mmr_t overflow_md_fifo_vc2_push : 1; - mmr_t overflow_pi_fifo_vc0_credit : 1; - mmr_t overflow_pi_fifo_vc2_credit : 1; - mmr_t overflow_iilb_fifo_vc0_credit : 1; - mmr_t overflow_iilb_fifo_vc2_credit : 1; - mmr_t overflow_md_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc0_credit : 1; - mmr_t overflow_ni_fifo_vc1_credit : 1; - mmr_t overflow_ni_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc3_credit : 1; - mmr_t tail_timeout_fifo02_vc0 : 1; - mmr_t tail_timeout_fifo02_vc2 : 1; - mmr_t tail_timeout_fifo13_vc1 : 1; - mmr_t tail_timeout_fifo13_vc3 : 1; - mmr_t tail_timeout_ni_vc0 : 1; - mmr_t tail_timeout_ni_vc1 : 1; - mmr_t tail_timeout_ni_vc2 : 1; - mmr_t tail_timeout_ni_vc3 : 1; - } sh_ni0_error_overflow_1_s; -} sh_ni0_error_overflow_1_u_t; - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_OVERFLOW_2" */ -/* ni0 Error Overflow Bits */ -/* ==================================================================== */ - -typedef union sh_ni0_error_overflow_2_u { - mmr_t sh_ni0_error_overflow_2_regval; - struct { - mmr_t illegal_vcni : 1; - mmr_t illegal_vcpi : 1; - mmr_t illegal_vcmd : 1; - mmr_t illegal_vciilb : 1; - mmr_t underflow_fifo02_vc0_pop : 1; - mmr_t underflow_fifo02_vc2_pop : 1; - mmr_t underflow_fifo13_vc1_pop : 1; - mmr_t underflow_fifo13_vc3_pop : 1; - mmr_t underflow_fifo02_vc0_push : 1; - mmr_t underflow_fifo02_vc2_push : 1; - mmr_t underflow_fifo13_vc1_push : 1; - mmr_t underflow_fifo13_vc3_push : 1; - mmr_t underflow_fifo02_vc0_credit : 1; - mmr_t underflow_fifo02_vc2_credit : 1; - mmr_t underflow_fifo13_vc0_credit : 1; - mmr_t underflow_fifo13_vc2_credit : 1; - mmr_t underflow0_vc0_credit : 1; - mmr_t underflow1_vc0_credit : 1; - mmr_t underflow2_vc0_credit : 1; - mmr_t underflow0_vc2_credit : 1; - mmr_t underflow1_vc2_credit : 1; - mmr_t underflow2_vc2_credit : 1; - mmr_t reserved_0 : 10; - mmr_t underflow_pi_fifo_vc0_pop : 1; - mmr_t underflow_pi_fifo_vc2_pop : 1; - mmr_t underflow_iilb_fifo_vc0_pop : 1; - mmr_t underflow_iilb_fifo_vc2_pop : 1; - mmr_t underflow_md_fifo_vc0_pop : 1; - mmr_t underflow_md_fifo_vc2_pop : 1; - mmr_t underflow_ni_fifo_vc0_pop : 1; - mmr_t underflow_ni_fifo_vc2_pop : 1; - mmr_t underflow_pi_fifo_vc0_push : 1; - mmr_t underflow_pi_fifo_vc2_push : 1; - mmr_t underflow_iilb_fifo_vc0_push : 1; - mmr_t underflow_iilb_fifo_vc2_push : 1; - mmr_t underflow_md_fifo_vc0_push : 1; - mmr_t underflow_md_fifo_vc2_push : 1; - mmr_t underflow_pi_fifo_vc0_credit : 1; - mmr_t underflow_pi_fifo_vc2_credit : 1; - mmr_t underflow_iilb_fifo_vc0_credit : 1; - mmr_t underflow_iilb_fifo_vc2_credit : 1; - mmr_t underflow_md_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc0_credit : 1; - mmr_t underflow_ni_fifo_vc1_credit : 1; - mmr_t underflow_ni_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc3_credit : 1; - mmr_t llp_deadlock_vc0 : 1; - mmr_t llp_deadlock_vc1 : 1; - mmr_t llp_deadlock_vc2 : 1; - mmr_t llp_deadlock_vc3 : 1; - mmr_t chiplet_nomatch : 1; - mmr_t lut_read_error : 1; - mmr_t retry_timeout_error : 1; - mmr_t reserved_1 : 1; - } sh_ni0_error_overflow_2_s; -} sh_ni0_error_overflow_2_u_t; - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_MASK_1" */ -/* ni0 Error Mask Bits */ -/* ==================================================================== */ - -typedef union sh_ni0_error_mask_1_u { - mmr_t sh_ni0_error_mask_1_regval; - struct { - mmr_t overflow_fifo02_debit0 : 1; - mmr_t overflow_fifo02_debit2 : 1; - mmr_t overflow_fifo13_debit0 : 1; - mmr_t overflow_fifo13_debit2 : 1; - mmr_t overflow_fifo02_vc0_pop : 1; - mmr_t overflow_fifo02_vc2_pop : 1; - mmr_t overflow_fifo13_vc1_pop : 1; - mmr_t overflow_fifo13_vc3_pop : 1; - mmr_t overflow_fifo02_vc0_push : 1; - mmr_t overflow_fifo02_vc2_push : 1; - mmr_t overflow_fifo13_vc1_push : 1; - mmr_t overflow_fifo13_vc3_push : 1; - mmr_t overflow_fifo02_vc0_credit : 1; - mmr_t overflow_fifo02_vc2_credit : 1; - mmr_t overflow_fifo13_vc0_credit : 1; - mmr_t overflow_fifo13_vc2_credit : 1; - mmr_t overflow0_vc0_credit : 1; - mmr_t overflow1_vc0_credit : 1; - mmr_t overflow2_vc0_credit : 1; - mmr_t overflow0_vc2_credit : 1; - mmr_t overflow1_vc2_credit : 1; - mmr_t overflow2_vc2_credit : 1; - mmr_t overflow_pi_fifo_debit0 : 1; - mmr_t overflow_pi_fifo_debit2 : 1; - mmr_t overflow_iilb_fifo_debit0 : 1; - mmr_t overflow_iilb_fifo_debit2 : 1; - mmr_t overflow_md_fifo_debit0 : 1; - mmr_t overflow_md_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit0 : 1; - mmr_t overflow_ni_fifo_debit1 : 1; - mmr_t overflow_ni_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit3 : 1; - mmr_t overflow_pi_fifo_vc0_pop : 1; - mmr_t overflow_pi_fifo_vc2_pop : 1; - mmr_t overflow_iilb_fifo_vc0_pop : 1; - mmr_t overflow_iilb_fifo_vc2_pop : 1; - mmr_t overflow_md_fifo_vc0_pop : 1; - mmr_t overflow_md_fifo_vc2_pop : 1; - mmr_t overflow_ni_fifo_vc0_pop : 1; - mmr_t overflow_ni_fifo_vc2_pop : 1; - mmr_t overflow_pi_fifo_vc0_push : 1; - mmr_t overflow_pi_fifo_vc2_push : 1; - mmr_t overflow_iilb_fifo_vc0_push : 1; - mmr_t overflow_iilb_fifo_vc2_push : 1; - mmr_t overflow_md_fifo_vc0_push : 1; - mmr_t overflow_md_fifo_vc2_push : 1; - mmr_t overflow_pi_fifo_vc0_credit : 1; - mmr_t overflow_pi_fifo_vc2_credit : 1; - mmr_t overflow_iilb_fifo_vc0_credit : 1; - mmr_t overflow_iilb_fifo_vc2_credit : 1; - mmr_t overflow_md_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc0_credit : 1; - mmr_t overflow_ni_fifo_vc1_credit : 1; - mmr_t overflow_ni_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc3_credit : 1; - mmr_t tail_timeout_fifo02_vc0 : 1; - mmr_t tail_timeout_fifo02_vc2 : 1; - mmr_t tail_timeout_fifo13_vc1 : 1; - mmr_t tail_timeout_fifo13_vc3 : 1; - mmr_t tail_timeout_ni_vc0 : 1; - mmr_t tail_timeout_ni_vc1 : 1; - mmr_t tail_timeout_ni_vc2 : 1; - mmr_t tail_timeout_ni_vc3 : 1; - } sh_ni0_error_mask_1_s; -} sh_ni0_error_mask_1_u_t; - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_MASK_2" */ -/* ni0 Error Mask Bits */ -/* ==================================================================== */ - -typedef union sh_ni0_error_mask_2_u { - mmr_t sh_ni0_error_mask_2_regval; - struct { - mmr_t illegal_vcni : 1; - mmr_t illegal_vcpi : 1; - mmr_t illegal_vcmd : 1; - mmr_t illegal_vciilb : 1; - mmr_t underflow_fifo02_vc0_pop : 1; - mmr_t underflow_fifo02_vc2_pop : 1; - mmr_t underflow_fifo13_vc1_pop : 1; - mmr_t underflow_fifo13_vc3_pop : 1; - mmr_t underflow_fifo02_vc0_push : 1; - mmr_t underflow_fifo02_vc2_push : 1; - mmr_t underflow_fifo13_vc1_push : 1; - mmr_t underflow_fifo13_vc3_push : 1; - mmr_t underflow_fifo02_vc0_credit : 1; - mmr_t underflow_fifo02_vc2_credit : 1; - mmr_t underflow_fifo13_vc0_credit : 1; - mmr_t underflow_fifo13_vc2_credit : 1; - mmr_t underflow0_vc0_credit : 1; - mmr_t underflow1_vc0_credit : 1; - mmr_t underflow2_vc0_credit : 1; - mmr_t underflow0_vc2_credit : 1; - mmr_t underflow1_vc2_credit : 1; - mmr_t underflow2_vc2_credit : 1; - mmr_t reserved_0 : 10; - mmr_t underflow_pi_fifo_vc0_pop : 1; - mmr_t underflow_pi_fifo_vc2_pop : 1; - mmr_t underflow_iilb_fifo_vc0_pop : 1; - mmr_t underflow_iilb_fifo_vc2_pop : 1; - mmr_t underflow_md_fifo_vc0_pop : 1; - mmr_t underflow_md_fifo_vc2_pop : 1; - mmr_t underflow_ni_fifo_vc0_pop : 1; - mmr_t underflow_ni_fifo_vc2_pop : 1; - mmr_t underflow_pi_fifo_vc0_push : 1; - mmr_t underflow_pi_fifo_vc2_push : 1; - mmr_t underflow_iilb_fifo_vc0_push : 1; - mmr_t underflow_iilb_fifo_vc2_push : 1; - mmr_t underflow_md_fifo_vc0_push : 1; - mmr_t underflow_md_fifo_vc2_push : 1; - mmr_t underflow_pi_fifo_vc0_credit : 1; - mmr_t underflow_pi_fifo_vc2_credit : 1; - mmr_t underflow_iilb_fifo_vc0_credit : 1; - mmr_t underflow_iilb_fifo_vc2_credit : 1; - mmr_t underflow_md_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc0_credit : 1; - mmr_t underflow_ni_fifo_vc1_credit : 1; - mmr_t underflow_ni_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc3_credit : 1; - mmr_t llp_deadlock_vc0 : 1; - mmr_t llp_deadlock_vc1 : 1; - mmr_t llp_deadlock_vc2 : 1; - mmr_t llp_deadlock_vc3 : 1; - mmr_t chiplet_nomatch : 1; - mmr_t lut_read_error : 1; - mmr_t retry_timeout_error : 1; - mmr_t reserved_1 : 1; - } sh_ni0_error_mask_2_s; -} sh_ni0_error_mask_2_u_t; - -/* ==================================================================== */ -/* Register "SH_NI0_FIRST_ERROR_1" */ -/* ni0 First Error Bits */ -/* ==================================================================== */ - -typedef union sh_ni0_first_error_1_u { - mmr_t sh_ni0_first_error_1_regval; - struct { - mmr_t overflow_fifo02_debit0 : 1; - mmr_t overflow_fifo02_debit2 : 1; - mmr_t overflow_fifo13_debit0 : 1; - mmr_t overflow_fifo13_debit2 : 1; - mmr_t overflow_fifo02_vc0_pop : 1; - mmr_t overflow_fifo02_vc2_pop : 1; - mmr_t overflow_fifo13_vc1_pop : 1; - mmr_t overflow_fifo13_vc3_pop : 1; - mmr_t overflow_fifo02_vc0_push : 1; - mmr_t overflow_fifo02_vc2_push : 1; - mmr_t overflow_fifo13_vc1_push : 1; - mmr_t overflow_fifo13_vc3_push : 1; - mmr_t overflow_fifo02_vc0_credit : 1; - mmr_t overflow_fifo02_vc2_credit : 1; - mmr_t overflow_fifo13_vc0_credit : 1; - mmr_t overflow_fifo13_vc2_credit : 1; - mmr_t overflow0_vc0_credit : 1; - mmr_t overflow1_vc0_credit : 1; - mmr_t overflow2_vc0_credit : 1; - mmr_t overflow0_vc2_credit : 1; - mmr_t overflow1_vc2_credit : 1; - mmr_t overflow2_vc2_credit : 1; - mmr_t overflow_pi_fifo_debit0 : 1; - mmr_t overflow_pi_fifo_debit2 : 1; - mmr_t overflow_iilb_fifo_debit0 : 1; - mmr_t overflow_iilb_fifo_debit2 : 1; - mmr_t overflow_md_fifo_debit0 : 1; - mmr_t overflow_md_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit0 : 1; - mmr_t overflow_ni_fifo_debit1 : 1; - mmr_t overflow_ni_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit3 : 1; - mmr_t overflow_pi_fifo_vc0_pop : 1; - mmr_t overflow_pi_fifo_vc2_pop : 1; - mmr_t overflow_iilb_fifo_vc0_pop : 1; - mmr_t overflow_iilb_fifo_vc2_pop : 1; - mmr_t overflow_md_fifo_vc0_pop : 1; - mmr_t overflow_md_fifo_vc2_pop : 1; - mmr_t overflow_ni_fifo_vc0_pop : 1; - mmr_t overflow_ni_fifo_vc2_pop : 1; - mmr_t overflow_pi_fifo_vc0_push : 1; - mmr_t overflow_pi_fifo_vc2_push : 1; - mmr_t overflow_iilb_fifo_vc0_push : 1; - mmr_t overflow_iilb_fifo_vc2_push : 1; - mmr_t overflow_md_fifo_vc0_push : 1; - mmr_t overflow_md_fifo_vc2_push : 1; - mmr_t overflow_pi_fifo_vc0_credit : 1; - mmr_t overflow_pi_fifo_vc2_credit : 1; - mmr_t overflow_iilb_fifo_vc0_credit : 1; - mmr_t overflow_iilb_fifo_vc2_credit : 1; - mmr_t overflow_md_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc0_credit : 1; - mmr_t overflow_ni_fifo_vc1_credit : 1; - mmr_t overflow_ni_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc3_credit : 1; - mmr_t tail_timeout_fifo02_vc0 : 1; - mmr_t tail_timeout_fifo02_vc2 : 1; - mmr_t tail_timeout_fifo13_vc1 : 1; - mmr_t tail_timeout_fifo13_vc3 : 1; - mmr_t tail_timeout_ni_vc0 : 1; - mmr_t tail_timeout_ni_vc1 : 1; - mmr_t tail_timeout_ni_vc2 : 1; - mmr_t tail_timeout_ni_vc3 : 1; - } sh_ni0_first_error_1_s; -} sh_ni0_first_error_1_u_t; - -/* ==================================================================== */ -/* Register "SH_NI0_FIRST_ERROR_2" */ -/* ni0 First Error Bits */ -/* ==================================================================== */ - -typedef union sh_ni0_first_error_2_u { - mmr_t sh_ni0_first_error_2_regval; - struct { - mmr_t illegal_vcni : 1; - mmr_t illegal_vcpi : 1; - mmr_t illegal_vcmd : 1; - mmr_t illegal_vciilb : 1; - mmr_t underflow_fifo02_vc0_pop : 1; - mmr_t underflow_fifo02_vc2_pop : 1; - mmr_t underflow_fifo13_vc1_pop : 1; - mmr_t underflow_fifo13_vc3_pop : 1; - mmr_t underflow_fifo02_vc0_push : 1; - mmr_t underflow_fifo02_vc2_push : 1; - mmr_t underflow_fifo13_vc1_push : 1; - mmr_t underflow_fifo13_vc3_push : 1; - mmr_t underflow_fifo02_vc0_credit : 1; - mmr_t underflow_fifo02_vc2_credit : 1; - mmr_t underflow_fifo13_vc0_credit : 1; - mmr_t underflow_fifo13_vc2_credit : 1; - mmr_t underflow0_vc0_credit : 1; - mmr_t underflow1_vc0_credit : 1; - mmr_t underflow2_vc0_credit : 1; - mmr_t underflow0_vc2_credit : 1; - mmr_t underflow1_vc2_credit : 1; - mmr_t underflow2_vc2_credit : 1; - mmr_t reserved_0 : 10; - mmr_t underflow_pi_fifo_vc0_pop : 1; - mmr_t underflow_pi_fifo_vc2_pop : 1; - mmr_t underflow_iilb_fifo_vc0_pop : 1; - mmr_t underflow_iilb_fifo_vc2_pop : 1; - mmr_t underflow_md_fifo_vc0_pop : 1; - mmr_t underflow_md_fifo_vc2_pop : 1; - mmr_t underflow_ni_fifo_vc0_pop : 1; - mmr_t underflow_ni_fifo_vc2_pop : 1; - mmr_t underflow_pi_fifo_vc0_push : 1; - mmr_t underflow_pi_fifo_vc2_push : 1; - mmr_t underflow_iilb_fifo_vc0_push : 1; - mmr_t underflow_iilb_fifo_vc2_push : 1; - mmr_t underflow_md_fifo_vc0_push : 1; - mmr_t underflow_md_fifo_vc2_push : 1; - mmr_t underflow_pi_fifo_vc0_credit : 1; - mmr_t underflow_pi_fifo_vc2_credit : 1; - mmr_t underflow_iilb_fifo_vc0_credit : 1; - mmr_t underflow_iilb_fifo_vc2_credit : 1; - mmr_t underflow_md_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc0_credit : 1; - mmr_t underflow_ni_fifo_vc1_credit : 1; - mmr_t underflow_ni_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc3_credit : 1; - mmr_t llp_deadlock_vc0 : 1; - mmr_t llp_deadlock_vc1 : 1; - mmr_t llp_deadlock_vc2 : 1; - mmr_t llp_deadlock_vc3 : 1; - mmr_t chiplet_nomatch : 1; - mmr_t lut_read_error : 1; - mmr_t retry_timeout_error : 1; - mmr_t reserved_1 : 1; - } sh_ni0_first_error_2_s; -} sh_ni0_first_error_2_u_t; - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_DETAIL_1" */ -/* ni0 Chiplet no match header bits 63:0 */ -/* ==================================================================== */ - -typedef union sh_ni0_error_detail_1_u { - mmr_t sh_ni0_error_detail_1_regval; - struct { - mmr_t header : 64; - } sh_ni0_error_detail_1_s; -} sh_ni0_error_detail_1_u_t; - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_DETAIL_2" */ -/* ni0 Chiplet no match header bits 127:64 */ -/* ==================================================================== */ - -typedef union sh_ni0_error_detail_2_u { - mmr_t sh_ni0_error_detail_2_regval; - struct { - mmr_t header : 64; - } sh_ni0_error_detail_2_s; -} sh_ni0_error_detail_2_u_t; - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_SUMMARY_1" */ -/* ni1 Error Summary Bits */ -/* ==================================================================== */ - -typedef union sh_ni1_error_summary_1_u { - mmr_t sh_ni1_error_summary_1_regval; - struct { - mmr_t overflow_fifo02_debit0 : 1; - mmr_t overflow_fifo02_debit2 : 1; - mmr_t overflow_fifo13_debit0 : 1; - mmr_t overflow_fifo13_debit2 : 1; - mmr_t overflow_fifo02_vc0_pop : 1; - mmr_t overflow_fifo02_vc2_pop : 1; - mmr_t overflow_fifo13_vc1_pop : 1; - mmr_t overflow_fifo13_vc3_pop : 1; - mmr_t overflow_fifo02_vc0_push : 1; - mmr_t overflow_fifo02_vc2_push : 1; - mmr_t overflow_fifo13_vc1_push : 1; - mmr_t overflow_fifo13_vc3_push : 1; - mmr_t overflow_fifo02_vc0_credit : 1; - mmr_t overflow_fifo02_vc2_credit : 1; - mmr_t overflow_fifo13_vc0_credit : 1; - mmr_t overflow_fifo13_vc2_credit : 1; - mmr_t overflow0_vc0_credit : 1; - mmr_t overflow1_vc0_credit : 1; - mmr_t overflow2_vc0_credit : 1; - mmr_t overflow0_vc2_credit : 1; - mmr_t overflow1_vc2_credit : 1; - mmr_t overflow2_vc2_credit : 1; - mmr_t overflow_pi_fifo_debit0 : 1; - mmr_t overflow_pi_fifo_debit2 : 1; - mmr_t overflow_iilb_fifo_debit0 : 1; - mmr_t overflow_iilb_fifo_debit2 : 1; - mmr_t overflow_md_fifo_debit0 : 1; - mmr_t overflow_md_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit0 : 1; - mmr_t overflow_ni_fifo_debit1 : 1; - mmr_t overflow_ni_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit3 : 1; - mmr_t overflow_pi_fifo_vc0_pop : 1; - mmr_t overflow_pi_fifo_vc2_pop : 1; - mmr_t overflow_iilb_fifo_vc0_pop : 1; - mmr_t overflow_iilb_fifo_vc2_pop : 1; - mmr_t overflow_md_fifo_vc0_pop : 1; - mmr_t overflow_md_fifo_vc2_pop : 1; - mmr_t overflow_ni_fifo_vc0_pop : 1; - mmr_t overflow_ni_fifo_vc2_pop : 1; - mmr_t overflow_pi_fifo_vc0_push : 1; - mmr_t overflow_pi_fifo_vc2_push : 1; - mmr_t overflow_iilb_fifo_vc0_push : 1; - mmr_t overflow_iilb_fifo_vc2_push : 1; - mmr_t overflow_md_fifo_vc0_push : 1; - mmr_t overflow_md_fifo_vc2_push : 1; - mmr_t overflow_pi_fifo_vc0_credit : 1; - mmr_t overflow_pi_fifo_vc2_credit : 1; - mmr_t overflow_iilb_fifo_vc0_credit : 1; - mmr_t overflow_iilb_fifo_vc2_credit : 1; - mmr_t overflow_md_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc0_credit : 1; - mmr_t overflow_ni_fifo_vc1_credit : 1; - mmr_t overflow_ni_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc3_credit : 1; - mmr_t tail_timeout_fifo02_vc0 : 1; - mmr_t tail_timeout_fifo02_vc2 : 1; - mmr_t tail_timeout_fifo13_vc1 : 1; - mmr_t tail_timeout_fifo13_vc3 : 1; - mmr_t tail_timeout_ni_vc0 : 1; - mmr_t tail_timeout_ni_vc1 : 1; - mmr_t tail_timeout_ni_vc2 : 1; - mmr_t tail_timeout_ni_vc3 : 1; - } sh_ni1_error_summary_1_s; -} sh_ni1_error_summary_1_u_t; - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_SUMMARY_2" */ -/* ni1 Error Summary Bits */ -/* ==================================================================== */ - -typedef union sh_ni1_error_summary_2_u { - mmr_t sh_ni1_error_summary_2_regval; - struct { - mmr_t illegal_vcni : 1; - mmr_t illegal_vcpi : 1; - mmr_t illegal_vcmd : 1; - mmr_t illegal_vciilb : 1; - mmr_t underflow_fifo02_vc0_pop : 1; - mmr_t underflow_fifo02_vc2_pop : 1; - mmr_t underflow_fifo13_vc1_pop : 1; - mmr_t underflow_fifo13_vc3_pop : 1; - mmr_t underflow_fifo02_vc0_push : 1; - mmr_t underflow_fifo02_vc2_push : 1; - mmr_t underflow_fifo13_vc1_push : 1; - mmr_t underflow_fifo13_vc3_push : 1; - mmr_t underflow_fifo02_vc0_credit : 1; - mmr_t underflow_fifo02_vc2_credit : 1; - mmr_t underflow_fifo13_vc0_credit : 1; - mmr_t underflow_fifo13_vc2_credit : 1; - mmr_t underflow0_vc0_credit : 1; - mmr_t underflow1_vc0_credit : 1; - mmr_t underflow2_vc0_credit : 1; - mmr_t underflow0_vc2_credit : 1; - mmr_t underflow1_vc2_credit : 1; - mmr_t underflow2_vc2_credit : 1; - mmr_t reserved_0 : 10; - mmr_t underflow_pi_fifo_vc0_pop : 1; - mmr_t underflow_pi_fifo_vc2_pop : 1; - mmr_t underflow_iilb_fifo_vc0_pop : 1; - mmr_t underflow_iilb_fifo_vc2_pop : 1; - mmr_t underflow_md_fifo_vc0_pop : 1; - mmr_t underflow_md_fifo_vc2_pop : 1; - mmr_t underflow_ni_fifo_vc0_pop : 1; - mmr_t underflow_ni_fifo_vc2_pop : 1; - mmr_t underflow_pi_fifo_vc0_push : 1; - mmr_t underflow_pi_fifo_vc2_push : 1; - mmr_t underflow_iilb_fifo_vc0_push : 1; - mmr_t underflow_iilb_fifo_vc2_push : 1; - mmr_t underflow_md_fifo_vc0_push : 1; - mmr_t underflow_md_fifo_vc2_push : 1; - mmr_t underflow_pi_fifo_vc0_credit : 1; - mmr_t underflow_pi_fifo_vc2_credit : 1; - mmr_t underflow_iilb_fifo_vc0_credit : 1; - mmr_t underflow_iilb_fifo_vc2_credit : 1; - mmr_t underflow_md_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc0_credit : 1; - mmr_t underflow_ni_fifo_vc1_credit : 1; - mmr_t underflow_ni_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc3_credit : 1; - mmr_t llp_deadlock_vc0 : 1; - mmr_t llp_deadlock_vc1 : 1; - mmr_t llp_deadlock_vc2 : 1; - mmr_t llp_deadlock_vc3 : 1; - mmr_t chiplet_nomatch : 1; - mmr_t lut_read_error : 1; - mmr_t retry_timeout_error : 1; - mmr_t reserved_1 : 1; - } sh_ni1_error_summary_2_s; -} sh_ni1_error_summary_2_u_t; - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_OVERFLOW_1" */ -/* ni1 Error Overflow Bits */ -/* ==================================================================== */ - -typedef union sh_ni1_error_overflow_1_u { - mmr_t sh_ni1_error_overflow_1_regval; - struct { - mmr_t overflow_fifo02_debit0 : 1; - mmr_t overflow_fifo02_debit2 : 1; - mmr_t overflow_fifo13_debit0 : 1; - mmr_t overflow_fifo13_debit2 : 1; - mmr_t overflow_fifo02_vc0_pop : 1; - mmr_t overflow_fifo02_vc2_pop : 1; - mmr_t overflow_fifo13_vc1_pop : 1; - mmr_t overflow_fifo13_vc3_pop : 1; - mmr_t overflow_fifo02_vc0_push : 1; - mmr_t overflow_fifo02_vc2_push : 1; - mmr_t overflow_fifo13_vc1_push : 1; - mmr_t overflow_fifo13_vc3_push : 1; - mmr_t overflow_fifo02_vc0_credit : 1; - mmr_t overflow_fifo02_vc2_credit : 1; - mmr_t overflow_fifo13_vc0_credit : 1; - mmr_t overflow_fifo13_vc2_credit : 1; - mmr_t overflow0_vc0_credit : 1; - mmr_t overflow1_vc0_credit : 1; - mmr_t overflow2_vc0_credit : 1; - mmr_t overflow0_vc2_credit : 1; - mmr_t overflow1_vc2_credit : 1; - mmr_t overflow2_vc2_credit : 1; - mmr_t overflow_pi_fifo_debit0 : 1; - mmr_t overflow_pi_fifo_debit2 : 1; - mmr_t overflow_iilb_fifo_debit0 : 1; - mmr_t overflow_iilb_fifo_debit2 : 1; - mmr_t overflow_md_fifo_debit0 : 1; - mmr_t overflow_md_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit0 : 1; - mmr_t overflow_ni_fifo_debit1 : 1; - mmr_t overflow_ni_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit3 : 1; - mmr_t overflow_pi_fifo_vc0_pop : 1; - mmr_t overflow_pi_fifo_vc2_pop : 1; - mmr_t overflow_iilb_fifo_vc0_pop : 1; - mmr_t overflow_iilb_fifo_vc2_pop : 1; - mmr_t overflow_md_fifo_vc0_pop : 1; - mmr_t overflow_md_fifo_vc2_pop : 1; - mmr_t overflow_ni_fifo_vc0_pop : 1; - mmr_t overflow_ni_fifo_vc2_pop : 1; - mmr_t overflow_pi_fifo_vc0_push : 1; - mmr_t overflow_pi_fifo_vc2_push : 1; - mmr_t overflow_iilb_fifo_vc0_push : 1; - mmr_t overflow_iilb_fifo_vc2_push : 1; - mmr_t overflow_md_fifo_vc0_push : 1; - mmr_t overflow_md_fifo_vc2_push : 1; - mmr_t overflow_pi_fifo_vc0_credit : 1; - mmr_t overflow_pi_fifo_vc2_credit : 1; - mmr_t overflow_iilb_fifo_vc0_credit : 1; - mmr_t overflow_iilb_fifo_vc2_credit : 1; - mmr_t overflow_md_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc0_credit : 1; - mmr_t overflow_ni_fifo_vc1_credit : 1; - mmr_t overflow_ni_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc3_credit : 1; - mmr_t tail_timeout_fifo02_vc0 : 1; - mmr_t tail_timeout_fifo02_vc2 : 1; - mmr_t tail_timeout_fifo13_vc1 : 1; - mmr_t tail_timeout_fifo13_vc3 : 1; - mmr_t tail_timeout_ni_vc0 : 1; - mmr_t tail_timeout_ni_vc1 : 1; - mmr_t tail_timeout_ni_vc2 : 1; - mmr_t tail_timeout_ni_vc3 : 1; - } sh_ni1_error_overflow_1_s; -} sh_ni1_error_overflow_1_u_t; - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_OVERFLOW_2" */ -/* ni1 Error Overflow Bits */ -/* ==================================================================== */ - -typedef union sh_ni1_error_overflow_2_u { - mmr_t sh_ni1_error_overflow_2_regval; - struct { - mmr_t illegal_vcni : 1; - mmr_t illegal_vcpi : 1; - mmr_t illegal_vcmd : 1; - mmr_t illegal_vciilb : 1; - mmr_t underflow_fifo02_vc0_pop : 1; - mmr_t underflow_fifo02_vc2_pop : 1; - mmr_t underflow_fifo13_vc1_pop : 1; - mmr_t underflow_fifo13_vc3_pop : 1; - mmr_t underflow_fifo02_vc0_push : 1; - mmr_t underflow_fifo02_vc2_push : 1; - mmr_t underflow_fifo13_vc1_push : 1; - mmr_t underflow_fifo13_vc3_push : 1; - mmr_t underflow_fifo02_vc0_credit : 1; - mmr_t underflow_fifo02_vc2_credit : 1; - mmr_t underflow_fifo13_vc0_credit : 1; - mmr_t underflow_fifo13_vc2_credit : 1; - mmr_t underflow0_vc0_credit : 1; - mmr_t underflow1_vc0_credit : 1; - mmr_t underflow2_vc0_credit : 1; - mmr_t underflow0_vc2_credit : 1; - mmr_t underflow1_vc2_credit : 1; - mmr_t underflow2_vc2_credit : 1; - mmr_t reserved_0 : 10; - mmr_t underflow_pi_fifo_vc0_pop : 1; - mmr_t underflow_pi_fifo_vc2_pop : 1; - mmr_t underflow_iilb_fifo_vc0_pop : 1; - mmr_t underflow_iilb_fifo_vc2_pop : 1; - mmr_t underflow_md_fifo_vc0_pop : 1; - mmr_t underflow_md_fifo_vc2_pop : 1; - mmr_t underflow_ni_fifo_vc0_pop : 1; - mmr_t underflow_ni_fifo_vc2_pop : 1; - mmr_t underflow_pi_fifo_vc0_push : 1; - mmr_t underflow_pi_fifo_vc2_push : 1; - mmr_t underflow_iilb_fifo_vc0_push : 1; - mmr_t underflow_iilb_fifo_vc2_push : 1; - mmr_t underflow_md_fifo_vc0_push : 1; - mmr_t underflow_md_fifo_vc2_push : 1; - mmr_t underflow_pi_fifo_vc0_credit : 1; - mmr_t underflow_pi_fifo_vc2_credit : 1; - mmr_t underflow_iilb_fifo_vc0_credit : 1; - mmr_t underflow_iilb_fifo_vc2_credit : 1; - mmr_t underflow_md_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc0_credit : 1; - mmr_t underflow_ni_fifo_vc1_credit : 1; - mmr_t underflow_ni_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc3_credit : 1; - mmr_t llp_deadlock_vc0 : 1; - mmr_t llp_deadlock_vc1 : 1; - mmr_t llp_deadlock_vc2 : 1; - mmr_t llp_deadlock_vc3 : 1; - mmr_t chiplet_nomatch : 1; - mmr_t lut_read_error : 1; - mmr_t retry_timeout_error : 1; - mmr_t reserved_1 : 1; - } sh_ni1_error_overflow_2_s; -} sh_ni1_error_overflow_2_u_t; - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_MASK_1" */ -/* ni1 Error Mask Bits */ -/* ==================================================================== */ - -typedef union sh_ni1_error_mask_1_u { - mmr_t sh_ni1_error_mask_1_regval; - struct { - mmr_t overflow_fifo02_debit0 : 1; - mmr_t overflow_fifo02_debit2 : 1; - mmr_t overflow_fifo13_debit0 : 1; - mmr_t overflow_fifo13_debit2 : 1; - mmr_t overflow_fifo02_vc0_pop : 1; - mmr_t overflow_fifo02_vc2_pop : 1; - mmr_t overflow_fifo13_vc1_pop : 1; - mmr_t overflow_fifo13_vc3_pop : 1; - mmr_t overflow_fifo02_vc0_push : 1; - mmr_t overflow_fifo02_vc2_push : 1; - mmr_t overflow_fifo13_vc1_push : 1; - mmr_t overflow_fifo13_vc3_push : 1; - mmr_t overflow_fifo02_vc0_credit : 1; - mmr_t overflow_fifo02_vc2_credit : 1; - mmr_t overflow_fifo13_vc0_credit : 1; - mmr_t overflow_fifo13_vc2_credit : 1; - mmr_t overflow0_vc0_credit : 1; - mmr_t overflow1_vc0_credit : 1; - mmr_t overflow2_vc0_credit : 1; - mmr_t overflow0_vc2_credit : 1; - mmr_t overflow1_vc2_credit : 1; - mmr_t overflow2_vc2_credit : 1; - mmr_t overflow_pi_fifo_debit0 : 1; - mmr_t overflow_pi_fifo_debit2 : 1; - mmr_t overflow_iilb_fifo_debit0 : 1; - mmr_t overflow_iilb_fifo_debit2 : 1; - mmr_t overflow_md_fifo_debit0 : 1; - mmr_t overflow_md_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit0 : 1; - mmr_t overflow_ni_fifo_debit1 : 1; - mmr_t overflow_ni_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit3 : 1; - mmr_t overflow_pi_fifo_vc0_pop : 1; - mmr_t overflow_pi_fifo_vc2_pop : 1; - mmr_t overflow_iilb_fifo_vc0_pop : 1; - mmr_t overflow_iilb_fifo_vc2_pop : 1; - mmr_t overflow_md_fifo_vc0_pop : 1; - mmr_t overflow_md_fifo_vc2_pop : 1; - mmr_t overflow_ni_fifo_vc0_pop : 1; - mmr_t overflow_ni_fifo_vc2_pop : 1; - mmr_t overflow_pi_fifo_vc0_push : 1; - mmr_t overflow_pi_fifo_vc2_push : 1; - mmr_t overflow_iilb_fifo_vc0_push : 1; - mmr_t overflow_iilb_fifo_vc2_push : 1; - mmr_t overflow_md_fifo_vc0_push : 1; - mmr_t overflow_md_fifo_vc2_push : 1; - mmr_t overflow_pi_fifo_vc0_credit : 1; - mmr_t overflow_pi_fifo_vc2_credit : 1; - mmr_t overflow_iilb_fifo_vc0_credit : 1; - mmr_t overflow_iilb_fifo_vc2_credit : 1; - mmr_t overflow_md_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc0_credit : 1; - mmr_t overflow_ni_fifo_vc1_credit : 1; - mmr_t overflow_ni_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc3_credit : 1; - mmr_t tail_timeout_fifo02_vc0 : 1; - mmr_t tail_timeout_fifo02_vc2 : 1; - mmr_t tail_timeout_fifo13_vc1 : 1; - mmr_t tail_timeout_fifo13_vc3 : 1; - mmr_t tail_timeout_ni_vc0 : 1; - mmr_t tail_timeout_ni_vc1 : 1; - mmr_t tail_timeout_ni_vc2 : 1; - mmr_t tail_timeout_ni_vc3 : 1; - } sh_ni1_error_mask_1_s; -} sh_ni1_error_mask_1_u_t; - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_MASK_2" */ -/* ni1 Error Mask Bits */ -/* ==================================================================== */ - -typedef union sh_ni1_error_mask_2_u { - mmr_t sh_ni1_error_mask_2_regval; - struct { - mmr_t illegal_vcni : 1; - mmr_t illegal_vcpi : 1; - mmr_t illegal_vcmd : 1; - mmr_t illegal_vciilb : 1; - mmr_t underflow_fifo02_vc0_pop : 1; - mmr_t underflow_fifo02_vc2_pop : 1; - mmr_t underflow_fifo13_vc1_pop : 1; - mmr_t underflow_fifo13_vc3_pop : 1; - mmr_t underflow_fifo02_vc0_push : 1; - mmr_t underflow_fifo02_vc2_push : 1; - mmr_t underflow_fifo13_vc1_push : 1; - mmr_t underflow_fifo13_vc3_push : 1; - mmr_t underflow_fifo02_vc0_credit : 1; - mmr_t underflow_fifo02_vc2_credit : 1; - mmr_t underflow_fifo13_vc0_credit : 1; - mmr_t underflow_fifo13_vc2_credit : 1; - mmr_t underflow0_vc0_credit : 1; - mmr_t underflow1_vc0_credit : 1; - mmr_t underflow2_vc0_credit : 1; - mmr_t underflow0_vc2_credit : 1; - mmr_t underflow1_vc2_credit : 1; - mmr_t underflow2_vc2_credit : 1; - mmr_t reserved_0 : 10; - mmr_t underflow_pi_fifo_vc0_pop : 1; - mmr_t underflow_pi_fifo_vc2_pop : 1; - mmr_t underflow_iilb_fifo_vc0_pop : 1; - mmr_t underflow_iilb_fifo_vc2_pop : 1; - mmr_t underflow_md_fifo_vc0_pop : 1; - mmr_t underflow_md_fifo_vc2_pop : 1; - mmr_t underflow_ni_fifo_vc0_pop : 1; - mmr_t underflow_ni_fifo_vc2_pop : 1; - mmr_t underflow_pi_fifo_vc0_push : 1; - mmr_t underflow_pi_fifo_vc2_push : 1; - mmr_t underflow_iilb_fifo_vc0_push : 1; - mmr_t underflow_iilb_fifo_vc2_push : 1; - mmr_t underflow_md_fifo_vc0_push : 1; - mmr_t underflow_md_fifo_vc2_push : 1; - mmr_t underflow_pi_fifo_vc0_credit : 1; - mmr_t underflow_pi_fifo_vc2_credit : 1; - mmr_t underflow_iilb_fifo_vc0_credit : 1; - mmr_t underflow_iilb_fifo_vc2_credit : 1; - mmr_t underflow_md_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc0_credit : 1; - mmr_t underflow_ni_fifo_vc1_credit : 1; - mmr_t underflow_ni_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc3_credit : 1; - mmr_t llp_deadlock_vc0 : 1; - mmr_t llp_deadlock_vc1 : 1; - mmr_t llp_deadlock_vc2 : 1; - mmr_t llp_deadlock_vc3 : 1; - mmr_t chiplet_nomatch : 1; - mmr_t lut_read_error : 1; - mmr_t retry_timeout_error : 1; - mmr_t reserved_1 : 1; - } sh_ni1_error_mask_2_s; -} sh_ni1_error_mask_2_u_t; - -/* ==================================================================== */ -/* Register "SH_NI1_FIRST_ERROR_1" */ -/* ni1 First Error Bits */ -/* ==================================================================== */ - -typedef union sh_ni1_first_error_1_u { - mmr_t sh_ni1_first_error_1_regval; - struct { - mmr_t overflow_fifo02_debit0 : 1; - mmr_t overflow_fifo02_debit2 : 1; - mmr_t overflow_fifo13_debit0 : 1; - mmr_t overflow_fifo13_debit2 : 1; - mmr_t overflow_fifo02_vc0_pop : 1; - mmr_t overflow_fifo02_vc2_pop : 1; - mmr_t overflow_fifo13_vc1_pop : 1; - mmr_t overflow_fifo13_vc3_pop : 1; - mmr_t overflow_fifo02_vc0_push : 1; - mmr_t overflow_fifo02_vc2_push : 1; - mmr_t overflow_fifo13_vc1_push : 1; - mmr_t overflow_fifo13_vc3_push : 1; - mmr_t overflow_fifo02_vc0_credit : 1; - mmr_t overflow_fifo02_vc2_credit : 1; - mmr_t overflow_fifo13_vc0_credit : 1; - mmr_t overflow_fifo13_vc2_credit : 1; - mmr_t overflow0_vc0_credit : 1; - mmr_t overflow1_vc0_credit : 1; - mmr_t overflow2_vc0_credit : 1; - mmr_t overflow0_vc2_credit : 1; - mmr_t overflow1_vc2_credit : 1; - mmr_t overflow2_vc2_credit : 1; - mmr_t overflow_pi_fifo_debit0 : 1; - mmr_t overflow_pi_fifo_debit2 : 1; - mmr_t overflow_iilb_fifo_debit0 : 1; - mmr_t overflow_iilb_fifo_debit2 : 1; - mmr_t overflow_md_fifo_debit0 : 1; - mmr_t overflow_md_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit0 : 1; - mmr_t overflow_ni_fifo_debit1 : 1; - mmr_t overflow_ni_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit3 : 1; - mmr_t overflow_pi_fifo_vc0_pop : 1; - mmr_t overflow_pi_fifo_vc2_pop : 1; - mmr_t overflow_iilb_fifo_vc0_pop : 1; - mmr_t overflow_iilb_fifo_vc2_pop : 1; - mmr_t overflow_md_fifo_vc0_pop : 1; - mmr_t overflow_md_fifo_vc2_pop : 1; - mmr_t overflow_ni_fifo_vc0_pop : 1; - mmr_t overflow_ni_fifo_vc2_pop : 1; - mmr_t overflow_pi_fifo_vc0_push : 1; - mmr_t overflow_pi_fifo_vc2_push : 1; - mmr_t overflow_iilb_fifo_vc0_push : 1; - mmr_t overflow_iilb_fifo_vc2_push : 1; - mmr_t overflow_md_fifo_vc0_push : 1; - mmr_t overflow_md_fifo_vc2_push : 1; - mmr_t overflow_pi_fifo_vc0_credit : 1; - mmr_t overflow_pi_fifo_vc2_credit : 1; - mmr_t overflow_iilb_fifo_vc0_credit : 1; - mmr_t overflow_iilb_fifo_vc2_credit : 1; - mmr_t overflow_md_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc0_credit : 1; - mmr_t overflow_ni_fifo_vc1_credit : 1; - mmr_t overflow_ni_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc3_credit : 1; - mmr_t tail_timeout_fifo02_vc0 : 1; - mmr_t tail_timeout_fifo02_vc2 : 1; - mmr_t tail_timeout_fifo13_vc1 : 1; - mmr_t tail_timeout_fifo13_vc3 : 1; - mmr_t tail_timeout_ni_vc0 : 1; - mmr_t tail_timeout_ni_vc1 : 1; - mmr_t tail_timeout_ni_vc2 : 1; - mmr_t tail_timeout_ni_vc3 : 1; - } sh_ni1_first_error_1_s; -} sh_ni1_first_error_1_u_t; - -/* ==================================================================== */ -/* Register "SH_NI1_FIRST_ERROR_2" */ -/* ni1 First Error Bits */ -/* ==================================================================== */ - -typedef union sh_ni1_first_error_2_u { - mmr_t sh_ni1_first_error_2_regval; - struct { - mmr_t illegal_vcni : 1; - mmr_t illegal_vcpi : 1; - mmr_t illegal_vcmd : 1; - mmr_t illegal_vciilb : 1; - mmr_t underflow_fifo02_vc0_pop : 1; - mmr_t underflow_fifo02_vc2_pop : 1; - mmr_t underflow_fifo13_vc1_pop : 1; - mmr_t underflow_fifo13_vc3_pop : 1; - mmr_t underflow_fifo02_vc0_push : 1; - mmr_t underflow_fifo02_vc2_push : 1; - mmr_t underflow_fifo13_vc1_push : 1; - mmr_t underflow_fifo13_vc3_push : 1; - mmr_t underflow_fifo02_vc0_credit : 1; - mmr_t underflow_fifo02_vc2_credit : 1; - mmr_t underflow_fifo13_vc0_credit : 1; - mmr_t underflow_fifo13_vc2_credit : 1; - mmr_t underflow0_vc0_credit : 1; - mmr_t underflow1_vc0_credit : 1; - mmr_t underflow2_vc0_credit : 1; - mmr_t underflow0_vc2_credit : 1; - mmr_t underflow1_vc2_credit : 1; - mmr_t underflow2_vc2_credit : 1; - mmr_t reserved_0 : 10; - mmr_t underflow_pi_fifo_vc0_pop : 1; - mmr_t underflow_pi_fifo_vc2_pop : 1; - mmr_t underflow_iilb_fifo_vc0_pop : 1; - mmr_t underflow_iilb_fifo_vc2_pop : 1; - mmr_t underflow_md_fifo_vc0_pop : 1; - mmr_t underflow_md_fifo_vc2_pop : 1; - mmr_t underflow_ni_fifo_vc0_pop : 1; - mmr_t underflow_ni_fifo_vc2_pop : 1; - mmr_t underflow_pi_fifo_vc0_push : 1; - mmr_t underflow_pi_fifo_vc2_push : 1; - mmr_t underflow_iilb_fifo_vc0_push : 1; - mmr_t underflow_iilb_fifo_vc2_push : 1; - mmr_t underflow_md_fifo_vc0_push : 1; - mmr_t underflow_md_fifo_vc2_push : 1; - mmr_t underflow_pi_fifo_vc0_credit : 1; - mmr_t underflow_pi_fifo_vc2_credit : 1; - mmr_t underflow_iilb_fifo_vc0_credit : 1; - mmr_t underflow_iilb_fifo_vc2_credit : 1; - mmr_t underflow_md_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc0_credit : 1; - mmr_t underflow_ni_fifo_vc1_credit : 1; - mmr_t underflow_ni_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc3_credit : 1; - mmr_t llp_deadlock_vc0 : 1; - mmr_t llp_deadlock_vc1 : 1; - mmr_t llp_deadlock_vc2 : 1; - mmr_t llp_deadlock_vc3 : 1; - mmr_t chiplet_nomatch : 1; - mmr_t lut_read_error : 1; - mmr_t retry_timeout_error : 1; - mmr_t reserved_1 : 1; - } sh_ni1_first_error_2_s; -} sh_ni1_first_error_2_u_t; - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_DETAIL_1" */ -/* ni1 Chiplet no match header bits 63:0 */ -/* ==================================================================== */ - -typedef union sh_ni1_error_detail_1_u { - mmr_t sh_ni1_error_detail_1_regval; - struct { - mmr_t header : 64; - } sh_ni1_error_detail_1_s; -} sh_ni1_error_detail_1_u_t; - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_DETAIL_2" */ -/* ni1 Chiplet no match header bits 127:64 */ -/* ==================================================================== */ - -typedef union sh_ni1_error_detail_2_u { - mmr_t sh_ni1_error_detail_2_regval; - struct { - mmr_t header : 64; - } sh_ni1_error_detail_2_s; -} sh_ni1_error_detail_2_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_CORRECTED_DETAIL_1" */ -/* Corrected error details */ -/* ==================================================================== */ - -typedef union sh_xn_corrected_detail_1_u { - mmr_t sh_xn_corrected_detail_1_regval; - struct { - mmr_t ecc0_syndrome : 8; - mmr_t ecc0_wc : 2; - mmr_t ecc0_vc : 2; - mmr_t reserved_0 : 4; - mmr_t ecc1_syndrome : 8; - mmr_t ecc1_wc : 2; - mmr_t ecc1_vc : 2; - mmr_t reserved_1 : 4; - mmr_t ecc2_syndrome : 8; - mmr_t ecc2_wc : 2; - mmr_t ecc2_vc : 2; - mmr_t reserved_2 : 4; - mmr_t ecc3_syndrome : 8; - mmr_t ecc3_wc : 2; - mmr_t ecc3_vc : 2; - mmr_t reserved_3 : 4; - } sh_xn_corrected_detail_1_s; -} sh_xn_corrected_detail_1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_CORRECTED_DETAIL_2" */ -/* Corrected error data */ -/* ==================================================================== */ - -typedef union sh_xn_corrected_detail_2_u { - mmr_t sh_xn_corrected_detail_2_regval; - struct { - mmr_t data : 64; - } sh_xn_corrected_detail_2_s; -} sh_xn_corrected_detail_2_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_CORRECTED_DETAIL_3" */ -/* Corrected error header0 */ -/* ==================================================================== */ - -typedef union sh_xn_corrected_detail_3_u { - mmr_t sh_xn_corrected_detail_3_regval; - struct { - mmr_t header0 : 64; - } sh_xn_corrected_detail_3_s; -} sh_xn_corrected_detail_3_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_CORRECTED_DETAIL_4" */ -/* Corrected error header1 */ -/* ==================================================================== */ - -typedef union sh_xn_corrected_detail_4_u { - mmr_t sh_xn_corrected_detail_4_regval; - struct { - mmr_t header1 : 42; - mmr_t reserved_0 : 20; - mmr_t err_group : 2; - } sh_xn_corrected_detail_4_s; -} sh_xn_corrected_detail_4_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_UNCORRECTED_DETAIL_1" */ -/* Uncorrected error details */ -/* ==================================================================== */ - -typedef union sh_xn_uncorrected_detail_1_u { - mmr_t sh_xn_uncorrected_detail_1_regval; - struct { - mmr_t ecc0_syndrome : 8; - mmr_t ecc0_wc : 2; - mmr_t ecc0_vc : 2; - mmr_t reserved_0 : 4; - mmr_t ecc1_syndrome : 8; - mmr_t ecc1_wc : 2; - mmr_t ecc1_vc : 2; - mmr_t reserved_1 : 4; - mmr_t ecc2_syndrome : 8; - mmr_t ecc2_wc : 2; - mmr_t ecc2_vc : 2; - mmr_t reserved_2 : 4; - mmr_t ecc3_syndrome : 8; - mmr_t ecc3_wc : 2; - mmr_t ecc3_vc : 2; - mmr_t reserved_3 : 4; - } sh_xn_uncorrected_detail_1_s; -} sh_xn_uncorrected_detail_1_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_UNCORRECTED_DETAIL_2" */ -/* Uncorrected error data */ -/* ==================================================================== */ - -typedef union sh_xn_uncorrected_detail_2_u { - mmr_t sh_xn_uncorrected_detail_2_regval; - struct { - mmr_t data : 64; - } sh_xn_uncorrected_detail_2_s; -} sh_xn_uncorrected_detail_2_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_UNCORRECTED_DETAIL_3" */ -/* Uncorrected error header0 */ -/* ==================================================================== */ - -typedef union sh_xn_uncorrected_detail_3_u { - mmr_t sh_xn_uncorrected_detail_3_regval; - struct { - mmr_t header0 : 64; - } sh_xn_uncorrected_detail_3_s; -} sh_xn_uncorrected_detail_3_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_UNCORRECTED_DETAIL_4" */ -/* Uncorrected error header1 */ -/* ==================================================================== */ - -typedef union sh_xn_uncorrected_detail_4_u { - mmr_t sh_xn_uncorrected_detail_4_regval; - struct { - mmr_t header1 : 42; - mmr_t reserved_0 : 20; - mmr_t err_group : 2; - } sh_xn_uncorrected_detail_4_s; -} sh_xn_uncorrected_detail_4_u_t; - -/* ==================================================================== */ -/* Register "SH_XNMD_ERROR_DETAIL_1" */ -/* Look Up Table Address (md) */ -/* ==================================================================== */ - -typedef union sh_xnmd_error_detail_1_u { - mmr_t sh_xnmd_error_detail_1_regval; - struct { - mmr_t lut_addr : 11; - mmr_t reserved_0 : 53; - } sh_xnmd_error_detail_1_s; -} sh_xnmd_error_detail_1_u_t; - -/* ==================================================================== */ -/* Register "SH_XNPI_ERROR_DETAIL_1" */ -/* Look Up Table Address (pi) */ -/* ==================================================================== */ - -typedef union sh_xnpi_error_detail_1_u { - mmr_t sh_xnpi_error_detail_1_regval; - struct { - mmr_t lut_addr : 11; - mmr_t reserved_0 : 53; - } sh_xnpi_error_detail_1_s; -} sh_xnpi_error_detail_1_u_t; - -/* ==================================================================== */ -/* Register "SH_XNIILB_ERROR_DETAIL_1" */ -/* Chiplet NoMatch header [63:0] */ -/* ==================================================================== */ - -typedef union sh_xniilb_error_detail_1_u { - mmr_t sh_xniilb_error_detail_1_regval; - struct { - mmr_t header : 64; - } sh_xniilb_error_detail_1_s; -} sh_xniilb_error_detail_1_u_t; - -/* ==================================================================== */ -/* Register "SH_XNIILB_ERROR_DETAIL_2" */ -/* Chiplet NoMatch header [127:64] */ -/* ==================================================================== */ - -typedef union sh_xniilb_error_detail_2_u { - mmr_t sh_xniilb_error_detail_2_regval; - struct { - mmr_t header : 64; - } sh_xniilb_error_detail_2_s; -} sh_xniilb_error_detail_2_u_t; - -/* ==================================================================== */ -/* Register "SH_XNIILB_ERROR_DETAIL_3" */ -/* Look Up Table Address (iilb) */ -/* ==================================================================== */ - -typedef union sh_xniilb_error_detail_3_u { - mmr_t sh_xniilb_error_detail_3_regval; - struct { - mmr_t lut_addr : 11; - mmr_t reserved_0 : 53; - } sh_xniilb_error_detail_3_s; -} sh_xniilb_error_detail_3_u_t; - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_DETAIL_3" */ -/* Look Up Table Address (ni0) */ -/* ==================================================================== */ - -typedef union sh_ni0_error_detail_3_u { - mmr_t sh_ni0_error_detail_3_regval; - struct { - mmr_t lut_addr : 11; - mmr_t reserved_0 : 53; - } sh_ni0_error_detail_3_s; -} sh_ni0_error_detail_3_u_t; - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_DETAIL_3" */ -/* Look Up Table Address (ni1) */ -/* ==================================================================== */ - -typedef union sh_ni1_error_detail_3_u { - mmr_t sh_ni1_error_detail_3_regval; - struct { - mmr_t lut_addr : 11; - mmr_t reserved_0 : 53; - } sh_ni1_error_detail_3_s; -} sh_ni1_error_detail_3_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_ERROR_SUMMARY" */ -/* ==================================================================== */ - -typedef union sh_xn_error_summary_u { - mmr_t sh_xn_error_summary_regval; - struct { - mmr_t ni0_pop_overflow : 1; - mmr_t ni0_push_overflow : 1; - mmr_t ni0_credit_overflow : 1; - mmr_t ni0_debit_overflow : 1; - mmr_t ni0_pop_underflow : 1; - mmr_t ni0_push_underflow : 1; - mmr_t ni0_credit_underflow : 1; - mmr_t ni0_llp_error : 1; - mmr_t ni0_pipe_error : 1; - mmr_t ni1_pop_overflow : 1; - mmr_t ni1_push_overflow : 1; - mmr_t ni1_credit_overflow : 1; - mmr_t ni1_debit_overflow : 1; - mmr_t ni1_pop_underflow : 1; - mmr_t ni1_push_underflow : 1; - mmr_t ni1_credit_underflow : 1; - mmr_t ni1_llp_error : 1; - mmr_t ni1_pipe_error : 1; - mmr_t xnmd_credit_overflow : 1; - mmr_t xnmd_debit_overflow : 1; - mmr_t xnmd_data_buff_overflow : 1; - mmr_t xnmd_credit_underflow : 1; - mmr_t xnmd_sbe_error : 1; - mmr_t xnmd_uce_error : 1; - mmr_t xnmd_lut_error : 1; - mmr_t xnpi_credit_overflow : 1; - mmr_t xnpi_debit_overflow : 1; - mmr_t xnpi_data_buff_overflow : 1; - mmr_t xnpi_credit_underflow : 1; - mmr_t xnpi_sbe_error : 1; - mmr_t xnpi_uce_error : 1; - mmr_t xnpi_lut_error : 1; - mmr_t iilb_debit_overflow : 1; - mmr_t iilb_credit_overflow : 1; - mmr_t iilb_fifo_overflow : 1; - mmr_t iilb_credit_underflow : 1; - mmr_t iilb_fifo_underflow : 1; - mmr_t iilb_chiplet_or_lut : 1; - mmr_t reserved_0 : 26; - } sh_xn_error_summary_s; -} sh_xn_error_summary_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_ERROR_OVERFLOW" */ -/* ==================================================================== */ - -typedef union sh_xn_error_overflow_u { - mmr_t sh_xn_error_overflow_regval; - struct { - mmr_t ni0_pop_overflow : 1; - mmr_t ni0_push_overflow : 1; - mmr_t ni0_credit_overflow : 1; - mmr_t ni0_debit_overflow : 1; - mmr_t ni0_pop_underflow : 1; - mmr_t ni0_push_underflow : 1; - mmr_t ni0_credit_underflow : 1; - mmr_t ni0_llp_error : 1; - mmr_t ni0_pipe_error : 1; - mmr_t ni1_pop_overflow : 1; - mmr_t ni1_push_overflow : 1; - mmr_t ni1_credit_overflow : 1; - mmr_t ni1_debit_overflow : 1; - mmr_t ni1_pop_underflow : 1; - mmr_t ni1_push_underflow : 1; - mmr_t ni1_credit_underflow : 1; - mmr_t ni1_llp_error : 1; - mmr_t ni1_pipe_error : 1; - mmr_t xnmd_credit_overflow : 1; - mmr_t xnmd_debit_overflow : 1; - mmr_t xnmd_data_buff_overflow : 1; - mmr_t xnmd_credit_underflow : 1; - mmr_t xnmd_sbe_error : 1; - mmr_t xnmd_uce_error : 1; - mmr_t xnmd_lut_error : 1; - mmr_t xnpi_credit_overflow : 1; - mmr_t xnpi_debit_overflow : 1; - mmr_t xnpi_data_buff_overflow : 1; - mmr_t xnpi_credit_underflow : 1; - mmr_t xnpi_sbe_error : 1; - mmr_t xnpi_uce_error : 1; - mmr_t xnpi_lut_error : 1; - mmr_t iilb_debit_overflow : 1; - mmr_t iilb_credit_overflow : 1; - mmr_t iilb_fifo_overflow : 1; - mmr_t iilb_credit_underflow : 1; - mmr_t iilb_fifo_underflow : 1; - mmr_t iilb_chiplet_or_lut : 1; - mmr_t reserved_0 : 26; - } sh_xn_error_overflow_s; -} sh_xn_error_overflow_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_ERROR_MASK" */ -/* ==================================================================== */ - -typedef union sh_xn_error_mask_u { - mmr_t sh_xn_error_mask_regval; - struct { - mmr_t ni0_pop_overflow : 1; - mmr_t ni0_push_overflow : 1; - mmr_t ni0_credit_overflow : 1; - mmr_t ni0_debit_overflow : 1; - mmr_t ni0_pop_underflow : 1; - mmr_t ni0_push_underflow : 1; - mmr_t ni0_credit_underflow : 1; - mmr_t ni0_llp_error : 1; - mmr_t ni0_pipe_error : 1; - mmr_t ni1_pop_overflow : 1; - mmr_t ni1_push_overflow : 1; - mmr_t ni1_credit_overflow : 1; - mmr_t ni1_debit_overflow : 1; - mmr_t ni1_pop_underflow : 1; - mmr_t ni1_push_underflow : 1; - mmr_t ni1_credit_underflow : 1; - mmr_t ni1_llp_error : 1; - mmr_t ni1_pipe_error : 1; - mmr_t xnmd_credit_overflow : 1; - mmr_t xnmd_debit_overflow : 1; - mmr_t xnmd_data_buff_overflow : 1; - mmr_t xnmd_credit_underflow : 1; - mmr_t xnmd_sbe_error : 1; - mmr_t xnmd_uce_error : 1; - mmr_t xnmd_lut_error : 1; - mmr_t xnpi_credit_overflow : 1; - mmr_t xnpi_debit_overflow : 1; - mmr_t xnpi_data_buff_overflow : 1; - mmr_t xnpi_credit_underflow : 1; - mmr_t xnpi_sbe_error : 1; - mmr_t xnpi_uce_error : 1; - mmr_t xnpi_lut_error : 1; - mmr_t iilb_debit_overflow : 1; - mmr_t iilb_credit_overflow : 1; - mmr_t iilb_fifo_overflow : 1; - mmr_t iilb_credit_underflow : 1; - mmr_t iilb_fifo_underflow : 1; - mmr_t iilb_chiplet_or_lut : 1; - mmr_t reserved_0 : 26; - } sh_xn_error_mask_s; -} sh_xn_error_mask_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_FIRST_ERROR" */ -/* ==================================================================== */ - -typedef union sh_xn_first_error_u { - mmr_t sh_xn_first_error_regval; - struct { - mmr_t ni0_pop_overflow : 1; - mmr_t ni0_push_overflow : 1; - mmr_t ni0_credit_overflow : 1; - mmr_t ni0_debit_overflow : 1; - mmr_t ni0_pop_underflow : 1; - mmr_t ni0_push_underflow : 1; - mmr_t ni0_credit_underflow : 1; - mmr_t ni0_llp_error : 1; - mmr_t ni0_pipe_error : 1; - mmr_t ni1_pop_overflow : 1; - mmr_t ni1_push_overflow : 1; - mmr_t ni1_credit_overflow : 1; - mmr_t ni1_debit_overflow : 1; - mmr_t ni1_pop_underflow : 1; - mmr_t ni1_push_underflow : 1; - mmr_t ni1_credit_underflow : 1; - mmr_t ni1_llp_error : 1; - mmr_t ni1_pipe_error : 1; - mmr_t xnmd_credit_overflow : 1; - mmr_t xnmd_debit_overflow : 1; - mmr_t xnmd_data_buff_overflow : 1; - mmr_t xnmd_credit_underflow : 1; - mmr_t xnmd_sbe_error : 1; - mmr_t xnmd_uce_error : 1; - mmr_t xnmd_lut_error : 1; - mmr_t xnpi_credit_overflow : 1; - mmr_t xnpi_debit_overflow : 1; - mmr_t xnpi_data_buff_overflow : 1; - mmr_t xnpi_credit_underflow : 1; - mmr_t xnpi_sbe_error : 1; - mmr_t xnpi_uce_error : 1; - mmr_t xnpi_lut_error : 1; - mmr_t iilb_debit_overflow : 1; - mmr_t iilb_credit_overflow : 1; - mmr_t iilb_fifo_overflow : 1; - mmr_t iilb_credit_underflow : 1; - mmr_t iilb_fifo_underflow : 1; - mmr_t iilb_chiplet_or_lut : 1; - mmr_t reserved_0 : 26; - } sh_xn_first_error_s; -} sh_xn_first_error_u_t; - -/* ==================================================================== */ -/* Register "SH_XNIILB_ERROR_SUMMARY" */ -/* ==================================================================== */ - -typedef union sh_xniilb_error_summary_u { - mmr_t sh_xniilb_error_summary_regval; - struct { - mmr_t overflow_ii_debit0 : 1; - mmr_t overflow_ii_debit2 : 1; - mmr_t overflow_lb_debit0 : 1; - mmr_t overflow_lb_debit2 : 1; - mmr_t overflow_ii_vc0 : 1; - mmr_t overflow_ii_vc2 : 1; - mmr_t underflow_ii_vc0 : 1; - mmr_t underflow_ii_vc2 : 1; - mmr_t overflow_lb_vc0 : 1; - mmr_t overflow_lb_vc2 : 1; - mmr_t underflow_lb_vc0 : 1; - mmr_t underflow_lb_vc2 : 1; - mmr_t overflow_pi_vc0_credit_in : 1; - mmr_t overflow_iilb_vc0_credit_in : 1; - mmr_t overflow_md_vc0_credit_in : 1; - mmr_t overflow_ni0_vc0_credit_in : 1; - mmr_t overflow_ni1_vc0_credit_in : 1; - mmr_t overflow_pi_vc2_credit_in : 1; - mmr_t overflow_iilb_vc2_credit_in : 1; - mmr_t overflow_md_vc2_credit_in : 1; - mmr_t overflow_ni0_vc2_credit_in : 1; - mmr_t overflow_ni1_vc2_credit_in : 1; - mmr_t underflow_pi_vc0_credit_in : 1; - mmr_t underflow_iilb_vc0_credit_in : 1; - mmr_t underflow_md_vc0_credit_in : 1; - mmr_t underflow_ni0_vc0_credit_in : 1; - mmr_t underflow_ni1_vc0_credit_in : 1; - mmr_t underflow_pi_vc2_credit_in : 1; - mmr_t underflow_iilb_vc2_credit_in : 1; - mmr_t underflow_md_vc2_credit_in : 1; - mmr_t underflow_ni0_vc2_credit_in : 1; - mmr_t underflow_ni1_vc2_credit_in : 1; - mmr_t overflow_pi_debit0 : 1; - mmr_t overflow_pi_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t overflow_md_debit0 : 1; - mmr_t overflow_md_debit2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_pi_vc0_credit_out : 1; - mmr_t overflow_pi_vc2_credit_out : 1; - mmr_t overflow_md_vc0_credit_out : 1; - mmr_t overflow_md_vc2_credit_out : 1; - mmr_t overflow_iilb_vc0_credit_out : 1; - mmr_t overflow_iilb_vc2_credit_out : 1; - mmr_t overflow_ni0_vc0_credit_out : 1; - mmr_t overflow_ni0_vc2_credit_out : 1; - mmr_t overflow_ni1_vc0_credit_out : 1; - mmr_t overflow_ni1_vc2_credit_out : 1; - mmr_t underflow_pi_vc0_credit_out : 1; - mmr_t underflow_pi_vc2_credit_out : 1; - mmr_t underflow_md_vc0_credit_out : 1; - mmr_t underflow_md_vc2_credit_out : 1; - mmr_t underflow_iilb_vc0_credit_out : 1; - mmr_t underflow_iilb_vc2_credit_out : 1; - mmr_t underflow_ni0_vc0_credit_out : 1; - mmr_t underflow_ni0_vc2_credit_out : 1; - mmr_t underflow_ni1_vc0_credit_out : 1; - mmr_t underflow_ni1_vc2_credit_out : 1; - mmr_t chiplet_nomatch : 1; - mmr_t lut_read_error : 1; - } sh_xniilb_error_summary_s; -} sh_xniilb_error_summary_u_t; - -/* ==================================================================== */ -/* Register "SH_XNIILB_ERROR_OVERFLOW" */ -/* ==================================================================== */ - -typedef union sh_xniilb_error_overflow_u { - mmr_t sh_xniilb_error_overflow_regval; - struct { - mmr_t overflow_ii_debit0 : 1; - mmr_t overflow_ii_debit2 : 1; - mmr_t overflow_lb_debit0 : 1; - mmr_t overflow_lb_debit2 : 1; - mmr_t overflow_ii_vc0 : 1; - mmr_t overflow_ii_vc2 : 1; - mmr_t underflow_ii_vc0 : 1; - mmr_t underflow_ii_vc2 : 1; - mmr_t overflow_lb_vc0 : 1; - mmr_t overflow_lb_vc2 : 1; - mmr_t underflow_lb_vc0 : 1; - mmr_t underflow_lb_vc2 : 1; - mmr_t overflow_pi_vc0_credit_in : 1; - mmr_t overflow_iilb_vc0_credit_in : 1; - mmr_t overflow_md_vc0_credit_in : 1; - mmr_t overflow_ni0_vc0_credit_in : 1; - mmr_t overflow_ni1_vc0_credit_in : 1; - mmr_t overflow_pi_vc2_credit_in : 1; - mmr_t overflow_iilb_vc2_credit_in : 1; - mmr_t overflow_md_vc2_credit_in : 1; - mmr_t overflow_ni0_vc2_credit_in : 1; - mmr_t overflow_ni1_vc2_credit_in : 1; - mmr_t underflow_pi_vc0_credit_in : 1; - mmr_t underflow_iilb_vc0_credit_in : 1; - mmr_t underflow_md_vc0_credit_in : 1; - mmr_t underflow_ni0_vc0_credit_in : 1; - mmr_t underflow_ni1_vc0_credit_in : 1; - mmr_t underflow_pi_vc2_credit_in : 1; - mmr_t underflow_iilb_vc2_credit_in : 1; - mmr_t underflow_md_vc2_credit_in : 1; - mmr_t underflow_ni0_vc2_credit_in : 1; - mmr_t underflow_ni1_vc2_credit_in : 1; - mmr_t overflow_pi_debit0 : 1; - mmr_t overflow_pi_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t overflow_md_debit0 : 1; - mmr_t overflow_md_debit2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_pi_vc0_credit_out : 1; - mmr_t overflow_pi_vc2_credit_out : 1; - mmr_t overflow_md_vc0_credit_out : 1; - mmr_t overflow_md_vc2_credit_out : 1; - mmr_t overflow_iilb_vc0_credit_out : 1; - mmr_t overflow_iilb_vc2_credit_out : 1; - mmr_t overflow_ni0_vc0_credit_out : 1; - mmr_t overflow_ni0_vc2_credit_out : 1; - mmr_t overflow_ni1_vc0_credit_out : 1; - mmr_t overflow_ni1_vc2_credit_out : 1; - mmr_t underflow_pi_vc0_credit_out : 1; - mmr_t underflow_pi_vc2_credit_out : 1; - mmr_t underflow_md_vc0_credit_out : 1; - mmr_t underflow_md_vc2_credit_out : 1; - mmr_t underflow_iilb_vc0_credit_out : 1; - mmr_t underflow_iilb_vc2_credit_out : 1; - mmr_t underflow_ni0_vc0_credit_out : 1; - mmr_t underflow_ni0_vc2_credit_out : 1; - mmr_t underflow_ni1_vc0_credit_out : 1; - mmr_t underflow_ni1_vc2_credit_out : 1; - mmr_t chiplet_nomatch : 1; - mmr_t lut_read_error : 1; - } sh_xniilb_error_overflow_s; -} sh_xniilb_error_overflow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNIILB_ERROR_MASK" */ -/* ==================================================================== */ - -typedef union sh_xniilb_error_mask_u { - mmr_t sh_xniilb_error_mask_regval; - struct { - mmr_t overflow_ii_debit0 : 1; - mmr_t overflow_ii_debit2 : 1; - mmr_t overflow_lb_debit0 : 1; - mmr_t overflow_lb_debit2 : 1; - mmr_t overflow_ii_vc0 : 1; - mmr_t overflow_ii_vc2 : 1; - mmr_t underflow_ii_vc0 : 1; - mmr_t underflow_ii_vc2 : 1; - mmr_t overflow_lb_vc0 : 1; - mmr_t overflow_lb_vc2 : 1; - mmr_t underflow_lb_vc0 : 1; - mmr_t underflow_lb_vc2 : 1; - mmr_t overflow_pi_vc0_credit_in : 1; - mmr_t overflow_iilb_vc0_credit_in : 1; - mmr_t overflow_md_vc0_credit_in : 1; - mmr_t overflow_ni0_vc0_credit_in : 1; - mmr_t overflow_ni1_vc0_credit_in : 1; - mmr_t overflow_pi_vc2_credit_in : 1; - mmr_t overflow_iilb_vc2_credit_in : 1; - mmr_t overflow_md_vc2_credit_in : 1; - mmr_t overflow_ni0_vc2_credit_in : 1; - mmr_t overflow_ni1_vc2_credit_in : 1; - mmr_t underflow_pi_vc0_credit_in : 1; - mmr_t underflow_iilb_vc0_credit_in : 1; - mmr_t underflow_md_vc0_credit_in : 1; - mmr_t underflow_ni0_vc0_credit_in : 1; - mmr_t underflow_ni1_vc0_credit_in : 1; - mmr_t underflow_pi_vc2_credit_in : 1; - mmr_t underflow_iilb_vc2_credit_in : 1; - mmr_t underflow_md_vc2_credit_in : 1; - mmr_t underflow_ni0_vc2_credit_in : 1; - mmr_t underflow_ni1_vc2_credit_in : 1; - mmr_t overflow_pi_debit0 : 1; - mmr_t overflow_pi_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t overflow_md_debit0 : 1; - mmr_t overflow_md_debit2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_pi_vc0_credit_out : 1; - mmr_t overflow_pi_vc2_credit_out : 1; - mmr_t overflow_md_vc0_credit_out : 1; - mmr_t overflow_md_vc2_credit_out : 1; - mmr_t overflow_iilb_vc0_credit_out : 1; - mmr_t overflow_iilb_vc2_credit_out : 1; - mmr_t overflow_ni0_vc0_credit_out : 1; - mmr_t overflow_ni0_vc2_credit_out : 1; - mmr_t overflow_ni1_vc0_credit_out : 1; - mmr_t overflow_ni1_vc2_credit_out : 1; - mmr_t underflow_pi_vc0_credit_out : 1; - mmr_t underflow_pi_vc2_credit_out : 1; - mmr_t underflow_md_vc0_credit_out : 1; - mmr_t underflow_md_vc2_credit_out : 1; - mmr_t underflow_iilb_vc0_credit_out : 1; - mmr_t underflow_iilb_vc2_credit_out : 1; - mmr_t underflow_ni0_vc0_credit_out : 1; - mmr_t underflow_ni0_vc2_credit_out : 1; - mmr_t underflow_ni1_vc0_credit_out : 1; - mmr_t underflow_ni1_vc2_credit_out : 1; - mmr_t chiplet_nomatch : 1; - mmr_t lut_read_error : 1; - } sh_xniilb_error_mask_s; -} sh_xniilb_error_mask_u_t; - -/* ==================================================================== */ -/* Register "SH_XNIILB_FIRST_ERROR" */ -/* ==================================================================== */ - -typedef union sh_xniilb_first_error_u { - mmr_t sh_xniilb_first_error_regval; - struct { - mmr_t overflow_ii_debit0 : 1; - mmr_t overflow_ii_debit2 : 1; - mmr_t overflow_lb_debit0 : 1; - mmr_t overflow_lb_debit2 : 1; - mmr_t overflow_ii_vc0 : 1; - mmr_t overflow_ii_vc2 : 1; - mmr_t underflow_ii_vc0 : 1; - mmr_t underflow_ii_vc2 : 1; - mmr_t overflow_lb_vc0 : 1; - mmr_t overflow_lb_vc2 : 1; - mmr_t underflow_lb_vc0 : 1; - mmr_t underflow_lb_vc2 : 1; - mmr_t overflow_pi_vc0_credit_in : 1; - mmr_t overflow_iilb_vc0_credit_in : 1; - mmr_t overflow_md_vc0_credit_in : 1; - mmr_t overflow_ni0_vc0_credit_in : 1; - mmr_t overflow_ni1_vc0_credit_in : 1; - mmr_t overflow_pi_vc2_credit_in : 1; - mmr_t overflow_iilb_vc2_credit_in : 1; - mmr_t overflow_md_vc2_credit_in : 1; - mmr_t overflow_ni0_vc2_credit_in : 1; - mmr_t overflow_ni1_vc2_credit_in : 1; - mmr_t underflow_pi_vc0_credit_in : 1; - mmr_t underflow_iilb_vc0_credit_in : 1; - mmr_t underflow_md_vc0_credit_in : 1; - mmr_t underflow_ni0_vc0_credit_in : 1; - mmr_t underflow_ni1_vc0_credit_in : 1; - mmr_t underflow_pi_vc2_credit_in : 1; - mmr_t underflow_iilb_vc2_credit_in : 1; - mmr_t underflow_md_vc2_credit_in : 1; - mmr_t underflow_ni0_vc2_credit_in : 1; - mmr_t underflow_ni1_vc2_credit_in : 1; - mmr_t overflow_pi_debit0 : 1; - mmr_t overflow_pi_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t overflow_md_debit0 : 1; - mmr_t overflow_md_debit2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_pi_vc0_credit_out : 1; - mmr_t overflow_pi_vc2_credit_out : 1; - mmr_t overflow_md_vc0_credit_out : 1; - mmr_t overflow_md_vc2_credit_out : 1; - mmr_t overflow_iilb_vc0_credit_out : 1; - mmr_t overflow_iilb_vc2_credit_out : 1; - mmr_t overflow_ni0_vc0_credit_out : 1; - mmr_t overflow_ni0_vc2_credit_out : 1; - mmr_t overflow_ni1_vc0_credit_out : 1; - mmr_t overflow_ni1_vc2_credit_out : 1; - mmr_t underflow_pi_vc0_credit_out : 1; - mmr_t underflow_pi_vc2_credit_out : 1; - mmr_t underflow_md_vc0_credit_out : 1; - mmr_t underflow_md_vc2_credit_out : 1; - mmr_t underflow_iilb_vc0_credit_out : 1; - mmr_t underflow_iilb_vc2_credit_out : 1; - mmr_t underflow_ni0_vc0_credit_out : 1; - mmr_t underflow_ni0_vc2_credit_out : 1; - mmr_t underflow_ni1_vc0_credit_out : 1; - mmr_t underflow_ni1_vc2_credit_out : 1; - mmr_t chiplet_nomatch : 1; - mmr_t lut_read_error : 1; - } sh_xniilb_first_error_s; -} sh_xniilb_first_error_u_t; - -/* ==================================================================== */ -/* Register "SH_XNPI_ERROR_SUMMARY" */ -/* ==================================================================== */ - -typedef union sh_xnpi_error_summary_u { - mmr_t sh_xnpi_error_summary_regval; - struct { - mmr_t underflow_ni0_vc0 : 1; - mmr_t overflow_ni0_vc0 : 1; - mmr_t underflow_ni0_vc2 : 1; - mmr_t overflow_ni0_vc2 : 1; - mmr_t underflow_ni1_vc0 : 1; - mmr_t overflow_ni1_vc0 : 1; - mmr_t underflow_ni1_vc2 : 1; - mmr_t overflow_ni1_vc2 : 1; - mmr_t underflow_iilb_vc0 : 1; - mmr_t overflow_iilb_vc0 : 1; - mmr_t underflow_iilb_vc2 : 1; - mmr_t overflow_iilb_vc2 : 1; - mmr_t underflow_vc0_credit : 1; - mmr_t overflow_vc0_credit : 1; - mmr_t underflow_vc2_credit : 1; - mmr_t overflow_vc2_credit : 1; - mmr_t overflow_databuff_vc0 : 1; - mmr_t overflow_databuff_vc2 : 1; - mmr_t lut_read_error : 1; - mmr_t single_bit_error0 : 1; - mmr_t single_bit_error1 : 1; - mmr_t single_bit_error2 : 1; - mmr_t single_bit_error3 : 1; - mmr_t uncor_error0 : 1; - mmr_t uncor_error1 : 1; - mmr_t uncor_error2 : 1; - mmr_t uncor_error3 : 1; - mmr_t underflow_sic_cntr0 : 1; - mmr_t overflow_sic_cntr0 : 1; - mmr_t underflow_sic_cntr2 : 1; - mmr_t overflow_sic_cntr2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t underflow_ni0_vc0_credit : 1; - mmr_t overflow_ni0_vc0_credit : 1; - mmr_t underflow_ni0_vc2_credit : 1; - mmr_t overflow_ni0_vc2_credit : 1; - mmr_t underflow_ni1_vc0_credit : 1; - mmr_t overflow_ni1_vc0_credit : 1; - mmr_t underflow_ni1_vc2_credit : 1; - mmr_t overflow_ni1_vc2_credit : 1; - mmr_t underflow_iilb_vc0_credit : 1; - mmr_t overflow_iilb_vc0_credit : 1; - mmr_t underflow_iilb_vc2_credit : 1; - mmr_t overflow_iilb_vc2_credit : 1; - mmr_t overflow_header_cancel_fifo : 1; - mmr_t reserved_0 : 14; - } sh_xnpi_error_summary_s; -} sh_xnpi_error_summary_u_t; - -/* ==================================================================== */ -/* Register "SH_XNPI_ERROR_OVERFLOW" */ -/* ==================================================================== */ - -typedef union sh_xnpi_error_overflow_u { - mmr_t sh_xnpi_error_overflow_regval; - struct { - mmr_t underflow_ni0_vc0 : 1; - mmr_t overflow_ni0_vc0 : 1; - mmr_t underflow_ni0_vc2 : 1; - mmr_t overflow_ni0_vc2 : 1; - mmr_t underflow_ni1_vc0 : 1; - mmr_t overflow_ni1_vc0 : 1; - mmr_t underflow_ni1_vc2 : 1; - mmr_t overflow_ni1_vc2 : 1; - mmr_t underflow_iilb_vc0 : 1; - mmr_t overflow_iilb_vc0 : 1; - mmr_t underflow_iilb_vc2 : 1; - mmr_t overflow_iilb_vc2 : 1; - mmr_t underflow_vc0_credit : 1; - mmr_t overflow_vc0_credit : 1; - mmr_t underflow_vc2_credit : 1; - mmr_t overflow_vc2_credit : 1; - mmr_t overflow_databuff_vc0 : 1; - mmr_t overflow_databuff_vc2 : 1; - mmr_t lut_read_error : 1; - mmr_t single_bit_error0 : 1; - mmr_t single_bit_error1 : 1; - mmr_t single_bit_error2 : 1; - mmr_t single_bit_error3 : 1; - mmr_t uncor_error0 : 1; - mmr_t uncor_error1 : 1; - mmr_t uncor_error2 : 1; - mmr_t uncor_error3 : 1; - mmr_t underflow_sic_cntr0 : 1; - mmr_t overflow_sic_cntr0 : 1; - mmr_t underflow_sic_cntr2 : 1; - mmr_t overflow_sic_cntr2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t underflow_ni0_vc0_credit : 1; - mmr_t overflow_ni0_vc0_credit : 1; - mmr_t underflow_ni0_vc2_credit : 1; - mmr_t overflow_ni0_vc2_credit : 1; - mmr_t underflow_ni1_vc0_credit : 1; - mmr_t overflow_ni1_vc0_credit : 1; - mmr_t underflow_ni1_vc2_credit : 1; - mmr_t overflow_ni1_vc2_credit : 1; - mmr_t underflow_iilb_vc0_credit : 1; - mmr_t overflow_iilb_vc0_credit : 1; - mmr_t underflow_iilb_vc2_credit : 1; - mmr_t overflow_iilb_vc2_credit : 1; - mmr_t overflow_header_cancel_fifo : 1; - mmr_t reserved_0 : 14; - } sh_xnpi_error_overflow_s; -} sh_xnpi_error_overflow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNPI_ERROR_MASK" */ -/* ==================================================================== */ - -typedef union sh_xnpi_error_mask_u { - mmr_t sh_xnpi_error_mask_regval; - struct { - mmr_t underflow_ni0_vc0 : 1; - mmr_t overflow_ni0_vc0 : 1; - mmr_t underflow_ni0_vc2 : 1; - mmr_t overflow_ni0_vc2 : 1; - mmr_t underflow_ni1_vc0 : 1; - mmr_t overflow_ni1_vc0 : 1; - mmr_t underflow_ni1_vc2 : 1; - mmr_t overflow_ni1_vc2 : 1; - mmr_t underflow_iilb_vc0 : 1; - mmr_t overflow_iilb_vc0 : 1; - mmr_t underflow_iilb_vc2 : 1; - mmr_t overflow_iilb_vc2 : 1; - mmr_t underflow_vc0_credit : 1; - mmr_t overflow_vc0_credit : 1; - mmr_t underflow_vc2_credit : 1; - mmr_t overflow_vc2_credit : 1; - mmr_t overflow_databuff_vc0 : 1; - mmr_t overflow_databuff_vc2 : 1; - mmr_t lut_read_error : 1; - mmr_t single_bit_error0 : 1; - mmr_t single_bit_error1 : 1; - mmr_t single_bit_error2 : 1; - mmr_t single_bit_error3 : 1; - mmr_t uncor_error0 : 1; - mmr_t uncor_error1 : 1; - mmr_t uncor_error2 : 1; - mmr_t uncor_error3 : 1; - mmr_t underflow_sic_cntr0 : 1; - mmr_t overflow_sic_cntr0 : 1; - mmr_t underflow_sic_cntr2 : 1; - mmr_t overflow_sic_cntr2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t underflow_ni0_vc0_credit : 1; - mmr_t overflow_ni0_vc0_credit : 1; - mmr_t underflow_ni0_vc2_credit : 1; - mmr_t overflow_ni0_vc2_credit : 1; - mmr_t underflow_ni1_vc0_credit : 1; - mmr_t overflow_ni1_vc0_credit : 1; - mmr_t underflow_ni1_vc2_credit : 1; - mmr_t overflow_ni1_vc2_credit : 1; - mmr_t underflow_iilb_vc0_credit : 1; - mmr_t overflow_iilb_vc0_credit : 1; - mmr_t underflow_iilb_vc2_credit : 1; - mmr_t overflow_iilb_vc2_credit : 1; - mmr_t overflow_header_cancel_fifo : 1; - mmr_t reserved_0 : 14; - } sh_xnpi_error_mask_s; -} sh_xnpi_error_mask_u_t; - -/* ==================================================================== */ -/* Register "SH_XNPI_FIRST_ERROR" */ -/* ==================================================================== */ - -typedef union sh_xnpi_first_error_u { - mmr_t sh_xnpi_first_error_regval; - struct { - mmr_t underflow_ni0_vc0 : 1; - mmr_t overflow_ni0_vc0 : 1; - mmr_t underflow_ni0_vc2 : 1; - mmr_t overflow_ni0_vc2 : 1; - mmr_t underflow_ni1_vc0 : 1; - mmr_t overflow_ni1_vc0 : 1; - mmr_t underflow_ni1_vc2 : 1; - mmr_t overflow_ni1_vc2 : 1; - mmr_t underflow_iilb_vc0 : 1; - mmr_t overflow_iilb_vc0 : 1; - mmr_t underflow_iilb_vc2 : 1; - mmr_t overflow_iilb_vc2 : 1; - mmr_t underflow_vc0_credit : 1; - mmr_t overflow_vc0_credit : 1; - mmr_t underflow_vc2_credit : 1; - mmr_t overflow_vc2_credit : 1; - mmr_t overflow_databuff_vc0 : 1; - mmr_t overflow_databuff_vc2 : 1; - mmr_t lut_read_error : 1; - mmr_t single_bit_error0 : 1; - mmr_t single_bit_error1 : 1; - mmr_t single_bit_error2 : 1; - mmr_t single_bit_error3 : 1; - mmr_t uncor_error0 : 1; - mmr_t uncor_error1 : 1; - mmr_t uncor_error2 : 1; - mmr_t uncor_error3 : 1; - mmr_t underflow_sic_cntr0 : 1; - mmr_t overflow_sic_cntr0 : 1; - mmr_t underflow_sic_cntr2 : 1; - mmr_t overflow_sic_cntr2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t underflow_ni0_vc0_credit : 1; - mmr_t overflow_ni0_vc0_credit : 1; - mmr_t underflow_ni0_vc2_credit : 1; - mmr_t overflow_ni0_vc2_credit : 1; - mmr_t underflow_ni1_vc0_credit : 1; - mmr_t overflow_ni1_vc0_credit : 1; - mmr_t underflow_ni1_vc2_credit : 1; - mmr_t overflow_ni1_vc2_credit : 1; - mmr_t underflow_iilb_vc0_credit : 1; - mmr_t overflow_iilb_vc0_credit : 1; - mmr_t underflow_iilb_vc2_credit : 1; - mmr_t overflow_iilb_vc2_credit : 1; - mmr_t overflow_header_cancel_fifo : 1; - mmr_t reserved_0 : 14; - } sh_xnpi_first_error_s; -} sh_xnpi_first_error_u_t; - -/* ==================================================================== */ -/* Register "SH_XNMD_ERROR_SUMMARY" */ -/* ==================================================================== */ - -typedef union sh_xnmd_error_summary_u { - mmr_t sh_xnmd_error_summary_regval; - struct { - mmr_t underflow_ni0_vc0 : 1; - mmr_t overflow_ni0_vc0 : 1; - mmr_t underflow_ni0_vc2 : 1; - mmr_t overflow_ni0_vc2 : 1; - mmr_t underflow_ni1_vc0 : 1; - mmr_t overflow_ni1_vc0 : 1; - mmr_t underflow_ni1_vc2 : 1; - mmr_t overflow_ni1_vc2 : 1; - mmr_t underflow_iilb_vc0 : 1; - mmr_t overflow_iilb_vc0 : 1; - mmr_t underflow_iilb_vc2 : 1; - mmr_t overflow_iilb_vc2 : 1; - mmr_t underflow_vc0_credit : 1; - mmr_t overflow_vc0_credit : 1; - mmr_t underflow_vc2_credit : 1; - mmr_t overflow_vc2_credit : 1; - mmr_t overflow_databuff_vc0 : 1; - mmr_t overflow_databuff_vc2 : 1; - mmr_t lut_read_error : 1; - mmr_t single_bit_error0 : 1; - mmr_t single_bit_error1 : 1; - mmr_t single_bit_error2 : 1; - mmr_t single_bit_error3 : 1; - mmr_t uncor_error0 : 1; - mmr_t uncor_error1 : 1; - mmr_t uncor_error2 : 1; - mmr_t uncor_error3 : 1; - mmr_t underflow_sic_cntr0 : 1; - mmr_t overflow_sic_cntr0 : 1; - mmr_t underflow_sic_cntr2 : 1; - mmr_t overflow_sic_cntr2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t underflow_ni0_vc0_credit : 1; - mmr_t overflow_ni0_vc0_credit : 1; - mmr_t underflow_ni0_vc2_credit : 1; - mmr_t overflow_ni0_vc2_credit : 1; - mmr_t underflow_ni1_vc0_credit : 1; - mmr_t overflow_ni1_vc0_credit : 1; - mmr_t underflow_ni1_vc2_credit : 1; - mmr_t overflow_ni1_vc2_credit : 1; - mmr_t underflow_iilb_vc0_credit : 1; - mmr_t overflow_iilb_vc0_credit : 1; - mmr_t underflow_iilb_vc2_credit : 1; - mmr_t overflow_iilb_vc2_credit : 1; - mmr_t overflow_header_cancel_fifo : 1; - mmr_t reserved_0 : 14; - } sh_xnmd_error_summary_s; -} sh_xnmd_error_summary_u_t; - -/* ==================================================================== */ -/* Register "SH_XNMD_ERROR_OVERFLOW" */ -/* ==================================================================== */ - -typedef union sh_xnmd_error_overflow_u { - mmr_t sh_xnmd_error_overflow_regval; - struct { - mmr_t underflow_ni0_vc0 : 1; - mmr_t overflow_ni0_vc0 : 1; - mmr_t underflow_ni0_vc2 : 1; - mmr_t overflow_ni0_vc2 : 1; - mmr_t underflow_ni1_vc0 : 1; - mmr_t overflow_ni1_vc0 : 1; - mmr_t underflow_ni1_vc2 : 1; - mmr_t overflow_ni1_vc2 : 1; - mmr_t underflow_iilb_vc0 : 1; - mmr_t overflow_iilb_vc0 : 1; - mmr_t underflow_iilb_vc2 : 1; - mmr_t overflow_iilb_vc2 : 1; - mmr_t underflow_vc0_credit : 1; - mmr_t overflow_vc0_credit : 1; - mmr_t underflow_vc2_credit : 1; - mmr_t overflow_vc2_credit : 1; - mmr_t overflow_databuff_vc0 : 1; - mmr_t overflow_databuff_vc2 : 1; - mmr_t lut_read_error : 1; - mmr_t single_bit_error0 : 1; - mmr_t single_bit_error1 : 1; - mmr_t single_bit_error2 : 1; - mmr_t single_bit_error3 : 1; - mmr_t uncor_error0 : 1; - mmr_t uncor_error1 : 1; - mmr_t uncor_error2 : 1; - mmr_t uncor_error3 : 1; - mmr_t underflow_sic_cntr0 : 1; - mmr_t overflow_sic_cntr0 : 1; - mmr_t underflow_sic_cntr2 : 1; - mmr_t overflow_sic_cntr2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t underflow_ni0_vc0_credit : 1; - mmr_t overflow_ni0_vc0_credit : 1; - mmr_t underflow_ni0_vc2_credit : 1; - mmr_t overflow_ni0_vc2_credit : 1; - mmr_t underflow_ni1_vc0_credit : 1; - mmr_t overflow_ni1_vc0_credit : 1; - mmr_t underflow_ni1_vc2_credit : 1; - mmr_t overflow_ni1_vc2_credit : 1; - mmr_t underflow_iilb_vc0_credit : 1; - mmr_t overflow_iilb_vc0_credit : 1; - mmr_t underflow_iilb_vc2_credit : 1; - mmr_t overflow_iilb_vc2_credit : 1; - mmr_t overflow_header_cancel_fifo : 1; - mmr_t reserved_0 : 14; - } sh_xnmd_error_overflow_s; -} sh_xnmd_error_overflow_u_t; - -/* ==================================================================== */ -/* Register "SH_XNMD_ERROR_MASK" */ -/* ==================================================================== */ - -typedef union sh_xnmd_error_mask_u { - mmr_t sh_xnmd_error_mask_regval; - struct { - mmr_t underflow_ni0_vc0 : 1; - mmr_t overflow_ni0_vc0 : 1; - mmr_t underflow_ni0_vc2 : 1; - mmr_t overflow_ni0_vc2 : 1; - mmr_t underflow_ni1_vc0 : 1; - mmr_t overflow_ni1_vc0 : 1; - mmr_t underflow_ni1_vc2 : 1; - mmr_t overflow_ni1_vc2 : 1; - mmr_t underflow_iilb_vc0 : 1; - mmr_t overflow_iilb_vc0 : 1; - mmr_t underflow_iilb_vc2 : 1; - mmr_t overflow_iilb_vc2 : 1; - mmr_t underflow_vc0_credit : 1; - mmr_t overflow_vc0_credit : 1; - mmr_t underflow_vc2_credit : 1; - mmr_t overflow_vc2_credit : 1; - mmr_t overflow_databuff_vc0 : 1; - mmr_t overflow_databuff_vc2 : 1; - mmr_t lut_read_error : 1; - mmr_t single_bit_error0 : 1; - mmr_t single_bit_error1 : 1; - mmr_t single_bit_error2 : 1; - mmr_t single_bit_error3 : 1; - mmr_t uncor_error0 : 1; - mmr_t uncor_error1 : 1; - mmr_t uncor_error2 : 1; - mmr_t uncor_error3 : 1; - mmr_t underflow_sic_cntr0 : 1; - mmr_t overflow_sic_cntr0 : 1; - mmr_t underflow_sic_cntr2 : 1; - mmr_t overflow_sic_cntr2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t underflow_ni0_vc0_credit : 1; - mmr_t overflow_ni0_vc0_credit : 1; - mmr_t underflow_ni0_vc2_credit : 1; - mmr_t overflow_ni0_vc2_credit : 1; - mmr_t underflow_ni1_vc0_credit : 1; - mmr_t overflow_ni1_vc0_credit : 1; - mmr_t underflow_ni1_vc2_credit : 1; - mmr_t overflow_ni1_vc2_credit : 1; - mmr_t underflow_iilb_vc0_credit : 1; - mmr_t overflow_iilb_vc0_credit : 1; - mmr_t underflow_iilb_vc2_credit : 1; - mmr_t overflow_iilb_vc2_credit : 1; - mmr_t overflow_header_cancel_fifo : 1; - mmr_t reserved_0 : 14; - } sh_xnmd_error_mask_s; -} sh_xnmd_error_mask_u_t; - -/* ==================================================================== */ -/* Register "SH_XNMD_FIRST_ERROR" */ -/* ==================================================================== */ - -typedef union sh_xnmd_first_error_u { - mmr_t sh_xnmd_first_error_regval; - struct { - mmr_t underflow_ni0_vc0 : 1; - mmr_t overflow_ni0_vc0 : 1; - mmr_t underflow_ni0_vc2 : 1; - mmr_t overflow_ni0_vc2 : 1; - mmr_t underflow_ni1_vc0 : 1; - mmr_t overflow_ni1_vc0 : 1; - mmr_t underflow_ni1_vc2 : 1; - mmr_t overflow_ni1_vc2 : 1; - mmr_t underflow_iilb_vc0 : 1; - mmr_t overflow_iilb_vc0 : 1; - mmr_t underflow_iilb_vc2 : 1; - mmr_t overflow_iilb_vc2 : 1; - mmr_t underflow_vc0_credit : 1; - mmr_t overflow_vc0_credit : 1; - mmr_t underflow_vc2_credit : 1; - mmr_t overflow_vc2_credit : 1; - mmr_t overflow_databuff_vc0 : 1; - mmr_t overflow_databuff_vc2 : 1; - mmr_t lut_read_error : 1; - mmr_t single_bit_error0 : 1; - mmr_t single_bit_error1 : 1; - mmr_t single_bit_error2 : 1; - mmr_t single_bit_error3 : 1; - mmr_t uncor_error0 : 1; - mmr_t uncor_error1 : 1; - mmr_t uncor_error2 : 1; - mmr_t uncor_error3 : 1; - mmr_t underflow_sic_cntr0 : 1; - mmr_t overflow_sic_cntr0 : 1; - mmr_t underflow_sic_cntr2 : 1; - mmr_t overflow_sic_cntr2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t underflow_ni0_vc0_credit : 1; - mmr_t overflow_ni0_vc0_credit : 1; - mmr_t underflow_ni0_vc2_credit : 1; - mmr_t overflow_ni0_vc2_credit : 1; - mmr_t underflow_ni1_vc0_credit : 1; - mmr_t overflow_ni1_vc0_credit : 1; - mmr_t underflow_ni1_vc2_credit : 1; - mmr_t overflow_ni1_vc2_credit : 1; - mmr_t underflow_iilb_vc0_credit : 1; - mmr_t overflow_iilb_vc0_credit : 1; - mmr_t underflow_iilb_vc2_credit : 1; - mmr_t overflow_iilb_vc2_credit : 1; - mmr_t overflow_header_cancel_fifo : 1; - mmr_t reserved_0 : 14; - } sh_xnmd_first_error_s; -} sh_xnmd_first_error_u_t; - -/* ==================================================================== */ -/* Register "SH_AUTO_REPLY_ENABLE0" */ -/* Automatic Maintenance Reply Enable 0 */ -/* ==================================================================== */ - -typedef union sh_auto_reply_enable0_u { - mmr_t sh_auto_reply_enable0_regval; - struct { - mmr_t enable0 : 64; - } sh_auto_reply_enable0_s; -} sh_auto_reply_enable0_u_t; - -/* ==================================================================== */ -/* Register "SH_AUTO_REPLY_ENABLE1" */ -/* Automatic Maintenance Reply Enable 1 */ -/* ==================================================================== */ - -typedef union sh_auto_reply_enable1_u { - mmr_t sh_auto_reply_enable1_regval; - struct { - mmr_t enable1 : 64; - } sh_auto_reply_enable1_s; -} sh_auto_reply_enable1_u_t; - -/* ==================================================================== */ -/* Register "SH_AUTO_REPLY_HEADER0" */ -/* Automatic Maintenance Reply Header 0 */ -/* ==================================================================== */ - -typedef union sh_auto_reply_header0_u { - mmr_t sh_auto_reply_header0_regval; - struct { - mmr_t header0 : 64; - } sh_auto_reply_header0_s; -} sh_auto_reply_header0_u_t; - -/* ==================================================================== */ -/* Register "SH_AUTO_REPLY_HEADER1" */ -/* Automatic Maintenance Reply Header 1 */ -/* ==================================================================== */ - -typedef union sh_auto_reply_header1_u { - mmr_t sh_auto_reply_header1_regval; - struct { - mmr_t header1 : 64; - } sh_auto_reply_header1_s; -} sh_auto_reply_header1_u_t; - -/* ==================================================================== */ -/* Register "SH_ENABLE_RP_AUTO_REPLY" */ -/* Enable Automatic Maintenance Reply From Reply Queue */ -/* ==================================================================== */ - -typedef union sh_enable_rp_auto_reply_u { - mmr_t sh_enable_rp_auto_reply_regval; - struct { - mmr_t enable : 1; - mmr_t reserved_0 : 63; - } sh_enable_rp_auto_reply_s; -} sh_enable_rp_auto_reply_u_t; - -/* ==================================================================== */ -/* Register "SH_ENABLE_RQ_AUTO_REPLY" */ -/* Enable Automatic Maintenance Reply From Request Queue */ -/* ==================================================================== */ - -typedef union sh_enable_rq_auto_reply_u { - mmr_t sh_enable_rq_auto_reply_regval; - struct { - mmr_t enable : 1; - mmr_t reserved_0 : 63; - } sh_enable_rq_auto_reply_s; -} sh_enable_rq_auto_reply_u_t; - -/* ==================================================================== */ -/* Register "SH_REDIRECT_INVAL" */ -/* Redirect invalidate to LB instead of PI */ -/* ==================================================================== */ - -typedef union sh_redirect_inval_u { - mmr_t sh_redirect_inval_regval; - struct { - mmr_t redirect : 1; - mmr_t reserved_0 : 63; - } sh_redirect_inval_s; -} sh_redirect_inval_u_t; - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_CNTRL" */ -/* Diagnostic Message Control Register */ -/* ==================================================================== */ - -typedef union sh_diag_msg_cntrl_u { - mmr_t sh_diag_msg_cntrl_regval; - struct { - mmr_t msg_length : 6; - mmr_t error_inject_point : 6; - mmr_t error_inject_enable : 1; - mmr_t port : 1; - mmr_t reserved_0 : 48; - mmr_t start : 1; - mmr_t busy : 1; - } sh_diag_msg_cntrl_s; -} sh_diag_msg_cntrl_u_t; - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA0L" */ -/* Diagnostic Data, lower 64 bits */ -/* ==================================================================== */ - -typedef union sh_diag_msg_data0l_u { - mmr_t sh_diag_msg_data0l_regval; - struct { - mmr_t data_lower : 64; - } sh_diag_msg_data0l_s; -} sh_diag_msg_data0l_u_t; - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA0U" */ -/* Diagnostice Data, upper 64 bits */ -/* ==================================================================== */ - -typedef union sh_diag_msg_data0u_u { - mmr_t sh_diag_msg_data0u_regval; - struct { - mmr_t data_upper : 64; - } sh_diag_msg_data0u_s; -} sh_diag_msg_data0u_u_t; - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA1L" */ -/* Diagnostic Data, lower 64 bits */ -/* ==================================================================== */ - -typedef union sh_diag_msg_data1l_u { - mmr_t sh_diag_msg_data1l_regval; - struct { - mmr_t data_lower : 64; - } sh_diag_msg_data1l_s; -} sh_diag_msg_data1l_u_t; - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA1U" */ -/* Diagnostice Data, upper 64 bits */ -/* ==================================================================== */ - -typedef union sh_diag_msg_data1u_u { - mmr_t sh_diag_msg_data1u_regval; - struct { - mmr_t data_upper : 64; - } sh_diag_msg_data1u_s; -} sh_diag_msg_data1u_u_t; - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA2L" */ -/* Diagnostic Data, lower 64 bits */ -/* ==================================================================== */ - -typedef union sh_diag_msg_data2l_u { - mmr_t sh_diag_msg_data2l_regval; - struct { - mmr_t data_lower : 64; - } sh_diag_msg_data2l_s; -} sh_diag_msg_data2l_u_t; - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA2U" */ -/* Diagnostice Data, upper 64 bits */ -/* ==================================================================== */ - -typedef union sh_diag_msg_data2u_u { - mmr_t sh_diag_msg_data2u_regval; - struct { - mmr_t data_upper : 64; - } sh_diag_msg_data2u_s; -} sh_diag_msg_data2u_u_t; - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA3L" */ -/* Diagnostic Data, lower 64 bits */ -/* ==================================================================== */ - -typedef union sh_diag_msg_data3l_u { - mmr_t sh_diag_msg_data3l_regval; - struct { - mmr_t data_lower : 64; - } sh_diag_msg_data3l_s; -} sh_diag_msg_data3l_u_t; - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA3U" */ -/* Diagnostice Data, upper 64 bits */ -/* ==================================================================== */ - -typedef union sh_diag_msg_data3u_u { - mmr_t sh_diag_msg_data3u_regval; - struct { - mmr_t data_upper : 64; - } sh_diag_msg_data3u_s; -} sh_diag_msg_data3u_u_t; - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA4L" */ -/* Diagnostic Data, lower 64 bits */ -/* ==================================================================== */ - -typedef union sh_diag_msg_data4l_u { - mmr_t sh_diag_msg_data4l_regval; - struct { - mmr_t data_lower : 64; - } sh_diag_msg_data4l_s; -} sh_diag_msg_data4l_u_t; - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA4U" */ -/* Diagnostice Data, upper 64 bits */ -/* ==================================================================== */ - -typedef union sh_diag_msg_data4u_u { - mmr_t sh_diag_msg_data4u_regval; - struct { - mmr_t data_upper : 64; - } sh_diag_msg_data4u_s; -} sh_diag_msg_data4u_u_t; - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA5L" */ -/* Diagnostic Data, lower 64 bits */ -/* ==================================================================== */ - -typedef union sh_diag_msg_data5l_u { - mmr_t sh_diag_msg_data5l_regval; - struct { - mmr_t data_lower : 64; - } sh_diag_msg_data5l_s; -} sh_diag_msg_data5l_u_t; - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA5U" */ -/* Diagnostice Data, upper 64 bits */ -/* ==================================================================== */ - -typedef union sh_diag_msg_data5u_u { - mmr_t sh_diag_msg_data5u_regval; - struct { - mmr_t data_upper : 64; - } sh_diag_msg_data5u_s; -} sh_diag_msg_data5u_u_t; - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA6L" */ -/* Diagnostic Data, lower 64 bits */ -/* ==================================================================== */ - -typedef union sh_diag_msg_data6l_u { - mmr_t sh_diag_msg_data6l_regval; - struct { - mmr_t data_lower : 64; - } sh_diag_msg_data6l_s; -} sh_diag_msg_data6l_u_t; - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA6U" */ -/* Diagnostice Data, upper 64 bits */ -/* ==================================================================== */ - -typedef union sh_diag_msg_data6u_u { - mmr_t sh_diag_msg_data6u_regval; - struct { - mmr_t data_upper : 64; - } sh_diag_msg_data6u_s; -} sh_diag_msg_data6u_u_t; - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA7L" */ -/* Diagnostic Data, lower 64 bits */ -/* ==================================================================== */ - -typedef union sh_diag_msg_data7l_u { - mmr_t sh_diag_msg_data7l_regval; - struct { - mmr_t data_lower : 64; - } sh_diag_msg_data7l_s; -} sh_diag_msg_data7l_u_t; - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA7U" */ -/* Diagnostice Data, upper 64 bits */ -/* ==================================================================== */ - -typedef union sh_diag_msg_data7u_u { - mmr_t sh_diag_msg_data7u_regval; - struct { - mmr_t data_upper : 64; - } sh_diag_msg_data7u_s; -} sh_diag_msg_data7u_u_t; - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA8L" */ -/* Diagnostic Data, lower 64 bits */ -/* ==================================================================== */ - -typedef union sh_diag_msg_data8l_u { - mmr_t sh_diag_msg_data8l_regval; - struct { - mmr_t data_lower : 64; - } sh_diag_msg_data8l_s; -} sh_diag_msg_data8l_u_t; - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA8U" */ -/* Diagnostice Data, upper 64 bits */ -/* ==================================================================== */ - -typedef union sh_diag_msg_data8u_u { - mmr_t sh_diag_msg_data8u_regval; - struct { - mmr_t data_upper : 64; - } sh_diag_msg_data8u_s; -} sh_diag_msg_data8u_u_t; - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_HDR0" */ -/* Diagnostice Data, lower 64 bits of header */ -/* ==================================================================== */ - -typedef union sh_diag_msg_hdr0_u { - mmr_t sh_diag_msg_hdr0_regval; - struct { - mmr_t header0 : 64; - } sh_diag_msg_hdr0_s; -} sh_diag_msg_hdr0_u_t; - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_HDR1" */ -/* Diagnostice Data, upper 64 bits of header */ -/* ==================================================================== */ - -typedef union sh_diag_msg_hdr1_u { - mmr_t sh_diag_msg_hdr1_regval; - struct { - mmr_t header1 : 64; - } sh_diag_msg_hdr1_s; -} sh_diag_msg_hdr1_u_t; - -/* ==================================================================== */ -/* Register "SH_DEBUG_SELECT" */ -/* SHub Debug Port Select */ -/* ==================================================================== */ - -typedef union sh_debug_select_u { - mmr_t sh_debug_select_regval; - struct { - mmr_t nibble0_nibble_sel : 3; - mmr_t nibble0_chiplet_sel : 3; - mmr_t nibble1_nibble_sel : 3; - mmr_t nibble1_chiplet_sel : 3; - mmr_t nibble2_nibble_sel : 3; - mmr_t nibble2_chiplet_sel : 3; - mmr_t nibble3_nibble_sel : 3; - mmr_t nibble3_chiplet_sel : 3; - mmr_t nibble4_nibble_sel : 3; - mmr_t nibble4_chiplet_sel : 3; - mmr_t nibble5_nibble_sel : 3; - mmr_t nibble5_chiplet_sel : 3; - mmr_t nibble6_nibble_sel : 3; - mmr_t nibble6_chiplet_sel : 3; - mmr_t nibble7_nibble_sel : 3; - mmr_t nibble7_chiplet_sel : 3; - mmr_t debug_ii_sel : 3; - mmr_t sel_ii : 9; - mmr_t reserved_0 : 3; - mmr_t trigger_enable : 1; - } sh_debug_select_s; -} sh_debug_select_u_t; - -/* ==================================================================== */ -/* Register "SH_TRIGGER_COMPARE_MASK" */ -/* SHub Trigger Compare Mask */ -/* ==================================================================== */ - -typedef union sh_trigger_compare_mask_u { - mmr_t sh_trigger_compare_mask_regval; - struct { - mmr_t mask : 32; - mmr_t reserved_0 : 32; - } sh_trigger_compare_mask_s; -} sh_trigger_compare_mask_u_t; - -/* ==================================================================== */ -/* Register "SH_TRIGGER_COMPARE_PATTERN" */ -/* SHub Trigger Compare Pattern */ -/* ==================================================================== */ - -typedef union sh_trigger_compare_pattern_u { - mmr_t sh_trigger_compare_pattern_regval; - struct { - mmr_t data : 32; - mmr_t reserved_0 : 32; - } sh_trigger_compare_pattern_s; -} sh_trigger_compare_pattern_u_t; - -/* ==================================================================== */ -/* Register "SH_TRIGGER_SEL" */ -/* Trigger select for SHUB debug port */ -/* ==================================================================== */ - -typedef union sh_trigger_sel_u { - mmr_t sh_trigger_sel_regval; - struct { - mmr_t nibble0_input_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble1_input_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble2_input_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble3_input_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble4_input_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble5_input_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble6_input_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble7_input_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t reserved_15 : 1; - } sh_trigger_sel_s; -} sh_trigger_sel_u_t; - -/* ==================================================================== */ -/* Register "SH_STOP_CLK_CONTROL" */ -/* Stop Clock Control */ -/* ==================================================================== */ - -typedef union sh_stop_clk_control_u { - mmr_t sh_stop_clk_control_regval; - struct { - mmr_t stimulus : 5; - mmr_t event : 1; - mmr_t polarity : 1; - mmr_t mode : 1; - mmr_t reserved_0 : 56; - } sh_stop_clk_control_s; -} sh_stop_clk_control_u_t; - -/* ==================================================================== */ -/* Register "SH_STOP_CLK_DELAY_PHASE" */ -/* Stop Clock Delay Phase */ -/* ==================================================================== */ - -typedef union sh_stop_clk_delay_phase_u { - mmr_t sh_stop_clk_delay_phase_regval; - struct { - mmr_t delay : 8; - mmr_t reserved_0 : 56; - } sh_stop_clk_delay_phase_s; -} sh_stop_clk_delay_phase_u_t; - -/* ==================================================================== */ -/* Register "SH_TSF_ARM_MASK" */ -/* Trigger sequencing facility arm mask */ -/* ==================================================================== */ - -typedef union sh_tsf_arm_mask_u { - mmr_t sh_tsf_arm_mask_regval; - struct { - mmr_t mask : 64; - } sh_tsf_arm_mask_s; -} sh_tsf_arm_mask_u_t; - -/* ==================================================================== */ -/* Register "SH_TSF_COUNTER_PRESETS" */ -/* Trigger sequencing facility counter presets */ -/* ==================================================================== */ - -typedef union sh_tsf_counter_presets_u { - mmr_t sh_tsf_counter_presets_regval; - struct { - mmr_t count_32 : 32; - mmr_t count_16 : 16; - mmr_t count_8b : 8; - mmr_t count_8a : 8; - } sh_tsf_counter_presets_s; -} sh_tsf_counter_presets_u_t; - -/* ==================================================================== */ -/* Register "SH_TSF_DECREMENT_CTL" */ -/* Trigger sequencing facility counter decrement control */ -/* ==================================================================== */ - -typedef union sh_tsf_decrement_ctl_u { - mmr_t sh_tsf_decrement_ctl_regval; - struct { - mmr_t ctl : 16; - mmr_t reserved_0 : 48; - } sh_tsf_decrement_ctl_s; -} sh_tsf_decrement_ctl_u_t; - -/* ==================================================================== */ -/* Register "SH_TSF_DIAG_MSG_CTL" */ -/* Trigger sequencing facility diagnostic message control */ -/* ==================================================================== */ - -typedef union sh_tsf_diag_msg_ctl_u { - mmr_t sh_tsf_diag_msg_ctl_regval; - struct { - mmr_t enable : 8; - mmr_t reserved_0 : 56; - } sh_tsf_diag_msg_ctl_s; -} sh_tsf_diag_msg_ctl_u_t; - -/* ==================================================================== */ -/* Register "SH_TSF_DISARM_MASK" */ -/* Trigger sequencing facility disarm mask */ -/* ==================================================================== */ - -typedef union sh_tsf_disarm_mask_u { - mmr_t sh_tsf_disarm_mask_regval; - struct { - mmr_t mask : 64; - } sh_tsf_disarm_mask_s; -} sh_tsf_disarm_mask_u_t; - -/* ==================================================================== */ -/* Register "SH_TSF_ENABLE_CTL" */ -/* Trigger sequencing facility counter enable control */ -/* ==================================================================== */ - -typedef union sh_tsf_enable_ctl_u { - mmr_t sh_tsf_enable_ctl_regval; - struct { - mmr_t ctl : 16; - mmr_t reserved_0 : 48; - } sh_tsf_enable_ctl_s; -} sh_tsf_enable_ctl_u_t; - -/* ==================================================================== */ -/* Register "SH_TSF_SOFTWARE_ARM" */ -/* Trigger sequencing facility software arm */ -/* ==================================================================== */ - -typedef union sh_tsf_software_arm_u { - mmr_t sh_tsf_software_arm_regval; - struct { - mmr_t bit0 : 1; - mmr_t bit1 : 1; - mmr_t bit2 : 1; - mmr_t bit3 : 1; - mmr_t bit4 : 1; - mmr_t bit5 : 1; - mmr_t bit6 : 1; - mmr_t bit7 : 1; - mmr_t reserved_0 : 56; - } sh_tsf_software_arm_s; -} sh_tsf_software_arm_u_t; - -/* ==================================================================== */ -/* Register "SH_TSF_SOFTWARE_DISARM" */ -/* Trigger sequencing facility software disarm */ -/* ==================================================================== */ - -typedef union sh_tsf_software_disarm_u { - mmr_t sh_tsf_software_disarm_regval; - struct { - mmr_t bit0 : 1; - mmr_t bit1 : 1; - mmr_t bit2 : 1; - mmr_t bit3 : 1; - mmr_t bit4 : 1; - mmr_t bit5 : 1; - mmr_t bit6 : 1; - mmr_t bit7 : 1; - mmr_t reserved_0 : 56; - } sh_tsf_software_disarm_s; -} sh_tsf_software_disarm_u_t; - -/* ==================================================================== */ -/* Register "SH_TSF_SOFTWARE_TRIGGERED" */ -/* Trigger sequencing facility software triggered */ -/* ==================================================================== */ - -typedef union sh_tsf_software_triggered_u { - mmr_t sh_tsf_software_triggered_regval; - struct { - mmr_t bit0 : 1; - mmr_t bit1 : 1; - mmr_t bit2 : 1; - mmr_t bit3 : 1; - mmr_t bit4 : 1; - mmr_t bit5 : 1; - mmr_t bit6 : 1; - mmr_t bit7 : 1; - mmr_t reserved_0 : 56; - } sh_tsf_software_triggered_s; -} sh_tsf_software_triggered_u_t; - -/* ==================================================================== */ -/* Register "SH_TSF_TRIGGER_MASK" */ -/* Trigger sequencing facility trigger mask */ -/* ==================================================================== */ - -typedef union sh_tsf_trigger_mask_u { - mmr_t sh_tsf_trigger_mask_regval; - struct { - mmr_t mask : 64; - } sh_tsf_trigger_mask_s; -} sh_tsf_trigger_mask_u_t; - -/* ==================================================================== */ -/* Register "SH_VEC_DATA" */ -/* Vector Write Request Message Data */ -/* ==================================================================== */ - -typedef union sh_vec_data_u { - mmr_t sh_vec_data_regval; - struct { - mmr_t data : 64; - } sh_vec_data_s; -} sh_vec_data_u_t; - -/* ==================================================================== */ -/* Register "SH_VEC_PARMS" */ -/* Vector Message Parameters Register */ -/* ==================================================================== */ - -typedef union sh_vec_parms_u { - mmr_t sh_vec_parms_regval; - struct { - mmr_t type : 1; - mmr_t ni_port : 1; - mmr_t reserved_0 : 1; - mmr_t address : 32; - mmr_t pio_id : 11; - mmr_t reserved_1 : 16; - mmr_t start : 1; - mmr_t busy : 1; - } sh_vec_parms_s; -} sh_vec_parms_u_t; - -/* ==================================================================== */ -/* Register "SH_VEC_ROUTE" */ -/* Vector Request Message Route */ -/* ==================================================================== */ - -typedef union sh_vec_route_u { - mmr_t sh_vec_route_regval; - struct { - mmr_t route : 64; - } sh_vec_route_s; -} sh_vec_route_u_t; - -/* ==================================================================== */ -/* Register "SH_CPU_PERM" */ -/* CPU MMR Access Permission Bits */ -/* ==================================================================== */ - -typedef union sh_cpu_perm_u { - mmr_t sh_cpu_perm_regval; - struct { - mmr_t access_bits : 64; - } sh_cpu_perm_s; -} sh_cpu_perm_u_t; - -/* ==================================================================== */ -/* Register "SH_CPU_PERM_OVR" */ -/* CPU MMR Access Permission Override */ -/* ==================================================================== */ - -typedef union sh_cpu_perm_ovr_u { - mmr_t sh_cpu_perm_ovr_regval; - struct { - mmr_t override : 64; - } sh_cpu_perm_ovr_s; -} sh_cpu_perm_ovr_u_t; - -/* ==================================================================== */ -/* Register "SH_EXT_IO_PERM" */ -/* External IO MMR Access Permission Bits */ -/* ==================================================================== */ - -typedef union sh_ext_io_perm_u { - mmr_t sh_ext_io_perm_regval; - struct { - mmr_t access_bits : 64; - } sh_ext_io_perm_s; -} sh_ext_io_perm_u_t; - -/* ==================================================================== */ -/* Register "SH_EXT_IOI_ACCESS" */ -/* External IO Interrupt Access Permission Bits */ -/* ==================================================================== */ - -typedef union sh_ext_ioi_access_u { - mmr_t sh_ext_ioi_access_regval; - struct { - mmr_t access_bits : 64; - } sh_ext_ioi_access_s; -} sh_ext_ioi_access_u_t; - -/* ==================================================================== */ -/* Register "SH_GC_FIL_CTRL" */ -/* SHub Global Clock Filter Control */ -/* ==================================================================== */ - -typedef union sh_gc_fil_ctrl_u { - mmr_t sh_gc_fil_ctrl_regval; - struct { - mmr_t offset : 5; - mmr_t reserved_0 : 3; - mmr_t mask_counter : 12; - mmr_t mask_enable : 1; - mmr_t reserved_1 : 3; - mmr_t dropout_counter : 10; - mmr_t reserved_2 : 2; - mmr_t dropout_thresh : 10; - mmr_t reserved_3 : 2; - mmr_t error_counter : 10; - mmr_t reserved_4 : 6; - } sh_gc_fil_ctrl_s; -} sh_gc_fil_ctrl_u_t; - -/* ==================================================================== */ -/* Register "SH_GC_SRC_CTRL" */ -/* SHub Global Clock Control */ -/* ==================================================================== */ - -typedef union sh_gc_src_ctrl_u { - mmr_t sh_gc_src_ctrl_regval; - struct { - mmr_t enable_counter : 1; - mmr_t reserved_0 : 3; - mmr_t max_count : 10; - mmr_t reserved_1 : 2; - mmr_t counter : 10; - mmr_t reserved_2 : 2; - mmr_t toggle_bit : 1; - mmr_t reserved_3 : 3; - mmr_t source_sel : 2; - mmr_t reserved_4 : 30; - } sh_gc_src_ctrl_s; -} sh_gc_src_ctrl_u_t; - -/* ==================================================================== */ -/* Register "SH_HARD_RESET" */ -/* SHub Hard Reset */ -/* ==================================================================== */ - -typedef union sh_hard_reset_u { - mmr_t sh_hard_reset_regval; - struct { - mmr_t hard_reset : 1; - mmr_t reserved_0 : 63; - } sh_hard_reset_s; -} sh_hard_reset_u_t; - -/* ==================================================================== */ -/* Register "SH_IO_PERM" */ -/* II MMR Access Permission Bits */ -/* ==================================================================== */ - -typedef union sh_io_perm_u { - mmr_t sh_io_perm_regval; - struct { - mmr_t access_bits : 64; - } sh_io_perm_s; -} sh_io_perm_u_t; - -/* ==================================================================== */ -/* Register "SH_IOI_ACCESS" */ -/* II Interrupt Access Permission Bits */ -/* ==================================================================== */ - -typedef union sh_ioi_access_u { - mmr_t sh_ioi_access_regval; - struct { - mmr_t access_bits : 64; - } sh_ioi_access_s; -} sh_ioi_access_u_t; - -/* ==================================================================== */ -/* Register "SH_IPI_ACCESS" */ -/* CPU interrupt Access Permission Bits */ -/* ==================================================================== */ - -typedef union sh_ipi_access_u { - mmr_t sh_ipi_access_regval; - struct { - mmr_t access_bits : 64; - } sh_ipi_access_s; -} sh_ipi_access_u_t; - -/* ==================================================================== */ -/* Register "SH_JTAG_CONFIG" */ -/* SHub JTAG configuration */ -/* ==================================================================== */ - -typedef union sh_jtag_config_u { - mmr_t sh_jtag_config_regval; - struct { - mmr_t md_clk_sel : 2; - mmr_t ni_clk_sel : 1; - mmr_t ii_clk_sel : 2; - mmr_t wrt90_target : 14; - mmr_t wrt90_overrider : 1; - mmr_t wrt90_override : 1; - mmr_t jtag_mci_reset_delay : 4; - mmr_t jtag_mci_target : 14; - mmr_t jtag_mci_override : 1; - mmr_t fsb_config_ioq_depth : 1; - mmr_t fsb_config_sample_binit : 1; - mmr_t fsb_config_enable_bus_parking : 1; - mmr_t fsb_config_clock_ratio : 5; - mmr_t fsb_config_output_tristate : 4; - mmr_t fsb_config_enable_bist : 1; - mmr_t fsb_config_aux : 2; - mmr_t gtl_config_re : 1; - mmr_t reserved_0 : 8; - } sh_jtag_config_s; -} sh_jtag_config_u_t; - -/* ==================================================================== */ -/* Register "SH_SHUB_ID" */ -/* SHub ID Number */ -/* ==================================================================== */ - -typedef union sh_shub_id_u { - mmr_t sh_shub_id_regval; - struct { - mmr_t force1 : 1; - mmr_t manufacturer : 11; - mmr_t part_number : 16; - mmr_t revision : 4; - mmr_t node_id : 11; - mmr_t reserved_0 : 1; - mmr_t sharing_mode : 2; - mmr_t reserved_1 : 2; - mmr_t nodes_per_bit : 5; - mmr_t reserved_2 : 3; - mmr_t ni_port : 1; - mmr_t reserved_3 : 7; - } sh_shub_id_s; -} sh_shub_id_u_t; - -/* ==================================================================== */ -/* Register "SH_SHUBS_PRESENT0" */ -/* Shubs 0 - 63 Present. Used for invalidate generation */ -/* ==================================================================== */ - -typedef union sh_shubs_present0_u { - mmr_t sh_shubs_present0_regval; - struct { - mmr_t shubs_present0 : 64; - } sh_shubs_present0_s; -} sh_shubs_present0_u_t; - -/* ==================================================================== */ -/* Register "SH_SHUBS_PRESENT1" */ -/* Shubs 64 - 127 Present. Used for invalidate generation */ -/* ==================================================================== */ - -typedef union sh_shubs_present1_u { - mmr_t sh_shubs_present1_regval; - struct { - mmr_t shubs_present1 : 64; - } sh_shubs_present1_s; -} sh_shubs_present1_u_t; - -/* ==================================================================== */ -/* Register "SH_SHUBS_PRESENT2" */ -/* Shubs 128 - 191 Present. Used for invalidate generation */ -/* ==================================================================== */ - -typedef union sh_shubs_present2_u { - mmr_t sh_shubs_present2_regval; - struct { - mmr_t shubs_present2 : 64; - } sh_shubs_present2_s; -} sh_shubs_present2_u_t; - -/* ==================================================================== */ -/* Register "SH_SHUBS_PRESENT3" */ -/* Shubs 192 - 255 Present. Used for invalidate generation */ -/* ==================================================================== */ - -typedef union sh_shubs_present3_u { - mmr_t sh_shubs_present3_regval; - struct { - mmr_t shubs_present3 : 64; - } sh_shubs_present3_s; -} sh_shubs_present3_u_t; - -/* ==================================================================== */ -/* Register "SH_SOFT_RESET" */ -/* SHub Soft Reset */ -/* ==================================================================== */ - -typedef union sh_soft_reset_u { - mmr_t sh_soft_reset_regval; - struct { - mmr_t soft_reset : 1; - mmr_t reserved_0 : 63; - } sh_soft_reset_s; -} sh_soft_reset_u_t; - -/* ==================================================================== */ -/* Register "SH_FIRST_ERROR" */ -/* Shub Global First Error Flags */ -/* ==================================================================== */ - -typedef union sh_first_error_u { - mmr_t sh_first_error_regval; - struct { - mmr_t first_error : 19; - mmr_t reserved_0 : 45; - } sh_first_error_s; -} sh_first_error_u_t; - -/* ==================================================================== */ -/* Register "SH_II_HW_TIME_STAMP" */ -/* II hardware error time stamp */ -/* ==================================================================== */ - -typedef union sh_ii_hw_time_stamp_u { - mmr_t sh_ii_hw_time_stamp_regval; - struct { - mmr_t time : 63; - mmr_t valid : 1; - } sh_ii_hw_time_stamp_s; -} sh_ii_hw_time_stamp_u_t; - -/* ==================================================================== */ -/* Register "SH_LB_HW_TIME_STAMP" */ -/* LB hardware error time stamp */ -/* ==================================================================== */ - -typedef union sh_lb_hw_time_stamp_u { - mmr_t sh_lb_hw_time_stamp_regval; - struct { - mmr_t time : 63; - mmr_t valid : 1; - } sh_lb_hw_time_stamp_s; -} sh_lb_hw_time_stamp_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_COR_TIME_STAMP" */ -/* MD correctable error time stamp */ -/* ==================================================================== */ - -typedef union sh_md_cor_time_stamp_u { - mmr_t sh_md_cor_time_stamp_regval; - struct { - mmr_t time : 63; - mmr_t valid : 1; - } sh_md_cor_time_stamp_s; -} sh_md_cor_time_stamp_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_HW_TIME_STAMP" */ -/* MD hardware error time stamp */ -/* ==================================================================== */ - -typedef union sh_md_hw_time_stamp_u { - mmr_t sh_md_hw_time_stamp_regval; - struct { - mmr_t time : 63; - mmr_t valid : 1; - } sh_md_hw_time_stamp_s; -} sh_md_hw_time_stamp_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_UNCOR_TIME_STAMP" */ -/* MD uncorrectable error time stamp */ -/* ==================================================================== */ - -typedef union sh_md_uncor_time_stamp_u { - mmr_t sh_md_uncor_time_stamp_regval; - struct { - mmr_t time : 63; - mmr_t valid : 1; - } sh_md_uncor_time_stamp_s; -} sh_md_uncor_time_stamp_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_COR_TIME_STAMP" */ -/* PI correctable error time stamp */ -/* ==================================================================== */ - -typedef union sh_pi_cor_time_stamp_u { - mmr_t sh_pi_cor_time_stamp_regval; - struct { - mmr_t time : 63; - mmr_t valid : 1; - } sh_pi_cor_time_stamp_s; -} sh_pi_cor_time_stamp_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_HW_TIME_STAMP" */ -/* PI hardware error time stamp */ -/* ==================================================================== */ - -typedef union sh_pi_hw_time_stamp_u { - mmr_t sh_pi_hw_time_stamp_regval; - struct { - mmr_t time : 63; - mmr_t valid : 1; - } sh_pi_hw_time_stamp_s; -} sh_pi_hw_time_stamp_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_UNCOR_TIME_STAMP" */ -/* PI uncorrectable error time stamp */ -/* ==================================================================== */ - -typedef union sh_pi_uncor_time_stamp_u { - mmr_t sh_pi_uncor_time_stamp_regval; - struct { - mmr_t time : 63; - mmr_t valid : 1; - } sh_pi_uncor_time_stamp_s; -} sh_pi_uncor_time_stamp_u_t; - -/* ==================================================================== */ -/* Register "SH_PROC0_ADV_TIME_STAMP" */ -/* Proc 0 advisory time stamp */ -/* ==================================================================== */ - -typedef union sh_proc0_adv_time_stamp_u { - mmr_t sh_proc0_adv_time_stamp_regval; - struct { - mmr_t time : 63; - mmr_t valid : 1; - } sh_proc0_adv_time_stamp_s; -} sh_proc0_adv_time_stamp_u_t; - -/* ==================================================================== */ -/* Register "SH_PROC0_ERR_TIME_STAMP" */ -/* Proc 0 error time stamp */ -/* ==================================================================== */ - -typedef union sh_proc0_err_time_stamp_u { - mmr_t sh_proc0_err_time_stamp_regval; - struct { - mmr_t time : 63; - mmr_t valid : 1; - } sh_proc0_err_time_stamp_s; -} sh_proc0_err_time_stamp_u_t; - -/* ==================================================================== */ -/* Register "SH_PROC1_ADV_TIME_STAMP" */ -/* Proc 1 advisory time stamp */ -/* ==================================================================== */ - -typedef union sh_proc1_adv_time_stamp_u { - mmr_t sh_proc1_adv_time_stamp_regval; - struct { - mmr_t time : 63; - mmr_t valid : 1; - } sh_proc1_adv_time_stamp_s; -} sh_proc1_adv_time_stamp_u_t; - -/* ==================================================================== */ -/* Register "SH_PROC1_ERR_TIME_STAMP" */ -/* Proc 1 error time stamp */ -/* ==================================================================== */ - -typedef union sh_proc1_err_time_stamp_u { - mmr_t sh_proc1_err_time_stamp_regval; - struct { - mmr_t time : 63; - mmr_t valid : 1; - } sh_proc1_err_time_stamp_s; -} sh_proc1_err_time_stamp_u_t; - -/* ==================================================================== */ -/* Register "SH_PROC2_ADV_TIME_STAMP" */ -/* Proc 2 advisory time stamp */ -/* ==================================================================== */ - -typedef union sh_proc2_adv_time_stamp_u { - mmr_t sh_proc2_adv_time_stamp_regval; - struct { - mmr_t time : 63; - mmr_t valid : 1; - } sh_proc2_adv_time_stamp_s; -} sh_proc2_adv_time_stamp_u_t; - -/* ==================================================================== */ -/* Register "SH_PROC2_ERR_TIME_STAMP" */ -/* Proc 2 error time stamp */ -/* ==================================================================== */ - -typedef union sh_proc2_err_time_stamp_u { - mmr_t sh_proc2_err_time_stamp_regval; - struct { - mmr_t time : 63; - mmr_t valid : 1; - } sh_proc2_err_time_stamp_s; -} sh_proc2_err_time_stamp_u_t; - -/* ==================================================================== */ -/* Register "SH_PROC3_ADV_TIME_STAMP" */ -/* Proc 3 advisory time stamp */ -/* ==================================================================== */ - -typedef union sh_proc3_adv_time_stamp_u { - mmr_t sh_proc3_adv_time_stamp_regval; - struct { - mmr_t time : 63; - mmr_t valid : 1; - } sh_proc3_adv_time_stamp_s; -} sh_proc3_adv_time_stamp_u_t; - -/* ==================================================================== */ -/* Register "SH_PROC3_ERR_TIME_STAMP" */ -/* Proc 3 error time stamp */ -/* ==================================================================== */ - -typedef union sh_proc3_err_time_stamp_u { - mmr_t sh_proc3_err_time_stamp_regval; - struct { - mmr_t time : 63; - mmr_t valid : 1; - } sh_proc3_err_time_stamp_s; -} sh_proc3_err_time_stamp_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_COR_TIME_STAMP" */ -/* XN correctable error time stamp */ -/* ==================================================================== */ - -typedef union sh_xn_cor_time_stamp_u { - mmr_t sh_xn_cor_time_stamp_regval; - struct { - mmr_t time : 63; - mmr_t valid : 1; - } sh_xn_cor_time_stamp_s; -} sh_xn_cor_time_stamp_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_HW_TIME_STAMP" */ -/* XN hardware error time stamp */ -/* ==================================================================== */ - -typedef union sh_xn_hw_time_stamp_u { - mmr_t sh_xn_hw_time_stamp_regval; - struct { - mmr_t time : 63; - mmr_t valid : 1; - } sh_xn_hw_time_stamp_s; -} sh_xn_hw_time_stamp_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_UNCOR_TIME_STAMP" */ -/* XN uncorrectable error time stamp */ -/* ==================================================================== */ - -typedef union sh_xn_uncor_time_stamp_u { - mmr_t sh_xn_uncor_time_stamp_regval; - struct { - mmr_t time : 63; - mmr_t valid : 1; - } sh_xn_uncor_time_stamp_s; -} sh_xn_uncor_time_stamp_u_t; - -/* ==================================================================== */ -/* Register "SH_DEBUG_PORT" */ -/* SHub Debug Port */ -/* ==================================================================== */ - -typedef union sh_debug_port_u { - mmr_t sh_debug_port_regval; - struct { - mmr_t debug_nibble0 : 4; - mmr_t debug_nibble1 : 4; - mmr_t debug_nibble2 : 4; - mmr_t debug_nibble3 : 4; - mmr_t debug_nibble4 : 4; - mmr_t debug_nibble5 : 4; - mmr_t debug_nibble6 : 4; - mmr_t debug_nibble7 : 4; - mmr_t reserved_0 : 32; - } sh_debug_port_s; -} sh_debug_port_u_t; - -/* ==================================================================== */ -/* Register "SH_II_DEBUG_DATA" */ -/* II Debug Data */ -/* ==================================================================== */ - -typedef union sh_ii_debug_data_u { - mmr_t sh_ii_debug_data_regval; - struct { - mmr_t ii_data : 32; - mmr_t reserved_0 : 32; - } sh_ii_debug_data_s; -} sh_ii_debug_data_u_t; - -/* ==================================================================== */ -/* Register "SH_II_WRAP_DEBUG_DATA" */ -/* SHub II Wrapper Debug Data */ -/* ==================================================================== */ - -typedef union sh_ii_wrap_debug_data_u { - mmr_t sh_ii_wrap_debug_data_regval; - struct { - mmr_t ii_wrap_data : 32; - mmr_t reserved_0 : 32; - } sh_ii_wrap_debug_data_s; -} sh_ii_wrap_debug_data_u_t; - -/* ==================================================================== */ -/* Register "SH_LB_DEBUG_DATA" */ -/* SHub LB Debug Data */ -/* ==================================================================== */ - -typedef union sh_lb_debug_data_u { - mmr_t sh_lb_debug_data_regval; - struct { - mmr_t lb_data : 32; - mmr_t reserved_0 : 32; - } sh_lb_debug_data_s; -} sh_lb_debug_data_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DEBUG_DATA" */ -/* SHub MD Debug Data */ -/* ==================================================================== */ - -typedef union sh_md_debug_data_u { - mmr_t sh_md_debug_data_regval; - struct { - mmr_t md_data : 32; - mmr_t reserved_0 : 32; - } sh_md_debug_data_s; -} sh_md_debug_data_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_DEBUG_DATA" */ -/* SHub PI Debug Data */ -/* ==================================================================== */ - -typedef union sh_pi_debug_data_u { - mmr_t sh_pi_debug_data_regval; - struct { - mmr_t pi_data : 32; - mmr_t reserved_0 : 32; - } sh_pi_debug_data_s; -} sh_pi_debug_data_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_DEBUG_DATA" */ -/* SHub XN Debug Data */ -/* ==================================================================== */ - -typedef union sh_xn_debug_data_u { - mmr_t sh_xn_debug_data_regval; - struct { - mmr_t xn_data : 32; - mmr_t reserved_0 : 32; - } sh_xn_debug_data_s; -} sh_xn_debug_data_u_t; - -/* ==================================================================== */ -/* Register "SH_TSF_ARMED_STATE" */ -/* Trigger sequencing facility arm state */ -/* ==================================================================== */ - -typedef union sh_tsf_armed_state_u { - mmr_t sh_tsf_armed_state_regval; - struct { - mmr_t state : 8; - mmr_t reserved_0 : 56; - } sh_tsf_armed_state_s; -} sh_tsf_armed_state_u_t; - -/* ==================================================================== */ -/* Register "SH_TSF_COUNTER_VALUE" */ -/* Trigger sequencing facility counter value */ -/* ==================================================================== */ - -typedef union sh_tsf_counter_value_u { - mmr_t sh_tsf_counter_value_regval; - struct { - mmr_t count_32 : 32; - mmr_t count_16 : 16; - mmr_t count_8b : 8; - mmr_t count_8a : 8; - } sh_tsf_counter_value_s; -} sh_tsf_counter_value_u_t; - -/* ==================================================================== */ -/* Register "SH_TSF_TRIGGERED_STATE" */ -/* Trigger sequencing facility triggered state */ -/* ==================================================================== */ - -typedef union sh_tsf_triggered_state_u { - mmr_t sh_tsf_triggered_state_regval; - struct { - mmr_t state : 8; - mmr_t reserved_0 : 56; - } sh_tsf_triggered_state_s; -} sh_tsf_triggered_state_u_t; - -/* ==================================================================== */ -/* Register "SH_VEC_RDDATA" */ -/* Vector Reply Message Data */ -/* ==================================================================== */ - -typedef union sh_vec_rddata_u { - mmr_t sh_vec_rddata_regval; - struct { - mmr_t data : 64; - } sh_vec_rddata_s; -} sh_vec_rddata_u_t; - -/* ==================================================================== */ -/* Register "SH_VEC_RETURN" */ -/* Vector Reply Message Return Route */ -/* ==================================================================== */ - -typedef union sh_vec_return_u { - mmr_t sh_vec_return_regval; - struct { - mmr_t route : 64; - } sh_vec_return_s; -} sh_vec_return_u_t; - -/* ==================================================================== */ -/* Register "SH_VEC_STATUS" */ -/* Vector Reply Message Status */ -/* ==================================================================== */ - -typedef union sh_vec_status_u { - mmr_t sh_vec_status_regval; - struct { - mmr_t type : 3; - mmr_t address : 32; - mmr_t pio_id : 11; - mmr_t source : 14; - mmr_t reserved_0 : 2; - mmr_t overrun : 1; - mmr_t status_valid : 1; - } sh_vec_status_s; -} sh_vec_status_u_t; - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNT0_CONTROL" */ -/* Performance Counter 0 Control */ -/* ==================================================================== */ - -typedef union sh_performance_count0_control_u { - mmr_t sh_performance_count0_control_regval; - struct { - mmr_t up_stimulus : 5; - mmr_t up_event : 1; - mmr_t up_polarity : 1; - mmr_t up_mode : 1; - mmr_t dn_stimulus : 5; - mmr_t dn_event : 1; - mmr_t dn_polarity : 1; - mmr_t dn_mode : 1; - mmr_t inc_enable : 1; - mmr_t dec_enable : 1; - mmr_t peak_det_enable : 1; - mmr_t reserved_0 : 45; - } sh_performance_count0_control_s; -} sh_performance_count0_control_u_t; - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNT1_CONTROL" */ -/* Performance Counter 1 Control */ -/* ==================================================================== */ - -typedef union sh_performance_count1_control_u { - mmr_t sh_performance_count1_control_regval; - struct { - mmr_t up_stimulus : 5; - mmr_t up_event : 1; - mmr_t up_polarity : 1; - mmr_t up_mode : 1; - mmr_t dn_stimulus : 5; - mmr_t dn_event : 1; - mmr_t dn_polarity : 1; - mmr_t dn_mode : 1; - mmr_t inc_enable : 1; - mmr_t dec_enable : 1; - mmr_t peak_det_enable : 1; - mmr_t reserved_0 : 45; - } sh_performance_count1_control_s; -} sh_performance_count1_control_u_t; - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNT2_CONTROL" */ -/* Performance Counter 2 Control */ -/* ==================================================================== */ - -typedef union sh_performance_count2_control_u { - mmr_t sh_performance_count2_control_regval; - struct { - mmr_t up_stimulus : 5; - mmr_t up_event : 1; - mmr_t up_polarity : 1; - mmr_t up_mode : 1; - mmr_t dn_stimulus : 5; - mmr_t dn_event : 1; - mmr_t dn_polarity : 1; - mmr_t dn_mode : 1; - mmr_t inc_enable : 1; - mmr_t dec_enable : 1; - mmr_t peak_det_enable : 1; - mmr_t reserved_0 : 45; - } sh_performance_count2_control_s; -} sh_performance_count2_control_u_t; - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNT3_CONTROL" */ -/* Performance Counter 3 Control */ -/* ==================================================================== */ - -typedef union sh_performance_count3_control_u { - mmr_t sh_performance_count3_control_regval; - struct { - mmr_t up_stimulus : 5; - mmr_t up_event : 1; - mmr_t up_polarity : 1; - mmr_t up_mode : 1; - mmr_t dn_stimulus : 5; - mmr_t dn_event : 1; - mmr_t dn_polarity : 1; - mmr_t dn_mode : 1; - mmr_t inc_enable : 1; - mmr_t dec_enable : 1; - mmr_t peak_det_enable : 1; - mmr_t reserved_0 : 45; - } sh_performance_count3_control_s; -} sh_performance_count3_control_u_t; - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNT4_CONTROL" */ -/* Performance Counter 4 Control */ -/* ==================================================================== */ - -typedef union sh_performance_count4_control_u { - mmr_t sh_performance_count4_control_regval; - struct { - mmr_t up_stimulus : 5; - mmr_t up_event : 1; - mmr_t up_polarity : 1; - mmr_t up_mode : 1; - mmr_t dn_stimulus : 5; - mmr_t dn_event : 1; - mmr_t dn_polarity : 1; - mmr_t dn_mode : 1; - mmr_t inc_enable : 1; - mmr_t dec_enable : 1; - mmr_t peak_det_enable : 1; - mmr_t reserved_0 : 45; - } sh_performance_count4_control_s; -} sh_performance_count4_control_u_t; - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNT5_CONTROL" */ -/* Performance Counter 5 Control */ -/* ==================================================================== */ - -typedef union sh_performance_count5_control_u { - mmr_t sh_performance_count5_control_regval; - struct { - mmr_t up_stimulus : 5; - mmr_t up_event : 1; - mmr_t up_polarity : 1; - mmr_t up_mode : 1; - mmr_t dn_stimulus : 5; - mmr_t dn_event : 1; - mmr_t dn_polarity : 1; - mmr_t dn_mode : 1; - mmr_t inc_enable : 1; - mmr_t dec_enable : 1; - mmr_t peak_det_enable : 1; - mmr_t reserved_0 : 45; - } sh_performance_count5_control_s; -} sh_performance_count5_control_u_t; - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNT6_CONTROL" */ -/* Performance Counter 6 Control */ -/* ==================================================================== */ - -typedef union sh_performance_count6_control_u { - mmr_t sh_performance_count6_control_regval; - struct { - mmr_t up_stimulus : 5; - mmr_t up_event : 1; - mmr_t up_polarity : 1; - mmr_t up_mode : 1; - mmr_t dn_stimulus : 5; - mmr_t dn_event : 1; - mmr_t dn_polarity : 1; - mmr_t dn_mode : 1; - mmr_t inc_enable : 1; - mmr_t dec_enable : 1; - mmr_t peak_det_enable : 1; - mmr_t reserved_0 : 45; - } sh_performance_count6_control_s; -} sh_performance_count6_control_u_t; - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNT7_CONTROL" */ -/* Performance Counter 7 Control */ -/* ==================================================================== */ - -typedef union sh_performance_count7_control_u { - mmr_t sh_performance_count7_control_regval; - struct { - mmr_t up_stimulus : 5; - mmr_t up_event : 1; - mmr_t up_polarity : 1; - mmr_t up_mode : 1; - mmr_t dn_stimulus : 5; - mmr_t dn_event : 1; - mmr_t dn_polarity : 1; - mmr_t dn_mode : 1; - mmr_t inc_enable : 1; - mmr_t dec_enable : 1; - mmr_t peak_det_enable : 1; - mmr_t reserved_0 : 45; - } sh_performance_count7_control_s; -} sh_performance_count7_control_u_t; - -/* ==================================================================== */ -/* Register "SH_PROFILE_DN_CONTROL" */ -/* Profile Counter Down Control */ -/* ==================================================================== */ - -typedef union sh_profile_dn_control_u { - mmr_t sh_profile_dn_control_regval; - struct { - mmr_t stimulus : 5; - mmr_t event : 1; - mmr_t polarity : 1; - mmr_t mode : 1; - mmr_t reserved_0 : 56; - } sh_profile_dn_control_s; -} sh_profile_dn_control_u_t; - -/* ==================================================================== */ -/* Register "SH_PROFILE_PEAK_CONTROL" */ -/* Profile Counter Peak Control */ -/* ==================================================================== */ - -typedef union sh_profile_peak_control_u { - mmr_t sh_profile_peak_control_regval; - struct { - mmr_t reserved_0 : 3; - mmr_t stimulus : 1; - mmr_t reserved_1 : 1; - mmr_t event : 1; - mmr_t polarity : 1; - mmr_t reserved_2 : 57; - } sh_profile_peak_control_s; -} sh_profile_peak_control_u_t; - -/* ==================================================================== */ -/* Register "SH_PROFILE_RANGE" */ -/* Profile Counter Range */ -/* ==================================================================== */ - -typedef union sh_profile_range_u { - mmr_t sh_profile_range_regval; - struct { - mmr_t range0 : 8; - mmr_t range1 : 8; - mmr_t range2 : 8; - mmr_t range3 : 8; - mmr_t range4 : 8; - mmr_t range5 : 8; - mmr_t range6 : 8; - mmr_t range7 : 8; - } sh_profile_range_s; -} sh_profile_range_u_t; - -/* ==================================================================== */ -/* Register "SH_PROFILE_UP_CONTROL" */ -/* Profile Counter Up Control */ -/* ==================================================================== */ - -typedef union sh_profile_up_control_u { - mmr_t sh_profile_up_control_regval; - struct { - mmr_t stimulus : 5; - mmr_t event : 1; - mmr_t polarity : 1; - mmr_t mode : 1; - mmr_t reserved_0 : 56; - } sh_profile_up_control_s; -} sh_profile_up_control_u_t; - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNTER0" */ -/* Performance Counter 0 */ -/* ==================================================================== */ - -typedef union sh_performance_counter0_u { - mmr_t sh_performance_counter0_regval; - struct { - mmr_t count : 32; - mmr_t reserved_0 : 32; - } sh_performance_counter0_s; -} sh_performance_counter0_u_t; - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNTER1" */ -/* Performance Counter 1 */ -/* ==================================================================== */ - -typedef union sh_performance_counter1_u { - mmr_t sh_performance_counter1_regval; - struct { - mmr_t count : 32; - mmr_t reserved_0 : 32; - } sh_performance_counter1_s; -} sh_performance_counter1_u_t; - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNTER2" */ -/* Performance Counter 2 */ -/* ==================================================================== */ - -typedef union sh_performance_counter2_u { - mmr_t sh_performance_counter2_regval; - struct { - mmr_t count : 32; - mmr_t reserved_0 : 32; - } sh_performance_counter2_s; -} sh_performance_counter2_u_t; - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNTER3" */ -/* Performance Counter 3 */ -/* ==================================================================== */ - -typedef union sh_performance_counter3_u { - mmr_t sh_performance_counter3_regval; - struct { - mmr_t count : 32; - mmr_t reserved_0 : 32; - } sh_performance_counter3_s; -} sh_performance_counter3_u_t; - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNTER4" */ -/* Performance Counter 4 */ -/* ==================================================================== */ - -typedef union sh_performance_counter4_u { - mmr_t sh_performance_counter4_regval; - struct { - mmr_t count : 32; - mmr_t reserved_0 : 32; - } sh_performance_counter4_s; -} sh_performance_counter4_u_t; - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNTER5" */ -/* Performance Counter 5 */ -/* ==================================================================== */ - -typedef union sh_performance_counter5_u { - mmr_t sh_performance_counter5_regval; - struct { - mmr_t count : 32; - mmr_t reserved_0 : 32; - } sh_performance_counter5_s; -} sh_performance_counter5_u_t; - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNTER6" */ -/* Performance Counter 6 */ -/* ==================================================================== */ - -typedef union sh_performance_counter6_u { - mmr_t sh_performance_counter6_regval; - struct { - mmr_t count : 32; - mmr_t reserved_0 : 32; - } sh_performance_counter6_s; -} sh_performance_counter6_u_t; - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNTER7" */ -/* Performance Counter 7 */ -/* ==================================================================== */ - -typedef union sh_performance_counter7_u { - mmr_t sh_performance_counter7_regval; - struct { - mmr_t count : 32; - mmr_t reserved_0 : 32; - } sh_performance_counter7_s; -} sh_performance_counter7_u_t; - -/* ==================================================================== */ -/* Register "SH_PROFILE_COUNTER" */ -/* Profile Counter */ -/* ==================================================================== */ - -typedef union sh_profile_counter_u { - mmr_t sh_profile_counter_regval; - struct { - mmr_t counter : 8; - mmr_t reserved_0 : 56; - } sh_profile_counter_s; -} sh_profile_counter_u_t; - -/* ==================================================================== */ -/* Register "SH_PROFILE_PEAK" */ -/* Profile Peak Counter */ -/* ==================================================================== */ - -typedef union sh_profile_peak_u { - mmr_t sh_profile_peak_regval; - struct { - mmr_t counter : 8; - mmr_t reserved_0 : 56; - } sh_profile_peak_s; -} sh_profile_peak_u_t; - -/* ==================================================================== */ -/* Register "SH_PTC_0" */ -/* Puge Translation Cache Message Configuration Information */ -/* ==================================================================== */ - -typedef union sh_ptc_0_u { - mmr_t sh_ptc_0_regval; - struct { - mmr_t a : 1; - mmr_t reserved_0 : 1; - mmr_t ps : 6; - mmr_t rid : 24; - mmr_t reserved_1 : 31; - mmr_t start : 1; - } sh_ptc_0_s; -} sh_ptc_0_u_t; - -/* ==================================================================== */ -/* Register "SH_PTC_1" */ -/* Puge Translation Cache Message Configuration Information */ -/* ==================================================================== */ - -typedef union sh_ptc_1_u { - mmr_t sh_ptc_1_regval; - struct { - mmr_t reserved_0 : 12; - mmr_t vpn : 49; - mmr_t reserved_1 : 2; - mmr_t start : 1; - } sh_ptc_1_s; -} sh_ptc_1_u_t; - -/* ==================================================================== */ -/* Register "SH_PTC_PARMS" */ -/* PTC Time-out parmaeters */ -/* ==================================================================== */ - -typedef union sh_ptc_parms_u { - mmr_t sh_ptc_parms_regval; - struct { - mmr_t ptc_to_wrap : 24; - mmr_t ptc_to_val : 12; - mmr_t reserved_0 : 28; - } sh_ptc_parms_s; -} sh_ptc_parms_u_t; - -/* ==================================================================== */ -/* Register "SH_INT_CMPA" */ -/* RTC Compare Value for Processor A */ -/* ==================================================================== */ - -typedef union sh_int_cmpa_u { - mmr_t sh_int_cmpa_regval; - struct { - mmr_t real_time_cmpa : 55; - mmr_t reserved_0 : 9; - } sh_int_cmpa_s; -} sh_int_cmpa_u_t; - -/* ==================================================================== */ -/* Register "SH_INT_CMPB" */ -/* RTC Compare Value for Processor B */ -/* ==================================================================== */ - -typedef union sh_int_cmpb_u { - mmr_t sh_int_cmpb_regval; - struct { - mmr_t real_time_cmpb : 55; - mmr_t reserved_0 : 9; - } sh_int_cmpb_s; -} sh_int_cmpb_u_t; - -/* ==================================================================== */ -/* Register "SH_INT_CMPC" */ -/* RTC Compare Value for Processor C */ -/* ==================================================================== */ - -typedef union sh_int_cmpc_u { - mmr_t sh_int_cmpc_regval; - struct { - mmr_t real_time_cmpc : 55; - mmr_t reserved_0 : 9; - } sh_int_cmpc_s; -} sh_int_cmpc_u_t; - -/* ==================================================================== */ -/* Register "SH_INT_CMPD" */ -/* RTC Compare Value for Processor D */ -/* ==================================================================== */ - -typedef union sh_int_cmpd_u { - mmr_t sh_int_cmpd_regval; - struct { - mmr_t real_time_cmpd : 55; - mmr_t reserved_0 : 9; - } sh_int_cmpd_s; -} sh_int_cmpd_u_t; - -/* ==================================================================== */ -/* Register "SH_INT_PROF" */ -/* Profile Compare Registers */ -/* ==================================================================== */ - -typedef union sh_int_prof_u { - mmr_t sh_int_prof_regval; - struct { - mmr_t profile_compare : 32; - mmr_t reserved_0 : 32; - } sh_int_prof_s; -} sh_int_prof_u_t; - -/* ==================================================================== */ -/* Register "SH_RTC" */ -/* Real-time Clock */ -/* ==================================================================== */ - -typedef union sh_rtc_u { - mmr_t sh_rtc_regval; - struct { - mmr_t real_time_clock : 55; - mmr_t reserved_0 : 9; - } sh_rtc_s; -} sh_rtc_u_t; - -/* ==================================================================== */ -/* Register "SH_SCRATCH0" */ -/* Scratch Register 0 */ -/* ==================================================================== */ - -typedef union sh_scratch0_u { - mmr_t sh_scratch0_regval; - struct { - mmr_t scratch0 : 64; - } sh_scratch0_s; -} sh_scratch0_u_t; - -/* ==================================================================== */ -/* Register "SH_SCRATCH1" */ -/* Scratch Register 1 */ -/* ==================================================================== */ - -typedef union sh_scratch1_u { - mmr_t sh_scratch1_regval; - struct { - mmr_t scratch1 : 64; - } sh_scratch1_s; -} sh_scratch1_u_t; - -/* ==================================================================== */ -/* Register "SH_SCRATCH2" */ -/* Scratch Register 2 */ -/* ==================================================================== */ - -typedef union sh_scratch2_u { - mmr_t sh_scratch2_regval; - struct { - mmr_t scratch2 : 64; - } sh_scratch2_s; -} sh_scratch2_u_t; - -/* ==================================================================== */ -/* Register "SH_SCRATCH3" */ -/* Scratch Register 3 */ -/* ==================================================================== */ - -typedef union sh_scratch3_u { - mmr_t sh_scratch3_regval; - struct { - mmr_t scratch3 : 1; - mmr_t reserved_0 : 63; - } sh_scratch3_s; -} sh_scratch3_u_t; - -/* ==================================================================== */ -/* Register "SH_SCRATCH4" */ -/* Scratch Register 4 */ -/* ==================================================================== */ - -typedef union sh_scratch4_u { - mmr_t sh_scratch4_regval; - struct { - mmr_t scratch4 : 1; - mmr_t reserved_0 : 63; - } sh_scratch4_s; -} sh_scratch4_u_t; - -/* ==================================================================== */ -/* Register "SH_CRB_MESSAGE_CONTROL" */ -/* Coherent Request Buffer Message Control */ -/* ==================================================================== */ - -typedef union sh_crb_message_control_u { - mmr_t sh_crb_message_control_regval; - struct { - mmr_t system_coherence_enable : 1; - mmr_t local_speculative_message_enable : 1; - mmr_t remote_speculative_message_enable : 1; - mmr_t message_color : 1; - mmr_t message_color_enable : 1; - mmr_t rrb_attribute_mismatch_fsb_enable : 1; - mmr_t wrb_attribute_mismatch_fsb_enable : 1; - mmr_t irb_attribute_mismatch_fsb_enable : 1; - mmr_t rrb_attribute_mismatch_xb_enable : 1; - mmr_t wrb_attribute_mismatch_xb_enable : 1; - mmr_t suppress_bogus_writes : 1; - mmr_t enable_ivack_consolidation : 1; - mmr_t reserved_0 : 20; - mmr_t ivack_stall_count : 16; - mmr_t ivack_throttle_control : 16; - } sh_crb_message_control_s; -} sh_crb_message_control_u_t; - -/* ==================================================================== */ -/* Register "SH_CRB_NACK_LIMIT" */ -/* CRB Nack Limit */ -/* ==================================================================== */ - -typedef union sh_crb_nack_limit_u { - mmr_t sh_crb_nack_limit_regval; - struct { - mmr_t limit : 12; - mmr_t pri_freq : 4; - mmr_t reserved_0 : 47; - mmr_t enable : 1; - } sh_crb_nack_limit_s; -} sh_crb_nack_limit_u_t; - -/* ==================================================================== */ -/* Register "SH_CRB_TIMEOUT_PRESCALE" */ -/* Coherent Request Buffer Timeout Prescale */ -/* ==================================================================== */ - -typedef union sh_crb_timeout_prescale_u { - mmr_t sh_crb_timeout_prescale_regval; - struct { - mmr_t scaling_factor : 32; - mmr_t reserved_0 : 32; - } sh_crb_timeout_prescale_s; -} sh_crb_timeout_prescale_u_t; - -/* ==================================================================== */ -/* Register "SH_CRB_TIMEOUT_SKID" */ -/* Coherent Request Buffer Timeout Skid Limit */ -/* ==================================================================== */ - -typedef union sh_crb_timeout_skid_u { - mmr_t sh_crb_timeout_skid_regval; - struct { - mmr_t skid : 6; - mmr_t reserved_0 : 57; - mmr_t reset_skid_count : 1; - } sh_crb_timeout_skid_s; -} sh_crb_timeout_skid_u_t; - -/* ==================================================================== */ -/* Register "SH_MEMORY_WRITE_STATUS_0" */ -/* Memory Write Status for CPU 0 */ -/* ==================================================================== */ - -typedef union sh_memory_write_status_0_u { - mmr_t sh_memory_write_status_0_regval; - struct { - mmr_t pending_write_count : 6; - mmr_t reserved_0 : 58; - } sh_memory_write_status_0_s; -} sh_memory_write_status_0_u_t; - -/* ==================================================================== */ -/* Register "SH_MEMORY_WRITE_STATUS_1" */ -/* Memory Write Status for CPU 1 */ -/* ==================================================================== */ - -typedef union sh_memory_write_status_1_u { - mmr_t sh_memory_write_status_1_regval; - struct { - mmr_t pending_write_count : 6; - mmr_t reserved_0 : 58; - } sh_memory_write_status_1_s; -} sh_memory_write_status_1_u_t; - -/* ==================================================================== */ -/* Register "SH_PIO_WRITE_STATUS_0" */ -/* PIO Write Status for CPU 0 */ -/* ==================================================================== */ - -typedef union sh_pio_write_status_0_u { - mmr_t sh_pio_write_status_0_regval; - struct { - mmr_t multi_write_error : 1; - mmr_t write_deadlock : 1; - mmr_t write_error : 1; - mmr_t write_error_address : 47; - mmr_t reserved_0 : 6; - mmr_t pending_write_count : 6; - mmr_t reserved_1 : 1; - mmr_t writes_ok : 1; - } sh_pio_write_status_0_s; -} sh_pio_write_status_0_u_t; - -/* ==================================================================== */ -/* Register "SH_PIO_WRITE_STATUS_1" */ -/* PIO Write Status for CPU 1 */ -/* ==================================================================== */ - -typedef union sh_pio_write_status_1_u { - mmr_t sh_pio_write_status_1_regval; - struct { - mmr_t multi_write_error : 1; - mmr_t write_deadlock : 1; - mmr_t write_error : 1; - mmr_t write_error_address : 47; - mmr_t reserved_0 : 6; - mmr_t pending_write_count : 6; - mmr_t reserved_1 : 1; - mmr_t writes_ok : 1; - } sh_pio_write_status_1_s; -} sh_pio_write_status_1_u_t; - -/* ==================================================================== */ -/* Register "SH_MEMORY_WRITE_STATUS_NON_USER_0" */ -/* Memory Write Status for CPU 0. OS access only */ -/* ==================================================================== */ - -typedef union sh_memory_write_status_non_user_0_u { - mmr_t sh_memory_write_status_non_user_0_regval; - struct { - mmr_t pending_write_count : 6; - mmr_t reserved_0 : 57; - mmr_t clear : 1; - } sh_memory_write_status_non_user_0_s; -} sh_memory_write_status_non_user_0_u_t; - -/* ==================================================================== */ -/* Register "SH_MEMORY_WRITE_STATUS_NON_USER_1" */ -/* Memory Write Status for CPU 1. OS access only */ -/* ==================================================================== */ - -typedef union sh_memory_write_status_non_user_1_u { - mmr_t sh_memory_write_status_non_user_1_regval; - struct { - mmr_t pending_write_count : 6; - mmr_t reserved_0 : 57; - mmr_t clear : 1; - } sh_memory_write_status_non_user_1_s; -} sh_memory_write_status_non_user_1_u_t; - -/* ==================================================================== */ -/* Register "SH_MMRBIST_ERR" */ -/* Error capture for bist read errors */ -/* ==================================================================== */ - -typedef union sh_mmrbist_err_u { - mmr_t sh_mmrbist_err_regval; - struct { - mmr_t addr : 33; - mmr_t reserved_0 : 3; - mmr_t detected : 1; - mmr_t multiple_detected : 1; - mmr_t cancelled : 1; - mmr_t reserved_1 : 25; - } sh_mmrbist_err_s; -} sh_mmrbist_err_u_t; - -/* ==================================================================== */ -/* Register "SH_MISC_ERR_HDR_LOWER" */ -/* Header capture register */ -/* ==================================================================== */ - -typedef union sh_misc_err_hdr_lower_u { - mmr_t sh_misc_err_hdr_lower_regval; - struct { - mmr_t reserved_0 : 3; - mmr_t addr : 33; - mmr_t cmd : 8; - mmr_t src : 14; - mmr_t reserved_1 : 2; - mmr_t write : 1; - mmr_t reserved_2 : 2; - mmr_t valid : 1; - } sh_misc_err_hdr_lower_s; -} sh_misc_err_hdr_lower_u_t; - -/* ==================================================================== */ -/* Register "SH_MISC_ERR_HDR_UPPER" */ -/* Error header capture packet and protocol errors */ -/* ==================================================================== */ - -typedef union sh_misc_err_hdr_upper_u { - mmr_t sh_misc_err_hdr_upper_regval; - struct { - mmr_t dir_protocol : 1; - mmr_t illegal_cmd : 1; - mmr_t nonexist_addr : 1; - mmr_t rmw_uc : 1; - mmr_t rmw_cor : 1; - mmr_t dir_acc : 1; - mmr_t pi_pkt_size : 1; - mmr_t xn_pkt_size : 1; - mmr_t reserved_0 : 12; - mmr_t echo : 9; - mmr_t reserved_1 : 35; - } sh_misc_err_hdr_upper_s; -} sh_misc_err_hdr_upper_u_t; - -/* ==================================================================== */ -/* Register "SH_DIR_UC_ERR_HDR_LOWER" */ -/* Header capture register */ -/* ==================================================================== */ - -typedef union sh_dir_uc_err_hdr_lower_u { - mmr_t sh_dir_uc_err_hdr_lower_regval; - struct { - mmr_t reserved_0 : 3; - mmr_t addr : 33; - mmr_t cmd : 8; - mmr_t src : 14; - mmr_t reserved_1 : 2; - mmr_t write : 1; - mmr_t reserved_2 : 2; - mmr_t valid : 1; - } sh_dir_uc_err_hdr_lower_s; -} sh_dir_uc_err_hdr_lower_u_t; - -/* ==================================================================== */ -/* Register "SH_DIR_UC_ERR_HDR_UPPER" */ -/* Error header capture packet and protocol errors */ -/* ==================================================================== */ - -typedef union sh_dir_uc_err_hdr_upper_u { - mmr_t sh_dir_uc_err_hdr_upper_regval; - struct { - mmr_t reserved_0 : 3; - mmr_t dir_uc : 1; - mmr_t reserved_1 : 16; - mmr_t echo : 9; - mmr_t reserved_2 : 35; - } sh_dir_uc_err_hdr_upper_s; -} sh_dir_uc_err_hdr_upper_u_t; - -/* ==================================================================== */ -/* Register "SH_DIR_COR_ERR_HDR_LOWER" */ -/* Header capture register */ -/* ==================================================================== */ - -typedef union sh_dir_cor_err_hdr_lower_u { - mmr_t sh_dir_cor_err_hdr_lower_regval; - struct { - mmr_t reserved_0 : 3; - mmr_t addr : 33; - mmr_t cmd : 8; - mmr_t src : 14; - mmr_t reserved_1 : 2; - mmr_t write : 1; - mmr_t reserved_2 : 2; - mmr_t valid : 1; - } sh_dir_cor_err_hdr_lower_s; -} sh_dir_cor_err_hdr_lower_u_t; - -/* ==================================================================== */ -/* Register "SH_DIR_COR_ERR_HDR_UPPER" */ -/* Error header capture packet and protocol errors */ -/* ==================================================================== */ - -typedef union sh_dir_cor_err_hdr_upper_u { - mmr_t sh_dir_cor_err_hdr_upper_regval; - struct { - mmr_t reserved_0 : 8; - mmr_t dir_cor : 1; - mmr_t reserved_1 : 11; - mmr_t echo : 9; - mmr_t reserved_2 : 35; - } sh_dir_cor_err_hdr_upper_s; -} sh_dir_cor_err_hdr_upper_u_t; - -/* ==================================================================== */ -/* Register "SH_MEM_ERROR_SUMMARY" */ -/* Memory error flags */ -/* ==================================================================== */ - -typedef union sh_mem_error_summary_u { - mmr_t sh_mem_error_summary_regval; - struct { - mmr_t illegal_cmd : 1; - mmr_t nonexist_addr : 1; - mmr_t dqlp_dir_perr : 1; - mmr_t dqrp_dir_perr : 1; - mmr_t dqlp_dir_uc : 1; - mmr_t dqlp_dir_cor : 1; - mmr_t dqrp_dir_uc : 1; - mmr_t dqrp_dir_cor : 1; - mmr_t acx_int_hw : 1; - mmr_t acy_int_hw : 1; - mmr_t dir_acc : 1; - mmr_t reserved_0 : 1; - mmr_t dqlp_int_uc : 1; - mmr_t dqlp_int_cor : 1; - mmr_t dqlp_int_hw : 1; - mmr_t reserved_1 : 1; - mmr_t dqls_int_uc : 1; - mmr_t dqls_int_cor : 1; - mmr_t dqls_int_hw : 1; - mmr_t reserved_2 : 1; - mmr_t dqrp_int_uc : 1; - mmr_t dqrp_int_cor : 1; - mmr_t dqrp_int_hw : 1; - mmr_t reserved_3 : 1; - mmr_t dqrs_int_uc : 1; - mmr_t dqrs_int_cor : 1; - mmr_t dqrs_int_hw : 1; - mmr_t reserved_4 : 1; - mmr_t pi_reply_overflow : 1; - mmr_t xn_reply_overflow : 1; - mmr_t pi_request_overflow : 1; - mmr_t xn_request_overflow : 1; - mmr_t red_black_err_timeout : 1; - mmr_t pi_pkt_size : 1; - mmr_t xn_pkt_size : 1; - mmr_t reserved_5 : 29; - } sh_mem_error_summary_s; -} sh_mem_error_summary_u_t; - -/* ==================================================================== */ -/* Register "SH_MEM_ERROR_OVERFLOW" */ -/* Memory error flags */ -/* ==================================================================== */ - -typedef union sh_mem_error_overflow_u { - mmr_t sh_mem_error_overflow_regval; - struct { - mmr_t illegal_cmd : 1; - mmr_t nonexist_addr : 1; - mmr_t dqlp_dir_perr : 1; - mmr_t dqrp_dir_perr : 1; - mmr_t dqlp_dir_uc : 1; - mmr_t dqlp_dir_cor : 1; - mmr_t dqrp_dir_uc : 1; - mmr_t dqrp_dir_cor : 1; - mmr_t acx_int_hw : 1; - mmr_t acy_int_hw : 1; - mmr_t dir_acc : 1; - mmr_t reserved_0 : 1; - mmr_t dqlp_int_uc : 1; - mmr_t dqlp_int_cor : 1; - mmr_t dqlp_int_hw : 1; - mmr_t reserved_1 : 1; - mmr_t dqls_int_uc : 1; - mmr_t dqls_int_cor : 1; - mmr_t dqls_int_hw : 1; - mmr_t reserved_2 : 1; - mmr_t dqrp_int_uc : 1; - mmr_t dqrp_int_cor : 1; - mmr_t dqrp_int_hw : 1; - mmr_t reserved_3 : 1; - mmr_t dqrs_int_uc : 1; - mmr_t dqrs_int_cor : 1; - mmr_t dqrs_int_hw : 1; - mmr_t reserved_4 : 1; - mmr_t pi_reply_overflow : 1; - mmr_t xn_reply_overflow : 1; - mmr_t pi_request_overflow : 1; - mmr_t xn_request_overflow : 1; - mmr_t red_black_err_timeout : 1; - mmr_t pi_pkt_size : 1; - mmr_t xn_pkt_size : 1; - mmr_t reserved_5 : 29; - } sh_mem_error_overflow_s; -} sh_mem_error_overflow_u_t; - -/* ==================================================================== */ -/* Register "SH_MEM_ERROR_MASK" */ -/* Memory error flags */ -/* ==================================================================== */ - -typedef union sh_mem_error_mask_u { - mmr_t sh_mem_error_mask_regval; - struct { - mmr_t illegal_cmd : 1; - mmr_t nonexist_addr : 1; - mmr_t dqlp_dir_perr : 1; - mmr_t dqrp_dir_perr : 1; - mmr_t dqlp_dir_uc : 1; - mmr_t dqlp_dir_cor : 1; - mmr_t dqrp_dir_uc : 1; - mmr_t dqrp_dir_cor : 1; - mmr_t acx_int_hw : 1; - mmr_t acy_int_hw : 1; - mmr_t dir_acc : 1; - mmr_t reserved_0 : 1; - mmr_t dqlp_int_uc : 1; - mmr_t dqlp_int_cor : 1; - mmr_t dqlp_int_hw : 1; - mmr_t reserved_1 : 1; - mmr_t dqls_int_uc : 1; - mmr_t dqls_int_cor : 1; - mmr_t dqls_int_hw : 1; - mmr_t reserved_2 : 1; - mmr_t dqrp_int_uc : 1; - mmr_t dqrp_int_cor : 1; - mmr_t dqrp_int_hw : 1; - mmr_t reserved_3 : 1; - mmr_t dqrs_int_uc : 1; - mmr_t dqrs_int_cor : 1; - mmr_t dqrs_int_hw : 1; - mmr_t reserved_4 : 1; - mmr_t pi_reply_overflow : 1; - mmr_t xn_reply_overflow : 1; - mmr_t pi_request_overflow : 1; - mmr_t xn_request_overflow : 1; - mmr_t red_black_err_timeout : 1; - mmr_t pi_pkt_size : 1; - mmr_t xn_pkt_size : 1; - mmr_t reserved_5 : 29; - } sh_mem_error_mask_s; -} sh_mem_error_mask_u_t; - -/* ==================================================================== */ -/* Register "SH_X_DIMM_CFG" */ -/* AC Mem Config Registers */ -/* ==================================================================== */ - -typedef union sh_x_dimm_cfg_u { - mmr_t sh_x_dimm_cfg_regval; - struct { - mmr_t dimm0_size : 3; - mmr_t dimm0_2bk : 1; - mmr_t dimm0_rev : 1; - mmr_t dimm0_cs : 2; - mmr_t reserved_0 : 1; - mmr_t dimm1_size : 3; - mmr_t dimm1_2bk : 1; - mmr_t dimm1_rev : 1; - mmr_t dimm1_cs : 2; - mmr_t reserved_1 : 1; - mmr_t dimm2_size : 3; - mmr_t dimm2_2bk : 1; - mmr_t dimm2_rev : 1; - mmr_t dimm2_cs : 2; - mmr_t reserved_2 : 1; - mmr_t dimm3_size : 3; - mmr_t dimm3_2bk : 1; - mmr_t dimm3_rev : 1; - mmr_t dimm3_cs : 2; - mmr_t reserved_3 : 1; - mmr_t freq : 4; - mmr_t reserved_4 : 28; - } sh_x_dimm_cfg_s; -} sh_x_dimm_cfg_u_t; - -/* ==================================================================== */ -/* Register "SH_Y_DIMM_CFG" */ -/* AC Mem Config Registers */ -/* ==================================================================== */ - -typedef union sh_y_dimm_cfg_u { - mmr_t sh_y_dimm_cfg_regval; - struct { - mmr_t dimm0_size : 3; - mmr_t dimm0_2bk : 1; - mmr_t dimm0_rev : 1; - mmr_t dimm0_cs : 2; - mmr_t reserved_0 : 1; - mmr_t dimm1_size : 3; - mmr_t dimm1_2bk : 1; - mmr_t dimm1_rev : 1; - mmr_t dimm1_cs : 2; - mmr_t reserved_1 : 1; - mmr_t dimm2_size : 3; - mmr_t dimm2_2bk : 1; - mmr_t dimm2_rev : 1; - mmr_t dimm2_cs : 2; - mmr_t reserved_2 : 1; - mmr_t dimm3_size : 3; - mmr_t dimm3_2bk : 1; - mmr_t dimm3_rev : 1; - mmr_t dimm3_cs : 2; - mmr_t reserved_3 : 1; - mmr_t freq : 4; - mmr_t reserved_4 : 28; - } sh_y_dimm_cfg_s; -} sh_y_dimm_cfg_u_t; - -/* ==================================================================== */ -/* Register "SH_JNR_DIMM_CFG" */ -/* AC Mem Config Registers */ -/* ==================================================================== */ - -typedef union sh_jnr_dimm_cfg_u { - mmr_t sh_jnr_dimm_cfg_regval; - struct { - mmr_t dimm0_size : 3; - mmr_t dimm0_2bk : 1; - mmr_t dimm0_rev : 1; - mmr_t dimm0_cs : 2; - mmr_t reserved_0 : 1; - mmr_t dimm1_size : 3; - mmr_t dimm1_2bk : 1; - mmr_t dimm1_rev : 1; - mmr_t dimm1_cs : 2; - mmr_t reserved_1 : 1; - mmr_t dimm2_size : 3; - mmr_t dimm2_2bk : 1; - mmr_t dimm2_rev : 1; - mmr_t dimm2_cs : 2; - mmr_t reserved_2 : 1; - mmr_t dimm3_size : 3; - mmr_t dimm3_2bk : 1; - mmr_t dimm3_rev : 1; - mmr_t dimm3_cs : 2; - mmr_t reserved_3 : 1; - mmr_t freq : 4; - mmr_t reserved_4 : 28; - } sh_jnr_dimm_cfg_s; -} sh_jnr_dimm_cfg_u_t; - -/* ==================================================================== */ -/* Register "SH_X_PHASE_CFG" */ -/* AC Phase Config Registers */ -/* ==================================================================== */ - -typedef union sh_x_phase_cfg_u { - mmr_t sh_x_phase_cfg_regval; - struct { - mmr_t ld_a : 5; - mmr_t ld_b : 5; - mmr_t dq_ld_a : 5; - mmr_t dq_ld_b : 5; - mmr_t hold : 5; - mmr_t hold_req : 5; - mmr_t add_cp : 5; - mmr_t bubble_en : 5; - mmr_t pha_bubble : 3; - mmr_t phb_bubble : 3; - mmr_t phc_bubble : 3; - mmr_t phd_bubble : 3; - mmr_t phe_bubble : 3; - mmr_t sel_a : 4; - mmr_t dq_sel_a : 4; - mmr_t reserved_0 : 1; - } sh_x_phase_cfg_s; -} sh_x_phase_cfg_u_t; - -/* ==================================================================== */ -/* Register "SH_X_CFG" */ -/* AC Config Registers */ -/* ==================================================================== */ - -typedef union sh_x_cfg_u { - mmr_t sh_x_cfg_regval; - struct { - mmr_t mode_serial : 1; - mmr_t dirc_random_replacement : 1; - mmr_t dir_counter_init : 6; - mmr_t ta_dlys : 32; - mmr_t da_bb_clr : 4; - mmr_t dc_bb_clr : 4; - mmr_t wt_bb_clr : 4; - mmr_t sso_wt_en : 1; - mmr_t trcd2_en : 1; - mmr_t trcd4_en : 1; - mmr_t req_cntr_dis : 1; - mmr_t req_cntr_val : 6; - mmr_t inv_cas_addr : 1; - mmr_t clr_dir_cache : 1; - } sh_x_cfg_s; -} sh_x_cfg_u_t; - -/* ==================================================================== */ -/* Register "SH_X_DQCT_CFG" */ -/* AC Config Registers */ -/* ==================================================================== */ - -typedef union sh_x_dqct_cfg_u { - mmr_t sh_x_dqct_cfg_regval; - struct { - mmr_t rd_sel : 4; - mmr_t wt_sel : 4; - mmr_t dta_rd_sel : 4; - mmr_t dta_wt_sel : 4; - mmr_t dir_rd_sel : 4; - mmr_t mdir_rd_sel : 4; - mmr_t reserved_0 : 40; - } sh_x_dqct_cfg_s; -} sh_x_dqct_cfg_u_t; - -/* ==================================================================== */ -/* Register "SH_X_REFRESH_CONTROL" */ -/* Refresh Control Register */ -/* ==================================================================== */ - -typedef union sh_x_refresh_control_u { - mmr_t sh_x_refresh_control_regval; - struct { - mmr_t enable : 8; - mmr_t interval : 9; - mmr_t hold : 6; - mmr_t interleave : 1; - mmr_t half_rate : 4; - mmr_t reserved_0 : 36; - } sh_x_refresh_control_s; -} sh_x_refresh_control_u_t; - -/* ==================================================================== */ -/* Register "SH_Y_PHASE_CFG" */ -/* AC Phase Config Registers */ -/* ==================================================================== */ - -typedef union sh_y_phase_cfg_u { - mmr_t sh_y_phase_cfg_regval; - struct { - mmr_t ld_a : 5; - mmr_t ld_b : 5; - mmr_t dq_ld_a : 5; - mmr_t dq_ld_b : 5; - mmr_t hold : 5; - mmr_t hold_req : 5; - mmr_t add_cp : 5; - mmr_t bubble_en : 5; - mmr_t pha_bubble : 3; - mmr_t phb_bubble : 3; - mmr_t phc_bubble : 3; - mmr_t phd_bubble : 3; - mmr_t phe_bubble : 3; - mmr_t sel_a : 4; - mmr_t dq_sel_a : 4; - mmr_t reserved_0 : 1; - } sh_y_phase_cfg_s; -} sh_y_phase_cfg_u_t; - -/* ==================================================================== */ -/* Register "SH_Y_CFG" */ -/* AC Config Registers */ -/* ==================================================================== */ - -typedef union sh_y_cfg_u { - mmr_t sh_y_cfg_regval; - struct { - mmr_t mode_serial : 1; - mmr_t dirc_random_replacement : 1; - mmr_t dir_counter_init : 6; - mmr_t ta_dlys : 32; - mmr_t da_bb_clr : 4; - mmr_t dc_bb_clr : 4; - mmr_t wt_bb_clr : 4; - mmr_t sso_wt_en : 1; - mmr_t trcd2_en : 1; - mmr_t trcd4_en : 1; - mmr_t req_cntr_dis : 1; - mmr_t req_cntr_val : 6; - mmr_t inv_cas_addr : 1; - mmr_t clr_dir_cache : 1; - } sh_y_cfg_s; -} sh_y_cfg_u_t; - -/* ==================================================================== */ -/* Register "SH_Y_DQCT_CFG" */ -/* AC Config Registers */ -/* ==================================================================== */ - -typedef union sh_y_dqct_cfg_u { - mmr_t sh_y_dqct_cfg_regval; - struct { - mmr_t rd_sel : 4; - mmr_t wt_sel : 4; - mmr_t dta_rd_sel : 4; - mmr_t dta_wt_sel : 4; - mmr_t dir_rd_sel : 4; - mmr_t mdir_rd_sel : 4; - mmr_t reserved_0 : 40; - } sh_y_dqct_cfg_s; -} sh_y_dqct_cfg_u_t; - -/* ==================================================================== */ -/* Register "SH_Y_REFRESH_CONTROL" */ -/* Refresh Control Register */ -/* ==================================================================== */ - -typedef union sh_y_refresh_control_u { - mmr_t sh_y_refresh_control_regval; - struct { - mmr_t enable : 8; - mmr_t interval : 9; - mmr_t hold : 6; - mmr_t interleave : 1; - mmr_t half_rate : 4; - mmr_t reserved_0 : 36; - } sh_y_refresh_control_s; -} sh_y_refresh_control_u_t; - -/* ==================================================================== */ -/* Register "SH_MEM_RED_BLACK" */ -/* MD fairness watchdog timers */ -/* ==================================================================== */ - -typedef union sh_mem_red_black_u { - mmr_t sh_mem_red_black_regval; - struct { - mmr_t time : 16; - mmr_t err_time : 36; - mmr_t reserved_0 : 12; - } sh_mem_red_black_s; -} sh_mem_red_black_u_t; - -/* ==================================================================== */ -/* Register "SH_MISC_MEM_CFG" */ -/* ==================================================================== */ - -typedef union sh_misc_mem_cfg_u { - mmr_t sh_misc_mem_cfg_regval; - struct { - mmr_t express_header_enable : 1; - mmr_t spec_header_enable : 1; - mmr_t jnr_bypass_enable : 1; - mmr_t xn_rd_same_as_pi : 1; - mmr_t low_write_buffer_threshold : 6; - mmr_t reserved_0 : 2; - mmr_t low_victim_buffer_threshold : 6; - mmr_t reserved_1 : 2; - mmr_t throttle_cnt : 8; - mmr_t disabled_read_tnums : 5; - mmr_t reserved_2 : 3; - mmr_t disabled_write_tnums : 5; - mmr_t reserved_3 : 3; - mmr_t disabled_victims : 6; - mmr_t reserved_4 : 2; - mmr_t alternate_xn_rp_plane : 1; - mmr_t reserved_5 : 11; - } sh_misc_mem_cfg_s; -} sh_misc_mem_cfg_u_t; - -/* ==================================================================== */ -/* Register "SH_PIO_RQ_CRD_CTL" */ -/* pio_rq Credit Circulation Control */ -/* ==================================================================== */ - -typedef union sh_pio_rq_crd_ctl_u { - mmr_t sh_pio_rq_crd_ctl_regval; - struct { - mmr_t depth : 6; - mmr_t reserved_0 : 58; - } sh_pio_rq_crd_ctl_s; -} sh_pio_rq_crd_ctl_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_MD_RQ_CRD_CTL" */ -/* pi_md_rq Credit Circulation Control */ -/* ==================================================================== */ - -typedef union sh_pi_md_rq_crd_ctl_u { - mmr_t sh_pi_md_rq_crd_ctl_regval; - struct { - mmr_t depth : 6; - mmr_t reserved_0 : 58; - } sh_pi_md_rq_crd_ctl_s; -} sh_pi_md_rq_crd_ctl_u_t; - -/* ==================================================================== */ -/* Register "SH_PI_MD_RP_CRD_CTL" */ -/* pi_md_rp Credit Circulation Control */ -/* ==================================================================== */ - -typedef union sh_pi_md_rp_crd_ctl_u { - mmr_t sh_pi_md_rp_crd_ctl_regval; - struct { - mmr_t depth : 6; - mmr_t reserved_0 : 58; - } sh_pi_md_rp_crd_ctl_s; -} sh_pi_md_rp_crd_ctl_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_MD_RQ_CRD_CTL" */ -/* xn_md_rq Credit Circulation Control */ -/* ==================================================================== */ - -typedef union sh_xn_md_rq_crd_ctl_u { - mmr_t sh_xn_md_rq_crd_ctl_regval; - struct { - mmr_t depth : 6; - mmr_t reserved_0 : 58; - } sh_xn_md_rq_crd_ctl_s; -} sh_xn_md_rq_crd_ctl_u_t; - -/* ==================================================================== */ -/* Register "SH_XN_MD_RP_CRD_CTL" */ -/* xn_md_rp Credit Circulation Control */ -/* ==================================================================== */ - -typedef union sh_xn_md_rp_crd_ctl_u { - mmr_t sh_xn_md_rp_crd_ctl_regval; - struct { - mmr_t depth : 6; - mmr_t reserved_0 : 58; - } sh_xn_md_rp_crd_ctl_s; -} sh_xn_md_rp_crd_ctl_u_t; - -/* ==================================================================== */ -/* Register "SH_X_TAG0" */ -/* AC tag Registers */ -/* ==================================================================== */ - -typedef union sh_x_tag0_u { - mmr_t sh_x_tag0_regval; - struct { - mmr_t tag : 20; - mmr_t reserved_0 : 44; - } sh_x_tag0_s; -} sh_x_tag0_u_t; - -/* ==================================================================== */ -/* Register "SH_X_TAG1" */ -/* AC tag Registers */ -/* ==================================================================== */ - -typedef union sh_x_tag1_u { - mmr_t sh_x_tag1_regval; - struct { - mmr_t tag : 20; - mmr_t reserved_0 : 44; - } sh_x_tag1_s; -} sh_x_tag1_u_t; - -/* ==================================================================== */ -/* Register "SH_X_TAG2" */ -/* AC tag Registers */ -/* ==================================================================== */ - -typedef union sh_x_tag2_u { - mmr_t sh_x_tag2_regval; - struct { - mmr_t tag : 20; - mmr_t reserved_0 : 44; - } sh_x_tag2_s; -} sh_x_tag2_u_t; - -/* ==================================================================== */ -/* Register "SH_X_TAG3" */ -/* AC tag Registers */ -/* ==================================================================== */ - -typedef union sh_x_tag3_u { - mmr_t sh_x_tag3_regval; - struct { - mmr_t tag : 20; - mmr_t reserved_0 : 44; - } sh_x_tag3_s; -} sh_x_tag3_u_t; - -/* ==================================================================== */ -/* Register "SH_X_TAG4" */ -/* AC tag Registers */ -/* ==================================================================== */ - -typedef union sh_x_tag4_u { - mmr_t sh_x_tag4_regval; - struct { - mmr_t tag : 20; - mmr_t reserved_0 : 44; - } sh_x_tag4_s; -} sh_x_tag4_u_t; - -/* ==================================================================== */ -/* Register "SH_X_TAG5" */ -/* AC tag Registers */ -/* ==================================================================== */ - -typedef union sh_x_tag5_u { - mmr_t sh_x_tag5_regval; - struct { - mmr_t tag : 20; - mmr_t reserved_0 : 44; - } sh_x_tag5_s; -} sh_x_tag5_u_t; - -/* ==================================================================== */ -/* Register "SH_X_TAG6" */ -/* AC tag Registers */ -/* ==================================================================== */ - -typedef union sh_x_tag6_u { - mmr_t sh_x_tag6_regval; - struct { - mmr_t tag : 20; - mmr_t reserved_0 : 44; - } sh_x_tag6_s; -} sh_x_tag6_u_t; - -/* ==================================================================== */ -/* Register "SH_X_TAG7" */ -/* AC tag Registers */ -/* ==================================================================== */ - -typedef union sh_x_tag7_u { - mmr_t sh_x_tag7_regval; - struct { - mmr_t tag : 20; - mmr_t reserved_0 : 44; - } sh_x_tag7_s; -} sh_x_tag7_u_t; - -/* ==================================================================== */ -/* Register "SH_Y_TAG0" */ -/* AC tag Registers */ -/* ==================================================================== */ - -typedef union sh_y_tag0_u { - mmr_t sh_y_tag0_regval; - struct { - mmr_t tag : 20; - mmr_t reserved_0 : 44; - } sh_y_tag0_s; -} sh_y_tag0_u_t; - -/* ==================================================================== */ -/* Register "SH_Y_TAG1" */ -/* AC tag Registers */ -/* ==================================================================== */ - -typedef union sh_y_tag1_u { - mmr_t sh_y_tag1_regval; - struct { - mmr_t tag : 20; - mmr_t reserved_0 : 44; - } sh_y_tag1_s; -} sh_y_tag1_u_t; - -/* ==================================================================== */ -/* Register "SH_Y_TAG2" */ -/* AC tag Registers */ -/* ==================================================================== */ - -typedef union sh_y_tag2_u { - mmr_t sh_y_tag2_regval; - struct { - mmr_t tag : 20; - mmr_t reserved_0 : 44; - } sh_y_tag2_s; -} sh_y_tag2_u_t; - -/* ==================================================================== */ -/* Register "SH_Y_TAG3" */ -/* AC tag Registers */ -/* ==================================================================== */ - -typedef union sh_y_tag3_u { - mmr_t sh_y_tag3_regval; - struct { - mmr_t tag : 20; - mmr_t reserved_0 : 44; - } sh_y_tag3_s; -} sh_y_tag3_u_t; - -/* ==================================================================== */ -/* Register "SH_Y_TAG4" */ -/* AC tag Registers */ -/* ==================================================================== */ - -typedef union sh_y_tag4_u { - mmr_t sh_y_tag4_regval; - struct { - mmr_t tag : 20; - mmr_t reserved_0 : 44; - } sh_y_tag4_s; -} sh_y_tag4_u_t; - -/* ==================================================================== */ -/* Register "SH_Y_TAG5" */ -/* AC tag Registers */ -/* ==================================================================== */ - -typedef union sh_y_tag5_u { - mmr_t sh_y_tag5_regval; - struct { - mmr_t tag : 20; - mmr_t reserved_0 : 44; - } sh_y_tag5_s; -} sh_y_tag5_u_t; - -/* ==================================================================== */ -/* Register "SH_Y_TAG6" */ -/* AC tag Registers */ -/* ==================================================================== */ - -typedef union sh_y_tag6_u { - mmr_t sh_y_tag6_regval; - struct { - mmr_t tag : 20; - mmr_t reserved_0 : 44; - } sh_y_tag6_s; -} sh_y_tag6_u_t; - -/* ==================================================================== */ -/* Register "SH_Y_TAG7" */ -/* AC tag Registers */ -/* ==================================================================== */ - -typedef union sh_y_tag7_u { - mmr_t sh_y_tag7_regval; - struct { - mmr_t tag : 20; - mmr_t reserved_0 : 44; - } sh_y_tag7_s; -} sh_y_tag7_u_t; - -/* ==================================================================== */ -/* Register "SH_MMRBIST_BASE" */ -/* mmr/bist base address */ -/* ==================================================================== */ - -typedef union sh_mmrbist_base_u { - mmr_t sh_mmrbist_base_regval; - struct { - mmr_t reserved_0 : 3; - mmr_t dword_addr : 47; - mmr_t reserved_1 : 14; - } sh_mmrbist_base_s; -} sh_mmrbist_base_u_t; - -/* ==================================================================== */ -/* Register "SH_MMRBIST_CTL" */ -/* Bist base address */ -/* ==================================================================== */ - -typedef union sh_mmrbist_ctl_u { - mmr_t sh_mmrbist_ctl_regval; - struct { - mmr_t block_length : 31; - mmr_t reserved_0 : 1; - mmr_t cmd : 7; - mmr_t reserved_1 : 1; - mmr_t in_progress : 1; - mmr_t fail : 1; - mmr_t mem_idle : 1; - mmr_t reserved_2 : 1; - mmr_t reset_state : 1; - mmr_t reserved_3 : 19; - } sh_mmrbist_ctl_s; -} sh_mmrbist_ctl_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DBUG_DATA_CFG" */ -/* configuration for md debug data muxes */ -/* ==================================================================== */ - -typedef union sh_md_dbug_data_cfg_u { - mmr_t sh_md_dbug_data_cfg_regval; - struct { - mmr_t nibble0_chiplet : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_nibble : 3; - mmr_t reserved_1 : 1; - mmr_t nibble1_chiplet : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_nibble : 3; - mmr_t reserved_3 : 1; - mmr_t nibble2_chiplet : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_nibble : 3; - mmr_t reserved_5 : 1; - mmr_t nibble3_chiplet : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_nibble : 3; - mmr_t reserved_7 : 1; - mmr_t nibble4_chiplet : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_nibble : 3; - mmr_t reserved_9 : 1; - mmr_t nibble5_chiplet : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_nibble : 3; - mmr_t reserved_11 : 1; - mmr_t nibble6_chiplet : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_nibble : 3; - mmr_t reserved_13 : 1; - mmr_t nibble7_chiplet : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_nibble : 3; - mmr_t reserved_15 : 1; - } sh_md_dbug_data_cfg_s; -} sh_md_dbug_data_cfg_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DBUG_TRIGGER_CFG" */ -/* configuration for md debug triggers */ -/* ==================================================================== */ - -typedef union sh_md_dbug_trigger_cfg_u { - mmr_t sh_md_dbug_trigger_cfg_regval; - struct { - mmr_t nibble0_chiplet : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_nibble : 3; - mmr_t reserved_1 : 1; - mmr_t nibble1_chiplet : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_nibble : 3; - mmr_t reserved_3 : 1; - mmr_t nibble2_chiplet : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_nibble : 3; - mmr_t reserved_5 : 1; - mmr_t nibble3_chiplet : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_nibble : 3; - mmr_t reserved_7 : 1; - mmr_t nibble4_chiplet : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_nibble : 3; - mmr_t reserved_9 : 1; - mmr_t nibble5_chiplet : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_nibble : 3; - mmr_t reserved_11 : 1; - mmr_t nibble6_chiplet : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_nibble : 3; - mmr_t reserved_13 : 1; - mmr_t nibble7_chiplet : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_nibble : 3; - mmr_t enable : 1; - } sh_md_dbug_trigger_cfg_s; -} sh_md_dbug_trigger_cfg_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DBUG_COMPARE" */ -/* md debug compare pattern and mask */ -/* ==================================================================== */ - -typedef union sh_md_dbug_compare_u { - mmr_t sh_md_dbug_compare_regval; - struct { - mmr_t pattern : 32; - mmr_t mask : 32; - } sh_md_dbug_compare_s; -} sh_md_dbug_compare_u_t; - -/* ==================================================================== */ -/* Register "SH_X_MOD_DBUG_SEL" */ -/* MD acx debug select */ -/* ==================================================================== */ - -typedef union sh_x_mod_dbug_sel_u { - mmr_t sh_x_mod_dbug_sel_regval; - struct { - mmr_t tag_sel : 8; - mmr_t wbq_sel : 8; - mmr_t arb_sel : 8; - mmr_t atl_sel : 11; - mmr_t atr_sel : 11; - mmr_t dql_sel : 6; - mmr_t dqr_sel : 6; - mmr_t reserved_0 : 6; - } sh_x_mod_dbug_sel_s; -} sh_x_mod_dbug_sel_u_t; - -/* ==================================================================== */ -/* Register "SH_X_DBUG_SEL" */ -/* MD acx debug select */ -/* ==================================================================== */ - -typedef union sh_x_dbug_sel_u { - mmr_t sh_x_dbug_sel_regval; - struct { - mmr_t dbg_sel : 24; - mmr_t reserved_0 : 40; - } sh_x_dbug_sel_s; -} sh_x_dbug_sel_u_t; - -/* ==================================================================== */ -/* Register "SH_X_LADDR_CMP" */ -/* MD acx address compare */ -/* ==================================================================== */ - -typedef union sh_x_laddr_cmp_u { - mmr_t sh_x_laddr_cmp_regval; - struct { - mmr_t cmp_val : 28; - mmr_t reserved_0 : 4; - mmr_t mask_val : 28; - mmr_t reserved_1 : 4; - } sh_x_laddr_cmp_s; -} sh_x_laddr_cmp_u_t; - -/* ==================================================================== */ -/* Register "SH_X_RADDR_CMP" */ -/* MD acx address compare */ -/* ==================================================================== */ - -typedef union sh_x_raddr_cmp_u { - mmr_t sh_x_raddr_cmp_regval; - struct { - mmr_t cmp_val : 28; - mmr_t reserved_0 : 4; - mmr_t mask_val : 28; - mmr_t reserved_1 : 4; - } sh_x_raddr_cmp_s; -} sh_x_raddr_cmp_u_t; - -/* ==================================================================== */ -/* Register "SH_X_TAG_CMP" */ -/* MD acx tagmgr compare */ -/* ==================================================================== */ - -typedef union sh_x_tag_cmp_u { - mmr_t sh_x_tag_cmp_regval; - struct { - mmr_t cmd : 8; - mmr_t addr : 33; - mmr_t src : 14; - mmr_t reserved_0 : 9; - } sh_x_tag_cmp_s; -} sh_x_tag_cmp_u_t; - -/* ==================================================================== */ -/* Register "SH_X_TAG_MASK" */ -/* MD acx tagmgr mask */ -/* ==================================================================== */ - -typedef union sh_x_tag_mask_u { - mmr_t sh_x_tag_mask_regval; - struct { - mmr_t cmd : 8; - mmr_t addr : 33; - mmr_t src : 14; - mmr_t reserved_0 : 9; - } sh_x_tag_mask_s; -} sh_x_tag_mask_u_t; - -/* ==================================================================== */ -/* Register "SH_Y_MOD_DBUG_SEL" */ -/* MD acy debug select */ -/* ==================================================================== */ - -typedef union sh_y_mod_dbug_sel_u { - mmr_t sh_y_mod_dbug_sel_regval; - struct { - mmr_t tag_sel : 8; - mmr_t wbq_sel : 8; - mmr_t arb_sel : 8; - mmr_t atl_sel : 11; - mmr_t atr_sel : 11; - mmr_t dql_sel : 6; - mmr_t dqr_sel : 6; - mmr_t reserved_0 : 6; - } sh_y_mod_dbug_sel_s; -} sh_y_mod_dbug_sel_u_t; - -/* ==================================================================== */ -/* Register "SH_Y_DBUG_SEL" */ -/* MD acy debug select */ -/* ==================================================================== */ - -typedef union sh_y_dbug_sel_u { - mmr_t sh_y_dbug_sel_regval; - struct { - mmr_t dbg_sel : 24; - mmr_t reserved_0 : 40; - } sh_y_dbug_sel_s; -} sh_y_dbug_sel_u_t; - -/* ==================================================================== */ -/* Register "SH_Y_LADDR_CMP" */ -/* MD acy address compare */ -/* ==================================================================== */ - -typedef union sh_y_laddr_cmp_u { - mmr_t sh_y_laddr_cmp_regval; - struct { - mmr_t cmp_val : 28; - mmr_t reserved_0 : 4; - mmr_t mask_val : 28; - mmr_t reserved_1 : 4; - } sh_y_laddr_cmp_s; -} sh_y_laddr_cmp_u_t; - -/* ==================================================================== */ -/* Register "SH_Y_RADDR_CMP" */ -/* MD acy address compare */ -/* ==================================================================== */ - -typedef union sh_y_raddr_cmp_u { - mmr_t sh_y_raddr_cmp_regval; - struct { - mmr_t cmp_val : 28; - mmr_t reserved_0 : 4; - mmr_t mask_val : 28; - mmr_t reserved_1 : 4; - } sh_y_raddr_cmp_s; -} sh_y_raddr_cmp_u_t; - -/* ==================================================================== */ -/* Register "SH_Y_TAG_CMP" */ -/* MD acy tagmgr compare */ -/* ==================================================================== */ - -typedef union sh_y_tag_cmp_u { - mmr_t sh_y_tag_cmp_regval; - struct { - mmr_t cmd : 8; - mmr_t addr : 33; - mmr_t src : 14; - mmr_t reserved_0 : 9; - } sh_y_tag_cmp_s; -} sh_y_tag_cmp_u_t; - -/* ==================================================================== */ -/* Register "SH_Y_TAG_MASK" */ -/* MD acy tagmgr mask */ -/* ==================================================================== */ - -typedef union sh_y_tag_mask_u { - mmr_t sh_y_tag_mask_regval; - struct { - mmr_t cmd : 8; - mmr_t addr : 33; - mmr_t src : 14; - mmr_t reserved_0 : 9; - } sh_y_tag_mask_s; -} sh_y_tag_mask_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_JNR_DBUG_DATA_CFG" */ -/* configuration for md jnr debug data muxes */ -/* ==================================================================== */ - -typedef union sh_md_jnr_dbug_data_cfg_u { - mmr_t sh_md_jnr_dbug_data_cfg_regval; - struct { - mmr_t nibble0_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble1_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble2_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble3_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble4_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble5_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble6_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble7_sel : 3; - mmr_t reserved_7 : 33; - } sh_md_jnr_dbug_data_cfg_s; -} sh_md_jnr_dbug_data_cfg_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_LAST_CREDIT" */ -/* captures last credit values on reset */ -/* ==================================================================== */ - -typedef union sh_md_last_credit_u { - mmr_t sh_md_last_credit_regval; - struct { - mmr_t rq_to_pi : 6; - mmr_t reserved_0 : 2; - mmr_t rp_to_pi : 6; - mmr_t reserved_1 : 2; - mmr_t rq_to_xn : 6; - mmr_t reserved_2 : 2; - mmr_t rp_to_xn : 6; - mmr_t reserved_3 : 2; - mmr_t to_lb : 6; - mmr_t reserved_4 : 26; - } sh_md_last_credit_s; -} sh_md_last_credit_u_t; - -/* ==================================================================== */ -/* Register "SH_MEM_CAPTURE_ADDR" */ -/* Address capture address register */ -/* ==================================================================== */ - -typedef union sh_mem_capture_addr_u { - mmr_t sh_mem_capture_addr_regval; - struct { - mmr_t reserved_0 : 3; - mmr_t addr : 33; - mmr_t cmd : 8; - mmr_t reserved_1 : 20; - } sh_mem_capture_addr_s; -} sh_mem_capture_addr_u_t; - -/* ==================================================================== */ -/* Register "SH_MEM_CAPTURE_MASK" */ -/* Address capture mask register */ -/* ==================================================================== */ - -typedef union sh_mem_capture_mask_u { - mmr_t sh_mem_capture_mask_regval; - struct { - mmr_t reserved_0 : 3; - mmr_t addr : 33; - mmr_t cmd : 8; - mmr_t enable_local : 1; - mmr_t enable_remote : 1; - mmr_t reserved_1 : 18; - } sh_mem_capture_mask_s; -} sh_mem_capture_mask_u_t; - -/* ==================================================================== */ -/* Register "SH_MEM_CAPTURE_HDR" */ -/* Address capture header register */ -/* ==================================================================== */ - -typedef union sh_mem_capture_hdr_u { - mmr_t sh_mem_capture_hdr_regval; - struct { - mmr_t reserved_0 : 3; - mmr_t addr : 33; - mmr_t cmd : 8; - mmr_t src : 14; - mmr_t cntr : 6; - } sh_mem_capture_hdr_s; -} sh_mem_capture_hdr_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_CONFIG" */ -/* DQ directory config register */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_dir_config_u { - mmr_t sh_md_dqlp_mmr_dir_config_regval; - struct { - mmr_t sys_size : 3; - mmr_t en_direcc : 1; - mmr_t en_dirpois : 1; - mmr_t reserved_0 : 59; - } sh_md_dqlp_mmr_dir_config_s; -} sh_md_dqlp_mmr_dir_config_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRESVEC0" */ -/* node [63:0] presence bits */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_dir_presvec0_u { - mmr_t sh_md_dqlp_mmr_dir_presvec0_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_presvec0_s; -} sh_md_dqlp_mmr_dir_presvec0_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRESVEC1" */ -/* node [127:64] presence bits */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_dir_presvec1_u { - mmr_t sh_md_dqlp_mmr_dir_presvec1_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_presvec1_s; -} sh_md_dqlp_mmr_dir_presvec1_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRESVEC2" */ -/* node [191:128] presence bits */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_dir_presvec2_u { - mmr_t sh_md_dqlp_mmr_dir_presvec2_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_presvec2_s; -} sh_md_dqlp_mmr_dir_presvec2_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRESVEC3" */ -/* node [255:192] presence bits */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_dir_presvec3_u { - mmr_t sh_md_dqlp_mmr_dir_presvec3_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_presvec3_s; -} sh_md_dqlp_mmr_dir_presvec3_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC0" */ -/* local vector for acc=0 */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_dir_locvec0_u { - mmr_t sh_md_dqlp_mmr_dir_locvec0_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_locvec0_s; -} sh_md_dqlp_mmr_dir_locvec0_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC1" */ -/* local vector for acc=1 */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_dir_locvec1_u { - mmr_t sh_md_dqlp_mmr_dir_locvec1_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_locvec1_s; -} sh_md_dqlp_mmr_dir_locvec1_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC2" */ -/* local vector for acc=2 */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_dir_locvec2_u { - mmr_t sh_md_dqlp_mmr_dir_locvec2_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_locvec2_s; -} sh_md_dqlp_mmr_dir_locvec2_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC3" */ -/* local vector for acc=3 */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_dir_locvec3_u { - mmr_t sh_md_dqlp_mmr_dir_locvec3_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_locvec3_s; -} sh_md_dqlp_mmr_dir_locvec3_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC4" */ -/* local vector for acc=4 */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_dir_locvec4_u { - mmr_t sh_md_dqlp_mmr_dir_locvec4_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_locvec4_s; -} sh_md_dqlp_mmr_dir_locvec4_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC5" */ -/* local vector for acc=5 */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_dir_locvec5_u { - mmr_t sh_md_dqlp_mmr_dir_locvec5_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_locvec5_s; -} sh_md_dqlp_mmr_dir_locvec5_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC6" */ -/* local vector for acc=6 */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_dir_locvec6_u { - mmr_t sh_md_dqlp_mmr_dir_locvec6_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_locvec6_s; -} sh_md_dqlp_mmr_dir_locvec6_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC7" */ -/* local vector for acc=7 */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_dir_locvec7_u { - mmr_t sh_md_dqlp_mmr_dir_locvec7_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_locvec7_s; -} sh_md_dqlp_mmr_dir_locvec7_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC0" */ -/* privilege vector for acc=0 */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_dir_privec0_u { - mmr_t sh_md_dqlp_mmr_dir_privec0_regval; - struct { - mmr_t in : 14; - mmr_t out : 14; - mmr_t reserved_0 : 36; - } sh_md_dqlp_mmr_dir_privec0_s; -} sh_md_dqlp_mmr_dir_privec0_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC1" */ -/* privilege vector for acc=1 */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_dir_privec1_u { - mmr_t sh_md_dqlp_mmr_dir_privec1_regval; - struct { - mmr_t in : 14; - mmr_t out : 14; - mmr_t reserved_0 : 36; - } sh_md_dqlp_mmr_dir_privec1_s; -} sh_md_dqlp_mmr_dir_privec1_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC2" */ -/* privilege vector for acc=2 */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_dir_privec2_u { - mmr_t sh_md_dqlp_mmr_dir_privec2_regval; - struct { - mmr_t in : 14; - mmr_t out : 14; - mmr_t reserved_0 : 36; - } sh_md_dqlp_mmr_dir_privec2_s; -} sh_md_dqlp_mmr_dir_privec2_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC3" */ -/* privilege vector for acc=3 */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_dir_privec3_u { - mmr_t sh_md_dqlp_mmr_dir_privec3_regval; - struct { - mmr_t in : 14; - mmr_t out : 14; - mmr_t reserved_0 : 36; - } sh_md_dqlp_mmr_dir_privec3_s; -} sh_md_dqlp_mmr_dir_privec3_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC4" */ -/* privilege vector for acc=4 */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_dir_privec4_u { - mmr_t sh_md_dqlp_mmr_dir_privec4_regval; - struct { - mmr_t in : 14; - mmr_t out : 14; - mmr_t reserved_0 : 36; - } sh_md_dqlp_mmr_dir_privec4_s; -} sh_md_dqlp_mmr_dir_privec4_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC5" */ -/* privilege vector for acc=5 */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_dir_privec5_u { - mmr_t sh_md_dqlp_mmr_dir_privec5_regval; - struct { - mmr_t in : 14; - mmr_t out : 14; - mmr_t reserved_0 : 36; - } sh_md_dqlp_mmr_dir_privec5_s; -} sh_md_dqlp_mmr_dir_privec5_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC6" */ -/* privilege vector for acc=6 */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_dir_privec6_u { - mmr_t sh_md_dqlp_mmr_dir_privec6_regval; - struct { - mmr_t in : 14; - mmr_t out : 14; - mmr_t reserved_0 : 36; - } sh_md_dqlp_mmr_dir_privec6_s; -} sh_md_dqlp_mmr_dir_privec6_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC7" */ -/* privilege vector for acc=7 */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_dir_privec7_u { - mmr_t sh_md_dqlp_mmr_dir_privec7_regval; - struct { - mmr_t in : 14; - mmr_t out : 14; - mmr_t reserved_0 : 36; - } sh_md_dqlp_mmr_dir_privec7_s; -} sh_md_dqlp_mmr_dir_privec7_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_TIMER" */ -/* MD SXRO timer */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_dir_timer_u { - mmr_t sh_md_dqlp_mmr_dir_timer_regval; - struct { - mmr_t timer_div : 12; - mmr_t timer_en : 1; - mmr_t timer_cur : 9; - mmr_t reserved_0 : 42; - } sh_md_dqlp_mmr_dir_timer_s; -} sh_md_dqlp_mmr_dir_timer_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY" */ -/* directory pio write data */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_piowd_dir_entry_u { - mmr_t sh_md_dqlp_mmr_piowd_dir_entry_regval; - struct { - mmr_t dira : 26; - mmr_t dirb : 26; - mmr_t pri : 3; - mmr_t acc : 3; - mmr_t reserved_0 : 6; - } sh_md_dqlp_mmr_piowd_dir_entry_s; -} sh_md_dqlp_mmr_piowd_dir_entry_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_PIOWD_DIR_ECC" */ -/* directory ecc register */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_piowd_dir_ecc_u { - mmr_t sh_md_dqlp_mmr_piowd_dir_ecc_regval; - struct { - mmr_t ecca : 7; - mmr_t eccb : 7; - mmr_t reserved_0 : 50; - } sh_md_dqlp_mmr_piowd_dir_ecc_s; -} sh_md_dqlp_mmr_piowd_dir_ecc_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY" */ -/* x directory pio read data */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_xpiord_xdir_entry_u { - mmr_t sh_md_dqlp_mmr_xpiord_xdir_entry_regval; - struct { - mmr_t dira : 26; - mmr_t dirb : 26; - mmr_t pri : 3; - mmr_t acc : 3; - mmr_t cor : 1; - mmr_t unc : 1; - mmr_t reserved_0 : 4; - } sh_md_dqlp_mmr_xpiord_xdir_entry_s; -} sh_md_dqlp_mmr_xpiord_xdir_entry_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XPIORD_XDIR_ECC" */ -/* x directory ecc */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_xpiord_xdir_ecc_u { - mmr_t sh_md_dqlp_mmr_xpiord_xdir_ecc_regval; - struct { - mmr_t ecca : 7; - mmr_t eccb : 7; - mmr_t reserved_0 : 50; - } sh_md_dqlp_mmr_xpiord_xdir_ecc_s; -} sh_md_dqlp_mmr_xpiord_xdir_ecc_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY" */ -/* y directory pio read data */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_ypiord_ydir_entry_u { - mmr_t sh_md_dqlp_mmr_ypiord_ydir_entry_regval; - struct { - mmr_t dira : 26; - mmr_t dirb : 26; - mmr_t pri : 3; - mmr_t acc : 3; - mmr_t cor : 1; - mmr_t unc : 1; - mmr_t reserved_0 : 4; - } sh_md_dqlp_mmr_ypiord_ydir_entry_s; -} sh_md_dqlp_mmr_ypiord_ydir_entry_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YPIORD_YDIR_ECC" */ -/* y directory ecc */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_ypiord_ydir_ecc_u { - mmr_t sh_md_dqlp_mmr_ypiord_ydir_ecc_regval; - struct { - mmr_t ecca : 7; - mmr_t eccb : 7; - mmr_t reserved_0 : 50; - } sh_md_dqlp_mmr_ypiord_ydir_ecc_s; -} sh_md_dqlp_mmr_ypiord_ydir_ecc_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XCERR1" */ -/* correctable dir ecc group 1 error register */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_xcerr1_u { - mmr_t sh_md_dqlp_mmr_xcerr1_regval; - struct { - mmr_t grp1 : 36; - mmr_t val : 1; - mmr_t more : 1; - mmr_t arm : 1; - mmr_t reserved_0 : 25; - } sh_md_dqlp_mmr_xcerr1_s; -} sh_md_dqlp_mmr_xcerr1_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XCERR2" */ -/* correctable dir ecc group 2 error register */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_xcerr2_u { - mmr_t sh_md_dqlp_mmr_xcerr2_regval; - struct { - mmr_t grp2 : 36; - mmr_t val : 1; - mmr_t more : 1; - mmr_t reserved_0 : 26; - } sh_md_dqlp_mmr_xcerr2_s; -} sh_md_dqlp_mmr_xcerr2_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XUERR1" */ -/* uncorrectable dir ecc group 1 error register */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_xuerr1_u { - mmr_t sh_md_dqlp_mmr_xuerr1_regval; - struct { - mmr_t grp1 : 36; - mmr_t val : 1; - mmr_t more : 1; - mmr_t arm : 1; - mmr_t reserved_0 : 25; - } sh_md_dqlp_mmr_xuerr1_s; -} sh_md_dqlp_mmr_xuerr1_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XUERR2" */ -/* uncorrectable dir ecc group 2 error register */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_xuerr2_u { - mmr_t sh_md_dqlp_mmr_xuerr2_regval; - struct { - mmr_t grp2 : 36; - mmr_t val : 1; - mmr_t more : 1; - mmr_t reserved_0 : 26; - } sh_md_dqlp_mmr_xuerr2_s; -} sh_md_dqlp_mmr_xuerr2_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XPERR" */ -/* protocol error register */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_xperr_u { - mmr_t sh_md_dqlp_mmr_xperr_regval; - struct { - mmr_t dir : 26; - mmr_t cmd : 8; - mmr_t src : 14; - mmr_t prige : 1; - mmr_t priv : 1; - mmr_t cor : 1; - mmr_t unc : 1; - mmr_t mybit : 8; - mmr_t val : 1; - mmr_t more : 1; - mmr_t arm : 1; - mmr_t reserved_0 : 1; - } sh_md_dqlp_mmr_xperr_s; -} sh_md_dqlp_mmr_xperr_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YCERR1" */ -/* correctable dir ecc group 1 error register */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_ycerr1_u { - mmr_t sh_md_dqlp_mmr_ycerr1_regval; - struct { - mmr_t grp1 : 36; - mmr_t val : 1; - mmr_t more : 1; - mmr_t arm : 1; - mmr_t reserved_0 : 25; - } sh_md_dqlp_mmr_ycerr1_s; -} sh_md_dqlp_mmr_ycerr1_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YCERR2" */ -/* correctable dir ecc group 2 error register */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_ycerr2_u { - mmr_t sh_md_dqlp_mmr_ycerr2_regval; - struct { - mmr_t grp2 : 36; - mmr_t val : 1; - mmr_t more : 1; - mmr_t reserved_0 : 26; - } sh_md_dqlp_mmr_ycerr2_s; -} sh_md_dqlp_mmr_ycerr2_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YUERR1" */ -/* uncorrectable dir ecc group 1 error register */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_yuerr1_u { - mmr_t sh_md_dqlp_mmr_yuerr1_regval; - struct { - mmr_t grp1 : 36; - mmr_t val : 1; - mmr_t more : 1; - mmr_t arm : 1; - mmr_t reserved_0 : 25; - } sh_md_dqlp_mmr_yuerr1_s; -} sh_md_dqlp_mmr_yuerr1_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YUERR2" */ -/* uncorrectable dir ecc group 2 error register */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_yuerr2_u { - mmr_t sh_md_dqlp_mmr_yuerr2_regval; - struct { - mmr_t grp2 : 36; - mmr_t val : 1; - mmr_t more : 1; - mmr_t reserved_0 : 26; - } sh_md_dqlp_mmr_yuerr2_s; -} sh_md_dqlp_mmr_yuerr2_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YPERR" */ -/* protocol error register */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_yperr_u { - mmr_t sh_md_dqlp_mmr_yperr_regval; - struct { - mmr_t dir : 26; - mmr_t cmd : 8; - mmr_t src : 14; - mmr_t prige : 1; - mmr_t priv : 1; - mmr_t cor : 1; - mmr_t unc : 1; - mmr_t mybit : 8; - mmr_t val : 1; - mmr_t more : 1; - mmr_t arm : 1; - mmr_t reserved_0 : 1; - } sh_md_dqlp_mmr_yperr_s; -} sh_md_dqlp_mmr_yperr_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_CMDTRIG" */ -/* cmd triggers */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_dir_cmdtrig_u { - mmr_t sh_md_dqlp_mmr_dir_cmdtrig_regval; - struct { - mmr_t cmd0 : 8; - mmr_t cmd1 : 8; - mmr_t cmd2 : 8; - mmr_t cmd3 : 8; - mmr_t reserved_0 : 32; - } sh_md_dqlp_mmr_dir_cmdtrig_s; -} sh_md_dqlp_mmr_dir_cmdtrig_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_TBLTRIG" */ -/* dir table trigger */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_dir_tbltrig_u { - mmr_t sh_md_dqlp_mmr_dir_tbltrig_regval; - struct { - mmr_t src : 14; - mmr_t cmd : 8; - mmr_t acc : 2; - mmr_t prige : 1; - mmr_t dirst : 9; - mmr_t mybit : 8; - mmr_t reserved_0 : 22; - } sh_md_dqlp_mmr_dir_tbltrig_s; -} sh_md_dqlp_mmr_dir_tbltrig_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_TBLMASK" */ -/* dir table trigger mask */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_dir_tblmask_u { - mmr_t sh_md_dqlp_mmr_dir_tblmask_regval; - struct { - mmr_t src : 14; - mmr_t cmd : 8; - mmr_t acc : 2; - mmr_t prige : 1; - mmr_t dirst : 9; - mmr_t mybit : 8; - mmr_t reserved_0 : 22; - } sh_md_dqlp_mmr_dir_tblmask_s; -} sh_md_dqlp_mmr_dir_tblmask_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XBIST_H" */ -/* rising edge bist/fill pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_xbist_h_u { - mmr_t sh_md_dqlp_mmr_xbist_h_regval; - struct { - mmr_t pat : 32; - mmr_t reserved_0 : 8; - mmr_t inv : 1; - mmr_t rot : 1; - mmr_t arm : 1; - mmr_t reserved_1 : 21; - } sh_md_dqlp_mmr_xbist_h_s; -} sh_md_dqlp_mmr_xbist_h_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XBIST_L" */ -/* falling edge bist/fill pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_xbist_l_u { - mmr_t sh_md_dqlp_mmr_xbist_l_regval; - struct { - mmr_t pat : 32; - mmr_t reserved_0 : 8; - mmr_t inv : 1; - mmr_t rot : 1; - mmr_t reserved_1 : 22; - } sh_md_dqlp_mmr_xbist_l_s; -} sh_md_dqlp_mmr_xbist_l_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XBIST_ERR_H" */ -/* rising edge bist error pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_xbist_err_h_u { - mmr_t sh_md_dqlp_mmr_xbist_err_h_regval; - struct { - mmr_t pat : 32; - mmr_t reserved_0 : 8; - mmr_t val : 1; - mmr_t more : 1; - mmr_t reserved_1 : 22; - } sh_md_dqlp_mmr_xbist_err_h_s; -} sh_md_dqlp_mmr_xbist_err_h_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XBIST_ERR_L" */ -/* falling edge bist error pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_xbist_err_l_u { - mmr_t sh_md_dqlp_mmr_xbist_err_l_regval; - struct { - mmr_t pat : 32; - mmr_t reserved_0 : 8; - mmr_t val : 1; - mmr_t more : 1; - mmr_t reserved_1 : 22; - } sh_md_dqlp_mmr_xbist_err_l_s; -} sh_md_dqlp_mmr_xbist_err_l_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YBIST_H" */ -/* rising edge bist/fill pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_ybist_h_u { - mmr_t sh_md_dqlp_mmr_ybist_h_regval; - struct { - mmr_t pat : 32; - mmr_t reserved_0 : 8; - mmr_t inv : 1; - mmr_t rot : 1; - mmr_t arm : 1; - mmr_t reserved_1 : 21; - } sh_md_dqlp_mmr_ybist_h_s; -} sh_md_dqlp_mmr_ybist_h_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YBIST_L" */ -/* falling edge bist/fill pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_ybist_l_u { - mmr_t sh_md_dqlp_mmr_ybist_l_regval; - struct { - mmr_t pat : 32; - mmr_t reserved_0 : 8; - mmr_t inv : 1; - mmr_t rot : 1; - mmr_t reserved_1 : 22; - } sh_md_dqlp_mmr_ybist_l_s; -} sh_md_dqlp_mmr_ybist_l_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YBIST_ERR_H" */ -/* rising edge bist error pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_ybist_err_h_u { - mmr_t sh_md_dqlp_mmr_ybist_err_h_regval; - struct { - mmr_t pat : 32; - mmr_t reserved_0 : 8; - mmr_t val : 1; - mmr_t more : 1; - mmr_t reserved_1 : 22; - } sh_md_dqlp_mmr_ybist_err_h_s; -} sh_md_dqlp_mmr_ybist_err_h_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YBIST_ERR_L" */ -/* falling edge bist error pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqlp_mmr_ybist_err_l_u { - mmr_t sh_md_dqlp_mmr_ybist_err_l_regval; - struct { - mmr_t pat : 32; - mmr_t reserved_0 : 8; - mmr_t val : 1; - mmr_t more : 1; - mmr_t reserved_1 : 22; - } sh_md_dqlp_mmr_ybist_err_l_s; -} sh_md_dqlp_mmr_ybist_err_l_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLS_MMR_XBIST_H" */ -/* rising edge bist/fill pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqls_mmr_xbist_h_u { - mmr_t sh_md_dqls_mmr_xbist_h_regval; - struct { - mmr_t pat : 40; - mmr_t inv : 1; - mmr_t rot : 1; - mmr_t arm : 1; - mmr_t reserved_0 : 21; - } sh_md_dqls_mmr_xbist_h_s; -} sh_md_dqls_mmr_xbist_h_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLS_MMR_XBIST_L" */ -/* falling edge bist/fill pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqls_mmr_xbist_l_u { - mmr_t sh_md_dqls_mmr_xbist_l_regval; - struct { - mmr_t pat : 40; - mmr_t inv : 1; - mmr_t rot : 1; - mmr_t reserved_0 : 22; - } sh_md_dqls_mmr_xbist_l_s; -} sh_md_dqls_mmr_xbist_l_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLS_MMR_XBIST_ERR_H" */ -/* rising edge bist error pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqls_mmr_xbist_err_h_u { - mmr_t sh_md_dqls_mmr_xbist_err_h_regval; - struct { - mmr_t pat : 40; - mmr_t val : 1; - mmr_t more : 1; - mmr_t reserved_0 : 22; - } sh_md_dqls_mmr_xbist_err_h_s; -} sh_md_dqls_mmr_xbist_err_h_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLS_MMR_XBIST_ERR_L" */ -/* falling edge bist error pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqls_mmr_xbist_err_l_u { - mmr_t sh_md_dqls_mmr_xbist_err_l_regval; - struct { - mmr_t pat : 40; - mmr_t val : 1; - mmr_t more : 1; - mmr_t reserved_0 : 22; - } sh_md_dqls_mmr_xbist_err_l_s; -} sh_md_dqls_mmr_xbist_err_l_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLS_MMR_YBIST_H" */ -/* rising edge bist/fill pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqls_mmr_ybist_h_u { - mmr_t sh_md_dqls_mmr_ybist_h_regval; - struct { - mmr_t pat : 40; - mmr_t inv : 1; - mmr_t rot : 1; - mmr_t arm : 1; - mmr_t reserved_0 : 21; - } sh_md_dqls_mmr_ybist_h_s; -} sh_md_dqls_mmr_ybist_h_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLS_MMR_YBIST_L" */ -/* falling edge bist/fill pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqls_mmr_ybist_l_u { - mmr_t sh_md_dqls_mmr_ybist_l_regval; - struct { - mmr_t pat : 40; - mmr_t inv : 1; - mmr_t rot : 1; - mmr_t reserved_0 : 22; - } sh_md_dqls_mmr_ybist_l_s; -} sh_md_dqls_mmr_ybist_l_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLS_MMR_YBIST_ERR_H" */ -/* rising edge bist error pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqls_mmr_ybist_err_h_u { - mmr_t sh_md_dqls_mmr_ybist_err_h_regval; - struct { - mmr_t pat : 40; - mmr_t val : 1; - mmr_t more : 1; - mmr_t reserved_0 : 22; - } sh_md_dqls_mmr_ybist_err_h_s; -} sh_md_dqls_mmr_ybist_err_h_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLS_MMR_YBIST_ERR_L" */ -/* falling edge bist error pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqls_mmr_ybist_err_l_u { - mmr_t sh_md_dqls_mmr_ybist_err_l_regval; - struct { - mmr_t pat : 40; - mmr_t val : 1; - mmr_t more : 1; - mmr_t reserved_0 : 22; - } sh_md_dqls_mmr_ybist_err_l_s; -} sh_md_dqls_mmr_ybist_err_l_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLS_MMR_JNR_DEBUG" */ -/* joiner/fct debug configuration */ -/* ==================================================================== */ - -typedef union sh_md_dqls_mmr_jnr_debug_u { - mmr_t sh_md_dqls_mmr_jnr_debug_regval; - struct { - mmr_t px : 1; - mmr_t rw : 1; - mmr_t reserved_0 : 62; - } sh_md_dqls_mmr_jnr_debug_s; -} sh_md_dqls_mmr_jnr_debug_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQLS_MMR_XAMOPW_ERR" */ -/* amo/partial rmw ecc error register */ -/* ==================================================================== */ - -typedef union sh_md_dqls_mmr_xamopw_err_u { - mmr_t sh_md_dqls_mmr_xamopw_err_regval; - struct { - mmr_t ssyn : 8; - mmr_t scor : 1; - mmr_t sunc : 1; - mmr_t reserved_0 : 6; - mmr_t rsyn : 8; - mmr_t rcor : 1; - mmr_t runc : 1; - mmr_t reserved_1 : 6; - mmr_t arm : 1; - mmr_t reserved_2 : 31; - } sh_md_dqls_mmr_xamopw_err_s; -} sh_md_dqls_mmr_xamopw_err_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_CONFIG" */ -/* DQ directory config register */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_dir_config_u { - mmr_t sh_md_dqrp_mmr_dir_config_regval; - struct { - mmr_t sys_size : 3; - mmr_t en_direcc : 1; - mmr_t en_dirpois : 1; - mmr_t reserved_0 : 59; - } sh_md_dqrp_mmr_dir_config_s; -} sh_md_dqrp_mmr_dir_config_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRESVEC0" */ -/* node [63:0] presence bits */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_dir_presvec0_u { - mmr_t sh_md_dqrp_mmr_dir_presvec0_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_presvec0_s; -} sh_md_dqrp_mmr_dir_presvec0_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRESVEC1" */ -/* node [127:64] presence bits */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_dir_presvec1_u { - mmr_t sh_md_dqrp_mmr_dir_presvec1_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_presvec1_s; -} sh_md_dqrp_mmr_dir_presvec1_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRESVEC2" */ -/* node [191:128] presence bits */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_dir_presvec2_u { - mmr_t sh_md_dqrp_mmr_dir_presvec2_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_presvec2_s; -} sh_md_dqrp_mmr_dir_presvec2_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRESVEC3" */ -/* node [255:192] presence bits */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_dir_presvec3_u { - mmr_t sh_md_dqrp_mmr_dir_presvec3_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_presvec3_s; -} sh_md_dqrp_mmr_dir_presvec3_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC0" */ -/* local vector for acc=0 */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_dir_locvec0_u { - mmr_t sh_md_dqrp_mmr_dir_locvec0_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_locvec0_s; -} sh_md_dqrp_mmr_dir_locvec0_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC1" */ -/* local vector for acc=1 */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_dir_locvec1_u { - mmr_t sh_md_dqrp_mmr_dir_locvec1_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_locvec1_s; -} sh_md_dqrp_mmr_dir_locvec1_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC2" */ -/* local vector for acc=2 */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_dir_locvec2_u { - mmr_t sh_md_dqrp_mmr_dir_locvec2_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_locvec2_s; -} sh_md_dqrp_mmr_dir_locvec2_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC3" */ -/* local vector for acc=3 */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_dir_locvec3_u { - mmr_t sh_md_dqrp_mmr_dir_locvec3_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_locvec3_s; -} sh_md_dqrp_mmr_dir_locvec3_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC4" */ -/* local vector for acc=4 */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_dir_locvec4_u { - mmr_t sh_md_dqrp_mmr_dir_locvec4_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_locvec4_s; -} sh_md_dqrp_mmr_dir_locvec4_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC5" */ -/* local vector for acc=5 */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_dir_locvec5_u { - mmr_t sh_md_dqrp_mmr_dir_locvec5_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_locvec5_s; -} sh_md_dqrp_mmr_dir_locvec5_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC6" */ -/* local vector for acc=6 */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_dir_locvec6_u { - mmr_t sh_md_dqrp_mmr_dir_locvec6_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_locvec6_s; -} sh_md_dqrp_mmr_dir_locvec6_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC7" */ -/* local vector for acc=7 */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_dir_locvec7_u { - mmr_t sh_md_dqrp_mmr_dir_locvec7_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_locvec7_s; -} sh_md_dqrp_mmr_dir_locvec7_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC0" */ -/* privilege vector for acc=0 */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_dir_privec0_u { - mmr_t sh_md_dqrp_mmr_dir_privec0_regval; - struct { - mmr_t in : 14; - mmr_t out : 14; - mmr_t reserved_0 : 36; - } sh_md_dqrp_mmr_dir_privec0_s; -} sh_md_dqrp_mmr_dir_privec0_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC1" */ -/* privilege vector for acc=1 */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_dir_privec1_u { - mmr_t sh_md_dqrp_mmr_dir_privec1_regval; - struct { - mmr_t in : 14; - mmr_t out : 14; - mmr_t reserved_0 : 36; - } sh_md_dqrp_mmr_dir_privec1_s; -} sh_md_dqrp_mmr_dir_privec1_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC2" */ -/* privilege vector for acc=2 */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_dir_privec2_u { - mmr_t sh_md_dqrp_mmr_dir_privec2_regval; - struct { - mmr_t in : 14; - mmr_t out : 14; - mmr_t reserved_0 : 36; - } sh_md_dqrp_mmr_dir_privec2_s; -} sh_md_dqrp_mmr_dir_privec2_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC3" */ -/* privilege vector for acc=3 */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_dir_privec3_u { - mmr_t sh_md_dqrp_mmr_dir_privec3_regval; - struct { - mmr_t in : 14; - mmr_t out : 14; - mmr_t reserved_0 : 36; - } sh_md_dqrp_mmr_dir_privec3_s; -} sh_md_dqrp_mmr_dir_privec3_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC4" */ -/* privilege vector for acc=4 */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_dir_privec4_u { - mmr_t sh_md_dqrp_mmr_dir_privec4_regval; - struct { - mmr_t in : 14; - mmr_t out : 14; - mmr_t reserved_0 : 36; - } sh_md_dqrp_mmr_dir_privec4_s; -} sh_md_dqrp_mmr_dir_privec4_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC5" */ -/* privilege vector for acc=5 */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_dir_privec5_u { - mmr_t sh_md_dqrp_mmr_dir_privec5_regval; - struct { - mmr_t in : 14; - mmr_t out : 14; - mmr_t reserved_0 : 36; - } sh_md_dqrp_mmr_dir_privec5_s; -} sh_md_dqrp_mmr_dir_privec5_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC6" */ -/* privilege vector for acc=6 */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_dir_privec6_u { - mmr_t sh_md_dqrp_mmr_dir_privec6_regval; - struct { - mmr_t in : 14; - mmr_t out : 14; - mmr_t reserved_0 : 36; - } sh_md_dqrp_mmr_dir_privec6_s; -} sh_md_dqrp_mmr_dir_privec6_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC7" */ -/* privilege vector for acc=7 */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_dir_privec7_u { - mmr_t sh_md_dqrp_mmr_dir_privec7_regval; - struct { - mmr_t in : 14; - mmr_t out : 14; - mmr_t reserved_0 : 36; - } sh_md_dqrp_mmr_dir_privec7_s; -} sh_md_dqrp_mmr_dir_privec7_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_TIMER" */ -/* MD SXRO timer */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_dir_timer_u { - mmr_t sh_md_dqrp_mmr_dir_timer_regval; - struct { - mmr_t timer_div : 12; - mmr_t timer_en : 1; - mmr_t timer_cur : 9; - mmr_t reserved_0 : 42; - } sh_md_dqrp_mmr_dir_timer_s; -} sh_md_dqrp_mmr_dir_timer_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY" */ -/* directory pio write data */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_piowd_dir_entry_u { - mmr_t sh_md_dqrp_mmr_piowd_dir_entry_regval; - struct { - mmr_t dira : 26; - mmr_t dirb : 26; - mmr_t pri : 3; - mmr_t acc : 3; - mmr_t reserved_0 : 6; - } sh_md_dqrp_mmr_piowd_dir_entry_s; -} sh_md_dqrp_mmr_piowd_dir_entry_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_PIOWD_DIR_ECC" */ -/* directory ecc register */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_piowd_dir_ecc_u { - mmr_t sh_md_dqrp_mmr_piowd_dir_ecc_regval; - struct { - mmr_t ecca : 7; - mmr_t eccb : 7; - mmr_t reserved_0 : 50; - } sh_md_dqrp_mmr_piowd_dir_ecc_s; -} sh_md_dqrp_mmr_piowd_dir_ecc_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY" */ -/* x directory pio read data */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_xpiord_xdir_entry_u { - mmr_t sh_md_dqrp_mmr_xpiord_xdir_entry_regval; - struct { - mmr_t dira : 26; - mmr_t dirb : 26; - mmr_t pri : 3; - mmr_t acc : 3; - mmr_t cor : 1; - mmr_t unc : 1; - mmr_t reserved_0 : 4; - } sh_md_dqrp_mmr_xpiord_xdir_entry_s; -} sh_md_dqrp_mmr_xpiord_xdir_entry_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XPIORD_XDIR_ECC" */ -/* x directory ecc */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_xpiord_xdir_ecc_u { - mmr_t sh_md_dqrp_mmr_xpiord_xdir_ecc_regval; - struct { - mmr_t ecca : 7; - mmr_t eccb : 7; - mmr_t reserved_0 : 50; - } sh_md_dqrp_mmr_xpiord_xdir_ecc_s; -} sh_md_dqrp_mmr_xpiord_xdir_ecc_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY" */ -/* y directory pio read data */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_ypiord_ydir_entry_u { - mmr_t sh_md_dqrp_mmr_ypiord_ydir_entry_regval; - struct { - mmr_t dira : 26; - mmr_t dirb : 26; - mmr_t pri : 3; - mmr_t acc : 3; - mmr_t cor : 1; - mmr_t unc : 1; - mmr_t reserved_0 : 4; - } sh_md_dqrp_mmr_ypiord_ydir_entry_s; -} sh_md_dqrp_mmr_ypiord_ydir_entry_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YPIORD_YDIR_ECC" */ -/* y directory ecc */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_ypiord_ydir_ecc_u { - mmr_t sh_md_dqrp_mmr_ypiord_ydir_ecc_regval; - struct { - mmr_t ecca : 7; - mmr_t eccb : 7; - mmr_t reserved_0 : 50; - } sh_md_dqrp_mmr_ypiord_ydir_ecc_s; -} sh_md_dqrp_mmr_ypiord_ydir_ecc_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XCERR1" */ -/* correctable dir ecc group 1 error register */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_xcerr1_u { - mmr_t sh_md_dqrp_mmr_xcerr1_regval; - struct { - mmr_t grp1 : 36; - mmr_t val : 1; - mmr_t more : 1; - mmr_t arm : 1; - mmr_t reserved_0 : 25; - } sh_md_dqrp_mmr_xcerr1_s; -} sh_md_dqrp_mmr_xcerr1_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XCERR2" */ -/* correctable dir ecc group 2 error register */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_xcerr2_u { - mmr_t sh_md_dqrp_mmr_xcerr2_regval; - struct { - mmr_t grp2 : 36; - mmr_t val : 1; - mmr_t more : 1; - mmr_t reserved_0 : 26; - } sh_md_dqrp_mmr_xcerr2_s; -} sh_md_dqrp_mmr_xcerr2_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XUERR1" */ -/* uncorrectable dir ecc group 1 error register */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_xuerr1_u { - mmr_t sh_md_dqrp_mmr_xuerr1_regval; - struct { - mmr_t grp1 : 36; - mmr_t val : 1; - mmr_t more : 1; - mmr_t arm : 1; - mmr_t reserved_0 : 25; - } sh_md_dqrp_mmr_xuerr1_s; -} sh_md_dqrp_mmr_xuerr1_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XUERR2" */ -/* uncorrectable dir ecc group 2 error register */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_xuerr2_u { - mmr_t sh_md_dqrp_mmr_xuerr2_regval; - struct { - mmr_t grp2 : 36; - mmr_t val : 1; - mmr_t more : 1; - mmr_t reserved_0 : 26; - } sh_md_dqrp_mmr_xuerr2_s; -} sh_md_dqrp_mmr_xuerr2_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XPERR" */ -/* protocol error register */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_xperr_u { - mmr_t sh_md_dqrp_mmr_xperr_regval; - struct { - mmr_t dir : 26; - mmr_t cmd : 8; - mmr_t src : 14; - mmr_t prige : 1; - mmr_t priv : 1; - mmr_t cor : 1; - mmr_t unc : 1; - mmr_t mybit : 8; - mmr_t val : 1; - mmr_t more : 1; - mmr_t arm : 1; - mmr_t reserved_0 : 1; - } sh_md_dqrp_mmr_xperr_s; -} sh_md_dqrp_mmr_xperr_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YCERR1" */ -/* correctable dir ecc group 1 error register */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_ycerr1_u { - mmr_t sh_md_dqrp_mmr_ycerr1_regval; - struct { - mmr_t grp1 : 36; - mmr_t val : 1; - mmr_t more : 1; - mmr_t arm : 1; - mmr_t reserved_0 : 25; - } sh_md_dqrp_mmr_ycerr1_s; -} sh_md_dqrp_mmr_ycerr1_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YCERR2" */ -/* correctable dir ecc group 2 error register */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_ycerr2_u { - mmr_t sh_md_dqrp_mmr_ycerr2_regval; - struct { - mmr_t grp2 : 36; - mmr_t val : 1; - mmr_t more : 1; - mmr_t reserved_0 : 26; - } sh_md_dqrp_mmr_ycerr2_s; -} sh_md_dqrp_mmr_ycerr2_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YUERR1" */ -/* uncorrectable dir ecc group 1 error register */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_yuerr1_u { - mmr_t sh_md_dqrp_mmr_yuerr1_regval; - struct { - mmr_t grp1 : 36; - mmr_t val : 1; - mmr_t more : 1; - mmr_t arm : 1; - mmr_t reserved_0 : 25; - } sh_md_dqrp_mmr_yuerr1_s; -} sh_md_dqrp_mmr_yuerr1_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YUERR2" */ -/* uncorrectable dir ecc group 2 error register */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_yuerr2_u { - mmr_t sh_md_dqrp_mmr_yuerr2_regval; - struct { - mmr_t grp2 : 36; - mmr_t val : 1; - mmr_t more : 1; - mmr_t reserved_0 : 26; - } sh_md_dqrp_mmr_yuerr2_s; -} sh_md_dqrp_mmr_yuerr2_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YPERR" */ -/* protocol error register */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_yperr_u { - mmr_t sh_md_dqrp_mmr_yperr_regval; - struct { - mmr_t dir : 26; - mmr_t cmd : 8; - mmr_t src : 14; - mmr_t prige : 1; - mmr_t priv : 1; - mmr_t cor : 1; - mmr_t unc : 1; - mmr_t mybit : 8; - mmr_t val : 1; - mmr_t more : 1; - mmr_t arm : 1; - mmr_t reserved_0 : 1; - } sh_md_dqrp_mmr_yperr_s; -} sh_md_dqrp_mmr_yperr_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_CMDTRIG" */ -/* cmd triggers */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_dir_cmdtrig_u { - mmr_t sh_md_dqrp_mmr_dir_cmdtrig_regval; - struct { - mmr_t cmd0 : 8; - mmr_t cmd1 : 8; - mmr_t cmd2 : 8; - mmr_t cmd3 : 8; - mmr_t reserved_0 : 32; - } sh_md_dqrp_mmr_dir_cmdtrig_s; -} sh_md_dqrp_mmr_dir_cmdtrig_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_TBLTRIG" */ -/* dir table trigger */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_dir_tbltrig_u { - mmr_t sh_md_dqrp_mmr_dir_tbltrig_regval; - struct { - mmr_t src : 14; - mmr_t cmd : 8; - mmr_t acc : 2; - mmr_t prige : 1; - mmr_t dirst : 9; - mmr_t mybit : 8; - mmr_t reserved_0 : 22; - } sh_md_dqrp_mmr_dir_tbltrig_s; -} sh_md_dqrp_mmr_dir_tbltrig_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_TBLMASK" */ -/* dir table trigger mask */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_dir_tblmask_u { - mmr_t sh_md_dqrp_mmr_dir_tblmask_regval; - struct { - mmr_t src : 14; - mmr_t cmd : 8; - mmr_t acc : 2; - mmr_t prige : 1; - mmr_t dirst : 9; - mmr_t mybit : 8; - mmr_t reserved_0 : 22; - } sh_md_dqrp_mmr_dir_tblmask_s; -} sh_md_dqrp_mmr_dir_tblmask_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XBIST_H" */ -/* rising edge bist/fill pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_xbist_h_u { - mmr_t sh_md_dqrp_mmr_xbist_h_regval; - struct { - mmr_t pat : 32; - mmr_t reserved_0 : 8; - mmr_t inv : 1; - mmr_t rot : 1; - mmr_t arm : 1; - mmr_t reserved_1 : 21; - } sh_md_dqrp_mmr_xbist_h_s; -} sh_md_dqrp_mmr_xbist_h_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XBIST_L" */ -/* falling edge bist/fill pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_xbist_l_u { - mmr_t sh_md_dqrp_mmr_xbist_l_regval; - struct { - mmr_t pat : 32; - mmr_t reserved_0 : 8; - mmr_t inv : 1; - mmr_t rot : 1; - mmr_t reserved_1 : 22; - } sh_md_dqrp_mmr_xbist_l_s; -} sh_md_dqrp_mmr_xbist_l_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XBIST_ERR_H" */ -/* rising edge bist error pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_xbist_err_h_u { - mmr_t sh_md_dqrp_mmr_xbist_err_h_regval; - struct { - mmr_t pat : 32; - mmr_t reserved_0 : 8; - mmr_t val : 1; - mmr_t more : 1; - mmr_t reserved_1 : 22; - } sh_md_dqrp_mmr_xbist_err_h_s; -} sh_md_dqrp_mmr_xbist_err_h_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XBIST_ERR_L" */ -/* falling edge bist error pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_xbist_err_l_u { - mmr_t sh_md_dqrp_mmr_xbist_err_l_regval; - struct { - mmr_t pat : 32; - mmr_t reserved_0 : 8; - mmr_t val : 1; - mmr_t more : 1; - mmr_t reserved_1 : 22; - } sh_md_dqrp_mmr_xbist_err_l_s; -} sh_md_dqrp_mmr_xbist_err_l_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YBIST_H" */ -/* rising edge bist/fill pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_ybist_h_u { - mmr_t sh_md_dqrp_mmr_ybist_h_regval; - struct { - mmr_t pat : 32; - mmr_t reserved_0 : 8; - mmr_t inv : 1; - mmr_t rot : 1; - mmr_t arm : 1; - mmr_t reserved_1 : 21; - } sh_md_dqrp_mmr_ybist_h_s; -} sh_md_dqrp_mmr_ybist_h_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YBIST_L" */ -/* falling edge bist/fill pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_ybist_l_u { - mmr_t sh_md_dqrp_mmr_ybist_l_regval; - struct { - mmr_t pat : 32; - mmr_t reserved_0 : 8; - mmr_t inv : 1; - mmr_t rot : 1; - mmr_t reserved_1 : 22; - } sh_md_dqrp_mmr_ybist_l_s; -} sh_md_dqrp_mmr_ybist_l_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YBIST_ERR_H" */ -/* rising edge bist error pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_ybist_err_h_u { - mmr_t sh_md_dqrp_mmr_ybist_err_h_regval; - struct { - mmr_t pat : 32; - mmr_t reserved_0 : 8; - mmr_t val : 1; - mmr_t more : 1; - mmr_t reserved_1 : 22; - } sh_md_dqrp_mmr_ybist_err_h_s; -} sh_md_dqrp_mmr_ybist_err_h_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YBIST_ERR_L" */ -/* falling edge bist error pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqrp_mmr_ybist_err_l_u { - mmr_t sh_md_dqrp_mmr_ybist_err_l_regval; - struct { - mmr_t pat : 32; - mmr_t reserved_0 : 8; - mmr_t val : 1; - mmr_t more : 1; - mmr_t reserved_1 : 22; - } sh_md_dqrp_mmr_ybist_err_l_s; -} sh_md_dqrp_mmr_ybist_err_l_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRS_MMR_XBIST_H" */ -/* rising edge bist/fill pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqrs_mmr_xbist_h_u { - mmr_t sh_md_dqrs_mmr_xbist_h_regval; - struct { - mmr_t pat : 40; - mmr_t inv : 1; - mmr_t rot : 1; - mmr_t arm : 1; - mmr_t reserved_0 : 21; - } sh_md_dqrs_mmr_xbist_h_s; -} sh_md_dqrs_mmr_xbist_h_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRS_MMR_XBIST_L" */ -/* falling edge bist/fill pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqrs_mmr_xbist_l_u { - mmr_t sh_md_dqrs_mmr_xbist_l_regval; - struct { - mmr_t pat : 40; - mmr_t inv : 1; - mmr_t rot : 1; - mmr_t reserved_0 : 22; - } sh_md_dqrs_mmr_xbist_l_s; -} sh_md_dqrs_mmr_xbist_l_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRS_MMR_XBIST_ERR_H" */ -/* rising edge bist error pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqrs_mmr_xbist_err_h_u { - mmr_t sh_md_dqrs_mmr_xbist_err_h_regval; - struct { - mmr_t pat : 40; - mmr_t val : 1; - mmr_t more : 1; - mmr_t reserved_0 : 22; - } sh_md_dqrs_mmr_xbist_err_h_s; -} sh_md_dqrs_mmr_xbist_err_h_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRS_MMR_XBIST_ERR_L" */ -/* falling edge bist error pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqrs_mmr_xbist_err_l_u { - mmr_t sh_md_dqrs_mmr_xbist_err_l_regval; - struct { - mmr_t pat : 40; - mmr_t val : 1; - mmr_t more : 1; - mmr_t reserved_0 : 22; - } sh_md_dqrs_mmr_xbist_err_l_s; -} sh_md_dqrs_mmr_xbist_err_l_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRS_MMR_YBIST_H" */ -/* rising edge bist/fill pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqrs_mmr_ybist_h_u { - mmr_t sh_md_dqrs_mmr_ybist_h_regval; - struct { - mmr_t pat : 40; - mmr_t inv : 1; - mmr_t rot : 1; - mmr_t arm : 1; - mmr_t reserved_0 : 21; - } sh_md_dqrs_mmr_ybist_h_s; -} sh_md_dqrs_mmr_ybist_h_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRS_MMR_YBIST_L" */ -/* falling edge bist/fill pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqrs_mmr_ybist_l_u { - mmr_t sh_md_dqrs_mmr_ybist_l_regval; - struct { - mmr_t pat : 40; - mmr_t inv : 1; - mmr_t rot : 1; - mmr_t reserved_0 : 22; - } sh_md_dqrs_mmr_ybist_l_s; -} sh_md_dqrs_mmr_ybist_l_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRS_MMR_YBIST_ERR_H" */ -/* rising edge bist error pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqrs_mmr_ybist_err_h_u { - mmr_t sh_md_dqrs_mmr_ybist_err_h_regval; - struct { - mmr_t pat : 40; - mmr_t val : 1; - mmr_t more : 1; - mmr_t reserved_0 : 22; - } sh_md_dqrs_mmr_ybist_err_h_s; -} sh_md_dqrs_mmr_ybist_err_h_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRS_MMR_YBIST_ERR_L" */ -/* falling edge bist error pattern */ -/* ==================================================================== */ - -typedef union sh_md_dqrs_mmr_ybist_err_l_u { - mmr_t sh_md_dqrs_mmr_ybist_err_l_regval; - struct { - mmr_t pat : 40; - mmr_t val : 1; - mmr_t more : 1; - mmr_t reserved_0 : 22; - } sh_md_dqrs_mmr_ybist_err_l_s; -} sh_md_dqrs_mmr_ybist_err_l_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRS_MMR_JNR_DEBUG" */ -/* joiner/fct debug configuration */ -/* ==================================================================== */ - -typedef union sh_md_dqrs_mmr_jnr_debug_u { - mmr_t sh_md_dqrs_mmr_jnr_debug_regval; - struct { - mmr_t px : 1; - mmr_t rw : 1; - mmr_t reserved_0 : 62; - } sh_md_dqrs_mmr_jnr_debug_s; -} sh_md_dqrs_mmr_jnr_debug_u_t; - -/* ==================================================================== */ -/* Register "SH_MD_DQRS_MMR_YAMOPW_ERR" */ -/* amo/partial rmw ecc error register */ -/* ==================================================================== */ - -typedef union sh_md_dqrs_mmr_yamopw_err_u { - mmr_t sh_md_dqrs_mmr_yamopw_err_regval; - struct { - mmr_t ssyn : 8; - mmr_t scor : 1; - mmr_t sunc : 1; - mmr_t reserved_0 : 6; - mmr_t rsyn : 8; - mmr_t rcor : 1; - mmr_t runc : 1; - mmr_t reserved_1 : 6; - mmr_t arm : 1; - mmr_t reserved_2 : 31; - } sh_md_dqrs_mmr_yamopw_err_s; -} sh_md_dqrs_mmr_yamopw_err_u_t; - -#endif /* _ASM_IA64_SN_SN2_SHUB_MMR_T_H */ diff --git a/include/asm-ia64/sn/sn2/shubio.h b/include/asm-ia64/sn/sn2/shubio.h deleted file mode 100644 index e984c5718848..000000000000 --- a/include/asm-ia64/sn/sn2/shubio.h +++ /dev/null @@ -1,3609 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. - */ - -#ifndef _ASM_IA64_SN_SN2_SHUBIO_H -#define _ASM_IA64_SN_SN2_SHUBIO_H - -#include <asm/sn/arch.h> - -#define HUB_WIDGET_ID_MAX 0xf -#define IIO_NUM_ITTES 7 -#define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1) - -#define IIO_WID 0x00400000 /* Crosstalk Widget Identification */ - /* This register is also accessible from - * Crosstalk at address 0x0. */ -#define IIO_WSTAT 0x00400008 /* Crosstalk Widget Status */ -#define IIO_WCR 0x00400020 /* Crosstalk Widget Control Register */ -#define IIO_ILAPR 0x00400100 /* IO Local Access Protection Register */ -#define IIO_ILAPO 0x00400108 /* IO Local Access Protection Override */ -#define IIO_IOWA 0x00400110 /* IO Outbound Widget Access */ -#define IIO_IIWA 0x00400118 /* IO Inbound Widget Access */ -#define IIO_IIDEM 0x00400120 /* IO Inbound Device Error Mask */ -#define IIO_ILCSR 0x00400128 /* IO LLP Control and Status Register */ -#define IIO_ILLR 0x00400130 /* IO LLP Log Register */ -#define IIO_IIDSR 0x00400138 /* IO Interrupt Destination */ - -#define IIO_IGFX0 0x00400140 /* IO Graphics Node-Widget Map 0 */ -#define IIO_IGFX1 0x00400148 /* IO Graphics Node-Widget Map 1 */ - -#define IIO_ISCR0 0x00400150 /* IO Scratch Register 0 */ -#define IIO_ISCR1 0x00400158 /* IO Scratch Register 1 */ - -#define IIO_ITTE1 0x00400160 /* IO Translation Table Entry 1 */ -#define IIO_ITTE2 0x00400168 /* IO Translation Table Entry 2 */ -#define IIO_ITTE3 0x00400170 /* IO Translation Table Entry 3 */ -#define IIO_ITTE4 0x00400178 /* IO Translation Table Entry 4 */ -#define IIO_ITTE5 0x00400180 /* IO Translation Table Entry 5 */ -#define IIO_ITTE6 0x00400188 /* IO Translation Table Entry 6 */ -#define IIO_ITTE7 0x00400190 /* IO Translation Table Entry 7 */ - -#define IIO_IPRB0 0x00400198 /* IO PRB Entry 0 */ -#define IIO_IPRB8 0x004001A0 /* IO PRB Entry 8 */ -#define IIO_IPRB9 0x004001A8 /* IO PRB Entry 9 */ -#define IIO_IPRBA 0x004001B0 /* IO PRB Entry A */ -#define IIO_IPRBB 0x004001B8 /* IO PRB Entry B */ -#define IIO_IPRBC 0x004001C0 /* IO PRB Entry C */ -#define IIO_IPRBD 0x004001C8 /* IO PRB Entry D */ -#define IIO_IPRBE 0x004001D0 /* IO PRB Entry E */ -#define IIO_IPRBF 0x004001D8 /* IO PRB Entry F */ - -#define IIO_IXCC 0x004001E0 /* IO Crosstalk Credit Count Timeout */ -#define IIO_IMEM 0x004001E8 /* IO Miscellaneous Error Mask */ -#define IIO_IXTT 0x004001F0 /* IO Crosstalk Timeout Threshold */ -#define IIO_IECLR 0x004001F8 /* IO Error Clear Register */ -#define IIO_IBCR 0x00400200 /* IO BTE Control Register */ - -#define IIO_IXSM 0x00400208 /* IO Crosstalk Spurious Message */ -#define IIO_IXSS 0x00400210 /* IO Crosstalk Spurious Sideband */ - -#define IIO_ILCT 0x00400218 /* IO LLP Channel Test */ - -#define IIO_IIEPH1 0x00400220 /* IO Incoming Error Packet Header, Part 1 */ -#define IIO_IIEPH2 0x00400228 /* IO Incoming Error Packet Header, Part 2 */ - - -#define IIO_ISLAPR 0x00400230 /* IO SXB Local Access Protection Regster */ -#define IIO_ISLAPO 0x00400238 /* IO SXB Local Access Protection Override */ - -#define IIO_IWI 0x00400240 /* IO Wrapper Interrupt Register */ -#define IIO_IWEL 0x00400248 /* IO Wrapper Error Log Register */ -#define IIO_IWC 0x00400250 /* IO Wrapper Control Register */ -#define IIO_IWS 0x00400258 /* IO Wrapper Status Register */ -#define IIO_IWEIM 0x00400260 /* IO Wrapper Error Interrupt Masking Register */ - -#define IIO_IPCA 0x00400300 /* IO PRB Counter Adjust */ - -#define IIO_IPRTE0_A 0x00400308 /* IO PIO Read Address Table Entry 0, Part A */ -#define IIO_IPRTE1_A 0x00400310 /* IO PIO Read Address Table Entry 1, Part A */ -#define IIO_IPRTE2_A 0x00400318 /* IO PIO Read Address Table Entry 2, Part A */ -#define IIO_IPRTE3_A 0x00400320 /* IO PIO Read Address Table Entry 3, Part A */ -#define IIO_IPRTE4_A 0x00400328 /* IO PIO Read Address Table Entry 4, Part A */ -#define IIO_IPRTE5_A 0x00400330 /* IO PIO Read Address Table Entry 5, Part A */ -#define IIO_IPRTE6_A 0x00400338 /* IO PIO Read Address Table Entry 6, Part A */ -#define IIO_IPRTE7_A 0x00400340 /* IO PIO Read Address Table Entry 7, Part A */ - -#define IIO_IPRTE0_B 0x00400348 /* IO PIO Read Address Table Entry 0, Part B */ -#define IIO_IPRTE1_B 0x00400350 /* IO PIO Read Address Table Entry 1, Part B */ -#define IIO_IPRTE2_B 0x00400358 /* IO PIO Read Address Table Entry 2, Part B */ -#define IIO_IPRTE3_B 0x00400360 /* IO PIO Read Address Table Entry 3, Part B */ -#define IIO_IPRTE4_B 0x00400368 /* IO PIO Read Address Table Entry 4, Part B */ -#define IIO_IPRTE5_B 0x00400370 /* IO PIO Read Address Table Entry 5, Part B */ -#define IIO_IPRTE6_B 0x00400378 /* IO PIO Read Address Table Entry 6, Part B */ -#define IIO_IPRTE7_B 0x00400380 /* IO PIO Read Address Table Entry 7, Part B */ - -#define IIO_IPDR 0x00400388 /* IO PIO Deallocation Register */ -#define IIO_ICDR 0x00400390 /* IO CRB Entry Deallocation Register */ -#define IIO_IFDR 0x00400398 /* IO IOQ FIFO Depth Register */ -#define IIO_IIAP 0x004003A0 /* IO IIQ Arbitration Parameters */ -#define IIO_ICMR 0x004003A8 /* IO CRB Management Register */ -#define IIO_ICCR 0x004003B0 /* IO CRB Control Register */ -#define IIO_ICTO 0x004003B8 /* IO CRB Timeout */ -#define IIO_ICTP 0x004003C0 /* IO CRB Timeout Prescalar */ - -#define IIO_ICRB0_A 0x00400400 /* IO CRB Entry 0_A */ -#define IIO_ICRB0_B 0x00400408 /* IO CRB Entry 0_B */ -#define IIO_ICRB0_C 0x00400410 /* IO CRB Entry 0_C */ -#define IIO_ICRB0_D 0x00400418 /* IO CRB Entry 0_D */ -#define IIO_ICRB0_E 0x00400420 /* IO CRB Entry 0_E */ - -#define IIO_ICRB1_A 0x00400430 /* IO CRB Entry 1_A */ -#define IIO_ICRB1_B 0x00400438 /* IO CRB Entry 1_B */ -#define IIO_ICRB1_C 0x00400440 /* IO CRB Entry 1_C */ -#define IIO_ICRB1_D 0x00400448 /* IO CRB Entry 1_D */ -#define IIO_ICRB1_E 0x00400450 /* IO CRB Entry 1_E */ - -#define IIO_ICRB2_A 0x00400460 /* IO CRB Entry 2_A */ -#define IIO_ICRB2_B 0x00400468 /* IO CRB Entry 2_B */ -#define IIO_ICRB2_C 0x00400470 /* IO CRB Entry 2_C */ -#define IIO_ICRB2_D 0x00400478 /* IO CRB Entry 2_D */ -#define IIO_ICRB2_E 0x00400480 /* IO CRB Entry 2_E */ - -#define IIO_ICRB3_A 0x00400490 /* IO CRB Entry 3_A */ -#define IIO_ICRB3_B 0x00400498 /* IO CRB Entry 3_B */ -#define IIO_ICRB3_C 0x004004a0 /* IO CRB Entry 3_C */ -#define IIO_ICRB3_D 0x004004a8 /* IO CRB Entry 3_D */ -#define IIO_ICRB3_E 0x004004b0 /* IO CRB Entry 3_E */ - -#define IIO_ICRB4_A 0x004004c0 /* IO CRB Entry 4_A */ -#define IIO_ICRB4_B 0x004004c8 /* IO CRB Entry 4_B */ -#define IIO_ICRB4_C 0x004004d0 /* IO CRB Entry 4_C */ -#define IIO_ICRB4_D 0x004004d8 /* IO CRB Entry 4_D */ -#define IIO_ICRB4_E 0x004004e0 /* IO CRB Entry 4_E */ - -#define IIO_ICRB5_A 0x004004f0 /* IO CRB Entry 5_A */ -#define IIO_ICRB5_B 0x004004f8 /* IO CRB Entry 5_B */ -#define IIO_ICRB5_C 0x00400500 /* IO CRB Entry 5_C */ -#define IIO_ICRB5_D 0x00400508 /* IO CRB Entry 5_D */ -#define IIO_ICRB5_E 0x00400510 /* IO CRB Entry 5_E */ - -#define IIO_ICRB6_A 0x00400520 /* IO CRB Entry 6_A */ -#define IIO_ICRB6_B 0x00400528 /* IO CRB Entry 6_B */ -#define IIO_ICRB6_C 0x00400530 /* IO CRB Entry 6_C */ -#define IIO_ICRB6_D 0x00400538 /* IO CRB Entry 6_D */ -#define IIO_ICRB6_E 0x00400540 /* IO CRB Entry 6_E */ - -#define IIO_ICRB7_A 0x00400550 /* IO CRB Entry 7_A */ -#define IIO_ICRB7_B 0x00400558 /* IO CRB Entry 7_B */ -#define IIO_ICRB7_C 0x00400560 /* IO CRB Entry 7_C */ -#define IIO_ICRB7_D 0x00400568 /* IO CRB Entry 7_D */ -#define IIO_ICRB7_E 0x00400570 /* IO CRB Entry 7_E */ - -#define IIO_ICRB8_A 0x00400580 /* IO CRB Entry 8_A */ -#define IIO_ICRB8_B 0x00400588 /* IO CRB Entry 8_B */ -#define IIO_ICRB8_C 0x00400590 /* IO CRB Entry 8_C */ -#define IIO_ICRB8_D 0x00400598 /* IO CRB Entry 8_D */ -#define IIO_ICRB8_E 0x004005a0 /* IO CRB Entry 8_E */ - -#define IIO_ICRB9_A 0x004005b0 /* IO CRB Entry 9_A */ -#define IIO_ICRB9_B 0x004005b8 /* IO CRB Entry 9_B */ -#define IIO_ICRB9_C 0x004005c0 /* IO CRB Entry 9_C */ -#define IIO_ICRB9_D 0x004005c8 /* IO CRB Entry 9_D */ -#define IIO_ICRB9_E 0x004005d0 /* IO CRB Entry 9_E */ - -#define IIO_ICRBA_A 0x004005e0 /* IO CRB Entry A_A */ -#define IIO_ICRBA_B 0x004005e8 /* IO CRB Entry A_B */ -#define IIO_ICRBA_C 0x004005f0 /* IO CRB Entry A_C */ -#define IIO_ICRBA_D 0x004005f8 /* IO CRB Entry A_D */ -#define IIO_ICRBA_E 0x00400600 /* IO CRB Entry A_E */ - -#define IIO_ICRBB_A 0x00400610 /* IO CRB Entry B_A */ -#define IIO_ICRBB_B 0x00400618 /* IO CRB Entry B_B */ -#define IIO_ICRBB_C 0x00400620 /* IO CRB Entry B_C */ -#define IIO_ICRBB_D 0x00400628 /* IO CRB Entry B_D */ -#define IIO_ICRBB_E 0x00400630 /* IO CRB Entry B_E */ - -#define IIO_ICRBC_A 0x00400640 /* IO CRB Entry C_A */ -#define IIO_ICRBC_B 0x00400648 /* IO CRB Entry C_B */ -#define IIO_ICRBC_C 0x00400650 /* IO CRB Entry C_C */ -#define IIO_ICRBC_D 0x00400658 /* IO CRB Entry C_D */ -#define IIO_ICRBC_E 0x00400660 /* IO CRB Entry C_E */ - -#define IIO_ICRBD_A 0x00400670 /* IO CRB Entry D_A */ -#define IIO_ICRBD_B 0x00400678 /* IO CRB Entry D_B */ -#define IIO_ICRBD_C 0x00400680 /* IO CRB Entry D_C */ -#define IIO_ICRBD_D 0x00400688 /* IO CRB Entry D_D */ -#define IIO_ICRBD_E 0x00400690 /* IO CRB Entry D_E */ - -#define IIO_ICRBE_A 0x004006a0 /* IO CRB Entry E_A */ -#define IIO_ICRBE_B 0x004006a8 /* IO CRB Entry E_B */ -#define IIO_ICRBE_C 0x004006b0 /* IO CRB Entry E_C */ -#define IIO_ICRBE_D 0x004006b8 /* IO CRB Entry E_D */ -#define IIO_ICRBE_E 0x004006c0 /* IO CRB Entry E_E */ - -#define IIO_ICSML 0x00400700 /* IO CRB Spurious Message Low */ -#define IIO_ICSMM 0x00400708 /* IO CRB Spurious Message Middle */ -#define IIO_ICSMH 0x00400710 /* IO CRB Spurious Message High */ - -#define IIO_IDBSS 0x00400718 /* IO Debug Submenu Select */ - -#define IIO_IBLS0 0x00410000 /* IO BTE Length Status 0 */ -#define IIO_IBSA0 0x00410008 /* IO BTE Source Address 0 */ -#define IIO_IBDA0 0x00410010 /* IO BTE Destination Address 0 */ -#define IIO_IBCT0 0x00410018 /* IO BTE Control Terminate 0 */ -#define IIO_IBNA0 0x00410020 /* IO BTE Notification Address 0 */ -#define IIO_IBIA0 0x00410028 /* IO BTE Interrupt Address 0 */ -#define IIO_IBLS1 0x00420000 /* IO BTE Length Status 1 */ -#define IIO_IBSA1 0x00420008 /* IO BTE Source Address 1 */ -#define IIO_IBDA1 0x00420010 /* IO BTE Destination Address 1 */ -#define IIO_IBCT1 0x00420018 /* IO BTE Control Terminate 1 */ -#define IIO_IBNA1 0x00420020 /* IO BTE Notification Address 1 */ -#define IIO_IBIA1 0x00420028 /* IO BTE Interrupt Address 1 */ - -#define IIO_IPCR 0x00430000 /* IO Performance Control */ -#define IIO_IPPR 0x00430008 /* IO Performance Profiling */ - - -/************************************************************************ - * * - * Description: This register echoes some information from the * - * LB_REV_ID register. It is available through Crosstalk as described * - * above. The REV_NUM and MFG_NUM fields receive their values from * - * the REVISION and MANUFACTURER fields in the LB_REV_ID register. * - * The PART_NUM field's value is the Crosstalk device ID number that * - * Steve Miller assigned to the SHub chip. * - * * - ************************************************************************/ - -typedef union ii_wid_u { - shubreg_t ii_wid_regval; - struct { - shubreg_t w_rsvd_1 : 1; - shubreg_t w_mfg_num : 11; - shubreg_t w_part_num : 16; - shubreg_t w_rev_num : 4; - shubreg_t w_rsvd : 32; - } ii_wid_fld_s; -} ii_wid_u_t; - - -/************************************************************************ - * * - * The fields in this register are set upon detection of an error * - * and cleared by various mechanisms, as explained in the * - * description. * - * * - ************************************************************************/ - -typedef union ii_wstat_u { - shubreg_t ii_wstat_regval; - struct { - shubreg_t w_pending : 4; - shubreg_t w_xt_crd_to : 1; - shubreg_t w_xt_tail_to : 1; - shubreg_t w_rsvd_3 : 3; - shubreg_t w_tx_mx_rty : 1; - shubreg_t w_rsvd_2 : 6; - shubreg_t w_llp_tx_cnt : 8; - shubreg_t w_rsvd_1 : 8; - shubreg_t w_crazy : 1; - shubreg_t w_rsvd : 31; - } ii_wstat_fld_s; -} ii_wstat_u_t; - - -/************************************************************************ - * * - * Description: This is a read-write enabled register. It controls * - * various aspects of the Crosstalk flow control. * - * * - ************************************************************************/ - -typedef union ii_wcr_u { - shubreg_t ii_wcr_regval; - struct { - shubreg_t w_wid : 4; - shubreg_t w_tag : 1; - shubreg_t w_rsvd_1 : 8; - shubreg_t w_dst_crd : 3; - shubreg_t w_f_bad_pkt : 1; - shubreg_t w_dir_con : 1; - shubreg_t w_e_thresh : 5; - shubreg_t w_rsvd : 41; - } ii_wcr_fld_s; -} ii_wcr_u_t; - - -/************************************************************************ - * * - * Description: This register's value is a bit vector that guards * - * access to local registers within the II as well as to external * - * Crosstalk widgets. Each bit in the register corresponds to a * - * particular region in the system; a region consists of one, two or * - * four nodes (depending on the value of the REGION_SIZE field in the * - * LB_REV_ID register, which is documented in Section 8.3.1.1). The * - * protection provided by this register applies to PIO read * - * operations as well as PIO write operations. The II will perform a * - * PIO read or write request only if the bit for the requestor's * - * region is set; otherwise, the II will not perform the requested * - * operation and will return an error response. When a PIO read or * - * write request targets an external Crosstalk widget, then not only * - * must the bit for the requestor's region be set in the ILAPR, but * - * also the target widget's bit in the IOWA register must be set in * - * order for the II to perform the requested operation; otherwise, * - * the II will return an error response. Hence, the protection * - * provided by the IOWA register supplements the protection provided * - * by the ILAPR for requests that target external Crosstalk widgets. * - * This register itself can be accessed only by the nodes whose * - * region ID bits are enabled in this same register. It can also be * - * accessed through the IAlias space by the local processors. * - * The reset value of this register allows access by all nodes. * - * * - ************************************************************************/ - -typedef union ii_ilapr_u { - shubreg_t ii_ilapr_regval; - struct { - shubreg_t i_region : 64; - } ii_ilapr_fld_s; -} ii_ilapr_u_t; - - - - -/************************************************************************ - * * - * Description: A write to this register of the 64-bit value * - * "SGIrules" in ASCII, will cause the bit in the ILAPR register * - * corresponding to the region of the requestor to be set (allow * - * access). A write of any other value will be ignored. Access * - * protection for this register is "SGIrules". * - * This register can also be accessed through the IAlias space. * - * However, this access will not change the access permissions in the * - * ILAPR. * - * * - ************************************************************************/ - -typedef union ii_ilapo_u { - shubreg_t ii_ilapo_regval; - struct { - shubreg_t i_io_ovrride : 64; - } ii_ilapo_fld_s; -} ii_ilapo_u_t; - - - -/************************************************************************ - * * - * This register qualifies all the PIO and Graphics writes launched * - * from the SHUB towards a widget. * - * * - ************************************************************************/ - -typedef union ii_iowa_u { - shubreg_t ii_iowa_regval; - struct { - shubreg_t i_w0_oac : 1; - shubreg_t i_rsvd_1 : 7; - shubreg_t i_wx_oac : 8; - shubreg_t i_rsvd : 48; - } ii_iowa_fld_s; -} ii_iowa_u_t; - - -/************************************************************************ - * * - * Description: This register qualifies all the requests launched * - * from a widget towards the Shub. This register is intended to be * - * used by software in case of misbehaving widgets. * - * * - * * - ************************************************************************/ - -typedef union ii_iiwa_u { - shubreg_t ii_iiwa_regval; - struct { - shubreg_t i_w0_iac : 1; - shubreg_t i_rsvd_1 : 7; - shubreg_t i_wx_iac : 8; - shubreg_t i_rsvd : 48; - } ii_iiwa_fld_s; -} ii_iiwa_u_t; - - - -/************************************************************************ - * * - * Description: This register qualifies all the operations launched * - * from a widget towards the SHub. It allows individual access * - * control for up to 8 devices per widget. A device refers to * - * individual DMA master hosted by a widget. * - * The bits in each field of this register are cleared by the Shub * - * upon detection of an error which requires the device to be * - * disabled. These fields assume that 0=TNUM=7 (i.e., Bridge-centric * - * Crosstalk). Whether or not a device has access rights to this * - * Shub is determined by an AND of the device enable bit in the * - * appropriate field of this register and the corresponding bit in * - * the Wx_IAC field (for the widget which this device belongs to). * - * The bits in this field are set by writing a 1 to them. Incoming * - * replies from Crosstalk are not subject to this access control * - * mechanism. * - * * - ************************************************************************/ - -typedef union ii_iidem_u { - shubreg_t ii_iidem_regval; - struct { - shubreg_t i_w8_dxs : 8; - shubreg_t i_w9_dxs : 8; - shubreg_t i_wa_dxs : 8; - shubreg_t i_wb_dxs : 8; - shubreg_t i_wc_dxs : 8; - shubreg_t i_wd_dxs : 8; - shubreg_t i_we_dxs : 8; - shubreg_t i_wf_dxs : 8; - } ii_iidem_fld_s; -} ii_iidem_u_t; - - -/************************************************************************ - * * - * This register contains the various programmable fields necessary * - * for controlling and observing the LLP signals. * - * * - ************************************************************************/ - -typedef union ii_ilcsr_u { - shubreg_t ii_ilcsr_regval; - struct { - shubreg_t i_nullto : 6; - shubreg_t i_rsvd_4 : 2; - shubreg_t i_wrmrst : 1; - shubreg_t i_rsvd_3 : 1; - shubreg_t i_llp_en : 1; - shubreg_t i_bm8 : 1; - shubreg_t i_llp_stat : 2; - shubreg_t i_remote_power : 1; - shubreg_t i_rsvd_2 : 1; - shubreg_t i_maxrtry : 10; - shubreg_t i_d_avail_sel : 2; - shubreg_t i_rsvd_1 : 4; - shubreg_t i_maxbrst : 10; - shubreg_t i_rsvd : 22; - - } ii_ilcsr_fld_s; -} ii_ilcsr_u_t; - - -/************************************************************************ - * * - * This is simply a status registers that monitors the LLP error * - * rate. * - * * - ************************************************************************/ - -typedef union ii_illr_u { - shubreg_t ii_illr_regval; - struct { - shubreg_t i_sn_cnt : 16; - shubreg_t i_cb_cnt : 16; - shubreg_t i_rsvd : 32; - } ii_illr_fld_s; -} ii_illr_u_t; - - -/************************************************************************ - * * - * Description: All II-detected non-BTE error interrupts are * - * specified via this register. * - * NOTE: The PI interrupt register address is hardcoded in the II. If * - * PI_ID==0, then the II sends an interrupt request (Duplonet PWRI * - * packet) to address offset 0x0180_0090 within the local register * - * address space of PI0 on the node specified by the NODE field. If * - * PI_ID==1, then the II sends the interrupt request to address * - * offset 0x01A0_0090 within the local register address space of PI1 * - * on the node specified by the NODE field. * - * * - ************************************************************************/ - -typedef union ii_iidsr_u { - shubreg_t ii_iidsr_regval; - struct { - shubreg_t i_level : 8; - shubreg_t i_pi_id : 1; - shubreg_t i_node : 11; - shubreg_t i_rsvd_3 : 4; - shubreg_t i_enable : 1; - shubreg_t i_rsvd_2 : 3; - shubreg_t i_int_sent : 2; - shubreg_t i_rsvd_1 : 2; - shubreg_t i_pi0_forward_int : 1; - shubreg_t i_pi1_forward_int : 1; - shubreg_t i_rsvd : 30; - } ii_iidsr_fld_s; -} ii_iidsr_u_t; - - - -/************************************************************************ - * * - * There are two instances of this register. This register is used * - * for matching up the incoming responses from the graphics widget to * - * the processor that initiated the graphics operation. The * - * write-responses are converted to graphics credits and returned to * - * the processor so that the processor interface can manage the flow * - * control. * - * * - ************************************************************************/ - -typedef union ii_igfx0_u { - shubreg_t ii_igfx0_regval; - struct { - shubreg_t i_w_num : 4; - shubreg_t i_pi_id : 1; - shubreg_t i_n_num : 12; - shubreg_t i_p_num : 1; - shubreg_t i_rsvd : 46; - } ii_igfx0_fld_s; -} ii_igfx0_u_t; - - -/************************************************************************ - * * - * There are two instances of this register. This register is used * - * for matching up the incoming responses from the graphics widget to * - * the processor that initiated the graphics operation. The * - * write-responses are converted to graphics credits and returned to * - * the processor so that the processor interface can manage the flow * - * control. * - * * - ************************************************************************/ - -typedef union ii_igfx1_u { - shubreg_t ii_igfx1_regval; - struct { - shubreg_t i_w_num : 4; - shubreg_t i_pi_id : 1; - shubreg_t i_n_num : 12; - shubreg_t i_p_num : 1; - shubreg_t i_rsvd : 46; - } ii_igfx1_fld_s; -} ii_igfx1_u_t; - - -/************************************************************************ - * * - * There are two instances of this registers. These registers are * - * used as scratch registers for software use. * - * * - ************************************************************************/ - -typedef union ii_iscr0_u { - shubreg_t ii_iscr0_regval; - struct { - shubreg_t i_scratch : 64; - } ii_iscr0_fld_s; -} ii_iscr0_u_t; - - - -/************************************************************************ - * * - * There are two instances of this registers. These registers are * - * used as scratch registers for software use. * - * * - ************************************************************************/ - -typedef union ii_iscr1_u { - shubreg_t ii_iscr1_regval; - struct { - shubreg_t i_scratch : 64; - } ii_iscr1_fld_s; -} ii_iscr1_u_t; - - -/************************************************************************ - * * - * Description: There are seven instances of translation table entry * - * registers. Each register maps a Shub Big Window to a 48-bit * - * address on Crosstalk. * - * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * - * number) are used to select one of these 7 registers. The Widget * - * number field is then derived from the W_NUM field for synthesizing * - * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * - * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * - * are padded with zeros. Although the maximum Crosstalk space * - * addressable by the SHub is thus the lower 16 GBytes per widget * - * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * - * space can be accessed. * - * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * - * Window number) are used to select one of these 7 registers. The * - * Widget number field is then derived from the W_NUM field for * - * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * - * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * - * field is used as Crosstalk[47], and remainder of the Crosstalk * - * address bits (Crosstalk[46:34]) are always zero. While the maximum * - * Crosstalk space addressable by the Shub is thus the lower * - * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * - * of this space can be accessed. * - * * - ************************************************************************/ - -typedef union ii_itte1_u { - shubreg_t ii_itte1_regval; - struct { - shubreg_t i_offset : 5; - shubreg_t i_rsvd_1 : 3; - shubreg_t i_w_num : 4; - shubreg_t i_iosp : 1; - shubreg_t i_rsvd : 51; - } ii_itte1_fld_s; -} ii_itte1_u_t; - - -/************************************************************************ - * * - * Description: There are seven instances of translation table entry * - * registers. Each register maps a Shub Big Window to a 48-bit * - * address on Crosstalk. * - * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * - * number) are used to select one of these 7 registers. The Widget * - * number field is then derived from the W_NUM field for synthesizing * - * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * - * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * - * are padded with zeros. Although the maximum Crosstalk space * - * addressable by the Shub is thus the lower 16 GBytes per widget * - * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * - * space can be accessed. * - * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * - * Window number) are used to select one of these 7 registers. The * - * Widget number field is then derived from the W_NUM field for * - * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * - * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * - * field is used as Crosstalk[47], and remainder of the Crosstalk * - * address bits (Crosstalk[46:34]) are always zero. While the maximum * - * Crosstalk space addressable by the Shub is thus the lower * - * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * - * of this space can be accessed. * - * * - ************************************************************************/ - -typedef union ii_itte2_u { - shubreg_t ii_itte2_regval; - struct { - shubreg_t i_offset : 5; - shubreg_t i_rsvd_1 : 3; - shubreg_t i_w_num : 4; - shubreg_t i_iosp : 1; - shubreg_t i_rsvd : 51; - } ii_itte2_fld_s; -} ii_itte2_u_t; - - -/************************************************************************ - * * - * Description: There are seven instances of translation table entry * - * registers. Each register maps a Shub Big Window to a 48-bit * - * address on Crosstalk. * - * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * - * number) are used to select one of these 7 registers. The Widget * - * number field is then derived from the W_NUM field for synthesizing * - * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * - * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * - * are padded with zeros. Although the maximum Crosstalk space * - * addressable by the Shub is thus the lower 16 GBytes per widget * - * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * - * space can be accessed. * - * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * - * Window number) are used to select one of these 7 registers. The * - * Widget number field is then derived from the W_NUM field for * - * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * - * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * - * field is used as Crosstalk[47], and remainder of the Crosstalk * - * address bits (Crosstalk[46:34]) are always zero. While the maximum * - * Crosstalk space addressable by the SHub is thus the lower * - * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * - * of this space can be accessed. * - * * - ************************************************************************/ - -typedef union ii_itte3_u { - shubreg_t ii_itte3_regval; - struct { - shubreg_t i_offset : 5; - shubreg_t i_rsvd_1 : 3; - shubreg_t i_w_num : 4; - shubreg_t i_iosp : 1; - shubreg_t i_rsvd : 51; - } ii_itte3_fld_s; -} ii_itte3_u_t; - - -/************************************************************************ - * * - * Description: There are seven instances of translation table entry * - * registers. Each register maps a SHub Big Window to a 48-bit * - * address on Crosstalk. * - * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * - * number) are used to select one of these 7 registers. The Widget * - * number field is then derived from the W_NUM field for synthesizing * - * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * - * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * - * are padded with zeros. Although the maximum Crosstalk space * - * addressable by the SHub is thus the lower 16 GBytes per widget * - * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * - * space can be accessed. * - * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * - * Window number) are used to select one of these 7 registers. The * - * Widget number field is then derived from the W_NUM field for * - * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * - * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * - * field is used as Crosstalk[47], and remainder of the Crosstalk * - * address bits (Crosstalk[46:34]) are always zero. While the maximum * - * Crosstalk space addressable by the SHub is thus the lower * - * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * - * of this space can be accessed. * - * * - ************************************************************************/ - -typedef union ii_itte4_u { - shubreg_t ii_itte4_regval; - struct { - shubreg_t i_offset : 5; - shubreg_t i_rsvd_1 : 3; - shubreg_t i_w_num : 4; - shubreg_t i_iosp : 1; - shubreg_t i_rsvd : 51; - } ii_itte4_fld_s; -} ii_itte4_u_t; - - -/************************************************************************ - * * - * Description: There are seven instances of translation table entry * - * registers. Each register maps a SHub Big Window to a 48-bit * - * address on Crosstalk. * - * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * - * number) are used to select one of these 7 registers. The Widget * - * number field is then derived from the W_NUM field for synthesizing * - * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * - * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * - * are padded with zeros. Although the maximum Crosstalk space * - * addressable by the Shub is thus the lower 16 GBytes per widget * - * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * - * space can be accessed. * - * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * - * Window number) are used to select one of these 7 registers. The * - * Widget number field is then derived from the W_NUM field for * - * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * - * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * - * field is used as Crosstalk[47], and remainder of the Crosstalk * - * address bits (Crosstalk[46:34]) are always zero. While the maximum * - * Crosstalk space addressable by the Shub is thus the lower * - * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * - * of this space can be accessed. * - * * - ************************************************************************/ - -typedef union ii_itte5_u { - shubreg_t ii_itte5_regval; - struct { - shubreg_t i_offset : 5; - shubreg_t i_rsvd_1 : 3; - shubreg_t i_w_num : 4; - shubreg_t i_iosp : 1; - shubreg_t i_rsvd : 51; - } ii_itte5_fld_s; -} ii_itte5_u_t; - - -/************************************************************************ - * * - * Description: There are seven instances of translation table entry * - * registers. Each register maps a Shub Big Window to a 48-bit * - * address on Crosstalk. * - * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * - * number) are used to select one of these 7 registers. The Widget * - * number field is then derived from the W_NUM field for synthesizing * - * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * - * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * - * are padded with zeros. Although the maximum Crosstalk space * - * addressable by the Shub is thus the lower 16 GBytes per widget * - * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * - * space can be accessed. * - * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * - * Window number) are used to select one of these 7 registers. The * - * Widget number field is then derived from the W_NUM field for * - * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * - * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * - * field is used as Crosstalk[47], and remainder of the Crosstalk * - * address bits (Crosstalk[46:34]) are always zero. While the maximum * - * Crosstalk space addressable by the Shub is thus the lower * - * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * - * of this space can be accessed. * - * * - ************************************************************************/ - -typedef union ii_itte6_u { - shubreg_t ii_itte6_regval; - struct { - shubreg_t i_offset : 5; - shubreg_t i_rsvd_1 : 3; - shubreg_t i_w_num : 4; - shubreg_t i_iosp : 1; - shubreg_t i_rsvd : 51; - } ii_itte6_fld_s; -} ii_itte6_u_t; - - -/************************************************************************ - * * - * Description: There are seven instances of translation table entry * - * registers. Each register maps a Shub Big Window to a 48-bit * - * address on Crosstalk. * - * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * - * number) are used to select one of these 7 registers. The Widget * - * number field is then derived from the W_NUM field for synthesizing * - * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * - * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * - * are padded with zeros. Although the maximum Crosstalk space * - * addressable by the Shub is thus the lower 16 GBytes per widget * - * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * - * space can be accessed. * - * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * - * Window number) are used to select one of these 7 registers. The * - * Widget number field is then derived from the W_NUM field for * - * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * - * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * - * field is used as Crosstalk[47], and remainder of the Crosstalk * - * address bits (Crosstalk[46:34]) are always zero. While the maximum * - * Crosstalk space addressable by the SHub is thus the lower * - * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * - * of this space can be accessed. * - * * - ************************************************************************/ - -typedef union ii_itte7_u { - shubreg_t ii_itte7_regval; - struct { - shubreg_t i_offset : 5; - shubreg_t i_rsvd_1 : 3; - shubreg_t i_w_num : 4; - shubreg_t i_iosp : 1; - shubreg_t i_rsvd : 51; - } ii_itte7_fld_s; -} ii_itte7_u_t; - - -/************************************************************************ - * * - * Description: There are 9 instances of this register, one per * - * actual widget in this implementation of SHub and Crossbow. * - * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * - * refers to Crossbow's internal space. * - * This register contains the state elements per widget that are * - * necessary to manage the PIO flow control on Crosstalk and on the * - * Router Network. See the PIO Flow Control chapter for a complete * - * description of this register * - * The SPUR_WR bit requires some explanation. When this register is * - * written, the new value of the C field is captured in an internal * - * register so the hardware can remember what the programmer wrote * - * into the credit counter. The SPUR_WR bit sets whenever the C field * - * increments above this stored value, which indicates that there * - * have been more responses received than requests sent. The SPUR_WR * - * bit cannot be cleared until a value is written to the IPRBx * - * register; the write will correct the C field and capture its new * - * value in the internal register. Even if IECLR[E_PRB_x] is set, the * - * SPUR_WR bit will persist if IPRBx hasn't yet been written. * - * . * - * * - ************************************************************************/ - -typedef union ii_iprb0_u { - shubreg_t ii_iprb0_regval; - struct { - shubreg_t i_c : 8; - shubreg_t i_na : 14; - shubreg_t i_rsvd_2 : 2; - shubreg_t i_nb : 14; - shubreg_t i_rsvd_1 : 2; - shubreg_t i_m : 2; - shubreg_t i_f : 1; - shubreg_t i_of_cnt : 5; - shubreg_t i_error : 1; - shubreg_t i_rd_to : 1; - shubreg_t i_spur_wr : 1; - shubreg_t i_spur_rd : 1; - shubreg_t i_rsvd : 11; - shubreg_t i_mult_err : 1; - } ii_iprb0_fld_s; -} ii_iprb0_u_t; - - -/************************************************************************ - * * - * Description: There are 9 instances of this register, one per * - * actual widget in this implementation of SHub and Crossbow. * - * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * - * refers to Crossbow's internal space. * - * This register contains the state elements per widget that are * - * necessary to manage the PIO flow control on Crosstalk and on the * - * Router Network. See the PIO Flow Control chapter for a complete * - * description of this register * - * The SPUR_WR bit requires some explanation. When this register is * - * written, the new value of the C field is captured in an internal * - * register so the hardware can remember what the programmer wrote * - * into the credit counter. The SPUR_WR bit sets whenever the C field * - * increments above this stored value, which indicates that there * - * have been more responses received than requests sent. The SPUR_WR * - * bit cannot be cleared until a value is written to the IPRBx * - * register; the write will correct the C field and capture its new * - * value in the internal register. Even if IECLR[E_PRB_x] is set, the * - * SPUR_WR bit will persist if IPRBx hasn't yet been written. * - * . * - * * - ************************************************************************/ - -typedef union ii_iprb8_u { - shubreg_t ii_iprb8_regval; - struct { - shubreg_t i_c : 8; - shubreg_t i_na : 14; - shubreg_t i_rsvd_2 : 2; - shubreg_t i_nb : 14; - shubreg_t i_rsvd_1 : 2; - shubreg_t i_m : 2; - shubreg_t i_f : 1; - shubreg_t i_of_cnt : 5; - shubreg_t i_error : 1; - shubreg_t i_rd_to : 1; - shubreg_t i_spur_wr : 1; - shubreg_t i_spur_rd : 1; - shubreg_t i_rsvd : 11; - shubreg_t i_mult_err : 1; - } ii_iprb8_fld_s; -} ii_iprb8_u_t; - - -/************************************************************************ - * * - * Description: There are 9 instances of this register, one per * - * actual widget in this implementation of SHub and Crossbow. * - * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * - * refers to Crossbow's internal space. * - * This register contains the state elements per widget that are * - * necessary to manage the PIO flow control on Crosstalk and on the * - * Router Network. See the PIO Flow Control chapter for a complete * - * description of this register * - * The SPUR_WR bit requires some explanation. When this register is * - * written, the new value of the C field is captured in an internal * - * register so the hardware can remember what the programmer wrote * - * into the credit counter. The SPUR_WR bit sets whenever the C field * - * increments above this stored value, which indicates that there * - * have been more responses received than requests sent. The SPUR_WR * - * bit cannot be cleared until a value is written to the IPRBx * - * register; the write will correct the C field and capture its new * - * value in the internal register. Even if IECLR[E_PRB_x] is set, the * - * SPUR_WR bit will persist if IPRBx hasn't yet been written. * - * . * - * * - ************************************************************************/ - -typedef union ii_iprb9_u { - shubreg_t ii_iprb9_regval; - struct { - shubreg_t i_c : 8; - shubreg_t i_na : 14; - shubreg_t i_rsvd_2 : 2; - shubreg_t i_nb : 14; - shubreg_t i_rsvd_1 : 2; - shubreg_t i_m : 2; - shubreg_t i_f : 1; - shubreg_t i_of_cnt : 5; - shubreg_t i_error : 1; - shubreg_t i_rd_to : 1; - shubreg_t i_spur_wr : 1; - shubreg_t i_spur_rd : 1; - shubreg_t i_rsvd : 11; - shubreg_t i_mult_err : 1; - } ii_iprb9_fld_s; -} ii_iprb9_u_t; - - -/************************************************************************ - * * - * Description: There are 9 instances of this register, one per * - * actual widget in this implementation of SHub and Crossbow. * - * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * - * refers to Crossbow's internal space. * - * This register contains the state elements per widget that are * - * necessary to manage the PIO flow control on Crosstalk and on the * - * Router Network. See the PIO Flow Control chapter for a complete * - * description of this register * - * The SPUR_WR bit requires some explanation. When this register is * - * written, the new value of the C field is captured in an internal * - * register so the hardware can remember what the programmer wrote * - * into the credit counter. The SPUR_WR bit sets whenever the C field * - * increments above this stored value, which indicates that there * - * have been more responses received than requests sent. The SPUR_WR * - * bit cannot be cleared until a value is written to the IPRBx * - * register; the write will correct the C field and capture its new * - * value in the internal register. Even if IECLR[E_PRB_x] is set, the * - * SPUR_WR bit will persist if IPRBx hasn't yet been written. * - * * - * * - ************************************************************************/ - -typedef union ii_iprba_u { - shubreg_t ii_iprba_regval; - struct { - shubreg_t i_c : 8; - shubreg_t i_na : 14; - shubreg_t i_rsvd_2 : 2; - shubreg_t i_nb : 14; - shubreg_t i_rsvd_1 : 2; - shubreg_t i_m : 2; - shubreg_t i_f : 1; - shubreg_t i_of_cnt : 5; - shubreg_t i_error : 1; - shubreg_t i_rd_to : 1; - shubreg_t i_spur_wr : 1; - shubreg_t i_spur_rd : 1; - shubreg_t i_rsvd : 11; - shubreg_t i_mult_err : 1; - } ii_iprba_fld_s; -} ii_iprba_u_t; - - -/************************************************************************ - * * - * Description: There are 9 instances of this register, one per * - * actual widget in this implementation of SHub and Crossbow. * - * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * - * refers to Crossbow's internal space. * - * This register contains the state elements per widget that are * - * necessary to manage the PIO flow control on Crosstalk and on the * - * Router Network. See the PIO Flow Control chapter for a complete * - * description of this register * - * The SPUR_WR bit requires some explanation. When this register is * - * written, the new value of the C field is captured in an internal * - * register so the hardware can remember what the programmer wrote * - * into the credit counter. The SPUR_WR bit sets whenever the C field * - * increments above this stored value, which indicates that there * - * have been more responses received than requests sent. The SPUR_WR * - * bit cannot be cleared until a value is written to the IPRBx * - * register; the write will correct the C field and capture its new * - * value in the internal register. Even if IECLR[E_PRB_x] is set, the * - * SPUR_WR bit will persist if IPRBx hasn't yet been written. * - * . * - * * - ************************************************************************/ - -typedef union ii_iprbb_u { - shubreg_t ii_iprbb_regval; - struct { - shubreg_t i_c : 8; - shubreg_t i_na : 14; - shubreg_t i_rsvd_2 : 2; - shubreg_t i_nb : 14; - shubreg_t i_rsvd_1 : 2; - shubreg_t i_m : 2; - shubreg_t i_f : 1; - shubreg_t i_of_cnt : 5; - shubreg_t i_error : 1; - shubreg_t i_rd_to : 1; - shubreg_t i_spur_wr : 1; - shubreg_t i_spur_rd : 1; - shubreg_t i_rsvd : 11; - shubreg_t i_mult_err : 1; - } ii_iprbb_fld_s; -} ii_iprbb_u_t; - - -/************************************************************************ - * * - * Description: There are 9 instances of this register, one per * - * actual widget in this implementation of SHub and Crossbow. * - * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * - * refers to Crossbow's internal space. * - * This register contains the state elements per widget that are * - * necessary to manage the PIO flow control on Crosstalk and on the * - * Router Network. See the PIO Flow Control chapter for a complete * - * description of this register * - * The SPUR_WR bit requires some explanation. When this register is * - * written, the new value of the C field is captured in an internal * - * register so the hardware can remember what the programmer wrote * - * into the credit counter. The SPUR_WR bit sets whenever the C field * - * increments above this stored value, which indicates that there * - * have been more responses received than requests sent. The SPUR_WR * - * bit cannot be cleared until a value is written to the IPRBx * - * register; the write will correct the C field and capture its new * - * value in the internal register. Even if IECLR[E_PRB_x] is set, the * - * SPUR_WR bit will persist if IPRBx hasn't yet been written. * - * . * - * * - ************************************************************************/ - -typedef union ii_iprbc_u { - shubreg_t ii_iprbc_regval; - struct { - shubreg_t i_c : 8; - shubreg_t i_na : 14; - shubreg_t i_rsvd_2 : 2; - shubreg_t i_nb : 14; - shubreg_t i_rsvd_1 : 2; - shubreg_t i_m : 2; - shubreg_t i_f : 1; - shubreg_t i_of_cnt : 5; - shubreg_t i_error : 1; - shubreg_t i_rd_to : 1; - shubreg_t i_spur_wr : 1; - shubreg_t i_spur_rd : 1; - shubreg_t i_rsvd : 11; - shubreg_t i_mult_err : 1; - } ii_iprbc_fld_s; -} ii_iprbc_u_t; - - -/************************************************************************ - * * - * Description: There are 9 instances of this register, one per * - * actual widget in this implementation of SHub and Crossbow. * - * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * - * refers to Crossbow's internal space. * - * This register contains the state elements per widget that are * - * necessary to manage the PIO flow control on Crosstalk and on the * - * Router Network. See the PIO Flow Control chapter for a complete * - * description of this register * - * The SPUR_WR bit requires some explanation. When this register is * - * written, the new value of the C field is captured in an internal * - * register so the hardware can remember what the programmer wrote * - * into the credit counter. The SPUR_WR bit sets whenever the C field * - * increments above this stored value, which indicates that there * - * have been more responses received than requests sent. The SPUR_WR * - * bit cannot be cleared until a value is written to the IPRBx * - * register; the write will correct the C field and capture its new * - * value in the internal register. Even if IECLR[E_PRB_x] is set, the * - * SPUR_WR bit will persist if IPRBx hasn't yet been written. * - * . * - * * - ************************************************************************/ - -typedef union ii_iprbd_u { - shubreg_t ii_iprbd_regval; - struct { - shubreg_t i_c : 8; - shubreg_t i_na : 14; - shubreg_t i_rsvd_2 : 2; - shubreg_t i_nb : 14; - shubreg_t i_rsvd_1 : 2; - shubreg_t i_m : 2; - shubreg_t i_f : 1; - shubreg_t i_of_cnt : 5; - shubreg_t i_error : 1; - shubreg_t i_rd_to : 1; - shubreg_t i_spur_wr : 1; - shubreg_t i_spur_rd : 1; - shubreg_t i_rsvd : 11; - shubreg_t i_mult_err : 1; - } ii_iprbd_fld_s; -} ii_iprbd_u_t; - - -/************************************************************************ - * * - * Description: There are 9 instances of this register, one per * - * actual widget in this implementation of SHub and Crossbow. * - * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * - * refers to Crossbow's internal space. * - * This register contains the state elements per widget that are * - * necessary to manage the PIO flow control on Crosstalk and on the * - * Router Network. See the PIO Flow Control chapter for a complete * - * description of this register * - * The SPUR_WR bit requires some explanation. When this register is * - * written, the new value of the C field is captured in an internal * - * register so the hardware can remember what the programmer wrote * - * into the credit counter. The SPUR_WR bit sets whenever the C field * - * increments above this stored value, which indicates that there * - * have been more responses received than requests sent. The SPUR_WR * - * bit cannot be cleared until a value is written to the IPRBx * - * register; the write will correct the C field and capture its new * - * value in the internal register. Even if IECLR[E_PRB_x] is set, the * - * SPUR_WR bit will persist if IPRBx hasn't yet been written. * - * . * - * * - ************************************************************************/ - -typedef union ii_iprbe_u { - shubreg_t ii_iprbe_regval; - struct { - shubreg_t i_c : 8; - shubreg_t i_na : 14; - shubreg_t i_rsvd_2 : 2; - shubreg_t i_nb : 14; - shubreg_t i_rsvd_1 : 2; - shubreg_t i_m : 2; - shubreg_t i_f : 1; - shubreg_t i_of_cnt : 5; - shubreg_t i_error : 1; - shubreg_t i_rd_to : 1; - shubreg_t i_spur_wr : 1; - shubreg_t i_spur_rd : 1; - shubreg_t i_rsvd : 11; - shubreg_t i_mult_err : 1; - } ii_iprbe_fld_s; -} ii_iprbe_u_t; - - -/************************************************************************ - * * - * Description: There are 9 instances of this register, one per * - * actual widget in this implementation of Shub and Crossbow. * - * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * - * refers to Crossbow's internal space. * - * This register contains the state elements per widget that are * - * necessary to manage the PIO flow control on Crosstalk and on the * - * Router Network. See the PIO Flow Control chapter for a complete * - * description of this register * - * The SPUR_WR bit requires some explanation. When this register is * - * written, the new value of the C field is captured in an internal * - * register so the hardware can remember what the programmer wrote * - * into the credit counter. The SPUR_WR bit sets whenever the C field * - * increments above this stored value, which indicates that there * - * have been more responses received than requests sent. The SPUR_WR * - * bit cannot be cleared until a value is written to the IPRBx * - * register; the write will correct the C field and capture its new * - * value in the internal register. Even if IECLR[E_PRB_x] is set, the * - * SPUR_WR bit will persist if IPRBx hasn't yet been written. * - * . * - * * - ************************************************************************/ - -typedef union ii_iprbf_u { - shubreg_t ii_iprbf_regval; - struct { - shubreg_t i_c : 8; - shubreg_t i_na : 14; - shubreg_t i_rsvd_2 : 2; - shubreg_t i_nb : 14; - shubreg_t i_rsvd_1 : 2; - shubreg_t i_m : 2; - shubreg_t i_f : 1; - shubreg_t i_of_cnt : 5; - shubreg_t i_error : 1; - shubreg_t i_rd_to : 1; - shubreg_t i_spur_wr : 1; - shubreg_t i_spur_rd : 1; - shubreg_t i_rsvd : 11; - shubreg_t i_mult_err : 1; - } ii_iprbe_fld_s; -} ii_iprbf_u_t; - - -/************************************************************************ - * * - * This register specifies the timeout value to use for monitoring * - * Crosstalk credits which are used outbound to Crosstalk. An * - * internal counter called the Crosstalk Credit Timeout Counter * - * increments every 128 II clocks. The counter starts counting * - * anytime the credit count drops below a threshold, and resets to * - * zero (stops counting) anytime the credit count is at or above the * - * threshold. The threshold is 1 credit in direct connect mode and 2 * - * in Crossbow connect mode. When the internal Crosstalk Credit * - * Timeout Counter reaches the value programmed in this register, a * - * Crosstalk Credit Timeout has occurred. The internal counter is not * - * readable from software, and stops counting at its maximum value, * - * so it cannot cause more than one interrupt. * - * * - ************************************************************************/ - -typedef union ii_ixcc_u { - shubreg_t ii_ixcc_regval; - struct { - shubreg_t i_time_out : 26; - shubreg_t i_rsvd : 38; - } ii_ixcc_fld_s; -} ii_ixcc_u_t; - - -/************************************************************************ - * * - * Description: This register qualifies all the PIO and DMA * - * operations launched from widget 0 towards the SHub. In * - * addition, it also qualifies accesses by the BTE streams. * - * The bits in each field of this register are cleared by the SHub * - * upon detection of an error which requires widget 0 or the BTE * - * streams to be terminated. Whether or not widget x has access * - * rights to this SHub is determined by an AND of the device * - * enable bit in the appropriate field of this register and bit 0 in * - * the Wx_IAC field. The bits in this field are set by writing a 1 to * - * them. Incoming replies from Crosstalk are not subject to this * - * access control mechanism. * - * * - ************************************************************************/ - -typedef union ii_imem_u { - shubreg_t ii_imem_regval; - struct { - shubreg_t i_w0_esd : 1; - shubreg_t i_rsvd_3 : 3; - shubreg_t i_b0_esd : 1; - shubreg_t i_rsvd_2 : 3; - shubreg_t i_b1_esd : 1; - shubreg_t i_rsvd_1 : 3; - shubreg_t i_clr_precise : 1; - shubreg_t i_rsvd : 51; - } ii_imem_fld_s; -} ii_imem_u_t; - - - -/************************************************************************ - * * - * Description: This register specifies the timeout value to use for * - * monitoring Crosstalk tail flits coming into the Shub in the * - * TAIL_TO field. An internal counter associated with this register * - * is incremented every 128 II internal clocks (7 bits). The counter * - * starts counting anytime a header micropacket is received and stops * - * counting (and resets to zero) any time a micropacket with a Tail * - * bit is received. Once the counter reaches the threshold value * - * programmed in this register, it generates an interrupt to the * - * processor that is programmed into the IIDSR. The counter saturates * - * (does not roll over) at its maximum value, so it cannot cause * - * another interrupt until after it is cleared. * - * The register also contains the Read Response Timeout values. The * - * Prescalar is 23 bits, and counts II clocks. An internal counter * - * increments on every II clock and when it reaches the value in the * - * Prescalar field, all IPRTE registers with their valid bits set * - * have their Read Response timers bumped. Whenever any of them match * - * the value in the RRSP_TO field, a Read Response Timeout has * - * occurred, and error handling occurs as described in the Error * - * Handling section of this document. * - * * - ************************************************************************/ - -typedef union ii_ixtt_u { - shubreg_t ii_ixtt_regval; - struct { - shubreg_t i_tail_to : 26; - shubreg_t i_rsvd_1 : 6; - shubreg_t i_rrsp_ps : 23; - shubreg_t i_rrsp_to : 5; - shubreg_t i_rsvd : 4; - } ii_ixtt_fld_s; -} ii_ixtt_u_t; - - -/************************************************************************ - * * - * Writing a 1 to the fields of this register clears the appropriate * - * error bits in other areas of SHub. Note that when the * - * E_PRB_x bits are used to clear error bits in PRB registers, * - * SPUR_RD and SPUR_WR may persist, because they require additional * - * action to clear them. See the IPRBx and IXSS Register * - * specifications. * - * * - ************************************************************************/ - -typedef union ii_ieclr_u { - shubreg_t ii_ieclr_regval; - struct { - shubreg_t i_e_prb_0 : 1; - shubreg_t i_rsvd : 7; - shubreg_t i_e_prb_8 : 1; - shubreg_t i_e_prb_9 : 1; - shubreg_t i_e_prb_a : 1; - shubreg_t i_e_prb_b : 1; - shubreg_t i_e_prb_c : 1; - shubreg_t i_e_prb_d : 1; - shubreg_t i_e_prb_e : 1; - shubreg_t i_e_prb_f : 1; - shubreg_t i_e_crazy : 1; - shubreg_t i_e_bte_0 : 1; - shubreg_t i_e_bte_1 : 1; - shubreg_t i_reserved_1 : 10; - shubreg_t i_spur_rd_hdr : 1; - shubreg_t i_cam_intr_to : 1; - shubreg_t i_cam_overflow : 1; - shubreg_t i_cam_read_miss : 1; - shubreg_t i_ioq_rep_underflow : 1; - shubreg_t i_ioq_req_underflow : 1; - shubreg_t i_ioq_rep_overflow : 1; - shubreg_t i_ioq_req_overflow : 1; - shubreg_t i_iiq_rep_overflow : 1; - shubreg_t i_iiq_req_overflow : 1; - shubreg_t i_ii_xn_rep_cred_overflow : 1; - shubreg_t i_ii_xn_req_cred_overflow : 1; - shubreg_t i_ii_xn_invalid_cmd : 1; - shubreg_t i_xn_ii_invalid_cmd : 1; - shubreg_t i_reserved_2 : 21; - } ii_ieclr_fld_s; -} ii_ieclr_u_t; - - -/************************************************************************ - * * - * This register controls both BTEs. SOFT_RESET is intended for * - * recovery after an error. COUNT controls the total number of CRBs * - * that both BTEs (combined) can use, which affects total BTE * - * bandwidth. * - * * - ************************************************************************/ - -typedef union ii_ibcr_u { - shubreg_t ii_ibcr_regval; - struct { - shubreg_t i_count : 4; - shubreg_t i_rsvd_1 : 4; - shubreg_t i_soft_reset : 1; - shubreg_t i_rsvd : 55; - } ii_ibcr_fld_s; -} ii_ibcr_u_t; - - -/************************************************************************ - * * - * This register contains the header of a spurious read response * - * received from Crosstalk. A spurious read response is defined as a * - * read response received by II from a widget for which (1) the SIDN * - * has a value between 1 and 7, inclusive (II never sends requests to * - * these widgets (2) there is no valid IPRTE register which * - * corresponds to the TNUM, or (3) the widget indicated in SIDN is * - * not the same as the widget recorded in the IPRTE register * - * referenced by the TNUM. If this condition is true, and if the * - * IXSS[VALID] bit is clear, then the header of the spurious read * - * response is capture in IXSM and IXSS, and IXSS[VALID] is set. The * - * errant header is thereby captured, and no further spurious read * - * respones are captured until IXSS[VALID] is cleared by setting the * - * appropriate bit in IECLR.Everytime a spurious read response is * - * detected, the SPUR_RD bit of the PRB corresponding to the incoming * - * message's SIDN field is set. This always happens, regarless of * - * whether a header is captured. The programmer should check * - * IXSM[SIDN] to determine which widget sent the spurious response, * - * because there may be more than one SPUR_RD bit set in the PRB * - * registers. The widget indicated by IXSM[SIDN] was the first * - * spurious read response to be received since the last time * - * IXSS[VALID] was clear. The SPUR_RD bit of the corresponding PRB * - * will be set. Any SPUR_RD bits in any other PRB registers indicate * - * spurious messages from other widets which were detected after the * - * header was captured.. * - * * - ************************************************************************/ - -typedef union ii_ixsm_u { - shubreg_t ii_ixsm_regval; - struct { - shubreg_t i_byte_en : 32; - shubreg_t i_reserved : 1; - shubreg_t i_tag : 3; - shubreg_t i_alt_pactyp : 4; - shubreg_t i_bo : 1; - shubreg_t i_error : 1; - shubreg_t i_vbpm : 1; - shubreg_t i_gbr : 1; - shubreg_t i_ds : 2; - shubreg_t i_ct : 1; - shubreg_t i_tnum : 5; - shubreg_t i_pactyp : 4; - shubreg_t i_sidn : 4; - shubreg_t i_didn : 4; - } ii_ixsm_fld_s; -} ii_ixsm_u_t; - - -/************************************************************************ - * * - * This register contains the sideband bits of a spurious read * - * response received from Crosstalk. * - * * - ************************************************************************/ - -typedef union ii_ixss_u { - shubreg_t ii_ixss_regval; - struct { - shubreg_t i_sideband : 8; - shubreg_t i_rsvd : 55; - shubreg_t i_valid : 1; - } ii_ixss_fld_s; -} ii_ixss_u_t; - - -/************************************************************************ - * * - * This register enables software to access the II LLP's test port. * - * Refer to the LLP 2.5 documentation for an explanation of the test * - * port. Software can write to this register to program the values * - * for the control fields (TestErrCapture, TestClear, TestFlit, * - * TestMask and TestSeed). Similarly, software can read from this * - * register to obtain the values of the test port's status outputs * - * (TestCBerr, TestValid and TestData). * - * * - ************************************************************************/ - -typedef union ii_ilct_u { - shubreg_t ii_ilct_regval; - struct { - shubreg_t i_test_seed : 20; - shubreg_t i_test_mask : 8; - shubreg_t i_test_data : 20; - shubreg_t i_test_valid : 1; - shubreg_t i_test_cberr : 1; - shubreg_t i_test_flit : 3; - shubreg_t i_test_clear : 1; - shubreg_t i_test_err_capture : 1; - shubreg_t i_rsvd : 9; - } ii_ilct_fld_s; -} ii_ilct_u_t; - - -/************************************************************************ - * * - * If the II detects an illegal incoming Duplonet packet (request or * - * reply) when VALID==0 in the IIEPH1 register, then it saves the * - * contents of the packet's header flit in the IIEPH1 and IIEPH2 * - * registers, sets the VALID bit in IIEPH1, clears the OVERRUN bit, * - * and assigns a value to the ERR_TYPE field which indicates the * - * specific nature of the error. The II recognizes four different * - * types of errors: short request packets (ERR_TYPE==2), short reply * - * packets (ERR_TYPE==3), long request packets (ERR_TYPE==4) and long * - * reply packets (ERR_TYPE==5). The encodings for these types of * - * errors were chosen to be consistent with the same types of errors * - * indicated by the ERR_TYPE field in the LB_ERROR_HDR1 register (in * - * the LB unit). If the II detects an illegal incoming Duplonet * - * packet when VALID==1 in the IIEPH1 register, then it merely sets * - * the OVERRUN bit to indicate that a subsequent error has happened, * - * and does nothing further. * - * * - ************************************************************************/ - -typedef union ii_iieph1_u { - shubreg_t ii_iieph1_regval; - struct { - shubreg_t i_command : 7; - shubreg_t i_rsvd_5 : 1; - shubreg_t i_suppl : 14; - shubreg_t i_rsvd_4 : 1; - shubreg_t i_source : 14; - shubreg_t i_rsvd_3 : 1; - shubreg_t i_err_type : 4; - shubreg_t i_rsvd_2 : 4; - shubreg_t i_overrun : 1; - shubreg_t i_rsvd_1 : 3; - shubreg_t i_valid : 1; - shubreg_t i_rsvd : 13; - } ii_iieph1_fld_s; -} ii_iieph1_u_t; - - -/************************************************************************ - * * - * This register holds the Address field from the header flit of an * - * incoming erroneous Duplonet packet, along with the tail bit which * - * accompanied this header flit. This register is essentially an * - * extension of IIEPH1. Two registers were necessary because the 64 * - * bits available in only a single register were insufficient to * - * capture the entire header flit of an erroneous packet. * - * * - ************************************************************************/ - -typedef union ii_iieph2_u { - shubreg_t ii_iieph2_regval; - struct { - shubreg_t i_rsvd_0 : 3; - shubreg_t i_address : 47; - shubreg_t i_rsvd_1 : 10; - shubreg_t i_tail : 1; - shubreg_t i_rsvd : 3; - } ii_iieph2_fld_s; -} ii_iieph2_u_t; - - -/******************************/ - - - -/************************************************************************ - * * - * This register's value is a bit vector that guards access from SXBs * - * to local registers within the II as well as to external Crosstalk * - * widgets * - * * - ************************************************************************/ - -typedef union ii_islapr_u { - shubreg_t ii_islapr_regval; - struct { - shubreg_t i_region : 64; - } ii_islapr_fld_s; -} ii_islapr_u_t; - - -/************************************************************************ - * * - * A write to this register of the 56-bit value "Pup+Bun" will cause * - * the bit in the ISLAPR register corresponding to the region of the * - * requestor to be set (access allowed). ( - * * - ************************************************************************/ - -typedef union ii_islapo_u { - shubreg_t ii_islapo_regval; - struct { - shubreg_t i_io_sbx_ovrride : 56; - shubreg_t i_rsvd : 8; - } ii_islapo_fld_s; -} ii_islapo_u_t; - -/************************************************************************ - * * - * Determines how long the wrapper will wait aftr an interrupt is * - * initially issued from the II before it times out the outstanding * - * interrupt and drops it from the interrupt queue. * - * * - ************************************************************************/ - -typedef union ii_iwi_u { - shubreg_t ii_iwi_regval; - struct { - shubreg_t i_prescale : 24; - shubreg_t i_rsvd : 8; - shubreg_t i_timeout : 8; - shubreg_t i_rsvd1 : 8; - shubreg_t i_intrpt_retry_period : 8; - shubreg_t i_rsvd2 : 8; - } ii_iwi_fld_s; -} ii_iwi_u_t; - -/************************************************************************ - * * - * Log errors which have occurred in the II wrapper. The errors are * - * cleared by writing to the IECLR register. * - * * - ************************************************************************/ - -typedef union ii_iwel_u { - shubreg_t ii_iwel_regval; - struct { - shubreg_t i_intr_timed_out : 1; - shubreg_t i_rsvd : 7; - shubreg_t i_cam_overflow : 1; - shubreg_t i_cam_read_miss : 1; - shubreg_t i_rsvd1 : 2; - shubreg_t i_ioq_rep_underflow : 1; - shubreg_t i_ioq_req_underflow : 1; - shubreg_t i_ioq_rep_overflow : 1; - shubreg_t i_ioq_req_overflow : 1; - shubreg_t i_iiq_rep_overflow : 1; - shubreg_t i_iiq_req_overflow : 1; - shubreg_t i_rsvd2 : 6; - shubreg_t i_ii_xn_rep_cred_over_under: 1; - shubreg_t i_ii_xn_req_cred_over_under: 1; - shubreg_t i_rsvd3 : 6; - shubreg_t i_ii_xn_invalid_cmd : 1; - shubreg_t i_xn_ii_invalid_cmd : 1; - shubreg_t i_rsvd4 : 30; - } ii_iwel_fld_s; -} ii_iwel_u_t; - -/************************************************************************ - * * - * Controls the II wrapper. * - * * - ************************************************************************/ - -typedef union ii_iwc_u { - shubreg_t ii_iwc_regval; - struct { - shubreg_t i_dma_byte_swap : 1; - shubreg_t i_rsvd : 3; - shubreg_t i_cam_read_lines_reset : 1; - shubreg_t i_rsvd1 : 3; - shubreg_t i_ii_xn_cred_over_under_log: 1; - shubreg_t i_rsvd2 : 19; - shubreg_t i_xn_rep_iq_depth : 5; - shubreg_t i_rsvd3 : 3; - shubreg_t i_xn_req_iq_depth : 5; - shubreg_t i_rsvd4 : 3; - shubreg_t i_iiq_depth : 6; - shubreg_t i_rsvd5 : 12; - shubreg_t i_force_rep_cred : 1; - shubreg_t i_force_req_cred : 1; - } ii_iwc_fld_s; -} ii_iwc_u_t; - -/************************************************************************ - * * - * Status in the II wrapper. * - * * - ************************************************************************/ - -typedef union ii_iws_u { - shubreg_t ii_iws_regval; - struct { - shubreg_t i_xn_rep_iq_credits : 5; - shubreg_t i_rsvd : 3; - shubreg_t i_xn_req_iq_credits : 5; - shubreg_t i_rsvd1 : 51; - } ii_iws_fld_s; -} ii_iws_u_t; - -/************************************************************************ - * * - * Masks errors in the IWEL register. * - * * - ************************************************************************/ - -typedef union ii_iweim_u { - shubreg_t ii_iweim_regval; - struct { - shubreg_t i_intr_timed_out : 1; - shubreg_t i_rsvd : 7; - shubreg_t i_cam_overflow : 1; - shubreg_t i_cam_read_miss : 1; - shubreg_t i_rsvd1 : 2; - shubreg_t i_ioq_rep_underflow : 1; - shubreg_t i_ioq_req_underflow : 1; - shubreg_t i_ioq_rep_overflow : 1; - shubreg_t i_ioq_req_overflow : 1; - shubreg_t i_iiq_rep_overflow : 1; - shubreg_t i_iiq_req_overflow : 1; - shubreg_t i_rsvd2 : 6; - shubreg_t i_ii_xn_rep_cred_overflow : 1; - shubreg_t i_ii_xn_req_cred_overflow : 1; - shubreg_t i_rsvd3 : 6; - shubreg_t i_ii_xn_invalid_cmd : 1; - shubreg_t i_xn_ii_invalid_cmd : 1; - shubreg_t i_rsvd4 : 30; - } ii_iweim_fld_s; -} ii_iweim_u_t; - - -/************************************************************************ - * * - * A write to this register causes a particular field in the * - * corresponding widget's PRB entry to be adjusted up or down by 1. * - * This counter should be used when recovering from error and reset * - * conditions. Note that software would be capable of causing * - * inadvertent overflow or underflow of these counters. * - * * - ************************************************************************/ - -typedef union ii_ipca_u { - shubreg_t ii_ipca_regval; - struct { - shubreg_t i_wid : 4; - shubreg_t i_adjust : 1; - shubreg_t i_rsvd_1 : 3; - shubreg_t i_field : 2; - shubreg_t i_rsvd : 54; - } ii_ipca_fld_s; -} ii_ipca_u_t; - - -/************************************************************************ - * * - * There are 8 instances of this register. This register contains * - * the information that the II has to remember once it has launched a * - * PIO Read operation. The contents are used to form the correct * - * Router Network packet and direct the Crosstalk reply to the * - * appropriate processor. * - * * - ************************************************************************/ - - -typedef union ii_iprte0a_u { - shubreg_t ii_iprte0a_regval; - struct { - shubreg_t i_rsvd_1 : 54; - shubreg_t i_widget : 4; - shubreg_t i_to_cnt : 5; - shubreg_t i_vld : 1; - } ii_iprte0a_fld_s; -} ii_iprte0a_u_t; - - -/************************************************************************ - * * - * There are 8 instances of this register. This register contains * - * the information that the II has to remember once it has launched a * - * PIO Read operation. The contents are used to form the correct * - * Router Network packet and direct the Crosstalk reply to the * - * appropriate processor. * - * * - ************************************************************************/ - -typedef union ii_iprte1a_u { - shubreg_t ii_iprte1a_regval; - struct { - shubreg_t i_rsvd_1 : 54; - shubreg_t i_widget : 4; - shubreg_t i_to_cnt : 5; - shubreg_t i_vld : 1; - } ii_iprte1a_fld_s; -} ii_iprte1a_u_t; - - -/************************************************************************ - * * - * There are 8 instances of this register. This register contains * - * the information that the II has to remember once it has launched a * - * PIO Read operation. The contents are used to form the correct * - * Router Network packet and direct the Crosstalk reply to the * - * appropriate processor. * - * * - ************************************************************************/ - -typedef union ii_iprte2a_u { - shubreg_t ii_iprte2a_regval; - struct { - shubreg_t i_rsvd_1 : 54; - shubreg_t i_widget : 4; - shubreg_t i_to_cnt : 5; - shubreg_t i_vld : 1; - } ii_iprte2a_fld_s; -} ii_iprte2a_u_t; - - -/************************************************************************ - * * - * There are 8 instances of this register. This register contains * - * the information that the II has to remember once it has launched a * - * PIO Read operation. The contents are used to form the correct * - * Router Network packet and direct the Crosstalk reply to the * - * appropriate processor. * - * * - ************************************************************************/ - -typedef union ii_iprte3a_u { - shubreg_t ii_iprte3a_regval; - struct { - shubreg_t i_rsvd_1 : 54; - shubreg_t i_widget : 4; - shubreg_t i_to_cnt : 5; - shubreg_t i_vld : 1; - } ii_iprte3a_fld_s; -} ii_iprte3a_u_t; - - -/************************************************************************ - * * - * There are 8 instances of this register. This register contains * - * the information that the II has to remember once it has launched a * - * PIO Read operation. The contents are used to form the correct * - * Router Network packet and direct the Crosstalk reply to the * - * appropriate processor. * - * * - ************************************************************************/ - -typedef union ii_iprte4a_u { - shubreg_t ii_iprte4a_regval; - struct { - shubreg_t i_rsvd_1 : 54; - shubreg_t i_widget : 4; - shubreg_t i_to_cnt : 5; - shubreg_t i_vld : 1; - } ii_iprte4a_fld_s; -} ii_iprte4a_u_t; - - -/************************************************************************ - * * - * There are 8 instances of this register. This register contains * - * the information that the II has to remember once it has launched a * - * PIO Read operation. The contents are used to form the correct * - * Router Network packet and direct the Crosstalk reply to the * - * appropriate processor. * - * * - ************************************************************************/ - -typedef union ii_iprte5a_u { - shubreg_t ii_iprte5a_regval; - struct { - shubreg_t i_rsvd_1 : 54; - shubreg_t i_widget : 4; - shubreg_t i_to_cnt : 5; - shubreg_t i_vld : 1; - } ii_iprte5a_fld_s; -} ii_iprte5a_u_t; - - -/************************************************************************ - * * - * There are 8 instances of this register. This register contains * - * the information that the II has to remember once it has launched a * - * PIO Read operation. The contents are used to form the correct * - * Router Network packet and direct the Crosstalk reply to the * - * appropriate processor. * - * * - ************************************************************************/ - -typedef union ii_iprte6a_u { - shubreg_t ii_iprte6a_regval; - struct { - shubreg_t i_rsvd_1 : 54; - shubreg_t i_widget : 4; - shubreg_t i_to_cnt : 5; - shubreg_t i_vld : 1; - } ii_iprte6a_fld_s; -} ii_iprte6a_u_t; - - -/************************************************************************ - * * - * There are 8 instances of this register. This register contains * - * the information that the II has to remember once it has launched a * - * PIO Read operation. The contents are used to form the correct * - * Router Network packet and direct the Crosstalk reply to the * - * appropriate processor. * - * * - ************************************************************************/ - -typedef union ii_iprte7a_u { - shubreg_t ii_iprte7a_regval; - struct { - shubreg_t i_rsvd_1 : 54; - shubreg_t i_widget : 4; - shubreg_t i_to_cnt : 5; - shubreg_t i_vld : 1; - } ii_iprtea7_fld_s; -} ii_iprte7a_u_t; - - - -/************************************************************************ - * * - * There are 8 instances of this register. This register contains * - * the information that the II has to remember once it has launched a * - * PIO Read operation. The contents are used to form the correct * - * Router Network packet and direct the Crosstalk reply to the * - * appropriate processor. * - * * - ************************************************************************/ - - -typedef union ii_iprte0b_u { - shubreg_t ii_iprte0b_regval; - struct { - shubreg_t i_rsvd_1 : 3; - shubreg_t i_address : 47; - shubreg_t i_init : 3; - shubreg_t i_source : 11; - } ii_iprte0b_fld_s; -} ii_iprte0b_u_t; - - -/************************************************************************ - * * - * There are 8 instances of this register. This register contains * - * the information that the II has to remember once it has launched a * - * PIO Read operation. The contents are used to form the correct * - * Router Network packet and direct the Crosstalk reply to the * - * appropriate processor. * - * * - ************************************************************************/ - -typedef union ii_iprte1b_u { - shubreg_t ii_iprte1b_regval; - struct { - shubreg_t i_rsvd_1 : 3; - shubreg_t i_address : 47; - shubreg_t i_init : 3; - shubreg_t i_source : 11; - } ii_iprte1b_fld_s; -} ii_iprte1b_u_t; - - -/************************************************************************ - * * - * There are 8 instances of this register. This register contains * - * the information that the II has to remember once it has launched a * - * PIO Read operation. The contents are used to form the correct * - * Router Network packet and direct the Crosstalk reply to the * - * appropriate processor. * - * * - ************************************************************************/ - -typedef union ii_iprte2b_u { - shubreg_t ii_iprte2b_regval; - struct { - shubreg_t i_rsvd_1 : 3; - shubreg_t i_address : 47; - shubreg_t i_init : 3; - shubreg_t i_source : 11; - } ii_iprte2b_fld_s; -} ii_iprte2b_u_t; - - -/************************************************************************ - * * - * There are 8 instances of this register. This register contains * - * the information that the II has to remember once it has launched a * - * PIO Read operation. The contents are used to form the correct * - * Router Network packet and direct the Crosstalk reply to the * - * appropriate processor. * - * * - ************************************************************************/ - -typedef union ii_iprte3b_u { - shubreg_t ii_iprte3b_regval; - struct { - shubreg_t i_rsvd_1 : 3; - shubreg_t i_address : 47; - shubreg_t i_init : 3; - shubreg_t i_source : 11; - } ii_iprte3b_fld_s; -} ii_iprte3b_u_t; - - -/************************************************************************ - * * - * There are 8 instances of this register. This register contains * - * the information that the II has to remember once it has launched a * - * PIO Read operation. The contents are used to form the correct * - * Router Network packet and direct the Crosstalk reply to the * - * appropriate processor. * - * * - ************************************************************************/ - -typedef union ii_iprte4b_u { - shubreg_t ii_iprte4b_regval; - struct { - shubreg_t i_rsvd_1 : 3; - shubreg_t i_address : 47; - shubreg_t i_init : 3; - shubreg_t i_source : 11; - } ii_iprte4b_fld_s; -} ii_iprte4b_u_t; - - -/************************************************************************ - * * - * There are 8 instances of this register. This register contains * - * the information that the II has to remember once it has launched a * - * PIO Read operation. The contents are used to form the correct * - * Router Network packet and direct the Crosstalk reply to the * - * appropriate processor. * - * * - ************************************************************************/ - -typedef union ii_iprte5b_u { - shubreg_t ii_iprte5b_regval; - struct { - shubreg_t i_rsvd_1 : 3; - shubreg_t i_address : 47; - shubreg_t i_init : 3; - shubreg_t i_source : 11; - } ii_iprte5b_fld_s; -} ii_iprte5b_u_t; - - -/************************************************************************ - * * - * There are 8 instances of this register. This register contains * - * the information that the II has to remember once it has launched a * - * PIO Read operation. The contents are used to form the correct * - * Router Network packet and direct the Crosstalk reply to the * - * appropriate processor. * - * * - ************************************************************************/ - -typedef union ii_iprte6b_u { - shubreg_t ii_iprte6b_regval; - struct { - shubreg_t i_rsvd_1 : 3; - shubreg_t i_address : 47; - shubreg_t i_init : 3; - shubreg_t i_source : 11; - - } ii_iprte6b_fld_s; -} ii_iprte6b_u_t; - - -/************************************************************************ - * * - * There are 8 instances of this register. This register contains * - * the information that the II has to remember once it has launched a * - * PIO Read operation. The contents are used to form the correct * - * Router Network packet and direct the Crosstalk reply to the * - * appropriate processor. * - * * - ************************************************************************/ - -typedef union ii_iprte7b_u { - shubreg_t ii_iprte7b_regval; - struct { - shubreg_t i_rsvd_1 : 3; - shubreg_t i_address : 47; - shubreg_t i_init : 3; - shubreg_t i_source : 11; - } ii_iprte7b_fld_s; -} ii_iprte7b_u_t; - - -/************************************************************************ - * * - * Description: SHub II contains a feature which did not exist in * - * the Hub which automatically cleans up after a Read Response * - * timeout, including deallocation of the IPRTE and recovery of IBuf * - * space. The inclusion of this register in SHub is for backward * - * compatibility * - * A write to this register causes an entry from the table of * - * outstanding PIO Read Requests to be freed and returned to the * - * stack of free entries. This register is used in handling the * - * timeout errors that result in a PIO Reply never returning from * - * Crosstalk. * - * Note that this register does not affect the contents of the IPRTE * - * registers. The Valid bits in those registers have to be * - * specifically turned off by software. * - * * - ************************************************************************/ - -typedef union ii_ipdr_u { - shubreg_t ii_ipdr_regval; - struct { - shubreg_t i_te : 3; - shubreg_t i_rsvd_1 : 1; - shubreg_t i_pnd : 1; - shubreg_t i_init_rpcnt : 1; - shubreg_t i_rsvd : 58; - } ii_ipdr_fld_s; -} ii_ipdr_u_t; - - -/************************************************************************ - * * - * A write to this register causes a CRB entry to be returned to the * - * queue of free CRBs. The entry should have previously been cleared * - * (mark bit) via backdoor access to the pertinent CRB entry. This * - * register is used in the last step of handling the errors that are * - * captured and marked in CRB entries. Briefly: 1) first error for * - * DMA write from a particular device, and first error for a * - * particular BTE stream, lead to a marked CRB entry, and processor * - * interrupt, 2) software reads the error information captured in the * - * CRB entry, and presumably takes some corrective action, 3) * - * software clears the mark bit, and finally 4) software writes to * - * the ICDR register to return the CRB entry to the list of free CRB * - * entries. * - * * - ************************************************************************/ - -typedef union ii_icdr_u { - shubreg_t ii_icdr_regval; - struct { - shubreg_t i_crb_num : 4; - shubreg_t i_pnd : 1; - shubreg_t i_rsvd : 59; - } ii_icdr_fld_s; -} ii_icdr_u_t; - - -/************************************************************************ - * * - * This register provides debug access to two FIFOs inside of II. * - * Both IOQ_MAX* fields of this register contain the instantaneous * - * depth (in units of the number of available entries) of the * - * associated IOQ FIFO. A read of this register will return the * - * number of free entries on each FIFO at the time of the read. So * - * when a FIFO is idle, the associated field contains the maximum * - * depth of the FIFO. This register is writable for debug reasons * - * and is intended to be written with the maximum desired FIFO depth * - * while the FIFO is idle. Software must assure that II is idle when * - * this register is written. If there are any active entries in any * - * of these FIFOs when this register is written, the results are * - * undefined. * - * * - ************************************************************************/ - -typedef union ii_ifdr_u { - shubreg_t ii_ifdr_regval; - struct { - shubreg_t i_ioq_max_rq : 7; - shubreg_t i_set_ioq_rq : 1; - shubreg_t i_ioq_max_rp : 7; - shubreg_t i_set_ioq_rp : 1; - shubreg_t i_rsvd : 48; - } ii_ifdr_fld_s; -} ii_ifdr_u_t; - - -/************************************************************************ - * * - * This register allows the II to become sluggish in removing * - * messages from its inbound queue (IIQ). This will cause messages to * - * back up in either virtual channel. Disabling the "molasses" mode * - * subsequently allows the II to be tested under stress. In the * - * sluggish ("Molasses") mode, the localized effects of congestion * - * can be observed. * - * * - ************************************************************************/ - -typedef union ii_iiap_u { - shubreg_t ii_iiap_regval; - struct { - shubreg_t i_rq_mls : 6; - shubreg_t i_rsvd_1 : 2; - shubreg_t i_rp_mls : 6; - shubreg_t i_rsvd : 50; - } ii_iiap_fld_s; -} ii_iiap_u_t; - - -/************************************************************************ - * * - * This register allows several parameters of CRB operation to be * - * set. Note that writing to this register can have catastrophic side * - * effects, if the CRB is not quiescent, i.e. if the CRB is * - * processing protocol messages when the write occurs. * - * * - ************************************************************************/ - -typedef union ii_icmr_u { - shubreg_t ii_icmr_regval; - struct { - shubreg_t i_sp_msg : 1; - shubreg_t i_rd_hdr : 1; - shubreg_t i_rsvd_4 : 2; - shubreg_t i_c_cnt : 4; - shubreg_t i_rsvd_3 : 4; - shubreg_t i_clr_rqpd : 1; - shubreg_t i_clr_rppd : 1; - shubreg_t i_rsvd_2 : 2; - shubreg_t i_fc_cnt : 4; - shubreg_t i_crb_vld : 15; - shubreg_t i_crb_mark : 15; - shubreg_t i_rsvd_1 : 2; - shubreg_t i_precise : 1; - shubreg_t i_rsvd : 11; - } ii_icmr_fld_s; -} ii_icmr_u_t; - - -/************************************************************************ - * * - * This register allows control of the table portion of the CRB * - * logic via software. Control operations from this register have * - * priority over all incoming Crosstalk or BTE requests. * - * * - ************************************************************************/ - -typedef union ii_iccr_u { - shubreg_t ii_iccr_regval; - struct { - shubreg_t i_crb_num : 4; - shubreg_t i_rsvd_1 : 4; - shubreg_t i_cmd : 8; - shubreg_t i_pending : 1; - shubreg_t i_rsvd : 47; - } ii_iccr_fld_s; -} ii_iccr_u_t; - - -/************************************************************************ - * * - * This register allows the maximum timeout value to be programmed. * - * * - ************************************************************************/ - -typedef union ii_icto_u { - shubreg_t ii_icto_regval; - struct { - shubreg_t i_timeout : 8; - shubreg_t i_rsvd : 56; - } ii_icto_fld_s; -} ii_icto_u_t; - - -/************************************************************************ - * * - * This register allows the timeout prescalar to be programmed. An * - * internal counter is associated with this register. When the * - * internal counter reaches the value of the PRESCALE field, the * - * timer registers in all valid CRBs are incremented (CRBx_D[TIMEOUT] * - * field). The internal counter resets to zero, and then continues * - * counting. * - * * - ************************************************************************/ - -typedef union ii_ictp_u { - shubreg_t ii_ictp_regval; - struct { - shubreg_t i_prescale : 24; - shubreg_t i_rsvd : 40; - } ii_ictp_fld_s; -} ii_ictp_u_t; - - -/************************************************************************ - * * - * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * - * used for Crosstalk operations (both cacheline and partial * - * operations) or BTE/IO. Because the CRB entries are very wide, five * - * registers (_A to _E) are required to read and write each entry. * - * The CRB Entry registers can be conceptualized as rows and columns * - * (illustrated in the table above). Each row contains the 4 * - * registers required for a single CRB Entry. The first doubleword * - * (column) for each entry is labeled A, and the second doubleword * - * (higher address) is labeled B, the third doubleword is labeled C, * - * the fourth doubleword is labeled D and the fifth doubleword is * - * labeled E. All CRB entries have their addresses on a quarter * - * cacheline aligned boundary. * - * Upon reset, only the following fields are initialized: valid * - * (VLD), priority count, timeout, timeout valid, and context valid. * - * All other bits should be cleared by software before use (after * - * recovering any potential error state from before the reset). * - * The following four tables summarize the format for the four * - * registers that are used for each ICRB# Entry. * - * * - ************************************************************************/ - -typedef union ii_icrb0_a_u { - shubreg_t ii_icrb0_a_regval; - struct { - shubreg_t ia_iow : 1; - shubreg_t ia_vld : 1; - shubreg_t ia_addr : 47; - shubreg_t ia_tnum : 5; - shubreg_t ia_sidn : 4; - shubreg_t ia_rsvd : 6; - } ii_icrb0_a_fld_s; -} ii_icrb0_a_u_t; - - -/************************************************************************ - * * - * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * - * used for Crosstalk operations (both cacheline and partial * - * operations) or BTE/IO. Because the CRB entries are very wide, five * - * registers (_A to _E) are required to read and write each entry. * - * * - ************************************************************************/ - -typedef union ii_icrb0_b_u { - shubreg_t ii_icrb0_b_regval; - struct { - shubreg_t ib_xt_err : 1; - shubreg_t ib_mark : 1; - shubreg_t ib_ln_uce : 1; - shubreg_t ib_errcode : 3; - shubreg_t ib_error : 1; - shubreg_t ib_stall__bte_1 : 1; - shubreg_t ib_stall__bte_0 : 1; - shubreg_t ib_stall__intr : 1; - shubreg_t ib_stall_ib : 1; - shubreg_t ib_intvn : 1; - shubreg_t ib_wb : 1; - shubreg_t ib_hold : 1; - shubreg_t ib_ack : 1; - shubreg_t ib_resp : 1; - shubreg_t ib_ack_cnt : 11; - shubreg_t ib_rsvd : 7; - shubreg_t ib_exc : 5; - shubreg_t ib_init : 3; - shubreg_t ib_imsg : 8; - shubreg_t ib_imsgtype : 2; - shubreg_t ib_use_old : 1; - shubreg_t ib_rsvd_1 : 11; - } ii_icrb0_b_fld_s; -} ii_icrb0_b_u_t; - - -/************************************************************************ - * * - * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * - * used for Crosstalk operations (both cacheline and partial * - * operations) or BTE/IO. Because the CRB entries are very wide, five * - * registers (_A to _E) are required to read and write each entry. * - * * - ************************************************************************/ - -typedef union ii_icrb0_c_u { - shubreg_t ii_icrb0_c_regval; - struct { - shubreg_t ic_source : 15; - shubreg_t ic_size : 2; - shubreg_t ic_ct : 1; - shubreg_t ic_bte_num : 1; - shubreg_t ic_gbr : 1; - shubreg_t ic_resprqd : 1; - shubreg_t ic_bo : 1; - shubreg_t ic_suppl : 15; - shubreg_t ic_rsvd : 27; - } ii_icrb0_c_fld_s; -} ii_icrb0_c_u_t; - - -/************************************************************************ - * * - * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * - * used for Crosstalk operations (both cacheline and partial * - * operations) or BTE/IO. Because the CRB entries are very wide, five * - * registers (_A to _E) are required to read and write each entry. * - * * - ************************************************************************/ - -typedef union ii_icrb0_d_u { - shubreg_t ii_icrb0_d_regval; - struct { - shubreg_t id_pa_be : 43; - shubreg_t id_bte_op : 1; - shubreg_t id_pr_psc : 4; - shubreg_t id_pr_cnt : 4; - shubreg_t id_sleep : 1; - shubreg_t id_rsvd : 11; - } ii_icrb0_d_fld_s; -} ii_icrb0_d_u_t; - - -/************************************************************************ - * * - * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * - * used for Crosstalk operations (both cacheline and partial * - * operations) or BTE/IO. Because the CRB entries are very wide, five * - * registers (_A to _E) are required to read and write each entry. * - * * - ************************************************************************/ - -typedef union ii_icrb0_e_u { - shubreg_t ii_icrb0_e_regval; - struct { - shubreg_t ie_timeout : 8; - shubreg_t ie_context : 15; - shubreg_t ie_rsvd : 1; - shubreg_t ie_tvld : 1; - shubreg_t ie_cvld : 1; - shubreg_t ie_rsvd_0 : 38; - } ii_icrb0_e_fld_s; -} ii_icrb0_e_u_t; - - -/************************************************************************ - * * - * This register contains the lower 64 bits of the header of the * - * spurious message captured by II. Valid when the SP_MSG bit in ICMR * - * register is set. * - * * - ************************************************************************/ - -typedef union ii_icsml_u { - shubreg_t ii_icsml_regval; - struct { - shubreg_t i_tt_addr : 47; - shubreg_t i_newsuppl_ex : 14; - shubreg_t i_reserved : 2; - shubreg_t i_overflow : 1; - } ii_icsml_fld_s; -} ii_icsml_u_t; - - -/************************************************************************ - * * - * This register contains the middle 64 bits of the header of the * - * spurious message captured by II. Valid when the SP_MSG bit in ICMR * - * register is set. * - * * - ************************************************************************/ - -typedef union ii_icsmm_u { - shubreg_t ii_icsmm_regval; - struct { - shubreg_t i_tt_ack_cnt : 11; - shubreg_t i_reserved : 53; - } ii_icsmm_fld_s; -} ii_icsmm_u_t; - - -/************************************************************************ - * * - * This register contains the microscopic state, all the inputs to * - * the protocol table, captured with the spurious message. Valid when * - * the SP_MSG bit in the ICMR register is set. * - * * - ************************************************************************/ - -typedef union ii_icsmh_u { - shubreg_t ii_icsmh_regval; - struct { - shubreg_t i_tt_vld : 1; - shubreg_t i_xerr : 1; - shubreg_t i_ft_cwact_o : 1; - shubreg_t i_ft_wact_o : 1; - shubreg_t i_ft_active_o : 1; - shubreg_t i_sync : 1; - shubreg_t i_mnusg : 1; - shubreg_t i_mnusz : 1; - shubreg_t i_plusz : 1; - shubreg_t i_plusg : 1; - shubreg_t i_tt_exc : 5; - shubreg_t i_tt_wb : 1; - shubreg_t i_tt_hold : 1; - shubreg_t i_tt_ack : 1; - shubreg_t i_tt_resp : 1; - shubreg_t i_tt_intvn : 1; - shubreg_t i_g_stall_bte1 : 1; - shubreg_t i_g_stall_bte0 : 1; - shubreg_t i_g_stall_il : 1; - shubreg_t i_g_stall_ib : 1; - shubreg_t i_tt_imsg : 8; - shubreg_t i_tt_imsgtype : 2; - shubreg_t i_tt_use_old : 1; - shubreg_t i_tt_respreqd : 1; - shubreg_t i_tt_bte_num : 1; - shubreg_t i_cbn : 1; - shubreg_t i_match : 1; - shubreg_t i_rpcnt_lt_34 : 1; - shubreg_t i_rpcnt_ge_34 : 1; - shubreg_t i_rpcnt_lt_18 : 1; - shubreg_t i_rpcnt_ge_18 : 1; - shubreg_t i_rpcnt_lt_2 : 1; - shubreg_t i_rpcnt_ge_2 : 1; - shubreg_t i_rqcnt_lt_18 : 1; - shubreg_t i_rqcnt_ge_18 : 1; - shubreg_t i_rqcnt_lt_2 : 1; - shubreg_t i_rqcnt_ge_2 : 1; - shubreg_t i_tt_device : 7; - shubreg_t i_tt_init : 3; - shubreg_t i_reserved : 5; - } ii_icsmh_fld_s; -} ii_icsmh_u_t; - - -/************************************************************************ - * * - * The Shub DEBUG unit provides a 3-bit selection signal to the * - * II core and a 3-bit selection signal to the fsbclk domain in the II * - * wrapper. * - * * - ************************************************************************/ - -typedef union ii_idbss_u { - shubreg_t ii_idbss_regval; - struct { - shubreg_t i_iioclk_core_submenu : 3; - shubreg_t i_rsvd : 5; - shubreg_t i_fsbclk_wrapper_submenu : 3; - shubreg_t i_rsvd_1 : 5; - shubreg_t i_iioclk_menu : 5; - shubreg_t i_rsvd_2 : 43; - } ii_idbss_fld_s; -} ii_idbss_u_t; - - -/************************************************************************ - * * - * Description: This register is used to set up the length for a * - * transfer and then to monitor the progress of that transfer. This * - * register needs to be initialized before a transfer is started. A * - * legitimate write to this register will set the Busy bit, clear the * - * Error bit, and initialize the length to the value desired. * - * While the transfer is in progress, hardware will decrement the * - * length field with each successful block that is copied. Once the * - * transfer completes, hardware will clear the Busy bit. The length * - * field will also contain the number of cache lines left to be * - * transferred. * - * * - ************************************************************************/ - -typedef union ii_ibls0_u { - shubreg_t ii_ibls0_regval; - struct { - shubreg_t i_length : 16; - shubreg_t i_error : 1; - shubreg_t i_rsvd_1 : 3; - shubreg_t i_busy : 1; - shubreg_t i_rsvd : 43; - } ii_ibls0_fld_s; -} ii_ibls0_u_t; - - -/************************************************************************ - * * - * This register should be loaded before a transfer is started. The * - * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * - * address as described in Section 1.3, Figure2 and Figure3. Since * - * the bottom 7 bits of the address are always taken to be zero, BTE * - * transfers are always cacheline-aligned. * - * * - ************************************************************************/ - -typedef union ii_ibsa0_u { - shubreg_t ii_ibsa0_regval; - struct { - shubreg_t i_rsvd_1 : 7; - shubreg_t i_addr : 42; - shubreg_t i_rsvd : 15; - } ii_ibsa0_fld_s; -} ii_ibsa0_u_t; - - -/************************************************************************ - * * - * This register should be loaded before a transfer is started. The * - * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * - * address as described in Section 1.3, Figure2 and Figure3. Since * - * the bottom 7 bits of the address are always taken to be zero, BTE * - * transfers are always cacheline-aligned. * - * * - ************************************************************************/ - -typedef union ii_ibda0_u { - shubreg_t ii_ibda0_regval; - struct { - shubreg_t i_rsvd_1 : 7; - shubreg_t i_addr : 42; - shubreg_t i_rsvd : 15; - } ii_ibda0_fld_s; -} ii_ibda0_u_t; - - -/************************************************************************ - * * - * Writing to this register sets up the attributes of the transfer * - * and initiates the transfer operation. Reading this register has * - * the side effect of terminating any transfer in progress. Note: * - * stopping a transfer midstream could have an adverse impact on the * - * other BTE. If a BTE stream has to be stopped (due to error * - * handling for example), both BTE streams should be stopped and * - * their transfers discarded. * - * * - ************************************************************************/ - -typedef union ii_ibct0_u { - shubreg_t ii_ibct0_regval; - struct { - shubreg_t i_zerofill : 1; - shubreg_t i_rsvd_2 : 3; - shubreg_t i_notify : 1; - shubreg_t i_rsvd_1 : 3; - shubreg_t i_poison : 1; - shubreg_t i_rsvd : 55; - } ii_ibct0_fld_s; -} ii_ibct0_u_t; - - -/************************************************************************ - * * - * This register contains the address to which the WINV is sent. * - * This address has to be cache line aligned. * - * * - ************************************************************************/ - -typedef union ii_ibna0_u { - shubreg_t ii_ibna0_regval; - struct { - shubreg_t i_rsvd_1 : 7; - shubreg_t i_addr : 42; - shubreg_t i_rsvd : 15; - } ii_ibna0_fld_s; -} ii_ibna0_u_t; - - -/************************************************************************ - * * - * This register contains the programmable level as well as the node * - * ID and PI unit of the processor to which the interrupt will be * - * sent. * - * * - ************************************************************************/ - -typedef union ii_ibia0_u { - shubreg_t ii_ibia0_regval; - struct { - shubreg_t i_rsvd_2 : 1; - shubreg_t i_node_id : 11; - shubreg_t i_rsvd_1 : 4; - shubreg_t i_level : 7; - shubreg_t i_rsvd : 41; - } ii_ibia0_fld_s; -} ii_ibia0_u_t; - - -/************************************************************************ - * * - * Description: This register is used to set up the length for a * - * transfer and then to monitor the progress of that transfer. This * - * register needs to be initialized before a transfer is started. A * - * legitimate write to this register will set the Busy bit, clear the * - * Error bit, and initialize the length to the value desired. * - * While the transfer is in progress, hardware will decrement the * - * length field with each successful block that is copied. Once the * - * transfer completes, hardware will clear the Busy bit. The length * - * field will also contain the number of cache lines left to be * - * transferred. * - * * - ************************************************************************/ - -typedef union ii_ibls1_u { - shubreg_t ii_ibls1_regval; - struct { - shubreg_t i_length : 16; - shubreg_t i_error : 1; - shubreg_t i_rsvd_1 : 3; - shubreg_t i_busy : 1; - shubreg_t i_rsvd : 43; - } ii_ibls1_fld_s; -} ii_ibls1_u_t; - - -/************************************************************************ - * * - * This register should be loaded before a transfer is started. The * - * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * - * address as described in Section 1.3, Figure2 and Figure3. Since * - * the bottom 7 bits of the address are always taken to be zero, BTE * - * transfers are always cacheline-aligned. * - * * - ************************************************************************/ - -typedef union ii_ibsa1_u { - shubreg_t ii_ibsa1_regval; - struct { - shubreg_t i_rsvd_1 : 7; - shubreg_t i_addr : 33; - shubreg_t i_rsvd : 24; - } ii_ibsa1_fld_s; -} ii_ibsa1_u_t; - - -/************************************************************************ - * * - * This register should be loaded before a transfer is started. The * - * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * - * address as described in Section 1.3, Figure2 and Figure3. Since * - * the bottom 7 bits of the address are always taken to be zero, BTE * - * transfers are always cacheline-aligned. * - * * - ************************************************************************/ - -typedef union ii_ibda1_u { - shubreg_t ii_ibda1_regval; - struct { - shubreg_t i_rsvd_1 : 7; - shubreg_t i_addr : 33; - shubreg_t i_rsvd : 24; - } ii_ibda1_fld_s; -} ii_ibda1_u_t; - - -/************************************************************************ - * * - * Writing to this register sets up the attributes of the transfer * - * and initiates the transfer operation. Reading this register has * - * the side effect of terminating any transfer in progress. Note: * - * stopping a transfer midstream could have an adverse impact on the * - * other BTE. If a BTE stream has to be stopped (due to error * - * handling for example), both BTE streams should be stopped and * - * their transfers discarded. * - * * - ************************************************************************/ - -typedef union ii_ibct1_u { - shubreg_t ii_ibct1_regval; - struct { - shubreg_t i_zerofill : 1; - shubreg_t i_rsvd_2 : 3; - shubreg_t i_notify : 1; - shubreg_t i_rsvd_1 : 3; - shubreg_t i_poison : 1; - shubreg_t i_rsvd : 55; - } ii_ibct1_fld_s; -} ii_ibct1_u_t; - - -/************************************************************************ - * * - * This register contains the address to which the WINV is sent. * - * This address has to be cache line aligned. * - * * - ************************************************************************/ - -typedef union ii_ibna1_u { - shubreg_t ii_ibna1_regval; - struct { - shubreg_t i_rsvd_1 : 7; - shubreg_t i_addr : 33; - shubreg_t i_rsvd : 24; - } ii_ibna1_fld_s; -} ii_ibna1_u_t; - - -/************************************************************************ - * * - * This register contains the programmable level as well as the node * - * ID and PI unit of the processor to which the interrupt will be * - * sent. * - * * - ************************************************************************/ - -typedef union ii_ibia1_u { - shubreg_t ii_ibia1_regval; - struct { - shubreg_t i_pi_id : 1; - shubreg_t i_node_id : 8; - shubreg_t i_rsvd_1 : 7; - shubreg_t i_level : 7; - shubreg_t i_rsvd : 41; - } ii_ibia1_fld_s; -} ii_ibia1_u_t; - - -/************************************************************************ - * * - * This register defines the resources that feed information into * - * the two performance counters located in the IO Performance * - * Profiling Register. There are 17 different quantities that can be * - * measured. Given these 17 different options, the two performance * - * counters have 15 of them in common; menu selections 0 through 0xE * - * are identical for each performance counter. As for the other two * - * options, one is available from one performance counter and the * - * other is available from the other performance counter. Hence, the * - * II supports all 17*16=272 possible combinations of quantities to * - * measure. * - * * - ************************************************************************/ - -typedef union ii_ipcr_u { - shubreg_t ii_ipcr_regval; - struct { - shubreg_t i_ippr0_c : 4; - shubreg_t i_ippr1_c : 4; - shubreg_t i_icct : 8; - shubreg_t i_rsvd : 48; - } ii_ipcr_fld_s; -} ii_ipcr_u_t; - - -/************************************************************************ - * * - * * - * * - ************************************************************************/ - -typedef union ii_ippr_u { - shubreg_t ii_ippr_regval; - struct { - shubreg_t i_ippr0 : 32; - shubreg_t i_ippr1 : 32; - } ii_ippr_fld_s; -} ii_ippr_u_t; - - -/************************************************************************** - * * - * The following defines which were not formed into structures are * - * probably indentical to another register, and the name of the * - * register is provided against each of these registers. This * - * information needs to be checked carefully * - * * - * IIO_ICRB1_A IIO_ICRB0_A * - * IIO_ICRB1_B IIO_ICRB0_B * - * IIO_ICRB1_C IIO_ICRB0_C * - * IIO_ICRB1_D IIO_ICRB0_D * - * IIO_ICRB1_E IIO_ICRB0_E * - * IIO_ICRB2_A IIO_ICRB0_A * - * IIO_ICRB2_B IIO_ICRB0_B * - * IIO_ICRB2_C IIO_ICRB0_C * - * IIO_ICRB2_D IIO_ICRB0_D * - * IIO_ICRB2_E IIO_ICRB0_E * - * IIO_ICRB3_A IIO_ICRB0_A * - * IIO_ICRB3_B IIO_ICRB0_B * - * IIO_ICRB3_C IIO_ICRB0_C * - * IIO_ICRB3_D IIO_ICRB0_D * - * IIO_ICRB3_E IIO_ICRB0_E * - * IIO_ICRB4_A IIO_ICRB0_A * - * IIO_ICRB4_B IIO_ICRB0_B * - * IIO_ICRB4_C IIO_ICRB0_C * - * IIO_ICRB4_D IIO_ICRB0_D * - * IIO_ICRB4_E IIO_ICRB0_E * - * IIO_ICRB5_A IIO_ICRB0_A * - * IIO_ICRB5_B IIO_ICRB0_B * - * IIO_ICRB5_C IIO_ICRB0_C * - * IIO_ICRB5_D IIO_ICRB0_D * - * IIO_ICRB5_E IIO_ICRB0_E * - * IIO_ICRB6_A IIO_ICRB0_A * - * IIO_ICRB6_B IIO_ICRB0_B * - * IIO_ICRB6_C IIO_ICRB0_C * - * IIO_ICRB6_D IIO_ICRB0_D * - * IIO_ICRB6_E IIO_ICRB0_E * - * IIO_ICRB7_A IIO_ICRB0_A * - * IIO_ICRB7_B IIO_ICRB0_B * - * IIO_ICRB7_C IIO_ICRB0_C * - * IIO_ICRB7_D IIO_ICRB0_D * - * IIO_ICRB7_E IIO_ICRB0_E * - * IIO_ICRB8_A IIO_ICRB0_A * - * IIO_ICRB8_B IIO_ICRB0_B * - * IIO_ICRB8_C IIO_ICRB0_C * - * IIO_ICRB8_D IIO_ICRB0_D * - * IIO_ICRB8_E IIO_ICRB0_E * - * IIO_ICRB9_A IIO_ICRB0_A * - * IIO_ICRB9_B IIO_ICRB0_B * - * IIO_ICRB9_C IIO_ICRB0_C * - * IIO_ICRB9_D IIO_ICRB0_D * - * IIO_ICRB9_E IIO_ICRB0_E * - * IIO_ICRBA_A IIO_ICRB0_A * - * IIO_ICRBA_B IIO_ICRB0_B * - * IIO_ICRBA_C IIO_ICRB0_C * - * IIO_ICRBA_D IIO_ICRB0_D * - * IIO_ICRBA_E IIO_ICRB0_E * - * IIO_ICRBB_A IIO_ICRB0_A * - * IIO_ICRBB_B IIO_ICRB0_B * - * IIO_ICRBB_C IIO_ICRB0_C * - * IIO_ICRBB_D IIO_ICRB0_D * - * IIO_ICRBB_E IIO_ICRB0_E * - * IIO_ICRBC_A IIO_ICRB0_A * - * IIO_ICRBC_B IIO_ICRB0_B * - * IIO_ICRBC_C IIO_ICRB0_C * - * IIO_ICRBC_D IIO_ICRB0_D * - * IIO_ICRBC_E IIO_ICRB0_E * - * IIO_ICRBD_A IIO_ICRB0_A * - * IIO_ICRBD_B IIO_ICRB0_B * - * IIO_ICRBD_C IIO_ICRB0_C * - * IIO_ICRBD_D IIO_ICRB0_D * - * IIO_ICRBD_E IIO_ICRB0_E * - * IIO_ICRBE_A IIO_ICRB0_A * - * IIO_ICRBE_B IIO_ICRB0_B * - * IIO_ICRBE_C IIO_ICRB0_C * - * IIO_ICRBE_D IIO_ICRB0_D * - * IIO_ICRBE_E IIO_ICRB0_E * - * * - **************************************************************************/ - - -/* - * Slightly friendlier names for some common registers. - */ -#define IIO_WIDGET IIO_WID /* Widget identification */ -#define IIO_WIDGET_STAT IIO_WSTAT /* Widget status register */ -#define IIO_WIDGET_CTRL IIO_WCR /* Widget control register */ -#define IIO_PROTECT IIO_ILAPR /* IO interface protection */ -#define IIO_PROTECT_OVRRD IIO_ILAPO /* IO protect override */ -#define IIO_OUTWIDGET_ACCESS IIO_IOWA /* Outbound widget access */ -#define IIO_INWIDGET_ACCESS IIO_IIWA /* Inbound widget access */ -#define IIO_INDEV_ERR_MASK IIO_IIDEM /* Inbound device error mask */ -#define IIO_LLP_CSR IIO_ILCSR /* LLP control and status */ -#define IIO_LLP_LOG IIO_ILLR /* LLP log */ -#define IIO_XTALKCC_TOUT IIO_IXCC /* Xtalk credit count timeout*/ -#define IIO_XTALKTT_TOUT IIO_IXTT /* Xtalk tail timeout */ -#define IIO_IO_ERR_CLR IIO_IECLR /* IO error clear */ -#define IIO_IGFX_0 IIO_IGFX0 -#define IIO_IGFX_1 IIO_IGFX1 -#define IIO_IBCT_0 IIO_IBCT0 -#define IIO_IBCT_1 IIO_IBCT1 -#define IIO_IBLS_0 IIO_IBLS0 -#define IIO_IBLS_1 IIO_IBLS1 -#define IIO_IBSA_0 IIO_IBSA0 -#define IIO_IBSA_1 IIO_IBSA1 -#define IIO_IBDA_0 IIO_IBDA0 -#define IIO_IBDA_1 IIO_IBDA1 -#define IIO_IBNA_0 IIO_IBNA0 -#define IIO_IBNA_1 IIO_IBNA1 -#define IIO_IBIA_0 IIO_IBIA0 -#define IIO_IBIA_1 IIO_IBIA1 -#define IIO_IOPRB_0 IIO_IPRB0 - -#define IIO_PRTE_A(_x) (IIO_IPRTE0_A + (8 * (_x))) -#define IIO_PRTE_B(_x) (IIO_IPRTE0_B + (8 * (_x))) -#define IIO_NUM_PRTES 8 /* Total number of PRB table entries */ -#define IIO_WIDPRTE_A(x) IIO_PRTE_A(((x) - 8)) /* widget ID to its PRTE num */ -#define IIO_WIDPRTE_B(x) IIO_PRTE_B(((x) - 8)) /* widget ID to its PRTE num */ - -#define IIO_NUM_IPRBS (9) - -#define IIO_LLP_CSR_IS_UP 0x00002000 -#define IIO_LLP_CSR_LLP_STAT_MASK 0x00003000 -#define IIO_LLP_CSR_LLP_STAT_SHFT 12 - -#define IIO_LLP_CB_MAX 0xffff /* in ILLR CB_CNT, Max Check Bit errors */ -#define IIO_LLP_SN_MAX 0xffff /* in ILLR SN_CNT, Max Sequence Number errors */ - -/* key to IIO_PROTECT_OVRRD */ -#define IIO_PROTECT_OVRRD_KEY 0x53474972756c6573ull /* "SGIrules" */ - -/* BTE register names */ -#define IIO_BTE_STAT_0 IIO_IBLS_0 /* Also BTE length/status 0 */ -#define IIO_BTE_SRC_0 IIO_IBSA_0 /* Also BTE source address 0 */ -#define IIO_BTE_DEST_0 IIO_IBDA_0 /* Also BTE dest. address 0 */ -#define IIO_BTE_CTRL_0 IIO_IBCT_0 /* Also BTE control/terminate 0 */ -#define IIO_BTE_NOTIFY_0 IIO_IBNA_0 /* Also BTE notification 0 */ -#define IIO_BTE_INT_0 IIO_IBIA_0 /* Also BTE interrupt 0 */ -#define IIO_BTE_OFF_0 0 /* Base offset from BTE 0 regs. */ -#define IIO_BTE_OFF_1 (IIO_IBLS_1 - IIO_IBLS_0) /* Offset from base to BTE 1 */ - -/* BTE register offsets from base */ -#define BTEOFF_STAT 0 -#define BTEOFF_SRC (IIO_BTE_SRC_0 - IIO_BTE_STAT_0) -#define BTEOFF_DEST (IIO_BTE_DEST_0 - IIO_BTE_STAT_0) -#define BTEOFF_CTRL (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0) -#define BTEOFF_NOTIFY (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0) -#define BTEOFF_INT (IIO_BTE_INT_0 - IIO_BTE_STAT_0) - - -/* names used in shub diags */ -#define IIO_BASE_BTE0 IIO_IBLS_0 -#define IIO_BASE_BTE1 IIO_IBLS_1 - -/* - * Macro which takes the widget number, and returns the - * IO PRB address of that widget. - * value _x is expected to be a widget number in the range - * 0, 8 - 0xF - */ -#define IIO_IOPRB(_x) (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \ - (_x) : \ - (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) ) - - -/* GFX Flow Control Node/Widget Register */ -#define IIO_IGFX_W_NUM_BITS 4 /* size of widget num field */ -#define IIO_IGFX_W_NUM_MASK ((1<<IIO_IGFX_W_NUM_BITS)-1) -#define IIO_IGFX_W_NUM_SHIFT 0 -#define IIO_IGFX_PI_NUM_BITS 1 /* size of PI num field */ -#define IIO_IGFX_PI_NUM_MASK ((1<<IIO_IGFX_PI_NUM_BITS)-1) -#define IIO_IGFX_PI_NUM_SHIFT 4 -#define IIO_IGFX_N_NUM_BITS 8 /* size of node num field */ -#define IIO_IGFX_N_NUM_MASK ((1<<IIO_IGFX_N_NUM_BITS)-1) -#define IIO_IGFX_N_NUM_SHIFT 5 -#define IIO_IGFX_P_NUM_BITS 1 /* size of processor num field */ -#define IIO_IGFX_P_NUM_MASK ((1<<IIO_IGFX_P_NUM_BITS)-1) -#define IIO_IGFX_P_NUM_SHIFT 16 -#define IIO_IGFX_INIT(widget, pi, node, cpu) (\ - (((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) | \ - (((pi) & IIO_IGFX_PI_NUM_MASK)<< IIO_IGFX_PI_NUM_SHIFT)| \ - (((node) & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) | \ - (((cpu) & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT)) - - -/* Scratch registers (all bits available) */ -#define IIO_SCRATCH_REG0 IIO_ISCR0 -#define IIO_SCRATCH_REG1 IIO_ISCR1 -#define IIO_SCRATCH_MASK 0xffffffffffffffffUL - -#define IIO_SCRATCH_BIT0_0 0x0000000000000001UL -#define IIO_SCRATCH_BIT0_1 0x0000000000000002UL -#define IIO_SCRATCH_BIT0_2 0x0000000000000004UL -#define IIO_SCRATCH_BIT0_3 0x0000000000000008UL -#define IIO_SCRATCH_BIT0_4 0x0000000000000010UL -#define IIO_SCRATCH_BIT0_5 0x0000000000000020UL -#define IIO_SCRATCH_BIT0_6 0x0000000000000040UL -#define IIO_SCRATCH_BIT0_7 0x0000000000000080UL -#define IIO_SCRATCH_BIT0_8 0x0000000000000100UL -#define IIO_SCRATCH_BIT0_9 0x0000000000000200UL -#define IIO_SCRATCH_BIT0_A 0x0000000000000400UL - -#define IIO_SCRATCH_BIT1_0 0x0000000000000001UL -#define IIO_SCRATCH_BIT1_1 0x0000000000000002UL -/* IO Translation Table Entries */ -#define IIO_NUM_ITTES 7 /* ITTEs numbered 0..6 */ - /* Hw manuals number them 1..7! */ -/* - * IIO_IMEM Register fields. - */ -#define IIO_IMEM_W0ESD 0x1UL /* Widget 0 shut down due to error */ -#define IIO_IMEM_B0ESD (1UL << 4) /* BTE 0 shut down due to error */ -#define IIO_IMEM_B1ESD (1UL << 8) /* BTE 1 Shut down due to error */ - -/* - * As a permanent workaround for a bug in the PI side of the shub, we've - * redefined big window 7 as small window 0. - XXX does this still apply for SN1?? - */ -#define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1) - -/* - * Use the top big window as a surrogate for the first small window - */ -#define SWIN0_BIGWIN HUB_NUM_BIG_WINDOW - -#define ILCSR_WARM_RESET 0x100 - -/* - * CRB manipulation macros - * The CRB macros are slightly complicated, since there are up to - * four registers associated with each CRB entry. - */ -#define IIO_NUM_CRBS 15 /* Number of CRBs */ -#define IIO_NUM_PC_CRBS 4 /* Number of partial cache CRBs */ -#define IIO_ICRB_OFFSET 8 -#define IIO_ICRB_0 IIO_ICRB0_A -#define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */ -/* XXX - This is now tuneable: - #define IIO_FIRST_PC_ENTRY 12 - */ - -#define IIO_ICRB_A(_x) ((u64)(IIO_ICRB_0 + (6 * IIO_ICRB_OFFSET * (_x)))) -#define IIO_ICRB_B(_x) ((u64)((char *)IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET)) -#define IIO_ICRB_C(_x) ((u64)((char *)IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET)) -#define IIO_ICRB_D(_x) ((u64)((char *)IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET)) -#define IIO_ICRB_E(_x) ((u64)((char *)IIO_ICRB_A(_x) + 4*IIO_ICRB_OFFSET)) - -#define TNUM_TO_WIDGET_DEV(_tnum) (_tnum & 0x7) - -/* - * values for "ecode" field - */ -#define IIO_ICRB_ECODE_DERR 0 /* Directory error due to IIO access */ -#define IIO_ICRB_ECODE_PERR 1 /* Poison error on IO access */ -#define IIO_ICRB_ECODE_WERR 2 /* Write error by IIO access - * e.g. WINV to a Read only line. */ -#define IIO_ICRB_ECODE_AERR 3 /* Access error caused by IIO access */ -#define IIO_ICRB_ECODE_PWERR 4 /* Error on partial write */ -#define IIO_ICRB_ECODE_PRERR 5 /* Error on partial read */ -#define IIO_ICRB_ECODE_TOUT 6 /* CRB timeout before deallocating */ -#define IIO_ICRB_ECODE_XTERR 7 /* Incoming xtalk pkt had error bit */ - -/* - * Values for field imsgtype - */ -#define IIO_ICRB_IMSGT_XTALK 0 /* Incoming Meessage from Xtalk */ -#define IIO_ICRB_IMSGT_BTE 1 /* Incoming message from BTE */ -#define IIO_ICRB_IMSGT_SN1NET 2 /* Incoming message from SN1 net */ -#define IIO_ICRB_IMSGT_CRB 3 /* Incoming message from CRB ??? */ - -/* - * values for field initiator. - */ -#define IIO_ICRB_INIT_XTALK 0 /* Message originated in xtalk */ -#define IIO_ICRB_INIT_BTE0 0x1 /* Message originated in BTE 0 */ -#define IIO_ICRB_INIT_SN1NET 0x2 /* Message originated in SN1net */ -#define IIO_ICRB_INIT_CRB 0x3 /* Message originated in CRB ? */ -#define IIO_ICRB_INIT_BTE1 0x5 /* MEssage originated in BTE 1 */ - -/* - * Number of credits Hub widget has while sending req/response to - * xbow. - * Value of 3 is required by Xbow 1.1 - * We may be able to increase this to 4 with Xbow 1.2. - */ -#define HUBII_XBOW_CREDIT 3 -#define HUBII_XBOW_REV2_CREDIT 4 - -/* - * Number of credits that xtalk devices should use when communicating - * with a SHub (depth of SHub's queue). - */ -#define HUB_CREDIT 4 - -/* - * Some IIO_PRB fields - */ -#define IIO_PRB_MULTI_ERR (1LL << 63) -#define IIO_PRB_SPUR_RD (1LL << 51) -#define IIO_PRB_SPUR_WR (1LL << 50) -#define IIO_PRB_RD_TO (1LL << 49) -#define IIO_PRB_ERROR (1LL << 48) - -/************************************************************************* - - Some of the IIO field masks and shifts are defined here. - This is in order to maintain compatibility in SN0 and SN1 code - -**************************************************************************/ - -/* - * ICMR register fields - * (Note: the IIO_ICMR_P_CNT and IIO_ICMR_PC_VLD from Hub are not - * present in SHub) - */ - -#define IIO_ICMR_CRB_VLD_SHFT 20 -#define IIO_ICMR_CRB_VLD_MASK (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT) - -#define IIO_ICMR_FC_CNT_SHFT 16 -#define IIO_ICMR_FC_CNT_MASK (0xf << IIO_ICMR_FC_CNT_SHFT) - -#define IIO_ICMR_C_CNT_SHFT 4 -#define IIO_ICMR_C_CNT_MASK (0xf << IIO_ICMR_C_CNT_SHFT) - -#define IIO_ICMR_PRECISE (1UL << 52) -#define IIO_ICMR_CLR_RPPD (1UL << 13) -#define IIO_ICMR_CLR_RQPD (1UL << 12) - -/* - * IIO PIO Deallocation register field masks : (IIO_IPDR) - XXX present but not needed in bedrock? See the manual. - */ -#define IIO_IPDR_PND (1 << 4) - -/* - * IIO CRB deallocation register field masks: (IIO_ICDR) - */ -#define IIO_ICDR_PND (1 << 4) - -/* - * IO BTE Length/Status (IIO_IBLS) register bit field definitions - */ -#define IBLS_BUSY (0x1UL << 20) -#define IBLS_ERROR_SHFT 16 -#define IBLS_ERROR (0x1UL << IBLS_ERROR_SHFT) -#define IBLS_LENGTH_MASK 0xffff - -/* - * IO BTE Control/Terminate register (IBCT) register bit field definitions - */ -#define IBCT_POISON (0x1UL << 8) -#define IBCT_NOTIFY (0x1UL << 4) -#define IBCT_ZFIL_MODE (0x1UL << 0) - -/* - * IIO Incoming Error Packet Header (IIO_IIEPH1/IIO_IIEPH2) - */ -#define IIEPH1_VALID (1UL << 44) -#define IIEPH1_OVERRUN (1UL << 40) -#define IIEPH1_ERR_TYPE_SHFT 32 -#define IIEPH1_ERR_TYPE_MASK 0xf -#define IIEPH1_SOURCE_SHFT 20 -#define IIEPH1_SOURCE_MASK 11 -#define IIEPH1_SUPPL_SHFT 8 -#define IIEPH1_SUPPL_MASK 11 -#define IIEPH1_CMD_SHFT 0 -#define IIEPH1_CMD_MASK 7 - -#define IIEPH2_TAIL (1UL << 40) -#define IIEPH2_ADDRESS_SHFT 0 -#define IIEPH2_ADDRESS_MASK 38 - -#define IIEPH1_ERR_SHORT_REQ 2 -#define IIEPH1_ERR_SHORT_REPLY 3 -#define IIEPH1_ERR_LONG_REQ 4 -#define IIEPH1_ERR_LONG_REPLY 5 - -/* - * IO Error Clear register bit field definitions - */ -#define IECLR_PI1_FWD_INT (1UL << 31) /* clear PI1_FORWARD_INT in iidsr */ -#define IECLR_PI0_FWD_INT (1UL << 30) /* clear PI0_FORWARD_INT in iidsr */ -#define IECLR_SPUR_RD_HDR (1UL << 29) /* clear valid bit in ixss reg */ -#define IECLR_BTE1 (1UL << 18) /* clear bte error 1 */ -#define IECLR_BTE0 (1UL << 17) /* clear bte error 0 */ -#define IECLR_CRAZY (1UL << 16) /* clear crazy bit in wstat reg */ -#define IECLR_PRB_F (1UL << 15) /* clear err bit in PRB_F reg */ -#define IECLR_PRB_E (1UL << 14) /* clear err bit in PRB_E reg */ -#define IECLR_PRB_D (1UL << 13) /* clear err bit in PRB_D reg */ -#define IECLR_PRB_C (1UL << 12) /* clear err bit in PRB_C reg */ -#define IECLR_PRB_B (1UL << 11) /* clear err bit in PRB_B reg */ -#define IECLR_PRB_A (1UL << 10) /* clear err bit in PRB_A reg */ -#define IECLR_PRB_9 (1UL << 9) /* clear err bit in PRB_9 reg */ -#define IECLR_PRB_8 (1UL << 8) /* clear err bit in PRB_8 reg */ -#define IECLR_PRB_0 (1UL << 0) /* clear err bit in PRB_0 reg */ - -/* - * IIO CRB control register Fields: IIO_ICCR - */ -#define IIO_ICCR_PENDING (0x10000) -#define IIO_ICCR_CMD_MASK (0xFF) -#define IIO_ICCR_CMD_SHFT (7) -#define IIO_ICCR_CMD_NOP (0x0) /* No Op */ -#define IIO_ICCR_CMD_WAKE (0x100) /* Reactivate CRB entry and process */ -#define IIO_ICCR_CMD_TIMEOUT (0x200) /* Make CRB timeout & mark invalid */ -#define IIO_ICCR_CMD_EJECT (0x400) /* Contents of entry written to memory - * via a WB - */ -#define IIO_ICCR_CMD_FLUSH (0x800) - -/* - * - * CRB Register description. - * - * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING - * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING - * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING - * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING - * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING - * - * Many of the fields in CRB are status bits used by hardware - * for implementation of the protocol. It's very dangerous to - * mess around with the CRB registers. - * - * It's OK to read the CRB registers and try to make sense out of the - * fields in CRB. - * - * Updating CRB requires all activities in Hub IIO to be quiesced. - * otherwise, a write to CRB could corrupt other CRB entries. - * CRBs are here only as a back door peek to shub IIO's status. - * Quiescing implies no dmas no PIOs - * either directly from the cpu or from sn0net. - * this is not something that can be done easily. So, AVOID updating - * CRBs. - */ - -#ifndef __ASSEMBLY__ - -/* - * Easy access macros for CRBs, all 5 registers (A-E) - */ -typedef ii_icrb0_a_u_t icrba_t; -#define a_sidn ii_icrb0_a_fld_s.ia_sidn -#define a_tnum ii_icrb0_a_fld_s.ia_tnum -#define a_addr ii_icrb0_a_fld_s.ia_addr -#define a_valid ii_icrb0_a_fld_s.ia_vld -#define a_iow ii_icrb0_a_fld_s.ia_iow -#define a_regvalue ii_icrb0_a_regval - -typedef ii_icrb0_b_u_t icrbb_t; -#define b_use_old ii_icrb0_b_fld_s.ib_use_old -#define b_imsgtype ii_icrb0_b_fld_s.ib_imsgtype -#define b_imsg ii_icrb0_b_fld_s.ib_imsg -#define b_initiator ii_icrb0_b_fld_s.ib_init -#define b_exc ii_icrb0_b_fld_s.ib_exc -#define b_ackcnt ii_icrb0_b_fld_s.ib_ack_cnt -#define b_resp ii_icrb0_b_fld_s.ib_resp -#define b_ack ii_icrb0_b_fld_s.ib_ack -#define b_hold ii_icrb0_b_fld_s.ib_hold -#define b_wb ii_icrb0_b_fld_s.ib_wb -#define b_intvn ii_icrb0_b_fld_s.ib_intvn -#define b_stall_ib ii_icrb0_b_fld_s.ib_stall_ib -#define b_stall_int ii_icrb0_b_fld_s.ib_stall__intr -#define b_stall_bte_0 ii_icrb0_b_fld_s.ib_stall__bte_0 -#define b_stall_bte_1 ii_icrb0_b_fld_s.ib_stall__bte_1 -#define b_error ii_icrb0_b_fld_s.ib_error -#define b_ecode ii_icrb0_b_fld_s.ib_errcode -#define b_lnetuce ii_icrb0_b_fld_s.ib_ln_uce -#define b_mark ii_icrb0_b_fld_s.ib_mark -#define b_xerr ii_icrb0_b_fld_s.ib_xt_err -#define b_regvalue ii_icrb0_b_regval - -typedef ii_icrb0_c_u_t icrbc_t; -#define c_suppl ii_icrb0_c_fld_s.ic_suppl -#define c_barrop ii_icrb0_c_fld_s.ic_bo -#define c_doresp ii_icrb0_c_fld_s.ic_resprqd -#define c_gbr ii_icrb0_c_fld_s.ic_gbr -#define c_btenum ii_icrb0_c_fld_s.ic_bte_num -#define c_cohtrans ii_icrb0_c_fld_s.ic_ct -#define c_xtsize ii_icrb0_c_fld_s.ic_size -#define c_source ii_icrb0_c_fld_s.ic_source -#define c_regvalue ii_icrb0_c_regval - - -typedef ii_icrb0_d_u_t icrbd_t; -#define d_sleep ii_icrb0_d_fld_s.id_sleep -#define d_pricnt ii_icrb0_d_fld_s.id_pr_cnt -#define d_pripsc ii_icrb0_d_fld_s.id_pr_psc -#define d_bteop ii_icrb0_d_fld_s.id_bte_op -#define d_bteaddr ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names*/ -#define d_benable ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names*/ -#define d_regvalue ii_icrb0_d_regval - -typedef ii_icrb0_e_u_t icrbe_t; -#define icrbe_ctxtvld ii_icrb0_e_fld_s.ie_cvld -#define icrbe_toutvld ii_icrb0_e_fld_s.ie_tvld -#define icrbe_context ii_icrb0_e_fld_s.ie_context -#define icrbe_timeout ii_icrb0_e_fld_s.ie_timeout -#define e_regvalue ii_icrb0_e_regval - -#endif /* __ASSEMBLY__ */ - -/* Number of widgets supported by shub */ -#define HUB_NUM_WIDGET 9 -#define HUB_WIDGET_ID_MIN 0x8 -#define HUB_WIDGET_ID_MAX 0xf - -#define HUB_WIDGET_PART_NUM 0xc120 -#define MAX_HUBS_PER_XBOW 2 - -#ifndef __ASSEMBLY__ -/* A few more #defines for backwards compatibility */ -#define iprb_t ii_iprb0_u_t -#define iprb_regval ii_iprb0_regval -#define iprb_mult_err ii_iprb0_fld_s.i_mult_err -#define iprb_spur_rd ii_iprb0_fld_s.i_spur_rd -#define iprb_spur_wr ii_iprb0_fld_s.i_spur_wr -#define iprb_rd_to ii_iprb0_fld_s.i_rd_to -#define iprb_ovflow ii_iprb0_fld_s.i_of_cnt -#define iprb_error ii_iprb0_fld_s.i_error -#define iprb_ff ii_iprb0_fld_s.i_f -#define iprb_mode ii_iprb0_fld_s.i_m -#define iprb_bnakctr ii_iprb0_fld_s.i_nb -#define iprb_anakctr ii_iprb0_fld_s.i_na -#define iprb_xtalkctr ii_iprb0_fld_s.i_c -#endif - -#define LNK_STAT_WORKING 0x2 /* LLP is working */ - -#define IIO_WSTAT_ECRAZY (1ULL << 32) /* Hub gone crazy */ -#define IIO_WSTAT_TXRETRY (1ULL << 9) /* Hub Tx Retry timeout */ -#define IIO_WSTAT_TXRETRY_MASK (0x7F) /* should be 0xFF?? */ -#define IIO_WSTAT_TXRETRY_SHFT (16) -#define IIO_WSTAT_TXRETRY_CNT(w) (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \ - IIO_WSTAT_TXRETRY_MASK) - -/* Number of II perf. counters we can multiplex at once */ - -#define IO_PERF_SETS 32 - -#ifdef __KERNEL__ -#include <asm/sn/dmamap.h> -#include <asm/sn/driver.h> -#include <asm/sn/xtalk/xtalk.h> - -/* Bit for the widget in inbound access register */ -#define IIO_IIWA_WIDGET(_w) ((uint64_t)(1ULL << _w)) -/* Bit for the widget in outbound access register */ -#define IIO_IOWA_WIDGET(_w) ((uint64_t)(1ULL << _w)) - -/* NOTE: The following define assumes that we are going to get - * widget numbers from 8 thru F and the device numbers within - * widget from 0 thru 7. - */ -#define IIO_IIDEM_WIDGETDEV_MASK(w, d) ((uint64_t)(1ULL << (8 * ((w) - 8) + (d)))) - -/* IO Interrupt Destination Register */ -#define IIO_IIDSR_SENT_SHIFT 28 -#define IIO_IIDSR_SENT_MASK 0x30000000 -#define IIO_IIDSR_ENB_SHIFT 24 -#define IIO_IIDSR_ENB_MASK 0x01000000 -#define IIO_IIDSR_NODE_SHIFT 9 -#define IIO_IIDSR_NODE_MASK 0x000ff700 -#define IIO_IIDSR_PI_ID_SHIFT 8 -#define IIO_IIDSR_PI_ID_MASK 0x00000100 -#define IIO_IIDSR_LVL_SHIFT 0 -#define IIO_IIDSR_LVL_MASK 0x000000ff - -/* Xtalk timeout threshhold register (IIO_IXTT) */ -#define IXTT_RRSP_TO_SHFT 55 /* read response timeout */ -#define IXTT_RRSP_TO_MASK (0x1FULL << IXTT_RRSP_TO_SHFT) -#define IXTT_RRSP_PS_SHFT 32 /* read responsed TO prescalar */ -#define IXTT_RRSP_PS_MASK (0x7FFFFFULL << IXTT_RRSP_PS_SHFT) -#define IXTT_TAIL_TO_SHFT 0 /* tail timeout counter threshold */ -#define IXTT_TAIL_TO_MASK (0x3FFFFFFULL << IXTT_TAIL_TO_SHFT) - -/* - * The IO LLP control status register and widget control register - */ - -typedef union hubii_wcr_u { - uint64_t wcr_reg_value; - struct { - uint64_t wcr_widget_id: 4, /* LLP crossbar credit */ - wcr_tag_mode: 1, /* Tag mode */ - wcr_rsvd1: 8, /* Reserved */ - wcr_xbar_crd: 3, /* LLP crossbar credit */ - wcr_f_bad_pkt: 1, /* Force bad llp pkt enable */ - wcr_dir_con: 1, /* widget direct connect */ - wcr_e_thresh: 5, /* elasticity threshold */ - wcr_rsvd: 41; /* unused */ - } wcr_fields_s; -} hubii_wcr_t; - -#define iwcr_dir_con wcr_fields_s.wcr_dir_con - -/* The structures below are defined to extract and modify the ii -performance registers */ - -/* io_perf_sel allows the caller to specify what tests will be - performed */ - -typedef union io_perf_sel { - uint64_t perf_sel_reg; - struct { - uint64_t perf_ippr0 : 4, - perf_ippr1 : 4, - perf_icct : 8, - perf_rsvd : 48; - } perf_sel_bits; -} io_perf_sel_t; - -/* io_perf_cnt is to extract the count from the shub registers. Due to - hardware problems there is only one counter, not two. */ - -typedef union io_perf_cnt { - uint64_t perf_cnt; - struct { - uint64_t perf_cnt : 20, - perf_rsvd2 : 12, - perf_rsvd1 : 32; - } perf_cnt_bits; - -} io_perf_cnt_t; - -typedef union iprte_a { - shubreg_t entry; - struct { - shubreg_t i_rsvd_1 : 3; - shubreg_t i_addr : 38; - shubreg_t i_init : 3; - shubreg_t i_source : 8; - shubreg_t i_rsvd : 2; - shubreg_t i_widget : 4; - shubreg_t i_to_cnt : 5; - shubreg_t i_vld : 1; - } iprte_fields; -} iprte_a_t; - - -/* PIO MANAGEMENT */ -typedef struct hub_piomap_s *hub_piomap_t; - -extern hub_piomap_t -hub_piomap_alloc(vertex_hdl_t dev, /* set up mapping for this device */ - device_desc_t dev_desc, /* device descriptor */ - iopaddr_t xtalk_addr, /* map for this xtalk_addr range */ - size_t byte_count, - size_t byte_count_max, /* maximum size of a mapping */ - unsigned flags); /* defined in sys/pio.h */ - -extern void hub_piomap_free(hub_piomap_t hub_piomap); - -extern caddr_t -hub_piomap_addr(hub_piomap_t hub_piomap, /* mapping resources */ - iopaddr_t xtalk_addr, /* map for this xtalk addr */ - size_t byte_count); /* map this many bytes */ - -extern void -hub_piomap_done(hub_piomap_t hub_piomap); - -extern caddr_t -hub_piotrans_addr( vertex_hdl_t dev, /* translate to this device */ - device_desc_t dev_desc, /* device descriptor */ - iopaddr_t xtalk_addr, /* Crosstalk address */ - size_t byte_count, /* map this many bytes */ - unsigned flags); /* (currently unused) */ - -/* DMA MANAGEMENT */ -typedef struct hub_dmamap_s *hub_dmamap_t; - -extern hub_dmamap_t -hub_dmamap_alloc( vertex_hdl_t dev, /* set up mappings for dev */ - device_desc_t dev_desc, /* device descriptor */ - size_t byte_count_max, /* max size of a mapping */ - unsigned flags); /* defined in dma.h */ - -extern void -hub_dmamap_free(hub_dmamap_t dmamap); - -extern iopaddr_t -hub_dmamap_addr( hub_dmamap_t dmamap, /* use mapping resources */ - paddr_t paddr, /* map for this address */ - size_t byte_count); /* map this many bytes */ - -extern void -hub_dmamap_done( hub_dmamap_t dmamap); /* done w/ mapping resources */ - -extern iopaddr_t -hub_dmatrans_addr( vertex_hdl_t dev, /* translate for this device */ - device_desc_t dev_desc, /* device descriptor */ - paddr_t paddr, /* system physical address */ - size_t byte_count, /* length */ - unsigned flags); /* defined in dma.h */ - -extern void -hub_dmamap_drain( hub_dmamap_t map); - -extern void -hub_dmaaddr_drain( vertex_hdl_t vhdl, - paddr_t addr, - size_t bytes); - - -/* INTERRUPT MANAGEMENT */ -typedef struct hub_intr_s *hub_intr_t; - -extern hub_intr_t -hub_intr_alloc( vertex_hdl_t dev, /* which device */ - device_desc_t dev_desc, /* device descriptor */ - vertex_hdl_t owner_dev); /* owner of this interrupt */ - -extern hub_intr_t -hub_intr_alloc_nothd(vertex_hdl_t dev, /* which device */ - device_desc_t dev_desc, /* device descriptor */ - vertex_hdl_t owner_dev); /* owner of this interrupt */ - -extern void -hub_intr_free(hub_intr_t intr_hdl); - -extern int -hub_intr_connect( hub_intr_t intr_hdl, /* xtalk intr resource hndl */ - intr_func_t intr_func, /* xtalk intr handler */ - void *intr_arg, /* arg to intr handler */ - xtalk_intr_setfunc_t setfunc, /* func to set intr hw */ - void *setfunc_arg); /* arg to setfunc */ - -extern void -hub_intr_disconnect(hub_intr_t intr_hdl); - - -/* CONFIGURATION MANAGEMENT */ - -extern void -hub_provider_startup(vertex_hdl_t hub); - -extern void -hub_provider_shutdown(vertex_hdl_t hub); - -#define HUB_PIO_CONVEYOR 0x1 /* PIO in conveyor belt mode */ -#define HUB_PIO_FIRE_N_FORGET 0x2 /* PIO in fire-and-forget mode */ - -/* Flags that make sense to hub_widget_flags_set */ -#define HUB_WIDGET_FLAGS ( \ - HUB_PIO_CONVEYOR | \ - HUB_PIO_FIRE_N_FORGET \ - ) - - -typedef int hub_widget_flags_t; - -/* Set the PIO mode for a widget. */ -extern int hub_widget_flags_set(nasid_t nasid, - xwidgetnum_t widget_num, - hub_widget_flags_t flags); - -/* Error Handling. */ -extern int hub_ioerror_handler(vertex_hdl_t, int, int, struct io_error_s *); -extern int kl_ioerror_handler(cnodeid_t, cnodeid_t, cpuid_t, - int, paddr_t, caddr_t, ioerror_mode_t); -#endif /* _KERNEL */ -#endif /* _ASM_IA64_SN_SN2_SHUBIO_H */ - diff --git a/include/asm-ia64/sn/sn2/slotnum.h b/include/asm-ia64/sn/sn2/slotnum.h deleted file mode 100644 index 03146d5e6cbd..000000000000 --- a/include/asm-ia64/sn/sn2/slotnum.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (c) 1992-1997,2001-2003 Silicon Graphics, Inc. All rights reserved. - */ - -#ifndef _ASM_IA64_SN_SN2_SLOTNUM_H -#define _ASM_IA64_SN_SN2_SLOTNUM_H - -#define SLOTNUM_MAXLENGTH 16 - -/* - * This file defines IO widget to slot/device assignments. - */ - - -/* This determines module to pnode mapping. */ - -#define NODESLOTS_PER_MODULE 1 -#define NODESLOTS_PER_MODULE_SHFT 1 - -#define SLOTNUM_NODE_CLASS 0x00 /* Node */ -#define SLOTNUM_ROUTER_CLASS 0x10 /* Router */ -#define SLOTNUM_XTALK_CLASS 0x20 /* Xtalk */ -#define SLOTNUM_MIDPLANE_CLASS 0x30 /* Midplane */ -#define SLOTNUM_XBOW_CLASS 0x40 /* Xbow */ -#define SLOTNUM_KNODE_CLASS 0x50 /* Kego node */ -#define SLOTNUM_PCI_CLASS 0x60 /* PCI widgets on XBridge */ -#define SLOTNUM_INVALID_CLASS 0xf0 /* Invalid */ - -#define SLOTNUM_CLASS_MASK 0xf0 -#define SLOTNUM_SLOT_MASK 0x0f - -#define SLOTNUM_GETCLASS(_sn) ((_sn) & SLOTNUM_CLASS_MASK) -#define SLOTNUM_GETSLOT(_sn) ((_sn) & SLOTNUM_SLOT_MASK) - - -#endif /* _ASM_IA64_SN_SN2_SLOTNUM_H */ diff --git a/include/asm-ia64/sn/sn2/sn_private.h b/include/asm-ia64/sn/sn2/sn_private.h deleted file mode 100644 index bee0da86f108..000000000000 --- a/include/asm-ia64/sn/sn2/sn_private.h +++ /dev/null @@ -1,245 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_SN2_SN_PRIVATE_H -#define _ASM_IA64_SN_SN2_SN_PRIVATE_H - -#include <linux/wait.h> -#include <asm/sn/nodepda.h> -#include <asm/sn/io.h> -#include <asm/sn/iograph.h> -#include <asm/sn/xtalk/xwidget.h> -#include <asm/sn/xtalk/xtalk_private.h> - -extern nasid_t master_nasid; - -/* promif.c */ -extern void he_arcs_set_vectors(void); -extern void mem_init(void); -extern void cpu_unenable(cpuid_t); -extern nasid_t get_lowest_nasid(void); -extern unsigned long get_master_bridge_base(void); -extern int check_nasid_equiv(nasid_t, nasid_t); -extern char get_console_pcislot(void); - -extern int is_master_baseio_nasid_widget(nasid_t test_nasid, - xwidgetnum_t test_wid); - -/* memsupport.c */ -extern void poison_state_alter_range(unsigned long start, int len, int poison); -extern int memory_present(paddr_t); -extern int memory_read_accessible(paddr_t); -extern int memory_write_accessible(paddr_t); -extern void memory_set_access(paddr_t, int, int); -extern void show_dir_state(paddr_t, void (*)(char *, ...)); -extern void check_dir_state(nasid_t, int, void (*)(char *, ...)); -extern void set_dir_owner(paddr_t, int); -extern void set_dir_state(paddr_t, int); -extern void set_dir_state_POISONED(paddr_t); -extern void set_dir_state_UNOWNED(paddr_t); -extern int is_POISONED_dir_state(paddr_t); -extern int is_UNOWNED_dir_state(paddr_t); -#ifdef LATER -extern void get_dir_ent(paddr_t paddr, int *state, - uint64_t * vec_ptr, hubreg_t * elo); -#endif - -/* intr.c */ -extern void intr_unreserve_level(cpuid_t cpu, int level); -extern int intr_connect_level(cpuid_t cpu, int bit); -extern int intr_disconnect_level(cpuid_t cpu, int bit); -extern cpuid_t intr_heuristic(vertex_hdl_t dev, int req_bit, int *resp_bit); -extern void intr_block_bit(cpuid_t cpu, int bit); -extern void intr_unblock_bit(cpuid_t cpu, int bit); -extern void setrtvector(intr_func_t); -extern void install_cpuintr(cpuid_t cpu); -extern void install_dbgintr(cpuid_t cpu); -extern void install_tlbintr(cpuid_t cpu); -extern void hub_migrintr_init(cnodeid_t /*cnode */ ); -extern int cause_intr_connect(int level, intr_func_t handler, - unsigned int intr_spl_mask); -extern int cause_intr_disconnect(int level); -extern void intr_dumpvec(cnodeid_t cnode, void (*pf) (char *, ...)); - -/* error_dump.c */ -extern char *hub_rrb_err_type[]; -extern char *hub_wrb_err_type[]; - -void nmi_dump(void); -void install_cpu_nmi_handler(int slice); - -/* klclock.c */ -extern void hub_rtc_init(cnodeid_t); - -/* bte.c */ -void bte_lateinit(void); -void bte_wait_for_xfer_completion(void *); - -/* klgraph.c */ -void klhwg_add_all_nodes(vertex_hdl_t); -void klhwg_add_all_modules(vertex_hdl_t); - -/* klidbg.c */ -void install_klidbg_functions(void); - -/* klnuma.c */ -extern void replicate_kernel_text(int numnodes); -extern unsigned long get_freemem_start(cnodeid_t cnode); -extern void setup_replication_mask(int maxnodes); - -/* init.c */ -extern cnodeid_t get_compact_nodeid(void); /* get compact node id */ -extern void init_platform_nodepda(nodepda_t * npda, cnodeid_t node); -extern int is_fine_dirmode(void); -extern void update_node_information(cnodeid_t); - -/* shubio.c */ -extern void hubio_init(void); -extern void hub_merge_clean(nasid_t nasid); -extern void hub_set_piomode(nasid_t nasid, int conveyor); - -/* shuberror.c */ -extern void hub_error_init(cnodeid_t); -extern void dump_error_spool(cpuid_t cpu, void (*pf) (char *, ...)); -extern void hubni_error_handler(char *, int); -extern int check_ni_errors(void); - -/* Used for debugger to signal upper software a breakpoint has taken place */ - -extern void *debugger_update; -extern unsigned long debugger_stopped; - -/* - * piomap, created by shub_pio_alloc. - * xtalk_info MUST BE FIRST, since this structure is cast to a - * xtalk_piomap_s by generic xtalk routines. - */ -struct hub_piomap_s { - struct xtalk_piomap_s hpio_xtalk_info; /* standard crosstalk pio info */ - vertex_hdl_t hpio_hub; /* which shub's mapping registers are set up */ - short hpio_holdcnt; /* count of current users of bigwin mapping */ - char hpio_bigwin_num; /* if big window map, which one */ - int hpio_flags; /* defined below */ -}; -/* hub_piomap flags */ -#define HUB_PIOMAP_IS_VALID 0x1 -#define HUB_PIOMAP_IS_BIGWINDOW 0x2 -#define HUB_PIOMAP_IS_FIXED 0x4 - -#define hub_piomap_xt_piomap(hp) (&hp->hpio_xtalk_info) -#define hub_piomap_hub_v(hp) (hp->hpio_hub) -#define hub_piomap_winnum(hp) (hp->hpio_bigwin_num) - -/* - * dmamap, created by shub_pio_alloc. - * xtalk_info MUST BE FIRST, since this structure is cast to a - * xtalk_dmamap_s by generic xtalk routines. - */ -struct hub_dmamap_s { - struct xtalk_dmamap_s hdma_xtalk_info; /* standard crosstalk dma info */ - vertex_hdl_t hdma_hub; /* which shub we go through */ - int hdma_flags; /* defined below */ -}; -/* shub_dmamap flags */ -#define HUB_DMAMAP_IS_VALID 0x1 -#define HUB_DMAMAP_USED 0x2 -#define HUB_DMAMAP_IS_FIXED 0x4 - -/* - * interrupt handle, created by shub_intr_alloc. - * xtalk_info MUST BE FIRST, since this structure is cast to a - * xtalk_intr_s by generic xtalk routines. - */ -struct hub_intr_s { - struct xtalk_intr_s i_xtalk_info; /* standard crosstalk intr info */ - cpuid_t i_cpuid; /* which cpu */ - int i_bit; /* which bit */ - int i_flags; -}; -/* flag values */ -#define HUB_INTR_IS_ALLOCED 0x1 /* for debug: allocated */ -#define HUB_INTR_IS_CONNECTED 0x4 /* for debug: connected to a software driver */ - -typedef struct hubinfo_s { - nodepda_t *h_nodepda; /* pointer to node's private data area */ - cnodeid_t h_cnodeid; /* compact nodeid */ - nasid_t h_nasid; /* nasid */ - - /* structures for PIO management */ - xwidgetnum_t h_widgetid; /* my widget # (as viewed from xbow) */ - struct hub_piomap_s h_small_window_piomap[HUB_WIDGET_ID_MAX + 1]; - wait_queue_head_t h_bwwait; /* wait for big window to free */ - spinlock_t h_bwlock; /* guard big window piomap's */ - spinlock_t h_crblock; /* gaurd CRB error handling */ - int h_num_big_window_fixed; /* count number of FIXED maps */ - struct hub_piomap_s h_big_window_piomap[HUB_NUM_BIG_WINDOW]; - hub_intr_t hub_ii_errintr; -} *hubinfo_t; - -#define hubinfo_get(vhdl, infoptr) ((void)hwgraph_info_get_LBL \ - (vhdl, INFO_LBL_NODE_INFO, (arbitrary_info_t *)infoptr)) - -#define hubinfo_set(vhdl, infoptr) (void)hwgraph_info_add_LBL \ - (vhdl, INFO_LBL_NODE_INFO, (arbitrary_info_t)infoptr) - -#define hubinfo_to_hubv(hinfo, hub_v) (hinfo->h_nodepda->node_vertex) - -/* - * Hub info PIO map access functions. - */ -#define hubinfo_bwin_piomap_get(hinfo, win) \ - (&hinfo->h_big_window_piomap[win]) -#define hubinfo_swin_piomap_get(hinfo, win) \ - (&hinfo->h_small_window_piomap[win]) - -/* cpu-specific information stored under INFO_LBL_CPU_INFO */ -typedef struct cpuinfo_s { - cpuid_t ci_cpuid; /* CPU ID */ -} *cpuinfo_t; - -#define cpuinfo_get(vhdl, infoptr) ((void)hwgraph_info_get_LBL \ - (vhdl, INFO_LBL_CPU_INFO, (arbitrary_info_t *)infoptr)) - -#define cpuinfo_set(vhdl, infoptr) (void)hwgraph_info_add_LBL \ - (vhdl, INFO_LBL_CPU_INFO, (arbitrary_info_t)infoptr) - -/* Special initialization function for xswitch vertices created during startup. */ -extern void xswitch_vertex_init(vertex_hdl_t xswitch); - -extern xtalk_provider_t hub_provider; -extern int numionodes; - -/* du.c */ -int ducons_write(char *buf, int len); - -/* memerror.c */ - -extern void install_eccintr(cpuid_t cpu); -extern void memerror_get_stats(cnodeid_t cnode, - int *bank_stats, int *bank_stats_max); -extern void probe_md_errors(nasid_t); -/* sysctlr.c */ -extern void sysctlr_init(void); -extern void sysctlr_power_off(int sdonly); -extern void sysctlr_keepalive(void); - -#define valid_cpuid(_x) (((_x) >= 0) && ((_x) < maxcpus)) - -/* Useful definitions to get the memory dimm given a physical - * address. - */ -#define paddr_dimm(_pa) ((_pa & MD_BANK_MASK) >> MD_BANK_SHFT) -#define paddr_cnode(_pa) (nasid_to_cnodeid(NASID_GET(_pa))) -extern void membank_pathname_get(paddr_t, char *); - -extern void crbx(nasid_t nasid, void (*pf) (char *, ...)); -void bootstrap(void); - -/* sndrv.c */ -extern int sndrv_attach(vertex_hdl_t vertex); - -#endif /* _ASM_IA64_SN_SN2_SN_PRIVATE_H */ diff --git a/include/asm-ia64/sn/sn_cpuid.h b/include/asm-ia64/sn/sn_cpuid.h index 529e4f5a497c..2fa88edac08f 100644 --- a/include/asm-ia64/sn/sn_cpuid.h +++ b/include/asm-ia64/sn/sn_cpuid.h @@ -7,7 +7,6 @@ * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved. */ - #ifndef _ASM_IA64_SN_SN_CPUID_H #define _ASM_IA64_SN_SN_CPUID_H @@ -84,6 +83,7 @@ */ #ifndef CONFIG_SMP +#define cpu_logical_id(cpu) 0 #define cpu_physical_id(cpuid) ((ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff) #endif @@ -93,7 +93,7 @@ */ #define cpu_physical_id_to_nasid(cpi) ((cpi) &0xfff) #define cpu_physical_id_to_slice(cpi) ((cpi>>12) & 3) -#define cpu_physical_id_to_coherence_id(cpi) (cpu_physical_id_to_nasid(cpi) >> 9) +#define cpu_physical_id_to_coherence_id(cpi) (((cpi) & 0x600) >> 9) #define get_nasid() ((ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xfff) #define get_slice() ((ia64_getreg(_IA64_REG_CR_LID) >> 28) & 0xf) #define get_node_number(addr) (((unsigned long)(addr)>>38) & 0x7ff) @@ -177,7 +177,8 @@ extern short physical_node_map[]; /* indexed by nasid to get cnode */ * cpuid_to_coherence_id - convert a cpuid to the coherence domain id it * resides on */ -#define cpuid_to_coherence_id(cpuid) cpu_physical_id_to_coherence_id(cpu_physical_id(cpuid)) +#define cpuid_to_coherence_id(cpuid) cpu_physical_id_to_coherence_id(cpu_physical_id(cpuid)) + #endif /* _ASM_IA64_SN_SN_CPUID_H */ diff --git a/include/asm-ia64/sn/sn_fru.h b/include/asm-ia64/sn/sn_fru.h index 3a9582b1313f..8c21ac3f0156 100644 --- a/include/asm-ia64/sn/sn_fru.h +++ b/include/asm-ia64/sn/sn_fru.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992-1997,1999-2003 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992-1997,1999-2004 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_SN_FRU_H #define _ASM_IA64_SN_SN_FRU_H diff --git a/include/asm-ia64/sn/sn_private.h b/include/asm-ia64/sn/sn_private.h deleted file mode 100644 index 897b8310dbf6..000000000000 --- a/include/asm-ia64/sn/sn_private.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_SN_PRIVATE_H -#define _ASM_IA64_SN_SN_PRIVATE_H - -#include <asm/sn/sn2/sn_private.h> - -#endif /* _ASM_IA64_SN_SN_PRIVATE_H */ diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h index 3d3d324a229a..4628a0f33a03 100644 --- a/include/asm-ia64/sn/sn_sal.h +++ b/include/asm-ia64/sn/sn_sal.h @@ -17,8 +17,6 @@ #include <asm/sn/sn_cpuid.h> #include <asm/sn/arch.h> #include <asm/sn/nodepda.h> -#include <asm/sn/klconfig.h> - // SGI Specific Calls #define SN_SAL_POD_MODE 0x02000001 @@ -62,7 +60,19 @@ #define SN_SAL_SYSCTL_IOBRICK_PCI_OP 0x02000042 // reentrant #define SN_SAL_IROUTER_OP 0x02000043 +#define SN_SAL_IOIF_INTERRUPT 0x0200004a #define SN_SAL_HWPERF_OP 0x02000050 // lock +#define SN_SAL_IOIF_ERROR_INTERRUPT 0x02000051 + +#define SN_SAL_IOIF_SLOT_ENABLE 0x02000053 +#define SN_SAL_IOIF_SLOT_DISABLE 0x02000054 +#define SN_SAL_IOIF_GET_HUBDEV_INFO 0x02000055 +#define SN_SAL_IOIF_GET_PCIBUS_INFO 0x02000056 +#define SN_SAL_IOIF_GET_PCIDEV_INFO 0x02000057 +#define SN_SAL_IOIF_GET_WIDGET_DMAFLUSH_LIST 0x02000058 + +#define SN_SAL_HUB_ERROR_INTERRUPT 0x02000060 + /* * Service-specific constants @@ -77,16 +87,9 @@ #define SAL_CONSOLE_INTR_XMIT 1 /* output interrupt */ #define SAL_CONSOLE_INTR_RECV 2 /* input interrupt */ -#ifdef CONFIG_HOTPLUG_PCI_SGI -/* power up / power down / reset a PCI slot or bus */ -#define SAL_SYSCTL_PCI_POWER_UP 0 -#define SAL_SYSCTL_PCI_POWER_DOWN 1 -#define SAL_SYSCTL_PCI_RESET 2 - -/* what type of I/O brick? */ -#define SAL_SYSCTL_IO_XTALK 0 /* connected via a compute node */ - -#endif /* CONFIG_HOTPLUG_PCI_SGI */ +/* interrupt handling */ +#define SAL_INTR_ALLOC 1 +#define SAL_INTR_FREE 2 /* * IRouter (i.e. generalized system controller) operations @@ -116,19 +119,6 @@ #define SALRET_INVALID_ARG (-2) #define SALRET_ERROR (-3) -/* - * SN_SAL_SET_ERROR_HANDLING_FEATURES bit settings - */ -enum -{ - /* if "rz always" is set, have the mca slaves call os_init_slave */ - SN_SAL_EHF_MCA_SLV_TO_OS_INIT_SLV=0, - /* do not rz on tlb checks, even if "rz always" is set */ - SN_SAL_EHF_NO_RZ_TLBC, - /* do not rz on PIO reads to I/O space, even if "rz always" is set */ - SN_SAL_EHF_NO_RZ_IO_READ, -}; - /** * sn_sal_rev_major - get the major SGI SAL revision number @@ -164,10 +154,8 @@ sn_sal_rev_minor(void) * Specify the minimum PROM revsion required for this kernel. * Note that they're stored in hex format... */ -#define SN_SAL_MIN_MAJOR 0x3 /* SN2 kernels need at least PROM 3.40 */ -#define SN_SAL_MIN_MINOR 0x40 - -u64 ia64_sn_probe_io_slot(long paddr, long size, void *data_ptr); +#define SN_SAL_MIN_MAJOR 0x4 /* SN2 kernels need at least PROM 4.0 */ +#define SN_SAL_MIN_MINOR 0x0 /* * Returns the master console nasid, if the call fails, return an illegal @@ -325,7 +313,7 @@ ia64_sn_plat_specific_err_print(int (*hook)(const char*, ...), char *rec) ret_stuff.v0 = 0; ret_stuff.v1 = 0; ret_stuff.v2 = 0; - SAL_CALL_REENTRANT(ret_stuff, SN_SAL_PRINT_ERROR, (uint64_t)hook, (uint64_t)rec, 0, 0, 0, 0, 0); + SAL_CALL_NOLOCK(ret_stuff, SN_SAL_PRINT_ERROR, (uint64_t)hook, (uint64_t)rec, 0, 0, 0, 0, 0); return ret_stuff.status; } @@ -646,12 +634,12 @@ sn_change_memprotect(u64 paddr, u64 len, u64 perms, u64 *nasid_array) unsigned long irq_flags; cnodeid = nasid_to_cnodeid(get_node_number(paddr)); - spin_lock(&NODEPDA(cnodeid)->bist_lock); + // spin_lock(&NODEPDA(cnodeid)->bist_lock); local_irq_save(irq_flags); SAL_CALL_NOLOCK(ret_stuff, SN_SAL_MEMPROTECT, paddr, len, nasid_array, perms, 0, 0, 0); local_irq_restore(irq_flags); - spin_unlock(&NODEPDA(cnodeid)->bist_lock); + // spin_unlock(&NODEPDA(cnodeid)->bist_lock); return ret_stuff.status; } #define SN_MEMPROT_ACCESS_CLASS_0 0x14a080 @@ -695,7 +683,7 @@ ia64_sn_fru_capture(void) */ static inline u64 ia64_sn_sysctl_iobrick_pci_op(nasid_t n, u64 connection_type, - u64 bus, slotid_t slot, + u64 bus, char slot, u64 action) { struct ia64_sal_retval rv = {0, 0, 0, 0}; @@ -707,26 +695,6 @@ ia64_sn_sysctl_iobrick_pci_op(nasid_t n, u64 connection_type, return 0; } -/* - * Tell the prom how the OS wants to handle specific error features. - * It takes an array of 7 u64. - */ -static inline u64 -ia64_sn_set_error_handling_features(const u64 *feature_bits) -{ - struct ia64_sal_retval rv = {0, 0, 0, 0}; - - SAL_CALL_REENTRANT(rv, SN_SAL_SET_ERROR_HANDLING_FEATURES, - feature_bits[0], - feature_bits[1], - feature_bits[2], - feature_bits[3], - feature_bits[4], - feature_bits[5], - feature_bits[6]); - return rv.status; -} - /* * Open a subchannel for sending arbitrary data to the system diff --git a/include/asm-ia64/sn/sndrv.h b/include/asm-ia64/sn/sndrv.h index 8af1f1d56957..aa00d42cde32 100644 --- a/include/asm-ia64/sn/sndrv.h +++ b/include/asm-ia64/sn/sndrv.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 2002-2003 Silicon Graphics, Inc. All Rights Reserved. + * Copyright (c) 2002-2004 Silicon Graphics, Inc. All Rights Reserved. */ #ifndef _ASM_IA64_SN_SNDRV_H @@ -35,18 +35,6 @@ #define SNDRV_SYNERGY_ENABLE 34 #define SNDRV_SYNERGY_FREQ 35 -/* see shubstats_ioctl() */ -#define SNDRV_SHUB_INFOSIZE 40 -#define SNDRV_SHUB_CONFIGURE 41 -#define SNDRV_SHUB_RESETSTATS 42 -#define SNDRV_SHUB_GETSTATS 43 -#define SNDRV_SHUB_GETNASID 44 -#define SNDRV_SHUB_GETMMR32 45 -#define SNDRV_SHUB_GETMMR64 46 -#define SNDRV_SHUB_GETMMR64_IO 47 -#define SNDRV_SHUB_PUTMMR64 48 -#define SNDRV_SHUB_PUTMMR64_IO 49 - /* Devices */ #define SNDRV_UKNOWN_DEVICE -1 #define SNDRV_ROUTER_DEVICE 1 diff --git a/include/asm-ia64/sn/vector.h b/include/asm-ia64/sn/vector.h deleted file mode 100644 index 6b39c7ace4b5..000000000000 --- a/include/asm-ia64/sn/vector.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_VECTOR_H -#define _ASM_IA64_SN_VECTOR_H - -#define NET_VEC_NULL ((net_vec_t) 0) -#define NET_VEC_BAD ((net_vec_t) -1) - -#define VEC_POLLS_W 128 /* Polls before write times out */ -#define VEC_POLLS_R 128 /* Polls before read times out */ -#define VEC_POLLS_X 128 /* Polls before exch times out */ - -#define VEC_RETRIES_W 8 /* Retries before write fails */ -#define VEC_RETRIES_R 8 /* Retries before read fails */ -#define VEC_RETRIES_X 4 /* Retries before exch fails */ - -#define NET_ERROR_NONE 0 /* No error */ -#define NET_ERROR_HARDWARE (-1) /* Hardware error */ -#define NET_ERROR_OVERRUN (-2) /* Extra response(s) */ -#define NET_ERROR_REPLY (-3) /* Reply parms mismatch */ -#define NET_ERROR_ADDRESS (-4) /* Addr error response */ -#define NET_ERROR_COMMAND (-5) /* Cmd error response */ -#define NET_ERROR_PROT (-6) /* Prot error response */ -#define NET_ERROR_TIMEOUT (-7) /* Too many retries */ -#define NET_ERROR_VECTOR (-8) /* Invalid vector/path */ -#define NET_ERROR_ROUTERLOCK (-9) /* Timeout locking rtr */ -#define NET_ERROR_INVAL (-10) /* Invalid vector request */ - -#ifndef __ASSEMBLY__ -#include <linux/types.h> -#include <asm/sn/types.h> - -typedef uint64_t net_reg_t; -typedef uint64_t net_vec_t; - -int vector_write(net_vec_t dest, - int write_id, int address, - uint64_t value); - -int vector_read(net_vec_t dest, - int write_id, int address, - uint64_t *value); - -int vector_write_node(net_vec_t dest, nasid_t nasid, - int write_id, int address, - uint64_t value); - -int vector_read_node(net_vec_t dest, nasid_t nasid, - int write_id, int address, - uint64_t *value); - -int vector_length(net_vec_t vec); -net_vec_t vector_get(net_vec_t vec, int n); -net_vec_t vector_prefix(net_vec_t vec, int n); -net_vec_t vector_modify(net_vec_t entry, int n, int route); -net_vec_t vector_reverse(net_vec_t vec); -net_vec_t vector_concat(net_vec_t vec1, net_vec_t vec2); - -char *net_errmsg(int); - -#ifndef _STANDALONE -int hub_vector_write(cnodeid_t cnode, net_vec_t vector, int writeid, - int addr, net_reg_t value); -int hub_vector_read(cnodeid_t cnode, net_vec_t vector, int writeid, - int addr, net_reg_t *value); -#endif - -#endif /* __ASSEMBLY__ */ - -#endif /* _ASM_IA64_SN_VECTOR_H */ diff --git a/include/asm-ia64/sn/xtalk/xbow.h b/include/asm-ia64/sn/xtalk/xbow.h deleted file mode 100644 index b1019a81bcc9..000000000000 --- a/include/asm-ia64/sn/xtalk/xbow.h +++ /dev/null @@ -1,675 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All Rights Reserved. - */ -#ifndef _ASM_IA64_SN_XTALK_XBOW_H -#define _ASM_IA64_SN_XTALK_XBOW_H - -/* - * xbow.h - header file for crossbow chip and xbow section of xbridge - */ - -#include <asm/types.h> -#include <asm/sn/xtalk/xtalk.h> -#include <asm/sn/xtalk/xwidget.h> -#include <asm/sn/xtalk/xswitch.h> -#ifndef __ASSEMBLY__ -#include <asm/sn/xtalk/xbow_info.h> -#endif - - -#define XBOW_DRV_PREFIX "xbow_" - -/* The crossbow chip supports 8 8/16 bits I/O ports, numbered 0x8 through 0xf. - * It also implements the widget 0 address space and register set. - */ -#define XBOW_PORT_0 0x0 -#define XBOW_PORT_8 0x8 -#define XBOW_PORT_9 0x9 -#define XBOW_PORT_A 0xa -#define XBOW_PORT_B 0xb -#define XBOW_PORT_C 0xc -#define XBOW_PORT_D 0xd -#define XBOW_PORT_E 0xe -#define XBOW_PORT_F 0xf - -#define MAX_XBOW_PORTS 8 /* number of ports on xbow chip */ -#define BASE_XBOW_PORT XBOW_PORT_8 /* Lowest external port */ -#define MAX_PORT_NUM 0x10 /* maximum port number + 1 */ -#define XBOW_WIDGET_ID 0 /* xbow is itself widget 0 */ - -#define XBOW_HUBLINK_LOW 0xa -#define XBOW_HUBLINK_HIGH 0xb - -#define XBOW_PEER_LINK(link) (link == XBOW_HUBLINK_LOW) ? \ - XBOW_HUBLINK_HIGH : XBOW_HUBLINK_LOW - - -#define XBOW_CREDIT 4 - -#define MAX_XBOW_NAME 16 - -#ifndef __ASSEMBLY__ -typedef uint32_t xbowreg_t; - -/* Register set for each xbow link */ -typedef volatile struct xb_linkregs_s { -/* - * we access these through synergy unswizzled space, so the address - * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.) - * That's why we put the register first and filler second. - */ - xbowreg_t link_ibf; - xbowreg_t filler0; /* filler for proper alignment */ - xbowreg_t link_control; - xbowreg_t filler1; - xbowreg_t link_status; - xbowreg_t filler2; - xbowreg_t link_arb_upper; - xbowreg_t filler3; - xbowreg_t link_arb_lower; - xbowreg_t filler4; - xbowreg_t link_status_clr; - xbowreg_t filler5; - xbowreg_t link_reset; - xbowreg_t filler6; - xbowreg_t link_aux_status; - xbowreg_t filler7; -} xb_linkregs_t; - -typedef volatile struct xbow_s { - /* standard widget configuration 0x000000-0x000057 */ - widget_cfg_t xb_widget; /* 0x000000 */ - - /* helper fieldnames for accessing bridge widget */ - -#define xb_wid_id xb_widget.w_id -#define xb_wid_stat xb_widget.w_status -#define xb_wid_err_upper xb_widget.w_err_upper_addr -#define xb_wid_err_lower xb_widget.w_err_lower_addr -#define xb_wid_control xb_widget.w_control -#define xb_wid_req_timeout xb_widget.w_req_timeout -#define xb_wid_int_upper xb_widget.w_intdest_upper_addr -#define xb_wid_int_lower xb_widget.w_intdest_lower_addr -#define xb_wid_err_cmdword xb_widget.w_err_cmd_word -#define xb_wid_llp xb_widget.w_llp_cfg -#define xb_wid_stat_clr xb_widget.w_tflush - -/* - * we access these through synergy unswizzled space, so the address - * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.) - * That's why we put the register first and filler second. - */ - /* xbow-specific widget configuration 0x000058-0x0000FF */ - xbowreg_t xb_wid_arb_reload; /* 0x00005C */ - xbowreg_t _pad_000058; - xbowreg_t xb_perf_ctr_a; /* 0x000064 */ - xbowreg_t _pad_000060; - xbowreg_t xb_perf_ctr_b; /* 0x00006c */ - xbowreg_t _pad_000068; - xbowreg_t xb_nic; /* 0x000074 */ - xbowreg_t _pad_000070; - - /* Xbridge only */ - xbowreg_t xb_w0_rst_fnc; /* 0x00007C */ - xbowreg_t _pad_000078; - xbowreg_t xb_l8_rst_fnc; /* 0x000084 */ - xbowreg_t _pad_000080; - xbowreg_t xb_l9_rst_fnc; /* 0x00008c */ - xbowreg_t _pad_000088; - xbowreg_t xb_la_rst_fnc; /* 0x000094 */ - xbowreg_t _pad_000090; - xbowreg_t xb_lb_rst_fnc; /* 0x00009c */ - xbowreg_t _pad_000098; - xbowreg_t xb_lc_rst_fnc; /* 0x0000a4 */ - xbowreg_t _pad_0000a0; - xbowreg_t xb_ld_rst_fnc; /* 0x0000ac */ - xbowreg_t _pad_0000a8; - xbowreg_t xb_le_rst_fnc; /* 0x0000b4 */ - xbowreg_t _pad_0000b0; - xbowreg_t xb_lf_rst_fnc; /* 0x0000bc */ - xbowreg_t _pad_0000b8; - xbowreg_t xb_lock; /* 0x0000c4 */ - xbowreg_t _pad_0000c0; - xbowreg_t xb_lock_clr; /* 0x0000cc */ - xbowreg_t _pad_0000c8; - /* end of Xbridge only */ - xbowreg_t _pad_0000d0[12]; - - /* Link Specific Registers, port 8..15 0x000100-0x000300 */ - xb_linkregs_t xb_link_raw[MAX_XBOW_PORTS]; -#define xb_link(p) xb_link_raw[(p) & (MAX_XBOW_PORTS - 1)] - -} xbow_t; - -/* Configuration structure which describes each xbow link */ -typedef struct xbow_cfg_s { - int xb_port; /* port number (0-15) */ - int xb_flags; /* port software flags */ - short xb_shift; /* shift for arb reg (mask is 0xff) */ - short xb_ul; /* upper or lower arb reg */ - int xb_pad; /* use this later (pad to ptr align) */ - xb_linkregs_t *xb_linkregs; /* pointer to link registers */ - widget_cfg_t *xb_widget; /* pointer to widget registers */ - char xb_name[MAX_XBOW_NAME]; /* port name */ - xbowreg_t xb_sh_arb_upper; /* shadow upper arb register */ - xbowreg_t xb_sh_arb_lower; /* shadow lower arb register */ -} xbow_cfg_t; - -#define XB_FLAGS_EXISTS 0x1 /* device exists */ -#define XB_FLAGS_MASTER 0x2 -#define XB_FLAGS_SLAVE 0x0 -#define XB_FLAGS_GBR 0x4 -#define XB_FLAGS_16BIT 0x8 -#define XB_FLAGS_8BIT 0x0 - -/* get xbow config information for port p */ -#define XB_CONFIG(p) xbow_cfg[xb_ports[p]] - -/* is widget port number valid? (based on version 7.0 of xbow spec) */ -#define XBOW_WIDGET_IS_VALID(wid) ((wid) >= XBOW_PORT_8 && (wid) <= XBOW_PORT_F) - -/* whether to use upper or lower arbitration register, given source widget id */ -#define XBOW_ARB_IS_UPPER(wid) ((wid) >= XBOW_PORT_8 && (wid) <= XBOW_PORT_B) -#define XBOW_ARB_IS_LOWER(wid) ((wid) >= XBOW_PORT_C && (wid) <= XBOW_PORT_F) - -/* offset of arbitration register, given source widget id */ -#define XBOW_ARB_OFF(wid) (XBOW_ARB_IS_UPPER(wid) ? 0x1c : 0x24) - -#endif /* __ASSEMBLY__ */ - -#define XBOW_WID_ID WIDGET_ID -#define XBOW_WID_STAT WIDGET_STATUS -#define XBOW_WID_ERR_UPPER WIDGET_ERR_UPPER_ADDR -#define XBOW_WID_ERR_LOWER WIDGET_ERR_LOWER_ADDR -#define XBOW_WID_CONTROL WIDGET_CONTROL -#define XBOW_WID_REQ_TO WIDGET_REQ_TIMEOUT -#define XBOW_WID_INT_UPPER WIDGET_INTDEST_UPPER_ADDR -#define XBOW_WID_INT_LOWER WIDGET_INTDEST_LOWER_ADDR -#define XBOW_WID_ERR_CMDWORD WIDGET_ERR_CMD_WORD -#define XBOW_WID_LLP WIDGET_LLP_CFG -#define XBOW_WID_STAT_CLR WIDGET_TFLUSH -#define XBOW_WID_ARB_RELOAD 0x5c -#define XBOW_WID_PERF_CTR_A 0x64 -#define XBOW_WID_PERF_CTR_B 0x6c -#define XBOW_WID_NIC 0x74 - -/* Xbridge only */ -#define XBOW_W0_RST_FNC 0x00007C -#define XBOW_L8_RST_FNC 0x000084 -#define XBOW_L9_RST_FNC 0x00008c -#define XBOW_LA_RST_FNC 0x000094 -#define XBOW_LB_RST_FNC 0x00009c -#define XBOW_LC_RST_FNC 0x0000a4 -#define XBOW_LD_RST_FNC 0x0000ac -#define XBOW_LE_RST_FNC 0x0000b4 -#define XBOW_LF_RST_FNC 0x0000bc -#define XBOW_RESET_FENCE(x) ((x) > 7 && (x) < 16) ? \ - (XBOW_W0_RST_FNC + ((x) - 7) * 8) : \ - ((x) == 0) ? XBOW_W0_RST_FNC : 0 -#define XBOW_LOCK 0x0000c4 -#define XBOW_LOCK_CLR 0x0000cc -/* End of Xbridge only */ - -/* used only in ide, but defined here within the reserved portion */ -/* of the widget0 address space (before 0xf4) */ -#define XBOW_WID_UNDEF 0xe4 - -/* xbow link register set base, legal value for x is 0x8..0xf */ -#define XB_LINK_BASE 0x100 -#define XB_LINK_OFFSET 0x40 -#define XB_LINK_REG_BASE(x) (XB_LINK_BASE + ((x) & (MAX_XBOW_PORTS - 1)) * XB_LINK_OFFSET) - -#define XB_LINK_IBUF_FLUSH(x) (XB_LINK_REG_BASE(x) + 0x4) -#define XB_LINK_CTRL(x) (XB_LINK_REG_BASE(x) + 0xc) -#define XB_LINK_STATUS(x) (XB_LINK_REG_BASE(x) + 0x14) -#define XB_LINK_ARB_UPPER(x) (XB_LINK_REG_BASE(x) + 0x1c) -#define XB_LINK_ARB_LOWER(x) (XB_LINK_REG_BASE(x) + 0x24) -#define XB_LINK_STATUS_CLR(x) (XB_LINK_REG_BASE(x) + 0x2c) -#define XB_LINK_RESET(x) (XB_LINK_REG_BASE(x) + 0x34) -#define XB_LINK_AUX_STATUS(x) (XB_LINK_REG_BASE(x) + 0x3c) - -/* link_control(x) */ -#define XB_CTRL_LINKALIVE_IE 0x80000000 /* link comes alive */ - /* reserved: 0x40000000 */ -#define XB_CTRL_PERF_CTR_MODE_MSK 0x30000000 /* perf counter mode */ -#define XB_CTRL_IBUF_LEVEL_MSK 0x0e000000 /* input packet buffer level */ -#define XB_CTRL_8BIT_MODE 0x01000000 /* force link into 8 bit mode */ -#define XB_CTRL_BAD_LLP_PKT 0x00800000 /* force bad LLP packet */ -#define XB_CTRL_WIDGET_CR_MSK 0x007c0000 /* LLP widget credit mask */ -#define XB_CTRL_WIDGET_CR_SHFT 18 /* LLP widget credit shift */ -#define XB_CTRL_ILLEGAL_DST_IE 0x00020000 /* illegal destination */ -#define XB_CTRL_OALLOC_IBUF_IE 0x00010000 /* overallocated input buffer */ - /* reserved: 0x0000fe00 */ -#define XB_CTRL_BNDWDTH_ALLOC_IE 0x00000100 /* bandwidth alloc */ -#define XB_CTRL_RCV_CNT_OFLOW_IE 0x00000080 /* rcv retry overflow */ -#define XB_CTRL_XMT_CNT_OFLOW_IE 0x00000040 /* xmt retry overflow */ -#define XB_CTRL_XMT_MAX_RTRY_IE 0x00000020 /* max transmit retry */ -#define XB_CTRL_RCV_IE 0x00000010 /* receive */ -#define XB_CTRL_XMT_RTRY_IE 0x00000008 /* transmit retry */ - /* reserved: 0x00000004 */ -#define XB_CTRL_MAXREQ_TOUT_IE 0x00000002 /* maximum request timeout */ -#define XB_CTRL_SRC_TOUT_IE 0x00000001 /* source timeout */ - -/* link_status(x) */ -#define XB_STAT_LINKALIVE XB_CTRL_LINKALIVE_IE - /* reserved: 0x7ff80000 */ -#define XB_STAT_MULTI_ERR 0x00040000 /* multi error */ -#define XB_STAT_ILLEGAL_DST_ERR XB_CTRL_ILLEGAL_DST_IE -#define XB_STAT_OALLOC_IBUF_ERR XB_CTRL_OALLOC_IBUF_IE -#define XB_STAT_BNDWDTH_ALLOC_ID_MSK 0x0000ff00 /* port bitmask */ -#define XB_STAT_RCV_CNT_OFLOW_ERR XB_CTRL_RCV_CNT_OFLOW_IE -#define XB_STAT_XMT_CNT_OFLOW_ERR XB_CTRL_XMT_CNT_OFLOW_IE -#define XB_STAT_XMT_MAX_RTRY_ERR XB_CTRL_XMT_MAX_RTRY_IE -#define XB_STAT_RCV_ERR XB_CTRL_RCV_IE -#define XB_STAT_XMT_RTRY_ERR XB_CTRL_XMT_RTRY_IE - /* reserved: 0x00000004 */ -#define XB_STAT_MAXREQ_TOUT_ERR XB_CTRL_MAXREQ_TOUT_IE -#define XB_STAT_SRC_TOUT_ERR XB_CTRL_SRC_TOUT_IE - -/* link_aux_status(x) */ -#define XB_AUX_STAT_RCV_CNT 0xff000000 -#define XB_AUX_STAT_XMT_CNT 0x00ff0000 -#define XB_AUX_STAT_TOUT_DST 0x0000ff00 -#define XB_AUX_LINKFAIL_RST_BAD 0x00000040 -#define XB_AUX_STAT_PRESENT 0x00000020 -#define XB_AUX_STAT_PORT_WIDTH 0x00000010 - /* reserved: 0x0000000f */ - -/* - * link_arb_upper/link_arb_lower(x), (reg) should be the link_arb_upper - * register if (x) is 0x8..0xb, link_arb_lower if (x) is 0xc..0xf - */ -#define XB_ARB_GBR_MSK 0x1f -#define XB_ARB_RR_MSK 0x7 -#define XB_ARB_GBR_SHFT(x) (((x) & 0x3) * 8) -#define XB_ARB_RR_SHFT(x) (((x) & 0x3) * 8 + 5) -#define XB_ARB_GBR_CNT(reg,x) ((reg) >> XB_ARB_GBR_SHFT(x) & XB_ARB_GBR_MSK) -#define XB_ARB_RR_CNT(reg,x) ((reg) >> XB_ARB_RR_SHFT(x) & XB_ARB_RR_MSK) - -/* XBOW_WID_STAT */ -#define XB_WID_STAT_LINK_INTR_SHFT (24) -#define XB_WID_STAT_LINK_INTR_MASK (0xFF << XB_WID_STAT_LINK_INTR_SHFT) -#define XB_WID_STAT_LINK_INTR(x) (0x1 << (((x)&7) + XB_WID_STAT_LINK_INTR_SHFT)) -#define XB_WID_STAT_WIDGET0_INTR 0x00800000 -#define XB_WID_STAT_SRCID_MASK 0x000003c0 /* Xbridge only */ -#define XB_WID_STAT_REG_ACC_ERR 0x00000020 -#define XB_WID_STAT_RECV_TOUT 0x00000010 /* Xbridge only */ -#define XB_WID_STAT_ARB_TOUT 0x00000008 /* Xbridge only */ -#define XB_WID_STAT_XTALK_ERR 0x00000004 -#define XB_WID_STAT_DST_TOUT 0x00000002 /* Xbridge only */ -#define XB_WID_STAT_MULTI_ERR 0x00000001 - -#define XB_WID_STAT_SRCID_SHFT 6 - -/* XBOW_WID_CONTROL */ -#define XB_WID_CTRL_REG_ACC_IE XB_WID_STAT_REG_ACC_ERR -#define XB_WID_CTRL_RECV_TOUT XB_WID_STAT_RECV_TOUT -#define XB_WID_CTRL_ARB_TOUT XB_WID_STAT_ARB_TOUT -#define XB_WID_CTRL_XTALK_IE XB_WID_STAT_XTALK_ERR - -/* XBOW_WID_INT_UPPER */ -/* defined in xwidget.h for WIDGET_INTDEST_UPPER_ADDR */ - -/* XBOW WIDGET part number, in the ID register */ -#define XBOW_WIDGET_PART_NUM 0x0 /* crossbow */ -#define XXBOW_WIDGET_PART_NUM 0xd000 /* Xbridge */ -#define XBOW_WIDGET_MFGR_NUM 0x0 -#define XXBOW_WIDGET_MFGR_NUM 0x0 -#define PXBOW_WIDGET_PART_NUM 0xd100 /* PIC */ - -#define XBOW_REV_1_0 0x1 /* xbow rev 1.0 is "1" */ -#define XBOW_REV_1_1 0x2 /* xbow rev 1.1 is "2" */ -#define XBOW_REV_1_2 0x3 /* xbow rev 1.2 is "3" */ -#define XBOW_REV_1_3 0x4 /* xbow rev 1.3 is "4" */ -#define XBOW_REV_2_0 0x5 /* xbow rev 2.0 is "5" */ - -#define XXBOW_PART_REV_1_0 (XXBOW_WIDGET_PART_NUM << 4 | 0x1 ) -#define XXBOW_PART_REV_2_0 (XXBOW_WIDGET_PART_NUM << 4 | 0x2 ) - -/* XBOW_WID_ARB_RELOAD */ -#define XBOW_WID_ARB_RELOAD_INT 0x3f /* GBR reload interval */ - -#define IS_XBRIDGE_XBOW(wid) \ - (XWIDGET_PART_NUM(wid) == XXBOW_WIDGET_PART_NUM && \ - XWIDGET_MFG_NUM(wid) == XXBOW_WIDGET_MFGR_NUM) - -#define IS_PIC_XBOW(wid) \ - (XWIDGET_PART_NUM(wid) == PXBOW_WIDGET_PART_NUM && \ - XWIDGET_MFG_NUM(wid) == XXBOW_WIDGET_MFGR_NUM) - -#define XBOW_WAR_ENABLED(pv, widid) ((1 << XWIDGET_REV_NUM(widid)) & pv) - -#ifndef __ASSEMBLY__ -/* - * XBOW Widget 0 Register formats. - * Format for many of these registers are similar to the standard - * widget register format described as part of xtalk specification - * Standard widget register field format description is available in - * xwidget.h - * Following structures define the format for xbow widget 0 registers - */ -/* - * Xbow Widget 0 Command error word - */ -typedef union xbw0_cmdword_u { - xbowreg_t cmdword; - struct { - uint32_t rsvd:8, /* Reserved */ - barr:1, /* Barrier operation */ - error:1, /* Error Occured */ - vbpm:1, /* Virtual Backplane message */ - gbr:1, /* GBR enable ? */ - ds:2, /* Data size */ - ct:1, /* Is it a coherent transaction */ - tnum:5, /* Transaction Number */ - pactyp:4, /* Packet type: */ - srcid:4, /* Source ID number */ - destid:4; /* Desination ID number */ - - } xbw0_cmdfield; -} xbw0_cmdword_t; - -#define xbcmd_destid xbw0_cmdfield.destid -#define xbcmd_srcid xbw0_cmdfield.srcid -#define xbcmd_pactyp xbw0_cmdfield.pactyp -#define xbcmd_tnum xbw0_cmdfield.tnum -#define xbcmd_ct xbw0_cmdfield.ct -#define xbcmd_ds xbw0_cmdfield.ds -#define xbcmd_gbr xbw0_cmdfield.gbr -#define xbcmd_vbpm xbw0_cmdfield.vbpm -#define xbcmd_error xbw0_cmdfield.error -#define xbcmd_barr xbw0_cmdfield.barr - -/* - * Values for field PACTYP in xbow error command word - */ -#define XBCMDTYP_READREQ 0 /* Read Request packet */ -#define XBCMDTYP_READRESP 1 /* Read Response packet */ -#define XBCMDTYP_WRREQ_RESP 2 /* Write Request with response */ -#define XBCMDTYP_WRRESP 3 /* Write Response */ -#define XBCMDTYP_WRREQ_NORESP 4 /* Write request with No Response */ -#define XBCMDTYP_FETCHOP 6 /* Fetch & Op packet */ -#define XBCMDTYP_STOREOP 8 /* Store & Op packet */ -#define XBCMDTYP_SPLPKT_REQ 0xE /* Special packet request */ -#define XBCMDTYP_SPLPKT_RESP 0xF /* Special packet response */ - -/* - * Values for field ds (datasize) in xbow error command word - */ -#define XBCMDSZ_DOUBLEWORD 0 -#define XBCMDSZ_QUARTRCACHE 1 -#define XBCMDSZ_FULLCACHE 2 - -/* - * Xbow widget 0 Status register format. - */ - -typedef union xbw0_status_u { - xbowreg_t statusword; - struct { - uint32_t mult_err:1, /* Multiple error occurred */ - connect_tout:1, /* Connection timeout */ - xtalk_err:1, /* Xtalk pkt with error bit */ - /* End of Xbridge only */ - w0_arb_tout, /* arbiter timeout err */ - w0_recv_tout, /* receive timeout err */ - /* Xbridge only */ - regacc_err:1, /* Reg Access error */ - src_id:4, /* source id. Xbridge only */ - resvd1:13, - wid0intr:1; /* Widget 0 err intr */ - } xbw0_stfield; -} xbw0_status_t; - -#define xbst_linkXintr xbw0_stfield.linkXintr -#define xbst_w0intr xbw0_stfield.wid0intr -#define xbst_regacc_err xbw0_stfield.regacc_err -#define xbst_xtalk_err xbw0_stfield.xtalk_err -#define xbst_connect_tout xbw0_stfield.connect_tout -#define xbst_mult_err xbw0_stfield.mult_err -#define xbst_src_id xbw0_stfield.src_id /* Xbridge only */ -#define xbst_w0_recv_tout xbw0_stfield.w0_recv_tout /* Xbridge only */ -#define xbst_w0_arb_tout xbw0_stfield.w0_arb_tout /* Xbridge only */ - -/* - * Xbow widget 0 Control register format - */ - -typedef union xbw0_ctrl_u { - xbowreg_t ctrlword; - struct { - uint32_t - resvd3:1, - conntout_intr:1, - xtalkerr_intr:1, - w0_arg_tout_intr:1, /* Xbridge only */ - w0_recv_tout_intr:1, /* Xbridge only */ - accerr_intr:1, - enable_w0_tout_cntr:1, /* Xbridge only */ - enable_watchdog:1, /* Xbridge only */ - resvd1:24; - } xbw0_ctrlfield; -} xbw0_ctrl_t; - -typedef union xbow_linkctrl_u { - xbowreg_t xbl_ctrlword; - struct { - uint32_t srcto_intr:1, - maxto_intr:1, - rsvd3:1, - trx_retry_intr:1, - rcv_err_intr:1, - trx_max_retry_intr:1, - trxov_intr:1, - rcvov_intr:1, - bwalloc_intr:1, - rsvd2:7, - obuf_intr:1, - idest_intr:1, - llp_credit:5, - force_badllp:1, - send_bm8:1, - inbuf_level:3, - perf_mode:2, - rsvd1:1, - alive_intr:1; - - } xb_linkcontrol; -} xbow_linkctrl_t; - -#define xbctl_accerr_intr (xbw0_ctrlfield.accerr_intr) -#define xbctl_xtalkerr_intr (xbw0_ctrlfield.xtalkerr_intr) -#define xbctl_cnntout_intr (xbw0_ctrlfield.conntout_intr) - -#define XBW0_CTRL_ACCERR_INTR (1 << 5) -#define XBW0_CTRL_XTERR_INTR (1 << 2) -#define XBW0_CTRL_CONNTOUT_INTR (1 << 1) - -/* - * Xbow Link specific Registers structure definitions. - */ - -typedef union xbow_linkX_status_u { - xbowreg_t linkstatus; - struct { - uint32_t pkt_toutsrc:1, - pkt_toutconn:1, /* max_req_tout in Xbridge */ - pkt_toutdest:1, /* reserved in Xbridge */ - llp_xmitretry:1, - llp_rcverror:1, - llp_maxtxretry:1, - llp_txovflow:1, - llp_rxovflow:1, - bw_errport:8, /* BW allocation error port */ - ioe:1, /* Input overallocation error */ - illdest:1, - merror:1, - resvd1:12, - alive:1; - } xb_linkstatus; -} xbwX_stat_t; - -#define link_alive xb_linkstatus.alive -#define link_multierror xb_linkstatus.merror -#define link_illegal_dest xb_linkstatus.illdest -#define link_ioe xb_linkstatus.ioe -#define link_max_req_tout xb_linkstatus.pkt_toutconn /* Xbridge */ -#define link_pkt_toutconn xb_linkstatus.pkt_toutconn /* Xbow */ -#define link_pkt_toutdest xb_linkstatus.pkt_toutdest -#define link_pkt_toutsrc xb_linkstatus.pkt_toutsrc - -typedef union xbow_aux_linkX_status_u { - xbowreg_t aux_linkstatus; - struct { - uint32_t rsvd2:4, - bit_mode_8:1, - wid_present:1, - fail_mode:1, - rsvd1:1, - to_src_loc:8, - tx_retry_cnt:8, - rx_err_cnt:8; - } xb_aux_linkstatus; -} xbow_aux_link_status_t; - -typedef union xbow_perf_count_u { - xbowreg_t xb_counter_val; - struct { - uint32_t count:20, - link_select:3, - rsvd:9; - } xb_perf; -} xbow_perfcount_t; - -#define XBOW_COUNTER_MASK 0xFFFFF - -extern int xbow_widget_present(xbow_t * xbow, int port); - -extern xwidget_intr_preset_f xbow_intr_preset; -extern xswitch_reset_link_f xbow_reset_link; -void xbow_mlreset(xbow_t *); - -/* ======================================================================== - */ - -#ifdef MACROFIELD_LINE -/* - * This table forms a relation between the byte offset macros normally - * used for ASM coding and the calculated byte offsets of the fields - * in the C structure. - * - * See xbow_check.c xbow_html.c for further details. - */ -#ifndef MACROFIELD_LINE_BITFIELD -#define MACROFIELD_LINE_BITFIELD(m) /* ignored */ -#endif - -struct macrofield_s xbow_macrofield[] = -{ - - MACROFIELD_LINE(XBOW_WID_ID, xb_wid_id) - MACROFIELD_LINE(XBOW_WID_STAT, xb_wid_stat) - MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0xF)) - MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0xE)) - MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0xD)) - MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0xC)) - MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0xB)) - MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0xA)) - MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0x9)) - MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0x8)) - MACROFIELD_LINE_BITFIELD(XB_WID_STAT_WIDGET0_INTR) - MACROFIELD_LINE_BITFIELD(XB_WID_STAT_REG_ACC_ERR) - MACROFIELD_LINE_BITFIELD(XB_WID_STAT_XTALK_ERR) - MACROFIELD_LINE_BITFIELD(XB_WID_STAT_MULTI_ERR) - MACROFIELD_LINE(XBOW_WID_ERR_UPPER, xb_wid_err_upper) - MACROFIELD_LINE(XBOW_WID_ERR_LOWER, xb_wid_err_lower) - MACROFIELD_LINE(XBOW_WID_CONTROL, xb_wid_control) - MACROFIELD_LINE_BITFIELD(XB_WID_CTRL_REG_ACC_IE) - MACROFIELD_LINE_BITFIELD(XB_WID_CTRL_XTALK_IE) - MACROFIELD_LINE(XBOW_WID_REQ_TO, xb_wid_req_timeout) - MACROFIELD_LINE(XBOW_WID_INT_UPPER, xb_wid_int_upper) - MACROFIELD_LINE(XBOW_WID_INT_LOWER, xb_wid_int_lower) - MACROFIELD_LINE(XBOW_WID_ERR_CMDWORD, xb_wid_err_cmdword) - MACROFIELD_LINE(XBOW_WID_LLP, xb_wid_llp) - MACROFIELD_LINE(XBOW_WID_STAT_CLR, xb_wid_stat_clr) - MACROFIELD_LINE(XBOW_WID_ARB_RELOAD, xb_wid_arb_reload) - MACROFIELD_LINE(XBOW_WID_PERF_CTR_A, xb_perf_ctr_a) - MACROFIELD_LINE(XBOW_WID_PERF_CTR_B, xb_perf_ctr_b) - MACROFIELD_LINE(XBOW_WID_NIC, xb_nic) - MACROFIELD_LINE(XB_LINK_REG_BASE(8), xb_link(8)) - MACROFIELD_LINE(XB_LINK_IBUF_FLUSH(8), xb_link(8).link_ibf) - MACROFIELD_LINE(XB_LINK_CTRL(8), xb_link(8).link_control) - MACROFIELD_LINE_BITFIELD(XB_CTRL_LINKALIVE_IE) - MACROFIELD_LINE_BITFIELD(XB_CTRL_PERF_CTR_MODE_MSK) - MACROFIELD_LINE_BITFIELD(XB_CTRL_IBUF_LEVEL_MSK) - MACROFIELD_LINE_BITFIELD(XB_CTRL_8BIT_MODE) - MACROFIELD_LINE_BITFIELD(XB_CTRL_BAD_LLP_PKT) - MACROFIELD_LINE_BITFIELD(XB_CTRL_WIDGET_CR_MSK) - MACROFIELD_LINE_BITFIELD(XB_CTRL_ILLEGAL_DST_IE) - MACROFIELD_LINE_BITFIELD(XB_CTRL_OALLOC_IBUF_IE) - MACROFIELD_LINE_BITFIELD(XB_CTRL_BNDWDTH_ALLOC_IE) - MACROFIELD_LINE_BITFIELD(XB_CTRL_RCV_CNT_OFLOW_IE) - MACROFIELD_LINE_BITFIELD(XB_CTRL_XMT_CNT_OFLOW_IE) - MACROFIELD_LINE_BITFIELD(XB_CTRL_XMT_MAX_RTRY_IE) - MACROFIELD_LINE_BITFIELD(XB_CTRL_RCV_IE) - MACROFIELD_LINE_BITFIELD(XB_CTRL_XMT_RTRY_IE) - MACROFIELD_LINE_BITFIELD(XB_CTRL_MAXREQ_TOUT_IE) - MACROFIELD_LINE_BITFIELD(XB_CTRL_SRC_TOUT_IE) - MACROFIELD_LINE(XB_LINK_STATUS(8), xb_link(8).link_status) - MACROFIELD_LINE_BITFIELD(XB_STAT_LINKALIVE) - MACROFIELD_LINE_BITFIELD(XB_STAT_MULTI_ERR) - MACROFIELD_LINE_BITFIELD(XB_STAT_ILLEGAL_DST_ERR) - MACROFIELD_LINE_BITFIELD(XB_STAT_OALLOC_IBUF_ERR) - MACROFIELD_LINE_BITFIELD(XB_STAT_BNDWDTH_ALLOC_ID_MSK) - MACROFIELD_LINE_BITFIELD(XB_STAT_RCV_CNT_OFLOW_ERR) - MACROFIELD_LINE_BITFIELD(XB_STAT_XMT_CNT_OFLOW_ERR) - MACROFIELD_LINE_BITFIELD(XB_STAT_XMT_MAX_RTRY_ERR) - MACROFIELD_LINE_BITFIELD(XB_STAT_RCV_ERR) - MACROFIELD_LINE_BITFIELD(XB_STAT_XMT_RTRY_ERR) - MACROFIELD_LINE_BITFIELD(XB_STAT_MAXREQ_TOUT_ERR) - MACROFIELD_LINE_BITFIELD(XB_STAT_SRC_TOUT_ERR) - MACROFIELD_LINE(XB_LINK_ARB_UPPER(8), xb_link(8).link_arb_upper) - MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0xb)) - MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0xb)) - MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0xa)) - MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0xa)) - MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0x9)) - MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0x9)) - MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0x8)) - MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0x8)) - MACROFIELD_LINE(XB_LINK_ARB_LOWER(8), xb_link(8).link_arb_lower) - MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0xf)) - MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0xf)) - MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0xe)) - MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0xe)) - MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0xd)) - MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0xd)) - MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0xc)) - MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0xc)) - MACROFIELD_LINE(XB_LINK_STATUS_CLR(8), xb_link(8).link_status_clr) - MACROFIELD_LINE(XB_LINK_RESET(8), xb_link(8).link_reset) - MACROFIELD_LINE(XB_LINK_AUX_STATUS(8), xb_link(8).link_aux_status) - MACROFIELD_LINE_BITFIELD(XB_AUX_STAT_RCV_CNT) - MACROFIELD_LINE_BITFIELD(XB_AUX_STAT_XMT_CNT) - MACROFIELD_LINE_BITFIELD(XB_AUX_LINKFAIL_RST_BAD) - MACROFIELD_LINE_BITFIELD(XB_AUX_STAT_PRESENT) - MACROFIELD_LINE_BITFIELD(XB_AUX_STAT_PORT_WIDTH) - MACROFIELD_LINE_BITFIELD(XB_AUX_STAT_TOUT_DST) - MACROFIELD_LINE(XB_LINK_REG_BASE(0x8), xb_link(0x8)) - MACROFIELD_LINE(XB_LINK_REG_BASE(0x9), xb_link(0x9)) - MACROFIELD_LINE(XB_LINK_REG_BASE(0xA), xb_link(0xA)) - MACROFIELD_LINE(XB_LINK_REG_BASE(0xB), xb_link(0xB)) - MACROFIELD_LINE(XB_LINK_REG_BASE(0xC), xb_link(0xC)) - MACROFIELD_LINE(XB_LINK_REG_BASE(0xD), xb_link(0xD)) - MACROFIELD_LINE(XB_LINK_REG_BASE(0xE), xb_link(0xE)) - MACROFIELD_LINE(XB_LINK_REG_BASE(0xF), xb_link(0xF)) -}; /* xbow_macrofield[] */ - -#endif /* MACROFIELD_LINE */ - -#endif /* __ASSEMBLY__ */ -#endif /* _ASM_IA64_SN_XTALK_XBOW_H */ diff --git a/include/asm-ia64/sn/xtalk/xbow_info.h b/include/asm-ia64/sn/xtalk/xbow_info.h deleted file mode 100644 index d9db1367b163..000000000000 --- a/include/asm-ia64/sn/xtalk/xbow_info.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All Rights Reserved. - */ -#ifndef _ASM_IA64_SN_XTALK_XBOW_INFO_H -#define _ASM_IA64_SN_XTALK_XBOW_INFO_H - -#include <linux/types.h> - -#define XBOW_PERF_MODES 0x03 - -typedef struct xbow_link_status { - uint64_t rx_err_count; - uint64_t tx_retry_count; -} xbow_link_status_t; - - -#endif /* _ASM_IA64_SN_XTALK_XBOW_INFO_H */ diff --git a/include/asm-ia64/sn/xtalk/xswitch.h b/include/asm-ia64/sn/xtalk/xswitch.h deleted file mode 100644 index ce95afc24372..000000000000 --- a/include/asm-ia64/sn/xtalk/xswitch.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All Rights Reserved. - */ -#ifndef _ASM_IA64_SN_XTALK_XSWITCH_H -#define _ASM_IA64_SN_XTALK_XSWITCH_H - -/* - * xswitch.h - controls the format of the data - * provided by xswitch verticies back to the - * xtalk bus providers. - */ - -#ifndef __ASSEMBLY__ - -#include <asm/sn/xtalk/xtalk.h> - -typedef struct xswitch_info_s *xswitch_info_t; - -typedef int - xswitch_reset_link_f(vertex_hdl_t xconn); - -typedef struct xswitch_provider_s { - xswitch_reset_link_f *reset_link; -} xswitch_provider_t; - -extern void xswitch_provider_register(vertex_hdl_t sw_vhdl, xswitch_provider_t * xsw_fns); - -xswitch_reset_link_f xswitch_reset_link; - -extern xswitch_info_t xswitch_info_new(vertex_hdl_t vhdl); - -extern void xswitch_info_link_is_ok(xswitch_info_t xswitch_info, - xwidgetnum_t port); -extern void xswitch_info_vhdl_set(xswitch_info_t xswitch_info, - xwidgetnum_t port, - vertex_hdl_t xwidget); -extern void xswitch_info_master_assignment_set(xswitch_info_t xswitch_info, - xwidgetnum_t port, - vertex_hdl_t master_vhdl); - -extern xswitch_info_t xswitch_info_get(vertex_hdl_t vhdl); - -extern int xswitch_info_link_ok(xswitch_info_t xswitch_info, - xwidgetnum_t port); -extern vertex_hdl_t xswitch_info_vhdl_get(xswitch_info_t xswitch_info, - xwidgetnum_t port); -extern vertex_hdl_t xswitch_info_master_assignment_get(xswitch_info_t xswitch_info, - xwidgetnum_t port); - -#endif /* __ASSEMBLY__ */ - -#endif /* _ASM_IA64_SN_XTALK_XSWITCH_H */ diff --git a/include/asm-ia64/sn/xtalk/xtalk.h b/include/asm-ia64/sn/xtalk/xtalk.h deleted file mode 100644 index 5475454b7376..000000000000 --- a/include/asm-ia64/sn/xtalk/xtalk.h +++ /dev/null @@ -1,360 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992-1997, 2000-2003 Silicon Graphics, Inc. All Rights Reserved. - */ -#ifndef _ASM_IA64_SN_XTALK_XTALK_H -#define _ASM_IA64_SN_XTALK_XTALK_H -#include <linux/config.h> - -#ifdef __KERNEL__ -#include "asm/sn/sgi.h" -#endif - - -/* - * xtalk.h -- platform-independent crosstalk interface - */ -/* - * User-level device driver visible types - */ -typedef char xwidgetnum_t; /* xtalk widget number (0..15) */ - -#define XWIDGET_NONE (-1) - -typedef int xwidget_part_num_t; /* xtalk widget part number */ - -#define XWIDGET_PART_NUM_NONE (-1) - -typedef int xwidget_rev_num_t; /* xtalk widget revision number */ - -#define XWIDGET_REV_NUM_NONE (-1) - -typedef int xwidget_mfg_num_t; /* xtalk widget manufacturing ID */ - -#define XWIDGET_MFG_NUM_NONE (-1) - -typedef struct xtalk_piomap_s *xtalk_piomap_t; - -/* It is often convenient to fold the XIO target port - * number into the XIO address. - */ -#define XIO_NOWHERE (0xFFFFFFFFFFFFFFFFull) -#define XIO_ADDR_BITS (0x0000FFFFFFFFFFFFull) -#define XIO_PORT_BITS (0xF000000000000000ull) -#define XIO_PORT_SHIFT (60) - -#define XIO_PACKED(x) (((x)&XIO_PORT_BITS) != 0) -#define XIO_ADDR(x) ((x)&XIO_ADDR_BITS) -#define XIO_PORT(x) ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT)) -#define XIO_PACK(p,o) ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS)) - - -/* - * Kernel/driver only definitions - */ -#ifdef __KERNEL__ - -#include <asm/types.h> -#include <asm/sn/types.h> -#include <asm/sn/ioerror.h> -#include <asm/sn/driver.h> -#include <asm/sn/dmamap.h> - -struct xwidget_hwid_s; - -/* - * Acceptable flag bits for xtalk service calls - * - * XTALK_FIXED: require that mappings be established - * using fixed sharable resources; address - * translation results will be permanently - * available. (PIOMAP_FIXED and DMAMAP_FIXED are - * the same numeric value and are acceptable). - * XTALK_NOSLEEP: if any part of the operation would - * sleep waiting for resoruces, return an error - * instead. (PIOMAP_NOSLEEP and DMAMAP_NOSLEEP are - * the same numeric value and are acceptable). - */ -#define XTALK_FIXED DMAMAP_FIXED -#define XTALK_NOSLEEP DMAMAP_NOSLEEP - -/* PIO MANAGEMENT */ -typedef xtalk_piomap_t -xtalk_piomap_alloc_f (vertex_hdl_t dev, /* set up mapping for this device */ - device_desc_t dev_desc, /* device descriptor */ - iopaddr_t xtalk_addr, /* map for this xtalk_addr range */ - size_t byte_count, - size_t byte_count_max, /* maximum size of a mapping */ - unsigned int flags); /* defined in sys/pio.h */ -typedef void -xtalk_piomap_free_f (xtalk_piomap_t xtalk_piomap); - -typedef caddr_t -xtalk_piomap_addr_f (xtalk_piomap_t xtalk_piomap, /* mapping resources */ - iopaddr_t xtalk_addr, /* map for this xtalk address */ - size_t byte_count); /* map this many bytes */ - -typedef void -xtalk_piomap_done_f (xtalk_piomap_t xtalk_piomap); - -typedef caddr_t -xtalk_piotrans_addr_f (vertex_hdl_t dev, /* translate for this device */ - device_desc_t dev_desc, /* device descriptor */ - iopaddr_t xtalk_addr, /* Crosstalk address */ - size_t byte_count, /* map this many bytes */ - unsigned int flags); /* (currently unused) */ - -extern caddr_t -xtalk_pio_addr (vertex_hdl_t dev, /* translate for this device */ - device_desc_t dev_desc, /* device descriptor */ - iopaddr_t xtalk_addr, /* Crosstalk address */ - size_t byte_count, /* map this many bytes */ - xtalk_piomap_t *xtalk_piomapp, /* RETURNS mapping resources */ - unsigned int flags); /* (currently unused) */ - -/* DMA MANAGEMENT */ - -typedef struct xtalk_dmamap_s *xtalk_dmamap_t; - -typedef xtalk_dmamap_t -xtalk_dmamap_alloc_f (vertex_hdl_t dev, /* set up mappings for this device */ - device_desc_t dev_desc, /* device descriptor */ - size_t byte_count_max, /* max size of a mapping */ - unsigned int flags); /* defined in dma.h */ - -typedef void -xtalk_dmamap_free_f (xtalk_dmamap_t dmamap); - -typedef iopaddr_t -xtalk_dmamap_addr_f (xtalk_dmamap_t dmamap, /* use these mapping resources */ - paddr_t paddr, /* map for this address */ - size_t byte_count); /* map this many bytes */ - -typedef void -xtalk_dmamap_done_f (xtalk_dmamap_t dmamap); - -typedef iopaddr_t -xtalk_dmatrans_addr_f (vertex_hdl_t dev, /* translate for this device */ - device_desc_t dev_desc, /* device descriptor */ - paddr_t paddr, /* system physical address */ - size_t byte_count, /* length */ - unsigned int flags); - -typedef void -xtalk_dmamap_drain_f (xtalk_dmamap_t map); /* drain this map's channel */ - -typedef void -xtalk_dmaaddr_drain_f (vertex_hdl_t vhdl, /* drain channel from this device */ - paddr_t addr, /* to this physical address */ - size_t bytes); /* for this many bytes */ - -/* INTERRUPT MANAGEMENT */ - -/* - * A xtalk interrupt resource handle. When resources are allocated - * in order to satisfy a xtalk_intr_alloc request, a xtalk_intr handle - * is returned. xtalk_intr_connect associates a software handler with - - * these system resources. - */ -typedef struct xtalk_intr_s *xtalk_intr_t; - - -/* - * When a crosstalk device connects an interrupt, it passes in a function - * that knows how to set its xtalk interrupt register appropriately. The - * low-level interrupt code may invoke this function later in order to - * migrate an interrupt transparently to the device driver(s) that use this - * interrupt. - * - * The argument passed to this function contains enough information for a - * crosstalk device to (re-)target an interrupt. A function of this type - * must be supplied by every crosstalk driver. - */ -typedef int -xtalk_intr_setfunc_f (xtalk_intr_t intr_hdl); /* interrupt handle */ - -typedef xtalk_intr_t -xtalk_intr_alloc_f (vertex_hdl_t dev, /* which crosstalk device */ - device_desc_t dev_desc, /* device descriptor */ - vertex_hdl_t owner_dev); /* owner of this intr */ - -typedef void -xtalk_intr_free_f (xtalk_intr_t intr_hdl); - -typedef int -xtalk_intr_connect_f (xtalk_intr_t intr_hdl, /* xtalk intr resource handle */ - intr_func_t intr_func, /* xtalk intr handler */ - void *intr_arg, /* arg to intr handler */ - xtalk_intr_setfunc_f *setfunc, /* func to set intr hw */ - void *setfunc_arg); /* arg to setfunc */ - -typedef void -xtalk_intr_disconnect_f (xtalk_intr_t intr_hdl); - -typedef vertex_hdl_t -xtalk_intr_cpu_get_f (xtalk_intr_t intr_hdl); /* xtalk intr resource handle */ - -/* CONFIGURATION MANAGEMENT */ - -typedef void -xtalk_provider_startup_f (vertex_hdl_t xtalk_provider); - -typedef void -xtalk_provider_shutdown_f (vertex_hdl_t xtalk_provider); - -typedef void -xtalk_widgetdev_enable_f (vertex_hdl_t, int); - -typedef void -xtalk_widgetdev_shutdown_f (vertex_hdl_t, int); - -/* Error Management */ - -/* Early Action Support */ -typedef caddr_t -xtalk_early_piotrans_addr_f (xwidget_part_num_t part_num, - xwidget_mfg_num_t mfg_num, - int which, - iopaddr_t xtalk_addr, - size_t byte_count, - unsigned int flags); - -/* - * Adapters that provide a crosstalk interface adhere to this software interface. - */ -typedef struct xtalk_provider_s { - /* PIO MANAGEMENT */ - xtalk_piomap_alloc_f *piomap_alloc; - xtalk_piomap_free_f *piomap_free; - xtalk_piomap_addr_f *piomap_addr; - xtalk_piomap_done_f *piomap_done; - xtalk_piotrans_addr_f *piotrans_addr; - - /* DMA MANAGEMENT */ - xtalk_dmamap_alloc_f *dmamap_alloc; - xtalk_dmamap_free_f *dmamap_free; - xtalk_dmamap_addr_f *dmamap_addr; - xtalk_dmamap_done_f *dmamap_done; - xtalk_dmatrans_addr_f *dmatrans_addr; - xtalk_dmamap_drain_f *dmamap_drain; - xtalk_dmaaddr_drain_f *dmaaddr_drain; - - /* INTERRUPT MANAGEMENT */ - xtalk_intr_alloc_f *intr_alloc; - xtalk_intr_alloc_f *intr_alloc_nothd; - xtalk_intr_free_f *intr_free; - xtalk_intr_connect_f *intr_connect; - xtalk_intr_disconnect_f *intr_disconnect; - - /* CONFIGURATION MANAGEMENT */ - xtalk_provider_startup_f *provider_startup; - xtalk_provider_shutdown_f *provider_shutdown; -} xtalk_provider_t; - -/* Crosstalk devices use these standard Crosstalk provider interfaces */ -extern xtalk_piomap_alloc_f xtalk_piomap_alloc; -extern xtalk_piomap_free_f xtalk_piomap_free; -extern xtalk_piomap_addr_f xtalk_piomap_addr; -extern xtalk_piomap_done_f xtalk_piomap_done; -extern xtalk_piotrans_addr_f xtalk_piotrans_addr; -extern xtalk_dmamap_alloc_f xtalk_dmamap_alloc; -extern xtalk_dmamap_free_f xtalk_dmamap_free; -extern xtalk_dmamap_addr_f xtalk_dmamap_addr; -extern xtalk_dmamap_done_f xtalk_dmamap_done; -extern xtalk_dmatrans_addr_f xtalk_dmatrans_addr; -extern xtalk_dmamap_drain_f xtalk_dmamap_drain; -extern xtalk_dmaaddr_drain_f xtalk_dmaaddr_drain; -extern xtalk_intr_alloc_f xtalk_intr_alloc; -extern xtalk_intr_alloc_f xtalk_intr_alloc_nothd; -extern xtalk_intr_free_f xtalk_intr_free; -extern xtalk_intr_connect_f xtalk_intr_connect; -extern xtalk_intr_disconnect_f xtalk_intr_disconnect; -extern xtalk_intr_cpu_get_f xtalk_intr_cpu_get; -extern xtalk_provider_startup_f xtalk_provider_startup; -extern xtalk_provider_shutdown_f xtalk_provider_shutdown; -extern xtalk_widgetdev_enable_f xtalk_widgetdev_enable; -extern xtalk_widgetdev_shutdown_f xtalk_widgetdev_shutdown; -extern xtalk_early_piotrans_addr_f xtalk_early_piotrans_addr; - -/* error management */ - -extern int xtalk_error_handler(vertex_hdl_t, - int, - ioerror_mode_t, - ioerror_t *); - -/* - * Generic crosstalk interface, for use with all crosstalk providers - * and all crosstalk devices. - */ -typedef unchar xtalk_intr_vector_t; /* crosstalk interrupt vector (0..255) */ - -#define XTALK_INTR_VECTOR_NONE (xtalk_intr_vector_t)0 - -/* Generic crosstalk interrupt interfaces */ -extern vertex_hdl_t xtalk_intr_dev_get(xtalk_intr_t xtalk_intr); -extern xwidgetnum_t xtalk_intr_target_get(xtalk_intr_t xtalk_intr); -extern xtalk_intr_vector_t xtalk_intr_vector_get(xtalk_intr_t xtalk_intr); -extern iopaddr_t xtalk_intr_addr_get(xtalk_intr_t xtalk_intr); -extern vertex_hdl_t xtalk_intr_cpu_get(xtalk_intr_t xtalk_intr); -extern void *xtalk_intr_sfarg_get(xtalk_intr_t xtalk_intr); - -/* Generic crosstalk pio interfaces */ -extern vertex_hdl_t xtalk_pio_dev_get(xtalk_piomap_t xtalk_piomap); -extern xwidgetnum_t xtalk_pio_target_get(xtalk_piomap_t xtalk_piomap); -extern iopaddr_t xtalk_pio_xtalk_addr_get(xtalk_piomap_t xtalk_piomap); -extern size_t xtalk_pio_mapsz_get(xtalk_piomap_t xtalk_piomap); -extern caddr_t xtalk_pio_kvaddr_get(xtalk_piomap_t xtalk_piomap); - -/* Generic crosstalk dma interfaces */ -extern vertex_hdl_t xtalk_dma_dev_get(xtalk_dmamap_t xtalk_dmamap); -extern xwidgetnum_t xtalk_dma_target_get(xtalk_dmamap_t xtalk_dmamap); - -/* Register/unregister Crosstalk providers and get implementation handle */ -extern void xtalk_set_early_piotrans_addr(xtalk_early_piotrans_addr_f *); -extern void xtalk_provider_register(vertex_hdl_t provider, xtalk_provider_t *xtalk_fns); -extern void xtalk_provider_unregister(vertex_hdl_t provider); -extern xtalk_provider_t *xtalk_provider_fns_get(vertex_hdl_t provider); - -/* Crosstalk Switch generic layer, for use by initialization code */ -extern void xswitch_census(vertex_hdl_t xswitchv); -extern void xswitch_init_widgets(vertex_hdl_t xswitchv); - -/* early init interrupt management */ - -typedef void -xwidget_intr_preset_f (void *which_widget, - int which_widget_intr, - xwidgetnum_t targ, - iopaddr_t addr, - xtalk_intr_vector_t vect); - -typedef void -xtalk_intr_prealloc_f (void *which_xtalk, - xtalk_intr_vector_t xtalk_vector, - xwidget_intr_preset_f *preset_func, - void *which_widget, - int which_widget_intr); - -typedef void -xtalk_intr_preconn_f (void *which_xtalk, - xtalk_intr_vector_t xtalk_vector, - intr_func_t intr_func, - intr_arg_t intr_arg); - - -#define XTALK_ADDR_TO_UPPER(xtalk_addr) (((iopaddr_t)(xtalk_addr) >> 32) & 0xffff) -#define XTALK_ADDR_TO_LOWER(xtalk_addr) ((iopaddr_t)(xtalk_addr) & 0xffffffff) - -typedef xtalk_intr_setfunc_f *xtalk_intr_setfunc_t; - -typedef void xtalk_iter_f(vertex_hdl_t vhdl); - -extern void xtalk_iterate(char *prefix, xtalk_iter_f *func); - -#endif /* __KERNEL__ */ -#endif /* _ASM_IA64_SN_XTALK_XTALK_H */ diff --git a/include/asm-ia64/sn/xtalk/xtalk_private.h b/include/asm-ia64/sn/xtalk/xtalk_private.h deleted file mode 100644 index 332e2c2a4600..000000000000 --- a/include/asm-ia64/sn/xtalk/xtalk_private.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992-1997, 2000-2003 Silicon Graphics, Inc. All Rights Reserved. - */ -#ifndef _ASM_IA64_SN_XTALK_XTALK_PRIVATE_H -#define _ASM_IA64_SN_XTALK_XTALK_PRIVATE_H - -#include <asm/sn/ioerror.h> /* for error function and arg types */ -#include <asm/sn/xtalk/xwidget.h> -#include <asm/sn/xtalk/xtalk.h> - -/* - * xtalk_private.h -- private definitions for xtalk - * crosstalk drivers should NOT include this file. - */ - -/* - * All Crosstalk providers set up PIO using this information. - */ -struct xtalk_piomap_s { - vertex_hdl_t xp_dev; /* a requestor of this mapping */ - xwidgetnum_t xp_target; /* target (node's widget number) */ - iopaddr_t xp_xtalk_addr; /* which crosstalk addr is mapped */ - size_t xp_mapsz; /* size of this mapping */ - caddr_t xp_kvaddr; /* kernel virtual address to use */ -}; - -/* - * All Crosstalk providers set up DMA using this information. - */ -struct xtalk_dmamap_s { - vertex_hdl_t xd_dev; /* a requestor of this mapping */ - xwidgetnum_t xd_target; /* target (node's widget number) */ -}; - -/* - * All Crosstalk providers set up interrupts using this information. - */ -struct xtalk_intr_s { - vertex_hdl_t xi_dev; /* requestor of this intr */ - xwidgetnum_t xi_target; /* master's widget number */ - xtalk_intr_vector_t xi_vector; /* 8-bit interrupt vector */ - iopaddr_t xi_addr; /* xtalk address to generate intr */ - void *xi_sfarg; /* argument for setfunc */ - xtalk_intr_setfunc_t xi_setfunc; /* device's setfunc routine */ -}; - -/* - * Xtalk interrupt handler structure access functions - */ -#define xwidget_hwid_is_sn1_xswitch(_hwid) \ - (((_hwid)->part_num == XXBOW_WIDGET_PART_NUM || \ - (_hwid)->part_num == PXBOW_WIDGET_PART_NUM) && \ - ((_hwid)->mfg_num == XXBOW_WIDGET_MFGR_NUM )) - -#define xwidget_hwid_is_xswitch(_hwid) \ - xwidget_hwid_is_sn1_xswitch(_hwid) - -/* common iograph info for all widgets, - * stashed in FASTINFO of widget connection points. - */ -struct xwidget_info_s { - char *w_fingerprint; - vertex_hdl_t w_vertex; /* back pointer to vertex */ - xwidgetnum_t w_id; /* widget id */ - struct xwidget_hwid_s w_hwid; /* hardware identification (part/rev/mfg) */ - vertex_hdl_t w_master; /* CACHED widget's master */ - xwidgetnum_t w_masterid; /* CACHED widget's master's widgetnum */ - error_handler_f *w_efunc; /* error handling function */ - error_handler_arg_t w_einfo; /* first parameter for efunc */ - char *w_name; /* canonical hwgraph name */ -}; - -extern char widget_info_fingerprint[]; - -#endif /* _ASM_IA64_SN_XTALK_XTALK_PRIVATE_H */ diff --git a/include/asm-ia64/sn/xtalk/xtalkaddrs.h b/include/asm-ia64/sn/xtalk/xtalkaddrs.h deleted file mode 100644 index afedfc0f3e6b..000000000000 --- a/include/asm-ia64/sn/xtalk/xtalkaddrs.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All Rights Reserved. - */ -#ifndef _ASM_IA64_SN_XTALK_XTALKADDRS_H -#define _ASM_IA64_SN_XTALK_XTALKADDRS_H - - -/* - * CrossTalk to SN0 Hub addressing support - * - * This file defines the mapping conventions used by the Hub's - * I/O interface when it receives a read or write request from - * a CrossTalk widget. - * - * Format for non-Memory accesses: - * - * +--------------+------------------------------------------------+ - * | 0 | XXXXX | SN0Addr | - * +----+---------+------------------------------------------------+ - * 47 46 40 39 0 - * bit 47 indicates Memory (0) - * bits 46..40 are unused - * bits 39..0 hold the memory address - * (bits 39..31 hold the nodeID in N mode - * bits 39..32 hold the nodeID in M mode - * By design, this looks exactly like a 0-extended SN0 Address, so - * we don't need to do any conversions. - * - * - * - * Format for non-Memory accesses: - * - * +--------------+------+---------+------+--+---------------------+ - * | 1 | DstNode | XXXX | BigW=0 | SW=1 | 1| Addr | - * +----+---------+------+---------+------+--+---------------------+ - * 47 46 38 37 31 30 28 27 24 23 22 0 - * - * bit 47 indicates IO (1) - * bits 46..38 hold the destination node ID - * bits 37..31 are unused - * bits 30..28 hold the big window being addressed - * bits 27..24 hold the small window being addressed - * 0 always refers to the xbow - * 1 always refers to the hub itself - * bit 23 indicates local (0) or remote (1) - * no accessing checks are done if this bit is 0 - * bits 22..0 hold the register address - * bits 22..21 determine which section of the hub - * 00 -> PI - * 01 -> MD - * 10 -> IO - * 11 -> NI - * This looks very much like a REMOTE_HUB access, except the nodeID - * is in a different place, and the highest xtalk bit is set. - */ -/* Hub-specific xtalk definitions */ - -#define HX_MEM_BIT 0L /* Hub's idea of xtalk memory access */ -#define HX_IO_BIT 1L /* Hub's idea of xtalk register access */ -#define HX_ACCTYPE_SHIFT 47 - -#define HX_NODE_SHIFT 39 - -#define HX_BIGWIN_SHIFT 28 -#define HX_SWIN_SHIFT 23 - -#define HX_LOCACC 0L /* local access */ -#define HX_REMACC 1L /* remote access */ -#define HX_ACCESS_SHIFT 23 - -/* - * Pre-calculate the fixed portion of a crosstalk address that maps - * to local register space on a hub. - */ -#define HX_REG_BASE ((HX_IO_BIT<<HX_ACCTYPE_SHIFT) + \ - (0L<<HX_BIGWIN_SHIFT) + \ - (1L<<HX_SWIN_SHIFT) + IALIAS_SIZE + \ - (HX_REMACC<<HX_ACCESS_SHIFT)) - -/* - * Return a crosstalk address which a widget can use to access a - * designated register on a designated node. - */ -#define HUBREG_AS_XTALKADDR(nasid, regaddr) \ - ((iopaddr_t)(HX_REG_BASE + (((long)nasid)<<HX_NODE_SHIFT) + ((long)regaddr))) - -#if TBD -#assert sizeof(iopaddr_t) == 8 -#endif /* TBD */ - -/* - * Get widget part number, given node id and widget id. - * Always do a 32-bit read, because some widgets, e.g., Bridge, require so. - * Widget ID is at offset 0 for 64-bit access. Add 4 to get lower 32 bits - * in big endian mode. - * XXX Double check this with Hub, Xbow, Bridge and other hardware folks. - */ -#define XWIDGET_ID_READ(nasid, widget) \ - (widgetreg_t)(*(volatile uint32_t *)(NODE_SWIN_BASE(nasid, widget) + WIDGET_ID)) - - -#endif /* _ASM_IA64_SN_XTALK_XTALKADDRS_H */ diff --git a/include/asm-ia64/sn/xtalk/xwidget.h b/include/asm-ia64/sn/xtalk/xwidget.h deleted file mode 100644 index d265bcc6bee5..000000000000 --- a/include/asm-ia64/sn/xtalk/xwidget.h +++ /dev/null @@ -1,240 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All Rights Reserved. - */ -#ifndef _ASM_IA64_SN_XTALK_XWIDGET_H -#define _ASM_IA64_SN_XTALK_XWIDGET_H - -/* - * xwidget.h - generic crosstalk widget header file - */ - -#ifdef __KERNEL__ -#include <asm/sn/xtalk/xtalk.h> -#ifndef __ASSEMBLY__ -#include <asm/sn/cdl.h> -#endif /* __ASSEMBLY__ */ -#else -#include <xtalk/xtalk.h> -#endif - -#define WIDGET_ID 0x00 -#define WIDGET_STATUS 0x08 -#define WIDGET_ERR_UPPER_ADDR 0x10 -#define WIDGET_ERR_LOWER_ADDR 0x18 -#define WIDGET_CONTROL 0x20 -#define WIDGET_REQ_TIMEOUT 0x28 -#define WIDGET_INTDEST_UPPER_ADDR 0x30 -#define WIDGET_INTDEST_LOWER_ADDR 0x38 -#define WIDGET_ERR_CMD_WORD 0x40 -#define WIDGET_LLP_CFG 0x48 -#define WIDGET_TFLUSH 0x50 - -/* WIDGET_ID */ -#define WIDGET_REV_NUM 0xf0000000 -#define WIDGET_PART_NUM 0x0ffff000 -#define WIDGET_MFG_NUM 0x00000ffe -#define WIDGET_REV_NUM_SHFT 28 -#define WIDGET_PART_NUM_SHFT 12 -#define WIDGET_MFG_NUM_SHFT 1 - -#define XWIDGET_PART_NUM(widgetid) (((widgetid) & WIDGET_PART_NUM) >> WIDGET_PART_NUM_SHFT) -#define XWIDGET_REV_NUM(widgetid) (((widgetid) & WIDGET_REV_NUM) >> WIDGET_REV_NUM_SHFT) -#define XWIDGET_MFG_NUM(widgetid) (((widgetid) & WIDGET_MFG_NUM) >> WIDGET_MFG_NUM_SHFT) -#define XWIDGET_PART_REV_NUM(widgetid) ((XWIDGET_PART_NUM(widgetid) << 4) | \ - XWIDGET_REV_NUM(widgetid)) -#define XWIDGET_PART_REV_NUM_REV(partrev) (partrev & 0xf) - -/* WIDGET_STATUS */ -#define WIDGET_LLP_REC_CNT 0xff000000 -#define WIDGET_LLP_TX_CNT 0x00ff0000 -#define WIDGET_PENDING 0x0000001f - -/* WIDGET_ERR_UPPER_ADDR */ -#define WIDGET_ERR_UPPER_ADDR_ONLY 0x0000ffff - -/* WIDGET_CONTROL */ -#define WIDGET_F_BAD_PKT 0x00010000 -#define WIDGET_LLP_XBAR_CRD 0x0000f000 -#define WIDGET_LLP_XBAR_CRD_SHFT 12 -#define WIDGET_CLR_RLLP_CNT 0x00000800 -#define WIDGET_CLR_TLLP_CNT 0x00000400 -#define WIDGET_SYS_END 0x00000200 -#define WIDGET_MAX_TRANS 0x000001f0 -#define WIDGET_PCI_SPEED 0x00000030 -#define WIDGET_PCI_SPEED_SHFT 4 -#define WIDGET_PCI_SPEED_33MHZ 0 -#define WIDGET_PCI_SPEED_66MHZ 1 -#define WIDGET_WIDGET_ID 0x0000000f - -/* WIDGET_INTDEST_UPPER_ADDR */ -#define WIDGET_INT_VECTOR 0xff000000 -#define WIDGET_INT_VECTOR_SHFT 24 -#define WIDGET_TARGET_ID 0x000f0000 -#define WIDGET_TARGET_ID_SHFT 16 -#define WIDGET_UPP_ADDR 0x0000ffff - -/* WIDGET_ERR_CMD_WORD */ -#define WIDGET_DIDN 0xf0000000 -#define WIDGET_SIDN 0x0f000000 -#define WIDGET_PACTYP 0x00f00000 -#define WIDGET_TNUM 0x000f8000 -#define WIDGET_COHERENT 0x00004000 -#define WIDGET_DS 0x00003000 -#define WIDGET_GBR 0x00000800 -#define WIDGET_VBPM 0x00000400 -#define WIDGET_ERROR 0x00000200 -#define WIDGET_BARRIER 0x00000100 - -/* WIDGET_LLP_CFG */ -#define WIDGET_LLP_MAXRETRY 0x03ff0000 -#define WIDGET_LLP_MAXRETRY_SHFT 16 -#define WIDGET_LLP_NULLTIMEOUT 0x0000fc00 -#define WIDGET_LLP_NULLTIMEOUT_SHFT 10 -#define WIDGET_LLP_MAXBURST 0x000003ff -#define WIDGET_LLP_MAXBURST_SHFT 0 - -/* - * according to the crosstalk spec, only 32-bits access to the widget - * configuration registers is allowed. some widgets may allow 64-bits - * access but software should not depend on it. registers beyond the - * widget target flush register are widget dependent thus will not be - * defined here - */ -#ifndef __ASSEMBLY__ -typedef uint32_t widgetreg_t; - -/* widget configuration registers */ -typedef volatile struct widget_cfg { -/* - * we access these through synergy unswizzled space, so the address - * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.) - * That's why we put the register first and filler second. - */ - widgetreg_t w_id; /* 0x04 */ - widgetreg_t w_pad_0; /* 0x00 */ - widgetreg_t w_status; /* 0x0c */ - widgetreg_t w_pad_1; /* 0x08 */ - widgetreg_t w_err_upper_addr; /* 0x14 */ - widgetreg_t w_pad_2; /* 0x10 */ - widgetreg_t w_err_lower_addr; /* 0x1c */ - widgetreg_t w_pad_3; /* 0x18 */ - widgetreg_t w_control; /* 0x24 */ - widgetreg_t w_pad_4; /* 0x20 */ - widgetreg_t w_req_timeout; /* 0x2c */ - widgetreg_t w_pad_5; /* 0x28 */ - widgetreg_t w_intdest_upper_addr; /* 0x34 */ - widgetreg_t w_pad_6; /* 0x30 */ - widgetreg_t w_intdest_lower_addr; /* 0x3c */ - widgetreg_t w_pad_7; /* 0x38 */ - widgetreg_t w_err_cmd_word; /* 0x44 */ - widgetreg_t w_pad_8; /* 0x40 */ - widgetreg_t w_llp_cfg; /* 0x4c */ - widgetreg_t w_pad_9; /* 0x48 */ - widgetreg_t w_tflush; /* 0x54 */ - widgetreg_t w_pad_10; /* 0x50 */ -} widget_cfg_t; - -typedef struct { - unsigned int other:8; - unsigned int bo:1; - unsigned int error:1; - unsigned int vbpm:1; - unsigned int gbr:1; - unsigned int ds:2; - unsigned int ct:1; - unsigned int tnum:5; - unsigned int pactyp:4; - unsigned int sidn:4; - unsigned int didn:4; -} w_err_cmd_word_f; - -typedef union { - w_err_cmd_word_f f; - widgetreg_t r; -} w_err_cmd_word_u; - -/* IO widget initialization function */ -typedef struct xwidget_info_s *xwidget_info_t; - -/* - * Crosstalk Widget Hardware Identification, as defined in the Crosstalk spec. - */ -typedef struct xwidget_hwid_s { - xwidget_mfg_num_t mfg_num; - xwidget_rev_num_t rev_num; - xwidget_part_num_t part_num; -} *xwidget_hwid_t; - - -/* - * Returns 1 if a driver that handles devices described by hwid1 is able - * to manage a device with hardwareid hwid2. NOTE: We don't check rev - * numbers at all. - */ -#define XWIDGET_HARDWARE_ID_MATCH(hwid1, hwid2) \ - (((hwid1)->part_num == (hwid2)->part_num) && \ - (((hwid1)->mfg_num == XWIDGET_MFG_NUM_NONE) || \ - ((hwid2)->mfg_num == XWIDGET_MFG_NUM_NONE) || \ - ((hwid1)->mfg_num == (hwid2)->mfg_num))) - - -/* Generic crosstalk widget initialization interface */ -#ifdef __KERNEL__ - -extern int xwidget_driver_register(xwidget_part_num_t part_num, - xwidget_mfg_num_t mfg_num, - char *driver_prefix, - unsigned int flags); - -extern void xwidget_driver_unregister(char *driver_prefix); - -extern int xwidget_register(struct xwidget_hwid_s *hwid, - vertex_hdl_t dev, - xwidgetnum_t id, - vertex_hdl_t master, - xwidgetnum_t targetid); - -extern int xwidget_unregister(vertex_hdl_t); - -extern void xwidget_reset(vertex_hdl_t xwidget); -extern void xwidget_gfx_reset(vertex_hdl_t xwidget); -extern char *xwidget_name_get(vertex_hdl_t xwidget); - -/* Generic crosstalk widget information access interface */ -extern xwidget_info_t xwidget_info_chk(vertex_hdl_t widget); -extern xwidget_info_t xwidget_info_get(vertex_hdl_t widget); -extern void xwidget_info_set(vertex_hdl_t widget, xwidget_info_t widget_info); -extern vertex_hdl_t xwidget_info_dev_get(xwidget_info_t xwidget_info); -extern xwidgetnum_t xwidget_info_id_get(xwidget_info_t xwidget_info); -extern int xwidget_info_type_get(xwidget_info_t xwidget_info); -extern int xwidget_info_state_get(xwidget_info_t xwidget_info); -extern vertex_hdl_t xwidget_info_master_get(xwidget_info_t xwidget_info); -extern xwidgetnum_t xwidget_info_masterid_get(xwidget_info_t xwidget_info); -extern xwidget_part_num_t xwidget_info_part_num_get(xwidget_info_t xwidget_info); -extern xwidget_rev_num_t xwidget_info_rev_num_get(xwidget_info_t xwidget_info); -extern xwidget_mfg_num_t xwidget_info_mfg_num_get(xwidget_info_t xwidget_info); - -extern xwidgetnum_t hub_widget_id(nasid_t); - - - -/* - * TBD: DELETE THIS ENTIRE STRUCTURE! Equivalent is now in - * xtalk_private.h: xwidget_info_s - * This is just here for now because we still have a lot of - * junk referencing it. - * However, since nobody looks inside ... - */ -typedef struct v_widget_s { - unsigned int v_widget_s_is_really_empty; -#define v_widget_s_is_really_empty and using this would be a syntax error. -} v_widget_t; -#endif /* _KERNEL */ - -#endif /* __ASSEMBLY__ */ - -#endif /* _ASM_IA64_SN_XTALK_XWIDGET_H */ diff --git a/include/asm-ia64/topology.h b/include/asm-ia64/topology.h index 1062f02b088e..5b0dd8cc6bd4 100644 --- a/include/asm-ia64/topology.h +++ b/include/asm-ia64/topology.h @@ -58,7 +58,26 @@ void build_cpu_to_node_map(void); | SD_BALANCE_EXEC \ | SD_WAKE_BALANCE, \ .last_balance = jiffies, \ - .balance_interval = 10, \ + .balance_interval = 1, \ + .nr_balance_failed = 0, \ +} + +/* sched_domains SD_ALLNODES_INIT for IA64 NUMA machines */ +#define SD_ALLNODES_INIT (struct sched_domain) { \ + .span = CPU_MASK_NONE, \ + .parent = NULL, \ + .groups = NULL, \ + .min_interval = 80, \ + .max_interval = 320, \ + .busy_factor = 320, \ + .imbalance_pct = 125, \ + .cache_hot_time = (10*1000000), \ + .cache_nice_tries = 1, \ + .per_cpu_gain = 100, \ + .flags = SD_LOAD_BALANCE \ + | SD_BALANCE_EXEC, \ + .last_balance = jiffies, \ + .balance_interval = 100*(63+num_online_cpus())/64, \ .nr_balance_failed = 0, \ } diff --git a/include/asm-m32r/pgtable.h b/include/asm-m32r/pgtable.h index 8894d84df6e0..30bef95696aa 100644 --- a/include/asm-m32r/pgtable.h +++ b/include/asm-m32r/pgtable.h @@ -408,7 +408,8 @@ static __inline__ void pmd_set(pmd_t * pmdp, pte_t * ptep) /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */ #define kern_addr_valid(addr) (1) -#define io_remap_page_range remap_page_range +#define io_remap_page_range(vma, vaddr, paddr, size, prot) \ + remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot) #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY diff --git a/include/asm-m68k/pgtable.h b/include/asm-m68k/pgtable.h index e939f8e04910..de64fccdf4b4 100644 --- a/include/asm-m68k/pgtable.h +++ b/include/asm-m68k/pgtable.h @@ -138,7 +138,8 @@ static inline void update_mmu_cache(struct vm_area_struct *vma, #define kern_addr_valid(addr) (1) -#define io_remap_page_range remap_page_range +#define io_remap_page_range(vma, vaddr, paddr, size, prot) \ + remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot) /* MMU-specific headers */ diff --git a/include/asm-m68knommu/pgtable.h b/include/asm-m68knommu/pgtable.h index 8f2b5904236a..ace19be6e8c8 100644 --- a/include/asm-m68knommu/pgtable.h +++ b/include/asm-m68knommu/pgtable.h @@ -54,7 +54,8 @@ extern int is_in_rom(unsigned long); * No page table caches to initialise. */ #define pgtable_cache_init() do { } while (0) -#define io_remap_page_range remap_page_range +#define io_remap_page_range(vma, vaddr, paddr, size, prot) \ + remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot) /* * All 32bit addresses are effectively valid for vmalloc... diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h index 9d5a8fad0949..c5d69bb707aa 100644 --- a/include/asm-mips/pgtable.h +++ b/include/asm-mips/pgtable.h @@ -245,7 +245,8 @@ static inline void update_mmu_cache(struct vm_area_struct *vma, */ #define HAVE_ARCH_UNMAPPED_AREA -#define io_remap_page_range remap_page_range +#define io_remap_page_range(vma, vaddr, paddr, size, prot) \ + remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot) /* * No page table caches to initialise diff --git a/include/asm-mips/sn/mapped_kernel.h b/include/asm-mips/sn/mapped_kernel.h index 6765d0f0575a..c774996ecf84 100644 --- a/include/asm-mips/sn/mapped_kernel.h +++ b/include/asm-mips/sn/mapped_kernel.h @@ -39,13 +39,11 @@ #define MAPPED_KERN_RW_TO_PHYS(x) \ ((unsigned long)MAPPED_ADDR_RW_TO_PHYS(x) | \ MAPPED_KERN_RW_PHYSBASE(get_compact_nodeid())) -#define MAPPED_OFFSET 16777216 #else /* CONFIG_MAPPED_KERNEL */ #define MAPPED_KERN_RO_TO_PHYS(x) (x - CKSEG0) #define MAPPED_KERN_RW_TO_PHYS(x) (x - CKSEG0) -#define MAPPED_OFFSET 0 #endif /* CONFIG_MAPPED_KERNEL */ diff --git a/include/asm-parisc/pgtable.h b/include/asm-parisc/pgtable.h index 1593a8a7a5fb..6505d5ac291b 100644 --- a/include/asm-parisc/pgtable.h +++ b/include/asm-parisc/pgtable.h @@ -505,7 +505,8 @@ static inline void ptep_mkdirty(pte_t *ptep) #endif /* !__ASSEMBLY__ */ -#define io_remap_page_range remap_page_range +#define io_remap_page_range(vma, vaddr, paddr, size, prot) \ + remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot) /* We provide our own get_unmapped_area to provide cache coherency */ diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h index 5abdd426b04f..707d2a7f72bc 100644 --- a/include/asm-ppc/io.h +++ b/include/asm-ppc/io.h @@ -3,6 +3,7 @@ #define _PPC_IO_H #include <linux/config.h> +#include <linux/string.h> #include <linux/types.h> #include <asm/page.h> @@ -41,34 +42,170 @@ #define PCI_DRAM_OFFSET pci_dram_offset #endif /* Platform-dependent I/O */ +#define ___IO_BASE ((void __iomem *)_IO_BASE) extern unsigned long isa_io_base; extern unsigned long isa_mem_base; extern unsigned long pci_dram_offset; -#define readb(addr) in_8((volatile u8 *)(addr)) -#define writeb(b,addr) out_8((volatile u8 *)(addr), (b)) +/* + * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. + * + * Read operations have additional twi & isync to make sure the read + * is actually performed (i.e. the data has come back) before we start + * executing any following instructions. + */ +extern inline int in_8(volatile unsigned char __iomem *addr) +{ + int ret; + + __asm__ __volatile__( + "lbz%U1%X1 %0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : "m" (*addr)); + return ret; +} + +extern inline void out_8(volatile unsigned char __iomem *addr, int val) +{ + __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); +} + +extern inline int in_le16(volatile unsigned short __iomem *addr) +{ + int ret; + + __asm__ __volatile__("lhbrx %0,0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : + "r" (addr), "m" (*addr)); + return ret; +} + +extern inline int in_be16(volatile unsigned short __iomem *addr) +{ + int ret; + + __asm__ __volatile__("lhz%U1%X1 %0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : "m" (*addr)); + return ret; +} + +extern inline void out_le16(volatile unsigned short __iomem *addr, int val) +{ + __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) : + "r" (val), "r" (addr)); +} + +extern inline void out_be16(volatile unsigned short __iomem *addr, int val) +{ + __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); +} + +extern inline unsigned in_le32(volatile unsigned __iomem *addr) +{ + unsigned ret; + + __asm__ __volatile__("lwbrx %0,0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : + "r" (addr), "m" (*addr)); + return ret; +} + +extern inline unsigned in_be32(volatile unsigned __iomem *addr) +{ + unsigned ret; + + __asm__ __volatile__("lwz%U1%X1 %0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : "m" (*addr)); + return ret; +} + +extern inline void out_le32(volatile unsigned __iomem *addr, int val) +{ + __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) : + "r" (val), "r" (addr)); +} + +extern inline void out_be32(volatile unsigned __iomem *addr, int val) +{ + __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); +} + +static inline __u8 readb(volatile void __iomem *addr) +{ + return in_8(addr); +} +static inline void writeb(__u8 b, volatile void __iomem *addr) +{ + out_8(addr, b); +} #if defined(CONFIG_APUS) -#define readw(addr) (*(volatile u16 *) (addr)) -#define readl(addr) (*(volatile u32 *) (addr)) -#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b)) -#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b)) +static inline __u16 readw(volatile void __iomem *addr) +{ + return *(__force volatile __u16 *)(addr); +} +static inline __u32 readl(volatile void __iomem *addr) +{ + return *(__force volatile __u32 *)(addr); +} +static inline void writew(__u16 b, volatile void __iomem *addr) +{ + *(__force volatile __u16 *)(addr) = b; +} +static inline void writel(__u32 b, volatile void __iomem *addr) +{ + *(__force volatile __u32 *)(addr) = b; +} #else -#define readw(addr) in_le16((volatile u16 *)(addr)) -#define readl(addr) in_le32((volatile u32 *)(addr)) -#define writew(b,addr) out_le16((volatile u16 *)(addr),(b)) -#define writel(b,addr) out_le32((volatile u32 *)(addr),(b)) +static inline __u16 readw(volatile void __iomem *addr) +{ + return in_le16(addr); +} +static inline __u32 readl(volatile void __iomem *addr) +{ + return in_le32(addr); +} +static inline void writew(__u16 b, volatile void __iomem *addr) +{ + out_le16(addr, b); +} +static inline void writel(__u32 b, volatile void __iomem *addr) +{ + out_le32(addr, b); +} #endif /* CONFIG_APUS */ #define readb_relaxed(addr) readb(addr) #define readw_relaxed(addr) readw(addr) #define readl_relaxed(addr) readl(addr) -#define __raw_readb(addr) (*(volatile unsigned char *)(addr)) -#define __raw_readw(addr) (*(volatile unsigned short *)(addr)) -#define __raw_readl(addr) (*(volatile unsigned int *)(addr)) -#define __raw_writeb(v, addr) (*(volatile unsigned char *)(addr) = (v)) -#define __raw_writew(v, addr) (*(volatile unsigned short *)(addr) = (v)) -#define __raw_writel(v, addr) (*(volatile unsigned int *)(addr) = (v)) +static inline __u8 __raw_readb(volatile void __iomem *addr) +{ + return *(__force volatile __u8 *)(addr); +} +static inline __u16 __raw_readw(volatile void __iomem *addr) +{ + return *(__force volatile __u16 *)(addr); +} +static inline __u32 __raw_readl(volatile void __iomem *addr) +{ + return *(__force volatile __u32 *)(addr); +} +static inline void __raw_writeb(__u8 b, volatile void __iomem *addr) +{ + *(__force volatile __u8 *)(addr) = b; +} +static inline void __raw_writew(__u16 b, volatile void __iomem *addr) +{ + *(__force volatile __u16 *)(addr) = b; +} +static inline void __raw_writel(__u32 b, volatile void __iomem *addr) +{ + *(__force volatile __u32 *)(addr) = b; +} /* * The insw/outsw/insl/outsl macros don't do byte-swapping. @@ -76,12 +213,12 @@ extern unsigned long pci_dram_offset; * are arrays of bytes, and byte-swapping is not appropriate in * that case. - paulus */ -#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns)) -#define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns)) -#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) -#define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) +#define insb(port, buf, ns) _insb((port)+___IO_BASE, (buf), (ns)) +#define outsb(port, buf, ns) _outsb((port)+___IO_BASE, (buf), (ns)) +#define insw(port, buf, ns) _insw_ns((port)+___IO_BASE, (buf), (ns)) +#define outsw(port, buf, ns) _outsw_ns((port)+___IO_BASE, (buf), (ns)) +#define insl(port, buf, nl) _insl_ns((port)+___IO_BASE, (buf), (nl)) +#define outsl(port, buf, nl) _outsl_ns((port)+___IO_BASE, (buf), (nl)) /* * On powermacs, we will get a machine check exception if we @@ -121,7 +258,7 @@ extern __inline__ unsigned int name(unsigned int port) \ " .long 3b,5b\n" \ ".previous" \ : "=&r" (x) \ - : "r" (port + _IO_BASE)); \ + : "r" (port + ___IO_BASE)); \ return x; \ } @@ -136,7 +273,7 @@ extern __inline__ void name(unsigned int val, unsigned int port) \ " .align 2\n" \ " .long 1b,2b\n" \ ".previous" \ - : : "r" (val), "r" (port + _IO_BASE)); \ + : : "r" (val), "r" (port + ___IO_BASE)); \ } __do_out_asm(outb, "stbx") @@ -148,9 +285,9 @@ __do_out_asm(outl,"stw%U0%X0") __do_out_asm(outw, "sth%U0%X0") #elif defined (CONFIG_8260_PCI9) /* in asm cannot be defined if PCI9 workaround is used */ -#define inb(port) in_8((u8 *)((port)+_IO_BASE)) -#define inw(port) in_le16((u16 *)((port)+_IO_BASE)) -#define inl(port) in_le32((u32 *)((port)+_IO_BASE)) +#define inb(port) in_8((port)+___IO_BASE) +#define inw(port) in_le16((port)+___IO_BASE) +#define inl(port) in_le32((port)+___IO_BASE) __do_out_asm(outw, "sthbrx") __do_out_asm(outl, "stwbrx") #else @@ -169,46 +306,55 @@ __do_out_asm(outl, "stwbrx") #define inl_p(port) inl((port)) #define outl_p(val, port) outl((val), (port)) -extern void _insb(volatile u8 *port, void *buf, int ns); -extern void _outsb(volatile u8 *port, const void *buf, int ns); -extern void _insw(volatile u16 *port, void *buf, int ns); -extern void _outsw(volatile u16 *port, const void *buf, int ns); -extern void _insl(volatile u32 *port, void *buf, int nl); -extern void _outsl(volatile u32 *port, const void *buf, int nl); -extern void _insw_ns(volatile u16 *port, void *buf, int ns); -extern void _outsw_ns(volatile u16 *port, const void *buf, int ns); -extern void _insl_ns(volatile u32 *port, void *buf, int nl); -extern void _outsl_ns(volatile u32 *port, const void *buf, int nl); +extern void _insb(volatile u8 __iomem *port, void *buf, int ns); +extern void _outsb(volatile u8 __iomem *port, const void *buf, int ns); +extern void _insw(volatile u16 __iomem *port, void *buf, int ns); +extern void _outsw(volatile u16 __iomem *port, const void *buf, int ns); +extern void _insl(volatile u32 __iomem *port, void *buf, int nl); +extern void _outsl(volatile u32 __iomem *port, const void *buf, int nl); +extern void _insw_ns(volatile u16 __iomem *port, void *buf, int ns); +extern void _outsw_ns(volatile u16 __iomem *port, const void *buf, int ns); +extern void _insl_ns(volatile u32 __iomem *port, void *buf, int nl); +extern void _outsl_ns(volatile u32 __iomem *port, const void *buf, int nl); /* * The *_ns versions below don't do byte-swapping. * Neither do the standard versions now, these are just here * for older code. */ -#define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) -#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) +#define insw_ns(port, buf, ns) _insw_ns((port)+___IO_BASE, (buf), (ns)) +#define outsw_ns(port, buf, ns) _outsw_ns((port)+___IO_BASE, (buf), (ns)) +#define insl_ns(port, buf, nl) _insl_ns((port)+___IO_BASE, (buf), (nl)) +#define outsl_ns(port, buf, nl) _outsl_ns((port)+___IO_BASE, (buf), (nl)) #define IO_SPACE_LIMIT ~0 -#define memset_io(a,b,c) memset((void *)(a),(b),(c)) -#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) -#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) +static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) +{ + memset((void __force *)addr, val, count); +} +static inline void memcpy_fromio(void *dst, volatile void __iomem *src, int count) +{ + memcpy(dst, (void __force *) src, count); +} +static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count) +{ + memcpy((void __force *) dst, src, count); +} /* * Map in an area of physical address space, for accessing * I/O devices etc. */ -extern void *__ioremap(phys_addr_t address, unsigned long size, +extern void __iomem *__ioremap(phys_addr_t address, unsigned long size, unsigned long flags); -extern void *ioremap(phys_addr_t address, unsigned long size); +extern void __iomem *ioremap(phys_addr_t address, unsigned long size); #ifdef CONFIG_44x -extern void *ioremap64(unsigned long long address, unsigned long size); +extern void __iomem *ioremap64(unsigned long long address, unsigned long size); #endif #define ioremap_nocache(addr, size) ioremap((addr), (size)) -extern void iounmap(void *addr); +extern void iounmap(volatile void __iomem *addr); extern unsigned long iopa(unsigned long addr); extern unsigned long mm_ptov(unsigned long addr) __attribute_const__; extern void io_block_mapping(unsigned long virt, phys_addr_t phys, @@ -288,94 +434,7 @@ extern inline void eieio(void) #define iobarrier_r() eieio() #define iobarrier_w() eieio() -/* - * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. - * - * Read operations have additional twi & isync to make sure the read - * is actually performed (i.e. the data has come back) before we start - * executing any following instructions. - */ -extern inline int in_8(volatile unsigned char *addr) -{ - int ret; - - __asm__ __volatile__( - "lbz%U1%X1 %0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : "m" (*addr)); - return ret; -} - -extern inline void out_8(volatile unsigned char *addr, int val) -{ - __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); -} - -extern inline int in_le16(volatile unsigned short *addr) -{ - int ret; - - __asm__ __volatile__("lhbrx %0,0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : - "r" (addr), "m" (*addr)); - return ret; -} - -extern inline int in_be16(volatile unsigned short *addr) -{ - int ret; - - __asm__ __volatile__("lhz%U1%X1 %0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : "m" (*addr)); - return ret; -} - -extern inline void out_le16(volatile unsigned short *addr, int val) -{ - __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) : - "r" (val), "r" (addr)); -} - -extern inline void out_be16(volatile unsigned short *addr, int val) -{ - __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); -} - -extern inline unsigned in_le32(volatile unsigned *addr) -{ - unsigned ret; - - __asm__ __volatile__("lwbrx %0,0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : - "r" (addr), "m" (*addr)); - return ret; -} - -extern inline unsigned in_be32(volatile unsigned *addr) -{ - unsigned ret; - - __asm__ __volatile__("lwz%U1%X1 %0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : "m" (*addr)); - return ret; -} - -extern inline void out_le32(volatile unsigned *addr, int val) -{ - __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) : - "r" (val), "r" (addr)); -} - -extern inline void out_be32(volatile unsigned *addr, int val) -{ - __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); -} - -static inline int check_signature(unsigned long io_addr, +static inline int check_signature(volatile void __iomem * io_addr, const unsigned char *signature, int length) { int retval = 0; diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h index 5effe3d09a0f..06ead03f4541 100644 --- a/include/asm-ppc/pgtable.h +++ b/include/asm-ppc/pgtable.h @@ -714,7 +714,8 @@ extern void kernel_set_cachemode (unsigned long address, unsigned long size, /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */ #define kern_addr_valid(addr) (1) -#define io_remap_page_range remap_page_range +#define io_remap_page_range(vma, vaddr, paddr, size, prot) \ + remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot) /* * No page table caches to initialise diff --git a/include/asm-ppc64/pci-bridge.h b/include/asm-ppc64/pci-bridge.h index a51c604b9db6..c7d9481451cd 100644 --- a/include/asm-ppc64/pci-bridge.h +++ b/include/asm-ppc64/pci-bridge.h @@ -34,6 +34,7 @@ struct pci_controller { char what[8]; /* Eye catcher */ enum phb_types type; /* Type of hardware */ struct pci_bus *bus; + char is_dynamic; void *arch_data; struct list_head list_node; @@ -47,6 +48,7 @@ struct pci_controller { * the PCI memory space in the CPU bus space */ unsigned long pci_mem_offset; + unsigned long pci_io_size; struct pci_ops *ops; volatile unsigned int *cfg_addr; @@ -88,7 +90,9 @@ static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev) } extern void pci_process_bridge_OF_ranges(struct pci_controller *hose, - struct device_node *dev, int primary); + struct device_node *dev); + +extern int pcibios_remove_root_bus(struct pci_controller *phb); /* Use this macro after the PCI bus walk for max performance when it * is known that sysdata is correct. diff --git a/include/asm-ppc64/pci.h b/include/asm-ppc64/pci.h index 032a2e6e8224..99ec4453acbb 100644 --- a/include/asm-ppc64/pci.h +++ b/include/asm-ppc64/pci.h @@ -229,6 +229,8 @@ remap_bus_range(struct pci_bus *bus); extern void pcibios_fixup_device_resources(struct pci_dev *dev, struct pci_bus *bus); +extern struct pci_controller *init_phb_dynamic(struct device_node *dn); + extern int pci_read_irq_line(struct pci_dev *dev); extern void pcibios_add_platform_entries(struct pci_dev *dev); diff --git a/include/asm-ppc64/pgtable.h b/include/asm-ppc64/pgtable.h index 5a4a18043ae1..d038d6ed06be 100644 --- a/include/asm-ppc64/pgtable.h +++ b/include/asm-ppc64/pgtable.h @@ -492,7 +492,8 @@ extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t); */ #define kern_addr_valid(addr) (1) -#define io_remap_page_range remap_page_range +#define io_remap_page_range(vma, vaddr, paddr, size, prot) \ + remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot) void pgtable_cache_init(void); diff --git a/include/asm-sh/pgtable.h b/include/asm-sh/pgtable.h index 345b012bb5b0..0f44e664aad1 100644 --- a/include/asm-sh/pgtable.h +++ b/include/asm-sh/pgtable.h @@ -274,7 +274,8 @@ typedef pte_t *pte_addr_t; #define kern_addr_valid(addr) (1) -#define io_remap_page_range remap_page_range +#define io_remap_page_range(vma, vaddr, paddr, size, prot) \ + remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot) /* * No page table caches to initialise diff --git a/include/asm-sh64/pgtable.h b/include/asm-sh64/pgtable.h index 1f333c1060a1..d9e015e32c7c 100644 --- a/include/asm-sh64/pgtable.h +++ b/include/asm-sh64/pgtable.h @@ -479,7 +479,8 @@ extern void update_mmu_cache(struct vm_area_struct * vma, #define PageSkip(page) (0) #define kern_addr_valid(addr) (1) -#define io_remap_page_range remap_page_range +#define io_remap_page_range(vma, vaddr, paddr, size, prot) \ + remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot) #endif /* !__ASSEMBLY__ */ /* diff --git a/include/asm-sparc/atomic.h b/include/asm-sparc/atomic.h index fe210f3614c3..37f6ab601c3d 100644 --- a/include/asm-sparc/atomic.h +++ b/include/asm-sparc/atomic.h @@ -46,6 +46,7 @@ extern void atomic_set(atomic_t *, int); #define atomic_inc_and_test(v) (atomic_inc_return(v) == 0) #define atomic_dec_and_test(v) (atomic_dec_return(v) == 0) +#define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0) /* This is the old 24-bit implementation. It's still used internally * by some sparc-specific code, notably the semaphore implementation. diff --git a/include/asm-sparc/unistd.h b/include/asm-sparc/unistd.h index f73f7e660190..7c6e9ae84bd8 100644 --- a/include/asm-sparc/unistd.h +++ b/include/asm-sparc/unistd.h @@ -296,8 +296,12 @@ #define __NR_mq_notify 277 #define __NR_mq_getsetattr 278 #define __NR_waitid 279 +#define __NR_sys_setaltroot 280 +#define __NR_add_key 281 +#define __NR_request_key 282 +#define __NR_keyctl 283 -/* WARNING: You MAY NOT add syscall numbers larger than 282, since +/* WARNING: You MAY NOT add syscall numbers larger than 283, since * all of the syscall tables in the Sparc kernel are * sized to have 283 entries (starting at zero). Therefore * find a free slot in the 0-282 range. diff --git a/include/asm-sparc64/atomic.h b/include/asm-sparc64/atomic.h index 5374f5b72f4f..823543ddf454 100644 --- a/include/asm-sparc64/atomic.h +++ b/include/asm-sparc64/atomic.h @@ -40,6 +40,12 @@ extern int __atomic64_sub(__s64, atomic64_t *); #define atomic_inc_return(v) __atomic_add(1, v) #define atomic64_inc_return(v) __atomic64_add(1, v) +#define atomic_sub_return(i, v) __atomic_sub(i, v) +#define atomic64_sub_return(i, v) __atomic64_sub(i, v) + +#define atomic_add_return(i, v) __atomic_add(i, v) +#define atomic64_add_return(i, v) __atomic64_add(i, v) + /* * atomic_inc_and_test - increment and test * @v: pointer of type atomic_t diff --git a/include/asm-sparc64/io.h b/include/asm-sparc64/io.h index 7861627d9a92..8c600b0603ff 100644 --- a/include/asm-sparc64/io.h +++ b/include/asm-sparc64/io.h @@ -114,7 +114,7 @@ extern void insl(void __iomem *addr, void *dst, unsigned long count); #define iowrite32_rep(a,s,c) outsl(a,s,c) /* Memory functions, same as I/O accesses on Ultra. */ -static inline u8 _readb(void __iomem *addr) +static inline u8 _readb(volatile void __iomem *addr) { u8 ret; __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */" @@ -123,7 +123,7 @@ static inline u8 _readb(void __iomem *addr) return ret; } -static inline u16 _readw(void __iomem *addr) +static inline u16 _readw(volatile void __iomem *addr) { u16 ret; __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */" @@ -133,7 +133,7 @@ static inline u16 _readw(void __iomem *addr) return ret; } -static inline u32 _readl(void __iomem *addr) +static inline u32 _readl(volatile void __iomem *addr) { u32 ret; __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */" @@ -143,7 +143,7 @@ static inline u32 _readl(void __iomem *addr) return ret; } -static inline u64 _readq(void __iomem *addr) +static inline u64 _readq(volatile void __iomem *addr) { u64 ret; __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */" @@ -153,28 +153,28 @@ static inline u64 _readq(void __iomem *addr) return ret; } -static inline void _writeb(u8 b, void __iomem *addr) +static inline void _writeb(u8 b, volatile void __iomem *addr) { __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */" : /* no outputs */ : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); } -static inline void _writew(u16 w, void __iomem *addr) +static inline void _writew(u16 w, volatile void __iomem *addr) { __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */" : /* no outputs */ : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); } -static inline void _writel(u32 l, void __iomem *addr) +static inline void _writel(u32 l, volatile void __iomem *addr) { __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */" : /* no outputs */ : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); } -static inline void _writeq(u64 q, void __iomem *addr) +static inline void _writeq(u64 q, volatile void __iomem *addr) { __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */" : /* no outputs */ @@ -444,9 +444,16 @@ out: /* On sparc64 we have the whole physical IO address space accessible * using physically addressed loads and stores, so this does nothing. */ -#define ioremap(__offset, __size) ((void __iomem *)(__offset)) +static inline void __iomem *ioremap(unsigned long offset, unsigned long size) +{ + return (void __iomem *)offset; +} + #define ioremap_nocache(X,Y) ioremap((X),(Y)) -#define iounmap(__addr) do { (void)(__addr); } while(0) + +static inline void iounmap(void __iomem *addr) +{ +} #define ioread8(X) readb(X) #define ioread16(X) readw(X) diff --git a/include/asm-sparc64/unistd.h b/include/asm-sparc64/unistd.h index 645cf7208e8e..9c6b4f49a66c 100644 --- a/include/asm-sparc64/unistd.h +++ b/include/asm-sparc64/unistd.h @@ -298,8 +298,12 @@ #define __NR_mq_notify 277 #define __NR_mq_getsetattr 278 #define __NR_waitid 279 +#define __NR_sys_setaltroot 280 +#define __NR_add_key 281 +#define __NR_request_key 282 +#define __NR_keyctl 283 -/* WARNING: You MAY NOT add syscall numbers larger than 282, since +/* WARNING: You MAY NOT add syscall numbers larger than 283, since * all of the syscall tables in the Sparc kernel are * sized to have 283 entries (starting at zero). Therefore * find a free slot in the 0-282 range. diff --git a/include/asm-x86_64/acpi.h b/include/asm-x86_64/acpi.h index 015faa095c2b..84758e9fd097 100644 --- a/include/asm-x86_64/acpi.h +++ b/include/asm-x86_64/acpi.h @@ -166,6 +166,8 @@ extern int acpi_pci_disabled; extern u8 x86_acpiid_to_apicid[]; +extern int acpi_skip_timer_override; + #endif /*__KERNEL__*/ #endif /*_ASM_ACPI_H*/ diff --git a/include/asm-x86_64/atomic.h b/include/asm-x86_64/atomic.h index e2b1f4879259..fc4c5956e1ea 100644 --- a/include/asm-x86_64/atomic.h +++ b/include/asm-x86_64/atomic.h @@ -338,6 +338,31 @@ static __inline__ long atomic64_add_negative(long i, atomic64_t *v) return c; } +/** + * atomic_add_return - add and return + * @v: pointer of type atomic_t + * @i: integer value to add + * + * Atomically adds @i to @v and returns @i + @v + */ +static __inline__ int atomic_add_return(int i, atomic_t *v) +{ + int __i = i; + __asm__ __volatile__( + LOCK "xaddl %0, %1;" + :"=r"(i) + :"m"(v->counter), "0"(i)); + return i + __i; +} + +static __inline__ int atomic_sub_return(int i, atomic_t *v) +{ + return atomic_add_return(-i,v); +} + +#define atomic_inc_return(v) (atomic_add_return(1,v)) +#define atomic_dec_return(v) (atomic_sub_return(1,v)) + /* These are x86-specific, used by some header files */ #define atomic_clear_mask(mask, addr) \ __asm__ __volatile__(LOCK "andl %0,%1" \ diff --git a/include/asm-x86_64/hpet.h b/include/asm-x86_64/hpet.h index 08ee1e7ce3a4..1facdec69cfb 100644 --- a/include/asm-x86_64/hpet.h +++ b/include/asm-x86_64/hpet.h @@ -28,12 +28,15 @@ #define HPET_ID_LEGSUP 0x00008000 #define HPET_ID_NUMBER 0x00001f00 #define HPET_ID_REV 0x000000ff +#define HPET_ID_NUMBER_SHIFT 8 #define HPET_ID_VENDOR_SHIFT 16 #define HPET_ID_VENDOR_8086 0x8086 #define HPET_CFG_ENABLE 0x001 #define HPET_CFG_LEGACY 0x002 +#define HPET_LEGACY_8254 2 +#define HPET_LEGACY_RTC 8 #define HPET_TN_ENABLE 0x004 #define HPET_TN_PERIODIC 0x008 diff --git a/include/asm-x86_64/io.h b/include/asm-x86_64/io.h index d5a214064cc0..d623a4cc9ba8 100644 --- a/include/asm-x86_64/io.h +++ b/include/asm-x86_64/io.h @@ -135,6 +135,8 @@ extern inline void * phys_to_virt(unsigned long address) #define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT) #endif +#include <asm-generic/iomap.h> + extern void __iomem *__ioremap(unsigned long offset, unsigned long size, unsigned long flags); extern inline void __iomem * ioremap (unsigned long offset, unsigned long size) @@ -148,7 +150,7 @@ extern inline void __iomem * ioremap (unsigned long offset, unsigned long size) * or read caching is not desirable: */ extern void __iomem * ioremap_nocache (unsigned long offset, unsigned long size); -extern void iounmap(void __iomem *addr); +extern void iounmap(volatile void __iomem *addr); /* * ISA I/O bus memory addresses are 1:1 with the physical address. @@ -173,10 +175,26 @@ extern void iounmap(void __iomem *addr); * memory location directly. */ -#define readb(addr) (*(__force volatile __u8 *) (__u8 __iomem *)(addr)) -#define readw(addr) (*(__force volatile __u16 *) (__u16 __iomem *)(addr)) -#define readl(addr) (*(__force volatile __u32 *) (__u32 __iomem *)(addr)) -#define readq(addr) (*(__force volatile __u64 *) (__u64 __iomem *)(addr)) +static inline __u8 __readb(volatile void __iomem *addr) +{ + return *(__force volatile __u8 *)addr; +} +static inline __u16 __readw(volatile void __iomem *addr) +{ + return *(__force volatile __u16 *)addr; +} +static inline __u32 __readl(volatile void __iomem *addr) +{ + return *(__force volatile __u32 *)addr; +} +static inline __u64 __readq(volatile void __iomem *addr) +{ + return *(__force volatile __u64 *)addr; +} +#define readb(x) __readb(x) +#define readw(x) __readw(x) +#define readl(x) __readl(x) +#define readq(x) __readq(x) #define readb_relaxed(a) readb(a) #define readw_relaxed(a) readw(a) #define readl_relaxed(a) readl(a) @@ -187,7 +205,7 @@ extern void iounmap(void __iomem *addr); #define __raw_readq readq #ifdef CONFIG_UNORDERED_IO -static inline void __writel(__u32 val, void __iomem *addr) +static inline void __writel(__u32 val, volatile void __iomem *addr) { volatile __u32 __iomem *target = addr; asm volatile("movnti %1,%0" @@ -195,21 +213,35 @@ static inline void __writel(__u32 val, void __iomem *addr) : "r" (val) : "memory"); } -static inline void __writeq(__u64 val, void __iomem *addr) +static inline void __writeq(__u64 val, volatile void __iomem *addr) { - volatile __u64 *target = addr; + volatile __u64 __iomem *target = addr; asm volatile("movnti %1,%0" : "=m" (*target) : "r" (val) : "memory"); } -#define writeq(val,addr) __writeq((val),(void __iomem *)(addr)) -#define writel(val,addr) __writel((val),(void __iomem *)(addr)) #else -#define writel(b,addr) (*(__force volatile __u32 *)(__u32 __iomem *)(addr) = (b)) -#define writeq(b,addr) (*(__force volatile __u64 *)(__u64 __iomem *)(addr) = (b)) +static inline void __writel(__u32 b, volatile void __iomem *addr) +{ + *(__force volatile __u32 *)addr = b; +} +static inline void __writeq(__u64 b, volatile void __iomem *addr) +{ + *(__force volatile __u64 *)addr = b; +} #endif -#define writeb(b,addr) (*(__force volatile __u8 *)(__u8 __iomem *)(addr) = (b)) -#define writew(b,addr) (*(__force volatile __u16 *)(__u16 __iomem *)(addr) = (b)) +static inline void __writeb(__u8 b, volatile void __iomem *addr) +{ + *(__force volatile __u8 *)addr = b; +} +static inline void __writew(__u16 b, volatile void __iomem *addr) +{ + *(__force volatile __u16 *)addr = b; +} +#define writeq(val,addr) __writeq((val),(addr)) +#define writel(val,addr) __writel((val),(addr)) +#define writew(val,addr) __writew((val),(addr)) +#define writeb(val,addr) __writeb((val),(addr)) #define __raw_writeb writeb #define __raw_writew writew #define __raw_writel writel @@ -218,11 +250,18 @@ static inline void __writeq(__u64 val, void __iomem *addr) void *__memcpy_fromio(void*,unsigned long,unsigned); void *__memcpy_toio(unsigned long,const void*,unsigned); -#define memcpy_fromio(to,from,len) \ - __memcpy_fromio((to),(unsigned long)(void __iomem *)(from),(len)) -#define memcpy_toio(to,from,len) \ - __memcpy_toio((unsigned long)(void __iomem *)(to),(from),(len)) -#define memset_io(a,b,c) memset((__force void *)(void __iomem *)(a),(b),(c)) +static inline void *memcpy_fromio(void *to, volatile void __iomem *from, unsigned len) +{ + return __memcpy_fromio(to,(unsigned long)from,len); +} +static inline void *memcpy_toio(volatile void __iomem *to, const void *from, unsigned len) +{ + return __memcpy_toio((unsigned long)to,from,len); +} +static inline void *memset_io(volatile void __iomem *a, int b, size_t c) +{ + return memset((__force void *)a,b,c); +} /* * ISA space is 'always mapped' on a typical x86 system, no need to @@ -263,7 +302,7 @@ void *__memcpy_toio(unsigned long,const void*,unsigned); * Returns 1 on a match. */ -static inline int check_signature(unsigned long io_addr, +static inline int check_signature(void __iomem *io_addr, const unsigned char *signature, int length) { int retval = 0; diff --git a/include/asm-x86_64/pgtable.h b/include/asm-x86_64/pgtable.h index 059ba4a7d4b6..cd56bb9fe4f4 100644 --- a/include/asm-x86_64/pgtable.h +++ b/include/asm-x86_64/pgtable.h @@ -421,7 +421,8 @@ extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot) extern int kern_addr_valid(unsigned long addr); -#define io_remap_page_range remap_page_range +#define io_remap_page_range(vma, vaddr, paddr, size, prot) \ + remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot) #define HAVE_ARCH_UNMAPPED_AREA diff --git a/include/asm-x86_64/uaccess.h b/include/asm-x86_64/uaccess.h index a7b9d33053c4..406102dbf298 100644 --- a/include/asm-x86_64/uaccess.h +++ b/include/asm-x86_64/uaccess.h @@ -102,7 +102,7 @@ extern void __get_user_8(void); /* Careful: we have to cast the result to the type of the pointer for sign reasons */ #define get_user(x,ptr) \ -({ long __val_gu; \ +({ unsigned long __val_gu; \ int __ret_gu; \ __chk_user_ptr(ptr); \ switch(sizeof (*(ptr))) { \ diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h index b2059869cb92..944d1088902e 100644 --- a/include/linux/blkdev.h +++ b/include/linux/blkdev.h @@ -125,13 +125,7 @@ struct request { /* no. of sectors left to complete in the current segment */ unsigned int hard_cur_sectors; - /* no. of segments left to submit in the current bio */ - unsigned short nr_cbio_segments; - /* no. of sectors left to submit in the current bio */ - unsigned long nr_cbio_sectors; - - struct bio *cbio; /* next bio to submit */ - struct bio *bio; /* next unfinished bio to complete */ + struct bio *bio; struct bio *biotail; void *elevator_private; @@ -465,32 +459,6 @@ static inline void blk_clear_queue_full(struct request_queue *q, int rw) */ #define blk_queue_headactive(q, head_active) -/* current index into bio being processed for submission */ -#define blk_rq_idx(rq) ((rq)->cbio->bi_vcnt - (rq)->nr_cbio_segments) - -/* current bio vector being processed */ -#define blk_rq_vec(rq) (bio_iovec_idx((rq)->cbio, blk_rq_idx(rq))) - -/* current offset with respect to start of the segment being submitted */ -#define blk_rq_offset(rq) \ - (((rq)->hard_cur_sectors - (rq)->current_nr_sectors) << 9) - -/* - * temporarily mapping a (possible) highmem bio (typically for PIO transfer) - */ - -/* Assumes rq->cbio != NULL */ -static inline char * rq_map_buffer(struct request *rq, unsigned long *flags) -{ - return (__bio_kmap_irq(rq->cbio, blk_rq_idx(rq), flags) - + blk_rq_offset(rq)); -} - -static inline void rq_unmap_buffer(char *buffer, unsigned long *flags) -{ - __bio_kunmap_irq(buffer, flags); -} - /* * q->prep_rq_fn return values */ @@ -589,7 +557,6 @@ static inline void blk_run_address_space(struct address_space *mapping) extern int end_that_request_first(struct request *, int, int); extern int end_that_request_chunk(struct request *, int, int); extern void end_that_request_last(struct request *); -extern int process_that_request_first(struct request *, unsigned int); extern void end_request(struct request *req, int uptodate); /* @@ -660,7 +627,6 @@ extern void blk_queue_invalidate_tags(request_queue_t *); extern long blk_congestion_wait(int rw, long timeout); extern void blk_rq_bio_prep(request_queue_t *, struct request *, struct bio *); -extern void blk_rq_prep_restart(struct request *); extern int blkdev_issue_flush(struct block_device *, sector_t *); #define MAX_PHYS_SEGMENTS 128 diff --git a/include/linux/compat_ioctl.h b/include/linux/compat_ioctl.h index 71da7d1260cd..a9d099134bf2 100644 --- a/include/linux/compat_ioctl.h +++ b/include/linux/compat_ioctl.h @@ -23,6 +23,8 @@ COMPATIBLE_IOCTL(TCSETS) COMPATIBLE_IOCTL(TCSETSW) COMPATIBLE_IOCTL(TCSETSF) COMPATIBLE_IOCTL(TIOCLINUX) +COMPATIBLE_IOCTL(TIOCSBRK) +COMPATIBLE_IOCTL(TIOCCBRK) /* Little t */ COMPATIBLE_IOCTL(TIOCGETD) COMPATIBLE_IOCTL(TIOCSETD) diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h index 48a23f1588a1..f8543228663f 100644 --- a/include/linux/cpufreq.h +++ b/include/linux/cpufreq.h @@ -22,6 +22,7 @@ #include <linux/sysfs.h> #include <linux/completion.h> #include <linux/workqueue.h> +#include <linux/cpumask.h> #define CPUFREQ_NAME_LEN 16 @@ -69,7 +70,8 @@ struct cpufreq_real_policy { }; struct cpufreq_policy { - unsigned int cpu; /* cpu nr */ + cpumask_t cpus; /* affected CPUs */ + unsigned int cpu; /* cpu nr of registered CPU */ struct cpufreq_cpuinfo cpuinfo;/* see above */ unsigned int min; /* in kHz */ diff --git a/include/linux/dvb/frontend.h b/include/linux/dvb/frontend.h index 51a69e389eae..0d59e6d76830 100644 --- a/include/linux/dvb/frontend.h +++ b/include/linux/dvb/frontend.h @@ -32,7 +32,8 @@ typedef enum fe_type { FE_QPSK, FE_QAM, - FE_OFDM + FE_OFDM, + FE_ATSC } fe_type_t; @@ -59,6 +60,8 @@ typedef enum fe_caps { FE_CAN_BANDWIDTH_AUTO = 0x40000, FE_CAN_GUARD_INTERVAL_AUTO = 0x80000, FE_CAN_HIERARCHY_AUTO = 0x100000, + FE_CAN_8VSB = 0x200000, + FE_CAN_16VSB = 0x400000, FE_NEEDS_BENDING = 0x20000000, // frontend requires frequency bending FE_CAN_RECOVER = 0x40000000, // frontend can recover from a cable unplug automatically FE_CAN_MUTE_TS = 0x80000000 // frontend can stop spurious TS data output diff --git a/include/linux/dvb/osd.h b/include/linux/dvb/osd.h index cdaff25eccc3..d236deac80f1 100644 --- a/include/linux/dvb/osd.h +++ b/include/linux/dvb/osd.h @@ -94,6 +94,7 @@ typedef enum { OSD_Text, // (x0,y0,size,color,text) OSD_SetWindow, // (x0) set window with number 0<x0<8 as current OSD_MoveWindow, // move current window to (x0, y0) + OSD_OpenRaw, // Open other types of OSD windows } OSD_Command; typedef struct osd_cmd_s { @@ -106,8 +107,39 @@ typedef struct osd_cmd_s { void __user *data; } osd_cmd_t; +/* OSD_OpenRaw: set 'color' to desired window type */ +typedef enum { + OSD_BITMAP1, /* 1 bit bitmap */ + OSD_BITMAP2, /* 2 bit bitmap */ + OSD_BITMAP4, /* 4 bit bitmap */ + OSD_BITMAP8, /* 8 bit bitmap */ + OSD_BITMAP1HR, /* 1 Bit bitmap half resolution */ + OSD_BITMAP2HR, /* 2 bit bitmap half resolution */ + OSD_BITMAP4HR, /* 4 bit bitmap half resolution */ + OSD_BITMAP8HR, /* 8 bit bitmap half resolution */ + OSD_YCRCB422, /* 4:2:2 YCRCB Graphic Display */ + OSD_YCRCB444, /* 4:4:4 YCRCB Graphic Display */ + OSD_YCRCB444HR, /* 4:4:4 YCRCB graphic half resolution */ + OSD_VIDEOTSIZE, /* True Size Normal MPEG Video Display */ + OSD_VIDEOHSIZE, /* MPEG Video Display Half Resolution */ + OSD_VIDEOQSIZE, /* MPEG Video Display Quarter Resolution */ + OSD_VIDEODSIZE, /* MPEG Video Display Double Resolution */ + OSD_VIDEOTHSIZE, /* True Size MPEG Video Display Half Resolution */ + OSD_VIDEOTQSIZE, /* True Size MPEG Video Display Quarter Resolution*/ + OSD_VIDEOTDSIZE, /* True Size MPEG Video Display Double Resolution */ + OSD_VIDEONSIZE, /* Full Size MPEG Video Display */ + OSD_CURSOR /* Cursor */ +} osd_raw_window_t; + +typedef struct osd_cap_s { + int cmd; +#define OSD_CAP_MEMSIZE 1 /* memory size */ + long val; +} osd_cap_t; + #define OSD_SEND_CMD _IOW('o', 160, osd_cmd_t) +#define OSD_GET_CAPABILITY _IOR('o', 161, osd_cap_t) #endif diff --git a/include/linux/edd.h b/include/linux/edd.h index 5f93881106fa..242600817a8d 100644 --- a/include/linux/edd.h +++ b/include/linux/edd.h @@ -37,14 +37,18 @@ #define EDDEXTSIZE 8 /* change these if you muck with the structures */ #define EDDPARMSIZE 74 #define CHECKEXTENSIONSPRESENT 0x41 +#define EXTENDEDREAD 0x42 #define GETDEVICEPARAMETERS 0x48 #define LEGACYGETDEVICEPARAMETERS 0x08 #define EDDMAGIC1 0x55AA #define EDDMAGIC2 0xAA55 +#define FIXEDDISKSUBSET 0x0001 +#define GET_DEVICE_PARAMETERS_SUPPORTED 0x0007 #define READ_SECTORS 0x02 /* int13 AH=0x02 is READ_SECTORS command */ #define EDD_MBR_SIG_OFFSET 0x1B8 /* offset of signature in the MBR */ +#define EDD_DEV_ADDR_PACKET_LEN 0x10 /* for int13 fn42 */ #define EDD_MBR_SIG_BUF 0x290 /* addr in boot params */ #define EDD_MBR_SIG_MAX 16 /* max number of signatures to store */ #define EDD_MBR_SIG_NR_BUF 0x1ea /* addr of number of MBR signtaures at EDD_MBR_SIG_BUF diff --git a/include/linux/fs.h b/include/linux/fs.h index 6768655fd11d..4a9463c662ed 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -633,6 +633,9 @@ struct file_lock_operations { struct lock_manager_operations { int (*fl_compare_owner)(struct file_lock *, struct file_lock *); void (*fl_notify)(struct file_lock *); /* unblock callback */ + void (*fl_copy_lock)(struct file_lock *, struct file_lock *); + void (*fl_release_private)(struct file_lock *); + void (*fl_break)(struct file_lock *); }; /* that will die - we need it for nfs_lock_info */ @@ -698,6 +701,8 @@ extern int posix_locks_deadlock(struct file_lock *, struct file_lock *); extern int flock_lock_file_wait(struct file *filp, struct file_lock *fl); extern int __break_lease(struct inode *inode, unsigned int flags); extern void lease_get_mtime(struct inode *, struct timespec *time); +extern int setlease(struct file *, long, struct file_lock **); +extern void remove_lease(struct file_lock *); extern int lock_may_read(struct inode *, loff_t start, unsigned long count); extern int lock_may_write(struct inode *, loff_t start, unsigned long count); extern void steal_locks(fl_owner_t from); @@ -1270,8 +1275,8 @@ extern int bd_claim(struct block_device *, void *); extern void bd_release(struct block_device *); /* fs/char_dev.c */ -extern int alloc_chrdev_region(dev_t *, unsigned, unsigned, char *); -extern int register_chrdev_region(dev_t, unsigned, char *); +extern int alloc_chrdev_region(dev_t *, unsigned, unsigned, const char *); +extern int register_chrdev_region(dev_t, unsigned, const char *); extern int register_chrdev(unsigned int, const char *, struct file_operations *); extern int unregister_chrdev(unsigned int, const char *); diff --git a/include/linux/generic_serial.h b/include/linux/generic_serial.h index f2bd22edba05..1c8417aff025 100644 --- a/include/linux/generic_serial.h +++ b/include/linux/generic_serial.h @@ -73,7 +73,7 @@ struct gs_port { void gs_put_char(struct tty_struct *tty, unsigned char ch); -int gs_write(struct tty_struct *tty, int from_user, +int gs_write(struct tty_struct *tty, const unsigned char *buf, int count); int gs_write_room(struct tty_struct *tty); int gs_chars_in_buffer(struct tty_struct *tty); diff --git a/include/linux/genhd.h b/include/linux/genhd.h index 749992dc71b7..0692f7778f4f 100644 --- a/include/linux/genhd.h +++ b/include/linux/genhd.h @@ -129,13 +129,14 @@ struct gendisk { /* * Macros to operate on percpu disk statistics: - * Since writes to disk_stats are serialised through the queue_lock, - * smp_processor_id() should be enough to get to the per_cpu versions - * of statistics counters + * + * The __ variants should only be called in critical sections. The full + * variants disable/enable preemption. */ #ifdef CONFIG_SMP -#define disk_stat_add(gendiskp, field, addnd) \ +#define __disk_stat_add(gendiskp, field, addnd) \ (per_cpu_ptr(gendiskp->dkstats, smp_processor_id())->field += addnd) + #define disk_stat_read(gendiskp, field) \ ({ \ typeof(gendiskp->dkstats->field) res = 0; \ @@ -159,7 +160,8 @@ static inline void disk_stat_set_all(struct gendisk *gendiskp, int value) { } #else -#define disk_stat_add(gendiskp, field, addnd) (gendiskp->dkstats.field += addnd) +#define __disk_stat_add(gendiskp, field, addnd) \ + (gendiskp->dkstats.field += addnd) #define disk_stat_read(gendiskp, field) (gendiskp->dkstats.field) static inline void disk_stat_set_all(struct gendisk *gendiskp, int value) { @@ -167,8 +169,21 @@ static inline void disk_stat_set_all(struct gendisk *gendiskp, int value) { } #endif -#define disk_stat_inc(gendiskp, field) disk_stat_add(gendiskp, field, 1) +#define disk_stat_add(gendiskp, field, addnd) \ + do { \ + preempt_disable(); \ + __disk_stat_add(gendiskp, field, addnd); \ + preempt_enable(); \ + } while (0) + +#define __disk_stat_dec(gendiskp, field) __disk_stat_add(gendiskp, field, -1) #define disk_stat_dec(gendiskp, field) disk_stat_add(gendiskp, field, -1) + +#define __disk_stat_inc(gendiskp, field) __disk_stat_add(gendiskp, field, 1) +#define disk_stat_inc(gendiskp, field) disk_stat_add(gendiskp, field, 1) + +#define __disk_stat_sub(gendiskp, field, subnd) \ + __disk_stat_add(gendiskp, field, -subnd) #define disk_stat_sub(gendiskp, field, subnd) \ disk_stat_add(gendiskp, field, -subnd) diff --git a/include/linux/i2c-vid.h b/include/linux/i2c-vid.h index 62424092e44e..974835e3530f 100644 --- a/include/linux/i2c-vid.h +++ b/include/linux/i2c-vid.h @@ -29,7 +29,22 @@ */ /* - Legal val values 00 - 1F. + AMD Opteron processors don't follow the Intel VRM spec. + I'm going to "make up" 2.4 as the VRM spec for the Opterons. + No good reason just a mnemonic for the 24x Opteron processor + series + + Opteron VID encoding is: + + 00000 = 1.550 V + 00001 = 1.525 V + . . . . + 11110 = 0.800 V + 11111 = 0.000 V (off) + */ + +/* + Legal val values 0x00 - 0x1f; except for VRD 10.0, 0x00 - 0x3f. vrm is the Intel VRM document version. Note: vrm version is scaled by 10 and the return value is scaled by 1000 to avoid floating point in the kernel. @@ -41,9 +56,28 @@ int i2c_which_vrm(void); static inline int vid_from_reg(int val, int vrm) { + int vid; + switch(vrm) { + case 0: return 0; + + case 100: /* VRD 10.0 */ + if((val & 0x1f) == 0x1f) + return 0; + if((val & 0x1f) <= 0x09 || val == 0x0a) + vid = 10875 - (val & 0x1f) * 250; + else + vid = 18625 - (val & 0x1f) * 250; + if(val & 0x20) + vid -= 125; + vid /= 10; /* only return 3 dec. places for now */ + return vid; + + case 24: /* Opteron processor */ + return(val == 0x1f ? 0 : 1550 - val * 25); + case 91: /* VRM 9.1 */ case 90: /* VRM 9.0 */ return(val == 0x1f ? 0 : diff --git a/include/linux/i2c.h b/include/linux/i2c.h index caac24868d85..bd2735bdca6b 100644 --- a/include/linux/i2c.h +++ b/include/linux/i2c.h @@ -568,7 +568,7 @@ union i2c_smbus_data { static unsigned short var[I2C_CLIENT_MAX_OPTS] = I2C_CLIENT_DEFAULTS; \ static unsigned int var##_num; \ /*MODULE_PARM(var,I2C_CLIENT_MODPARM);*/ \ - module_param_array(var, short, var##_num, 0); \ + module_param_array(var, short, &var##_num, 0); \ MODULE_PARM_DESC(var,desc) /* This is the one you want to use in your own modules */ diff --git a/include/linux/i2o.h b/include/linux/i2o.h index 3481de9c5837..f571709b0443 100644 --- a/include/linux/i2o.h +++ b/include/linux/i2o.h @@ -502,6 +502,45 @@ static inline void i2o_flush_reply(struct i2o_controller *c, u32 m) }; /** + * i2o_out_to_virt - Turn an I2O message to a virtual address + * @c: controller + * @m: message engine value + * + * Turn a receive message from an I2O controller bus address into + * a Linux virtual address. The shared page frame is a linear block + * so we simply have to shift the offset. This function does not + * work for sender side messages as they are ioremap objects + * provided by the I2O controller. + */ +static inline struct i2o_message *i2o_msg_out_to_virt(struct i2o_controller *c, + u32 m) +{ + if (unlikely + (m < c->out_queue.phys + || m >= c->out_queue.phys + c->out_queue.len)) + BUG(); + + return c->out_queue.virt + (m - c->out_queue.phys); +}; + +/** + * i2o_msg_in_to_virt - Turn an I2O message to a virtual address + * @c: controller + * @m: message engine value + * + * Turn a send message from an I2O controller bus address into + * a Linux virtual address. The shared page frame is a linear block + * so we simply have to shift the offset. This function does not + * work for receive side messages as they are kmalloc objects + * in a different pool. + */ +static inline struct i2o_message *i2o_msg_in_to_virt(struct i2o_controller *c, + u32 m) +{ + return c->in_queue.virt + m; +}; + +/** * i2o_dma_alloc - Allocate DMA memory * @dev: struct device pointer to the PCI device of the I2O controller * @addr: i2o_dma struct which should get the DMA buffer diff --git a/include/linux/ide.h b/include/linux/ide.h index f6a39379ada9..f4bafe0cd0fb 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -242,7 +242,7 @@ typedef int (ide_ack_intr_t)(struct hwif_s *); typedef enum { ide_unknown, ide_generic, ide_pci, ide_cmd640, ide_dtc2278, ide_ali14xx, ide_qd65xx, ide_umc8672, ide_ht6560b, - ide_pdc4030, ide_rz1000, ide_trm290, + ide_rz1000, ide_trm290, ide_cmd646, ide_cy82c693, ide_4drives, ide_pmac, ide_etrax100, ide_acorn, ide_forced @@ -789,27 +789,6 @@ typedef struct ide_drive_s { struct gendisk *disk; } ide_drive_t; -/* - * mapping stuff, prepare for highmem... - * - * temporarily mapping a (possible) highmem bio for PIO transfer - */ -#ifndef CONFIG_IDE_TASKFILE_IO - -#define ide_rq_offset(rq) \ - (((rq)->hard_cur_sectors - (rq)->current_nr_sectors) << 9) - -static inline void *ide_map_buffer(struct request *rq, unsigned long *flags) -{ - return bio_kmap_irq(rq->bio, flags) + ide_rq_offset(rq); -} - -static inline void ide_unmap_buffer(struct request *rq, char *buffer, unsigned long *flags) -{ - bio_kunmap_irq(buffer, flags); -} -#endif /* !CONFIG_IDE_TASKFILE_IO */ - #define IDE_CHIPSET_PCI_MASK \ ((1<<ide_pci)|(1<<ide_cmd646)|(1<<ide_ali14xx)) #define IDE_CHIPSET_IS_PCI(c) ((IDE_CHIPSET_PCI_MASK >> (c)) & 1) @@ -853,8 +832,6 @@ typedef struct hwif_s { #if 0 ide_hwif_ops_t *hwifops; #else - /* routine is for HBA specific IDENTITY operations */ - int (*identify)(ide_drive_t *); /* routine to tune PIO mode for drives */ void (*tuneproc)(ide_drive_t *, u8); /* routine to retune DMA modes for drives */ @@ -887,9 +864,9 @@ typedef struct hwif_s { void (*atapi_input_bytes)(ide_drive_t *, void *, u32); void (*atapi_output_bytes)(ide_drive_t *, void *, u32); - int (*ide_dma_read)(ide_drive_t *drive); - int (*ide_dma_write)(ide_drive_t *drive); - int (*ide_dma_begin)(ide_drive_t *drive); + int (*dma_setup)(ide_drive_t *); + void (*dma_exec_cmd)(ide_drive_t *, u8); + void (*dma_start)(ide_drive_t *); int (*ide_dma_end)(ide_drive_t *drive); int (*ide_dma_check)(ide_drive_t *drive); int (*ide_dma_on)(ide_drive_t *drive); @@ -920,12 +897,18 @@ typedef struct hwif_s { dma_addr_t dmatable_dma; /* Scatter-gather list used to build the above */ struct scatterlist *sg_table; + int sg_max_nents; /* Maximum number of entries in it */ int sg_nents; /* Current number of entries in it */ int sg_dma_direction; /* dma transfer direction */ /* data phase of the active command (currently only valid for PIO/DMA) */ int data_phase; + unsigned int nsect; + unsigned int nleft; + unsigned int cursg; + unsigned int cursg_ofs; + int mmio; /* hosts iomio (0) or custom (2) select */ int rqsize; /* max sectors per request */ int irq; /* our irq number */ @@ -1369,35 +1352,6 @@ extern void atapi_output_bytes(ide_drive_t *, void *, u32); extern void taskfile_input_data(ide_drive_t *, void *, u32); extern void taskfile_output_data(ide_drive_t *, void *, u32); -#define IDE_PIO_IN 0 -#define IDE_PIO_OUT 1 - -static inline void __task_sectors(ide_drive_t *drive, char *buf, - unsigned nsect, unsigned rw) -{ - /* - * IRQ can happen instantly after reading/writing - * last sector of the datablock. - */ - if (rw == IDE_PIO_OUT) - taskfile_output_data(drive, buf, nsect * SECTOR_WORDS); - else - taskfile_input_data(drive, buf, nsect * SECTOR_WORDS); -} - -#ifdef CONFIG_IDE_TASKFILE_IO -static inline void task_bio_sectors(ide_drive_t *drive, struct request *rq, - unsigned nsect, unsigned rw) -{ - unsigned long flags; - char *buf = rq_map_buffer(rq, &flags); - - process_that_request_first(rq, nsect); - __task_sectors(drive, buf, nsect, rw); - rq_unmap_buffer(buf, &flags); -} -#endif /* CONFIG_IDE_TASKFILE_IO */ - extern int drive_is_ready(ide_drive_t *); extern int wait_for_ready(ide_drive_t *, int /* timeout */); @@ -1528,6 +1482,9 @@ typedef struct ide_pci_device_s { extern void ide_setup_pci_device(struct pci_dev *, ide_pci_device_t *); extern void ide_setup_pci_devices(struct pci_dev *, struct pci_dev *, ide_pci_device_t *); +void ide_map_sg(ide_drive_t *, struct request *); +void ide_init_sg_cmd(ide_drive_t *, struct request *); + #define BAD_DMA_DRIVE 0 #define GOOD_DMA_DRIVE 1 @@ -1544,16 +1501,14 @@ extern void ide_destroy_dmatable(ide_drive_t *); extern ide_startstop_t ide_dma_intr(ide_drive_t *); extern int ide_release_dma(ide_hwif_t *); extern void ide_setup_dma(ide_hwif_t *, unsigned long, unsigned int); -extern int ide_start_dma(ide_hwif_t *, ide_drive_t *, int); extern int __ide_dma_host_off(ide_drive_t *); extern int __ide_dma_off_quietly(ide_drive_t *); extern int __ide_dma_host_on(ide_drive_t *); extern int __ide_dma_on(ide_drive_t *); extern int __ide_dma_check(ide_drive_t *); -extern int __ide_dma_read(ide_drive_t *); -extern int __ide_dma_write(ide_drive_t *); -extern int __ide_dma_begin(ide_drive_t *); +extern int ide_dma_setup(ide_drive_t *); +extern void ide_dma_start(ide_drive_t *); extern int __ide_dma_end(ide_drive_t *); extern int __ide_dma_test_irq(ide_drive_t *); extern int __ide_dma_verbose(ide_drive_t *); diff --git a/include/linux/idr.h b/include/linux/idr.h index 1b0c1e6d1e2d..ca3b7e462576 100644 --- a/include/linux/idr.h +++ b/include/linux/idr.h @@ -9,7 +9,7 @@ * tables. */ #include <linux/types.h> -#include <asm/bitops.h> +#include <linux/bitops.h> #if BITS_PER_LONG == 32 # define IDR_BITS 5 diff --git a/include/linux/if_ppp.h b/include/linux/if_ppp.h index 6ee8b0470b1d..572aff7daa21 100644 --- a/include/linux/if_ppp.h +++ b/include/linux/if_ppp.h @@ -92,7 +92,7 @@ struct npioctl { /* Structure describing a CCP configuration option, for PPPIOCSCOMPRESS */ struct ppp_option_data { - __u8 *ptr; + __u8 __user *ptr; __u32 length; int transmit; }; diff --git a/include/linux/lockd/debug.h b/include/linux/lockd/debug.h index 5b6961d739d4..34b2b7f33c3b 100644 --- a/include/linux/lockd/debug.h +++ b/include/linux/lockd/debug.h @@ -45,4 +45,13 @@ #define NLMDBG_ALL 0x7fff +/* + * Support for printing NLM cookies in dprintk() + */ +#ifdef RPC_DEBUG +struct nlm_cookie; +/* Call this function with the BKL held (it uses a static buffer) */ +extern const char *nlmdbg_cookie2a(const struct nlm_cookie *); +#endif + #endif /* LINUX_LOCKD_DEBUG_H */ diff --git a/include/linux/lockd/xdr.h b/include/linux/lockd/xdr.h index ef14dbd2a67c..d7a5cc4cfa97 100644 --- a/include/linux/lockd/xdr.h +++ b/include/linux/lockd/xdr.h @@ -13,10 +13,9 @@ #include <linux/nfs.h> #include <linux/sunrpc/xdr.h> +#define NLM_MAXCOOKIELEN 32 #define NLM_MAXSTRLEN 1024 -#define QUADLEN(len) (((len) + 3) >> 2) - #define nlm_granted __constant_htonl(NLM_LCK_GRANTED) #define nlm_lck_denied __constant_htonl(NLM_LCK_DENIED) #define nlm_lck_denied_nolocks __constant_htonl(NLM_LCK_DENIED_NOLOCKS) @@ -33,13 +32,14 @@ struct nlm_lock { }; /* - * NLM cookies. Technically they can be 1K, Nobody uses over 8 bytes - * however. + * NLM cookies. Technically they can be 1K, but Linux only uses 8 bytes. + * FreeBSD uses 16, Apple Mac OS X 10.3 uses 20. Therefore we set it to + * 32 bytes. */ struct nlm_cookie { - unsigned char data[8]; + unsigned char data[NLM_MAXCOOKIELEN]; unsigned int len; }; diff --git a/include/linux/mm.h b/include/linux/mm.h index 158ee1c501f0..1538a9dd4f62 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -758,8 +758,15 @@ extern struct vm_area_struct *find_extend_vma(struct mm_struct *mm, unsigned lon extern struct page * vmalloc_to_page(void *addr); extern struct page * follow_page(struct mm_struct *mm, unsigned long address, int write); -extern int remap_page_range(struct vm_area_struct *vma, unsigned long from, - unsigned long to, unsigned long size, pgprot_t prot); +int remap_pfn_range(struct vm_area_struct *, unsigned long, + unsigned long, unsigned long, pgprot_t); + +static inline __deprecated /* since 25 Sept 2004 -- wli */ +int remap_page_range(struct vm_area_struct *vma, unsigned long uvaddr, + unsigned long paddr, unsigned long size, pgprot_t prot) +{ + return remap_pfn_range(vma, uvaddr, paddr >> PAGE_SHIFT, size, prot); +} #ifdef CONFIG_PROC_FS void __vm_stat_account(struct mm_struct *, unsigned long, struct file *, long); diff --git a/include/linux/module.h b/include/linux/module.h index e5d2d6112f4b..f557855b02dd 100644 --- a/include/linux/module.h +++ b/include/linux/module.h @@ -141,11 +141,9 @@ extern struct module __this_module; customizations, eg "rh3" or "rusty1". Using this automatically adds a checksum of the .c files and the - local headers to the end. Use MODULE_VERSION("") if you want just - this. Macro includes room for this. + local headers in "srcversion". */ -#define MODULE_VERSION(_version) \ - MODULE_INFO(version, _version "\0xxxxxxxxxxxxxxxxxxxxxxxx") +#define MODULE_VERSION(_version) MODULE_INFO(version, _version) /* Given an address, look for it in the exception tables */ const struct exception_table_entry *search_exception_tables(unsigned long add); diff --git a/include/linux/moduleparam.h b/include/linux/moduleparam.h index 7a145cd86c40..4e6e7a51d74f 100644 --- a/include/linux/moduleparam.h +++ b/include/linux/moduleparam.h @@ -129,16 +129,16 @@ extern int param_set_invbool(const char *val, struct kernel_param *kp); extern int param_get_invbool(char *buffer, struct kernel_param *kp); #define param_check_invbool(name, p) __param_check(name, p, int) -/* Comma-separated array: num is set to number they actually specified. */ -#define module_param_array_named(name, array, type, num, perm) \ +/* Comma-separated array: *nump is set to number they actually specified. */ +#define module_param_array_named(name, array, type, nump, perm) \ static struct kparam_array __param_arr_##name \ - = { ARRAY_SIZE(array), &num, param_set_##type, param_get_##type,\ + = { ARRAY_SIZE(array), nump, param_set_##type, param_get_##type,\ sizeof(array[0]), array }; \ module_param_call(name, param_array_set, param_array_get, \ &__param_arr_##name, perm) -#define module_param_array(name, type, num, perm) \ - module_param_array_named(name, name, type, num, perm) +#define module_param_array(name, type, nump, perm) \ + module_param_array_named(name, name, type, nump, perm) extern int param_array_set(const char *val, struct kernel_param *kp); extern int param_array_get(char *buffer, struct kernel_param *kp); diff --git a/include/linux/msdos_fs.h b/include/linux/msdos_fs.h index d35fe747bd94..d6097bfc6715 100644 --- a/include/linux/msdos_fs.h +++ b/include/linux/msdos_fs.h @@ -87,8 +87,8 @@ #define FAT_FSINFO_SIG1 0x41615252 #define FAT_FSINFO_SIG2 0x61417272 -#define IS_FSINFO(x) (CF_LE_L((x)->signature1) == FAT_FSINFO_SIG1 \ - && CF_LE_L((x)->signature2) == FAT_FSINFO_SIG2) +#define IS_FSINFO(x) (le32_to_cpu((x)->signature1) == FAT_FSINFO_SIG1 \ + && le32_to_cpu((x)->signature2) == FAT_FSINFO_SIG2) /* * ioctl commands @@ -232,8 +232,6 @@ static inline void fatwchar_to16(__u8 *dst, const wchar_t *src, size_t len) extern int fat_access(struct super_block *sb, int nr, int new_value); extern int __fat_access(struct super_block *sb, int nr, int new_value); extern int fat_bmap(struct inode *inode, sector_t sector, sector_t *phys); -extern void fat_cache_init(struct super_block *sb); -extern void fat_cache_add(struct inode *inode, int f_clu, int d_clu); extern void fat_cache_inval_inode(struct inode *inode); extern int fat_get_cluster(struct inode *inode, int cluster, int *fclus, int *dclus); @@ -244,9 +242,6 @@ extern struct file_operations fat_dir_operations; extern int fat_search_long(struct inode *inode, const unsigned char *name, int name_len, int anycase, loff_t *spos, loff_t *lpos); -extern int fat_readdir(struct file *filp, void *dirent, filldir_t filldir); -extern int fat_dir_ioctl(struct inode * inode, struct file * filp, - unsigned int cmd, unsigned long arg); extern int fat_add_entries(struct inode *dir, int slots, struct buffer_head **bh, struct msdos_dir_entry **de, loff_t *i_pos); extern int fat_new_dir(struct inode *dir, struct inode *parent, int is_vfat); @@ -264,19 +259,13 @@ extern int fat_get_block(struct inode *inode, sector_t iblock, extern void fat_truncate(struct inode *inode); /* fat/inode.c */ -extern void fat_hash_init(void); extern void fat_attach(struct inode *inode, loff_t i_pos); extern void fat_detach(struct inode *inode); extern struct inode *fat_iget(struct super_block *sb, loff_t i_pos); extern struct inode *fat_build_inode(struct super_block *sb, struct msdos_dir_entry *de, loff_t i_pos, int *res); -extern void fat_delete_inode(struct inode *inode); -extern void fat_clear_inode(struct inode *inode); -extern void fat_put_super(struct super_block *sb); int fat_fill_super(struct super_block *sb, void *data, int silent, struct inode_operations *fs_dir_inode_ops, int isvfat); -extern int fat_statfs(struct super_block *sb, struct kstatfs *buf); -extern int fat_write_inode(struct inode *inode, int wait); extern int fat_notify_change(struct dentry * dentry, struct iattr * attr); /* fat/misc.c */ diff --git a/include/linux/msdos_fs_i.h b/include/linux/msdos_fs_i.h index f2383d22a831..b50018cf7e3d 100644 --- a/include/linux/msdos_fs_i.h +++ b/include/linux/msdos_fs_i.h @@ -7,10 +7,14 @@ * MS-DOS file system inode data in memory */ +#define FAT_CACHE_VALID 0 /* special case for valid cache */ + struct msdos_inode_info { - /* cache of lastest accessed cluster */ - int file_cluster; /* cluster number in the file. */ - int disk_cluster; /* cluster number on disk. */ + spinlock_t cache_lru_lock; + struct list_head cache_lru; + int nr_caches; + /* for avoiding the race between fat_free() and fat_get_cluster() */ + unsigned int cache_valid_id; loff_t mmu_private; int i_start; /* first cluster or 0 */ @@ -18,7 +22,7 @@ struct msdos_inode_info { int i_attrs; /* unused attribute bits */ int i_ctime_ms; /* unused change time in milliseconds */ loff_t i_pos; /* on-disk position of directory entry or 0 */ - struct list_head i_fat_hash; /* hash by i_location */ + struct hlist_node i_fat_hash; /* hash by i_location */ struct inode vfs_inode; }; diff --git a/include/linux/msdos_fs_sb.h b/include/linux/msdos_fs_sb.h index c79a172225d3..3310996efbcc 100644 --- a/include/linux/msdos_fs_sb.h +++ b/include/linux/msdos_fs_sb.h @@ -26,14 +26,9 @@ struct fat_mount_options { nocase:1; /* Does this need case conversion? 0=need case conversion*/ }; -#define FAT_CACHE_NR 8 /* number of FAT cache */ - -struct fat_cache { - int start_cluster; /* first cluster of the chain. */ - int file_cluster; /* cluster number in the file. */ - int disk_cluster; /* cluster number on disk. */ - struct fat_cache *next; /* next cache entry */ -}; +#define FAT_HASH_BITS 8 +#define FAT_HASH_SIZE (1UL << FAT_HASH_BITS) +#define FAT_HASH_MASK (FAT_HASH_SIZE-1) struct msdos_sb_info { unsigned short sec_per_clus; /* sectors/cluster */ @@ -58,8 +53,8 @@ struct msdos_sb_info { int dir_per_block; /* dir entries per block */ int dir_per_block_bits; /* log2(dir_per_block) */ - spinlock_t cache_lock; - struct fat_cache cache_array[FAT_CACHE_NR], *cache; + spinlock_t inode_hash_lock; + struct hlist_head inode_hashtable[FAT_HASH_SIZE]; }; #endif diff --git a/include/linux/mtd/cfi.h b/include/linux/mtd/cfi.h index a3efae0cd9a2..284f24851f1d 100644 --- a/include/linux/mtd/cfi.h +++ b/include/linux/mtd/cfi.h @@ -1,7 +1,7 @@ /* Common Flash Interface structures * See http://support.intel.com/design/flash/technote/index.htm - * $Id: cfi.h,v 1.45 2004/07/20 02:44:27 dwmw2 Exp $ + * $Id: cfi.h,v 1.48 2004/10/20 23:08:05 dwmw2 Exp $ */ #ifndef __MTD_CFI_H__ @@ -177,16 +177,19 @@ struct cfi_bri_query { uint32_t ConfField[1]; /* Not host ordered */ } __attribute__((packed)); -#define P_ID_NONE 0 -#define P_ID_INTEL_EXT 1 -#define P_ID_AMD_STD 2 -#define P_ID_INTEL_STD 3 -#define P_ID_AMD_EXT 4 -#define P_ID_ST_ADV 32 -#define P_ID_MITSUBISHI_STD 256 -#define P_ID_MITSUBISHI_EXT 257 -#define P_ID_SST_PAGE 258 -#define P_ID_RESERVED 65535 +#define P_ID_NONE 0x0000 +#define P_ID_INTEL_EXT 0x0001 +#define P_ID_AMD_STD 0x0002 +#define P_ID_INTEL_STD 0x0003 +#define P_ID_AMD_EXT 0x0004 +#define P_ID_WINBOND 0x0006 +#define P_ID_ST_ADV 0x0020 +#define P_ID_MITSUBISHI_STD 0x0100 +#define P_ID_MITSUBISHI_EXT 0x0101 +#define P_ID_SST_PAGE 0x0102 +#define P_ID_INTEL_PERFORMANCE 0x0200 +#define P_ID_INTEL_DATA 0x0210 +#define P_ID_RESERVED 0xffff #define CFI_MODE_CFI 1 @@ -350,17 +353,26 @@ static inline void cfi_spin_unlock(spinlock_t *mutex) struct cfi_extquery *cfi_read_pri(struct map_info *map, uint16_t adr, uint16_t size, const char* name); - struct cfi_fixup { uint16_t mfr; uint16_t id; - void (*fixup)(struct map_info *map, void* param); + void (*fixup)(struct mtd_info *mtd, void* param); void* param; }; #define CFI_MFR_ANY 0xffff #define CFI_ID_ANY 0xffff -void cfi_fixup(struct map_info *map, struct cfi_fixup* fixups); +#define CFI_MFR_AMD 0x0001 +#define CFI_MFR_ST 0x0020 /* STMicroelectronics */ + +void cfi_fixup(struct mtd_info *mtd, struct cfi_fixup* fixups); + +typedef int (*varsize_frob_t)(struct map_info *map, struct flchip *chip, + unsigned long adr, int len, void *thunk); + +int cfi_varsize_frob(struct mtd_info *mtd, varsize_frob_t frob, + loff_t ofs, size_t len, void *thunk); + #endif /* __MTD_CFI_H__ */ diff --git a/include/linux/mtd/doc2000.h b/include/linux/mtd/doc2000.h index 0fd8f49c649b..bc58c4f55ab0 100644 --- a/include/linux/mtd/doc2000.h +++ b/include/linux/mtd/doc2000.h @@ -6,7 +6,7 @@ * Copyright (C) 2002-2003 Greg Ungerer <gerg@snapgear.com> * Copyright (C) 2002-2003 SnapGear Inc * - * $Id: doc2000.h,v 1.22 2003/11/05 10:51:36 dwmw2 Exp $ + * $Id: doc2000.h,v 1.23 2004/09/16 23:26:08 gleixner Exp $ * * Released under GPL */ @@ -89,8 +89,8 @@ #define WriteDOC_(d, adr, reg) do{ *(volatile __u16 *)(((unsigned long)adr)+((reg)<<1)) = (__u16)d; wmb();} while(0) #define DOC_IOREMAP_LEN 0x4000 #else -#define ReadDOC_(adr, reg) readb(((unsigned long)adr) + (reg)) -#define WriteDOC_(d, adr, reg) writeb(d, ((unsigned long)adr) + (reg)) +#define ReadDOC_(adr, reg) readb((void __iomem *)(((unsigned long)adr) + (reg))) +#define WriteDOC_(d, adr, reg) writeb(d, (void __iomem *)(((unsigned long)adr) + (reg))) #define DOC_IOREMAP_LEN 0x2000 #endif @@ -168,7 +168,7 @@ struct Nand { struct DiskOnChip { unsigned long physadr; - unsigned long virtadr; + void __iomem *virtadr; unsigned long totlen; unsigned char ChipID; /* Type of DiskOnChip */ int ioreg; diff --git a/include/linux/mtd/gen_probe.h b/include/linux/mtd/gen_probe.h index 2d66b33f805d..f6208098660c 100644 --- a/include/linux/mtd/gen_probe.h +++ b/include/linux/mtd/gen_probe.h @@ -10,7 +10,7 @@ #include <linux/mtd/flashchip.h> #include <linux/mtd/map.h> #include <linux/mtd/cfi.h> -#include <asm/bitops.h> +#include <linux/bitops.h> struct chip_probe { char *name; diff --git a/include/linux/mtd/map.h b/include/linux/mtd/map.h index 278d0f30de20..a960be2cc33c 100644 --- a/include/linux/mtd/map.h +++ b/include/linux/mtd/map.h @@ -1,6 +1,6 @@ /* Overhauled routines for dealing with different mmap regions of flash */ -/* $Id: map.h,v 1.43 2004/07/14 13:30:27 dwmw2 Exp $ */ +/* $Id: map.h,v 1.45 2004/09/21 14:31:17 bjd Exp $ */ #ifndef __LINUX_MTD_MAP_H__ #define __LINUX_MTD_MAP_H__ @@ -8,6 +8,7 @@ #include <linux/config.h> #include <linux/types.h> #include <linux/list.h> +#include <linux/mtd/compatmac.h> #include <asm/unaligned.h> #include <asm/system.h> #include <asm/io.h> @@ -55,6 +56,11 @@ #define map_bankwidth_is_4(map) (0) #endif +/* ensure we never evaluate anything shorted than an unsigned long + * to zero, and ensure we'll never miss the end of an comparison (bjd) */ + +#define map_calc_words(map) ((map_bankwidth(map) + (sizeof(unsigned long)-1))/ sizeof(unsigned long)) + #ifdef CONFIG_MTD_MAP_BANK_WIDTH_8 # ifdef map_bankwidth # undef map_bankwidth @@ -63,12 +69,12 @@ # undef map_bankwidth_is_large # define map_bankwidth_is_large(map) (map_bankwidth(map) > BITS_PER_LONG/8) # undef map_words -# define map_words(map) (map_bankwidth(map) / sizeof(unsigned long)) +# define map_words(map) map_calc_words(map) # endif # else # define map_bankwidth(map) 8 # define map_bankwidth_is_large(map) (BITS_PER_LONG < 64) -# define map_words(map) (map_bankwidth(map) / sizeof(unsigned long)) +# define map_words(map) map_calc_words(map) # endif #define map_bankwidth_is_8(map) (map_bankwidth(map) == 8) #undef MAX_MAP_BANKWIDTH @@ -84,11 +90,11 @@ # undef map_bankwidth_is_large # define map_bankwidth_is_large(map) (map_bankwidth(map) > BITS_PER_LONG/8) # undef map_words -# define map_words(map) (map_bankwidth(map) / sizeof(unsigned long)) +# define map_words(map) map_calc_words(map) # else # define map_bankwidth(map) 16 # define map_bankwidth_is_large(map) (1) -# define map_words(map) (map_bankwidth(map) / sizeof(unsigned long)) +# define map_words(map) map_calc_words(map) # endif #define map_bankwidth_is_16(map) (map_bankwidth(map) == 16) #undef MAX_MAP_BANKWIDTH @@ -104,11 +110,11 @@ # undef map_bankwidth_is_large # define map_bankwidth_is_large(map) (map_bankwidth(map) > BITS_PER_LONG/8) # undef map_words -# define map_words(map) (map_bankwidth(map) / sizeof(unsigned long)) +# define map_words(map) map_calc_words(map) # else # define map_bankwidth(map) 32 # define map_bankwidth_is_large(map) (1) -# define map_words(map) (map_bankwidth(map) / sizeof(unsigned long)) +# define map_words(map) map_calc_words(map) # endif #define map_bankwidth_is_32(map) (map_bankwidth(map) == 32) #undef MAX_MAP_BANKWIDTH diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 7de9f8dfa8ab..9453cb58c683 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -5,7 +5,7 @@ * Steven J. Hill <sjhill@realitydiluted.com> * Thomas Gleixner <tglx@linutronix.de> * - * $Id: nand.h,v 1.63 2004/07/07 16:29:43 gleixner Exp $ + * $Id: nand.h,v 1.66 2004/10/02 10:07:08 gleixner Exp $ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -212,6 +212,18 @@ typedef enum { FL_CACHEDPRG, } nand_state_t; +/* Keep gcc happy */ +struct nand_chip; + +/** + * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices + * @lock: protection lock + * @active: the mtd device which holds the controller currently + */ +struct nand_hw_control { + spinlock_t lock; + struct nand_chip *active; +}; /** * struct nand_chip - NAND Private Flash Chip Data @@ -265,12 +277,13 @@ typedef enum { * @bbt: [INTERN] bad block table pointer * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup * @bbt_md: [REPLACEABLE] bad block table mirror descriptor + * @controller: [OPTIONAL] a pointer to a hardware controller structure which is shared among multiple independend devices * @priv: [OPTIONAL] pointer to private chip date */ struct nand_chip { - unsigned long IO_ADDR_R; - unsigned long IO_ADDR_W; + void __iomem *IO_ADDR_R; + void __iomem *IO_ADDR_W; u_char (*read_byte)(struct mtd_info *mtd); void (*write_byte)(struct mtd_info *mtd, u_char byte); @@ -317,6 +330,7 @@ struct nand_chip { uint8_t *bbt; struct nand_bbt_descr *bbt_td; struct nand_bbt_descr *bbt_md; + struct nand_hw_control *controller; void *priv; }; diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index 010a623c3bdf..9472745b6510 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -697,8 +697,12 @@ extern int netdev_nit; static inline int netif_rx_ni(struct sk_buff *skb) { int err = netif_rx(skb); + + preempt_disable(); if (softirq_pending(smp_processor_id())) do_softirq(); + preempt_enable(); + return err; } diff --git a/include/linux/nfs4.h b/include/linux/nfs4.h index 96974ab10f27..5ca8a8d8ccdf 100644 --- a/include/linux/nfs4.h +++ b/include/linux/nfs4.h @@ -35,6 +35,7 @@ #define NFS4_FH_VOL_RENAME 0x0008 #define NFS4_OPEN_RESULT_CONFIRM 0x0002 +#define NFS4_OPEN_RESULT_LOCKTYPE_POSIX 0x0004 #define NFS4_SHARE_ACCESS_READ 0x0001 #define NFS4_SHARE_ACCESS_WRITE 0x0002 diff --git a/include/linux/nfsd/state.h b/include/linux/nfsd/state.h index 97d84c887853..a56399b985a4 100644 --- a/include/linux/nfsd/state.h +++ b/include/linux/nfsd/state.h @@ -38,6 +38,7 @@ #define _NFSD4_STATE_H #include <linux/list.h> +#include <linux/kref.h> #include <linux/sunrpc/clnt.h> #define NFS4_OPAQUE_LIMIT 1024 @@ -168,6 +169,7 @@ struct nfs4_replay { * reaped by laundramat thread after lease period. */ struct nfs4_stateowner { + struct kref so_ref; struct list_head so_idhash; /* hash by so_id */ struct list_head so_strhash; /* hash by op_name */ struct list_head so_perclient; /* nfs4_client->cl_perclient */ @@ -248,4 +250,18 @@ extern void nfs4_lock_state(void); extern void nfs4_unlock_state(void); extern int nfs4_in_grace(void); extern int nfs4_check_open_reclaim(clientid_t *clid); +extern void nfs4_free_stateowner(struct kref *kref); + +static inline void +nfs4_put_stateowner(struct nfs4_stateowner *so) +{ + kref_put(&so->so_ref, nfs4_free_stateowner); +} + +static inline void +nfs4_get_stateowner(struct nfs4_stateowner *so) +{ + kref_get(&so->so_ref); +} + #endif /* NFSD4_STATE_H */ diff --git a/include/linux/nfsd/xdr4.h b/include/linux/nfsd/xdr4.h index bf94561ca623..d629b5e55d90 100644 --- a/include/linux/nfsd/xdr4.h +++ b/include/linux/nfsd/xdr4.h @@ -116,6 +116,7 @@ struct nfsd4_link { }; struct nfsd4_lock_denied { + clientid_t ld_clientid; struct nfs4_stateowner *ld_sop; u64 ld_start; u64 ld_length; diff --git a/include/linux/pci.h b/include/linux/pci.h index 61ba98e2a3d8..5d806aca0b30 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1,5 +1,5 @@ /* - * $Id: pci.h,v 1.87 1998/10/11 15:13:12 mj Exp $ + * pci.h * * PCI defines and function prototypes * Copyright 1994, Drew Eckhardt @@ -676,6 +676,12 @@ struct pci_driver { .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID +/* + * pci_module_init is obsolete, this stays here till we fix up all usages of it + * in the tree. + */ +#define pci_module_init pci_register_driver + /* these external functions are only available when PCI support is enabled */ #ifdef CONFIG_PCI @@ -721,10 +727,6 @@ extern void pci_remove_bus_device(struct pci_dev *dev); struct pci_dev *pci_find_device (unsigned int vendor, unsigned int device, const struct pci_dev *from); struct pci_dev *pci_find_device_reverse (unsigned int vendor, unsigned int device, const struct pci_dev *from); -struct pci_dev *pci_find_subsys (unsigned int vendor, unsigned int device, - unsigned int ss_vendor, unsigned int ss_device, - const struct pci_dev *from); -struct pci_dev *pci_find_class (unsigned int class, const struct pci_dev *from); struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn); int pci_find_capability (struct pci_dev *dev, int cap); int pci_find_ext_capability (struct pci_dev *dev, int cap); @@ -735,6 +737,8 @@ struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device, unsigned int ss_vendor, unsigned int ss_device, struct pci_dev *from); struct pci_dev *pci_get_slot (struct pci_bus *bus, unsigned int devfn); +struct pci_dev *pci_get_class (unsigned int class, struct pci_dev *from); +int pci_dev_present(const struct pci_device_id *ids); int pci_bus_read_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 *val); int pci_bus_read_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 *val); @@ -781,8 +785,8 @@ int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask); int pci_assign_resource(struct pci_dev *dev, int i); /* Power management related routines */ -int pci_save_state(struct pci_dev *dev, u32 *buffer); -int pci_restore_state(struct pci_dev *dev, u32 *buffer); +int pci_save_state(struct pci_dev *dev); +int pci_restore_state(struct pci_dev *dev); int pci_set_power_state(struct pci_dev *dev, int state); int pci_enable_wake(struct pci_dev *dev, u32 state, int enable); @@ -862,10 +866,6 @@ extern void msi_remove_pci_irq_vectors(struct pci_dev *dev); #include <asm/pci.h> -/* Backwards compat, remove in 2.7.x */ -#define pci_dma_sync_single pci_dma_sync_single_for_cpu -#define pci_dma_sync_sg pci_dma_sync_sg_for_cpu - /* * If the system does not have PCI, clearly these return errors. Define * these as simple inline functions to avoid hair in drivers. @@ -884,16 +884,9 @@ _PCI_NOP_ALL(write,) static inline struct pci_dev *pci_find_device(unsigned int vendor, unsigned int device, const struct pci_dev *from) { return NULL; } -static inline struct pci_dev *pci_find_class(unsigned int class, const struct pci_dev *from) -{ return NULL; } - static inline struct pci_dev *pci_find_slot(unsigned int bus, unsigned int devfn) { return NULL; } -static inline struct pci_dev *pci_find_subsys(unsigned int vendor, unsigned int device, -unsigned int ss_vendor, unsigned int ss_device, const struct pci_dev *from) -{ return NULL; } - static inline struct pci_dev *pci_get_device (unsigned int vendor, unsigned int device, struct pci_dev *from) { return NULL; } @@ -901,10 +894,15 @@ static inline struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int unsigned int ss_vendor, unsigned int ss_device, struct pci_dev *from) { return NULL; } +static inline struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from) +{ return NULL; } + +#define pci_dev_present(ids) (0) +#define pci_dev_put(dev) do { } while (0) + static inline void pci_set_master(struct pci_dev *dev) { } static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } static inline void pci_disable_device(struct pci_dev *dev) { } -static inline int pci_module_init(struct pci_driver *drv) { return -ENODEV; } static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) { return -EIO; } static inline int pci_dac_set_dma_mask(struct pci_dev *dev, u64 mask) { return -EIO; } static inline int pci_assign_resource(struct pci_dev *dev, int i) { return -EBUSY;} @@ -915,8 +913,8 @@ static inline int pci_find_ext_capability (struct pci_dev *dev, int cap) {return static inline const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev) { return NULL; } /* Power management related routines */ -static inline int pci_save_state(struct pci_dev *dev, u32 *buffer) { return 0; } -static inline int pci_restore_state(struct pci_dev *dev, u32 *buffer) { return 0; } +static inline int pci_save_state(struct pci_dev *dev) { return 0; } +static inline int pci_restore_state(struct pci_dev *dev) { return 0; } static inline int pci_set_power_state(struct pci_dev *dev, int state) { return 0; } static inline int pci_enable_wake(struct pci_dev *dev, u32 state, int enable) { return 0; } @@ -925,19 +923,6 @@ static inline int pci_enable_wake(struct pci_dev *dev, u32 state, int enable) { #else /* - * a helper function which helps ensure correct pci_driver - * setup and cleanup for commonly-encountered hotplug/modular cases - * - * This MUST stay in a header, as it checks for -DMODULE - */ -static inline int pci_module_init(struct pci_driver *drv) -{ - int rc = pci_register_driver (drv); - - return rc < 0 ? rc : 0; -} - -/* * PCI domain support. Sometimes called PCI segment (eg by ACPI), * a PCI domain is defined to be a set of PCI busses which share * configuration space. @@ -1010,6 +995,7 @@ struct pci_fixup { enum pci_fixup_pass { pci_fixup_header, /* Called immediately after reading configuration header */ pci_fixup_final, /* Final phase of device fixups */ + pci_fixup_enable, /* pci_enable_device() time */ }; /* Anonymous variables would be nice... */ @@ -1023,6 +1009,12 @@ enum pci_fixup_pass { __attribute__((__section__(".pci_fixup_final"))) = { \ vendor, device, hook }; +#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ + static struct pci_fixup __pci_fixup_##vendor##device##hook __attribute_used__ \ + __attribute__((__section__(".pci_fixup_enable"))) = { \ + vendor, device, hook }; + + void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); extern int pci_pci_problems; diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 271f3eb29a60..f2cdec811f1f 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -569,6 +569,7 @@ #define PCI_DEVICE_ID_NEC_PCX2 0x0046 /* PowerVR */ #define PCI_DEVICE_ID_NEC_NILE4 0x005a #define PCI_DEVICE_ID_NEC_VRC5476 0x009b +#define PCI_DEVICE_ID_NEC_VRC4173 0x00a5 #define PCI_DEVICE_ID_NEC_VRC5477_AC97 0x00a6 #define PCI_DEVICE_ID_NEC_PC9821CS01 0x800c /* PC-9821-CS01 */ #define PCI_DEVICE_ID_NEC_PC9821NRB06 0x800d /* PC-9821NR-B06 */ @@ -1199,6 +1200,7 @@ #define PCI_DEVICE_ID_VIA_8763_0 0x0198 #define PCI_DEVICE_ID_VIA_8380_0 0x0204 #define PCI_DEVICE_ID_VIA_3238_0 0x0238 +#define PCI_DEVICE_ID_VIA_PT880 0x0258 #define PCI_DEVICE_ID_VIA_PX8X0_0 0x0259 #define PCI_DEVICE_ID_VIA_3269_0 0x0269 #define PCI_DEVICE_ID_VIA_K8T800PRO_0 0x0282 @@ -1257,7 +1259,6 @@ #define PCI_DEVICE_ID_VIA_8377_0 0x3189 #define PCI_DEVICE_ID_VIA_8378_0 0x3205 #define PCI_DEVICE_ID_VIA_8783_0 0x3208 -#define PCI_DEVICE_ID_VIA_PT880 0x3258 #define PCI_DEVICE_ID_VIA_P4M400 0x3209 #define PCI_DEVICE_ID_VIA_8237 0x3227 #define PCI_DEVICE_ID_VIA_3296_0 0x0296 diff --git a/include/linux/posix-timers.h b/include/linux/posix-timers.h index ec4910e37c65..e7c08acbe796 100644 --- a/include/linux/posix-timers.h +++ b/include/linux/posix-timers.h @@ -4,6 +4,26 @@ #include <linux/spinlock.h> #include <linux/list.h> +/* POSIX.1b interval timer structure. */ +struct k_itimer { + struct list_head list; /* free/ allocate list */ + spinlock_t it_lock; + clockid_t it_clock; /* which timer type */ + timer_t it_id; /* timer id */ + int it_overrun; /* overrun on pending signal */ + int it_overrun_last; /* overrun on last delivered signal */ + int it_requeue_pending; /* waiting to requeue this timer */ + int it_sigev_notify; /* notify word of sigevent struct */ + int it_sigev_signo; /* signo word of sigevent struct */ + sigval_t it_sigev_value; /* value word of sigevent struct */ + unsigned long it_incr; /* interval specified in jiffies */ + struct task_struct *it_process; /* process to send signal to */ + struct timer_list it_timer; + struct sigqueue *sigq; /* signal queue entry. */ + struct list_head abs_timer_entry; /* clock abs_timer_list */ + struct timespec wall_to_prev; /* wall_to_monotonic used when set */ +}; + struct k_clock_abs { struct list_head list; spinlock_t lock; @@ -13,9 +33,10 @@ struct k_clock { struct k_clock_abs *abs_struct; int (*clock_set) (struct timespec * tp); int (*clock_get) (struct timespec * tp); - int (*nsleep) (int flags, - struct timespec * new_setting, - struct itimerspec * old_setting); + int (*timer_create) (int which_clock, struct sigevent __user *timer_event_spec, + timer_t __user * created_timer_id); + int (*nsleep) (int which_clock, int flags, + struct timespec * t); int (*timer_set) (struct k_itimer * timr, int flags, struct itimerspec * new_setting, struct itimerspec * old_setting); @@ -23,6 +44,17 @@ struct k_clock { void (*timer_get) (struct k_itimer * timr, struct itimerspec * cur_setting); }; + +void register_posix_clock(int clock_id, struct k_clock *new_clock); + +/* Error handlers for timer_create, nanosleep and settime */ +int do_posix_clock_notimer_create(int which_clock, + struct sigevent __user *time_event_spec, + timer_t __user *created_timer_id); + +int do_posix_clock_nonanosleep(int which_clock, int flags, struct timespec * t); +int do_posix_clock_nosettime(struct timespec *tp); + struct now_struct { unsigned long jiffies; }; @@ -42,3 +74,4 @@ struct now_struct { } \ }while (0) #endif + diff --git a/include/linux/rbtree.h b/include/linux/rbtree.h index 3ae0c6e140af..4b7cc4fe366d 100644 --- a/include/linux/rbtree.h +++ b/include/linux/rbtree.h @@ -113,8 +113,7 @@ struct rb_root }; #define RB_ROOT (struct rb_root) { NULL, } -#define rb_entry(ptr, type, member) \ - ((type *)((char *)(ptr)-(unsigned long)(&((type *)0)->member))) +#define rb_entry(ptr, type, member) container_of(ptr, type, member) extern void rb_insert_color(struct rb_node *, struct rb_root *); extern void rb_erase(struct rb_node *, struct rb_root *); diff --git a/include/linux/reiserfs_fs_sb.h b/include/linux/reiserfs_fs_sb.h index 891418bb525a..ba465f763066 100644 --- a/include/linux/reiserfs_fs_sb.h +++ b/include/linux/reiserfs_fs_sb.h @@ -467,6 +467,7 @@ enum reiserfs_mount_options { REISERFS_TEST2, REISERFS_TEST3, REISERFS_TEST4, + REISERFS_UNSUPPORTED_OPT, }; #define reiserfs_r5_hash(s) (REISERFS_SB(s)->s_mount_opt & (1 << FORCE_R5_HASH)) diff --git a/include/linux/rslib.h b/include/linux/rslib.h new file mode 100644 index 000000000000..980c8f74d8dc --- /dev/null +++ b/include/linux/rslib.h @@ -0,0 +1,105 @@ +/* + * include/linux/rslib.h + * + * Overview: + * Generic Reed Solomon encoder / decoder library + * + * Copyright (C) 2004 Thomas Gleixner (tglx@linutronix.de) + * + * RS code lifted from reed solomon library written by Phil Karn + * Copyright 2002 Phil Karn, KA9Q + * + * $Id: rslib.h,v 1.3 2004/10/05 22:08:22 gleixner Exp $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _RSLIB_H_ +#define _RSLIB_H_ + +#include <linux/list.h> + +/** + * struct rs_control - rs control structure + * + * @mm: Bits per symbol + * @nn: Symbols per block (= (1<<mm)-1) + * @alpha_to: log lookup table + * @index_of: Antilog lookup table + * @genpoly: Generator polynomial + * @nroots: Number of generator roots = number of parity symbols + * @fcr: First consecutive root, index form + * @prim: Primitive element, index form + * @iprim: prim-th root of 1, index form + * @gfpoly: The primitive generator polynominal + * @users: Users of this structure + * @list: List entry for the rs control list +*/ +struct rs_control { + int mm; + int nn; + uint16_t *alpha_to; + uint16_t *index_of; + uint16_t *genpoly; + int nroots; + int fcr; + int prim; + int iprim; + int gfpoly; + int users; + struct list_head list; +}; + +/* General purpose RS codec, 8-bit data width, symbol width 1-15 bit */ +#ifdef CONFIG_REED_SOLOMON_ENC8 +int encode_rs8(struct rs_control *rs, uint8_t *data, int len, uint16_t *par, + uint16_t invmsk); +#endif +#ifdef CONFIG_REED_SOLOMON_DEC8 +int decode_rs8(struct rs_control *rs, uint8_t *data, uint16_t *par, int len, + uint16_t *s, int no_eras, int *eras_pos, uint16_t invmsk, + uint16_t *corr); +#endif + +/* General purpose RS codec, 16-bit data width, symbol width 1-15 bit */ +#ifdef CONFIG_REED_SOLOMON_ENC16 +int encode_rs16(struct rs_control *rs, uint16_t *data, int len, uint16_t *par, + uint16_t invmsk); +#endif +#ifdef CONFIG_REED_SOLOMON_DEC16 +int decode_rs16(struct rs_control *rs, uint16_t *data, uint16_t *par, int len, + uint16_t *s, int no_eras, int *eras_pos, uint16_t invmsk, + uint16_t *corr); +#endif + +/* Create or get a matching rs control structure */ +struct rs_control *init_rs(int symsize, int gfpoly, int fcr, int prim, + int nroots); + +/* Release a rs control structure */ +void free_rs(struct rs_control *rs); + +/** modulo replacement for galois field arithmetics + * + * @rs: the rs control structure + * @x: the value to reduce + * + * where + * rs->mm = number of bits per symbol + * rs->nn = (2^rs->mm) - 1 + * + * Simple arithmetic modulo would return a wrong result for values + * >= 3 * rs->nn +*/ +static inline int rs_modnn(struct rs_control *rs, int x) +{ + while (x >= rs->nn) { + x -= rs->nn; + x = (x >> rs->mm) + (x & rs->nn); + } + return x; +} + +#endif diff --git a/include/linux/rtnetlink.h b/include/linux/rtnetlink.h index ac4528ead16e..9bb86160c2f2 100644 --- a/include/linux/rtnetlink.h +++ b/include/linux/rtnetlink.h @@ -698,6 +698,7 @@ enum TCA_XSTATS, TCA_RATE, TCA_FCNT, + TCA_STATS2, __TCA_MAX }; diff --git a/include/linux/scatterlist.h b/include/linux/scatterlist.h new file mode 100644 index 000000000000..7f717e95ae37 --- /dev/null +++ b/include/linux/scatterlist.h @@ -0,0 +1,14 @@ +#ifndef _LINUX_SCATTERLIST_H +#define _LINUX_SCATTERLIST_H + +static inline void sg_init_one(struct scatterlist *sg, + u8 *buf, unsigned int buflen) +{ + memset(sg, 0, sizeof(*sg)); + + sg->page = virt_to_page(buf); + sg->offset = offset_in_page(buf); + sg->length = buflen; +} + +#endif /* _LINUX_SCATTERLIST_H */ diff --git a/include/linux/sched.h b/include/linux/sched.h index c8f981f108d4..04c8d47e8654 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -218,7 +218,7 @@ struct mm_struct { struct rw_semaphore mmap_sem; spinlock_t page_table_lock; /* Protects task page tables and mm->rss */ - struct list_head mmlist; /* List of all active mm's. These are globally strung + struct list_head mmlist; /* List of maybe swapped mm's. These are globally strung * together off init_mm.mmlist, and are protected * by mmlist_lock */ @@ -252,8 +252,6 @@ struct mm_struct { struct kioctx default_kioctx; }; -extern int mmlist_nr; - struct sighand_struct { atomic_t count; struct k_sigaction action[_NSIG]; @@ -377,26 +375,6 @@ typedef struct prio_array prio_array_t; struct backing_dev_info; struct reclaim_state; -/* POSIX.1b interval timer structure. */ -struct k_itimer { - struct list_head list; /* free/ allocate list */ - spinlock_t it_lock; - clockid_t it_clock; /* which timer type */ - timer_t it_id; /* timer id */ - int it_overrun; /* overrun on pending signal */ - int it_overrun_last; /* overrun on last delivered signal */ - int it_requeue_pending; /* waiting to requeue this timer */ - int it_sigev_notify; /* notify word of sigevent struct */ - int it_sigev_signo; /* signo word of sigevent struct */ - sigval_t it_sigev_value; /* value word of sigevent struct */ - unsigned long it_incr; /* interval specified in jiffies */ - struct task_struct *it_process; /* process to send signal to */ - struct timer_list it_timer; - struct sigqueue *sigq; /* signal queue entry. */ - struct list_head abs_timer_entry; /* clock abs_timer_list */ - struct timespec wall_to_prev; /* wall_to_monotonic used when set */ -}; - #ifdef CONFIG_SCHEDSTATS struct sched_info { /* cumulative counters */ @@ -722,6 +700,7 @@ do { if (atomic_dec_and_test(&(tsk)->usage)) __put_task_struct(tsk); } while(0) #define PF_SWAPOFF 0x00080000 /* I am in swapoff */ #define PF_LESS_THROTTLE 0x00100000 /* Throttle me less: I clean memory */ #define PF_SYNCWRITE 0x00200000 /* I am doing a sync write */ +#define PF_BORROWED_MM 0x00400000 /* I am a kthread doing use_mm */ #ifdef CONFIG_SMP extern int set_cpus_allowed(task_t *p, cpumask_t new_mask); diff --git a/include/linux/security.h b/include/linux/security.h index ab0941c9fca7..c1792f3fb6ca 100644 --- a/include/linux/security.h +++ b/include/linux/security.h @@ -40,6 +40,7 @@ struct ctl_table; * as the default capabilities functions */ extern int cap_capable (struct task_struct *tsk, int cap); +extern int cap_settime (struct timespec *ts, struct timezone *tz); extern int cap_ptrace (struct task_struct *parent, struct task_struct *child); extern int cap_capget (struct task_struct *target, kernel_cap_t *effective, kernel_cap_t *inheritable, kernel_cap_t *permitted); extern int cap_capset_check (struct task_struct *target, kernel_cap_t *effective, kernel_cap_t *inheritable, kernel_cap_t *permitted); @@ -1001,6 +1002,12 @@ struct swap_info_struct; * See the syslog(2) manual page for an explanation of the @type values. * @type contains the type of action. * Return 0 if permission is granted. + * @settime: + * Check permission to change the system time. + * struct timespec and timezone are defined in include/linux/time.h + * @ts contains new time + * @tz contains new timezone + * Return 0 if permission is granted. * @vm_enough_memory: * Check permissions for allocating a new virtual mapping. * @pages contains the number of pages. @@ -1036,6 +1043,7 @@ struct security_operations { int (*quotactl) (int cmds, int type, int id, struct super_block * sb); int (*quota_on) (struct file * f); int (*syslog) (int type); + int (*settime) (struct timespec *ts, struct timezone *tz); int (*vm_enough_memory) (long pages); int (*bprm_alloc_security) (struct linux_binprm * bprm); @@ -1291,6 +1299,12 @@ static inline int security_syslog(int type) return security_ops->syslog(type); } +static inline int security_settime(struct timespec *ts, struct timezone *tz) +{ + return security_ops->settime(ts, tz); +} + + static inline int security_vm_enough_memory(long pages) { return security_ops->vm_enough_memory(pages); @@ -1963,6 +1977,11 @@ static inline int security_syslog(int type) return cap_syslog(type); } +static inline int security_settime(struct timespec *ts, struct timezone *tz) +{ + return cap_settime(ts, tz); +} + static inline int security_vm_enough_memory(long pages) { return cap_vm_enough_memory(pages); diff --git a/include/linux/serial_reg.h b/include/linux/serial_reg.h index 7b2414bd5837..faa0c3662bc3 100644 --- a/include/linux/serial_reg.h +++ b/include/linux/serial_reg.h @@ -14,47 +14,63 @@ #ifndef _LINUX_SERIAL_REG_H #define _LINUX_SERIAL_REG_H -#define UART_RX 0 /* In: Receive buffer (DLAB=0) */ -#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */ -#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */ -#define UART_TRG 0 /* (LCR=BF) FCTR bit 7 selects Rx or Tx - * In: Fifo count - * Out: Fifo custom trigger levels - * XR16C85x only */ +/* + * DLAB=0 + */ +#define UART_RX 0 /* In: Receive buffer */ +#define UART_TX 0 /* Out: Transmit buffer */ -#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */ #define UART_IER 1 /* Out: Interrupt Enable Register */ -#define UART_FCTR 1 /* (LCR=BF) Feature Control Register - * XR16C85x only */ +#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ +#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ +#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ +#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ +/* + * Sleep mode for ST16650 and TI16750. For the ST16650, EFR[4]=1 + */ +#define UART_IERX_SLEEP 0x10 /* Enable sleep mode */ #define UART_IIR 2 /* In: Interrupt ID Register */ -#define UART_FCR 2 /* Out: FIFO Control Register */ -#define UART_EFR 2 /* I/O: Extended Features Register */ - /* (DLAB=1, 16C660 only) */ +#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ +#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ +#define UART_IIR_MSI 0x00 /* Modem status interrupt */ +#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ +#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ +#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ -#define UART_LCR 3 /* Out: Line Control Register */ -#define UART_MCR 4 /* Out: Modem Control Register */ -#define UART_LSR 5 /* In: Line Status Register */ -#define UART_MSR 6 /* In: Modem Status Register */ -#define UART_SCR 7 /* I/O: Scratch Register */ -#define UART_EMSR 7 /* (LCR=BF) Extended Mode Select Register - * FCTR bit 6 selects SCR or EMSR - * XR16c85x only */ - -/* - * These are the definitions for the FIFO Control Register - * (16650 only) - */ +#define UART_FCR 2 /* Out: FIFO Control Register */ #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ +/* + * Note: The FIFO trigger levels are chip specific: + * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11 + * PC16550D: 1 4 8 14 xx xx xx xx + * TI16C550A: 1 4 8 14 xx xx xx xx + * TI16C550C: 1 4 8 14 xx xx xx xx + * ST16C550: 1 4 8 14 xx xx xx xx + * ST16C650: 8 16 24 28 16 8 24 30 PORT_16650V2 + * NS16C552: 1 4 8 14 xx xx xx xx + * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654 + * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750 + * TI16C752: 8 16 56 60 8 16 32 56 + */ +#define UART_FCR_R_TRIG_00 0x00 +#define UART_FCR_R_TRIG_01 0x40 +#define UART_FCR_R_TRIG_10 0x80 +#define UART_FCR_R_TRIG_11 0xc0 +#define UART_FCR_T_TRIG_00 0x00 +#define UART_FCR_T_TRIG_01 0x10 +#define UART_FCR_T_TRIG_10 0x20 +#define UART_FCR_T_TRIG_11 0x30 + #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ -/* 16650 redefinitions */ +/* 16650 definitions */ #define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */ #define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */ #define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */ @@ -63,83 +79,129 @@ #define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */ #define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */ #define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */ -/* TI 16750 definitions */ -#define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode */ +#define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode (TI16C750) */ +#define UART_LCR 3 /* Out: Line Control Register */ /* - * These are the definitions for the Line Control Register - * * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. */ -#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ -#define UART_LCR_SBC 0x40 /* Set break control */ -#define UART_LCR_SPAR 0x20 /* Stick parity (?) */ -#define UART_LCR_EPAR 0x10 /* Even parity select */ -#define UART_LCR_PARITY 0x08 /* Parity Enable */ -#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */ -#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ -#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ -#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ -#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ +#define UART_LCR_SBC 0x40 /* Set break control */ +#define UART_LCR_SPAR 0x20 /* Stick parity (?) */ +#define UART_LCR_EPAR 0x10 /* Even parity select */ +#define UART_LCR_PARITY 0x08 /* Parity Enable */ +#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 bit, 1=2 bits */ +#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ +#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ +#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ + +#define UART_MCR 4 /* Out: Modem Control Register */ +#define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */ +#define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */ +#define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */ +#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */ +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ +#define UART_MCR_OUT2 0x08 /* Out2 complement */ +#define UART_MCR_OUT1 0x04 /* Out1 complement */ +#define UART_MCR_RTS 0x02 /* RTS complement */ +#define UART_MCR_DTR 0x01 /* DTR complement */ + +#define UART_LSR 5 /* In: Line Status Register */ +#define UART_LSR_TEMT 0x40 /* Transmitter empty */ +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ +#define UART_LSR_BI 0x10 /* Break interrupt indicator */ +#define UART_LSR_FE 0x08 /* Frame error indicator */ +#define UART_LSR_PE 0x04 /* Parity error indicator */ +#define UART_LSR_OE 0x02 /* Overrun error indicator */ +#define UART_LSR_DR 0x01 /* Receiver data ready */ + +#define UART_MSR 6 /* In: Modem Status Register */ +#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ +#define UART_MSR_RI 0x40 /* Ring Indicator */ +#define UART_MSR_DSR 0x20 /* Data Set Ready */ +#define UART_MSR_CTS 0x10 /* Clear to Send */ +#define UART_MSR_DDCD 0x08 /* Delta DCD */ +#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ +#define UART_MSR_DDSR 0x02 /* Delta DSR */ +#define UART_MSR_DCTS 0x01 /* Delta CTS */ +#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ + +#define UART_SCR 7 /* I/O: Scratch Register */ /* - * These are the definitions for the Line Status Register + * DLAB=1 */ -#define UART_LSR_TEMT 0x40 /* Transmitter empty */ -#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ -#define UART_LSR_BI 0x10 /* Break interrupt indicator */ -#define UART_LSR_FE 0x08 /* Frame error indicator */ -#define UART_LSR_PE 0x04 /* Parity error indicator */ -#define UART_LSR_OE 0x02 /* Overrun error indicator */ -#define UART_LSR_DR 0x01 /* Receiver data ready */ +#define UART_DLL 0 /* Out: Divisor Latch Low */ +#define UART_DLM 1 /* Out: Divisor Latch High */ /* - * These are the definitions for the Interrupt Identification Register + * LCR=0xBF (or DLAB=1 for 16C660) + */ +#define UART_EFR 2 /* I/O: Extended Features Register */ +#define UART_EFR_CTS 0x80 /* CTS flow control */ +#define UART_EFR_RTS 0x40 /* RTS flow control */ +#define UART_EFR_SCD 0x20 /* Special character detect */ +#define UART_EFR_ECB 0x10 /* Enhanced control bit */ +/* + * the low four bits control software flow control */ -#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ -#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ - -#define UART_IIR_MSI 0x00 /* Modem status interrupt */ -#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ -#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ -#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ /* - * These are the definitions for the Interrupt Enable Register + * LCR=0xBF, TI16C752, ST16650, ST16650A, ST16654 */ -#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ -#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ -#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ -#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ +#define UART_XON1 4 /* I/O: Xon character 1 */ +#define UART_XON2 5 /* I/O: Xon character 2 */ +#define UART_XOFF1 6 /* I/O: Xoff character 1 */ +#define UART_XOFF2 7 /* I/O: Xoff character 2 */ + /* - * Sleep mode for ST16650 and TI16750. - * Note that for 16650, EFR-bit 4 must be selected as well. + * EFR[4]=1 MCR[6]=1, TI16C752 */ -#define UART_IERX_SLEEP 0x10 /* Enable sleep mode */ +#define UART_TI752_TCR 6 /* I/O: transmission control register */ +#define UART_TI752_TLR 7 /* I/O: trigger level register */ /* - * These are the definitions for the Modem Control Register + * LCR=0xBF, XR16C85x */ -#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C750) */ -#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ -#define UART_MCR_OUT2 0x08 /* Out2 complement */ -#define UART_MCR_OUT1 0x04 /* Out1 complement */ -#define UART_MCR_RTS 0x02 /* RTS complement */ -#define UART_MCR_DTR 0x01 /* DTR complement */ +#define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx + * In: Fifo count + * Out: Fifo custom trigger levels */ +/* + * These are the definitions for the Programmable Trigger Register + */ +#define UART_TRG_1 0x01 +#define UART_TRG_4 0x04 +#define UART_TRG_8 0x08 +#define UART_TRG_16 0x10 +#define UART_TRG_32 0x20 +#define UART_TRG_64 0x40 +#define UART_TRG_96 0x60 +#define UART_TRG_120 0x78 +#define UART_TRG_128 0x80 + +#define UART_FCTR 1 /* Feature Control Register */ +#define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */ +#define UART_FCTR_RTS_4DELAY 0x01 +#define UART_FCTR_RTS_6DELAY 0x02 +#define UART_FCTR_RTS_8DELAY 0x03 +#define UART_FCTR_IRDA 0x04 /* IrDa data encode select */ +#define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */ +#define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */ +#define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */ +#define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */ +#define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */ +#define UART_FCTR_SCR_SWAP 0x40 /* Scratch pad register swap */ +#define UART_FCTR_RX 0x00 /* Programmable trigger mode select */ +#define UART_FCTR_TX 0x80 /* Programmable trigger mode select */ /* - * These are the definitions for the Modem Status Register + * LCR=0xBF, FCTR[6]=1 */ -#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ -#define UART_MSR_RI 0x40 /* Ring Indicator */ -#define UART_MSR_DSR 0x20 /* Data Set Ready */ -#define UART_MSR_CTS 0x10 /* Clear to Send */ -#define UART_MSR_DDCD 0x08 /* Delta DCD */ -#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ -#define UART_MSR_DDSR 0x02 /* Delta DSR */ -#define UART_MSR_DCTS 0x01 /* Delta CTS */ -#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ +#define UART_EMSR 7 /* Extended Mode Select Register */ +#define UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */ +#define UART_EMSR_ALT_COUNT 0x02 /* Alternating count select */ /* * The Intel XScale on-chip UARTs define these bits @@ -156,17 +218,8 @@ #define UART_FCR_PXAR16 0x80 /* receive FIFO treshold = 16 */ #define UART_FCR_PXAR32 0xc0 /* receive FIFO treshold = 32 */ -/* - * These are the definitions for the Extended Features Register - * (StarTech 16C660 only, when DLAB=1) - */ -#define UART_EFR_CTS 0x80 /* CTS flow control */ -#define UART_EFR_RTS 0x40 /* RTS flow control */ -#define UART_EFR_SCD 0x20 /* Special character detect */ -#define UART_EFR_ECB 0x10 /* Enhanced control bit */ -/* - * the low four bits control software flow control - */ + + /* * These register definitions are for the 16C950 @@ -203,47 +256,7 @@ #define UART_ACR_ICRRD 0x40 /* ICR Read enable */ #define UART_ACR_ASREN 0x80 /* Additional status enable */ -/* - * These are the definitions for the Feature Control Register - * (XR16C85x only, when LCR=bf; doubles with the Interrupt Enable - * Register, UART register #1) - */ -#define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */ -#define UART_FCTR_RTS_4DELAY 0x01 -#define UART_FCTR_RTS_6DELAY 0x02 -#define UART_FCTR_RTS_8DELAY 0x03 -#define UART_FCTR_IRDA 0x04 /* IrDa data encode select */ -#define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */ -#define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */ -#define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */ -#define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */ -#define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */ -#define UART_FCTR_SCR_SWAP 0x40 /* Scratch pad register swap */ -#define UART_FCTR_RX 0x00 /* Programmable trigger mode select */ -#define UART_FCTR_TX 0x80 /* Programmable trigger mode select */ - -/* - * These are the definitions for the Enhanced Mode Select Register - * (XR16C85x only, when LCR=bf and FCTR bit 6=1; doubles with the - * Scratch register, UART register #7) - */ -#define UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */ -#define UART_EMSR_ALT_COUNT 0x02 /* Alternating count select */ -/* - * These are the definitions for the Programmable Trigger - * Register (XR16C85x only, when LCR=bf; doubles with the UART RX/TX - * register, UART register #0) - */ -#define UART_TRG_1 0x01 -#define UART_TRG_4 0x04 -#define UART_TRG_8 0x08 -#define UART_TRG_16 0x10 -#define UART_TRG_32 0x20 -#define UART_TRG_64 0x40 -#define UART_TRG_96 0x60 -#define UART_TRG_120 0x78 -#define UART_TRG_128 0x80 /* * These definitions are for the RSA-DV II/S card, from diff --git a/include/linux/slab.h b/include/linux/slab.h index e51014cb24a0..7c81a7863b99 100644 --- a/include/linux/slab.h +++ b/include/linux/slab.h @@ -61,7 +61,14 @@ extern kmem_cache_t *kmem_cache_create(const char *, size_t, size_t, unsigned lo extern int kmem_cache_destroy(kmem_cache_t *); extern int kmem_cache_shrink(kmem_cache_t *); extern void *kmem_cache_alloc(kmem_cache_t *, int); +#ifdef CONFIG_NUMA extern void *kmem_cache_alloc_node(kmem_cache_t *, int); +#else +static inline void *kmem_cache_alloc_node(kmem_cache_t *cachep, int node) +{ + return kmem_cache_alloc(cachep, GFP_KERNEL); +} +#endif extern void kmem_cache_free(kmem_cache_t *, void *); extern unsigned int kmem_cache_size(kmem_cache_t *); diff --git a/include/linux/swap.h b/include/linux/swap.h index 371e8260c577..b0f07148e0eb 100644 --- a/include/linux/swap.h +++ b/include/linux/swap.h @@ -230,6 +230,7 @@ extern spinlock_t swaplock; /* linux/mm/thrash.c */ extern struct mm_struct * swap_token_mm; +extern unsigned long swap_token_default_timeout; extern void grab_swap_token(void); extern void __put_swap_token(struct mm_struct *); diff --git a/include/linux/swapops.h b/include/linux/swapops.h index 0cfc704d0565..d4c7db35e708 100644 --- a/include/linux/swapops.h +++ b/include/linux/swapops.h @@ -30,8 +30,7 @@ static inline swp_entry_t swp_entry(unsigned long type, pgoff_t offset) */ static inline unsigned swp_type(swp_entry_t entry) { - return (entry.val >> SWP_TYPE_SHIFT(entry)) & - ((1 << MAX_SWAPFILES_SHIFT) - 1); + return (entry.val >> SWP_TYPE_SHIFT(entry)); } /* diff --git a/include/linux/sysctl.h b/include/linux/sysctl.h index 8db31f8d17ff..129ff0ac8a15 100644 --- a/include/linux/sysctl.h +++ b/include/linux/sysctl.h @@ -167,6 +167,7 @@ enum VM_HUGETLB_GROUP=25, /* permitted hugetlb group */ VM_VFS_CACHE_PRESSURE=26, /* dcache/icache reclaim pressure */ VM_LEGACY_VA_LAYOUT=27, /* legacy/compatibility virtual address space layout */ + VM_SWAP_TOKEN_TIMEOUT=28, /* default time for token time out */ }; diff --git a/include/linux/tc_act/tc_mirred.h b/include/linux/tc_act/tc_mirred.h new file mode 100644 index 000000000000..71d63409d568 --- /dev/null +++ b/include/linux/tc_act/tc_mirred.h @@ -0,0 +1,28 @@ +#ifndef __LINUX_TC_MIR_H +#define __LINUX_TC_MIR_H + +#include <linux/pkt_cls.h> + +#define TCA_ACT_MIRRED 8 +#define TCA_EGRESS_REDIR 1 /* packet redirect to EGRESS*/ +#define TCA_EGRESS_MIRROR 2 /* mirror packet to EGRESS */ +#define TCA_INGRESS_REDIR 3 /* packet redirect to INGRESS*/ +#define TCA_INGRESS_MIRROR 4 /* mirror packet to INGRESS */ + +struct tc_mirred +{ + tc_gen; + int eaction; /* one of IN/EGRESS_MIRROR/REDIR */ + __u32 ifindex; /* ifindex of egress port */ +}; + +enum +{ + TCA_MIRRED_UNSPEC, + TCA_MIRRED_TM, + TCA_MIRRED_PARMS, + __TCA_MIRRED_MAX +}; +#define TCA_MIRRED_MAX (__TCA_MIRRED_MAX - 1) + +#endif diff --git a/include/linux/time.h b/include/linux/time.h index ae174b8ab036..0814ed4a4586 100644 --- a/include/linux/time.h +++ b/include/linux/time.h @@ -157,7 +157,13 @@ struct itimerval { #define CLOCK_REALTIME_HR 4 #define CLOCK_MONOTONIC_HR 5 -#define MAX_CLOCKS 6 +/* + * The IDs of various hardware clocks + */ + + +#define CLOCK_SGI_CYCLE 10 +#define MAX_CLOCKS 16 #define CLOCKS_MASK (CLOCK_REALTIME | CLOCK_MONOTONIC | \ CLOCK_REALTIME_HR | CLOCK_MONOTONIC_HR) #define CLOCKS_MONO (CLOCK_MONOTONIC & CLOCK_MONOTONIC_HR) diff --git a/include/linux/tty.h b/include/linux/tty.h index f9fd14991956..1b76106272d3 100644 --- a/include/linux/tty.h +++ b/include/linux/tty.h @@ -291,6 +291,8 @@ struct tty_struct { unsigned int canon_column; struct semaphore atomic_read; struct semaphore atomic_write; + unsigned char *write_buf; + int write_cnt; spinlock_t read_lock; /* If the tty has a pending do_SAK, queue it here - akpm */ struct work_struct SAK_work; diff --git a/include/linux/tty_driver.h b/include/linux/tty_driver.h index bbf6a3813fc8..b368b296d035 100644 --- a/include/linux/tty_driver.h +++ b/include/linux/tty_driver.h @@ -17,7 +17,7 @@ * * This routine is called when a particular tty device is closed. * - * int (*write)(struct tty_struct * tty, int from_user, + * int (*write)(struct tty_struct * tty, * const unsigned char *buf, int count); * * This routine is called by the kernel to write a series of @@ -124,7 +124,7 @@ struct tty_struct; struct tty_operations { int (*open)(struct tty_struct * tty, struct file * filp); void (*close)(struct tty_struct * tty, struct file * filp); - int (*write)(struct tty_struct * tty, int from_user, + int (*write)(struct tty_struct * tty, const unsigned char *buf, int count); void (*put_char)(struct tty_struct *tty, unsigned char ch); void (*flush_chars)(struct tty_struct *tty); @@ -186,7 +186,7 @@ struct tty_driver { */ int (*open)(struct tty_struct * tty, struct file * filp); void (*close)(struct tty_struct * tty, struct file * filp); - int (*write)(struct tty_struct * tty, int from_user, + int (*write)(struct tty_struct * tty, const unsigned char *buf, int count); void (*put_char)(struct tty_struct *tty, unsigned char ch); void (*flush_chars)(struct tty_struct *tty); diff --git a/include/linux/tty_ldisc.h b/include/linux/tty_ldisc.h index deacf01e50e8..6066afde5ce4 100644 --- a/include/linux/tty_ldisc.h +++ b/include/linux/tty_ldisc.h @@ -123,7 +123,7 @@ struct tty_ldisc { ssize_t (*read)(struct tty_struct * tty, struct file * file, unsigned char __user * buf, size_t nr); ssize_t (*write)(struct tty_struct * tty, struct file * file, - const unsigned char __user * buf, size_t nr); + const unsigned char * buf, size_t nr); int (*ioctl)(struct tty_struct * tty, struct file * file, unsigned int cmd, unsigned long arg); void (*set_termios)(struct tty_struct *tty, struct termios * old); diff --git a/include/media/saa7146.h b/include/media/saa7146.h index e62f03fb4c5d..5e9f64e67bc8 100644 --- a/include/media/saa7146.h +++ b/include/media/saa7146.h @@ -154,7 +154,7 @@ struct saa7146_dev }; /* from saa7146_i2c.c */ -int saa7146_i2c_adapter_prepare(struct saa7146_dev *dev, struct i2c_adapter *i2c_adapter, unsigned int class, u32 bitrate); +int saa7146_i2c_adapter_prepare(struct saa7146_dev *dev, struct i2c_adapter *i2c_adapter, u32 bitrate); int saa7146_i2c_transfer(struct saa7146_dev *saa, const struct i2c_msg msgs[], int num, int retries); /* from saa7146_core.c */ diff --git a/include/media/saa7146_vv.h b/include/media/saa7146_vv.h index de5672cdec02..61a509eb1bc6 100644 --- a/include/media/saa7146_vv.h +++ b/include/media/saa7146_vv.h @@ -35,6 +35,7 @@ struct saa7146_format { u32 trans; u8 depth; u8 flags; + u8 swap; }; struct saa7146_standard @@ -188,8 +189,8 @@ struct saa7146_use_ops { }; /* from saa7146_fops.c */ -int saa7146_register_device(struct video_device *vid, struct saa7146_dev* dev, char *name, int type); -int saa7146_unregister_device(struct video_device *vid, struct saa7146_dev* dev); +int saa7146_register_device(struct video_device **vid, struct saa7146_dev* dev, char *name, int type); +int saa7146_unregister_device(struct video_device **vid, struct saa7146_dev* dev); void saa7146_buffer_finish(struct saa7146_dev *dev, struct saa7146_dmaqueue *q, int state); void saa7146_buffer_next(struct saa7146_dev *dev, struct saa7146_dmaqueue *q,int vbi); int saa7146_buffer_queue(struct saa7146_dev *dev, struct saa7146_dmaqueue *q, struct saa7146_buf *buf); diff --git a/include/media/tuner.h b/include/media/tuner.h index 9597ffeb016c..229128120307 100644 --- a/include/media/tuner.h +++ b/include/media/tuner.h @@ -1,3 +1,4 @@ + /* tuner.h - definition for different tuners @@ -69,9 +70,12 @@ #define TUNER_PHILIPS_ATSC 42 #define TUNER_PHILIPS_FM1236_MK3 43 #define TUNER_PHILIPS_4IN1 44 /* ATI TV Wonder Pro - Conexant */ +/* Microtune mergeged with Temic 12/31/1999 partially financed by Alps - these may be similar to Temic */ #define TUNER_MICROTUNE_4049FM5 45 #define TUNER_LG_NTSC_TAPE 47 #define TUNER_TNF_8831BGFF 48 +#define TUNER_MICROTUNE_4042FI5 49 /* FusionHDTV 3 Gold - 4042 FI5 (3X 8147) */ +#define TUNER_TCL_2002N 50 #define NOTUNER 0 #define PAL 1 /* PAL_BG */ @@ -91,6 +95,7 @@ #define Microtune 8 #define HITACHI 9 #define Panasonic 10 +#define TCL 11 #define TUNER_SET_TYPE _IOW('t',1,int) /* set tuner type */ #define TUNER_SET_TVFREQ _IOW('t',2,int) /* set tv freq */ diff --git a/include/media/video-buf.h b/include/media/video-buf.h index 3c17bdf0b790..3fd4d7db18e3 100644 --- a/include/media/video-buf.h +++ b/include/media/video-buf.h @@ -1,4 +1,6 @@ /* + * $Id: video-buf.h,v 1.7 2004/10/11 14:53:13 kraxel Exp $ + * * generic helper functions for video4linux capture buffers, to handle * memory management and PCI DMA. Right now bttv + saa7134 use it. * @@ -165,12 +167,12 @@ struct videobuf_buffer { }; struct videobuf_queue_ops { - int (*buf_setup)(struct file *file, + int (*buf_setup)(void *priv, unsigned int *count, unsigned int *size); - int (*buf_prepare)(struct file *file,struct videobuf_buffer *vb, + int (*buf_prepare)(void *priv,struct videobuf_buffer *vb, enum v4l2_field field); - void (*buf_queue)(struct file *file,struct videobuf_buffer *vb); - void (*buf_release)(struct file *file,struct videobuf_buffer *vb); + void (*buf_queue)(void *priv,struct videobuf_buffer *vb); + void (*buf_release)(void *priv,struct videobuf_buffer *vb); }; struct videobuf_queue { @@ -208,36 +210,37 @@ void videobuf_queue_init(struct videobuf_queue *q, enum v4l2_field field, unsigned int msize); int videobuf_queue_is_busy(struct videobuf_queue *q); -void videobuf_queue_cancel(struct file *file, struct videobuf_queue *q); +void videobuf_queue_cancel(void *priv, struct videobuf_queue *q); enum v4l2_field videobuf_next_field(struct videobuf_queue *q); void videobuf_status(struct v4l2_buffer *b, struct videobuf_buffer *vb, enum v4l2_buf_type type); -int videobuf_reqbufs(struct file *file, struct videobuf_queue *q, +int videobuf_reqbufs(void *priv, struct videobuf_queue *q, struct v4l2_requestbuffers *req); int videobuf_querybuf(struct videobuf_queue *q, struct v4l2_buffer *b); -int videobuf_qbuf(struct file *file, struct videobuf_queue *q, +int videobuf_qbuf(void *priv, struct videobuf_queue *q, struct v4l2_buffer *b); -int videobuf_dqbuf(struct file *file, struct videobuf_queue *q, - struct v4l2_buffer *b); -int videobuf_streamon(struct file *file, struct videobuf_queue *q); -int videobuf_streamoff(struct file *file, struct videobuf_queue *q); - -int videobuf_read_start(struct file *file, struct videobuf_queue *q); -void videobuf_read_stop(struct file *file, struct videobuf_queue *q); -ssize_t videobuf_read_stream(struct file *file, struct videobuf_queue *q, +int videobuf_dqbuf(void *priv, struct videobuf_queue *q, + struct v4l2_buffer *b, int nonblocking); +int videobuf_streamon(void *priv, struct videobuf_queue *q); +int videobuf_streamoff(void *priv, struct videobuf_queue *q); + +int videobuf_read_start(void *priv, struct videobuf_queue *q); +void videobuf_read_stop(void *priv, struct videobuf_queue *q); +ssize_t videobuf_read_stream(void *priv, struct videobuf_queue *q, char __user *data, size_t count, loff_t *ppos, - int vbihack); -ssize_t videobuf_read_one(struct file *file, struct videobuf_queue *q, - char __user *data, size_t count, loff_t *ppos); -unsigned int videobuf_poll_stream(struct file *file, + int vbihack, int nonblocking); +ssize_t videobuf_read_one(void *priv, struct videobuf_queue *q, + char __user *data, size_t count, loff_t *ppos, + int nonblocking); +unsigned int videobuf_poll_stream(struct file *file, void *priv, struct videobuf_queue *q, poll_table *wait); -int videobuf_mmap_setup(struct file *file, struct videobuf_queue *q, +int videobuf_mmap_setup(void *priv, struct videobuf_queue *q, unsigned int bcount, unsigned int bsize, enum v4l2_memory memory); -int videobuf_mmap_free(struct file *file, struct videobuf_queue *q); +int videobuf_mmap_free(void *priv, struct videobuf_queue *q); int videobuf_mmap_mapper(struct vm_area_struct *vma, struct videobuf_queue *q); diff --git a/include/mtd/mtd-abi.h b/include/mtd/mtd-abi.h index e872ad77058b..db93b7b108bb 100644 --- a/include/mtd/mtd-abi.h +++ b/include/mtd/mtd-abi.h @@ -1,5 +1,5 @@ /* - * $Id: mtd-abi.h,v 1.5 2004/06/22 09:29:35 gleixner Exp $ + * $Id: mtd-abi.h,v 1.6 2004/08/09 13:38:30 dwmw2 Exp $ * * Portions of MTD ABI definition which are shared by kernel and user space */ @@ -7,6 +7,11 @@ #ifndef __MTD_ABI_H__ #define __MTD_ABI_H__ +#ifndef __KERNEL__ /* Urgh. The whole point of splitting this out into + separate files was to avoid #ifdef __KERNEL__ */ +#define __user +#endif + struct erase_info_user { uint32_t start; uint32_t length; diff --git a/include/net/bluetooth/bluetooth.h b/include/net/bluetooth/bluetooth.h index 9c5436227ac7..02bdef01cc36 100644 --- a/include/net/bluetooth/bluetooth.h +++ b/include/net/bluetooth/bluetooth.h @@ -133,6 +133,7 @@ uint bt_sock_poll(struct file * file, struct socket *sock, poll_table *wait); int bt_sock_wait_state(struct sock *sk, int state, unsigned long timeo); void bt_accept_enqueue(struct sock *parent, struct sock *sk); +void bt_accept_unlink(struct sock *sk); struct sock *bt_accept_dequeue(struct sock *parent, struct socket *newsock); /* Skb helpers */ diff --git a/include/net/bluetooth/hci.h b/include/net/bluetooth/hci.h index 06e19d370efd..f6d234a7a43e 100644 --- a/include/net/bluetooth/hci.h +++ b/include/net/bluetooth/hci.h @@ -68,7 +68,9 @@ enum { HCI_ENCRYPT, HCI_INQUIRY, - HCI_RAW + HCI_RAW, + + HCI_SECMGR }; /* HCI ioctl defines */ @@ -91,7 +93,8 @@ enum { #define HCISETLINKMODE _IOW('H', 226, int) #define HCISETACLMTU _IOW('H', 227, int) #define HCISETSCOMTU _IOW('H', 228, int) -#define HCISETRAWVND _IOW('H', 229, int) + +#define HCISETSECMGR _IOW('H', 230, int) #define HCIINQUIRY _IOR('H', 240, int) @@ -324,20 +327,28 @@ struct hci_cp_inquiry { #define OCF_INQUIRY_CANCEL 0x0002 #define OCF_LINK_KEY_REPLY 0x000B -#define OCF_LINK_KEY_NEG_REPLY 0x000C struct hci_cp_link_key_reply { bdaddr_t bdaddr; __u8 link_key[16]; } __attribute__ ((packed)); +#define OCF_LINK_KEY_NEG_REPLY 0x000C +struct hci_cp_link_key_neg_reply { + bdaddr_t bdaddr; +} __attribute__ ((packed)); + #define OCF_PIN_CODE_REPLY 0x000D -#define OCF_PIN_CODE_NEG_REPLY 0x000E struct hci_cp_pin_code_reply { bdaddr_t bdaddr; __u8 pin_len; __u8 pin_code[16]; } __attribute__ ((packed)); +#define OCF_PIN_CODE_NEG_REPLY 0x000E +struct hci_cp_pin_code_neg_reply { + bdaddr_t bdaddr; +} __attribute__ ((packed)); + #define OCF_CHANGE_CONN_PTYPE 0x000F struct hci_cp_change_conn_ptype { __u16 handle; diff --git a/include/net/bluetooth/hci_core.h b/include/net/bluetooth/hci_core.h index 63f73088b3ce..2c9995af03a8 100644 --- a/include/net/bluetooth/hci_core.h +++ b/include/net/bluetooth/hci_core.h @@ -53,7 +53,8 @@ struct inquiry_cache { struct hci_conn_hash { struct list_head list; spinlock_t lock; - unsigned int num; + unsigned int acl_num; + unsigned int sco_num; }; struct hci_dev { @@ -209,21 +210,28 @@ static inline void hci_conn_hash_init(struct hci_dev *hdev) struct hci_conn_hash *h = &hdev->conn_hash; INIT_LIST_HEAD(&h->list); spin_lock_init(&h->lock); - h->num = 0; + h->acl_num = 0; + h->sco_num = 0; } static inline void hci_conn_hash_add(struct hci_dev *hdev, struct hci_conn *c) { struct hci_conn_hash *h = &hdev->conn_hash; list_add(&c->list, &h->list); - h->num++; + if (c->type == ACL_LINK) + h->acl_num++; + else + h->sco_num++; } static inline void hci_conn_hash_del(struct hci_dev *hdev, struct hci_conn *c) { struct hci_conn_hash *h = &hdev->conn_hash; list_del(&c->list); - h->num--; + if (c->type == ACL_LINK) + h->acl_num++; + else + h->sco_num--; } static inline struct hci_conn *hci_conn_hash_lookup_handle(struct hci_dev *hdev, diff --git a/include/net/gen_stats.h b/include/net/gen_stats.h index e3ec2ebdd62e..9a9bea508d1b 100644 --- a/include/net/gen_stats.h +++ b/include/net/gen_stats.h @@ -41,5 +41,8 @@ extern int gen_new_estimator(struct gnet_stats_basic *bstats, spinlock_t *stats_lock, struct rtattr *opt); extern void gen_kill_estimator(struct gnet_stats_basic *bstats, struct gnet_stats_rate_est *rate_est); +extern int gen_replace_estimator(struct gnet_stats_basic *bstats, + struct gnet_stats_rate_est *rate_est, + spinlock_t *stats_lock, struct rtattr *opt); #endif diff --git a/include/net/pkt_act.h b/include/net/pkt_act.h index e7e7da355012..7c30074c4a6f 100644 --- a/include/net/pkt_act.h +++ b/include/net/pkt_act.h @@ -3,7 +3,7 @@ #include <asm/uaccess.h> #include <asm/system.h> -#include <asm/bitops.h> +#include <linux/bitops.h> #include <linux/config.h> #include <linux/types.h> #include <linux/kernel.h> diff --git a/include/net/pkt_sched.h b/include/net/pkt_sched.h index dab127cc2b1d..8391882cc787 100644 --- a/include/net/pkt_sched.h +++ b/include/net/pkt_sched.h @@ -9,6 +9,7 @@ #include <net/pkt_cls.h> #include <linux/module.h> #include <linux/rtnetlink.h> +#include <net/gen_stats.h> struct rtattr; struct Qdisc; @@ -86,7 +87,9 @@ struct Qdisc struct net_device *dev; struct list_head list; - struct tc_stats stats; + struct gnet_stats_basic bstats; + struct gnet_stats_queue qstats; + struct gnet_stats_rate_est rate_est; spinlock_t *stats_lock; struct rcu_head q_rcu; int (*reshape_fail)(struct sk_buff *skb, struct Qdisc *q); diff --git a/include/net/sock.h b/include/net/sock.h index 0666e2edd3c7..563096ab673a 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -1336,6 +1336,13 @@ static inline void sock_valbool_flag(struct sock *sk, int bit, int valbool) extern __u32 sysctl_wmem_max; extern __u32 sysctl_rmem_max; +#ifdef CONFIG_NET int siocdevprivate_ioctl(unsigned int fd, unsigned int cmd, unsigned long arg); +#else +static inline int siocdevprivate_ioctl(unsigned int fd, unsigned int cmd, unsigned long arg) +{ + return -ENODEV; +} +#endif #endif /* _SOCK_H */ diff --git a/include/net/tc_act/tc_mirred.h b/include/net/tc_act/tc_mirred.h new file mode 100644 index 000000000000..f7f9b76c2511 --- /dev/null +++ b/include/net/tc_act/tc_mirred.h @@ -0,0 +1,15 @@ +#ifndef __NET_TC_MIR_H +#define __NET_TC_MIR_H + +#include <net/pkt_sched.h> + +struct tcf_mirred +{ + tca_gen(mirred); + int eaction; + int ifindex; + int ok_push; + struct net_device *dev; +}; + +#endif diff --git a/include/pcmcia/bulkmem.h b/include/pcmcia/bulkmem.h index c21d64d62b60..f6954220f419 100644 --- a/include/pcmcia/bulkmem.h +++ b/include/pcmcia/bulkmem.h @@ -53,155 +53,7 @@ typedef struct region_info_t { #define REGION_BAR_MASK 0xe000 #define REGION_BAR_SHIFT 13 -/* For OpenMemory */ -typedef struct open_mem_t { - u_int Attributes; - u_int Offset; -} open_mem_t; - -/* Attributes for OpenMemory */ -#define MEMORY_TYPE 0x0001 -#define MEMORY_TYPE_CM 0x0000 -#define MEMORY_TYPE_AM 0x0001 -#define MEMORY_EXCLUSIVE 0x0002 -#define MEMORY_PREFETCH 0x0008 -#define MEMORY_CACHEABLE 0x0010 -#define MEMORY_BAR_MASK 0xe000 -#define MEMORY_BAR_SHIFT 13 - -typedef struct eraseq_entry_t { - memory_handle_t Handle; - u_char State; - u_int Size; - u_int Offset; - void *Optional; -} eraseq_entry_t; - -typedef struct eraseq_hdr_t { - int QueueEntryCnt; - eraseq_entry_t *QueueEntryArray; -} eraseq_hdr_t; - -#define ERASE_QUEUED 0x00 -#define ERASE_IN_PROGRESS(n) (((n) > 0) && ((n) < 0x80)) -#define ERASE_IDLE 0xff -#define ERASE_PASSED 0xe0 -#define ERASE_FAILED 0xe1 - -#define ERASE_MISSING 0x80 -#define ERASE_MEDIA_WRPROT 0x84 -#define ERASE_NOT_ERASABLE 0x85 -#define ERASE_BAD_OFFSET 0xc1 -#define ERASE_BAD_TECH 0xc2 -#define ERASE_BAD_SOCKET 0xc3 -#define ERASE_BAD_VCC 0xc4 -#define ERASE_BAD_VPP 0xc5 -#define ERASE_BAD_SIZE 0xc6 - -/* For CopyMemory */ -typedef struct copy_op_t { - u_int Attributes; - u_int SourceOffset; - u_int DestOffset; - u_int Count; -} copy_op_t; - -/* For ReadMemory and WriteMemory */ -typedef struct mem_op_t { - u_int Attributes; - u_int Offset; - u_int Count; -} mem_op_t; - -#define MEM_OP_BUFFER 0x01 -#define MEM_OP_BUFFER_USER 0x00 -#define MEM_OP_BUFFER_KERNEL 0x01 -#define MEM_OP_DISABLE_ERASE 0x02 -#define MEM_OP_VERIFY 0x04 - -/* For RegisterMTD */ -typedef struct mtd_reg_t { - u_int Attributes; - u_int Offset; - u_long MediaID; -} mtd_reg_t; - -/* - * Definitions for MTD requests - */ - -typedef struct mtd_request_t { - u_int SrcCardOffset; - u_int DestCardOffset; - u_int TransferLength; - u_int Function; - u_long MediaID; - u_int Status; - u_int Timeout; -} mtd_request_t; - -/* Fields in MTD Function */ -#define MTD_REQ_ACTION 0x003 -#define MTD_REQ_ERASE 0x000 -#define MTD_REQ_READ 0x001 -#define MTD_REQ_WRITE 0x002 -#define MTD_REQ_COPY 0x003 -#define MTD_REQ_NOERASE 0x004 -#define MTD_REQ_VERIFY 0x008 -#define MTD_REQ_READY 0x010 -#define MTD_REQ_TIMEOUT 0x020 -#define MTD_REQ_LAST 0x040 -#define MTD_REQ_FIRST 0x080 -#define MTD_REQ_KERNEL 0x100 - -/* Status codes */ -#define MTD_WAITREQ 0x00 -#define MTD_WAITTIMER 0x01 -#define MTD_WAITRDY 0x02 -#define MTD_WAITPOWER 0x03 - -/* - * Definitions for MTD helper functions - */ - -/* For MTDModifyWindow */ -typedef struct mtd_mod_win_t { - u_int Attributes; - u_int AccessSpeed; - u_int CardOffset; -} mtd_mod_win_t; - -/* For MTDSetVpp */ -typedef struct mtd_vpp_req_t { - u_char Vpp1, Vpp2; -} mtd_vpp_req_t; - -/* For MTDRDYMask */ -typedef struct mtd_rdy_req_t { - u_int Mask; -} mtd_rdy_req_t; - -enum mtd_helper { - MTDRequestWindow, MTDModifyWindow, MTDReleaseWindow, - MTDSetVpp, MTDRDYMask -}; - -#ifdef IN_CARD_SERVICES -extern int MTDHelperEntry(int func, void *a1, void *a2); -#else -extern int MTDHelperEntry(int func, ...); -#endif - int pcmcia_get_first_region(client_handle_t handle, region_info_t *rgn); int pcmcia_get_next_region(client_handle_t handle, region_info_t *rgn); -int pcmcia_register_mtd(client_handle_t handle, mtd_reg_t *reg); -int pcmcia_register_erase_queue(client_handle_t *handle, eraseq_hdr_t *header, eraseq_handle_t *e); -int pcmcia_deregister_erase_queue(eraseq_handle_t eraseq); -int pcmcia_check_erase_queue(eraseq_handle_t eraseq); -int pcmcia_open_memory(client_handle_t *handle, open_mem_t *open, memory_handle_t *m); -int pcmcia_close_memory(memory_handle_t handle); -int pcmcia_read_memory(memory_handle_t handle, mem_op_t *req, caddr_t buf); -int pcmcia_write_memory(memory_handle_t handle, mem_op_t *req, caddr_t buf); -int pcmcia_copy_memory(memory_handle_t handle, copy_op_t *req); #endif /* _LINUX_BULKMEM_H */ diff --git a/include/pcmcia/cistpl.h b/include/pcmcia/cistpl.h index a14f0b91335d..499f748c0028 100644 --- a/include/pcmcia/cistpl.h +++ b/include/pcmcia/cistpl.h @@ -607,6 +607,14 @@ int pcmcia_get_tuple_data(client_handle_t handle, tuple_t *tuple); int pcmcia_parse_tuple(client_handle_t handle, tuple_t *tuple, cisparse_t *parse); int pcmcia_validate_cis(client_handle_t handle, cisinfo_t *info); -int pcmcia_replace_cis(client_handle_t handle, cisdump_t *cis); +int pcmcia_replace_cis(struct pcmcia_socket *s, cisdump_t *cis); + +/* don't use outside of PCMCIA core yet */ +int pccard_get_next_tuple(struct pcmcia_socket *s, unsigned int func, tuple_t *tuple); +int pccard_get_first_tuple(struct pcmcia_socket *s, unsigned int function, tuple_t *tuple); +int pccard_get_tuple_data(struct pcmcia_socket *s, tuple_t *tuple); +int pccard_parse_tuple(tuple_t *tuple, cisparse_t *parse); + +int pccard_validate_cis(struct pcmcia_socket *s, unsigned int function, cisinfo_t *info); #endif /* LINUX_CISTPL_H */ diff --git a/include/pcmcia/cs.h b/include/pcmcia/cs.h index 871d8f1d9ac8..48eddee1e554 100644 --- a/include/pcmcia/cs.h +++ b/include/pcmcia/cs.h @@ -348,7 +348,6 @@ typedef struct mtd_bind_t { #define CS_EVENT_RESET_PHYSICAL 0x000200 #define CS_EVENT_CARD_RESET 0x000400 #define CS_EVENT_REGISTRATION_COMPLETE 0x000800 -#define CS_EVENT_RESET_COMPLETE 0x001000 #define CS_EVENT_PM_SUSPEND 0x002000 #define CS_EVENT_PM_RESUME 0x004000 #define CS_EVENT_INSERTION_REQUEST 0x008000 @@ -425,16 +424,12 @@ int pcmcia_access_configuration_register(client_handle_t handle, conf_reg_t *reg int pcmcia_deregister_client(client_handle_t handle); int pcmcia_get_configuration_info(client_handle_t handle, config_info_t *config); int pcmcia_get_card_services_info(servinfo_t *info); -int pcmcia_get_first_client(client_handle_t *handle, client_req_t *req); -int pcmcia_get_next_client(client_handle_t *handle, client_req_t *req); -int pcmcia_get_window(window_handle_t *handle, int idx, win_req_t *req); int pcmcia_get_first_window(window_handle_t *win, win_req_t *req); int pcmcia_get_next_window(window_handle_t *win, win_req_t *req); int pcmcia_get_status(client_handle_t handle, cs_status_t *status); int pcmcia_get_mem_page(window_handle_t win, memreq_t *req); int pcmcia_map_mem_page(window_handle_t win, memreq_t *req); int pcmcia_modify_configuration(client_handle_t handle, modconf_t *mod); -int pcmcia_modify_window(window_handle_t win, modwin_t *req); int pcmcia_register_client(client_handle_t *handle, client_reg_t *req); int pcmcia_release_configuration(client_handle_t handle); int pcmcia_release_io(client_handle_t handle, io_req_t *req); @@ -449,12 +444,14 @@ int pcmcia_suspend_card(struct pcmcia_socket *skt); int pcmcia_resume_card(struct pcmcia_socket *skt); int pcmcia_eject_card(struct pcmcia_socket *skt); int pcmcia_insert_card(struct pcmcia_socket *skt); -int pcmcia_set_event_mask(client_handle_t handle, eventmask_t *mask); int pcmcia_report_error(client_handle_t handle, error_info_t *err); -struct pci_bus *pcmcia_lookup_bus(client_handle_t handle); -/* rsrc_mgr.c */ -int pcmcia_adjust_resource_info(client_handle_t handle, adjust_t *adj); +#ifdef CONFIG_PCMCIA_OBSOLETE +int pcmcia_get_first_client(client_handle_t *handle, client_req_t *req); +int pcmcia_get_next_client(client_handle_t *handle, client_req_t *req); +int pcmcia_modify_window(window_handle_t win, modwin_t *req); +int pcmcia_set_event_mask(client_handle_t handle, eventmask_t *mask); +#endif #endif /* __KERNEL__ */ diff --git a/include/pcmcia/cs_types.h b/include/pcmcia/cs_types.h index abc32897e390..3a4aec08549e 100644 --- a/include/pcmcia/cs_types.h +++ b/include/pcmcia/cs_types.h @@ -56,9 +56,6 @@ typedef struct window_t *window_handle_t; struct region_t; typedef struct region_t *memory_handle_t; -struct eraseq_t; -typedef struct eraseq_t *eraseq_handle_t; - #ifndef DEV_NAME_LEN #define DEV_NAME_LEN 32 #endif diff --git a/include/pcmcia/ftl.h b/include/pcmcia/ftl.h deleted file mode 100644 index 62a8071f2f7f..000000000000 --- a/include/pcmcia/ftl.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * ftl.h 1.8 2000/06/12 21:55:40 - * - * The contents of this file are subject to the Mozilla Public License - * Version 1.1 (the "License"); you may not use this file except in - * compliance with the License. You may obtain a copy of the License - * at http://www.mozilla.org/MPL/ - * - * Software distributed under the License is distributed on an "AS IS" - * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See - * the License for the specific language governing rights and - * limitations under the License. - * - * The initial developer of the original code is David A. Hinds - * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds - * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. - * - * Alternatively, the contents of this file may be used under the - * terms of the GNU General Public License version 2 (the "GPL"), in which - * case the provisions of the GPL are applicable instead of the - * above. If you wish to allow the use of your version of this file - * only under the terms of the GPL and not to allow others to use - * your version of this file under the MPL, indicate your decision by - * deleting the provisions above and replace them with the notice and - * other provisions required by the GPL. If you do not delete the - * provisions above, a recipient may use your version of this file - * under either the MPL or the GPL. - */ - -#ifndef _LINUX_FTL_H -#define _LINUX_FTL_H - -typedef struct erase_unit_header_t { - u_char LinkTargetTuple[5]; - u_char DataOrgTuple[10]; - u_char NumTransferUnits; - u_int EraseCount; - u_short LogicalEUN; - u_char BlockSize; - u_char EraseUnitSize; - u_short FirstPhysicalEUN; - u_short NumEraseUnits; - u_int FormattedSize; - u_int FirstVMAddress; - u_short NumVMPages; - u_char Flags; - u_char Code; - u_int SerialNumber; - u_int AltEUHOffset; - u_int BAMOffset; - u_char Reserved[12]; - u_char EndTuple[2]; -} erase_unit_header_t; - -/* Flags in erase_unit_header_t */ -#define HIDDEN_AREA 0x01 -#define REVERSE_POLARITY 0x02 -#define DOUBLE_BAI 0x04 - -/* Definitions for block allocation information */ - -#define BLOCK_FREE(b) ((b) == 0xffffffff) -#define BLOCK_DELETED(b) (((b) == 0) || ((b) == 0xfffffffe)) - -#define BLOCK_TYPE(b) ((b) & 0x7f) -#define BLOCK_ADDRESS(b) ((b) & ~0x7f) -#define BLOCK_NUMBER(b) ((b) >> 9) -#define BLOCK_CONTROL 0x30 -#define BLOCK_DATA 0x40 -#define BLOCK_REPLACEMENT 0x60 -#define BLOCK_BAD 0x70 - -#endif /* _LINUX_FTL_H */ diff --git a/include/pcmcia/memory.h b/include/pcmcia/memory.h deleted file mode 100644 index ef87944dd4b3..000000000000 --- a/include/pcmcia/memory.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * memory.h 1.7 2000/06/12 21:55:40 - * - * The contents of this file are subject to the Mozilla Public License - * Version 1.1 (the "License"); you may not use this file except in - * compliance with the License. You may obtain a copy of the License - * at http://www.mozilla.org/MPL/ - * - * Software distributed under the License is distributed on an "AS IS" - * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See - * the License for the specific language governing rights and - * limitations under the License. - * - * The initial developer of the original code is David A. Hinds - * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds - * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. - * - * Alternatively, the contents of this file may be used under the - * terms of the GNU General Public License version 2 (the "GPL"), in which - * case the provisions of the GPL are applicable instead of the - * above. If you wish to allow the use of your version of this file - * only under the terms of the GPL and not to allow others to use - * your version of this file under the MPL, indicate your decision by - * deleting the provisions above and replace them with the notice and - * other provisions required by the GPL. If you do not delete the - * provisions above, a recipient may use your version of this file - * under either the MPL or the GPL. - */ - -#ifndef _LINUX_MEMORY_H -#define _LINUX_MEMORY_H - -typedef struct erase_info_t { - u_long Offset; - u_long Size; -} erase_info_t; - -#define MEMGETINFO _IOR('M', 1, region_info_t) -#define MEMERASE _IOW('M', 2, erase_info_t) - -#endif /* _LINUX_MEMORY_H */ diff --git a/include/pcmcia/ss.h b/include/pcmcia/ss.h index 7883d79b9055..1958cda29889 100644 --- a/include/pcmcia/ss.h +++ b/include/pcmcia/ss.h @@ -135,13 +135,6 @@ struct pccard_operations { */ struct pcmcia_socket; -typedef struct erase_busy_t { - eraseq_entry_t *erase; - client_handle_t client; - struct timer_list timeout; - struct erase_busy_t *prev, *next; -} erase_busy_t; - typedef struct io_window_t { u_int Attributes; ioaddr_t BasePort, NumPorts; @@ -185,7 +178,6 @@ struct pcmcia_socket { io_window_t io[MAX_IO_WIN]; window_t win[MAX_WIN]; struct region_t *c_region, *a_region; - erase_busy_t erase_busy; struct list_head cis_cache; u_int fake_cis_len; char *fake_cis; diff --git a/include/video/kyro.h b/include/video/kyro.h index c5f9b0f001e7..6996149f3b41 100644 --- a/include/video/kyro.h +++ b/include/video/kyro.h @@ -13,7 +13,7 @@ #define _KYRO_H struct kyrofb_info { - void *regbase; + void __iomem *regbase; u32 HTot; /* Hor Total Time */ u32 HFP; /* Hor Front Porch */ |