diff options
| author | Tony Luck <tony.luck@intel.com> | 2004-10-20 22:58:50 +0000 |
|---|---|---|
| committer | Tony Luck <tony.luck@intel.com> | 2004-10-20 22:58:50 +0000 |
| commit | fbeac694cf859cc273f436eb037fb7a4437a573c (patch) | |
| tree | 1bc10dfb66802eaf95f1335092453a4a99937d5c /include | |
| parent | a8ff88031f2af02480cff92ed41e18a2d51b11b3 (diff) | |
| parent | 2e02e15b2fc00451e8298f789b24e22bb30b77f3 (diff) | |
Merge
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-ia64/machvec.h | 16 | ||||
| -rw-r--r-- | include/asm-ia64/sn/addrs.h | 34 | ||||
| -rw-r--r-- | include/asm-ia64/sn/io.h | 32 | ||||
| -rw-r--r-- | include/asm-ia64/sn/shub_mmr.h | 31523 | ||||
| -rw-r--r-- | include/asm-ia64/topology.h | 21 |
5 files changed, 124 insertions, 31502 deletions
diff --git a/include/asm-ia64/machvec.h b/include/asm-ia64/machvec.h index ff881e2bf9fe..c86afb81cd02 100644 --- a/include/asm-ia64/machvec.h +++ b/include/asm-ia64/machvec.h @@ -62,14 +62,14 @@ typedef unsigned int ia64_mv_inl_t (unsigned long); typedef void ia64_mv_outb_t (unsigned char, unsigned long); typedef void ia64_mv_outw_t (unsigned short, unsigned long); typedef void ia64_mv_outl_t (unsigned int, unsigned long); -typedef unsigned char ia64_mv_readb_t (void *); -typedef unsigned short ia64_mv_readw_t (void *); -typedef unsigned int ia64_mv_readl_t (void *); -typedef unsigned long ia64_mv_readq_t (void *); -typedef unsigned char ia64_mv_readb_relaxed_t (void *); -typedef unsigned short ia64_mv_readw_relaxed_t (void *); -typedef unsigned int ia64_mv_readl_relaxed_t (void *); -typedef unsigned long ia64_mv_readq_relaxed_t (void *); +typedef unsigned char ia64_mv_readb_t (const volatile void __iomem *); +typedef unsigned short ia64_mv_readw_t (const volatile void __iomem *); +typedef unsigned int ia64_mv_readl_t (const volatile void __iomem *); +typedef unsigned long ia64_mv_readq_t (const volatile void __iomem *); +typedef unsigned char ia64_mv_readb_relaxed_t (const volatile void __iomem *); +typedef unsigned short ia64_mv_readw_relaxed_t (const volatile void __iomem *); +typedef unsigned int ia64_mv_readl_relaxed_t (const volatile void __iomem *); +typedef unsigned long ia64_mv_readq_relaxed_t (const volatile void __iomem *); static inline void machvec_noop (void) diff --git a/include/asm-ia64/sn/addrs.h b/include/asm-ia64/sn/addrs.h index 3ad100b8d873..1220d1f122d1 100644 --- a/include/asm-ia64/sn/addrs.h +++ b/include/asm-ia64/sn/addrs.h @@ -69,27 +69,27 @@ typedef union ia64_sn2_pa { } ia64_sn2_pa_t; #endif -#define TO_PHYS_MASK 0x0001ffcfffffffff /* Note - clear AS bits */ +#define TO_PHYS_MASK 0x0001ffcfffffffffUL /* Note - clear AS bits */ /* Regions determined by AS */ -#define LOCAL_MMR_SPACE 0xc000008000000000 /* Local MMR space */ -#define LOCAL_PHYS_MMR_SPACE 0x8000008000000000 /* Local PhysicalMMR space */ -#define LOCAL_MEM_SPACE 0xc000010000000000 /* Local Memory space */ +#define LOCAL_MMR_SPACE 0xc000008000000000UL /* Local MMR space */ +#define LOCAL_PHYS_MMR_SPACE 0x8000008000000000UL /* Local PhysicalMMR space */ +#define LOCAL_MEM_SPACE 0xc000010000000000UL /* Local Memory space */ /* It so happens that setting bit 35 indicates a reference to the SHUB or TIO * MMR space. */ -#define GLOBAL_MMR_SPACE 0xc000000800000000 /* Global MMR space */ -#define TIO_MMR_SPACE 0xc000000800000000 /* TIO MMR space */ -#define ICE_MMR_SPACE 0xc000000000000000 /* ICE MMR space */ -#define GLOBAL_PHYS_MMR_SPACE 0x0000000800000000 /* Global Physical MMR space */ -#define GET_SPACE 0xe000001000000000 /* GET space */ -#define AMO_SPACE 0xc000002000000000 /* AMO space */ -#define CACHEABLE_MEM_SPACE 0xe000003000000000 /* Cacheable memory space */ -#define UNCACHED 0xc000000000000000 /* UnCacheable memory space */ -#define UNCACHED_PHYS 0x8000000000000000 /* UnCacheable physical memory space */ - -#define PHYS_MEM_SPACE 0x0000003000000000 /* physical memory space */ +#define GLOBAL_MMR_SPACE 0xc000000800000000UL /* Global MMR space */ +#define TIO_MMR_SPACE 0xc000000800000000UL /* TIO MMR space */ +#define ICE_MMR_SPACE 0xc000000000000000UL /* ICE MMR space */ +#define GLOBAL_PHYS_MMR_SPACE 0x0000000800000000UL /* Global Physical MMR space */ +#define GET_SPACE 0xe000001000000000UL /* GET space */ +#define AMO_SPACE 0xc000002000000000UL /* AMO space */ +#define CACHEABLE_MEM_SPACE 0xe000003000000000UL /* Cacheable memory space */ +#define UNCACHED 0xc000000000000000UL /* UnCacheable memory space */ +#define UNCACHED_PHYS 0x8000000000000000UL /* UnCacheable physical memory space */ + +#define PHYS_MEM_SPACE 0x0000003000000000UL /* physical memory space */ /* SN2 address macros */ /* NID_SHFT has the right value for both SHUB and TIO addresses.*/ @@ -105,7 +105,7 @@ typedef union ia64_sn2_pa { #define GLOBAL_MEM_ADDR(n,a) (CACHEABLE_MEM_SPACE | REMOTE_ADDR(n,a)) /* non-II mmr's start at top of big window space (4G) */ -#define BWIN_TOP 0x0000000100000000 +#define BWIN_TOP 0x0000000100000000UL /* * general address defines - for code common to SN0/SN1/SN2 @@ -256,7 +256,7 @@ typedef union ia64_sn2_pa { (((~(_x)) & BWIN_TOP)>>9) | (_x)) #define REMOTE_HUB(_n, _x) \ - ((volatile uint64_t *)(REMOTE_HUB_BASE(_x) | ((((long)(_n))<<NASID_SHFT)))) + ((uint64_t *)(REMOTE_HUB_BASE(_x) | ((((long)(_n))<<NASID_SHFT)))) /* diff --git a/include/asm-ia64/sn/io.h b/include/asm-ia64/sn/io.h index 5e21dd47b2da..46d46842e3f0 100644 --- a/include/asm-ia64/sn/io.h +++ b/include/asm-ia64/sn/io.h @@ -129,44 +129,44 @@ ___sn_outl (unsigned int val, unsigned long port) */ static inline unsigned char -___sn_readb (void *addr) +___sn_readb (const volatile void __iomem *addr) { unsigned char val; - val = *(volatile unsigned char *)addr; + val = *(volatile unsigned char __force *)addr; __sn_mf_a(); sn_dma_flush((unsigned long)addr); return val; } static inline unsigned short -___sn_readw (void *addr) +___sn_readw (const volatile void __iomem *addr) { unsigned short val; - val = *(volatile unsigned short *)addr; + val = *(volatile unsigned short __force *)addr; __sn_mf_a(); sn_dma_flush((unsigned long)addr); return val; } static inline unsigned int -___sn_readl (void *addr) +___sn_readl (const volatile void __iomem *addr) { unsigned int val; - val = *(volatile unsigned int *) addr; + val = *(volatile unsigned int __force *)addr; __sn_mf_a(); sn_dma_flush((unsigned long)addr); return val; } static inline unsigned long -___sn_readq (void *addr) +___sn_readq (const volatile void __iomem *addr) { unsigned long val; - val = *(volatile unsigned long *) addr; + val = *(volatile unsigned long __force *)addr; __sn_mf_a(); sn_dma_flush((unsigned long)addr); return val; @@ -215,27 +215,27 @@ sn_inl_fast (unsigned long port) } static inline unsigned char -___sn_readb_relaxed (void *addr) +___sn_readb_relaxed (const volatile void __iomem *addr) { - return *(volatile unsigned char *)addr; + return *(volatile unsigned char __force *)addr; } static inline unsigned short -___sn_readw_relaxed (void *addr) +___sn_readw_relaxed (const volatile void __iomem *addr) { - return *(volatile unsigned short *)addr; + return *(volatile unsigned short __force *)addr; } static inline unsigned int -___sn_readl_relaxed (void *addr) +___sn_readl_relaxed (const volatile void __iomem *addr) { - return *(volatile unsigned int *) addr; + return *(volatile unsigned int __force *) addr; } static inline unsigned long -___sn_readq_relaxed (void *addr) +___sn_readq_relaxed (const volatile void __iomem *addr) { - return *(volatile unsigned long *) addr; + return *(volatile unsigned long __force *) addr; } struct pci_dev; diff --git a/include/asm-ia64/sn/shub_mmr.h b/include/asm-ia64/sn/shub_mmr.h index a0f364a1569c..430c50fd1485 100644 --- a/include/asm-ia64/sn/shub_mmr.h +++ b/include/asm-ia64/sn/shub_mmr.h @@ -11,2126 +11,130 @@ #define _ASM_IA64_SN_SHUB_MMR_H /* ==================================================================== */ -/* Register "SH_FSB_BINIT_CONTROL" */ -/* FSB BINIT# Control */ -/* ==================================================================== */ - -#define SH_FSB_BINIT_CONTROL 0x0000000120010000 -#define SH_FSB_BINIT_CONTROL_MASK 0x0000000000000001 -#define SH_FSB_BINIT_CONTROL_INIT 0x0000000000000000 - -/* SH_FSB_BINIT_CONTROL_BINIT */ -/* Description: Assert the FSB's BINIT# Signal */ -#define SH_FSB_BINIT_CONTROL_BINIT_SHFT 0 -#define SH_FSB_BINIT_CONTROL_BINIT_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_FSB_RESET_CONTROL" */ -/* FSB Reset Control */ -/* ==================================================================== */ - -#define SH_FSB_RESET_CONTROL 0x0000000120010080 -#define SH_FSB_RESET_CONTROL_MASK 0x0000000000000001 -#define SH_FSB_RESET_CONTROL_INIT 0x0000000000000000 - -/* SH_FSB_RESET_CONTROL_RESET */ -/* Description: Assert the FSB's RESET# Signal */ -#define SH_FSB_RESET_CONTROL_RESET_SHFT 0 -#define SH_FSB_RESET_CONTROL_RESET_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_FSB_SYSTEM_AGENT_CONFIG" */ -/* FSB System Agent Configuration */ -/* ==================================================================== */ - -#define SH_FSB_SYSTEM_AGENT_CONFIG 0x0000000120010100 -#define SH_FSB_SYSTEM_AGENT_CONFIG_MASK 0x00003fff0187fff9 -#define SH_FSB_SYSTEM_AGENT_CONFIG_INIT 0x0000000000000000 - -/* SH_FSB_SYSTEM_AGENT_CONFIG_RCNT_SCNT_EN */ -/* Description: RCNT/SCNT Assertion Enabled */ -#define SH_FSB_SYSTEM_AGENT_CONFIG_RCNT_SCNT_EN_SHFT 0 -#define SH_FSB_SYSTEM_AGENT_CONFIG_RCNT_SCNT_EN_MASK 0x0000000000000001 - -/* SH_FSB_SYSTEM_AGENT_CONFIG_BERR_ASSERT_EN */ -/* Description: BERR Assertion Enabled for Bus Errors */ -#define SH_FSB_SYSTEM_AGENT_CONFIG_BERR_ASSERT_EN_SHFT 3 -#define SH_FSB_SYSTEM_AGENT_CONFIG_BERR_ASSERT_EN_MASK 0x0000000000000008 - -/* SH_FSB_SYSTEM_AGENT_CONFIG_BERR_SAMPLING_EN */ -/* Description: BERR Sampling Enabled */ -#define SH_FSB_SYSTEM_AGENT_CONFIG_BERR_SAMPLING_EN_SHFT 4 -#define SH_FSB_SYSTEM_AGENT_CONFIG_BERR_SAMPLING_EN_MASK 0x0000000000000010 - -/* SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_ASSERT_EN */ -/* Description: BINIT Assertion Enabled */ -#define SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_ASSERT_EN_SHFT 5 -#define SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_ASSERT_EN_MASK 0x0000000000000020 - -/* SH_FSB_SYSTEM_AGENT_CONFIG_BNR_THROTTLING_EN */ -/* Description: stutter FSB request assertion */ -#define SH_FSB_SYSTEM_AGENT_CONFIG_BNR_THROTTLING_EN_SHFT 6 -#define SH_FSB_SYSTEM_AGENT_CONFIG_BNR_THROTTLING_EN_MASK 0x0000000000000040 - -/* SH_FSB_SYSTEM_AGENT_CONFIG_SHORT_HANG_EN */ -/* Description: use short duration hang timeout */ -#define SH_FSB_SYSTEM_AGENT_CONFIG_SHORT_HANG_EN_SHFT 7 -#define SH_FSB_SYSTEM_AGENT_CONFIG_SHORT_HANG_EN_MASK 0x0000000000000080 - -/* SH_FSB_SYSTEM_AGENT_CONFIG_INTA_RSP_DATA */ -/* Description: Interrupt Acknowledge Response Data */ -#define SH_FSB_SYSTEM_AGENT_CONFIG_INTA_RSP_DATA_SHFT 8 -#define SH_FSB_SYSTEM_AGENT_CONFIG_INTA_RSP_DATA_MASK 0x000000000000ff00 - -/* SH_FSB_SYSTEM_AGENT_CONFIG_IO_TRANS_RSP */ -/* Description: IO Transaction Response */ -#define SH_FSB_SYSTEM_AGENT_CONFIG_IO_TRANS_RSP_SHFT 16 -#define SH_FSB_SYSTEM_AGENT_CONFIG_IO_TRANS_RSP_MASK 0x0000000000010000 - -/* SH_FSB_SYSTEM_AGENT_CONFIG_XTPR_TRANS_RSP */ -/* Description: External Task Priority Register (xTPR) Transaction */ -/* Response */ -#define SH_FSB_SYSTEM_AGENT_CONFIG_XTPR_TRANS_RSP_SHFT 17 -#define SH_FSB_SYSTEM_AGENT_CONFIG_XTPR_TRANS_RSP_MASK 0x0000000000020000 - -/* SH_FSB_SYSTEM_AGENT_CONFIG_INTA_TRANS_RSP */ -/* Description: Interrupt Acknowledge Transaction Response */ -#define SH_FSB_SYSTEM_AGENT_CONFIG_INTA_TRANS_RSP_SHFT 18 -#define SH_FSB_SYSTEM_AGENT_CONFIG_INTA_TRANS_RSP_MASK 0x0000000000040000 - -/* SH_FSB_SYSTEM_AGENT_CONFIG_TDOT */ -/* Description: Throttle Data-bus Ownership Transitions */ -#define SH_FSB_SYSTEM_AGENT_CONFIG_TDOT_SHFT 23 -#define SH_FSB_SYSTEM_AGENT_CONFIG_TDOT_MASK 0x0000000000800000 - -/* SH_FSB_SYSTEM_AGENT_CONFIG_SERIALIZE_FSB_EN */ -/* Description: serialize processor transactions */ -#define SH_FSB_SYSTEM_AGENT_CONFIG_SERIALIZE_FSB_EN_SHFT 24 -#define SH_FSB_SYSTEM_AGENT_CONFIG_SERIALIZE_FSB_EN_MASK 0x0000000001000000 - -/* SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_EVENT_ENABLES */ -/* Description: FSB error binit enables */ -#define SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_EVENT_ENABLES_SHFT 32 -#define SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_EVENT_ENABLES_MASK 0x00003fff00000000 - -/* ==================================================================== */ -/* Register "SH_FSB_VGA_REMAP" */ -/* FSB VGA Address Space Remap */ -/* ==================================================================== */ - -#define SH_FSB_VGA_REMAP 0x0000000120010180 -#define SH_FSB_VGA_REMAP_MASK 0x4001fffffffe0000 -#define SH_FSB_VGA_REMAP_INIT 0x0000000000000000 - -/* SH_FSB_VGA_REMAP_OFFSET */ -/* Description: VGA Remap Node Offset */ -#define SH_FSB_VGA_REMAP_OFFSET_SHFT 17 -#define SH_FSB_VGA_REMAP_OFFSET_MASK 0x0000000ffffe0000 - -/* SH_FSB_VGA_REMAP_ASID */ -/* Description: VGA Remap Address Space ID */ -#define SH_FSB_VGA_REMAP_ASID_SHFT 36 -#define SH_FSB_VGA_REMAP_ASID_MASK 0x0000003000000000 - -/* SH_FSB_VGA_REMAP_NID */ -/* Description: VGA Remap Node ID */ -#define SH_FSB_VGA_REMAP_NID_SHFT 38 -#define SH_FSB_VGA_REMAP_NID_MASK 0x0001ffc000000000 - -/* SH_FSB_VGA_REMAP_VGA_REMAPPING_ENABLED */ -/* Description: VGA Remapping Enabled */ -#define SH_FSB_VGA_REMAP_VGA_REMAPPING_ENABLED_SHFT 62 -#define SH_FSB_VGA_REMAP_VGA_REMAPPING_ENABLED_MASK 0x4000000000000000 - -/* ==================================================================== */ -/* Register "SH_FSB_RESET_STATUS" */ -/* FSB Reset Status */ -/* ==================================================================== */ - -#define SH_FSB_RESET_STATUS 0x0000000120020000 -#define SH_FSB_RESET_STATUS_MASK 0x0000000000000001 -#define SH_FSB_RESET_STATUS_INIT 0x0000000000000000 - -/* SH_FSB_RESET_STATUS_RESET_IN_PROGRESS */ -/* Description: Reset in Progress */ -#define SH_FSB_RESET_STATUS_RESET_IN_PROGRESS_SHFT 0 -#define SH_FSB_RESET_STATUS_RESET_IN_PROGRESS_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_FSB_SYMMETRIC_AGENT_STATUS" */ -/* FSB Symmetric Agent Status */ -/* ==================================================================== */ - -#define SH_FSB_SYMMETRIC_AGENT_STATUS 0x0000000120020080 -#define SH_FSB_SYMMETRIC_AGENT_STATUS_MASK 0x0000000000000007 -#define SH_FSB_SYMMETRIC_AGENT_STATUS_INIT 0x0000000000000000 - -/* SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_0_ACTIVE */ -/* Description: CPU 0 Active. */ -#define SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_0_ACTIVE_SHFT 0 -#define SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_0_ACTIVE_MASK 0x0000000000000001 - -/* SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_1_ACTIVE */ -/* Description: CPU 1 Active. */ -#define SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_1_ACTIVE_SHFT 1 -#define SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_1_ACTIVE_MASK 0x0000000000000002 - -/* SH_FSB_SYMMETRIC_AGENT_STATUS_CPUS_READY */ -/* Description: The Processors are Ready */ -#define SH_FSB_SYMMETRIC_AGENT_STATUS_CPUS_READY_SHFT 2 -#define SH_FSB_SYMMETRIC_AGENT_STATUS_CPUS_READY_MASK 0x0000000000000004 - -/* ==================================================================== */ -/* Register "SH_GFX_CREDIT_COUNT_0" */ -/* Graphics-write Credit Count for CPU 0 */ -/* ==================================================================== */ - -#define SH_GFX_CREDIT_COUNT_0 0x0000000120030000 -#define SH_GFX_CREDIT_COUNT_0_MASK 0x80000000000fffff -#define SH_GFX_CREDIT_COUNT_0_INIT 0x000000000000003f - -/* SH_GFX_CREDIT_COUNT_0_COUNT */ -/* Description: Credit Count */ -#define SH_GFX_CREDIT_COUNT_0_COUNT_SHFT 0 -#define SH_GFX_CREDIT_COUNT_0_COUNT_MASK 0x00000000000fffff - -/* SH_GFX_CREDIT_COUNT_0_RESET_GFX_STATE */ -/* Description: Reset GFX state */ -#define SH_GFX_CREDIT_COUNT_0_RESET_GFX_STATE_SHFT 63 -#define SH_GFX_CREDIT_COUNT_0_RESET_GFX_STATE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_GFX_CREDIT_COUNT_1" */ -/* Graphics-write Credit Count for CPU 1 */ -/* ==================================================================== */ - -#define SH_GFX_CREDIT_COUNT_1 0x0000000120030080 -#define SH_GFX_CREDIT_COUNT_1_MASK 0x80000000000fffff -#define SH_GFX_CREDIT_COUNT_1_INIT 0x000000000000003f - -/* SH_GFX_CREDIT_COUNT_1_COUNT */ -/* Description: Credit Count */ -#define SH_GFX_CREDIT_COUNT_1_COUNT_SHFT 0 -#define SH_GFX_CREDIT_COUNT_1_COUNT_MASK 0x00000000000fffff - -/* SH_GFX_CREDIT_COUNT_1_RESET_GFX_STATE */ -/* Description: Reset GFX state */ -#define SH_GFX_CREDIT_COUNT_1_RESET_GFX_STATE_SHFT 63 -#define SH_GFX_CREDIT_COUNT_1_RESET_GFX_STATE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_GFX_MODE_CNTRL_0" */ -/* Graphics credit mode amd message ordering for CPU 0 */ -/* ==================================================================== */ - -#define SH_GFX_MODE_CNTRL_0 0x0000000120030100 -#define SH_GFX_MODE_CNTRL_0_MASK 0x0000000000000007 -#define SH_GFX_MODE_CNTRL_0_INIT 0x0000000000000003 - -/* SH_GFX_MODE_CNTRL_0_DWORD_CREDITS */ -/* Description: GFX credits are tracked by D-words */ -#define SH_GFX_MODE_CNTRL_0_DWORD_CREDITS_SHFT 0 -#define SH_GFX_MODE_CNTRL_0_DWORD_CREDITS_MASK 0x0000000000000001 - -/* SH_GFX_MODE_CNTRL_0_MIXED_MODE_CREDITS */ -/* Description: GFX credits are tracked by D-words and messages */ -#define SH_GFX_MODE_CNTRL_0_MIXED_MODE_CREDITS_SHFT 1 -#define SH_GFX_MODE_CNTRL_0_MIXED_MODE_CREDITS_MASK 0x0000000000000002 - -/* SH_GFX_MODE_CNTRL_0_RELAXED_ORDERING */ -/* Description: GFX message routing order */ -#define SH_GFX_MODE_CNTRL_0_RELAXED_ORDERING_SHFT 2 -#define SH_GFX_MODE_CNTRL_0_RELAXED_ORDERING_MASK 0x0000000000000004 - -/* ==================================================================== */ -/* Register "SH_GFX_MODE_CNTRL_1" */ -/* Graphics credit mode amd message ordering for CPU 1 */ -/* ==================================================================== */ - -#define SH_GFX_MODE_CNTRL_1 0x0000000120030180 -#define SH_GFX_MODE_CNTRL_1_MASK 0x0000000000000007 -#define SH_GFX_MODE_CNTRL_1_INIT 0x0000000000000003 - -/* SH_GFX_MODE_CNTRL_1_DWORD_CREDITS */ -/* Description: GFX credits are tracked by D-words */ -#define SH_GFX_MODE_CNTRL_1_DWORD_CREDITS_SHFT 0 -#define SH_GFX_MODE_CNTRL_1_DWORD_CREDITS_MASK 0x0000000000000001 - -/* SH_GFX_MODE_CNTRL_1_MIXED_MODE_CREDITS */ -/* Description: GFX credits are tracked by D-words and messages */ -#define SH_GFX_MODE_CNTRL_1_MIXED_MODE_CREDITS_SHFT 1 -#define SH_GFX_MODE_CNTRL_1_MIXED_MODE_CREDITS_MASK 0x0000000000000002 - -/* SH_GFX_MODE_CNTRL_1_RELAXED_ORDERING */ -/* Description: GFX message routing order */ -#define SH_GFX_MODE_CNTRL_1_RELAXED_ORDERING_SHFT 2 -#define SH_GFX_MODE_CNTRL_1_RELAXED_ORDERING_MASK 0x0000000000000004 - -/* ==================================================================== */ -/* Register "SH_GFX_SKID_CREDIT_COUNT_0" */ -/* Graphics-write Skid Credit Count for CPU 0 */ -/* ==================================================================== */ - -#define SH_GFX_SKID_CREDIT_COUNT_0 0x0000000120030200 -#define SH_GFX_SKID_CREDIT_COUNT_0_MASK 0x00000000000fffff -#define SH_GFX_SKID_CREDIT_COUNT_0_INIT 0x0000000000000030 - -/* SH_GFX_SKID_CREDIT_COUNT_0_SKID */ -/* Description: Skid Credit Count */ -#define SH_GFX_SKID_CREDIT_COUNT_0_SKID_SHFT 0 -#define SH_GFX_SKID_CREDIT_COUNT_0_SKID_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_GFX_SKID_CREDIT_COUNT_1" */ -/* Graphics-write Skid Credit Count for CPU 1 */ -/* ==================================================================== */ - -#define SH_GFX_SKID_CREDIT_COUNT_1 0x0000000120030280 -#define SH_GFX_SKID_CREDIT_COUNT_1_MASK 0x00000000000fffff -#define SH_GFX_SKID_CREDIT_COUNT_1_INIT 0x0000000000000030 - -/* SH_GFX_SKID_CREDIT_COUNT_1_SKID */ -/* Description: Skid Credit Count */ -#define SH_GFX_SKID_CREDIT_COUNT_1_SKID_SHFT 0 -#define SH_GFX_SKID_CREDIT_COUNT_1_SKID_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_GFX_STALL_LIMIT_0" */ -/* Graphics-write Stall Limit for CPU 0 */ -/* ==================================================================== */ - -#define SH_GFX_STALL_LIMIT_0 0x0000000120030300 -#define SH_GFX_STALL_LIMIT_0_MASK 0x0000000003ffffff -#define SH_GFX_STALL_LIMIT_0_INIT 0x0000000000010000 - -/* SH_GFX_STALL_LIMIT_0_LIMIT */ -/* Description: Graphics Stall Limit for CPU 0 */ -#define SH_GFX_STALL_LIMIT_0_LIMIT_SHFT 0 -#define SH_GFX_STALL_LIMIT_0_LIMIT_MASK 0x0000000003ffffff - -/* ==================================================================== */ -/* Register "SH_GFX_STALL_LIMIT_1" */ -/* Graphics-write Stall Limit for CPU 1 */ -/* ==================================================================== */ - -#define SH_GFX_STALL_LIMIT_1 0x0000000120030380 -#define SH_GFX_STALL_LIMIT_1_MASK 0x0000000003ffffff -#define SH_GFX_STALL_LIMIT_1_INIT 0x0000000000010000 - -/* SH_GFX_STALL_LIMIT_1_LIMIT */ -/* Description: Graphics Stall Limit for CPU 1 */ -#define SH_GFX_STALL_LIMIT_1_LIMIT_SHFT 0 -#define SH_GFX_STALL_LIMIT_1_LIMIT_MASK 0x0000000003ffffff - -/* ==================================================================== */ -/* Register "SH_GFX_STALL_TIMER_0" */ -/* Graphics-write Stall Timer for CPU 0 */ -/* ==================================================================== */ - -#define SH_GFX_STALL_TIMER_0 0x0000000120030400 -#define SH_GFX_STALL_TIMER_0_MASK 0x0000000003ffffff -#define SH_GFX_STALL_TIMER_0_INIT 0x0000000000000000 - -/* SH_GFX_STALL_TIMER_0_TIMER_VALUE */ -/* Description: Timer Value */ -#define SH_GFX_STALL_TIMER_0_TIMER_VALUE_SHFT 0 -#define SH_GFX_STALL_TIMER_0_TIMER_VALUE_MASK 0x0000000003ffffff - -/* ==================================================================== */ -/* Register "SH_GFX_STALL_TIMER_1" */ -/* Graphics-write Stall Timer for CPU 1 */ -/* ==================================================================== */ - -#define SH_GFX_STALL_TIMER_1 0x0000000120030480 -#define SH_GFX_STALL_TIMER_1_MASK 0x0000000003ffffff -#define SH_GFX_STALL_TIMER_1_INIT 0x0000000000000000 - -/* SH_GFX_STALL_TIMER_1_TIMER_VALUE */ -/* Description: Timer Value */ -#define SH_GFX_STALL_TIMER_1_TIMER_VALUE_SHFT 0 -#define SH_GFX_STALL_TIMER_1_TIMER_VALUE_MASK 0x0000000003ffffff - -/* ==================================================================== */ -/* Register "SH_GFX_WINDOW_0" */ -/* Graphics-write Window for CPU 0 */ -/* ==================================================================== */ - -#define SH_GFX_WINDOW_0 0x0000000120030500 -#define SH_GFX_WINDOW_0_MASK 0x8000000fff000000 -#define SH_GFX_WINDOW_0_INIT 0x0000000000000000 - -/* SH_GFX_WINDOW_0_BASE_ADDR */ -/* Description: Base Address for CPU 0's 16 MB Graphics Window */ -#define SH_GFX_WINDOW_0_BASE_ADDR_SHFT 24 -#define SH_GFX_WINDOW_0_BASE_ADDR_MASK 0x0000000fff000000 - -/* SH_GFX_WINDOW_0_GFX_WINDOW_EN */ -/* Description: Graphics Window Enabled */ -#define SH_GFX_WINDOW_0_GFX_WINDOW_EN_SHFT 63 -#define SH_GFX_WINDOW_0_GFX_WINDOW_EN_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_GFX_WINDOW_1" */ -/* Graphics-write Window for CPU 1 */ -/* ==================================================================== */ - -#define SH_GFX_WINDOW_1 0x0000000120030580 -#define SH_GFX_WINDOW_1_MASK 0x8000000fff000000 -#define SH_GFX_WINDOW_1_INIT 0x0000000000000000 - -/* SH_GFX_WINDOW_1_BASE_ADDR */ -/* Description: Base Address for CPU 1's 16 MB Graphics Window */ -#define SH_GFX_WINDOW_1_BASE_ADDR_SHFT 24 -#define SH_GFX_WINDOW_1_BASE_ADDR_MASK 0x0000000fff000000 - -/* SH_GFX_WINDOW_1_GFX_WINDOW_EN */ -/* Description: Graphics Window Enabled */ -#define SH_GFX_WINDOW_1_GFX_WINDOW_EN_SHFT 63 -#define SH_GFX_WINDOW_1_GFX_WINDOW_EN_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_GFX_INTERRUPT_TIMER_LIMIT_0" */ -/* Graphics-write Interrupt Limit for CPU 0 */ -/* ==================================================================== */ - -#define SH_GFX_INTERRUPT_TIMER_LIMIT_0 0x0000000120030600 -#define SH_GFX_INTERRUPT_TIMER_LIMIT_0_MASK 0x00000000000000ff -#define SH_GFX_INTERRUPT_TIMER_LIMIT_0_INIT 0x0000000000000040 - -/* SH_GFX_INTERRUPT_TIMER_LIMIT_0_INTERRUPT_TIMER_LIMIT */ -/* Description: GFX Interrupt Timer Limit */ -#define SH_GFX_INTERRUPT_TIMER_LIMIT_0_INTERRUPT_TIMER_LIMIT_SHFT 0 -#define SH_GFX_INTERRUPT_TIMER_LIMIT_0_INTERRUPT_TIMER_LIMIT_MASK 0x00000000000000ff - -/* ==================================================================== */ -/* Register "SH_GFX_INTERRUPT_TIMER_LIMIT_1" */ -/* Graphics-write Interrupt Limit for CPU 1 */ -/* ==================================================================== */ - -#define SH_GFX_INTERRUPT_TIMER_LIMIT_1 0x0000000120030680 -#define SH_GFX_INTERRUPT_TIMER_LIMIT_1_MASK 0x00000000000000ff -#define SH_GFX_INTERRUPT_TIMER_LIMIT_1_INIT 0x0000000000000040 - -/* SH_GFX_INTERRUPT_TIMER_LIMIT_1_INTERRUPT_TIMER_LIMIT */ -/* Description: GFX Interrupt Timer Limit */ -#define SH_GFX_INTERRUPT_TIMER_LIMIT_1_INTERRUPT_TIMER_LIMIT_SHFT 0 -#define SH_GFX_INTERRUPT_TIMER_LIMIT_1_INTERRUPT_TIMER_LIMIT_MASK 0x00000000000000ff - -/* ==================================================================== */ -/* Register "SH_GFX_WRITE_STATUS_0" */ -/* Graphics Write Status for CPU 0 */ -/* ==================================================================== */ - -#define SH_GFX_WRITE_STATUS_0 0x0000000120040000 -#define SH_GFX_WRITE_STATUS_0_MASK 0x8000000000000001 -#define SH_GFX_WRITE_STATUS_0_INIT 0x0000000000000000 - -/* SH_GFX_WRITE_STATUS_0_BUSY */ -/* Description: Busy */ -#define SH_GFX_WRITE_STATUS_0_BUSY_SHFT 0 -#define SH_GFX_WRITE_STATUS_0_BUSY_MASK 0x0000000000000001 - -/* SH_GFX_WRITE_STATUS_0_RE_ENABLE_GFX_STALL */ -/* Description: Re-enable GFX stall logic for this processor */ -#define SH_GFX_WRITE_STATUS_0_RE_ENABLE_GFX_STALL_SHFT 63 -#define SH_GFX_WRITE_STATUS_0_RE_ENABLE_GFX_STALL_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_GFX_WRITE_STATUS_1" */ -/* Graphics Write Status for CPU 1 */ -/* ==================================================================== */ - -#define SH_GFX_WRITE_STATUS_1 0x0000000120040080 -#define SH_GFX_WRITE_STATUS_1_MASK 0x8000000000000001 -#define SH_GFX_WRITE_STATUS_1_INIT 0x0000000000000000 - -/* SH_GFX_WRITE_STATUS_1_BUSY */ -/* Description: Busy */ -#define SH_GFX_WRITE_STATUS_1_BUSY_SHFT 0 -#define SH_GFX_WRITE_STATUS_1_BUSY_MASK 0x0000000000000001 - -/* SH_GFX_WRITE_STATUS_1_RE_ENABLE_GFX_STALL */ -/* Description: Re-enable GFX stall logic for this processor */ -#define SH_GFX_WRITE_STATUS_1_RE_ENABLE_GFX_STALL_SHFT 63 -#define SH_GFX_WRITE_STATUS_1_RE_ENABLE_GFX_STALL_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_II_INT0" */ -/* SHub II Interrupt 0 Registers */ -/* ==================================================================== */ - -#define SH_II_INT0 0x0000000110000000 -#define SH_II_INT0_MASK 0x00000000000001ff -#define SH_II_INT0_INIT 0x0000000000000000 - -/* SH_II_INT0_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_II_INT0_IDX_SHFT 0 -#define SH_II_INT0_IDX_MASK 0x00000000000000ff - -/* SH_II_INT0_SEND */ -/* Description: Send Interrupt Message to PI, This generates a puls */ -#define SH_II_INT0_SEND_SHFT 8 -#define SH_II_INT0_SEND_MASK 0x0000000000000100 - -/* ==================================================================== */ -/* Register "SH_II_INT0_CONFIG" */ -/* SHub II Interrupt 0 Config Registers */ -/* ==================================================================== */ - -#define SH_II_INT0_CONFIG 0x0000000110000080 -#define SH_II_INT0_CONFIG_MASK 0x0003ffffffefffff -#define SH_II_INT0_CONFIG_INIT 0x0000000000000000 - -/* SH_II_INT0_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_II_INT0_CONFIG_TYPE_SHFT 0 -#define SH_II_INT0_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_II_INT0_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_II_INT0_CONFIG_AGT_SHFT 3 -#define SH_II_INT0_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_II_INT0_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_II_INT0_CONFIG_PID_SHFT 4 -#define SH_II_INT0_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_II_INT0_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_II_INT0_CONFIG_BASE_SHFT 21 -#define SH_II_INT0_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* ==================================================================== */ -/* Register "SH_II_INT0_ENABLE" */ -/* SHub II Interrupt 0 Enable Registers */ -/* ==================================================================== */ - -#define SH_II_INT0_ENABLE 0x0000000110000200 -#define SH_II_INT0_ENABLE_MASK 0x0000000000000001 -#define SH_II_INT0_ENABLE_INIT 0x0000000000000000 - -/* SH_II_INT0_ENABLE_II_ENABLE */ -/* Description: Enable II Interrupt */ -#define SH_II_INT0_ENABLE_II_ENABLE_SHFT 0 -#define SH_II_INT0_ENABLE_II_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_II_INT1" */ -/* SHub II Interrupt 1 Registers */ -/* ==================================================================== */ - -#define SH_II_INT1 0x0000000110000100 -#define SH_II_INT1_MASK 0x00000000000001ff -#define SH_II_INT1_INIT 0x0000000000000000 - -/* SH_II_INT1_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_II_INT1_IDX_SHFT 0 -#define SH_II_INT1_IDX_MASK 0x00000000000000ff - -/* SH_II_INT1_SEND */ -/* Description: Send Interrupt Message to PI, This generates a puls */ -#define SH_II_INT1_SEND_SHFT 8 -#define SH_II_INT1_SEND_MASK 0x0000000000000100 - -/* ==================================================================== */ -/* Register "SH_II_INT1_CONFIG" */ -/* SHub II Interrupt 1 Config Registers */ -/* ==================================================================== */ - -#define SH_II_INT1_CONFIG 0x0000000110000180 -#define SH_II_INT1_CONFIG_MASK 0x0003ffffffefffff -#define SH_II_INT1_CONFIG_INIT 0x0000000000000000 - -/* SH_II_INT1_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_II_INT1_CONFIG_TYPE_SHFT 0 -#define SH_II_INT1_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_II_INT1_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_II_INT1_CONFIG_AGT_SHFT 3 -#define SH_II_INT1_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_II_INT1_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_II_INT1_CONFIG_PID_SHFT 4 -#define SH_II_INT1_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_II_INT1_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_II_INT1_CONFIG_BASE_SHFT 21 -#define SH_II_INT1_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* ==================================================================== */ -/* Register "SH_II_INT1_ENABLE" */ -/* SHub II Interrupt 1 Enable Registers */ -/* ==================================================================== */ - -#define SH_II_INT1_ENABLE 0x0000000110000280 -#define SH_II_INT1_ENABLE_MASK 0x0000000000000001 -#define SH_II_INT1_ENABLE_INIT 0x0000000000000000 - -/* SH_II_INT1_ENABLE_II_ENABLE */ -/* Description: Enable II 1 Interrupt */ -#define SH_II_INT1_ENABLE_II_ENABLE_SHFT 0 -#define SH_II_INT1_ENABLE_II_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_INT_NODE_ID_CONFIG" */ -/* SHub Interrupt Node ID Configuration */ -/* ==================================================================== */ - -#define SH_INT_NODE_ID_CONFIG 0x0000000110000300 -#define SH_INT_NODE_ID_CONFIG_MASK 0x0000000000000fff -#define SH_INT_NODE_ID_CONFIG_INIT 0x0000000000000000 - -/* SH_INT_NODE_ID_CONFIG_NODE_ID */ -/* Description: Node ID for interrupt messages */ -#define SH_INT_NODE_ID_CONFIG_NODE_ID_SHFT 0 -#define SH_INT_NODE_ID_CONFIG_NODE_ID_MASK 0x00000000000007ff - -/* SH_INT_NODE_ID_CONFIG_ID_SEL */ -/* Description: Select node id for interrupt messages */ -#define SH_INT_NODE_ID_CONFIG_ID_SEL_SHFT 11 -#define SH_INT_NODE_ID_CONFIG_ID_SEL_MASK 0x0000000000000800 - -/* ==================================================================== */ /* Register "SH_IPI_INT" */ /* SHub Inter-Processor Interrupt Registers */ /* ==================================================================== */ - -#define SH_IPI_INT 0x0000000110000380 -#define SH_IPI_INT_MASK 0x8ff3ffffffefffff -#define SH_IPI_INT_INIT 0x0000000000000000 +#define SH_IPI_INT 0x0000000110000380UL +#define SH_IPI_INT_MASK 0x8ff3ffffffefffffUL +#define SH_IPI_INT_INIT 0x0000000000000000UL /* SH_IPI_INT_TYPE */ /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ #define SH_IPI_INT_TYPE_SHFT 0 -#define SH_IPI_INT_TYPE_MASK 0x0000000000000007 +#define SH_IPI_INT_TYPE_MASK 0x0000000000000007UL /* SH_IPI_INT_AGT */ /* Description: Agent, must be 0 for SHub */ #define SH_IPI_INT_AGT_SHFT 3 -#define SH_IPI_INT_AGT_MASK 0x0000000000000008 +#define SH_IPI_INT_AGT_MASK 0x0000000000000008UL /* SH_IPI_INT_PID */ /* Description: Processor ID, same setting as on targeted McKinley */ #define SH_IPI_INT_PID_SHFT 4 -#define SH_IPI_INT_PID_MASK 0x00000000000ffff0 +#define SH_IPI_INT_PID_MASK 0x00000000000ffff0UL /* SH_IPI_INT_BASE */ /* Description: Optional interrupt vector area, 2MB aligned */ #define SH_IPI_INT_BASE_SHFT 21 -#define SH_IPI_INT_BASE_MASK 0x0003ffffffe00000 +#define SH_IPI_INT_BASE_MASK 0x0003ffffffe00000UL /* SH_IPI_INT_IDX */ /* Description: Targeted McKinley interrupt vector */ #define SH_IPI_INT_IDX_SHFT 52 -#define SH_IPI_INT_IDX_MASK 0x0ff0000000000000 +#define SH_IPI_INT_IDX_MASK 0x0ff0000000000000UL /* SH_IPI_INT_SEND */ /* Description: Send Interrupt Message to PI, This generates a puls */ #define SH_IPI_INT_SEND_SHFT 63 -#define SH_IPI_INT_SEND_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_IPI_INT_ENABLE" */ -/* SHub Inter-Processor Interrupt Enable Registers */ -/* ==================================================================== */ - -#define SH_IPI_INT_ENABLE 0x0000000110000400 -#define SH_IPI_INT_ENABLE_MASK 0x0000000000000001 -#define SH_IPI_INT_ENABLE_INIT 0x0000000000000000 - -/* SH_IPI_INT_ENABLE_PIO_ENABLE */ -/* Description: Enable PIO Interrupt */ -#define SH_IPI_INT_ENABLE_PIO_ENABLE_SHFT 0 -#define SH_IPI_INT_ENABLE_PIO_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT0_CONFIG" */ -/* SHub Local Interrupt 0 Registers */ -/* ==================================================================== */ - -#define SH_LOCAL_INT0_CONFIG 0x0000000110000480 -#define SH_LOCAL_INT0_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_LOCAL_INT0_CONFIG_INIT 0x0000000000000000 - -/* SH_LOCAL_INT0_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_LOCAL_INT0_CONFIG_TYPE_SHFT 0 -#define SH_LOCAL_INT0_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_LOCAL_INT0_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_LOCAL_INT0_CONFIG_AGT_SHFT 3 -#define SH_LOCAL_INT0_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_LOCAL_INT0_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_LOCAL_INT0_CONFIG_PID_SHFT 4 -#define SH_LOCAL_INT0_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_LOCAL_INT0_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_LOCAL_INT0_CONFIG_BASE_SHFT 21 -#define SH_LOCAL_INT0_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_LOCAL_INT0_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_LOCAL_INT0_CONFIG_IDX_SHFT 52 -#define SH_LOCAL_INT0_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT0_ENABLE" */ -/* SHub Local Interrupt 0 Enable */ -/* ==================================================================== */ - -#define SH_LOCAL_INT0_ENABLE 0x0000000110000500 -#define SH_LOCAL_INT0_ENABLE_MASK 0x000000000000f7ff -#define SH_LOCAL_INT0_ENABLE_INIT 0x0000000000000000 - -/* SH_LOCAL_INT0_ENABLE_PI_HW_INT */ -/* Description: Enable PI Hardware interrupt */ -#define SH_LOCAL_INT0_ENABLE_PI_HW_INT_SHFT 0 -#define SH_LOCAL_INT0_ENABLE_PI_HW_INT_MASK 0x0000000000000001 - -/* SH_LOCAL_INT0_ENABLE_MD_HW_INT */ -/* Description: Enable MD Hardware interrupt */ -#define SH_LOCAL_INT0_ENABLE_MD_HW_INT_SHFT 1 -#define SH_LOCAL_INT0_ENABLE_MD_HW_INT_MASK 0x0000000000000002 - -/* SH_LOCAL_INT0_ENABLE_XN_HW_INT */ -/* Description: Enable XN Hardware interrupt */ -#define SH_LOCAL_INT0_ENABLE_XN_HW_INT_SHFT 2 -#define SH_LOCAL_INT0_ENABLE_XN_HW_INT_MASK 0x0000000000000004 - -/* SH_LOCAL_INT0_ENABLE_LB_HW_INT */ -/* Description: Enable LB Hardware interrupt */ -#define SH_LOCAL_INT0_ENABLE_LB_HW_INT_SHFT 3 -#define SH_LOCAL_INT0_ENABLE_LB_HW_INT_MASK 0x0000000000000008 - -/* SH_LOCAL_INT0_ENABLE_II_HW_INT */ -/* Description: Enable II wrapper Hardware interrupt */ -#define SH_LOCAL_INT0_ENABLE_II_HW_INT_SHFT 4 -#define SH_LOCAL_INT0_ENABLE_II_HW_INT_MASK 0x0000000000000010 - -/* SH_LOCAL_INT0_ENABLE_PI_CE_INT */ -/* Description: Enable PI Correctable Error Interrupt */ -#define SH_LOCAL_INT0_ENABLE_PI_CE_INT_SHFT 5 -#define SH_LOCAL_INT0_ENABLE_PI_CE_INT_MASK 0x0000000000000020 - -/* SH_LOCAL_INT0_ENABLE_MD_CE_INT */ -/* Description: Enable MD Correctable Error Interrupt */ -#define SH_LOCAL_INT0_ENABLE_MD_CE_INT_SHFT 6 -#define SH_LOCAL_INT0_ENABLE_MD_CE_INT_MASK 0x0000000000000040 - -/* SH_LOCAL_INT0_ENABLE_XN_CE_INT */ -/* Description: Enable XN Correctable Error Interrupt */ -#define SH_LOCAL_INT0_ENABLE_XN_CE_INT_SHFT 7 -#define SH_LOCAL_INT0_ENABLE_XN_CE_INT_MASK 0x0000000000000080 - -/* SH_LOCAL_INT0_ENABLE_PI_UCE_INT */ -/* Description: Enable PI Correctable Error Interrupt */ -#define SH_LOCAL_INT0_ENABLE_PI_UCE_INT_SHFT 8 -#define SH_LOCAL_INT0_ENABLE_PI_UCE_INT_MASK 0x0000000000000100 - -/* SH_LOCAL_INT0_ENABLE_MD_UCE_INT */ -/* Description: Enable MD Correctable Error Interrupt */ -#define SH_LOCAL_INT0_ENABLE_MD_UCE_INT_SHFT 9 -#define SH_LOCAL_INT0_ENABLE_MD_UCE_INT_MASK 0x0000000000000200 - -/* SH_LOCAL_INT0_ENABLE_XN_UCE_INT */ -/* Description: Enable XN Correctable Error Interrupt */ -#define SH_LOCAL_INT0_ENABLE_XN_UCE_INT_SHFT 10 -#define SH_LOCAL_INT0_ENABLE_XN_UCE_INT_MASK 0x0000000000000400 - -/* SH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT */ -/* Description: Enable System Shutdown Interrupt */ -#define SH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12 -#define SH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000 - -/* SH_LOCAL_INT0_ENABLE_UART_INT */ -/* Description: Enable Junk Bus UART Interrupt */ -#define SH_LOCAL_INT0_ENABLE_UART_INT_SHFT 13 -#define SH_LOCAL_INT0_ENABLE_UART_INT_MASK 0x0000000000002000 - -/* SH_LOCAL_INT0_ENABLE_L1_NMI_INT */ -/* Description: Enable L1 Controller NMI Interrupt */ -#define SH_LOCAL_INT0_ENABLE_L1_NMI_INT_SHFT 14 -#define SH_LOCAL_INT0_ENABLE_L1_NMI_INT_MASK 0x0000000000004000 - -/* SH_LOCAL_INT0_ENABLE_STOP_CLOCK */ -/* Description: Stop Clock Interrupt */ -#define SH_LOCAL_INT0_ENABLE_STOP_CLOCK_SHFT 15 -#define SH_LOCAL_INT0_ENABLE_STOP_CLOCK_MASK 0x0000000000008000 - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT1_CONFIG" */ -/* SHub Local Interrupt 1 Registers */ -/* ==================================================================== */ - -#define SH_LOCAL_INT1_CONFIG 0x0000000110000580 -#define SH_LOCAL_INT1_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_LOCAL_INT1_CONFIG_INIT 0x0000000000000000 - -/* SH_LOCAL_INT1_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_LOCAL_INT1_CONFIG_TYPE_SHFT 0 -#define SH_LOCAL_INT1_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_LOCAL_INT1_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_LOCAL_INT1_CONFIG_AGT_SHFT 3 -#define SH_LOCAL_INT1_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_LOCAL_INT1_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_LOCAL_INT1_CONFIG_PID_SHFT 4 -#define SH_LOCAL_INT1_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_LOCAL_INT1_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_LOCAL_INT1_CONFIG_BASE_SHFT 21 -#define SH_LOCAL_INT1_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_LOCAL_INT1_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_LOCAL_INT1_CONFIG_IDX_SHFT 52 -#define SH_LOCAL_INT1_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT1_ENABLE" */ -/* SHub Local Interrupt 1 Enable */ -/* ==================================================================== */ - -#define SH_LOCAL_INT1_ENABLE 0x0000000110000600 -#define SH_LOCAL_INT1_ENABLE_MASK 0x000000000000f7ff -#define SH_LOCAL_INT1_ENABLE_INIT 0x0000000000000000 - -/* SH_LOCAL_INT1_ENABLE_PI_HW_INT */ -/* Description: Enable PI Hardware interrupt */ -#define SH_LOCAL_INT1_ENABLE_PI_HW_INT_SHFT 0 -#define SH_LOCAL_INT1_ENABLE_PI_HW_INT_MASK 0x0000000000000001 - -/* SH_LOCAL_INT1_ENABLE_MD_HW_INT */ -/* Description: Enable MD Hardware interrupt */ -#define SH_LOCAL_INT1_ENABLE_MD_HW_INT_SHFT 1 -#define SH_LOCAL_INT1_ENABLE_MD_HW_INT_MASK 0x0000000000000002 - -/* SH_LOCAL_INT1_ENABLE_XN_HW_INT */ -/* Description: Enable XN Hardware interrupt */ -#define SH_LOCAL_INT1_ENABLE_XN_HW_INT_SHFT 2 -#define SH_LOCAL_INT1_ENABLE_XN_HW_INT_MASK 0x0000000000000004 - -/* SH_LOCAL_INT1_ENABLE_LB_HW_INT */ -/* Description: Enable LB Hardware interrupt */ -#define SH_LOCAL_INT1_ENABLE_LB_HW_INT_SHFT 3 -#define SH_LOCAL_INT1_ENABLE_LB_HW_INT_MASK 0x0000000000000008 - -/* SH_LOCAL_INT1_ENABLE_II_HW_INT */ -/* Description: Enable II wrapper Hardware interrupt */ -#define SH_LOCAL_INT1_ENABLE_II_HW_INT_SHFT 4 -#define SH_LOCAL_INT1_ENABLE_II_HW_INT_MASK 0x0000000000000010 - -/* SH_LOCAL_INT1_ENABLE_PI_CE_INT */ -/* Description: Enable PI Correctable Error Interrupt */ -#define SH_LOCAL_INT1_ENABLE_PI_CE_INT_SHFT 5 -#define SH_LOCAL_INT1_ENABLE_PI_CE_INT_MASK 0x0000000000000020 - -/* SH_LOCAL_INT1_ENABLE_MD_CE_INT */ -/* Description: Enable MD Correctable Error Interrupt */ -#define SH_LOCAL_INT1_ENABLE_MD_CE_INT_SHFT 6 -#define SH_LOCAL_INT1_ENABLE_MD_CE_INT_MASK 0x0000000000000040 - -/* SH_LOCAL_INT1_ENABLE_XN_CE_INT */ -/* Description: Enable XN Correctable Error Interrupt */ -#define SH_LOCAL_INT1_ENABLE_XN_CE_INT_SHFT 7 -#define SH_LOCAL_INT1_ENABLE_XN_CE_INT_MASK 0x0000000000000080 - -/* SH_LOCAL_INT1_ENABLE_PI_UCE_INT */ -/* Description: Enable PI Correctable Error Interrupt */ -#define SH_LOCAL_INT1_ENABLE_PI_UCE_INT_SHFT 8 -#define SH_LOCAL_INT1_ENABLE_PI_UCE_INT_MASK 0x0000000000000100 - -/* SH_LOCAL_INT1_ENABLE_MD_UCE_INT */ -/* Description: Enable MD Correctable Error Interrupt */ -#define SH_LOCAL_INT1_ENABLE_MD_UCE_INT_SHFT 9 -#define SH_LOCAL_INT1_ENABLE_MD_UCE_INT_MASK 0x0000000000000200 - -/* SH_LOCAL_INT1_ENABLE_XN_UCE_INT */ -/* Description: Enable XN Correctable Error Interrupt */ -#define SH_LOCAL_INT1_ENABLE_XN_UCE_INT_SHFT 10 -#define SH_LOCAL_INT1_ENABLE_XN_UCE_INT_MASK 0x0000000000000400 - -/* SH_LOCAL_INT1_ENABLE_SYSTEM_SHUTDOWN_INT */ -/* Description: Enable System Shutdown Interrupt */ -#define SH_LOCAL_INT1_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12 -#define SH_LOCAL_INT1_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000 - -/* SH_LOCAL_INT1_ENABLE_UART_INT */ -/* Description: Enable Junk Bus UART Interrupt */ -#define SH_LOCAL_INT1_ENABLE_UART_INT_SHFT 13 -#define SH_LOCAL_INT1_ENABLE_UART_INT_MASK 0x0000000000002000 - -/* SH_LOCAL_INT1_ENABLE_L1_NMI_INT */ -/* Description: Enable L1 Controller NMI Interrupt */ -#define SH_LOCAL_INT1_ENABLE_L1_NMI_INT_SHFT 14 -#define SH_LOCAL_INT1_ENABLE_L1_NMI_INT_MASK 0x0000000000004000 - -/* SH_LOCAL_INT1_ENABLE_STOP_CLOCK */ -/* Description: Stop Clock Interrupt */ -#define SH_LOCAL_INT1_ENABLE_STOP_CLOCK_SHFT 15 -#define SH_LOCAL_INT1_ENABLE_STOP_CLOCK_MASK 0x0000000000008000 - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT2_CONFIG" */ -/* SHub Local Interrupt 2 Registers */ -/* ==================================================================== */ - -#define SH_LOCAL_INT2_CONFIG 0x0000000110000680 -#define SH_LOCAL_INT2_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_LOCAL_INT2_CONFIG_INIT 0x0000000000000000 - -/* SH_LOCAL_INT2_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_LOCAL_INT2_CONFIG_TYPE_SHFT 0 -#define SH_LOCAL_INT2_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_LOCAL_INT2_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_LOCAL_INT2_CONFIG_AGT_SHFT 3 -#define SH_LOCAL_INT2_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_LOCAL_INT2_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_LOCAL_INT2_CONFIG_PID_SHFT 4 -#define SH_LOCAL_INT2_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_LOCAL_INT2_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_LOCAL_INT2_CONFIG_BASE_SHFT 21 -#define SH_LOCAL_INT2_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_LOCAL_INT2_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_LOCAL_INT2_CONFIG_IDX_SHFT 52 -#define SH_LOCAL_INT2_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT2_ENABLE" */ -/* SHub Local Interrupt 2 Enable */ -/* ==================================================================== */ - -#define SH_LOCAL_INT2_ENABLE 0x0000000110000700 -#define SH_LOCAL_INT2_ENABLE_MASK 0x000000000000f7ff -#define SH_LOCAL_INT2_ENABLE_INIT 0x0000000000000000 - -/* SH_LOCAL_INT2_ENABLE_PI_HW_INT */ -/* Description: Enable PI Hardware interrupt */ -#define SH_LOCAL_INT2_ENABLE_PI_HW_INT_SHFT 0 -#define SH_LOCAL_INT2_ENABLE_PI_HW_INT_MASK 0x0000000000000001 - -/* SH_LOCAL_INT2_ENABLE_MD_HW_INT */ -/* Description: Enable MD Hardware interrupt */ -#define SH_LOCAL_INT2_ENABLE_MD_HW_INT_SHFT 1 -#define SH_LOCAL_INT2_ENABLE_MD_HW_INT_MASK 0x0000000000000002 - -/* SH_LOCAL_INT2_ENABLE_XN_HW_INT */ -/* Description: Enable XN Hardware interrupt */ -#define SH_LOCAL_INT2_ENABLE_XN_HW_INT_SHFT 2 -#define SH_LOCAL_INT2_ENABLE_XN_HW_INT_MASK 0x0000000000000004 - -/* SH_LOCAL_INT2_ENABLE_LB_HW_INT */ -/* Description: Enable LB Hardware interrupt */ -#define SH_LOCAL_INT2_ENABLE_LB_HW_INT_SHFT 3 -#define SH_LOCAL_INT2_ENABLE_LB_HW_INT_MASK 0x0000000000000008 - -/* SH_LOCAL_INT2_ENABLE_II_HW_INT */ -/* Description: Enable II wrapper Hardware interrupt */ -#define SH_LOCAL_INT2_ENABLE_II_HW_INT_SHFT 4 -#define SH_LOCAL_INT2_ENABLE_II_HW_INT_MASK 0x0000000000000010 - -/* SH_LOCAL_INT2_ENABLE_PI_CE_INT */ -/* Description: Enable PI Correctable Error Interrupt */ -#define SH_LOCAL_INT2_ENABLE_PI_CE_INT_SHFT 5 -#define SH_LOCAL_INT2_ENABLE_PI_CE_INT_MASK 0x0000000000000020 - -/* SH_LOCAL_INT2_ENABLE_MD_CE_INT */ -/* Description: Enable MD Correctable Error Interrupt */ -#define SH_LOCAL_INT2_ENABLE_MD_CE_INT_SHFT 6 -#define SH_LOCAL_INT2_ENABLE_MD_CE_INT_MASK 0x0000000000000040 - -/* SH_LOCAL_INT2_ENABLE_XN_CE_INT */ -/* Description: Enable XN Correctable Error Interrupt */ -#define SH_LOCAL_INT2_ENABLE_XN_CE_INT_SHFT 7 -#define SH_LOCAL_INT2_ENABLE_XN_CE_INT_MASK 0x0000000000000080 - -/* SH_LOCAL_INT2_ENABLE_PI_UCE_INT */ -/* Description: Enable PI Correctable Error Interrupt */ -#define SH_LOCAL_INT2_ENABLE_PI_UCE_INT_SHFT 8 -#define SH_LOCAL_INT2_ENABLE_PI_UCE_INT_MASK 0x0000000000000100 - -/* SH_LOCAL_INT2_ENABLE_MD_UCE_INT */ -/* Description: Enable MD Correctable Error Interrupt */ -#define SH_LOCAL_INT2_ENABLE_MD_UCE_INT_SHFT 9 -#define SH_LOCAL_INT2_ENABLE_MD_UCE_INT_MASK 0x0000000000000200 - -/* SH_LOCAL_INT2_ENABLE_XN_UCE_INT */ -/* Description: Enable XN Correctable Error Interrupt */ -#define SH_LOCAL_INT2_ENABLE_XN_UCE_INT_SHFT 10 -#define SH_LOCAL_INT2_ENABLE_XN_UCE_INT_MASK 0x0000000000000400 - -/* SH_LOCAL_INT2_ENABLE_SYSTEM_SHUTDOWN_INT */ -/* Description: Enable System Shutdown Interrupt */ -#define SH_LOCAL_INT2_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12 -#define SH_LOCAL_INT2_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000 - -/* SH_LOCAL_INT2_ENABLE_UART_INT */ -/* Description: Enable Junk Bus UART Interrupt */ -#define SH_LOCAL_INT2_ENABLE_UART_INT_SHFT 13 -#define SH_LOCAL_INT2_ENABLE_UART_INT_MASK 0x0000000000002000 - -/* SH_LOCAL_INT2_ENABLE_L1_NMI_INT */ -/* Description: Enable L1 Controller NMI Interrupt */ -#define SH_LOCAL_INT2_ENABLE_L1_NMI_INT_SHFT 14 -#define SH_LOCAL_INT2_ENABLE_L1_NMI_INT_MASK 0x0000000000004000 - -/* SH_LOCAL_INT2_ENABLE_STOP_CLOCK */ -/* Description: Stop Clock Interrupt */ -#define SH_LOCAL_INT2_ENABLE_STOP_CLOCK_SHFT 15 -#define SH_LOCAL_INT2_ENABLE_STOP_CLOCK_MASK 0x0000000000008000 - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT3_CONFIG" */ -/* SHub Local Interrupt 3 Registers */ -/* ==================================================================== */ - -#define SH_LOCAL_INT3_CONFIG 0x0000000110000780 -#define SH_LOCAL_INT3_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_LOCAL_INT3_CONFIG_INIT 0x0000000000000000 - -/* SH_LOCAL_INT3_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_LOCAL_INT3_CONFIG_TYPE_SHFT 0 -#define SH_LOCAL_INT3_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_LOCAL_INT3_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_LOCAL_INT3_CONFIG_AGT_SHFT 3 -#define SH_LOCAL_INT3_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_LOCAL_INT3_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_LOCAL_INT3_CONFIG_PID_SHFT 4 -#define SH_LOCAL_INT3_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_LOCAL_INT3_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_LOCAL_INT3_CONFIG_BASE_SHFT 21 -#define SH_LOCAL_INT3_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_LOCAL_INT3_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_LOCAL_INT3_CONFIG_IDX_SHFT 52 -#define SH_LOCAL_INT3_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT3_ENABLE" */ -/* SHub Local Interrupt 3 Enable */ -/* ==================================================================== */ - -#define SH_LOCAL_INT3_ENABLE 0x0000000110000800 -#define SH_LOCAL_INT3_ENABLE_MASK 0x000000000000f7ff -#define SH_LOCAL_INT3_ENABLE_INIT 0x0000000000000000 - -/* SH_LOCAL_INT3_ENABLE_PI_HW_INT */ -/* Description: Enable PI Hardware interrupt */ -#define SH_LOCAL_INT3_ENABLE_PI_HW_INT_SHFT 0 -#define SH_LOCAL_INT3_ENABLE_PI_HW_INT_MASK 0x0000000000000001 - -/* SH_LOCAL_INT3_ENABLE_MD_HW_INT */ -/* Description: Enable MD Hardware interrupt */ -#define SH_LOCAL_INT3_ENABLE_MD_HW_INT_SHFT 1 -#define SH_LOCAL_INT3_ENABLE_MD_HW_INT_MASK 0x0000000000000002 - -/* SH_LOCAL_INT3_ENABLE_XN_HW_INT */ -/* Description: Enable XN Hardware interrupt */ -#define SH_LOCAL_INT3_ENABLE_XN_HW_INT_SHFT 2 -#define SH_LOCAL_INT3_ENABLE_XN_HW_INT_MASK 0x0000000000000004 - -/* SH_LOCAL_INT3_ENABLE_LB_HW_INT */ -/* Description: Enable LB Hardware interrupt */ -#define SH_LOCAL_INT3_ENABLE_LB_HW_INT_SHFT 3 -#define SH_LOCAL_INT3_ENABLE_LB_HW_INT_MASK 0x0000000000000008 - -/* SH_LOCAL_INT3_ENABLE_II_HW_INT */ -/* Description: Enable II wrapper Hardware interrupt */ -#define SH_LOCAL_INT3_ENABLE_II_HW_INT_SHFT 4 -#define SH_LOCAL_INT3_ENABLE_II_HW_INT_MASK 0x0000000000000010 - -/* SH_LOCAL_INT3_ENABLE_PI_CE_INT */ -/* Description: Enable PI Correctable Error Interrupt */ -#define SH_LOCAL_INT3_ENABLE_PI_CE_INT_SHFT 5 -#define SH_LOCAL_INT3_ENABLE_PI_CE_INT_MASK 0x0000000000000020 - -/* SH_LOCAL_INT3_ENABLE_MD_CE_INT */ -/* Description: Enable MD Correctable Error Interrupt */ -#define SH_LOCAL_INT3_ENABLE_MD_CE_INT_SHFT 6 -#define SH_LOCAL_INT3_ENABLE_MD_CE_INT_MASK 0x0000000000000040 - -/* SH_LOCAL_INT3_ENABLE_XN_CE_INT */ -/* Description: Enable XN Correctable Error Interrupt */ -#define SH_LOCAL_INT3_ENABLE_XN_CE_INT_SHFT 7 -#define SH_LOCAL_INT3_ENABLE_XN_CE_INT_MASK 0x0000000000000080 - -/* SH_LOCAL_INT3_ENABLE_PI_UCE_INT */ -/* Description: Enable PI Correctable Error Interrupt */ -#define SH_LOCAL_INT3_ENABLE_PI_UCE_INT_SHFT 8 -#define SH_LOCAL_INT3_ENABLE_PI_UCE_INT_MASK 0x0000000000000100 - -/* SH_LOCAL_INT3_ENABLE_MD_UCE_INT */ -/* Description: Enable MD Correctable Error Interrupt */ -#define SH_LOCAL_INT3_ENABLE_MD_UCE_INT_SHFT 9 -#define SH_LOCAL_INT3_ENABLE_MD_UCE_INT_MASK 0x0000000000000200 - -/* SH_LOCAL_INT3_ENABLE_XN_UCE_INT */ -/* Description: Enable XN Correctable Error Interrupt */ -#define SH_LOCAL_INT3_ENABLE_XN_UCE_INT_SHFT 10 -#define SH_LOCAL_INT3_ENABLE_XN_UCE_INT_MASK 0x0000000000000400 - -/* SH_LOCAL_INT3_ENABLE_SYSTEM_SHUTDOWN_INT */ -/* Description: Enable System Shutdown Interrupt */ -#define SH_LOCAL_INT3_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12 -#define SH_LOCAL_INT3_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000 - -/* SH_LOCAL_INT3_ENABLE_UART_INT */ -/* Description: Enable Junk Bus UART Interrupt */ -#define SH_LOCAL_INT3_ENABLE_UART_INT_SHFT 13 -#define SH_LOCAL_INT3_ENABLE_UART_INT_MASK 0x0000000000002000 - -/* SH_LOCAL_INT3_ENABLE_L1_NMI_INT */ -/* Description: Enable L1 Controller NMI Interrupt */ -#define SH_LOCAL_INT3_ENABLE_L1_NMI_INT_SHFT 14 -#define SH_LOCAL_INT3_ENABLE_L1_NMI_INT_MASK 0x0000000000004000 - -/* SH_LOCAL_INT3_ENABLE_STOP_CLOCK */ -/* Description: Stop Clock Interrupt */ -#define SH_LOCAL_INT3_ENABLE_STOP_CLOCK_SHFT 15 -#define SH_LOCAL_INT3_ENABLE_STOP_CLOCK_MASK 0x0000000000008000 - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT4_CONFIG" */ -/* SHub Local Interrupt 4 Registers */ -/* ==================================================================== */ - -#define SH_LOCAL_INT4_CONFIG 0x0000000110000880 -#define SH_LOCAL_INT4_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_LOCAL_INT4_CONFIG_INIT 0x0000000000000000 - -/* SH_LOCAL_INT4_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_LOCAL_INT4_CONFIG_TYPE_SHFT 0 -#define SH_LOCAL_INT4_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_LOCAL_INT4_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_LOCAL_INT4_CONFIG_AGT_SHFT 3 -#define SH_LOCAL_INT4_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_LOCAL_INT4_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_LOCAL_INT4_CONFIG_PID_SHFT 4 -#define SH_LOCAL_INT4_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_LOCAL_INT4_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_LOCAL_INT4_CONFIG_BASE_SHFT 21 -#define SH_LOCAL_INT4_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_LOCAL_INT4_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_LOCAL_INT4_CONFIG_IDX_SHFT 52 -#define SH_LOCAL_INT4_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT4_ENABLE" */ -/* SHub Local Interrupt 4 Enable */ -/* ==================================================================== */ - -#define SH_LOCAL_INT4_ENABLE 0x0000000110000900 -#define SH_LOCAL_INT4_ENABLE_MASK 0x000000000000f7ff -#define SH_LOCAL_INT4_ENABLE_INIT 0x0000000000000000 - -/* SH_LOCAL_INT4_ENABLE_PI_HW_INT */ -/* Description: Enable PI Hardware interrupt */ -#define SH_LOCAL_INT4_ENABLE_PI_HW_INT_SHFT 0 -#define SH_LOCAL_INT4_ENABLE_PI_HW_INT_MASK 0x0000000000000001 - -/* SH_LOCAL_INT4_ENABLE_MD_HW_INT */ -/* Description: Enable MD Hardware interrupt */ -#define SH_LOCAL_INT4_ENABLE_MD_HW_INT_SHFT 1 -#define SH_LOCAL_INT4_ENABLE_MD_HW_INT_MASK 0x0000000000000002 - -/* SH_LOCAL_INT4_ENABLE_XN_HW_INT */ -/* Description: Enable XN Hardware interrupt */ -#define SH_LOCAL_INT4_ENABLE_XN_HW_INT_SHFT 2 -#define SH_LOCAL_INT4_ENABLE_XN_HW_INT_MASK 0x0000000000000004 - -/* SH_LOCAL_INT4_ENABLE_LB_HW_INT */ -/* Description: Enable LB Hardware interrupt */ -#define SH_LOCAL_INT4_ENABLE_LB_HW_INT_SHFT 3 -#define SH_LOCAL_INT4_ENABLE_LB_HW_INT_MASK 0x0000000000000008 - -/* SH_LOCAL_INT4_ENABLE_II_HW_INT */ -/* Description: Enable II wrapper Hardware interrupt */ -#define SH_LOCAL_INT4_ENABLE_II_HW_INT_SHFT 4 -#define SH_LOCAL_INT4_ENABLE_II_HW_INT_MASK 0x0000000000000010 - -/* SH_LOCAL_INT4_ENABLE_PI_CE_INT */ -/* Description: Enable PI Correctable Error Interrupt */ -#define SH_LOCAL_INT4_ENABLE_PI_CE_INT_SHFT 5 -#define SH_LOCAL_INT4_ENABLE_PI_CE_INT_MASK 0x0000000000000020 - -/* SH_LOCAL_INT4_ENABLE_MD_CE_INT */ -/* Description: Enable MD Correctable Error Interrupt */ -#define SH_LOCAL_INT4_ENABLE_MD_CE_INT_SHFT 6 -#define SH_LOCAL_INT4_ENABLE_MD_CE_INT_MASK 0x0000000000000040 - -/* SH_LOCAL_INT4_ENABLE_XN_CE_INT */ -/* Description: Enable XN Correctable Error Interrupt */ -#define SH_LOCAL_INT4_ENABLE_XN_CE_INT_SHFT 7 -#define SH_LOCAL_INT4_ENABLE_XN_CE_INT_MASK 0x0000000000000080 - -/* SH_LOCAL_INT4_ENABLE_PI_UCE_INT */ -/* Description: Enable PI Correctable Error Interrupt */ -#define SH_LOCAL_INT4_ENABLE_PI_UCE_INT_SHFT 8 -#define SH_LOCAL_INT4_ENABLE_PI_UCE_INT_MASK 0x0000000000000100 - -/* SH_LOCAL_INT4_ENABLE_MD_UCE_INT */ -/* Description: Enable MD Correctable Error Interrupt */ -#define SH_LOCAL_INT4_ENABLE_MD_UCE_INT_SHFT 9 -#define SH_LOCAL_INT4_ENABLE_MD_UCE_INT_MASK 0x0000000000000200 - -/* SH_LOCAL_INT4_ENABLE_XN_UCE_INT */ -/* Description: Enable XN Correctable Error Interrupt */ -#define SH_LOCAL_INT4_ENABLE_XN_UCE_INT_SHFT 10 -#define SH_LOCAL_INT4_ENABLE_XN_UCE_INT_MASK 0x0000000000000400 - -/* SH_LOCAL_INT4_ENABLE_SYSTEM_SHUTDOWN_INT */ -/* Description: Enable System Shutdown Interrupt */ -#define SH_LOCAL_INT4_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12 -#define SH_LOCAL_INT4_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000 - -/* SH_LOCAL_INT4_ENABLE_UART_INT */ -/* Description: Enable Junk Bus UART Interrupt */ -#define SH_LOCAL_INT4_ENABLE_UART_INT_SHFT 13 -#define SH_LOCAL_INT4_ENABLE_UART_INT_MASK 0x0000000000002000 - -/* SH_LOCAL_INT4_ENABLE_L1_NMI_INT */ -/* Description: Enable L1 Controller NMI Interrupt */ -#define SH_LOCAL_INT4_ENABLE_L1_NMI_INT_SHFT 14 -#define SH_LOCAL_INT4_ENABLE_L1_NMI_INT_MASK 0x0000000000004000 - -/* SH_LOCAL_INT4_ENABLE_STOP_CLOCK */ -/* Description: Stop Clock Interrupt */ -#define SH_LOCAL_INT4_ENABLE_STOP_CLOCK_SHFT 15 -#define SH_LOCAL_INT4_ENABLE_STOP_CLOCK_MASK 0x0000000000008000 - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT5_CONFIG" */ -/* SHub Local Interrupt 5 Registers */ -/* ==================================================================== */ - -#define SH_LOCAL_INT5_CONFIG 0x0000000110000980 -#define SH_LOCAL_INT5_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_LOCAL_INT5_CONFIG_INIT 0x0000000000000000 - -/* SH_LOCAL_INT5_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_LOCAL_INT5_CONFIG_TYPE_SHFT 0 -#define SH_LOCAL_INT5_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_LOCAL_INT5_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_LOCAL_INT5_CONFIG_AGT_SHFT 3 -#define SH_LOCAL_INT5_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_LOCAL_INT5_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_LOCAL_INT5_CONFIG_PID_SHFT 4 -#define SH_LOCAL_INT5_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_LOCAL_INT5_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_LOCAL_INT5_CONFIG_BASE_SHFT 21 -#define SH_LOCAL_INT5_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_LOCAL_INT5_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_LOCAL_INT5_CONFIG_IDX_SHFT 52 -#define SH_LOCAL_INT5_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_LOCAL_INT5_ENABLE" */ -/* SHub Local Interrupt 5 Enable */ -/* ==================================================================== */ - -#define SH_LOCAL_INT5_ENABLE 0x0000000110000a00 -#define SH_LOCAL_INT5_ENABLE_MASK 0x000000000000f7ff -#define SH_LOCAL_INT5_ENABLE_INIT 0x0000000000000000 - -/* SH_LOCAL_INT5_ENABLE_PI_HW_INT */ -/* Description: Enable PI Hardware interrupt */ -#define SH_LOCAL_INT5_ENABLE_PI_HW_INT_SHFT 0 -#define SH_LOCAL_INT5_ENABLE_PI_HW_INT_MASK 0x0000000000000001 - -/* SH_LOCAL_INT5_ENABLE_MD_HW_INT */ -/* Description: Enable MD Hardware interrupt */ -#define SH_LOCAL_INT5_ENABLE_MD_HW_INT_SHFT 1 -#define SH_LOCAL_INT5_ENABLE_MD_HW_INT_MASK 0x0000000000000002 - -/* SH_LOCAL_INT5_ENABLE_XN_HW_INT */ -/* Description: Enable XN Hardware interrupt */ -#define SH_LOCAL_INT5_ENABLE_XN_HW_INT_SHFT 2 -#define SH_LOCAL_INT5_ENABLE_XN_HW_INT_MASK 0x0000000000000004 - -/* SH_LOCAL_INT5_ENABLE_LB_HW_INT */ -/* Description: Enable LB Hardware interrupt */ -#define SH_LOCAL_INT5_ENABLE_LB_HW_INT_SHFT 3 -#define SH_LOCAL_INT5_ENABLE_LB_HW_INT_MASK 0x0000000000000008 - -/* SH_LOCAL_INT5_ENABLE_II_HW_INT */ -/* Description: Enable II wrapper Hardware interrupt */ -#define SH_LOCAL_INT5_ENABLE_II_HW_INT_SHFT 4 -#define SH_LOCAL_INT5_ENABLE_II_HW_INT_MASK 0x0000000000000010 - -/* SH_LOCAL_INT5_ENABLE_PI_CE_INT */ -/* Description: Enable PI Correctable Error Interrupt */ -#define SH_LOCAL_INT5_ENABLE_PI_CE_INT_SHFT 5 -#define SH_LOCAL_INT5_ENABLE_PI_CE_INT_MASK 0x0000000000000020 - -/* SH_LOCAL_INT5_ENABLE_MD_CE_INT */ -/* Description: Enable MD Correctable Error Interrupt */ -#define SH_LOCAL_INT5_ENABLE_MD_CE_INT_SHFT 6 -#define SH_LOCAL_INT5_ENABLE_MD_CE_INT_MASK 0x0000000000000040 - -/* SH_LOCAL_INT5_ENABLE_XN_CE_INT */ -/* Description: Enable XN Correctable Error Interrupt */ -#define SH_LOCAL_INT5_ENABLE_XN_CE_INT_SHFT 7 -#define SH_LOCAL_INT5_ENABLE_XN_CE_INT_MASK 0x0000000000000080 - -/* SH_LOCAL_INT5_ENABLE_PI_UCE_INT */ -/* Description: Enable PI Correctable Error Interrupt */ -#define SH_LOCAL_INT5_ENABLE_PI_UCE_INT_SHFT 8 -#define SH_LOCAL_INT5_ENABLE_PI_UCE_INT_MASK 0x0000000000000100 - -/* SH_LOCAL_INT5_ENABLE_MD_UCE_INT */ -/* Description: Enable MD Correctable Error Interrupt */ -#define SH_LOCAL_INT5_ENABLE_MD_UCE_INT_SHFT 9 -#define SH_LOCAL_INT5_ENABLE_MD_UCE_INT_MASK 0x0000000000000200 - -/* SH_LOCAL_INT5_ENABLE_XN_UCE_INT */ -/* Description: Enable XN Correctable Error Interrupt */ -#define SH_LOCAL_INT5_ENABLE_XN_UCE_INT_SHFT 10 -#define SH_LOCAL_INT5_ENABLE_XN_UCE_INT_MASK 0x0000000000000400 - -/* SH_LOCAL_INT5_ENABLE_SYSTEM_SHUTDOWN_INT */ -/* Description: Enable System Shutdown Interrupt */ -#define SH_LOCAL_INT5_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12 -#define SH_LOCAL_INT5_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000 - -/* SH_LOCAL_INT5_ENABLE_UART_INT */ -/* Description: Enable Junk Bus UART Interrupt */ -#define SH_LOCAL_INT5_ENABLE_UART_INT_SHFT 13 -#define SH_LOCAL_INT5_ENABLE_UART_INT_MASK 0x0000000000002000 - -/* SH_LOCAL_INT5_ENABLE_L1_NMI_INT */ -/* Description: Enable L1 Controller NMI Interrupt */ -#define SH_LOCAL_INT5_ENABLE_L1_NMI_INT_SHFT 14 -#define SH_LOCAL_INT5_ENABLE_L1_NMI_INT_MASK 0x0000000000004000 - -/* SH_LOCAL_INT5_ENABLE_STOP_CLOCK */ -/* Description: Stop Clock Interrupt */ -#define SH_LOCAL_INT5_ENABLE_STOP_CLOCK_SHFT 15 -#define SH_LOCAL_INT5_ENABLE_STOP_CLOCK_MASK 0x0000000000008000 - -/* ==================================================================== */ -/* Register "SH_PROC0_ERR_INT_CONFIG" */ -/* SHub Processor 0 Error Interrupt Registers */ -/* ==================================================================== */ - -#define SH_PROC0_ERR_INT_CONFIG 0x0000000110000a80 -#define SH_PROC0_ERR_INT_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_PROC0_ERR_INT_CONFIG_INIT 0x0000000000000000 - -/* SH_PROC0_ERR_INT_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_PROC0_ERR_INT_CONFIG_TYPE_SHFT 0 -#define SH_PROC0_ERR_INT_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_PROC0_ERR_INT_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_PROC0_ERR_INT_CONFIG_AGT_SHFT 3 -#define SH_PROC0_ERR_INT_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_PROC0_ERR_INT_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_PROC0_ERR_INT_CONFIG_PID_SHFT 4 -#define SH_PROC0_ERR_INT_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_PROC0_ERR_INT_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_PROC0_ERR_INT_CONFIG_BASE_SHFT 21 -#define SH_PROC0_ERR_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_PROC0_ERR_INT_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_PROC0_ERR_INT_CONFIG_IDX_SHFT 52 -#define SH_PROC0_ERR_INT_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC1_ERR_INT_CONFIG" */ -/* SHub Processor 1 Error Interrupt Registers */ -/* ==================================================================== */ - -#define SH_PROC1_ERR_INT_CONFIG 0x0000000110000b00 -#define SH_PROC1_ERR_INT_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_PROC1_ERR_INT_CONFIG_INIT 0x0000000000000000 - -/* SH_PROC1_ERR_INT_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_PROC1_ERR_INT_CONFIG_TYPE_SHFT 0 -#define SH_PROC1_ERR_INT_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_PROC1_ERR_INT_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_PROC1_ERR_INT_CONFIG_AGT_SHFT 3 -#define SH_PROC1_ERR_INT_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_PROC1_ERR_INT_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_PROC1_ERR_INT_CONFIG_PID_SHFT 4 -#define SH_PROC1_ERR_INT_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_PROC1_ERR_INT_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_PROC1_ERR_INT_CONFIG_BASE_SHFT 21 -#define SH_PROC1_ERR_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_PROC1_ERR_INT_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_PROC1_ERR_INT_CONFIG_IDX_SHFT 52 -#define SH_PROC1_ERR_INT_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC2_ERR_INT_CONFIG" */ -/* SHub Processor 2 Error Interrupt Registers */ -/* ==================================================================== */ - -#define SH_PROC2_ERR_INT_CONFIG 0x0000000110000b80 -#define SH_PROC2_ERR_INT_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_PROC2_ERR_INT_CONFIG_INIT 0x0000000000000000 - -/* SH_PROC2_ERR_INT_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_PROC2_ERR_INT_CONFIG_TYPE_SHFT 0 -#define SH_PROC2_ERR_INT_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_PROC2_ERR_INT_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_PROC2_ERR_INT_CONFIG_AGT_SHFT 3 -#define SH_PROC2_ERR_INT_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_PROC2_ERR_INT_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_PROC2_ERR_INT_CONFIG_PID_SHFT 4 -#define SH_PROC2_ERR_INT_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_PROC2_ERR_INT_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_PROC2_ERR_INT_CONFIG_BASE_SHFT 21 -#define SH_PROC2_ERR_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_PROC2_ERR_INT_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_PROC2_ERR_INT_CONFIG_IDX_SHFT 52 -#define SH_PROC2_ERR_INT_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC3_ERR_INT_CONFIG" */ -/* SHub Processor 3 Error Interrupt Registers */ -/* ==================================================================== */ - -#define SH_PROC3_ERR_INT_CONFIG 0x0000000110000c00 -#define SH_PROC3_ERR_INT_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_PROC3_ERR_INT_CONFIG_INIT 0x0000000000000000 - -/* SH_PROC3_ERR_INT_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_PROC3_ERR_INT_CONFIG_TYPE_SHFT 0 -#define SH_PROC3_ERR_INT_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_PROC3_ERR_INT_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_PROC3_ERR_INT_CONFIG_AGT_SHFT 3 -#define SH_PROC3_ERR_INT_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_PROC3_ERR_INT_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_PROC3_ERR_INT_CONFIG_PID_SHFT 4 -#define SH_PROC3_ERR_INT_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_PROC3_ERR_INT_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_PROC3_ERR_INT_CONFIG_BASE_SHFT 21 -#define SH_PROC3_ERR_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_PROC3_ERR_INT_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_PROC3_ERR_INT_CONFIG_IDX_SHFT 52 -#define SH_PROC3_ERR_INT_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC0_ADV_INT_CONFIG" */ -/* SHub Processor 0 Advisory Interrupt Registers */ -/* ==================================================================== */ - -#define SH_PROC0_ADV_INT_CONFIG 0x0000000110000c80 -#define SH_PROC0_ADV_INT_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_PROC0_ADV_INT_CONFIG_INIT 0x0000000000000000 - -/* SH_PROC0_ADV_INT_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_PROC0_ADV_INT_CONFIG_TYPE_SHFT 0 -#define SH_PROC0_ADV_INT_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_PROC0_ADV_INT_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_PROC0_ADV_INT_CONFIG_AGT_SHFT 3 -#define SH_PROC0_ADV_INT_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_PROC0_ADV_INT_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_PROC0_ADV_INT_CONFIG_PID_SHFT 4 -#define SH_PROC0_ADV_INT_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_PROC0_ADV_INT_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_PROC0_ADV_INT_CONFIG_BASE_SHFT 21 -#define SH_PROC0_ADV_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_PROC0_ADV_INT_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_PROC0_ADV_INT_CONFIG_IDX_SHFT 52 -#define SH_PROC0_ADV_INT_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC1_ADV_INT_CONFIG" */ -/* SHub Processor 1 Advisory Interrupt Registers */ -/* ==================================================================== */ - -#define SH_PROC1_ADV_INT_CONFIG 0x0000000110000d00 -#define SH_PROC1_ADV_INT_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_PROC1_ADV_INT_CONFIG_INIT 0x0000000000000000 - -/* SH_PROC1_ADV_INT_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_PROC1_ADV_INT_CONFIG_TYPE_SHFT 0 -#define SH_PROC1_ADV_INT_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_PROC1_ADV_INT_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_PROC1_ADV_INT_CONFIG_AGT_SHFT 3 -#define SH_PROC1_ADV_INT_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_PROC1_ADV_INT_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_PROC1_ADV_INT_CONFIG_PID_SHFT 4 -#define SH_PROC1_ADV_INT_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_PROC1_ADV_INT_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_PROC1_ADV_INT_CONFIG_BASE_SHFT 21 -#define SH_PROC1_ADV_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_PROC1_ADV_INT_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_PROC1_ADV_INT_CONFIG_IDX_SHFT 52 -#define SH_PROC1_ADV_INT_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC2_ADV_INT_CONFIG" */ -/* SHub Processor 2 Advisory Interrupt Registers */ -/* ==================================================================== */ - -#define SH_PROC2_ADV_INT_CONFIG 0x0000000110000d80 -#define SH_PROC2_ADV_INT_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_PROC2_ADV_INT_CONFIG_INIT 0x0000000000000000 - -/* SH_PROC2_ADV_INT_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_PROC2_ADV_INT_CONFIG_TYPE_SHFT 0 -#define SH_PROC2_ADV_INT_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_PROC2_ADV_INT_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_PROC2_ADV_INT_CONFIG_AGT_SHFT 3 -#define SH_PROC2_ADV_INT_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_PROC2_ADV_INT_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_PROC2_ADV_INT_CONFIG_PID_SHFT 4 -#define SH_PROC2_ADV_INT_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_PROC2_ADV_INT_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_PROC2_ADV_INT_CONFIG_BASE_SHFT 21 -#define SH_PROC2_ADV_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_PROC2_ADV_INT_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_PROC2_ADV_INT_CONFIG_IDX_SHFT 52 -#define SH_PROC2_ADV_INT_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC3_ADV_INT_CONFIG" */ -/* SHub Processor 3 Advisory Interrupt Registers */ -/* ==================================================================== */ - -#define SH_PROC3_ADV_INT_CONFIG 0x0000000110000e00 -#define SH_PROC3_ADV_INT_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_PROC3_ADV_INT_CONFIG_INIT 0x0000000000000000 - -/* SH_PROC3_ADV_INT_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_PROC3_ADV_INT_CONFIG_TYPE_SHFT 0 -#define SH_PROC3_ADV_INT_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_PROC3_ADV_INT_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_PROC3_ADV_INT_CONFIG_AGT_SHFT 3 -#define SH_PROC3_ADV_INT_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_PROC3_ADV_INT_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_PROC3_ADV_INT_CONFIG_PID_SHFT 4 -#define SH_PROC3_ADV_INT_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_PROC3_ADV_INT_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_PROC3_ADV_INT_CONFIG_BASE_SHFT 21 -#define SH_PROC3_ADV_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_PROC3_ADV_INT_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_PROC3_ADV_INT_CONFIG_IDX_SHFT 52 -#define SH_PROC3_ADV_INT_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC0_ERR_INT_ENABLE" */ -/* SHub Processor 0 Error Interrupt Enable Registers */ -/* ==================================================================== */ - -#define SH_PROC0_ERR_INT_ENABLE 0x0000000110000e80 -#define SH_PROC0_ERR_INT_ENABLE_MASK 0x0000000000000001 -#define SH_PROC0_ERR_INT_ENABLE_INIT 0x0000000000000000 - -/* SH_PROC0_ERR_INT_ENABLE_PROC0_ERR_ENABLE */ -/* Description: Enable Processor 0 Error Interrupt */ -#define SH_PROC0_ERR_INT_ENABLE_PROC0_ERR_ENABLE_SHFT 0 -#define SH_PROC0_ERR_INT_ENABLE_PROC0_ERR_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_PROC1_ERR_INT_ENABLE" */ -/* SHub Processor 1 Error Interrupt Enable Registers */ -/* ==================================================================== */ +#define SH_IPI_INT_SEND_MASK 0x8000000000000000UL -#define SH_PROC1_ERR_INT_ENABLE 0x0000000110000f00 -#define SH_PROC1_ERR_INT_ENABLE_MASK 0x0000000000000001 -#define SH_PROC1_ERR_INT_ENABLE_INIT 0x0000000000000000 - -/* SH_PROC1_ERR_INT_ENABLE_PROC1_ERR_ENABLE */ -/* Description: Enable Processor 1 Error Interrupt */ -#define SH_PROC1_ERR_INT_ENABLE_PROC1_ERR_ENABLE_SHFT 0 -#define SH_PROC1_ERR_INT_ENABLE_PROC1_ERR_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_PROC2_ERR_INT_ENABLE" */ -/* SHub Processor 2 Error Interrupt Enable Registers */ -/* ==================================================================== */ - -#define SH_PROC2_ERR_INT_ENABLE 0x0000000110000f80 -#define SH_PROC2_ERR_INT_ENABLE_MASK 0x0000000000000001 -#define SH_PROC2_ERR_INT_ENABLE_INIT 0x0000000000000000 - -/* SH_PROC2_ERR_INT_ENABLE_PROC2_ERR_ENABLE */ -/* Description: Enable Processor 2 Error Interrupt */ -#define SH_PROC2_ERR_INT_ENABLE_PROC2_ERR_ENABLE_SHFT 0 -#define SH_PROC2_ERR_INT_ENABLE_PROC2_ERR_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_PROC3_ERR_INT_ENABLE" */ -/* SHub Processor 3 Error Interrupt Enable Registers */ -/* ==================================================================== */ - -#define SH_PROC3_ERR_INT_ENABLE 0x0000000110001000 -#define SH_PROC3_ERR_INT_ENABLE_MASK 0x0000000000000001 -#define SH_PROC3_ERR_INT_ENABLE_INIT 0x0000000000000000 - -/* SH_PROC3_ERR_INT_ENABLE_PROC3_ERR_ENABLE */ -/* Description: Enable Processor 3 Error Interrupt */ -#define SH_PROC3_ERR_INT_ENABLE_PROC3_ERR_ENABLE_SHFT 0 -#define SH_PROC3_ERR_INT_ENABLE_PROC3_ERR_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_PROC0_ADV_INT_ENABLE" */ -/* SHub Processor 0 Advisory Interrupt Enable Registers */ -/* ==================================================================== */ - -#define SH_PROC0_ADV_INT_ENABLE 0x0000000110001080 -#define SH_PROC0_ADV_INT_ENABLE_MASK 0x0000000000000001 -#define SH_PROC0_ADV_INT_ENABLE_INIT 0x0000000000000000 - -/* SH_PROC0_ADV_INT_ENABLE_PROC0_ADV_ENABLE */ -/* Description: Enable Processor 0 Advisory Interrupt */ -#define SH_PROC0_ADV_INT_ENABLE_PROC0_ADV_ENABLE_SHFT 0 -#define SH_PROC0_ADV_INT_ENABLE_PROC0_ADV_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_PROC1_ADV_INT_ENABLE" */ -/* SHub Processor 1 Advisory Interrupt Enable Registers */ -/* ==================================================================== */ - -#define SH_PROC1_ADV_INT_ENABLE 0x0000000110001100 -#define SH_PROC1_ADV_INT_ENABLE_MASK 0x0000000000000001 -#define SH_PROC1_ADV_INT_ENABLE_INIT 0x0000000000000000 - -/* SH_PROC1_ADV_INT_ENABLE_PROC1_ADV_ENABLE */ -/* Description: Enable Processor 1 Advisory Interrupt */ -#define SH_PROC1_ADV_INT_ENABLE_PROC1_ADV_ENABLE_SHFT 0 -#define SH_PROC1_ADV_INT_ENABLE_PROC1_ADV_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_PROC2_ADV_INT_ENABLE" */ -/* SHub Processor 2 Advisory Interrupt Enable Registers */ -/* ==================================================================== */ - -#define SH_PROC2_ADV_INT_ENABLE 0x0000000110001180 -#define SH_PROC2_ADV_INT_ENABLE_MASK 0x0000000000000001 -#define SH_PROC2_ADV_INT_ENABLE_INIT 0x0000000000000000 - -/* SH_PROC2_ADV_INT_ENABLE_PROC2_ADV_ENABLE */ -/* Description: Enable Processor 2 Advisory Interrupt */ -#define SH_PROC2_ADV_INT_ENABLE_PROC2_ADV_ENABLE_SHFT 0 -#define SH_PROC2_ADV_INT_ENABLE_PROC2_ADV_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_PROC3_ADV_INT_ENABLE" */ -/* SHub Processor 3 Advisory Interrupt Enable Registers */ -/* ==================================================================== */ - -#define SH_PROC3_ADV_INT_ENABLE 0x0000000110001200 -#define SH_PROC3_ADV_INT_ENABLE_MASK 0x0000000000000001 -#define SH_PROC3_ADV_INT_ENABLE_INIT 0x0000000000000000 - -/* SH_PROC3_ADV_INT_ENABLE_PROC3_ADV_ENABLE */ -/* Description: Enable Processor 3 Advisory Interrupt */ -#define SH_PROC3_ADV_INT_ENABLE_PROC3_ADV_ENABLE_SHFT 0 -#define SH_PROC3_ADV_INT_ENABLE_PROC3_ADV_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_PROFILE_INT_CONFIG" */ -/* SHub Profile Interrupt Configuration Registers */ /* ==================================================================== */ - -#define SH_PROFILE_INT_CONFIG 0x0000000110001280 -#define SH_PROFILE_INT_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_PROFILE_INT_CONFIG_INIT 0x0000000000000000 - -/* SH_PROFILE_INT_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_PROFILE_INT_CONFIG_TYPE_SHFT 0 -#define SH_PROFILE_INT_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_PROFILE_INT_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_PROFILE_INT_CONFIG_AGT_SHFT 3 -#define SH_PROFILE_INT_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_PROFILE_INT_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_PROFILE_INT_CONFIG_PID_SHFT 4 -#define SH_PROFILE_INT_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_PROFILE_INT_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_PROFILE_INT_CONFIG_BASE_SHFT 21 -#define SH_PROFILE_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_PROFILE_INT_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_PROFILE_INT_CONFIG_IDX_SHFT 52 -#define SH_PROFILE_INT_CONFIG_IDX_MASK 0x0ff0000000000000 - -/* ==================================================================== */ -/* Register "SH_PROFILE_INT_ENABLE" */ -/* SHub Profile Interrupt Enable Registers */ -/* ==================================================================== */ - -#define SH_PROFILE_INT_ENABLE 0x0000000110001300 -#define SH_PROFILE_INT_ENABLE_MASK 0x0000000000000001 -#define SH_PROFILE_INT_ENABLE_INIT 0x0000000000000000 - -/* SH_PROFILE_INT_ENABLE_PROFILE_ENABLE */ -/* Description: Enable Profile Interrupt */ -#define SH_PROFILE_INT_ENABLE_PROFILE_ENABLE_SHFT 0 -#define SH_PROFILE_INT_ENABLE_PROFILE_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_RTC0_INT_CONFIG" */ -/* SHub RTC 0 Interrupt Config Registers */ +/* Register "SH_EVENT_OCCURRED" */ +/* SHub Interrupt Event Occurred */ /* ==================================================================== */ - -#define SH_RTC0_INT_CONFIG 0x0000000110001380 -#define SH_RTC0_INT_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_RTC0_INT_CONFIG_INIT 0x0000000000000000 - -/* SH_RTC0_INT_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_RTC0_INT_CONFIG_TYPE_SHFT 0 -#define SH_RTC0_INT_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_RTC0_INT_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_RTC0_INT_CONFIG_AGT_SHFT 3 -#define SH_RTC0_INT_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_RTC0_INT_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_RTC0_INT_CONFIG_PID_SHFT 4 -#define SH_RTC0_INT_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_RTC0_INT_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_RTC0_INT_CONFIG_BASE_SHFT 21 -#define SH_RTC0_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_RTC0_INT_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_RTC0_INT_CONFIG_IDX_SHFT 52 -#define SH_RTC0_INT_CONFIG_IDX_MASK 0x0ff0000000000000 +#define SH_EVENT_OCCURRED 0x0000000110010000UL +#define SH_EVENT_OCCURRED_ALIAS 0x0000000110010008UL /* ==================================================================== */ -/* Register "SH_RTC0_INT_ENABLE" */ -/* SHub RTC 0 Interrupt Enable Registers */ +/* Register "SH_PI_CAM_CONTROL" */ +/* CRB CAM MMR Access Control */ /* ==================================================================== */ - -#define SH_RTC0_INT_ENABLE 0x0000000110001400 -#define SH_RTC0_INT_ENABLE_MASK 0x0000000000000001 -#define SH_RTC0_INT_ENABLE_INIT 0x0000000000000000 - -/* SH_RTC0_INT_ENABLE_RTC0_ENABLE */ -/* Description: Enable RTC 0 Interrupt */ -#define SH_RTC0_INT_ENABLE_RTC0_ENABLE_SHFT 0 -#define SH_RTC0_INT_ENABLE_RTC0_ENABLE_MASK 0x0000000000000001 +#ifndef __ASSEMBLY__ +#define SH_PI_CAM_CONTROL 0x0000000120050300UL +#else +#define SH_PI_CAM_CONTROL 0x0000000120050300 +#endif /* ==================================================================== */ -/* Register "SH_RTC1_INT_CONFIG" */ -/* SHub RTC 1 Interrupt Config Registers */ +/* Register "SH_SHUB_ID" */ +/* SHub ID Number */ /* ==================================================================== */ - -#define SH_RTC1_INT_CONFIG 0x0000000110001480 -#define SH_RTC1_INT_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_RTC1_INT_CONFIG_INIT 0x0000000000000000 - -/* SH_RTC1_INT_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_RTC1_INT_CONFIG_TYPE_SHFT 0 -#define SH_RTC1_INT_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_RTC1_INT_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_RTC1_INT_CONFIG_AGT_SHFT 3 -#define SH_RTC1_INT_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_RTC1_INT_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_RTC1_INT_CONFIG_PID_SHFT 4 -#define SH_RTC1_INT_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_RTC1_INT_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_RTC1_INT_CONFIG_BASE_SHFT 21 -#define SH_RTC1_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_RTC1_INT_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_RTC1_INT_CONFIG_IDX_SHFT 52 -#define SH_RTC1_INT_CONFIG_IDX_MASK 0x0ff0000000000000 +#define SH_SHUB_ID 0x0000000110060580UL +#define SH_SHUB_ID_REVISION_SHFT 28 +#define SH_SHUB_ID_REVISION_MASK 0x00000000f0000000 /* ==================================================================== */ -/* Register "SH_RTC1_INT_ENABLE" */ -/* SHub RTC 1 Interrupt Enable Registers */ +/* Register "SH_PTC_0" */ +/* Puge Translation Cache Message Configuration Information */ /* ==================================================================== */ - -#define SH_RTC1_INT_ENABLE 0x0000000110001500 -#define SH_RTC1_INT_ENABLE_MASK 0x0000000000000001 -#define SH_RTC1_INT_ENABLE_INIT 0x0000000000000000 - -/* SH_RTC1_INT_ENABLE_RTC1_ENABLE */ -/* Description: Enable RTC 1 Interrupt */ -#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT 0 -#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK 0x0000000000000001 +#define SH_PTC_0 0x00000001101a0000UL +#define SH_PTC_1 0x00000001101a0080UL /* ==================================================================== */ -/* Register "SH_RTC2_INT_CONFIG" */ -/* SHub RTC 2 Interrupt Config Registers */ +/* Register "SH_RTC" */ +/* Real-time Clock */ /* ==================================================================== */ - -#define SH_RTC2_INT_CONFIG 0x0000000110001580 -#define SH_RTC2_INT_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_RTC2_INT_CONFIG_INIT 0x0000000000000000 - -/* SH_RTC2_INT_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_RTC2_INT_CONFIG_TYPE_SHFT 0 -#define SH_RTC2_INT_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_RTC2_INT_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_RTC2_INT_CONFIG_AGT_SHFT 3 -#define SH_RTC2_INT_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_RTC2_INT_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_RTC2_INT_CONFIG_PID_SHFT 4 -#define SH_RTC2_INT_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_RTC2_INT_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_RTC2_INT_CONFIG_BASE_SHFT 21 -#define SH_RTC2_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 - -/* SH_RTC2_INT_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_RTC2_INT_CONFIG_IDX_SHFT 52 -#define SH_RTC2_INT_CONFIG_IDX_MASK 0x0ff0000000000000 +#define SH_RTC 0x00000001101c0000UL +#define SH_RTC_MASK 0x007fffffffffffffUL /* ==================================================================== */ -/* Register "SH_RTC2_INT_ENABLE" */ -/* SHub RTC 2 Interrupt Enable Registers */ +/* Register "SH_MEMORY_WRITE_STATUS_0|1" */ +/* Memory Write Status for CPU 0 & 1 */ /* ==================================================================== */ - -#define SH_RTC2_INT_ENABLE 0x0000000110001600 -#define SH_RTC2_INT_ENABLE_MASK 0x0000000000000001 -#define SH_RTC2_INT_ENABLE_INIT 0x0000000000000000 - -/* SH_RTC2_INT_ENABLE_RTC2_ENABLE */ -/* Description: Enable RTC 2 Interrupt */ -#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT 0 -#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK 0x0000000000000001 +#define SH_MEMORY_WRITE_STATUS_0 0x0000000120070000UL +#define SH_MEMORY_WRITE_STATUS_1 0x0000000120070080UL /* ==================================================================== */ -/* Register "SH_RTC3_INT_CONFIG" */ -/* SHub RTC 3 Interrupt Config Registers */ +/* Register "SH_PIO_WRITE_STATUS_0|1" */ +/* PIO Write Status for CPU 0 & 1 */ /* ==================================================================== */ +#ifndef __ASSEMBLY__ +#define SH_PIO_WRITE_STATUS_0 0x0000000120070200UL +#define SH_PIO_WRITE_STATUS_1 0x0000000120070280UL -#define SH_RTC3_INT_CONFIG 0x0000000110001680 -#define SH_RTC3_INT_CONFIG_MASK 0x0ff3ffffffefffff -#define SH_RTC3_INT_CONFIG_INIT 0x0000000000000000 - -/* SH_RTC3_INT_CONFIG_TYPE */ -/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ -#define SH_RTC3_INT_CONFIG_TYPE_SHFT 0 -#define SH_RTC3_INT_CONFIG_TYPE_MASK 0x0000000000000007 - -/* SH_RTC3_INT_CONFIG_AGT */ -/* Description: Agent, must be 0 for SHub */ -#define SH_RTC3_INT_CONFIG_AGT_SHFT 3 -#define SH_RTC3_INT_CONFIG_AGT_MASK 0x0000000000000008 - -/* SH_RTC3_INT_CONFIG_PID */ -/* Description: Processor ID, same setting as on targeted McKinley */ -#define SH_RTC3_INT_CONFIG_PID_SHFT 4 -#define SH_RTC3_INT_CONFIG_PID_MASK 0x00000000000ffff0 - -/* SH_RTC3_INT_CONFIG_BASE */ -/* Description: Optional interrupt vector area, 2MB aligned */ -#define SH_RTC3_INT_CONFIG_BASE_SHFT 21 -#define SH_RTC3_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 +/* SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK */ +/* Description: Deadlock response detected */ +#define SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK_SHFT 1 +#define SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK_MASK 0x0000000000000002 -/* SH_RTC3_INT_CONFIG_IDX */ -/* Description: Targeted McKinley interrupt vector */ -#define SH_RTC3_INT_CONFIG_IDX_SHFT 52 -#define SH_RTC3_INT_CONFIG_IDX_MASK 0x0ff0000000000000 +/* SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT */ +/* Description: Count of currently pending PIO writes */ +#define SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_SHFT 56 +#define SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_MASK 0x3f00000000000000UL +#else +#define SH_PIO_WRITE_STATUS_0 0x0000000120070200 +#define SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_SHFT 56 +#define SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK_SHFT 1 +#endif /* ==================================================================== */ -/* Register "SH_RTC3_INT_ENABLE" */ -/* SHub RTC 3 Interrupt Enable Registers */ +/* Register "SH_PIO_WRITE_STATUS_0_ALIAS" */ /* ==================================================================== */ - -#define SH_RTC3_INT_ENABLE 0x0000000110001700 -#define SH_RTC3_INT_ENABLE_MASK 0x0000000000000001 -#define SH_RTC3_INT_ENABLE_INIT 0x0000000000000000 - -/* SH_RTC3_INT_ENABLE_RTC3_ENABLE */ -/* Description: Enable RTC 3 Interrupt */ -#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT 0 -#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK 0x0000000000000001 +#ifndef __ASSEMBLY__ +#define SH_PIO_WRITE_STATUS_0_ALIAS 0x0000000120070208UL +#else +#define SH_PIO_WRITE_STATUS_0_ALIAS 0x0000000120070208 +#endif /* ==================================================================== */ /* Register "SH_EVENT_OCCURRED" */ /* SHub Interrupt Event Occurred */ /* ==================================================================== */ - -#define SH_EVENT_OCCURRED 0x0000000110010000 -#define SH_EVENT_OCCURRED_MASK 0x000000007fffffff -#define SH_EVENT_OCCURRED_INIT 0x0000000000000000 - -/* SH_EVENT_OCCURRED_PI_HW_INT */ -/* Description: Pending PI Hardware interrupt */ -#define SH_EVENT_OCCURRED_PI_HW_INT_SHFT 0 -#define SH_EVENT_OCCURRED_PI_HW_INT_MASK 0x0000000000000001 - -/* SH_EVENT_OCCURRED_MD_HW_INT */ -/* Description: Pending MD Hardware interrupt */ -#define SH_EVENT_OCCURRED_MD_HW_INT_SHFT 1 -#define SH_EVENT_OCCURRED_MD_HW_INT_MASK 0x0000000000000002 - -/* SH_EVENT_OCCURRED_XN_HW_INT */ -/* Description: Pending XN Hardware interrupt */ -#define SH_EVENT_OCCURRED_XN_HW_INT_SHFT 2 -#define SH_EVENT_OCCURRED_XN_HW_INT_MASK 0x0000000000000004 - -/* SH_EVENT_OCCURRED_LB_HW_INT */ -/* Description: Pending LB Hardware interrupt */ -#define SH_EVENT_OCCURRED_LB_HW_INT_SHFT 3 -#define SH_EVENT_OCCURRED_LB_HW_INT_MASK 0x0000000000000008 - -/* SH_EVENT_OCCURRED_II_HW_INT */ -/* Description: Pending II wrapper Hardware interrupt */ -#define SH_EVENT_OCCURRED_II_HW_INT_SHFT 4 -#define SH_EVENT_OCCURRED_II_HW_INT_MASK 0x0000000000000010 - -/* SH_EVENT_OCCURRED_PI_CE_INT */ -/* Description: Pending PI Correctable Error Interrupt */ -#define SH_EVENT_OCCURRED_PI_CE_INT_SHFT 5 -#define SH_EVENT_OCCURRED_PI_CE_INT_MASK 0x0000000000000020 - -/* SH_EVENT_OCCURRED_MD_CE_INT */ -/* Description: Pending MD Correctable Error Interrupt */ -#define SH_EVENT_OCCURRED_MD_CE_INT_SHFT 6 -#define SH_EVENT_OCCURRED_MD_CE_INT_MASK 0x0000000000000040 - -/* SH_EVENT_OCCURRED_XN_CE_INT */ -/* Description: Pending XN Correctable Error Interrupt */ -#define SH_EVENT_OCCURRED_XN_CE_INT_SHFT 7 -#define SH_EVENT_OCCURRED_XN_CE_INT_MASK 0x0000000000000080 - -/* SH_EVENT_OCCURRED_PI_UCE_INT */ -/* Description: Pending PI Correctable Error Interrupt */ -#define SH_EVENT_OCCURRED_PI_UCE_INT_SHFT 8 -#define SH_EVENT_OCCURRED_PI_UCE_INT_MASK 0x0000000000000100 - -/* SH_EVENT_OCCURRED_MD_UCE_INT */ -/* Description: Pending MD Correctable Error Interrupt */ -#define SH_EVENT_OCCURRED_MD_UCE_INT_SHFT 9 -#define SH_EVENT_OCCURRED_MD_UCE_INT_MASK 0x0000000000000200 - -/* SH_EVENT_OCCURRED_XN_UCE_INT */ -/* Description: Pending XN Correctable Error Interrupt */ -#define SH_EVENT_OCCURRED_XN_UCE_INT_SHFT 10 -#define SH_EVENT_OCCURRED_XN_UCE_INT_MASK 0x0000000000000400 - -/* SH_EVENT_OCCURRED_PROC0_ADV_INT */ -/* Description: Pending Processor 0 Advisory Interrupt */ -#define SH_EVENT_OCCURRED_PROC0_ADV_INT_SHFT 11 -#define SH_EVENT_OCCURRED_PROC0_ADV_INT_MASK 0x0000000000000800 - -/* SH_EVENT_OCCURRED_PROC1_ADV_INT */ -/* Description: Pending Processor 1 Advisory Interrupt */ -#define SH_EVENT_OCCURRED_PROC1_ADV_INT_SHFT 12 -#define SH_EVENT_OCCURRED_PROC1_ADV_INT_MASK 0x0000000000001000 - -/* SH_EVENT_OCCURRED_PROC2_ADV_INT */ -/* Description: Pending Processor 2 Advisory Interrupt */ -#define SH_EVENT_OCCURRED_PROC2_ADV_INT_SHFT 13 -#define SH_EVENT_OCCURRED_PROC2_ADV_INT_MASK 0x0000000000002000 - -/* SH_EVENT_OCCURRED_PROC3_ADV_INT */ -/* Description: Pending Processor 3 Advisory Interrupt */ -#define SH_EVENT_OCCURRED_PROC3_ADV_INT_SHFT 14 -#define SH_EVENT_OCCURRED_PROC3_ADV_INT_MASK 0x0000000000004000 - -/* SH_EVENT_OCCURRED_PROC0_ERR_INT */ -/* Description: Pending Processor 0 Error Interrupt */ -#define SH_EVENT_OCCURRED_PROC0_ERR_INT_SHFT 15 -#define SH_EVENT_OCCURRED_PROC0_ERR_INT_MASK 0x0000000000008000 - -/* SH_EVENT_OCCURRED_PROC1_ERR_INT */ -/* Description: Pending Processor 1 Error Interrupt */ -#define SH_EVENT_OCCURRED_PROC1_ERR_INT_SHFT 16 -#define SH_EVENT_OCCURRED_PROC1_ERR_INT_MASK 0x0000000000010000 - -/* SH_EVENT_OCCURRED_PROC2_ERR_INT */ -/* Description: Pending Processor 2 Error Interrupt */ -#define SH_EVENT_OCCURRED_PROC2_ERR_INT_SHFT 17 -#define SH_EVENT_OCCURRED_PROC2_ERR_INT_MASK 0x0000000000020000 - -/* SH_EVENT_OCCURRED_PROC3_ERR_INT */ -/* Description: Pending Processor 3 Error Interrupt */ -#define SH_EVENT_OCCURRED_PROC3_ERR_INT_SHFT 18 -#define SH_EVENT_OCCURRED_PROC3_ERR_INT_MASK 0x0000000000040000 - -/* SH_EVENT_OCCURRED_SYSTEM_SHUTDOWN_INT */ -/* Description: Pending System Shutdown Interrupt */ -#define SH_EVENT_OCCURRED_SYSTEM_SHUTDOWN_INT_SHFT 19 -#define SH_EVENT_OCCURRED_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000080000 - /* SH_EVENT_OCCURRED_UART_INT */ /* Description: Pending Junk Bus UART Interrupt */ #define SH_EVENT_OCCURRED_UART_INT_SHFT 20 #define SH_EVENT_OCCURRED_UART_INT_MASK 0x0000000000100000 -/* SH_EVENT_OCCURRED_L1_NMI_INT */ -/* Description: Pending L1 Controller NMI Interrupt */ -#define SH_EVENT_OCCURRED_L1_NMI_INT_SHFT 21 -#define SH_EVENT_OCCURRED_L1_NMI_INT_MASK 0x0000000000200000 - -/* SH_EVENT_OCCURRED_STOP_CLOCK */ -/* Description: Pending Stop Clock Interrupt */ -#define SH_EVENT_OCCURRED_STOP_CLOCK_SHFT 22 -#define SH_EVENT_OCCURRED_STOP_CLOCK_MASK 0x0000000000400000 - -/* SH_EVENT_OCCURRED_RTC0_INT */ -/* Description: Pending RTC 0 Interrupt */ -#define SH_EVENT_OCCURRED_RTC0_INT_SHFT 23 -#define SH_EVENT_OCCURRED_RTC0_INT_MASK 0x0000000000800000 - -/* SH_EVENT_OCCURRED_RTC1_INT */ -/* Description: Pending RTC 1 Interrupt */ -#define SH_EVENT_OCCURRED_RTC1_INT_SHFT 24 -#define SH_EVENT_OCCURRED_RTC1_INT_MASK 0x0000000001000000 - -/* SH_EVENT_OCCURRED_RTC2_INT */ -/* Description: Pending RTC 2 Interrupt */ -#define SH_EVENT_OCCURRED_RTC2_INT_SHFT 25 -#define SH_EVENT_OCCURRED_RTC2_INT_MASK 0x0000000002000000 - -/* SH_EVENT_OCCURRED_RTC3_INT */ -/* Description: Pending RTC 3 Interrupt */ -#define SH_EVENT_OCCURRED_RTC3_INT_SHFT 26 -#define SH_EVENT_OCCURRED_RTC3_INT_MASK 0x0000000004000000 - -/* SH_EVENT_OCCURRED_PROFILE_INT */ -/* Description: Pending Profile Interrupt */ -#define SH_EVENT_OCCURRED_PROFILE_INT_SHFT 27 -#define SH_EVENT_OCCURRED_PROFILE_INT_MASK 0x0000000008000000 - /* SH_EVENT_OCCURRED_IPI_INT */ /* Description: Pending IPI Interrupt */ #define SH_EVENT_OCCURRED_IPI_INT_SHFT 28 @@ -2147,23468 +151,10 @@ #define SH_EVENT_OCCURRED_II_INT1_MASK 0x0000000040000000 /* ==================================================================== */ -/* Register "SH_EVENT_OCCURRED_ALIAS" */ -/* SHub Interrupt Event Occurred Alias */ -/* ==================================================================== */ - -#define SH_EVENT_OCCURRED_ALIAS 0x0000000110010008 - -/* ==================================================================== */ -/* Register "SH_EVENT_OVERFLOW" */ -/* SHub Interrupt Event Occurred Overflow */ -/* ==================================================================== */ - -#define SH_EVENT_OVERFLOW 0x0000000110010080 -#define SH_EVENT_OVERFLOW_MASK 0x000000000fffffff -#define SH_EVENT_OVERFLOW_INIT 0x0000000000000000 - -/* SH_EVENT_OVERFLOW_PI_HW_INT */ -/* Description: Pending PI Hardware interrupt */ -#define SH_EVENT_OVERFLOW_PI_HW_INT_SHFT 0 -#define SH_EVENT_OVERFLOW_PI_HW_INT_MASK 0x0000000000000001 - -/* SH_EVENT_OVERFLOW_MD_HW_INT */ -/* Description: Pending MD Hardware interrupt */ -#define SH_EVENT_OVERFLOW_MD_HW_INT_SHFT 1 -#define SH_EVENT_OVERFLOW_MD_HW_INT_MASK 0x0000000000000002 - -/* SH_EVENT_OVERFLOW_XN_HW_INT */ -/* Description: Pending XN Hardware interrupt */ -#define SH_EVENT_OVERFLOW_XN_HW_INT_SHFT 2 -#define SH_EVENT_OVERFLOW_XN_HW_INT_MASK 0x0000000000000004 - -/* SH_EVENT_OVERFLOW_LB_HW_INT */ -/* Description: Pending LB Hardware interrupt */ -#define SH_EVENT_OVERFLOW_LB_HW_INT_SHFT 3 -#define SH_EVENT_OVERFLOW_LB_HW_INT_MASK 0x0000000000000008 - -/* SH_EVENT_OVERFLOW_II_HW_INT */ -/* Description: Pending II wrapper Hardware interrupt */ -#define SH_EVENT_OVERFLOW_II_HW_INT_SHFT 4 -#define SH_EVENT_OVERFLOW_II_HW_INT_MASK 0x0000000000000010 - -/* SH_EVENT_OVERFLOW_PI_CE_INT */ -/* Description: Pending PI Correctable Error Interrupt */ -#define SH_EVENT_OVERFLOW_PI_CE_INT_SHFT 5 -#define SH_EVENT_OVERFLOW_PI_CE_INT_MASK 0x0000000000000020 - -/* SH_EVENT_OVERFLOW_MD_CE_INT */ -/* Description: Pending MD Correctable Error Interrupt */ -#define SH_EVENT_OVERFLOW_MD_CE_INT_SHFT 6 -#define SH_EVENT_OVERFLOW_MD_CE_INT_MASK 0x0000000000000040 - -/* SH_EVENT_OVERFLOW_XN_CE_INT */ -/* Description: Pending XN Correctable Error Interrupt */ -#define SH_EVENT_OVERFLOW_XN_CE_INT_SHFT 7 -#define SH_EVENT_OVERFLOW_XN_CE_INT_MASK 0x0000000000000080 - -/* SH_EVENT_OVERFLOW_PI_UCE_INT */ -/* Description: Pending PI Correctable Error Interrupt */ -#define SH_EVENT_OVERFLOW_PI_UCE_INT_SHFT 8 -#define SH_EVENT_OVERFLOW_PI_UCE_INT_MASK 0x0000000000000100 - -/* SH_EVENT_OVERFLOW_MD_UCE_INT */ -/* Description: Pending MD Correctable Error Interrupt */ -#define SH_EVENT_OVERFLOW_MD_UCE_INT_SHFT 9 -#define SH_EVENT_OVERFLOW_MD_UCE_INT_MASK 0x0000000000000200 - -/* SH_EVENT_OVERFLOW_XN_UCE_INT */ -/* Description: Pending XN Correctable Error Interrupt */ -#define SH_EVENT_OVERFLOW_XN_UCE_INT_SHFT 10 -#define SH_EVENT_OVERFLOW_XN_UCE_INT_MASK 0x0000000000000400 - -/* SH_EVENT_OVERFLOW_PROC0_ADV_INT */ -/* Description: Pending Processor 0 Advisory Interrupt */ -#define SH_EVENT_OVERFLOW_PROC0_ADV_INT_SHFT 11 -#define SH_EVENT_OVERFLOW_PROC0_ADV_INT_MASK 0x0000000000000800 - -/* SH_EVENT_OVERFLOW_PROC1_ADV_INT */ -/* Description: Pending Processor 1 Advisory Interrupt */ -#define SH_EVENT_OVERFLOW_PROC1_ADV_INT_SHFT 12 -#define SH_EVENT_OVERFLOW_PROC1_ADV_INT_MASK 0x0000000000001000 - -/* SH_EVENT_OVERFLOW_PROC2_ADV_INT */ -/* Description: Pending Processor 2 Advisory Interrupt */ -#define SH_EVENT_OVERFLOW_PROC2_ADV_INT_SHFT 13 -#define SH_EVENT_OVERFLOW_PROC2_ADV_INT_MASK 0x0000000000002000 - -/* SH_EVENT_OVERFLOW_PROC3_ADV_INT */ -/* Description: Pending Processor 3 Advisory Interrupt */ -#define SH_EVENT_OVERFLOW_PROC3_ADV_INT_SHFT 14 -#define SH_EVENT_OVERFLOW_PROC3_ADV_INT_MASK 0x0000000000004000 - -/* SH_EVENT_OVERFLOW_PROC0_ERR_INT */ -/* Description: Pending Processor 0 Error Interrupt */ -#define SH_EVENT_OVERFLOW_PROC0_ERR_INT_SHFT 15 -#define SH_EVENT_OVERFLOW_PROC0_ERR_INT_MASK 0x0000000000008000 - -/* SH_EVENT_OVERFLOW_PROC1_ERR_INT */ -/* Description: Pending Processor 1 Error Interrupt */ -#define SH_EVENT_OVERFLOW_PROC1_ERR_INT_SHFT 16 -#define SH_EVENT_OVERFLOW_PROC1_ERR_INT_MASK 0x0000000000010000 - -/* SH_EVENT_OVERFLOW_PROC2_ERR_INT */ -/* Description: Pending Processor 2 Error Interrupt */ -#define SH_EVENT_OVERFLOW_PROC2_ERR_INT_SHFT 17 -#define SH_EVENT_OVERFLOW_PROC2_ERR_INT_MASK 0x0000000000020000 - -/* SH_EVENT_OVERFLOW_PROC3_ERR_INT */ -/* Description: Pending Processor 3 Error Interrupt */ -#define SH_EVENT_OVERFLOW_PROC3_ERR_INT_SHFT 18 -#define SH_EVENT_OVERFLOW_PROC3_ERR_INT_MASK 0x0000000000040000 - -/* SH_EVENT_OVERFLOW_SYSTEM_SHUTDOWN_INT */ -/* Description: Pending System Shutdown Interrupt */ -#define SH_EVENT_OVERFLOW_SYSTEM_SHUTDOWN_INT_SHFT 19 -#define SH_EVENT_OVERFLOW_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000080000 - -/* SH_EVENT_OVERFLOW_UART_INT */ -/* Description: Pending Junk Bus UART Interrupt */ -#define SH_EVENT_OVERFLOW_UART_INT_SHFT 20 -#define SH_EVENT_OVERFLOW_UART_INT_MASK 0x0000000000100000 - -/* SH_EVENT_OVERFLOW_L1_NMI_INT */ -/* Description: Pending L1 Controller NMI Interrupt */ -#define SH_EVENT_OVERFLOW_L1_NMI_INT_SHFT 21 -#define SH_EVENT_OVERFLOW_L1_NMI_INT_MASK 0x0000000000200000 - -/* SH_EVENT_OVERFLOW_STOP_CLOCK */ -/* Description: Pending Stop Clock Interrupt */ -#define SH_EVENT_OVERFLOW_STOP_CLOCK_SHFT 22 -#define SH_EVENT_OVERFLOW_STOP_CLOCK_MASK 0x0000000000400000 - -/* SH_EVENT_OVERFLOW_RTC0_INT */ -/* Description: Pending RTC 0 Interrupt */ -#define SH_EVENT_OVERFLOW_RTC0_INT_SHFT 23 -#define SH_EVENT_OVERFLOW_RTC0_INT_MASK 0x0000000000800000 - -/* SH_EVENT_OVERFLOW_RTC1_INT */ -/* Description: Pending RTC 1 Interrupt */ -#define SH_EVENT_OVERFLOW_RTC1_INT_SHFT 24 -#define SH_EVENT_OVERFLOW_RTC1_INT_MASK 0x0000000001000000 - -/* SH_EVENT_OVERFLOW_RTC2_INT */ -/* Description: Pending RTC 2 Interrupt */ -#define SH_EVENT_OVERFLOW_RTC2_INT_SHFT 25 -#define SH_EVENT_OVERFLOW_RTC2_INT_MASK 0x0000000002000000 - -/* SH_EVENT_OVERFLOW_RTC3_INT */ -/* Description: Pending RTC 3 Interrupt */ -#define SH_EVENT_OVERFLOW_RTC3_INT_SHFT 26 -#define SH_EVENT_OVERFLOW_RTC3_INT_MASK 0x0000000004000000 - -/* SH_EVENT_OVERFLOW_PROFILE_INT */ -/* Description: Pending Profile Interrupt */ -#define SH_EVENT_OVERFLOW_PROFILE_INT_SHFT 27 -#define SH_EVENT_OVERFLOW_PROFILE_INT_MASK 0x0000000008000000 - -/* ==================================================================== */ -/* Register "SH_EVENT_OVERFLOW_ALIAS" */ -/* SHub Interrupt Event Occurred Overflow Alias */ -/* ==================================================================== */ - -#define SH_EVENT_OVERFLOW_ALIAS 0x0000000110010088 - -/* ==================================================================== */ -/* Register "SH_JUNK_BUS_TIME" */ -/* Junk Bus Timing */ -/* ==================================================================== */ - -#define SH_JUNK_BUS_TIME 0x0000000110020000 -#define SH_JUNK_BUS_TIME_MASK 0x00000000ffffffff -#define SH_JUNK_BUS_TIME_INIT 0x0000000040404040 - -/* SH_JUNK_BUS_TIME_FPROM_SETUP_HOLD */ -/* Description: Fprom_Setup_Hold */ -#define SH_JUNK_BUS_TIME_FPROM_SETUP_HOLD_SHFT 0 -#define SH_JUNK_BUS_TIME_FPROM_SETUP_HOLD_MASK 0x00000000000000ff - -/* SH_JUNK_BUS_TIME_FPROM_ENABLE */ -/* Description: Fprom_Enable */ -#define SH_JUNK_BUS_TIME_FPROM_ENABLE_SHFT 8 -#define SH_JUNK_BUS_TIME_FPROM_ENABLE_MASK 0x000000000000ff00 - -/* SH_JUNK_BUS_TIME_UART_SETUP_HOLD */ -/* Description: Uart_Setup_Hold */ -#define SH_JUNK_BUS_TIME_UART_SETUP_HOLD_SHFT 16 -#define SH_JUNK_BUS_TIME_UART_SETUP_HOLD_MASK 0x0000000000ff0000 - -/* SH_JUNK_BUS_TIME_UART_ENABLE */ -/* Description: Uart_Enable */ -#define SH_JUNK_BUS_TIME_UART_ENABLE_SHFT 24 -#define SH_JUNK_BUS_TIME_UART_ENABLE_MASK 0x00000000ff000000 - -/* ==================================================================== */ -/* Register "SH_JUNK_LATCH_TIME" */ -/* Junk Bus Latch Timing */ -/* ==================================================================== */ - -#define SH_JUNK_LATCH_TIME 0x0000000110020080 -#define SH_JUNK_LATCH_TIME_MASK 0x0000000000000007 -#define SH_JUNK_LATCH_TIME_INIT 0x0000000000000002 - -/* SH_JUNK_LATCH_TIME_SETUP_HOLD */ -/* Description: Setup and Hold Time */ -#define SH_JUNK_LATCH_TIME_SETUP_HOLD_SHFT 0 -#define SH_JUNK_LATCH_TIME_SETUP_HOLD_MASK 0x0000000000000007 - -/* ==================================================================== */ -/* Register "SH_JUNK_NACK_RESET" */ -/* Junk Bus Nack Counter Reset */ -/* ==================================================================== */ - -#define SH_JUNK_NACK_RESET 0x0000000110020100 -#define SH_JUNK_NACK_RESET_MASK 0x0000000000000001 -#define SH_JUNK_NACK_RESET_INIT 0x0000000000000000 - -/* SH_JUNK_NACK_RESET_PULSE */ -/* Description: Junk bus nack counter reset */ -#define SH_JUNK_NACK_RESET_PULSE_SHFT 0 -#define SH_JUNK_NACK_RESET_PULSE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_JUNK_BUS_LED0" */ -/* Junk Bus LED0 */ -/* ==================================================================== */ - -#define SH_JUNK_BUS_LED0 0x0000000110030000 -#define SH_JUNK_BUS_LED0_MASK 0x00000000000000ff -#define SH_JUNK_BUS_LED0_INIT 0x0000000000000000 - -/* SH_JUNK_BUS_LED0_LED0_DATA */ -/* Description: LED0_data */ -#define SH_JUNK_BUS_LED0_LED0_DATA_SHFT 0 -#define SH_JUNK_BUS_LED0_LED0_DATA_MASK 0x00000000000000ff - -/* ==================================================================== */ -/* Register "SH_JUNK_BUS_LED1" */ -/* Junk Bus LED1 */ -/* ==================================================================== */ - -#define SH_JUNK_BUS_LED1 0x0000000110030080 -#define SH_JUNK_BUS_LED1_MASK 0x00000000000000ff -#define SH_JUNK_BUS_LED1_INIT 0x0000000000000000 - -/* SH_JUNK_BUS_LED1_LED1_DATA */ -/* Description: LED1_data */ -#define SH_JUNK_BUS_LED1_LED1_DATA_SHFT 0 -#define SH_JUNK_BUS_LED1_LED1_DATA_MASK 0x00000000000000ff - -/* ==================================================================== */ -/* Register "SH_JUNK_BUS_LED2" */ -/* Junk Bus LED2 */ -/* ==================================================================== */ - -#define SH_JUNK_BUS_LED2 0x0000000110030100 -#define SH_JUNK_BUS_LED2_MASK 0x00000000000000ff -#define SH_JUNK_BUS_LED2_INIT 0x0000000000000000 - -/* SH_JUNK_BUS_LED2_LED2_DATA */ -/* Description: LED2_data */ -#define SH_JUNK_BUS_LED2_LED2_DATA_SHFT 0 -#define SH_JUNK_BUS_LED2_LED2_DATA_MASK 0x00000000000000ff - -/* ==================================================================== */ -/* Register "SH_JUNK_BUS_LED3" */ -/* Junk Bus LED3 */ -/* ==================================================================== */ - -#define SH_JUNK_BUS_LED3 0x0000000110030180 -#define SH_JUNK_BUS_LED3_MASK 0x00000000000000ff -#define SH_JUNK_BUS_LED3_INIT 0x0000000000000000 - -/* SH_JUNK_BUS_LED3_LED3_DATA */ -/* Description: LED3_data */ -#define SH_JUNK_BUS_LED3_LED3_DATA_SHFT 0 -#define SH_JUNK_BUS_LED3_LED3_DATA_MASK 0x00000000000000ff - -/* ==================================================================== */ -/* Register "SH_JUNK_ERROR_STATUS" */ -/* Junk Bus Error Status */ -/* ==================================================================== */ - -#define SH_JUNK_ERROR_STATUS 0x0000000110030200 -#define SH_JUNK_ERROR_STATUS_MASK 0x1fff7fffffffffff -#define SH_JUNK_ERROR_STATUS_INIT 0x0000000000000000 - -/* SH_JUNK_ERROR_STATUS_ADDRESS */ -/* Description: Failing junk bus address */ -#define SH_JUNK_ERROR_STATUS_ADDRESS_SHFT 0 -#define SH_JUNK_ERROR_STATUS_ADDRESS_MASK 0x00007fffffffffff - -/* SH_JUNK_ERROR_STATUS_CMD */ -/* Description: Junk bus command */ -#define SH_JUNK_ERROR_STATUS_CMD_SHFT 48 -#define SH_JUNK_ERROR_STATUS_CMD_MASK 0x00ff000000000000 - -/* SH_JUNK_ERROR_STATUS_MODE */ -/* Description: Mode */ -#define SH_JUNK_ERROR_STATUS_MODE_SHFT 56 -#define SH_JUNK_ERROR_STATUS_MODE_MASK 0x0100000000000000 - -/* SH_JUNK_ERROR_STATUS_STATUS */ -/* Description: Status */ -#define SH_JUNK_ERROR_STATUS_STATUS_SHFT 57 -#define SH_JUNK_ERROR_STATUS_STATUS_MASK 0x1e00000000000000 - -/* ==================================================================== */ -/* Register "SH_NI0_LLP_STAT" */ -/* This register describes the LLP status. */ -/* ==================================================================== */ - -#define SH_NI0_LLP_STAT 0x0000000150000000 -#define SH_NI0_LLP_STAT_MASK 0x000000000000000f -#define SH_NI0_LLP_STAT_INIT 0x0000000000000000 - -/* SH_NI0_LLP_STAT_LINK_RESET_STATE */ -/* Description: Status of LLP link. */ -#define SH_NI0_LLP_STAT_LINK_RESET_STATE_SHFT 0 -#define SH_NI0_LLP_STAT_LINK_RESET_STATE_MASK 0x000000000000000f - -/* ==================================================================== */ -/* Register "SH_NI0_LLP_RESET" */ -/* Writing issues a reset to the network interface */ -/* ==================================================================== */ - -#define SH_NI0_LLP_RESET 0x0000000150000008 -#define SH_NI0_LLP_RESET_MASK 0x0000000000000003 -#define SH_NI0_LLP_RESET_INIT 0x0000000000000000 - -/* SH_NI0_LLP_RESET_LINK */ -/* Description: Send Link Reset. Generates a pulse. */ -#define SH_NI0_LLP_RESET_LINK_SHFT 0 -#define SH_NI0_LLP_RESET_LINK_MASK 0x0000000000000001 - -/* SH_NI0_LLP_RESET_WARM */ -/* Description: Send Warm Reset. Generates a pulse. */ -#define SH_NI0_LLP_RESET_WARM_SHFT 1 -#define SH_NI0_LLP_RESET_WARM_MASK 0x0000000000000002 - -/* ==================================================================== */ -/* Register "SH_NI0_LLP_RESET_EN" */ -/* Controls LLP warm reset propagation */ -/* ==================================================================== */ - -#define SH_NI0_LLP_RESET_EN 0x0000000150000010 -#define SH_NI0_LLP_RESET_EN_MASK 0x0000000000000001 -#define SH_NI0_LLP_RESET_EN_INIT 0x0000000000000001 - -/* SH_NI0_LLP_RESET_EN_OK */ -/* Description: Allow LLP warm reset to reset SHUB */ -#define SH_NI0_LLP_RESET_EN_OK_SHFT 0 -#define SH_NI0_LLP_RESET_EN_OK_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_NI0_LLP_CHAN_MODE" */ -/* Sets the signaling mode of LLP and channel */ -/* ==================================================================== */ - -#define SH_NI0_LLP_CHAN_MODE 0x0000000150000018 -#define SH_NI0_LLP_CHAN_MODE_MASK 0x000000000000001f -#define SH_NI0_LLP_CHAN_MODE_INIT 0x0000000000000000 - -/* SH_NI0_LLP_CHAN_MODE_BITMODE32 */ -/* Description: Enables 32-bit (plus sideband) channel phits */ -#define SH_NI0_LLP_CHAN_MODE_BITMODE32_SHFT 0 -#define SH_NI0_LLP_CHAN_MODE_BITMODE32_MASK 0x0000000000000001 - -/* SH_NI0_LLP_CHAN_MODE_AC_ENCODE */ -/* Description: Enables nearly dc-free encoding for AC-coupling */ -#define SH_NI0_LLP_CHAN_MODE_AC_ENCODE_SHFT 1 -#define SH_NI0_LLP_CHAN_MODE_AC_ENCODE_MASK 0x0000000000000002 - -/* SH_NI0_LLP_CHAN_MODE_ENABLE_TUNING */ -/* Description: Enables automatic tuning of channel skew. */ -#define SH_NI0_LLP_CHAN_MODE_ENABLE_TUNING_SHFT 2 -#define SH_NI0_LLP_CHAN_MODE_ENABLE_TUNING_MASK 0x0000000000000004 - -/* SH_NI0_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD */ -/* Description: Enables remote fine tune updates */ -#define SH_NI0_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD_SHFT 3 -#define SH_NI0_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD_MASK 0x0000000000000008 - -/* SH_NI0_LLP_CHAN_MODE_ENABLE_CLKQUAD */ -/* Description: Enables quadrature clock in the pfssd */ -#define SH_NI0_LLP_CHAN_MODE_ENABLE_CLKQUAD_SHFT 4 -#define SH_NI0_LLP_CHAN_MODE_ENABLE_CLKQUAD_MASK 0x0000000000000010 - -/* ==================================================================== */ -/* Register "SH_NI0_LLP_CONFIG" */ -/* Sets the configuration of LLP and channel */ -/* ==================================================================== */ - -#define SH_NI0_LLP_CONFIG 0x0000000150000020 -#define SH_NI0_LLP_CONFIG_MASK 0x0000003fffffffff -#define SH_NI0_LLP_CONFIG_INIT 0x00000007fc6ffd00 - -/* SH_NI0_LLP_CONFIG_MAXBURST */ -#define SH_NI0_LLP_CONFIG_MAXBURST_SHFT 0 -#define SH_NI0_LLP_CONFIG_MAXBURST_MASK 0x00000000000003ff - -/* SH_NI0_LLP_CONFIG_MAXRETRY */ -#define SH_NI0_LLP_CONFIG_MAXRETRY_SHFT 10 -#define SH_NI0_LLP_CONFIG_MAXRETRY_MASK 0x00000000000ffc00 - -/* SH_NI0_LLP_CONFIG_NULLTIMEOUT */ -#define SH_NI0_LLP_CONFIG_NULLTIMEOUT_SHFT 20 -#define SH_NI0_LLP_CONFIG_NULLTIMEOUT_MASK 0x0000000003f00000 - -/* SH_NI0_LLP_CONFIG_FTU_TIME */ -#define SH_NI0_LLP_CONFIG_FTU_TIME_SHFT 26 -#define SH_NI0_LLP_CONFIG_FTU_TIME_MASK 0x0000003ffc000000 - -/* ==================================================================== */ -/* Register "SH_NI0_LLP_TEST_CTL" */ -/* ==================================================================== */ - -#define SH_NI0_LLP_TEST_CTL 0x0000000150000028 -#define SH_NI0_LLP_TEST_CTL_MASK 0x7ff3f3ffffffffff -#define SH_NI0_LLP_TEST_CTL_INIT 0x000000000a5fffff - -/* SH_NI0_LLP_TEST_CTL_PATTERN */ -/* Description: Send channel data pattern */ -#define SH_NI0_LLP_TEST_CTL_PATTERN_SHFT 0 -#define SH_NI0_LLP_TEST_CTL_PATTERN_MASK 0x000000ffffffffff - -/* SH_NI0_LLP_TEST_CTL_SEND_TEST_MODE */ -/* Description: Enables continuous send of data */ -#define SH_NI0_LLP_TEST_CTL_SEND_TEST_MODE_SHFT 40 -#define SH_NI0_LLP_TEST_CTL_SEND_TEST_MODE_MASK 0x0000030000000000 - -/* SH_NI0_LLP_TEST_CTL_WIRE_SEL */ -#define SH_NI0_LLP_TEST_CTL_WIRE_SEL_SHFT 44 -#define SH_NI0_LLP_TEST_CTL_WIRE_SEL_MASK 0x0003f00000000000 - -/* SH_NI0_LLP_TEST_CTL_LFSR_MODE */ -#define SH_NI0_LLP_TEST_CTL_LFSR_MODE_SHFT 52 -#define SH_NI0_LLP_TEST_CTL_LFSR_MODE_MASK 0x0030000000000000 - -/* SH_NI0_LLP_TEST_CTL_NOISE_MODE */ -#define SH_NI0_LLP_TEST_CTL_NOISE_MODE_SHFT 54 -#define SH_NI0_LLP_TEST_CTL_NOISE_MODE_MASK 0x00c0000000000000 - -/* SH_NI0_LLP_TEST_CTL_ARMCAPTURE */ -/* Description: Enable Capture of Next MicroPacket */ -#define SH_NI0_LLP_TEST_CTL_ARMCAPTURE_SHFT 56 -#define SH_NI0_LLP_TEST_CTL_ARMCAPTURE_MASK 0x0100000000000000 - -/* SH_NI0_LLP_TEST_CTL_CAPTURECBONLY */ -/* Description: Only capture a micropacket with a Check Byte error */ -#define SH_NI0_LLP_TEST_CTL_CAPTURECBONLY_SHFT 57 -#define SH_NI0_LLP_TEST_CTL_CAPTURECBONLY_MASK 0x0200000000000000 - -/* SH_NI0_LLP_TEST_CTL_SENDCBERROR */ -/* Description: Sends a single error */ -#define SH_NI0_LLP_TEST_CTL_SENDCBERROR_SHFT 58 -#define SH_NI0_LLP_TEST_CTL_SENDCBERROR_MASK 0x0400000000000000 - -/* SH_NI0_LLP_TEST_CTL_SENDSNERROR */ -/* Description: Sends a single sequence number error */ -#define SH_NI0_LLP_TEST_CTL_SENDSNERROR_SHFT 59 -#define SH_NI0_LLP_TEST_CTL_SENDSNERROR_MASK 0x0800000000000000 - -/* SH_NI0_LLP_TEST_CTL_FAKESNERROR */ -/* Description: Causes receiver to pretend it saw a sn error */ -#define SH_NI0_LLP_TEST_CTL_FAKESNERROR_SHFT 60 -#define SH_NI0_LLP_TEST_CTL_FAKESNERROR_MASK 0x1000000000000000 - -/* SH_NI0_LLP_TEST_CTL_CAPTURED */ -/* Description: Indicates a Valid Micropacket was captured */ -#define SH_NI0_LLP_TEST_CTL_CAPTURED_SHFT 61 -#define SH_NI0_LLP_TEST_CTL_CAPTURED_MASK 0x2000000000000000 - -/* SH_NI0_LLP_TEST_CTL_CBERROR */ -/* Description: Indicates a Micropacket with a CB error was capture */ -#define SH_NI0_LLP_TEST_CTL_CBERROR_SHFT 62 -#define SH_NI0_LLP_TEST_CTL_CBERROR_MASK 0x4000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI0_LLP_CAPT_WD1" */ -/* low order 64-bit captured word */ -/* ==================================================================== */ - -#define SH_NI0_LLP_CAPT_WD1 0x0000000150000030 -#define SH_NI0_LLP_CAPT_WD1_MASK 0xffffffffffffffff -#define SH_NI0_LLP_CAPT_WD1_INIT 0x0000000000000000 - -/* SH_NI0_LLP_CAPT_WD1_DATA */ -/* Description: low order 64-bit captured word */ -#define SH_NI0_LLP_CAPT_WD1_DATA_SHFT 0 -#define SH_NI0_LLP_CAPT_WD1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_NI0_LLP_CAPT_WD2" */ -/* high order 64-bit captured word */ -/* ==================================================================== */ - -#define SH_NI0_LLP_CAPT_WD2 0x0000000150000038 -#define SH_NI0_LLP_CAPT_WD2_MASK 0xffffffffffffffff -#define SH_NI0_LLP_CAPT_WD2_INIT 0x0000000000000000 - -/* SH_NI0_LLP_CAPT_WD2_DATA */ -/* Description: high order 64-bit captured word */ -#define SH_NI0_LLP_CAPT_WD2_DATA_SHFT 0 -#define SH_NI0_LLP_CAPT_WD2_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_NI0_LLP_CAPT_SBCB" */ -/* captured sideband, sequence, and CRC */ -/* ==================================================================== */ - -#define SH_NI0_LLP_CAPT_SBCB 0x0000000150000040 -#define SH_NI0_LLP_CAPT_SBCB_MASK 0x0000001fffffffff -#define SH_NI0_LLP_CAPT_SBCB_INIT 0x0000000000000000 - -/* SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVSBSN */ -/* Description: sideband and sequence */ -#define SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVSBSN_SHFT 0 -#define SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVSBSN_MASK 0x000000000000ffff - -/* SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVCRC */ -/* Description: CRC */ -#define SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVCRC_SHFT 16 -#define SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVCRC_MASK 0x00000000ffff0000 - -/* SH_NI0_LLP_CAPT_SBCB_SENTALLCBERRORS */ -/* Description: All CB errors have been sent */ -#define SH_NI0_LLP_CAPT_SBCB_SENTALLCBERRORS_SHFT 32 -#define SH_NI0_LLP_CAPT_SBCB_SENTALLCBERRORS_MASK 0x0000000100000000 - -/* SH_NI0_LLP_CAPT_SBCB_SENTALLSNERRORS */ -/* Description: All SN errors have been sent */ -#define SH_NI0_LLP_CAPT_SBCB_SENTALLSNERRORS_SHFT 33 -#define SH_NI0_LLP_CAPT_SBCB_SENTALLSNERRORS_MASK 0x0000000200000000 - -/* SH_NI0_LLP_CAPT_SBCB_FAKEDALLSNERRORS */ -/* Description: All faked SN errors have been sent */ -#define SH_NI0_LLP_CAPT_SBCB_FAKEDALLSNERRORS_SHFT 34 -#define SH_NI0_LLP_CAPT_SBCB_FAKEDALLSNERRORS_MASK 0x0000000400000000 - -/* SH_NI0_LLP_CAPT_SBCB_CHARGEOVERFLOW */ -/* Description: wire charge counter overflowed, valid if llp_mode e */ -#define SH_NI0_LLP_CAPT_SBCB_CHARGEOVERFLOW_SHFT 35 -#define SH_NI0_LLP_CAPT_SBCB_CHARGEOVERFLOW_MASK 0x0000000800000000 - -/* SH_NI0_LLP_CAPT_SBCB_CHARGEUNDERFLOW */ -/* Description: wire charge counter underflowed, valid if llp_mode */ -/* enabled */ -#define SH_NI0_LLP_CAPT_SBCB_CHARGEUNDERFLOW_SHFT 36 -#define SH_NI0_LLP_CAPT_SBCB_CHARGEUNDERFLOW_MASK 0x0000001000000000 - -/* ==================================================================== */ -/* Register "SH_NI0_LLP_ERR" */ -/* ==================================================================== */ - -#define SH_NI0_LLP_ERR 0x0000000150000048 -#define SH_NI0_LLP_ERR_MASK 0x001fffffffffffff -#define SH_NI0_LLP_ERR_INIT 0x0000000000000000 - -/* SH_NI0_LLP_ERR_RX_SN_ERR_COUNT */ -/* Description: Counts the sequence number errors received */ -#define SH_NI0_LLP_ERR_RX_SN_ERR_COUNT_SHFT 0 -#define SH_NI0_LLP_ERR_RX_SN_ERR_COUNT_MASK 0x00000000000000ff - -/* SH_NI0_LLP_ERR_RX_CB_ERR_COUNT */ -/* Description: Counts the check byte errors received */ -#define SH_NI0_LLP_ERR_RX_CB_ERR_COUNT_SHFT 8 -#define SH_NI0_LLP_ERR_RX_CB_ERR_COUNT_MASK 0x000000000000ff00 - -/* SH_NI0_LLP_ERR_RETRY_COUNT */ -/* Description: Counts the retries */ -#define SH_NI0_LLP_ERR_RETRY_COUNT_SHFT 16 -#define SH_NI0_LLP_ERR_RETRY_COUNT_MASK 0x0000000000ff0000 - -/* SH_NI0_LLP_ERR_RETRY_TIMEOUT */ -/* Description: Indicates a retry timeout has occurred */ -#define SH_NI0_LLP_ERR_RETRY_TIMEOUT_SHFT 24 -#define SH_NI0_LLP_ERR_RETRY_TIMEOUT_MASK 0x0000000001000000 - -/* SH_NI0_LLP_ERR_RCV_LINK_RESET */ -/* Description: Indicates a link reset has been received */ -#define SH_NI0_LLP_ERR_RCV_LINK_RESET_SHFT 25 -#define SH_NI0_LLP_ERR_RCV_LINK_RESET_MASK 0x0000000002000000 - -/* SH_NI0_LLP_ERR_SQUASH */ -/* Description: Indicates a micropacket was squashed */ -#define SH_NI0_LLP_ERR_SQUASH_SHFT 26 -#define SH_NI0_LLP_ERR_SQUASH_MASK 0x0000000004000000 - -/* SH_NI0_LLP_ERR_POWER_NOT_OK */ -/* Description: Detects and traps a loss of power_OK */ -#define SH_NI0_LLP_ERR_POWER_NOT_OK_SHFT 27 -#define SH_NI0_LLP_ERR_POWER_NOT_OK_MASK 0x0000000008000000 - -/* SH_NI0_LLP_ERR_WIRE_CNT */ -/* Description: counts the errors detected on a single wire test */ -#define SH_NI0_LLP_ERR_WIRE_CNT_SHFT 28 -#define SH_NI0_LLP_ERR_WIRE_CNT_MASK 0x000ffffff0000000 - -/* SH_NI0_LLP_ERR_WIRE_OVERFLOW */ -/* Description: wire_error_cnt has overflowed */ -#define SH_NI0_LLP_ERR_WIRE_OVERFLOW_SHFT 52 -#define SH_NI0_LLP_ERR_WIRE_OVERFLOW_MASK 0x0010000000000000 - -/* ==================================================================== */ -/* Register "SH_NI1_LLP_STAT" */ -/* This register describes the LLP status. */ -/* ==================================================================== */ - -#define SH_NI1_LLP_STAT 0x0000000150002000 -#define SH_NI1_LLP_STAT_MASK 0x000000000000000f -#define SH_NI1_LLP_STAT_INIT 0x0000000000000000 - -/* SH_NI1_LLP_STAT_LINK_RESET_STATE */ -/* Description: Status of LLP link. */ -#define SH_NI1_LLP_STAT_LINK_RESET_STATE_SHFT 0 -#define SH_NI1_LLP_STAT_LINK_RESET_STATE_MASK 0x000000000000000f - -/* ==================================================================== */ -/* Register "SH_NI1_LLP_RESET" */ -/* Writing issues a reset to the network interface */ -/* ==================================================================== */ - -#define SH_NI1_LLP_RESET 0x0000000150002008 -#define SH_NI1_LLP_RESET_MASK 0x0000000000000003 -#define SH_NI1_LLP_RESET_INIT 0x0000000000000000 - -/* SH_NI1_LLP_RESET_LINK */ -/* Description: Send Link Reset. Generates a pulse. */ -#define SH_NI1_LLP_RESET_LINK_SHFT 0 -#define SH_NI1_LLP_RESET_LINK_MASK 0x0000000000000001 - -/* SH_NI1_LLP_RESET_WARM */ -/* Description: Send Warm Reset. Generates a pulse. */ -#define SH_NI1_LLP_RESET_WARM_SHFT 1 -#define SH_NI1_LLP_RESET_WARM_MASK 0x0000000000000002 - -/* ==================================================================== */ -/* Register "SH_NI1_LLP_RESET_EN" */ -/* Controls LLP warm reset propagation */ -/* ==================================================================== */ - -#define SH_NI1_LLP_RESET_EN 0x0000000150002010 -#define SH_NI1_LLP_RESET_EN_MASK 0x0000000000000001 -#define SH_NI1_LLP_RESET_EN_INIT 0x0000000000000001 - -/* SH_NI1_LLP_RESET_EN_OK */ -/* Description: Allow LLP warm reset to reset SHUB */ -#define SH_NI1_LLP_RESET_EN_OK_SHFT 0 -#define SH_NI1_LLP_RESET_EN_OK_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_NI1_LLP_CHAN_MODE" */ -/* Sets the signaling mode of LLP and channel */ -/* ==================================================================== */ - -#define SH_NI1_LLP_CHAN_MODE 0x0000000150002018 -#define SH_NI1_LLP_CHAN_MODE_MASK 0x000000000000001f -#define SH_NI1_LLP_CHAN_MODE_INIT 0x0000000000000000 - -/* SH_NI1_LLP_CHAN_MODE_BITMODE32 */ -/* Description: Enables 32-bit (plus sideband) channel phits */ -#define SH_NI1_LLP_CHAN_MODE_BITMODE32_SHFT 0 -#define SH_NI1_LLP_CHAN_MODE_BITMODE32_MASK 0x0000000000000001 - -/* SH_NI1_LLP_CHAN_MODE_AC_ENCODE */ -/* Description: Enables nearly dc-free encoding for AC-coupling */ -#define SH_NI1_LLP_CHAN_MODE_AC_ENCODE_SHFT 1 -#define SH_NI1_LLP_CHAN_MODE_AC_ENCODE_MASK 0x0000000000000002 - -/* SH_NI1_LLP_CHAN_MODE_ENABLE_TUNING */ -/* Description: Enables automatic tuning of channel skew. */ -#define SH_NI1_LLP_CHAN_MODE_ENABLE_TUNING_SHFT 2 -#define SH_NI1_LLP_CHAN_MODE_ENABLE_TUNING_MASK 0x0000000000000004 - -/* SH_NI1_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD */ -/* Description: Enables remote fine tune updates */ -#define SH_NI1_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD_SHFT 3 -#define SH_NI1_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD_MASK 0x0000000000000008 - -/* SH_NI1_LLP_CHAN_MODE_ENABLE_CLKQUAD */ -/* Description: Enables quadrature clock in the pfssd */ -#define SH_NI1_LLP_CHAN_MODE_ENABLE_CLKQUAD_SHFT 4 -#define SH_NI1_LLP_CHAN_MODE_ENABLE_CLKQUAD_MASK 0x0000000000000010 - -/* ==================================================================== */ -/* Register "SH_NI1_LLP_CONFIG" */ -/* Sets the configuration of LLP and channel */ -/* ==================================================================== */ - -#define SH_NI1_LLP_CONFIG 0x0000000150002020 -#define SH_NI1_LLP_CONFIG_MASK 0x0000003fffffffff -#define SH_NI1_LLP_CONFIG_INIT 0x00000007fc6ffd00 - -/* SH_NI1_LLP_CONFIG_MAXBURST */ -#define SH_NI1_LLP_CONFIG_MAXBURST_SHFT 0 -#define SH_NI1_LLP_CONFIG_MAXBURST_MASK 0x00000000000003ff - -/* SH_NI1_LLP_CONFIG_MAXRETRY */ -#define SH_NI1_LLP_CONFIG_MAXRETRY_SHFT 10 -#define SH_NI1_LLP_CONFIG_MAXRETRY_MASK 0x00000000000ffc00 - -/* SH_NI1_LLP_CONFIG_NULLTIMEOUT */ -#define SH_NI1_LLP_CONFIG_NULLTIMEOUT_SHFT 20 -#define SH_NI1_LLP_CONFIG_NULLTIMEOUT_MASK 0x0000000003f00000 - -/* SH_NI1_LLP_CONFIG_FTU_TIME */ -#define SH_NI1_LLP_CONFIG_FTU_TIME_SHFT 26 -#define SH_NI1_LLP_CONFIG_FTU_TIME_MASK 0x0000003ffc000000 - -/* ==================================================================== */ -/* Register "SH_NI1_LLP_TEST_CTL" */ -/* ==================================================================== */ - -#define SH_NI1_LLP_TEST_CTL 0x0000000150002028 -#define SH_NI1_LLP_TEST_CTL_MASK 0x7ff3f3ffffffffff -#define SH_NI1_LLP_TEST_CTL_INIT 0x000000000a5fffff - -/* SH_NI1_LLP_TEST_CTL_PATTERN */ -/* Description: Send channel data pattern */ -#define SH_NI1_LLP_TEST_CTL_PATTERN_SHFT 0 -#define SH_NI1_LLP_TEST_CTL_PATTERN_MASK 0x000000ffffffffff - -/* SH_NI1_LLP_TEST_CTL_SEND_TEST_MODE */ -/* Description: Enables continuous send of data */ -#define SH_NI1_LLP_TEST_CTL_SEND_TEST_MODE_SHFT 40 -#define SH_NI1_LLP_TEST_CTL_SEND_TEST_MODE_MASK 0x0000030000000000 - -/* SH_NI1_LLP_TEST_CTL_WIRE_SEL */ -#define SH_NI1_LLP_TEST_CTL_WIRE_SEL_SHFT 44 -#define SH_NI1_LLP_TEST_CTL_WIRE_SEL_MASK 0x0003f00000000000 - -/* SH_NI1_LLP_TEST_CTL_LFSR_MODE */ -#define SH_NI1_LLP_TEST_CTL_LFSR_MODE_SHFT 52 -#define SH_NI1_LLP_TEST_CTL_LFSR_MODE_MASK 0x0030000000000000 - -/* SH_NI1_LLP_TEST_CTL_NOISE_MODE */ -#define SH_NI1_LLP_TEST_CTL_NOISE_MODE_SHFT 54 -#define SH_NI1_LLP_TEST_CTL_NOISE_MODE_MASK 0x00c0000000000000 - -/* SH_NI1_LLP_TEST_CTL_ARMCAPTURE */ -/* Description: Enable Capture of Next MicroPacket */ -#define SH_NI1_LLP_TEST_CTL_ARMCAPTURE_SHFT 56 -#define SH_NI1_LLP_TEST_CTL_ARMCAPTURE_MASK 0x0100000000000000 - -/* SH_NI1_LLP_TEST_CTL_CAPTURECBONLY */ -/* Description: Only capture a micropacket with a Check Byte error */ -#define SH_NI1_LLP_TEST_CTL_CAPTURECBONLY_SHFT 57 -#define SH_NI1_LLP_TEST_CTL_CAPTURECBONLY_MASK 0x0200000000000000 - -/* SH_NI1_LLP_TEST_CTL_SENDCBERROR */ -/* Description: Sends a single error */ -#define SH_NI1_LLP_TEST_CTL_SENDCBERROR_SHFT 58 -#define SH_NI1_LLP_TEST_CTL_SENDCBERROR_MASK 0x0400000000000000 - -/* SH_NI1_LLP_TEST_CTL_SENDSNERROR */ -/* Description: Sends a single sequence number error */ -#define SH_NI1_LLP_TEST_CTL_SENDSNERROR_SHFT 59 -#define SH_NI1_LLP_TEST_CTL_SENDSNERROR_MASK 0x0800000000000000 - -/* SH_NI1_LLP_TEST_CTL_FAKESNERROR */ -/* Description: Causes receiver to pretend it saw a sn error */ -#define SH_NI1_LLP_TEST_CTL_FAKESNERROR_SHFT 60 -#define SH_NI1_LLP_TEST_CTL_FAKESNERROR_MASK 0x1000000000000000 - -/* SH_NI1_LLP_TEST_CTL_CAPTURED */ -/* Description: Indicates a Valid Micropacket was captured */ -#define SH_NI1_LLP_TEST_CTL_CAPTURED_SHFT 61 -#define SH_NI1_LLP_TEST_CTL_CAPTURED_MASK 0x2000000000000000 - -/* SH_NI1_LLP_TEST_CTL_CBERROR */ -/* Description: Indicates a Micropacket with a CB error was capture */ -#define SH_NI1_LLP_TEST_CTL_CBERROR_SHFT 62 -#define SH_NI1_LLP_TEST_CTL_CBERROR_MASK 0x4000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI1_LLP_CAPT_WD1" */ -/* low order 64-bit captured word */ -/* ==================================================================== */ - -#define SH_NI1_LLP_CAPT_WD1 0x0000000150002030 -#define SH_NI1_LLP_CAPT_WD1_MASK 0xffffffffffffffff -#define SH_NI1_LLP_CAPT_WD1_INIT 0x0000000000000000 - -/* SH_NI1_LLP_CAPT_WD1_DATA */ -/* Description: low order 64-bit captured word */ -#define SH_NI1_LLP_CAPT_WD1_DATA_SHFT 0 -#define SH_NI1_LLP_CAPT_WD1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_NI1_LLP_CAPT_WD2" */ -/* high order 64-bit captured word */ -/* ==================================================================== */ - -#define SH_NI1_LLP_CAPT_WD2 0x0000000150002038 -#define SH_NI1_LLP_CAPT_WD2_MASK 0xffffffffffffffff -#define SH_NI1_LLP_CAPT_WD2_INIT 0x0000000000000000 - -/* SH_NI1_LLP_CAPT_WD2_DATA */ -/* Description: high order 64-bit captured word */ -#define SH_NI1_LLP_CAPT_WD2_DATA_SHFT 0 -#define SH_NI1_LLP_CAPT_WD2_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_NI1_LLP_CAPT_SBCB" */ -/* captured sideband, sequence, and CRC */ -/* ==================================================================== */ - -#define SH_NI1_LLP_CAPT_SBCB 0x0000000150002040 -#define SH_NI1_LLP_CAPT_SBCB_MASK 0x0000001fffffffff -#define SH_NI1_LLP_CAPT_SBCB_INIT 0x0000000000000000 - -/* SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVSBSN */ -/* Description: sideband and sequence */ -#define SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVSBSN_SHFT 0 -#define SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVSBSN_MASK 0x000000000000ffff - -/* SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVCRC */ -/* Description: CRC */ -#define SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVCRC_SHFT 16 -#define SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVCRC_MASK 0x00000000ffff0000 - -/* SH_NI1_LLP_CAPT_SBCB_SENTALLCBERRORS */ -/* Description: All CB errors have been sent */ -#define SH_NI1_LLP_CAPT_SBCB_SENTALLCBERRORS_SHFT 32 -#define SH_NI1_LLP_CAPT_SBCB_SENTALLCBERRORS_MASK 0x0000000100000000 - -/* SH_NI1_LLP_CAPT_SBCB_SENTALLSNERRORS */ -/* Description: All SN errors have been sent */ -#define SH_NI1_LLP_CAPT_SBCB_SENTALLSNERRORS_SHFT 33 -#define SH_NI1_LLP_CAPT_SBCB_SENTALLSNERRORS_MASK 0x0000000200000000 - -/* SH_NI1_LLP_CAPT_SBCB_FAKEDALLSNERRORS */ -/* Description: All faked SN errors have been sent */ -#define SH_NI1_LLP_CAPT_SBCB_FAKEDALLSNERRORS_SHFT 34 -#define SH_NI1_LLP_CAPT_SBCB_FAKEDALLSNERRORS_MASK 0x0000000400000000 - -/* SH_NI1_LLP_CAPT_SBCB_CHARGEOVERFLOW */ -/* Description: wire charge counter overflowed, valid if llp_mode e */ -#define SH_NI1_LLP_CAPT_SBCB_CHARGEOVERFLOW_SHFT 35 -#define SH_NI1_LLP_CAPT_SBCB_CHARGEOVERFLOW_MASK 0x0000000800000000 - -/* SH_NI1_LLP_CAPT_SBCB_CHARGEUNDERFLOW */ -/* Description: wire charge counter underflowed, valid if llp_mode */ -/* enabled */ -#define SH_NI1_LLP_CAPT_SBCB_CHARGEUNDERFLOW_SHFT 36 -#define SH_NI1_LLP_CAPT_SBCB_CHARGEUNDERFLOW_MASK 0x0000001000000000 - -/* ==================================================================== */ -/* Register "SH_NI1_LLP_ERR" */ -/* ==================================================================== */ - -#define SH_NI1_LLP_ERR 0x0000000150002048 -#define SH_NI1_LLP_ERR_MASK 0x001fffffffffffff -#define SH_NI1_LLP_ERR_INIT 0x0000000000000000 - -/* SH_NI1_LLP_ERR_RX_SN_ERR_COUNT */ -/* Description: Counts the sequence number errors received */ -#define SH_NI1_LLP_ERR_RX_SN_ERR_COUNT_SHFT 0 -#define SH_NI1_LLP_ERR_RX_SN_ERR_COUNT_MASK 0x00000000000000ff - -/* SH_NI1_LLP_ERR_RX_CB_ERR_COUNT */ -/* Description: Counts the check byte errors received */ -#define SH_NI1_LLP_ERR_RX_CB_ERR_COUNT_SHFT 8 -#define SH_NI1_LLP_ERR_RX_CB_ERR_COUNT_MASK 0x000000000000ff00 - -/* SH_NI1_LLP_ERR_RETRY_COUNT */ -/* Description: Counts the retries */ -#define SH_NI1_LLP_ERR_RETRY_COUNT_SHFT 16 -#define SH_NI1_LLP_ERR_RETRY_COUNT_MASK 0x0000000000ff0000 - -/* SH_NI1_LLP_ERR_RETRY_TIMEOUT */ -/* Description: Indicates a retry timeout has occurred */ -#define SH_NI1_LLP_ERR_RETRY_TIMEOUT_SHFT 24 -#define SH_NI1_LLP_ERR_RETRY_TIMEOUT_MASK 0x0000000001000000 - -/* SH_NI1_LLP_ERR_RCV_LINK_RESET */ -/* Description: Indicates a link reset has been received */ -#define SH_NI1_LLP_ERR_RCV_LINK_RESET_SHFT 25 -#define SH_NI1_LLP_ERR_RCV_LINK_RESET_MASK 0x0000000002000000 - -/* SH_NI1_LLP_ERR_SQUASH */ -/* Description: Indicates a micropacket was squashed */ -#define SH_NI1_LLP_ERR_SQUASH_SHFT 26 -#define SH_NI1_LLP_ERR_SQUASH_MASK 0x0000000004000000 - -/* SH_NI1_LLP_ERR_POWER_NOT_OK */ -/* Description: Detects and traps a loss of power_OK */ -#define SH_NI1_LLP_ERR_POWER_NOT_OK_SHFT 27 -#define SH_NI1_LLP_ERR_POWER_NOT_OK_MASK 0x0000000008000000 - -/* SH_NI1_LLP_ERR_WIRE_CNT */ -/* Description: counts the errors detected on a single wire test */ -#define SH_NI1_LLP_ERR_WIRE_CNT_SHFT 28 -#define SH_NI1_LLP_ERR_WIRE_CNT_MASK 0x000ffffff0000000 - -/* SH_NI1_LLP_ERR_WIRE_OVERFLOW */ -/* Description: wire_error_cnt has overflowed */ -#define SH_NI1_LLP_ERR_WIRE_OVERFLOW_SHFT 52 -#define SH_NI1_LLP_ERR_WIRE_OVERFLOW_MASK 0x0010000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_LLP_TO_FIFO02_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_LLP_TO_FIFO02_FLOW 0x0000000150001010 -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_MASK 0x3f3f003f3f00bfbf -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN_SHFT 24 -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000 - -/* SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP_SHFT 32 -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000 - -/* SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN_SHFT 48 -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000 - -/* SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP_SHFT 56 -#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_LLP_TO_FIFO13_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_LLP_TO_FIFO13_FLOW 0x0000000150001020 -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_MASK 0x3f3f003f3f00bfbf -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN_SHFT 24 -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000 - -/* SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP_SHFT 32 -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000 - -/* SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN_SHFT 48 -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000 - -/* SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP_SHFT 56 -#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_LLP_DEBIT_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_LLP_DEBIT_FLOW 0x0000000150001030 -#define SH_XNNI0_LLP_DEBIT_FLOW_MASK 0x1f1f1f1f1f1f1f1f -#define SH_XNNI0_LLP_DEBIT_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_DYN */ -/* Description: vc0 debit dynamic value */ -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_DYN_SHFT 0 -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_DYN_MASK 0x000000000000001f - -/* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_CAP */ -/* Description: vc0 debit captured value */ -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_CAP_SHFT 8 -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_CAP_MASK 0x0000000000001f00 - -/* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_DYN */ -/* Description: vc1 debit dynamic value */ -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_DYN_SHFT 16 -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_DYN_MASK 0x00000000001f0000 - -/* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_CAP */ -/* Description: vc1 debit captured value */ -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_CAP_SHFT 24 -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_CAP_MASK 0x000000001f000000 - -/* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_DYN */ -/* Description: vc2 debit dynamic value */ -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_DYN_SHFT 32 -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_DYN_MASK 0x0000001f00000000 - -/* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_CAP */ -/* Description: vc2 debit captured value */ -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_CAP_SHFT 40 -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_CAP_MASK 0x00001f0000000000 - -/* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_DYN */ -/* Description: vc3 debit dynamic value */ -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_DYN_SHFT 48 -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_DYN_MASK 0x001f000000000000 - -/* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_CAP */ -/* Description: vc3 debit captured value */ -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_CAP_SHFT 56 -#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_CAP_MASK 0x1f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_LINK_0_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_LINK_0_FLOW 0x0000000150001040 -#define SH_XNNI0_LINK_0_FLOW_MASK 0x000000007f7f7fbf -#define SH_XNNI0_LINK_0_FLOW_INIT 0x0000000000001800 - -/* SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on vc0 from debit cntr */ -#define SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 Limit Test */ -#define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_TEST_SHFT 8 -#define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_TEST_MASK 0x0000000000007f00 - -/* SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_DYN */ -/* Description: Dynamic vc0 credit value */ -#define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_DYN_SHFT 16 -#define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_DYN_MASK 0x00000000007f0000 - -/* SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_CAP */ -/* Description: Captured vc0 credit */ -#define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_CAP_SHFT 24 -#define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_CAP_MASK 0x000000007f000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_LINK_1_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_LINK_1_FLOW 0x0000000150001050 -#define SH_XNNI0_LINK_1_FLOW_MASK 0x000000007f7f7fbf -#define SH_XNNI0_LINK_1_FLOW_INIT 0x0000000000001800 - -/* SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_WITHHOLD */ -/* Description: vc1 withhold */ -#define SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_WITHHOLD_SHFT 0 -#define SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED */ -/* Description: Force Credit on vc1 from debit cntr */ -#define SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED_SHFT 7 -#define SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_TEST */ -/* Description: vc1 Limit Test */ -#define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_TEST_SHFT 8 -#define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_TEST_MASK 0x0000000000007f00 - -/* SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_DYN */ -/* Description: Dynamic vc1 credit value */ -#define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_DYN_SHFT 16 -#define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_DYN_MASK 0x00000000007f0000 - -/* SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_CAP */ -/* Description: Captured vc1 credit */ -#define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_CAP_SHFT 24 -#define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_CAP_MASK 0x000000007f000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_LINK_2_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_LINK_2_FLOW 0x0000000150001060 -#define SH_XNNI0_LINK_2_FLOW_MASK 0x000000007f7f7fbf -#define SH_XNNI0_LINK_2_FLOW_INIT 0x0000000000001800 - -/* SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_WITHHOLD_SHFT 0 -#define SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on vc2 from debit cntr */ -#define SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 7 -#define SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 Limit Test */ -#define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_TEST_SHFT 8 -#define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_TEST_MASK 0x0000000000007f00 - -/* SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_DYN */ -/* Description: Dynamic vc2 credit value */ -#define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_DYN_SHFT 16 -#define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_DYN_MASK 0x00000000007f0000 - -/* SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_CAP */ -/* Description: Captured vc2 credit */ -#define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_CAP_SHFT 24 -#define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_CAP_MASK 0x000000007f000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_LINK_3_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_LINK_3_FLOW 0x0000000150001070 -#define SH_XNNI0_LINK_3_FLOW_MASK 0x000000007f7f7fbf -#define SH_XNNI0_LINK_3_FLOW_INIT 0x0000000000001800 - -/* SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_WITHHOLD */ -/* Description: vc3 withhold */ -#define SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_WITHHOLD_SHFT 0 -#define SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED */ -/* Description: Force Credit on vc3 from debit cntr */ -#define SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED_SHFT 7 -#define SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_TEST */ -/* Description: vc3 Limit Test */ -#define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_TEST_SHFT 8 -#define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_TEST_MASK 0x0000000000007f00 - -/* SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_DYN */ -/* Description: Dynamic vc3 credit value */ -#define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_DYN_SHFT 16 -#define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_DYN_MASK 0x00000000007f0000 - -/* SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_CAP */ -/* Description: Captured vc3 credit */ -#define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_CAP_SHFT 24 -#define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_CAP_MASK 0x000000007f000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_LLP_TO_FIFO02_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_LLP_TO_FIFO02_FLOW 0x0000000150003010 -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_MASK 0x3f3f003f3f00bfbf -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN_SHFT 24 -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000 - -/* SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP_SHFT 32 -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000 - -/* SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN_SHFT 48 -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000 - -/* SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP_SHFT 56 -#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_LLP_TO_FIFO13_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_LLP_TO_FIFO13_FLOW 0x0000000150003020 -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_MASK 0x3f3f003f3f00bfbf -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN_SHFT 24 -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000 - -/* SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP_SHFT 32 -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000 - -/* SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN_SHFT 48 -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000 - -/* SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP_SHFT 56 -#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_LLP_DEBIT_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_LLP_DEBIT_FLOW 0x0000000150003030 -#define SH_XNNI1_LLP_DEBIT_FLOW_MASK 0x1f1f1f1f1f1f1f1f -#define SH_XNNI1_LLP_DEBIT_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_DYN */ -/* Description: vc0 debit dynamic value */ -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_DYN_SHFT 0 -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_DYN_MASK 0x000000000000001f - -/* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_CAP */ -/* Description: vc0 debit captured value */ -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_CAP_SHFT 8 -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_CAP_MASK 0x0000000000001f00 - -/* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_DYN */ -/* Description: vc1 debit dynamic value */ -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_DYN_SHFT 16 -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_DYN_MASK 0x00000000001f0000 - -/* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_CAP */ -/* Description: vc1 debit captured value */ -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_CAP_SHFT 24 -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_CAP_MASK 0x000000001f000000 - -/* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_DYN */ -/* Description: vc2 debit dynamic value */ -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_DYN_SHFT 32 -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_DYN_MASK 0x0000001f00000000 - -/* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_CAP */ -/* Description: vc2 debit captured value */ -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_CAP_SHFT 40 -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_CAP_MASK 0x00001f0000000000 - -/* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_DYN */ -/* Description: vc3 debit dynamic value */ -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_DYN_SHFT 48 -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_DYN_MASK 0x001f000000000000 - -/* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_CAP */ -/* Description: vc3 debit captured value */ -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_CAP_SHFT 56 -#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_CAP_MASK 0x1f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_LINK_0_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_LINK_0_FLOW 0x0000000150003040 -#define SH_XNNI1_LINK_0_FLOW_MASK 0x000000007f7f7fbf -#define SH_XNNI1_LINK_0_FLOW_INIT 0x0000000000001800 - -/* SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on vc0 from debit cntr */ -#define SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 Limit Test */ -#define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_TEST_SHFT 8 -#define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_TEST_MASK 0x0000000000007f00 - -/* SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_DYN */ -/* Description: Dynamic vc0 credit value */ -#define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_DYN_SHFT 16 -#define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_DYN_MASK 0x00000000007f0000 - -/* SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_CAP */ -/* Description: Captured vc0 credit */ -#define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_CAP_SHFT 24 -#define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_CAP_MASK 0x000000007f000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_LINK_1_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_LINK_1_FLOW 0x0000000150003050 -#define SH_XNNI1_LINK_1_FLOW_MASK 0x000000007f7f7fbf -#define SH_XNNI1_LINK_1_FLOW_INIT 0x0000000000001800 - -/* SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_WITHHOLD */ -/* Description: vc1 withhold */ -#define SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_WITHHOLD_SHFT 0 -#define SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED */ -/* Description: Force Credit on vc1 from debit cntr */ -#define SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED_SHFT 7 -#define SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_TEST */ -/* Description: vc1 Limit Test */ -#define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_TEST_SHFT 8 -#define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_TEST_MASK 0x0000000000007f00 - -/* SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_DYN */ -/* Description: Dynamic vc1 credit value */ -#define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_DYN_SHFT 16 -#define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_DYN_MASK 0x00000000007f0000 - -/* SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_CAP */ -/* Description: Captured vc1 credit */ -#define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_CAP_SHFT 24 -#define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_CAP_MASK 0x000000007f000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_LINK_2_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_LINK_2_FLOW 0x0000000150003060 -#define SH_XNNI1_LINK_2_FLOW_MASK 0x000000007f7f7fbf -#define SH_XNNI1_LINK_2_FLOW_INIT 0x0000000000001800 - -/* SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_WITHHOLD_SHFT 0 -#define SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on vc2 from debit cntr */ -#define SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 7 -#define SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 Limit Test */ -#define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_TEST_SHFT 8 -#define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_TEST_MASK 0x0000000000007f00 - -/* SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_DYN */ -/* Description: Dynamic vc2 credit value */ -#define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_DYN_SHFT 16 -#define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_DYN_MASK 0x00000000007f0000 - -/* SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_CAP */ -/* Description: Captured vc2 credit */ -#define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_CAP_SHFT 24 -#define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_CAP_MASK 0x000000007f000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_LINK_3_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_LINK_3_FLOW 0x0000000150003070 -#define SH_XNNI1_LINK_3_FLOW_MASK 0x000000007f7f7fbf -#define SH_XNNI1_LINK_3_FLOW_INIT 0x0000000000001800 - -/* SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_WITHHOLD */ -/* Description: vc3 withhold */ -#define SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_WITHHOLD_SHFT 0 -#define SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED */ -/* Description: Force Credit on vc3 from debit cntr */ -#define SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED_SHFT 7 -#define SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_TEST */ -/* Description: vc3 Limit Test */ -#define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_TEST_SHFT 8 -#define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_TEST_MASK 0x0000000000007f00 - -/* SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_DYN */ -/* Description: Dynamic vc3 credit value */ -#define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_DYN_SHFT 16 -#define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_DYN_MASK 0x00000000007f0000 - -/* SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_CAP */ -/* Description: Captured vc3 credit */ -#define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_CAP_SHFT 24 -#define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_CAP_MASK 0x000000007f000000 - -/* ==================================================================== */ -/* Register "SH_IILB_LOCAL_TABLE" */ -/* local lookup table */ -/* ==================================================================== */ - -#define SH_IILB_LOCAL_TABLE 0x0000000150020000 -#define SH_IILB_LOCAL_TABLE_MASK 0x800000000000003f -#define SH_IILB_LOCAL_TABLE_MEMDEPTH 128 -#define SH_IILB_LOCAL_TABLE_INIT 0x0000000000000000 - -/* SH_IILB_LOCAL_TABLE_DIR0 */ -/* Description: Direction field for next chip */ -#define SH_IILB_LOCAL_TABLE_DIR0_SHFT 0 -#define SH_IILB_LOCAL_TABLE_DIR0_MASK 0x000000000000000f - -/* SH_IILB_LOCAL_TABLE_V0 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_IILB_LOCAL_TABLE_V0_SHFT 4 -#define SH_IILB_LOCAL_TABLE_V0_MASK 0x0000000000000010 - -/* SH_IILB_LOCAL_TABLE_NI_SEL0 */ -/* Description: ni select for requests */ -#define SH_IILB_LOCAL_TABLE_NI_SEL0_SHFT 5 -#define SH_IILB_LOCAL_TABLE_NI_SEL0_MASK 0x0000000000000020 - -/* SH_IILB_LOCAL_TABLE_VALID */ -/* Description: Indicates that this entry is valid */ -#define SH_IILB_LOCAL_TABLE_VALID_SHFT 63 -#define SH_IILB_LOCAL_TABLE_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_IILB_GLOBAL_TABLE" */ -/* global lookup table */ -/* ==================================================================== */ - -#define SH_IILB_GLOBAL_TABLE 0x0000000150020400 -#define SH_IILB_GLOBAL_TABLE_MASK 0x800000000000003f -#define SH_IILB_GLOBAL_TABLE_MEMDEPTH 16 -#define SH_IILB_GLOBAL_TABLE_INIT 0x0000000000000000 - -/* SH_IILB_GLOBAL_TABLE_DIR0 */ -/* Description: Direction field for next chip */ -#define SH_IILB_GLOBAL_TABLE_DIR0_SHFT 0 -#define SH_IILB_GLOBAL_TABLE_DIR0_MASK 0x000000000000000f - -/* SH_IILB_GLOBAL_TABLE_V0 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_IILB_GLOBAL_TABLE_V0_SHFT 4 -#define SH_IILB_GLOBAL_TABLE_V0_MASK 0x0000000000000010 - -/* SH_IILB_GLOBAL_TABLE_NI_SEL0 */ -/* Description: ni select for requests */ -#define SH_IILB_GLOBAL_TABLE_NI_SEL0_SHFT 5 -#define SH_IILB_GLOBAL_TABLE_NI_SEL0_MASK 0x0000000000000020 - -/* SH_IILB_GLOBAL_TABLE_VALID */ -/* Description: Indicates that this entry is valid */ -#define SH_IILB_GLOBAL_TABLE_VALID_SHFT 63 -#define SH_IILB_GLOBAL_TABLE_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_IILB_OVER_RIDE_TABLE" */ -/* If enabled, bypass the Global/Local tables */ -/* ==================================================================== */ - -#define SH_IILB_OVER_RIDE_TABLE 0x0000000150020480 -#define SH_IILB_OVER_RIDE_TABLE_MASK 0x800000000000003f -#define SH_IILB_OVER_RIDE_TABLE_INIT 0x8000000000000000 - -/* SH_IILB_OVER_RIDE_TABLE_DIR0 */ -/* Description: Direction field for next chip */ -#define SH_IILB_OVER_RIDE_TABLE_DIR0_SHFT 0 -#define SH_IILB_OVER_RIDE_TABLE_DIR0_MASK 0x000000000000000f - -/* SH_IILB_OVER_RIDE_TABLE_V0 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_IILB_OVER_RIDE_TABLE_V0_SHFT 4 -#define SH_IILB_OVER_RIDE_TABLE_V0_MASK 0x0000000000000010 - -/* SH_IILB_OVER_RIDE_TABLE_NI_SEL0 */ -/* Description: ni select */ -#define SH_IILB_OVER_RIDE_TABLE_NI_SEL0_SHFT 5 -#define SH_IILB_OVER_RIDE_TABLE_NI_SEL0_MASK 0x0000000000000020 - -/* SH_IILB_OVER_RIDE_TABLE_ENABLE */ -/* Description: Indicates that this entry is enabled */ -#define SH_IILB_OVER_RIDE_TABLE_ENABLE_SHFT 63 -#define SH_IILB_OVER_RIDE_TABLE_ENABLE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_IILB_RSP_PLANE_HINT" */ -/* If enabled, invert incoming response only plane hint bit before lo */ -/* ==================================================================== */ - -#define SH_IILB_RSP_PLANE_HINT 0x0000000150020488 -#define SH_IILB_RSP_PLANE_HINT_MASK 0x0000000000000000 -#define SH_IILB_RSP_PLANE_HINT_INIT 0x0000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_LOCAL_TABLE" */ -/* local lookup table */ -/* ==================================================================== */ - -#define SH_PI_LOCAL_TABLE 0x0000000150021000 -#define SH_PI_LOCAL_TABLE_MASK 0x8000000000003f3f -#define SH_PI_LOCAL_TABLE_MEMDEPTH 128 -#define SH_PI_LOCAL_TABLE_INIT 0x0000000000000000 - -/* SH_PI_LOCAL_TABLE_DIR0 */ -/* Description: Direction field for next chip */ -#define SH_PI_LOCAL_TABLE_DIR0_SHFT 0 -#define SH_PI_LOCAL_TABLE_DIR0_MASK 0x000000000000000f - -/* SH_PI_LOCAL_TABLE_V0 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_PI_LOCAL_TABLE_V0_SHFT 4 -#define SH_PI_LOCAL_TABLE_V0_MASK 0x0000000000000010 - -/* SH_PI_LOCAL_TABLE_NI_SEL0 */ -/* Description: ni select for requests */ -#define SH_PI_LOCAL_TABLE_NI_SEL0_SHFT 5 -#define SH_PI_LOCAL_TABLE_NI_SEL0_MASK 0x0000000000000020 - -/* SH_PI_LOCAL_TABLE_DIR1 */ -#define SH_PI_LOCAL_TABLE_DIR1_SHFT 8 -#define SH_PI_LOCAL_TABLE_DIR1_MASK 0x0000000000000f00 - -/* SH_PI_LOCAL_TABLE_V1 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_PI_LOCAL_TABLE_V1_SHFT 12 -#define SH_PI_LOCAL_TABLE_V1_MASK 0x0000000000001000 - -/* SH_PI_LOCAL_TABLE_NI_SEL1 */ -/* Description: ni select for plane-hint 1 */ -#define SH_PI_LOCAL_TABLE_NI_SEL1_SHFT 13 -#define SH_PI_LOCAL_TABLE_NI_SEL1_MASK 0x0000000000002000 - -/* SH_PI_LOCAL_TABLE_VALID */ -/* Description: Indicates that this entry is valid */ -#define SH_PI_LOCAL_TABLE_VALID_SHFT 63 -#define SH_PI_LOCAL_TABLE_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_GLOBAL_TABLE" */ -/* global lookup table */ -/* ==================================================================== */ - -#define SH_PI_GLOBAL_TABLE 0x0000000150021400 -#define SH_PI_GLOBAL_TABLE_MASK 0x8000000000003f3f -#define SH_PI_GLOBAL_TABLE_MEMDEPTH 16 -#define SH_PI_GLOBAL_TABLE_INIT 0x0000000000000000 - -/* SH_PI_GLOBAL_TABLE_DIR0 */ -/* Description: Direction field for next chip */ -#define SH_PI_GLOBAL_TABLE_DIR0_SHFT 0 -#define SH_PI_GLOBAL_TABLE_DIR0_MASK 0x000000000000000f - -/* SH_PI_GLOBAL_TABLE_V0 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_PI_GLOBAL_TABLE_V0_SHFT 4 -#define SH_PI_GLOBAL_TABLE_V0_MASK 0x0000000000000010 - -/* SH_PI_GLOBAL_TABLE_NI_SEL0 */ -/* Description: ni select for requests */ -#define SH_PI_GLOBAL_TABLE_NI_SEL0_SHFT 5 -#define SH_PI_GLOBAL_TABLE_NI_SEL0_MASK 0x0000000000000020 - -/* SH_PI_GLOBAL_TABLE_DIR1 */ -#define SH_PI_GLOBAL_TABLE_DIR1_SHFT 8 -#define SH_PI_GLOBAL_TABLE_DIR1_MASK 0x0000000000000f00 - -/* SH_PI_GLOBAL_TABLE_V1 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_PI_GLOBAL_TABLE_V1_SHFT 12 -#define SH_PI_GLOBAL_TABLE_V1_MASK 0x0000000000001000 - -/* SH_PI_GLOBAL_TABLE_NI_SEL1 */ -/* Description: ni select for plane-hint 1 */ -#define SH_PI_GLOBAL_TABLE_NI_SEL1_SHFT 13 -#define SH_PI_GLOBAL_TABLE_NI_SEL1_MASK 0x0000000000002000 - -/* SH_PI_GLOBAL_TABLE_VALID */ -/* Description: Indicates that this entry is valid */ -#define SH_PI_GLOBAL_TABLE_VALID_SHFT 63 -#define SH_PI_GLOBAL_TABLE_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_OVER_RIDE_TABLE" */ -/* If enabled, bypass the Global/Local tables */ -/* ==================================================================== */ - -#define SH_PI_OVER_RIDE_TABLE 0x0000000150021480 -#define SH_PI_OVER_RIDE_TABLE_MASK 0x8000000000003f3f -#define SH_PI_OVER_RIDE_TABLE_INIT 0x8000000000002000 - -/* SH_PI_OVER_RIDE_TABLE_DIR0 */ -/* Description: Direction field for next chip */ -#define SH_PI_OVER_RIDE_TABLE_DIR0_SHFT 0 -#define SH_PI_OVER_RIDE_TABLE_DIR0_MASK 0x000000000000000f - -/* SH_PI_OVER_RIDE_TABLE_V0 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_PI_OVER_RIDE_TABLE_V0_SHFT 4 -#define SH_PI_OVER_RIDE_TABLE_V0_MASK 0x0000000000000010 - -/* SH_PI_OVER_RIDE_TABLE_NI_SEL0 */ -/* Description: ni select */ -#define SH_PI_OVER_RIDE_TABLE_NI_SEL0_SHFT 5 -#define SH_PI_OVER_RIDE_TABLE_NI_SEL0_MASK 0x0000000000000020 - -/* SH_PI_OVER_RIDE_TABLE_DIR1 */ -#define SH_PI_OVER_RIDE_TABLE_DIR1_SHFT 8 -#define SH_PI_OVER_RIDE_TABLE_DIR1_MASK 0x0000000000000f00 - -/* SH_PI_OVER_RIDE_TABLE_V1 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_PI_OVER_RIDE_TABLE_V1_SHFT 12 -#define SH_PI_OVER_RIDE_TABLE_V1_MASK 0x0000000000001000 - -/* SH_PI_OVER_RIDE_TABLE_NI_SEL1 */ -/* Description: ni select */ -#define SH_PI_OVER_RIDE_TABLE_NI_SEL1_SHFT 13 -#define SH_PI_OVER_RIDE_TABLE_NI_SEL1_MASK 0x0000000000002000 - -/* SH_PI_OVER_RIDE_TABLE_ENABLE */ -/* Description: Indicates that this entry is enabled */ -#define SH_PI_OVER_RIDE_TABLE_ENABLE_SHFT 63 -#define SH_PI_OVER_RIDE_TABLE_ENABLE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_RSP_PLANE_HINT" */ -/* If enabled, invert incoming response only plane hint bit before lo */ -/* ==================================================================== */ - -#define SH_PI_RSP_PLANE_HINT 0x0000000150021488 -#define SH_PI_RSP_PLANE_HINT_MASK 0x0000000000000001 -#define SH_PI_RSP_PLANE_HINT_INIT 0x0000000000000000 - -/* SH_PI_RSP_PLANE_HINT_INVERT */ -/* Description: Invert Response Plane Hint */ -#define SH_PI_RSP_PLANE_HINT_INVERT_SHFT 0 -#define SH_PI_RSP_PLANE_HINT_INVERT_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_NI0_LOCAL_TABLE" */ -/* local lookup table */ -/* ==================================================================== */ - -#define SH_NI0_LOCAL_TABLE 0x0000000150022000 -#define SH_NI0_LOCAL_TABLE_MASK 0x800000000000001f -#define SH_NI0_LOCAL_TABLE_MEMDEPTH 128 -#define SH_NI0_LOCAL_TABLE_INIT 0x0000000000000000 - -/* SH_NI0_LOCAL_TABLE_DIR0 */ -/* Description: Direction field for next chip */ -#define SH_NI0_LOCAL_TABLE_DIR0_SHFT 0 -#define SH_NI0_LOCAL_TABLE_DIR0_MASK 0x000000000000000f - -/* SH_NI0_LOCAL_TABLE_V0 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_NI0_LOCAL_TABLE_V0_SHFT 4 -#define SH_NI0_LOCAL_TABLE_V0_MASK 0x0000000000000010 - -/* SH_NI0_LOCAL_TABLE_VALID */ -/* Description: Indicates that this entry is valid */ -#define SH_NI0_LOCAL_TABLE_VALID_SHFT 63 -#define SH_NI0_LOCAL_TABLE_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI0_GLOBAL_TABLE" */ -/* global lookup table */ -/* ==================================================================== */ - -#define SH_NI0_GLOBAL_TABLE 0x0000000150022400 -#define SH_NI0_GLOBAL_TABLE_MASK 0x800000000000001f -#define SH_NI0_GLOBAL_TABLE_MEMDEPTH 16 -#define SH_NI0_GLOBAL_TABLE_INIT 0x0000000000000000 - -/* SH_NI0_GLOBAL_TABLE_DIR0 */ -/* Description: Direction field for next chip */ -#define SH_NI0_GLOBAL_TABLE_DIR0_SHFT 0 -#define SH_NI0_GLOBAL_TABLE_DIR0_MASK 0x000000000000000f - -/* SH_NI0_GLOBAL_TABLE_V0 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_NI0_GLOBAL_TABLE_V0_SHFT 4 -#define SH_NI0_GLOBAL_TABLE_V0_MASK 0x0000000000000010 - -/* SH_NI0_GLOBAL_TABLE_VALID */ -/* Description: Indicates that this entry is valid */ -#define SH_NI0_GLOBAL_TABLE_VALID_SHFT 63 -#define SH_NI0_GLOBAL_TABLE_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI0_OVER_RIDE_TABLE" */ -/* If enabled, bypass the Global/Local tables */ -/* ==================================================================== */ - -#define SH_NI0_OVER_RIDE_TABLE 0x0000000150022480 -#define SH_NI0_OVER_RIDE_TABLE_MASK 0x800000000000001f -#define SH_NI0_OVER_RIDE_TABLE_INIT 0x8000000000000000 - -/* SH_NI0_OVER_RIDE_TABLE_DIR0 */ -/* Description: Direction field for next chip */ -#define SH_NI0_OVER_RIDE_TABLE_DIR0_SHFT 0 -#define SH_NI0_OVER_RIDE_TABLE_DIR0_MASK 0x000000000000000f - -/* SH_NI0_OVER_RIDE_TABLE_V0 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_NI0_OVER_RIDE_TABLE_V0_SHFT 4 -#define SH_NI0_OVER_RIDE_TABLE_V0_MASK 0x0000000000000010 - -/* SH_NI0_OVER_RIDE_TABLE_ENABLE */ -/* Description: Indicates that this entry is enabled */ -#define SH_NI0_OVER_RIDE_TABLE_ENABLE_SHFT 63 -#define SH_NI0_OVER_RIDE_TABLE_ENABLE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI0_RSP_PLANE_HINT" */ -/* If enabled, invert incoming response only plane hint bit before lo */ -/* ==================================================================== */ - -#define SH_NI0_RSP_PLANE_HINT 0x0000000150022488 -#define SH_NI0_RSP_PLANE_HINT_MASK 0x0000000000000000 -#define SH_NI0_RSP_PLANE_HINT_INIT 0x0000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI1_LOCAL_TABLE" */ -/* local lookup table */ -/* ==================================================================== */ - -#define SH_NI1_LOCAL_TABLE 0x0000000150023000 -#define SH_NI1_LOCAL_TABLE_MASK 0x800000000000001f -#define SH_NI1_LOCAL_TABLE_MEMDEPTH 128 -#define SH_NI1_LOCAL_TABLE_INIT 0x0000000000000000 - -/* SH_NI1_LOCAL_TABLE_DIR0 */ -/* Description: Direction field for next chip */ -#define SH_NI1_LOCAL_TABLE_DIR0_SHFT 0 -#define SH_NI1_LOCAL_TABLE_DIR0_MASK 0x000000000000000f - -/* SH_NI1_LOCAL_TABLE_V0 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_NI1_LOCAL_TABLE_V0_SHFT 4 -#define SH_NI1_LOCAL_TABLE_V0_MASK 0x0000000000000010 - -/* SH_NI1_LOCAL_TABLE_VALID */ -/* Description: Indicates that this entry is valid */ -#define SH_NI1_LOCAL_TABLE_VALID_SHFT 63 -#define SH_NI1_LOCAL_TABLE_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI1_GLOBAL_TABLE" */ -/* global lookup table */ -/* ==================================================================== */ - -#define SH_NI1_GLOBAL_TABLE 0x0000000150023400 -#define SH_NI1_GLOBAL_TABLE_MASK 0x800000000000001f -#define SH_NI1_GLOBAL_TABLE_MEMDEPTH 16 -#define SH_NI1_GLOBAL_TABLE_INIT 0x0000000000000000 - -/* SH_NI1_GLOBAL_TABLE_DIR0 */ -/* Description: Direction field for next chip */ -#define SH_NI1_GLOBAL_TABLE_DIR0_SHFT 0 -#define SH_NI1_GLOBAL_TABLE_DIR0_MASK 0x000000000000000f - -/* SH_NI1_GLOBAL_TABLE_V0 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_NI1_GLOBAL_TABLE_V0_SHFT 4 -#define SH_NI1_GLOBAL_TABLE_V0_MASK 0x0000000000000010 - -/* SH_NI1_GLOBAL_TABLE_VALID */ -/* Description: Indicates that this entry is valid */ -#define SH_NI1_GLOBAL_TABLE_VALID_SHFT 63 -#define SH_NI1_GLOBAL_TABLE_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI1_OVER_RIDE_TABLE" */ -/* If enabled, bypass the Global/Local tables */ -/* ==================================================================== */ - -#define SH_NI1_OVER_RIDE_TABLE 0x0000000150023480 -#define SH_NI1_OVER_RIDE_TABLE_MASK 0x800000000000001f -#define SH_NI1_OVER_RIDE_TABLE_INIT 0x8000000000000000 - -/* SH_NI1_OVER_RIDE_TABLE_DIR0 */ -/* Description: Direction field for next chip */ -#define SH_NI1_OVER_RIDE_TABLE_DIR0_SHFT 0 -#define SH_NI1_OVER_RIDE_TABLE_DIR0_MASK 0x000000000000000f - -/* SH_NI1_OVER_RIDE_TABLE_V0 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_NI1_OVER_RIDE_TABLE_V0_SHFT 4 -#define SH_NI1_OVER_RIDE_TABLE_V0_MASK 0x0000000000000010 - -/* SH_NI1_OVER_RIDE_TABLE_ENABLE */ -/* Description: Indicates that this entry is enabled */ -#define SH_NI1_OVER_RIDE_TABLE_ENABLE_SHFT 63 -#define SH_NI1_OVER_RIDE_TABLE_ENABLE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI1_RSP_PLANE_HINT" */ -/* If enabled, invert incoming response only plane hint bit before lo */ -/* ==================================================================== */ - -#define SH_NI1_RSP_PLANE_HINT 0x0000000150023488 -#define SH_NI1_RSP_PLANE_HINT_MASK 0x0000000000000000 -#define SH_NI1_RSP_PLANE_HINT_INIT 0x0000000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_LOCAL_TABLE" */ -/* local lookup table */ -/* ==================================================================== */ - -#define SH_MD_LOCAL_TABLE 0x0000000150024000 -#define SH_MD_LOCAL_TABLE_MASK 0x8000000000003f3f -#define SH_MD_LOCAL_TABLE_MEMDEPTH 128 -#define SH_MD_LOCAL_TABLE_INIT 0x0000000000000000 - -/* SH_MD_LOCAL_TABLE_DIR0 */ -/* Description: Direction field for next chip */ -#define SH_MD_LOCAL_TABLE_DIR0_SHFT 0 -#define SH_MD_LOCAL_TABLE_DIR0_MASK 0x000000000000000f - -/* SH_MD_LOCAL_TABLE_V0 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_MD_LOCAL_TABLE_V0_SHFT 4 -#define SH_MD_LOCAL_TABLE_V0_MASK 0x0000000000000010 - -/* SH_MD_LOCAL_TABLE_NI_SEL0 */ -/* Description: ni select for requests */ -#define SH_MD_LOCAL_TABLE_NI_SEL0_SHFT 5 -#define SH_MD_LOCAL_TABLE_NI_SEL0_MASK 0x0000000000000020 - -/* SH_MD_LOCAL_TABLE_DIR1 */ -#define SH_MD_LOCAL_TABLE_DIR1_SHFT 8 -#define SH_MD_LOCAL_TABLE_DIR1_MASK 0x0000000000000f00 - -/* SH_MD_LOCAL_TABLE_V1 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_MD_LOCAL_TABLE_V1_SHFT 12 -#define SH_MD_LOCAL_TABLE_V1_MASK 0x0000000000001000 - -/* SH_MD_LOCAL_TABLE_NI_SEL1 */ -/* Description: ni select for plane-hint 1 */ -#define SH_MD_LOCAL_TABLE_NI_SEL1_SHFT 13 -#define SH_MD_LOCAL_TABLE_NI_SEL1_MASK 0x0000000000002000 - -/* SH_MD_LOCAL_TABLE_VALID */ -/* Description: Indicates that this entry is valid */ -#define SH_MD_LOCAL_TABLE_VALID_SHFT 63 -#define SH_MD_LOCAL_TABLE_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_GLOBAL_TABLE" */ -/* global lookup table */ -/* ==================================================================== */ - -#define SH_MD_GLOBAL_TABLE 0x0000000150024400 -#define SH_MD_GLOBAL_TABLE_MASK 0x8000000000003f3f -#define SH_MD_GLOBAL_TABLE_MEMDEPTH 16 -#define SH_MD_GLOBAL_TABLE_INIT 0x0000000000000000 - -/* SH_MD_GLOBAL_TABLE_DIR0 */ -/* Description: Direction field for next chip */ -#define SH_MD_GLOBAL_TABLE_DIR0_SHFT 0 -#define SH_MD_GLOBAL_TABLE_DIR0_MASK 0x000000000000000f - -/* SH_MD_GLOBAL_TABLE_V0 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_MD_GLOBAL_TABLE_V0_SHFT 4 -#define SH_MD_GLOBAL_TABLE_V0_MASK 0x0000000000000010 - -/* SH_MD_GLOBAL_TABLE_NI_SEL0 */ -/* Description: ni select for requests */ -#define SH_MD_GLOBAL_TABLE_NI_SEL0_SHFT 5 -#define SH_MD_GLOBAL_TABLE_NI_SEL0_MASK 0x0000000000000020 - -/* SH_MD_GLOBAL_TABLE_DIR1 */ -#define SH_MD_GLOBAL_TABLE_DIR1_SHFT 8 -#define SH_MD_GLOBAL_TABLE_DIR1_MASK 0x0000000000000f00 - -/* SH_MD_GLOBAL_TABLE_V1 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_MD_GLOBAL_TABLE_V1_SHFT 12 -#define SH_MD_GLOBAL_TABLE_V1_MASK 0x0000000000001000 - -/* SH_MD_GLOBAL_TABLE_NI_SEL1 */ -/* Description: ni select for plane-hint 1 */ -#define SH_MD_GLOBAL_TABLE_NI_SEL1_SHFT 13 -#define SH_MD_GLOBAL_TABLE_NI_SEL1_MASK 0x0000000000002000 - -/* SH_MD_GLOBAL_TABLE_VALID */ -/* Description: Indicates that this entry is valid */ -#define SH_MD_GLOBAL_TABLE_VALID_SHFT 63 -#define SH_MD_GLOBAL_TABLE_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_OVER_RIDE_TABLE" */ -/* If enabled, bypass the Global/Local tables */ -/* ==================================================================== */ - -#define SH_MD_OVER_RIDE_TABLE 0x0000000150024480 -#define SH_MD_OVER_RIDE_TABLE_MASK 0x8000000000003f3f -#define SH_MD_OVER_RIDE_TABLE_INIT 0x8000000000002000 - -/* SH_MD_OVER_RIDE_TABLE_DIR0 */ -/* Description: Direction field for next chip */ -#define SH_MD_OVER_RIDE_TABLE_DIR0_SHFT 0 -#define SH_MD_OVER_RIDE_TABLE_DIR0_MASK 0x000000000000000f - -/* SH_MD_OVER_RIDE_TABLE_V0 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_MD_OVER_RIDE_TABLE_V0_SHFT 4 -#define SH_MD_OVER_RIDE_TABLE_V0_MASK 0x0000000000000010 - -/* SH_MD_OVER_RIDE_TABLE_NI_SEL0 */ -/* Description: ni select */ -#define SH_MD_OVER_RIDE_TABLE_NI_SEL0_SHFT 5 -#define SH_MD_OVER_RIDE_TABLE_NI_SEL0_MASK 0x0000000000000020 - -/* SH_MD_OVER_RIDE_TABLE_DIR1 */ -#define SH_MD_OVER_RIDE_TABLE_DIR1_SHFT 8 -#define SH_MD_OVER_RIDE_TABLE_DIR1_MASK 0x0000000000000f00 - -/* SH_MD_OVER_RIDE_TABLE_V1 */ -/* Description: Low bit of virtual channel for next chip */ -#define SH_MD_OVER_RIDE_TABLE_V1_SHFT 12 -#define SH_MD_OVER_RIDE_TABLE_V1_MASK 0x0000000000001000 - -/* SH_MD_OVER_RIDE_TABLE_NI_SEL1 */ -/* Description: ni select */ -#define SH_MD_OVER_RIDE_TABLE_NI_SEL1_SHFT 13 -#define SH_MD_OVER_RIDE_TABLE_NI_SEL1_MASK 0x0000000000002000 - -/* SH_MD_OVER_RIDE_TABLE_ENABLE */ -/* Description: Indicates that this entry is enabled */ -#define SH_MD_OVER_RIDE_TABLE_ENABLE_SHFT 63 -#define SH_MD_OVER_RIDE_TABLE_ENABLE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_RSP_PLANE_HINT" */ -/* If enabled, invert incoming response only plane hint bit before lo */ -/* ==================================================================== */ - -#define SH_MD_RSP_PLANE_HINT 0x0000000150024488 -#define SH_MD_RSP_PLANE_HINT_MASK 0x0000000000000001 -#define SH_MD_RSP_PLANE_HINT_INIT 0x0000000000000000 - -/* SH_MD_RSP_PLANE_HINT_INVERT */ -/* Description: Invert Response Plane Hint */ -#define SH_MD_RSP_PLANE_HINT_INVERT_SHFT 0 -#define SH_MD_RSP_PLANE_HINT_INVERT_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_LB_LIQ_CTL" */ -/* Local Block LIQ Control */ -/* ==================================================================== */ - -#define SH_LB_LIQ_CTL 0x0000000110040000 -#define SH_LB_LIQ_CTL_MASK 0x0000000000070f1f -#define SH_LB_LIQ_CTL_INIT 0x0000000000000000 - -/* SH_LB_LIQ_CTL_LIQ_REQ_CTL */ -/* Description: LIQ Request Control */ -#define SH_LB_LIQ_CTL_LIQ_REQ_CTL_SHFT 0 -#define SH_LB_LIQ_CTL_LIQ_REQ_CTL_MASK 0x000000000000001f - -/* SH_LB_LIQ_CTL_LIQ_RPL_CTL */ -/* Description: LIQ Reply Control */ -#define SH_LB_LIQ_CTL_LIQ_RPL_CTL_SHFT 8 -#define SH_LB_LIQ_CTL_LIQ_RPL_CTL_MASK 0x0000000000000f00 - -/* SH_LB_LIQ_CTL_FORCE_RQ_CREDIT */ -/* Description: Force request credit */ -#define SH_LB_LIQ_CTL_FORCE_RQ_CREDIT_SHFT 16 -#define SH_LB_LIQ_CTL_FORCE_RQ_CREDIT_MASK 0x0000000000010000 - -/* SH_LB_LIQ_CTL_FORCE_RP_CREDIT */ -/* Description: Force reply credit */ -#define SH_LB_LIQ_CTL_FORCE_RP_CREDIT_SHFT 17 -#define SH_LB_LIQ_CTL_FORCE_RP_CREDIT_MASK 0x0000000000020000 - -/* SH_LB_LIQ_CTL_FORCE_LINVV_CREDIT */ -/* Description: Force linvv credit */ -#define SH_LB_LIQ_CTL_FORCE_LINVV_CREDIT_SHFT 18 -#define SH_LB_LIQ_CTL_FORCE_LINVV_CREDIT_MASK 0x0000000000040000 - -/* ==================================================================== */ -/* Register "SH_LB_LOQ_CTL" */ -/* Local Block LOQ Control */ -/* ==================================================================== */ - -#define SH_LB_LOQ_CTL 0x0000000110040080 -#define SH_LB_LOQ_CTL_MASK 0x0000000000000003 -#define SH_LB_LOQ_CTL_INIT 0x0000000000000000 - -/* SH_LB_LOQ_CTL_LOQ_REQ_CTL */ -/* Description: LOQ Request Control */ -#define SH_LB_LOQ_CTL_LOQ_REQ_CTL_SHFT 0 -#define SH_LB_LOQ_CTL_LOQ_REQ_CTL_MASK 0x0000000000000001 - -/* SH_LB_LOQ_CTL_LOQ_RPL_CTL */ -/* Description: LOQ Reply Control */ -#define SH_LB_LOQ_CTL_LOQ_RPL_CTL_SHFT 1 -#define SH_LB_LOQ_CTL_LOQ_RPL_CTL_MASK 0x0000000000000002 - -/* ==================================================================== */ -/* Register "SH_LB_MAX_REP_CREDIT_CNT" */ -/* Maximum number of reply credits from XN */ -/* ==================================================================== */ - -#define SH_LB_MAX_REP_CREDIT_CNT 0x0000000110040100 -#define SH_LB_MAX_REP_CREDIT_CNT_MASK 0x000000000000001f -#define SH_LB_MAX_REP_CREDIT_CNT_INIT 0x000000000000001f - -/* SH_LB_MAX_REP_CREDIT_CNT_MAX_CNT */ -/* Description: Max reply credits */ -#define SH_LB_MAX_REP_CREDIT_CNT_MAX_CNT_SHFT 0 -#define SH_LB_MAX_REP_CREDIT_CNT_MAX_CNT_MASK 0x000000000000001f - -/* ==================================================================== */ -/* Register "SH_LB_MAX_REQ_CREDIT_CNT" */ -/* Maximum number of request credits from XN */ -/* ==================================================================== */ - -#define SH_LB_MAX_REQ_CREDIT_CNT 0x0000000110040180 -#define SH_LB_MAX_REQ_CREDIT_CNT_MASK 0x000000000000001f -#define SH_LB_MAX_REQ_CREDIT_CNT_INIT 0x000000000000001f - -/* SH_LB_MAX_REQ_CREDIT_CNT_MAX_CNT */ -/* Description: Max request credits */ -#define SH_LB_MAX_REQ_CREDIT_CNT_MAX_CNT_SHFT 0 -#define SH_LB_MAX_REQ_CREDIT_CNT_MAX_CNT_MASK 0x000000000000001f - -/* ==================================================================== */ -/* Register "SH_PIO_TIME_OUT" */ -/* Local Block PIO time out value */ -/* ==================================================================== */ - -#define SH_PIO_TIME_OUT 0x0000000110040200 -#define SH_PIO_TIME_OUT_MASK 0x000000000000ffff -#define SH_PIO_TIME_OUT_INIT 0x0000000000000400 - -/* SH_PIO_TIME_OUT_VALUE */ -/* Description: PIO time out value */ -#define SH_PIO_TIME_OUT_VALUE_SHFT 0 -#define SH_PIO_TIME_OUT_VALUE_MASK 0x000000000000ffff - -/* ==================================================================== */ -/* Register "SH_PIO_NACK_RESET" */ -/* Local Block PIO Reset for nack counters */ -/* ==================================================================== */ - -#define SH_PIO_NACK_RESET 0x0000000110040280 -#define SH_PIO_NACK_RESET_MASK 0x0000000000000001 -#define SH_PIO_NACK_RESET_INIT 0x0000000000000000 - -/* SH_PIO_NACK_RESET_PULSE */ -/* Description: PIO nack counter reset */ -#define SH_PIO_NACK_RESET_PULSE_SHFT 0 -#define SH_PIO_NACK_RESET_PULSE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_CONVEYOR_BELT_TIME_OUT" */ -/* Local Block conveyor belt time out value */ -/* ==================================================================== */ - -#define SH_CONVEYOR_BELT_TIME_OUT 0x0000000110040300 -#define SH_CONVEYOR_BELT_TIME_OUT_MASK 0x0000000000000fff -#define SH_CONVEYOR_BELT_TIME_OUT_INIT 0x0000000000000000 - -/* SH_CONVEYOR_BELT_TIME_OUT_VALUE */ -/* Description: Conveyor belt time out value */ -#define SH_CONVEYOR_BELT_TIME_OUT_VALUE_SHFT 0 -#define SH_CONVEYOR_BELT_TIME_OUT_VALUE_MASK 0x0000000000000fff - -/* ==================================================================== */ -/* Register "SH_LB_CREDIT_STATUS" */ -/* Credit Counter Status Register */ -/* ==================================================================== */ - -#define SH_LB_CREDIT_STATUS 0x0000000110050000 -#define SH_LB_CREDIT_STATUS_MASK 0x000000000ffff3df -#define SH_LB_CREDIT_STATUS_INIT 0x0000000000000000 - -/* SH_LB_CREDIT_STATUS_LIQ_RQ_CREDIT */ -/* Description: LIQ request queue credit counter */ -#define SH_LB_CREDIT_STATUS_LIQ_RQ_CREDIT_SHFT 0 -#define SH_LB_CREDIT_STATUS_LIQ_RQ_CREDIT_MASK 0x000000000000001f - -/* SH_LB_CREDIT_STATUS_LIQ_RP_CREDIT */ -/* Description: LIQ reply queue credit counter */ -#define SH_LB_CREDIT_STATUS_LIQ_RP_CREDIT_SHFT 6 -#define SH_LB_CREDIT_STATUS_LIQ_RP_CREDIT_MASK 0x00000000000003c0 - -/* SH_LB_CREDIT_STATUS_LINVV_CREDIT */ -/* Description: LINVV credit counter */ -#define SH_LB_CREDIT_STATUS_LINVV_CREDIT_SHFT 12 -#define SH_LB_CREDIT_STATUS_LINVV_CREDIT_MASK 0x000000000003f000 - -/* SH_LB_CREDIT_STATUS_LOQ_RQ_CREDIT */ -/* Description: LOQ request queue credit counter */ -#define SH_LB_CREDIT_STATUS_LOQ_RQ_CREDIT_SHFT 18 -#define SH_LB_CREDIT_STATUS_LOQ_RQ_CREDIT_MASK 0x00000000007c0000 - -/* SH_LB_CREDIT_STATUS_LOQ_RP_CREDIT */ -/* Description: LOQ reply queue credit counter */ -#define SH_LB_CREDIT_STATUS_LOQ_RP_CREDIT_SHFT 23 -#define SH_LB_CREDIT_STATUS_LOQ_RP_CREDIT_MASK 0x000000000f800000 - -/* ==================================================================== */ -/* Register "SH_LB_DEBUG_LOCAL_SEL" */ -/* LB Debug Port Select */ -/* ==================================================================== */ - -#define SH_LB_DEBUG_LOCAL_SEL 0x0000000110050080 -#define SH_LB_DEBUG_LOCAL_SEL_MASK 0xf777777777777777 -#define SH_LB_DEBUG_LOCAL_SEL_INIT 0x0000000000000000 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_CHIPLET_SEL */ -/* Description: Nibble 0 Chiplet select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_CHIPLET_SEL_SHFT 0 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000007 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_CHIPLET_SEL */ -/* Description: Nibble 1 Chiplet select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_CHIPLET_SEL_SHFT 8 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000700 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_CHIPLET_SEL */ -/* Description: Nibble 2 Chiplet select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_CHIPLET_SEL_SHFT 16 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000070000 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_CHIPLET_SEL */ -/* Description: Nibble 3 Chiplet select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_CHIPLET_SEL_SHFT 24 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_CHIPLET_SEL_MASK 0x0000000007000000 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_CHIPLET_SEL */ -/* Description: Nibble 4 Chiplet select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_CHIPLET_SEL_SHFT 32 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_CHIPLET_SEL_MASK 0x0000000700000000 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_CHIPLET_SEL */ -/* Description: Nibble 5 Chiplet select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_CHIPLET_SEL_SHFT 40 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_CHIPLET_SEL_MASK 0x0000070000000000 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_CHIPLET_SEL */ -/* Description: Nibble 6 Chiplet select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_CHIPLET_SEL_SHFT 48 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_CHIPLET_SEL_MASK 0x0007000000000000 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_CHIPLET_SEL */ -/* Description: Nibble 7 Chiplet select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_CHIPLET_SEL_SHFT 56 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_CHIPLET_SEL_MASK 0x0700000000000000 - -/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60 -#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* SH_LB_DEBUG_LOCAL_SEL_TRIGGER_ENABLE */ -/* Description: Enable trigger on bit 32 of Analyzer data */ -#define SH_LB_DEBUG_LOCAL_SEL_TRIGGER_ENABLE_SHFT 63 -#define SH_LB_DEBUG_LOCAL_SEL_TRIGGER_ENABLE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_LB_DEBUG_PERF_SEL" */ -/* LB Debug Port Performance Select */ -/* ==================================================================== */ - -#define SH_LB_DEBUG_PERF_SEL 0x0000000110050100 -#define SH_LB_DEBUG_PERF_SEL_MASK 0x7777777777777777 -#define SH_LB_DEBUG_PERF_SEL_INIT 0x0000000000000000 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE0_CHIPLET_SEL */ -/* Description: Nibble 0 Chiplet select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE0_CHIPLET_SEL_SHFT 0 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000007 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE1_CHIPLET_SEL */ -/* Description: Nibble 1 Chiplet select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE1_CHIPLET_SEL_SHFT 8 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000700 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE2_CHIPLET_SEL */ -/* Description: Nibble 2 Chiplet select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE2_CHIPLET_SEL_SHFT 16 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000070000 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE3_CHIPLET_SEL */ -/* Description: Nibble 3 Chiplet select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE3_CHIPLET_SEL_SHFT 24 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE3_CHIPLET_SEL_MASK 0x0000000007000000 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE4_CHIPLET_SEL */ -/* Description: Nibble 4 Chiplet select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE4_CHIPLET_SEL_SHFT 32 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE4_CHIPLET_SEL_MASK 0x0000000700000000 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE5_CHIPLET_SEL */ -/* Description: Nibble 5 Chiplet select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE5_CHIPLET_SEL_SHFT 40 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE5_CHIPLET_SEL_MASK 0x0000070000000000 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE6_CHIPLET_SEL */ -/* Description: Nibble 6 Chiplet select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE6_CHIPLET_SEL_SHFT 48 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE6_CHIPLET_SEL_MASK 0x0007000000000000 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE7_CHIPLET_SEL */ -/* Description: Nibble 7 Chiplet select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE7_CHIPLET_SEL_SHFT 56 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE7_CHIPLET_SEL_MASK 0x0700000000000000 - -/* SH_LB_DEBUG_PERF_SEL_NIBBLE7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_LB_DEBUG_PERF_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60 -#define SH_LB_DEBUG_PERF_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* ==================================================================== */ -/* Register "SH_LB_DEBUG_TRIG_SEL" */ -/* LB Debug Trigger Select */ -/* ==================================================================== */ - -#define SH_LB_DEBUG_TRIG_SEL 0x0000000110050180 -#define SH_LB_DEBUG_TRIG_SEL_MASK 0x7777777777777777 -#define SH_LB_DEBUG_TRIG_SEL_INIT 0x0000000000000000 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER0_CHIPLET_SEL */ -/* Description: Nibble 0 Chiplet select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER0_CHIPLET_SEL_SHFT 0 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER0_CHIPLET_SEL_MASK 0x0000000000000007 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL_SHFT 4 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER1_CHIPLET_SEL */ -/* Description: Nibble 1 Chiplet select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER1_CHIPLET_SEL_SHFT 8 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER1_CHIPLET_SEL_MASK 0x0000000000000700 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL_SHFT 12 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER2_CHIPLET_SEL */ -/* Description: Nibble 2 Chiplet select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER2_CHIPLET_SEL_SHFT 16 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER2_CHIPLET_SEL_MASK 0x0000000000070000 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL_SHFT 20 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER3_CHIPLET_SEL */ -/* Description: Nibble 3 Chiplet select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER3_CHIPLET_SEL_SHFT 24 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER3_CHIPLET_SEL_MASK 0x0000000007000000 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL_SHFT 28 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER4_CHIPLET_SEL */ -/* Description: Nibble 4 Chiplet select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER4_CHIPLET_SEL_SHFT 32 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER4_CHIPLET_SEL_MASK 0x0000000700000000 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL_SHFT 36 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER5_CHIPLET_SEL */ -/* Description: Nibble 5 Chiplet select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER5_CHIPLET_SEL_SHFT 40 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER5_CHIPLET_SEL_MASK 0x0000070000000000 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL_SHFT 44 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER6_CHIPLET_SEL */ -/* Description: Nibble 6 Chiplet select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER6_CHIPLET_SEL_SHFT 48 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER6_CHIPLET_SEL_MASK 0x0007000000000000 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL_SHFT 52 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER7_CHIPLET_SEL */ -/* Description: Nibble 7 Chiplet select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER7_CHIPLET_SEL_SHFT 56 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER7_CHIPLET_SEL_MASK 0x0700000000000000 - -/* SH_LB_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL_SHFT 60 -#define SH_LB_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* ==================================================================== */ -/* Register "SH_LB_ERROR_DETAIL_1" */ -/* LB Error capture information: HDR1 */ -/* ==================================================================== */ - -#define SH_LB_ERROR_DETAIL_1 0x0000000110050200 -#define SH_LB_ERROR_DETAIL_1_MASK 0x8003073fff3fffff -#define SH_LB_ERROR_DETAIL_1_INIT 0x0000000000000000 - -/* SH_LB_ERROR_DETAIL_1_COMMAND */ -/* Description: COMMAND */ -#define SH_LB_ERROR_DETAIL_1_COMMAND_SHFT 0 -#define SH_LB_ERROR_DETAIL_1_COMMAND_MASK 0x00000000000000ff - -/* SH_LB_ERROR_DETAIL_1_SUPPL */ -/* Description: SUPPLMENTAL */ -#define SH_LB_ERROR_DETAIL_1_SUPPL_SHFT 8 -#define SH_LB_ERROR_DETAIL_1_SUPPL_MASK 0x00000000003fff00 - -/* SH_LB_ERROR_DETAIL_1_SOURCE */ -/* Description: SOURCE */ -#define SH_LB_ERROR_DETAIL_1_SOURCE_SHFT 24 -#define SH_LB_ERROR_DETAIL_1_SOURCE_MASK 0x0000003fff000000 - -/* SH_LB_ERROR_DETAIL_1_DEST */ -/* Description: DEST */ -#define SH_LB_ERROR_DETAIL_1_DEST_SHFT 40 -#define SH_LB_ERROR_DETAIL_1_DEST_MASK 0x0000070000000000 - -/* SH_LB_ERROR_DETAIL_1_HDR_ERR */ -/* Description: HDR_ERR */ -#define SH_LB_ERROR_DETAIL_1_HDR_ERR_SHFT 48 -#define SH_LB_ERROR_DETAIL_1_HDR_ERR_MASK 0x0001000000000000 - -/* SH_LB_ERROR_DETAIL_1_DATA_ERR */ -/* Description: DATA_ERR */ -#define SH_LB_ERROR_DETAIL_1_DATA_ERR_SHFT 49 -#define SH_LB_ERROR_DETAIL_1_DATA_ERR_MASK 0x0002000000000000 - -/* SH_LB_ERROR_DETAIL_1_VALID */ -/* Description: VALID */ -#define SH_LB_ERROR_DETAIL_1_VALID_SHFT 63 -#define SH_LB_ERROR_DETAIL_1_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_LB_ERROR_DETAIL_2" */ -/* LB Error Bits */ -/* ==================================================================== */ - -#define SH_LB_ERROR_DETAIL_2 0x0000000110050280 -#define SH_LB_ERROR_DETAIL_2_MASK 0x00007fffffffffff -#define SH_LB_ERROR_DETAIL_2_INIT 0x0000000000000000 - -/* SH_LB_ERROR_DETAIL_2_ADDRESS */ -/* Description: ADDRESS */ -#define SH_LB_ERROR_DETAIL_2_ADDRESS_SHFT 0 -#define SH_LB_ERROR_DETAIL_2_ADDRESS_MASK 0x00007fffffffffff - -/* ==================================================================== */ -/* Register "SH_LB_ERROR_DETAIL_3" */ -/* LB Error Bits */ -/* ==================================================================== */ - -#define SH_LB_ERROR_DETAIL_3 0x0000000110050300 -#define SH_LB_ERROR_DETAIL_3_MASK 0xffffffffffffffff -#define SH_LB_ERROR_DETAIL_3_INIT 0x0000000000000000 - -/* SH_LB_ERROR_DETAIL_3_DATA */ -/* Description: DATA */ -#define SH_LB_ERROR_DETAIL_3_DATA_SHFT 0 -#define SH_LB_ERROR_DETAIL_3_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_LB_ERROR_DETAIL_4" */ -/* LB Error Bits */ -/* ==================================================================== */ - -#define SH_LB_ERROR_DETAIL_4 0x0000000110050380 -#define SH_LB_ERROR_DETAIL_4_MASK 0xffffffffffffffff -#define SH_LB_ERROR_DETAIL_4_INIT 0x0000000000000000 - -/* SH_LB_ERROR_DETAIL_4_ROUTE */ -/* Description: ROUTE */ -#define SH_LB_ERROR_DETAIL_4_ROUTE_SHFT 0 -#define SH_LB_ERROR_DETAIL_4_ROUTE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_LB_ERROR_DETAIL_5" */ -/* LB Error Bits */ -/* ==================================================================== */ - -#define SH_LB_ERROR_DETAIL_5 0x0000000110050400 -#define SH_LB_ERROR_DETAIL_5_MASK 0x000000000000007f -#define SH_LB_ERROR_DETAIL_5_INIT 0x0000000000000000 - -/* SH_LB_ERROR_DETAIL_5_READ_RETRY */ -/* Description: Read retry error */ -#define SH_LB_ERROR_DETAIL_5_READ_RETRY_SHFT 0 -#define SH_LB_ERROR_DETAIL_5_READ_RETRY_MASK 0x0000000000000001 - -/* SH_LB_ERROR_DETAIL_5_PTC1_WRITE */ -/* Description: PTC1 write error */ -#define SH_LB_ERROR_DETAIL_5_PTC1_WRITE_SHFT 1 -#define SH_LB_ERROR_DETAIL_5_PTC1_WRITE_MASK 0x0000000000000002 - -/* SH_LB_ERROR_DETAIL_5_WRITE_RETRY */ -/* Description: Write retry error */ -#define SH_LB_ERROR_DETAIL_5_WRITE_RETRY_SHFT 2 -#define SH_LB_ERROR_DETAIL_5_WRITE_RETRY_MASK 0x0000000000000004 - -/* SH_LB_ERROR_DETAIL_5_COUNT_A_OVERFLOW */ -/* Description: Nack A counter overflow error */ -#define SH_LB_ERROR_DETAIL_5_COUNT_A_OVERFLOW_SHFT 3 -#define SH_LB_ERROR_DETAIL_5_COUNT_A_OVERFLOW_MASK 0x0000000000000008 - -/* SH_LB_ERROR_DETAIL_5_COUNT_B_OVERFLOW */ -/* Description: Nack B counter overflow error */ -#define SH_LB_ERROR_DETAIL_5_COUNT_B_OVERFLOW_SHFT 4 -#define SH_LB_ERROR_DETAIL_5_COUNT_B_OVERFLOW_MASK 0x0000000000000010 - -/* SH_LB_ERROR_DETAIL_5_NACK_A_TIMEOUT */ -/* Description: Nack A counter timeout error */ -#define SH_LB_ERROR_DETAIL_5_NACK_A_TIMEOUT_SHFT 5 -#define SH_LB_ERROR_DETAIL_5_NACK_A_TIMEOUT_MASK 0x0000000000000020 - -/* SH_LB_ERROR_DETAIL_5_NACK_B_TIMEOUT */ -/* Description: Nack B counter timeout error */ -#define SH_LB_ERROR_DETAIL_5_NACK_B_TIMEOUT_SHFT 6 -#define SH_LB_ERROR_DETAIL_5_NACK_B_TIMEOUT_MASK 0x0000000000000040 - -/* ==================================================================== */ -/* Register "SH_LB_ERROR_MASK" */ -/* LB Error Mask */ -/* ==================================================================== */ - -#define SH_LB_ERROR_MASK 0x0000000110050480 -#define SH_LB_ERROR_MASK_MASK 0x00000000007fffff -#define SH_LB_ERROR_MASK_INIT 0x00000000007fffff - -/* SH_LB_ERROR_MASK_RQ_BAD_CMD */ -/* Description: RQ_BAD_CMD */ -#define SH_LB_ERROR_MASK_RQ_BAD_CMD_SHFT 0 -#define SH_LB_ERROR_MASK_RQ_BAD_CMD_MASK 0x0000000000000001 - -/* SH_LB_ERROR_MASK_RP_BAD_CMD */ -/* Description: RP_BAD_CMD */ -#define SH_LB_ERROR_MASK_RP_BAD_CMD_SHFT 1 -#define SH_LB_ERROR_MASK_RP_BAD_CMD_MASK 0x0000000000000002 - -/* SH_LB_ERROR_MASK_RQ_SHORT */ -/* Description: RQ_SHORT */ -#define SH_LB_ERROR_MASK_RQ_SHORT_SHFT 2 -#define SH_LB_ERROR_MASK_RQ_SHORT_MASK 0x0000000000000004 - -/* SH_LB_ERROR_MASK_RP_SHORT */ -/* Description: RP_SHORT */ -#define SH_LB_ERROR_MASK_RP_SHORT_SHFT 3 -#define SH_LB_ERROR_MASK_RP_SHORT_MASK 0x0000000000000008 - -/* SH_LB_ERROR_MASK_RQ_LONG */ -/* Description: RQ_LONG */ -#define SH_LB_ERROR_MASK_RQ_LONG_SHFT 4 -#define SH_LB_ERROR_MASK_RQ_LONG_MASK 0x0000000000000010 - -/* SH_LB_ERROR_MASK_RP_LONG */ -/* Description: RP_LONG */ -#define SH_LB_ERROR_MASK_RP_LONG_SHFT 5 -#define SH_LB_ERROR_MASK_RP_LONG_MASK 0x0000000000000020 - -/* SH_LB_ERROR_MASK_RQ_BAD_DATA */ -/* Description: RQ_BAD_DATA */ -#define SH_LB_ERROR_MASK_RQ_BAD_DATA_SHFT 6 -#define SH_LB_ERROR_MASK_RQ_BAD_DATA_MASK 0x0000000000000040 - -/* SH_LB_ERROR_MASK_RP_BAD_DATA */ -/* Description: RP_BAD_DATA */ -#define SH_LB_ERROR_MASK_RP_BAD_DATA_SHFT 7 -#define SH_LB_ERROR_MASK_RP_BAD_DATA_MASK 0x0000000000000080 - -/* SH_LB_ERROR_MASK_RQ_BAD_ADDR */ -/* Description: RQ_BAD_ADDR */ -#define SH_LB_ERROR_MASK_RQ_BAD_ADDR_SHFT 8 -#define SH_LB_ERROR_MASK_RQ_BAD_ADDR_MASK 0x0000000000000100 - -/* SH_LB_ERROR_MASK_RQ_TIME_OUT */ -/* Description: RQ_TIME_OUT */ -#define SH_LB_ERROR_MASK_RQ_TIME_OUT_SHFT 9 -#define SH_LB_ERROR_MASK_RQ_TIME_OUT_MASK 0x0000000000000200 - -/* SH_LB_ERROR_MASK_LINVV_OVERFLOW */ -/* Description: LINVV_OVERFLOW */ -#define SH_LB_ERROR_MASK_LINVV_OVERFLOW_SHFT 10 -#define SH_LB_ERROR_MASK_LINVV_OVERFLOW_MASK 0x0000000000000400 - -/* SH_LB_ERROR_MASK_UNEXPECTED_LINV */ -/* Description: UNEXPECTED_LINV */ -#define SH_LB_ERROR_MASK_UNEXPECTED_LINV_SHFT 11 -#define SH_LB_ERROR_MASK_UNEXPECTED_LINV_MASK 0x0000000000000800 - -/* SH_LB_ERROR_MASK_PTC_1_TIMEOUT */ -/* Description: PTC_1 Time out */ -#define SH_LB_ERROR_MASK_PTC_1_TIMEOUT_SHFT 12 -#define SH_LB_ERROR_MASK_PTC_1_TIMEOUT_MASK 0x0000000000001000 - -/* SH_LB_ERROR_MASK_JUNK_BUS_ERR */ -/* Description: Junk Bus error */ -#define SH_LB_ERROR_MASK_JUNK_BUS_ERR_SHFT 13 -#define SH_LB_ERROR_MASK_JUNK_BUS_ERR_MASK 0x0000000000002000 - -/* SH_LB_ERROR_MASK_PIO_CB_ERR */ -/* Description: PIO Conveyor Belt operation error */ -#define SH_LB_ERROR_MASK_PIO_CB_ERR_SHFT 14 -#define SH_LB_ERROR_MASK_PIO_CB_ERR_MASK 0x0000000000004000 - -/* SH_LB_ERROR_MASK_VECTOR_RQ_ROUTE_ERROR */ -/* Description: Vector request Route data was invalid */ -#define SH_LB_ERROR_MASK_VECTOR_RQ_ROUTE_ERROR_SHFT 15 -#define SH_LB_ERROR_MASK_VECTOR_RQ_ROUTE_ERROR_MASK 0x0000000000008000 - -/* SH_LB_ERROR_MASK_VECTOR_RP_ROUTE_ERROR */ -/* Description: Vector reply Route data was invalid */ -#define SH_LB_ERROR_MASK_VECTOR_RP_ROUTE_ERROR_SHFT 16 -#define SH_LB_ERROR_MASK_VECTOR_RP_ROUTE_ERROR_MASK 0x0000000000010000 - -/* SH_LB_ERROR_MASK_GCLK_DROP */ -/* Description: Gclk drop error */ -#define SH_LB_ERROR_MASK_GCLK_DROP_SHFT 17 -#define SH_LB_ERROR_MASK_GCLK_DROP_MASK 0x0000000000020000 - -/* SH_LB_ERROR_MASK_RQ_FIFO_ERROR */ -/* Description: Request queue FIFO error */ -#define SH_LB_ERROR_MASK_RQ_FIFO_ERROR_SHFT 18 -#define SH_LB_ERROR_MASK_RQ_FIFO_ERROR_MASK 0x0000000000040000 - -/* SH_LB_ERROR_MASK_RP_FIFO_ERROR */ -/* Description: Reply queue FIFO error */ -#define SH_LB_ERROR_MASK_RP_FIFO_ERROR_SHFT 19 -#define SH_LB_ERROR_MASK_RP_FIFO_ERROR_MASK 0x0000000000080000 - -/* SH_LB_ERROR_MASK_UNEXP_VALID */ -/* Description: Unexpected valid error */ -#define SH_LB_ERROR_MASK_UNEXP_VALID_SHFT 20 -#define SH_LB_ERROR_MASK_UNEXP_VALID_MASK 0x0000000000100000 - -/* SH_LB_ERROR_MASK_RQ_CREDIT_OVERFLOW */ -/* Description: Request queue credit overflow */ -#define SH_LB_ERROR_MASK_RQ_CREDIT_OVERFLOW_SHFT 21 -#define SH_LB_ERROR_MASK_RQ_CREDIT_OVERFLOW_MASK 0x0000000000200000 - -/* SH_LB_ERROR_MASK_RP_CREDIT_OVERFLOW */ -/* Description: Reply queue credit overflow */ -#define SH_LB_ERROR_MASK_RP_CREDIT_OVERFLOW_SHFT 22 -#define SH_LB_ERROR_MASK_RP_CREDIT_OVERFLOW_MASK 0x0000000000400000 - -/* ==================================================================== */ -/* Register "SH_LB_ERROR_OVERFLOW" */ -/* LB Error Overflow */ -/* ==================================================================== */ - -#define SH_LB_ERROR_OVERFLOW 0x0000000110050500 -#define SH_LB_ERROR_OVERFLOW_MASK 0x00000000007fffff -#define SH_LB_ERROR_OVERFLOW_INIT 0x0000000000000000 - -/* SH_LB_ERROR_OVERFLOW_RQ_BAD_CMD_OVRFL */ -/* Description: RQ_BAD_CMD_OVRFL */ -#define SH_LB_ERROR_OVERFLOW_RQ_BAD_CMD_OVRFL_SHFT 0 -#define SH_LB_ERROR_OVERFLOW_RQ_BAD_CMD_OVRFL_MASK 0x0000000000000001 - -/* SH_LB_ERROR_OVERFLOW_RP_BAD_CMD_OVRFL */ -/* Description: RP_BAD_CMD_OVRFL */ -#define SH_LB_ERROR_OVERFLOW_RP_BAD_CMD_OVRFL_SHFT 1 -#define SH_LB_ERROR_OVERFLOW_RP_BAD_CMD_OVRFL_MASK 0x0000000000000002 - -/* SH_LB_ERROR_OVERFLOW_RQ_SHORT_OVRFL */ -/* Description: RQ_SHORT_OVRFL */ -#define SH_LB_ERROR_OVERFLOW_RQ_SHORT_OVRFL_SHFT 2 -#define SH_LB_ERROR_OVERFLOW_RQ_SHORT_OVRFL_MASK 0x0000000000000004 - -/* SH_LB_ERROR_OVERFLOW_RP_SHORT_OVRFL */ -/* Description: RP_SHORT_OVRFL */ -#define SH_LB_ERROR_OVERFLOW_RP_SHORT_OVRFL_SHFT 3 -#define SH_LB_ERROR_OVERFLOW_RP_SHORT_OVRFL_MASK 0x0000000000000008 - -/* SH_LB_ERROR_OVERFLOW_RQ_LONG_OVRFL */ -/* Description: RQ_LONG_OVRFL */ -#define SH_LB_ERROR_OVERFLOW_RQ_LONG_OVRFL_SHFT 4 -#define SH_LB_ERROR_OVERFLOW_RQ_LONG_OVRFL_MASK 0x0000000000000010 - -/* SH_LB_ERROR_OVERFLOW_RP_LONG_OVRFL */ -/* Description: RP_LONG_OVRFL */ -#define SH_LB_ERROR_OVERFLOW_RP_LONG_OVRFL_SHFT 5 -#define SH_LB_ERROR_OVERFLOW_RP_LONG_OVRFL_MASK 0x0000000000000020 - -/* SH_LB_ERROR_OVERFLOW_RQ_BAD_DATA_OVRFL */ -/* Description: RQ_BAD_DATA_OVRFL */ -#define SH_LB_ERROR_OVERFLOW_RQ_BAD_DATA_OVRFL_SHFT 6 -#define SH_LB_ERROR_OVERFLOW_RQ_BAD_DATA_OVRFL_MASK 0x0000000000000040 - -/* SH_LB_ERROR_OVERFLOW_RP_BAD_DATA_OVRFL */ -/* Description: RP_BAD_DATA_OVRFL */ -#define SH_LB_ERROR_OVERFLOW_RP_BAD_DATA_OVRFL_SHFT 7 -#define SH_LB_ERROR_OVERFLOW_RP_BAD_DATA_OVRFL_MASK 0x0000000000000080 - -/* SH_LB_ERROR_OVERFLOW_RQ_BAD_ADDR_OVRFL */ -/* Description: RQ_BAD_ADDR_OVRFL */ -#define SH_LB_ERROR_OVERFLOW_RQ_BAD_ADDR_OVRFL_SHFT 8 -#define SH_LB_ERROR_OVERFLOW_RQ_BAD_ADDR_OVRFL_MASK 0x0000000000000100 - -/* SH_LB_ERROR_OVERFLOW_RQ_TIME_OUT_OVRFL */ -/* Description: RQ_TIME_OUT_OVRFL */ -#define SH_LB_ERROR_OVERFLOW_RQ_TIME_OUT_OVRFL_SHFT 9 -#define SH_LB_ERROR_OVERFLOW_RQ_TIME_OUT_OVRFL_MASK 0x0000000000000200 - -/* SH_LB_ERROR_OVERFLOW_LINVV_OVERFLOW_OVRFL */ -/* Description: LINVV_OVERFLOW_OVRFL */ -#define SH_LB_ERROR_OVERFLOW_LINVV_OVERFLOW_OVRFL_SHFT 10 -#define SH_LB_ERROR_OVERFLOW_LINVV_OVERFLOW_OVRFL_MASK 0x0000000000000400 - -/* SH_LB_ERROR_OVERFLOW_UNEXPECTED_LINV_OVRFL */ -/* Description: UNEXPECTED_LINV_OVRFL */ -#define SH_LB_ERROR_OVERFLOW_UNEXPECTED_LINV_OVRFL_SHFT 11 -#define SH_LB_ERROR_OVERFLOW_UNEXPECTED_LINV_OVRFL_MASK 0x0000000000000800 - -/* SH_LB_ERROR_OVERFLOW_PTC_1_TIMEOUT_OVRFL */ -/* Description: PTC_1 Time out overflow */ -#define SH_LB_ERROR_OVERFLOW_PTC_1_TIMEOUT_OVRFL_SHFT 12 -#define SH_LB_ERROR_OVERFLOW_PTC_1_TIMEOUT_OVRFL_MASK 0x0000000000001000 - -/* SH_LB_ERROR_OVERFLOW_JUNK_BUS_ERR_OVRFL */ -/* Description: Junk Bus error overflow */ -#define SH_LB_ERROR_OVERFLOW_JUNK_BUS_ERR_OVRFL_SHFT 13 -#define SH_LB_ERROR_OVERFLOW_JUNK_BUS_ERR_OVRFL_MASK 0x0000000000002000 - -/* SH_LB_ERROR_OVERFLOW_PIO_CB_ERR_OVRFL */ -/* Description: PIO Conveyor Belt operation error overflow */ -#define SH_LB_ERROR_OVERFLOW_PIO_CB_ERR_OVRFL_SHFT 14 -#define SH_LB_ERROR_OVERFLOW_PIO_CB_ERR_OVRFL_MASK 0x0000000000004000 - -/* SH_LB_ERROR_OVERFLOW_VECTOR_RQ_ROUTE_ERROR_OVRFL */ -/* Description: Vector request Route data was invalid overflow */ -#define SH_LB_ERROR_OVERFLOW_VECTOR_RQ_ROUTE_ERROR_OVRFL_SHFT 15 -#define SH_LB_ERROR_OVERFLOW_VECTOR_RQ_ROUTE_ERROR_OVRFL_MASK 0x0000000000008000 - -/* SH_LB_ERROR_OVERFLOW_VECTOR_RP_ROUTE_ERROR_OVRFL */ -/* Description: Vector reply Route data was invalid overflow */ -#define SH_LB_ERROR_OVERFLOW_VECTOR_RP_ROUTE_ERROR_OVRFL_SHFT 16 -#define SH_LB_ERROR_OVERFLOW_VECTOR_RP_ROUTE_ERROR_OVRFL_MASK 0x0000000000010000 - -/* SH_LB_ERROR_OVERFLOW_GCLK_DROP_OVRFL */ -/* Description: Gclk drop error overflow */ -#define SH_LB_ERROR_OVERFLOW_GCLK_DROP_OVRFL_SHFT 17 -#define SH_LB_ERROR_OVERFLOW_GCLK_DROP_OVRFL_MASK 0x0000000000020000 - -/* SH_LB_ERROR_OVERFLOW_RQ_FIFO_ERROR_OVRFL */ -/* Description: Request queue FIFO error overflow */ -#define SH_LB_ERROR_OVERFLOW_RQ_FIFO_ERROR_OVRFL_SHFT 18 -#define SH_LB_ERROR_OVERFLOW_RQ_FIFO_ERROR_OVRFL_MASK 0x0000000000040000 - -/* SH_LB_ERROR_OVERFLOW_RP_FIFO_ERROR_OVRFL */ -/* Description: Reply queue FIFO error overflow */ -#define SH_LB_ERROR_OVERFLOW_RP_FIFO_ERROR_OVRFL_SHFT 19 -#define SH_LB_ERROR_OVERFLOW_RP_FIFO_ERROR_OVRFL_MASK 0x0000000000080000 - -/* SH_LB_ERROR_OVERFLOW_UNEXP_VALID_OVRFL */ -/* Description: Unexpected valid error overflow */ -#define SH_LB_ERROR_OVERFLOW_UNEXP_VALID_OVRFL_SHFT 20 -#define SH_LB_ERROR_OVERFLOW_UNEXP_VALID_OVRFL_MASK 0x0000000000100000 - -/* SH_LB_ERROR_OVERFLOW_RQ_CREDIT_OVERFLOW_OVRFL */ -/* Description: Request queue credit overflow */ -#define SH_LB_ERROR_OVERFLOW_RQ_CREDIT_OVERFLOW_OVRFL_SHFT 21 -#define SH_LB_ERROR_OVERFLOW_RQ_CREDIT_OVERFLOW_OVRFL_MASK 0x0000000000200000 - -/* SH_LB_ERROR_OVERFLOW_RP_CREDIT_OVERFLOW_OVRFL */ -/* Description: Reply queue credit overflow */ -#define SH_LB_ERROR_OVERFLOW_RP_CREDIT_OVERFLOW_OVRFL_SHFT 22 -#define SH_LB_ERROR_OVERFLOW_RP_CREDIT_OVERFLOW_OVRFL_MASK 0x0000000000400000 - -/* ==================================================================== */ -/* Register "SH_LB_ERROR_OVERFLOW_ALIAS" */ -/* LB Error Overflow */ -/* ==================================================================== */ - -#define SH_LB_ERROR_OVERFLOW_ALIAS 0x0000000110050508 - -/* ==================================================================== */ -/* Register "SH_LB_ERROR_SUMMARY" */ -/* LB Error Bits */ -/* ==================================================================== */ - -#define SH_LB_ERROR_SUMMARY 0x0000000110050580 -#define SH_LB_ERROR_SUMMARY_MASK 0x00000000007fffff -#define SH_LB_ERROR_SUMMARY_INIT 0x0000000000000000 - -/* SH_LB_ERROR_SUMMARY_RQ_BAD_CMD */ -/* Description: RQ_BAD_CMD */ -#define SH_LB_ERROR_SUMMARY_RQ_BAD_CMD_SHFT 0 -#define SH_LB_ERROR_SUMMARY_RQ_BAD_CMD_MASK 0x0000000000000001 - -/* SH_LB_ERROR_SUMMARY_RP_BAD_CMD */ -/* Description: RP_BAD_CMD */ -#define SH_LB_ERROR_SUMMARY_RP_BAD_CMD_SHFT 1 -#define SH_LB_ERROR_SUMMARY_RP_BAD_CMD_MASK 0x0000000000000002 - -/* SH_LB_ERROR_SUMMARY_RQ_SHORT */ -/* Description: RQ_SHORT */ -#define SH_LB_ERROR_SUMMARY_RQ_SHORT_SHFT 2 -#define SH_LB_ERROR_SUMMARY_RQ_SHORT_MASK 0x0000000000000004 - -/* SH_LB_ERROR_SUMMARY_RP_SHORT */ -/* Description: RP_SHORT */ -#define SH_LB_ERROR_SUMMARY_RP_SHORT_SHFT 3 -#define SH_LB_ERROR_SUMMARY_RP_SHORT_MASK 0x0000000000000008 - -/* SH_LB_ERROR_SUMMARY_RQ_LONG */ -/* Description: RQ_LONG */ -#define SH_LB_ERROR_SUMMARY_RQ_LONG_SHFT 4 -#define SH_LB_ERROR_SUMMARY_RQ_LONG_MASK 0x0000000000000010 - -/* SH_LB_ERROR_SUMMARY_RP_LONG */ -/* Description: RP_LONG */ -#define SH_LB_ERROR_SUMMARY_RP_LONG_SHFT 5 -#define SH_LB_ERROR_SUMMARY_RP_LONG_MASK 0x0000000000000020 - -/* SH_LB_ERROR_SUMMARY_RQ_BAD_DATA */ -/* Description: RQ_BAD_DATA */ -#define SH_LB_ERROR_SUMMARY_RQ_BAD_DATA_SHFT 6 -#define SH_LB_ERROR_SUMMARY_RQ_BAD_DATA_MASK 0x0000000000000040 - -/* SH_LB_ERROR_SUMMARY_RP_BAD_DATA */ -/* Description: RP_BAD_DATA */ -#define SH_LB_ERROR_SUMMARY_RP_BAD_DATA_SHFT 7 -#define SH_LB_ERROR_SUMMARY_RP_BAD_DATA_MASK 0x0000000000000080 - -/* SH_LB_ERROR_SUMMARY_RQ_BAD_ADDR */ -/* Description: RQ_BAD_ADDR */ -#define SH_LB_ERROR_SUMMARY_RQ_BAD_ADDR_SHFT 8 -#define SH_LB_ERROR_SUMMARY_RQ_BAD_ADDR_MASK 0x0000000000000100 - -/* SH_LB_ERROR_SUMMARY_RQ_TIME_OUT */ -/* Description: RQ_TIME_OUT */ -#define SH_LB_ERROR_SUMMARY_RQ_TIME_OUT_SHFT 9 -#define SH_LB_ERROR_SUMMARY_RQ_TIME_OUT_MASK 0x0000000000000200 - -/* SH_LB_ERROR_SUMMARY_LINVV_OVERFLOW */ -/* Description: LINVV_OVERFLOW */ -#define SH_LB_ERROR_SUMMARY_LINVV_OVERFLOW_SHFT 10 -#define SH_LB_ERROR_SUMMARY_LINVV_OVERFLOW_MASK 0x0000000000000400 - -/* SH_LB_ERROR_SUMMARY_UNEXPECTED_LINV */ -/* Description: UNEXPECTED_LINV */ -#define SH_LB_ERROR_SUMMARY_UNEXPECTED_LINV_SHFT 11 -#define SH_LB_ERROR_SUMMARY_UNEXPECTED_LINV_MASK 0x0000000000000800 - -/* SH_LB_ERROR_SUMMARY_PTC_1_TIMEOUT */ -/* Description: PTC_1 Time out */ -#define SH_LB_ERROR_SUMMARY_PTC_1_TIMEOUT_SHFT 12 -#define SH_LB_ERROR_SUMMARY_PTC_1_TIMEOUT_MASK 0x0000000000001000 - -/* SH_LB_ERROR_SUMMARY_JUNK_BUS_ERR */ -/* Description: Junk Bus error */ -#define SH_LB_ERROR_SUMMARY_JUNK_BUS_ERR_SHFT 13 -#define SH_LB_ERROR_SUMMARY_JUNK_BUS_ERR_MASK 0x0000000000002000 - -/* SH_LB_ERROR_SUMMARY_PIO_CB_ERR */ -/* Description: PIO Conveyor Belt operation error */ -#define SH_LB_ERROR_SUMMARY_PIO_CB_ERR_SHFT 14 -#define SH_LB_ERROR_SUMMARY_PIO_CB_ERR_MASK 0x0000000000004000 - -/* SH_LB_ERROR_SUMMARY_VECTOR_RQ_ROUTE_ERROR */ -/* Description: Vector request Route data was invalid */ -#define SH_LB_ERROR_SUMMARY_VECTOR_RQ_ROUTE_ERROR_SHFT 15 -#define SH_LB_ERROR_SUMMARY_VECTOR_RQ_ROUTE_ERROR_MASK 0x0000000000008000 - -/* SH_LB_ERROR_SUMMARY_VECTOR_RP_ROUTE_ERROR */ -/* Description: Vector reply Route data was invalid */ -#define SH_LB_ERROR_SUMMARY_VECTOR_RP_ROUTE_ERROR_SHFT 16 -#define SH_LB_ERROR_SUMMARY_VECTOR_RP_ROUTE_ERROR_MASK 0x0000000000010000 - -/* SH_LB_ERROR_SUMMARY_GCLK_DROP */ -/* Description: Gclk drop error */ -#define SH_LB_ERROR_SUMMARY_GCLK_DROP_SHFT 17 -#define SH_LB_ERROR_SUMMARY_GCLK_DROP_MASK 0x0000000000020000 - -/* SH_LB_ERROR_SUMMARY_RQ_FIFO_ERROR */ -/* Description: Request queue FIFO error */ -#define SH_LB_ERROR_SUMMARY_RQ_FIFO_ERROR_SHFT 18 -#define SH_LB_ERROR_SUMMARY_RQ_FIFO_ERROR_MASK 0x0000000000040000 - -/* SH_LB_ERROR_SUMMARY_RP_FIFO_ERROR */ -/* Description: Reply queue FIFO error */ -#define SH_LB_ERROR_SUMMARY_RP_FIFO_ERROR_SHFT 19 -#define SH_LB_ERROR_SUMMARY_RP_FIFO_ERROR_MASK 0x0000000000080000 - -/* SH_LB_ERROR_SUMMARY_UNEXP_VALID */ -/* Description: Unexpected valid error */ -#define SH_LB_ERROR_SUMMARY_UNEXP_VALID_SHFT 20 -#define SH_LB_ERROR_SUMMARY_UNEXP_VALID_MASK 0x0000000000100000 - -/* SH_LB_ERROR_SUMMARY_RQ_CREDIT_OVERFLOW */ -/* Description: Request queue credit overflow */ -#define SH_LB_ERROR_SUMMARY_RQ_CREDIT_OVERFLOW_SHFT 21 -#define SH_LB_ERROR_SUMMARY_RQ_CREDIT_OVERFLOW_MASK 0x0000000000200000 - -/* SH_LB_ERROR_SUMMARY_RP_CREDIT_OVERFLOW */ -/* Description: Reply queue credit overflow */ -#define SH_LB_ERROR_SUMMARY_RP_CREDIT_OVERFLOW_SHFT 22 -#define SH_LB_ERROR_SUMMARY_RP_CREDIT_OVERFLOW_MASK 0x0000000000400000 - -/* ==================================================================== */ -/* Register "SH_LB_ERROR_SUMMARY_ALIAS" */ -/* LB Error Bits Alias */ -/* ==================================================================== */ - -#define SH_LB_ERROR_SUMMARY_ALIAS 0x0000000110050588 - -/* ==================================================================== */ -/* Register "SH_LB_FIRST_ERROR" */ -/* LB First Error */ -/* ==================================================================== */ - -#define SH_LB_FIRST_ERROR 0x0000000110050600 -#define SH_LB_FIRST_ERROR_MASK 0x00000000007fffff -#define SH_LB_FIRST_ERROR_INIT 0x0000000000000000 - -/* SH_LB_FIRST_ERROR_RQ_BAD_CMD */ -/* Description: RQ_BAD_CMD */ -#define SH_LB_FIRST_ERROR_RQ_BAD_CMD_SHFT 0 -#define SH_LB_FIRST_ERROR_RQ_BAD_CMD_MASK 0x0000000000000001 - -/* SH_LB_FIRST_ERROR_RP_BAD_CMD */ -/* Description: RP_BAD_CMD */ -#define SH_LB_FIRST_ERROR_RP_BAD_CMD_SHFT 1 -#define SH_LB_FIRST_ERROR_RP_BAD_CMD_MASK 0x0000000000000002 - -/* SH_LB_FIRST_ERROR_RQ_SHORT */ -/* Description: RQ_SHORT */ -#define SH_LB_FIRST_ERROR_RQ_SHORT_SHFT 2 -#define SH_LB_FIRST_ERROR_RQ_SHORT_MASK 0x0000000000000004 - -/* SH_LB_FIRST_ERROR_RP_SHORT */ -/* Description: RP_SHORT */ -#define SH_LB_FIRST_ERROR_RP_SHORT_SHFT 3 -#define SH_LB_FIRST_ERROR_RP_SHORT_MASK 0x0000000000000008 - -/* SH_LB_FIRST_ERROR_RQ_LONG */ -/* Description: RQ_LONG */ -#define SH_LB_FIRST_ERROR_RQ_LONG_SHFT 4 -#define SH_LB_FIRST_ERROR_RQ_LONG_MASK 0x0000000000000010 - -/* SH_LB_FIRST_ERROR_RP_LONG */ -/* Description: RP_LONG */ -#define SH_LB_FIRST_ERROR_RP_LONG_SHFT 5 -#define SH_LB_FIRST_ERROR_RP_LONG_MASK 0x0000000000000020 - -/* SH_LB_FIRST_ERROR_RQ_BAD_DATA */ -/* Description: RQ_BAD_DATA */ -#define SH_LB_FIRST_ERROR_RQ_BAD_DATA_SHFT 6 -#define SH_LB_FIRST_ERROR_RQ_BAD_DATA_MASK 0x0000000000000040 - -/* SH_LB_FIRST_ERROR_RP_BAD_DATA */ -/* Description: RP_BAD_DATA */ -#define SH_LB_FIRST_ERROR_RP_BAD_DATA_SHFT 7 -#define SH_LB_FIRST_ERROR_RP_BAD_DATA_MASK 0x0000000000000080 - -/* SH_LB_FIRST_ERROR_RQ_BAD_ADDR */ -/* Description: RQ_BAD_ADDR */ -#define SH_LB_FIRST_ERROR_RQ_BAD_ADDR_SHFT 8 -#define SH_LB_FIRST_ERROR_RQ_BAD_ADDR_MASK 0x0000000000000100 - -/* SH_LB_FIRST_ERROR_RQ_TIME_OUT */ -/* Description: RQ_TIME_OUT */ -#define SH_LB_FIRST_ERROR_RQ_TIME_OUT_SHFT 9 -#define SH_LB_FIRST_ERROR_RQ_TIME_OUT_MASK 0x0000000000000200 - -/* SH_LB_FIRST_ERROR_LINVV_OVERFLOW */ -/* Description: LINVV_OVERFLOW */ -#define SH_LB_FIRST_ERROR_LINVV_OVERFLOW_SHFT 10 -#define SH_LB_FIRST_ERROR_LINVV_OVERFLOW_MASK 0x0000000000000400 - -/* SH_LB_FIRST_ERROR_UNEXPECTED_LINV */ -/* Description: UNEXPECTED_LINV */ -#define SH_LB_FIRST_ERROR_UNEXPECTED_LINV_SHFT 11 -#define SH_LB_FIRST_ERROR_UNEXPECTED_LINV_MASK 0x0000000000000800 - -/* SH_LB_FIRST_ERROR_PTC_1_TIMEOUT */ -/* Description: PTC_1 Time out */ -#define SH_LB_FIRST_ERROR_PTC_1_TIMEOUT_SHFT 12 -#define SH_LB_FIRST_ERROR_PTC_1_TIMEOUT_MASK 0x0000000000001000 - -/* SH_LB_FIRST_ERROR_JUNK_BUS_ERR */ -/* Description: Junk Bus error */ -#define SH_LB_FIRST_ERROR_JUNK_BUS_ERR_SHFT 13 -#define SH_LB_FIRST_ERROR_JUNK_BUS_ERR_MASK 0x0000000000002000 - -/* SH_LB_FIRST_ERROR_PIO_CB_ERR */ -/* Description: PIO Conveyor Belt operation error */ -#define SH_LB_FIRST_ERROR_PIO_CB_ERR_SHFT 14 -#define SH_LB_FIRST_ERROR_PIO_CB_ERR_MASK 0x0000000000004000 - -/* SH_LB_FIRST_ERROR_VECTOR_RQ_ROUTE_ERROR */ -/* Description: Vector request Route data was invalid */ -#define SH_LB_FIRST_ERROR_VECTOR_RQ_ROUTE_ERROR_SHFT 15 -#define SH_LB_FIRST_ERROR_VECTOR_RQ_ROUTE_ERROR_MASK 0x0000000000008000 - -/* SH_LB_FIRST_ERROR_VECTOR_RP_ROUTE_ERROR */ -/* Description: Vector reply Route data was invalid */ -#define SH_LB_FIRST_ERROR_VECTOR_RP_ROUTE_ERROR_SHFT 16 -#define SH_LB_FIRST_ERROR_VECTOR_RP_ROUTE_ERROR_MASK 0x0000000000010000 - -/* SH_LB_FIRST_ERROR_GCLK_DROP */ -/* Description: Gclk drop error */ -#define SH_LB_FIRST_ERROR_GCLK_DROP_SHFT 17 -#define SH_LB_FIRST_ERROR_GCLK_DROP_MASK 0x0000000000020000 - -/* SH_LB_FIRST_ERROR_RQ_FIFO_ERROR */ -/* Description: Request queue FIFO error */ -#define SH_LB_FIRST_ERROR_RQ_FIFO_ERROR_SHFT 18 -#define SH_LB_FIRST_ERROR_RQ_FIFO_ERROR_MASK 0x0000000000040000 - -/* SH_LB_FIRST_ERROR_RP_FIFO_ERROR */ -/* Description: Reply queue FIFO error */ -#define SH_LB_FIRST_ERROR_RP_FIFO_ERROR_SHFT 19 -#define SH_LB_FIRST_ERROR_RP_FIFO_ERROR_MASK 0x0000000000080000 - -/* SH_LB_FIRST_ERROR_UNEXP_VALID */ -/* Description: Unexpected valid error */ -#define SH_LB_FIRST_ERROR_UNEXP_VALID_SHFT 20 -#define SH_LB_FIRST_ERROR_UNEXP_VALID_MASK 0x0000000000100000 - -/* SH_LB_FIRST_ERROR_RQ_CREDIT_OVERFLOW */ -/* Description: Request queue credit overflow */ -#define SH_LB_FIRST_ERROR_RQ_CREDIT_OVERFLOW_SHFT 21 -#define SH_LB_FIRST_ERROR_RQ_CREDIT_OVERFLOW_MASK 0x0000000000200000 - -/* SH_LB_FIRST_ERROR_RP_CREDIT_OVERFLOW */ -/* Description: Reply queue credit overflow */ -#define SH_LB_FIRST_ERROR_RP_CREDIT_OVERFLOW_SHFT 22 -#define SH_LB_FIRST_ERROR_RP_CREDIT_OVERFLOW_MASK 0x0000000000400000 - -/* ==================================================================== */ -/* Register "SH_LB_LAST_CREDIT" */ -/* Credit counter status register */ -/* ==================================================================== */ - -#define SH_LB_LAST_CREDIT 0x0000000110050680 -#define SH_LB_LAST_CREDIT_MASK 0x000000000ffff3df -#define SH_LB_LAST_CREDIT_INIT 0x0000000000000000 - -/* SH_LB_LAST_CREDIT_LIQ_RQ_CREDIT */ -/* Description: LIQ request queue credit counter */ -#define SH_LB_LAST_CREDIT_LIQ_RQ_CREDIT_SHFT 0 -#define SH_LB_LAST_CREDIT_LIQ_RQ_CREDIT_MASK 0x000000000000001f - -/* SH_LB_LAST_CREDIT_LIQ_RP_CREDIT */ -/* Description: LIQ reply queue credit counter */ -#define SH_LB_LAST_CREDIT_LIQ_RP_CREDIT_SHFT 6 -#define SH_LB_LAST_CREDIT_LIQ_RP_CREDIT_MASK 0x00000000000003c0 - -/* SH_LB_LAST_CREDIT_LINVV_CREDIT */ -/* Description: LINVV credit counter */ -#define SH_LB_LAST_CREDIT_LINVV_CREDIT_SHFT 12 -#define SH_LB_LAST_CREDIT_LINVV_CREDIT_MASK 0x000000000003f000 - -/* SH_LB_LAST_CREDIT_LOQ_RQ_CREDIT */ -/* Description: LOQ request queue credit counter */ -#define SH_LB_LAST_CREDIT_LOQ_RQ_CREDIT_SHFT 18 -#define SH_LB_LAST_CREDIT_LOQ_RQ_CREDIT_MASK 0x00000000007c0000 - -/* SH_LB_LAST_CREDIT_LOQ_RP_CREDIT */ -/* Description: LOQ reply queue credit counter */ -#define SH_LB_LAST_CREDIT_LOQ_RP_CREDIT_SHFT 23 -#define SH_LB_LAST_CREDIT_LOQ_RP_CREDIT_MASK 0x000000000f800000 - -/* ==================================================================== */ -/* Register "SH_LB_NACK_STATUS" */ -/* Nack Counter Status Register */ -/* ==================================================================== */ - -#define SH_LB_NACK_STATUS 0x0000000110050700 -#define SH_LB_NACK_STATUS_MASK 0x3fffffff0fff0fff -#define SH_LB_NACK_STATUS_INIT 0x0000000000000000 - -/* SH_LB_NACK_STATUS_PIO_NACK_A */ -/* Description: PIO nackA counter */ -#define SH_LB_NACK_STATUS_PIO_NACK_A_SHFT 0 -#define SH_LB_NACK_STATUS_PIO_NACK_A_MASK 0x0000000000000fff - -/* SH_LB_NACK_STATUS_PIO_NACK_B */ -/* Description: PIO nackA counter */ -#define SH_LB_NACK_STATUS_PIO_NACK_B_SHFT 16 -#define SH_LB_NACK_STATUS_PIO_NACK_B_MASK 0x000000000fff0000 - -/* SH_LB_NACK_STATUS_JUNK_NACK */ -/* Description: Junk bus nack counter */ -#define SH_LB_NACK_STATUS_JUNK_NACK_SHFT 32 -#define SH_LB_NACK_STATUS_JUNK_NACK_MASK 0x0000ffff00000000 - -/* SH_LB_NACK_STATUS_CB_TIMEOUT_COUNT */ -/* Description: Conveyor belt time out counter */ -#define SH_LB_NACK_STATUS_CB_TIMEOUT_COUNT_SHFT 48 -#define SH_LB_NACK_STATUS_CB_TIMEOUT_COUNT_MASK 0x0fff000000000000 - -/* SH_LB_NACK_STATUS_CB_STATE */ -/* Description: Conveyor belt state */ -#define SH_LB_NACK_STATUS_CB_STATE_SHFT 60 -#define SH_LB_NACK_STATUS_CB_STATE_MASK 0x3000000000000000 - -/* ==================================================================== */ -/* Register "SH_LB_TRIGGER_COMPARE" */ -/* LB Test-point Trigger Compare */ -/* ==================================================================== */ - -#define SH_LB_TRIGGER_COMPARE 0x0000000110050780 -#define SH_LB_TRIGGER_COMPARE_MASK 0x00000000ffffffff -#define SH_LB_TRIGGER_COMPARE_INIT 0x0000000000000000 - -/* SH_LB_TRIGGER_COMPARE_MASK */ -/* Description: Mask to select Debug bits for trigger generation */ -#define SH_LB_TRIGGER_COMPARE_MASK_SHFT 0 -#define SH_LB_TRIGGER_COMPARE_MASK_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_LB_TRIGGER_DATA" */ -/* LB Test-point Trigger Compare Data */ -/* ==================================================================== */ - -#define SH_LB_TRIGGER_DATA 0x0000000110050800 -#define SH_LB_TRIGGER_DATA_MASK 0x00000000ffffffff -#define SH_LB_TRIGGER_DATA_INIT 0x00000000ffffffff - -/* SH_LB_TRIGGER_DATA_COMPARE_PATTERN */ -/* Description: debug bit pattern for trigger generation */ -#define SH_LB_TRIGGER_DATA_COMPARE_PATTERN_SHFT 0 -#define SH_LB_TRIGGER_DATA_COMPARE_PATTERN_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_PI_AEC_CONFIG" */ -/* PI Adaptive Error Correction Configuration */ -/* ==================================================================== */ - -#define SH_PI_AEC_CONFIG 0x0000000120050000 -#define SH_PI_AEC_CONFIG_MASK 0x0000000000000007 -#define SH_PI_AEC_CONFIG_INIT 0x0000000000000000 - -/* SH_PI_AEC_CONFIG_MODE */ -/* Description: AEC Operation Mode */ -#define SH_PI_AEC_CONFIG_MODE_SHFT 0 -#define SH_PI_AEC_CONFIG_MODE_MASK 0x0000000000000007 - -/* ==================================================================== */ -/* Register "SH_PI_AFI_ERROR_MASK" */ -/* PI AFI Error Mask */ -/* ==================================================================== */ - -#define SH_PI_AFI_ERROR_MASK 0x0000000120050080 -#define SH_PI_AFI_ERROR_MASK_MASK 0x00000007ffe00000 -#define SH_PI_AFI_ERROR_MASK_INIT 0x00000007ffe00000 - -/* SH_PI_AFI_ERROR_MASK_HUNG_BUS */ -/* Description: FSB is hung */ -#define SH_PI_AFI_ERROR_MASK_HUNG_BUS_SHFT 21 -#define SH_PI_AFI_ERROR_MASK_HUNG_BUS_MASK 0x0000000000200000 - -/* SH_PI_AFI_ERROR_MASK_RSP_PARITY */ -/* Description: Parity error detecte during response phase */ -#define SH_PI_AFI_ERROR_MASK_RSP_PARITY_SHFT 22 -#define SH_PI_AFI_ERROR_MASK_RSP_PARITY_MASK 0x0000000000400000 - -/* SH_PI_AFI_ERROR_MASK_IOQ_OVERRUN */ -/* Description: Over run error detected on IOQ */ -#define SH_PI_AFI_ERROR_MASK_IOQ_OVERRUN_SHFT 23 -#define SH_PI_AFI_ERROR_MASK_IOQ_OVERRUN_MASK 0x0000000000800000 - -/* SH_PI_AFI_ERROR_MASK_REQ_FORMAT */ -/* Description: FSB request format not supported */ -#define SH_PI_AFI_ERROR_MASK_REQ_FORMAT_SHFT 24 -#define SH_PI_AFI_ERROR_MASK_REQ_FORMAT_MASK 0x0000000001000000 - -/* SH_PI_AFI_ERROR_MASK_ADDR_ACCESS */ -/* Description: Access to Address is not supported */ -#define SH_PI_AFI_ERROR_MASK_ADDR_ACCESS_SHFT 25 -#define SH_PI_AFI_ERROR_MASK_ADDR_ACCESS_MASK 0x0000000002000000 - -/* SH_PI_AFI_ERROR_MASK_REQ_PARITY */ -/* Description: Parity error detected during request phase */ -#define SH_PI_AFI_ERROR_MASK_REQ_PARITY_SHFT 26 -#define SH_PI_AFI_ERROR_MASK_REQ_PARITY_MASK 0x0000000004000000 - -/* SH_PI_AFI_ERROR_MASK_ADDR_PARITY */ -/* Description: Parity error detected on address */ -#define SH_PI_AFI_ERROR_MASK_ADDR_PARITY_SHFT 27 -#define SH_PI_AFI_ERROR_MASK_ADDR_PARITY_MASK 0x0000000008000000 - -/* SH_PI_AFI_ERROR_MASK_SHUB_FSB_DQE */ -/* Description: SHUB_FSB_DQE */ -#define SH_PI_AFI_ERROR_MASK_SHUB_FSB_DQE_SHFT 28 -#define SH_PI_AFI_ERROR_MASK_SHUB_FSB_DQE_MASK 0x0000000010000000 - -/* SH_PI_AFI_ERROR_MASK_SHUB_FSB_UCE */ -/* Description: An un-correctable ECC error was detected */ -#define SH_PI_AFI_ERROR_MASK_SHUB_FSB_UCE_SHFT 29 -#define SH_PI_AFI_ERROR_MASK_SHUB_FSB_UCE_MASK 0x0000000020000000 - -/* SH_PI_AFI_ERROR_MASK_SHUB_FSB_CE */ -/* Description: An correctable ECC error was detected */ -#define SH_PI_AFI_ERROR_MASK_SHUB_FSB_CE_SHFT 30 -#define SH_PI_AFI_ERROR_MASK_SHUB_FSB_CE_MASK 0x0000000040000000 - -/* SH_PI_AFI_ERROR_MASK_LIVELOCK */ -/* Description: AFI livelock error was detected */ -#define SH_PI_AFI_ERROR_MASK_LIVELOCK_SHFT 31 -#define SH_PI_AFI_ERROR_MASK_LIVELOCK_MASK 0x0000000080000000 - -/* SH_PI_AFI_ERROR_MASK_BAD_SNOOP */ -/* Description: AFI bad snoop error was detected */ -#define SH_PI_AFI_ERROR_MASK_BAD_SNOOP_SHFT 32 -#define SH_PI_AFI_ERROR_MASK_BAD_SNOOP_MASK 0x0000000100000000 - -/* SH_PI_AFI_ERROR_MASK_FSB_TBL_MISS */ -/* Description: AFI FSB request table miss error was detected */ -#define SH_PI_AFI_ERROR_MASK_FSB_TBL_MISS_SHFT 33 -#define SH_PI_AFI_ERROR_MASK_FSB_TBL_MISS_MASK 0x0000000200000000 - -/* SH_PI_AFI_ERROR_MASK_MSG_LEN */ -/* Description: Runt or Obese message received from SIC */ -#define SH_PI_AFI_ERROR_MASK_MSG_LEN_SHFT 34 -#define SH_PI_AFI_ERROR_MASK_MSG_LEN_MASK 0x0000000400000000 - -/* ==================================================================== */ -/* Register "SH_PI_AFI_TEST_POINT_COMPARE" */ -/* PI AFI Test Point Compare */ -/* ==================================================================== */ - -#define SH_PI_AFI_TEST_POINT_COMPARE 0x0000000120050100 -#define SH_PI_AFI_TEST_POINT_COMPARE_MASK 0xffffffffffffffff -#define SH_PI_AFI_TEST_POINT_COMPARE_INIT 0xffffffff00000000 - -/* SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_MASK */ -/* Description: Mask to select Debug bits for trigger generation */ -#define SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_MASK_SHFT 0 -#define SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_MASK_MASK 0x00000000ffffffff - -/* SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_PATTERN */ -/* Description: debug bit pattern for trigger generation */ -#define SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_PATTERN_SHFT 32 -#define SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_PATTERN_MASK 0xffffffff00000000 - -/* ==================================================================== */ -/* Register "SH_PI_AFI_TEST_POINT_SELECT" */ -/* PI AFI Test Point Select */ -/* ==================================================================== */ - -#define SH_PI_AFI_TEST_POINT_SELECT 0x0000000120050180 -#define SH_PI_AFI_TEST_POINT_SELECT_MASK 0xff7f7f7f7f7f7f7f -#define SH_PI_AFI_TEST_POINT_SELECT_INIT 0x0000000000000000 - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL */ -/* Description: Nibble 0: Word Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_SHFT 0 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_MASK 0x000000000000000f - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL */ -/* Description: Nibble 0: Nibble Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_SHFT 4 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL */ -/* Description: Nibble 1: Word Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_SHFT 8 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000f00 - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL */ -/* Description: Nibble 1: Nibble Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_SHFT 12 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL */ -/* Description: Nibble 2: Word Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_SHFT 16 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_MASK 0x00000000000f0000 - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL */ -/* Description: Nibble 2: Nibble Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_SHFT 20 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL */ -/* Description: Nibble 3: Word Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_SHFT 24 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_MASK 0x000000000f000000 - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL */ -/* Description: Nibble 3: Nibble Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_SHFT 28 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL */ -/* Description: Nibble 4: Word Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_SHFT 32 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_MASK 0x0000000f00000000 - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL */ -/* Description: Nibble 4: Nibble Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_SHFT 36 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL */ -/* Description: Nibble 5: Word Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_SHFT 40 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_MASK 0x00000f0000000000 - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL */ -/* Description: Nibble 5: Nibble Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_SHFT 44 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL */ -/* Description: Nibble 6: Word Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_SHFT 48 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_MASK 0x000f000000000000 - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL */ -/* Description: Nibble 6: Nibble Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_SHFT 52 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL */ -/* Description: Nibble 7: Word Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_SHFT 56 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_MASK 0x0f00000000000000 - -/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL */ -/* Description: Nibble 7: Nibble Select */ -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_SHFT 60 -#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* SH_PI_AFI_TEST_POINT_SELECT_TRIGGER_ENABLE */ -/* Description: Trigger Enabled */ -#define SH_PI_AFI_TEST_POINT_SELECT_TRIGGER_ENABLE_SHFT 63 -#define SH_PI_AFI_TEST_POINT_SELECT_TRIGGER_ENABLE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_AFI_TEST_POINT_TRIGGER_SELECT" */ -/* PI CRBC Test Point Trigger Select */ -/* ==================================================================== */ - -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT 0x0000000120050200 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_MASK 0x7f7f7f7f7f7f7f7f -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_INIT 0x0000000000000000 - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL */ -/* Description: Nibble 0 Chiplet select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_SHFT 0 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_MASK 0x000000000000000f - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_SHFT 4 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL */ -/* Description: Nibble 1 Chiplet select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_SHFT 8 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_MASK 0x0000000000000f00 - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_SHFT 12 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL */ -/* Description: Nibble 2 Chiplet select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_SHFT 16 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_MASK 0x00000000000f0000 - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_SHFT 20 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL */ -/* Description: Nibble 3 Chiplet select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_SHFT 24 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_MASK 0x000000000f000000 - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_SHFT 28 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL */ -/* Description: Nibble 4 Chiplet select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_SHFT 32 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_MASK 0x0000000f00000000 - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_SHFT 36 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL */ -/* Description: Nibble 5 Chiplet select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_SHFT 40 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_MASK 0x00000f0000000000 - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_SHFT 44 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL */ -/* Description: Nibble 6 Chiplet select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_SHFT 48 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_MASK 0x000f000000000000 - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_SHFT 52 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL */ -/* Description: Nibble 7 Chiplet select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_SHFT 56 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_MASK 0x0f00000000000000 - -/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_SHFT 60 -#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_AUTO_REPLY_ENABLE" */ -/* PI Auto Reply Enable */ -/* ==================================================================== */ - -#define SH_PI_AUTO_REPLY_ENABLE 0x0000000120050280 -#define SH_PI_AUTO_REPLY_ENABLE_MASK 0x0000000000000001 -#define SH_PI_AUTO_REPLY_ENABLE_INIT 0x0000000000000000 - -/* SH_PI_AUTO_REPLY_ENABLE_AUTO_REPLY_ENABLE */ -/* Description: Auto Reply Enabled */ -#define SH_PI_AUTO_REPLY_ENABLE_AUTO_REPLY_ENABLE_SHFT 0 -#define SH_PI_AUTO_REPLY_ENABLE_AUTO_REPLY_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_PI_CAM_CONTROL" */ -/* CRB CAM MMR Access Control */ -/* ==================================================================== */ - -#define SH_PI_CAM_CONTROL 0x0000000120050300 -#define SH_PI_CAM_CONTROL_MASK 0x800000000000037f -#define SH_PI_CAM_CONTROL_INIT 0x0000000000000000 - -/* SH_PI_CAM_CONTROL_CAM_INDX */ -/* Description: CRB CAM Index to perform read/write on. */ -#define SH_PI_CAM_CONTROL_CAM_INDX_SHFT 0 -#define SH_PI_CAM_CONTROL_CAM_INDX_MASK 0x000000000000007f - -/* SH_PI_CAM_CONTROL_CAM_WRITE */ -/* Description: Is CRB CAM MMR function a write. */ -#define SH_PI_CAM_CONTROL_CAM_WRITE_SHFT 8 -#define SH_PI_CAM_CONTROL_CAM_WRITE_MASK 0x0000000000000100 - -/* SH_PI_CAM_CONTROL_RRB_RD_XFER_CLEAR */ -/* Description: Clear RRB read tranfer pending. */ -#define SH_PI_CAM_CONTROL_RRB_RD_XFER_CLEAR_SHFT 9 -#define SH_PI_CAM_CONTROL_RRB_RD_XFER_CLEAR_MASK 0x0000000000000200 - -/* SH_PI_CAM_CONTROL_START */ -/* Description: Start CRB CAM read/write operation */ -#define SH_PI_CAM_CONTROL_START_SHFT 63 -#define SH_PI_CAM_CONTROL_START_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_CRBC_TEST_POINT_COMPARE" */ -/* PI CRBC Test Point Compare */ -/* ==================================================================== */ - -#define SH_PI_CRBC_TEST_POINT_COMPARE 0x0000000120050380 -#define SH_PI_CRBC_TEST_POINT_COMPARE_MASK 0xffffffffffffffff -#define SH_PI_CRBC_TEST_POINT_COMPARE_INIT 0xffffffff00000000 - -/* SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_MASK */ -/* Description: Mask to select Debug bits for trigger generation */ -#define SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_MASK_SHFT 0 -#define SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_MASK_MASK 0x00000000ffffffff - -/* SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_PATTERN */ -/* Description: debug bit pattern for trigger generation */ -#define SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_PATTERN_SHFT 32 -#define SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_PATTERN_MASK 0xffffffff00000000 - -/* ==================================================================== */ -/* Register "SH_PI_CRBC_TEST_POINT_SELECT" */ -/* PI CRBC Test Point Select */ -/* ==================================================================== */ - -#define SH_PI_CRBC_TEST_POINT_SELECT 0x0000000120050400 -#define SH_PI_CRBC_TEST_POINT_SELECT_MASK 0xf777777777777777 -#define SH_PI_CRBC_TEST_POINT_SELECT_INIT 0x0000000000000000 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL */ -/* Description: Nibble 0 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_SHFT 0 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000007 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_SHFT 4 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL */ -/* Description: Nibble 1 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_SHFT 8 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000700 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_SHFT 12 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL */ -/* Description: Nibble 2 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_SHFT 16 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000070000 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_SHFT 20 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL */ -/* Description: Nibble 3 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_SHFT 24 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_MASK 0x0000000007000000 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_SHFT 28 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL */ -/* Description: Nibble 4 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_SHFT 32 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_MASK 0x0000000700000000 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_SHFT 36 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL */ -/* Description: Nibble 5 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_SHFT 40 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_MASK 0x0000070000000000 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_SHFT 44 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL */ -/* Description: Nibble 6 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_SHFT 48 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_MASK 0x0007000000000000 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_SHFT 52 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL */ -/* Description: Nibble 7 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_SHFT 56 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_MASK 0x0700000000000000 - -/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_SHFT 60 -#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* SH_PI_CRBC_TEST_POINT_SELECT_TRIGGER_ENABLE */ -/* Description: Enable trigger on bit 32 of Analyzer data */ -#define SH_PI_CRBC_TEST_POINT_SELECT_TRIGGER_ENABLE_SHFT 63 -#define SH_PI_CRBC_TEST_POINT_SELECT_TRIGGER_ENABLE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT" */ -/* PI CRBC Test Point Trigger Select */ -/* ==================================================================== */ - -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT 0x0000000120050480 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_MASK 0x7777777777777777 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_INIT 0x0000000000000000 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL */ -/* Description: Nibble 0 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_SHFT 0 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_MASK 0x0000000000000007 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_SHFT 4 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL */ -/* Description: Nibble 1 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_SHFT 8 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_MASK 0x0000000000000700 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_SHFT 12 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL */ -/* Description: Nibble 2 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_SHFT 16 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_MASK 0x0000000000070000 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_SHFT 20 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL */ -/* Description: Nibble 3 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_SHFT 24 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_MASK 0x0000000007000000 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_SHFT 28 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL */ -/* Description: Nibble 4 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_SHFT 32 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_MASK 0x0000000700000000 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_SHFT 36 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL */ -/* Description: Nibble 5 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_SHFT 40 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_MASK 0x0000070000000000 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_SHFT 44 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL */ -/* Description: Nibble 6 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_SHFT 48 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_MASK 0x0007000000000000 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_SHFT 52 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL */ -/* Description: Nibble 7 Chiplet select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_SHFT 56 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_MASK 0x0700000000000000 - -/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_SHFT 60 -#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_ERROR_MASK" */ -/* PI CRBP Error Mask */ -/* ==================================================================== */ - -#define SH_PI_CRBP_ERROR_MASK 0x0000000120050500 -#define SH_PI_CRBP_ERROR_MASK_MASK 0x00000000001fffff -#define SH_PI_CRBP_ERROR_MASK_INIT 0x00000000001fffff - -/* SH_PI_CRBP_ERROR_MASK_FSB_PROTO_ERR */ -/* Description: Mask detection internal protocol table misses */ -#define SH_PI_CRBP_ERROR_MASK_FSB_PROTO_ERR_SHFT 0 -#define SH_PI_CRBP_ERROR_MASK_FSB_PROTO_ERR_MASK 0x0000000000000001 - -/* SH_PI_CRBP_ERROR_MASK_GFX_RP_ERR */ -/* Description: Mask graphic reply error detection */ -#define SH_PI_CRBP_ERROR_MASK_GFX_RP_ERR_SHFT 1 -#define SH_PI_CRBP_ERROR_MASK_GFX_RP_ERR_MASK 0x0000000000000002 - -/* SH_PI_CRBP_ERROR_MASK_XB_PROTO_ERR */ -/* Description: Mask detection of external protocol table misses */ -#define SH_PI_CRBP_ERROR_MASK_XB_PROTO_ERR_SHFT 2 -#define SH_PI_CRBP_ERROR_MASK_XB_PROTO_ERR_MASK 0x0000000000000004 - -/* SH_PI_CRBP_ERROR_MASK_MEM_RP_ERR */ -/* Description: Mask memory error reply message detection */ -#define SH_PI_CRBP_ERROR_MASK_MEM_RP_ERR_SHFT 3 -#define SH_PI_CRBP_ERROR_MASK_MEM_RP_ERR_MASK 0x0000000000000008 - -/* SH_PI_CRBP_ERROR_MASK_PIO_RP_ERR */ -/* Description: Mask PIO reply error message detection */ -#define SH_PI_CRBP_ERROR_MASK_PIO_RP_ERR_SHFT 4 -#define SH_PI_CRBP_ERROR_MASK_PIO_RP_ERR_MASK 0x0000000000000010 - -/* SH_PI_CRBP_ERROR_MASK_MEM_TO_ERR */ -/* Description: Mask memory time-out detection */ -#define SH_PI_CRBP_ERROR_MASK_MEM_TO_ERR_SHFT 5 -#define SH_PI_CRBP_ERROR_MASK_MEM_TO_ERR_MASK 0x0000000000000020 - -/* SH_PI_CRBP_ERROR_MASK_PIO_TO_ERR */ -/* Description: Mask PIO time-out detection */ -#define SH_PI_CRBP_ERROR_MASK_PIO_TO_ERR_SHFT 6 -#define SH_PI_CRBP_ERROR_MASK_PIO_TO_ERR_MASK 0x0000000000000040 - -/* SH_PI_CRBP_ERROR_MASK_FSB_SHUB_UCE */ -/* Description: Mask un-correctable ECC error detection */ -#define SH_PI_CRBP_ERROR_MASK_FSB_SHUB_UCE_SHFT 7 -#define SH_PI_CRBP_ERROR_MASK_FSB_SHUB_UCE_MASK 0x0000000000000080 - -/* SH_PI_CRBP_ERROR_MASK_FSB_SHUB_CE */ -/* Description: Mask correctable ECC error detection */ -#define SH_PI_CRBP_ERROR_MASK_FSB_SHUB_CE_SHFT 8 -#define SH_PI_CRBP_ERROR_MASK_FSB_SHUB_CE_MASK 0x0000000000000100 - -/* SH_PI_CRBP_ERROR_MASK_MSG_COLOR_ERR */ -/* Description: Mask detection of color errors */ -#define SH_PI_CRBP_ERROR_MASK_MSG_COLOR_ERR_SHFT 9 -#define SH_PI_CRBP_ERROR_MASK_MSG_COLOR_ERR_MASK 0x0000000000000200 - -/* SH_PI_CRBP_ERROR_MASK_MD_RQ_Q_OFLOW */ -/* Description: Mask MD Request input buffer over flow error */ -#define SH_PI_CRBP_ERROR_MASK_MD_RQ_Q_OFLOW_SHFT 10 -#define SH_PI_CRBP_ERROR_MASK_MD_RQ_Q_OFLOW_MASK 0x0000000000000400 - -/* SH_PI_CRBP_ERROR_MASK_MD_RP_Q_OFLOW */ -/* Description: Mask MD Reply input buffer over flow error */ -#define SH_PI_CRBP_ERROR_MASK_MD_RP_Q_OFLOW_SHFT 11 -#define SH_PI_CRBP_ERROR_MASK_MD_RP_Q_OFLOW_MASK 0x0000000000000800 - -/* SH_PI_CRBP_ERROR_MASK_XN_RQ_Q_OFLOW */ -/* Description: Mask XN Request input buffer over flow error */ -#define SH_PI_CRBP_ERROR_MASK_XN_RQ_Q_OFLOW_SHFT 12 -#define SH_PI_CRBP_ERROR_MASK_XN_RQ_Q_OFLOW_MASK 0x0000000000001000 - -/* SH_PI_CRBP_ERROR_MASK_XN_RP_Q_OFLOW */ -/* Description: Mask XN Reply input buffer over flow error */ -#define SH_PI_CRBP_ERROR_MASK_XN_RP_Q_OFLOW_SHFT 13 -#define SH_PI_CRBP_ERROR_MASK_XN_RP_Q_OFLOW_MASK 0x0000000000002000 - -/* SH_PI_CRBP_ERROR_MASK_NACK_OFLOW */ -/* Description: Mask NACK over flow error */ -#define SH_PI_CRBP_ERROR_MASK_NACK_OFLOW_SHFT 14 -#define SH_PI_CRBP_ERROR_MASK_NACK_OFLOW_MASK 0x0000000000004000 - -/* SH_PI_CRBP_ERROR_MASK_GFX_INT_0 */ -/* Description: Mask GFX transfer interrupt for CPU 0 */ -#define SH_PI_CRBP_ERROR_MASK_GFX_INT_0_SHFT 15 -#define SH_PI_CRBP_ERROR_MASK_GFX_INT_0_MASK 0x0000000000008000 - -/* SH_PI_CRBP_ERROR_MASK_GFX_INT_1 */ -/* Description: Mask GFX transfer interrupt for CPU 1 */ -#define SH_PI_CRBP_ERROR_MASK_GFX_INT_1_SHFT 16 -#define SH_PI_CRBP_ERROR_MASK_GFX_INT_1_MASK 0x0000000000010000 - -/* SH_PI_CRBP_ERROR_MASK_MD_RQ_CRD_OFLOW */ -/* Description: Mask MD Request Credit Overflow Error */ -#define SH_PI_CRBP_ERROR_MASK_MD_RQ_CRD_OFLOW_SHFT 17 -#define SH_PI_CRBP_ERROR_MASK_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000 - -/* SH_PI_CRBP_ERROR_MASK_MD_RP_CRD_OFLOW */ -/* Description: Mask MD Reply Credit Overflow Error */ -#define SH_PI_CRBP_ERROR_MASK_MD_RP_CRD_OFLOW_SHFT 18 -#define SH_PI_CRBP_ERROR_MASK_MD_RP_CRD_OFLOW_MASK 0x0000000000040000 - -/* SH_PI_CRBP_ERROR_MASK_XN_RQ_CRD_OFLOW */ -/* Description: Mask XN Request Credit Overflow Error */ -#define SH_PI_CRBP_ERROR_MASK_XN_RQ_CRD_OFLOW_SHFT 19 -#define SH_PI_CRBP_ERROR_MASK_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000 - -/* SH_PI_CRBP_ERROR_MASK_XN_RP_CRD_OFLOW */ -/* Description: Mask XN Reply Credit Overflow Error */ -#define SH_PI_CRBP_ERROR_MASK_XN_RP_CRD_OFLOW_SHFT 20 -#define SH_PI_CRBP_ERROR_MASK_XN_RP_CRD_OFLOW_MASK 0x0000000000100000 - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_FSB_PIPE_COMPARE" */ -/* CRBP FSB Pipe Compare */ -/* ==================================================================== */ - -#define SH_PI_CRBP_FSB_PIPE_COMPARE 0x0000000120050580 -#define SH_PI_CRBP_FSB_PIPE_COMPARE_MASK 0x001fffffffffffff -#define SH_PI_CRBP_FSB_PIPE_COMPARE_INIT 0x0000000000000000 - -/* SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_ADDRESS */ -/* Description: Address A or B to compare against */ -#define SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_ADDRESS_SHFT 0 -#define SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_ADDRESS_MASK 0x00007fffffffffff - -/* SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_REQ */ -/* Description: REQa or REQb value to compare against */ -#define SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_REQ_SHFT 47 -#define SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_REQ_MASK 0x001f800000000000 - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_FSB_PIPE_MASK" */ -/* CRBP Compare Mask */ -/* ==================================================================== */ - -#define SH_PI_CRBP_FSB_PIPE_MASK 0x0000000120050600 -#define SH_PI_CRBP_FSB_PIPE_MASK_MASK 0x001fffffffffffff -#define SH_PI_CRBP_FSB_PIPE_MASK_INIT 0x0000000000000000 - -/* SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_ADDRESS_MASK */ -/* Description: Address A or B mask values */ -#define SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_ADDRESS_MASK_SHFT 0 -#define SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_ADDRESS_MASK_MASK 0x00007fffffffffff - -/* SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_REQ_MASK */ -/* Description: REQa or REQb mask values */ -#define SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_REQ_MASK_SHFT 47 -#define SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_REQ_MASK_MASK 0x001f800000000000 - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_TEST_POINT_COMPARE" */ -/* PI CRBP Test Point Compare */ -/* ==================================================================== */ - -#define SH_PI_CRBP_TEST_POINT_COMPARE 0x0000000120050680 -#define SH_PI_CRBP_TEST_POINT_COMPARE_MASK 0xffffffffffffffff -#define SH_PI_CRBP_TEST_POINT_COMPARE_INIT 0xffffffff00000000 - -/* SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_MASK */ -/* Description: Mask to select Debug bits for trigger generation */ -#define SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_MASK_SHFT 0 -#define SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_MASK_MASK 0x00000000ffffffff - -/* SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_PATTERN */ -/* Description: debug bit pattern for trigger generation */ -#define SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_PATTERN_SHFT 32 -#define SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_PATTERN_MASK 0xffffffff00000000 - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_TEST_POINT_SELECT" */ -/* PI CRBP Test Point Select */ -/* ==================================================================== */ - -#define SH_PI_CRBP_TEST_POINT_SELECT 0x0000000120050700 -#define SH_PI_CRBP_TEST_POINT_SELECT_MASK 0xf777777777777777 -#define SH_PI_CRBP_TEST_POINT_SELECT_INIT 0x0000000000000000 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL */ -/* Description: Nibble 0 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_SHFT 0 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000007 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_SHFT 4 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL */ -/* Description: Nibble 1 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_SHFT 8 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000700 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_SHFT 12 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL */ -/* Description: Nibble 2 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_SHFT 16 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000070000 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_SHFT 20 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL */ -/* Description: Nibble 3 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_SHFT 24 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_MASK 0x0000000007000000 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_SHFT 28 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL */ -/* Description: Nibble 4 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_SHFT 32 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_MASK 0x0000000700000000 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_SHFT 36 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL */ -/* Description: Nibble 5 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_SHFT 40 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_MASK 0x0000070000000000 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_SHFT 44 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL */ -/* Description: Nibble 6 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_SHFT 48 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_MASK 0x0007000000000000 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_SHFT 52 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL */ -/* Description: Nibble 7 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_SHFT 56 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_MASK 0x0700000000000000 - -/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_SHFT 60 -#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* SH_PI_CRBP_TEST_POINT_SELECT_TRIGGER_ENABLE */ -/* Description: Enable trigger on bit 32 of Analyzer data */ -#define SH_PI_CRBP_TEST_POINT_SELECT_TRIGGER_ENABLE_SHFT 63 -#define SH_PI_CRBP_TEST_POINT_SELECT_TRIGGER_ENABLE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT" */ -/* PI CRBP Test Point Trigger Select */ -/* ==================================================================== */ - -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT 0x0000000120050780 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_MASK 0x7777777777777777 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_INIT 0x0000000000000000 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL */ -/* Description: Nibble 0 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_SHFT 0 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_MASK 0x0000000000000007 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_SHFT 4 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL */ -/* Description: Nibble 1 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_SHFT 8 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_MASK 0x0000000000000700 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_SHFT 12 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL */ -/* Description: Nibble 2 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_SHFT 16 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_MASK 0x0000000000070000 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_SHFT 20 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL */ -/* Description: Nibble 3 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_SHFT 24 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_MASK 0x0000000007000000 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_SHFT 28 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL */ -/* Description: Nibble 4 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_SHFT 32 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_MASK 0x0000000700000000 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_SHFT 36 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL */ -/* Description: Nibble 5 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_SHFT 40 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_MASK 0x0000070000000000 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_SHFT 44 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL */ -/* Description: Nibble 6 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_SHFT 48 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_MASK 0x0007000000000000 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_SHFT 52 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL */ -/* Description: Nibble 7 Chiplet select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_SHFT 56 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_MASK 0x0700000000000000 - -/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_SHFT 60 -#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_XB_PIPE_COMPARE_0" */ -/* CRBP XB Pipe Compare */ -/* ==================================================================== */ - -#define SH_PI_CRBP_XB_PIPE_COMPARE_0 0x0000000120050800 -#define SH_PI_CRBP_XB_PIPE_COMPARE_0_MASK 0x007fffffffffffff -#define SH_PI_CRBP_XB_PIPE_COMPARE_0_INIT 0x0000000000000000 - -/* SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_ADDRESS */ -/* Description: Address to compare against */ -#define SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_ADDRESS_SHFT 0 -#define SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_ADDRESS_MASK 0x00007fffffffffff - -/* SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_COMMAND */ -/* Description: SN2NET Command to compare against */ -#define SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_COMMAND_SHFT 47 -#define SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_COMMAND_MASK 0x007f800000000000 - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_XB_PIPE_COMPARE_1" */ -/* CRBP XB Pipe Compare */ -/* ==================================================================== */ - -#define SH_PI_CRBP_XB_PIPE_COMPARE_1 0x0000000120050880 -#define SH_PI_CRBP_XB_PIPE_COMPARE_1_MASK 0x000001ff3fff3fff -#define SH_PI_CRBP_XB_PIPE_COMPARE_1_INIT 0x0000000000000000 - -/* SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SOURCE */ -/* Description: Source to compare against */ -#define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SOURCE_SHFT 0 -#define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SOURCE_MASK 0x0000000000003fff - -/* SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SUPPLEMENTAL */ -/* Description: Supplemental to compare against */ -#define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SUPPLEMENTAL_SHFT 16 -#define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SUPPLEMENTAL_MASK 0x000000003fff0000 - -/* SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_ECHO */ -/* Description: Echo to compare against */ -#define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_ECHO_SHFT 32 -#define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_ECHO_MASK 0x000001ff00000000 - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_XB_PIPE_MASK_0" */ -/* CRBP Compare Mask Register 1 */ -/* ==================================================================== */ - -#define SH_PI_CRBP_XB_PIPE_MASK_0 0x0000000120050900 -#define SH_PI_CRBP_XB_PIPE_MASK_0_MASK 0x007fffffffffffff -#define SH_PI_CRBP_XB_PIPE_MASK_0_INIT 0x0000000000000000 - -/* SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_ADDRESS_MASK */ -/* Description: Address to compare against */ -#define SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_ADDRESS_MASK_SHFT 0 -#define SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_ADDRESS_MASK_MASK 0x00007fffffffffff - -/* SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_COMMAND_MASK */ -/* Description: SN2NET Command to compare against */ -#define SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_COMMAND_MASK_SHFT 47 -#define SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_COMMAND_MASK_MASK 0x007f800000000000 - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_XB_PIPE_MASK_1" */ -/* CRBP XB Pipe Compare Mask Register 1 */ -/* ==================================================================== */ - -#define SH_PI_CRBP_XB_PIPE_MASK_1 0x0000000120050980 -#define SH_PI_CRBP_XB_PIPE_MASK_1_MASK 0x000001ff3fff3fff -#define SH_PI_CRBP_XB_PIPE_MASK_1_INIT 0x0000000000000000 - -/* SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SOURCE_MASK */ -/* Description: Source to compare against */ -#define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SOURCE_MASK_SHFT 0 -#define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SOURCE_MASK_MASK 0x0000000000003fff - -/* SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SUPPLEMENTAL_MASK */ -/* Description: Supplemental to compare against */ -#define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SUPPLEMENTAL_MASK_SHFT 16 -#define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SUPPLEMENTAL_MASK_MASK 0x000000003fff0000 - -/* SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_ECHO_MASK */ -/* Description: Echo to compare against */ -#define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_ECHO_MASK_SHFT 32 -#define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_ECHO_MASK_MASK 0x000001ff00000000 - -/* ==================================================================== */ -/* Register "SH_PI_DPC_QUEUE_CONFIG" */ -/* DPC Queue Configuration */ -/* ==================================================================== */ - -#define SH_PI_DPC_QUEUE_CONFIG 0x0000000120050a00 -#define SH_PI_DPC_QUEUE_CONFIG_MASK 0x000000001f1f1f1f -#define SH_PI_DPC_QUEUE_CONFIG_INIT 0x000000000c010c01 - -/* SH_PI_DPC_QUEUE_CONFIG_DWCQ_AE_LEVEL */ -/* Description: DXB WTL Command Queue Almost Empty Level */ -#define SH_PI_DPC_QUEUE_CONFIG_DWCQ_AE_LEVEL_SHFT 0 -#define SH_PI_DPC_QUEUE_CONFIG_DWCQ_AE_LEVEL_MASK 0x000000000000001f - -/* SH_PI_DPC_QUEUE_CONFIG_DWCQ_AF_THRESH */ -/* Description: DXB WTL Command Queue Almost Full Threshold */ -#define SH_PI_DPC_QUEUE_CONFIG_DWCQ_AF_THRESH_SHFT 8 -#define SH_PI_DPC_QUEUE_CONFIG_DWCQ_AF_THRESH_MASK 0x0000000000001f00 - -/* SH_PI_DPC_QUEUE_CONFIG_FWCQ_AE_LEVEL */ -/* Description: FSB WTL Command Queue Almost Empty Level */ -#define SH_PI_DPC_QUEUE_CONFIG_FWCQ_AE_LEVEL_SHFT 16 -#define SH_PI_DPC_QUEUE_CONFIG_FWCQ_AE_LEVEL_MASK 0x00000000001f0000 - -/* SH_PI_DPC_QUEUE_CONFIG_FWCQ_AF_THRESH */ -/* Description: FSB WTL Command Queue Almost Full Threshold */ -#define SH_PI_DPC_QUEUE_CONFIG_FWCQ_AF_THRESH_SHFT 24 -#define SH_PI_DPC_QUEUE_CONFIG_FWCQ_AF_THRESH_MASK 0x000000001f000000 - -/* ==================================================================== */ -/* Register "SH_PI_ERROR_MASK" */ -/* PI Error Mask */ -/* ==================================================================== */ - -#define SH_PI_ERROR_MASK 0x0000000120050a80 -#define SH_PI_ERROR_MASK_MASK 0x00000007ffffffff -#define SH_PI_ERROR_MASK_INIT 0x00000007ffffffff - -/* SH_PI_ERROR_MASK_FSB_PROTO_ERR */ -/* Description: Mask detection of internal protocol table misses */ -#define SH_PI_ERROR_MASK_FSB_PROTO_ERR_SHFT 0 -#define SH_PI_ERROR_MASK_FSB_PROTO_ERR_MASK 0x0000000000000001 - -/* SH_PI_ERROR_MASK_GFX_RP_ERR */ -/* Description: Mask graphic reply error message error detection */ -#define SH_PI_ERROR_MASK_GFX_RP_ERR_SHFT 1 -#define SH_PI_ERROR_MASK_GFX_RP_ERR_MASK 0x0000000000000002 - -/* SH_PI_ERROR_MASK_XB_PROTO_ERR */ -/* Description: Mask detection of external protocol table misses */ -#define SH_PI_ERROR_MASK_XB_PROTO_ERR_SHFT 2 -#define SH_PI_ERROR_MASK_XB_PROTO_ERR_MASK 0x0000000000000004 - -/* SH_PI_ERROR_MASK_MEM_RP_ERR */ -/* Description: Mask memory reply error detection */ -#define SH_PI_ERROR_MASK_MEM_RP_ERR_SHFT 3 -#define SH_PI_ERROR_MASK_MEM_RP_ERR_MASK 0x0000000000000008 - -/* SH_PI_ERROR_MASK_PIO_RP_ERR */ -/* Description: Mask PIO reply error detection */ -#define SH_PI_ERROR_MASK_PIO_RP_ERR_SHFT 4 -#define SH_PI_ERROR_MASK_PIO_RP_ERR_MASK 0x0000000000000010 - -/* SH_PI_ERROR_MASK_MEM_TO_ERR */ -/* Description: Mask CRB time-out errors */ -#define SH_PI_ERROR_MASK_MEM_TO_ERR_SHFT 5 -#define SH_PI_ERROR_MASK_MEM_TO_ERR_MASK 0x0000000000000020 - -/* SH_PI_ERROR_MASK_PIO_TO_ERR */ -/* Description: Mask PIO time-out errors */ -#define SH_PI_ERROR_MASK_PIO_TO_ERR_SHFT 6 -#define SH_PI_ERROR_MASK_PIO_TO_ERR_MASK 0x0000000000000040 - -/* SH_PI_ERROR_MASK_FSB_SHUB_UCE */ -/* Description: Mask un-correctable ECC error detection */ -#define SH_PI_ERROR_MASK_FSB_SHUB_UCE_SHFT 7 -#define SH_PI_ERROR_MASK_FSB_SHUB_UCE_MASK 0x0000000000000080 - -/* SH_PI_ERROR_MASK_FSB_SHUB_CE */ -/* Description: Mask correctable ECC error detection */ -#define SH_PI_ERROR_MASK_FSB_SHUB_CE_SHFT 8 -#define SH_PI_ERROR_MASK_FSB_SHUB_CE_MASK 0x0000000000000100 - -/* SH_PI_ERROR_MASK_MSG_COLOR_ERR */ -/* Description: Mask message color error detection */ -#define SH_PI_ERROR_MASK_MSG_COLOR_ERR_SHFT 9 -#define SH_PI_ERROR_MASK_MSG_COLOR_ERR_MASK 0x0000000000000200 - -/* SH_PI_ERROR_MASK_MD_RQ_Q_OFLOW */ -/* Description: Mask MD Request input buffer over flow error */ -#define SH_PI_ERROR_MASK_MD_RQ_Q_OFLOW_SHFT 10 -#define SH_PI_ERROR_MASK_MD_RQ_Q_OFLOW_MASK 0x0000000000000400 - -/* SH_PI_ERROR_MASK_MD_RP_Q_OFLOW */ -/* Description: Mask MD Reply input buffer over flow error */ -#define SH_PI_ERROR_MASK_MD_RP_Q_OFLOW_SHFT 11 -#define SH_PI_ERROR_MASK_MD_RP_Q_OFLOW_MASK 0x0000000000000800 - -/* SH_PI_ERROR_MASK_XN_RQ_Q_OFLOW */ -/* Description: Mask XN Request input buffer over flow error */ -#define SH_PI_ERROR_MASK_XN_RQ_Q_OFLOW_SHFT 12 -#define SH_PI_ERROR_MASK_XN_RQ_Q_OFLOW_MASK 0x0000000000001000 - -/* SH_PI_ERROR_MASK_XN_RP_Q_OFLOW */ -/* Description: Mask XN Reply input buffer over flow error */ -#define SH_PI_ERROR_MASK_XN_RP_Q_OFLOW_SHFT 13 -#define SH_PI_ERROR_MASK_XN_RP_Q_OFLOW_MASK 0x0000000000002000 - -/* SH_PI_ERROR_MASK_NACK_OFLOW */ -/* Description: Mask NACK over flow error */ -#define SH_PI_ERROR_MASK_NACK_OFLOW_SHFT 14 -#define SH_PI_ERROR_MASK_NACK_OFLOW_MASK 0x0000000000004000 - -/* SH_PI_ERROR_MASK_GFX_INT_0 */ -/* Description: Mask GFX transfer interrupt for CPU 0 */ -#define SH_PI_ERROR_MASK_GFX_INT_0_SHFT 15 -#define SH_PI_ERROR_MASK_GFX_INT_0_MASK 0x0000000000008000 - -/* SH_PI_ERROR_MASK_GFX_INT_1 */ -/* Description: Mask GFX transfer interrupt for CPU 1 */ -#define SH_PI_ERROR_MASK_GFX_INT_1_SHFT 16 -#define SH_PI_ERROR_MASK_GFX_INT_1_MASK 0x0000000000010000 - -/* SH_PI_ERROR_MASK_MD_RQ_CRD_OFLOW */ -/* Description: Mask MD Request Credit Overflow Error */ -#define SH_PI_ERROR_MASK_MD_RQ_CRD_OFLOW_SHFT 17 -#define SH_PI_ERROR_MASK_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000 - -/* SH_PI_ERROR_MASK_MD_RP_CRD_OFLOW */ -/* Description: Mask MD Reply Credit Overflow Error */ -#define SH_PI_ERROR_MASK_MD_RP_CRD_OFLOW_SHFT 18 -#define SH_PI_ERROR_MASK_MD_RP_CRD_OFLOW_MASK 0x0000000000040000 - -/* SH_PI_ERROR_MASK_XN_RQ_CRD_OFLOW */ -/* Description: Mask XN Request Credit Overflow Error */ -#define SH_PI_ERROR_MASK_XN_RQ_CRD_OFLOW_SHFT 19 -#define SH_PI_ERROR_MASK_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000 - -/* SH_PI_ERROR_MASK_XN_RP_CRD_OFLOW */ -/* Description: Mask XN Reply Credit Overflow Error */ -#define SH_PI_ERROR_MASK_XN_RP_CRD_OFLOW_SHFT 20 -#define SH_PI_ERROR_MASK_XN_RP_CRD_OFLOW_MASK 0x0000000000100000 - -/* SH_PI_ERROR_MASK_HUNG_BUS */ -/* Description: Mask FSB hung error */ -#define SH_PI_ERROR_MASK_HUNG_BUS_SHFT 21 -#define SH_PI_ERROR_MASK_HUNG_BUS_MASK 0x0000000000200000 - -/* SH_PI_ERROR_MASK_RSP_PARITY */ -/* Description: Parity error detecte during response phase */ -#define SH_PI_ERROR_MASK_RSP_PARITY_SHFT 22 -#define SH_PI_ERROR_MASK_RSP_PARITY_MASK 0x0000000000400000 - -/* SH_PI_ERROR_MASK_IOQ_OVERRUN */ -/* Description: Over run error detected on IOQ */ -#define SH_PI_ERROR_MASK_IOQ_OVERRUN_SHFT 23 -#define SH_PI_ERROR_MASK_IOQ_OVERRUN_MASK 0x0000000000800000 - -/* SH_PI_ERROR_MASK_REQ_FORMAT */ -/* Description: FSB request format not supported */ -#define SH_PI_ERROR_MASK_REQ_FORMAT_SHFT 24 -#define SH_PI_ERROR_MASK_REQ_FORMAT_MASK 0x0000000001000000 - -/* SH_PI_ERROR_MASK_ADDR_ACCESS */ -/* Description: Access to Address is not supported */ -#define SH_PI_ERROR_MASK_ADDR_ACCESS_SHFT 25 -#define SH_PI_ERROR_MASK_ADDR_ACCESS_MASK 0x0000000002000000 - -/* SH_PI_ERROR_MASK_REQ_PARITY */ -/* Description: Parity error detected during request phase */ -#define SH_PI_ERROR_MASK_REQ_PARITY_SHFT 26 -#define SH_PI_ERROR_MASK_REQ_PARITY_MASK 0x0000000004000000 - -/* SH_PI_ERROR_MASK_ADDR_PARITY */ -/* Description: Parity error detected on address */ -#define SH_PI_ERROR_MASK_ADDR_PARITY_SHFT 27 -#define SH_PI_ERROR_MASK_ADDR_PARITY_MASK 0x0000000008000000 - -/* SH_PI_ERROR_MASK_SHUB_FSB_DQE */ -/* Description: SHUB_FSB_DQE */ -#define SH_PI_ERROR_MASK_SHUB_FSB_DQE_SHFT 28 -#define SH_PI_ERROR_MASK_SHUB_FSB_DQE_MASK 0x0000000010000000 - -/* SH_PI_ERROR_MASK_SHUB_FSB_UCE */ -/* Description: An un-correctable ECC error was detected */ -#define SH_PI_ERROR_MASK_SHUB_FSB_UCE_SHFT 29 -#define SH_PI_ERROR_MASK_SHUB_FSB_UCE_MASK 0x0000000020000000 - -/* SH_PI_ERROR_MASK_SHUB_FSB_CE */ -/* Description: An correctable ECC error was detected */ -#define SH_PI_ERROR_MASK_SHUB_FSB_CE_SHFT 30 -#define SH_PI_ERROR_MASK_SHUB_FSB_CE_MASK 0x0000000040000000 - -/* SH_PI_ERROR_MASK_LIVELOCK */ -/* Description: AFI livelock error was detected */ -#define SH_PI_ERROR_MASK_LIVELOCK_SHFT 31 -#define SH_PI_ERROR_MASK_LIVELOCK_MASK 0x0000000080000000 - -/* SH_PI_ERROR_MASK_BAD_SNOOP */ -/* Description: AFI bad snoop error was detected */ -#define SH_PI_ERROR_MASK_BAD_SNOOP_SHFT 32 -#define SH_PI_ERROR_MASK_BAD_SNOOP_MASK 0x0000000100000000 - -/* SH_PI_ERROR_MASK_FSB_TBL_MISS */ -/* Description: AFI FSB request table miss error was detected */ -#define SH_PI_ERROR_MASK_FSB_TBL_MISS_SHFT 33 -#define SH_PI_ERROR_MASK_FSB_TBL_MISS_MASK 0x0000000200000000 - -/* SH_PI_ERROR_MASK_MSG_LENGTH */ -/* Description: Message length error on received message from SIC */ -#define SH_PI_ERROR_MASK_MSG_LENGTH_SHFT 34 -#define SH_PI_ERROR_MASK_MSG_LENGTH_MASK 0x0000000400000000 - -/* ==================================================================== */ -/* Register "SH_PI_EXPRESS_REPLY_CONFIG" */ -/* PI Express Reply Configuration */ -/* ==================================================================== */ - -#define SH_PI_EXPRESS_REPLY_CONFIG 0x0000000120050b00 -#define SH_PI_EXPRESS_REPLY_CONFIG_MASK 0x0000000000000007 -#define SH_PI_EXPRESS_REPLY_CONFIG_INIT 0x0000000000000001 - -/* SH_PI_EXPRESS_REPLY_CONFIG_MODE */ -/* Description: Express Reply Mode */ -#define SH_PI_EXPRESS_REPLY_CONFIG_MODE_SHFT 0 -#define SH_PI_EXPRESS_REPLY_CONFIG_MODE_MASK 0x0000000000000007 - -/* ==================================================================== */ -/* Register "SH_PI_FSB_COMPARE_VALUE" */ -/* FSB Compare Value */ -/* ==================================================================== */ - -#define SH_PI_FSB_COMPARE_VALUE 0x0000000120050c00 -#define SH_PI_FSB_COMPARE_VALUE_MASK 0xffffffffffffffff -#define SH_PI_FSB_COMPARE_VALUE_INIT 0x0000000000000000 - -/* SH_PI_FSB_COMPARE_VALUE_COMPARE_VALUE */ -/* Description: Compare value */ -#define SH_PI_FSB_COMPARE_VALUE_COMPARE_VALUE_SHFT 0 -#define SH_PI_FSB_COMPARE_VALUE_COMPARE_VALUE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_PI_FSB_COMPARE_MASK" */ -/* FSB Compare Mask */ -/* ==================================================================== */ - -#define SH_PI_FSB_COMPARE_MASK 0x0000000120050b80 -#define SH_PI_FSB_COMPARE_MASK_MASK 0xffffffffffffffff -#define SH_PI_FSB_COMPARE_MASK_INIT 0x0000000000000000 - -/* SH_PI_FSB_COMPARE_MASK_MASK_VALUE */ -/* Description: Mask value */ -#define SH_PI_FSB_COMPARE_MASK_MASK_VALUE_SHFT 0 -#define SH_PI_FSB_COMPARE_MASK_MASK_VALUE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_PI_FSB_ERROR_INJECTION" */ -/* Inject an Error onto the FSB */ -/* ==================================================================== */ - -#define SH_PI_FSB_ERROR_INJECTION 0x0000000120050c80 -#define SH_PI_FSB_ERROR_INJECTION_MASK 0x000000070fff03ff -#define SH_PI_FSB_ERROR_INJECTION_INIT 0x0000000000000000 - -/* SH_PI_FSB_ERROR_INJECTION_RP_PE_TO_FSB */ -/* Description: Inject a RP# Parity Error onto the FSB */ -#define SH_PI_FSB_ERROR_INJECTION_RP_PE_TO_FSB_SHFT 0 -#define SH_PI_FSB_ERROR_INJECTION_RP_PE_TO_FSB_MASK 0x0000000000000001 - -/* SH_PI_FSB_ERROR_INJECTION_AP0_PE_TO_FSB */ -/* Description: Inject an AP[0]# Parity Error onto the FSB */ -#define SH_PI_FSB_ERROR_INJECTION_AP0_PE_TO_FSB_SHFT 1 -#define SH_PI_FSB_ERROR_INJECTION_AP0_PE_TO_FSB_MASK 0x0000000000000002 - -/* SH_PI_FSB_ERROR_INJECTION_AP1_PE_TO_FSB */ -/* Description: Inject an AP[1]# Parity Error onto the FSB */ -#define SH_PI_FSB_ERROR_INJECTION_AP1_PE_TO_FSB_SHFT 2 -#define SH_PI_FSB_ERROR_INJECTION_AP1_PE_TO_FSB_MASK 0x0000000000000004 - -/* SH_PI_FSB_ERROR_INJECTION_RSP_PE_TO_FSB */ -/* Description: Inject a RSP# Parity Error onto the FSB */ -#define SH_PI_FSB_ERROR_INJECTION_RSP_PE_TO_FSB_SHFT 3 -#define SH_PI_FSB_ERROR_INJECTION_RSP_PE_TO_FSB_MASK 0x0000000000000008 - -/* SH_PI_FSB_ERROR_INJECTION_DW0_CE_TO_FSB */ -/* Description: Inject a Correctable Error in Doubleword 0 onto the */ -#define SH_PI_FSB_ERROR_INJECTION_DW0_CE_TO_FSB_SHFT 4 -#define SH_PI_FSB_ERROR_INJECTION_DW0_CE_TO_FSB_MASK 0x0000000000000010 - -/* SH_PI_FSB_ERROR_INJECTION_DW0_UCE_TO_FSB */ -/* Description: Inject an Uncorrectable Error in Doubleword 0 onto */ -/* the FSB */ -#define SH_PI_FSB_ERROR_INJECTION_DW0_UCE_TO_FSB_SHFT 5 -#define SH_PI_FSB_ERROR_INJECTION_DW0_UCE_TO_FSB_MASK 0x0000000000000020 - -/* SH_PI_FSB_ERROR_INJECTION_DW1_CE_TO_FSB */ -/* Description: Inject a Correctable Error in Doubleword 1 onto the */ -#define SH_PI_FSB_ERROR_INJECTION_DW1_CE_TO_FSB_SHFT 6 -#define SH_PI_FSB_ERROR_INJECTION_DW1_CE_TO_FSB_MASK 0x0000000000000040 - -/* SH_PI_FSB_ERROR_INJECTION_DW1_UCE_TO_FSB */ -/* Description: Inject an Uncorrectable Error in Doubleword 1 onto */ -/* the FSB */ -#define SH_PI_FSB_ERROR_INJECTION_DW1_UCE_TO_FSB_SHFT 7 -#define SH_PI_FSB_ERROR_INJECTION_DW1_UCE_TO_FSB_MASK 0x0000000000000080 - -/* SH_PI_FSB_ERROR_INJECTION_IP0_PE_TO_FSB */ -/* Description: Inject an IP[0]# Parity Error onto the FSB */ -#define SH_PI_FSB_ERROR_INJECTION_IP0_PE_TO_FSB_SHFT 8 -#define SH_PI_FSB_ERROR_INJECTION_IP0_PE_TO_FSB_MASK 0x0000000000000100 - -/* SH_PI_FSB_ERROR_INJECTION_IP1_PE_TO_FSB */ -/* Description: Inject an IP[1]# Parity Error onto the FSB */ -#define SH_PI_FSB_ERROR_INJECTION_IP1_PE_TO_FSB_SHFT 9 -#define SH_PI_FSB_ERROR_INJECTION_IP1_PE_TO_FSB_MASK 0x0000000000000200 - -/* SH_PI_FSB_ERROR_INJECTION_RP_PE_FROM_FSB */ -/* Description: Inject a RP# Parity Error When Sampling the FSB */ -#define SH_PI_FSB_ERROR_INJECTION_RP_PE_FROM_FSB_SHFT 16 -#define SH_PI_FSB_ERROR_INJECTION_RP_PE_FROM_FSB_MASK 0x0000000000010000 - -/* SH_PI_FSB_ERROR_INJECTION_AP0_PE_FROM_FSB */ -/* Description: Inject an AP[0]# Parity Error When Sampling the FSB */ -#define SH_PI_FSB_ERROR_INJECTION_AP0_PE_FROM_FSB_SHFT 17 -#define SH_PI_FSB_ERROR_INJECTION_AP0_PE_FROM_FSB_MASK 0x0000000000020000 - -/* SH_PI_FSB_ERROR_INJECTION_AP1_PE_FROM_FSB */ -/* Description: Inject an AP[1]# Parity Error When Sampling the FSB */ -#define SH_PI_FSB_ERROR_INJECTION_AP1_PE_FROM_FSB_SHFT 18 -#define SH_PI_FSB_ERROR_INJECTION_AP1_PE_FROM_FSB_MASK 0x0000000000040000 - -/* SH_PI_FSB_ERROR_INJECTION_RSP_PE_FROM_FSB */ -/* Description: Inject a RSP# Parity Error When Sampling the FSB */ -#define SH_PI_FSB_ERROR_INJECTION_RSP_PE_FROM_FSB_SHFT 19 -#define SH_PI_FSB_ERROR_INJECTION_RSP_PE_FROM_FSB_MASK 0x0000000000080000 - -/* SH_PI_FSB_ERROR_INJECTION_DW0_CE_FROM_FSB */ -/* Description: Inject a Correctable Error in Doubleword 0 of SIC D */ -/* ata Packet 0 */ -#define SH_PI_FSB_ERROR_INJECTION_DW0_CE_FROM_FSB_SHFT 20 -#define SH_PI_FSB_ERROR_INJECTION_DW0_CE_FROM_FSB_MASK 0x0000000000100000 - -/* SH_PI_FSB_ERROR_INJECTION_DW0_UCE_FROM_FSB */ -/* Description: Inject a Uncorrectable Error in Doubleword 0 of SIC */ -/* Data Packet 0 */ -#define SH_PI_FSB_ERROR_INJECTION_DW0_UCE_FROM_FSB_SHFT 21 -#define SH_PI_FSB_ERROR_INJECTION_DW0_UCE_FROM_FSB_MASK 0x0000000000200000 - -/* SH_PI_FSB_ERROR_INJECTION_DW1_CE_FROM_FSB */ -/* Description: Inject a Correctable Error in Doubleword 0 of SIC D */ -/* ata Packet 0 */ -#define SH_PI_FSB_ERROR_INJECTION_DW1_CE_FROM_FSB_SHFT 22 -#define SH_PI_FSB_ERROR_INJECTION_DW1_CE_FROM_FSB_MASK 0x0000000000400000 - -/* SH_PI_FSB_ERROR_INJECTION_DW1_UCE_FROM_FSB */ -/* Description: Inject a Uncorrectable Error in Doubleword 0 of SIC */ -/* Data Packet 0 */ -#define SH_PI_FSB_ERROR_INJECTION_DW1_UCE_FROM_FSB_SHFT 23 -#define SH_PI_FSB_ERROR_INJECTION_DW1_UCE_FROM_FSB_MASK 0x0000000000800000 - -/* SH_PI_FSB_ERROR_INJECTION_DW2_CE_FROM_FSB */ -/* Description: Inject a Correctable Error in Doubleword 0 of SIC D */ -/* ata Packet 0 */ -#define SH_PI_FSB_ERROR_INJECTION_DW2_CE_FROM_FSB_SHFT 24 -#define SH_PI_FSB_ERROR_INJECTION_DW2_CE_FROM_FSB_MASK 0x0000000001000000 - -/* SH_PI_FSB_ERROR_INJECTION_DW2_UCE_FROM_FSB */ -/* Description: Inject a Uncorrectable Error in Doubleword 0 of SIC */ -/* Data Packet 0 */ -#define SH_PI_FSB_ERROR_INJECTION_DW2_UCE_FROM_FSB_SHFT 25 -#define SH_PI_FSB_ERROR_INJECTION_DW2_UCE_FROM_FSB_MASK 0x0000000002000000 - -/* SH_PI_FSB_ERROR_INJECTION_DW3_CE_FROM_FSB */ -/* Description: Inject a Correctable Error in Doubleword 0 of SIC D */ -/* ata Packet 0 */ -#define SH_PI_FSB_ERROR_INJECTION_DW3_CE_FROM_FSB_SHFT 26 -#define SH_PI_FSB_ERROR_INJECTION_DW3_CE_FROM_FSB_MASK 0x0000000004000000 - -/* SH_PI_FSB_ERROR_INJECTION_DW3_UCE_FROM_FSB */ -/* Description: Inject a Uncorrectable Error in Doubleword 0 of SIC */ -/* Data Packet 0 */ -#define SH_PI_FSB_ERROR_INJECTION_DW3_UCE_FROM_FSB_SHFT 27 -#define SH_PI_FSB_ERROR_INJECTION_DW3_UCE_FROM_FSB_MASK 0x0000000008000000 - -/* SH_PI_FSB_ERROR_INJECTION_IOQ_OVERRUN */ -/* Description: Inject an ioq overrun Error on the FSB */ -#define SH_PI_FSB_ERROR_INJECTION_IOQ_OVERRUN_SHFT 32 -#define SH_PI_FSB_ERROR_INJECTION_IOQ_OVERRUN_MASK 0x0000000100000000 - -/* SH_PI_FSB_ERROR_INJECTION_LIVELOCK */ -/* Description: Inject a livelock Error on the FSB */ -#define SH_PI_FSB_ERROR_INJECTION_LIVELOCK_SHFT 33 -#define SH_PI_FSB_ERROR_INJECTION_LIVELOCK_MASK 0x0000000200000000 - -/* SH_PI_FSB_ERROR_INJECTION_BUS_HANG */ -/* Description: Inject an bus hang on the FSB */ -#define SH_PI_FSB_ERROR_INJECTION_BUS_HANG_SHFT 34 -#define SH_PI_FSB_ERROR_INJECTION_BUS_HANG_MASK 0x0000000400000000 - -/* ==================================================================== */ -/* Register "SH_PI_MD2PI_REPLY_VC_CONFIG" */ -/* MD-to-PI Reply Virtual Channel Configuration */ -/* ==================================================================== */ - -#define SH_PI_MD2PI_REPLY_VC_CONFIG 0x0000000120050d00 -#define SH_PI_MD2PI_REPLY_VC_CONFIG_MASK 0xc000000000003fff -#define SH_PI_MD2PI_REPLY_VC_CONFIG_INIT 0x000000000000088c - -/* SH_PI_MD2PI_REPLY_VC_CONFIG_HDR_DEPTH */ -/* Description: Depth of header Buffer */ -#define SH_PI_MD2PI_REPLY_VC_CONFIG_HDR_DEPTH_SHFT 0 -#define SH_PI_MD2PI_REPLY_VC_CONFIG_HDR_DEPTH_MASK 0x000000000000000f - -/* SH_PI_MD2PI_REPLY_VC_CONFIG_DATA_DEPTH */ -/* Description: Number of data buffers Available */ -#define SH_PI_MD2PI_REPLY_VC_CONFIG_DATA_DEPTH_SHFT 4 -#define SH_PI_MD2PI_REPLY_VC_CONFIG_DATA_DEPTH_MASK 0x00000000000000f0 - -/* SH_PI_MD2PI_REPLY_VC_CONFIG_MAX_CREDITS */ -/* Description: Maximum credits from sender */ -#define SH_PI_MD2PI_REPLY_VC_CONFIG_MAX_CREDITS_SHFT 8 -#define SH_PI_MD2PI_REPLY_VC_CONFIG_MAX_CREDITS_MASK 0x0000000000003f00 - -/* SH_PI_MD2PI_REPLY_VC_CONFIG_FORCE_CREDIT */ -/* Description: Send an extra credit to sender */ -#define SH_PI_MD2PI_REPLY_VC_CONFIG_FORCE_CREDIT_SHFT 62 -#define SH_PI_MD2PI_REPLY_VC_CONFIG_FORCE_CREDIT_MASK 0x4000000000000000 - -/* SH_PI_MD2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS */ -/* Description: Capture credit and status information */ -#define SH_PI_MD2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS_SHFT 63 -#define SH_PI_MD2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_MD2PI_REQUEST_VC_CONFIG" */ -/* MD-to-PI Request Virtual Channel Configuration */ -/* ==================================================================== */ - -#define SH_PI_MD2PI_REQUEST_VC_CONFIG 0x0000000120050d80 -#define SH_PI_MD2PI_REQUEST_VC_CONFIG_MASK 0xc000000000003fff -#define SH_PI_MD2PI_REQUEST_VC_CONFIG_INIT 0x000000000000088c - -/* SH_PI_MD2PI_REQUEST_VC_CONFIG_HDR_DEPTH */ -/* Description: Depth of header Buffer */ -#define SH_PI_MD2PI_REQUEST_VC_CONFIG_HDR_DEPTH_SHFT 0 -#define SH_PI_MD2PI_REQUEST_VC_CONFIG_HDR_DEPTH_MASK 0x000000000000000f - -/* SH_PI_MD2PI_REQUEST_VC_CONFIG_DATA_DEPTH */ -/* Description: Number of data buffers Available */ -#define SH_PI_MD2PI_REQUEST_VC_CONFIG_DATA_DEPTH_SHFT 4 -#define SH_PI_MD2PI_REQUEST_VC_CONFIG_DATA_DEPTH_MASK 0x00000000000000f0 - -/* SH_PI_MD2PI_REQUEST_VC_CONFIG_MAX_CREDITS */ -/* Description: Maximum credits from sender */ -#define SH_PI_MD2PI_REQUEST_VC_CONFIG_MAX_CREDITS_SHFT 8 -#define SH_PI_MD2PI_REQUEST_VC_CONFIG_MAX_CREDITS_MASK 0x0000000000003f00 - -/* SH_PI_MD2PI_REQUEST_VC_CONFIG_FORCE_CREDIT */ -/* Description: Send an extra credit to sender */ -#define SH_PI_MD2PI_REQUEST_VC_CONFIG_FORCE_CREDIT_SHFT 62 -#define SH_PI_MD2PI_REQUEST_VC_CONFIG_FORCE_CREDIT_MASK 0x4000000000000000 - -/* SH_PI_MD2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS */ -/* Description: Capture credit and status information */ -#define SH_PI_MD2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS_SHFT 63 -#define SH_PI_MD2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_QUEUE_ERROR_INJECTION" */ -/* PI Queue Error Injection */ -/* ==================================================================== */ - -#define SH_PI_QUEUE_ERROR_INJECTION 0x0000000120050e00 -#define SH_PI_QUEUE_ERROR_INJECTION_MASK 0x00000000000000ff -#define SH_PI_QUEUE_ERROR_INJECTION_INIT 0x0000000000000000 - -/* SH_PI_QUEUE_ERROR_INJECTION_DAT_DFR_Q */ -#define SH_PI_QUEUE_ERROR_INJECTION_DAT_DFR_Q_SHFT 0 -#define SH_PI_QUEUE_ERROR_INJECTION_DAT_DFR_Q_MASK 0x0000000000000001 - -/* SH_PI_QUEUE_ERROR_INJECTION_DXB_WTL_CMND_Q */ -#define SH_PI_QUEUE_ERROR_INJECTION_DXB_WTL_CMND_Q_SHFT 1 -#define SH_PI_QUEUE_ERROR_INJECTION_DXB_WTL_CMND_Q_MASK 0x0000000000000002 - -/* SH_PI_QUEUE_ERROR_INJECTION_FSB_WTL_CMND_Q */ -#define SH_PI_QUEUE_ERROR_INJECTION_FSB_WTL_CMND_Q_SHFT 2 -#define SH_PI_QUEUE_ERROR_INJECTION_FSB_WTL_CMND_Q_MASK 0x0000000000000004 - -/* SH_PI_QUEUE_ERROR_INJECTION_MDPI_RPY_BFR */ -#define SH_PI_QUEUE_ERROR_INJECTION_MDPI_RPY_BFR_SHFT 3 -#define SH_PI_QUEUE_ERROR_INJECTION_MDPI_RPY_BFR_MASK 0x0000000000000008 - -/* SH_PI_QUEUE_ERROR_INJECTION_PTC_INTR */ -#define SH_PI_QUEUE_ERROR_INJECTION_PTC_INTR_SHFT 4 -#define SH_PI_QUEUE_ERROR_INJECTION_PTC_INTR_MASK 0x0000000000000010 - -/* SH_PI_QUEUE_ERROR_INJECTION_RXL_KILL_Q */ -#define SH_PI_QUEUE_ERROR_INJECTION_RXL_KILL_Q_SHFT 5 -#define SH_PI_QUEUE_ERROR_INJECTION_RXL_KILL_Q_MASK 0x0000000000000020 - -/* SH_PI_QUEUE_ERROR_INJECTION_RXL_RDY_Q */ -#define SH_PI_QUEUE_ERROR_INJECTION_RXL_RDY_Q_SHFT 6 -#define SH_PI_QUEUE_ERROR_INJECTION_RXL_RDY_Q_MASK 0x0000000000000040 - -/* SH_PI_QUEUE_ERROR_INJECTION_XNPI_RPY_BFR */ -#define SH_PI_QUEUE_ERROR_INJECTION_XNPI_RPY_BFR_SHFT 7 -#define SH_PI_QUEUE_ERROR_INJECTION_XNPI_RPY_BFR_MASK 0x0000000000000080 - -/* ==================================================================== */ -/* Register "SH_PI_TEST_POINT_COMPARE" */ -/* PI Test Point Compare */ -/* ==================================================================== */ - -#define SH_PI_TEST_POINT_COMPARE 0x0000000120050e80 -#define SH_PI_TEST_POINT_COMPARE_MASK 0xffffffffffffffff -#define SH_PI_TEST_POINT_COMPARE_INIT 0xffffffff00000000 - -/* SH_PI_TEST_POINT_COMPARE_COMPARE_MASK */ -/* Description: Mask to select test point data for trigger generati */ -#define SH_PI_TEST_POINT_COMPARE_COMPARE_MASK_SHFT 0 -#define SH_PI_TEST_POINT_COMPARE_COMPARE_MASK_MASK 0x00000000ffffffff - -/* SH_PI_TEST_POINT_COMPARE_COMPARE_PATTERN */ -/* Description: Pattern of test point data to cause trigger */ -#define SH_PI_TEST_POINT_COMPARE_COMPARE_PATTERN_SHFT 32 -#define SH_PI_TEST_POINT_COMPARE_COMPARE_PATTERN_MASK 0xffffffff00000000 - -/* ==================================================================== */ -/* Register "SH_PI_TEST_POINT_SELECT" */ -/* PI Test Point Select */ -/* ==================================================================== */ - -#define SH_PI_TEST_POINT_SELECT 0x0000000120050f00 -#define SH_PI_TEST_POINT_SELECT_MASK 0xf777777777777777 -#define SH_PI_TEST_POINT_SELECT_INIT 0x0000000000000000 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL */ -/* Description: Nibble 0 data is from Chiplet X */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_SHFT 0 -#define SH_PI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000007 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL */ -/* Description: Nibble X is routed to Nibble 0 */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_SHFT 4 -#define SH_PI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL */ -/* Description: Nibble 1 data is from Chiplet X */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_SHFT 8 -#define SH_PI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000700 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL */ -/* Description: Nibble X is routed to Nibble 1 */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_SHFT 12 -#define SH_PI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL */ -/* Description: Nibble 2 data is from Chiplet X */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_SHFT 16 -#define SH_PI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000070000 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL */ -/* Description: Nibble X is routed to Nibble 2 */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_SHFT 20 -#define SH_PI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL */ -/* Description: Nibble 3 data is from Chiplet X */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_SHFT 24 -#define SH_PI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_MASK 0x0000000007000000 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL */ -/* Description: Nibble X is routed to Nibble 3 */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_SHFT 28 -#define SH_PI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL */ -/* Description: Nibble 4 data is from Chiplet X */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_SHFT 32 -#define SH_PI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_MASK 0x0000000700000000 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL */ -/* Description: Nibble X is routed to Nibble 4 */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_SHFT 36 -#define SH_PI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL */ -/* Description: Nibble 5 data is from Chiplet X */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_SHFT 40 -#define SH_PI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_MASK 0x0000070000000000 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL */ -/* Description: Nibble X is routed to Nibble 5 */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_SHFT 44 -#define SH_PI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL */ -/* Description: Nibble 6 data is from Chiplet X */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_SHFT 48 -#define SH_PI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_MASK 0x0007000000000000 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL */ -/* Description: Nibble X is routed to Nibble 6 */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_SHFT 52 -#define SH_PI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL */ -/* Description: Nibble 7 data is from Chiplet X */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_SHFT 56 -#define SH_PI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_MASK 0x0700000000000000 - -/* SH_PI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL */ -/* Description: Nibble X is routed to Nibble 7 */ -#define SH_PI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_SHFT 60 -#define SH_PI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* SH_PI_TEST_POINT_SELECT_TRIGGER_ENABLE */ -/* Description: Enable trigger on bit 32 of Analyzer data */ -#define SH_PI_TEST_POINT_SELECT_TRIGGER_ENABLE_SHFT 63 -#define SH_PI_TEST_POINT_SELECT_TRIGGER_ENABLE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_TEST_POINT_TRIGGER_SELECT" */ -/* PI Test Point Trigger Select */ -/* ==================================================================== */ - -#define SH_PI_TEST_POINT_TRIGGER_SELECT 0x0000000120050f80 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_MASK 0x7777777777777777 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_INIT 0x0000000000000000 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL */ -/* Description: Nibble 0 Chiplet select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_SHFT 0 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_MASK 0x0000000000000007 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_SHFT 4 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL */ -/* Description: Nibble 1 Chiplet select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_SHFT 8 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_MASK 0x0000000000000700 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_SHFT 12 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL */ -/* Description: Nibble 2 Chiplet select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_SHFT 16 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_MASK 0x0000000000070000 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_SHFT 20 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL */ -/* Description: Nibble 3 Chiplet select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_SHFT 24 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_MASK 0x0000000007000000 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_SHFT 28 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL */ -/* Description: Nibble 4 Chiplet select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_SHFT 32 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_MASK 0x0000000700000000 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_SHFT 36 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL */ -/* Description: Nibble 5 Chiplet select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_SHFT 40 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_MASK 0x0000070000000000 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_SHFT 44 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL */ -/* Description: Nibble 6 Chiplet select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_SHFT 48 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_MASK 0x0007000000000000 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_SHFT 52 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL */ -/* Description: Nibble 7 Chiplet select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_SHFT 56 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_MASK 0x0700000000000000 - -/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_SHFT 60 -#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_XN2PI_REPLY_VC_CONFIG" */ -/* XN-to-PI Reply Virtual Channel Configuration */ -/* ==================================================================== */ - -#define SH_PI_XN2PI_REPLY_VC_CONFIG 0x0000000120051000 -#define SH_PI_XN2PI_REPLY_VC_CONFIG_MASK 0xc000000000003fff -#define SH_PI_XN2PI_REPLY_VC_CONFIG_INIT 0x000000000000068c - -/* SH_PI_XN2PI_REPLY_VC_CONFIG_HDR_DEPTH */ -/* Description: Depth of header Buffer */ -#define SH_PI_XN2PI_REPLY_VC_CONFIG_HDR_DEPTH_SHFT 0 -#define SH_PI_XN2PI_REPLY_VC_CONFIG_HDR_DEPTH_MASK 0x000000000000000f - -/* SH_PI_XN2PI_REPLY_VC_CONFIG_DATA_DEPTH */ -/* Description: Number of data buffers Available */ -#define SH_PI_XN2PI_REPLY_VC_CONFIG_DATA_DEPTH_SHFT 4 -#define SH_PI_XN2PI_REPLY_VC_CONFIG_DATA_DEPTH_MASK 0x00000000000000f0 - -/* SH_PI_XN2PI_REPLY_VC_CONFIG_MAX_CREDITS */ -/* Description: Maximum credits from sender */ -#define SH_PI_XN2PI_REPLY_VC_CONFIG_MAX_CREDITS_SHFT 8 -#define SH_PI_XN2PI_REPLY_VC_CONFIG_MAX_CREDITS_MASK 0x0000000000003f00 - -/* SH_PI_XN2PI_REPLY_VC_CONFIG_FORCE_CREDIT */ -/* Description: Send an extra credit to sender */ -#define SH_PI_XN2PI_REPLY_VC_CONFIG_FORCE_CREDIT_SHFT 62 -#define SH_PI_XN2PI_REPLY_VC_CONFIG_FORCE_CREDIT_MASK 0x4000000000000000 - -/* SH_PI_XN2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS */ -/* Description: Capture credit and status information */ -#define SH_PI_XN2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS_SHFT 63 -#define SH_PI_XN2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_XN2PI_REQUEST_VC_CONFIG" */ -/* XN-to-PI Request Virtual Channel Configuration */ -/* ==================================================================== */ - -#define SH_PI_XN2PI_REQUEST_VC_CONFIG 0x0000000120051080 -#define SH_PI_XN2PI_REQUEST_VC_CONFIG_MASK 0xc000000000003fff -#define SH_PI_XN2PI_REQUEST_VC_CONFIG_INIT 0x000000000000068c - -/* SH_PI_XN2PI_REQUEST_VC_CONFIG_HDR_DEPTH */ -/* Description: Depth of header Buffer */ -#define SH_PI_XN2PI_REQUEST_VC_CONFIG_HDR_DEPTH_SHFT 0 -#define SH_PI_XN2PI_REQUEST_VC_CONFIG_HDR_DEPTH_MASK 0x000000000000000f - -/* SH_PI_XN2PI_REQUEST_VC_CONFIG_DATA_DEPTH */ -/* Description: Number of data buffers Available */ -#define SH_PI_XN2PI_REQUEST_VC_CONFIG_DATA_DEPTH_SHFT 4 -#define SH_PI_XN2PI_REQUEST_VC_CONFIG_DATA_DEPTH_MASK 0x00000000000000f0 - -/* SH_PI_XN2PI_REQUEST_VC_CONFIG_MAX_CREDITS */ -/* Description: Maximum credits from sender */ -#define SH_PI_XN2PI_REQUEST_VC_CONFIG_MAX_CREDITS_SHFT 8 -#define SH_PI_XN2PI_REQUEST_VC_CONFIG_MAX_CREDITS_MASK 0x0000000000003f00 - -/* SH_PI_XN2PI_REQUEST_VC_CONFIG_FORCE_CREDIT */ -/* Description: Send an extra credit to sender */ -#define SH_PI_XN2PI_REQUEST_VC_CONFIG_FORCE_CREDIT_SHFT 62 -#define SH_PI_XN2PI_REQUEST_VC_CONFIG_FORCE_CREDIT_MASK 0x4000000000000000 - -/* SH_PI_XN2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS */ -/* Description: Capture credit and status information */ -#define SH_PI_XN2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS_SHFT 63 -#define SH_PI_XN2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_AEC_STATUS" */ -/* PI Adaptive Error Correction Status */ -/* ==================================================================== */ - -#define SH_PI_AEC_STATUS 0x0000000120060000 -#define SH_PI_AEC_STATUS_MASK 0x0000000000000007 -#define SH_PI_AEC_STATUS_INIT 0x0000000000000000 - -/* SH_PI_AEC_STATUS_STATE */ -/* Description: AEC State */ -#define SH_PI_AEC_STATUS_STATE_SHFT 0 -#define SH_PI_AEC_STATUS_STATE_MASK 0x0000000000000007 - -/* ==================================================================== */ -/* Register "SH_PI_AFI_FIRST_ERROR" */ -/* PI AFI First Error */ -/* ==================================================================== */ - -#define SH_PI_AFI_FIRST_ERROR 0x0000000120060080 -#define SH_PI_AFI_FIRST_ERROR_MASK 0x00000007ffe00180 -#define SH_PI_AFI_FIRST_ERROR_INIT 0x0000000000000000 - -/* SH_PI_AFI_FIRST_ERROR_FSB_SHUB_UCE */ -/* Description: An un-correctable ECC error was detected */ -#define SH_PI_AFI_FIRST_ERROR_FSB_SHUB_UCE_SHFT 7 -#define SH_PI_AFI_FIRST_ERROR_FSB_SHUB_UCE_MASK 0x0000000000000080 - -/* SH_PI_AFI_FIRST_ERROR_FSB_SHUB_CE */ -/* Description: A correctable ECC error was detected */ -#define SH_PI_AFI_FIRST_ERROR_FSB_SHUB_CE_SHFT 8 -#define SH_PI_AFI_FIRST_ERROR_FSB_SHUB_CE_MASK 0x0000000000000100 - -/* SH_PI_AFI_FIRST_ERROR_HUNG_BUS */ -/* Description: FSB is hung */ -#define SH_PI_AFI_FIRST_ERROR_HUNG_BUS_SHFT 21 -#define SH_PI_AFI_FIRST_ERROR_HUNG_BUS_MASK 0x0000000000200000 - -/* SH_PI_AFI_FIRST_ERROR_RSP_PARITY */ -/* Description: Parity error detecte during response phase */ -#define SH_PI_AFI_FIRST_ERROR_RSP_PARITY_SHFT 22 -#define SH_PI_AFI_FIRST_ERROR_RSP_PARITY_MASK 0x0000000000400000 - -/* SH_PI_AFI_FIRST_ERROR_IOQ_OVERRUN */ -/* Description: Over run error detected on IOQ */ -#define SH_PI_AFI_FIRST_ERROR_IOQ_OVERRUN_SHFT 23 -#define SH_PI_AFI_FIRST_ERROR_IOQ_OVERRUN_MASK 0x0000000000800000 - -/* SH_PI_AFI_FIRST_ERROR_REQ_FORMAT */ -/* Description: FSB request format not supported */ -#define SH_PI_AFI_FIRST_ERROR_REQ_FORMAT_SHFT 24 -#define SH_PI_AFI_FIRST_ERROR_REQ_FORMAT_MASK 0x0000000001000000 - -/* SH_PI_AFI_FIRST_ERROR_ADDR_ACCESS */ -/* Description: Access to Address is not supported */ -#define SH_PI_AFI_FIRST_ERROR_ADDR_ACCESS_SHFT 25 -#define SH_PI_AFI_FIRST_ERROR_ADDR_ACCESS_MASK 0x0000000002000000 - -/* SH_PI_AFI_FIRST_ERROR_REQ_PARITY */ -/* Description: Parity error detected during request phase */ -#define SH_PI_AFI_FIRST_ERROR_REQ_PARITY_SHFT 26 -#define SH_PI_AFI_FIRST_ERROR_REQ_PARITY_MASK 0x0000000004000000 - -/* SH_PI_AFI_FIRST_ERROR_ADDR_PARITY */ -/* Description: Parity error detected on address */ -#define SH_PI_AFI_FIRST_ERROR_ADDR_PARITY_SHFT 27 -#define SH_PI_AFI_FIRST_ERROR_ADDR_PARITY_MASK 0x0000000008000000 - -/* SH_PI_AFI_FIRST_ERROR_SHUB_FSB_DQE */ -/* Description: SHUB_FSB_DQE */ -#define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_DQE_SHFT 28 -#define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_DQE_MASK 0x0000000010000000 - -/* SH_PI_AFI_FIRST_ERROR_SHUB_FSB_UCE */ -/* Description: An un-correctable ECC error was detected */ -#define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_UCE_SHFT 29 -#define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_UCE_MASK 0x0000000020000000 - -/* SH_PI_AFI_FIRST_ERROR_SHUB_FSB_CE */ -/* Description: An correctable ECC error was detected */ -#define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_CE_SHFT 30 -#define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_CE_MASK 0x0000000040000000 - -/* SH_PI_AFI_FIRST_ERROR_LIVELOCK */ -/* Description: AFI livelock error was detected */ -#define SH_PI_AFI_FIRST_ERROR_LIVELOCK_SHFT 31 -#define SH_PI_AFI_FIRST_ERROR_LIVELOCK_MASK 0x0000000080000000 - -/* SH_PI_AFI_FIRST_ERROR_BAD_SNOOP */ -/* Description: AFI bad snoop error was detected */ -#define SH_PI_AFI_FIRST_ERROR_BAD_SNOOP_SHFT 32 -#define SH_PI_AFI_FIRST_ERROR_BAD_SNOOP_MASK 0x0000000100000000 - -/* SH_PI_AFI_FIRST_ERROR_FSB_TBL_MISS */ -/* Description: AFI FSB request table miss error was detected */ -#define SH_PI_AFI_FIRST_ERROR_FSB_TBL_MISS_SHFT 33 -#define SH_PI_AFI_FIRST_ERROR_FSB_TBL_MISS_MASK 0x0000000200000000 - -/* SH_PI_AFI_FIRST_ERROR_MSG_LEN */ -/* Description: Runt or Obese message received from SIC */ -#define SH_PI_AFI_FIRST_ERROR_MSG_LEN_SHFT 34 -#define SH_PI_AFI_FIRST_ERROR_MSG_LEN_MASK 0x0000000400000000 - -/* ==================================================================== */ -/* Register "SH_PI_CAM_ADDRESS_READ_DATA" */ -/* CRB CAM MMR Address Read Data */ -/* ==================================================================== */ - -#define SH_PI_CAM_ADDRESS_READ_DATA 0x0000000120060100 -#define SH_PI_CAM_ADDRESS_READ_DATA_MASK 0x8000ffffffffffff -#define SH_PI_CAM_ADDRESS_READ_DATA_INIT 0x0000000000000000 - -/* SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR */ -/* Description: CRB CAM Address Read Data. */ -#define SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR_SHFT 0 -#define SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR_MASK 0x0000ffffffffffff - -/* SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR_VAL */ -/* Description: CRB CAM Address Read Data Valid. */ -#define SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR_VAL_SHFT 63 -#define SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR_VAL_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_CAM_LPRA_READ_DATA" */ -/* CRB CAM MMR LPRA Read Data */ -/* ==================================================================== */ - -#define SH_PI_CAM_LPRA_READ_DATA 0x0000000120060180 -#define SH_PI_CAM_LPRA_READ_DATA_MASK 0xffffffffffffffff -#define SH_PI_CAM_LPRA_READ_DATA_INIT 0x0000000000000000 - -/* SH_PI_CAM_LPRA_READ_DATA_CAM_LPRA */ -/* Description: CRB CAM LPRA read data. */ -#define SH_PI_CAM_LPRA_READ_DATA_CAM_LPRA_SHFT 0 -#define SH_PI_CAM_LPRA_READ_DATA_CAM_LPRA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_PI_CAM_STATE_READ_DATA" */ -/* CRB CAM MMR State Read Data */ -/* ==================================================================== */ - -#define SH_PI_CAM_STATE_READ_DATA 0x0000000120060200 -#define SH_PI_CAM_STATE_READ_DATA_MASK 0x8003ffff0000003f -#define SH_PI_CAM_STATE_READ_DATA_INIT 0x0000000000000000 - -/* SH_PI_CAM_STATE_READ_DATA_CAM_STATE */ -/* Description: CRB CAM State read data. */ -#define SH_PI_CAM_STATE_READ_DATA_CAM_STATE_SHFT 0 -#define SH_PI_CAM_STATE_READ_DATA_CAM_STATE_MASK 0x000000000000000f - -/* SH_PI_CAM_STATE_READ_DATA_CAM_TO */ -/* Description: CRB CAM Time-out Status. */ -#define SH_PI_CAM_STATE_READ_DATA_CAM_TO_SHFT 4 -#define SH_PI_CAM_STATE_READ_DATA_CAM_TO_MASK 0x0000000000000010 - -/* SH_PI_CAM_STATE_READ_DATA_CAM_STATE_RD_PEND */ -/* Description: CRB CAM State Read Pending. */ -#define SH_PI_CAM_STATE_READ_DATA_CAM_STATE_RD_PEND_SHFT 5 -#define SH_PI_CAM_STATE_READ_DATA_CAM_STATE_RD_PEND_MASK 0x0000000000000020 - -/* SH_PI_CAM_STATE_READ_DATA_CAM_LPRA */ -/* Description: CRB LPRA Overflow Data. */ -#define SH_PI_CAM_STATE_READ_DATA_CAM_LPRA_SHFT 32 -#define SH_PI_CAM_STATE_READ_DATA_CAM_LPRA_MASK 0x0003ffff00000000 - -/* SH_PI_CAM_STATE_READ_DATA_CAM_RD_DATA_VAL */ -/* Description: CRB CAM MMR read data is valid. */ -#define SH_PI_CAM_STATE_READ_DATA_CAM_RD_DATA_VAL_SHFT 63 -#define SH_PI_CAM_STATE_READ_DATA_CAM_RD_DATA_VAL_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_CORRECTED_DETAIL_1" */ -/* PI Corrected Error Detail */ -/* ==================================================================== */ - -#define SH_PI_CORRECTED_DETAIL_1 0x0000000120060280 -#define SH_PI_CORRECTED_DETAIL_1_MASK 0xffffffffffffffff -#define SH_PI_CORRECTED_DETAIL_1_INIT 0x0000000000000000 - -/* SH_PI_CORRECTED_DETAIL_1_ADDRESS */ -/* Description: Address of Message that logged Correctable Error */ -#define SH_PI_CORRECTED_DETAIL_1_ADDRESS_SHFT 0 -#define SH_PI_CORRECTED_DETAIL_1_ADDRESS_MASK 0x0000ffffffffffff - -/* SH_PI_CORRECTED_DETAIL_1_SYNDROME */ -/* Description: Syndrome for double word data with Correctable Erro */ -#define SH_PI_CORRECTED_DETAIL_1_SYNDROME_SHFT 48 -#define SH_PI_CORRECTED_DETAIL_1_SYNDROME_MASK 0x00ff000000000000 - -/* SH_PI_CORRECTED_DETAIL_1_DEP */ -/* Description: DEP code for Double word in error */ -#define SH_PI_CORRECTED_DETAIL_1_DEP_SHFT 56 -#define SH_PI_CORRECTED_DETAIL_1_DEP_MASK 0xff00000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_CORRECTED_DETAIL_2" */ -/* PI Corrected Error Detail 2 */ -/* ==================================================================== */ - -#define SH_PI_CORRECTED_DETAIL_2 0x0000000120060300 -#define SH_PI_CORRECTED_DETAIL_2_MASK 0xffffffffffffffff -#define SH_PI_CORRECTED_DETAIL_2_INIT 0x0000000000000000 - -/* SH_PI_CORRECTED_DETAIL_2_DATA */ -/* Description: Double word data in error */ -#define SH_PI_CORRECTED_DETAIL_2_DATA_SHFT 0 -#define SH_PI_CORRECTED_DETAIL_2_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_PI_CORRECTED_DETAIL_3" */ -/* PI Corrected Error Detail 3 */ -/* ==================================================================== */ - -#define SH_PI_CORRECTED_DETAIL_3 0x0000000120060380 -#define SH_PI_CORRECTED_DETAIL_3_MASK 0xffffffffffffffff -#define SH_PI_CORRECTED_DETAIL_3_INIT 0x0000000000000000 - -/* SH_PI_CORRECTED_DETAIL_3_ADDRESS */ -/* Description: Address of Message that logged Correctable Error */ -#define SH_PI_CORRECTED_DETAIL_3_ADDRESS_SHFT 0 -#define SH_PI_CORRECTED_DETAIL_3_ADDRESS_MASK 0x0000ffffffffffff - -/* SH_PI_CORRECTED_DETAIL_3_SYNDROME */ -/* Description: Syndrome for double word data with Correctable Erro */ -#define SH_PI_CORRECTED_DETAIL_3_SYNDROME_SHFT 48 -#define SH_PI_CORRECTED_DETAIL_3_SYNDROME_MASK 0x00ff000000000000 - -/* SH_PI_CORRECTED_DETAIL_3_DEP */ -/* Description: DEP code for Double word in error */ -#define SH_PI_CORRECTED_DETAIL_3_DEP_SHFT 56 -#define SH_PI_CORRECTED_DETAIL_3_DEP_MASK 0xff00000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_CORRECTED_DETAIL_4" */ -/* PI Corrected Error Detail 4 */ -/* ==================================================================== */ - -#define SH_PI_CORRECTED_DETAIL_4 0x0000000120060400 -#define SH_PI_CORRECTED_DETAIL_4_MASK 0xffffffffffffffff -#define SH_PI_CORRECTED_DETAIL_4_INIT 0x0000000000000000 - -/* SH_PI_CORRECTED_DETAIL_4_DATA */ -/* Description: Double word data in error */ -#define SH_PI_CORRECTED_DETAIL_4_DATA_SHFT 0 -#define SH_PI_CORRECTED_DETAIL_4_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_PI_CRBP_FIRST_ERROR" */ -/* PI CRBP First Error */ -/* ==================================================================== */ - -#define SH_PI_CRBP_FIRST_ERROR 0x0000000120060480 -#define SH_PI_CRBP_FIRST_ERROR_MASK 0x00000000001fffff -#define SH_PI_CRBP_FIRST_ERROR_INIT 0x0000000000000000 - -/* SH_PI_CRBP_FIRST_ERROR_FSB_PROTO_ERR */ -/* Description: CRB's FSB pipe detected protocol table miss */ -#define SH_PI_CRBP_FIRST_ERROR_FSB_PROTO_ERR_SHFT 0 -#define SH_PI_CRBP_FIRST_ERROR_FSB_PROTO_ERR_MASK 0x0000000000000001 - -/* SH_PI_CRBP_FIRST_ERROR_GFX_RP_ERR */ -/* Description: CRB's XB pipe received a GFX error reply */ -#define SH_PI_CRBP_FIRST_ERROR_GFX_RP_ERR_SHFT 1 -#define SH_PI_CRBP_FIRST_ERROR_GFX_RP_ERR_MASK 0x0000000000000002 - -/* SH_PI_CRBP_FIRST_ERROR_XB_PROTO_ERR */ -/* Description: CRB's XB pipe detected protocol table miss */ -#define SH_PI_CRBP_FIRST_ERROR_XB_PROTO_ERR_SHFT 2 -#define SH_PI_CRBP_FIRST_ERROR_XB_PROTO_ERR_MASK 0x0000000000000004 - -/* SH_PI_CRBP_FIRST_ERROR_MEM_RP_ERR */ -/* Description: CRB's XB pipe received a memory error reply message */ -#define SH_PI_CRBP_FIRST_ERROR_MEM_RP_ERR_SHFT 3 -#define SH_PI_CRBP_FIRST_ERROR_MEM_RP_ERR_MASK 0x0000000000000008 - -/* SH_PI_CRBP_FIRST_ERROR_PIO_RP_ERR */ -/* Description: CRB's XB pipe received a PIO error reply message */ -#define SH_PI_CRBP_FIRST_ERROR_PIO_RP_ERR_SHFT 4 -#define SH_PI_CRBP_FIRST_ERROR_PIO_RP_ERR_MASK 0x0000000000000010 - -/* SH_PI_CRBP_FIRST_ERROR_MEM_TO_ERR */ -/* Description: CRB's XB pipe detected a CRB time-out */ -#define SH_PI_CRBP_FIRST_ERROR_MEM_TO_ERR_SHFT 5 -#define SH_PI_CRBP_FIRST_ERROR_MEM_TO_ERR_MASK 0x0000000000000020 - -/* SH_PI_CRBP_FIRST_ERROR_PIO_TO_ERR */ -/* Description: CRB's XB pipe detected a PIO time-out */ -#define SH_PI_CRBP_FIRST_ERROR_PIO_TO_ERR_SHFT 6 -#define SH_PI_CRBP_FIRST_ERROR_PIO_TO_ERR_MASK 0x0000000000000040 - -/* SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_UCE */ -/* Description: An un-correctable ECC error was detected */ -#define SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_UCE_SHFT 7 -#define SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_UCE_MASK 0x0000000000000080 - -/* SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_CE */ -/* Description: A correctable ECC error was detected */ -#define SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_CE_SHFT 8 -#define SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_CE_MASK 0x0000000000000100 - -/* SH_PI_CRBP_FIRST_ERROR_MSG_COLOR_ERR */ -/* Description: Message color was wrong */ -#define SH_PI_CRBP_FIRST_ERROR_MSG_COLOR_ERR_SHFT 9 -#define SH_PI_CRBP_FIRST_ERROR_MSG_COLOR_ERR_MASK 0x0000000000000200 - -/* SH_PI_CRBP_FIRST_ERROR_MD_RQ_Q_OFLOW */ -/* Description: MD Request input buffer over flow error */ -#define SH_PI_CRBP_FIRST_ERROR_MD_RQ_Q_OFLOW_SHFT 10 -#define SH_PI_CRBP_FIRST_ERROR_MD_RQ_Q_OFLOW_MASK 0x0000000000000400 - -/* SH_PI_CRBP_FIRST_ERROR_MD_RP_Q_OFLOW */ -/* Description: MD Reply input buffer over flow error */ -#define SH_PI_CRBP_FIRST_ERROR_MD_RP_Q_OFLOW_SHFT 11 -#define SH_PI_CRBP_FIRST_ERROR_MD_RP_Q_OFLOW_MASK 0x0000000000000800 - -/* SH_PI_CRBP_FIRST_ERROR_XN_RQ_Q_OFLOW */ -/* Description: XN Request input buffer over flow error */ -#define SH_PI_CRBP_FIRST_ERROR_XN_RQ_Q_OFLOW_SHFT 12 -#define SH_PI_CRBP_FIRST_ERROR_XN_RQ_Q_OFLOW_MASK 0x0000000000001000 - -/* SH_PI_CRBP_FIRST_ERROR_XN_RP_Q_OFLOW */ -/* Description: XN Reply input buffer over flow error */ -#define SH_PI_CRBP_FIRST_ERROR_XN_RP_Q_OFLOW_SHFT 13 -#define SH_PI_CRBP_FIRST_ERROR_XN_RP_Q_OFLOW_MASK 0x0000000000002000 - -/* SH_PI_CRBP_FIRST_ERROR_NACK_OFLOW */ -/* Description: NACK over flow error */ -#define SH_PI_CRBP_FIRST_ERROR_NACK_OFLOW_SHFT 14 -#define SH_PI_CRBP_FIRST_ERROR_NACK_OFLOW_MASK 0x0000000000004000 - -/* SH_PI_CRBP_FIRST_ERROR_GFX_INT_0 */ -/* Description: GFX transfer interrupt for CPU 0 */ -#define SH_PI_CRBP_FIRST_ERROR_GFX_INT_0_SHFT 15 -#define SH_PI_CRBP_FIRST_ERROR_GFX_INT_0_MASK 0x0000000000008000 - -/* SH_PI_CRBP_FIRST_ERROR_GFX_INT_1 */ -/* Description: GFX transfer interrupt for CPU 1 */ -#define SH_PI_CRBP_FIRST_ERROR_GFX_INT_1_SHFT 16 -#define SH_PI_CRBP_FIRST_ERROR_GFX_INT_1_MASK 0x0000000000010000 - -/* SH_PI_CRBP_FIRST_ERROR_MD_RQ_CRD_OFLOW */ -/* Description: MD Request Credit Overflow Error */ -#define SH_PI_CRBP_FIRST_ERROR_MD_RQ_CRD_OFLOW_SHFT 17 -#define SH_PI_CRBP_FIRST_ERROR_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000 - -/* SH_PI_CRBP_FIRST_ERROR_MD_RP_CRD_OFLOW */ -/* Description: MD Reply Credit Overflow Error */ -#define SH_PI_CRBP_FIRST_ERROR_MD_RP_CRD_OFLOW_SHFT 18 -#define SH_PI_CRBP_FIRST_ERROR_MD_RP_CRD_OFLOW_MASK 0x0000000000040000 - -/* SH_PI_CRBP_FIRST_ERROR_XN_RQ_CRD_OFLOW */ -/* Description: XN Request Credit Overflow Error */ -#define SH_PI_CRBP_FIRST_ERROR_XN_RQ_CRD_OFLOW_SHFT 19 -#define SH_PI_CRBP_FIRST_ERROR_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000 - -/* SH_PI_CRBP_FIRST_ERROR_XN_RP_CRD_OFLOW */ -/* Description: XN Reply Credit Overflow Error */ -#define SH_PI_CRBP_FIRST_ERROR_XN_RP_CRD_OFLOW_SHFT 20 -#define SH_PI_CRBP_FIRST_ERROR_XN_RP_CRD_OFLOW_MASK 0x0000000000100000 - -/* ==================================================================== */ -/* Register "SH_PI_ERROR_DETAIL_1" */ -/* PI Error Detail 1 */ -/* ==================================================================== */ - -#define SH_PI_ERROR_DETAIL_1 0x0000000120060500 -#define SH_PI_ERROR_DETAIL_1_MASK 0xffffffffffffffff -#define SH_PI_ERROR_DETAIL_1_INIT 0x0000000000000000 - -/* SH_PI_ERROR_DETAIL_1_STATUS */ -/* Description: Error Detail 1 */ -#define SH_PI_ERROR_DETAIL_1_STATUS_SHFT 0 -#define SH_PI_ERROR_DETAIL_1_STATUS_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_PI_ERROR_DETAIL_2" */ -/* PI Error Detail 2 */ -/* ==================================================================== */ - -#define SH_PI_ERROR_DETAIL_2 0x0000000120060580 -#define SH_PI_ERROR_DETAIL_2_MASK 0xffffffffffffffff -#define SH_PI_ERROR_DETAIL_2_INIT 0x0000000000000000 - -/* SH_PI_ERROR_DETAIL_2_STATUS */ -/* Description: Error Status */ -#define SH_PI_ERROR_DETAIL_2_STATUS_SHFT 0 -#define SH_PI_ERROR_DETAIL_2_STATUS_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_PI_ERROR_OVERFLOW" */ -/* PI Error Overflow */ -/* ==================================================================== */ - -#define SH_PI_ERROR_OVERFLOW 0x0000000120060600 -#define SH_PI_ERROR_OVERFLOW_MASK 0x00000007ffffffff -#define SH_PI_ERROR_OVERFLOW_INIT 0x0000000000000000 - -/* SH_PI_ERROR_OVERFLOW_FSB_PROTO_ERR */ -/* Description: CRB's FSB pipe detected protocol table miss */ -#define SH_PI_ERROR_OVERFLOW_FSB_PROTO_ERR_SHFT 0 -#define SH_PI_ERROR_OVERFLOW_FSB_PROTO_ERR_MASK 0x0000000000000001 - -/* SH_PI_ERROR_OVERFLOW_GFX_RP_ERR */ -/* Description: CRB's XB pipe received another GFX reply error mess */ -#define SH_PI_ERROR_OVERFLOW_GFX_RP_ERR_SHFT 1 -#define SH_PI_ERROR_OVERFLOW_GFX_RP_ERR_MASK 0x0000000000000002 - -/* SH_PI_ERROR_OVERFLOW_XB_PROTO_ERR */ -/* Description: CRB's XB pipe detected another protocol table miss */ -#define SH_PI_ERROR_OVERFLOW_XB_PROTO_ERR_SHFT 2 -#define SH_PI_ERROR_OVERFLOW_XB_PROTO_ERR_MASK 0x0000000000000004 - -/* SH_PI_ERROR_OVERFLOW_MEM_RP_ERR */ -/* Description: CRB's XB pipe received another memory reply error m */ -#define SH_PI_ERROR_OVERFLOW_MEM_RP_ERR_SHFT 3 -#define SH_PI_ERROR_OVERFLOW_MEM_RP_ERR_MASK 0x0000000000000008 - -/* SH_PI_ERROR_OVERFLOW_PIO_RP_ERR */ -/* Description: CRB's XB pipe received another PIO reply error mess */ -#define SH_PI_ERROR_OVERFLOW_PIO_RP_ERR_SHFT 4 -#define SH_PI_ERROR_OVERFLOW_PIO_RP_ERR_MASK 0x0000000000000010 - -/* SH_PI_ERROR_OVERFLOW_MEM_TO_ERR */ -/* Description: CRB's XB pipe detected a CRB time-out */ -#define SH_PI_ERROR_OVERFLOW_MEM_TO_ERR_SHFT 5 -#define SH_PI_ERROR_OVERFLOW_MEM_TO_ERR_MASK 0x0000000000000020 - -/* SH_PI_ERROR_OVERFLOW_PIO_TO_ERR */ -/* Description: CRB's XB pipe detected a PIO time-out */ -#define SH_PI_ERROR_OVERFLOW_PIO_TO_ERR_SHFT 6 -#define SH_PI_ERROR_OVERFLOW_PIO_TO_ERR_MASK 0x0000000000000040 - -/* SH_PI_ERROR_OVERFLOW_FSB_SHUB_UCE */ -/* Description: An un-correctable ECC error was detected */ -#define SH_PI_ERROR_OVERFLOW_FSB_SHUB_UCE_SHFT 7 -#define SH_PI_ERROR_OVERFLOW_FSB_SHUB_UCE_MASK 0x0000000000000080 - -/* SH_PI_ERROR_OVERFLOW_FSB_SHUB_CE */ -/* Description: An correctable ECC error was detected */ -#define SH_PI_ERROR_OVERFLOW_FSB_SHUB_CE_SHFT 8 -#define SH_PI_ERROR_OVERFLOW_FSB_SHUB_CE_MASK 0x0000000000000100 - -/* SH_PI_ERROR_OVERFLOW_MSG_COLOR_ERR */ -/* Description: Message color was not correct */ -#define SH_PI_ERROR_OVERFLOW_MSG_COLOR_ERR_SHFT 9 -#define SH_PI_ERROR_OVERFLOW_MSG_COLOR_ERR_MASK 0x0000000000000200 - -/* SH_PI_ERROR_OVERFLOW_MD_RQ_Q_OFLOW */ -/* Description: MD Request input buffer over flow error */ -#define SH_PI_ERROR_OVERFLOW_MD_RQ_Q_OFLOW_SHFT 10 -#define SH_PI_ERROR_OVERFLOW_MD_RQ_Q_OFLOW_MASK 0x0000000000000400 - -/* SH_PI_ERROR_OVERFLOW_MD_RP_Q_OFLOW */ -/* Description: MD Reply input buffer over flow error */ -#define SH_PI_ERROR_OVERFLOW_MD_RP_Q_OFLOW_SHFT 11 -#define SH_PI_ERROR_OVERFLOW_MD_RP_Q_OFLOW_MASK 0x0000000000000800 - -/* SH_PI_ERROR_OVERFLOW_XN_RQ_Q_OFLOW */ -/* Description: XN Request input buffer over flow error */ -#define SH_PI_ERROR_OVERFLOW_XN_RQ_Q_OFLOW_SHFT 12 -#define SH_PI_ERROR_OVERFLOW_XN_RQ_Q_OFLOW_MASK 0x0000000000001000 - -/* SH_PI_ERROR_OVERFLOW_XN_RP_Q_OFLOW */ -/* Description: XN Reply input buffer over flow error */ -#define SH_PI_ERROR_OVERFLOW_XN_RP_Q_OFLOW_SHFT 13 -#define SH_PI_ERROR_OVERFLOW_XN_RP_Q_OFLOW_MASK 0x0000000000002000 - -/* SH_PI_ERROR_OVERFLOW_NACK_OFLOW */ -/* Description: NACK over flow error */ -#define SH_PI_ERROR_OVERFLOW_NACK_OFLOW_SHFT 14 -#define SH_PI_ERROR_OVERFLOW_NACK_OFLOW_MASK 0x0000000000004000 - -/* SH_PI_ERROR_OVERFLOW_GFX_INT_0 */ -/* Description: GFX transfer interrupt for CPU 0 */ -#define SH_PI_ERROR_OVERFLOW_GFX_INT_0_SHFT 15 -#define SH_PI_ERROR_OVERFLOW_GFX_INT_0_MASK 0x0000000000008000 - -/* SH_PI_ERROR_OVERFLOW_GFX_INT_1 */ -/* Description: GFX transfer interrupt for CPU 1 */ -#define SH_PI_ERROR_OVERFLOW_GFX_INT_1_SHFT 16 -#define SH_PI_ERROR_OVERFLOW_GFX_INT_1_MASK 0x0000000000010000 - -/* SH_PI_ERROR_OVERFLOW_MD_RQ_CRD_OFLOW */ -/* Description: MD Request Credit Overflow Error */ -#define SH_PI_ERROR_OVERFLOW_MD_RQ_CRD_OFLOW_SHFT 17 -#define SH_PI_ERROR_OVERFLOW_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000 - -/* SH_PI_ERROR_OVERFLOW_MD_RP_CRD_OFLOW */ -/* Description: MD Reply Credit Overflow Error */ -#define SH_PI_ERROR_OVERFLOW_MD_RP_CRD_OFLOW_SHFT 18 -#define SH_PI_ERROR_OVERFLOW_MD_RP_CRD_OFLOW_MASK 0x0000000000040000 - -/* SH_PI_ERROR_OVERFLOW_XN_RQ_CRD_OFLOW */ -/* Description: XN Request Credit Overflow Error */ -#define SH_PI_ERROR_OVERFLOW_XN_RQ_CRD_OFLOW_SHFT 19 -#define SH_PI_ERROR_OVERFLOW_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000 - -/* SH_PI_ERROR_OVERFLOW_XN_RP_CRD_OFLOW */ -/* Description: XN Reply Credit Overflow Error */ -#define SH_PI_ERROR_OVERFLOW_XN_RP_CRD_OFLOW_SHFT 20 -#define SH_PI_ERROR_OVERFLOW_XN_RP_CRD_OFLOW_MASK 0x0000000000100000 - -/* SH_PI_ERROR_OVERFLOW_HUNG_BUS */ -/* Description: FSB is hung */ -#define SH_PI_ERROR_OVERFLOW_HUNG_BUS_SHFT 21 -#define SH_PI_ERROR_OVERFLOW_HUNG_BUS_MASK 0x0000000000200000 - -/* SH_PI_ERROR_OVERFLOW_RSP_PARITY */ -/* Description: Parity error detecte during response phase */ -#define SH_PI_ERROR_OVERFLOW_RSP_PARITY_SHFT 22 -#define SH_PI_ERROR_OVERFLOW_RSP_PARITY_MASK 0x0000000000400000 - -/* SH_PI_ERROR_OVERFLOW_IOQ_OVERRUN */ -/* Description: Over run error detected on IOQ */ -#define SH_PI_ERROR_OVERFLOW_IOQ_OVERRUN_SHFT 23 -#define SH_PI_ERROR_OVERFLOW_IOQ_OVERRUN_MASK 0x0000000000800000 - -/* SH_PI_ERROR_OVERFLOW_REQ_FORMAT */ -/* Description: FSB request format not supported */ -#define SH_PI_ERROR_OVERFLOW_REQ_FORMAT_SHFT 24 -#define SH_PI_ERROR_OVERFLOW_REQ_FORMAT_MASK 0x0000000001000000 - -/* SH_PI_ERROR_OVERFLOW_ADDR_ACCESS */ -/* Description: Access to Address is not supported */ -#define SH_PI_ERROR_OVERFLOW_ADDR_ACCESS_SHFT 25 -#define SH_PI_ERROR_OVERFLOW_ADDR_ACCESS_MASK 0x0000000002000000 - -/* SH_PI_ERROR_OVERFLOW_REQ_PARITY */ -/* Description: Parity error detected during request phase */ -#define SH_PI_ERROR_OVERFLOW_REQ_PARITY_SHFT 26 -#define SH_PI_ERROR_OVERFLOW_REQ_PARITY_MASK 0x0000000004000000 - -/* SH_PI_ERROR_OVERFLOW_ADDR_PARITY */ -/* Description: Parity error detected on address */ -#define SH_PI_ERROR_OVERFLOW_ADDR_PARITY_SHFT 27 -#define SH_PI_ERROR_OVERFLOW_ADDR_PARITY_MASK 0x0000000008000000 - -/* SH_PI_ERROR_OVERFLOW_SHUB_FSB_DQE */ -/* Description: SHUB_FSB_DQE */ -#define SH_PI_ERROR_OVERFLOW_SHUB_FSB_DQE_SHFT 28 -#define SH_PI_ERROR_OVERFLOW_SHUB_FSB_DQE_MASK 0x0000000010000000 - -/* SH_PI_ERROR_OVERFLOW_SHUB_FSB_UCE */ -/* Description: An un-correctable ECC error was detected */ -#define SH_PI_ERROR_OVERFLOW_SHUB_FSB_UCE_SHFT 29 -#define SH_PI_ERROR_OVERFLOW_SHUB_FSB_UCE_MASK 0x0000000020000000 - -/* SH_PI_ERROR_OVERFLOW_SHUB_FSB_CE */ -/* Description: An correctable ECC error was detected */ -#define SH_PI_ERROR_OVERFLOW_SHUB_FSB_CE_SHFT 30 -#define SH_PI_ERROR_OVERFLOW_SHUB_FSB_CE_MASK 0x0000000040000000 - -/* SH_PI_ERROR_OVERFLOW_LIVELOCK */ -/* Description: AFI livelock error was detected */ -#define SH_PI_ERROR_OVERFLOW_LIVELOCK_SHFT 31 -#define SH_PI_ERROR_OVERFLOW_LIVELOCK_MASK 0x0000000080000000 - -/* SH_PI_ERROR_OVERFLOW_BAD_SNOOP */ -/* Description: AFI bad snoop error was detected */ -#define SH_PI_ERROR_OVERFLOW_BAD_SNOOP_SHFT 32 -#define SH_PI_ERROR_OVERFLOW_BAD_SNOOP_MASK 0x0000000100000000 - -/* SH_PI_ERROR_OVERFLOW_FSB_TBL_MISS */ -/* Description: AFI FSB request table miss error was detected */ -#define SH_PI_ERROR_OVERFLOW_FSB_TBL_MISS_SHFT 33 -#define SH_PI_ERROR_OVERFLOW_FSB_TBL_MISS_MASK 0x0000000200000000 - -/* SH_PI_ERROR_OVERFLOW_MSG_LENGTH */ -/* Description: Message length error on received message from SIC */ -#define SH_PI_ERROR_OVERFLOW_MSG_LENGTH_SHFT 34 -#define SH_PI_ERROR_OVERFLOW_MSG_LENGTH_MASK 0x0000000400000000 - -/* ==================================================================== */ -/* Register "SH_PI_ERROR_OVERFLOW_ALIAS" */ -/* PI Error Overflow Alias */ -/* ==================================================================== */ - -#define SH_PI_ERROR_OVERFLOW_ALIAS 0x0000000120060608 - -/* ==================================================================== */ -/* Register "SH_PI_ERROR_SUMMARY" */ -/* PI Error Summary */ -/* ==================================================================== */ - -#define SH_PI_ERROR_SUMMARY 0x0000000120060680 -#define SH_PI_ERROR_SUMMARY_MASK 0x00000007ffffffff -#define SH_PI_ERROR_SUMMARY_INIT 0x0000000000000000 - -/* SH_PI_ERROR_SUMMARY_FSB_PROTO_ERR */ -/* Description: CRB's FSB pipe detected protocol table miss */ -#define SH_PI_ERROR_SUMMARY_FSB_PROTO_ERR_SHFT 0 -#define SH_PI_ERROR_SUMMARY_FSB_PROTO_ERR_MASK 0x0000000000000001 - -/* SH_PI_ERROR_SUMMARY_GFX_RP_ERR */ -/* Description: Graphic reply error message received */ -#define SH_PI_ERROR_SUMMARY_GFX_RP_ERR_SHFT 1 -#define SH_PI_ERROR_SUMMARY_GFX_RP_ERR_MASK 0x0000000000000002 - -/* SH_PI_ERROR_SUMMARY_XB_PROTO_ERR */ -/* Description: CRB's XB pipe detected protocol table miss */ -#define SH_PI_ERROR_SUMMARY_XB_PROTO_ERR_SHFT 2 -#define SH_PI_ERROR_SUMMARY_XB_PROTO_ERR_MASK 0x0000000000000004 - -/* SH_PI_ERROR_SUMMARY_MEM_RP_ERR */ -/* Description: Memory reply error message received */ -#define SH_PI_ERROR_SUMMARY_MEM_RP_ERR_SHFT 3 -#define SH_PI_ERROR_SUMMARY_MEM_RP_ERR_MASK 0x0000000000000008 - -/* SH_PI_ERROR_SUMMARY_PIO_RP_ERR */ -/* Description: PIO error reply message received */ -#define SH_PI_ERROR_SUMMARY_PIO_RP_ERR_SHFT 4 -#define SH_PI_ERROR_SUMMARY_PIO_RP_ERR_MASK 0x0000000000000010 - -/* SH_PI_ERROR_SUMMARY_MEM_TO_ERR */ -/* Description: CRB's XB pipe detected a CRB time-out */ -#define SH_PI_ERROR_SUMMARY_MEM_TO_ERR_SHFT 5 -#define SH_PI_ERROR_SUMMARY_MEM_TO_ERR_MASK 0x0000000000000020 - -/* SH_PI_ERROR_SUMMARY_PIO_TO_ERR */ -/* Description: CRB's XB pipe detected a PIO time-out */ -#define SH_PI_ERROR_SUMMARY_PIO_TO_ERR_SHFT 6 -#define SH_PI_ERROR_SUMMARY_PIO_TO_ERR_MASK 0x0000000000000040 - -/* SH_PI_ERROR_SUMMARY_FSB_SHUB_UCE */ -/* Description: An un-correctable ECC error was detected */ -#define SH_PI_ERROR_SUMMARY_FSB_SHUB_UCE_SHFT 7 -#define SH_PI_ERROR_SUMMARY_FSB_SHUB_UCE_MASK 0x0000000000000080 - -/* SH_PI_ERROR_SUMMARY_FSB_SHUB_CE */ -/* Description: An correctable ECC error was detected */ -#define SH_PI_ERROR_SUMMARY_FSB_SHUB_CE_SHFT 8 -#define SH_PI_ERROR_SUMMARY_FSB_SHUB_CE_MASK 0x0000000000000100 - -/* SH_PI_ERROR_SUMMARY_MSG_COLOR_ERR */ -/* Description: Message color was wrong */ -#define SH_PI_ERROR_SUMMARY_MSG_COLOR_ERR_SHFT 9 -#define SH_PI_ERROR_SUMMARY_MSG_COLOR_ERR_MASK 0x0000000000000200 - -/* SH_PI_ERROR_SUMMARY_MD_RQ_Q_OFLOW */ -/* Description: MD Request input buffer over flow error */ -#define SH_PI_ERROR_SUMMARY_MD_RQ_Q_OFLOW_SHFT 10 -#define SH_PI_ERROR_SUMMARY_MD_RQ_Q_OFLOW_MASK 0x0000000000000400 - -/* SH_PI_ERROR_SUMMARY_MD_RP_Q_OFLOW */ -/* Description: MD Reply input buffer over flow error */ -#define SH_PI_ERROR_SUMMARY_MD_RP_Q_OFLOW_SHFT 11 -#define SH_PI_ERROR_SUMMARY_MD_RP_Q_OFLOW_MASK 0x0000000000000800 - -/* SH_PI_ERROR_SUMMARY_XN_RQ_Q_OFLOW */ -/* Description: XN Request input buffer over flow error */ -#define SH_PI_ERROR_SUMMARY_XN_RQ_Q_OFLOW_SHFT 12 -#define SH_PI_ERROR_SUMMARY_XN_RQ_Q_OFLOW_MASK 0x0000000000001000 - -/* SH_PI_ERROR_SUMMARY_XN_RP_Q_OFLOW */ -/* Description: XN Reply input buffer over flow error */ -#define SH_PI_ERROR_SUMMARY_XN_RP_Q_OFLOW_SHFT 13 -#define SH_PI_ERROR_SUMMARY_XN_RP_Q_OFLOW_MASK 0x0000000000002000 - -/* SH_PI_ERROR_SUMMARY_NACK_OFLOW */ -/* Description: NACK over flow error */ -#define SH_PI_ERROR_SUMMARY_NACK_OFLOW_SHFT 14 -#define SH_PI_ERROR_SUMMARY_NACK_OFLOW_MASK 0x0000000000004000 - -/* SH_PI_ERROR_SUMMARY_GFX_INT_0 */ -/* Description: GFX transfer interrupt for CPU 0 */ -#define SH_PI_ERROR_SUMMARY_GFX_INT_0_SHFT 15 -#define SH_PI_ERROR_SUMMARY_GFX_INT_0_MASK 0x0000000000008000 - -/* SH_PI_ERROR_SUMMARY_GFX_INT_1 */ -/* Description: GFX transfer interrupt for CPU 1 */ -#define SH_PI_ERROR_SUMMARY_GFX_INT_1_SHFT 16 -#define SH_PI_ERROR_SUMMARY_GFX_INT_1_MASK 0x0000000000010000 - -/* SH_PI_ERROR_SUMMARY_MD_RQ_CRD_OFLOW */ -/* Description: MD Request Credit Overflow Error */ -#define SH_PI_ERROR_SUMMARY_MD_RQ_CRD_OFLOW_SHFT 17 -#define SH_PI_ERROR_SUMMARY_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000 - -/* SH_PI_ERROR_SUMMARY_MD_RP_CRD_OFLOW */ -/* Description: MD Reply Credit Overflow Error */ -#define SH_PI_ERROR_SUMMARY_MD_RP_CRD_OFLOW_SHFT 18 -#define SH_PI_ERROR_SUMMARY_MD_RP_CRD_OFLOW_MASK 0x0000000000040000 - -/* SH_PI_ERROR_SUMMARY_XN_RQ_CRD_OFLOW */ -/* Description: XN Request Credit Overflow Error */ -#define SH_PI_ERROR_SUMMARY_XN_RQ_CRD_OFLOW_SHFT 19 -#define SH_PI_ERROR_SUMMARY_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000 - -/* SH_PI_ERROR_SUMMARY_XN_RP_CRD_OFLOW */ -/* Description: XN Reply Credit Overflow Error */ -#define SH_PI_ERROR_SUMMARY_XN_RP_CRD_OFLOW_SHFT 20 -#define SH_PI_ERROR_SUMMARY_XN_RP_CRD_OFLOW_MASK 0x0000000000100000 - -/* SH_PI_ERROR_SUMMARY_HUNG_BUS */ -/* Description: FSB is hung */ -#define SH_PI_ERROR_SUMMARY_HUNG_BUS_SHFT 21 -#define SH_PI_ERROR_SUMMARY_HUNG_BUS_MASK 0x0000000000200000 - -/* SH_PI_ERROR_SUMMARY_RSP_PARITY */ -/* Description: Parity error detecte during response phase */ -#define SH_PI_ERROR_SUMMARY_RSP_PARITY_SHFT 22 -#define SH_PI_ERROR_SUMMARY_RSP_PARITY_MASK 0x0000000000400000 - -/* SH_PI_ERROR_SUMMARY_IOQ_OVERRUN */ -/* Description: Over run error detected on IOQ */ -#define SH_PI_ERROR_SUMMARY_IOQ_OVERRUN_SHFT 23 -#define SH_PI_ERROR_SUMMARY_IOQ_OVERRUN_MASK 0x0000000000800000 - -/* SH_PI_ERROR_SUMMARY_REQ_FORMAT */ -/* Description: FSB request format not supported */ -#define SH_PI_ERROR_SUMMARY_REQ_FORMAT_SHFT 24 -#define SH_PI_ERROR_SUMMARY_REQ_FORMAT_MASK 0x0000000001000000 - -/* SH_PI_ERROR_SUMMARY_ADDR_ACCESS */ -/* Description: Access to Address is not supported */ -#define SH_PI_ERROR_SUMMARY_ADDR_ACCESS_SHFT 25 -#define SH_PI_ERROR_SUMMARY_ADDR_ACCESS_MASK 0x0000000002000000 - -/* SH_PI_ERROR_SUMMARY_REQ_PARITY */ -/* Description: Parity error detected during request phase */ -#define SH_PI_ERROR_SUMMARY_REQ_PARITY_SHFT 26 -#define SH_PI_ERROR_SUMMARY_REQ_PARITY_MASK 0x0000000004000000 - -/* SH_PI_ERROR_SUMMARY_ADDR_PARITY */ -/* Description: Parity error detected on address */ -#define SH_PI_ERROR_SUMMARY_ADDR_PARITY_SHFT 27 -#define SH_PI_ERROR_SUMMARY_ADDR_PARITY_MASK 0x0000000008000000 - -/* SH_PI_ERROR_SUMMARY_SHUB_FSB_DQE */ -/* Description: SHUB_FSB_DQE error */ -#define SH_PI_ERROR_SUMMARY_SHUB_FSB_DQE_SHFT 28 -#define SH_PI_ERROR_SUMMARY_SHUB_FSB_DQE_MASK 0x0000000010000000 - -/* SH_PI_ERROR_SUMMARY_SHUB_FSB_UCE */ -/* Description: An un-correctable ECC error was detected */ -#define SH_PI_ERROR_SUMMARY_SHUB_FSB_UCE_SHFT 29 -#define SH_PI_ERROR_SUMMARY_SHUB_FSB_UCE_MASK 0x0000000020000000 - -/* SH_PI_ERROR_SUMMARY_SHUB_FSB_CE */ -/* Description: An correctable ECC error was detected */ -#define SH_PI_ERROR_SUMMARY_SHUB_FSB_CE_SHFT 30 -#define SH_PI_ERROR_SUMMARY_SHUB_FSB_CE_MASK 0x0000000040000000 - -/* SH_PI_ERROR_SUMMARY_LIVELOCK */ -/* Description: AFI livelock error was detected */ -#define SH_PI_ERROR_SUMMARY_LIVELOCK_SHFT 31 -#define SH_PI_ERROR_SUMMARY_LIVELOCK_MASK 0x0000000080000000 - -/* SH_PI_ERROR_SUMMARY_BAD_SNOOP */ -/* Description: AFI bad snoop error was detected */ -#define SH_PI_ERROR_SUMMARY_BAD_SNOOP_SHFT 32 -#define SH_PI_ERROR_SUMMARY_BAD_SNOOP_MASK 0x0000000100000000 - -/* SH_PI_ERROR_SUMMARY_FSB_TBL_MISS */ -/* Description: AFI FSB request table miss error was detected */ -#define SH_PI_ERROR_SUMMARY_FSB_TBL_MISS_SHFT 33 -#define SH_PI_ERROR_SUMMARY_FSB_TBL_MISS_MASK 0x0000000200000000 - -/* SH_PI_ERROR_SUMMARY_MSG_LENGTH */ -/* Description: Message length error on received message from SIC */ -#define SH_PI_ERROR_SUMMARY_MSG_LENGTH_SHFT 34 -#define SH_PI_ERROR_SUMMARY_MSG_LENGTH_MASK 0x0000000400000000 - -/* ==================================================================== */ -/* Register "SH_PI_ERROR_SUMMARY_ALIAS" */ -/* PI Error Summary Alias */ -/* ==================================================================== */ - -#define SH_PI_ERROR_SUMMARY_ALIAS 0x0000000120060688 - -/* ==================================================================== */ -/* Register "SH_PI_EXPRESS_REPLY_STATUS" */ -/* PI Express Reply Status */ -/* ==================================================================== */ - -#define SH_PI_EXPRESS_REPLY_STATUS 0x0000000120060700 -#define SH_PI_EXPRESS_REPLY_STATUS_MASK 0x0000000000000007 -#define SH_PI_EXPRESS_REPLY_STATUS_INIT 0x0000000000000000 - -/* SH_PI_EXPRESS_REPLY_STATUS_STATE */ -/* Description: Express Reply State */ -#define SH_PI_EXPRESS_REPLY_STATUS_STATE_SHFT 0 -#define SH_PI_EXPRESS_REPLY_STATUS_STATE_MASK 0x0000000000000007 - -/* ==================================================================== */ -/* Register "SH_PI_FIRST_ERROR" */ -/* PI First Error */ -/* ==================================================================== */ - -#define SH_PI_FIRST_ERROR 0x0000000120060780 -#define SH_PI_FIRST_ERROR_MASK 0x00000007ffffffff -#define SH_PI_FIRST_ERROR_INIT 0x0000000000000000 - -/* SH_PI_FIRST_ERROR_FSB_PROTO_ERR */ -/* Description: CRB's FSB pipe detected protocol table miss */ -#define SH_PI_FIRST_ERROR_FSB_PROTO_ERR_SHFT 0 -#define SH_PI_FIRST_ERROR_FSB_PROTO_ERR_MASK 0x0000000000000001 - -/* SH_PI_FIRST_ERROR_GFX_RP_ERR */ -/* Description: Graphics error reply message received */ -#define SH_PI_FIRST_ERROR_GFX_RP_ERR_SHFT 1 -#define SH_PI_FIRST_ERROR_GFX_RP_ERR_MASK 0x0000000000000002 - -/* SH_PI_FIRST_ERROR_XB_PROTO_ERR */ -/* Description: CRB's XB pipe detected protocol table miss */ -#define SH_PI_FIRST_ERROR_XB_PROTO_ERR_SHFT 2 -#define SH_PI_FIRST_ERROR_XB_PROTO_ERR_MASK 0x0000000000000004 - -/* SH_PI_FIRST_ERROR_MEM_RP_ERR */ -/* Description: Memory reply error message received */ -#define SH_PI_FIRST_ERROR_MEM_RP_ERR_SHFT 3 -#define SH_PI_FIRST_ERROR_MEM_RP_ERR_MASK 0x0000000000000008 - -/* SH_PI_FIRST_ERROR_PIO_RP_ERR */ -/* Description: PIO reply error message received */ -#define SH_PI_FIRST_ERROR_PIO_RP_ERR_SHFT 4 -#define SH_PI_FIRST_ERROR_PIO_RP_ERR_MASK 0x0000000000000010 - -/* SH_PI_FIRST_ERROR_MEM_TO_ERR */ -/* Description: CRB's XB pipe detected a CRB time-out */ -#define SH_PI_FIRST_ERROR_MEM_TO_ERR_SHFT 5 -#define SH_PI_FIRST_ERROR_MEM_TO_ERR_MASK 0x0000000000000020 - -/* SH_PI_FIRST_ERROR_PIO_TO_ERR */ -/* Description: CRB's XB pipe detected a PIO time-out */ -#define SH_PI_FIRST_ERROR_PIO_TO_ERR_SHFT 6 -#define SH_PI_FIRST_ERROR_PIO_TO_ERR_MASK 0x0000000000000040 - -/* SH_PI_FIRST_ERROR_FSB_SHUB_UCE */ -/* Description: An un-correctable ECC error was detected */ -#define SH_PI_FIRST_ERROR_FSB_SHUB_UCE_SHFT 7 -#define SH_PI_FIRST_ERROR_FSB_SHUB_UCE_MASK 0x0000000000000080 - -/* SH_PI_FIRST_ERROR_FSB_SHUB_CE */ -/* Description: A correctable ECC error was detected */ -#define SH_PI_FIRST_ERROR_FSB_SHUB_CE_SHFT 8 -#define SH_PI_FIRST_ERROR_FSB_SHUB_CE_MASK 0x0000000000000100 - -/* SH_PI_FIRST_ERROR_MSG_COLOR_ERR */ -/* Description: Message color was wrong */ -#define SH_PI_FIRST_ERROR_MSG_COLOR_ERR_SHFT 9 -#define SH_PI_FIRST_ERROR_MSG_COLOR_ERR_MASK 0x0000000000000200 - -/* SH_PI_FIRST_ERROR_MD_RQ_Q_OFLOW */ -/* Description: MD Request input buffer over flow error */ -#define SH_PI_FIRST_ERROR_MD_RQ_Q_OFLOW_SHFT 10 -#define SH_PI_FIRST_ERROR_MD_RQ_Q_OFLOW_MASK 0x0000000000000400 - -/* SH_PI_FIRST_ERROR_MD_RP_Q_OFLOW */ -/* Description: MD Reply input buffer over flow error */ -#define SH_PI_FIRST_ERROR_MD_RP_Q_OFLOW_SHFT 11 -#define SH_PI_FIRST_ERROR_MD_RP_Q_OFLOW_MASK 0x0000000000000800 - -/* SH_PI_FIRST_ERROR_XN_RQ_Q_OFLOW */ -/* Description: XN Request input buffer over flow error */ -#define SH_PI_FIRST_ERROR_XN_RQ_Q_OFLOW_SHFT 12 -#define SH_PI_FIRST_ERROR_XN_RQ_Q_OFLOW_MASK 0x0000000000001000 - -/* SH_PI_FIRST_ERROR_XN_RP_Q_OFLOW */ -/* Description: XN Reply input buffer over flow error */ -#define SH_PI_FIRST_ERROR_XN_RP_Q_OFLOW_SHFT 13 -#define SH_PI_FIRST_ERROR_XN_RP_Q_OFLOW_MASK 0x0000000000002000 - -/* SH_PI_FIRST_ERROR_NACK_OFLOW */ -/* Description: NACK over flow error */ -#define SH_PI_FIRST_ERROR_NACK_OFLOW_SHFT 14 -#define SH_PI_FIRST_ERROR_NACK_OFLOW_MASK 0x0000000000004000 - -/* SH_PI_FIRST_ERROR_GFX_INT_0 */ -/* Description: GFX transfer interrupt for CPU 0 */ -#define SH_PI_FIRST_ERROR_GFX_INT_0_SHFT 15 -#define SH_PI_FIRST_ERROR_GFX_INT_0_MASK 0x0000000000008000 - -/* SH_PI_FIRST_ERROR_GFX_INT_1 */ -/* Description: GFX transfer interrupt for CPU 1 */ -#define SH_PI_FIRST_ERROR_GFX_INT_1_SHFT 16 -#define SH_PI_FIRST_ERROR_GFX_INT_1_MASK 0x0000000000010000 - -/* SH_PI_FIRST_ERROR_MD_RQ_CRD_OFLOW */ -/* Description: MD Request Credit Overflow Error */ -#define SH_PI_FIRST_ERROR_MD_RQ_CRD_OFLOW_SHFT 17 -#define SH_PI_FIRST_ERROR_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000 - -/* SH_PI_FIRST_ERROR_MD_RP_CRD_OFLOW */ -/* Description: MD Reply Credit Overflow Error */ -#define SH_PI_FIRST_ERROR_MD_RP_CRD_OFLOW_SHFT 18 -#define SH_PI_FIRST_ERROR_MD_RP_CRD_OFLOW_MASK 0x0000000000040000 - -/* SH_PI_FIRST_ERROR_XN_RQ_CRD_OFLOW */ -/* Description: XN Request Credit Overflow Error */ -#define SH_PI_FIRST_ERROR_XN_RQ_CRD_OFLOW_SHFT 19 -#define SH_PI_FIRST_ERROR_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000 - -/* SH_PI_FIRST_ERROR_XN_RP_CRD_OFLOW */ -/* Description: XN Reply Credit Overflow Error */ -#define SH_PI_FIRST_ERROR_XN_RP_CRD_OFLOW_SHFT 20 -#define SH_PI_FIRST_ERROR_XN_RP_CRD_OFLOW_MASK 0x0000000000100000 - -/* SH_PI_FIRST_ERROR_HUNG_BUS */ -/* Description: FSB is hung */ -#define SH_PI_FIRST_ERROR_HUNG_BUS_SHFT 21 -#define SH_PI_FIRST_ERROR_HUNG_BUS_MASK 0x0000000000200000 - -/* SH_PI_FIRST_ERROR_RSP_PARITY */ -/* Description: Parity error detecte during response phase */ -#define SH_PI_FIRST_ERROR_RSP_PARITY_SHFT 22 -#define SH_PI_FIRST_ERROR_RSP_PARITY_MASK 0x0000000000400000 - -/* SH_PI_FIRST_ERROR_IOQ_OVERRUN */ -/* Description: Over run error detected on IOQ */ -#define SH_PI_FIRST_ERROR_IOQ_OVERRUN_SHFT 23 -#define SH_PI_FIRST_ERROR_IOQ_OVERRUN_MASK 0x0000000000800000 - -/* SH_PI_FIRST_ERROR_REQ_FORMAT */ -/* Description: FSB request format not supported */ -#define SH_PI_FIRST_ERROR_REQ_FORMAT_SHFT 24 -#define SH_PI_FIRST_ERROR_REQ_FORMAT_MASK 0x0000000001000000 - -/* SH_PI_FIRST_ERROR_ADDR_ACCESS */ -/* Description: Access to Address is not supported */ -#define SH_PI_FIRST_ERROR_ADDR_ACCESS_SHFT 25 -#define SH_PI_FIRST_ERROR_ADDR_ACCESS_MASK 0x0000000002000000 - -/* SH_PI_FIRST_ERROR_REQ_PARITY */ -/* Description: Parity error detected during request phase */ -#define SH_PI_FIRST_ERROR_REQ_PARITY_SHFT 26 -#define SH_PI_FIRST_ERROR_REQ_PARITY_MASK 0x0000000004000000 - -/* SH_PI_FIRST_ERROR_ADDR_PARITY */ -/* Description: Parity error detected on address */ -#define SH_PI_FIRST_ERROR_ADDR_PARITY_SHFT 27 -#define SH_PI_FIRST_ERROR_ADDR_PARITY_MASK 0x0000000008000000 - -/* SH_PI_FIRST_ERROR_SHUB_FSB_DQE */ -/* Description: SHUB_FSB_DQE */ -#define SH_PI_FIRST_ERROR_SHUB_FSB_DQE_SHFT 28 -#define SH_PI_FIRST_ERROR_SHUB_FSB_DQE_MASK 0x0000000010000000 - -/* SH_PI_FIRST_ERROR_SHUB_FSB_UCE */ -/* Description: An un-correctable ECC error was detected */ -#define SH_PI_FIRST_ERROR_SHUB_FSB_UCE_SHFT 29 -#define SH_PI_FIRST_ERROR_SHUB_FSB_UCE_MASK 0x0000000020000000 - -/* SH_PI_FIRST_ERROR_SHUB_FSB_CE */ -/* Description: An correctable ECC error was detected */ -#define SH_PI_FIRST_ERROR_SHUB_FSB_CE_SHFT 30 -#define SH_PI_FIRST_ERROR_SHUB_FSB_CE_MASK 0x0000000040000000 - -/* SH_PI_FIRST_ERROR_LIVELOCK */ -/* Description: AFI livelock error was detected */ -#define SH_PI_FIRST_ERROR_LIVELOCK_SHFT 31 -#define SH_PI_FIRST_ERROR_LIVELOCK_MASK 0x0000000080000000 - -/* SH_PI_FIRST_ERROR_BAD_SNOOP */ -/* Description: AFI bad snoop error was detected */ -#define SH_PI_FIRST_ERROR_BAD_SNOOP_SHFT 32 -#define SH_PI_FIRST_ERROR_BAD_SNOOP_MASK 0x0000000100000000 - -/* SH_PI_FIRST_ERROR_FSB_TBL_MISS */ -/* Description: AFI FSB request table miss error was detected */ -#define SH_PI_FIRST_ERROR_FSB_TBL_MISS_SHFT 33 -#define SH_PI_FIRST_ERROR_FSB_TBL_MISS_MASK 0x0000000200000000 - -/* SH_PI_FIRST_ERROR_MSG_LENGTH */ -/* Description: Message length error on received message from SIC */ -#define SH_PI_FIRST_ERROR_MSG_LENGTH_SHFT 34 -#define SH_PI_FIRST_ERROR_MSG_LENGTH_MASK 0x0000000400000000 - -/* ==================================================================== */ -/* Register "SH_PI_FIRST_ERROR_ALIAS" */ -/* PI First Error Alias */ -/* ==================================================================== */ - -#define SH_PI_FIRST_ERROR_ALIAS 0x0000000120060788 - -/* ==================================================================== */ -/* Register "SH_PI_PI2MD_REPLY_VC_STATUS" */ -/* PI-to-MD Reply Virtual Channel Status */ -/* ==================================================================== */ - -#define SH_PI_PI2MD_REPLY_VC_STATUS 0x0000000120060900 -#define SH_PI_PI2MD_REPLY_VC_STATUS_MASK 0x000000000000003f -#define SH_PI_PI2MD_REPLY_VC_STATUS_INIT 0x0000000000000000 - -/* SH_PI_PI2MD_REPLY_VC_STATUS_OUTPUT_CRD_STAT */ -/* Description: Status of output credits */ -#define SH_PI_PI2MD_REPLY_VC_STATUS_OUTPUT_CRD_STAT_SHFT 0 -#define SH_PI_PI2MD_REPLY_VC_STATUS_OUTPUT_CRD_STAT_MASK 0x000000000000003f - -/* ==================================================================== */ -/* Register "SH_PI_PI2MD_REQUEST_VC_STATUS" */ -/* PI-to-MD Request Virtual Channel Status */ -/* ==================================================================== */ - -#define SH_PI_PI2MD_REQUEST_VC_STATUS 0x0000000120060980 -#define SH_PI_PI2MD_REQUEST_VC_STATUS_MASK 0x000000000000003f -#define SH_PI_PI2MD_REQUEST_VC_STATUS_INIT 0x0000000000000000 - -/* SH_PI_PI2MD_REQUEST_VC_STATUS_OUTPUT_CRD_STAT */ -/* Description: Status of output credits */ -#define SH_PI_PI2MD_REQUEST_VC_STATUS_OUTPUT_CRD_STAT_SHFT 0 -#define SH_PI_PI2MD_REQUEST_VC_STATUS_OUTPUT_CRD_STAT_MASK 0x000000000000003f - -/* ==================================================================== */ -/* Register "SH_PI_PI2XN_REPLY_VC_STATUS" */ -/* PI-to-XN Reply Virtual Channel Status */ -/* ==================================================================== */ - -#define SH_PI_PI2XN_REPLY_VC_STATUS 0x0000000120060a00 -#define SH_PI_PI2XN_REPLY_VC_STATUS_MASK 0x000000000000003f -#define SH_PI_PI2XN_REPLY_VC_STATUS_INIT 0x0000000000000000 - -/* SH_PI_PI2XN_REPLY_VC_STATUS_OUTPUT_CRD_STAT */ -/* Description: Status of output credits */ -#define SH_PI_PI2XN_REPLY_VC_STATUS_OUTPUT_CRD_STAT_SHFT 0 -#define SH_PI_PI2XN_REPLY_VC_STATUS_OUTPUT_CRD_STAT_MASK 0x000000000000003f - -/* ==================================================================== */ -/* Register "SH_PI_PI2XN_REQUEST_VC_STATUS" */ -/* PI-to-XN Request Virtual Channel Status */ -/* ==================================================================== */ - -#define SH_PI_PI2XN_REQUEST_VC_STATUS 0x0000000120060a80 -#define SH_PI_PI2XN_REQUEST_VC_STATUS_MASK 0x000000000000003f -#define SH_PI_PI2XN_REQUEST_VC_STATUS_INIT 0x0000000000000000 - -/* SH_PI_PI2XN_REQUEST_VC_STATUS_OUTPUT_CRD_STAT */ -/* Description: Status of output credits */ -#define SH_PI_PI2XN_REQUEST_VC_STATUS_OUTPUT_CRD_STAT_SHFT 0 -#define SH_PI_PI2XN_REQUEST_VC_STATUS_OUTPUT_CRD_STAT_MASK 0x000000000000003f - -/* ==================================================================== */ -/* Register "SH_PI_UNCORRECTED_DETAIL_1" */ -/* PI Uncorrected Error Detail 1 */ -/* ==================================================================== */ - -#define SH_PI_UNCORRECTED_DETAIL_1 0x0000000120060b00 -#define SH_PI_UNCORRECTED_DETAIL_1_MASK 0xffffffffffffffff -#define SH_PI_UNCORRECTED_DETAIL_1_INIT 0x0000000000000000 - -/* SH_PI_UNCORRECTED_DETAIL_1_ADDRESS */ -/* Description: Address of Message that logged Uncorrectable Error */ -#define SH_PI_UNCORRECTED_DETAIL_1_ADDRESS_SHFT 0 -#define SH_PI_UNCORRECTED_DETAIL_1_ADDRESS_MASK 0x0000ffffffffffff - -/* SH_PI_UNCORRECTED_DETAIL_1_SYNDROME */ -/* Description: Syndrome for double word data with Uncorrectable Er */ -#define SH_PI_UNCORRECTED_DETAIL_1_SYNDROME_SHFT 48 -#define SH_PI_UNCORRECTED_DETAIL_1_SYNDROME_MASK 0x00ff000000000000 - -/* SH_PI_UNCORRECTED_DETAIL_1_DEP */ -/* Description: DEP for Double word in error */ -#define SH_PI_UNCORRECTED_DETAIL_1_DEP_SHFT 56 -#define SH_PI_UNCORRECTED_DETAIL_1_DEP_MASK 0xff00000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_UNCORRECTED_DETAIL_2" */ -/* PI Uncorrected Error Detail 2 */ -/* ==================================================================== */ - -#define SH_PI_UNCORRECTED_DETAIL_2 0x0000000120060b80 -#define SH_PI_UNCORRECTED_DETAIL_2_MASK 0xffffffffffffffff -#define SH_PI_UNCORRECTED_DETAIL_2_INIT 0x0000000000000000 - -/* SH_PI_UNCORRECTED_DETAIL_2_DATA */ -/* Description: Double word data in error */ -#define SH_PI_UNCORRECTED_DETAIL_2_DATA_SHFT 0 -#define SH_PI_UNCORRECTED_DETAIL_2_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_PI_UNCORRECTED_DETAIL_3" */ -/* PI Uncorrected Error Detail 3 */ -/* ==================================================================== */ - -#define SH_PI_UNCORRECTED_DETAIL_3 0x0000000120060c00 -#define SH_PI_UNCORRECTED_DETAIL_3_MASK 0xffffffffffffffff -#define SH_PI_UNCORRECTED_DETAIL_3_INIT 0x0000000000000000 - -/* SH_PI_UNCORRECTED_DETAIL_3_ADDRESS */ -/* Description: Address of Message that logged Uncorrectable Error */ -#define SH_PI_UNCORRECTED_DETAIL_3_ADDRESS_SHFT 0 -#define SH_PI_UNCORRECTED_DETAIL_3_ADDRESS_MASK 0x0000ffffffffffff - -/* SH_PI_UNCORRECTED_DETAIL_3_SYNDROME */ -/* Description: Syndrome for double word data with Uncorrectable Er */ -#define SH_PI_UNCORRECTED_DETAIL_3_SYNDROME_SHFT 48 -#define SH_PI_UNCORRECTED_DETAIL_3_SYNDROME_MASK 0x00ff000000000000 - -/* SH_PI_UNCORRECTED_DETAIL_3_DEP */ -/* Description: DCP for Double word in error */ -#define SH_PI_UNCORRECTED_DETAIL_3_DEP_SHFT 56 -#define SH_PI_UNCORRECTED_DETAIL_3_DEP_MASK 0xff00000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_UNCORRECTED_DETAIL_4" */ -/* PI Uncorrected Error Detail 4 */ -/* ==================================================================== */ - -#define SH_PI_UNCORRECTED_DETAIL_4 0x0000000120060c80 -#define SH_PI_UNCORRECTED_DETAIL_4_MASK 0xffffffffffffffff -#define SH_PI_UNCORRECTED_DETAIL_4_INIT 0x0000000000000000 - -/* SH_PI_UNCORRECTED_DETAIL_4_DATA */ -/* Description: Double word data in error */ -#define SH_PI_UNCORRECTED_DETAIL_4_DATA_SHFT 0 -#define SH_PI_UNCORRECTED_DETAIL_4_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_PI_MD2PI_REPLY_VC_STATUS" */ -/* MD-to-PI Reply Virtual Channel Status */ -/* ==================================================================== */ - -#define SH_PI_MD2PI_REPLY_VC_STATUS 0x0000000120060800 -#define SH_PI_MD2PI_REPLY_VC_STATUS_MASK 0x0000000000000fff -#define SH_PI_MD2PI_REPLY_VC_STATUS_INIT 0x0000000000000000 - -/* SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT */ -/* Description: Status of input header credits */ -#define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT_SHFT 0 -#define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT_MASK 0x000000000000000f - -/* SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT */ -/* Description: Status of data credits */ -#define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT_SHFT 4 -#define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT_MASK 0x00000000000000f0 - -/* SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT */ -/* Description: Status of MD Reply Input Queue */ -#define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT_SHFT 8 -#define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT_MASK 0x0000000000000f00 - -/* ==================================================================== */ -/* Register "SH_PI_MD2PI_REQUEST_VC_STATUS" */ -/* MD-to-PI Request Virtual Channel Status */ -/* ==================================================================== */ - -#define SH_PI_MD2PI_REQUEST_VC_STATUS 0x0000000120060880 -#define SH_PI_MD2PI_REQUEST_VC_STATUS_MASK 0x0000000000000fff -#define SH_PI_MD2PI_REQUEST_VC_STATUS_INIT 0x0000000000000000 - -/* SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT */ -/* Description: Status of input header credits */ -#define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT_SHFT 0 -#define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT_MASK 0x000000000000000f - -/* SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT */ -/* Description: Status of input data credits */ -#define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT_SHFT 4 -#define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT_MASK 0x00000000000000f0 - -/* SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT */ -/* Description: Status of MD Request Input Queue */ -#define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT_SHFT 8 -#define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT_MASK 0x0000000000000f00 - -/* ==================================================================== */ -/* Register "SH_PI_XN2PI_REPLY_VC_STATUS" */ -/* XN-to-PI Reply Virtual Channel Status */ -/* ==================================================================== */ - -#define SH_PI_XN2PI_REPLY_VC_STATUS 0x0000000120060d00 -#define SH_PI_XN2PI_REPLY_VC_STATUS_MASK 0x0000000000000fff -#define SH_PI_XN2PI_REPLY_VC_STATUS_INIT 0x0000000000000000 - -/* SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT */ -/* Description: Status of input header credits */ -#define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT_SHFT 0 -#define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT_MASK 0x000000000000000f - -/* SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT */ -/* Description: Status of input data credits */ -#define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT_SHFT 4 -#define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT_MASK 0x00000000000000f0 - -/* SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT */ -/* Description: Status of XN Reply Input Queue */ -#define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT_SHFT 8 -#define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT_MASK 0x0000000000000f00 - -/* ==================================================================== */ -/* Register "SH_PI_XN2PI_REQUEST_VC_STATUS" */ -/* XN-to-PI Request Virtual Channel Status */ -/* ==================================================================== */ - -#define SH_PI_XN2PI_REQUEST_VC_STATUS 0x0000000120060d80 -#define SH_PI_XN2PI_REQUEST_VC_STATUS_MASK 0x0000000000000fff -#define SH_PI_XN2PI_REQUEST_VC_STATUS_INIT 0x0000000000000000 - -/* SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT */ -/* Description: Status of input header credits */ -#define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT_SHFT 0 -#define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT_MASK 0x000000000000000f - -/* SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT */ -/* Description: Status of input data credits */ -#define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT_SHFT 4 -#define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT_MASK 0x00000000000000f0 - -/* SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT */ -/* Description: Status of XN Request Input Queue */ -#define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT_SHFT 8 -#define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT_MASK 0x0000000000000f00 - -/* ==================================================================== */ -/* Register "SH_XNPI_SIC_FLOW" */ -/* ==================================================================== */ - -#define SH_XNPI_SIC_FLOW 0x0000000150030000 -#define SH_XNPI_SIC_FLOW_MASK 0x9f1f1f1f1f1f9f9f -#define SH_XNPI_SIC_FLOW_INIT 0x0000080000080000 - -/* SH_XNPI_SIC_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNPI_SIC_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNPI_SIC_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000001f - -/* SH_XNPI_SIC_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNPI_SIC_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNPI_SIC_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNPI_SIC_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNPI_SIC_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNPI_SIC_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000001f00 - -/* SH_XNPI_SIC_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNPI_SIC_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNPI_SIC_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNPI_SIC_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 credit_test */ -#define SH_XNPI_SIC_FLOW_CREDIT_VC0_TEST_SHFT 16 -#define SH_XNPI_SIC_FLOW_CREDIT_VC0_TEST_MASK 0x00000000001f0000 - -/* SH_XNPI_SIC_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNPI_SIC_FLOW_CREDIT_VC0_DYN_SHFT 24 -#define SH_XNPI_SIC_FLOW_CREDIT_VC0_DYN_MASK 0x000000001f000000 - -/* SH_XNPI_SIC_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNPI_SIC_FLOW_CREDIT_VC0_CAP_SHFT 32 -#define SH_XNPI_SIC_FLOW_CREDIT_VC0_CAP_MASK 0x0000001f00000000 - -/* SH_XNPI_SIC_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 credit_test */ -#define SH_XNPI_SIC_FLOW_CREDIT_VC2_TEST_SHFT 40 -#define SH_XNPI_SIC_FLOW_CREDIT_VC2_TEST_MASK 0x00001f0000000000 - -/* SH_XNPI_SIC_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNPI_SIC_FLOW_CREDIT_VC2_DYN_SHFT 48 -#define SH_XNPI_SIC_FLOW_CREDIT_VC2_DYN_MASK 0x001f000000000000 - -/* SH_XNPI_SIC_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNPI_SIC_FLOW_CREDIT_VC2_CAP_SHFT 56 -#define SH_XNPI_SIC_FLOW_CREDIT_VC2_CAP_MASK 0x1f00000000000000 - -/* SH_XNPI_SIC_FLOW_DISABLE_BYPASS_OUT */ -#define SH_XNPI_SIC_FLOW_DISABLE_BYPASS_OUT_SHFT 63 -#define SH_XNPI_SIC_FLOW_DISABLE_BYPASS_OUT_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_XNPI_TO_NI0_PORT_FLOW" */ -/* ==================================================================== */ - -#define SH_XNPI_TO_NI0_PORT_FLOW 0x0000000150030010 -#define SH_XNPI_TO_NI0_PORT_FLOW_MASK 0x3f3f003f3f00bfbf -#define SH_XNPI_TO_NI0_PORT_FLOW_INIT 0x0000000000000000 - -/* SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24 -#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000 - -/* SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32 -#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000 - -/* SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48 -#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000 - -/* SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56 -#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNPI_TO_NI1_PORT_FLOW" */ -/* ==================================================================== */ - -#define SH_XNPI_TO_NI1_PORT_FLOW 0x0000000150030020 -#define SH_XNPI_TO_NI1_PORT_FLOW_MASK 0x3f3f003f3f00bfbf -#define SH_XNPI_TO_NI1_PORT_FLOW_INIT 0x0000000000000000 - -/* SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24 -#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000 - -/* SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32 -#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000 - -/* SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48 -#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000 - -/* SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56 -#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNPI_TO_IILB_PORT_FLOW" */ -/* ==================================================================== */ - -#define SH_XNPI_TO_IILB_PORT_FLOW 0x0000000150030030 -#define SH_XNPI_TO_IILB_PORT_FLOW_MASK 0x3f3f003f3f00bfbf -#define SH_XNPI_TO_IILB_PORT_FLOW_INIT 0x0000000000000000 - -/* SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24 -#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000 - -/* SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32 -#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000 - -/* SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48 -#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000 - -/* SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56 -#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNPI_FR_NI0_PORT_FLOW_FIFO" */ -/* ==================================================================== */ - -#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO 0x0000000150030040 -#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_MASK 0x00001f1f3f3f3f3f -#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_INIT 0x00000c0c00000000 - -/* SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN */ -/* Description: vc0 fifo entry dynamic value */ -#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0 -#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f - -/* SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP */ -/* Description: vc0 fifo entry captured value */ -#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8 -#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00 - -/* SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN */ -/* Description: vc2 fifo entry dynamic value */ -#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16 -#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000 - -/* SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP */ -/* Description: vc2 fifo entry captured value */ -#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24 -#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000 - -/* SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST */ -/* Description: vc0 test credits limit */ -#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32 -#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000 - -/* SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST */ -/* Description: vc2 test credits limit */ -#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40 -#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNPI_FR_NI1_PORT_FLOW_FIFO" */ -/* ==================================================================== */ - -#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO 0x0000000150030050 -#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_MASK 0x00001f1f3f3f3f3f -#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_INIT 0x00000c0c00000000 - -/* SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN */ -/* Description: vc0 fifo entry dynamic value */ -#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0 -#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f - -/* SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP */ -/* Description: vc0 fifo entry captured value */ -#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8 -#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00 - -/* SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN */ -/* Description: vc2 fifo entry dynamic value */ -#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16 -#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000 - -/* SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP */ -/* Description: vc2 fifo entry captured value */ -#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24 -#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000 - -/* SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST */ -/* Description: vc0 test credits limit */ -#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32 -#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000 - -/* SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST */ -/* Description: vc2 test credits limit */ -#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40 -#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNPI_FR_IILB_PORT_FLOW_FIFO" */ -/* ==================================================================== */ - -#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO 0x0000000150030060 -#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_MASK 0x00001f1f3f3f3f3f -#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_INIT 0x00000c0c00000000 - -/* SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN */ -/* Description: vc0 fifo entry dynamic value */ -#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0 -#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f - -/* SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP */ -/* Description: vc0 fifo entry captured value */ -#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8 -#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00 - -/* SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN */ -/* Description: vc2 fifo entry dynamic value */ -#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16 -#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000 - -/* SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP */ -/* Description: vc2 fifo entry captured value */ -#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24 -#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000 - -/* SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST */ -/* Description: vc0 test credits limit */ -#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32 -#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000 - -/* SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST */ -/* Description: vc2 test credits limit */ -#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40 -#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNMD_SIC_FLOW" */ -/* ==================================================================== */ - -#define SH_XNMD_SIC_FLOW 0x0000000150030100 -#define SH_XNMD_SIC_FLOW_MASK 0x9f1f1f1f1f1f9f9f -#define SH_XNMD_SIC_FLOW_INIT 0x0000090000090000 - -/* SH_XNMD_SIC_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNMD_SIC_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNMD_SIC_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000001f - -/* SH_XNMD_SIC_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNMD_SIC_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNMD_SIC_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNMD_SIC_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNMD_SIC_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNMD_SIC_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000001f00 - -/* SH_XNMD_SIC_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNMD_SIC_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNMD_SIC_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNMD_SIC_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 credit_test */ -#define SH_XNMD_SIC_FLOW_CREDIT_VC0_TEST_SHFT 16 -#define SH_XNMD_SIC_FLOW_CREDIT_VC0_TEST_MASK 0x00000000001f0000 - -/* SH_XNMD_SIC_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNMD_SIC_FLOW_CREDIT_VC0_DYN_SHFT 24 -#define SH_XNMD_SIC_FLOW_CREDIT_VC0_DYN_MASK 0x000000001f000000 - -/* SH_XNMD_SIC_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNMD_SIC_FLOW_CREDIT_VC0_CAP_SHFT 32 -#define SH_XNMD_SIC_FLOW_CREDIT_VC0_CAP_MASK 0x0000001f00000000 - -/* SH_XNMD_SIC_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 credit_test */ -#define SH_XNMD_SIC_FLOW_CREDIT_VC2_TEST_SHFT 40 -#define SH_XNMD_SIC_FLOW_CREDIT_VC2_TEST_MASK 0x00001f0000000000 - -/* SH_XNMD_SIC_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNMD_SIC_FLOW_CREDIT_VC2_DYN_SHFT 48 -#define SH_XNMD_SIC_FLOW_CREDIT_VC2_DYN_MASK 0x001f000000000000 - -/* SH_XNMD_SIC_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNMD_SIC_FLOW_CREDIT_VC2_CAP_SHFT 56 -#define SH_XNMD_SIC_FLOW_CREDIT_VC2_CAP_MASK 0x1f00000000000000 - -/* SH_XNMD_SIC_FLOW_DISABLE_BYPASS_OUT */ -#define SH_XNMD_SIC_FLOW_DISABLE_BYPASS_OUT_SHFT 63 -#define SH_XNMD_SIC_FLOW_DISABLE_BYPASS_OUT_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_XNMD_TO_NI0_PORT_FLOW" */ -/* ==================================================================== */ - -#define SH_XNMD_TO_NI0_PORT_FLOW 0x0000000150030110 -#define SH_XNMD_TO_NI0_PORT_FLOW_MASK 0x3f3f003f3f00bfbf -#define SH_XNMD_TO_NI0_PORT_FLOW_INIT 0x0000000000000000 - -/* SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24 -#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000 - -/* SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32 -#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000 - -/* SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48 -#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000 - -/* SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56 -#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNMD_TO_NI1_PORT_FLOW" */ -/* ==================================================================== */ - -#define SH_XNMD_TO_NI1_PORT_FLOW 0x0000000150030120 -#define SH_XNMD_TO_NI1_PORT_FLOW_MASK 0x3f3f003f3f00bfbf -#define SH_XNMD_TO_NI1_PORT_FLOW_INIT 0x0000000000000000 - -/* SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24 -#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000 - -/* SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32 -#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000 - -/* SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48 -#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000 - -/* SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56 -#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNMD_TO_IILB_PORT_FLOW" */ -/* ==================================================================== */ - -#define SH_XNMD_TO_IILB_PORT_FLOW 0x0000000150030130 -#define SH_XNMD_TO_IILB_PORT_FLOW_MASK 0x3f3f003f3f00bfbf -#define SH_XNMD_TO_IILB_PORT_FLOW_INIT 0x0000000000000000 - -/* SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24 -#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000 - -/* SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32 -#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000 - -/* SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48 -#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000 - -/* SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56 -#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNMD_FR_NI0_PORT_FLOW_FIFO" */ -/* ==================================================================== */ - -#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO 0x0000000150030140 -#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_MASK 0x00001f1f3f3f3f3f -#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_INIT 0x00000c0c00000000 - -/* SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN */ -/* Description: vc0 fifo entry dynamic value */ -#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0 -#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f - -/* SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP */ -/* Description: vc0 fifo entry captured value */ -#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8 -#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00 - -/* SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN */ -/* Description: vc2 fifo entry dynamic value */ -#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16 -#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000 - -/* SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP */ -/* Description: vc2 fifo entry captured value */ -#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24 -#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000 - -/* SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST */ -/* Description: vc0 test credits limit */ -#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32 -#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000 - -/* SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST */ -/* Description: vc2 test credits limit */ -#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40 -#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNMD_FR_NI1_PORT_FLOW_FIFO" */ -/* ==================================================================== */ - -#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO 0x0000000150030150 -#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_MASK 0x00001f1f3f3f3f3f -#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_INIT 0x00000c0c00000000 - -/* SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN */ -/* Description: vc0 fifo entry dynamic value */ -#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0 -#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f - -/* SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP */ -/* Description: vc0 fifo entry captured value */ -#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8 -#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00 - -/* SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN */ -/* Description: vc2 fifo entry dynamic value */ -#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16 -#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000 - -/* SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP */ -/* Description: vc2 fifo entry captured value */ -#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24 -#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000 - -/* SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST */ -/* Description: vc0 test credits limit */ -#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32 -#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000 - -/* SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST */ -/* Description: vc2 test credits limit */ -#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40 -#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNMD_FR_IILB_PORT_FLOW_FIFO" */ -/* ==================================================================== */ - -#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO 0x0000000150030160 -#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_MASK 0x00001f1f3f3f3f3f -#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_INIT 0x00000c0c00000000 - -/* SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN */ -/* Description: vc0 fifo entry dynamic value */ -#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0 -#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f - -/* SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP */ -/* Description: vc0 fifo entry captured value */ -#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8 -#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00 - -/* SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN */ -/* Description: vc2 fifo entry dynamic value */ -#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16 -#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000 - -/* SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP */ -/* Description: vc2 fifo entry captured value */ -#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24 -#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000 - -/* SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST */ -/* Description: vc0 test credits limit */ -#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32 -#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000 - -/* SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST */ -/* Description: vc2 test credits limit */ -#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40 -#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNII_INTRA_FLOW" */ -/* ==================================================================== */ - -#define SH_XNII_INTRA_FLOW 0x0000000150030200 -#define SH_XNII_INTRA_FLOW_MASK 0x7f7f7f7f7f7fbfbf -#define SH_XNII_INTRA_FLOW_INIT 0x00003f00003f0000 - -/* SH_XNII_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNII_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNII_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNII_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNII_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNII_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNII_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNII_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNII_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNII_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNII_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNII_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNII_INTRA_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 credit_test */ -#define SH_XNII_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 16 -#define SH_XNII_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x00000000007f0000 - -/* SH_XNII_INTRA_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNII_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 24 -#define SH_XNII_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x000000007f000000 - -/* SH_XNII_INTRA_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNII_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 32 -#define SH_XNII_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x0000007f00000000 - -/* SH_XNII_INTRA_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 credit_test */ -#define SH_XNII_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 40 -#define SH_XNII_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x00007f0000000000 - -/* SH_XNII_INTRA_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNII_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 48 -#define SH_XNII_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x007f000000000000 - -/* SH_XNII_INTRA_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNII_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 56 -#define SH_XNII_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x7f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNLB_INTRA_FLOW" */ -/* ==================================================================== */ - -#define SH_XNLB_INTRA_FLOW 0x0000000150030210 -#define SH_XNLB_INTRA_FLOW_MASK 0xff7f7f7f7f7fbfbf -#define SH_XNLB_INTRA_FLOW_INIT 0x0000080000100000 - -/* SH_XNLB_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNLB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNLB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNLB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNLB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNLB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNLB_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNLB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNLB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNLB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNLB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNLB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNLB_INTRA_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 credit_test */ -#define SH_XNLB_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 16 -#define SH_XNLB_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x00000000007f0000 - -/* SH_XNLB_INTRA_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNLB_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 24 -#define SH_XNLB_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x000000007f000000 - -/* SH_XNLB_INTRA_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNLB_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 32 -#define SH_XNLB_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x0000007f00000000 - -/* SH_XNLB_INTRA_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 credit_test */ -#define SH_XNLB_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 40 -#define SH_XNLB_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x00007f0000000000 - -/* SH_XNLB_INTRA_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNLB_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 48 -#define SH_XNLB_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x007f000000000000 - -/* SH_XNLB_INTRA_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNLB_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 56 -#define SH_XNLB_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x7f00000000000000 - -/* SH_XNLB_INTRA_FLOW_DISABLE_BYPASS_IN */ -#define SH_XNLB_INTRA_FLOW_DISABLE_BYPASS_IN_SHFT 63 -#define SH_XNLB_INTRA_FLOW_DISABLE_BYPASS_IN_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT 0x0000000150030220 -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 - -/* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_DYN */ -/* Description: vc0 debit dynamic value */ -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 - -/* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_CAP */ -/* Description: vc0 debit captured value */ -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 - -/* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_DYN */ -/* Description: vc2 debit dynamic value */ -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 - -/* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_CAP */ -/* Description: vc2 debit captured value */ -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 -#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT 0x0000000150030230 -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 - -/* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_DYN */ -/* Description: vc0 debit dynamic value */ -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 - -/* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_CAP */ -/* Description: vc0 debit captured value */ -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 - -/* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_DYN */ -/* Description: vc2 debit dynamic value */ -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 - -/* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_CAP */ -/* Description: vc2 debit captured value */ -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 -#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT 0x0000000150030240 -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 - -/* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN */ -/* Description: vc0 debit dynamic value */ -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 - -/* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP */ -/* Description: vc0 debit captured value */ -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 - -/* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN */ -/* Description: vc2 debit dynamic value */ -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 - -/* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP */ -/* Description: vc2 debit captured value */ -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 -#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT 0x0000000150030250 -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 - -/* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN */ -/* Description: vc0 debit dynamic value */ -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 - -/* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP */ -/* Description: vc0 debit captured value */ -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 - -/* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN */ -/* Description: vc2 debit dynamic value */ -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 - -/* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP */ -/* Description: vc2 debit captured value */ -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 -#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT 0x0000000150030260 -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 - -/* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN */ -/* Description: vc0 debit dynamic value */ -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 - -/* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP */ -/* Description: vc0 debit captured value */ -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 - -/* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN */ -/* Description: vc2 debit dynamic value */ -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 - -/* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP */ -/* Description: vc2 debit captured value */ -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 -#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT 0x0000000150030270 -#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f -#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c - -/* SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 credit_test */ -#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 -#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f - -/* SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 -#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 - -/* SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 -#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 - -/* SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 credit_test */ -#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 -#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 - -/* SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 -#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 - -/* SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 -#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT 0x0000000150030280 -#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f -#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c - -/* SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 credit_test */ -#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 -#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f - -/* SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 -#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 - -/* SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 -#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 - -/* SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 credit_test */ -#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 -#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 - -/* SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 -#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 - -/* SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 -#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT 0x0000000150030290 -#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f -#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c - -/* SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 credit_test */ -#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 -#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f - -/* SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 -#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 - -/* SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 -#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 - -/* SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 credit_test */ -#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 -#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 - -/* SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 -#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 - -/* SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 -#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT 0x00000001500302a0 -#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f -#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c - -/* SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 credit_test */ -#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 -#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f - -/* SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 -#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 - -/* SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 -#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 - -/* SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 credit_test */ -#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 -#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 - -/* SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 -#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 - -/* SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 -#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT 0x00000001500302b0 -#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f -#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c - -/* SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 credit_test */ -#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 -#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f - -/* SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 -#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 - -/* SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 -#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 - -/* SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 credit_test */ -#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 -#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 - -/* SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 -#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 - -/* SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 -#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT 0x0000000150030300 -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 - -/* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN */ -/* Description: vc0 debit dynamic value */ -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 - -/* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP */ -/* Description: vc0 debit captured value */ -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 - -/* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN */ -/* Description: vc2 debit dynamic value */ -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 - -/* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP */ -/* Description: vc2 debit captured value */ -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 -#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT 0x0000000150030310 -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 - -/* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN */ -/* Description: vc0 debit dynamic value */ -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 - -/* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP */ -/* Description: vc0 debit captured value */ -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 - -/* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN */ -/* Description: vc2 debit dynamic value */ -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 - -/* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP */ -/* Description: vc2 debit captured value */ -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 -#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT 0x0000000150030320 -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 - -/* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN */ -/* Description: vc0 debit dynamic value */ -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 - -/* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP */ -/* Description: vc0 debit captured value */ -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 - -/* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN */ -/* Description: vc2 debit dynamic value */ -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 - -/* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP */ -/* Description: vc2 debit captured value */ -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 -#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT 0x0000000150030330 -#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f -#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c - -/* SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 credit_test */ -#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 -#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f - -/* SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 -#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 - -/* SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 -#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 - -/* SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 credit_test */ -#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 -#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 - -/* SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 -#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 - -/* SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 -#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT 0x0000000150030340 -#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f -#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c - -/* SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 credit_test */ -#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 -#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f - -/* SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 -#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 - -/* SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 -#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 - -/* SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 credit_test */ -#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 -#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 - -/* SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 -#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 - -/* SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 -#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT 0x0000000150030350 -#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f -#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c - -/* SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 credit_test */ -#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 -#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f - -/* SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 -#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 - -/* SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 -#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 - -/* SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 credit_test */ -#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 -#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 - -/* SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 -#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 - -/* SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 -#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_0_INTRANI_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_0_INTRANI_FLOW 0x0000000150030360 -#define SH_XNNI0_0_INTRANI_FLOW_MASK 0x00000000000000bf -#define SH_XNNI0_0_INTRANI_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* ==================================================================== */ -/* Register "SH_XNNI0_1_INTRANI_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_1_INTRANI_FLOW 0x0000000150030370 -#define SH_XNNI0_1_INTRANI_FLOW_MASK 0x00000000000000bf -#define SH_XNNI0_1_INTRANI_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD */ -/* Description: vc1 withhold */ -#define SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD_SHFT 0 -#define SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED */ -/* Description: Force Credit on VC1 from debit cntr */ -#define SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED_SHFT 7 -#define SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED_MASK 0x0000000000000080 - -/* ==================================================================== */ -/* Register "SH_XNNI0_2_INTRANI_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_2_INTRANI_FLOW 0x0000000150030380 -#define SH_XNNI0_2_INTRANI_FLOW_MASK 0x00000000000000bf -#define SH_XNNI0_2_INTRANI_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD_SHFT 0 -#define SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 7 -#define SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000000080 - -/* ==================================================================== */ -/* Register "SH_XNNI0_3_INTRANI_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_3_INTRANI_FLOW 0x0000000150030390 -#define SH_XNNI0_3_INTRANI_FLOW_MASK 0x00000000000000bf -#define SH_XNNI0_3_INTRANI_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD */ -/* Description: vc3 withhold */ -#define SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD_SHFT 0 -#define SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED */ -/* Description: Force Credit on VC3 from debit cntr */ -#define SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED_SHFT 7 -#define SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED_MASK 0x0000000000000080 - -/* ==================================================================== */ -/* Register "SH_XNNI0_VCSWITCH_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_VCSWITCH_FLOW 0x00000001500303a0 -#define SH_XNNI0_VCSWITCH_FLOW_MASK 0x0000000701010101 -#define SH_XNNI0_VCSWITCH_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI0_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH */ -/* Description: Swap VC0/2 with VC1/3 */ -#define SH_XNNI0_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH_SHFT 0 -#define SH_XNNI0_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH_MASK 0x0000000000000001 - -/* SH_XNNI0_VCSWITCH_FLOW_PI_VCFIFO_SWITCH */ -/* Description: Swap VC0/2 with VC1/3 */ -#define SH_XNNI0_VCSWITCH_FLOW_PI_VCFIFO_SWITCH_SHFT 8 -#define SH_XNNI0_VCSWITCH_FLOW_PI_VCFIFO_SWITCH_MASK 0x0000000000000100 - -/* SH_XNNI0_VCSWITCH_FLOW_MD_VCFIFO_SWITCH */ -/* Description: Swap VC0/2 with VC1/3 */ -#define SH_XNNI0_VCSWITCH_FLOW_MD_VCFIFO_SWITCH_SHFT 16 -#define SH_XNNI0_VCSWITCH_FLOW_MD_VCFIFO_SWITCH_MASK 0x0000000000010000 - -/* SH_XNNI0_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH */ -/* Description: Swap VC0/2 with VC1/3 */ -#define SH_XNNI0_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH_SHFT 24 -#define SH_XNNI0_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH_MASK 0x0000000001000000 - -/* SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN */ -#define SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN_SHFT 32 -#define SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN_MASK 0x0000000100000000 - -/* SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT */ -#define SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT_SHFT 33 -#define SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT_MASK 0x0000000200000000 - -/* SH_XNNI0_VCSWITCH_FLOW_ASYNC_FIFOES */ -#define SH_XNNI0_VCSWITCH_FLOW_ASYNC_FIFOES_SHFT 34 -#define SH_XNNI0_VCSWITCH_FLOW_ASYNC_FIFOES_MASK 0x0000000400000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_TIMER_REG" */ -/* ==================================================================== */ - -#define SH_XNNI0_TIMER_REG 0x00000001500303b0 -#define SH_XNNI0_TIMER_REG_MASK 0x0000000100ffffff -#define SH_XNNI0_TIMER_REG_INIT 0x0000000000ffffff - -/* SH_XNNI0_TIMER_REG_TIMEOUT_REG */ -/* Description: Master Timeout Counter */ -#define SH_XNNI0_TIMER_REG_TIMEOUT_REG_SHFT 0 -#define SH_XNNI0_TIMER_REG_TIMEOUT_REG_MASK 0x0000000000ffffff - -/* SH_XNNI0_TIMER_REG_LINKCLEANUP_REG */ -/* Description: Link Clean Up */ -#define SH_XNNI0_TIMER_REG_LINKCLEANUP_REG_SHFT 32 -#define SH_XNNI0_TIMER_REG_LINKCLEANUP_REG_MASK 0x0000000100000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_FIFO02_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_FIFO02_FLOW 0x00000001500303c0 -#define SH_XNNI0_FIFO02_FLOW_MASK 0x00000f0f0f0f0f0f -#define SH_XNNI0_FIFO02_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI0_FIFO02_FLOW_COUNT_VC0_LIMIT */ -/* Description: limit reg zero disables functionality */ -#define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_LIMIT_SHFT 0 -#define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_LIMIT_MASK 0x000000000000000f - -/* SH_XNNI0_FIFO02_FLOW_COUNT_VC0_DYN */ -/* Description: dynamic counter value */ -#define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_DYN_SHFT 8 -#define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_DYN_MASK 0x0000000000000f00 - -/* SH_XNNI0_FIFO02_FLOW_COUNT_VC0_CAP */ -/* Description: captured counter value */ -#define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_CAP_SHFT 16 -#define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_CAP_MASK 0x00000000000f0000 - -/* SH_XNNI0_FIFO02_FLOW_COUNT_VC2_LIMIT */ -/* Description: limit reg zero disables functionality */ -#define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_LIMIT_SHFT 24 -#define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_LIMIT_MASK 0x000000000f000000 - -/* SH_XNNI0_FIFO02_FLOW_COUNT_VC2_DYN */ -/* Description: counter dynamic value */ -#define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_DYN_SHFT 32 -#define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_DYN_MASK 0x0000000f00000000 - -/* SH_XNNI0_FIFO02_FLOW_COUNT_VC2_CAP */ -/* Description: captured counter value */ -#define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_CAP_SHFT 40 -#define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_CAP_MASK 0x00000f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_FIFO13_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_FIFO13_FLOW 0x00000001500303d0 -#define SH_XNNI0_FIFO13_FLOW_MASK 0x00000f0f0f0f0f0f -#define SH_XNNI0_FIFO13_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI0_FIFO13_FLOW_COUNT_VC1_LIMIT */ -/* Description: limit reg zero disables functionality */ -#define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_LIMIT_SHFT 0 -#define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_LIMIT_MASK 0x000000000000000f - -/* SH_XNNI0_FIFO13_FLOW_COUNT_VC1_DYN */ -/* Description: dynamic counter value */ -#define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_DYN_SHFT 8 -#define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_DYN_MASK 0x0000000000000f00 - -/* SH_XNNI0_FIFO13_FLOW_COUNT_VC1_CAP */ -/* Description: captured counter value */ -#define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_CAP_SHFT 16 -#define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_CAP_MASK 0x00000000000f0000 - -/* SH_XNNI0_FIFO13_FLOW_COUNT_VC3_LIMIT */ -/* Description: limit reg zero disables functionality */ -#define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_LIMIT_SHFT 24 -#define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_LIMIT_MASK 0x000000000f000000 - -/* SH_XNNI0_FIFO13_FLOW_COUNT_VC3_DYN */ -/* Description: counter dynamic value */ -#define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_DYN_SHFT 32 -#define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_DYN_MASK 0x0000000f00000000 - -/* SH_XNNI0_FIFO13_FLOW_COUNT_VC3_CAP */ -/* Description: captured counter value */ -#define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_CAP_SHFT 40 -#define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_CAP_MASK 0x00000f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_NI_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_NI_FLOW 0x00000001500303e0 -#define SH_XNNI0_NI_FLOW_MASK 0xff0fff0fff0fff0f -#define SH_XNNI0_NI_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI0_NI_FLOW_VC0_LIMIT */ -/* Description: vc0 limit reg, zero disables functionality */ -#define SH_XNNI0_NI_FLOW_VC0_LIMIT_SHFT 0 -#define SH_XNNI0_NI_FLOW_VC0_LIMIT_MASK 0x000000000000000f - -/* SH_XNNI0_NI_FLOW_VC0_DYN */ -/* Description: vc0 counter dynamic value */ -#define SH_XNNI0_NI_FLOW_VC0_DYN_SHFT 8 -#define SH_XNNI0_NI_FLOW_VC0_DYN_MASK 0x0000000000000f00 - -/* SH_XNNI0_NI_FLOW_VC0_CAP */ -/* Description: vc0 counter captured value */ -#define SH_XNNI0_NI_FLOW_VC0_CAP_SHFT 12 -#define SH_XNNI0_NI_FLOW_VC0_CAP_MASK 0x000000000000f000 - -/* SH_XNNI0_NI_FLOW_VC1_LIMIT */ -/* Description: vc1 limit reg, zero disables functionality */ -#define SH_XNNI0_NI_FLOW_VC1_LIMIT_SHFT 16 -#define SH_XNNI0_NI_FLOW_VC1_LIMIT_MASK 0x00000000000f0000 - -/* SH_XNNI0_NI_FLOW_VC1_DYN */ -/* Description: vc1 counter dynamic value */ -#define SH_XNNI0_NI_FLOW_VC1_DYN_SHFT 24 -#define SH_XNNI0_NI_FLOW_VC1_DYN_MASK 0x000000000f000000 - -/* SH_XNNI0_NI_FLOW_VC1_CAP */ -/* Description: vc1 counter captured value */ -#define SH_XNNI0_NI_FLOW_VC1_CAP_SHFT 28 -#define SH_XNNI0_NI_FLOW_VC1_CAP_MASK 0x00000000f0000000 - -/* SH_XNNI0_NI_FLOW_VC2_LIMIT */ -/* Description: vc2 limit reg, zero disables functionality */ -#define SH_XNNI0_NI_FLOW_VC2_LIMIT_SHFT 32 -#define SH_XNNI0_NI_FLOW_VC2_LIMIT_MASK 0x0000000f00000000 - -/* SH_XNNI0_NI_FLOW_VC2_DYN */ -/* Description: vc2 counter dynamic value */ -#define SH_XNNI0_NI_FLOW_VC2_DYN_SHFT 40 -#define SH_XNNI0_NI_FLOW_VC2_DYN_MASK 0x00000f0000000000 - -/* SH_XNNI0_NI_FLOW_VC2_CAP */ -/* Description: vc2 counter captured value */ -#define SH_XNNI0_NI_FLOW_VC2_CAP_SHFT 44 -#define SH_XNNI0_NI_FLOW_VC2_CAP_MASK 0x0000f00000000000 - -/* SH_XNNI0_NI_FLOW_VC3_LIMIT */ -/* Description: vc3 limit reg, zero disables functionality */ -#define SH_XNNI0_NI_FLOW_VC3_LIMIT_SHFT 48 -#define SH_XNNI0_NI_FLOW_VC3_LIMIT_MASK 0x000f000000000000 - -/* SH_XNNI0_NI_FLOW_VC3_DYN */ -/* Description: vc3 counter dynamic value */ -#define SH_XNNI0_NI_FLOW_VC3_DYN_SHFT 56 -#define SH_XNNI0_NI_FLOW_VC3_DYN_MASK 0x0f00000000000000 - -/* SH_XNNI0_NI_FLOW_VC3_CAP */ -/* Description: vc3 counter captured value */ -#define SH_XNNI0_NI_FLOW_VC3_CAP_SHFT 60 -#define SH_XNNI0_NI_FLOW_VC3_CAP_MASK 0xf000000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_DEAD_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI0_DEAD_FLOW 0x00000001500303f0 -#define SH_XNNI0_DEAD_FLOW_MASK 0xff0fff0fff0fff0f -#define SH_XNNI0_DEAD_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI0_DEAD_FLOW_VC0_LIMIT */ -/* Description: vc0 limit reg, zero disables functionality */ -#define SH_XNNI0_DEAD_FLOW_VC0_LIMIT_SHFT 0 -#define SH_XNNI0_DEAD_FLOW_VC0_LIMIT_MASK 0x000000000000000f - -/* SH_XNNI0_DEAD_FLOW_VC0_DYN */ -/* Description: vc0 counter dynamic value */ -#define SH_XNNI0_DEAD_FLOW_VC0_DYN_SHFT 8 -#define SH_XNNI0_DEAD_FLOW_VC0_DYN_MASK 0x0000000000000f00 - -/* SH_XNNI0_DEAD_FLOW_VC0_CAP */ -/* Description: vc0 counter captured value */ -#define SH_XNNI0_DEAD_FLOW_VC0_CAP_SHFT 12 -#define SH_XNNI0_DEAD_FLOW_VC0_CAP_MASK 0x000000000000f000 - -/* SH_XNNI0_DEAD_FLOW_VC1_LIMIT */ -/* Description: vc1 limit reg, zero disables functionality */ -#define SH_XNNI0_DEAD_FLOW_VC1_LIMIT_SHFT 16 -#define SH_XNNI0_DEAD_FLOW_VC1_LIMIT_MASK 0x00000000000f0000 - -/* SH_XNNI0_DEAD_FLOW_VC1_DYN */ -/* Description: vc1 counter dynamic value */ -#define SH_XNNI0_DEAD_FLOW_VC1_DYN_SHFT 24 -#define SH_XNNI0_DEAD_FLOW_VC1_DYN_MASK 0x000000000f000000 - -/* SH_XNNI0_DEAD_FLOW_VC1_CAP */ -/* Description: vc1 counter captured value */ -#define SH_XNNI0_DEAD_FLOW_VC1_CAP_SHFT 28 -#define SH_XNNI0_DEAD_FLOW_VC1_CAP_MASK 0x00000000f0000000 - -/* SH_XNNI0_DEAD_FLOW_VC2_LIMIT */ -/* Description: vc2 limit reg, zero disables functionality */ -#define SH_XNNI0_DEAD_FLOW_VC2_LIMIT_SHFT 32 -#define SH_XNNI0_DEAD_FLOW_VC2_LIMIT_MASK 0x0000000f00000000 - -/* SH_XNNI0_DEAD_FLOW_VC2_DYN */ -/* Description: vc2 counter dynamic value */ -#define SH_XNNI0_DEAD_FLOW_VC2_DYN_SHFT 40 -#define SH_XNNI0_DEAD_FLOW_VC2_DYN_MASK 0x00000f0000000000 - -/* SH_XNNI0_DEAD_FLOW_VC2_CAP */ -/* Description: vc2 counter captured value */ -#define SH_XNNI0_DEAD_FLOW_VC2_CAP_SHFT 44 -#define SH_XNNI0_DEAD_FLOW_VC2_CAP_MASK 0x0000f00000000000 - -/* SH_XNNI0_DEAD_FLOW_VC3_LIMIT */ -/* Description: vc3 limit reg, zero disables functionality */ -#define SH_XNNI0_DEAD_FLOW_VC3_LIMIT_SHFT 48 -#define SH_XNNI0_DEAD_FLOW_VC3_LIMIT_MASK 0x000f000000000000 - -/* SH_XNNI0_DEAD_FLOW_VC3_DYN */ -/* Description: vc3 counter dynamic value */ -#define SH_XNNI0_DEAD_FLOW_VC3_DYN_SHFT 56 -#define SH_XNNI0_DEAD_FLOW_VC3_DYN_MASK 0x0f00000000000000 - -/* SH_XNNI0_DEAD_FLOW_VC3_CAP */ -/* Description: vc3 counter captured value */ -#define SH_XNNI0_DEAD_FLOW_VC3_CAP_SHFT 60 -#define SH_XNNI0_DEAD_FLOW_VC3_CAP_MASK 0xf000000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI0_INJECT_AGE" */ -/* ==================================================================== */ - -#define SH_XNNI0_INJECT_AGE 0x0000000150030400 -#define SH_XNNI0_INJECT_AGE_MASK 0x000000000000ffff -#define SH_XNNI0_INJECT_AGE_INIT 0x0000000000000000 - -/* SH_XNNI0_INJECT_AGE_REQUEST_INJECT */ -/* Description: Value of AGE field for outgoing requests */ -#define SH_XNNI0_INJECT_AGE_REQUEST_INJECT_SHFT 0 -#define SH_XNNI0_INJECT_AGE_REQUEST_INJECT_MASK 0x00000000000000ff - -/* SH_XNNI0_INJECT_AGE_REPLY_INJECT */ -/* Description: Value of AGE field for outgoing replies */ -#define SH_XNNI0_INJECT_AGE_REPLY_INJECT_SHFT 8 -#define SH_XNNI0_INJECT_AGE_REPLY_INJECT_MASK 0x000000000000ff00 - -/* ==================================================================== */ -/* Register "SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT 0x0000000150030500 -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 - -/* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN */ -/* Description: vc0 debit dynamic value */ -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 - -/* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP */ -/* Description: vc0 debit captured value */ -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 - -/* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN */ -/* Description: vc2 debit dynamic value */ -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 - -/* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP */ -/* Description: vc2 debit captured value */ -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 -#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT 0x0000000150030510 -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 - -/* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN */ -/* Description: vc0 debit dynamic value */ -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 - -/* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP */ -/* Description: vc0 debit captured value */ -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 - -/* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN */ -/* Description: vc2 debit dynamic value */ -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 - -/* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP */ -/* Description: vc2 debit captured value */ -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 -#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT" */ -/* ==================================================================== */ - -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT 0x0000000150030520 -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 - -/* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 - -/* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 - -/* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN */ -/* Description: vc0 debit dynamic value */ -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 - -/* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP */ -/* Description: vc0 debit captured value */ -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 - -/* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN */ -/* Description: vc2 debit dynamic value */ -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 - -/* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP */ -/* Description: vc2 debit captured value */ -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 -#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT 0x0000000150030530 -#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f -#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c - -/* SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 credit_test */ -#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 -#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f - -/* SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 -#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 - -/* SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 -#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 - -/* SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 credit_test */ -#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 -#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 - -/* SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 -#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 - -/* SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 -#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT 0x0000000150030540 -#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f -#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c - -/* SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 credit_test */ -#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 -#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f - -/* SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 -#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 - -/* SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 -#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 - -/* SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 credit_test */ -#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 -#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 - -/* SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 -#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 - -/* SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 -#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT" */ -/* ==================================================================== */ - -#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT 0x0000000150030550 -#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f -#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c - -/* SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST */ -/* Description: vc0 credit_test */ -#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 -#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f - -/* SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN */ -/* Description: vc0 credit dynamic value */ -#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 -#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 - -/* SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP */ -/* Description: vc0 credit captured value */ -#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 -#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 - -/* SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST */ -/* Description: vc2 credit_test */ -#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 -#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 - -/* SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN */ -/* Description: vc2 credit dynamic value */ -#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 -#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 - -/* SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP */ -/* Description: vc2 credit captured value */ -#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 -#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_0_INTRANI_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_0_INTRANI_FLOW 0x0000000150030560 -#define SH_XNNI1_0_INTRANI_FLOW_MASK 0x00000000000000bf -#define SH_XNNI1_0_INTRANI_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD */ -/* Description: vc0 withhold */ -#define SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 -#define SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED */ -/* Description: Force Credit on VC0 from debit cntr */ -#define SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 -#define SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 - -/* ==================================================================== */ -/* Register "SH_XNNI1_1_INTRANI_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_1_INTRANI_FLOW 0x0000000150030570 -#define SH_XNNI1_1_INTRANI_FLOW_MASK 0x00000000000000bf -#define SH_XNNI1_1_INTRANI_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD */ -/* Description: vc1 withhold */ -#define SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD_SHFT 0 -#define SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED */ -/* Description: Force Credit on VC1 from debit cntr */ -#define SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED_SHFT 7 -#define SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED_MASK 0x0000000000000080 - -/* ==================================================================== */ -/* Register "SH_XNNI1_2_INTRANI_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_2_INTRANI_FLOW 0x0000000150030580 -#define SH_XNNI1_2_INTRANI_FLOW_MASK 0x00000000000000bf -#define SH_XNNI1_2_INTRANI_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD */ -/* Description: vc2 withhold */ -#define SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD_SHFT 0 -#define SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED */ -/* Description: Force Credit on VC2 from debit cntr */ -#define SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 7 -#define SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000000080 - -/* ==================================================================== */ -/* Register "SH_XNNI1_3_INTRANI_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_3_INTRANI_FLOW 0x0000000150030590 -#define SH_XNNI1_3_INTRANI_FLOW_MASK 0x00000000000000bf -#define SH_XNNI1_3_INTRANI_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD */ -/* Description: vc3 withhold */ -#define SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD_SHFT 0 -#define SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD_MASK 0x000000000000003f - -/* SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED */ -/* Description: Force Credit on VC3 from debit cntr */ -#define SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED_SHFT 7 -#define SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED_MASK 0x0000000000000080 - -/* ==================================================================== */ -/* Register "SH_XNNI1_VCSWITCH_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_VCSWITCH_FLOW 0x00000001500305a0 -#define SH_XNNI1_VCSWITCH_FLOW_MASK 0x0000000701010101 -#define SH_XNNI1_VCSWITCH_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI1_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH */ -/* Description: Swap VC0/2 with VC1/3 */ -#define SH_XNNI1_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH_SHFT 0 -#define SH_XNNI1_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH_MASK 0x0000000000000001 - -/* SH_XNNI1_VCSWITCH_FLOW_PI_VCFIFO_SWITCH */ -/* Description: Swap VC0/2 with VC1/3 */ -#define SH_XNNI1_VCSWITCH_FLOW_PI_VCFIFO_SWITCH_SHFT 8 -#define SH_XNNI1_VCSWITCH_FLOW_PI_VCFIFO_SWITCH_MASK 0x0000000000000100 - -/* SH_XNNI1_VCSWITCH_FLOW_MD_VCFIFO_SWITCH */ -/* Description: Swap VC0/2 with VC1/3 */ -#define SH_XNNI1_VCSWITCH_FLOW_MD_VCFIFO_SWITCH_SHFT 16 -#define SH_XNNI1_VCSWITCH_FLOW_MD_VCFIFO_SWITCH_MASK 0x0000000000010000 - -/* SH_XNNI1_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH */ -/* Description: Swap VC0/2 with VC1/3 */ -#define SH_XNNI1_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH_SHFT 24 -#define SH_XNNI1_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH_MASK 0x0000000001000000 - -/* SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN */ -#define SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN_SHFT 32 -#define SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN_MASK 0x0000000100000000 - -/* SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT */ -#define SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT_SHFT 33 -#define SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT_MASK 0x0000000200000000 - -/* SH_XNNI1_VCSWITCH_FLOW_ASYNC_FIFOES */ -#define SH_XNNI1_VCSWITCH_FLOW_ASYNC_FIFOES_SHFT 34 -#define SH_XNNI1_VCSWITCH_FLOW_ASYNC_FIFOES_MASK 0x0000000400000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_TIMER_REG" */ -/* ==================================================================== */ - -#define SH_XNNI1_TIMER_REG 0x00000001500305b0 -#define SH_XNNI1_TIMER_REG_MASK 0x0000000100ffffff -#define SH_XNNI1_TIMER_REG_INIT 0x0000000000ffffff - -/* SH_XNNI1_TIMER_REG_TIMEOUT_REG */ -/* Description: Master Timeout Counter */ -#define SH_XNNI1_TIMER_REG_TIMEOUT_REG_SHFT 0 -#define SH_XNNI1_TIMER_REG_TIMEOUT_REG_MASK 0x0000000000ffffff - -/* SH_XNNI1_TIMER_REG_LINKCLEANUP_REG */ -/* Description: Link Clean Up */ -#define SH_XNNI1_TIMER_REG_LINKCLEANUP_REG_SHFT 32 -#define SH_XNNI1_TIMER_REG_LINKCLEANUP_REG_MASK 0x0000000100000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_FIFO02_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_FIFO02_FLOW 0x00000001500305c0 -#define SH_XNNI1_FIFO02_FLOW_MASK 0x00000f0f0f0f0f0f -#define SH_XNNI1_FIFO02_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI1_FIFO02_FLOW_COUNT_VC0_LIMIT */ -/* Description: limit reg zero disables functionality */ -#define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_LIMIT_SHFT 0 -#define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_LIMIT_MASK 0x000000000000000f - -/* SH_XNNI1_FIFO02_FLOW_COUNT_VC0_DYN */ -/* Description: dynamic counter value */ -#define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_DYN_SHFT 8 -#define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_DYN_MASK 0x0000000000000f00 - -/* SH_XNNI1_FIFO02_FLOW_COUNT_VC0_CAP */ -/* Description: captured counter value */ -#define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_CAP_SHFT 16 -#define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_CAP_MASK 0x00000000000f0000 - -/* SH_XNNI1_FIFO02_FLOW_COUNT_VC2_LIMIT */ -/* Description: limit reg zero disables functionality */ -#define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_LIMIT_SHFT 24 -#define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_LIMIT_MASK 0x000000000f000000 - -/* SH_XNNI1_FIFO02_FLOW_COUNT_VC2_DYN */ -/* Description: counter dynamic value */ -#define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_DYN_SHFT 32 -#define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_DYN_MASK 0x0000000f00000000 - -/* SH_XNNI1_FIFO02_FLOW_COUNT_VC2_CAP */ -/* Description: captured counter value */ -#define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_CAP_SHFT 40 -#define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_CAP_MASK 0x00000f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_FIFO13_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_FIFO13_FLOW 0x00000001500305d0 -#define SH_XNNI1_FIFO13_FLOW_MASK 0x00000f0f0f0f0f0f -#define SH_XNNI1_FIFO13_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI1_FIFO13_FLOW_COUNT_VC1_LIMIT */ -/* Description: limit reg zero disables functionality */ -#define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_LIMIT_SHFT 0 -#define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_LIMIT_MASK 0x000000000000000f - -/* SH_XNNI1_FIFO13_FLOW_COUNT_VC1_DYN */ -/* Description: dynamic counter value */ -#define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_DYN_SHFT 8 -#define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_DYN_MASK 0x0000000000000f00 - -/* SH_XNNI1_FIFO13_FLOW_COUNT_VC1_CAP */ -/* Description: captured counter value */ -#define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_CAP_SHFT 16 -#define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_CAP_MASK 0x00000000000f0000 - -/* SH_XNNI1_FIFO13_FLOW_COUNT_VC3_LIMIT */ -/* Description: limit reg zero disables functionality */ -#define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_LIMIT_SHFT 24 -#define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_LIMIT_MASK 0x000000000f000000 - -/* SH_XNNI1_FIFO13_FLOW_COUNT_VC3_DYN */ -/* Description: counter dynamic value */ -#define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_DYN_SHFT 32 -#define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_DYN_MASK 0x0000000f00000000 - -/* SH_XNNI1_FIFO13_FLOW_COUNT_VC3_CAP */ -/* Description: captured counter value */ -#define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_CAP_SHFT 40 -#define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_CAP_MASK 0x00000f0000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_NI_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_NI_FLOW 0x00000001500305e0 -#define SH_XNNI1_NI_FLOW_MASK 0xff0fff0fff0fff0f -#define SH_XNNI1_NI_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI1_NI_FLOW_VC0_LIMIT */ -/* Description: vc0 limit reg, zero disables functionality */ -#define SH_XNNI1_NI_FLOW_VC0_LIMIT_SHFT 0 -#define SH_XNNI1_NI_FLOW_VC0_LIMIT_MASK 0x000000000000000f - -/* SH_XNNI1_NI_FLOW_VC0_DYN */ -/* Description: vc0 counter dynamic value */ -#define SH_XNNI1_NI_FLOW_VC0_DYN_SHFT 8 -#define SH_XNNI1_NI_FLOW_VC0_DYN_MASK 0x0000000000000f00 - -/* SH_XNNI1_NI_FLOW_VC0_CAP */ -/* Description: vc0 counter captured value */ -#define SH_XNNI1_NI_FLOW_VC0_CAP_SHFT 12 -#define SH_XNNI1_NI_FLOW_VC0_CAP_MASK 0x000000000000f000 - -/* SH_XNNI1_NI_FLOW_VC1_LIMIT */ -/* Description: vc1 limit reg, zero disables functionality */ -#define SH_XNNI1_NI_FLOW_VC1_LIMIT_SHFT 16 -#define SH_XNNI1_NI_FLOW_VC1_LIMIT_MASK 0x00000000000f0000 - -/* SH_XNNI1_NI_FLOW_VC1_DYN */ -/* Description: vc1 counter dynamic value */ -#define SH_XNNI1_NI_FLOW_VC1_DYN_SHFT 24 -#define SH_XNNI1_NI_FLOW_VC1_DYN_MASK 0x000000000f000000 - -/* SH_XNNI1_NI_FLOW_VC1_CAP */ -/* Description: vc1 counter captured value */ -#define SH_XNNI1_NI_FLOW_VC1_CAP_SHFT 28 -#define SH_XNNI1_NI_FLOW_VC1_CAP_MASK 0x00000000f0000000 - -/* SH_XNNI1_NI_FLOW_VC2_LIMIT */ -/* Description: vc2 limit reg, zero disables functionality */ -#define SH_XNNI1_NI_FLOW_VC2_LIMIT_SHFT 32 -#define SH_XNNI1_NI_FLOW_VC2_LIMIT_MASK 0x0000000f00000000 - -/* SH_XNNI1_NI_FLOW_VC2_DYN */ -/* Description: vc2 counter dynamic value */ -#define SH_XNNI1_NI_FLOW_VC2_DYN_SHFT 40 -#define SH_XNNI1_NI_FLOW_VC2_DYN_MASK 0x00000f0000000000 - -/* SH_XNNI1_NI_FLOW_VC2_CAP */ -/* Description: vc2 counter captured value */ -#define SH_XNNI1_NI_FLOW_VC2_CAP_SHFT 44 -#define SH_XNNI1_NI_FLOW_VC2_CAP_MASK 0x0000f00000000000 - -/* SH_XNNI1_NI_FLOW_VC3_LIMIT */ -/* Description: vc3 limit reg, zero disables functionality */ -#define SH_XNNI1_NI_FLOW_VC3_LIMIT_SHFT 48 -#define SH_XNNI1_NI_FLOW_VC3_LIMIT_MASK 0x000f000000000000 - -/* SH_XNNI1_NI_FLOW_VC3_DYN */ -/* Description: vc3 counter dynamic value */ -#define SH_XNNI1_NI_FLOW_VC3_DYN_SHFT 56 -#define SH_XNNI1_NI_FLOW_VC3_DYN_MASK 0x0f00000000000000 - -/* SH_XNNI1_NI_FLOW_VC3_CAP */ -/* Description: vc3 counter captured value */ -#define SH_XNNI1_NI_FLOW_VC3_CAP_SHFT 60 -#define SH_XNNI1_NI_FLOW_VC3_CAP_MASK 0xf000000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_DEAD_FLOW" */ -/* ==================================================================== */ - -#define SH_XNNI1_DEAD_FLOW 0x00000001500305f0 -#define SH_XNNI1_DEAD_FLOW_MASK 0xff0fff0fff0fff0f -#define SH_XNNI1_DEAD_FLOW_INIT 0x0000000000000000 - -/* SH_XNNI1_DEAD_FLOW_VC0_LIMIT */ -/* Description: vc0 limit reg, zero disables functionality */ -#define SH_XNNI1_DEAD_FLOW_VC0_LIMIT_SHFT 0 -#define SH_XNNI1_DEAD_FLOW_VC0_LIMIT_MASK 0x000000000000000f - -/* SH_XNNI1_DEAD_FLOW_VC0_DYN */ -/* Description: vc0 counter dynamic value */ -#define SH_XNNI1_DEAD_FLOW_VC0_DYN_SHFT 8 -#define SH_XNNI1_DEAD_FLOW_VC0_DYN_MASK 0x0000000000000f00 - -/* SH_XNNI1_DEAD_FLOW_VC0_CAP */ -/* Description: vc0 counter captured value */ -#define SH_XNNI1_DEAD_FLOW_VC0_CAP_SHFT 12 -#define SH_XNNI1_DEAD_FLOW_VC0_CAP_MASK 0x000000000000f000 - -/* SH_XNNI1_DEAD_FLOW_VC1_LIMIT */ -/* Description: vc1 limit reg, zero disables functionality */ -#define SH_XNNI1_DEAD_FLOW_VC1_LIMIT_SHFT 16 -#define SH_XNNI1_DEAD_FLOW_VC1_LIMIT_MASK 0x00000000000f0000 - -/* SH_XNNI1_DEAD_FLOW_VC1_DYN */ -/* Description: vc1 counter dynamic value */ -#define SH_XNNI1_DEAD_FLOW_VC1_DYN_SHFT 24 -#define SH_XNNI1_DEAD_FLOW_VC1_DYN_MASK 0x000000000f000000 - -/* SH_XNNI1_DEAD_FLOW_VC1_CAP */ -/* Description: vc1 counter captured value */ -#define SH_XNNI1_DEAD_FLOW_VC1_CAP_SHFT 28 -#define SH_XNNI1_DEAD_FLOW_VC1_CAP_MASK 0x00000000f0000000 - -/* SH_XNNI1_DEAD_FLOW_VC2_LIMIT */ -/* Description: vc2 limit reg, zero disables functionality */ -#define SH_XNNI1_DEAD_FLOW_VC2_LIMIT_SHFT 32 -#define SH_XNNI1_DEAD_FLOW_VC2_LIMIT_MASK 0x0000000f00000000 - -/* SH_XNNI1_DEAD_FLOW_VC2_DYN */ -/* Description: vc2 counter dynamic value */ -#define SH_XNNI1_DEAD_FLOW_VC2_DYN_SHFT 40 -#define SH_XNNI1_DEAD_FLOW_VC2_DYN_MASK 0x00000f0000000000 - -/* SH_XNNI1_DEAD_FLOW_VC2_CAP */ -/* Description: vc2 counter captured value */ -#define SH_XNNI1_DEAD_FLOW_VC2_CAP_SHFT 44 -#define SH_XNNI1_DEAD_FLOW_VC2_CAP_MASK 0x0000f00000000000 - -/* SH_XNNI1_DEAD_FLOW_VC3_LIMIT */ -/* Description: vc3 limit reg, zero disables functionality */ -#define SH_XNNI1_DEAD_FLOW_VC3_LIMIT_SHFT 48 -#define SH_XNNI1_DEAD_FLOW_VC3_LIMIT_MASK 0x000f000000000000 - -/* SH_XNNI1_DEAD_FLOW_VC3_DYN */ -/* Description: vc3 counter dynamic value */ -#define SH_XNNI1_DEAD_FLOW_VC3_DYN_SHFT 56 -#define SH_XNNI1_DEAD_FLOW_VC3_DYN_MASK 0x0f00000000000000 - -/* SH_XNNI1_DEAD_FLOW_VC3_CAP */ -/* Description: vc3 counter captured value */ -#define SH_XNNI1_DEAD_FLOW_VC3_CAP_SHFT 60 -#define SH_XNNI1_DEAD_FLOW_VC3_CAP_MASK 0xf000000000000000 - -/* ==================================================================== */ -/* Register "SH_XNNI1_INJECT_AGE" */ -/* ==================================================================== */ - -#define SH_XNNI1_INJECT_AGE 0x0000000150030600 -#define SH_XNNI1_INJECT_AGE_MASK 0x000000000000ffff -#define SH_XNNI1_INJECT_AGE_INIT 0x0000000000000000 - -/* SH_XNNI1_INJECT_AGE_REQUEST_INJECT */ -/* Description: Value of AGE field for outgoing requests */ -#define SH_XNNI1_INJECT_AGE_REQUEST_INJECT_SHFT 0 -#define SH_XNNI1_INJECT_AGE_REQUEST_INJECT_MASK 0x00000000000000ff - -/* SH_XNNI1_INJECT_AGE_REPLY_INJECT */ -/* Description: Value of AGE field for outgoing replies */ -#define SH_XNNI1_INJECT_AGE_REPLY_INJECT_SHFT 8 -#define SH_XNNI1_INJECT_AGE_REPLY_INJECT_MASK 0x000000000000ff00 - -/* ==================================================================== */ -/* Register "SH_XN_DEBUG_SEL" */ -/* XN Debug Port Select */ -/* ==================================================================== */ - -#define SH_XN_DEBUG_SEL 0x0000000150031000 -#define SH_XN_DEBUG_SEL_MASK 0xf777777777777777 -#define SH_XN_DEBUG_SEL_INIT 0x0000000000000000 - -/* SH_XN_DEBUG_SEL_NIBBLE0_RLM_SEL */ -/* Description: Nibble 0 RLM select */ -#define SH_XN_DEBUG_SEL_NIBBLE0_RLM_SEL_SHFT 0 -#define SH_XN_DEBUG_SEL_NIBBLE0_RLM_SEL_MASK 0x0000000000000007 - -/* SH_XN_DEBUG_SEL_NIBBLE0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_XN_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4 -#define SH_XN_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_XN_DEBUG_SEL_NIBBLE1_RLM_SEL */ -/* Description: Nibble 1 RLM select */ -#define SH_XN_DEBUG_SEL_NIBBLE1_RLM_SEL_SHFT 8 -#define SH_XN_DEBUG_SEL_NIBBLE1_RLM_SEL_MASK 0x0000000000000700 - -/* SH_XN_DEBUG_SEL_NIBBLE1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_XN_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12 -#define SH_XN_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_XN_DEBUG_SEL_NIBBLE2_RLM_SEL */ -/* Description: Nibble 2 RLM select */ -#define SH_XN_DEBUG_SEL_NIBBLE2_RLM_SEL_SHFT 16 -#define SH_XN_DEBUG_SEL_NIBBLE2_RLM_SEL_MASK 0x0000000000070000 - -/* SH_XN_DEBUG_SEL_NIBBLE2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_XN_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20 -#define SH_XN_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_XN_DEBUG_SEL_NIBBLE3_RLM_SEL */ -/* Description: Nibble 3 RLM select */ -#define SH_XN_DEBUG_SEL_NIBBLE3_RLM_SEL_SHFT 24 -#define SH_XN_DEBUG_SEL_NIBBLE3_RLM_SEL_MASK 0x0000000007000000 - -/* SH_XN_DEBUG_SEL_NIBBLE3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_XN_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28 -#define SH_XN_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_XN_DEBUG_SEL_NIBBLE4_RLM_SEL */ -/* Description: Nibble 4 RLM select */ -#define SH_XN_DEBUG_SEL_NIBBLE4_RLM_SEL_SHFT 32 -#define SH_XN_DEBUG_SEL_NIBBLE4_RLM_SEL_MASK 0x0000000700000000 - -/* SH_XN_DEBUG_SEL_NIBBLE4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_XN_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36 -#define SH_XN_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_XN_DEBUG_SEL_NIBBLE5_RLM_SEL */ -/* Description: Nibble 5 RLM select */ -#define SH_XN_DEBUG_SEL_NIBBLE5_RLM_SEL_SHFT 40 -#define SH_XN_DEBUG_SEL_NIBBLE5_RLM_SEL_MASK 0x0000070000000000 - -/* SH_XN_DEBUG_SEL_NIBBLE5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_XN_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44 -#define SH_XN_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_XN_DEBUG_SEL_NIBBLE6_RLM_SEL */ -/* Description: Nibble 6 RLM select */ -#define SH_XN_DEBUG_SEL_NIBBLE6_RLM_SEL_SHFT 48 -#define SH_XN_DEBUG_SEL_NIBBLE6_RLM_SEL_MASK 0x0007000000000000 - -/* SH_XN_DEBUG_SEL_NIBBLE6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_XN_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52 -#define SH_XN_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_XN_DEBUG_SEL_NIBBLE7_RLM_SEL */ -/* Description: Nibble 7 RLM select */ -#define SH_XN_DEBUG_SEL_NIBBLE7_RLM_SEL_SHFT 56 -#define SH_XN_DEBUG_SEL_NIBBLE7_RLM_SEL_MASK 0x0700000000000000 - -/* SH_XN_DEBUG_SEL_NIBBLE7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_XN_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60 -#define SH_XN_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* SH_XN_DEBUG_SEL_TRIGGER_ENABLE */ -/* Description: Enable trigger on bit 32 of Analyzer data */ -#define SH_XN_DEBUG_SEL_TRIGGER_ENABLE_SHFT 63 -#define SH_XN_DEBUG_SEL_TRIGGER_ENABLE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_XN_DEBUG_TRIG_SEL" */ -/* XN Debug trigger Select */ -/* ==================================================================== */ - -#define SH_XN_DEBUG_TRIG_SEL 0x0000000150031020 -#define SH_XN_DEBUG_TRIG_SEL_MASK 0x7777777777777777 -#define SH_XN_DEBUG_TRIG_SEL_INIT 0x0000000000000000 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER0_RLM_SEL */ -/* Description: Nibble 0 RLM select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER0_RLM_SEL_SHFT 0 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER0_RLM_SEL_MASK 0x0000000000000007 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL_SHFT 4 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER1_RLM_SEL */ -/* Description: Nibble 1 RLM select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER1_RLM_SEL_SHFT 8 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER1_RLM_SEL_MASK 0x0000000000000700 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL_SHFT 12 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER2_RLM_SEL */ -/* Description: Nibble 2 RLM select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER2_RLM_SEL_SHFT 16 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER2_RLM_SEL_MASK 0x0000000000070000 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL_SHFT 20 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER3_RLM_SEL */ -/* Description: Nibble 3 RLM select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER3_RLM_SEL_SHFT 24 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER3_RLM_SEL_MASK 0x0000000007000000 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL_SHFT 28 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER4_RLM_SEL */ -/* Description: Nibble 4 RLM select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER4_RLM_SEL_SHFT 32 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER4_RLM_SEL_MASK 0x0000000700000000 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL_SHFT 36 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER5_RLM_SEL */ -/* Description: Nibble 5 RLM select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER5_RLM_SEL_SHFT 40 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER5_RLM_SEL_MASK 0x0000070000000000 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL_SHFT 44 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER6_RLM_SEL */ -/* Description: Nibble 6 RLM select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER6_RLM_SEL_SHFT 48 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER6_RLM_SEL_MASK 0x0007000000000000 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL_SHFT 52 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER7_RLM_SEL */ -/* Description: Nibble 7 RLM select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER7_RLM_SEL_SHFT 56 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER7_RLM_SEL_MASK 0x0700000000000000 - -/* SH_XN_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL_SHFT 60 -#define SH_XN_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* ==================================================================== */ -/* Register "SH_XN_TRIGGER_COMPARE" */ -/* XN Debug Compare */ -/* ==================================================================== */ - -#define SH_XN_TRIGGER_COMPARE 0x0000000150031040 -#define SH_XN_TRIGGER_COMPARE_MASK 0x00000000ffffffff -#define SH_XN_TRIGGER_COMPARE_INIT 0x0000000000000000 - -/* SH_XN_TRIGGER_COMPARE_MASK */ -/* Description: Mask to select Debug bits for trigger generation */ -#define SH_XN_TRIGGER_COMPARE_MASK_SHFT 0 -#define SH_XN_TRIGGER_COMPARE_MASK_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_XN_TRIGGER_DATA" */ -/* XN Debug Compare Data */ -/* ==================================================================== */ - -#define SH_XN_TRIGGER_DATA 0x0000000150031050 -#define SH_XN_TRIGGER_DATA_MASK 0x00000000ffffffff -#define SH_XN_TRIGGER_DATA_INIT 0x00000000ffffffff - -/* SH_XN_TRIGGER_DATA_COMPARE_PATTERN */ -/* Description: debug bit pattern for trigger generation */ -#define SH_XN_TRIGGER_DATA_COMPARE_PATTERN_SHFT 0 -#define SH_XN_TRIGGER_DATA_COMPARE_PATTERN_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_DEBUG_SEL" */ -/* XN IILB Debug Port Select */ -/* ==================================================================== */ - -#define SH_XN_IILB_DEBUG_SEL 0x0000000150031060 -#define SH_XN_IILB_DEBUG_SEL_MASK 0x7777777777777777 -#define SH_XN_IILB_DEBUG_SEL_INIT 0x0000000000000000 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE0_INPUT_SEL */ -/* Description: Nibble 0 input select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE0_INPUT_SEL_SHFT 0 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE1_INPUT_SEL */ -/* Description: Nibble 1 input select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE1_INPUT_SEL_SHFT 8 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE2_INPUT_SEL */ -/* Description: Nibble 2 input select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE2_INPUT_SEL_SHFT 16 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE3_INPUT_SEL */ -/* Description: Nibble 3 input select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE3_INPUT_SEL_SHFT 24 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE4_INPUT_SEL */ -/* Description: Nibble 4 input select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE4_INPUT_SEL_SHFT 32 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE5_INPUT_SEL */ -/* Description: Nibble 5 input select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE5_INPUT_SEL_SHFT 40 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE6_INPUT_SEL */ -/* Description: Nibble 6 input select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE6_INPUT_SEL_SHFT 48 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE7_INPUT_SEL */ -/* Description: Nibble 7 input select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE7_INPUT_SEL_SHFT 56 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000 - -/* SH_XN_IILB_DEBUG_SEL_NIBBLE7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_XN_IILB_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60 -#define SH_XN_IILB_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* ==================================================================== */ -/* Register "SH_XN_PI_DEBUG_SEL" */ -/* XN PI Debug Port Select */ -/* ==================================================================== */ - -#define SH_XN_PI_DEBUG_SEL 0x00000001500310a0 -#define SH_XN_PI_DEBUG_SEL_MASK 0x7777777777777777 -#define SH_XN_PI_DEBUG_SEL_INIT 0x0000000000000000 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE0_INPUT_SEL */ -/* Description: Nibble 0 input select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE0_INPUT_SEL_SHFT 0 -#define SH_XN_PI_DEBUG_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4 -#define SH_XN_PI_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE1_INPUT_SEL */ -/* Description: Nibble 1 input select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE1_INPUT_SEL_SHFT 8 -#define SH_XN_PI_DEBUG_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12 -#define SH_XN_PI_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE2_INPUT_SEL */ -/* Description: Nibble 2 input select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE2_INPUT_SEL_SHFT 16 -#define SH_XN_PI_DEBUG_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20 -#define SH_XN_PI_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE3_INPUT_SEL */ -/* Description: Nibble 3 input select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE3_INPUT_SEL_SHFT 24 -#define SH_XN_PI_DEBUG_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28 -#define SH_XN_PI_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE4_INPUT_SEL */ -/* Description: Nibble 4 input select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE4_INPUT_SEL_SHFT 32 -#define SH_XN_PI_DEBUG_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36 -#define SH_XN_PI_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE5_INPUT_SEL */ -/* Description: Nibble 5 input select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE5_INPUT_SEL_SHFT 40 -#define SH_XN_PI_DEBUG_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44 -#define SH_XN_PI_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE6_INPUT_SEL */ -/* Description: Nibble 6 input select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE6_INPUT_SEL_SHFT 48 -#define SH_XN_PI_DEBUG_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52 -#define SH_XN_PI_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE7_INPUT_SEL */ -/* Description: Nibble 7 input select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE7_INPUT_SEL_SHFT 56 -#define SH_XN_PI_DEBUG_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000 - -/* SH_XN_PI_DEBUG_SEL_NIBBLE7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_XN_PI_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60 -#define SH_XN_PI_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* ==================================================================== */ -/* Register "SH_XN_MD_DEBUG_SEL" */ -/* XN MD Debug Port Select */ -/* ==================================================================== */ - -#define SH_XN_MD_DEBUG_SEL 0x0000000150031080 -#define SH_XN_MD_DEBUG_SEL_MASK 0x7777777777777777 -#define SH_XN_MD_DEBUG_SEL_INIT 0x0000000000000000 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE0_INPUT_SEL */ -/* Description: Nibble 0 input select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE0_INPUT_SEL_SHFT 0 -#define SH_XN_MD_DEBUG_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4 -#define SH_XN_MD_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE1_INPUT_SEL */ -/* Description: Nibble 1 input select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE1_INPUT_SEL_SHFT 8 -#define SH_XN_MD_DEBUG_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12 -#define SH_XN_MD_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE2_INPUT_SEL */ -/* Description: Nibble 2 input select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE2_INPUT_SEL_SHFT 16 -#define SH_XN_MD_DEBUG_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20 -#define SH_XN_MD_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE3_INPUT_SEL */ -/* Description: Nibble 3 input select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE3_INPUT_SEL_SHFT 24 -#define SH_XN_MD_DEBUG_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28 -#define SH_XN_MD_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE4_INPUT_SEL */ -/* Description: Nibble 4 input select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE4_INPUT_SEL_SHFT 32 -#define SH_XN_MD_DEBUG_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36 -#define SH_XN_MD_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE5_INPUT_SEL */ -/* Description: Nibble 5 input select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE5_INPUT_SEL_SHFT 40 -#define SH_XN_MD_DEBUG_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44 -#define SH_XN_MD_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE6_INPUT_SEL */ -/* Description: Nibble 6 input select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE6_INPUT_SEL_SHFT 48 -#define SH_XN_MD_DEBUG_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52 -#define SH_XN_MD_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE7_INPUT_SEL */ -/* Description: Nibble 7 input select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE7_INPUT_SEL_SHFT 56 -#define SH_XN_MD_DEBUG_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000 - -/* SH_XN_MD_DEBUG_SEL_NIBBLE7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_XN_MD_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60 -#define SH_XN_MD_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* ==================================================================== */ -/* Register "SH_XN_NI0_DEBUG_SEL" */ -/* XN NI0 Debug Port Select */ -/* ==================================================================== */ - -#define SH_XN_NI0_DEBUG_SEL 0x00000001500310c0 -#define SH_XN_NI0_DEBUG_SEL_MASK 0x7777777777777777 -#define SH_XN_NI0_DEBUG_SEL_INIT 0x0000000000000000 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE0_INPUT_SEL */ -/* Description: Nibble 0 input select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE0_INPUT_SEL_SHFT 0 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE1_INPUT_SEL */ -/* Description: Nibble 1 input select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE1_INPUT_SEL_SHFT 8 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE2_INPUT_SEL */ -/* Description: Nibble 2 input select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE2_INPUT_SEL_SHFT 16 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE3_INPUT_SEL */ -/* Description: Nibble 3 input select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE3_INPUT_SEL_SHFT 24 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE4_INPUT_SEL */ -/* Description: Nibble 4 input select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE4_INPUT_SEL_SHFT 32 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE5_INPUT_SEL */ -/* Description: Nibble 5 input select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE5_INPUT_SEL_SHFT 40 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE6_INPUT_SEL */ -/* Description: Nibble 6 input select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE6_INPUT_SEL_SHFT 48 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE7_INPUT_SEL */ -/* Description: Nibble 7 input select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE7_INPUT_SEL_SHFT 56 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000 - -/* SH_XN_NI0_DEBUG_SEL_NIBBLE7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_XN_NI0_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60 -#define SH_XN_NI0_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* ==================================================================== */ -/* Register "SH_XN_NI1_DEBUG_SEL" */ -/* XN NI1 Debug Port Select */ -/* ==================================================================== */ - -#define SH_XN_NI1_DEBUG_SEL 0x00000001500310e0 -#define SH_XN_NI1_DEBUG_SEL_MASK 0x7777777777777777 -#define SH_XN_NI1_DEBUG_SEL_INIT 0x0000000000000000 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE0_INPUT_SEL */ -/* Description: Nibble 0 input select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE0_INPUT_SEL_SHFT 0 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE1_INPUT_SEL */ -/* Description: Nibble 1 input select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE1_INPUT_SEL_SHFT 8 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE2_INPUT_SEL */ -/* Description: Nibble 2 input select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE2_INPUT_SEL_SHFT 16 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE3_INPUT_SEL */ -/* Description: Nibble 3 input select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE3_INPUT_SEL_SHFT 24 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE4_INPUT_SEL */ -/* Description: Nibble 4 input select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE4_INPUT_SEL_SHFT 32 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE5_INPUT_SEL */ -/* Description: Nibble 5 input select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE5_INPUT_SEL_SHFT 40 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE6_INPUT_SEL */ -/* Description: Nibble 6 input select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE6_INPUT_SEL_SHFT 48 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE7_INPUT_SEL */ -/* Description: Nibble 7 input select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE7_INPUT_SEL_SHFT 56 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000 - -/* SH_XN_NI1_DEBUG_SEL_NIBBLE7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_XN_NI1_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60 -#define SH_XN_NI1_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* ==================================================================== */ -/* Register "SH_XN_IILB_LB_CMP_EXP_DATA0" */ -/* IILB compare LB input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_IILB_LB_CMP_EXP_DATA0 0x0000000150031100 -#define SH_XN_IILB_LB_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_IILB_LB_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_IILB_LB_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_IILB_LB_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_IILB_LB_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_LB_CMP_EXP_DATA1" */ -/* IILB compare LB input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_IILB_LB_CMP_EXP_DATA1 0x0000000150031110 -#define SH_XN_IILB_LB_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_IILB_LB_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_IILB_LB_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_IILB_LB_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_IILB_LB_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_LB_CMP_ENABLE0" */ -/* IILB compare LB input enable0 */ -/* ==================================================================== */ - -#define SH_XN_IILB_LB_CMP_ENABLE0 0x0000000150031120 -#define SH_XN_IILB_LB_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_IILB_LB_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_IILB_LB_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_IILB_LB_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_IILB_LB_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_LB_CMP_ENABLE1" */ -/* IILB compare LB input enable1 */ -/* ==================================================================== */ - -#define SH_XN_IILB_LB_CMP_ENABLE1 0x0000000150031130 -#define SH_XN_IILB_LB_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_IILB_LB_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_IILB_LB_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_IILB_LB_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_IILB_LB_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_II_CMP_EXP_DATA0" */ -/* IILB compare II input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_IILB_II_CMP_EXP_DATA0 0x0000000150031140 -#define SH_XN_IILB_II_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_IILB_II_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_IILB_II_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_IILB_II_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_IILB_II_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_II_CMP_EXP_DATA1" */ -/* IILB compare II input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_IILB_II_CMP_EXP_DATA1 0x0000000150031150 -#define SH_XN_IILB_II_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_IILB_II_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_IILB_II_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_IILB_II_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_IILB_II_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_II_CMP_ENABLE0" */ -/* IILB compare II input enable0 */ -/* ==================================================================== */ - -#define SH_XN_IILB_II_CMP_ENABLE0 0x0000000150031160 -#define SH_XN_IILB_II_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_IILB_II_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_IILB_II_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_IILB_II_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_IILB_II_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_II_CMP_ENABLE1" */ -/* IILB compare II input enable1 */ -/* ==================================================================== */ - -#define SH_XN_IILB_II_CMP_ENABLE1 0x0000000150031170 -#define SH_XN_IILB_II_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_IILB_II_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_IILB_II_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_IILB_II_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_IILB_II_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_MD_CMP_EXP_DATA0" */ -/* IILB compare MD input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_IILB_MD_CMP_EXP_DATA0 0x0000000150031180 -#define SH_XN_IILB_MD_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_IILB_MD_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_IILB_MD_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_IILB_MD_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_IILB_MD_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_MD_CMP_EXP_DATA1" */ -/* IILB compare MD input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_IILB_MD_CMP_EXP_DATA1 0x0000000150031190 -#define SH_XN_IILB_MD_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_IILB_MD_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_IILB_MD_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_IILB_MD_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_IILB_MD_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_MD_CMP_ENABLE0" */ -/* IILB compare MD input enable0 */ -/* ==================================================================== */ - -#define SH_XN_IILB_MD_CMP_ENABLE0 0x00000001500311a0 -#define SH_XN_IILB_MD_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_IILB_MD_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_IILB_MD_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_IILB_MD_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_IILB_MD_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_MD_CMP_ENABLE1" */ -/* IILB compare MD input enable1 */ -/* ==================================================================== */ - -#define SH_XN_IILB_MD_CMP_ENABLE1 0x00000001500311b0 -#define SH_XN_IILB_MD_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_IILB_MD_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_IILB_MD_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_IILB_MD_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_IILB_MD_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_PI_CMP_EXP_DATA0" */ -/* IILB compare PI input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_IILB_PI_CMP_EXP_DATA0 0x00000001500311c0 -#define SH_XN_IILB_PI_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_IILB_PI_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_IILB_PI_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_IILB_PI_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_IILB_PI_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_PI_CMP_EXP_DATA1" */ -/* IILB compare PI input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_IILB_PI_CMP_EXP_DATA1 0x00000001500311d0 -#define SH_XN_IILB_PI_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_IILB_PI_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_IILB_PI_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_IILB_PI_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_IILB_PI_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_PI_CMP_ENABLE0" */ -/* IILB compare PI input enable0 */ -/* ==================================================================== */ - -#define SH_XN_IILB_PI_CMP_ENABLE0 0x00000001500311e0 -#define SH_XN_IILB_PI_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_IILB_PI_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_IILB_PI_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_IILB_PI_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_IILB_PI_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_PI_CMP_ENABLE1" */ -/* IILB compare PI input enable1 */ -/* ==================================================================== */ - -#define SH_XN_IILB_PI_CMP_ENABLE1 0x00000001500311f0 -#define SH_XN_IILB_PI_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_IILB_PI_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_IILB_PI_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_IILB_PI_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_IILB_PI_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_NI0_CMP_EXP_DATA0" */ -/* IILB compare NI0 input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_IILB_NI0_CMP_EXP_DATA0 0x0000000150031200 -#define SH_XN_IILB_NI0_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_IILB_NI0_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_IILB_NI0_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_IILB_NI0_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_IILB_NI0_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_NI0_CMP_EXP_DATA1" */ -/* IILB compare NI0 input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_IILB_NI0_CMP_EXP_DATA1 0x0000000150031210 -#define SH_XN_IILB_NI0_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_IILB_NI0_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_IILB_NI0_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_IILB_NI0_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_IILB_NI0_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_NI0_CMP_ENABLE0" */ -/* IILB compare NI0 input enable0 */ -/* ==================================================================== */ - -#define SH_XN_IILB_NI0_CMP_ENABLE0 0x0000000150031220 -#define SH_XN_IILB_NI0_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_IILB_NI0_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_IILB_NI0_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_IILB_NI0_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_IILB_NI0_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_NI0_CMP_ENABLE1" */ -/* IILB compare NI0 input enable1 */ -/* ==================================================================== */ - -#define SH_XN_IILB_NI0_CMP_ENABLE1 0x0000000150031230 -#define SH_XN_IILB_NI0_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_IILB_NI0_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_IILB_NI0_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_IILB_NI0_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_IILB_NI0_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_NI1_CMP_EXP_DATA0" */ -/* IILB compare NI1 input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_IILB_NI1_CMP_EXP_DATA0 0x0000000150031240 -#define SH_XN_IILB_NI1_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_IILB_NI1_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_IILB_NI1_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_IILB_NI1_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_IILB_NI1_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_NI1_CMP_EXP_DATA1" */ -/* IILB compare NI1 input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_IILB_NI1_CMP_EXP_DATA1 0x0000000150031250 -#define SH_XN_IILB_NI1_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_IILB_NI1_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_IILB_NI1_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_IILB_NI1_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_IILB_NI1_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_NI1_CMP_ENABLE0" */ -/* IILB compare NI1 input enable0 */ -/* ==================================================================== */ - -#define SH_XN_IILB_NI1_CMP_ENABLE0 0x0000000150031260 -#define SH_XN_IILB_NI1_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_IILB_NI1_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_IILB_NI1_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_IILB_NI1_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_IILB_NI1_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_IILB_NI1_CMP_ENABLE1" */ -/* IILB compare NI1 input enable1 */ -/* ==================================================================== */ - -#define SH_XN_IILB_NI1_CMP_ENABLE1 0x0000000150031270 -#define SH_XN_IILB_NI1_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_IILB_NI1_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_IILB_NI1_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_IILB_NI1_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_IILB_NI1_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_IILB_CMP_EXP_DATA0" */ -/* MD compare IILB input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_MD_IILB_CMP_EXP_DATA0 0x0000000150031500 -#define SH_XN_MD_IILB_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_MD_IILB_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_MD_IILB_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_MD_IILB_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_MD_IILB_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_IILB_CMP_EXP_DATA1" */ -/* MD compare IILB input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_MD_IILB_CMP_EXP_DATA1 0x0000000150031510 -#define SH_XN_MD_IILB_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_MD_IILB_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_MD_IILB_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_MD_IILB_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_MD_IILB_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_IILB_CMP_ENABLE0" */ -/* MD compare IILB input enable0 */ -/* ==================================================================== */ - -#define SH_XN_MD_IILB_CMP_ENABLE0 0x0000000150031520 -#define SH_XN_MD_IILB_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_MD_IILB_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_MD_IILB_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_MD_IILB_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_MD_IILB_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_IILB_CMP_ENABLE1" */ -/* MD compare IILB input enable1 */ -/* ==================================================================== */ - -#define SH_XN_MD_IILB_CMP_ENABLE1 0x0000000150031530 -#define SH_XN_MD_IILB_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_MD_IILB_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_MD_IILB_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_MD_IILB_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_MD_IILB_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_NI0_CMP_EXP_DATA0" */ -/* MD compare NI0 input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_MD_NI0_CMP_EXP_DATA0 0x0000000150031540 -#define SH_XN_MD_NI0_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_MD_NI0_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_MD_NI0_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_MD_NI0_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_MD_NI0_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_NI0_CMP_EXP_DATA1" */ -/* MD compare NI0 input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_MD_NI0_CMP_EXP_DATA1 0x0000000150031550 -#define SH_XN_MD_NI0_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_MD_NI0_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_MD_NI0_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_MD_NI0_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_MD_NI0_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_NI0_CMP_ENABLE0" */ -/* MD compare NI0 input enable0 */ -/* ==================================================================== */ - -#define SH_XN_MD_NI0_CMP_ENABLE0 0x0000000150031560 -#define SH_XN_MD_NI0_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_MD_NI0_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_MD_NI0_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_MD_NI0_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_MD_NI0_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_NI0_CMP_ENABLE1" */ -/* MD compare NI0 input enable1 */ -/* ==================================================================== */ - -#define SH_XN_MD_NI0_CMP_ENABLE1 0x0000000150031570 -#define SH_XN_MD_NI0_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_MD_NI0_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_MD_NI0_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_MD_NI0_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_MD_NI0_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_NI1_CMP_EXP_DATA0" */ -/* MD compare NI1 input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_MD_NI1_CMP_EXP_DATA0 0x0000000150031580 -#define SH_XN_MD_NI1_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_MD_NI1_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_MD_NI1_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_MD_NI1_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_MD_NI1_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_NI1_CMP_EXP_DATA1" */ -/* MD compare NI1 input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_MD_NI1_CMP_EXP_DATA1 0x0000000150031590 -#define SH_XN_MD_NI1_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_MD_NI1_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_MD_NI1_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_MD_NI1_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_MD_NI1_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_NI1_CMP_ENABLE0" */ -/* MD compare NI1 input enable0 */ -/* ==================================================================== */ - -#define SH_XN_MD_NI1_CMP_ENABLE0 0x00000001500315a0 -#define SH_XN_MD_NI1_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_MD_NI1_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_MD_NI1_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_MD_NI1_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_MD_NI1_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_NI1_CMP_ENABLE1" */ -/* MD compare NI1 input enable1 */ -/* ==================================================================== */ - -#define SH_XN_MD_NI1_CMP_ENABLE1 0x00000001500315b0 -#define SH_XN_MD_NI1_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_MD_NI1_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_MD_NI1_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_MD_NI1_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_MD_NI1_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_EXP_HDR0" */ -/* MD compare SIC input expected header0 */ -/* ==================================================================== */ - -#define SH_XN_MD_SIC_CMP_EXP_HDR0 0x00000001500315c0 -#define SH_XN_MD_SIC_CMP_EXP_HDR0_MASK 0xffffffffffffffff -#define SH_XN_MD_SIC_CMP_EXP_HDR0_INIT 0x0000000000000000 - -/* SH_XN_MD_SIC_CMP_EXP_HDR0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_MD_SIC_CMP_EXP_HDR0_DATA_SHFT 0 -#define SH_XN_MD_SIC_CMP_EXP_HDR0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_EXP_HDR1" */ -/* MD compare SIC input expected header1 */ -/* ==================================================================== */ - -#define SH_XN_MD_SIC_CMP_EXP_HDR1 0x00000001500315d0 -#define SH_XN_MD_SIC_CMP_EXP_HDR1_MASK 0x000003ffffffffff -#define SH_XN_MD_SIC_CMP_EXP_HDR1_INIT 0x0000000000000000 - -/* SH_XN_MD_SIC_CMP_EXP_HDR1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_MD_SIC_CMP_EXP_HDR1_DATA_SHFT 0 -#define SH_XN_MD_SIC_CMP_EXP_HDR1_DATA_MASK 0x000003ffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_HDR_ENABLE0" */ -/* MD compare SIC header enable0 */ -/* ==================================================================== */ - -#define SH_XN_MD_SIC_CMP_HDR_ENABLE0 0x00000001500315e0 -#define SH_XN_MD_SIC_CMP_HDR_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_MD_SIC_CMP_HDR_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_MD_SIC_CMP_HDR_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_MD_SIC_CMP_HDR_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_MD_SIC_CMP_HDR_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_HDR_ENABLE1" */ -/* MD compare SIC header enable1 */ -/* ==================================================================== */ - -#define SH_XN_MD_SIC_CMP_HDR_ENABLE1 0x00000001500315f0 -#define SH_XN_MD_SIC_CMP_HDR_ENABLE1_MASK 0x000003ffffffffff -#define SH_XN_MD_SIC_CMP_HDR_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_MD_SIC_CMP_HDR_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_MD_SIC_CMP_HDR_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_MD_SIC_CMP_HDR_ENABLE1_ENABLE_MASK 0x000003ffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_DATA0" */ -/* MD compare SIC data0 */ -/* ==================================================================== */ - -#define SH_XN_MD_SIC_CMP_DATA0 0x0000000150031600 -#define SH_XN_MD_SIC_CMP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_MD_SIC_CMP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_MD_SIC_CMP_DATA0_DATA0 */ -/* Description: Data0 */ -#define SH_XN_MD_SIC_CMP_DATA0_DATA0_SHFT 0 -#define SH_XN_MD_SIC_CMP_DATA0_DATA0_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_DATA1" */ -/* MD compare SIC data1 */ -/* ==================================================================== */ - -#define SH_XN_MD_SIC_CMP_DATA1 0x0000000150031610 -#define SH_XN_MD_SIC_CMP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_MD_SIC_CMP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_MD_SIC_CMP_DATA1_DATA1 */ -/* Description: Data1 */ -#define SH_XN_MD_SIC_CMP_DATA1_DATA1_SHFT 0 -#define SH_XN_MD_SIC_CMP_DATA1_DATA1_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_DATA2" */ -/* MD compare SIC data2 */ -/* ==================================================================== */ - -#define SH_XN_MD_SIC_CMP_DATA2 0x0000000150031620 -#define SH_XN_MD_SIC_CMP_DATA2_MASK 0xffffffffffffffff -#define SH_XN_MD_SIC_CMP_DATA2_INIT 0x0000000000000000 - -/* SH_XN_MD_SIC_CMP_DATA2_DATA2 */ -/* Description: Data2 */ -#define SH_XN_MD_SIC_CMP_DATA2_DATA2_SHFT 0 -#define SH_XN_MD_SIC_CMP_DATA2_DATA2_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_DATA3" */ -/* MD compare SIC data3 */ -/* ==================================================================== */ - -#define SH_XN_MD_SIC_CMP_DATA3 0x0000000150031630 -#define SH_XN_MD_SIC_CMP_DATA3_MASK 0xffffffffffffffff -#define SH_XN_MD_SIC_CMP_DATA3_INIT 0x0000000000000000 - -/* SH_XN_MD_SIC_CMP_DATA3_DATA3 */ -/* Description: Data3 */ -#define SH_XN_MD_SIC_CMP_DATA3_DATA3_SHFT 0 -#define SH_XN_MD_SIC_CMP_DATA3_DATA3_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE0" */ -/* MD enable compare SIC data0 */ -/* ==================================================================== */ - -#define SH_XN_MD_SIC_CMP_DATA_ENABLE0 0x0000000150031640 -#define SH_XN_MD_SIC_CMP_DATA_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_MD_SIC_CMP_DATA_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_MD_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0 */ -/* Description: Data0 */ -#define SH_XN_MD_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0_SHFT 0 -#define SH_XN_MD_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE1" */ -/* MD enable compare SIC data1 */ -/* ==================================================================== */ - -#define SH_XN_MD_SIC_CMP_DATA_ENABLE1 0x0000000150031650 -#define SH_XN_MD_SIC_CMP_DATA_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_MD_SIC_CMP_DATA_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_MD_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1 */ -/* Description: Data1 */ -#define SH_XN_MD_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1_SHFT 0 -#define SH_XN_MD_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE2" */ -/* MD enable compare SIC data2 */ -/* ==================================================================== */ - -#define SH_XN_MD_SIC_CMP_DATA_ENABLE2 0x0000000150031660 -#define SH_XN_MD_SIC_CMP_DATA_ENABLE2_MASK 0xffffffffffffffff -#define SH_XN_MD_SIC_CMP_DATA_ENABLE2_INIT 0x0000000000000000 - -/* SH_XN_MD_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2 */ -/* Description: Data2 */ -#define SH_XN_MD_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2_SHFT 0 -#define SH_XN_MD_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE3" */ -/* MD enable compare SIC data3 */ -/* ==================================================================== */ - -#define SH_XN_MD_SIC_CMP_DATA_ENABLE3 0x0000000150031670 -#define SH_XN_MD_SIC_CMP_DATA_ENABLE3_MASK 0xffffffffffffffff -#define SH_XN_MD_SIC_CMP_DATA_ENABLE3_INIT 0x0000000000000000 - -/* SH_XN_MD_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3 */ -/* Description: Data3 */ -#define SH_XN_MD_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3_SHFT 0 -#define SH_XN_MD_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_IILB_CMP_EXP_DATA0" */ -/* PI compare IILB input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_PI_IILB_CMP_EXP_DATA0 0x0000000150031300 -#define SH_XN_PI_IILB_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_PI_IILB_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_PI_IILB_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_PI_IILB_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_PI_IILB_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_IILB_CMP_EXP_DATA1" */ -/* PI compare IILB input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_PI_IILB_CMP_EXP_DATA1 0x0000000150031310 -#define SH_XN_PI_IILB_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_PI_IILB_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_PI_IILB_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_PI_IILB_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_PI_IILB_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_IILB_CMP_ENABLE0" */ -/* PI compare IILB input enable0 */ -/* ==================================================================== */ - -#define SH_XN_PI_IILB_CMP_ENABLE0 0x0000000150031320 -#define SH_XN_PI_IILB_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_PI_IILB_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_PI_IILB_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_PI_IILB_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_PI_IILB_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_IILB_CMP_ENABLE1" */ -/* PI compare IILB input enable1 */ -/* ==================================================================== */ - -#define SH_XN_PI_IILB_CMP_ENABLE1 0x0000000150031330 -#define SH_XN_PI_IILB_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_PI_IILB_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_PI_IILB_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_PI_IILB_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_PI_IILB_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_NI0_CMP_EXP_DATA0" */ -/* PI compare NI0 input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_PI_NI0_CMP_EXP_DATA0 0x0000000150031340 -#define SH_XN_PI_NI0_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_PI_NI0_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_PI_NI0_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_PI_NI0_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_PI_NI0_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_NI0_CMP_EXP_DATA1" */ -/* PI compare NI0 input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_PI_NI0_CMP_EXP_DATA1 0x0000000150031350 -#define SH_XN_PI_NI0_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_PI_NI0_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_PI_NI0_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_PI_NI0_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_PI_NI0_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_NI0_CMP_ENABLE0" */ -/* PI compare NI0 input enable0 */ -/* ==================================================================== */ - -#define SH_XN_PI_NI0_CMP_ENABLE0 0x0000000150031360 -#define SH_XN_PI_NI0_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_PI_NI0_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_PI_NI0_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_PI_NI0_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_PI_NI0_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_NI0_CMP_ENABLE1" */ -/* PI compare NI0 input enable1 */ -/* ==================================================================== */ - -#define SH_XN_PI_NI0_CMP_ENABLE1 0x0000000150031370 -#define SH_XN_PI_NI0_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_PI_NI0_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_PI_NI0_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_PI_NI0_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_PI_NI0_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_NI1_CMP_EXP_DATA0" */ -/* PI compare NI1 input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_PI_NI1_CMP_EXP_DATA0 0x0000000150031380 -#define SH_XN_PI_NI1_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_PI_NI1_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_PI_NI1_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_PI_NI1_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_PI_NI1_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_NI1_CMP_EXP_DATA1" */ -/* PI compare NI1 input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_PI_NI1_CMP_EXP_DATA1 0x0000000150031390 -#define SH_XN_PI_NI1_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_PI_NI1_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_PI_NI1_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_PI_NI1_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_PI_NI1_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_NI1_CMP_ENABLE0" */ -/* PI compare NI1 input enable0 */ -/* ==================================================================== */ - -#define SH_XN_PI_NI1_CMP_ENABLE0 0x00000001500313a0 -#define SH_XN_PI_NI1_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_PI_NI1_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_PI_NI1_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_PI_NI1_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_PI_NI1_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_NI1_CMP_ENABLE1" */ -/* PI compare NI1 input enable1 */ -/* ==================================================================== */ - -#define SH_XN_PI_NI1_CMP_ENABLE1 0x00000001500313b0 -#define SH_XN_PI_NI1_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_PI_NI1_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_PI_NI1_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_PI_NI1_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_PI_NI1_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_EXP_HDR0" */ -/* PI compare SIC input expected header0 */ -/* ==================================================================== */ - -#define SH_XN_PI_SIC_CMP_EXP_HDR0 0x00000001500313c0 -#define SH_XN_PI_SIC_CMP_EXP_HDR0_MASK 0xffffffffffffffff -#define SH_XN_PI_SIC_CMP_EXP_HDR0_INIT 0x0000000000000000 - -/* SH_XN_PI_SIC_CMP_EXP_HDR0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_PI_SIC_CMP_EXP_HDR0_DATA_SHFT 0 -#define SH_XN_PI_SIC_CMP_EXP_HDR0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_EXP_HDR1" */ -/* PI compare SIC input expected header1 */ -/* ==================================================================== */ - -#define SH_XN_PI_SIC_CMP_EXP_HDR1 0x00000001500313d0 -#define SH_XN_PI_SIC_CMP_EXP_HDR1_MASK 0x000003ffffffffff -#define SH_XN_PI_SIC_CMP_EXP_HDR1_INIT 0x0000000000000000 - -/* SH_XN_PI_SIC_CMP_EXP_HDR1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_PI_SIC_CMP_EXP_HDR1_DATA_SHFT 0 -#define SH_XN_PI_SIC_CMP_EXP_HDR1_DATA_MASK 0x000003ffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_HDR_ENABLE0" */ -/* PI compare SIC header enable0 */ -/* ==================================================================== */ - -#define SH_XN_PI_SIC_CMP_HDR_ENABLE0 0x00000001500313e0 -#define SH_XN_PI_SIC_CMP_HDR_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_PI_SIC_CMP_HDR_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_PI_SIC_CMP_HDR_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_PI_SIC_CMP_HDR_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_PI_SIC_CMP_HDR_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_HDR_ENABLE1" */ -/* PI compare SIC header enable1 */ -/* ==================================================================== */ - -#define SH_XN_PI_SIC_CMP_HDR_ENABLE1 0x00000001500313f0 -#define SH_XN_PI_SIC_CMP_HDR_ENABLE1_MASK 0x000003ffffffffff -#define SH_XN_PI_SIC_CMP_HDR_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_PI_SIC_CMP_HDR_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_PI_SIC_CMP_HDR_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_PI_SIC_CMP_HDR_ENABLE1_ENABLE_MASK 0x000003ffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_DATA0" */ -/* PI compare SIC data0 */ -/* ==================================================================== */ - -#define SH_XN_PI_SIC_CMP_DATA0 0x0000000150031400 -#define SH_XN_PI_SIC_CMP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_PI_SIC_CMP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_PI_SIC_CMP_DATA0_DATA0 */ -/* Description: Data0 */ -#define SH_XN_PI_SIC_CMP_DATA0_DATA0_SHFT 0 -#define SH_XN_PI_SIC_CMP_DATA0_DATA0_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_DATA1" */ -/* PI compare SIC data1 */ -/* ==================================================================== */ - -#define SH_XN_PI_SIC_CMP_DATA1 0x0000000150031410 -#define SH_XN_PI_SIC_CMP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_PI_SIC_CMP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_PI_SIC_CMP_DATA1_DATA1 */ -/* Description: Data1 */ -#define SH_XN_PI_SIC_CMP_DATA1_DATA1_SHFT 0 -#define SH_XN_PI_SIC_CMP_DATA1_DATA1_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_DATA2" */ -/* PI compare SIC data2 */ -/* ==================================================================== */ - -#define SH_XN_PI_SIC_CMP_DATA2 0x0000000150031420 -#define SH_XN_PI_SIC_CMP_DATA2_MASK 0xffffffffffffffff -#define SH_XN_PI_SIC_CMP_DATA2_INIT 0x0000000000000000 - -/* SH_XN_PI_SIC_CMP_DATA2_DATA2 */ -/* Description: Data2 */ -#define SH_XN_PI_SIC_CMP_DATA2_DATA2_SHFT 0 -#define SH_XN_PI_SIC_CMP_DATA2_DATA2_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_DATA3" */ -/* PI compare SIC data3 */ -/* ==================================================================== */ - -#define SH_XN_PI_SIC_CMP_DATA3 0x0000000150031430 -#define SH_XN_PI_SIC_CMP_DATA3_MASK 0xffffffffffffffff -#define SH_XN_PI_SIC_CMP_DATA3_INIT 0x0000000000000000 - -/* SH_XN_PI_SIC_CMP_DATA3_DATA3 */ -/* Description: Data3 */ -#define SH_XN_PI_SIC_CMP_DATA3_DATA3_SHFT 0 -#define SH_XN_PI_SIC_CMP_DATA3_DATA3_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE0" */ -/* PI enable compare SIC data0 */ -/* ==================================================================== */ - -#define SH_XN_PI_SIC_CMP_DATA_ENABLE0 0x0000000150031440 -#define SH_XN_PI_SIC_CMP_DATA_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_PI_SIC_CMP_DATA_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_PI_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0 */ -/* Description: Data0 */ -#define SH_XN_PI_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0_SHFT 0 -#define SH_XN_PI_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE1" */ -/* PI enable compare SIC data1 */ -/* ==================================================================== */ - -#define SH_XN_PI_SIC_CMP_DATA_ENABLE1 0x0000000150031450 -#define SH_XN_PI_SIC_CMP_DATA_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_PI_SIC_CMP_DATA_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_PI_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1 */ -/* Description: Data1 */ -#define SH_XN_PI_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1_SHFT 0 -#define SH_XN_PI_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE2" */ -/* PI enable compare SIC data2 */ -/* ==================================================================== */ - -#define SH_XN_PI_SIC_CMP_DATA_ENABLE2 0x0000000150031460 -#define SH_XN_PI_SIC_CMP_DATA_ENABLE2_MASK 0xffffffffffffffff -#define SH_XN_PI_SIC_CMP_DATA_ENABLE2_INIT 0x0000000000000000 - -/* SH_XN_PI_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2 */ -/* Description: Data2 */ -#define SH_XN_PI_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2_SHFT 0 -#define SH_XN_PI_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE3" */ -/* PI enable compare SIC data3 */ -/* ==================================================================== */ - -#define SH_XN_PI_SIC_CMP_DATA_ENABLE3 0x0000000150031470 -#define SH_XN_PI_SIC_CMP_DATA_ENABLE3_MASK 0xffffffffffffffff -#define SH_XN_PI_SIC_CMP_DATA_ENABLE3_INIT 0x0000000000000000 - -/* SH_XN_PI_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3 */ -/* Description: Data3 */ -#define SH_XN_PI_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3_SHFT 0 -#define SH_XN_PI_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_IILB_CMP_EXP_DATA0" */ -/* NI0 compare IILB input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_NI0_IILB_CMP_EXP_DATA0 0x0000000150031700 -#define SH_XN_NI0_IILB_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_NI0_IILB_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_NI0_IILB_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_NI0_IILB_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_NI0_IILB_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_IILB_CMP_EXP_DATA1" */ -/* NI0 compare IILB input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_NI0_IILB_CMP_EXP_DATA1 0x0000000150031710 -#define SH_XN_NI0_IILB_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_NI0_IILB_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_NI0_IILB_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_NI0_IILB_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_NI0_IILB_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_IILB_CMP_ENABLE0" */ -/* NI0 compare IILB input enable0 */ -/* ==================================================================== */ - -#define SH_XN_NI0_IILB_CMP_ENABLE0 0x0000000150031720 -#define SH_XN_NI0_IILB_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_NI0_IILB_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_NI0_IILB_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_NI0_IILB_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_NI0_IILB_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_IILB_CMP_ENABLE1" */ -/* NI0 compare IILB input enable1 */ -/* ==================================================================== */ - -#define SH_XN_NI0_IILB_CMP_ENABLE1 0x0000000150031730 -#define SH_XN_NI0_IILB_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_NI0_IILB_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_NI0_IILB_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_NI0_IILB_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_NI0_IILB_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_PI_CMP_EXP_DATA0" */ -/* NI0 compare PI input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_NI0_PI_CMP_EXP_DATA0 0x0000000150031740 -#define SH_XN_NI0_PI_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_NI0_PI_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_NI0_PI_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_NI0_PI_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_NI0_PI_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_PI_CMP_EXP_DATA1" */ -/* NI0 compare PI input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_NI0_PI_CMP_EXP_DATA1 0x0000000150031750 -#define SH_XN_NI0_PI_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_NI0_PI_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_NI0_PI_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_NI0_PI_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_NI0_PI_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_PI_CMP_ENABLE0" */ -/* NI0 compare PI input enable0 */ -/* ==================================================================== */ - -#define SH_XN_NI0_PI_CMP_ENABLE0 0x0000000150031760 -#define SH_XN_NI0_PI_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_NI0_PI_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_NI0_PI_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_NI0_PI_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_NI0_PI_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_PI_CMP_ENABLE1" */ -/* NI0 compare PI input enable1 */ -/* ==================================================================== */ - -#define SH_XN_NI0_PI_CMP_ENABLE1 0x0000000150031770 -#define SH_XN_NI0_PI_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_NI0_PI_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_NI0_PI_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_NI0_PI_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_NI0_PI_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_MD_CMP_EXP_DATA0" */ -/* NI0 compare MD input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_NI0_MD_CMP_EXP_DATA0 0x0000000150031780 -#define SH_XN_NI0_MD_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_NI0_MD_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_NI0_MD_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_NI0_MD_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_NI0_MD_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_MD_CMP_EXP_DATA1" */ -/* NI0 compare MD input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_NI0_MD_CMP_EXP_DATA1 0x0000000150031790 -#define SH_XN_NI0_MD_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_NI0_MD_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_NI0_MD_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_NI0_MD_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_NI0_MD_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_MD_CMP_ENABLE0" */ -/* NI0 compare MD input enable0 */ -/* ==================================================================== */ - -#define SH_XN_NI0_MD_CMP_ENABLE0 0x00000001500317a0 -#define SH_XN_NI0_MD_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_NI0_MD_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_NI0_MD_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_NI0_MD_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_NI0_MD_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_MD_CMP_ENABLE1" */ -/* NI0 compare MD input enable1 */ -/* ==================================================================== */ - -#define SH_XN_NI0_MD_CMP_ENABLE1 0x00000001500317b0 -#define SH_XN_NI0_MD_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_NI0_MD_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_NI0_MD_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_NI0_MD_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_NI0_MD_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_NI_CMP_EXP_DATA0" */ -/* NI0 compare NI input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_NI0_NI_CMP_EXP_DATA0 0x00000001500317c0 -#define SH_XN_NI0_NI_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_NI0_NI_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_NI0_NI_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_NI0_NI_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_NI0_NI_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_NI_CMP_EXP_DATA1" */ -/* NI0 compare NI input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_NI0_NI_CMP_EXP_DATA1 0x00000001500317d0 -#define SH_XN_NI0_NI_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_NI0_NI_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_NI0_NI_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_NI0_NI_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_NI0_NI_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_NI_CMP_ENABLE0" */ -/* NI0 compare NI input enable0 */ -/* ==================================================================== */ - -#define SH_XN_NI0_NI_CMP_ENABLE0 0x00000001500317e0 -#define SH_XN_NI0_NI_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_NI0_NI_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_NI0_NI_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_NI0_NI_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_NI0_NI_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_NI_CMP_ENABLE1" */ -/* NI0 compare NI input enable1 */ -/* ==================================================================== */ - -#define SH_XN_NI0_NI_CMP_ENABLE1 0x00000001500317f0 -#define SH_XN_NI0_NI_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_NI0_NI_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_NI0_NI_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_NI0_NI_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_NI0_NI_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_LLP_CMP_EXP_DATA0" */ -/* NI0 compare LLP input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_NI0_LLP_CMP_EXP_DATA0 0x0000000150031800 -#define SH_XN_NI0_LLP_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_NI0_LLP_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_NI0_LLP_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_NI0_LLP_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_NI0_LLP_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_LLP_CMP_EXP_DATA1" */ -/* NI0 compare LLP input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_NI0_LLP_CMP_EXP_DATA1 0x0000000150031810 -#define SH_XN_NI0_LLP_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_NI0_LLP_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_NI0_LLP_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_NI0_LLP_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_NI0_LLP_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_LLP_CMP_ENABLE0" */ -/* NI0 compare LLP input enable0 */ -/* ==================================================================== */ - -#define SH_XN_NI0_LLP_CMP_ENABLE0 0x0000000150031820 -#define SH_XN_NI0_LLP_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_NI0_LLP_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_NI0_LLP_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_NI0_LLP_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_NI0_LLP_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI0_LLP_CMP_ENABLE1" */ -/* NI0 compare LLP input enable1 */ -/* ==================================================================== */ - -#define SH_XN_NI0_LLP_CMP_ENABLE1 0x0000000150031830 -#define SH_XN_NI0_LLP_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_NI0_LLP_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_NI0_LLP_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_NI0_LLP_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_NI0_LLP_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_IILB_CMP_EXP_DATA0" */ -/* NI1 compare IILB input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_NI1_IILB_CMP_EXP_DATA0 0x0000000150031900 -#define SH_XN_NI1_IILB_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_NI1_IILB_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_NI1_IILB_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_NI1_IILB_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_NI1_IILB_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_IILB_CMP_EXP_DATA1" */ -/* NI1 compare IILB input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_NI1_IILB_CMP_EXP_DATA1 0x0000000150031910 -#define SH_XN_NI1_IILB_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_NI1_IILB_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_NI1_IILB_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_NI1_IILB_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_NI1_IILB_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_IILB_CMP_ENABLE0" */ -/* NI1 compare IILB input enable0 */ -/* ==================================================================== */ - -#define SH_XN_NI1_IILB_CMP_ENABLE0 0x0000000150031920 -#define SH_XN_NI1_IILB_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_NI1_IILB_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_NI1_IILB_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_NI1_IILB_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_NI1_IILB_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_IILB_CMP_ENABLE1" */ -/* NI1 compare IILB input enable1 */ -/* ==================================================================== */ - -#define SH_XN_NI1_IILB_CMP_ENABLE1 0x0000000150031930 -#define SH_XN_NI1_IILB_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_NI1_IILB_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_NI1_IILB_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_NI1_IILB_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_NI1_IILB_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_PI_CMP_EXP_DATA0" */ -/* NI1 compare PI input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_NI1_PI_CMP_EXP_DATA0 0x0000000150031940 -#define SH_XN_NI1_PI_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_NI1_PI_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_NI1_PI_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_NI1_PI_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_NI1_PI_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_PI_CMP_EXP_DATA1" */ -/* NI1 compare PI input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_NI1_PI_CMP_EXP_DATA1 0x0000000150031950 -#define SH_XN_NI1_PI_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_NI1_PI_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_NI1_PI_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_NI1_PI_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_NI1_PI_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_PI_CMP_ENABLE0" */ -/* NI1 compare PI input enable0 */ -/* ==================================================================== */ - -#define SH_XN_NI1_PI_CMP_ENABLE0 0x0000000150031960 -#define SH_XN_NI1_PI_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_NI1_PI_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_NI1_PI_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_NI1_PI_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_NI1_PI_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_PI_CMP_ENABLE1" */ -/* NI1 compare PI input enable1 */ -/* ==================================================================== */ - -#define SH_XN_NI1_PI_CMP_ENABLE1 0x0000000150031970 -#define SH_XN_NI1_PI_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_NI1_PI_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_NI1_PI_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_NI1_PI_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_NI1_PI_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_MD_CMP_EXP_DATA0" */ -/* NI1 compare MD input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_NI1_MD_CMP_EXP_DATA0 0x0000000150031980 -#define SH_XN_NI1_MD_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_NI1_MD_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_NI1_MD_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_NI1_MD_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_NI1_MD_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_MD_CMP_EXP_DATA1" */ -/* NI1 compare MD input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_NI1_MD_CMP_EXP_DATA1 0x0000000150031990 -#define SH_XN_NI1_MD_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_NI1_MD_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_NI1_MD_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_NI1_MD_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_NI1_MD_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_MD_CMP_ENABLE0" */ -/* NI1 compare MD input enable0 */ -/* ==================================================================== */ - -#define SH_XN_NI1_MD_CMP_ENABLE0 0x00000001500319a0 -#define SH_XN_NI1_MD_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_NI1_MD_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_NI1_MD_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_NI1_MD_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_NI1_MD_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_MD_CMP_ENABLE1" */ -/* NI1 compare MD input enable1 */ -/* ==================================================================== */ - -#define SH_XN_NI1_MD_CMP_ENABLE1 0x00000001500319b0 -#define SH_XN_NI1_MD_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_NI1_MD_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_NI1_MD_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_NI1_MD_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_NI1_MD_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_NI_CMP_EXP_DATA0" */ -/* NI1 compare NI input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_NI1_NI_CMP_EXP_DATA0 0x00000001500319c0 -#define SH_XN_NI1_NI_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_NI1_NI_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_NI1_NI_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_NI1_NI_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_NI1_NI_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_NI_CMP_EXP_DATA1" */ -/* NI1 compare NI input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_NI1_NI_CMP_EXP_DATA1 0x00000001500319d0 -#define SH_XN_NI1_NI_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_NI1_NI_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_NI1_NI_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_NI1_NI_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_NI1_NI_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_NI_CMP_ENABLE0" */ -/* NI1 compare NI input enable0 */ -/* ==================================================================== */ - -#define SH_XN_NI1_NI_CMP_ENABLE0 0x00000001500319e0 -#define SH_XN_NI1_NI_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_NI1_NI_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_NI1_NI_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_NI1_NI_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_NI1_NI_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_NI_CMP_ENABLE1" */ -/* NI1 compare NI input enable1 */ -/* ==================================================================== */ - -#define SH_XN_NI1_NI_CMP_ENABLE1 0x00000001500319f0 -#define SH_XN_NI1_NI_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_NI1_NI_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_NI1_NI_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_NI1_NI_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_NI1_NI_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_LLP_CMP_EXP_DATA0" */ -/* NI1 compare LLP input expected data0 */ -/* ==================================================================== */ - -#define SH_XN_NI1_LLP_CMP_EXP_DATA0 0x0000000150031a00 -#define SH_XN_NI1_LLP_CMP_EXP_DATA0_MASK 0xffffffffffffffff -#define SH_XN_NI1_LLP_CMP_EXP_DATA0_INIT 0x0000000000000000 - -/* SH_XN_NI1_LLP_CMP_EXP_DATA0_DATA */ -/* Description: Expected data 0 */ -#define SH_XN_NI1_LLP_CMP_EXP_DATA0_DATA_SHFT 0 -#define SH_XN_NI1_LLP_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_LLP_CMP_EXP_DATA1" */ -/* NI1 compare LLP input expected data1 */ -/* ==================================================================== */ - -#define SH_XN_NI1_LLP_CMP_EXP_DATA1 0x0000000150031a10 -#define SH_XN_NI1_LLP_CMP_EXP_DATA1_MASK 0xffffffffffffffff -#define SH_XN_NI1_LLP_CMP_EXP_DATA1_INIT 0x0000000000000000 - -/* SH_XN_NI1_LLP_CMP_EXP_DATA1_DATA */ -/* Description: Expected data 1 */ -#define SH_XN_NI1_LLP_CMP_EXP_DATA1_DATA_SHFT 0 -#define SH_XN_NI1_LLP_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_LLP_CMP_ENABLE0" */ -/* NI1 compare LLP input enable0 */ -/* ==================================================================== */ - -#define SH_XN_NI1_LLP_CMP_ENABLE0 0x0000000150031a20 -#define SH_XN_NI1_LLP_CMP_ENABLE0_MASK 0xffffffffffffffff -#define SH_XN_NI1_LLP_CMP_ENABLE0_INIT 0x0000000000000000 - -/* SH_XN_NI1_LLP_CMP_ENABLE0_ENABLE */ -/* Description: Enable0 */ -#define SH_XN_NI1_LLP_CMP_ENABLE0_ENABLE_SHFT 0 -#define SH_XN_NI1_LLP_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_NI1_LLP_CMP_ENABLE1" */ -/* NI1 compare LLP input enable1 */ -/* ==================================================================== */ - -#define SH_XN_NI1_LLP_CMP_ENABLE1 0x0000000150031a30 -#define SH_XN_NI1_LLP_CMP_ENABLE1_MASK 0xffffffffffffffff -#define SH_XN_NI1_LLP_CMP_ENABLE1_INIT 0x0000000000000000 - -/* SH_XN_NI1_LLP_CMP_ENABLE1_ENABLE */ -/* Description: Enable1 */ -#define SH_XN_NI1_LLP_CMP_ENABLE1_ENABLE_SHFT 0 -#define SH_XN_NI1_LLP_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XNPI_ECC_INJ_REG" */ -/* ==================================================================== */ - -#define SH_XNPI_ECC_INJ_REG 0x0000000150032000 -#define SH_XNPI_ECC_INJ_REG_MASK 0xf0fff0fff0fff0ff -#define SH_XNPI_ECC_INJ_REG_INIT 0x0000000000000000 - -/* SH_XNPI_ECC_INJ_REG_BYTE0 */ -/* Description: Replacement Checkbyte */ -#define SH_XNPI_ECC_INJ_REG_BYTE0_SHFT 0 -#define SH_XNPI_ECC_INJ_REG_BYTE0_MASK 0x00000000000000ff - -/* SH_XNPI_ECC_INJ_REG_DATA_1SHOT0 */ -/* Description: 1 shot mask data */ -#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT0_SHFT 12 -#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT0_MASK 0x0000000000001000 - -/* SH_XNPI_ECC_INJ_REG_DATA_CONT0 */ -/* Description: toggle mask data */ -#define SH_XNPI_ECC_INJ_REG_DATA_CONT0_SHFT 13 -#define SH_XNPI_ECC_INJ_REG_DATA_CONT0_MASK 0x0000000000002000 - -/* SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT0 */ -/* Description: Replace Checkbyte One Shot */ -#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT0_SHFT 14 -#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT0_MASK 0x0000000000004000 - -/* SH_XNPI_ECC_INJ_REG_DATA_CB_CONT0 */ -/* Description: Replace Checkbyte Continuous */ -#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT0_SHFT 15 -#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT0_MASK 0x0000000000008000 - -/* SH_XNPI_ECC_INJ_REG_BYTE1 */ -/* Description: Replacement Checkbyte */ -#define SH_XNPI_ECC_INJ_REG_BYTE1_SHFT 16 -#define SH_XNPI_ECC_INJ_REG_BYTE1_MASK 0x0000000000ff0000 - -/* SH_XNPI_ECC_INJ_REG_DATA_1SHOT1 */ -/* Description: 1 shot mask data */ -#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT1_SHFT 28 -#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT1_MASK 0x0000000010000000 - -/* SH_XNPI_ECC_INJ_REG_DATA_CONT1 */ -/* Description: toggle mask data */ -#define SH_XNPI_ECC_INJ_REG_DATA_CONT1_SHFT 29 -#define SH_XNPI_ECC_INJ_REG_DATA_CONT1_MASK 0x0000000020000000 - -/* SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT1 */ -/* Description: Replace Checkbyte One Shot */ -#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT1_SHFT 30 -#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT1_MASK 0x0000000040000000 - -/* SH_XNPI_ECC_INJ_REG_DATA_CB_CONT1 */ -/* Description: Replace Checkbyte Continous */ -#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT1_SHFT 31 -#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT1_MASK 0x0000000080000000 - -/* SH_XNPI_ECC_INJ_REG_BYTE2 */ -/* Description: Replacement Checkbyte */ -#define SH_XNPI_ECC_INJ_REG_BYTE2_SHFT 32 -#define SH_XNPI_ECC_INJ_REG_BYTE2_MASK 0x000000ff00000000 - -/* SH_XNPI_ECC_INJ_REG_DATA_1SHOT2 */ -/* Description: 1 shot mask data */ -#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT2_SHFT 44 -#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT2_MASK 0x0000100000000000 - -/* SH_XNPI_ECC_INJ_REG_DATA_CONT2 */ -/* Description: toggle mask data */ -#define SH_XNPI_ECC_INJ_REG_DATA_CONT2_SHFT 45 -#define SH_XNPI_ECC_INJ_REG_DATA_CONT2_MASK 0x0000200000000000 - -/* SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT2 */ -/* Description: Replace Checkbyte OneShot */ -#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT2_SHFT 46 -#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT2_MASK 0x0000400000000000 - -/* SH_XNPI_ECC_INJ_REG_DATA_CB_CONT2 */ -/* Description: Replace Checkbyte Continous */ -#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT2_SHFT 47 -#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT2_MASK 0x0000800000000000 - -/* SH_XNPI_ECC_INJ_REG_BYTE3 */ -/* Description: Replacement Checkbyte */ -#define SH_XNPI_ECC_INJ_REG_BYTE3_SHFT 48 -#define SH_XNPI_ECC_INJ_REG_BYTE3_MASK 0x00ff000000000000 - -/* SH_XNPI_ECC_INJ_REG_DATA_1SHOT3 */ -/* Description: 1 shot mask data */ -#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT3_SHFT 60 -#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT3_MASK 0x1000000000000000 - -/* SH_XNPI_ECC_INJ_REG_DATA_CONT3 */ -/* Description: toggle mask data */ -#define SH_XNPI_ECC_INJ_REG_DATA_CONT3_SHFT 61 -#define SH_XNPI_ECC_INJ_REG_DATA_CONT3_MASK 0x2000000000000000 - -/* SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT3 */ -/* Description: Replace Checkbyte One-Shot */ -#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT3_SHFT 62 -#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT3_MASK 0x4000000000000000 - -/* SH_XNPI_ECC_INJ_REG_DATA_CB_CONT3 */ -/* Description: Replace Checkbyte Continous */ -#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT3_SHFT 63 -#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT3_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_XNPI_ECC0_INJ_MASK_REG" */ -/* ==================================================================== */ - -#define SH_XNPI_ECC0_INJ_MASK_REG 0x0000000150032008 -#define SH_XNPI_ECC0_INJ_MASK_REG_MASK 0xffffffffffffffff -#define SH_XNPI_ECC0_INJ_MASK_REG_INIT 0x0000000000000000 - -/* SH_XNPI_ECC0_INJ_MASK_REG_MASK_ECC0 */ -/* Description: Replacement Data */ -#define SH_XNPI_ECC0_INJ_MASK_REG_MASK_ECC0_SHFT 0 -#define SH_XNPI_ECC0_INJ_MASK_REG_MASK_ECC0_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XNPI_ECC1_INJ_MASK_REG" */ -/* ==================================================================== */ - -#define SH_XNPI_ECC1_INJ_MASK_REG 0x0000000150032010 -#define SH_XNPI_ECC1_INJ_MASK_REG_MASK 0xffffffffffffffff -#define SH_XNPI_ECC1_INJ_MASK_REG_INIT 0x0000000000000000 - -/* SH_XNPI_ECC1_INJ_MASK_REG_MASK_ECC1 */ -/* Description: Replacement Data */ -#define SH_XNPI_ECC1_INJ_MASK_REG_MASK_ECC1_SHFT 0 -#define SH_XNPI_ECC1_INJ_MASK_REG_MASK_ECC1_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XNPI_ECC2_INJ_MASK_REG" */ -/* ==================================================================== */ - -#define SH_XNPI_ECC2_INJ_MASK_REG 0x0000000150032018 -#define SH_XNPI_ECC2_INJ_MASK_REG_MASK 0xffffffffffffffff -#define SH_XNPI_ECC2_INJ_MASK_REG_INIT 0x0000000000000000 - -/* SH_XNPI_ECC2_INJ_MASK_REG_MASK_ECC2 */ -/* Description: Replacement Data */ -#define SH_XNPI_ECC2_INJ_MASK_REG_MASK_ECC2_SHFT 0 -#define SH_XNPI_ECC2_INJ_MASK_REG_MASK_ECC2_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XNPI_ECC3_INJ_MASK_REG" */ -/* ==================================================================== */ - -#define SH_XNPI_ECC3_INJ_MASK_REG 0x0000000150032020 -#define SH_XNPI_ECC3_INJ_MASK_REG_MASK 0xffffffffffffffff -#define SH_XNPI_ECC3_INJ_MASK_REG_INIT 0x0000000000000000 - -/* SH_XNPI_ECC3_INJ_MASK_REG_MASK_ECC3 */ -/* Description: Replacement Data */ -#define SH_XNPI_ECC3_INJ_MASK_REG_MASK_ECC3_SHFT 0 -#define SH_XNPI_ECC3_INJ_MASK_REG_MASK_ECC3_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XNMD_ECC_INJ_REG" */ -/* ==================================================================== */ - -#define SH_XNMD_ECC_INJ_REG 0x0000000150032030 -#define SH_XNMD_ECC_INJ_REG_MASK 0xf0fff0fff0fff0ff -#define SH_XNMD_ECC_INJ_REG_INIT 0x0000000000000000 - -/* SH_XNMD_ECC_INJ_REG_BYTE0 */ -/* Description: Replacement Checkbyte */ -#define SH_XNMD_ECC_INJ_REG_BYTE0_SHFT 0 -#define SH_XNMD_ECC_INJ_REG_BYTE0_MASK 0x00000000000000ff - -/* SH_XNMD_ECC_INJ_REG_DATA_1SHOT0 */ -/* Description: 1 shot mask data */ -#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT0_SHFT 12 -#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT0_MASK 0x0000000000001000 - -/* SH_XNMD_ECC_INJ_REG_DATA_CONT0 */ -/* Description: toggle mask data */ -#define SH_XNMD_ECC_INJ_REG_DATA_CONT0_SHFT 13 -#define SH_XNMD_ECC_INJ_REG_DATA_CONT0_MASK 0x0000000000002000 - -/* SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT0 */ -/* Description: Replace Checkbyte One Shot */ -#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT0_SHFT 14 -#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT0_MASK 0x0000000000004000 - -/* SH_XNMD_ECC_INJ_REG_DATA_CB_CONT0 */ -/* Description: Replace Checkbyte Continuous */ -#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT0_SHFT 15 -#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT0_MASK 0x0000000000008000 - -/* SH_XNMD_ECC_INJ_REG_BYTE1 */ -/* Description: Replacement Checkbyte */ -#define SH_XNMD_ECC_INJ_REG_BYTE1_SHFT 16 -#define SH_XNMD_ECC_INJ_REG_BYTE1_MASK 0x0000000000ff0000 - -/* SH_XNMD_ECC_INJ_REG_DATA_1SHOT1 */ -/* Description: 1 shot mask data */ -#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT1_SHFT 28 -#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT1_MASK 0x0000000010000000 - -/* SH_XNMD_ECC_INJ_REG_DATA_CONT1 */ -/* Description: toggle mask data */ -#define SH_XNMD_ECC_INJ_REG_DATA_CONT1_SHFT 29 -#define SH_XNMD_ECC_INJ_REG_DATA_CONT1_MASK 0x0000000020000000 - -/* SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT1 */ -/* Description: Replace Checkbyte One Shot */ -#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT1_SHFT 30 -#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT1_MASK 0x0000000040000000 - -/* SH_XNMD_ECC_INJ_REG_DATA_CB_CONT1 */ -/* Description: Replace Checkbyte Continous */ -#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT1_SHFT 31 -#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT1_MASK 0x0000000080000000 - -/* SH_XNMD_ECC_INJ_REG_BYTE2 */ -/* Description: Replacement Checkbyte */ -#define SH_XNMD_ECC_INJ_REG_BYTE2_SHFT 32 -#define SH_XNMD_ECC_INJ_REG_BYTE2_MASK 0x000000ff00000000 - -/* SH_XNMD_ECC_INJ_REG_DATA_1SHOT2 */ -/* Description: 1 shot mask data */ -#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT2_SHFT 44 -#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT2_MASK 0x0000100000000000 - -/* SH_XNMD_ECC_INJ_REG_DATA_CONT2 */ -/* Description: toggle mask data */ -#define SH_XNMD_ECC_INJ_REG_DATA_CONT2_SHFT 45 -#define SH_XNMD_ECC_INJ_REG_DATA_CONT2_MASK 0x0000200000000000 - -/* SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT2 */ -/* Description: Replace Checkbyte OneShot */ -#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT2_SHFT 46 -#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT2_MASK 0x0000400000000000 - -/* SH_XNMD_ECC_INJ_REG_DATA_CB_CONT2 */ -/* Description: Replace Checkbyte Continous */ -#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT2_SHFT 47 -#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT2_MASK 0x0000800000000000 - -/* SH_XNMD_ECC_INJ_REG_BYTE3 */ -/* Description: Replacement Checkbyte */ -#define SH_XNMD_ECC_INJ_REG_BYTE3_SHFT 48 -#define SH_XNMD_ECC_INJ_REG_BYTE3_MASK 0x00ff000000000000 - -/* SH_XNMD_ECC_INJ_REG_DATA_1SHOT3 */ -/* Description: 1 shot mask data */ -#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT3_SHFT 60 -#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT3_MASK 0x1000000000000000 - -/* SH_XNMD_ECC_INJ_REG_DATA_CONT3 */ -/* Description: toggle mask data */ -#define SH_XNMD_ECC_INJ_REG_DATA_CONT3_SHFT 61 -#define SH_XNMD_ECC_INJ_REG_DATA_CONT3_MASK 0x2000000000000000 - -/* SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT3 */ -/* Description: Replace Checkbyte One-Shot */ -#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT3_SHFT 62 -#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT3_MASK 0x4000000000000000 - -/* SH_XNMD_ECC_INJ_REG_DATA_CB_CONT3 */ -/* Description: Replace Checkbyte Continous */ -#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT3_SHFT 63 -#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT3_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_XNMD_ECC0_INJ_MASK_REG" */ -/* ==================================================================== */ - -#define SH_XNMD_ECC0_INJ_MASK_REG 0x0000000150032038 -#define SH_XNMD_ECC0_INJ_MASK_REG_MASK 0xffffffffffffffff -#define SH_XNMD_ECC0_INJ_MASK_REG_INIT 0x0000000000000000 - -/* SH_XNMD_ECC0_INJ_MASK_REG_MASK_ECC0 */ -/* Description: Replacement Data */ -#define SH_XNMD_ECC0_INJ_MASK_REG_MASK_ECC0_SHFT 0 -#define SH_XNMD_ECC0_INJ_MASK_REG_MASK_ECC0_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XNMD_ECC1_INJ_MASK_REG" */ -/* ==================================================================== */ - -#define SH_XNMD_ECC1_INJ_MASK_REG 0x0000000150032040 -#define SH_XNMD_ECC1_INJ_MASK_REG_MASK 0xffffffffffffffff -#define SH_XNMD_ECC1_INJ_MASK_REG_INIT 0x0000000000000000 - -/* SH_XNMD_ECC1_INJ_MASK_REG_MASK_ECC1 */ -/* Description: Replacement Data */ -#define SH_XNMD_ECC1_INJ_MASK_REG_MASK_ECC1_SHFT 0 -#define SH_XNMD_ECC1_INJ_MASK_REG_MASK_ECC1_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XNMD_ECC2_INJ_MASK_REG" */ -/* ==================================================================== */ - -#define SH_XNMD_ECC2_INJ_MASK_REG 0x0000000150032048 -#define SH_XNMD_ECC2_INJ_MASK_REG_MASK 0xffffffffffffffff -#define SH_XNMD_ECC2_INJ_MASK_REG_INIT 0x0000000000000000 - -/* SH_XNMD_ECC2_INJ_MASK_REG_MASK_ECC2 */ -/* Description: Replacement Data */ -#define SH_XNMD_ECC2_INJ_MASK_REG_MASK_ECC2_SHFT 0 -#define SH_XNMD_ECC2_INJ_MASK_REG_MASK_ECC2_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XNMD_ECC3_INJ_MASK_REG" */ -/* ==================================================================== */ - -#define SH_XNMD_ECC3_INJ_MASK_REG 0x0000000150032050 -#define SH_XNMD_ECC3_INJ_MASK_REG_MASK 0xffffffffffffffff -#define SH_XNMD_ECC3_INJ_MASK_REG_INIT 0x0000000000000000 - -/* SH_XNMD_ECC3_INJ_MASK_REG_MASK_ECC3 */ -/* Description: Replacement Data */ -#define SH_XNMD_ECC3_INJ_MASK_REG_MASK_ECC3_SHFT 0 -#define SH_XNMD_ECC3_INJ_MASK_REG_MASK_ECC3_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XNMD_ECC_ERR_REPORT" */ -/* ==================================================================== */ - -#define SH_XNMD_ECC_ERR_REPORT 0x0000000150032058 -#define SH_XNMD_ECC_ERR_REPORT_MASK 0x0001000100010001 -#define SH_XNMD_ECC_ERR_REPORT_INIT 0x0000000000000000 - -/* SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE0 */ -/* Description: Disable Error Correction */ -#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE0_SHFT 0 -#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE0_MASK 0x0000000000000001 - -/* SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE1 */ -/* Description: Disable Error Correction */ -#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE1_SHFT 16 -#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE1_MASK 0x0000000000010000 - -/* SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE2 */ -/* Description: Disable Error Correction */ -#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE2_SHFT 32 -#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE2_MASK 0x0000000100000000 - -/* SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE3 */ -/* Description: Disable Error Correction */ -#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE3_SHFT 48 -#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE3_MASK 0x0001000000000000 - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_SUMMARY_1" */ -/* ni0 Error Summary Bits */ -/* ==================================================================== */ - -#define SH_NI0_ERROR_SUMMARY_1 0x0000000150040500 -#define SH_NI0_ERROR_SUMMARY_1_MASK 0xffffffffffffffff -#define SH_NI0_ERROR_SUMMARY_1_INIT 0xffffffffffffffff - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0 */ -/* Description: Fifo 02 debit0 overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2 */ -/* Description: Fifo 02 debit2 overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0 */ -/* Description: Fifo 13 debit0 overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2 */ -/* Description: Fifo 13 debit2 overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit overflow 0 */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit overflow 1 */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit overflow 2 */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit overflow 0 */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit overflow 1 */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit overflow 2 */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0 */ -/* Description: PI Fifo debit0 overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2 */ -/* Description: PI Fifo debit2 overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0 */ -/* Description: IILB Fifo debit0 overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2 */ -/* Description: IILB Fifo debit2 overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0 */ -/* Description: MD Fifo debit0 overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2 */ -/* Description: MD Fifo debit2 overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0 */ -/* Description: NI Fifo debit0 overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1 */ -/* Description: NI Fifo debit1 overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2 */ -/* Description: NI Fifo debit2 overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3 */ -/* Description: NI Fifo debit3 overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit overflow */ -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0 */ -/* Description: Fifo02 vc0 tail timeout */ -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56 -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000 - -/* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2 */ -/* Description: Fifo02 vc2 tail timeout */ -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57 -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000 - -/* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1 */ -/* Description: Fifo13 vc1 tail timeout */ -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58 -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000 - -/* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3 */ -/* Description: Fifo13 vc3 tail timeout */ -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59 -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000 - -/* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0 */ -/* Description: NI vc0 tail timeout */ -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0_SHFT 60 -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000 - -/* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1 */ -/* Description: NI vc1 tail timeout */ -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1_SHFT 61 -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000 - -/* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2 */ -/* Description: NI vc2 tail timeout */ -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2_SHFT 62 -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000 - -/* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3 */ -/* Description: NI vc3 tail timeout */ -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3_SHFT 63 -#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_SUMMARY_1_ALIAS" */ -/* ni0 Error Summary Bits Alias */ -/* ==================================================================== */ - -#define SH_NI0_ERROR_SUMMARY_1_ALIAS 0x0000000150040508 - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_SUMMARY_2" */ -/* ni0 Error Summary Bits */ -/* ==================================================================== */ - -#define SH_NI0_ERROR_SUMMARY_2 0x0000000150040510 -#define SH_NI0_ERROR_SUMMARY_2_MASK 0x7fffffff003fffff -#define SH_NI0_ERROR_SUMMARY_2_INIT 0x7fffffff003fffff - -/* SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCNI */ -/* Description: Illegal VC NI */ -#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCNI_SHFT 0 -#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCNI_MASK 0x0000000000000001 - -/* SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCPI */ -/* Description: Illegal VC PI */ -#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCPI_SHFT 1 -#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCPI_MASK 0x0000000000000002 - -/* SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCMD */ -/* Description: Illegal VC MD */ -#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCMD_SHFT 2 -#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCMD_MASK 0x0000000000000004 - -/* SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCIILB */ -/* Description: Illegal VC IILB */ -#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCIILB_SHFT 3 -#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCIILB_MASK 0x0000000000000008 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit underflow 0 */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit underflow 1 */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit underflow 2 */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit underflow 0 */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit underflow 1 */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit underflow 2 */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit underflow */ -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0 */ -/* Description: llp deadlock vc0 */ -#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0_SHFT 56 -#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000 - -/* SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1 */ -/* Description: llp deadlock vc1 */ -#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1_SHFT 57 -#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000 - -/* SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2 */ -/* Description: llp deadlock vc2 */ -#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2_SHFT 58 -#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000 - -/* SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3 */ -/* Description: llp deadlock vc3 */ -#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3_SHFT 59 -#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000 - -/* SH_NI0_ERROR_SUMMARY_2_CHIPLET_NOMATCH */ -/* Description: chiplet nomatch */ -#define SH_NI0_ERROR_SUMMARY_2_CHIPLET_NOMATCH_SHFT 60 -#define SH_NI0_ERROR_SUMMARY_2_CHIPLET_NOMATCH_MASK 0x1000000000000000 - -/* SH_NI0_ERROR_SUMMARY_2_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_NI0_ERROR_SUMMARY_2_LUT_READ_ERROR_SHFT 61 -#define SH_NI0_ERROR_SUMMARY_2_LUT_READ_ERROR_MASK 0x2000000000000000 - -/* SH_NI0_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR */ -/* Description: Retry Timeout Error */ -#define SH_NI0_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR_SHFT 62 -#define SH_NI0_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_SUMMARY_2_ALIAS" */ -/* ni0 Error Summary Bits Alias */ -/* ==================================================================== */ - -#define SH_NI0_ERROR_SUMMARY_2_ALIAS 0x0000000150040518 - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_OVERFLOW_1" */ -/* ni0 Error Overflow Bits */ -/* ==================================================================== */ - -#define SH_NI0_ERROR_OVERFLOW_1 0x0000000150040520 -#define SH_NI0_ERROR_OVERFLOW_1_MASK 0xffffffffffffffff -#define SH_NI0_ERROR_OVERFLOW_1_INIT 0xffffffffffffffff - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0 */ -/* Description: Fifo 02 debit0 overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2 */ -/* Description: Fifo 02 debit2 overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0 */ -/* Description: Fifo 13 debit0 overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2 */ -/* Description: Fifo 13 debit2 overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit overflow 0 */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit overflow 1 */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit overflow 2 */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit overflow 0 */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit overflow 1 */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit overflow 2 */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0 */ -/* Description: PI Fifo debit0 overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2 */ -/* Description: PI Fifo debit2 overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0 */ -/* Description: IILB Fifo debit0 overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2 */ -/* Description: IILB Fifo debit2 overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0 */ -/* Description: MD Fifo debit0 overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2 */ -/* Description: MD Fifo debit2 overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0 */ -/* Description: NI Fifo debit0 overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1 */ -/* Description: NI Fifo debit1 overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2 */ -/* Description: NI Fifo debit2 overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3 */ -/* Description: NI Fifo debit3 overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit overflow */ -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0 */ -/* Description: Fifo02 vc0 tail timeout */ -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56 -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2 */ -/* Description: Fifo02 vc2 tail timeout */ -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57 -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1 */ -/* Description: Fifo13 vc1 tail timeout */ -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58 -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3 */ -/* Description: Fifo13 vc3 tail timeout */ -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59 -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0 */ -/* Description: NI vc0 tail timeout */ -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0_SHFT 60 -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1 */ -/* Description: NI vc1 tail timeout */ -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1_SHFT 61 -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2 */ -/* Description: NI vc2 tail timeout */ -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2_SHFT 62 -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000 - -/* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3 */ -/* Description: NI vc3 tail timeout */ -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3_SHFT 63 -#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_OVERFLOW_1_ALIAS" */ -/* ni0 Error Overflow Bits Alias */ -/* ==================================================================== */ - -#define SH_NI0_ERROR_OVERFLOW_1_ALIAS 0x0000000150040528 - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_OVERFLOW_2" */ -/* ni0 Error Overflow Bits */ -/* ==================================================================== */ - -#define SH_NI0_ERROR_OVERFLOW_2 0x0000000150040530 -#define SH_NI0_ERROR_OVERFLOW_2_MASK 0x7fffffff003fffff -#define SH_NI0_ERROR_OVERFLOW_2_INIT 0x7fffffff003fffff - -/* SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCNI */ -/* Description: Illegal VC NI */ -#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCNI_SHFT 0 -#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCNI_MASK 0x0000000000000001 - -/* SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCPI */ -/* Description: Illegal VC PI */ -#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCPI_SHFT 1 -#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCPI_MASK 0x0000000000000002 - -/* SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCMD */ -/* Description: Illegal VC MD */ -#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCMD_SHFT 2 -#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCMD_MASK 0x0000000000000004 - -/* SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCIILB */ -/* Description: Illegal VC IILB */ -#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCIILB_SHFT 3 -#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCIILB_MASK 0x0000000000000008 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit underflow 0 */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit underflow 1 */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit underflow 2 */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit underflow 0 */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit underflow 1 */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit underflow 2 */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit underflow */ -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0 */ -/* Description: llp deadlock vc0 */ -#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0_SHFT 56 -#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1 */ -/* Description: llp deadlock vc1 */ -#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1_SHFT 57 -#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2 */ -/* Description: llp deadlock vc2 */ -#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2_SHFT 58 -#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3 */ -/* Description: llp deadlock vc3 */ -#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3_SHFT 59 -#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_CHIPLET_NOMATCH */ -/* Description: chiplet nomatch */ -#define SH_NI0_ERROR_OVERFLOW_2_CHIPLET_NOMATCH_SHFT 60 -#define SH_NI0_ERROR_OVERFLOW_2_CHIPLET_NOMATCH_MASK 0x1000000000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_NI0_ERROR_OVERFLOW_2_LUT_READ_ERROR_SHFT 61 -#define SH_NI0_ERROR_OVERFLOW_2_LUT_READ_ERROR_MASK 0x2000000000000000 - -/* SH_NI0_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR */ -/* Description: Retry Timeout Error */ -#define SH_NI0_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR_SHFT 62 -#define SH_NI0_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_OVERFLOW_2_ALIAS" */ -/* ni0 Error Overflow Bits Alias */ -/* ==================================================================== */ - -#define SH_NI0_ERROR_OVERFLOW_2_ALIAS 0x0000000150040538 - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_MASK_1" */ -/* ni0 Error Mask Bits */ -/* ==================================================================== */ - -#define SH_NI0_ERROR_MASK_1 0x0000000150040540 -#define SH_NI0_ERROR_MASK_1_MASK 0xffffffffffffffff -#define SH_NI0_ERROR_MASK_1_INIT 0xffffffffffffffff - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0 */ -/* Description: Fifo 02 debit0 overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2 */ -/* Description: Fifo 02 debit2 overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0 */ -/* Description: Fifo 13 debit0 overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2 */ -/* Description: Fifo 13 debit2 overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit overflow 0 */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI0_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit overflow 1 */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI0_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit overflow 2 */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI0_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit overflow 0 */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI0_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit overflow 1 */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI0_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit overflow 2 */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI0_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0 */ -/* Description: PI Fifo debit0 overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2 */ -/* Description: PI Fifo debit2 overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0 */ -/* Description: IILB Fifo debit0 overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2 */ -/* Description: IILB Fifo debit2 overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0 */ -/* Description: MD Fifo debit0 overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2 */ -/* Description: MD Fifo debit2 overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0 */ -/* Description: NI Fifo debit0 overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1 */ -/* Description: NI Fifo debit1 overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2 */ -/* Description: NI Fifo debit2 overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3 */ -/* Description: NI Fifo debit3 overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit overflow */ -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0 */ -/* Description: Fifo02 vc0 tail timeout */ -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56 -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000 - -/* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2 */ -/* Description: Fifo02 vc2 tail timeout */ -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57 -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000 - -/* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1 */ -/* Description: Fifo13 vc1 tail timeout */ -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58 -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000 - -/* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3 */ -/* Description: Fifo13 vc3 tail timeout */ -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59 -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000 - -/* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0 */ -/* Description: NI vc0 tail timeout */ -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0_SHFT 60 -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000 - -/* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1 */ -/* Description: NI vc1 tail timeout */ -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1_SHFT 61 -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000 - -/* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2 */ -/* Description: NI vc2 tail timeout */ -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2_SHFT 62 -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000 - -/* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3 */ -/* Description: NI vc3 tail timeout */ -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3_SHFT 63 -#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_MASK_2" */ -/* ni0 Error Mask Bits */ -/* ==================================================================== */ - -#define SH_NI0_ERROR_MASK_2 0x0000000150040550 -#define SH_NI0_ERROR_MASK_2_MASK 0x7fffffff003fffff -#define SH_NI0_ERROR_MASK_2_INIT 0x7fffffff003fffff - -/* SH_NI0_ERROR_MASK_2_ILLEGAL_VCNI */ -/* Description: Illegal VC NI */ -#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCNI_SHFT 0 -#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCNI_MASK 0x0000000000000001 - -/* SH_NI0_ERROR_MASK_2_ILLEGAL_VCPI */ -/* Description: Illegal VC PI */ -#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCPI_SHFT 1 -#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCPI_MASK 0x0000000000000002 - -/* SH_NI0_ERROR_MASK_2_ILLEGAL_VCMD */ -/* Description: Illegal VC MD */ -#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCMD_SHFT 2 -#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCMD_MASK 0x0000000000000004 - -/* SH_NI0_ERROR_MASK_2_ILLEGAL_VCIILB */ -/* Description: Illegal VC IILB */ -#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCIILB_SHFT 3 -#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCIILB_MASK 0x0000000000000008 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit underflow 0 */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit underflow 1 */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit underflow 2 */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit underflow 0 */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit underflow 1 */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit underflow 2 */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit underflow */ -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC0 */ -/* Description: llp deadlock vc0 */ -#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC0_SHFT 56 -#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000 - -/* SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC1 */ -/* Description: llp deadlock vc1 */ -#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC1_SHFT 57 -#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000 - -/* SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC2 */ -/* Description: llp deadlock vc2 */ -#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC2_SHFT 58 -#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000 - -/* SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC3 */ -/* Description: llp deadlock vc3 */ -#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC3_SHFT 59 -#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000 - -/* SH_NI0_ERROR_MASK_2_CHIPLET_NOMATCH */ -/* Description: chiplet nomatch */ -#define SH_NI0_ERROR_MASK_2_CHIPLET_NOMATCH_SHFT 60 -#define SH_NI0_ERROR_MASK_2_CHIPLET_NOMATCH_MASK 0x1000000000000000 - -/* SH_NI0_ERROR_MASK_2_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_NI0_ERROR_MASK_2_LUT_READ_ERROR_SHFT 61 -#define SH_NI0_ERROR_MASK_2_LUT_READ_ERROR_MASK 0x2000000000000000 - -/* SH_NI0_ERROR_MASK_2_RETRY_TIMEOUT_ERROR */ -/* Description: Retry Timeout Error */ -#define SH_NI0_ERROR_MASK_2_RETRY_TIMEOUT_ERROR_SHFT 62 -#define SH_NI0_ERROR_MASK_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI0_FIRST_ERROR_1" */ -/* ni0 First Error Bits */ -/* ==================================================================== */ - -#define SH_NI0_FIRST_ERROR_1 0x0000000150040560 -#define SH_NI0_FIRST_ERROR_1_MASK 0xffffffffffffffff -#define SH_NI0_FIRST_ERROR_1_INIT 0xffffffffffffffff - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0 */ -/* Description: Fifo 02 debit0 overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2 */ -/* Description: Fifo 02 debit2 overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0 */ -/* Description: Fifo 13 debit0 overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2 */ -/* Description: Fifo 13 debit2 overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit overflow 0 */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit overflow 1 */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit overflow 2 */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit overflow 0 */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit overflow 1 */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit overflow 2 */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0 */ -/* Description: PI Fifo debit0 overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2 */ -/* Description: PI Fifo debit2 overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0 */ -/* Description: IILB Fifo debit0 overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2 */ -/* Description: IILB Fifo debit2 overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0 */ -/* Description: MD Fifo debit0 overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2 */ -/* Description: MD Fifo debit2 overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0 */ -/* Description: NI Fifo debit0 overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1 */ -/* Description: NI Fifo debit1 overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2 */ -/* Description: NI Fifo debit2 overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3 */ -/* Description: NI Fifo debit3 overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit overflow */ -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0 */ -/* Description: Fifo02 vc0 tail timeout */ -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56 -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000 - -/* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2 */ -/* Description: Fifo02 vc2 tail timeout */ -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57 -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000 - -/* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1 */ -/* Description: Fifo13 vc1 tail timeout */ -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58 -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000 - -/* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3 */ -/* Description: Fifo13 vc3 tail timeout */ -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59 -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000 - -/* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0 */ -/* Description: NI vc0 tail timeout */ -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0_SHFT 60 -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000 - -/* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1 */ -/* Description: NI vc1 tail timeout */ -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1_SHFT 61 -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000 - -/* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2 */ -/* Description: NI vc2 tail timeout */ -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2_SHFT 62 -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000 - -/* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3 */ -/* Description: NI vc3 tail timeout */ -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3_SHFT 63 -#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI0_FIRST_ERROR_2" */ -/* ni0 First Error Bits */ -/* ==================================================================== */ - -#define SH_NI0_FIRST_ERROR_2 0x0000000150040570 -#define SH_NI0_FIRST_ERROR_2_MASK 0x7fffffff003fffff -#define SH_NI0_FIRST_ERROR_2_INIT 0x7fffffff003fffff - -/* SH_NI0_FIRST_ERROR_2_ILLEGAL_VCNI */ -/* Description: Illegal VC NI */ -#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCNI_SHFT 0 -#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCNI_MASK 0x0000000000000001 - -/* SH_NI0_FIRST_ERROR_2_ILLEGAL_VCPI */ -/* Description: Illegal VC PI */ -#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCPI_SHFT 1 -#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCPI_MASK 0x0000000000000002 - -/* SH_NI0_FIRST_ERROR_2_ILLEGAL_VCMD */ -/* Description: Illegal VC MD */ -#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCMD_SHFT 2 -#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCMD_MASK 0x0000000000000004 - -/* SH_NI0_FIRST_ERROR_2_ILLEGAL_VCIILB */ -/* Description: Illegal VC IILB */ -#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCIILB_SHFT 3 -#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCIILB_MASK 0x0000000000000008 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit underflow 0 */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit underflow 1 */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit underflow 2 */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit underflow 0 */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit underflow 1 */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit underflow 2 */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit underflow */ -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC0 */ -/* Description: llp deadlock vc0 */ -#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC0_SHFT 56 -#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000 - -/* SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC1 */ -/* Description: llp deadlock vc1 */ -#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC1_SHFT 57 -#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000 - -/* SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC2 */ -/* Description: llp deadlock vc2 */ -#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC2_SHFT 58 -#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000 - -/* SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC3 */ -/* Description: llp deadlock vc3 */ -#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC3_SHFT 59 -#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000 - -/* SH_NI0_FIRST_ERROR_2_CHIPLET_NOMATCH */ -/* Description: chiplet nomatch */ -#define SH_NI0_FIRST_ERROR_2_CHIPLET_NOMATCH_SHFT 60 -#define SH_NI0_FIRST_ERROR_2_CHIPLET_NOMATCH_MASK 0x1000000000000000 - -/* SH_NI0_FIRST_ERROR_2_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_NI0_FIRST_ERROR_2_LUT_READ_ERROR_SHFT 61 -#define SH_NI0_FIRST_ERROR_2_LUT_READ_ERROR_MASK 0x2000000000000000 - -/* SH_NI0_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR */ -/* Description: Retry Timeout Error */ -#define SH_NI0_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR_SHFT 62 -#define SH_NI0_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_DETAIL_1" */ -/* ni0 Chiplet no match header bits 63:0 */ -/* ==================================================================== */ - -#define SH_NI0_ERROR_DETAIL_1 0x0000000150040580 -#define SH_NI0_ERROR_DETAIL_1_MASK 0xffffffffffffffff -#define SH_NI0_ERROR_DETAIL_1_INIT 0x0000000000000000 - -/* SH_NI0_ERROR_DETAIL_1_HEADER */ -/* Description: Header bits 63:0 */ -#define SH_NI0_ERROR_DETAIL_1_HEADER_SHFT 0 -#define SH_NI0_ERROR_DETAIL_1_HEADER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_DETAIL_2" */ -/* ni0 Chiplet no match header bits 127:64 */ -/* ==================================================================== */ - -#define SH_NI0_ERROR_DETAIL_2 0x0000000150040590 -#define SH_NI0_ERROR_DETAIL_2_MASK 0xffffffffffffffff -#define SH_NI0_ERROR_DETAIL_2_INIT 0x0000000000000000 - -/* SH_NI0_ERROR_DETAIL_2_HEADER */ -/* Description: Header bits 127:64 */ -#define SH_NI0_ERROR_DETAIL_2_HEADER_SHFT 0 -#define SH_NI0_ERROR_DETAIL_2_HEADER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_SUMMARY_1" */ -/* ni1 Error Summary Bits */ -/* ==================================================================== */ - -#define SH_NI1_ERROR_SUMMARY_1 0x0000000150040600 -#define SH_NI1_ERROR_SUMMARY_1_MASK 0xffffffffffffffff -#define SH_NI1_ERROR_SUMMARY_1_INIT 0xffffffffffffffff - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0 */ -/* Description: Fifo 02 debit0 overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2 */ -/* Description: Fifo 02 debit2 overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0 */ -/* Description: Fifo 13 debit0 overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2 */ -/* Description: Fifo 13 debit2 overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit overflow 0 */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit overflow 1 */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit overflow 2 */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit overflow 0 */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit overflow 1 */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit overflow 2 */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0 */ -/* Description: PI Fifo debit0 overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2 */ -/* Description: PI Fifo debit2 overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0 */ -/* Description: IILB Fifo debit0 overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2 */ -/* Description: IILB Fifo debit2 overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0 */ -/* Description: MD Fifo debit0 overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2 */ -/* Description: MD Fifo debit2 overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0 */ -/* Description: NI Fifo debit0 overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1 */ -/* Description: NI Fifo debit1 overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2 */ -/* Description: NI Fifo debit2 overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3 */ -/* Description: NI Fifo debit3 overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit overflow */ -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0 */ -/* Description: Fifo02 vc0 tail timeout */ -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56 -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000 - -/* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2 */ -/* Description: Fifo02 vc2 tail timeout */ -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57 -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000 - -/* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1 */ -/* Description: Fifo13 vc1 tail timeout */ -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58 -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000 - -/* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3 */ -/* Description: Fifo13 vc3 tail timeout */ -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59 -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000 - -/* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0 */ -/* Description: NI vc0 tail timeout */ -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0_SHFT 60 -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000 - -/* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1 */ -/* Description: NI vc1 tail timeout */ -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1_SHFT 61 -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000 - -/* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2 */ -/* Description: NI vc2 tail timeout */ -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2_SHFT 62 -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000 - -/* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3 */ -/* Description: NI vc3 tail timeout */ -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3_SHFT 63 -#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_SUMMARY_1_ALIAS" */ -/* ni1 Error Summary Bits Alias */ -/* ==================================================================== */ - -#define SH_NI1_ERROR_SUMMARY_1_ALIAS 0x0000000150040608 - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_SUMMARY_2" */ -/* ni1 Error Summary Bits */ -/* ==================================================================== */ - -#define SH_NI1_ERROR_SUMMARY_2 0x0000000150040610 -#define SH_NI1_ERROR_SUMMARY_2_MASK 0x7fffffff003fffff -#define SH_NI1_ERROR_SUMMARY_2_INIT 0x7fffffff003fffff - -/* SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCNI */ -/* Description: Illegal VC NI */ -#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCNI_SHFT 0 -#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCNI_MASK 0x0000000000000001 - -/* SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCPI */ -/* Description: Illegal VC PI */ -#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCPI_SHFT 1 -#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCPI_MASK 0x0000000000000002 - -/* SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCMD */ -/* Description: Illegal VC MD */ -#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCMD_SHFT 2 -#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCMD_MASK 0x0000000000000004 - -/* SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCIILB */ -/* Description: Illegal VC IILB */ -#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCIILB_SHFT 3 -#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCIILB_MASK 0x0000000000000008 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit underflow 0 */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit underflow 1 */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit underflow 2 */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit underflow 0 */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit underflow 1 */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit underflow 2 */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit underflow */ -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0 */ -/* Description: llp deadlock vc0 */ -#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0_SHFT 56 -#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000 - -/* SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1 */ -/* Description: llp deadlock vc1 */ -#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1_SHFT 57 -#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000 - -/* SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2 */ -/* Description: llp deadlock vc2 */ -#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2_SHFT 58 -#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000 - -/* SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3 */ -/* Description: llp deadlock vc3 */ -#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3_SHFT 59 -#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000 - -/* SH_NI1_ERROR_SUMMARY_2_CHIPLET_NOMATCH */ -/* Description: chiplet nomatch */ -#define SH_NI1_ERROR_SUMMARY_2_CHIPLET_NOMATCH_SHFT 60 -#define SH_NI1_ERROR_SUMMARY_2_CHIPLET_NOMATCH_MASK 0x1000000000000000 - -/* SH_NI1_ERROR_SUMMARY_2_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_NI1_ERROR_SUMMARY_2_LUT_READ_ERROR_SHFT 61 -#define SH_NI1_ERROR_SUMMARY_2_LUT_READ_ERROR_MASK 0x2000000000000000 - -/* SH_NI1_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR */ -/* Description: Retry Timeout Error */ -#define SH_NI1_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR_SHFT 62 -#define SH_NI1_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_SUMMARY_2_ALIAS" */ -/* ni1 Error Summary Bits Alias */ -/* ==================================================================== */ - -#define SH_NI1_ERROR_SUMMARY_2_ALIAS 0x0000000150040618 - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_OVERFLOW_1" */ -/* ni1 Error Overflow Bits */ -/* ==================================================================== */ - -#define SH_NI1_ERROR_OVERFLOW_1 0x0000000150040620 -#define SH_NI1_ERROR_OVERFLOW_1_MASK 0xffffffffffffffff -#define SH_NI1_ERROR_OVERFLOW_1_INIT 0xffffffffffffffff - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0 */ -/* Description: Fifo 02 debit0 overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2 */ -/* Description: Fifo 02 debit2 overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0 */ -/* Description: Fifo 13 debit0 overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2 */ -/* Description: Fifo 13 debit2 overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit overflow 0 */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit overflow 1 */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit overflow 2 */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit overflow 0 */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit overflow 1 */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit overflow 2 */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0 */ -/* Description: PI Fifo debit0 overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2 */ -/* Description: PI Fifo debit2 overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0 */ -/* Description: IILB Fifo debit0 overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2 */ -/* Description: IILB Fifo debit2 overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0 */ -/* Description: MD Fifo debit0 overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2 */ -/* Description: MD Fifo debit2 overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0 */ -/* Description: NI Fifo debit0 overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1 */ -/* Description: NI Fifo debit1 overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2 */ -/* Description: NI Fifo debit2 overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3 */ -/* Description: NI Fifo debit3 overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit overflow */ -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0 */ -/* Description: Fifo02 vc0 tail timeout */ -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56 -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2 */ -/* Description: Fifo02 vc2 tail timeout */ -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57 -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1 */ -/* Description: Fifo13 vc1 tail timeout */ -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58 -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3 */ -/* Description: Fifo13 vc3 tail timeout */ -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59 -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0 */ -/* Description: NI vc0 tail timeout */ -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0_SHFT 60 -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1 */ -/* Description: NI vc1 tail timeout */ -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1_SHFT 61 -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2 */ -/* Description: NI vc2 tail timeout */ -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2_SHFT 62 -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000 - -/* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3 */ -/* Description: NI vc3 tail timeout */ -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3_SHFT 63 -#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_OVERFLOW_1_ALIAS" */ -/* ni1 Error Overflow Bits Alias */ -/* ==================================================================== */ - -#define SH_NI1_ERROR_OVERFLOW_1_ALIAS 0x0000000150040628 - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_OVERFLOW_2" */ -/* ni1 Error Overflow Bits */ -/* ==================================================================== */ - -#define SH_NI1_ERROR_OVERFLOW_2 0x0000000150040630 -#define SH_NI1_ERROR_OVERFLOW_2_MASK 0x7fffffff003fffff -#define SH_NI1_ERROR_OVERFLOW_2_INIT 0x7fffffff003fffff - -/* SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCNI */ -/* Description: Illegal VC NI */ -#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCNI_SHFT 0 -#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCNI_MASK 0x0000000000000001 - -/* SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCPI */ -/* Description: Illegal VC PI */ -#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCPI_SHFT 1 -#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCPI_MASK 0x0000000000000002 - -/* SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCMD */ -/* Description: Illegal VC MD */ -#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCMD_SHFT 2 -#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCMD_MASK 0x0000000000000004 - -/* SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCIILB */ -/* Description: Illegal VC IILB */ -#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCIILB_SHFT 3 -#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCIILB_MASK 0x0000000000000008 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit underflow 0 */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit underflow 1 */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit underflow 2 */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit underflow 0 */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit underflow 1 */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit underflow 2 */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit underflow */ -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0 */ -/* Description: llp deadlock vc0 */ -#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0_SHFT 56 -#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1 */ -/* Description: llp deadlock vc1 */ -#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1_SHFT 57 -#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2 */ -/* Description: llp deadlock vc2 */ -#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2_SHFT 58 -#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3 */ -/* Description: llp deadlock vc3 */ -#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3_SHFT 59 -#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_CHIPLET_NOMATCH */ -/* Description: chiplet nomatch */ -#define SH_NI1_ERROR_OVERFLOW_2_CHIPLET_NOMATCH_SHFT 60 -#define SH_NI1_ERROR_OVERFLOW_2_CHIPLET_NOMATCH_MASK 0x1000000000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_NI1_ERROR_OVERFLOW_2_LUT_READ_ERROR_SHFT 61 -#define SH_NI1_ERROR_OVERFLOW_2_LUT_READ_ERROR_MASK 0x2000000000000000 - -/* SH_NI1_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR */ -/* Description: Retry Timeout Error */ -#define SH_NI1_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR_SHFT 62 -#define SH_NI1_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_OVERFLOW_2_ALIAS" */ -/* ni1 Error Overflow Bits Alias */ -/* ==================================================================== */ - -#define SH_NI1_ERROR_OVERFLOW_2_ALIAS 0x0000000150040638 - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_MASK_1" */ -/* ni1 Error Mask Bits */ -/* ==================================================================== */ - -#define SH_NI1_ERROR_MASK_1 0x0000000150040640 -#define SH_NI1_ERROR_MASK_1_MASK 0xffffffffffffffff -#define SH_NI1_ERROR_MASK_1_INIT 0xffffffffffffffff - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0 */ -/* Description: Fifo 02 debit0 overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2 */ -/* Description: Fifo 02 debit2 overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0 */ -/* Description: Fifo 13 debit0 overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2 */ -/* Description: Fifo 13 debit2 overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit overflow 0 */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI1_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit overflow 1 */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI1_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit overflow 2 */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI1_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit overflow 0 */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI1_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit overflow 1 */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI1_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit overflow 2 */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI1_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0 */ -/* Description: PI Fifo debit0 overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2 */ -/* Description: PI Fifo debit2 overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0 */ -/* Description: IILB Fifo debit0 overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2 */ -/* Description: IILB Fifo debit2 overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0 */ -/* Description: MD Fifo debit0 overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2 */ -/* Description: MD Fifo debit2 overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0 */ -/* Description: NI Fifo debit0 overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1 */ -/* Description: NI Fifo debit1 overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2 */ -/* Description: NI Fifo debit2 overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3 */ -/* Description: NI Fifo debit3 overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit overflow */ -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0 */ -/* Description: Fifo02 vc0 tail timeout */ -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56 -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000 - -/* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2 */ -/* Description: Fifo02 vc2 tail timeout */ -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57 -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000 - -/* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1 */ -/* Description: Fifo13 vc1 tail timeout */ -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58 -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000 - -/* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3 */ -/* Description: Fifo13 vc3 tail timeout */ -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59 -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000 - -/* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0 */ -/* Description: NI vc0 tail timeout */ -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0_SHFT 60 -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000 - -/* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1 */ -/* Description: NI vc1 tail timeout */ -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1_SHFT 61 -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000 - -/* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2 */ -/* Description: NI vc2 tail timeout */ -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2_SHFT 62 -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000 - -/* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3 */ -/* Description: NI vc3 tail timeout */ -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3_SHFT 63 -#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_MASK_2" */ -/* ni1 Error Mask Bits */ -/* ==================================================================== */ - -#define SH_NI1_ERROR_MASK_2 0x0000000150040650 -#define SH_NI1_ERROR_MASK_2_MASK 0x7fffffff003fffff -#define SH_NI1_ERROR_MASK_2_INIT 0x7fffffff003fffff - -/* SH_NI1_ERROR_MASK_2_ILLEGAL_VCNI */ -/* Description: Illegal VC NI */ -#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCNI_SHFT 0 -#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCNI_MASK 0x0000000000000001 - -/* SH_NI1_ERROR_MASK_2_ILLEGAL_VCPI */ -/* Description: Illegal VC PI */ -#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCPI_SHFT 1 -#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCPI_MASK 0x0000000000000002 - -/* SH_NI1_ERROR_MASK_2_ILLEGAL_VCMD */ -/* Description: Illegal VC MD */ -#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCMD_SHFT 2 -#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCMD_MASK 0x0000000000000004 - -/* SH_NI1_ERROR_MASK_2_ILLEGAL_VCIILB */ -/* Description: Illegal VC IILB */ -#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCIILB_SHFT 3 -#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCIILB_MASK 0x0000000000000008 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit underflow 0 */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit underflow 1 */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit underflow 2 */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit underflow 0 */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit underflow 1 */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit underflow 2 */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit underflow */ -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC0 */ -/* Description: llp deadlock vc0 */ -#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC0_SHFT 56 -#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000 - -/* SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC1 */ -/* Description: llp deadlock vc1 */ -#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC1_SHFT 57 -#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000 - -/* SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC2 */ -/* Description: llp deadlock vc2 */ -#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC2_SHFT 58 -#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000 - -/* SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC3 */ -/* Description: llp deadlock vc3 */ -#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC3_SHFT 59 -#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000 - -/* SH_NI1_ERROR_MASK_2_CHIPLET_NOMATCH */ -/* Description: chiplet nomatch */ -#define SH_NI1_ERROR_MASK_2_CHIPLET_NOMATCH_SHFT 60 -#define SH_NI1_ERROR_MASK_2_CHIPLET_NOMATCH_MASK 0x1000000000000000 - -/* SH_NI1_ERROR_MASK_2_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_NI1_ERROR_MASK_2_LUT_READ_ERROR_SHFT 61 -#define SH_NI1_ERROR_MASK_2_LUT_READ_ERROR_MASK 0x2000000000000000 - -/* SH_NI1_ERROR_MASK_2_RETRY_TIMEOUT_ERROR */ -/* Description: Retry Timeout Error */ -#define SH_NI1_ERROR_MASK_2_RETRY_TIMEOUT_ERROR_SHFT 62 -#define SH_NI1_ERROR_MASK_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI1_FIRST_ERROR_1" */ -/* ni1 First Error Bits */ -/* ==================================================================== */ - -#define SH_NI1_FIRST_ERROR_1 0x0000000150040660 -#define SH_NI1_FIRST_ERROR_1_MASK 0xffffffffffffffff -#define SH_NI1_FIRST_ERROR_1_INIT 0xffffffffffffffff - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0 */ -/* Description: Fifo 02 debit0 overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2 */ -/* Description: Fifo 02 debit2 overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0 */ -/* Description: Fifo 13 debit0 overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2 */ -/* Description: Fifo 13 debit2 overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit overflow 0 */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit overflow 1 */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit overflow 2 */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit overflow 0 */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit overflow 1 */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit overflow 2 */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0 */ -/* Description: PI Fifo debit0 overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2 */ -/* Description: PI Fifo debit2 overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0 */ -/* Description: IILB Fifo debit0 overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2 */ -/* Description: IILB Fifo debit2 overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0 */ -/* Description: MD Fifo debit0 overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2 */ -/* Description: MD Fifo debit2 overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0 */ -/* Description: NI Fifo debit0 overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1 */ -/* Description: NI Fifo debit1 overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2 */ -/* Description: NI Fifo debit2 overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3 */ -/* Description: NI Fifo debit3 overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit overflow */ -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0 */ -/* Description: Fifo02 vc0 tail timeout */ -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56 -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000 - -/* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2 */ -/* Description: Fifo02 vc2 tail timeout */ -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57 -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000 - -/* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1 */ -/* Description: Fifo13 vc1 tail timeout */ -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58 -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000 - -/* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3 */ -/* Description: Fifo13 vc3 tail timeout */ -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59 -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000 - -/* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0 */ -/* Description: NI vc0 tail timeout */ -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0_SHFT 60 -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000 - -/* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1 */ -/* Description: NI vc1 tail timeout */ -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1_SHFT 61 -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000 - -/* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2 */ -/* Description: NI vc2 tail timeout */ -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2_SHFT 62 -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000 - -/* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3 */ -/* Description: NI vc3 tail timeout */ -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3_SHFT 63 -#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI1_FIRST_ERROR_2" */ -/* ni1 First Error Bits */ -/* ==================================================================== */ - -#define SH_NI1_FIRST_ERROR_2 0x0000000150040670 -#define SH_NI1_FIRST_ERROR_2_MASK 0x7fffffff003fffff -#define SH_NI1_FIRST_ERROR_2_INIT 0x7fffffff003fffff - -/* SH_NI1_FIRST_ERROR_2_ILLEGAL_VCNI */ -/* Description: Illegal VC NI */ -#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCNI_SHFT 0 -#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCNI_MASK 0x0000000000000001 - -/* SH_NI1_FIRST_ERROR_2_ILLEGAL_VCPI */ -/* Description: Illegal VC PI */ -#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCPI_SHFT 1 -#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCPI_MASK 0x0000000000000002 - -/* SH_NI1_FIRST_ERROR_2_ILLEGAL_VCMD */ -/* Description: Illegal VC MD */ -#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCMD_SHFT 2 -#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCMD_MASK 0x0000000000000004 - -/* SH_NI1_FIRST_ERROR_2_ILLEGAL_VCIILB */ -/* Description: Illegal VC IILB */ -#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCIILB_SHFT 3 -#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCIILB_MASK 0x0000000000000008 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP */ -/* Description: Fifo 02 vc0 pop underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP */ -/* Description: Fifo 02 vc2 pop underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP */ -/* Description: Fifo 13 vc1 pop underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP */ -/* Description: Fifo 13 vc3 pop underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH */ -/* Description: Fifo 02 vc0 push underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH */ -/* Description: Fifo 02 vc2 push underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH */ -/* Description: Fifo 13 vc1 push underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH */ -/* Description: Fifo 13 vc3 push underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT */ -/* Description: Fifo 02 vc0 credit underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT */ -/* Description: Fifo 02 vc2 credit underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT */ -/* Description: Fifo 13 vc0 credit underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT */ -/* Description: Fifo 13 vc2 credit underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT */ -/* Description: VC0 credit underflow 0 */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT_SHFT 16 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT */ -/* Description: VC0 credit underflow 1 */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT_SHFT 17 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT */ -/* Description: VC0 credit underflow 2 */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT_SHFT 18 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT */ -/* Description: VC2 credit underflow 0 */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT_SHFT 19 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT */ -/* Description: VC2 credit underflow 1 */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT_SHFT 20 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT */ -/* Description: VC2 credit underflow 2 */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT_SHFT 21 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP */ -/* Description: PI Fifo vc0 pop underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP */ -/* Description: PI Fifo vc2 pop underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP */ -/* Description: IILB Fifo vc0 pop underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP */ -/* Description: IILB Fifo vc2 pop underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP */ -/* Description: MD Fifo vc0 pop underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP */ -/* Description: MD Fifo vc2 pop underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP */ -/* Description: NI Fifo vc0 pop underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP */ -/* Description: NI Fifo vc2 pop underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH */ -/* Description: PI Fifo vc0 push underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH */ -/* Description: PI Fifo vc2 push underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */ -/* Description: IILB Fifo vc0 push underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */ -/* Description: IILB Fifo vc2 push underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH */ -/* Description: MD Fifo vc0 push underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH */ -/* Description: MD Fifo vc2 push underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */ -/* Description: PI Fifo vc0 credit underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */ -/* Description: PI Fifo vc2 credit underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */ -/* Description: IILB Fifo vc0 credit underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */ -/* Description: IILB Fifo vc2 credit underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */ -/* Description: MD Fifo vc0 credit underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */ -/* Description: MD Fifo vc2 credit underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */ -/* Description: NI Fifo vc0 credit underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */ -/* Description: NI Fifo vc1 credit underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */ -/* Description: NI Fifo vc2 credit underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 - -/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */ -/* Description: NI Fifo vc3 credit underflow */ -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 -#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 - -/* SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC0 */ -/* Description: llp deadlock vc0 */ -#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC0_SHFT 56 -#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000 - -/* SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC1 */ -/* Description: llp deadlock vc1 */ -#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC1_SHFT 57 -#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000 - -/* SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC2 */ -/* Description: llp deadlock vc2 */ -#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC2_SHFT 58 -#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000 - -/* SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC3 */ -/* Description: llp deadlock vc3 */ -#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC3_SHFT 59 -#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000 - -/* SH_NI1_FIRST_ERROR_2_CHIPLET_NOMATCH */ -/* Description: chiplet nomatch */ -#define SH_NI1_FIRST_ERROR_2_CHIPLET_NOMATCH_SHFT 60 -#define SH_NI1_FIRST_ERROR_2_CHIPLET_NOMATCH_MASK 0x1000000000000000 - -/* SH_NI1_FIRST_ERROR_2_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_NI1_FIRST_ERROR_2_LUT_READ_ERROR_SHFT 61 -#define SH_NI1_FIRST_ERROR_2_LUT_READ_ERROR_MASK 0x2000000000000000 - -/* SH_NI1_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR */ -/* Description: Retry Timeout Error */ -#define SH_NI1_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR_SHFT 62 -#define SH_NI1_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000 - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_DETAIL_1" */ -/* ni1 Chiplet no match header bits 63:0 */ -/* ==================================================================== */ - -#define SH_NI1_ERROR_DETAIL_1 0x0000000150040680 -#define SH_NI1_ERROR_DETAIL_1_MASK 0xffffffffffffffff -#define SH_NI1_ERROR_DETAIL_1_INIT 0x0000000000000000 - -/* SH_NI1_ERROR_DETAIL_1_HEADER */ -/* Description: Header bits 63:0 */ -#define SH_NI1_ERROR_DETAIL_1_HEADER_SHFT 0 -#define SH_NI1_ERROR_DETAIL_1_HEADER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_DETAIL_2" */ -/* ni1 Chiplet no match header bits 127:64 */ -/* ==================================================================== */ - -#define SH_NI1_ERROR_DETAIL_2 0x0000000150040690 -#define SH_NI1_ERROR_DETAIL_2_MASK 0xffffffffffffffff -#define SH_NI1_ERROR_DETAIL_2_INIT 0x0000000000000000 - -/* SH_NI1_ERROR_DETAIL_2_HEADER */ -/* Description: Header bits 127:64 */ -#define SH_NI1_ERROR_DETAIL_2_HEADER_SHFT 0 -#define SH_NI1_ERROR_DETAIL_2_HEADER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_CORRECTED_DETAIL_1" */ -/* Corrected error details */ -/* ==================================================================== */ - -#define SH_XN_CORRECTED_DETAIL_1 0x0000000150040070 -#define SH_XN_CORRECTED_DETAIL_1_MASK 0x0fff0fff0fff0fff -#define SH_XN_CORRECTED_DETAIL_1_INIT 0x0000000000000000 - -/* SH_XN_CORRECTED_DETAIL_1_ECC0_SYNDROME */ -/* Description: ECC0 Syndrome */ -#define SH_XN_CORRECTED_DETAIL_1_ECC0_SYNDROME_SHFT 0 -#define SH_XN_CORRECTED_DETAIL_1_ECC0_SYNDROME_MASK 0x00000000000000ff - -/* SH_XN_CORRECTED_DETAIL_1_ECC0_WC */ -/* Description: ECC0 Word Count */ -#define SH_XN_CORRECTED_DETAIL_1_ECC0_WC_SHFT 8 -#define SH_XN_CORRECTED_DETAIL_1_ECC0_WC_MASK 0x0000000000000300 - -/* SH_XN_CORRECTED_DETAIL_1_ECC0_VC */ -/* Description: ECC0 Virtual Channel */ -#define SH_XN_CORRECTED_DETAIL_1_ECC0_VC_SHFT 10 -#define SH_XN_CORRECTED_DETAIL_1_ECC0_VC_MASK 0x0000000000000c00 - -/* SH_XN_CORRECTED_DETAIL_1_ECC1_SYNDROME */ -/* Description: ECC1 Syndrome */ -#define SH_XN_CORRECTED_DETAIL_1_ECC1_SYNDROME_SHFT 16 -#define SH_XN_CORRECTED_DETAIL_1_ECC1_SYNDROME_MASK 0x0000000000ff0000 - -/* SH_XN_CORRECTED_DETAIL_1_ECC1_WC */ -/* Description: ECC1 Word Count */ -#define SH_XN_CORRECTED_DETAIL_1_ECC1_WC_SHFT 24 -#define SH_XN_CORRECTED_DETAIL_1_ECC1_WC_MASK 0x0000000003000000 - -/* SH_XN_CORRECTED_DETAIL_1_ECC1_VC */ -/* Description: ECC1 Virtual Channel */ -#define SH_XN_CORRECTED_DETAIL_1_ECC1_VC_SHFT 26 -#define SH_XN_CORRECTED_DETAIL_1_ECC1_VC_MASK 0x000000000c000000 - -/* SH_XN_CORRECTED_DETAIL_1_ECC2_SYNDROME */ -/* Description: ECC2 Syndrome */ -#define SH_XN_CORRECTED_DETAIL_1_ECC2_SYNDROME_SHFT 32 -#define SH_XN_CORRECTED_DETAIL_1_ECC2_SYNDROME_MASK 0x000000ff00000000 - -/* SH_XN_CORRECTED_DETAIL_1_ECC2_WC */ -/* Description: ECC2 Word Count */ -#define SH_XN_CORRECTED_DETAIL_1_ECC2_WC_SHFT 40 -#define SH_XN_CORRECTED_DETAIL_1_ECC2_WC_MASK 0x0000030000000000 - -/* SH_XN_CORRECTED_DETAIL_1_ECC2_VC */ -/* Description: ECC2 Virtual Channel */ -#define SH_XN_CORRECTED_DETAIL_1_ECC2_VC_SHFT 42 -#define SH_XN_CORRECTED_DETAIL_1_ECC2_VC_MASK 0x00000c0000000000 - -/* SH_XN_CORRECTED_DETAIL_1_ECC3_SYNDROME */ -/* Description: ECC3 Syndrome */ -#define SH_XN_CORRECTED_DETAIL_1_ECC3_SYNDROME_SHFT 48 -#define SH_XN_CORRECTED_DETAIL_1_ECC3_SYNDROME_MASK 0x00ff000000000000 - -/* SH_XN_CORRECTED_DETAIL_1_ECC3_WC */ -/* Description: ECC3 Word Count */ -#define SH_XN_CORRECTED_DETAIL_1_ECC3_WC_SHFT 56 -#define SH_XN_CORRECTED_DETAIL_1_ECC3_WC_MASK 0x0300000000000000 - -/* SH_XN_CORRECTED_DETAIL_1_ECC3_VC */ -/* Description: ECC3 Virtual Channel */ -#define SH_XN_CORRECTED_DETAIL_1_ECC3_VC_SHFT 58 -#define SH_XN_CORRECTED_DETAIL_1_ECC3_VC_MASK 0x0c00000000000000 - -/* ==================================================================== */ -/* Register "SH_XN_CORRECTED_DETAIL_2" */ -/* Corrected error data */ -/* ==================================================================== */ - -#define SH_XN_CORRECTED_DETAIL_2 0x0000000150040080 -#define SH_XN_CORRECTED_DETAIL_2_MASK 0xffffffffffffffff -#define SH_XN_CORRECTED_DETAIL_2_INIT 0x0000000000000000 - -/* SH_XN_CORRECTED_DETAIL_2_DATA */ -/* Description: ECC data */ -#define SH_XN_CORRECTED_DETAIL_2_DATA_SHFT 0 -#define SH_XN_CORRECTED_DETAIL_2_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_CORRECTED_DETAIL_3" */ -/* Corrected error header0 */ -/* ==================================================================== */ - -#define SH_XN_CORRECTED_DETAIL_3 0x0000000150040090 -#define SH_XN_CORRECTED_DETAIL_3_MASK 0xffffffffffffffff -#define SH_XN_CORRECTED_DETAIL_3_INIT 0x0000000000000000 - -/* SH_XN_CORRECTED_DETAIL_3_HEADER0 */ -/* Description: ECC header0 (bits 63 - 0) */ -#define SH_XN_CORRECTED_DETAIL_3_HEADER0_SHFT 0 -#define SH_XN_CORRECTED_DETAIL_3_HEADER0_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_CORRECTED_DETAIL_4" */ -/* Corrected error header1 */ -/* ==================================================================== */ - -#define SH_XN_CORRECTED_DETAIL_4 0x00000001500400a0 -#define SH_XN_CORRECTED_DETAIL_4_MASK 0xc00003ffffffffff -#define SH_XN_CORRECTED_DETAIL_4_INIT 0x0000000000000000 - -/* SH_XN_CORRECTED_DETAIL_4_HEADER1 */ -/* Description: ECC header1 (bits 104 - 64) */ -#define SH_XN_CORRECTED_DETAIL_4_HEADER1_SHFT 0 -#define SH_XN_CORRECTED_DETAIL_4_HEADER1_MASK 0x000003ffffffffff - -/* SH_XN_CORRECTED_DETAIL_4_ERR_GROUP */ -/* Description: Error group */ -#define SH_XN_CORRECTED_DETAIL_4_ERR_GROUP_SHFT 62 -#define SH_XN_CORRECTED_DETAIL_4_ERR_GROUP_MASK 0xc000000000000000 - -/* ==================================================================== */ -/* Register "SH_XN_UNCORRECTED_DETAIL_1" */ -/* Uncorrected error details */ -/* ==================================================================== */ - -#define SH_XN_UNCORRECTED_DETAIL_1 0x00000001500400b0 -#define SH_XN_UNCORRECTED_DETAIL_1_MASK 0x0fff0fff0fff0fff -#define SH_XN_UNCORRECTED_DETAIL_1_INIT 0x0000000000000000 - -/* SH_XN_UNCORRECTED_DETAIL_1_ECC0_SYNDROME */ -/* Description: ECC0 Syndrome */ -#define SH_XN_UNCORRECTED_DETAIL_1_ECC0_SYNDROME_SHFT 0 -#define SH_XN_UNCORRECTED_DETAIL_1_ECC0_SYNDROME_MASK 0x00000000000000ff - -/* SH_XN_UNCORRECTED_DETAIL_1_ECC0_WC */ -/* Description: ECC0 Word Count */ -#define SH_XN_UNCORRECTED_DETAIL_1_ECC0_WC_SHFT 8 -#define SH_XN_UNCORRECTED_DETAIL_1_ECC0_WC_MASK 0x0000000000000300 - -/* SH_XN_UNCORRECTED_DETAIL_1_ECC0_VC */ -/* Description: ECC0 Virtual Channel */ -#define SH_XN_UNCORRECTED_DETAIL_1_ECC0_VC_SHFT 10 -#define SH_XN_UNCORRECTED_DETAIL_1_ECC0_VC_MASK 0x0000000000000c00 - -/* SH_XN_UNCORRECTED_DETAIL_1_ECC1_SYNDROME */ -/* Description: ECC1 Syndrome */ -#define SH_XN_UNCORRECTED_DETAIL_1_ECC1_SYNDROME_SHFT 16 -#define SH_XN_UNCORRECTED_DETAIL_1_ECC1_SYNDROME_MASK 0x0000000000ff0000 - -/* SH_XN_UNCORRECTED_DETAIL_1_ECC1_WC */ -/* Description: ECC1 Word Count */ -#define SH_XN_UNCORRECTED_DETAIL_1_ECC1_WC_SHFT 24 -#define SH_XN_UNCORRECTED_DETAIL_1_ECC1_WC_MASK 0x0000000003000000 - -/* SH_XN_UNCORRECTED_DETAIL_1_ECC1_VC */ -/* Description: ECC1 Virtual Channel */ -#define SH_XN_UNCORRECTED_DETAIL_1_ECC1_VC_SHFT 26 -#define SH_XN_UNCORRECTED_DETAIL_1_ECC1_VC_MASK 0x000000000c000000 - -/* SH_XN_UNCORRECTED_DETAIL_1_ECC2_SYNDROME */ -/* Description: ECC2 Syndrome */ -#define SH_XN_UNCORRECTED_DETAIL_1_ECC2_SYNDROME_SHFT 32 -#define SH_XN_UNCORRECTED_DETAIL_1_ECC2_SYNDROME_MASK 0x000000ff00000000 - -/* SH_XN_UNCORRECTED_DETAIL_1_ECC2_WC */ -/* Description: ECC2 Word Count */ -#define SH_XN_UNCORRECTED_DETAIL_1_ECC2_WC_SHFT 40 -#define SH_XN_UNCORRECTED_DETAIL_1_ECC2_WC_MASK 0x0000030000000000 - -/* SH_XN_UNCORRECTED_DETAIL_1_ECC2_VC */ -/* Description: ECC2 Virtual Channel */ -#define SH_XN_UNCORRECTED_DETAIL_1_ECC2_VC_SHFT 42 -#define SH_XN_UNCORRECTED_DETAIL_1_ECC2_VC_MASK 0x00000c0000000000 - -/* SH_XN_UNCORRECTED_DETAIL_1_ECC3_SYNDROME */ -/* Description: ECC3 Syndrome */ -#define SH_XN_UNCORRECTED_DETAIL_1_ECC3_SYNDROME_SHFT 48 -#define SH_XN_UNCORRECTED_DETAIL_1_ECC3_SYNDROME_MASK 0x00ff000000000000 - -/* SH_XN_UNCORRECTED_DETAIL_1_ECC3_WC */ -/* Description: ECC3 Word Count */ -#define SH_XN_UNCORRECTED_DETAIL_1_ECC3_WC_SHFT 56 -#define SH_XN_UNCORRECTED_DETAIL_1_ECC3_WC_MASK 0x0300000000000000 - -/* SH_XN_UNCORRECTED_DETAIL_1_ECC3_VC */ -/* Description: ECC3 Virtual Channel */ -#define SH_XN_UNCORRECTED_DETAIL_1_ECC3_VC_SHFT 58 -#define SH_XN_UNCORRECTED_DETAIL_1_ECC3_VC_MASK 0x0c00000000000000 - -/* ==================================================================== */ -/* Register "SH_XN_UNCORRECTED_DETAIL_2" */ -/* Uncorrected error data */ -/* ==================================================================== */ - -#define SH_XN_UNCORRECTED_DETAIL_2 0x00000001500400c0 -#define SH_XN_UNCORRECTED_DETAIL_2_MASK 0xffffffffffffffff -#define SH_XN_UNCORRECTED_DETAIL_2_INIT 0x0000000000000000 - -/* SH_XN_UNCORRECTED_DETAIL_2_DATA */ -/* Description: ECC data */ -#define SH_XN_UNCORRECTED_DETAIL_2_DATA_SHFT 0 -#define SH_XN_UNCORRECTED_DETAIL_2_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_UNCORRECTED_DETAIL_3" */ -/* Uncorrected error header0 */ -/* ==================================================================== */ - -#define SH_XN_UNCORRECTED_DETAIL_3 0x00000001500400d0 -#define SH_XN_UNCORRECTED_DETAIL_3_MASK 0xffffffffffffffff -#define SH_XN_UNCORRECTED_DETAIL_3_INIT 0x0000000000000000 - -/* SH_XN_UNCORRECTED_DETAIL_3_HEADER0 */ -/* Description: ECC header0 (bits 63 - 0) */ -#define SH_XN_UNCORRECTED_DETAIL_3_HEADER0_SHFT 0 -#define SH_XN_UNCORRECTED_DETAIL_3_HEADER0_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XN_UNCORRECTED_DETAIL_4" */ -/* Uncorrected error header1 */ -/* ==================================================================== */ - -#define SH_XN_UNCORRECTED_DETAIL_4 0x00000001500400e0 -#define SH_XN_UNCORRECTED_DETAIL_4_MASK 0xc00003ffffffffff -#define SH_XN_UNCORRECTED_DETAIL_4_INIT 0x0000000000000000 - -/* SH_XN_UNCORRECTED_DETAIL_4_HEADER1 */ -/* Description: ECC header1 (bits 104 - 64) */ -#define SH_XN_UNCORRECTED_DETAIL_4_HEADER1_SHFT 0 -#define SH_XN_UNCORRECTED_DETAIL_4_HEADER1_MASK 0x000003ffffffffff - -/* SH_XN_UNCORRECTED_DETAIL_4_ERR_GROUP */ -/* Description: Error group */ -#define SH_XN_UNCORRECTED_DETAIL_4_ERR_GROUP_SHFT 62 -#define SH_XN_UNCORRECTED_DETAIL_4_ERR_GROUP_MASK 0xc000000000000000 - -/* ==================================================================== */ -/* Register "SH_XNMD_ERROR_DETAIL_1" */ -/* Look Up Table Address (md) */ -/* ==================================================================== */ - -#define SH_XNMD_ERROR_DETAIL_1 0x00000001500400f0 -#define SH_XNMD_ERROR_DETAIL_1_MASK 0x00000000000007ff -#define SH_XNMD_ERROR_DETAIL_1_INIT 0x0000000000000000 - -/* SH_XNMD_ERROR_DETAIL_1_LUT_ADDR */ -/* Description: Look Up Table Read Address */ -#define SH_XNMD_ERROR_DETAIL_1_LUT_ADDR_SHFT 0 -#define SH_XNMD_ERROR_DETAIL_1_LUT_ADDR_MASK 0x00000000000007ff - -/* ==================================================================== */ -/* Register "SH_XNPI_ERROR_DETAIL_1" */ -/* Look Up Table Address (pi) */ -/* ==================================================================== */ - -#define SH_XNPI_ERROR_DETAIL_1 0x0000000150040100 -#define SH_XNPI_ERROR_DETAIL_1_MASK 0x00000000000007ff -#define SH_XNPI_ERROR_DETAIL_1_INIT 0x0000000000000000 - -/* SH_XNPI_ERROR_DETAIL_1_LUT_ADDR */ -/* Description: Look Up Table Read Address */ -#define SH_XNPI_ERROR_DETAIL_1_LUT_ADDR_SHFT 0 -#define SH_XNPI_ERROR_DETAIL_1_LUT_ADDR_MASK 0x00000000000007ff - -/* ==================================================================== */ -/* Register "SH_XNIILB_ERROR_DETAIL_1" */ -/* Chiplet NoMatch header [63:0] */ -/* ==================================================================== */ - -#define SH_XNIILB_ERROR_DETAIL_1 0x0000000150040110 -#define SH_XNIILB_ERROR_DETAIL_1_MASK 0xffffffffffffffff -#define SH_XNIILB_ERROR_DETAIL_1_INIT 0x0000000000000000 - -/* SH_XNIILB_ERROR_DETAIL_1_HEADER */ -/* Description: header bits [63:0] */ -#define SH_XNIILB_ERROR_DETAIL_1_HEADER_SHFT 0 -#define SH_XNIILB_ERROR_DETAIL_1_HEADER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XNIILB_ERROR_DETAIL_2" */ -/* Chiplet NoMatch header [127:64] */ -/* ==================================================================== */ - -#define SH_XNIILB_ERROR_DETAIL_2 0x0000000150040120 -#define SH_XNIILB_ERROR_DETAIL_2_MASK 0xffffffffffffffff -#define SH_XNIILB_ERROR_DETAIL_2_INIT 0x0000000000000000 - -/* SH_XNIILB_ERROR_DETAIL_2_HEADER */ -/* Description: header bits [127:64] */ -#define SH_XNIILB_ERROR_DETAIL_2_HEADER_SHFT 0 -#define SH_XNIILB_ERROR_DETAIL_2_HEADER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_XNIILB_ERROR_DETAIL_3" */ -/* Look Up Table Address (iilb) */ -/* ==================================================================== */ - -#define SH_XNIILB_ERROR_DETAIL_3 0x0000000150040130 -#define SH_XNIILB_ERROR_DETAIL_3_MASK 0x00000000000007ff -#define SH_XNIILB_ERROR_DETAIL_3_INIT 0x0000000000000000 - -/* SH_XNIILB_ERROR_DETAIL_3_LUT_ADDR */ -/* Description: Look Up Table Read Address */ -#define SH_XNIILB_ERROR_DETAIL_3_LUT_ADDR_SHFT 0 -#define SH_XNIILB_ERROR_DETAIL_3_LUT_ADDR_MASK 0x00000000000007ff - -/* ==================================================================== */ -/* Register "SH_NI0_ERROR_DETAIL_3" */ -/* Look Up Table Address (ni0) */ -/* ==================================================================== */ - -#define SH_NI0_ERROR_DETAIL_3 0x0000000150040140 -#define SH_NI0_ERROR_DETAIL_3_MASK 0x00000000000007ff -#define SH_NI0_ERROR_DETAIL_3_INIT 0x0000000000000000 - -/* SH_NI0_ERROR_DETAIL_3_LUT_ADDR */ -/* Description: Look Up Table Read Address */ -#define SH_NI0_ERROR_DETAIL_3_LUT_ADDR_SHFT 0 -#define SH_NI0_ERROR_DETAIL_3_LUT_ADDR_MASK 0x00000000000007ff - -/* ==================================================================== */ -/* Register "SH_NI1_ERROR_DETAIL_3" */ -/* Look Up Table Address (ni1) */ -/* ==================================================================== */ - -#define SH_NI1_ERROR_DETAIL_3 0x0000000150040150 -#define SH_NI1_ERROR_DETAIL_3_MASK 0x00000000000007ff -#define SH_NI1_ERROR_DETAIL_3_INIT 0x0000000000000000 - -/* SH_NI1_ERROR_DETAIL_3_LUT_ADDR */ -/* Description: Look Up Table Read Address */ -#define SH_NI1_ERROR_DETAIL_3_LUT_ADDR_SHFT 0 -#define SH_NI1_ERROR_DETAIL_3_LUT_ADDR_MASK 0x00000000000007ff - -/* ==================================================================== */ -/* Register "SH_XN_ERROR_SUMMARY" */ -/* ==================================================================== */ - -#define SH_XN_ERROR_SUMMARY 0x0000000150040000 -#define SH_XN_ERROR_SUMMARY_MASK 0x0000003fffffffff -#define SH_XN_ERROR_SUMMARY_INIT 0x0000003fffffffff - -/* SH_XN_ERROR_SUMMARY_NI0_POP_OVERFLOW */ -/* Description: NI0 pop overflow */ -#define SH_XN_ERROR_SUMMARY_NI0_POP_OVERFLOW_SHFT 0 -#define SH_XN_ERROR_SUMMARY_NI0_POP_OVERFLOW_MASK 0x0000000000000001 - -/* SH_XN_ERROR_SUMMARY_NI0_PUSH_OVERFLOW */ -/* Description: NI0 push overflow */ -#define SH_XN_ERROR_SUMMARY_NI0_PUSH_OVERFLOW_SHFT 1 -#define SH_XN_ERROR_SUMMARY_NI0_PUSH_OVERFLOW_MASK 0x0000000000000002 - -/* SH_XN_ERROR_SUMMARY_NI0_CREDIT_OVERFLOW */ -/* Description: NI0 credit overflow */ -#define SH_XN_ERROR_SUMMARY_NI0_CREDIT_OVERFLOW_SHFT 2 -#define SH_XN_ERROR_SUMMARY_NI0_CREDIT_OVERFLOW_MASK 0x0000000000000004 - -/* SH_XN_ERROR_SUMMARY_NI0_DEBIT_OVERFLOW */ -/* Description: NI0 debit overflow */ -#define SH_XN_ERROR_SUMMARY_NI0_DEBIT_OVERFLOW_SHFT 3 -#define SH_XN_ERROR_SUMMARY_NI0_DEBIT_OVERFLOW_MASK 0x0000000000000008 - -/* SH_XN_ERROR_SUMMARY_NI0_POP_UNDERFLOW */ -/* Description: NI0 pop underflow */ -#define SH_XN_ERROR_SUMMARY_NI0_POP_UNDERFLOW_SHFT 4 -#define SH_XN_ERROR_SUMMARY_NI0_POP_UNDERFLOW_MASK 0x0000000000000010 - -/* SH_XN_ERROR_SUMMARY_NI0_PUSH_UNDERFLOW */ -/* Description: NI0 push underflow */ -#define SH_XN_ERROR_SUMMARY_NI0_PUSH_UNDERFLOW_SHFT 5 -#define SH_XN_ERROR_SUMMARY_NI0_PUSH_UNDERFLOW_MASK 0x0000000000000020 - -/* SH_XN_ERROR_SUMMARY_NI0_CREDIT_UNDERFLOW */ -/* Description: NI0 credit underflow */ -#define SH_XN_ERROR_SUMMARY_NI0_CREDIT_UNDERFLOW_SHFT 6 -#define SH_XN_ERROR_SUMMARY_NI0_CREDIT_UNDERFLOW_MASK 0x0000000000000040 - -/* SH_XN_ERROR_SUMMARY_NI0_LLP_ERROR */ -/* Description: NI0 llp error */ -#define SH_XN_ERROR_SUMMARY_NI0_LLP_ERROR_SHFT 7 -#define SH_XN_ERROR_SUMMARY_NI0_LLP_ERROR_MASK 0x0000000000000080 - -/* SH_XN_ERROR_SUMMARY_NI0_PIPE_ERROR */ -/* Description: NI0 Pipe in/out errors */ -#define SH_XN_ERROR_SUMMARY_NI0_PIPE_ERROR_SHFT 8 -#define SH_XN_ERROR_SUMMARY_NI0_PIPE_ERROR_MASK 0x0000000000000100 - -/* SH_XN_ERROR_SUMMARY_NI1_POP_OVERFLOW */ -/* Description: NI1 pop overflow */ -#define SH_XN_ERROR_SUMMARY_NI1_POP_OVERFLOW_SHFT 9 -#define SH_XN_ERROR_SUMMARY_NI1_POP_OVERFLOW_MASK 0x0000000000000200 - -/* SH_XN_ERROR_SUMMARY_NI1_PUSH_OVERFLOW */ -/* Description: NI1 push overflow */ -#define SH_XN_ERROR_SUMMARY_NI1_PUSH_OVERFLOW_SHFT 10 -#define SH_XN_ERROR_SUMMARY_NI1_PUSH_OVERFLOW_MASK 0x0000000000000400 - -/* SH_XN_ERROR_SUMMARY_NI1_CREDIT_OVERFLOW */ -/* Description: NI1 credit overflow */ -#define SH_XN_ERROR_SUMMARY_NI1_CREDIT_OVERFLOW_SHFT 11 -#define SH_XN_ERROR_SUMMARY_NI1_CREDIT_OVERFLOW_MASK 0x0000000000000800 - -/* SH_XN_ERROR_SUMMARY_NI1_DEBIT_OVERFLOW */ -/* Description: NI1 debit overflow */ -#define SH_XN_ERROR_SUMMARY_NI1_DEBIT_OVERFLOW_SHFT 12 -#define SH_XN_ERROR_SUMMARY_NI1_DEBIT_OVERFLOW_MASK 0x0000000000001000 - -/* SH_XN_ERROR_SUMMARY_NI1_POP_UNDERFLOW */ -/* Description: NI1 pop underflow */ -#define SH_XN_ERROR_SUMMARY_NI1_POP_UNDERFLOW_SHFT 13 -#define SH_XN_ERROR_SUMMARY_NI1_POP_UNDERFLOW_MASK 0x0000000000002000 - -/* SH_XN_ERROR_SUMMARY_NI1_PUSH_UNDERFLOW */ -/* Description: NI1 push underflow */ -#define SH_XN_ERROR_SUMMARY_NI1_PUSH_UNDERFLOW_SHFT 14 -#define SH_XN_ERROR_SUMMARY_NI1_PUSH_UNDERFLOW_MASK 0x0000000000004000 - -/* SH_XN_ERROR_SUMMARY_NI1_CREDIT_UNDERFLOW */ -/* Description: NI1 credit underflow */ -#define SH_XN_ERROR_SUMMARY_NI1_CREDIT_UNDERFLOW_SHFT 15 -#define SH_XN_ERROR_SUMMARY_NI1_CREDIT_UNDERFLOW_MASK 0x0000000000008000 - -/* SH_XN_ERROR_SUMMARY_NI1_LLP_ERROR */ -/* Description: NI1 llp error */ -#define SH_XN_ERROR_SUMMARY_NI1_LLP_ERROR_SHFT 16 -#define SH_XN_ERROR_SUMMARY_NI1_LLP_ERROR_MASK 0x0000000000010000 - -/* SH_XN_ERROR_SUMMARY_NI1_PIPE_ERROR */ -/* Description: NI1 pipe in/out error */ -#define SH_XN_ERROR_SUMMARY_NI1_PIPE_ERROR_SHFT 17 -#define SH_XN_ERROR_SUMMARY_NI1_PIPE_ERROR_MASK 0x0000000000020000 - -/* SH_XN_ERROR_SUMMARY_XNMD_CREDIT_OVERFLOW */ -/* Description: XNMD credit overflow */ -#define SH_XN_ERROR_SUMMARY_XNMD_CREDIT_OVERFLOW_SHFT 18 -#define SH_XN_ERROR_SUMMARY_XNMD_CREDIT_OVERFLOW_MASK 0x0000000000040000 - -/* SH_XN_ERROR_SUMMARY_XNMD_DEBIT_OVERFLOW */ -/* Description: XNMD debit overflow */ -#define SH_XN_ERROR_SUMMARY_XNMD_DEBIT_OVERFLOW_SHFT 19 -#define SH_XN_ERROR_SUMMARY_XNMD_DEBIT_OVERFLOW_MASK 0x0000000000080000 - -/* SH_XN_ERROR_SUMMARY_XNMD_DATA_BUFF_OVERFLOW */ -/* Description: XNMD data buffer overflow */ -#define SH_XN_ERROR_SUMMARY_XNMD_DATA_BUFF_OVERFLOW_SHFT 20 -#define SH_XN_ERROR_SUMMARY_XNMD_DATA_BUFF_OVERFLOW_MASK 0x0000000000100000 - -/* SH_XN_ERROR_SUMMARY_XNMD_CREDIT_UNDERFLOW */ -/* Description: XNMD credit underflow */ -#define SH_XN_ERROR_SUMMARY_XNMD_CREDIT_UNDERFLOW_SHFT 21 -#define SH_XN_ERROR_SUMMARY_XNMD_CREDIT_UNDERFLOW_MASK 0x0000000000200000 - -/* SH_XN_ERROR_SUMMARY_XNMD_SBE_ERROR */ -/* Description: XNMD single bit error */ -#define SH_XN_ERROR_SUMMARY_XNMD_SBE_ERROR_SHFT 22 -#define SH_XN_ERROR_SUMMARY_XNMD_SBE_ERROR_MASK 0x0000000000400000 - -/* SH_XN_ERROR_SUMMARY_XNMD_UCE_ERROR */ -/* Description: XNMD uncorrectable error */ -#define SH_XN_ERROR_SUMMARY_XNMD_UCE_ERROR_SHFT 23 -#define SH_XN_ERROR_SUMMARY_XNMD_UCE_ERROR_MASK 0x0000000000800000 - -/* SH_XN_ERROR_SUMMARY_XNMD_LUT_ERROR */ -/* Description: XNMD look up table error */ -#define SH_XN_ERROR_SUMMARY_XNMD_LUT_ERROR_SHFT 24 -#define SH_XN_ERROR_SUMMARY_XNMD_LUT_ERROR_MASK 0x0000000001000000 - -/* SH_XN_ERROR_SUMMARY_XNPI_CREDIT_OVERFLOW */ -/* Description: XNMD credit overflow */ -#define SH_XN_ERROR_SUMMARY_XNPI_CREDIT_OVERFLOW_SHFT 25 -#define SH_XN_ERROR_SUMMARY_XNPI_CREDIT_OVERFLOW_MASK 0x0000000002000000 - -/* SH_XN_ERROR_SUMMARY_XNPI_DEBIT_OVERFLOW */ -/* Description: XNPI debit overflow */ -#define SH_XN_ERROR_SUMMARY_XNPI_DEBIT_OVERFLOW_SHFT 26 -#define SH_XN_ERROR_SUMMARY_XNPI_DEBIT_OVERFLOW_MASK 0x0000000004000000 - -/* SH_XN_ERROR_SUMMARY_XNPI_DATA_BUFF_OVERFLOW */ -/* Description: XNPI data buffer overflow */ -#define SH_XN_ERROR_SUMMARY_XNPI_DATA_BUFF_OVERFLOW_SHFT 27 -#define SH_XN_ERROR_SUMMARY_XNPI_DATA_BUFF_OVERFLOW_MASK 0x0000000008000000 - -/* SH_XN_ERROR_SUMMARY_XNPI_CREDIT_UNDERFLOW */ -/* Description: XNPI credit underflow */ -#define SH_XN_ERROR_SUMMARY_XNPI_CREDIT_UNDERFLOW_SHFT 28 -#define SH_XN_ERROR_SUMMARY_XNPI_CREDIT_UNDERFLOW_MASK 0x0000000010000000 - -/* SH_XN_ERROR_SUMMARY_XNPI_SBE_ERROR */ -/* Description: XNPI single bit error */ -#define SH_XN_ERROR_SUMMARY_XNPI_SBE_ERROR_SHFT 29 -#define SH_XN_ERROR_SUMMARY_XNPI_SBE_ERROR_MASK 0x0000000020000000 - -/* SH_XN_ERROR_SUMMARY_XNPI_UCE_ERROR */ -/* Description: XNPI uncorrectable error */ -#define SH_XN_ERROR_SUMMARY_XNPI_UCE_ERROR_SHFT 30 -#define SH_XN_ERROR_SUMMARY_XNPI_UCE_ERROR_MASK 0x0000000040000000 - -/* SH_XN_ERROR_SUMMARY_XNPI_LUT_ERROR */ -/* Description: XNPI look up table error */ -#define SH_XN_ERROR_SUMMARY_XNPI_LUT_ERROR_SHFT 31 -#define SH_XN_ERROR_SUMMARY_XNPI_LUT_ERROR_MASK 0x0000000080000000 - -/* SH_XN_ERROR_SUMMARY_IILB_DEBIT_OVERFLOW */ -/* Description: IILB debit overflow */ -#define SH_XN_ERROR_SUMMARY_IILB_DEBIT_OVERFLOW_SHFT 32 -#define SH_XN_ERROR_SUMMARY_IILB_DEBIT_OVERFLOW_MASK 0x0000000100000000 - -/* SH_XN_ERROR_SUMMARY_IILB_CREDIT_OVERFLOW */ -/* Description: IILB credit overflow */ -#define SH_XN_ERROR_SUMMARY_IILB_CREDIT_OVERFLOW_SHFT 33 -#define SH_XN_ERROR_SUMMARY_IILB_CREDIT_OVERFLOW_MASK 0x0000000200000000 - -/* SH_XN_ERROR_SUMMARY_IILB_FIFO_OVERFLOW */ -/* Description: IILB fifo overflow */ -#define SH_XN_ERROR_SUMMARY_IILB_FIFO_OVERFLOW_SHFT 34 -#define SH_XN_ERROR_SUMMARY_IILB_FIFO_OVERFLOW_MASK 0x0000000400000000 - -/* SH_XN_ERROR_SUMMARY_IILB_CREDIT_UNDERFLOW */ -/* Description: IILB credit underflow */ -#define SH_XN_ERROR_SUMMARY_IILB_CREDIT_UNDERFLOW_SHFT 35 -#define SH_XN_ERROR_SUMMARY_IILB_CREDIT_UNDERFLOW_MASK 0x0000000800000000 - -/* SH_XN_ERROR_SUMMARY_IILB_FIFO_UNDERFLOW */ -/* Description: IILB fifo underflow */ -#define SH_XN_ERROR_SUMMARY_IILB_FIFO_UNDERFLOW_SHFT 36 -#define SH_XN_ERROR_SUMMARY_IILB_FIFO_UNDERFLOW_MASK 0x0000001000000000 - -/* SH_XN_ERROR_SUMMARY_IILB_CHIPLET_OR_LUT */ -/* Description: IILB chiplet nomatch or lut read error */ -#define SH_XN_ERROR_SUMMARY_IILB_CHIPLET_OR_LUT_SHFT 37 -#define SH_XN_ERROR_SUMMARY_IILB_CHIPLET_OR_LUT_MASK 0x0000002000000000 - -/* ==================================================================== */ -/* Register "SH_XN_ERRORS_ALIAS" */ -/* ==================================================================== */ - -#define SH_XN_ERRORS_ALIAS 0x0000000150040008 - -/* ==================================================================== */ -/* Register "SH_XN_ERROR_OVERFLOW" */ -/* ==================================================================== */ - -#define SH_XN_ERROR_OVERFLOW 0x0000000150040020 -#define SH_XN_ERROR_OVERFLOW_MASK 0x0000003fffffffff -#define SH_XN_ERROR_OVERFLOW_INIT 0x0000003fffffffff - -/* SH_XN_ERROR_OVERFLOW_NI0_POP_OVERFLOW */ -/* Description: NI0 pop overflow */ -#define SH_XN_ERROR_OVERFLOW_NI0_POP_OVERFLOW_SHFT 0 -#define SH_XN_ERROR_OVERFLOW_NI0_POP_OVERFLOW_MASK 0x0000000000000001 - -/* SH_XN_ERROR_OVERFLOW_NI0_PUSH_OVERFLOW */ -/* Description: NI0 push overflow */ -#define SH_XN_ERROR_OVERFLOW_NI0_PUSH_OVERFLOW_SHFT 1 -#define SH_XN_ERROR_OVERFLOW_NI0_PUSH_OVERFLOW_MASK 0x0000000000000002 - -/* SH_XN_ERROR_OVERFLOW_NI0_CREDIT_OVERFLOW */ -/* Description: NI0 credit overflow */ -#define SH_XN_ERROR_OVERFLOW_NI0_CREDIT_OVERFLOW_SHFT 2 -#define SH_XN_ERROR_OVERFLOW_NI0_CREDIT_OVERFLOW_MASK 0x0000000000000004 - -/* SH_XN_ERROR_OVERFLOW_NI0_DEBIT_OVERFLOW */ -/* Description: NI0 debit overflow */ -#define SH_XN_ERROR_OVERFLOW_NI0_DEBIT_OVERFLOW_SHFT 3 -#define SH_XN_ERROR_OVERFLOW_NI0_DEBIT_OVERFLOW_MASK 0x0000000000000008 - -/* SH_XN_ERROR_OVERFLOW_NI0_POP_UNDERFLOW */ -/* Description: NI0 pop underflow */ -#define SH_XN_ERROR_OVERFLOW_NI0_POP_UNDERFLOW_SHFT 4 -#define SH_XN_ERROR_OVERFLOW_NI0_POP_UNDERFLOW_MASK 0x0000000000000010 - -/* SH_XN_ERROR_OVERFLOW_NI0_PUSH_UNDERFLOW */ -/* Description: NI0 push underflow */ -#define SH_XN_ERROR_OVERFLOW_NI0_PUSH_UNDERFLOW_SHFT 5 -#define SH_XN_ERROR_OVERFLOW_NI0_PUSH_UNDERFLOW_MASK 0x0000000000000020 - -/* SH_XN_ERROR_OVERFLOW_NI0_CREDIT_UNDERFLOW */ -/* Description: NI0 credit underflow */ -#define SH_XN_ERROR_OVERFLOW_NI0_CREDIT_UNDERFLOW_SHFT 6 -#define SH_XN_ERROR_OVERFLOW_NI0_CREDIT_UNDERFLOW_MASK 0x0000000000000040 - -/* SH_XN_ERROR_OVERFLOW_NI0_LLP_ERROR */ -/* Description: NI0 llp error */ -#define SH_XN_ERROR_OVERFLOW_NI0_LLP_ERROR_SHFT 7 -#define SH_XN_ERROR_OVERFLOW_NI0_LLP_ERROR_MASK 0x0000000000000080 - -/* SH_XN_ERROR_OVERFLOW_NI0_PIPE_ERROR */ -/* Description: NI0 Pipe in/out errors */ -#define SH_XN_ERROR_OVERFLOW_NI0_PIPE_ERROR_SHFT 8 -#define SH_XN_ERROR_OVERFLOW_NI0_PIPE_ERROR_MASK 0x0000000000000100 - -/* SH_XN_ERROR_OVERFLOW_NI1_POP_OVERFLOW */ -/* Description: NI1 pop overflow */ -#define SH_XN_ERROR_OVERFLOW_NI1_POP_OVERFLOW_SHFT 9 -#define SH_XN_ERROR_OVERFLOW_NI1_POP_OVERFLOW_MASK 0x0000000000000200 - -/* SH_XN_ERROR_OVERFLOW_NI1_PUSH_OVERFLOW */ -/* Description: NI1 push overflow */ -#define SH_XN_ERROR_OVERFLOW_NI1_PUSH_OVERFLOW_SHFT 10 -#define SH_XN_ERROR_OVERFLOW_NI1_PUSH_OVERFLOW_MASK 0x0000000000000400 - -/* SH_XN_ERROR_OVERFLOW_NI1_CREDIT_OVERFLOW */ -/* Description: NI1 credit overflow */ -#define SH_XN_ERROR_OVERFLOW_NI1_CREDIT_OVERFLOW_SHFT 11 -#define SH_XN_ERROR_OVERFLOW_NI1_CREDIT_OVERFLOW_MASK 0x0000000000000800 - -/* SH_XN_ERROR_OVERFLOW_NI1_DEBIT_OVERFLOW */ -/* Description: NI1 debit overflow */ -#define SH_XN_ERROR_OVERFLOW_NI1_DEBIT_OVERFLOW_SHFT 12 -#define SH_XN_ERROR_OVERFLOW_NI1_DEBIT_OVERFLOW_MASK 0x0000000000001000 - -/* SH_XN_ERROR_OVERFLOW_NI1_POP_UNDERFLOW */ -/* Description: NI1 pop underflow */ -#define SH_XN_ERROR_OVERFLOW_NI1_POP_UNDERFLOW_SHFT 13 -#define SH_XN_ERROR_OVERFLOW_NI1_POP_UNDERFLOW_MASK 0x0000000000002000 - -/* SH_XN_ERROR_OVERFLOW_NI1_PUSH_UNDERFLOW */ -/* Description: NI1 push underflow */ -#define SH_XN_ERROR_OVERFLOW_NI1_PUSH_UNDERFLOW_SHFT 14 -#define SH_XN_ERROR_OVERFLOW_NI1_PUSH_UNDERFLOW_MASK 0x0000000000004000 - -/* SH_XN_ERROR_OVERFLOW_NI1_CREDIT_UNDERFLOW */ -/* Description: NI1 credit underflow */ -#define SH_XN_ERROR_OVERFLOW_NI1_CREDIT_UNDERFLOW_SHFT 15 -#define SH_XN_ERROR_OVERFLOW_NI1_CREDIT_UNDERFLOW_MASK 0x0000000000008000 - -/* SH_XN_ERROR_OVERFLOW_NI1_LLP_ERROR */ -/* Description: NI1 llp error */ -#define SH_XN_ERROR_OVERFLOW_NI1_LLP_ERROR_SHFT 16 -#define SH_XN_ERROR_OVERFLOW_NI1_LLP_ERROR_MASK 0x0000000000010000 - -/* SH_XN_ERROR_OVERFLOW_NI1_PIPE_ERROR */ -/* Description: NI1 pipe in/out error */ -#define SH_XN_ERROR_OVERFLOW_NI1_PIPE_ERROR_SHFT 17 -#define SH_XN_ERROR_OVERFLOW_NI1_PIPE_ERROR_MASK 0x0000000000020000 - -/* SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_OVERFLOW */ -/* Description: XNMD credit overflow */ -#define SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_OVERFLOW_SHFT 18 -#define SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_OVERFLOW_MASK 0x0000000000040000 - -/* SH_XN_ERROR_OVERFLOW_XNMD_DEBIT_OVERFLOW */ -/* Description: XNMD debit overflow */ -#define SH_XN_ERROR_OVERFLOW_XNMD_DEBIT_OVERFLOW_SHFT 19 -#define SH_XN_ERROR_OVERFLOW_XNMD_DEBIT_OVERFLOW_MASK 0x0000000000080000 - -/* SH_XN_ERROR_OVERFLOW_XNMD_DATA_BUFF_OVERFLOW */ -/* Description: XNMD data buffer overflow */ -#define SH_XN_ERROR_OVERFLOW_XNMD_DATA_BUFF_OVERFLOW_SHFT 20 -#define SH_XN_ERROR_OVERFLOW_XNMD_DATA_BUFF_OVERFLOW_MASK 0x0000000000100000 - -/* SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_UNDERFLOW */ -/* Description: XNMD credit underflow */ -#define SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_UNDERFLOW_SHFT 21 -#define SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_UNDERFLOW_MASK 0x0000000000200000 - -/* SH_XN_ERROR_OVERFLOW_XNMD_SBE_ERROR */ -/* Description: XNMD single bit error */ -#define SH_XN_ERROR_OVERFLOW_XNMD_SBE_ERROR_SHFT 22 -#define SH_XN_ERROR_OVERFLOW_XNMD_SBE_ERROR_MASK 0x0000000000400000 - -/* SH_XN_ERROR_OVERFLOW_XNMD_UCE_ERROR */ -/* Description: XNMD uncorrectable error */ -#define SH_XN_ERROR_OVERFLOW_XNMD_UCE_ERROR_SHFT 23 -#define SH_XN_ERROR_OVERFLOW_XNMD_UCE_ERROR_MASK 0x0000000000800000 - -/* SH_XN_ERROR_OVERFLOW_XNMD_LUT_ERROR */ -/* Description: XNMD look up table error */ -#define SH_XN_ERROR_OVERFLOW_XNMD_LUT_ERROR_SHFT 24 -#define SH_XN_ERROR_OVERFLOW_XNMD_LUT_ERROR_MASK 0x0000000001000000 - -/* SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_OVERFLOW */ -/* Description: XNMD credit overflow */ -#define SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_OVERFLOW_SHFT 25 -#define SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_OVERFLOW_MASK 0x0000000002000000 - -/* SH_XN_ERROR_OVERFLOW_XNPI_DEBIT_OVERFLOW */ -/* Description: XNPI debit overflow */ -#define SH_XN_ERROR_OVERFLOW_XNPI_DEBIT_OVERFLOW_SHFT 26 -#define SH_XN_ERROR_OVERFLOW_XNPI_DEBIT_OVERFLOW_MASK 0x0000000004000000 - -/* SH_XN_ERROR_OVERFLOW_XNPI_DATA_BUFF_OVERFLOW */ -/* Description: XNPI data buffer overflow */ -#define SH_XN_ERROR_OVERFLOW_XNPI_DATA_BUFF_OVERFLOW_SHFT 27 -#define SH_XN_ERROR_OVERFLOW_XNPI_DATA_BUFF_OVERFLOW_MASK 0x0000000008000000 - -/* SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_UNDERFLOW */ -/* Description: XNPI credit underflow */ -#define SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_UNDERFLOW_SHFT 28 -#define SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_UNDERFLOW_MASK 0x0000000010000000 - -/* SH_XN_ERROR_OVERFLOW_XNPI_SBE_ERROR */ -/* Description: XNPI single bit error */ -#define SH_XN_ERROR_OVERFLOW_XNPI_SBE_ERROR_SHFT 29 -#define SH_XN_ERROR_OVERFLOW_XNPI_SBE_ERROR_MASK 0x0000000020000000 - -/* SH_XN_ERROR_OVERFLOW_XNPI_UCE_ERROR */ -/* Description: XNPI uncorrectable error */ -#define SH_XN_ERROR_OVERFLOW_XNPI_UCE_ERROR_SHFT 30 -#define SH_XN_ERROR_OVERFLOW_XNPI_UCE_ERROR_MASK 0x0000000040000000 - -/* SH_XN_ERROR_OVERFLOW_XNPI_LUT_ERROR */ -/* Description: XNPI look up table error */ -#define SH_XN_ERROR_OVERFLOW_XNPI_LUT_ERROR_SHFT 31 -#define SH_XN_ERROR_OVERFLOW_XNPI_LUT_ERROR_MASK 0x0000000080000000 - -/* SH_XN_ERROR_OVERFLOW_IILB_DEBIT_OVERFLOW */ -/* Description: IILB debit overflow */ -#define SH_XN_ERROR_OVERFLOW_IILB_DEBIT_OVERFLOW_SHFT 32 -#define SH_XN_ERROR_OVERFLOW_IILB_DEBIT_OVERFLOW_MASK 0x0000000100000000 - -/* SH_XN_ERROR_OVERFLOW_IILB_CREDIT_OVERFLOW */ -/* Description: IILB credit overflow */ -#define SH_XN_ERROR_OVERFLOW_IILB_CREDIT_OVERFLOW_SHFT 33 -#define SH_XN_ERROR_OVERFLOW_IILB_CREDIT_OVERFLOW_MASK 0x0000000200000000 - -/* SH_XN_ERROR_OVERFLOW_IILB_FIFO_OVERFLOW */ -/* Description: IILB fifo overflow */ -#define SH_XN_ERROR_OVERFLOW_IILB_FIFO_OVERFLOW_SHFT 34 -#define SH_XN_ERROR_OVERFLOW_IILB_FIFO_OVERFLOW_MASK 0x0000000400000000 - -/* SH_XN_ERROR_OVERFLOW_IILB_CREDIT_UNDERFLOW */ -/* Description: IILB credit underflow */ -#define SH_XN_ERROR_OVERFLOW_IILB_CREDIT_UNDERFLOW_SHFT 35 -#define SH_XN_ERROR_OVERFLOW_IILB_CREDIT_UNDERFLOW_MASK 0x0000000800000000 - -/* SH_XN_ERROR_OVERFLOW_IILB_FIFO_UNDERFLOW */ -/* Description: IILB fifo underflow */ -#define SH_XN_ERROR_OVERFLOW_IILB_FIFO_UNDERFLOW_SHFT 36 -#define SH_XN_ERROR_OVERFLOW_IILB_FIFO_UNDERFLOW_MASK 0x0000001000000000 - -/* SH_XN_ERROR_OVERFLOW_IILB_CHIPLET_OR_LUT */ -/* Description: IILB chiplet nomatch or lut read error */ -#define SH_XN_ERROR_OVERFLOW_IILB_CHIPLET_OR_LUT_SHFT 37 -#define SH_XN_ERROR_OVERFLOW_IILB_CHIPLET_OR_LUT_MASK 0x0000002000000000 - -/* ==================================================================== */ -/* Register "SH_XN_ERROR_OVERFLOW_ALIAS" */ -/* ==================================================================== */ - -#define SH_XN_ERROR_OVERFLOW_ALIAS 0x0000000150040028 - -/* ==================================================================== */ -/* Register "SH_XN_ERROR_MASK" */ -/* ==================================================================== */ - -#define SH_XN_ERROR_MASK 0x0000000150040040 -#define SH_XN_ERROR_MASK_MASK 0x0000003fffffffff -#define SH_XN_ERROR_MASK_INIT 0x0000003fffffffff - -/* SH_XN_ERROR_MASK_NI0_POP_OVERFLOW */ -/* Description: NI0 pop overflow */ -#define SH_XN_ERROR_MASK_NI0_POP_OVERFLOW_SHFT 0 -#define SH_XN_ERROR_MASK_NI0_POP_OVERFLOW_MASK 0x0000000000000001 - -/* SH_XN_ERROR_MASK_NI0_PUSH_OVERFLOW */ -/* Description: NI0 push overflow */ -#define SH_XN_ERROR_MASK_NI0_PUSH_OVERFLOW_SHFT 1 -#define SH_XN_ERROR_MASK_NI0_PUSH_OVERFLOW_MASK 0x0000000000000002 - -/* SH_XN_ERROR_MASK_NI0_CREDIT_OVERFLOW */ -/* Description: NI0 credit overflow */ -#define SH_XN_ERROR_MASK_NI0_CREDIT_OVERFLOW_SHFT 2 -#define SH_XN_ERROR_MASK_NI0_CREDIT_OVERFLOW_MASK 0x0000000000000004 - -/* SH_XN_ERROR_MASK_NI0_DEBIT_OVERFLOW */ -/* Description: NI0 debit overflow */ -#define SH_XN_ERROR_MASK_NI0_DEBIT_OVERFLOW_SHFT 3 -#define SH_XN_ERROR_MASK_NI0_DEBIT_OVERFLOW_MASK 0x0000000000000008 - -/* SH_XN_ERROR_MASK_NI0_POP_UNDERFLOW */ -/* Description: NI0 pop underflow */ -#define SH_XN_ERROR_MASK_NI0_POP_UNDERFLOW_SHFT 4 -#define SH_XN_ERROR_MASK_NI0_POP_UNDERFLOW_MASK 0x0000000000000010 - -/* SH_XN_ERROR_MASK_NI0_PUSH_UNDERFLOW */ -/* Description: NI0 push underflow */ -#define SH_XN_ERROR_MASK_NI0_PUSH_UNDERFLOW_SHFT 5 -#define SH_XN_ERROR_MASK_NI0_PUSH_UNDERFLOW_MASK 0x0000000000000020 - -/* SH_XN_ERROR_MASK_NI0_CREDIT_UNDERFLOW */ -/* Description: NI0 credit underflow */ -#define SH_XN_ERROR_MASK_NI0_CREDIT_UNDERFLOW_SHFT 6 -#define SH_XN_ERROR_MASK_NI0_CREDIT_UNDERFLOW_MASK 0x0000000000000040 - -/* SH_XN_ERROR_MASK_NI0_LLP_ERROR */ -/* Description: NI0 llp error */ -#define SH_XN_ERROR_MASK_NI0_LLP_ERROR_SHFT 7 -#define SH_XN_ERROR_MASK_NI0_LLP_ERROR_MASK 0x0000000000000080 - -/* SH_XN_ERROR_MASK_NI0_PIPE_ERROR */ -/* Description: NI0 Pipe in/out errors */ -#define SH_XN_ERROR_MASK_NI0_PIPE_ERROR_SHFT 8 -#define SH_XN_ERROR_MASK_NI0_PIPE_ERROR_MASK 0x0000000000000100 - -/* SH_XN_ERROR_MASK_NI1_POP_OVERFLOW */ -/* Description: NI1 pop overflow */ -#define SH_XN_ERROR_MASK_NI1_POP_OVERFLOW_SHFT 9 -#define SH_XN_ERROR_MASK_NI1_POP_OVERFLOW_MASK 0x0000000000000200 - -/* SH_XN_ERROR_MASK_NI1_PUSH_OVERFLOW */ -/* Description: NI1 push overflow */ -#define SH_XN_ERROR_MASK_NI1_PUSH_OVERFLOW_SHFT 10 -#define SH_XN_ERROR_MASK_NI1_PUSH_OVERFLOW_MASK 0x0000000000000400 - -/* SH_XN_ERROR_MASK_NI1_CREDIT_OVERFLOW */ -/* Description: NI1 credit overflow */ -#define SH_XN_ERROR_MASK_NI1_CREDIT_OVERFLOW_SHFT 11 -#define SH_XN_ERROR_MASK_NI1_CREDIT_OVERFLOW_MASK 0x0000000000000800 - -/* SH_XN_ERROR_MASK_NI1_DEBIT_OVERFLOW */ -/* Description: NI1 debit overflow */ -#define SH_XN_ERROR_MASK_NI1_DEBIT_OVERFLOW_SHFT 12 -#define SH_XN_ERROR_MASK_NI1_DEBIT_OVERFLOW_MASK 0x0000000000001000 - -/* SH_XN_ERROR_MASK_NI1_POP_UNDERFLOW */ -/* Description: NI1 pop underflow */ -#define SH_XN_ERROR_MASK_NI1_POP_UNDERFLOW_SHFT 13 -#define SH_XN_ERROR_MASK_NI1_POP_UNDERFLOW_MASK 0x0000000000002000 - -/* SH_XN_ERROR_MASK_NI1_PUSH_UNDERFLOW */ -/* Description: NI1 push underflow */ -#define SH_XN_ERROR_MASK_NI1_PUSH_UNDERFLOW_SHFT 14 -#define SH_XN_ERROR_MASK_NI1_PUSH_UNDERFLOW_MASK 0x0000000000004000 - -/* SH_XN_ERROR_MASK_NI1_CREDIT_UNDERFLOW */ -/* Description: NI1 credit underflow */ -#define SH_XN_ERROR_MASK_NI1_CREDIT_UNDERFLOW_SHFT 15 -#define SH_XN_ERROR_MASK_NI1_CREDIT_UNDERFLOW_MASK 0x0000000000008000 - -/* SH_XN_ERROR_MASK_NI1_LLP_ERROR */ -/* Description: NI1 llp error */ -#define SH_XN_ERROR_MASK_NI1_LLP_ERROR_SHFT 16 -#define SH_XN_ERROR_MASK_NI1_LLP_ERROR_MASK 0x0000000000010000 - -/* SH_XN_ERROR_MASK_NI1_PIPE_ERROR */ -/* Description: NI1 pipe in/out error */ -#define SH_XN_ERROR_MASK_NI1_PIPE_ERROR_SHFT 17 -#define SH_XN_ERROR_MASK_NI1_PIPE_ERROR_MASK 0x0000000000020000 - -/* SH_XN_ERROR_MASK_XNMD_CREDIT_OVERFLOW */ -/* Description: XNMD credit overflow */ -#define SH_XN_ERROR_MASK_XNMD_CREDIT_OVERFLOW_SHFT 18 -#define SH_XN_ERROR_MASK_XNMD_CREDIT_OVERFLOW_MASK 0x0000000000040000 - -/* SH_XN_ERROR_MASK_XNMD_DEBIT_OVERFLOW */ -/* Description: XNMD debit overflow */ -#define SH_XN_ERROR_MASK_XNMD_DEBIT_OVERFLOW_SHFT 19 -#define SH_XN_ERROR_MASK_XNMD_DEBIT_OVERFLOW_MASK 0x0000000000080000 - -/* SH_XN_ERROR_MASK_XNMD_DATA_BUFF_OVERFLOW */ -/* Description: XNMD data buffer overflow */ -#define SH_XN_ERROR_MASK_XNMD_DATA_BUFF_OVERFLOW_SHFT 20 -#define SH_XN_ERROR_MASK_XNMD_DATA_BUFF_OVERFLOW_MASK 0x0000000000100000 - -/* SH_XN_ERROR_MASK_XNMD_CREDIT_UNDERFLOW */ -/* Description: XNMD credit underflow */ -#define SH_XN_ERROR_MASK_XNMD_CREDIT_UNDERFLOW_SHFT 21 -#define SH_XN_ERROR_MASK_XNMD_CREDIT_UNDERFLOW_MASK 0x0000000000200000 - -/* SH_XN_ERROR_MASK_XNMD_SBE_ERROR */ -/* Description: XNMD single bit error */ -#define SH_XN_ERROR_MASK_XNMD_SBE_ERROR_SHFT 22 -#define SH_XN_ERROR_MASK_XNMD_SBE_ERROR_MASK 0x0000000000400000 - -/* SH_XN_ERROR_MASK_XNMD_UCE_ERROR */ -/* Description: XNMD uncorrectable error */ -#define SH_XN_ERROR_MASK_XNMD_UCE_ERROR_SHFT 23 -#define SH_XN_ERROR_MASK_XNMD_UCE_ERROR_MASK 0x0000000000800000 - -/* SH_XN_ERROR_MASK_XNMD_LUT_ERROR */ -/* Description: XNMD look up table error */ -#define SH_XN_ERROR_MASK_XNMD_LUT_ERROR_SHFT 24 -#define SH_XN_ERROR_MASK_XNMD_LUT_ERROR_MASK 0x0000000001000000 - -/* SH_XN_ERROR_MASK_XNPI_CREDIT_OVERFLOW */ -/* Description: XNMD credit overflow */ -#define SH_XN_ERROR_MASK_XNPI_CREDIT_OVERFLOW_SHFT 25 -#define SH_XN_ERROR_MASK_XNPI_CREDIT_OVERFLOW_MASK 0x0000000002000000 - -/* SH_XN_ERROR_MASK_XNPI_DEBIT_OVERFLOW */ -/* Description: XNPI debit overflow */ -#define SH_XN_ERROR_MASK_XNPI_DEBIT_OVERFLOW_SHFT 26 -#define SH_XN_ERROR_MASK_XNPI_DEBIT_OVERFLOW_MASK 0x0000000004000000 - -/* SH_XN_ERROR_MASK_XNPI_DATA_BUFF_OVERFLOW */ -/* Description: XNPI data buffer overflow */ -#define SH_XN_ERROR_MASK_XNPI_DATA_BUFF_OVERFLOW_SHFT 27 -#define SH_XN_ERROR_MASK_XNPI_DATA_BUFF_OVERFLOW_MASK 0x0000000008000000 - -/* SH_XN_ERROR_MASK_XNPI_CREDIT_UNDERFLOW */ -/* Description: XNPI credit underflow */ -#define SH_XN_ERROR_MASK_XNPI_CREDIT_UNDERFLOW_SHFT 28 -#define SH_XN_ERROR_MASK_XNPI_CREDIT_UNDERFLOW_MASK 0x0000000010000000 - -/* SH_XN_ERROR_MASK_XNPI_SBE_ERROR */ -/* Description: XNPI single bit error */ -#define SH_XN_ERROR_MASK_XNPI_SBE_ERROR_SHFT 29 -#define SH_XN_ERROR_MASK_XNPI_SBE_ERROR_MASK 0x0000000020000000 - -/* SH_XN_ERROR_MASK_XNPI_UCE_ERROR */ -/* Description: XNPI uncorrectable error */ -#define SH_XN_ERROR_MASK_XNPI_UCE_ERROR_SHFT 30 -#define SH_XN_ERROR_MASK_XNPI_UCE_ERROR_MASK 0x0000000040000000 - -/* SH_XN_ERROR_MASK_XNPI_LUT_ERROR */ -/* Description: XNPI look up table error */ -#define SH_XN_ERROR_MASK_XNPI_LUT_ERROR_SHFT 31 -#define SH_XN_ERROR_MASK_XNPI_LUT_ERROR_MASK 0x0000000080000000 - -/* SH_XN_ERROR_MASK_IILB_DEBIT_OVERFLOW */ -/* Description: IILB debit overflow */ -#define SH_XN_ERROR_MASK_IILB_DEBIT_OVERFLOW_SHFT 32 -#define SH_XN_ERROR_MASK_IILB_DEBIT_OVERFLOW_MASK 0x0000000100000000 - -/* SH_XN_ERROR_MASK_IILB_CREDIT_OVERFLOW */ -/* Description: IILB credit overflow */ -#define SH_XN_ERROR_MASK_IILB_CREDIT_OVERFLOW_SHFT 33 -#define SH_XN_ERROR_MASK_IILB_CREDIT_OVERFLOW_MASK 0x0000000200000000 - -/* SH_XN_ERROR_MASK_IILB_FIFO_OVERFLOW */ -/* Description: IILB fifo overflow */ -#define SH_XN_ERROR_MASK_IILB_FIFO_OVERFLOW_SHFT 34 -#define SH_XN_ERROR_MASK_IILB_FIFO_OVERFLOW_MASK 0x0000000400000000 - -/* SH_XN_ERROR_MASK_IILB_CREDIT_UNDERFLOW */ -/* Description: IILB credit underflow */ -#define SH_XN_ERROR_MASK_IILB_CREDIT_UNDERFLOW_SHFT 35 -#define SH_XN_ERROR_MASK_IILB_CREDIT_UNDERFLOW_MASK 0x0000000800000000 - -/* SH_XN_ERROR_MASK_IILB_FIFO_UNDERFLOW */ -/* Description: IILB fifo underflow */ -#define SH_XN_ERROR_MASK_IILB_FIFO_UNDERFLOW_SHFT 36 -#define SH_XN_ERROR_MASK_IILB_FIFO_UNDERFLOW_MASK 0x0000001000000000 - -/* SH_XN_ERROR_MASK_IILB_CHIPLET_OR_LUT */ -/* Description: IILB chiplet nomatch or lut read error */ -#define SH_XN_ERROR_MASK_IILB_CHIPLET_OR_LUT_SHFT 37 -#define SH_XN_ERROR_MASK_IILB_CHIPLET_OR_LUT_MASK 0x0000002000000000 - -/* ==================================================================== */ -/* Register "SH_XN_FIRST_ERROR" */ -/* ==================================================================== */ - -#define SH_XN_FIRST_ERROR 0x0000000150040060 -#define SH_XN_FIRST_ERROR_MASK 0x0000003fffffffff -#define SH_XN_FIRST_ERROR_INIT 0x0000003fffffffff - -/* SH_XN_FIRST_ERROR_NI0_POP_OVERFLOW */ -/* Description: NI0 pop overflow */ -#define SH_XN_FIRST_ERROR_NI0_POP_OVERFLOW_SHFT 0 -#define SH_XN_FIRST_ERROR_NI0_POP_OVERFLOW_MASK 0x0000000000000001 - -/* SH_XN_FIRST_ERROR_NI0_PUSH_OVERFLOW */ -/* Description: NI0 push overflow */ -#define SH_XN_FIRST_ERROR_NI0_PUSH_OVERFLOW_SHFT 1 -#define SH_XN_FIRST_ERROR_NI0_PUSH_OVERFLOW_MASK 0x0000000000000002 - -/* SH_XN_FIRST_ERROR_NI0_CREDIT_OVERFLOW */ -/* Description: NI0 credit overflow */ -#define SH_XN_FIRST_ERROR_NI0_CREDIT_OVERFLOW_SHFT 2 -#define SH_XN_FIRST_ERROR_NI0_CREDIT_OVERFLOW_MASK 0x0000000000000004 - -/* SH_XN_FIRST_ERROR_NI0_DEBIT_OVERFLOW */ -/* Description: NI0 debit overflow */ -#define SH_XN_FIRST_ERROR_NI0_DEBIT_OVERFLOW_SHFT 3 -#define SH_XN_FIRST_ERROR_NI0_DEBIT_OVERFLOW_MASK 0x0000000000000008 - -/* SH_XN_FIRST_ERROR_NI0_POP_UNDERFLOW */ -/* Description: NI0 pop underflow */ -#define SH_XN_FIRST_ERROR_NI0_POP_UNDERFLOW_SHFT 4 -#define SH_XN_FIRST_ERROR_NI0_POP_UNDERFLOW_MASK 0x0000000000000010 - -/* SH_XN_FIRST_ERROR_NI0_PUSH_UNDERFLOW */ -/* Description: NI0 push underflow */ -#define SH_XN_FIRST_ERROR_NI0_PUSH_UNDERFLOW_SHFT 5 -#define SH_XN_FIRST_ERROR_NI0_PUSH_UNDERFLOW_MASK 0x0000000000000020 - -/* SH_XN_FIRST_ERROR_NI0_CREDIT_UNDERFLOW */ -/* Description: NI0 credit underflow */ -#define SH_XN_FIRST_ERROR_NI0_CREDIT_UNDERFLOW_SHFT 6 -#define SH_XN_FIRST_ERROR_NI0_CREDIT_UNDERFLOW_MASK 0x0000000000000040 - -/* SH_XN_FIRST_ERROR_NI0_LLP_ERROR */ -/* Description: NI0 llp error */ -#define SH_XN_FIRST_ERROR_NI0_LLP_ERROR_SHFT 7 -#define SH_XN_FIRST_ERROR_NI0_LLP_ERROR_MASK 0x0000000000000080 - -/* SH_XN_FIRST_ERROR_NI0_PIPE_ERROR */ -/* Description: NI0 Pipe in/out errors */ -#define SH_XN_FIRST_ERROR_NI0_PIPE_ERROR_SHFT 8 -#define SH_XN_FIRST_ERROR_NI0_PIPE_ERROR_MASK 0x0000000000000100 - -/* SH_XN_FIRST_ERROR_NI1_POP_OVERFLOW */ -/* Description: NI1 pop overflow */ -#define SH_XN_FIRST_ERROR_NI1_POP_OVERFLOW_SHFT 9 -#define SH_XN_FIRST_ERROR_NI1_POP_OVERFLOW_MASK 0x0000000000000200 - -/* SH_XN_FIRST_ERROR_NI1_PUSH_OVERFLOW */ -/* Description: NI1 push overflow */ -#define SH_XN_FIRST_ERROR_NI1_PUSH_OVERFLOW_SHFT 10 -#define SH_XN_FIRST_ERROR_NI1_PUSH_OVERFLOW_MASK 0x0000000000000400 - -/* SH_XN_FIRST_ERROR_NI1_CREDIT_OVERFLOW */ -/* Description: NI1 credit overflow */ -#define SH_XN_FIRST_ERROR_NI1_CREDIT_OVERFLOW_SHFT 11 -#define SH_XN_FIRST_ERROR_NI1_CREDIT_OVERFLOW_MASK 0x0000000000000800 - -/* SH_XN_FIRST_ERROR_NI1_DEBIT_OVERFLOW */ -/* Description: NI1 debit overflow */ -#define SH_XN_FIRST_ERROR_NI1_DEBIT_OVERFLOW_SHFT 12 -#define SH_XN_FIRST_ERROR_NI1_DEBIT_OVERFLOW_MASK 0x0000000000001000 - -/* SH_XN_FIRST_ERROR_NI1_POP_UNDERFLOW */ -/* Description: NI1 pop underflow */ -#define SH_XN_FIRST_ERROR_NI1_POP_UNDERFLOW_SHFT 13 -#define SH_XN_FIRST_ERROR_NI1_POP_UNDERFLOW_MASK 0x0000000000002000 - -/* SH_XN_FIRST_ERROR_NI1_PUSH_UNDERFLOW */ -/* Description: NI1 push underflow */ -#define SH_XN_FIRST_ERROR_NI1_PUSH_UNDERFLOW_SHFT 14 -#define SH_XN_FIRST_ERROR_NI1_PUSH_UNDERFLOW_MASK 0x0000000000004000 - -/* SH_XN_FIRST_ERROR_NI1_CREDIT_UNDERFLOW */ -/* Description: NI1 credit underflow */ -#define SH_XN_FIRST_ERROR_NI1_CREDIT_UNDERFLOW_SHFT 15 -#define SH_XN_FIRST_ERROR_NI1_CREDIT_UNDERFLOW_MASK 0x0000000000008000 - -/* SH_XN_FIRST_ERROR_NI1_LLP_ERROR */ -/* Description: NI1 llp error */ -#define SH_XN_FIRST_ERROR_NI1_LLP_ERROR_SHFT 16 -#define SH_XN_FIRST_ERROR_NI1_LLP_ERROR_MASK 0x0000000000010000 - -/* SH_XN_FIRST_ERROR_NI1_PIPE_ERROR */ -/* Description: NI1 pipe in/out error */ -#define SH_XN_FIRST_ERROR_NI1_PIPE_ERROR_SHFT 17 -#define SH_XN_FIRST_ERROR_NI1_PIPE_ERROR_MASK 0x0000000000020000 - -/* SH_XN_FIRST_ERROR_XNMD_CREDIT_OVERFLOW */ -/* Description: XNMD credit overflow */ -#define SH_XN_FIRST_ERROR_XNMD_CREDIT_OVERFLOW_SHFT 18 -#define SH_XN_FIRST_ERROR_XNMD_CREDIT_OVERFLOW_MASK 0x0000000000040000 - -/* SH_XN_FIRST_ERROR_XNMD_DEBIT_OVERFLOW */ -/* Description: XNMD debit overflow */ -#define SH_XN_FIRST_ERROR_XNMD_DEBIT_OVERFLOW_SHFT 19 -#define SH_XN_FIRST_ERROR_XNMD_DEBIT_OVERFLOW_MASK 0x0000000000080000 - -/* SH_XN_FIRST_ERROR_XNMD_DATA_BUFF_OVERFLOW */ -/* Description: XNMD data buffer overflow */ -#define SH_XN_FIRST_ERROR_XNMD_DATA_BUFF_OVERFLOW_SHFT 20 -#define SH_XN_FIRST_ERROR_XNMD_DATA_BUFF_OVERFLOW_MASK 0x0000000000100000 - -/* SH_XN_FIRST_ERROR_XNMD_CREDIT_UNDERFLOW */ -/* Description: XNMD credit underflow */ -#define SH_XN_FIRST_ERROR_XNMD_CREDIT_UNDERFLOW_SHFT 21 -#define SH_XN_FIRST_ERROR_XNMD_CREDIT_UNDERFLOW_MASK 0x0000000000200000 - -/* SH_XN_FIRST_ERROR_XNMD_SBE_ERROR */ -/* Description: XNMD single bit error */ -#define SH_XN_FIRST_ERROR_XNMD_SBE_ERROR_SHFT 22 -#define SH_XN_FIRST_ERROR_XNMD_SBE_ERROR_MASK 0x0000000000400000 - -/* SH_XN_FIRST_ERROR_XNMD_UCE_ERROR */ -/* Description: XNMD uncorrectable error */ -#define SH_XN_FIRST_ERROR_XNMD_UCE_ERROR_SHFT 23 -#define SH_XN_FIRST_ERROR_XNMD_UCE_ERROR_MASK 0x0000000000800000 - -/* SH_XN_FIRST_ERROR_XNMD_LUT_ERROR */ -/* Description: XNMD look up table error */ -#define SH_XN_FIRST_ERROR_XNMD_LUT_ERROR_SHFT 24 -#define SH_XN_FIRST_ERROR_XNMD_LUT_ERROR_MASK 0x0000000001000000 - -/* SH_XN_FIRST_ERROR_XNPI_CREDIT_OVERFLOW */ -/* Description: XNMD credit overflow */ -#define SH_XN_FIRST_ERROR_XNPI_CREDIT_OVERFLOW_SHFT 25 -#define SH_XN_FIRST_ERROR_XNPI_CREDIT_OVERFLOW_MASK 0x0000000002000000 - -/* SH_XN_FIRST_ERROR_XNPI_DEBIT_OVERFLOW */ -/* Description: XNPI debit overflow */ -#define SH_XN_FIRST_ERROR_XNPI_DEBIT_OVERFLOW_SHFT 26 -#define SH_XN_FIRST_ERROR_XNPI_DEBIT_OVERFLOW_MASK 0x0000000004000000 - -/* SH_XN_FIRST_ERROR_XNPI_DATA_BUFF_OVERFLOW */ -/* Description: XNPI data buffer overflow */ -#define SH_XN_FIRST_ERROR_XNPI_DATA_BUFF_OVERFLOW_SHFT 27 -#define SH_XN_FIRST_ERROR_XNPI_DATA_BUFF_OVERFLOW_MASK 0x0000000008000000 - -/* SH_XN_FIRST_ERROR_XNPI_CREDIT_UNDERFLOW */ -/* Description: XNPI credit underflow */ -#define SH_XN_FIRST_ERROR_XNPI_CREDIT_UNDERFLOW_SHFT 28 -#define SH_XN_FIRST_ERROR_XNPI_CREDIT_UNDERFLOW_MASK 0x0000000010000000 - -/* SH_XN_FIRST_ERROR_XNPI_SBE_ERROR */ -/* Description: XNPI single bit error */ -#define SH_XN_FIRST_ERROR_XNPI_SBE_ERROR_SHFT 29 -#define SH_XN_FIRST_ERROR_XNPI_SBE_ERROR_MASK 0x0000000020000000 - -/* SH_XN_FIRST_ERROR_XNPI_UCE_ERROR */ -/* Description: XNPI uncorrectable error */ -#define SH_XN_FIRST_ERROR_XNPI_UCE_ERROR_SHFT 30 -#define SH_XN_FIRST_ERROR_XNPI_UCE_ERROR_MASK 0x0000000040000000 - -/* SH_XN_FIRST_ERROR_XNPI_LUT_ERROR */ -/* Description: XNPI look up table error */ -#define SH_XN_FIRST_ERROR_XNPI_LUT_ERROR_SHFT 31 -#define SH_XN_FIRST_ERROR_XNPI_LUT_ERROR_MASK 0x0000000080000000 - -/* SH_XN_FIRST_ERROR_IILB_DEBIT_OVERFLOW */ -/* Description: IILB debit overflow */ -#define SH_XN_FIRST_ERROR_IILB_DEBIT_OVERFLOW_SHFT 32 -#define SH_XN_FIRST_ERROR_IILB_DEBIT_OVERFLOW_MASK 0x0000000100000000 - -/* SH_XN_FIRST_ERROR_IILB_CREDIT_OVERFLOW */ -/* Description: IILB credit overflow */ -#define SH_XN_FIRST_ERROR_IILB_CREDIT_OVERFLOW_SHFT 33 -#define SH_XN_FIRST_ERROR_IILB_CREDIT_OVERFLOW_MASK 0x0000000200000000 - -/* SH_XN_FIRST_ERROR_IILB_FIFO_OVERFLOW */ -/* Description: IILB fifo overflow */ -#define SH_XN_FIRST_ERROR_IILB_FIFO_OVERFLOW_SHFT 34 -#define SH_XN_FIRST_ERROR_IILB_FIFO_OVERFLOW_MASK 0x0000000400000000 - -/* SH_XN_FIRST_ERROR_IILB_CREDIT_UNDERFLOW */ -/* Description: IILB credit underflow */ -#define SH_XN_FIRST_ERROR_IILB_CREDIT_UNDERFLOW_SHFT 35 -#define SH_XN_FIRST_ERROR_IILB_CREDIT_UNDERFLOW_MASK 0x0000000800000000 - -/* SH_XN_FIRST_ERROR_IILB_FIFO_UNDERFLOW */ -/* Description: IILB fifo underflow */ -#define SH_XN_FIRST_ERROR_IILB_FIFO_UNDERFLOW_SHFT 36 -#define SH_XN_FIRST_ERROR_IILB_FIFO_UNDERFLOW_MASK 0x0000001000000000 - -/* SH_XN_FIRST_ERROR_IILB_CHIPLET_OR_LUT */ -/* Description: IILB chiplet nomatch or lut read error */ -#define SH_XN_FIRST_ERROR_IILB_CHIPLET_OR_LUT_SHFT 37 -#define SH_XN_FIRST_ERROR_IILB_CHIPLET_OR_LUT_MASK 0x0000002000000000 - -/* ==================================================================== */ -/* Register "SH_XNIILB_ERROR_SUMMARY" */ -/* ==================================================================== */ - -#define SH_XNIILB_ERROR_SUMMARY 0x0000000150040200 -#define SH_XNIILB_ERROR_SUMMARY_MASK 0xffffffffffffffff -#define SH_XNIILB_ERROR_SUMMARY_INIT 0xffffffffffffffff - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT0 */ -/* Description: II debit0 overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT0_SHFT 0 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT0_MASK 0x0000000000000001 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT2 */ -/* Description: II debit2 overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT2_SHFT 1 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT2_MASK 0x0000000000000002 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT0 */ -/* Description: LB debit0 overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT0_SHFT 2 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT0_MASK 0x0000000000000004 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT2 */ -/* Description: LB debit2 overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT2_SHFT 3 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT2_MASK 0x0000000000000008 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC0 */ -/* Description: II VC0 fifo overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC0_SHFT 4 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC0_MASK 0x0000000000000010 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC2 */ -/* Description: II VC2 fifo overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC2_SHFT 5 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC2_MASK 0x0000000000000020 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC0 */ -/* Description: II VC0 fifo underflow */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC0_SHFT 6 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC0_MASK 0x0000000000000040 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC2 */ -/* Description: II VC2 fifo underflow */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC2_SHFT 7 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC2_MASK 0x0000000000000080 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC0 */ -/* Description: LB VC0 fifo overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC0_SHFT 8 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC0_MASK 0x0000000000000100 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC2 */ -/* Description: LB VC2 fifo overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC2_SHFT 9 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC2_MASK 0x0000000000000200 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC0 */ -/* Description: LB VC0 fifo underflow */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC0_SHFT 10 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC0_MASK 0x0000000000000400 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC2 */ -/* Description: LB VC2 fifo underflow */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC2_SHFT 11 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC2_MASK 0x0000000000000800 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_IN */ -/* Description: PI VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_IN_SHFT 12 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000001000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_IN */ -/* Description: IILB VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_IN_SHFT 13 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000002000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_IN */ -/* Description: MD VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_IN_SHFT 14 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000000004000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_IN */ -/* Description: NI0 VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_IN_SHFT 15 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000000008000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_IN */ -/* Description: NI1 VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_IN_SHFT 16 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000000010000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_IN */ -/* Description: PI VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_IN_SHFT 17 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000000020000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_IN */ -/* Description: IILB VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_IN_SHFT 18 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000000040000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_IN */ -/* Description: MD VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_IN_SHFT 19 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000000080000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_IN */ -/* Description: NI0 VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_IN_SHFT 20 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000000100000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_IN */ -/* Description: NI1 VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_IN_SHFT 21 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000000200000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_IN */ -/* Description: PI VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_IN_SHFT 22 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000400000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_IN */ -/* Description: IILB VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_IN_SHFT 23 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000800000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_IN */ -/* Description: MD VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_IN_SHFT 24 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000001000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_IN */ -/* Description: NI0 VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_IN_SHFT 25 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000002000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_IN */ -/* Description: NI1 VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_IN_SHFT 26 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000004000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_IN */ -/* Description: PI VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_IN_SHFT 27 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000008000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_IN */ -/* Description: IILB VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_IN_SHFT 28 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000010000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_IN */ -/* Description: MD VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_IN_SHFT 29 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000020000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_IN */ -/* Description: NI0 VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_IN_SHFT 30 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000040000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_IN */ -/* Description: NI1 VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_IN_SHFT 31 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000080000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT0 */ -/* Description: PI Fifo Debit0 overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT0_SHFT 32 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT0_MASK 0x0000000100000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT2 */ -/* Description: PI Fifo Debit2 overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT2_SHFT 33 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT2_MASK 0x0000000200000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0 */ -/* Description: IILB Fifo Debit0 overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_SHFT 34 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_MASK 0x0000000400000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2 */ -/* Description: IILB Fifo Debit2 overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_SHFT 35 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_MASK 0x0000000800000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT0 */ -/* Description: MD Fifo Debit0 overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT0_SHFT 36 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT0_MASK 0x0000001000000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT2 */ -/* Description: MD Fifo Debit2 overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT2_SHFT 37 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT2_MASK 0x0000002000000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0 */ -/* Description: NI0 Fifo Debit0 overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_SHFT 38 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_MASK 0x0000004000000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2 */ -/* Description: NI0 Fifo Debit2 overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_SHFT 39 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_MASK 0x0000008000000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0 */ -/* Description: NI1 Fifo Debit0 overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_SHFT 40 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_MASK 0x0000010000000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2 */ -/* Description: NI1 Fifo Debit2 overflow */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_SHFT 41 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_MASK 0x0000020000000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_OUT_SHFT 42 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0000040000000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_OUT_SHFT 43 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0000080000000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_OUT_SHFT 44 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0000100000000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_OUT_SHFT 45 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0000200000000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_OUT_SHFT 46 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0000400000000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_OUT_SHFT 47 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0000800000000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_OUT_SHFT 48 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0001000000000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_OUT_SHFT 49 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0002000000000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_OUT_SHFT 50 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x0004000000000000 - -/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_OUT_SHFT 51 -#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x0008000000000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_OUT_SHFT 52 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0010000000000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_OUT_SHFT 53 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0020000000000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_OUT_SHFT 54 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0040000000000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_OUT_SHFT 55 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0080000000000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_OUT_SHFT 56 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0100000000000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_OUT_SHFT 57 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0200000000000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_OUT_SHFT 58 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0400000000000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_OUT_SHFT 59 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0800000000000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_OUT_SHFT 60 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x1000000000000000 - -/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_OUT_SHFT 61 -#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x2000000000000000 - -/* SH_XNIILB_ERROR_SUMMARY_CHIPLET_NOMATCH */ -/* Description: chiplet nomatch */ -#define SH_XNIILB_ERROR_SUMMARY_CHIPLET_NOMATCH_SHFT 62 -#define SH_XNIILB_ERROR_SUMMARY_CHIPLET_NOMATCH_MASK 0x4000000000000000 - -/* SH_XNIILB_ERROR_SUMMARY_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_XNIILB_ERROR_SUMMARY_LUT_READ_ERROR_SHFT 63 -#define SH_XNIILB_ERROR_SUMMARY_LUT_READ_ERROR_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_XNIILB_ERRORS_ALIAS" */ -/* ==================================================================== */ - -#define SH_XNIILB_ERRORS_ALIAS 0x0000000150040208 - -/* ==================================================================== */ -/* Register "SH_XNIILB_ERROR_OVERFLOW" */ -/* ==================================================================== */ - -#define SH_XNIILB_ERROR_OVERFLOW 0x0000000150040220 -#define SH_XNIILB_ERROR_OVERFLOW_MASK 0xffffffffffffffff -#define SH_XNIILB_ERROR_OVERFLOW_INIT 0xffffffffffffffff - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT0 */ -/* Description: II debit0 overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT0_SHFT 0 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT0_MASK 0x0000000000000001 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT2 */ -/* Description: II debit2 overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT2_SHFT 1 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT2_MASK 0x0000000000000002 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT0 */ -/* Description: LB debit0 overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT0_SHFT 2 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT0_MASK 0x0000000000000004 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT2 */ -/* Description: LB debit2 overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT2_SHFT 3 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT2_MASK 0x0000000000000008 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC0 */ -/* Description: II VC0 fifo overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC0_SHFT 4 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC0_MASK 0x0000000000000010 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC2 */ -/* Description: II VC2 fifo overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC2_SHFT 5 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC2_MASK 0x0000000000000020 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC0 */ -/* Description: II VC0 fifo underflow */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC0_SHFT 6 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC0_MASK 0x0000000000000040 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC2 */ -/* Description: II VC2 fifo underflow */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC2_SHFT 7 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC2_MASK 0x0000000000000080 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC0 */ -/* Description: LB VC0 fifo overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC0_SHFT 8 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC0_MASK 0x0000000000000100 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC2 */ -/* Description: LB VC2 fifo overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC2_SHFT 9 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC2_MASK 0x0000000000000200 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC0 */ -/* Description: LB VC0 fifo underflow */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC0_SHFT 10 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC0_MASK 0x0000000000000400 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC2 */ -/* Description: LB VC2 fifo underflow */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC2_SHFT 11 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC2_MASK 0x0000000000000800 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_IN */ -/* Description: PI VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_IN_SHFT 12 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000001000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_IN */ -/* Description: IILB VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_IN_SHFT 13 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000002000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_IN */ -/* Description: MD VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_IN_SHFT 14 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000000004000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_IN */ -/* Description: NI0 VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_IN_SHFT 15 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000000008000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_IN */ -/* Description: NI1 VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_IN_SHFT 16 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000000010000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_IN */ -/* Description: PI VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_IN_SHFT 17 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000000020000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_IN */ -/* Description: IILB VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_IN_SHFT 18 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000000040000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_IN */ -/* Description: MD VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_IN_SHFT 19 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000000080000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_IN */ -/* Description: NI0 VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_IN_SHFT 20 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000000100000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_IN */ -/* Description: NI1 VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_IN_SHFT 21 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000000200000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_IN */ -/* Description: PI VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_IN_SHFT 22 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000400000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_IN */ -/* Description: IILB VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_IN_SHFT 23 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000800000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_IN */ -/* Description: MD VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_IN_SHFT 24 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000001000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_IN */ -/* Description: NI0 VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_IN_SHFT 25 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000002000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_IN */ -/* Description: NI1 VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_IN_SHFT 26 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000004000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_IN */ -/* Description: PI VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_IN_SHFT 27 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000008000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_IN */ -/* Description: IILB VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_IN_SHFT 28 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000010000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_IN */ -/* Description: MD VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_IN_SHFT 29 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000020000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_IN */ -/* Description: NI0 VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_IN_SHFT 30 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000040000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_IN */ -/* Description: NI1 VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_IN_SHFT 31 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000080000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT0 */ -/* Description: PI Fifo Debit0 overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT0_SHFT 32 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT0_MASK 0x0000000100000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT2 */ -/* Description: PI Fifo Debit2 overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT2_SHFT 33 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT2_MASK 0x0000000200000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0 */ -/* Description: IILB Fifo Debit0 overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_SHFT 34 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_MASK 0x0000000400000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2 */ -/* Description: IILB Fifo Debit2 overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_SHFT 35 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_MASK 0x0000000800000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT0 */ -/* Description: MD Fifo Debit0 overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT0_SHFT 36 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT0_MASK 0x0000001000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT2 */ -/* Description: MD Fifo Debit2 overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT2_SHFT 37 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT2_MASK 0x0000002000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0 */ -/* Description: NI0 Fifo Debit0 overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_SHFT 38 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_MASK 0x0000004000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2 */ -/* Description: NI0 Fifo Debit2 overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_SHFT 39 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_MASK 0x0000008000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0 */ -/* Description: NI1 Fifo Debit0 overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_SHFT 40 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_MASK 0x0000010000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2 */ -/* Description: NI1 Fifo Debit2 overflow */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_SHFT 41 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_MASK 0x0000020000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_OUT_SHFT 42 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0000040000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_OUT_SHFT 43 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0000080000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_OUT_SHFT 44 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0000100000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_OUT_SHFT 45 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0000200000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_OUT_SHFT 46 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0000400000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_OUT_SHFT 47 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0000800000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_OUT_SHFT 48 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0001000000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_OUT_SHFT 49 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0002000000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_OUT_SHFT 50 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x0004000000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_OUT_SHFT 51 -#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x0008000000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_OUT_SHFT 52 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0010000000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_OUT_SHFT 53 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0020000000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_OUT_SHFT 54 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0040000000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_OUT_SHFT 55 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0080000000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_OUT_SHFT 56 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0100000000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_OUT_SHFT 57 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0200000000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_OUT_SHFT 58 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0400000000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_OUT_SHFT 59 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0800000000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_OUT_SHFT 60 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x1000000000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_OUT_SHFT 61 -#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x2000000000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_CHIPLET_NOMATCH */ -/* Description: chiplet nomatch */ -#define SH_XNIILB_ERROR_OVERFLOW_CHIPLET_NOMATCH_SHFT 62 -#define SH_XNIILB_ERROR_OVERFLOW_CHIPLET_NOMATCH_MASK 0x4000000000000000 - -/* SH_XNIILB_ERROR_OVERFLOW_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_XNIILB_ERROR_OVERFLOW_LUT_READ_ERROR_SHFT 63 -#define SH_XNIILB_ERROR_OVERFLOW_LUT_READ_ERROR_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_XNIILB_ERROR_OVERFLOW_ALIAS" */ -/* ==================================================================== */ - -#define SH_XNIILB_ERROR_OVERFLOW_ALIAS 0x0000000150040228 - -/* ==================================================================== */ -/* Register "SH_XNIILB_ERROR_MASK" */ -/* ==================================================================== */ - -#define SH_XNIILB_ERROR_MASK 0x0000000150040240 -#define SH_XNIILB_ERROR_MASK_MASK 0xffffffffffffffff -#define SH_XNIILB_ERROR_MASK_INIT 0xffffffffffffffff - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT0 */ -/* Description: II debit0 overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT0_SHFT 0 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT0_MASK 0x0000000000000001 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT2 */ -/* Description: II debit2 overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT2_SHFT 1 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT2_MASK 0x0000000000000002 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT0 */ -/* Description: LB debit0 overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT0_SHFT 2 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT0_MASK 0x0000000000000004 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT2 */ -/* Description: LB debit2 overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT2_SHFT 3 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT2_MASK 0x0000000000000008 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC0 */ -/* Description: II VC0 fifo overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC0_SHFT 4 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC0_MASK 0x0000000000000010 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC2 */ -/* Description: II VC2 fifo overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC2_SHFT 5 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC2_MASK 0x0000000000000020 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC0 */ -/* Description: II VC0 fifo underflow */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC0_SHFT 6 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC0_MASK 0x0000000000000040 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC2 */ -/* Description: II VC2 fifo underflow */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC2_SHFT 7 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC2_MASK 0x0000000000000080 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC0 */ -/* Description: LB VC0 fifo overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC0_SHFT 8 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC0_MASK 0x0000000000000100 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC2 */ -/* Description: LB VC2 fifo overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC2_SHFT 9 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC2_MASK 0x0000000000000200 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC0 */ -/* Description: LB VC0 fifo underflow */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC0_SHFT 10 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC0_MASK 0x0000000000000400 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC2 */ -/* Description: LB VC2 fifo underflow */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC2_SHFT 11 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC2_MASK 0x0000000000000800 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_IN */ -/* Description: PI VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_IN_SHFT 12 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000001000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_IN */ -/* Description: IILB VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_IN_SHFT 13 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000002000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_IN */ -/* Description: MD VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_IN_SHFT 14 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000000004000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_IN */ -/* Description: NI0 VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_IN_SHFT 15 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000000008000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_IN */ -/* Description: NI1 VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_IN_SHFT 16 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000000010000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_IN */ -/* Description: PI VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_IN_SHFT 17 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000000020000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_IN */ -/* Description: IILB VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_IN_SHFT 18 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000000040000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_IN */ -/* Description: MD VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_IN_SHFT 19 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000000080000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_IN */ -/* Description: NI0 VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_IN_SHFT 20 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000000100000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_IN */ -/* Description: NI1 VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_IN_SHFT 21 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000000200000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_IN */ -/* Description: PI VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_IN_SHFT 22 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000400000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_IN */ -/* Description: IILB VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_IN_SHFT 23 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000800000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_IN */ -/* Description: MD VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_IN_SHFT 24 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000001000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_IN */ -/* Description: NI0 VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_IN_SHFT 25 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000002000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_IN */ -/* Description: NI1 VC0 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_IN_SHFT 26 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000004000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_IN */ -/* Description: PI VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_IN_SHFT 27 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000008000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_IN */ -/* Description: IILB VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_IN_SHFT 28 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000010000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_IN */ -/* Description: MD VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_IN_SHFT 29 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000020000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_IN */ -/* Description: NI0 VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_IN_SHFT 30 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000040000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_IN */ -/* Description: NI1 VC2 credit overflow Pipe In */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_IN_SHFT 31 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000080000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT0 */ -/* Description: PI Fifo Debit0 overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT0_SHFT 32 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT0_MASK 0x0000000100000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT2 */ -/* Description: PI Fifo Debit2 overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT2_SHFT 33 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT2_MASK 0x0000000200000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT0 */ -/* Description: IILB Fifo Debit0 overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT0_SHFT 34 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT0_MASK 0x0000000400000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT2 */ -/* Description: IILB Fifo Debit2 overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT2_SHFT 35 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT2_MASK 0x0000000800000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT0 */ -/* Description: MD Fifo Debit0 overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT0_SHFT 36 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT0_MASK 0x0000001000000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT2 */ -/* Description: MD Fifo Debit2 overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT2_SHFT 37 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT2_MASK 0x0000002000000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT0 */ -/* Description: NI0 Fifo Debit0 overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT0_SHFT 38 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT0_MASK 0x0000004000000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT2 */ -/* Description: NI0 Fifo Debit2 overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT2_SHFT 39 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT2_MASK 0x0000008000000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT0 */ -/* Description: NI1 Fifo Debit0 overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT0_SHFT 40 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT0_MASK 0x0000010000000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT2 */ -/* Description: NI1 Fifo Debit2 overflow */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT2_SHFT 41 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT2_MASK 0x0000020000000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_OUT_SHFT 42 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0000040000000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_OUT_SHFT 43 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0000080000000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_OUT_SHFT 44 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0000100000000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_OUT_SHFT 45 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0000200000000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_OUT_SHFT 46 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0000400000000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_OUT_SHFT 47 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0000800000000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_OUT_SHFT 48 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0001000000000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_OUT_SHFT 49 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0002000000000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_OUT_SHFT 50 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x0004000000000000 - -/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_OUT_SHFT 51 -#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x0008000000000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_OUT_SHFT 52 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0010000000000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_OUT_SHFT 53 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0020000000000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_OUT_SHFT 54 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0040000000000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_OUT_SHFT 55 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0080000000000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_OUT_SHFT 56 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0100000000000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_OUT_SHFT 57 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0200000000000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_OUT_SHFT 58 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0400000000000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_OUT_SHFT 59 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0800000000000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_OUT_SHFT 60 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x1000000000000000 - -/* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_OUT_SHFT 61 -#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x2000000000000000 - -/* SH_XNIILB_ERROR_MASK_CHIPLET_NOMATCH */ -/* Description: chiplet nomatch */ -#define SH_XNIILB_ERROR_MASK_CHIPLET_NOMATCH_SHFT 62 -#define SH_XNIILB_ERROR_MASK_CHIPLET_NOMATCH_MASK 0x4000000000000000 - -/* SH_XNIILB_ERROR_MASK_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_XNIILB_ERROR_MASK_LUT_READ_ERROR_SHFT 63 -#define SH_XNIILB_ERROR_MASK_LUT_READ_ERROR_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_XNIILB_FIRST_ERROR" */ -/* ==================================================================== */ - -#define SH_XNIILB_FIRST_ERROR 0x0000000150040260 -#define SH_XNIILB_FIRST_ERROR_MASK 0xffffffffffffffff -#define SH_XNIILB_FIRST_ERROR_INIT 0xffffffffffffffff - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT0 */ -/* Description: II debit0 overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT0_SHFT 0 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT0_MASK 0x0000000000000001 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT2 */ -/* Description: II debit2 overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT2_SHFT 1 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT2_MASK 0x0000000000000002 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT0 */ -/* Description: LB debit0 overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT0_SHFT 2 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT0_MASK 0x0000000000000004 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT2 */ -/* Description: LB debit2 overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT2_SHFT 3 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT2_MASK 0x0000000000000008 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC0 */ -/* Description: II VC0 fifo overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC0_SHFT 4 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC0_MASK 0x0000000000000010 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC2 */ -/* Description: II VC2 fifo overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC2_SHFT 5 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC2_MASK 0x0000000000000020 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC0 */ -/* Description: II VC0 fifo underflow */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC0_SHFT 6 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC0_MASK 0x0000000000000040 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC2 */ -/* Description: II VC2 fifo underflow */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC2_SHFT 7 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC2_MASK 0x0000000000000080 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC0 */ -/* Description: LB VC0 fifo overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC0_SHFT 8 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC0_MASK 0x0000000000000100 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC2 */ -/* Description: LB VC2 fifo overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC2_SHFT 9 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC2_MASK 0x0000000000000200 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC0 */ -/* Description: LB VC0 fifo underflow */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC0_SHFT 10 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC0_MASK 0x0000000000000400 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC2 */ -/* Description: LB VC2 fifo underflow */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC2_SHFT 11 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC2_MASK 0x0000000000000800 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_IN */ -/* Description: PI VC0 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_IN_SHFT 12 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000001000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_IN */ -/* Description: IILB VC0 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_IN_SHFT 13 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000002000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_IN */ -/* Description: MD VC0 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_IN_SHFT 14 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000000004000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_IN */ -/* Description: NI0 VC0 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_IN_SHFT 15 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000000008000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_IN */ -/* Description: NI1 VC0 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_IN_SHFT 16 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000000010000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_IN */ -/* Description: PI VC2 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_IN_SHFT 17 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000000020000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_IN */ -/* Description: IILB VC2 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_IN_SHFT 18 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000000040000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_IN */ -/* Description: MD VC2 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_IN_SHFT 19 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000000080000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_IN */ -/* Description: NI0 VC2 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_IN_SHFT 20 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000000100000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_IN */ -/* Description: NI1 VC2 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_IN_SHFT 21 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000000200000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_IN */ -/* Description: PI VC0 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_IN_SHFT 22 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000400000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_IN */ -/* Description: IILB VC0 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_IN_SHFT 23 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000800000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_IN */ -/* Description: MD VC0 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_IN_SHFT 24 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000001000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_IN */ -/* Description: NI0 VC0 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_IN_SHFT 25 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000002000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_IN */ -/* Description: NI1 VC0 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_IN_SHFT 26 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000004000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_IN */ -/* Description: PI VC2 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_IN_SHFT 27 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000008000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_IN */ -/* Description: IILB VC2 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_IN_SHFT 28 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000010000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_IN */ -/* Description: MD VC2 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_IN_SHFT 29 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000020000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_IN */ -/* Description: NI0 VC2 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_IN_SHFT 30 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000040000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_IN */ -/* Description: NI1 VC2 credit overflow Pipe In */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_IN_SHFT 31 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000080000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT0 */ -/* Description: PI Fifo Debit0 overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT0_SHFT 32 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT0_MASK 0x0000000100000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT2 */ -/* Description: PI Fifo Debit2 overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT2_SHFT 33 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT2_MASK 0x0000000200000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT0 */ -/* Description: IILB Fifo Debit0 overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_SHFT 34 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_MASK 0x0000000400000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT2 */ -/* Description: IILB Fifo Debit2 overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_SHFT 35 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_MASK 0x0000000800000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT0 */ -/* Description: MD Fifo Debit0 overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT0_SHFT 36 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT0_MASK 0x0000001000000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT2 */ -/* Description: MD Fifo Debit2 overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT2_SHFT 37 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT2_MASK 0x0000002000000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT0 */ -/* Description: NI0 Fifo Debit0 overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_SHFT 38 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_MASK 0x0000004000000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT2 */ -/* Description: NI0 Fifo Debit2 overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_SHFT 39 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_MASK 0x0000008000000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT0 */ -/* Description: NI1 Fifo Debit0 overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_SHFT 40 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_MASK 0x0000010000000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT2 */ -/* Description: NI1 Fifo Debit2 overflow */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_SHFT 41 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_MASK 0x0000020000000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_OUT_SHFT 42 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0000040000000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_OUT_SHFT 43 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0000080000000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_OUT_SHFT 44 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0000100000000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_OUT_SHFT 45 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0000200000000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_OUT_SHFT 46 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0000400000000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_OUT_SHFT 47 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0000800000000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_OUT_SHFT 48 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0001000000000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_OUT_SHFT 49 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0002000000000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_OUT_SHFT 50 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x0004000000000000 - -/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_OUT_SHFT 51 -#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x0008000000000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_OUT_SHFT 52 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0010000000000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_OUT */ -/* Description: PI VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_OUT_SHFT 53 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0020000000000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_OUT_SHFT 54 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0040000000000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_OUT */ -/* Description: MD VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_OUT_SHFT 55 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0080000000000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_OUT_SHFT 56 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0100000000000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_OUT */ -/* Description: IILB VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_OUT_SHFT 57 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0200000000000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_OUT_SHFT 58 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0400000000000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_OUT */ -/* Description: NI0 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_OUT_SHFT 59 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0800000000000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_OUT_SHFT 60 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x1000000000000000 - -/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_OUT */ -/* Description: NI1 VC0 Credit overflow Pipe Out */ -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_OUT_SHFT 61 -#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x2000000000000000 - -/* SH_XNIILB_FIRST_ERROR_CHIPLET_NOMATCH */ -/* Description: chiplet nomatch */ -#define SH_XNIILB_FIRST_ERROR_CHIPLET_NOMATCH_SHFT 62 -#define SH_XNIILB_FIRST_ERROR_CHIPLET_NOMATCH_MASK 0x4000000000000000 - -/* SH_XNIILB_FIRST_ERROR_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_XNIILB_FIRST_ERROR_LUT_READ_ERROR_SHFT 63 -#define SH_XNIILB_FIRST_ERROR_LUT_READ_ERROR_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_XNPI_ERROR_SUMMARY" */ -/* ==================================================================== */ - -#define SH_XNPI_ERROR_SUMMARY 0x0000000150040300 -#define SH_XNPI_ERROR_SUMMARY_MASK 0x0003ffffffffffff -#define SH_XNPI_ERROR_SUMMARY_INIT 0x0003ffffffffffff - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_SHFT 0 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0_SHFT 1 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0_MASK 0x0000000000000002 - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_SHFT 2 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2_SHFT 3 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2_MASK 0x0000000000000008 - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_SHFT 4 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0_SHFT 5 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0_MASK 0x0000000000000020 - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_SHFT 6 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2_SHFT 7 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2_MASK 0x0000000000000080 - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_SHFT 8 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0_SHFT 9 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0_MASK 0x0000000000000200 - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_SHFT 10 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2_SHFT 11 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2_MASK 0x0000000000000800 - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT_SHFT 12 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT_SHFT 13 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000 - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT_SHFT 14 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT_SHFT 15 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0 */ -/* Description: VC0 Data Buffer overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0_SHFT 16 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2 */ -/* Description: VC2 Data Buffer overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2_SHFT 17 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000 - -/* SH_XNPI_ERROR_SUMMARY_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_XNPI_ERROR_SUMMARY_LUT_READ_ERROR_SHFT 18 -#define SH_XNPI_ERROR_SUMMARY_LUT_READ_ERROR_MASK 0x0000000000040000 - -/* SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR0 */ -/* Description: Single Bit Error in Bits 63:0 */ -#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR0_SHFT 19 -#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR0_MASK 0x0000000000080000 - -/* SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR1 */ -/* Description: Single Bit Error in Bits 127:64 */ -#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR1_SHFT 20 -#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR1_MASK 0x0000000000100000 - -/* SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR2 */ -/* Description: Single Bit Error in Bits 191:128 */ -#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR2_SHFT 21 -#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR2_MASK 0x0000000000200000 - -/* SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR3 */ -/* Description: Single Bit Error in Bits 255:192 */ -#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR3_SHFT 22 -#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR3_MASK 0x0000000000400000 - -/* SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR0 */ -/* Description: Uncorrectable Error in Bits 63:0 */ -#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR0_SHFT 23 -#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR0_MASK 0x0000000000800000 - -/* SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR1 */ -/* Description: Uncorrectable Error in Bits 127:64 */ -#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR1_SHFT 24 -#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR1_MASK 0x0000000001000000 - -/* SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR2 */ -/* Description: Uncorrectable Error in Bits 191:128 */ -#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR2_SHFT 25 -#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR2_MASK 0x0000000002000000 - -/* SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR3 */ -/* Description: Uncorrectable Error in Bits 255:192 */ -#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR3_SHFT 26 -#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR3_MASK 0x0000000004000000 - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0_SHFT 27 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0_SHFT 28 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000 - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2_SHFT 29 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2_SHFT 30 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0 */ -/* Description: NI0 Debit 0 Overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_SHFT 31 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2 */ -/* Description: NI0 Debit 2 Overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_SHFT 32 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0 */ -/* Description: NI1 Debit 0 Overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_SHFT 33 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2 */ -/* Description: NI1 Debit 2 Overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_SHFT 34 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0 */ -/* Description: IILB Debit 0 Overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_SHFT 35 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2 */ -/* Description: IILB Debit 2 Overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_SHFT 36 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000 - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_SHFT 38 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000 - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_SHFT 40 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000 - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_SHFT 42 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000 - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_SHFT 44 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000 - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_SHFT 46 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Underflow */ -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47 -#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_SHFT 48 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000 - -/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO */ -/* Description: Header Cancel Fifo Overflow */ -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49 -#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000 - -/* ==================================================================== */ -/* Register "SH_XNPI_ERRORS_ALIAS" */ -/* ==================================================================== */ - -#define SH_XNPI_ERRORS_ALIAS 0x0000000150040308 - -/* ==================================================================== */ -/* Register "SH_XNPI_ERROR_OVERFLOW" */ -/* ==================================================================== */ - -#define SH_XNPI_ERROR_OVERFLOW 0x0000000150040320 -#define SH_XNPI_ERROR_OVERFLOW_MASK 0x0003ffffffffffff -#define SH_XNPI_ERROR_OVERFLOW_INIT 0x0003ffffffffffff - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_SHFT 0 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_SHFT 1 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_MASK 0x0000000000000002 - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_SHFT 2 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_SHFT 3 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_MASK 0x0000000000000008 - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_SHFT 4 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_SHFT 5 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_MASK 0x0000000000000020 - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_SHFT 6 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_SHFT 7 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_MASK 0x0000000000000080 - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_SHFT 8 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_SHFT 9 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_MASK 0x0000000000000200 - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_SHFT 10 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_SHFT 11 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_MASK 0x0000000000000800 - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT_SHFT 12 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT_SHFT 13 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000 - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT_SHFT 14 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT_SHFT 15 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0 */ -/* Description: VC0 Data Buffer overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0_SHFT 16 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2 */ -/* Description: VC2 Data Buffer overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2_SHFT 17 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000 - -/* SH_XNPI_ERROR_OVERFLOW_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_XNPI_ERROR_OVERFLOW_LUT_READ_ERROR_SHFT 18 -#define SH_XNPI_ERROR_OVERFLOW_LUT_READ_ERROR_MASK 0x0000000000040000 - -/* SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR0 */ -/* Description: Single Bit Error in Bits 63:0 */ -#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR0_SHFT 19 -#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR0_MASK 0x0000000000080000 - -/* SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR1 */ -/* Description: Single Bit Error in Bits 127:64 */ -#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR1_SHFT 20 -#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR1_MASK 0x0000000000100000 - -/* SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR2 */ -/* Description: Single Bit Error in Bits 191:128 */ -#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR2_SHFT 21 -#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR2_MASK 0x0000000000200000 - -/* SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR3 */ -/* Description: Single Bit Error in Bits 255:192 */ -#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR3_SHFT 22 -#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR3_MASK 0x0000000000400000 - -/* SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR0 */ -/* Description: Uncorrectable Error in Bits 63:0 */ -#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR0_SHFT 23 -#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR0_MASK 0x0000000000800000 - -/* SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR1 */ -/* Description: Uncorrectable Error in Bits 127:64 */ -#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR1_SHFT 24 -#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR1_MASK 0x0000000001000000 - -/* SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR2 */ -/* Description: Uncorrectable Error in Bits 191:128 */ -#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR2_SHFT 25 -#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR2_MASK 0x0000000002000000 - -/* SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR3 */ -/* Description: Uncorrectable Error in Bits 255:192 */ -#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR3_SHFT 26 -#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR3_MASK 0x0000000004000000 - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0_SHFT 27 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0_SHFT 28 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000 - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2_SHFT 29 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2_SHFT 30 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0 */ -/* Description: NI0 Debit 0 Overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_SHFT 31 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2 */ -/* Description: NI0 Debit 2 Overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_SHFT 32 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0 */ -/* Description: NI1 Debit 0 Overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_SHFT 33 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2 */ -/* Description: NI1 Debit 2 Overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_SHFT 34 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0 */ -/* Description: IILB Debit 0 Overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_SHFT 35 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2 */ -/* Description: IILB Debit 2 Overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_SHFT 36 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000 - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_SHFT 38 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000 - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_SHFT 40 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000 - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_SHFT 42 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000 - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_SHFT 44 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000 - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_SHFT 46 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Underflow */ -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47 -#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_SHFT 48 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000 - -/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO */ -/* Description: Header Cancel Fifo Overflow */ -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49 -#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000 - -/* ==================================================================== */ -/* Register "SH_XNPI_ERROR_OVERFLOW_ALIAS" */ -/* ==================================================================== */ - -#define SH_XNPI_ERROR_OVERFLOW_ALIAS 0x0000000150040328 - -/* ==================================================================== */ -/* Register "SH_XNPI_ERROR_MASK" */ -/* ==================================================================== */ - -#define SH_XNPI_ERROR_MASK 0x0000000150040340 -#define SH_XNPI_ERROR_MASK_MASK 0x0003ffffffffffff -#define SH_XNPI_ERROR_MASK_INIT 0x0003ffffffffffff - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0_SHFT 0 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0_SHFT 1 -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0_MASK 0x0000000000000002 - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2_SHFT 2 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2_SHFT 3 -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2_MASK 0x0000000000000008 - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0_SHFT 4 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0_SHFT 5 -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0_MASK 0x0000000000000020 - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2_SHFT 6 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2_SHFT 7 -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2_MASK 0x0000000000000080 - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0_SHFT 8 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0_SHFT 9 -#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0_MASK 0x0000000000000200 - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2_SHFT 10 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2_SHFT 11 -#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2_MASK 0x0000000000000800 - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_VC0_CREDIT_SHFT 12 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_VC0_CREDIT_SHFT 13 -#define SH_XNPI_ERROR_MASK_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000 - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_VC2_CREDIT_SHFT 14 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_VC2_CREDIT_SHFT 15 -#define SH_XNPI_ERROR_MASK_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC0 */ -/* Description: VC0 Data Buffer overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC0_SHFT 16 -#define SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC2 */ -/* Description: VC2 Data Buffer overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC2_SHFT 17 -#define SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000 - -/* SH_XNPI_ERROR_MASK_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_XNPI_ERROR_MASK_LUT_READ_ERROR_SHFT 18 -#define SH_XNPI_ERROR_MASK_LUT_READ_ERROR_MASK 0x0000000000040000 - -/* SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR0 */ -/* Description: Single Bit Error in Bits 63:0 */ -#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR0_SHFT 19 -#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR0_MASK 0x0000000000080000 - -/* SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR1 */ -/* Description: Single Bit Error in Bits 127:64 */ -#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR1_SHFT 20 -#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR1_MASK 0x0000000000100000 - -/* SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR2 */ -/* Description: Single Bit Error in Bits 191:128 */ -#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR2_SHFT 21 -#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR2_MASK 0x0000000000200000 - -/* SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR3 */ -/* Description: Single Bit Error in Bits 255:192 */ -#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR3_SHFT 22 -#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR3_MASK 0x0000000000400000 - -/* SH_XNPI_ERROR_MASK_UNCOR_ERROR0 */ -/* Description: Uncorrectable Error in Bits 63:0 */ -#define SH_XNPI_ERROR_MASK_UNCOR_ERROR0_SHFT 23 -#define SH_XNPI_ERROR_MASK_UNCOR_ERROR0_MASK 0x0000000000800000 - -/* SH_XNPI_ERROR_MASK_UNCOR_ERROR1 */ -/* Description: Uncorrectable Error in Bits 127:64 */ -#define SH_XNPI_ERROR_MASK_UNCOR_ERROR1_SHFT 24 -#define SH_XNPI_ERROR_MASK_UNCOR_ERROR1_MASK 0x0000000001000000 - -/* SH_XNPI_ERROR_MASK_UNCOR_ERROR2 */ -/* Description: Uncorrectable Error in Bits 191:128 */ -#define SH_XNPI_ERROR_MASK_UNCOR_ERROR2_SHFT 25 -#define SH_XNPI_ERROR_MASK_UNCOR_ERROR2_MASK 0x0000000002000000 - -/* SH_XNPI_ERROR_MASK_UNCOR_ERROR3 */ -/* Description: Uncorrectable Error in Bits 255:192 */ -#define SH_XNPI_ERROR_MASK_UNCOR_ERROR3_SHFT 26 -#define SH_XNPI_ERROR_MASK_UNCOR_ERROR3_MASK 0x0000000004000000 - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR0_SHFT 27 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR0_SHFT 28 -#define SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000 - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR2_SHFT 29 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR2_SHFT 30 -#define SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT0 */ -/* Description: NI0 Debit 0 Overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT0_SHFT 31 -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT2 */ -/* Description: NI0 Debit 2 Overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT2_SHFT 32 -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT0 */ -/* Description: NI1 Debit 0 Overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT0_SHFT 33 -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT2 */ -/* Description: NI1 Debit 2 Overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT2_SHFT 34 -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT0 */ -/* Description: IILB Debit 0 Overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT0_SHFT 35 -#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT2 */ -/* Description: IILB Debit 2 Overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT2_SHFT 36 -#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000 - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_SHFT 38 -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000 - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_SHFT 40 -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000 - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_SHFT 42 -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000 - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_SHFT 44 -#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000 - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_SHFT 46 -#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Underflow */ -#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47 -#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_SHFT 48 -#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000 - -/* SH_XNPI_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO */ -/* Description: Header Cancel Fifo Overflow */ -#define SH_XNPI_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49 -#define SH_XNPI_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000 - -/* ==================================================================== */ -/* Register "SH_XNPI_FIRST_ERROR" */ -/* ==================================================================== */ - -#define SH_XNPI_FIRST_ERROR 0x0000000150040360 -#define SH_XNPI_FIRST_ERROR_MASK 0x0003ffffffffffff -#define SH_XNPI_FIRST_ERROR_INIT 0x0003ffffffffffff - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0_SHFT 0 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0_SHFT 1 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0_MASK 0x0000000000000002 - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2_SHFT 2 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2_SHFT 3 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2_MASK 0x0000000000000008 - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0_SHFT 4 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0_SHFT 5 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0_MASK 0x0000000000000020 - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2_SHFT 6 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2_SHFT 7 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2_MASK 0x0000000000000080 - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0_SHFT 8 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0_SHFT 9 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0_MASK 0x0000000000000200 - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2_SHFT 10 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2_SHFT 11 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2_MASK 0x0000000000000800 - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_VC0_CREDIT_SHFT 12 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_VC0_CREDIT_SHFT 13 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000 - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_VC2_CREDIT_SHFT 14 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_VC2_CREDIT_SHFT 15 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC0 */ -/* Description: VC0 Data Buffer overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC0_SHFT 16 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC2 */ -/* Description: VC2 Data Buffer overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC2_SHFT 17 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000 - -/* SH_XNPI_FIRST_ERROR_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_XNPI_FIRST_ERROR_LUT_READ_ERROR_SHFT 18 -#define SH_XNPI_FIRST_ERROR_LUT_READ_ERROR_MASK 0x0000000000040000 - -/* SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR0 */ -/* Description: Single Bit Error in Bits 63:0 */ -#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR0_SHFT 19 -#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR0_MASK 0x0000000000080000 - -/* SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR1 */ -/* Description: Single Bit Error in Bits 127:64 */ -#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR1_SHFT 20 -#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR1_MASK 0x0000000000100000 - -/* SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR2 */ -/* Description: Single Bit Error in Bits 191:128 */ -#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR2_SHFT 21 -#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR2_MASK 0x0000000000200000 - -/* SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR3 */ -/* Description: Single Bit Error in Bits 255:192 */ -#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR3_SHFT 22 -#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR3_MASK 0x0000000000400000 - -/* SH_XNPI_FIRST_ERROR_UNCOR_ERROR0 */ -/* Description: Uncorrectable Error in Bits 63:0 */ -#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR0_SHFT 23 -#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR0_MASK 0x0000000000800000 - -/* SH_XNPI_FIRST_ERROR_UNCOR_ERROR1 */ -/* Description: Uncorrectable Error in Bits 127:64 */ -#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR1_SHFT 24 -#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR1_MASK 0x0000000001000000 - -/* SH_XNPI_FIRST_ERROR_UNCOR_ERROR2 */ -/* Description: Uncorrectable Error in Bits 191:128 */ -#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR2_SHFT 25 -#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR2_MASK 0x0000000002000000 - -/* SH_XNPI_FIRST_ERROR_UNCOR_ERROR3 */ -/* Description: Uncorrectable Error in Bits 255:192 */ -#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR3_SHFT 26 -#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR3_MASK 0x0000000004000000 - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR0_SHFT 27 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR0_SHFT 28 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000 - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR2_SHFT 29 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR2_SHFT 30 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT0 */ -/* Description: NI0 Debit 0 Overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_SHFT 31 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT2 */ -/* Description: NI0 Debit 2 Overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_SHFT 32 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT0 */ -/* Description: NI1 Debit 0 Overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_SHFT 33 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT2 */ -/* Description: NI1 Debit 2 Overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_SHFT 34 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT0 */ -/* Description: IILB Debit 0 Overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_SHFT 35 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT2 */ -/* Description: IILB Debit 2 Overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_SHFT 36 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000 - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_SHFT 38 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000 - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_SHFT 40 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000 - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_SHFT 42 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000 - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_SHFT 44 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000 - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_SHFT 46 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Underflow */ -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47 -#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_SHFT 48 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000 - -/* SH_XNPI_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO */ -/* Description: Header Cancel Fifo Overflow */ -#define SH_XNPI_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49 -#define SH_XNPI_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000 - -/* ==================================================================== */ -/* Register "SH_XNMD_ERROR_SUMMARY" */ -/* ==================================================================== */ - -#define SH_XNMD_ERROR_SUMMARY 0x0000000150040400 -#define SH_XNMD_ERROR_SUMMARY_MASK 0x0003ffffffffffff -#define SH_XNMD_ERROR_SUMMARY_INIT 0x0003ffffffffffff - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_SHFT 0 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0_SHFT 1 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0_MASK 0x0000000000000002 - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_SHFT 2 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2_SHFT 3 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2_MASK 0x0000000000000008 - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_SHFT 4 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0_SHFT 5 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0_MASK 0x0000000000000020 - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_SHFT 6 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2_SHFT 7 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2_MASK 0x0000000000000080 - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_SHFT 8 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0_SHFT 9 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0_MASK 0x0000000000000200 - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_SHFT 10 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2_SHFT 11 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2_MASK 0x0000000000000800 - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT_SHFT 12 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT_SHFT 13 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000 - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT_SHFT 14 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT_SHFT 15 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0 */ -/* Description: VC0 Data Buffer overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0_SHFT 16 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2 */ -/* Description: VC2 Data Buffer overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2_SHFT 17 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000 - -/* SH_XNMD_ERROR_SUMMARY_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_XNMD_ERROR_SUMMARY_LUT_READ_ERROR_SHFT 18 -#define SH_XNMD_ERROR_SUMMARY_LUT_READ_ERROR_MASK 0x0000000000040000 - -/* SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR0 */ -/* Description: Single Bit Error in Bits 63:0 */ -#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR0_SHFT 19 -#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR0_MASK 0x0000000000080000 - -/* SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR1 */ -/* Description: Single Bit Error in Bits 127:64 */ -#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR1_SHFT 20 -#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR1_MASK 0x0000000000100000 - -/* SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR2 */ -/* Description: Single Bit Error in Bits 191:128 */ -#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR2_SHFT 21 -#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR2_MASK 0x0000000000200000 - -/* SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR3 */ -/* Description: Single Bit Error in Bits 255:192 */ -#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR3_SHFT 22 -#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR3_MASK 0x0000000000400000 - -/* SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR0 */ -/* Description: Uncorrectable Error in Bits 63:0 */ -#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR0_SHFT 23 -#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR0_MASK 0x0000000000800000 - -/* SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR1 */ -/* Description: Uncorrectable Error in Bits 127:64 */ -#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR1_SHFT 24 -#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR1_MASK 0x0000000001000000 - -/* SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR2 */ -/* Description: Uncorrectable Error in Bits 191:128 */ -#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR2_SHFT 25 -#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR2_MASK 0x0000000002000000 - -/* SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR3 */ -/* Description: Uncorrectable Error in Bits 255:192 */ -#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR3_SHFT 26 -#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR3_MASK 0x0000000004000000 - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0_SHFT 27 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0_SHFT 28 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000 - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2_SHFT 29 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2_SHFT 30 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0 */ -/* Description: NI0 Debit 0 Overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_SHFT 31 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2 */ -/* Description: NI0 Debit 2 Overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_SHFT 32 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0 */ -/* Description: NI1 Debit 0 Overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_SHFT 33 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2 */ -/* Description: NI1 Debit 2 Overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_SHFT 34 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0 */ -/* Description: IILB Debit 0 Overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_SHFT 35 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2 */ -/* Description: IILB Debit 2 Overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_SHFT 36 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000 - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_SHFT 38 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000 - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_SHFT 40 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000 - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_SHFT 42 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000 - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_SHFT 44 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000 - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_SHFT 46 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Underflow */ -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47 -#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_SHFT 48 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000 - -/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO */ -/* Description: Header Cancel Fifo Overflow */ -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49 -#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000 - -/* ==================================================================== */ -/* Register "SH_XNMD_ERRORS_ALIAS" */ -/* ==================================================================== */ - -#define SH_XNMD_ERRORS_ALIAS 0x0000000150040408 - -/* ==================================================================== */ -/* Register "SH_XNMD_ERROR_OVERFLOW" */ -/* ==================================================================== */ - -#define SH_XNMD_ERROR_OVERFLOW 0x0000000150040420 -#define SH_XNMD_ERROR_OVERFLOW_MASK 0x0003ffffffffffff -#define SH_XNMD_ERROR_OVERFLOW_INIT 0x0003ffffffffffff - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_SHFT 0 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_SHFT 1 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_MASK 0x0000000000000002 - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_SHFT 2 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_SHFT 3 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_MASK 0x0000000000000008 - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_SHFT 4 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_SHFT 5 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_MASK 0x0000000000000020 - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_SHFT 6 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_SHFT 7 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_MASK 0x0000000000000080 - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_SHFT 8 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_SHFT 9 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_MASK 0x0000000000000200 - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_SHFT 10 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_SHFT 11 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_MASK 0x0000000000000800 - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT_SHFT 12 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT_SHFT 13 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000 - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT_SHFT 14 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT_SHFT 15 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0 */ -/* Description: VC0 Data Buffer overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0_SHFT 16 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2 */ -/* Description: VC2 Data Buffer overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2_SHFT 17 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000 - -/* SH_XNMD_ERROR_OVERFLOW_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_XNMD_ERROR_OVERFLOW_LUT_READ_ERROR_SHFT 18 -#define SH_XNMD_ERROR_OVERFLOW_LUT_READ_ERROR_MASK 0x0000000000040000 - -/* SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR0 */ -/* Description: Single Bit Error in Bits 63:0 */ -#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR0_SHFT 19 -#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR0_MASK 0x0000000000080000 - -/* SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR1 */ -/* Description: Single Bit Error in Bits 127:64 */ -#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR1_SHFT 20 -#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR1_MASK 0x0000000000100000 - -/* SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR2 */ -/* Description: Single Bit Error in Bits 191:128 */ -#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR2_SHFT 21 -#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR2_MASK 0x0000000000200000 - -/* SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR3 */ -/* Description: Single Bit Error in Bits 255:192 */ -#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR3_SHFT 22 -#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR3_MASK 0x0000000000400000 - -/* SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR0 */ -/* Description: Uncorrectable Error in Bits 63:0 */ -#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR0_SHFT 23 -#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR0_MASK 0x0000000000800000 - -/* SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR1 */ -/* Description: Uncorrectable Error in Bits 127:64 */ -#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR1_SHFT 24 -#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR1_MASK 0x0000000001000000 - -/* SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR2 */ -/* Description: Uncorrectable Error in Bits 191:128 */ -#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR2_SHFT 25 -#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR2_MASK 0x0000000002000000 - -/* SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR3 */ -/* Description: Uncorrectable Error in Bits 255:192 */ -#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR3_SHFT 26 -#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR3_MASK 0x0000000004000000 - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0_SHFT 27 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0_SHFT 28 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000 - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2_SHFT 29 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2_SHFT 30 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0 */ -/* Description: NI0 Debit 0 Overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_SHFT 31 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2 */ -/* Description: NI0 Debit 2 Overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_SHFT 32 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0 */ -/* Description: NI1 Debit 0 Overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_SHFT 33 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2 */ -/* Description: NI1 Debit 2 Overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_SHFT 34 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0 */ -/* Description: IILB Debit 0 Overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_SHFT 35 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2 */ -/* Description: IILB Debit 2 Overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_SHFT 36 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000 - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_SHFT 38 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000 - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_SHFT 40 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000 - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_SHFT 42 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000 - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_SHFT 44 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000 - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_SHFT 46 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Underflow */ -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47 -#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_SHFT 48 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000 - -/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO */ -/* Description: Header Cancel Fifo Overflow */ -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49 -#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000 - -/* ==================================================================== */ -/* Register "SH_XNMD_ERROR_OVERFLOW_ALIAS" */ -/* ==================================================================== */ - -#define SH_XNMD_ERROR_OVERFLOW_ALIAS 0x0000000150040428 - -/* ==================================================================== */ -/* Register "SH_XNMD_ERROR_MASK" */ -/* ==================================================================== */ - -#define SH_XNMD_ERROR_MASK 0x0000000150040440 -#define SH_XNMD_ERROR_MASK_MASK 0x0003ffffffffffff -#define SH_XNMD_ERROR_MASK_INIT 0x0003ffffffffffff - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0_SHFT 0 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0_SHFT 1 -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0_MASK 0x0000000000000002 - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2_SHFT 2 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2_SHFT 3 -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2_MASK 0x0000000000000008 - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0_SHFT 4 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0_SHFT 5 -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0_MASK 0x0000000000000020 - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2_SHFT 6 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2_SHFT 7 -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2_MASK 0x0000000000000080 - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0_SHFT 8 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0_SHFT 9 -#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0_MASK 0x0000000000000200 - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2_SHFT 10 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2_SHFT 11 -#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2_MASK 0x0000000000000800 - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_VC0_CREDIT_SHFT 12 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_VC0_CREDIT_SHFT 13 -#define SH_XNMD_ERROR_MASK_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000 - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_VC2_CREDIT_SHFT 14 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_VC2_CREDIT_SHFT 15 -#define SH_XNMD_ERROR_MASK_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC0 */ -/* Description: VC0 Data Buffer overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC0_SHFT 16 -#define SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC2 */ -/* Description: VC2 Data Buffer overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC2_SHFT 17 -#define SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000 - -/* SH_XNMD_ERROR_MASK_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_XNMD_ERROR_MASK_LUT_READ_ERROR_SHFT 18 -#define SH_XNMD_ERROR_MASK_LUT_READ_ERROR_MASK 0x0000000000040000 - -/* SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR0 */ -/* Description: Single Bit Error in Bits 63:0 */ -#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR0_SHFT 19 -#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR0_MASK 0x0000000000080000 - -/* SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR1 */ -/* Description: Single Bit Error in Bits 127:64 */ -#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR1_SHFT 20 -#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR1_MASK 0x0000000000100000 - -/* SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR2 */ -/* Description: Single Bit Error in Bits 191:128 */ -#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR2_SHFT 21 -#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR2_MASK 0x0000000000200000 - -/* SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR3 */ -/* Description: Single Bit Error in Bits 255:192 */ -#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR3_SHFT 22 -#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR3_MASK 0x0000000000400000 - -/* SH_XNMD_ERROR_MASK_UNCOR_ERROR0 */ -/* Description: Uncorrectable Error in Bits 63:0 */ -#define SH_XNMD_ERROR_MASK_UNCOR_ERROR0_SHFT 23 -#define SH_XNMD_ERROR_MASK_UNCOR_ERROR0_MASK 0x0000000000800000 - -/* SH_XNMD_ERROR_MASK_UNCOR_ERROR1 */ -/* Description: Uncorrectable Error in Bits 127:64 */ -#define SH_XNMD_ERROR_MASK_UNCOR_ERROR1_SHFT 24 -#define SH_XNMD_ERROR_MASK_UNCOR_ERROR1_MASK 0x0000000001000000 - -/* SH_XNMD_ERROR_MASK_UNCOR_ERROR2 */ -/* Description: Uncorrectable Error in Bits 191:128 */ -#define SH_XNMD_ERROR_MASK_UNCOR_ERROR2_SHFT 25 -#define SH_XNMD_ERROR_MASK_UNCOR_ERROR2_MASK 0x0000000002000000 - -/* SH_XNMD_ERROR_MASK_UNCOR_ERROR3 */ -/* Description: Uncorrectable Error in Bits 255:192 */ -#define SH_XNMD_ERROR_MASK_UNCOR_ERROR3_SHFT 26 -#define SH_XNMD_ERROR_MASK_UNCOR_ERROR3_MASK 0x0000000004000000 - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR0_SHFT 27 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR0_SHFT 28 -#define SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000 - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR2_SHFT 29 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR2_SHFT 30 -#define SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT0 */ -/* Description: NI0 Debit 0 Overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT0_SHFT 31 -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT2 */ -/* Description: NI0 Debit 2 Overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT2_SHFT 32 -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT0 */ -/* Description: NI1 Debit 0 Overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT0_SHFT 33 -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT2 */ -/* Description: NI1 Debit 2 Overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT2_SHFT 34 -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT0 */ -/* Description: IILB Debit 0 Overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT0_SHFT 35 -#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT2 */ -/* Description: IILB Debit 2 Overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT2_SHFT 36 -#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000 - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_SHFT 38 -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000 - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_SHFT 40 -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000 - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_SHFT 42 -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000 - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_SHFT 44 -#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000 - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_SHFT 46 -#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Underflow */ -#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47 -#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_SHFT 48 -#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000 - -/* SH_XNMD_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO */ -/* Description: Header Cancel Fifo Overflow */ -#define SH_XNMD_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49 -#define SH_XNMD_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000 - -/* ==================================================================== */ -/* Register "SH_XNMD_FIRST_ERROR" */ -/* ==================================================================== */ - -#define SH_XNMD_FIRST_ERROR 0x0000000150040460 -#define SH_XNMD_FIRST_ERROR_MASK 0x0003ffffffffffff -#define SH_XNMD_FIRST_ERROR_INIT 0x0003ffffffffffff - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0_SHFT 0 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0 */ -/* Description: NI0 VC0 fifo overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0_SHFT 1 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0_MASK 0x0000000000000002 - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2_SHFT 2 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2 */ -/* Description: NI0 VC2 fifo overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2_SHFT 3 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2_MASK 0x0000000000000008 - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0_SHFT 4 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0 */ -/* Description: NI1 VC0 fifo overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0_SHFT 5 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0_MASK 0x0000000000000020 - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2_SHFT 6 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2 */ -/* Description: NI1 VC2 fifo overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2_SHFT 7 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2_MASK 0x0000000000000080 - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0_SHFT 8 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0 */ -/* Description: IILB VC0 fifo overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0_SHFT 9 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0_MASK 0x0000000000000200 - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2_SHFT 10 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2 */ -/* Description: IILB VC2 fifo overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2_SHFT 11 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2_MASK 0x0000000000000800 - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_VC0_CREDIT_SHFT 12 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_VC0_CREDIT */ -/* Description: VC0 Credit overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_VC0_CREDIT_SHFT 13 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000 - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_VC2_CREDIT_SHFT 14 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_VC2_CREDIT */ -/* Description: VC2 Credit overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_VC2_CREDIT_SHFT 15 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC0 */ -/* Description: VC0 Data Buffer overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC0_SHFT 16 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC2 */ -/* Description: VC2 Data Buffer overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC2_SHFT 17 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000 - -/* SH_XNMD_FIRST_ERROR_LUT_READ_ERROR */ -/* Description: LUT Read Error */ -#define SH_XNMD_FIRST_ERROR_LUT_READ_ERROR_SHFT 18 -#define SH_XNMD_FIRST_ERROR_LUT_READ_ERROR_MASK 0x0000000000040000 - -/* SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR0 */ -/* Description: Single Bit Error in Bits 63:0 */ -#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR0_SHFT 19 -#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR0_MASK 0x0000000000080000 - -/* SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR1 */ -/* Description: Single Bit Error in Bits 127:64 */ -#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR1_SHFT 20 -#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR1_MASK 0x0000000000100000 - -/* SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR2 */ -/* Description: Single Bit Error in Bits 191:128 */ -#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR2_SHFT 21 -#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR2_MASK 0x0000000000200000 - -/* SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR3 */ -/* Description: Single Bit Error in Bits 255:192 */ -#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR3_SHFT 22 -#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR3_MASK 0x0000000000400000 - -/* SH_XNMD_FIRST_ERROR_UNCOR_ERROR0 */ -/* Description: Uncorrectable Error in Bits 63:0 */ -#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR0_SHFT 23 -#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR0_MASK 0x0000000000800000 - -/* SH_XNMD_FIRST_ERROR_UNCOR_ERROR1 */ -/* Description: Uncorrectable Error in Bits 127:64 */ -#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR1_SHFT 24 -#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR1_MASK 0x0000000001000000 - -/* SH_XNMD_FIRST_ERROR_UNCOR_ERROR2 */ -/* Description: Uncorrectable Error in Bits 191:128 */ -#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR2_SHFT 25 -#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR2_MASK 0x0000000002000000 - -/* SH_XNMD_FIRST_ERROR_UNCOR_ERROR3 */ -/* Description: Uncorrectable Error in Bits 255:192 */ -#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR3_SHFT 26 -#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR3_MASK 0x0000000004000000 - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR0_SHFT 27 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR0 */ -/* Description: SIC Counter 0 Overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR0_SHFT 28 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000 - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR2_SHFT 29 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR2 */ -/* Description: SIC Counter 2 Overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR2_SHFT 30 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT0 */ -/* Description: NI0 Debit 0 Overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_SHFT 31 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT2 */ -/* Description: NI0 Debit 2 Overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_SHFT 32 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT0 */ -/* Description: NI1 Debit 0 Overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_SHFT 33 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT2 */ -/* Description: NI1 Debit 2 Overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_SHFT 34 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT0 */ -/* Description: IILB Debit 0 Overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_SHFT 35 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT2 */ -/* Description: IILB Debit 2 Overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_SHFT 36 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000 - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT */ -/* Description: NI0 VC0 Credit Overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_SHFT 38 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000 - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT */ -/* Description: NI0 VC2 Credit Overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_SHFT 40 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000 - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT */ -/* Description: NI1 VC0 Credit Overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_SHFT 42 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000 - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT */ -/* Description: NI1 VC2 Credit Overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_SHFT 44 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000 - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT */ -/* Description: IILB VC0 Credit Overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_SHFT 46 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000 - -/* SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Underflow */ -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47 -#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT */ -/* Description: IILB VC2 Credit Overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_SHFT 48 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000 - -/* SH_XNMD_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO */ -/* Description: Header Cancel Fifo Overflow */ -#define SH_XNMD_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49 -#define SH_XNMD_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000 - -/* ==================================================================== */ -/* Register "SH_AUTO_REPLY_ENABLE0" */ -/* Automatic Maintenance Reply Enable 0 */ -/* ==================================================================== */ - -#define SH_AUTO_REPLY_ENABLE0 0x0000000110061000 -#define SH_AUTO_REPLY_ENABLE0_MASK 0xffffffffffffffff -#define SH_AUTO_REPLY_ENABLE0_INIT 0x0000000000000000 - -/* SH_AUTO_REPLY_ENABLE0_ENABLE0 */ -/* Description: Enable 0 */ -#define SH_AUTO_REPLY_ENABLE0_ENABLE0_SHFT 0 -#define SH_AUTO_REPLY_ENABLE0_ENABLE0_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_AUTO_REPLY_ENABLE1" */ -/* Automatic Maintenance Reply Enable 1 */ -/* ==================================================================== */ - -#define SH_AUTO_REPLY_ENABLE1 0x0000000110061080 -#define SH_AUTO_REPLY_ENABLE1_MASK 0xffffffffffffffff -#define SH_AUTO_REPLY_ENABLE1_INIT 0x0000000000000000 - -/* SH_AUTO_REPLY_ENABLE1_ENABLE1 */ -/* Description: Enable 1 */ -#define SH_AUTO_REPLY_ENABLE1_ENABLE1_SHFT 0 -#define SH_AUTO_REPLY_ENABLE1_ENABLE1_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_AUTO_REPLY_HEADER0" */ -/* Automatic Maintenance Reply Header 0 */ -/* ==================================================================== */ - -#define SH_AUTO_REPLY_HEADER0 0x0000000110061100 -#define SH_AUTO_REPLY_HEADER0_MASK 0xffffffffffffffff -#define SH_AUTO_REPLY_HEADER0_INIT 0x0000000000000000 - -/* SH_AUTO_REPLY_HEADER0_HEADER0 */ -/* Description: Header 0 */ -#define SH_AUTO_REPLY_HEADER0_HEADER0_SHFT 0 -#define SH_AUTO_REPLY_HEADER0_HEADER0_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_AUTO_REPLY_HEADER1" */ -/* Automatic Maintenance Reply Header 1 */ -/* ==================================================================== */ - -#define SH_AUTO_REPLY_HEADER1 0x0000000110061180 -#define SH_AUTO_REPLY_HEADER1_MASK 0xffffffffffffffff -#define SH_AUTO_REPLY_HEADER1_INIT 0x0000000000000000 - -/* SH_AUTO_REPLY_HEADER1_HEADER1 */ -/* Description: Header 1 */ -#define SH_AUTO_REPLY_HEADER1_HEADER1_SHFT 0 -#define SH_AUTO_REPLY_HEADER1_HEADER1_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_ENABLE_RP_AUTO_REPLY" */ -/* Enable Automatic Maintenance Reply From Reply Queue */ -/* ==================================================================== */ - -#define SH_ENABLE_RP_AUTO_REPLY 0x0000000110061200 -#define SH_ENABLE_RP_AUTO_REPLY_MASK 0x0000000000000001 -#define SH_ENABLE_RP_AUTO_REPLY_INIT 0x0000000000000000 - -/* SH_ENABLE_RP_AUTO_REPLY_ENABLE */ -/* Description: Enable Reply Auto Reply */ -#define SH_ENABLE_RP_AUTO_REPLY_ENABLE_SHFT 0 -#define SH_ENABLE_RP_AUTO_REPLY_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_ENABLE_RQ_AUTO_REPLY" */ -/* Enable Automatic Maintenance Reply From Request Queue */ -/* ==================================================================== */ - -#define SH_ENABLE_RQ_AUTO_REPLY 0x0000000110061280 -#define SH_ENABLE_RQ_AUTO_REPLY_MASK 0x0000000000000001 -#define SH_ENABLE_RQ_AUTO_REPLY_INIT 0x0000000000000000 - -/* SH_ENABLE_RQ_AUTO_REPLY_ENABLE */ -/* Description: Enable Request Auto Reply */ -#define SH_ENABLE_RQ_AUTO_REPLY_ENABLE_SHFT 0 -#define SH_ENABLE_RQ_AUTO_REPLY_ENABLE_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_REDIRECT_INVAL" */ -/* Redirect invalidate to LB instead of PI */ -/* ==================================================================== */ - -#define SH_REDIRECT_INVAL 0x0000000110061300 -#define SH_REDIRECT_INVAL_MASK 0x0000000000000001 -#define SH_REDIRECT_INVAL_INIT 0x0000000000000000 - -/* SH_REDIRECT_INVAL_REDIRECT */ -/* Description: Redirect invalidates to LB instead of PI */ -#define SH_REDIRECT_INVAL_REDIRECT_SHFT 0 -#define SH_REDIRECT_INVAL_REDIRECT_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_CNTRL" */ -/* Diagnostic Message Control Register */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_CNTRL 0x0000000110062000 -#define SH_DIAG_MSG_CNTRL_MASK 0xc000000000003fff -#define SH_DIAG_MSG_CNTRL_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_CNTRL_MSG_LENGTH */ -/* Description: Message data payload length, 0 - 63 */ -#define SH_DIAG_MSG_CNTRL_MSG_LENGTH_SHFT 0 -#define SH_DIAG_MSG_CNTRL_MSG_LENGTH_MASK 0x000000000000003f - -/* SH_DIAG_MSG_CNTRL_ERROR_INJECT_POINT */ -/* Description: Point message that the error bit would be activated */ -#define SH_DIAG_MSG_CNTRL_ERROR_INJECT_POINT_SHFT 6 -#define SH_DIAG_MSG_CNTRL_ERROR_INJECT_POINT_MASK 0x0000000000000fc0 - -/* SH_DIAG_MSG_CNTRL_ERROR_INJECT_ENABLE */ -/* Description: Enable ERROR_INJECT_POINT field */ -#define SH_DIAG_MSG_CNTRL_ERROR_INJECT_ENABLE_SHFT 12 -#define SH_DIAG_MSG_CNTRL_ERROR_INJECT_ENABLE_MASK 0x0000000000001000 - -/* SH_DIAG_MSG_CNTRL_PORT */ -/* Description: 0 = request port, 1 = reply port */ -#define SH_DIAG_MSG_CNTRL_PORT_SHFT 13 -#define SH_DIAG_MSG_CNTRL_PORT_MASK 0x0000000000002000 - -/* SH_DIAG_MSG_CNTRL_START */ -/* Description: Start */ -#define SH_DIAG_MSG_CNTRL_START_SHFT 62 -#define SH_DIAG_MSG_CNTRL_START_MASK 0x4000000000000000 - -/* SH_DIAG_MSG_CNTRL_BUSY */ -/* Description: Busy */ -#define SH_DIAG_MSG_CNTRL_BUSY_SHFT 63 -#define SH_DIAG_MSG_CNTRL_BUSY_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA0L" */ -/* Diagnostic Data, lower 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA0L 0x0000000110062080 -#define SH_DIAG_MSG_DATA0L_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA0L_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA0L_DATA_LOWER */ -/* Description: Lower 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA0L_DATA_LOWER_SHFT 0 -#define SH_DIAG_MSG_DATA0L_DATA_LOWER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA0U" */ -/* Diagnostice Data, upper 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA0U 0x0000000110062100 -#define SH_DIAG_MSG_DATA0U_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA0U_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA0U_DATA_UPPER */ -/* Description: Upper 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA0U_DATA_UPPER_SHFT 0 -#define SH_DIAG_MSG_DATA0U_DATA_UPPER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA1L" */ -/* Diagnostic Data, lower 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA1L 0x0000000110062180 -#define SH_DIAG_MSG_DATA1L_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA1L_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA1L_DATA_LOWER */ -/* Description: Lower 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA1L_DATA_LOWER_SHFT 0 -#define SH_DIAG_MSG_DATA1L_DATA_LOWER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA1U" */ -/* Diagnostice Data, upper 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA1U 0x0000000110062200 -#define SH_DIAG_MSG_DATA1U_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA1U_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA1U_DATA_UPPER */ -/* Description: Upper 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA1U_DATA_UPPER_SHFT 0 -#define SH_DIAG_MSG_DATA1U_DATA_UPPER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA2L" */ -/* Diagnostic Data, lower 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA2L 0x0000000110062280 -#define SH_DIAG_MSG_DATA2L_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA2L_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA2L_DATA_LOWER */ -/* Description: Lower 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA2L_DATA_LOWER_SHFT 0 -#define SH_DIAG_MSG_DATA2L_DATA_LOWER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA2U" */ -/* Diagnostice Data, upper 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA2U 0x0000000110062300 -#define SH_DIAG_MSG_DATA2U_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA2U_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA2U_DATA_UPPER */ -/* Description: Upper 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA2U_DATA_UPPER_SHFT 0 -#define SH_DIAG_MSG_DATA2U_DATA_UPPER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA3L" */ -/* Diagnostic Data, lower 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA3L 0x0000000110062380 -#define SH_DIAG_MSG_DATA3L_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA3L_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA3L_DATA_LOWER */ -/* Description: Lower 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA3L_DATA_LOWER_SHFT 0 -#define SH_DIAG_MSG_DATA3L_DATA_LOWER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA3U" */ -/* Diagnostice Data, upper 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA3U 0x0000000110062400 -#define SH_DIAG_MSG_DATA3U_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA3U_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA3U_DATA_UPPER */ -/* Description: Upper 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA3U_DATA_UPPER_SHFT 0 -#define SH_DIAG_MSG_DATA3U_DATA_UPPER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA4L" */ -/* Diagnostic Data, lower 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA4L 0x0000000110062480 -#define SH_DIAG_MSG_DATA4L_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA4L_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA4L_DATA_LOWER */ -/* Description: Lower 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA4L_DATA_LOWER_SHFT 0 -#define SH_DIAG_MSG_DATA4L_DATA_LOWER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA4U" */ -/* Diagnostice Data, upper 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA4U 0x0000000110062500 -#define SH_DIAG_MSG_DATA4U_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA4U_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA4U_DATA_UPPER */ -/* Description: Upper 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA4U_DATA_UPPER_SHFT 0 -#define SH_DIAG_MSG_DATA4U_DATA_UPPER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA5L" */ -/* Diagnostic Data, lower 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA5L 0x0000000110062580 -#define SH_DIAG_MSG_DATA5L_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA5L_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA5L_DATA_LOWER */ -/* Description: Lower 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA5L_DATA_LOWER_SHFT 0 -#define SH_DIAG_MSG_DATA5L_DATA_LOWER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA5U" */ -/* Diagnostice Data, upper 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA5U 0x0000000110062600 -#define SH_DIAG_MSG_DATA5U_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA5U_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA5U_DATA_UPPER */ -/* Description: Upper 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA5U_DATA_UPPER_SHFT 0 -#define SH_DIAG_MSG_DATA5U_DATA_UPPER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA6L" */ -/* Diagnostic Data, lower 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA6L 0x0000000110062680 -#define SH_DIAG_MSG_DATA6L_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA6L_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA6L_DATA_LOWER */ -/* Description: Lower 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA6L_DATA_LOWER_SHFT 0 -#define SH_DIAG_MSG_DATA6L_DATA_LOWER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA6U" */ -/* Diagnostice Data, upper 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA6U 0x0000000110062700 -#define SH_DIAG_MSG_DATA6U_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA6U_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA6U_DATA_UPPER */ -/* Description: Upper 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA6U_DATA_UPPER_SHFT 0 -#define SH_DIAG_MSG_DATA6U_DATA_UPPER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA7L" */ -/* Diagnostic Data, lower 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA7L 0x0000000110062780 -#define SH_DIAG_MSG_DATA7L_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA7L_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA7L_DATA_LOWER */ -/* Description: Lower 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA7L_DATA_LOWER_SHFT 0 -#define SH_DIAG_MSG_DATA7L_DATA_LOWER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA7U" */ -/* Diagnostice Data, upper 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA7U 0x0000000110062800 -#define SH_DIAG_MSG_DATA7U_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA7U_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA7U_DATA_UPPER */ -/* Description: Upper 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA7U_DATA_UPPER_SHFT 0 -#define SH_DIAG_MSG_DATA7U_DATA_UPPER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA8L" */ -/* Diagnostic Data, lower 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA8L 0x0000000110062880 -#define SH_DIAG_MSG_DATA8L_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA8L_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA8L_DATA_LOWER */ -/* Description: Lower 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA8L_DATA_LOWER_SHFT 0 -#define SH_DIAG_MSG_DATA8L_DATA_LOWER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_DATA8U" */ -/* Diagnostice Data, upper 64 bits */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_DATA8U 0x0000000110062900 -#define SH_DIAG_MSG_DATA8U_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_DATA8U_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_DATA8U_DATA_UPPER */ -/* Description: Upper 64 bits of Diagnositic Message Data */ -#define SH_DIAG_MSG_DATA8U_DATA_UPPER_SHFT 0 -#define SH_DIAG_MSG_DATA8U_DATA_UPPER_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_HDR0" */ -/* Diagnostice Data, lower 64 bits of header */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_HDR0 0x0000000110062980 -#define SH_DIAG_MSG_HDR0_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_HDR0_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_HDR0_HEADER0 */ -/* Description: Lower 64 bits of Diagnositic Message Header */ -#define SH_DIAG_MSG_HDR0_HEADER0_SHFT 0 -#define SH_DIAG_MSG_HDR0_HEADER0_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DIAG_MSG_HDR1" */ -/* Diagnostice Data, upper 64 bits of header */ -/* ==================================================================== */ - -#define SH_DIAG_MSG_HDR1 0x0000000110062a00 -#define SH_DIAG_MSG_HDR1_MASK 0xffffffffffffffff -#define SH_DIAG_MSG_HDR1_INIT 0x0000000000000000 - -/* SH_DIAG_MSG_HDR1_HEADER1 */ -/* Description: Upper 64 bits of Diagnositic Message Header */ -#define SH_DIAG_MSG_HDR1_HEADER1_SHFT 0 -#define SH_DIAG_MSG_HDR1_HEADER1_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_DEBUG_SELECT" */ -/* SHub Debug Port Select */ -/* ==================================================================== */ - -#define SH_DEBUG_SELECT 0x0000000110063000 -#define SH_DEBUG_SELECT_MASK 0x8fffffffffffffff -#define SH_DEBUG_SELECT_INIT 0x0000e38e38e38e38 - -/* SH_DEBUG_SELECT_NIBBLE0_NIBBLE_SEL */ -/* Description: Nibble0_nibble_select */ -#define SH_DEBUG_SELECT_NIBBLE0_NIBBLE_SEL_SHFT 0 -#define SH_DEBUG_SELECT_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000007 - -/* SH_DEBUG_SELECT_NIBBLE0_CHIPLET_SEL */ -/* Description: Nibble0_chiplet_select */ -#define SH_DEBUG_SELECT_NIBBLE0_CHIPLET_SEL_SHFT 3 -#define SH_DEBUG_SELECT_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000038 - -/* SH_DEBUG_SELECT_NIBBLE1_NIBBLE_SEL */ -/* Description: Nibble1_nibble_select */ -#define SH_DEBUG_SELECT_NIBBLE1_NIBBLE_SEL_SHFT 6 -#define SH_DEBUG_SELECT_NIBBLE1_NIBBLE_SEL_MASK 0x00000000000001c0 - -/* SH_DEBUG_SELECT_NIBBLE1_CHIPLET_SEL */ -/* Description: Nibble1_chiplet_select */ -#define SH_DEBUG_SELECT_NIBBLE1_CHIPLET_SEL_SHFT 9 -#define SH_DEBUG_SELECT_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000e00 - -/* SH_DEBUG_SELECT_NIBBLE2_NIBBLE_SEL */ -/* Description: Nibble2_nibble_select */ -#define SH_DEBUG_SELECT_NIBBLE2_NIBBLE_SEL_SHFT 12 -#define SH_DEBUG_SELECT_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_DEBUG_SELECT_NIBBLE2_CHIPLET_SEL */ -/* Description: Nibble2_chiplet_select */ -#define SH_DEBUG_SELECT_NIBBLE2_CHIPLET_SEL_SHFT 15 -#define SH_DEBUG_SELECT_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000038000 - -/* SH_DEBUG_SELECT_NIBBLE3_NIBBLE_SEL */ -/* Description: Nibble3_nibble_select */ -#define SH_DEBUG_SELECT_NIBBLE3_NIBBLE_SEL_SHFT 18 -#define SH_DEBUG_SELECT_NIBBLE3_NIBBLE_SEL_MASK 0x00000000001c0000 - -/* SH_DEBUG_SELECT_NIBBLE3_CHIPLET_SEL */ -/* Description: Nibble3_chiplet_select */ -#define SH_DEBUG_SELECT_NIBBLE3_CHIPLET_SEL_SHFT 21 -#define SH_DEBUG_SELECT_NIBBLE3_CHIPLET_SEL_MASK 0x0000000000e00000 - -/* SH_DEBUG_SELECT_NIBBLE4_NIBBLE_SEL */ -/* Description: Nibble4_nibble_select */ -#define SH_DEBUG_SELECT_NIBBLE4_NIBBLE_SEL_SHFT 24 -#define SH_DEBUG_SELECT_NIBBLE4_NIBBLE_SEL_MASK 0x0000000007000000 - -/* SH_DEBUG_SELECT_NIBBLE4_CHIPLET_SEL */ -/* Description: Nibble4_chiplet_select */ -#define SH_DEBUG_SELECT_NIBBLE4_CHIPLET_SEL_SHFT 27 -#define SH_DEBUG_SELECT_NIBBLE4_CHIPLET_SEL_MASK 0x0000000038000000 - -/* SH_DEBUG_SELECT_NIBBLE5_NIBBLE_SEL */ -/* Description: Nibble5_nibble_select */ -#define SH_DEBUG_SELECT_NIBBLE5_NIBBLE_SEL_SHFT 30 -#define SH_DEBUG_SELECT_NIBBLE5_NIBBLE_SEL_MASK 0x00000001c0000000 - -/* SH_DEBUG_SELECT_NIBBLE5_CHIPLET_SEL */ -/* Description: Nibble5_chiplet_select */ -#define SH_DEBUG_SELECT_NIBBLE5_CHIPLET_SEL_SHFT 33 -#define SH_DEBUG_SELECT_NIBBLE5_CHIPLET_SEL_MASK 0x0000000e00000000 - -/* SH_DEBUG_SELECT_NIBBLE6_NIBBLE_SEL */ -/* Description: Nibble6_nibble_select */ -#define SH_DEBUG_SELECT_NIBBLE6_NIBBLE_SEL_SHFT 36 -#define SH_DEBUG_SELECT_NIBBLE6_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_DEBUG_SELECT_NIBBLE6_CHIPLET_SEL */ -/* Description: Nibble6_chiplet_select */ -#define SH_DEBUG_SELECT_NIBBLE6_CHIPLET_SEL_SHFT 39 -#define SH_DEBUG_SELECT_NIBBLE6_CHIPLET_SEL_MASK 0x0000038000000000 - -/* SH_DEBUG_SELECT_NIBBLE7_NIBBLE_SEL */ -/* Description: Nibble7_nibble_select */ -#define SH_DEBUG_SELECT_NIBBLE7_NIBBLE_SEL_SHFT 42 -#define SH_DEBUG_SELECT_NIBBLE7_NIBBLE_SEL_MASK 0x00001c0000000000 - -/* SH_DEBUG_SELECT_NIBBLE7_CHIPLET_SEL */ -/* Description: Nibble7_chiplet_select */ -#define SH_DEBUG_SELECT_NIBBLE7_CHIPLET_SEL_SHFT 45 -#define SH_DEBUG_SELECT_NIBBLE7_CHIPLET_SEL_MASK 0x0000e00000000000 - -/* SH_DEBUG_SELECT_DEBUG_II_SEL */ -/* Description: Select bits to II port */ -#define SH_DEBUG_SELECT_DEBUG_II_SEL_SHFT 48 -#define SH_DEBUG_SELECT_DEBUG_II_SEL_MASK 0x0007000000000000 - -/* SH_DEBUG_SELECT_SEL_II */ -/* Description: Select II to debug port */ -#define SH_DEBUG_SELECT_SEL_II_SHFT 51 -#define SH_DEBUG_SELECT_SEL_II_MASK 0x0ff8000000000000 - -/* SH_DEBUG_SELECT_TRIGGER_ENABLE */ -/* Description: Enable trigger on bit 32 of Analyzer data */ -#define SH_DEBUG_SELECT_TRIGGER_ENABLE_SHFT 63 -#define SH_DEBUG_SELECT_TRIGGER_ENABLE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_TRIGGER_COMPARE_MASK" */ -/* SHub Trigger Compare Mask */ -/* ==================================================================== */ - -#define SH_TRIGGER_COMPARE_MASK 0x0000000110063080 -#define SH_TRIGGER_COMPARE_MASK_MASK 0x00000000ffffffff -#define SH_TRIGGER_COMPARE_MASK_INIT 0x0000000000000000 - -/* SH_TRIGGER_COMPARE_MASK_MASK */ -/* Description: SHub Trigger Compare Mask */ -#define SH_TRIGGER_COMPARE_MASK_MASK_SHFT 0 -#define SH_TRIGGER_COMPARE_MASK_MASK_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_TRIGGER_COMPARE_PATTERN" */ -/* SHub Trigger Compare Pattern */ -/* ==================================================================== */ - -#define SH_TRIGGER_COMPARE_PATTERN 0x0000000110063100 -#define SH_TRIGGER_COMPARE_PATTERN_MASK 0x00000000ffffffff -#define SH_TRIGGER_COMPARE_PATTERN_INIT 0x0000000000000000 - -/* SH_TRIGGER_COMPARE_PATTERN_DATA */ -/* Description: SHub Trigger Compare Pattern */ -#define SH_TRIGGER_COMPARE_PATTERN_DATA_SHFT 0 -#define SH_TRIGGER_COMPARE_PATTERN_DATA_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_TRIGGER_SEL" */ -/* Trigger select for SHUB debug port */ -/* ==================================================================== */ - -#define SH_TRIGGER_SEL 0x0000000110063180 -#define SH_TRIGGER_SEL_MASK 0x7777777777777777 -#define SH_TRIGGER_SEL_INIT 0x0000000000000000 - -/* SH_TRIGGER_SEL_NIBBLE0_INPUT_SEL */ -/* Description: Nibble 0 input select */ -#define SH_TRIGGER_SEL_NIBBLE0_INPUT_SEL_SHFT 0 -#define SH_TRIGGER_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007 - -/* SH_TRIGGER_SEL_NIBBLE0_NIBBLE_SEL */ -/* Description: Nibble 0 Nibble select */ -#define SH_TRIGGER_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4 -#define SH_TRIGGER_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 - -/* SH_TRIGGER_SEL_NIBBLE1_INPUT_SEL */ -/* Description: Nibble 1 input select */ -#define SH_TRIGGER_SEL_NIBBLE1_INPUT_SEL_SHFT 8 -#define SH_TRIGGER_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700 - -/* SH_TRIGGER_SEL_NIBBLE1_NIBBLE_SEL */ -/* Description: Nibble 1 Nibble select */ -#define SH_TRIGGER_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12 -#define SH_TRIGGER_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 - -/* SH_TRIGGER_SEL_NIBBLE2_INPUT_SEL */ -/* Description: Nibble 2 input select */ -#define SH_TRIGGER_SEL_NIBBLE2_INPUT_SEL_SHFT 16 -#define SH_TRIGGER_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000 - -/* SH_TRIGGER_SEL_NIBBLE2_NIBBLE_SEL */ -/* Description: Nibble 2 Nibble select */ -#define SH_TRIGGER_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20 -#define SH_TRIGGER_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 - -/* SH_TRIGGER_SEL_NIBBLE3_INPUT_SEL */ -/* Description: Nibble 3 input select */ -#define SH_TRIGGER_SEL_NIBBLE3_INPUT_SEL_SHFT 24 -#define SH_TRIGGER_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000 - -/* SH_TRIGGER_SEL_NIBBLE3_NIBBLE_SEL */ -/* Description: Nibble 3 Nibble select */ -#define SH_TRIGGER_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28 -#define SH_TRIGGER_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 - -/* SH_TRIGGER_SEL_NIBBLE4_INPUT_SEL */ -/* Description: Nibble 4 input select */ -#define SH_TRIGGER_SEL_NIBBLE4_INPUT_SEL_SHFT 32 -#define SH_TRIGGER_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000 - -/* SH_TRIGGER_SEL_NIBBLE4_NIBBLE_SEL */ -/* Description: Nibble 4 Nibble select */ -#define SH_TRIGGER_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36 -#define SH_TRIGGER_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 - -/* SH_TRIGGER_SEL_NIBBLE5_INPUT_SEL */ -/* Description: Nibble 5 input select */ -#define SH_TRIGGER_SEL_NIBBLE5_INPUT_SEL_SHFT 40 -#define SH_TRIGGER_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000 - -/* SH_TRIGGER_SEL_NIBBLE5_NIBBLE_SEL */ -/* Description: Nibble 5 Nibble select */ -#define SH_TRIGGER_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44 -#define SH_TRIGGER_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 - -/* SH_TRIGGER_SEL_NIBBLE6_INPUT_SEL */ -/* Description: Nibble 6 input select */ -#define SH_TRIGGER_SEL_NIBBLE6_INPUT_SEL_SHFT 48 -#define SH_TRIGGER_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000 - -/* SH_TRIGGER_SEL_NIBBLE6_NIBBLE_SEL */ -/* Description: Nibble 6 Nibble select */ -#define SH_TRIGGER_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52 -#define SH_TRIGGER_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 - -/* SH_TRIGGER_SEL_NIBBLE7_INPUT_SEL */ -/* Description: Nibble 7 input select */ -#define SH_TRIGGER_SEL_NIBBLE7_INPUT_SEL_SHFT 56 -#define SH_TRIGGER_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000 - -/* SH_TRIGGER_SEL_NIBBLE7_NIBBLE_SEL */ -/* Description: Nibble 7 Nibble select */ -#define SH_TRIGGER_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60 -#define SH_TRIGGER_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 - -/* ==================================================================== */ -/* Register "SH_STOP_CLK_CONTROL" */ -/* Stop Clock Control */ -/* ==================================================================== */ - -#define SH_STOP_CLK_CONTROL 0x0000000110064000 -#define SH_STOP_CLK_CONTROL_MASK 0x00000000000000ff -#define SH_STOP_CLK_CONTROL_INIT 0x00000000000000e0 - -/* SH_STOP_CLK_CONTROL_STIMULUS */ -/* Description: Counter stimulus */ -#define SH_STOP_CLK_CONTROL_STIMULUS_SHFT 0 -#define SH_STOP_CLK_CONTROL_STIMULUS_MASK 0x000000000000001f - -/* SH_STOP_CLK_CONTROL_EVENT */ -/* Description: Counter event select (0-greater than, 1-equal) */ -#define SH_STOP_CLK_CONTROL_EVENT_SHFT 5 -#define SH_STOP_CLK_CONTROL_EVENT_MASK 0x0000000000000020 - -/* SH_STOP_CLK_CONTROL_POLARITY */ -/* Description: Counter polarity select (0-negative edge, 1-positiv */ -/* e edge) */ -#define SH_STOP_CLK_CONTROL_POLARITY_SHFT 6 -#define SH_STOP_CLK_CONTROL_POLARITY_MASK 0x0000000000000040 - -/* SH_STOP_CLK_CONTROL_MODE */ -/* Description: Counter mode select (0-internal, 1-external) */ -#define SH_STOP_CLK_CONTROL_MODE_SHFT 7 -#define SH_STOP_CLK_CONTROL_MODE_MASK 0x0000000000000080 - -/* ==================================================================== */ -/* Register "SH_STOP_CLK_DELAY_PHASE" */ -/* Stop Clock Delay Phase */ -/* ==================================================================== */ - -#define SH_STOP_CLK_DELAY_PHASE 0x0000000110064080 -#define SH_STOP_CLK_DELAY_PHASE_MASK 0x00000000000000ff -#define SH_STOP_CLK_DELAY_PHASE_INIT 0x0000000000000000 - -/* SH_STOP_CLK_DELAY_PHASE_DELAY */ -/* Description: Delay phase */ -#define SH_STOP_CLK_DELAY_PHASE_DELAY_SHFT 0 -#define SH_STOP_CLK_DELAY_PHASE_DELAY_MASK 0x00000000000000ff - -/* ==================================================================== */ -/* Register "SH_TSF_ARM_MASK" */ -/* Trigger sequencing facility arm mask */ -/* ==================================================================== */ - -#define SH_TSF_ARM_MASK 0x0000000110065000 -#define SH_TSF_ARM_MASK_MASK 0xffffffffffffffff -#define SH_TSF_ARM_MASK_INIT 0x0000000000000000 - -/* SH_TSF_ARM_MASK_MASK */ -/* Description: Trigger sequencing facility arm mask */ -#define SH_TSF_ARM_MASK_MASK_SHFT 0 -#define SH_TSF_ARM_MASK_MASK_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_TSF_COUNTER_PRESETS" */ -/* Trigger sequencing facility counter presets */ -/* ==================================================================== */ - -#define SH_TSF_COUNTER_PRESETS 0x0000000110065080 -#define SH_TSF_COUNTER_PRESETS_MASK 0xffffffffffffffff -#define SH_TSF_COUNTER_PRESETS_INIT 0x0000000000000000 - -/* SH_TSF_COUNTER_PRESETS_COUNT_32 */ -/* Description: Trigger sequencing facility counter 32 */ -#define SH_TSF_COUNTER_PRESETS_COUNT_32_SHFT 0 -#define SH_TSF_COUNTER_PRESETS_COUNT_32_MASK 0x00000000ffffffff - -/* SH_TSF_COUNTER_PRESETS_COUNT_16 */ -/* Description: Trigger sequencing facility counter 16 */ -#define SH_TSF_COUNTER_PRESETS_COUNT_16_SHFT 32 -#define SH_TSF_COUNTER_PRESETS_COUNT_16_MASK 0x0000ffff00000000 - -/* SH_TSF_COUNTER_PRESETS_COUNT_8B */ -/* Description: Trigger sequencing facility counter 8b */ -#define SH_TSF_COUNTER_PRESETS_COUNT_8B_SHFT 48 -#define SH_TSF_COUNTER_PRESETS_COUNT_8B_MASK 0x00ff000000000000 - -/* SH_TSF_COUNTER_PRESETS_COUNT_8A */ -/* Description: Trigger sequencing facility counter 8a */ -#define SH_TSF_COUNTER_PRESETS_COUNT_8A_SHFT 56 -#define SH_TSF_COUNTER_PRESETS_COUNT_8A_MASK 0xff00000000000000 - -/* ==================================================================== */ -/* Register "SH_TSF_DECREMENT_CTL" */ -/* Trigger sequencing facility counter decrement control */ -/* ==================================================================== */ - -#define SH_TSF_DECREMENT_CTL 0x0000000110065100 -#define SH_TSF_DECREMENT_CTL_MASK 0x000000000000ffff -#define SH_TSF_DECREMENT_CTL_INIT 0x0000000000000000 - -/* SH_TSF_DECREMENT_CTL_CTL */ -/* Description: Trigger sequencing facility counter decrement contr */ -#define SH_TSF_DECREMENT_CTL_CTL_SHFT 0 -#define SH_TSF_DECREMENT_CTL_CTL_MASK 0x000000000000ffff - -/* ==================================================================== */ -/* Register "SH_TSF_DIAG_MSG_CTL" */ -/* Trigger sequencing facility diagnostic message control */ -/* ==================================================================== */ - -#define SH_TSF_DIAG_MSG_CTL 0x0000000110065180 -#define SH_TSF_DIAG_MSG_CTL_MASK 0x00000000000000ff -#define SH_TSF_DIAG_MSG_CTL_INIT 0x0000000000000000 - -/* SH_TSF_DIAG_MSG_CTL_ENABLE */ -/* Description: Trigger sequencing facility diagnostic message cont */ -#define SH_TSF_DIAG_MSG_CTL_ENABLE_SHFT 0 -#define SH_TSF_DIAG_MSG_CTL_ENABLE_MASK 0x00000000000000ff - -/* ==================================================================== */ -/* Register "SH_TSF_DISARM_MASK" */ -/* Trigger sequencing facility disarm mask */ -/* ==================================================================== */ - -#define SH_TSF_DISARM_MASK 0x0000000110065200 -#define SH_TSF_DISARM_MASK_MASK 0xffffffffffffffff -#define SH_TSF_DISARM_MASK_INIT 0x0000000000000000 - -/* SH_TSF_DISARM_MASK_MASK */ -/* Description: Trigger sequencing facility disarm mask */ -#define SH_TSF_DISARM_MASK_MASK_SHFT 0 -#define SH_TSF_DISARM_MASK_MASK_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_TSF_ENABLE_CTL" */ -/* Trigger sequencing facility counter enable control */ -/* ==================================================================== */ - -#define SH_TSF_ENABLE_CTL 0x0000000110065280 -#define SH_TSF_ENABLE_CTL_MASK 0x000000000000ffff -#define SH_TSF_ENABLE_CTL_INIT 0x0000000000000000 - -/* SH_TSF_ENABLE_CTL_CTL */ -/* Description: Trigger sequencing facility counter enable control */ -#define SH_TSF_ENABLE_CTL_CTL_SHFT 0 -#define SH_TSF_ENABLE_CTL_CTL_MASK 0x000000000000ffff - -/* ==================================================================== */ -/* Register "SH_TSF_SOFTWARE_ARM" */ -/* Trigger sequencing facility software arm */ -/* ==================================================================== */ - -#define SH_TSF_SOFTWARE_ARM 0x0000000110065300 -#define SH_TSF_SOFTWARE_ARM_MASK 0x00000000000000ff -#define SH_TSF_SOFTWARE_ARM_INIT 0x0000000000000000 - -/* SH_TSF_SOFTWARE_ARM_BIT0 */ -/* Description: Trigger sequencing facility software arm bit 0 */ -#define SH_TSF_SOFTWARE_ARM_BIT0_SHFT 0 -#define SH_TSF_SOFTWARE_ARM_BIT0_MASK 0x0000000000000001 - -/* SH_TSF_SOFTWARE_ARM_BIT1 */ -/* Description: Trigger sequencing facility software arm bit 1 */ -#define SH_TSF_SOFTWARE_ARM_BIT1_SHFT 1 -#define SH_TSF_SOFTWARE_ARM_BIT1_MASK 0x0000000000000002 - -/* SH_TSF_SOFTWARE_ARM_BIT2 */ -/* Description: Trigger sequencing facility software arm bit 2 */ -#define SH_TSF_SOFTWARE_ARM_BIT2_SHFT 2 -#define SH_TSF_SOFTWARE_ARM_BIT2_MASK 0x0000000000000004 - -/* SH_TSF_SOFTWARE_ARM_BIT3 */ -/* Description: Trigger sequencing facility software arm bit 3 */ -#define SH_TSF_SOFTWARE_ARM_BIT3_SHFT 3 -#define SH_TSF_SOFTWARE_ARM_BIT3_MASK 0x0000000000000008 - -/* SH_TSF_SOFTWARE_ARM_BIT4 */ -/* Description: Trigger sequencing facility software arm bit 4 */ -#define SH_TSF_SOFTWARE_ARM_BIT4_SHFT 4 -#define SH_TSF_SOFTWARE_ARM_BIT4_MASK 0x0000000000000010 - -/* SH_TSF_SOFTWARE_ARM_BIT5 */ -/* Description: Trigger sequencing facility software arm bit 5 */ -#define SH_TSF_SOFTWARE_ARM_BIT5_SHFT 5 -#define SH_TSF_SOFTWARE_ARM_BIT5_MASK 0x0000000000000020 - -/* SH_TSF_SOFTWARE_ARM_BIT6 */ -/* Description: Trigger sequencing facility software arm bit 6 */ -#define SH_TSF_SOFTWARE_ARM_BIT6_SHFT 6 -#define SH_TSF_SOFTWARE_ARM_BIT6_MASK 0x0000000000000040 - -/* SH_TSF_SOFTWARE_ARM_BIT7 */ -/* Description: Trigger sequencing facility software arm bit 7 */ -#define SH_TSF_SOFTWARE_ARM_BIT7_SHFT 7 -#define SH_TSF_SOFTWARE_ARM_BIT7_MASK 0x0000000000000080 - -/* ==================================================================== */ -/* Register "SH_TSF_SOFTWARE_DISARM" */ -/* Trigger sequencing facility software disarm */ -/* ==================================================================== */ - -#define SH_TSF_SOFTWARE_DISARM 0x0000000110065380 -#define SH_TSF_SOFTWARE_DISARM_MASK 0x00000000000000ff -#define SH_TSF_SOFTWARE_DISARM_INIT 0x0000000000000000 - -/* SH_TSF_SOFTWARE_DISARM_BIT0 */ -/* Description: Trigger sequencing facility software disarm bit 0 */ -#define SH_TSF_SOFTWARE_DISARM_BIT0_SHFT 0 -#define SH_TSF_SOFTWARE_DISARM_BIT0_MASK 0x0000000000000001 - -/* SH_TSF_SOFTWARE_DISARM_BIT1 */ -/* Description: Trigger sequencing facility software disarm bit 1 */ -#define SH_TSF_SOFTWARE_DISARM_BIT1_SHFT 1 -#define SH_TSF_SOFTWARE_DISARM_BIT1_MASK 0x0000000000000002 - -/* SH_TSF_SOFTWARE_DISARM_BIT2 */ -/* Description: Trigger sequencing facility software disarm bit 2 */ -#define SH_TSF_SOFTWARE_DISARM_BIT2_SHFT 2 -#define SH_TSF_SOFTWARE_DISARM_BIT2_MASK 0x0000000000000004 - -/* SH_TSF_SOFTWARE_DISARM_BIT3 */ -/* Description: Trigger sequencing facility software disarm bit 3 */ -#define SH_TSF_SOFTWARE_DISARM_BIT3_SHFT 3 -#define SH_TSF_SOFTWARE_DISARM_BIT3_MASK 0x0000000000000008 - -/* SH_TSF_SOFTWARE_DISARM_BIT4 */ -/* Description: Trigger sequencing facility software disarm bit 4 */ -#define SH_TSF_SOFTWARE_DISARM_BIT4_SHFT 4 -#define SH_TSF_SOFTWARE_DISARM_BIT4_MASK 0x0000000000000010 - -/* SH_TSF_SOFTWARE_DISARM_BIT5 */ -/* Description: Trigger sequencing facility software disarm bit 5 */ -#define SH_TSF_SOFTWARE_DISARM_BIT5_SHFT 5 -#define SH_TSF_SOFTWARE_DISARM_BIT5_MASK 0x0000000000000020 - -/* SH_TSF_SOFTWARE_DISARM_BIT6 */ -/* Description: Trigger sequencing facility software disarm bit 6 */ -#define SH_TSF_SOFTWARE_DISARM_BIT6_SHFT 6 -#define SH_TSF_SOFTWARE_DISARM_BIT6_MASK 0x0000000000000040 - -/* SH_TSF_SOFTWARE_DISARM_BIT7 */ -/* Description: Trigger sequencing facility software disarm bit 7 */ -#define SH_TSF_SOFTWARE_DISARM_BIT7_SHFT 7 -#define SH_TSF_SOFTWARE_DISARM_BIT7_MASK 0x0000000000000080 - -/* ==================================================================== */ -/* Register "SH_TSF_SOFTWARE_TRIGGERED" */ -/* Trigger sequencing facility software triggered */ -/* ==================================================================== */ - -#define SH_TSF_SOFTWARE_TRIGGERED 0x0000000110065400 -#define SH_TSF_SOFTWARE_TRIGGERED_MASK 0x00000000000000ff -#define SH_TSF_SOFTWARE_TRIGGERED_INIT 0x0000000000000000 - -/* SH_TSF_SOFTWARE_TRIGGERED_BIT0 */ -/* Description: Trigger sequencing facility software triggered bit */ -#define SH_TSF_SOFTWARE_TRIGGERED_BIT0_SHFT 0 -#define SH_TSF_SOFTWARE_TRIGGERED_BIT0_MASK 0x0000000000000001 - -/* SH_TSF_SOFTWARE_TRIGGERED_BIT1 */ -/* Description: Trigger sequencing facility software triggered bit */ -#define SH_TSF_SOFTWARE_TRIGGERED_BIT1_SHFT 1 -#define SH_TSF_SOFTWARE_TRIGGERED_BIT1_MASK 0x0000000000000002 - -/* SH_TSF_SOFTWARE_TRIGGERED_BIT2 */ -/* Description: Trigger sequencing facility software triggered bit */ -#define SH_TSF_SOFTWARE_TRIGGERED_BIT2_SHFT 2 -#define SH_TSF_SOFTWARE_TRIGGERED_BIT2_MASK 0x0000000000000004 - -/* SH_TSF_SOFTWARE_TRIGGERED_BIT3 */ -/* Description: Trigger sequencing facility software triggered bit */ -#define SH_TSF_SOFTWARE_TRIGGERED_BIT3_SHFT 3 -#define SH_TSF_SOFTWARE_TRIGGERED_BIT3_MASK 0x0000000000000008 - -/* SH_TSF_SOFTWARE_TRIGGERED_BIT4 */ -/* Description: Trigger sequencing facility software triggered bit */ -#define SH_TSF_SOFTWARE_TRIGGERED_BIT4_SHFT 4 -#define SH_TSF_SOFTWARE_TRIGGERED_BIT4_MASK 0x0000000000000010 - -/* SH_TSF_SOFTWARE_TRIGGERED_BIT5 */ -/* Description: Trigger sequencing facility software triggered bit */ -#define SH_TSF_SOFTWARE_TRIGGERED_BIT5_SHFT 5 -#define SH_TSF_SOFTWARE_TRIGGERED_BIT5_MASK 0x0000000000000020 - -/* SH_TSF_SOFTWARE_TRIGGERED_BIT6 */ -/* Description: Trigger sequencing facility software triggered bit */ -#define SH_TSF_SOFTWARE_TRIGGERED_BIT6_SHFT 6 -#define SH_TSF_SOFTWARE_TRIGGERED_BIT6_MASK 0x0000000000000040 - -/* SH_TSF_SOFTWARE_TRIGGERED_BIT7 */ -/* Description: Trigger sequencing facility software triggered bit */ -#define SH_TSF_SOFTWARE_TRIGGERED_BIT7_SHFT 7 -#define SH_TSF_SOFTWARE_TRIGGERED_BIT7_MASK 0x0000000000000080 - -/* ==================================================================== */ -/* Register "SH_TSF_TRIGGER_MASK" */ -/* Trigger sequencing facility trigger mask */ -/* ==================================================================== */ - -#define SH_TSF_TRIGGER_MASK 0x0000000110065480 -#define SH_TSF_TRIGGER_MASK_MASK 0xffffffffffffffff -#define SH_TSF_TRIGGER_MASK_INIT 0x0000000000000000 - -/* SH_TSF_TRIGGER_MASK_MASK */ -/* Description: Trigger sequencing facility trigger mask */ -#define SH_TSF_TRIGGER_MASK_MASK_SHFT 0 -#define SH_TSF_TRIGGER_MASK_MASK_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_VEC_DATA" */ -/* Vector Write Request Message Data */ -/* ==================================================================== */ - -#define SH_VEC_DATA 0x0000000110066000 -#define SH_VEC_DATA_MASK 0xffffffffffffffff -#define SH_VEC_DATA_INIT 0x0000000000000000 - -/* SH_VEC_DATA_DATA */ -/* Description: Data */ -#define SH_VEC_DATA_DATA_SHFT 0 -#define SH_VEC_DATA_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_VEC_PARMS" */ -/* Vector Message Parameters Register */ -/* ==================================================================== */ - -#define SH_VEC_PARMS 0x0000000110066080 -#define SH_VEC_PARMS_MASK 0xc0003ffffffffffb -#define SH_VEC_PARMS_INIT 0x0000000000000000 - -/* SH_VEC_PARMS_TYPE */ -/* Description: Vector Request Message Type */ -#define SH_VEC_PARMS_TYPE_SHFT 0 -#define SH_VEC_PARMS_TYPE_MASK 0x0000000000000001 - -/* SH_VEC_PARMS_NI_PORT */ -/* Description: Network Interface Port Select */ -#define SH_VEC_PARMS_NI_PORT_SHFT 1 -#define SH_VEC_PARMS_NI_PORT_MASK 0x0000000000000002 - -/* SH_VEC_PARMS_ADDRESS */ -/* Description: Address[37:6] */ -#define SH_VEC_PARMS_ADDRESS_SHFT 3 -#define SH_VEC_PARMS_ADDRESS_MASK 0x00000007fffffff8 - -/* SH_VEC_PARMS_PIO_ID */ -/* Description: PIO ID */ -#define SH_VEC_PARMS_PIO_ID_SHFT 35 -#define SH_VEC_PARMS_PIO_ID_MASK 0x00003ff800000000 - -/* SH_VEC_PARMS_START */ -/* Description: Start */ -#define SH_VEC_PARMS_START_SHFT 62 -#define SH_VEC_PARMS_START_MASK 0x4000000000000000 - -/* SH_VEC_PARMS_BUSY */ -/* Description: Busy */ -#define SH_VEC_PARMS_BUSY_SHFT 63 -#define SH_VEC_PARMS_BUSY_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_VEC_ROUTE" */ -/* Vector Request Message Route */ -/* ==================================================================== */ - -#define SH_VEC_ROUTE 0x0000000110066100 -#define SH_VEC_ROUTE_MASK 0xffffffffffffffff -#define SH_VEC_ROUTE_INIT 0x0000000000000000 - -/* SH_VEC_ROUTE_ROUTE */ -/* Description: Route */ -#define SH_VEC_ROUTE_ROUTE_SHFT 0 -#define SH_VEC_ROUTE_ROUTE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_CPU_PERM" */ -/* CPU MMR Access Permission Bits */ -/* ==================================================================== */ - -#define SH_CPU_PERM 0x0000000110060000 -#define SH_CPU_PERM_MASK 0xffffffffffffffff -#define SH_CPU_PERM_INIT 0xffffffffffffffff - -/* SH_CPU_PERM_ACCESS_BITS */ -/* Description: Access Bits */ -#define SH_CPU_PERM_ACCESS_BITS_SHFT 0 -#define SH_CPU_PERM_ACCESS_BITS_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_CPU_PERM_OVR" */ -/* CPU MMR Access Permission Override */ -/* ==================================================================== */ - -#define SH_CPU_PERM_OVR 0x0000000110060080 -#define SH_CPU_PERM_OVR_MASK 0xffffffffffffffff -#define SH_CPU_PERM_OVR_INIT 0x0000000000000000 - -/* SH_CPU_PERM_OVR_OVERRIDE */ -/* Description: Override */ -#define SH_CPU_PERM_OVR_OVERRIDE_SHFT 0 -#define SH_CPU_PERM_OVR_OVERRIDE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_EXT_IO_PERM" */ -/* External IO MMR Access Permission Bits */ -/* ==================================================================== */ - -#define SH_EXT_IO_PERM 0x0000000110060100 -#define SH_EXT_IO_PERM_MASK 0xffffffffffffffff -#define SH_EXT_IO_PERM_INIT 0x0000000000000000 - -/* SH_EXT_IO_PERM_ACCESS_BITS */ -/* Description: Access Bits */ -#define SH_EXT_IO_PERM_ACCESS_BITS_SHFT 0 -#define SH_EXT_IO_PERM_ACCESS_BITS_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_EXT_IOI_ACCESS" */ -/* External IO Interrupt Access Permission Bits */ -/* ==================================================================== */ - -#define SH_EXT_IOI_ACCESS 0x0000000110060180 -#define SH_EXT_IOI_ACCESS_MASK 0xffffffffffffffff -#define SH_EXT_IOI_ACCESS_INIT 0xffffffffffffffff - -/* SH_EXT_IOI_ACCESS_ACCESS_BITS */ -/* Description: Access Bits */ -#define SH_EXT_IOI_ACCESS_ACCESS_BITS_SHFT 0 -#define SH_EXT_IOI_ACCESS_ACCESS_BITS_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_GC_FIL_CTRL" */ -/* SHub Global Clock Filter Control */ -/* ==================================================================== */ - -#define SH_GC_FIL_CTRL 0x0000000110060200 -#define SH_GC_FIL_CTRL_MASK 0x03ff3ff3ff1fff1f -#define SH_GC_FIL_CTRL_INIT 0x0000000000000000 - -/* SH_GC_FIL_CTRL_OFFSET */ -/* Description: Offset */ -#define SH_GC_FIL_CTRL_OFFSET_SHFT 0 -#define SH_GC_FIL_CTRL_OFFSET_MASK 0x000000000000001f - -/* SH_GC_FIL_CTRL_MASK_COUNTER */ -/* Description: Mask Counter */ -#define SH_GC_FIL_CTRL_MASK_COUNTER_SHFT 8 -#define SH_GC_FIL_CTRL_MASK_COUNTER_MASK 0x00000000000fff00 - -/* SH_GC_FIL_CTRL_MASK_ENABLE */ -/* Description: Mask Enable */ -#define SH_GC_FIL_CTRL_MASK_ENABLE_SHFT 20 -#define SH_GC_FIL_CTRL_MASK_ENABLE_MASK 0x0000000000100000 - -/* SH_GC_FIL_CTRL_DROPOUT_COUNTER */ -/* Description: Dropout Counter */ -#define SH_GC_FIL_CTRL_DROPOUT_COUNTER_SHFT 24 -#define SH_GC_FIL_CTRL_DROPOUT_COUNTER_MASK 0x00000003ff000000 - -/* SH_GC_FIL_CTRL_DROPOUT_THRESH */ -/* Description: Dropout threshold */ -#define SH_GC_FIL_CTRL_DROPOUT_THRESH_SHFT 36 -#define SH_GC_FIL_CTRL_DROPOUT_THRESH_MASK 0x00003ff000000000 - -/* SH_GC_FIL_CTRL_ERROR_COUNTER */ -/* Description: Error counter */ -#define SH_GC_FIL_CTRL_ERROR_COUNTER_SHFT 48 -#define SH_GC_FIL_CTRL_ERROR_COUNTER_MASK 0x03ff000000000000 - -/* ==================================================================== */ -/* Register "SH_GC_SRC_CTRL" */ -/* SHub Global Clock Control */ -/* ==================================================================== */ - -#define SH_GC_SRC_CTRL 0x0000000110060280 -#define SH_GC_SRC_CTRL_MASK 0x0000000313ff3ff1 -#define SH_GC_SRC_CTRL_INIT 0x0000000100000000 - -/* SH_GC_SRC_CTRL_ENABLE_COUNTER */ -/* Description: Enable Counter */ -#define SH_GC_SRC_CTRL_ENABLE_COUNTER_SHFT 0 -#define SH_GC_SRC_CTRL_ENABLE_COUNTER_MASK 0x0000000000000001 - -/* SH_GC_SRC_CTRL_MAX_COUNT */ -/* Description: Max Count */ -#define SH_GC_SRC_CTRL_MAX_COUNT_SHFT 4 -#define SH_GC_SRC_CTRL_MAX_COUNT_MASK 0x0000000000003ff0 - -/* SH_GC_SRC_CTRL_COUNTER */ -/* Description: Counter */ -#define SH_GC_SRC_CTRL_COUNTER_SHFT 16 -#define SH_GC_SRC_CTRL_COUNTER_MASK 0x0000000003ff0000 - -/* SH_GC_SRC_CTRL_TOGGLE_BIT */ -/* Description: Toggle bit */ -#define SH_GC_SRC_CTRL_TOGGLE_BIT_SHFT 28 -#define SH_GC_SRC_CTRL_TOGGLE_BIT_MASK 0x0000000010000000 - -/* SH_GC_SRC_CTRL_SOURCE_SEL */ -/* Description: Source select (0=ext., 1=Int., 2=SHUB) */ -#define SH_GC_SRC_CTRL_SOURCE_SEL_SHFT 32 -#define SH_GC_SRC_CTRL_SOURCE_SEL_MASK 0x0000000300000000 - -/* ==================================================================== */ -/* Register "SH_HARD_RESET" */ -/* SHub Hard Reset */ -/* ==================================================================== */ - -#define SH_HARD_RESET 0x0000000110060300 -#define SH_HARD_RESET_MASK 0x0000000000000001 -#define SH_HARD_RESET_INIT 0x0000000000000000 - -/* SH_HARD_RESET_HARD_RESET */ -/* Description: Hard Reset */ -#define SH_HARD_RESET_HARD_RESET_SHFT 0 -#define SH_HARD_RESET_HARD_RESET_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_IO_PERM" */ -/* II MMR Access Permission Bits */ -/* ==================================================================== */ - -#define SH_IO_PERM 0x0000000110060380 -#define SH_IO_PERM_MASK 0xffffffffffffffff -#define SH_IO_PERM_INIT 0x0000000000000000 - -/* SH_IO_PERM_ACCESS_BITS */ -/* Description: Access Bits */ -#define SH_IO_PERM_ACCESS_BITS_SHFT 0 -#define SH_IO_PERM_ACCESS_BITS_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_IOI_ACCESS" */ -/* II Interrupt Access Permission Bits */ -/* ==================================================================== */ - -#define SH_IOI_ACCESS 0x0000000110060400 -#define SH_IOI_ACCESS_MASK 0xffffffffffffffff -#define SH_IOI_ACCESS_INIT 0xffffffffffffffff - -/* SH_IOI_ACCESS_ACCESS_BITS */ -/* Description: Access Bits */ -#define SH_IOI_ACCESS_ACCESS_BITS_SHFT 0 -#define SH_IOI_ACCESS_ACCESS_BITS_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_IPI_ACCESS" */ -/* CPU interrupt Access Permission Bits */ -/* ==================================================================== */ - -#define SH_IPI_ACCESS 0x0000000110060480 -#define SH_IPI_ACCESS_MASK 0xffffffffffffffff -#define SH_IPI_ACCESS_INIT 0xffffffffffffffff - -/* SH_IPI_ACCESS_ACCESS_BITS */ -/* Description: Access Bits */ -#define SH_IPI_ACCESS_ACCESS_BITS_SHFT 0 -#define SH_IPI_ACCESS_ACCESS_BITS_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_JTAG_CONFIG" */ -/* SHub JTAG configuration */ -/* ==================================================================== */ - -#define SH_JTAG_CONFIG 0x0000000110060500 -#define SH_JTAG_CONFIG_MASK 0x00ffffffffffffff -#define SH_JTAG_CONFIG_INIT 0x0000000000000000 - -/* SH_JTAG_CONFIG_MD_CLK_SEL */ -/* Description: Select divide freq of DRAMCLK */ -#define SH_JTAG_CONFIG_MD_CLK_SEL_SHFT 0 -#define SH_JTAG_CONFIG_MD_CLK_SEL_MASK 0x0000000000000003 - -/* SH_JTAG_CONFIG_NI_CLK_SEL */ -/* Description: Selects clock source for NICLK domain */ -#define SH_JTAG_CONFIG_NI_CLK_SEL_SHFT 2 -#define SH_JTAG_CONFIG_NI_CLK_SEL_MASK 0x0000000000000004 - -/* SH_JTAG_CONFIG_II_CLK_SEL */ -/* Description: Selects clock source for IOCLK domain */ -#define SH_JTAG_CONFIG_II_CLK_SEL_SHFT 3 -#define SH_JTAG_CONFIG_II_CLK_SEL_MASK 0x0000000000000018 - -/* SH_JTAG_CONFIG_WRT90_TARGET */ -/* Description: wrt90_target */ -#define SH_JTAG_CONFIG_WRT90_TARGET_SHFT 5 -#define SH_JTAG_CONFIG_WRT90_TARGET_MASK 0x000000000007ffe0 - -/* SH_JTAG_CONFIG_WRT90_OVERRIDER */ -/* Description: wrt90_overrideR */ -#define SH_JTAG_CONFIG_WRT90_OVERRIDER_SHFT 19 -#define SH_JTAG_CONFIG_WRT90_OVERRIDER_MASK 0x0000000000080000 - -/* SH_JTAG_CONFIG_WRT90_OVERRIDE */ -/* Description: wrt90_override */ -#define SH_JTAG_CONFIG_WRT90_OVERRIDE_SHFT 20 -#define SH_JTAG_CONFIG_WRT90_OVERRIDE_MASK 0x0000000000100000 - -/* SH_JTAG_CONFIG_JTAG_MCI_RESET_DELAY */ -/* Description: jtag_mci_reset_delay */ -#define SH_JTAG_CONFIG_JTAG_MCI_RESET_DELAY_SHFT 21 -#define SH_JTAG_CONFIG_JTAG_MCI_RESET_DELAY_MASK 0x0000000001e00000 - -/* SH_JTAG_CONFIG_JTAG_MCI_TARGET */ -/* Description: jtag_mci_target */ -#define SH_JTAG_CONFIG_JTAG_MCI_TARGET_SHFT 25 -#define SH_JTAG_CONFIG_JTAG_MCI_TARGET_MASK 0x0000007ffe000000 - -/* SH_JTAG_CONFIG_JTAG_MCI_OVERRIDE */ -/* Description: jtag_mci_override */ -#define SH_JTAG_CONFIG_JTAG_MCI_OVERRIDE_SHFT 39 -#define SH_JTAG_CONFIG_JTAG_MCI_OVERRIDE_MASK 0x0000008000000000 - -/* SH_JTAG_CONFIG_FSB_CONFIG_IOQ_DEPTH */ -/* Description: 0=depth 8, 1=depth1 */ -#define SH_JTAG_CONFIG_FSB_CONFIG_IOQ_DEPTH_SHFT 40 -#define SH_JTAG_CONFIG_FSB_CONFIG_IOQ_DEPTH_MASK 0x0000010000000000 - -/* SH_JTAG_CONFIG_FSB_CONFIG_SAMPLE_BINIT */ -/* Description: Enable sampling of BINIT */ -#define SH_JTAG_CONFIG_FSB_CONFIG_SAMPLE_BINIT_SHFT 41 -#define SH_JTAG_CONFIG_FSB_CONFIG_SAMPLE_BINIT_MASK 0x0000020000000000 - -/* SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BUS_PARKING */ -#define SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BUS_PARKING_SHFT 42 -#define SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BUS_PARKING_MASK 0x0000040000000000 - -/* SH_JTAG_CONFIG_FSB_CONFIG_CLOCK_RATIO */ -#define SH_JTAG_CONFIG_FSB_CONFIG_CLOCK_RATIO_SHFT 43 -#define SH_JTAG_CONFIG_FSB_CONFIG_CLOCK_RATIO_MASK 0x0000f80000000000 - -/* SH_JTAG_CONFIG_FSB_CONFIG_OUTPUT_TRISTATE */ -/* Description: Output tristate control */ -#define SH_JTAG_CONFIG_FSB_CONFIG_OUTPUT_TRISTATE_SHFT 48 -#define SH_JTAG_CONFIG_FSB_CONFIG_OUTPUT_TRISTATE_MASK 0x000f000000000000 - -/* SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BIST */ -/* Description: Enables BIST */ -#define SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BIST_SHFT 52 -#define SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BIST_MASK 0x0010000000000000 - -/* SH_JTAG_CONFIG_FSB_CONFIG_AUX */ -/* Description: Enables BIST */ -#define SH_JTAG_CONFIG_FSB_CONFIG_AUX_SHFT 53 -#define SH_JTAG_CONFIG_FSB_CONFIG_AUX_MASK 0x0060000000000000 - -/* SH_JTAG_CONFIG_GTL_CONFIG_RE */ -/* Description: Reference Enable selection for GTL io */ -#define SH_JTAG_CONFIG_GTL_CONFIG_RE_SHFT 55 -#define SH_JTAG_CONFIG_GTL_CONFIG_RE_MASK 0x0080000000000000 - -/* ==================================================================== */ -/* Register "SH_SHUB_ID" */ -/* SHub ID Number */ -/* ==================================================================== */ - -#define SH_SHUB_ID 0x0000000110060580 -#define SH_SHUB_ID_MASK 0x011f37ffffffffff -#define SH_SHUB_ID_INIT 0x0010300000000000 - -/* SH_SHUB_ID_FORCE1 */ -/* Description: Must be 1 */ -#define SH_SHUB_ID_FORCE1_SHFT 0 -#define SH_SHUB_ID_FORCE1_MASK 0x0000000000000001 - -/* SH_SHUB_ID_MANUFACTURER */ -/* Description: Manufacturer */ -#define SH_SHUB_ID_MANUFACTURER_SHFT 1 -#define SH_SHUB_ID_MANUFACTURER_MASK 0x0000000000000ffe - -/* SH_SHUB_ID_PART_NUMBER */ -/* Description: Part Number */ -#define SH_SHUB_ID_PART_NUMBER_SHFT 12 -#define SH_SHUB_ID_PART_NUMBER_MASK 0x000000000ffff000 - -/* SH_SHUB_ID_REVISION */ -/* Description: Revision */ -#define SH_SHUB_ID_REVISION_SHFT 28 -#define SH_SHUB_ID_REVISION_MASK 0x00000000f0000000 - -/* SH_SHUB_ID_NODE_ID */ -/* Description: Node Identification */ -#define SH_SHUB_ID_NODE_ID_SHFT 32 -#define SH_SHUB_ID_NODE_ID_MASK 0x000007ff00000000 - -/* SH_SHUB_ID_SHARING_MODE */ -/* Description: Sharing mode (Coherency Domain Size) */ -#define SH_SHUB_ID_SHARING_MODE_SHFT 44 -#define SH_SHUB_ID_SHARING_MODE_MASK 0x0000300000000000 - -/* SH_SHUB_ID_NODES_PER_BIT */ -/* Description: Nodes per bit definition for MMR access */ -#define SH_SHUB_ID_NODES_PER_BIT_SHFT 48 -#define SH_SHUB_ID_NODES_PER_BIT_MASK 0x001f000000000000 - -/* SH_SHUB_ID_NI_PORT */ -/* Description: NI port of vector reference, 0 = NI0, 1 = NI1 */ -#define SH_SHUB_ID_NI_PORT_SHFT 56 -#define SH_SHUB_ID_NI_PORT_MASK 0x0100000000000000 - -/* ==================================================================== */ -/* Register "SH_SHUBS_PRESENT0" */ -/* Shubs 0 - 63 Present. Used for invalidate generation */ -/* ==================================================================== */ - -#define SH_SHUBS_PRESENT0 0x0000000110060600 -#define SH_SHUBS_PRESENT0_MASK 0xffffffffffffffff -#define SH_SHUBS_PRESENT0_INIT 0xffffffffffffffff - -/* SH_SHUBS_PRESENT0_SHUBS_PRESENT0 */ -/* Description: Shubs 0 - 63 Present configuration */ -#define SH_SHUBS_PRESENT0_SHUBS_PRESENT0_SHFT 0 -#define SH_SHUBS_PRESENT0_SHUBS_PRESENT0_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_SHUBS_PRESENT1" */ -/* Shubs 64 - 127 Present. Used for invalidate generation */ -/* ==================================================================== */ - -#define SH_SHUBS_PRESENT1 0x0000000110060680 -#define SH_SHUBS_PRESENT1_MASK 0xffffffffffffffff -#define SH_SHUBS_PRESENT1_INIT 0xffffffffffffffff - -/* SH_SHUBS_PRESENT1_SHUBS_PRESENT1 */ -/* Description: Shubs 64 - 127 Present configuration */ -#define SH_SHUBS_PRESENT1_SHUBS_PRESENT1_SHFT 0 -#define SH_SHUBS_PRESENT1_SHUBS_PRESENT1_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_SHUBS_PRESENT2" */ -/* Shubs 128 - 191 Present. Used for invalidate generation */ -/* ==================================================================== */ - -#define SH_SHUBS_PRESENT2 0x0000000110060700 -#define SH_SHUBS_PRESENT2_MASK 0xffffffffffffffff -#define SH_SHUBS_PRESENT2_INIT 0xffffffffffffffff - -/* SH_SHUBS_PRESENT2_SHUBS_PRESENT2 */ -/* Description: Shubs 128 - 191 Present configuration */ -#define SH_SHUBS_PRESENT2_SHUBS_PRESENT2_SHFT 0 -#define SH_SHUBS_PRESENT2_SHUBS_PRESENT2_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_SHUBS_PRESENT3" */ -/* Shubs 192 - 255 Present. Used for invalidate generation */ -/* ==================================================================== */ - -#define SH_SHUBS_PRESENT3 0x0000000110060780 -#define SH_SHUBS_PRESENT3_MASK 0xffffffffffffffff -#define SH_SHUBS_PRESENT3_INIT 0xffffffffffffffff - -/* SH_SHUBS_PRESENT3_SHUBS_PRESENT3 */ -/* Description: Shubs 192 - 255 Present configuration */ -#define SH_SHUBS_PRESENT3_SHUBS_PRESENT3_SHFT 0 -#define SH_SHUBS_PRESENT3_SHUBS_PRESENT3_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_SOFT_RESET" */ -/* SHub Soft Reset */ -/* ==================================================================== */ - -#define SH_SOFT_RESET 0x0000000110060800 -#define SH_SOFT_RESET_MASK 0x0000000000000001 -#define SH_SOFT_RESET_INIT 0x0000000000000000 - -/* SH_SOFT_RESET_SOFT_RESET */ -/* Description: Soft Reset */ -#define SH_SOFT_RESET_SOFT_RESET_SHFT 0 -#define SH_SOFT_RESET_SOFT_RESET_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_FIRST_ERROR" */ -/* Shub Global First Error Flags */ -/* ==================================================================== */ - -#define SH_FIRST_ERROR 0x0000000110071000 -#define SH_FIRST_ERROR_MASK 0x000000000007ffff -#define SH_FIRST_ERROR_INIT 0x0000000000000000 - -/* SH_FIRST_ERROR_FIRST_ERROR */ -/* Description: Chiplet with first error */ -#define SH_FIRST_ERROR_FIRST_ERROR_SHFT 0 -#define SH_FIRST_ERROR_FIRST_ERROR_MASK 0x000000000007ffff - -/* ==================================================================== */ -/* Register "SH_II_HW_TIME_STAMP" */ -/* II hardware error time stamp */ -/* ==================================================================== */ - -#define SH_II_HW_TIME_STAMP 0x0000000110071080 -#define SH_II_HW_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_II_HW_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_II_HW_TIME_STAMP_TIME */ -/* Description: II hardware error time stamp */ -#define SH_II_HW_TIME_STAMP_TIME_SHFT 0 -#define SH_II_HW_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_II_HW_TIME_STAMP_VALID */ -/* Description: II hardware error time stamp valid */ -#define SH_II_HW_TIME_STAMP_VALID_SHFT 63 -#define SH_II_HW_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_LB_HW_TIME_STAMP" */ -/* LB hardware error time stamp */ -/* ==================================================================== */ - -#define SH_LB_HW_TIME_STAMP 0x0000000110071100 -#define SH_LB_HW_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_LB_HW_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_LB_HW_TIME_STAMP_TIME */ -/* Description: LB hardware error time stamp */ -#define SH_LB_HW_TIME_STAMP_TIME_SHFT 0 -#define SH_LB_HW_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_LB_HW_TIME_STAMP_VALID */ -/* Description: LB hardware error time stamp valid */ -#define SH_LB_HW_TIME_STAMP_VALID_SHFT 63 -#define SH_LB_HW_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_COR_TIME_STAMP" */ -/* MD correctable error time stamp */ -/* ==================================================================== */ - -#define SH_MD_COR_TIME_STAMP 0x0000000110071180 -#define SH_MD_COR_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_MD_COR_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_MD_COR_TIME_STAMP_TIME */ -/* Description: MD correctable error time stamp */ -#define SH_MD_COR_TIME_STAMP_TIME_SHFT 0 -#define SH_MD_COR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_MD_COR_TIME_STAMP_VALID */ -/* Description: MD correctable error time stamp valid */ -#define SH_MD_COR_TIME_STAMP_VALID_SHFT 63 -#define SH_MD_COR_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_HW_TIME_STAMP" */ -/* MD hardware error time stamp */ -/* ==================================================================== */ - -#define SH_MD_HW_TIME_STAMP 0x0000000110071200 -#define SH_MD_HW_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_MD_HW_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_MD_HW_TIME_STAMP_TIME */ -/* Description: MD hardware error time stamp */ -#define SH_MD_HW_TIME_STAMP_TIME_SHFT 0 -#define SH_MD_HW_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_MD_HW_TIME_STAMP_VALID */ -/* Description: MD hardware error time stamp valid */ -#define SH_MD_HW_TIME_STAMP_VALID_SHFT 63 -#define SH_MD_HW_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_UNCOR_TIME_STAMP" */ -/* MD uncorrectable error time stamp */ -/* ==================================================================== */ - -#define SH_MD_UNCOR_TIME_STAMP 0x0000000110071280 -#define SH_MD_UNCOR_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_MD_UNCOR_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_MD_UNCOR_TIME_STAMP_TIME */ -/* Description: MD uncorrectable error time stamp */ -#define SH_MD_UNCOR_TIME_STAMP_TIME_SHFT 0 -#define SH_MD_UNCOR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_MD_UNCOR_TIME_STAMP_VALID */ -/* Description: MD uncorrectable error time stamp valid */ -#define SH_MD_UNCOR_TIME_STAMP_VALID_SHFT 63 -#define SH_MD_UNCOR_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_COR_TIME_STAMP" */ -/* PI correctable error time stamp */ -/* ==================================================================== */ - -#define SH_PI_COR_TIME_STAMP 0x0000000110071300 -#define SH_PI_COR_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_PI_COR_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_PI_COR_TIME_STAMP_TIME */ -/* Description: PI correctable error time stamp */ -#define SH_PI_COR_TIME_STAMP_TIME_SHFT 0 -#define SH_PI_COR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_PI_COR_TIME_STAMP_VALID */ -/* Description: PI correctable error time stamp valid */ -#define SH_PI_COR_TIME_STAMP_VALID_SHFT 63 -#define SH_PI_COR_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_HW_TIME_STAMP" */ -/* PI hardware error time stamp */ -/* ==================================================================== */ - -#define SH_PI_HW_TIME_STAMP 0x0000000110071380 -#define SH_PI_HW_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_PI_HW_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_PI_HW_TIME_STAMP_TIME */ -/* Description: PI hardware error time stamp */ -#define SH_PI_HW_TIME_STAMP_TIME_SHFT 0 -#define SH_PI_HW_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_PI_HW_TIME_STAMP_VALID */ -/* Description: PI hardware error time stamp valid */ -#define SH_PI_HW_TIME_STAMP_VALID_SHFT 63 -#define SH_PI_HW_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PI_UNCOR_TIME_STAMP" */ -/* PI uncorrectable error time stamp */ -/* ==================================================================== */ - -#define SH_PI_UNCOR_TIME_STAMP 0x0000000110071400 -#define SH_PI_UNCOR_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_PI_UNCOR_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_PI_UNCOR_TIME_STAMP_TIME */ -/* Description: PI uncorrectable error time stamp */ -#define SH_PI_UNCOR_TIME_STAMP_TIME_SHFT 0 -#define SH_PI_UNCOR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_PI_UNCOR_TIME_STAMP_VALID */ -/* Description: PI uncorrectable error time stamp valid */ -#define SH_PI_UNCOR_TIME_STAMP_VALID_SHFT 63 -#define SH_PI_UNCOR_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC0_ADV_TIME_STAMP" */ -/* Proc 0 advisory time stamp */ -/* ==================================================================== */ - -#define SH_PROC0_ADV_TIME_STAMP 0x0000000110071480 -#define SH_PROC0_ADV_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_PROC0_ADV_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_PROC0_ADV_TIME_STAMP_TIME */ -/* Description: Processor 0 advisory time stamp */ -#define SH_PROC0_ADV_TIME_STAMP_TIME_SHFT 0 -#define SH_PROC0_ADV_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_PROC0_ADV_TIME_STAMP_VALID */ -/* Description: Processor 0 advisory time stamp valid */ -#define SH_PROC0_ADV_TIME_STAMP_VALID_SHFT 63 -#define SH_PROC0_ADV_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC0_ERR_TIME_STAMP" */ -/* Proc 0 error time stamp */ -/* ==================================================================== */ - -#define SH_PROC0_ERR_TIME_STAMP 0x0000000110071500 -#define SH_PROC0_ERR_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_PROC0_ERR_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_PROC0_ERR_TIME_STAMP_TIME */ -/* Description: Processor 0 error time stamp */ -#define SH_PROC0_ERR_TIME_STAMP_TIME_SHFT 0 -#define SH_PROC0_ERR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_PROC0_ERR_TIME_STAMP_VALID */ -/* Description: Processor 0 error time stamp valid */ -#define SH_PROC0_ERR_TIME_STAMP_VALID_SHFT 63 -#define SH_PROC0_ERR_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC1_ADV_TIME_STAMP" */ -/* Proc 1 advisory time stamp */ -/* ==================================================================== */ - -#define SH_PROC1_ADV_TIME_STAMP 0x0000000110071580 -#define SH_PROC1_ADV_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_PROC1_ADV_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_PROC1_ADV_TIME_STAMP_TIME */ -/* Description: Processor 1 advisory time stamp */ -#define SH_PROC1_ADV_TIME_STAMP_TIME_SHFT 0 -#define SH_PROC1_ADV_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_PROC1_ADV_TIME_STAMP_VALID */ -/* Description: Processor 1 advisory time stamp valid */ -#define SH_PROC1_ADV_TIME_STAMP_VALID_SHFT 63 -#define SH_PROC1_ADV_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC1_ERR_TIME_STAMP" */ -/* Proc 1 error time stamp */ -/* ==================================================================== */ - -#define SH_PROC1_ERR_TIME_STAMP 0x0000000110071600 -#define SH_PROC1_ERR_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_PROC1_ERR_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_PROC1_ERR_TIME_STAMP_TIME */ -/* Description: Processor 1 error time stamp */ -#define SH_PROC1_ERR_TIME_STAMP_TIME_SHFT 0 -#define SH_PROC1_ERR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_PROC1_ERR_TIME_STAMP_VALID */ -/* Description: Processor 1 error time stamp valid */ -#define SH_PROC1_ERR_TIME_STAMP_VALID_SHFT 63 -#define SH_PROC1_ERR_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC2_ADV_TIME_STAMP" */ -/* Proc 2 advisory time stamp */ -/* ==================================================================== */ - -#define SH_PROC2_ADV_TIME_STAMP 0x0000000110071680 -#define SH_PROC2_ADV_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_PROC2_ADV_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_PROC2_ADV_TIME_STAMP_TIME */ -/* Description: Processor 2 advisory time stamp */ -#define SH_PROC2_ADV_TIME_STAMP_TIME_SHFT 0 -#define SH_PROC2_ADV_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_PROC2_ADV_TIME_STAMP_VALID */ -/* Description: Processor 2 advisory time stamp valid */ -#define SH_PROC2_ADV_TIME_STAMP_VALID_SHFT 63 -#define SH_PROC2_ADV_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC2_ERR_TIME_STAMP" */ -/* Proc 2 error time stamp */ -/* ==================================================================== */ - -#define SH_PROC2_ERR_TIME_STAMP 0x0000000110071700 -#define SH_PROC2_ERR_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_PROC2_ERR_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_PROC2_ERR_TIME_STAMP_TIME */ -/* Description: Processor 2 error time stamp */ -#define SH_PROC2_ERR_TIME_STAMP_TIME_SHFT 0 -#define SH_PROC2_ERR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_PROC2_ERR_TIME_STAMP_VALID */ -/* Description: Processor 2 error time stamp valid */ -#define SH_PROC2_ERR_TIME_STAMP_VALID_SHFT 63 -#define SH_PROC2_ERR_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC3_ADV_TIME_STAMP" */ -/* Proc 3 advisory time stamp */ -/* ==================================================================== */ - -#define SH_PROC3_ADV_TIME_STAMP 0x0000000110071780 -#define SH_PROC3_ADV_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_PROC3_ADV_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_PROC3_ADV_TIME_STAMP_TIME */ -/* Description: Processor 3 advisory time stamp */ -#define SH_PROC3_ADV_TIME_STAMP_TIME_SHFT 0 -#define SH_PROC3_ADV_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_PROC3_ADV_TIME_STAMP_VALID */ -/* Description: Processor 3 advisory time stamp valid */ -#define SH_PROC3_ADV_TIME_STAMP_VALID_SHFT 63 -#define SH_PROC3_ADV_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PROC3_ERR_TIME_STAMP" */ -/* Proc 3 error time stamp */ -/* ==================================================================== */ - -#define SH_PROC3_ERR_TIME_STAMP 0x0000000110071800 -#define SH_PROC3_ERR_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_PROC3_ERR_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_PROC3_ERR_TIME_STAMP_TIME */ -/* Description: Processor 3 error time stamp */ -#define SH_PROC3_ERR_TIME_STAMP_TIME_SHFT 0 -#define SH_PROC3_ERR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_PROC3_ERR_TIME_STAMP_VALID */ -/* Description: Processor 3 error time stamp valid */ -#define SH_PROC3_ERR_TIME_STAMP_VALID_SHFT 63 -#define SH_PROC3_ERR_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_XN_COR_TIME_STAMP" */ -/* XN correctable error time stamp */ -/* ==================================================================== */ - -#define SH_XN_COR_TIME_STAMP 0x0000000110071880 -#define SH_XN_COR_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_XN_COR_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_XN_COR_TIME_STAMP_TIME */ -/* Description: XN correctable error time stamp */ -#define SH_XN_COR_TIME_STAMP_TIME_SHFT 0 -#define SH_XN_COR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_XN_COR_TIME_STAMP_VALID */ -/* Description: XN correctable error time stamp valid */ -#define SH_XN_COR_TIME_STAMP_VALID_SHFT 63 -#define SH_XN_COR_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_XN_HW_TIME_STAMP" */ -/* XN hardware error time stamp */ -/* ==================================================================== */ - -#define SH_XN_HW_TIME_STAMP 0x0000000110071900 -#define SH_XN_HW_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_XN_HW_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_XN_HW_TIME_STAMP_TIME */ -/* Description: XN hardware error time stamp */ -#define SH_XN_HW_TIME_STAMP_TIME_SHFT 0 -#define SH_XN_HW_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_XN_HW_TIME_STAMP_VALID */ -/* Description: XN hardware error time stamp valid */ -#define SH_XN_HW_TIME_STAMP_VALID_SHFT 63 -#define SH_XN_HW_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_XN_UNCOR_TIME_STAMP" */ -/* XN uncorrectable error time stamp */ -/* ==================================================================== */ - -#define SH_XN_UNCOR_TIME_STAMP 0x0000000110071980 -#define SH_XN_UNCOR_TIME_STAMP_MASK 0xffffffffffffffff -#define SH_XN_UNCOR_TIME_STAMP_INIT 0x0000000000000000 - -/* SH_XN_UNCOR_TIME_STAMP_TIME */ -/* Description: XN uncorrectable error time stamp */ -#define SH_XN_UNCOR_TIME_STAMP_TIME_SHFT 0 -#define SH_XN_UNCOR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff - -/* SH_XN_UNCOR_TIME_STAMP_VALID */ -/* Description: XN uncorrectable error time stamp valid */ -#define SH_XN_UNCOR_TIME_STAMP_VALID_SHFT 63 -#define SH_XN_UNCOR_TIME_STAMP_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_DEBUG_PORT" */ -/* SHub Debug Port */ -/* ==================================================================== */ - -#define SH_DEBUG_PORT 0x0000000110072000 -#define SH_DEBUG_PORT_MASK 0x00000000ffffffff -#define SH_DEBUG_PORT_INIT 0x0000000000000000 - -/* SH_DEBUG_PORT_DEBUG_NIBBLE0 */ -/* Description: Debug port nibble 0 */ -#define SH_DEBUG_PORT_DEBUG_NIBBLE0_SHFT 0 -#define SH_DEBUG_PORT_DEBUG_NIBBLE0_MASK 0x000000000000000f - -/* SH_DEBUG_PORT_DEBUG_NIBBLE1 */ -/* Description: Debug port nibble 1 */ -#define SH_DEBUG_PORT_DEBUG_NIBBLE1_SHFT 4 -#define SH_DEBUG_PORT_DEBUG_NIBBLE1_MASK 0x00000000000000f0 - -/* SH_DEBUG_PORT_DEBUG_NIBBLE2 */ -/* Description: Debug port nibble 2 */ -#define SH_DEBUG_PORT_DEBUG_NIBBLE2_SHFT 8 -#define SH_DEBUG_PORT_DEBUG_NIBBLE2_MASK 0x0000000000000f00 - -/* SH_DEBUG_PORT_DEBUG_NIBBLE3 */ -/* Description: Debug port nibble 3 */ -#define SH_DEBUG_PORT_DEBUG_NIBBLE3_SHFT 12 -#define SH_DEBUG_PORT_DEBUG_NIBBLE3_MASK 0x000000000000f000 - -/* SH_DEBUG_PORT_DEBUG_NIBBLE4 */ -/* Description: Debug port nibble 4 */ -#define SH_DEBUG_PORT_DEBUG_NIBBLE4_SHFT 16 -#define SH_DEBUG_PORT_DEBUG_NIBBLE4_MASK 0x00000000000f0000 - -/* SH_DEBUG_PORT_DEBUG_NIBBLE5 */ -/* Description: Debug port nibble 5 */ -#define SH_DEBUG_PORT_DEBUG_NIBBLE5_SHFT 20 -#define SH_DEBUG_PORT_DEBUG_NIBBLE5_MASK 0x0000000000f00000 - -/* SH_DEBUG_PORT_DEBUG_NIBBLE6 */ -/* Description: Debug port nibble 6 */ -#define SH_DEBUG_PORT_DEBUG_NIBBLE6_SHFT 24 -#define SH_DEBUG_PORT_DEBUG_NIBBLE6_MASK 0x000000000f000000 - -/* SH_DEBUG_PORT_DEBUG_NIBBLE7 */ -/* Description: Debug port nibble 7 */ -#define SH_DEBUG_PORT_DEBUG_NIBBLE7_SHFT 28 -#define SH_DEBUG_PORT_DEBUG_NIBBLE7_MASK 0x00000000f0000000 - -/* ==================================================================== */ -/* Register "SH_II_DEBUG_DATA" */ -/* II Debug Data */ -/* ==================================================================== */ - -#define SH_II_DEBUG_DATA 0x0000000110072080 -#define SH_II_DEBUG_DATA_MASK 0x00000000ffffffff -#define SH_II_DEBUG_DATA_INIT 0x0000000000000000 - -/* SH_II_DEBUG_DATA_II_DATA */ -/* Description: II debug data */ -#define SH_II_DEBUG_DATA_II_DATA_SHFT 0 -#define SH_II_DEBUG_DATA_II_DATA_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_II_WRAP_DEBUG_DATA" */ -/* SHub II Wrapper Debug Data */ -/* ==================================================================== */ - -#define SH_II_WRAP_DEBUG_DATA 0x0000000110072100 -#define SH_II_WRAP_DEBUG_DATA_MASK 0x00000000ffffffff -#define SH_II_WRAP_DEBUG_DATA_INIT 0x0000000000000000 - -/* SH_II_WRAP_DEBUG_DATA_II_WRAP_DATA */ -/* Description: II wrapper debug data */ -#define SH_II_WRAP_DEBUG_DATA_II_WRAP_DATA_SHFT 0 -#define SH_II_WRAP_DEBUG_DATA_II_WRAP_DATA_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_LB_DEBUG_DATA" */ -/* SHub LB Debug Data */ -/* ==================================================================== */ - -#define SH_LB_DEBUG_DATA 0x0000000110072180 -#define SH_LB_DEBUG_DATA_MASK 0x00000000ffffffff -#define SH_LB_DEBUG_DATA_INIT 0x0000000000000000 - -/* SH_LB_DEBUG_DATA_LB_DATA */ -/* Description: LB debug data */ -#define SH_LB_DEBUG_DATA_LB_DATA_SHFT 0 -#define SH_LB_DEBUG_DATA_LB_DATA_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DEBUG_DATA" */ -/* SHub MD Debug Data */ -/* ==================================================================== */ - -#define SH_MD_DEBUG_DATA 0x0000000110072200 -#define SH_MD_DEBUG_DATA_MASK 0x00000000ffffffff -#define SH_MD_DEBUG_DATA_INIT 0x0000000000000000 - -/* SH_MD_DEBUG_DATA_MD_DATA */ -/* Description: MD debug data */ -#define SH_MD_DEBUG_DATA_MD_DATA_SHFT 0 -#define SH_MD_DEBUG_DATA_MD_DATA_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_PI_DEBUG_DATA" */ -/* SHub PI Debug Data */ -/* ==================================================================== */ - -#define SH_PI_DEBUG_DATA 0x0000000110072280 -#define SH_PI_DEBUG_DATA_MASK 0x00000000ffffffff -#define SH_PI_DEBUG_DATA_INIT 0x0000000000000000 - -/* SH_PI_DEBUG_DATA_PI_DATA */ -/* Description: PI Debug Data */ -#define SH_PI_DEBUG_DATA_PI_DATA_SHFT 0 -#define SH_PI_DEBUG_DATA_PI_DATA_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_XN_DEBUG_DATA" */ -/* SHub XN Debug Data */ -/* ==================================================================== */ - -#define SH_XN_DEBUG_DATA 0x0000000110072300 -#define SH_XN_DEBUG_DATA_MASK 0x00000000ffffffff -#define SH_XN_DEBUG_DATA_INIT 0x0000000000000000 - -/* SH_XN_DEBUG_DATA_XN_DATA */ -/* Description: XN debug data */ -#define SH_XN_DEBUG_DATA_XN_DATA_SHFT 0 -#define SH_XN_DEBUG_DATA_XN_DATA_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_TSF_ARMED_STATE" */ -/* Trigger sequencing facility arm state */ -/* ==================================================================== */ - -#define SH_TSF_ARMED_STATE 0x0000000110073000 -#define SH_TSF_ARMED_STATE_MASK 0x00000000000000ff -#define SH_TSF_ARMED_STATE_INIT 0x0000000000000000 - -/* SH_TSF_ARMED_STATE_STATE */ -/* Description: Trigger sequencing facility armed state */ -#define SH_TSF_ARMED_STATE_STATE_SHFT 0 -#define SH_TSF_ARMED_STATE_STATE_MASK 0x00000000000000ff - -/* ==================================================================== */ -/* Register "SH_TSF_COUNTER_VALUE" */ -/* Trigger sequencing facility counter value */ -/* ==================================================================== */ - -#define SH_TSF_COUNTER_VALUE 0x0000000110073080 -#define SH_TSF_COUNTER_VALUE_MASK 0xffffffffffffffff -#define SH_TSF_COUNTER_VALUE_INIT 0x0000000000000000 - -/* SH_TSF_COUNTER_VALUE_COUNT_32 */ -/* Description: Trigger sequencing facility counter 32 */ -#define SH_TSF_COUNTER_VALUE_COUNT_32_SHFT 0 -#define SH_TSF_COUNTER_VALUE_COUNT_32_MASK 0x00000000ffffffff - -/* SH_TSF_COUNTER_VALUE_COUNT_16 */ -/* Description: Trigger sequencing facility counter 16 */ -#define SH_TSF_COUNTER_VALUE_COUNT_16_SHFT 32 -#define SH_TSF_COUNTER_VALUE_COUNT_16_MASK 0x0000ffff00000000 - -/* SH_TSF_COUNTER_VALUE_COUNT_8B */ -/* Description: Trigger sequencing facility counter 8b */ -#define SH_TSF_COUNTER_VALUE_COUNT_8B_SHFT 48 -#define SH_TSF_COUNTER_VALUE_COUNT_8B_MASK 0x00ff000000000000 - -/* SH_TSF_COUNTER_VALUE_COUNT_8A */ -/* Description: Trigger sequencing facility counter 8a */ -#define SH_TSF_COUNTER_VALUE_COUNT_8A_SHFT 56 -#define SH_TSF_COUNTER_VALUE_COUNT_8A_MASK 0xff00000000000000 - -/* ==================================================================== */ -/* Register "SH_TSF_TRIGGERED_STATE" */ -/* Trigger sequencing facility triggered state */ -/* ==================================================================== */ - -#define SH_TSF_TRIGGERED_STATE 0x0000000110073100 -#define SH_TSF_TRIGGERED_STATE_MASK 0x00000000000000ff -#define SH_TSF_TRIGGERED_STATE_INIT 0x0000000000000000 - -/* SH_TSF_TRIGGERED_STATE_STATE */ -/* Description: Trigger sequencing facility triggered state */ -#define SH_TSF_TRIGGERED_STATE_STATE_SHFT 0 -#define SH_TSF_TRIGGERED_STATE_STATE_MASK 0x00000000000000ff - -/* ==================================================================== */ -/* Register "SH_VEC_RDDATA" */ -/* Vector Reply Message Data */ -/* ==================================================================== */ - -#define SH_VEC_RDDATA 0x0000000110074000 -#define SH_VEC_RDDATA_MASK 0xffffffffffffffff -#define SH_VEC_RDDATA_INIT 0x0000000000000000 - -/* SH_VEC_RDDATA_DATA */ -/* Description: Data */ -#define SH_VEC_RDDATA_DATA_SHFT 0 -#define SH_VEC_RDDATA_DATA_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_VEC_RETURN" */ -/* Vector Reply Message Return Route */ -/* ==================================================================== */ - -#define SH_VEC_RETURN 0x0000000110074080 -#define SH_VEC_RETURN_MASK 0xffffffffffffffff -#define SH_VEC_RETURN_INIT 0x0000000000000000 - -/* SH_VEC_RETURN_ROUTE */ -/* Description: Route */ -#define SH_VEC_RETURN_ROUTE_SHFT 0 -#define SH_VEC_RETURN_ROUTE_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_VEC_STATUS" */ -/* Vector Reply Message Status */ -/* ==================================================================== */ - -#define SH_VEC_STATUS 0x0000000110074100 -#define SH_VEC_STATUS_MASK 0xcfffffffffffffff -#define SH_VEC_STATUS_INIT 0x0000000000000000 - -/* SH_VEC_STATUS_TYPE */ -/* Description: Type */ -#define SH_VEC_STATUS_TYPE_SHFT 0 -#define SH_VEC_STATUS_TYPE_MASK 0x0000000000000007 - -/* SH_VEC_STATUS_ADDRESS */ -/* Description: Address */ -#define SH_VEC_STATUS_ADDRESS_SHFT 3 -#define SH_VEC_STATUS_ADDRESS_MASK 0x00000007fffffff8 - -/* SH_VEC_STATUS_PIO_ID */ -/* Description: PIO ID */ -#define SH_VEC_STATUS_PIO_ID_SHFT 35 -#define SH_VEC_STATUS_PIO_ID_MASK 0x00003ff800000000 - -/* SH_VEC_STATUS_SOURCE */ -/* Description: Source */ -#define SH_VEC_STATUS_SOURCE_SHFT 46 -#define SH_VEC_STATUS_SOURCE_MASK 0x0fffc00000000000 - -/* SH_VEC_STATUS_OVERRUN */ -/* Description: Overrun */ -#define SH_VEC_STATUS_OVERRUN_SHFT 62 -#define SH_VEC_STATUS_OVERRUN_MASK 0x4000000000000000 - -/* SH_VEC_STATUS_STATUS_VALID */ -/* Description: Status_Valid */ -#define SH_VEC_STATUS_STATUS_VALID_SHFT 63 -#define SH_VEC_STATUS_STATUS_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_VEC_STATUS_ALIAS" */ -/* Vector Reply Message Status Alias */ -/* ==================================================================== */ - -#define SH_VEC_STATUS_ALIAS 0x0000000110074108 - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNT0_CONTROL" */ -/* Performance Counter 0 Control */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNT0_CONTROL 0x0000000110080000 -#define SH_PERFORMANCE_COUNT0_CONTROL_MASK 0x000000000007ffff -#define SH_PERFORMANCE_COUNT0_CONTROL_INIT 0x000000000000b8b8 - -/* SH_PERFORMANCE_COUNT0_CONTROL_UP_STIMULUS */ -/* Description: Counter 0 up stimulus */ -#define SH_PERFORMANCE_COUNT0_CONTROL_UP_STIMULUS_SHFT 0 -#define SH_PERFORMANCE_COUNT0_CONTROL_UP_STIMULUS_MASK 0x000000000000001f - -/* SH_PERFORMANCE_COUNT0_CONTROL_UP_EVENT */ -/* Description: Counter 0 up event select (1-greater than, 0-equal) */ -#define SH_PERFORMANCE_COUNT0_CONTROL_UP_EVENT_SHFT 5 -#define SH_PERFORMANCE_COUNT0_CONTROL_UP_EVENT_MASK 0x0000000000000020 - -/* SH_PERFORMANCE_COUNT0_CONTROL_UP_POLARITY */ -/* Description: Counter 0 up polarity select (1-negative edge, 0-po */ -/* sitive edge) */ -#define SH_PERFORMANCE_COUNT0_CONTROL_UP_POLARITY_SHFT 6 -#define SH_PERFORMANCE_COUNT0_CONTROL_UP_POLARITY_MASK 0x0000000000000040 - -/* SH_PERFORMANCE_COUNT0_CONTROL_UP_MODE */ -/* Description: Counter 0 up mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT0_CONTROL_UP_MODE_SHFT 7 -#define SH_PERFORMANCE_COUNT0_CONTROL_UP_MODE_MASK 0x0000000000000080 - -/* SH_PERFORMANCE_COUNT0_CONTROL_DN_STIMULUS */ -/* Description: Counter 0 down stimulus */ -#define SH_PERFORMANCE_COUNT0_CONTROL_DN_STIMULUS_SHFT 8 -#define SH_PERFORMANCE_COUNT0_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00 - -/* SH_PERFORMANCE_COUNT0_CONTROL_DN_EVENT */ -/* Description: Counter 0 down event select (1-greater than, 0-equa */ -#define SH_PERFORMANCE_COUNT0_CONTROL_DN_EVENT_SHFT 13 -#define SH_PERFORMANCE_COUNT0_CONTROL_DN_EVENT_MASK 0x0000000000002000 - -/* SH_PERFORMANCE_COUNT0_CONTROL_DN_POLARITY */ -/* Description: Counter 0 down polarity select (1-negative edge, 0- */ -/* positive edge) */ -#define SH_PERFORMANCE_COUNT0_CONTROL_DN_POLARITY_SHFT 14 -#define SH_PERFORMANCE_COUNT0_CONTROL_DN_POLARITY_MASK 0x0000000000004000 - -/* SH_PERFORMANCE_COUNT0_CONTROL_DN_MODE */ -/* Description: Counter 0 down mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT0_CONTROL_DN_MODE_SHFT 15 -#define SH_PERFORMANCE_COUNT0_CONTROL_DN_MODE_MASK 0x0000000000008000 - -/* SH_PERFORMANCE_COUNT0_CONTROL_INC_ENABLE */ -/* Description: Counter 0 enable increment */ -#define SH_PERFORMANCE_COUNT0_CONTROL_INC_ENABLE_SHFT 16 -#define SH_PERFORMANCE_COUNT0_CONTROL_INC_ENABLE_MASK 0x0000000000010000 - -/* SH_PERFORMANCE_COUNT0_CONTROL_DEC_ENABLE */ -/* Description: Counter 0 enable decrement */ -#define SH_PERFORMANCE_COUNT0_CONTROL_DEC_ENABLE_SHFT 17 -#define SH_PERFORMANCE_COUNT0_CONTROL_DEC_ENABLE_MASK 0x0000000000020000 - -/* SH_PERFORMANCE_COUNT0_CONTROL_PEAK_DET_ENABLE */ -/* Description: Counter 0 enable peak detection */ -#define SH_PERFORMANCE_COUNT0_CONTROL_PEAK_DET_ENABLE_SHFT 18 -#define SH_PERFORMANCE_COUNT0_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000 - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNT1_CONTROL" */ -/* Performance Counter 1 Control */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNT1_CONTROL 0x0000000110090000 -#define SH_PERFORMANCE_COUNT1_CONTROL_MASK 0x000000000007ffff -#define SH_PERFORMANCE_COUNT1_CONTROL_INIT 0x000000000000b8b8 - -/* SH_PERFORMANCE_COUNT1_CONTROL_UP_STIMULUS */ -/* Description: Counter 1 up stimulus */ -#define SH_PERFORMANCE_COUNT1_CONTROL_UP_STIMULUS_SHFT 0 -#define SH_PERFORMANCE_COUNT1_CONTROL_UP_STIMULUS_MASK 0x000000000000001f - -/* SH_PERFORMANCE_COUNT1_CONTROL_UP_EVENT */ -/* Description: Counter 1 up event select (1-greater than, 0-equal) */ -#define SH_PERFORMANCE_COUNT1_CONTROL_UP_EVENT_SHFT 5 -#define SH_PERFORMANCE_COUNT1_CONTROL_UP_EVENT_MASK 0x0000000000000020 - -/* SH_PERFORMANCE_COUNT1_CONTROL_UP_POLARITY */ -/* Description: Counter 1 up polarity select (1-negative edge, 0-po */ -/* sitive edge) */ -#define SH_PERFORMANCE_COUNT1_CONTROL_UP_POLARITY_SHFT 6 -#define SH_PERFORMANCE_COUNT1_CONTROL_UP_POLARITY_MASK 0x0000000000000040 - -/* SH_PERFORMANCE_COUNT1_CONTROL_UP_MODE */ -/* Description: Counter 1 up mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT1_CONTROL_UP_MODE_SHFT 7 -#define SH_PERFORMANCE_COUNT1_CONTROL_UP_MODE_MASK 0x0000000000000080 - -/* SH_PERFORMANCE_COUNT1_CONTROL_DN_STIMULUS */ -/* Description: Counter 1 down stimulus */ -#define SH_PERFORMANCE_COUNT1_CONTROL_DN_STIMULUS_SHFT 8 -#define SH_PERFORMANCE_COUNT1_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00 - -/* SH_PERFORMANCE_COUNT1_CONTROL_DN_EVENT */ -/* Description: Counter 1 down event select (1-greater than, 0-equa */ -#define SH_PERFORMANCE_COUNT1_CONTROL_DN_EVENT_SHFT 13 -#define SH_PERFORMANCE_COUNT1_CONTROL_DN_EVENT_MASK 0x0000000000002000 - -/* SH_PERFORMANCE_COUNT1_CONTROL_DN_POLARITY */ -/* Description: Counter 1 down polarity select (1-negative edge, 0- */ -/* positive edge) */ -#define SH_PERFORMANCE_COUNT1_CONTROL_DN_POLARITY_SHFT 14 -#define SH_PERFORMANCE_COUNT1_CONTROL_DN_POLARITY_MASK 0x0000000000004000 - -/* SH_PERFORMANCE_COUNT1_CONTROL_DN_MODE */ -/* Description: Counter 1 down mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT1_CONTROL_DN_MODE_SHFT 15 -#define SH_PERFORMANCE_COUNT1_CONTROL_DN_MODE_MASK 0x0000000000008000 - -/* SH_PERFORMANCE_COUNT1_CONTROL_INC_ENABLE */ -/* Description: Counter 1 enable increment */ -#define SH_PERFORMANCE_COUNT1_CONTROL_INC_ENABLE_SHFT 16 -#define SH_PERFORMANCE_COUNT1_CONTROL_INC_ENABLE_MASK 0x0000000000010000 - -/* SH_PERFORMANCE_COUNT1_CONTROL_DEC_ENABLE */ -/* Description: Counter 1 enable decrement */ -#define SH_PERFORMANCE_COUNT1_CONTROL_DEC_ENABLE_SHFT 17 -#define SH_PERFORMANCE_COUNT1_CONTROL_DEC_ENABLE_MASK 0x0000000000020000 - -/* SH_PERFORMANCE_COUNT1_CONTROL_PEAK_DET_ENABLE */ -/* Description: Counter 1 enable peak detection */ -#define SH_PERFORMANCE_COUNT1_CONTROL_PEAK_DET_ENABLE_SHFT 18 -#define SH_PERFORMANCE_COUNT1_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000 - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNT2_CONTROL" */ -/* Performance Counter 2 Control */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNT2_CONTROL 0x00000001100a0000 -#define SH_PERFORMANCE_COUNT2_CONTROL_MASK 0x000000000007ffff -#define SH_PERFORMANCE_COUNT2_CONTROL_INIT 0x000000000000b8b8 - -/* SH_PERFORMANCE_COUNT2_CONTROL_UP_STIMULUS */ -/* Description: Counter 2 up stimulus */ -#define SH_PERFORMANCE_COUNT2_CONTROL_UP_STIMULUS_SHFT 0 -#define SH_PERFORMANCE_COUNT2_CONTROL_UP_STIMULUS_MASK 0x000000000000001f - -/* SH_PERFORMANCE_COUNT2_CONTROL_UP_EVENT */ -/* Description: Counter 2 up event select (1-greater than, 0-equal) */ -#define SH_PERFORMANCE_COUNT2_CONTROL_UP_EVENT_SHFT 5 -#define SH_PERFORMANCE_COUNT2_CONTROL_UP_EVENT_MASK 0x0000000000000020 - -/* SH_PERFORMANCE_COUNT2_CONTROL_UP_POLARITY */ -/* Description: Counter 2 up polarity select (1-negative edge, 0-po */ -/* sitive edge) */ -#define SH_PERFORMANCE_COUNT2_CONTROL_UP_POLARITY_SHFT 6 -#define SH_PERFORMANCE_COUNT2_CONTROL_UP_POLARITY_MASK 0x0000000000000040 - -/* SH_PERFORMANCE_COUNT2_CONTROL_UP_MODE */ -/* Description: Counter 2 up mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT2_CONTROL_UP_MODE_SHFT 7 -#define SH_PERFORMANCE_COUNT2_CONTROL_UP_MODE_MASK 0x0000000000000080 - -/* SH_PERFORMANCE_COUNT2_CONTROL_DN_STIMULUS */ -/* Description: Counter 2 down stimulus */ -#define SH_PERFORMANCE_COUNT2_CONTROL_DN_STIMULUS_SHFT 8 -#define SH_PERFORMANCE_COUNT2_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00 - -/* SH_PERFORMANCE_COUNT2_CONTROL_DN_EVENT */ -/* Description: Counter 2 down event select (1-greater than, 0-equa */ -#define SH_PERFORMANCE_COUNT2_CONTROL_DN_EVENT_SHFT 13 -#define SH_PERFORMANCE_COUNT2_CONTROL_DN_EVENT_MASK 0x0000000000002000 - -/* SH_PERFORMANCE_COUNT2_CONTROL_DN_POLARITY */ -/* Description: Counter 2 down polarity select (1-negative edge, 0- */ -/* positive edge) */ -#define SH_PERFORMANCE_COUNT2_CONTROL_DN_POLARITY_SHFT 14 -#define SH_PERFORMANCE_COUNT2_CONTROL_DN_POLARITY_MASK 0x0000000000004000 - -/* SH_PERFORMANCE_COUNT2_CONTROL_DN_MODE */ -/* Description: Counter 2 down mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT2_CONTROL_DN_MODE_SHFT 15 -#define SH_PERFORMANCE_COUNT2_CONTROL_DN_MODE_MASK 0x0000000000008000 - -/* SH_PERFORMANCE_COUNT2_CONTROL_INC_ENABLE */ -/* Description: Counter 2 enable increment */ -#define SH_PERFORMANCE_COUNT2_CONTROL_INC_ENABLE_SHFT 16 -#define SH_PERFORMANCE_COUNT2_CONTROL_INC_ENABLE_MASK 0x0000000000010000 - -/* SH_PERFORMANCE_COUNT2_CONTROL_DEC_ENABLE */ -/* Description: Counter 2 enable decrement */ -#define SH_PERFORMANCE_COUNT2_CONTROL_DEC_ENABLE_SHFT 17 -#define SH_PERFORMANCE_COUNT2_CONTROL_DEC_ENABLE_MASK 0x0000000000020000 - -/* SH_PERFORMANCE_COUNT2_CONTROL_PEAK_DET_ENABLE */ -/* Description: Counter 2 enable peak detection */ -#define SH_PERFORMANCE_COUNT2_CONTROL_PEAK_DET_ENABLE_SHFT 18 -#define SH_PERFORMANCE_COUNT2_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000 - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNT3_CONTROL" */ -/* Performance Counter 3 Control */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNT3_CONTROL 0x00000001100b0000 -#define SH_PERFORMANCE_COUNT3_CONTROL_MASK 0x000000000007ffff -#define SH_PERFORMANCE_COUNT3_CONTROL_INIT 0x000000000000b8b8 - -/* SH_PERFORMANCE_COUNT3_CONTROL_UP_STIMULUS */ -/* Description: Counter 3 up stimulus */ -#define SH_PERFORMANCE_COUNT3_CONTROL_UP_STIMULUS_SHFT 0 -#define SH_PERFORMANCE_COUNT3_CONTROL_UP_STIMULUS_MASK 0x000000000000001f - -/* SH_PERFORMANCE_COUNT3_CONTROL_UP_EVENT */ -/* Description: Counter 3 up event select (1-greater than, 0-equal) */ -#define SH_PERFORMANCE_COUNT3_CONTROL_UP_EVENT_SHFT 5 -#define SH_PERFORMANCE_COUNT3_CONTROL_UP_EVENT_MASK 0x0000000000000020 - -/* SH_PERFORMANCE_COUNT3_CONTROL_UP_POLARITY */ -/* Description: Counter 3 up polarity select (1-negative edge, 0-po */ -/* sitive edge) */ -#define SH_PERFORMANCE_COUNT3_CONTROL_UP_POLARITY_SHFT 6 -#define SH_PERFORMANCE_COUNT3_CONTROL_UP_POLARITY_MASK 0x0000000000000040 - -/* SH_PERFORMANCE_COUNT3_CONTROL_UP_MODE */ -/* Description: Counter 3 up mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT3_CONTROL_UP_MODE_SHFT 7 -#define SH_PERFORMANCE_COUNT3_CONTROL_UP_MODE_MASK 0x0000000000000080 - -/* SH_PERFORMANCE_COUNT3_CONTROL_DN_STIMULUS */ -/* Description: Counter 3 down stimulus */ -#define SH_PERFORMANCE_COUNT3_CONTROL_DN_STIMULUS_SHFT 8 -#define SH_PERFORMANCE_COUNT3_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00 - -/* SH_PERFORMANCE_COUNT3_CONTROL_DN_EVENT */ -/* Description: Counter 3 down event select (1-greater than, 0-equa */ -#define SH_PERFORMANCE_COUNT3_CONTROL_DN_EVENT_SHFT 13 -#define SH_PERFORMANCE_COUNT3_CONTROL_DN_EVENT_MASK 0x0000000000002000 - -/* SH_PERFORMANCE_COUNT3_CONTROL_DN_POLARITY */ -/* Description: Counter 3 down polarity select (1-negative edge, 0- */ -/* positive edge) */ -#define SH_PERFORMANCE_COUNT3_CONTROL_DN_POLARITY_SHFT 14 -#define SH_PERFORMANCE_COUNT3_CONTROL_DN_POLARITY_MASK 0x0000000000004000 - -/* SH_PERFORMANCE_COUNT3_CONTROL_DN_MODE */ -/* Description: Counter 3 down mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT3_CONTROL_DN_MODE_SHFT 15 -#define SH_PERFORMANCE_COUNT3_CONTROL_DN_MODE_MASK 0x0000000000008000 - -/* SH_PERFORMANCE_COUNT3_CONTROL_INC_ENABLE */ -/* Description: Counter 3 enable increment */ -#define SH_PERFORMANCE_COUNT3_CONTROL_INC_ENABLE_SHFT 16 -#define SH_PERFORMANCE_COUNT3_CONTROL_INC_ENABLE_MASK 0x0000000000010000 - -/* SH_PERFORMANCE_COUNT3_CONTROL_DEC_ENABLE */ -/* Description: Counter 3 enable decrement */ -#define SH_PERFORMANCE_COUNT3_CONTROL_DEC_ENABLE_SHFT 17 -#define SH_PERFORMANCE_COUNT3_CONTROL_DEC_ENABLE_MASK 0x0000000000020000 - -/* SH_PERFORMANCE_COUNT3_CONTROL_PEAK_DET_ENABLE */ -/* Description: Counter 3 enable peak detection */ -#define SH_PERFORMANCE_COUNT3_CONTROL_PEAK_DET_ENABLE_SHFT 18 -#define SH_PERFORMANCE_COUNT3_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000 - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNT4_CONTROL" */ -/* Performance Counter 4 Control */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNT4_CONTROL 0x00000001100c0000 -#define SH_PERFORMANCE_COUNT4_CONTROL_MASK 0x000000000007ffff -#define SH_PERFORMANCE_COUNT4_CONTROL_INIT 0x000000000000b8b8 - -/* SH_PERFORMANCE_COUNT4_CONTROL_UP_STIMULUS */ -/* Description: Counter 4 up stimulus */ -#define SH_PERFORMANCE_COUNT4_CONTROL_UP_STIMULUS_SHFT 0 -#define SH_PERFORMANCE_COUNT4_CONTROL_UP_STIMULUS_MASK 0x000000000000001f - -/* SH_PERFORMANCE_COUNT4_CONTROL_UP_EVENT */ -/* Description: Counter 4 up event select (1-greater than, 0-equal) */ -#define SH_PERFORMANCE_COUNT4_CONTROL_UP_EVENT_SHFT 5 -#define SH_PERFORMANCE_COUNT4_CONTROL_UP_EVENT_MASK 0x0000000000000020 - -/* SH_PERFORMANCE_COUNT4_CONTROL_UP_POLARITY */ -/* Description: Counter 4 up polarity select (1-negative edge, 0-po */ -/* sitive edge) */ -#define SH_PERFORMANCE_COUNT4_CONTROL_UP_POLARITY_SHFT 6 -#define SH_PERFORMANCE_COUNT4_CONTROL_UP_POLARITY_MASK 0x0000000000000040 - -/* SH_PERFORMANCE_COUNT4_CONTROL_UP_MODE */ -/* Description: Counter 4 up mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT4_CONTROL_UP_MODE_SHFT 7 -#define SH_PERFORMANCE_COUNT4_CONTROL_UP_MODE_MASK 0x0000000000000080 - -/* SH_PERFORMANCE_COUNT4_CONTROL_DN_STIMULUS */ -/* Description: Counter 4 down stimulus */ -#define SH_PERFORMANCE_COUNT4_CONTROL_DN_STIMULUS_SHFT 8 -#define SH_PERFORMANCE_COUNT4_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00 - -/* SH_PERFORMANCE_COUNT4_CONTROL_DN_EVENT */ -/* Description: Counter 4 down event select (1-greater than, 0-equa */ -#define SH_PERFORMANCE_COUNT4_CONTROL_DN_EVENT_SHFT 13 -#define SH_PERFORMANCE_COUNT4_CONTROL_DN_EVENT_MASK 0x0000000000002000 - -/* SH_PERFORMANCE_COUNT4_CONTROL_DN_POLARITY */ -/* Description: Counter 4 down polarity select (1-negative edge, 0- */ -/* positive edge) */ -#define SH_PERFORMANCE_COUNT4_CONTROL_DN_POLARITY_SHFT 14 -#define SH_PERFORMANCE_COUNT4_CONTROL_DN_POLARITY_MASK 0x0000000000004000 - -/* SH_PERFORMANCE_COUNT4_CONTROL_DN_MODE */ -/* Description: Counter 4 down mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT4_CONTROL_DN_MODE_SHFT 15 -#define SH_PERFORMANCE_COUNT4_CONTROL_DN_MODE_MASK 0x0000000000008000 - -/* SH_PERFORMANCE_COUNT4_CONTROL_INC_ENABLE */ -/* Description: Counter 4 enable increment */ -#define SH_PERFORMANCE_COUNT4_CONTROL_INC_ENABLE_SHFT 16 -#define SH_PERFORMANCE_COUNT4_CONTROL_INC_ENABLE_MASK 0x0000000000010000 - -/* SH_PERFORMANCE_COUNT4_CONTROL_DEC_ENABLE */ -/* Description: Counter 4 enable decrement */ -#define SH_PERFORMANCE_COUNT4_CONTROL_DEC_ENABLE_SHFT 17 -#define SH_PERFORMANCE_COUNT4_CONTROL_DEC_ENABLE_MASK 0x0000000000020000 - -/* SH_PERFORMANCE_COUNT4_CONTROL_PEAK_DET_ENABLE */ -/* Description: Counter 4 enable peak detection */ -#define SH_PERFORMANCE_COUNT4_CONTROL_PEAK_DET_ENABLE_SHFT 18 -#define SH_PERFORMANCE_COUNT4_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000 - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNT5_CONTROL" */ -/* Performance Counter 5 Control */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNT5_CONTROL 0x00000001100d0000 -#define SH_PERFORMANCE_COUNT5_CONTROL_MASK 0x000000000007ffff -#define SH_PERFORMANCE_COUNT5_CONTROL_INIT 0x000000000000b8b8 - -/* SH_PERFORMANCE_COUNT5_CONTROL_UP_STIMULUS */ -/* Description: Counter 5 up stimulus */ -#define SH_PERFORMANCE_COUNT5_CONTROL_UP_STIMULUS_SHFT 0 -#define SH_PERFORMANCE_COUNT5_CONTROL_UP_STIMULUS_MASK 0x000000000000001f - -/* SH_PERFORMANCE_COUNT5_CONTROL_UP_EVENT */ -/* Description: Counter 5 up event select (1-greater than, 0-equal) */ -#define SH_PERFORMANCE_COUNT5_CONTROL_UP_EVENT_SHFT 5 -#define SH_PERFORMANCE_COUNT5_CONTROL_UP_EVENT_MASK 0x0000000000000020 - -/* SH_PERFORMANCE_COUNT5_CONTROL_UP_POLARITY */ -/* Description: Counter 5 up polarity select (1-negative edge, 0-po */ -/* sitive edge) */ -#define SH_PERFORMANCE_COUNT5_CONTROL_UP_POLARITY_SHFT 6 -#define SH_PERFORMANCE_COUNT5_CONTROL_UP_POLARITY_MASK 0x0000000000000040 - -/* SH_PERFORMANCE_COUNT5_CONTROL_UP_MODE */ -/* Description: Counter 5 up mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT5_CONTROL_UP_MODE_SHFT 7 -#define SH_PERFORMANCE_COUNT5_CONTROL_UP_MODE_MASK 0x0000000000000080 - -/* SH_PERFORMANCE_COUNT5_CONTROL_DN_STIMULUS */ -/* Description: Counter 5 down stimulus */ -#define SH_PERFORMANCE_COUNT5_CONTROL_DN_STIMULUS_SHFT 8 -#define SH_PERFORMANCE_COUNT5_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00 - -/* SH_PERFORMANCE_COUNT5_CONTROL_DN_EVENT */ -/* Description: Counter 5 down event select (1-greater than, 0-equa */ -#define SH_PERFORMANCE_COUNT5_CONTROL_DN_EVENT_SHFT 13 -#define SH_PERFORMANCE_COUNT5_CONTROL_DN_EVENT_MASK 0x0000000000002000 - -/* SH_PERFORMANCE_COUNT5_CONTROL_DN_POLARITY */ -/* Description: Counter 5 down polarity select (1-negative edge, 0- */ -/* positive edge) */ -#define SH_PERFORMANCE_COUNT5_CONTROL_DN_POLARITY_SHFT 14 -#define SH_PERFORMANCE_COUNT5_CONTROL_DN_POLARITY_MASK 0x0000000000004000 - -/* SH_PERFORMANCE_COUNT5_CONTROL_DN_MODE */ -/* Description: Counter 5 down mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT5_CONTROL_DN_MODE_SHFT 15 -#define SH_PERFORMANCE_COUNT5_CONTROL_DN_MODE_MASK 0x0000000000008000 - -/* SH_PERFORMANCE_COUNT5_CONTROL_INC_ENABLE */ -/* Description: Counter 5 enable increment */ -#define SH_PERFORMANCE_COUNT5_CONTROL_INC_ENABLE_SHFT 16 -#define SH_PERFORMANCE_COUNT5_CONTROL_INC_ENABLE_MASK 0x0000000000010000 - -/* SH_PERFORMANCE_COUNT5_CONTROL_DEC_ENABLE */ -/* Description: Counter 5 enable decrement */ -#define SH_PERFORMANCE_COUNT5_CONTROL_DEC_ENABLE_SHFT 17 -#define SH_PERFORMANCE_COUNT5_CONTROL_DEC_ENABLE_MASK 0x0000000000020000 - -/* SH_PERFORMANCE_COUNT5_CONTROL_PEAK_DET_ENABLE */ -/* Description: Counter 5 enable peak detection */ -#define SH_PERFORMANCE_COUNT5_CONTROL_PEAK_DET_ENABLE_SHFT 18 -#define SH_PERFORMANCE_COUNT5_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000 - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNT6_CONTROL" */ -/* Performance Counter 6 Control */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNT6_CONTROL 0x00000001100e0000 -#define SH_PERFORMANCE_COUNT6_CONTROL_MASK 0x000000000007ffff -#define SH_PERFORMANCE_COUNT6_CONTROL_INIT 0x000000000000b8b8 - -/* SH_PERFORMANCE_COUNT6_CONTROL_UP_STIMULUS */ -/* Description: Counter 6 up stimulus */ -#define SH_PERFORMANCE_COUNT6_CONTROL_UP_STIMULUS_SHFT 0 -#define SH_PERFORMANCE_COUNT6_CONTROL_UP_STIMULUS_MASK 0x000000000000001f - -/* SH_PERFORMANCE_COUNT6_CONTROL_UP_EVENT */ -/* Description: Counter 6 up event select (1-greater than, 0-equal) */ -#define SH_PERFORMANCE_COUNT6_CONTROL_UP_EVENT_SHFT 5 -#define SH_PERFORMANCE_COUNT6_CONTROL_UP_EVENT_MASK 0x0000000000000020 - -/* SH_PERFORMANCE_COUNT6_CONTROL_UP_POLARITY */ -/* Description: Counter 6 up polarity select (1-negative edge, 0-po */ -/* sitive edge) */ -#define SH_PERFORMANCE_COUNT6_CONTROL_UP_POLARITY_SHFT 6 -#define SH_PERFORMANCE_COUNT6_CONTROL_UP_POLARITY_MASK 0x0000000000000040 - -/* SH_PERFORMANCE_COUNT6_CONTROL_UP_MODE */ -/* Description: Counter 6 up mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT6_CONTROL_UP_MODE_SHFT 7 -#define SH_PERFORMANCE_COUNT6_CONTROL_UP_MODE_MASK 0x0000000000000080 - -/* SH_PERFORMANCE_COUNT6_CONTROL_DN_STIMULUS */ -/* Description: Counter 6 down stimulus */ -#define SH_PERFORMANCE_COUNT6_CONTROL_DN_STIMULUS_SHFT 8 -#define SH_PERFORMANCE_COUNT6_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00 - -/* SH_PERFORMANCE_COUNT6_CONTROL_DN_EVENT */ -/* Description: Counter 6 down event select (1-greater than, 0-equa */ -#define SH_PERFORMANCE_COUNT6_CONTROL_DN_EVENT_SHFT 13 -#define SH_PERFORMANCE_COUNT6_CONTROL_DN_EVENT_MASK 0x0000000000002000 - -/* SH_PERFORMANCE_COUNT6_CONTROL_DN_POLARITY */ -/* Description: Counter 6 down polarity select (1-negative edge, 0- */ -/* positive edge) */ -#define SH_PERFORMANCE_COUNT6_CONTROL_DN_POLARITY_SHFT 14 -#define SH_PERFORMANCE_COUNT6_CONTROL_DN_POLARITY_MASK 0x0000000000004000 - -/* SH_PERFORMANCE_COUNT6_CONTROL_DN_MODE */ -/* Description: Counter 6 down mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT6_CONTROL_DN_MODE_SHFT 15 -#define SH_PERFORMANCE_COUNT6_CONTROL_DN_MODE_MASK 0x0000000000008000 - -/* SH_PERFORMANCE_COUNT6_CONTROL_INC_ENABLE */ -/* Description: Counter 6 enable increment */ -#define SH_PERFORMANCE_COUNT6_CONTROL_INC_ENABLE_SHFT 16 -#define SH_PERFORMANCE_COUNT6_CONTROL_INC_ENABLE_MASK 0x0000000000010000 - -/* SH_PERFORMANCE_COUNT6_CONTROL_DEC_ENABLE */ -/* Description: Counter 6 enable decrement */ -#define SH_PERFORMANCE_COUNT6_CONTROL_DEC_ENABLE_SHFT 17 -#define SH_PERFORMANCE_COUNT6_CONTROL_DEC_ENABLE_MASK 0x0000000000020000 - -/* SH_PERFORMANCE_COUNT6_CONTROL_PEAK_DET_ENABLE */ -/* Description: Counter 6 enable peak detection */ -#define SH_PERFORMANCE_COUNT6_CONTROL_PEAK_DET_ENABLE_SHFT 18 -#define SH_PERFORMANCE_COUNT6_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000 - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNT7_CONTROL" */ -/* Performance Counter 7 Control */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNT7_CONTROL 0x00000001100f0000 -#define SH_PERFORMANCE_COUNT7_CONTROL_MASK 0x000000000007ffff -#define SH_PERFORMANCE_COUNT7_CONTROL_INIT 0x000000000000b8b8 - -/* SH_PERFORMANCE_COUNT7_CONTROL_UP_STIMULUS */ -/* Description: Counter 7 up stimulus */ -#define SH_PERFORMANCE_COUNT7_CONTROL_UP_STIMULUS_SHFT 0 -#define SH_PERFORMANCE_COUNT7_CONTROL_UP_STIMULUS_MASK 0x000000000000001f - -/* SH_PERFORMANCE_COUNT7_CONTROL_UP_EVENT */ -/* Description: Counter 7 up event select (1-greater than, 0-equal) */ -#define SH_PERFORMANCE_COUNT7_CONTROL_UP_EVENT_SHFT 5 -#define SH_PERFORMANCE_COUNT7_CONTROL_UP_EVENT_MASK 0x0000000000000020 - -/* SH_PERFORMANCE_COUNT7_CONTROL_UP_POLARITY */ -/* Description: Counter 7 up polarity select (1-negative edge, 0-po */ -/* sitive edge) */ -#define SH_PERFORMANCE_COUNT7_CONTROL_UP_POLARITY_SHFT 6 -#define SH_PERFORMANCE_COUNT7_CONTROL_UP_POLARITY_MASK 0x0000000000000040 - -/* SH_PERFORMANCE_COUNT7_CONTROL_UP_MODE */ -/* Description: Counter 7 up mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT7_CONTROL_UP_MODE_SHFT 7 -#define SH_PERFORMANCE_COUNT7_CONTROL_UP_MODE_MASK 0x0000000000000080 - -/* SH_PERFORMANCE_COUNT7_CONTROL_DN_STIMULUS */ -/* Description: Counter 7 down stimulus */ -#define SH_PERFORMANCE_COUNT7_CONTROL_DN_STIMULUS_SHFT 8 -#define SH_PERFORMANCE_COUNT7_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00 - -/* SH_PERFORMANCE_COUNT7_CONTROL_DN_EVENT */ -/* Description: Counter 7 down event select (1-greater than, 0-equa */ -#define SH_PERFORMANCE_COUNT7_CONTROL_DN_EVENT_SHFT 13 -#define SH_PERFORMANCE_COUNT7_CONTROL_DN_EVENT_MASK 0x0000000000002000 - -/* SH_PERFORMANCE_COUNT7_CONTROL_DN_POLARITY */ -/* Description: Counter 7 down polarity select (1-negative edge, 0- */ -/* positive edge) */ -#define SH_PERFORMANCE_COUNT7_CONTROL_DN_POLARITY_SHFT 14 -#define SH_PERFORMANCE_COUNT7_CONTROL_DN_POLARITY_MASK 0x0000000000004000 - -/* SH_PERFORMANCE_COUNT7_CONTROL_DN_MODE */ -/* Description: Counter 7 down mode select (1-internal, 0-external) */ -#define SH_PERFORMANCE_COUNT7_CONTROL_DN_MODE_SHFT 15 -#define SH_PERFORMANCE_COUNT7_CONTROL_DN_MODE_MASK 0x0000000000008000 - -/* SH_PERFORMANCE_COUNT7_CONTROL_INC_ENABLE */ -/* Description: Counter 7 enable increment */ -#define SH_PERFORMANCE_COUNT7_CONTROL_INC_ENABLE_SHFT 16 -#define SH_PERFORMANCE_COUNT7_CONTROL_INC_ENABLE_MASK 0x0000000000010000 - -/* SH_PERFORMANCE_COUNT7_CONTROL_DEC_ENABLE */ -/* Description: Counter 7 enable decrement */ -#define SH_PERFORMANCE_COUNT7_CONTROL_DEC_ENABLE_SHFT 17 -#define SH_PERFORMANCE_COUNT7_CONTROL_DEC_ENABLE_MASK 0x0000000000020000 - -/* SH_PERFORMANCE_COUNT7_CONTROL_PEAK_DET_ENABLE */ -/* Description: Counter 7 enable peak detection */ -#define SH_PERFORMANCE_COUNT7_CONTROL_PEAK_DET_ENABLE_SHFT 18 -#define SH_PERFORMANCE_COUNT7_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000 - -/* ==================================================================== */ -/* Register "SH_PROFILE_DN_CONTROL" */ -/* Profile Counter Down Control */ -/* ==================================================================== */ - -#define SH_PROFILE_DN_CONTROL 0x0000000110100000 -#define SH_PROFILE_DN_CONTROL_MASK 0x00000000000000ff -#define SH_PROFILE_DN_CONTROL_INIT 0x00000000000000b8 - -/* SH_PROFILE_DN_CONTROL_STIMULUS */ -/* Description: Counter stimulus */ -#define SH_PROFILE_DN_CONTROL_STIMULUS_SHFT 0 -#define SH_PROFILE_DN_CONTROL_STIMULUS_MASK 0x000000000000001f - -/* SH_PROFILE_DN_CONTROL_EVENT */ -/* Description: Counter event select (1-greater than, 0-equal) */ -#define SH_PROFILE_DN_CONTROL_EVENT_SHFT 5 -#define SH_PROFILE_DN_CONTROL_EVENT_MASK 0x0000000000000020 - -/* SH_PROFILE_DN_CONTROL_POLARITY */ -/* Description: Counter polarity select (1-negative edge, 0-positiv */ -/* e edge) */ -#define SH_PROFILE_DN_CONTROL_POLARITY_SHFT 6 -#define SH_PROFILE_DN_CONTROL_POLARITY_MASK 0x0000000000000040 - -/* SH_PROFILE_DN_CONTROL_MODE */ -/* Description: Counter mode select (1-internal, 0-external) */ -#define SH_PROFILE_DN_CONTROL_MODE_SHFT 7 -#define SH_PROFILE_DN_CONTROL_MODE_MASK 0x0000000000000080 - -/* ==================================================================== */ -/* Register "SH_PROFILE_PEAK_CONTROL" */ -/* Profile Counter Peak Control */ -/* ==================================================================== */ - -#define SH_PROFILE_PEAK_CONTROL 0x0000000110100080 -#define SH_PROFILE_PEAK_CONTROL_MASK 0x0000000000000068 -#define SH_PROFILE_PEAK_CONTROL_INIT 0x0000000000000060 - -/* SH_PROFILE_PEAK_CONTROL_STIMULUS */ -/* Description: Counter stimulus */ -#define SH_PROFILE_PEAK_CONTROL_STIMULUS_SHFT 3 -#define SH_PROFILE_PEAK_CONTROL_STIMULUS_MASK 0x0000000000000008 - -/* SH_PROFILE_PEAK_CONTROL_EVENT */ -/* Description: Counter event select (0-greater than, 1-equal) */ -#define SH_PROFILE_PEAK_CONTROL_EVENT_SHFT 5 -#define SH_PROFILE_PEAK_CONTROL_EVENT_MASK 0x0000000000000020 - -/* SH_PROFILE_PEAK_CONTROL_POLARITY */ -/* Description: Counter polarity select (0-negative edge, 1-positiv */ -/* e edge) */ -#define SH_PROFILE_PEAK_CONTROL_POLARITY_SHFT 6 -#define SH_PROFILE_PEAK_CONTROL_POLARITY_MASK 0x0000000000000040 - -/* ==================================================================== */ -/* Register "SH_PROFILE_RANGE" */ -/* Profile Counter Range */ -/* ==================================================================== */ - -#define SH_PROFILE_RANGE 0x0000000110100100 -#define SH_PROFILE_RANGE_MASK 0xffffffffffffffff -#define SH_PROFILE_RANGE_INIT 0x0000000000000000 - -/* SH_PROFILE_RANGE_RANGE0 */ -/* Description: Profiling range 0 */ -#define SH_PROFILE_RANGE_RANGE0_SHFT 0 -#define SH_PROFILE_RANGE_RANGE0_MASK 0x00000000000000ff - -/* SH_PROFILE_RANGE_RANGE1 */ -/* Description: Profiling range 1 */ -#define SH_PROFILE_RANGE_RANGE1_SHFT 8 -#define SH_PROFILE_RANGE_RANGE1_MASK 0x000000000000ff00 - -/* SH_PROFILE_RANGE_RANGE2 */ -/* Description: Profiling range 2 */ -#define SH_PROFILE_RANGE_RANGE2_SHFT 16 -#define SH_PROFILE_RANGE_RANGE2_MASK 0x0000000000ff0000 - -/* SH_PROFILE_RANGE_RANGE3 */ -/* Description: Profiling range 3 */ -#define SH_PROFILE_RANGE_RANGE3_SHFT 24 -#define SH_PROFILE_RANGE_RANGE3_MASK 0x00000000ff000000 - -/* SH_PROFILE_RANGE_RANGE4 */ -/* Description: Profiling range 4 */ -#define SH_PROFILE_RANGE_RANGE4_SHFT 32 -#define SH_PROFILE_RANGE_RANGE4_MASK 0x000000ff00000000 - -/* SH_PROFILE_RANGE_RANGE5 */ -/* Description: Profiling range 5 */ -#define SH_PROFILE_RANGE_RANGE5_SHFT 40 -#define SH_PROFILE_RANGE_RANGE5_MASK 0x0000ff0000000000 - -/* SH_PROFILE_RANGE_RANGE6 */ -/* Description: Profiling range 6 */ -#define SH_PROFILE_RANGE_RANGE6_SHFT 48 -#define SH_PROFILE_RANGE_RANGE6_MASK 0x00ff000000000000 - -/* SH_PROFILE_RANGE_RANGE7 */ -/* Description: Profiling range 7 */ -#define SH_PROFILE_RANGE_RANGE7_SHFT 56 -#define SH_PROFILE_RANGE_RANGE7_MASK 0xff00000000000000 - -/* ==================================================================== */ -/* Register "SH_PROFILE_UP_CONTROL" */ -/* Profile Counter Up Control */ -/* ==================================================================== */ - -#define SH_PROFILE_UP_CONTROL 0x0000000110100180 -#define SH_PROFILE_UP_CONTROL_MASK 0x00000000000000ff -#define SH_PROFILE_UP_CONTROL_INIT 0x00000000000000b8 - -/* SH_PROFILE_UP_CONTROL_STIMULUS */ -/* Description: Counter stimulus */ -#define SH_PROFILE_UP_CONTROL_STIMULUS_SHFT 0 -#define SH_PROFILE_UP_CONTROL_STIMULUS_MASK 0x000000000000001f - -/* SH_PROFILE_UP_CONTROL_EVENT */ -/* Description: Counter event select (1-greater than, 0-equal) */ -#define SH_PROFILE_UP_CONTROL_EVENT_SHFT 5 -#define SH_PROFILE_UP_CONTROL_EVENT_MASK 0x0000000000000020 - -/* SH_PROFILE_UP_CONTROL_POLARITY */ -/* Description: Counter polarity select (1-negative edge, 0-positiv */ -/* e edge) */ -#define SH_PROFILE_UP_CONTROL_POLARITY_SHFT 6 -#define SH_PROFILE_UP_CONTROL_POLARITY_MASK 0x0000000000000040 - -/* SH_PROFILE_UP_CONTROL_MODE */ -/* Description: Counter mode select (1-internal, 0-external) */ -#define SH_PROFILE_UP_CONTROL_MODE_SHFT 7 -#define SH_PROFILE_UP_CONTROL_MODE_MASK 0x0000000000000080 - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNTER0" */ -/* Performance Counter 0 */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNTER0 0x0000000110110000 -#define SH_PERFORMANCE_COUNTER0_MASK 0x00000000ffffffff -#define SH_PERFORMANCE_COUNTER0_INIT 0x0000000000000000 - -/* SH_PERFORMANCE_COUNTER0_COUNT */ -/* Description: Counter 0 */ -#define SH_PERFORMANCE_COUNTER0_COUNT_SHFT 0 -#define SH_PERFORMANCE_COUNTER0_COUNT_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNTER1" */ -/* Performance Counter 1 */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNTER1 0x0000000110120000 -#define SH_PERFORMANCE_COUNTER1_MASK 0x00000000ffffffff -#define SH_PERFORMANCE_COUNTER1_INIT 0x0000000000000000 - -/* SH_PERFORMANCE_COUNTER1_COUNT */ -/* Description: Counter 1 */ -#define SH_PERFORMANCE_COUNTER1_COUNT_SHFT 0 -#define SH_PERFORMANCE_COUNTER1_COUNT_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNTER2" */ -/* Performance Counter 2 */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNTER2 0x0000000110130000 -#define SH_PERFORMANCE_COUNTER2_MASK 0x00000000ffffffff -#define SH_PERFORMANCE_COUNTER2_INIT 0x0000000000000000 - -/* SH_PERFORMANCE_COUNTER2_COUNT */ -/* Description: Counter 2 */ -#define SH_PERFORMANCE_COUNTER2_COUNT_SHFT 0 -#define SH_PERFORMANCE_COUNTER2_COUNT_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNTER3" */ -/* Performance Counter 3 */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNTER3 0x0000000110140000 -#define SH_PERFORMANCE_COUNTER3_MASK 0x00000000ffffffff -#define SH_PERFORMANCE_COUNTER3_INIT 0x0000000000000000 - -/* SH_PERFORMANCE_COUNTER3_COUNT */ -/* Description: Counter 3 */ -#define SH_PERFORMANCE_COUNTER3_COUNT_SHFT 0 -#define SH_PERFORMANCE_COUNTER3_COUNT_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNTER4" */ -/* Performance Counter 4 */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNTER4 0x0000000110150000 -#define SH_PERFORMANCE_COUNTER4_MASK 0x00000000ffffffff -#define SH_PERFORMANCE_COUNTER4_INIT 0x0000000000000000 - -/* SH_PERFORMANCE_COUNTER4_COUNT */ -/* Description: Counter 4 */ -#define SH_PERFORMANCE_COUNTER4_COUNT_SHFT 0 -#define SH_PERFORMANCE_COUNTER4_COUNT_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNTER5" */ -/* Performance Counter 5 */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNTER5 0x0000000110160000 -#define SH_PERFORMANCE_COUNTER5_MASK 0x00000000ffffffff -#define SH_PERFORMANCE_COUNTER5_INIT 0x0000000000000000 - -/* SH_PERFORMANCE_COUNTER5_COUNT */ -/* Description: Counter 5 */ -#define SH_PERFORMANCE_COUNTER5_COUNT_SHFT 0 -#define SH_PERFORMANCE_COUNTER5_COUNT_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNTER6" */ -/* Performance Counter 6 */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNTER6 0x0000000110170000 -#define SH_PERFORMANCE_COUNTER6_MASK 0x00000000ffffffff -#define SH_PERFORMANCE_COUNTER6_INIT 0x0000000000000000 - -/* SH_PERFORMANCE_COUNTER6_COUNT */ -/* Description: Counter 6 */ -#define SH_PERFORMANCE_COUNTER6_COUNT_SHFT 0 -#define SH_PERFORMANCE_COUNTER6_COUNT_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_PERFORMANCE_COUNTER7" */ -/* Performance Counter 7 */ -/* ==================================================================== */ - -#define SH_PERFORMANCE_COUNTER7 0x0000000110180000 -#define SH_PERFORMANCE_COUNTER7_MASK 0x00000000ffffffff -#define SH_PERFORMANCE_COUNTER7_INIT 0x0000000000000000 - -/* SH_PERFORMANCE_COUNTER7_COUNT */ -/* Description: Counter 7 */ -#define SH_PERFORMANCE_COUNTER7_COUNT_SHFT 0 -#define SH_PERFORMANCE_COUNTER7_COUNT_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_PROFILE_COUNTER" */ -/* Profile Counter */ -/* ==================================================================== */ - -#define SH_PROFILE_COUNTER 0x0000000110190000 -#define SH_PROFILE_COUNTER_MASK 0x00000000000000ff -#define SH_PROFILE_COUNTER_INIT 0x0000000000000000 - -/* SH_PROFILE_COUNTER_COUNTER */ -/* Description: Counter Value */ -#define SH_PROFILE_COUNTER_COUNTER_SHFT 0 -#define SH_PROFILE_COUNTER_COUNTER_MASK 0x00000000000000ff - -/* ==================================================================== */ -/* Register "SH_PROFILE_PEAK" */ -/* Profile Peak Counter */ -/* ==================================================================== */ - -#define SH_PROFILE_PEAK 0x0000000110190080 -#define SH_PROFILE_PEAK_MASK 0x00000000000000ff -#define SH_PROFILE_PEAK_INIT 0x0000000000000000 - -/* SH_PROFILE_PEAK_COUNTER */ -/* Description: Counter Value */ -#define SH_PROFILE_PEAK_COUNTER_SHFT 0 -#define SH_PROFILE_PEAK_COUNTER_MASK 0x00000000000000ff - -/* ==================================================================== */ /* Register "SH_PTC_0" */ /* Puge Translation Cache Message Configuration Information */ /* ==================================================================== */ - -#define SH_PTC_0 0x00000001101a0000 +#define SH_PTC_0 0x00000001101a0000UL #define SH_PTC_0_MASK 0x80000000fffffffd #define SH_PTC_0_INIT 0x0000000000000000 @@ -25636,8 +182,7 @@ /* Register "SH_PTC_1" */ /* Puge Translation Cache Message Configuration Information */ /* ==================================================================== */ - -#define SH_PTC_1 0x00000001101a0080 +#define SH_PTC_1 0x00000001101a0080UL #define SH_PTC_1_MASK 0x9ffffffffffff000 #define SH_PTC_1_INIT 0x0000000000000000 @@ -25651,5946 +196,4 @@ #define SH_PTC_1_START_SHFT 63 #define SH_PTC_1_START_MASK 0x8000000000000000 -/* ==================================================================== */ -/* Register "SH_PTC_PARMS" */ -/* PTC Time-out parmaeters */ -/* ==================================================================== */ - -#define SH_PTC_PARMS 0x00000001101a0100 -#define SH_PTC_PARMS_MASK 0x0000000fffffffff -#define SH_PTC_PARMS_INIT 0x00000007ffffffff - -/* SH_PTC_PARMS_PTC_TO_WRAP */ -/* Description: PTC time-out period */ -#define SH_PTC_PARMS_PTC_TO_WRAP_SHFT 0 -#define SH_PTC_PARMS_PTC_TO_WRAP_MASK 0x0000000000ffffff - -/* SH_PTC_PARMS_PTC_TO_VAL */ -/* Description: PTC time-out valid */ -#define SH_PTC_PARMS_PTC_TO_VAL_SHFT 24 -#define SH_PTC_PARMS_PTC_TO_VAL_MASK 0x0000000fff000000 - -/* ==================================================================== */ -/* Register "SH_INT_CMPA" */ -/* RTC Compare Value for Processor A */ -/* ==================================================================== */ - -#define SH_INT_CMPA 0x00000001101b0000 -#define SH_INT_CMPA_MASK 0x007fffffffffffff -#define SH_INT_CMPA_INIT 0x0000000000000000 - -/* SH_INT_CMPA_REAL_TIME_CMPA */ -/* Description: Real Time Clock Compare */ -#define SH_INT_CMPA_REAL_TIME_CMPA_SHFT 0 -#define SH_INT_CMPA_REAL_TIME_CMPA_MASK 0x007fffffffffffff - -/* ==================================================================== */ -/* Register "SH_INT_CMPB" */ -/* RTC Compare Value for Processor B */ -/* ==================================================================== */ - -#define SH_INT_CMPB 0x00000001101b0080 -#define SH_INT_CMPB_MASK 0x007fffffffffffff -#define SH_INT_CMPB_INIT 0x0000000000000000 - -/* SH_INT_CMPB_REAL_TIME_CMPB */ -/* Description: Real Time Clock Compare */ -#define SH_INT_CMPB_REAL_TIME_CMPB_SHFT 0 -#define SH_INT_CMPB_REAL_TIME_CMPB_MASK 0x007fffffffffffff - -/* ==================================================================== */ -/* Register "SH_INT_CMPC" */ -/* RTC Compare Value for Processor C */ -/* ==================================================================== */ - -#define SH_INT_CMPC 0x00000001101b0100 -#define SH_INT_CMPC_MASK 0x007fffffffffffff -#define SH_INT_CMPC_INIT 0x0000000000000000 - -/* SH_INT_CMPC_REAL_TIME_CMPC */ -/* Description: Real Time Clock Compare */ -#define SH_INT_CMPC_REAL_TIME_CMPC_SHFT 0 -#define SH_INT_CMPC_REAL_TIME_CMPC_MASK 0x007fffffffffffff - -/* ==================================================================== */ -/* Register "SH_INT_CMPD" */ -/* RTC Compare Value for Processor D */ -/* ==================================================================== */ - -#define SH_INT_CMPD 0x00000001101b0180 -#define SH_INT_CMPD_MASK 0x007fffffffffffff -#define SH_INT_CMPD_INIT 0x0000000000000000 - -/* SH_INT_CMPD_REAL_TIME_CMPD */ -/* Description: Real Time Clock Compare */ -#define SH_INT_CMPD_REAL_TIME_CMPD_SHFT 0 -#define SH_INT_CMPD_REAL_TIME_CMPD_MASK 0x007fffffffffffff - -/* ==================================================================== */ -/* Register "SH_INT_PROF" */ -/* Profile Compare Registers */ -/* ==================================================================== */ - -#define SH_INT_PROF 0x00000001101b0200 -#define SH_INT_PROF_MASK 0x00000000ffffffff -#define SH_INT_PROF_INIT 0x0000000000000000 - -/* SH_INT_PROF_PROFILE_COMPARE */ -/* Description: Profile Compare */ -#define SH_INT_PROF_PROFILE_COMPARE_SHFT 0 -#define SH_INT_PROF_PROFILE_COMPARE_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_RTC" */ -/* Real-time Clock */ -/* ==================================================================== */ - -#define SH_RTC 0x00000001101c0000UL -#define SH_RTC_MASK 0x007fffffffffffffUL -#define SH_RTC_INIT 0x0000000000000000 - -/* SH_RTC_REAL_TIME_CLOCK */ -/* Description: Real-time Clock */ -#define SH_RTC_REAL_TIME_CLOCK_SHFT 0 -#define SH_RTC_REAL_TIME_CLOCK_MASK 0x007fffffffffffffUL - -/* ==================================================================== */ -/* Register "SH_SCRATCH0" */ -/* Scratch Register 0 */ -/* ==================================================================== */ - -#define SH_SCRATCH0 0x00000001101d0000 -#define SH_SCRATCH0_MASK 0xffffffffffffffff -#define SH_SCRATCH0_INIT 0x0000000000000000 - -/* SH_SCRATCH0_SCRATCH0 */ -/* Description: Scratch register 0 */ -#define SH_SCRATCH0_SCRATCH0_SHFT 0 -#define SH_SCRATCH0_SCRATCH0_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_SCRATCH0_ALIAS" */ -/* Scratch Register 0 Alias Address */ -/* ==================================================================== */ - -#define SH_SCRATCH0_ALIAS 0x00000001101d0008 - -/* ==================================================================== */ -/* Register "SH_SCRATCH1" */ -/* Scratch Register 1 */ -/* ==================================================================== */ - -#define SH_SCRATCH1 0x00000001101d0080 -#define SH_SCRATCH1_MASK 0xffffffffffffffff -#define SH_SCRATCH1_INIT 0x0000000000000000 - -/* SH_SCRATCH1_SCRATCH1 */ -/* Description: Scratch register 1 */ -#define SH_SCRATCH1_SCRATCH1_SHFT 0 -#define SH_SCRATCH1_SCRATCH1_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_SCRATCH1_ALIAS" */ -/* Scratch Register 1 Alias Address */ -/* ==================================================================== */ - -#define SH_SCRATCH1_ALIAS 0x00000001101d0088 - -/* ==================================================================== */ -/* Register "SH_SCRATCH2" */ -/* Scratch Register 2 */ -/* ==================================================================== */ - -#define SH_SCRATCH2 0x00000001101d0100 -#define SH_SCRATCH2_MASK 0xffffffffffffffff -#define SH_SCRATCH2_INIT 0x0000000000000000 - -/* SH_SCRATCH2_SCRATCH2 */ -/* Description: Scratch register 2 */ -#define SH_SCRATCH2_SCRATCH2_SHFT 0 -#define SH_SCRATCH2_SCRATCH2_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_SCRATCH2_ALIAS" */ -/* Scratch Register 2 Alias Address */ -/* ==================================================================== */ - -#define SH_SCRATCH2_ALIAS 0x00000001101d0108 - -/* ==================================================================== */ -/* Register "SH_SCRATCH3" */ -/* Scratch Register 3 */ -/* ==================================================================== */ - -#define SH_SCRATCH3 0x00000001101d0180 -#define SH_SCRATCH3_MASK 0x0000000000000001 -#define SH_SCRATCH3_INIT 0x0000000000000000 - -/* SH_SCRATCH3_SCRATCH3 */ -/* Description: Scratch register 3 */ -#define SH_SCRATCH3_SCRATCH3_SHFT 0 -#define SH_SCRATCH3_SCRATCH3_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_SCRATCH3_ALIAS" */ -/* Scratch Register 3 Alias Address */ -/* ==================================================================== */ - -#define SH_SCRATCH3_ALIAS 0x00000001101d0188 - -/* ==================================================================== */ -/* Register "SH_SCRATCH4" */ -/* Scratch Register 4 */ -/* ==================================================================== */ - -#define SH_SCRATCH4 0x00000001101d0200 -#define SH_SCRATCH4_MASK 0x0000000000000001 -#define SH_SCRATCH4_INIT 0x0000000000000000 - -/* SH_SCRATCH4_SCRATCH4 */ -/* Description: Scratch register 4 */ -#define SH_SCRATCH4_SCRATCH4_SHFT 0 -#define SH_SCRATCH4_SCRATCH4_MASK 0x0000000000000001 - -/* ==================================================================== */ -/* Register "SH_SCRATCH4_ALIAS" */ -/* Scratch Register 4 Alias Address */ -/* ==================================================================== */ - -#define SH_SCRATCH4_ALIAS 0x00000001101d0208 - -/* ==================================================================== */ -/* Register "SH_CRB_MESSAGE_CONTROL" */ -/* Coherent Request Buffer Message Control */ -/* ==================================================================== */ - -#define SH_CRB_MESSAGE_CONTROL 0x0000000120000000 -#define SH_CRB_MESSAGE_CONTROL_MASK 0xffffffff00000fff -#define SH_CRB_MESSAGE_CONTROL_INIT 0x0000000000000006 - -/* SH_CRB_MESSAGE_CONTROL_SYSTEM_COHERENCE_ENABLE */ -/* Description: System Coherence Enabled */ -#define SH_CRB_MESSAGE_CONTROL_SYSTEM_COHERENCE_ENABLE_SHFT 0 -#define SH_CRB_MESSAGE_CONTROL_SYSTEM_COHERENCE_ENABLE_MASK 0x0000000000000001 - -/* SH_CRB_MESSAGE_CONTROL_LOCAL_SPECULATIVE_MESSAGE_ENABLE */ -/* Description: Speculative Read Requests to Local Memory Enabled */ -#define SH_CRB_MESSAGE_CONTROL_LOCAL_SPECULATIVE_MESSAGE_ENABLE_SHFT 1 -#define SH_CRB_MESSAGE_CONTROL_LOCAL_SPECULATIVE_MESSAGE_ENABLE_MASK 0x0000000000000002 - -/* SH_CRB_MESSAGE_CONTROL_REMOTE_SPECULATIVE_MESSAGE_ENABLE */ -/* Description: Speculative Read Requests to Remote Memory Enabled */ -#define SH_CRB_MESSAGE_CONTROL_REMOTE_SPECULATIVE_MESSAGE_ENABLE_SHFT 2 -#define SH_CRB_MESSAGE_CONTROL_REMOTE_SPECULATIVE_MESSAGE_ENABLE_MASK 0x0000000000000004 - -/* SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR */ -/* Description: Define color of message */ -#define SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR_SHFT 3 -#define SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR_MASK 0x0000000000000008 - -/* SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR_ENABLE */ -/* Description: Enable color message processing */ -#define SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR_ENABLE_SHFT 4 -#define SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR_ENABLE_MASK 0x0000000000000010 - -/* SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_FSB_ENABLE */ -/* Description: Enable FSB RRB Mismatch check */ -#define SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_SHFT 5 -#define SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_MASK 0x0000000000000020 - -/* SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_FSB_ENABLE */ -/* Description: Enable FSB WRB Mismatch check */ -#define SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_SHFT 6 -#define SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_MASK 0x0000000000000040 - -/* SH_CRB_MESSAGE_CONTROL_IRB_ATTRIBUTE_MISMATCH_FSB_ENABLE */ -/* Description: Enable FSB IRB Mismatch check */ -#define SH_CRB_MESSAGE_CONTROL_IRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_SHFT 7 -#define SH_CRB_MESSAGE_CONTROL_IRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_MASK 0x0000000000000080 - -/* SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_XB_ENABLE */ -/* Description: Enable XB RRB Mismatch check */ -#define SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_XB_ENABLE_SHFT 8 -#define SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_XB_ENABLE_MASK 0x0000000000000100 - -/* SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_XB_ENABLE */ -/* Description: Enable XB WRB Mismatch check */ -#define SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_XB_ENABLE_SHFT 9 -#define SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_XB_ENABLE_MASK 0x0000000000000200 - -/* SH_CRB_MESSAGE_CONTROL_SUPPRESS_BOGUS_WRITES */ -/* Description: ignor residual write data */ -#define SH_CRB_MESSAGE_CONTROL_SUPPRESS_BOGUS_WRITES_SHFT 10 -#define SH_CRB_MESSAGE_CONTROL_SUPPRESS_BOGUS_WRITES_MASK 0x0000000000000400 - -/* SH_CRB_MESSAGE_CONTROL_ENABLE_IVACK_CONSOLIDATION */ -/* Description: enable IVACK reply consolidation */ -#define SH_CRB_MESSAGE_CONTROL_ENABLE_IVACK_CONSOLIDATION_SHFT 11 -#define SH_CRB_MESSAGE_CONTROL_ENABLE_IVACK_CONSOLIDATION_MASK 0x0000000000000800 - -/* SH_CRB_MESSAGE_CONTROL_IVACK_STALL_COUNT */ -/* Description: IVACK stall counter */ -#define SH_CRB_MESSAGE_CONTROL_IVACK_STALL_COUNT_SHFT 32 -#define SH_CRB_MESSAGE_CONTROL_IVACK_STALL_COUNT_MASK 0x0000ffff00000000 - -/* SH_CRB_MESSAGE_CONTROL_IVACK_THROTTLE_CONTROL */ -/* Description: IVACK throttling limit/timer control */ -#define SH_CRB_MESSAGE_CONTROL_IVACK_THROTTLE_CONTROL_SHFT 48 -#define SH_CRB_MESSAGE_CONTROL_IVACK_THROTTLE_CONTROL_MASK 0xffff000000000000 - -/* ==================================================================== */ -/* Register "SH_CRB_NACK_LIMIT" */ -/* CRB Nack Limit */ -/* ==================================================================== */ - -#define SH_CRB_NACK_LIMIT 0x0000000120000080 -#define SH_CRB_NACK_LIMIT_MASK 0x800000000000ffff -#define SH_CRB_NACK_LIMIT_INIT 0x0000000000000000 - -/* SH_CRB_NACK_LIMIT_LIMIT */ -/* Description: Nack Count Limit */ -#define SH_CRB_NACK_LIMIT_LIMIT_SHFT 0 -#define SH_CRB_NACK_LIMIT_LIMIT_MASK 0x0000000000000fff - -/* SH_CRB_NACK_LIMIT_PRI_FREQ */ -/* Description: Frequency at which priority count is incremented */ -#define SH_CRB_NACK_LIMIT_PRI_FREQ_SHFT 12 -#define SH_CRB_NACK_LIMIT_PRI_FREQ_MASK 0x000000000000f000 - -/* SH_CRB_NACK_LIMIT_ENABLE */ -/* Description: Enable NACK limit detection */ -#define SH_CRB_NACK_LIMIT_ENABLE_SHFT 63 -#define SH_CRB_NACK_LIMIT_ENABLE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_CRB_TIMEOUT_PRESCALE" */ -/* Coherent Request Buffer Timeout Prescale */ -/* ==================================================================== */ - -#define SH_CRB_TIMEOUT_PRESCALE 0x0000000120000100 -#define SH_CRB_TIMEOUT_PRESCALE_MASK 0x00000000ffffffff -#define SH_CRB_TIMEOUT_PRESCALE_INIT 0x0000000000000000 - -/* SH_CRB_TIMEOUT_PRESCALE_SCALING_FACTOR */ -/* Description: CRB Time-out Prescale Factor */ -#define SH_CRB_TIMEOUT_PRESCALE_SCALING_FACTOR_SHFT 0 -#define SH_CRB_TIMEOUT_PRESCALE_SCALING_FACTOR_MASK 0x00000000ffffffff - -/* ==================================================================== */ -/* Register "SH_CRB_TIMEOUT_SKID" */ -/* Coherent Request Buffer Timeout Skid Limit */ -/* ==================================================================== */ - -#define SH_CRB_TIMEOUT_SKID 0x0000000120000180 -#define SH_CRB_TIMEOUT_SKID_MASK 0x800000000000003f -#define SH_CRB_TIMEOUT_SKID_INIT 0x0000000000000007 - -/* SH_CRB_TIMEOUT_SKID_SKID */ -/* Description: CRB Time-out Skid */ -#define SH_CRB_TIMEOUT_SKID_SKID_SHFT 0 -#define SH_CRB_TIMEOUT_SKID_SKID_MASK 0x000000000000003f - -/* SH_CRB_TIMEOUT_SKID_RESET_SKID_COUNT */ -/* Description: Reset Skid counter */ -#define SH_CRB_TIMEOUT_SKID_RESET_SKID_COUNT_SHFT 63 -#define SH_CRB_TIMEOUT_SKID_RESET_SKID_COUNT_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_MEMORY_WRITE_STATUS_0" */ -/* Memory Write Status for CPU 0 */ -/* ==================================================================== */ - -#define SH_MEMORY_WRITE_STATUS_0 0x0000000120070000 -#define SH_MEMORY_WRITE_STATUS_0_MASK 0x000000000000003f -#define SH_MEMORY_WRITE_STATUS_0_INIT 0x0000000000000000 - -/* SH_MEMORY_WRITE_STATUS_0_PENDING_WRITE_COUNT */ -/* Description: Pending Write Count */ -#define SH_MEMORY_WRITE_STATUS_0_PENDING_WRITE_COUNT_SHFT 0 -#define SH_MEMORY_WRITE_STATUS_0_PENDING_WRITE_COUNT_MASK 0x000000000000003f - -/* ==================================================================== */ -/* Register "SH_MEMORY_WRITE_STATUS_1" */ -/* Memory Write Status for CPU 1 */ -/* ==================================================================== */ - -#define SH_MEMORY_WRITE_STATUS_1 0x0000000120070080 -#define SH_MEMORY_WRITE_STATUS_1_MASK 0x000000000000003f -#define SH_MEMORY_WRITE_STATUS_1_INIT 0x0000000000000000 - -/* SH_MEMORY_WRITE_STATUS_1_PENDING_WRITE_COUNT */ -/* Description: Pending Write Count */ -#define SH_MEMORY_WRITE_STATUS_1_PENDING_WRITE_COUNT_SHFT 0 -#define SH_MEMORY_WRITE_STATUS_1_PENDING_WRITE_COUNT_MASK 0x000000000000003f - -/* ==================================================================== */ -/* Register "SH_PIO_WRITE_STATUS_0" */ -/* PIO Write Status for CPU 0 */ -/* ==================================================================== */ - -#define SH_PIO_WRITE_STATUS_0 0x0000000120070200 -#define SH_PIO_WRITE_STATUS_0_MASK 0xbf03ffffffffffff -#define SH_PIO_WRITE_STATUS_0_INIT 0x8000000000000000 - -/* SH_PIO_WRITE_STATUS_0_MULTI_WRITE_ERROR */ -/* Description: More than one PIO write error occurred */ -#define SH_PIO_WRITE_STATUS_0_MULTI_WRITE_ERROR_SHFT 0 -#define SH_PIO_WRITE_STATUS_0_MULTI_WRITE_ERROR_MASK 0x0000000000000001 - -/* SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK */ -/* Description: Deaklock response detected */ -#define SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK_SHFT 1 -#define SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK_MASK 0x0000000000000002 - -/* SH_PIO_WRITE_STATUS_0_WRITE_ERROR */ -/* Description: Error response detected */ -#define SH_PIO_WRITE_STATUS_0_WRITE_ERROR_SHFT 2 -#define SH_PIO_WRITE_STATUS_0_WRITE_ERROR_MASK 0x0000000000000004 - -/* SH_PIO_WRITE_STATUS_0_WRITE_ERROR_ADDRESS */ -/* Description: Address associated with error response */ -#define SH_PIO_WRITE_STATUS_0_WRITE_ERROR_ADDRESS_SHFT 3 -#define SH_PIO_WRITE_STATUS_0_WRITE_ERROR_ADDRESS_MASK 0x0003fffffffffff8 - -/* SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT */ -/* Description: Count of currently pending PIO writes */ -#define SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_SHFT 56 -#define SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_MASK 0x3f00000000000000 - -/* SH_PIO_WRITE_STATUS_0_WRITES_OK */ -/* Description: No pending writes or errors */ -#define SH_PIO_WRITE_STATUS_0_WRITES_OK_SHFT 63 -#define SH_PIO_WRITE_STATUS_0_WRITES_OK_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PIO_WRITE_STATUS_1" */ -/* PIO Write Status for CPU 1 */ -/* ==================================================================== */ - -#define SH_PIO_WRITE_STATUS_1 0x0000000120070280 -#define SH_PIO_WRITE_STATUS_1_MASK 0xbf03ffffffffffff -#define SH_PIO_WRITE_STATUS_1_INIT 0x8000000000000000 - -/* SH_PIO_WRITE_STATUS_1_MULTI_WRITE_ERROR */ -/* Description: More than one PIO write error occurred */ -#define SH_PIO_WRITE_STATUS_1_MULTI_WRITE_ERROR_SHFT 0 -#define SH_PIO_WRITE_STATUS_1_MULTI_WRITE_ERROR_MASK 0x0000000000000001 - -/* SH_PIO_WRITE_STATUS_1_WRITE_DEADLOCK */ -/* Description: Deaklock response detected */ -#define SH_PIO_WRITE_STATUS_1_WRITE_DEADLOCK_SHFT 1 -#define SH_PIO_WRITE_STATUS_1_WRITE_DEADLOCK_MASK 0x0000000000000002 - -/* SH_PIO_WRITE_STATUS_1_WRITE_ERROR */ -/* Description: Error response detected */ -#define SH_PIO_WRITE_STATUS_1_WRITE_ERROR_SHFT 2 -#define SH_PIO_WRITE_STATUS_1_WRITE_ERROR_MASK 0x0000000000000004 - -/* SH_PIO_WRITE_STATUS_1_WRITE_ERROR_ADDRESS */ -/* Description: Address associated with error response */ -#define SH_PIO_WRITE_STATUS_1_WRITE_ERROR_ADDRESS_SHFT 3 -#define SH_PIO_WRITE_STATUS_1_WRITE_ERROR_ADDRESS_MASK 0x0003fffffffffff8 - -/* SH_PIO_WRITE_STATUS_1_PENDING_WRITE_COUNT */ -/* Description: Count of currently pending PIO writes */ -#define SH_PIO_WRITE_STATUS_1_PENDING_WRITE_COUNT_SHFT 56 -#define SH_PIO_WRITE_STATUS_1_PENDING_WRITE_COUNT_MASK 0x3f00000000000000 - -/* SH_PIO_WRITE_STATUS_1_WRITES_OK */ -/* Description: No pending writes or errors */ -#define SH_PIO_WRITE_STATUS_1_WRITES_OK_SHFT 63 -#define SH_PIO_WRITE_STATUS_1_WRITES_OK_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_PIO_WRITE_STATUS_0_ALIAS" */ -/* ==================================================================== */ - -#define SH_PIO_WRITE_STATUS_0_ALIAS 0x0000000120070208 - -/* ==================================================================== */ -/* Register "SH_PIO_WRITE_STATUS_1_ALIAS" */ -/* ==================================================================== */ - -#define SH_PIO_WRITE_STATUS_1_ALIAS 0x0000000120070288 - -/* ==================================================================== */ -/* Register "SH_MEMORY_WRITE_STATUS_NON_USER_0" */ -/* Memory Write Status for CPU 0. OS access only */ -/* ==================================================================== */ - -#define SH_MEMORY_WRITE_STATUS_NON_USER_0 0x0000000120070400 -#define SH_MEMORY_WRITE_STATUS_NON_USER_0_MASK 0x800000000000003f -#define SH_MEMORY_WRITE_STATUS_NON_USER_0_INIT 0x0000000000000000 - -/* SH_MEMORY_WRITE_STATUS_NON_USER_0_PENDING_WRITE_COUNT */ -/* Description: Pending Write Count */ -#define SH_MEMORY_WRITE_STATUS_NON_USER_0_PENDING_WRITE_COUNT_SHFT 0 -#define SH_MEMORY_WRITE_STATUS_NON_USER_0_PENDING_WRITE_COUNT_MASK 0x000000000000003f - -/* SH_MEMORY_WRITE_STATUS_NON_USER_0_CLEAR */ -/* Description: Clear pending write count */ -#define SH_MEMORY_WRITE_STATUS_NON_USER_0_CLEAR_SHFT 63 -#define SH_MEMORY_WRITE_STATUS_NON_USER_0_CLEAR_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_MEMORY_WRITE_STATUS_NON_USER_1" */ -/* Memory Write Status for CPU 1. OS access only */ -/* ==================================================================== */ - -#define SH_MEMORY_WRITE_STATUS_NON_USER_1 0x0000000120070480 -#define SH_MEMORY_WRITE_STATUS_NON_USER_1_MASK 0x800000000000003f -#define SH_MEMORY_WRITE_STATUS_NON_USER_1_INIT 0x0000000000000000 - -/* SH_MEMORY_WRITE_STATUS_NON_USER_1_PENDING_WRITE_COUNT */ -/* Description: Pending Write Count */ -#define SH_MEMORY_WRITE_STATUS_NON_USER_1_PENDING_WRITE_COUNT_SHFT 0 -#define SH_MEMORY_WRITE_STATUS_NON_USER_1_PENDING_WRITE_COUNT_MASK 0x000000000000003f - -/* SH_MEMORY_WRITE_STATUS_NON_USER_1_CLEAR */ -/* Description: Clear pending write count */ -#define SH_MEMORY_WRITE_STATUS_NON_USER_1_CLEAR_SHFT 63 -#define SH_MEMORY_WRITE_STATUS_NON_USER_1_CLEAR_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_MMRBIST_ERR" */ -/* Error capture for bist read errors */ -/* ==================================================================== */ - -#define SH_MMRBIST_ERR 0x0000000100000080 -#define SH_MMRBIST_ERR_MASK 0x00000071ffffffff -#define SH_MMRBIST_ERR_INIT 0x0000000000000000 - -/* SH_MMRBIST_ERR_ADDR */ -/* Description: dword address of bist error */ -#define SH_MMRBIST_ERR_ADDR_SHFT 0 -#define SH_MMRBIST_ERR_ADDR_MASK 0x00000001ffffffff - -/* SH_MMRBIST_ERR_DETECTED */ -/* Description: error detected flag */ -#define SH_MMRBIST_ERR_DETECTED_SHFT 36 -#define SH_MMRBIST_ERR_DETECTED_MASK 0x0000001000000000 - -/* SH_MMRBIST_ERR_MULTIPLE_DETECTED */ -/* Description: multiple errors detected flag */ -#define SH_MMRBIST_ERR_MULTIPLE_DETECTED_SHFT 37 -#define SH_MMRBIST_ERR_MULTIPLE_DETECTED_MASK 0x0000002000000000 - -/* SH_MMRBIST_ERR_CANCELLED */ -/* Description: mmr/bist was cancelled */ -#define SH_MMRBIST_ERR_CANCELLED_SHFT 38 -#define SH_MMRBIST_ERR_CANCELLED_MASK 0x0000004000000000 - -/* ==================================================================== */ -/* Register "SH_MISC_ERR_HDR_LOWER" */ -/* Header capture register */ -/* ==================================================================== */ - -#define SH_MISC_ERR_HDR_LOWER 0x0000000100000088 -#define SH_MISC_ERR_HDR_LOWER_MASK 0x93fffffffffffff8 -#define SH_MISC_ERR_HDR_LOWER_INIT 0x0000000000000000 - -/* SH_MISC_ERR_HDR_LOWER_ADDR */ -/* Description: upper bits of reference address */ -#define SH_MISC_ERR_HDR_LOWER_ADDR_SHFT 3 -#define SH_MISC_ERR_HDR_LOWER_ADDR_MASK 0x0000000ffffffff8 - -/* SH_MISC_ERR_HDR_LOWER_CMD */ -/* Description: command of reference */ -#define SH_MISC_ERR_HDR_LOWER_CMD_SHFT 36 -#define SH_MISC_ERR_HDR_LOWER_CMD_MASK 0x00000ff000000000 - -/* SH_MISC_ERR_HDR_LOWER_SRC */ -/* Description: source node of reference */ -#define SH_MISC_ERR_HDR_LOWER_SRC_SHFT 44 -#define SH_MISC_ERR_HDR_LOWER_SRC_MASK 0x03fff00000000000 - -/* SH_MISC_ERR_HDR_LOWER_WRITE */ -/* Description: reference is a write */ -#define SH_MISC_ERR_HDR_LOWER_WRITE_SHFT 60 -#define SH_MISC_ERR_HDR_LOWER_WRITE_MASK 0x1000000000000000 - -/* SH_MISC_ERR_HDR_LOWER_VALID */ -/* Description: set when capture occurs */ -#define SH_MISC_ERR_HDR_LOWER_VALID_SHFT 63 -#define SH_MISC_ERR_HDR_LOWER_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_MISC_ERR_HDR_UPPER" */ -/* Error header capture packet and protocol errors */ -/* ==================================================================== */ - -#define SH_MISC_ERR_HDR_UPPER 0x0000000100000090 -#define SH_MISC_ERR_HDR_UPPER_MASK 0x000000001ff000ff -#define SH_MISC_ERR_HDR_UPPER_INIT 0x0000000000000000 - -/* SH_MISC_ERR_HDR_UPPER_DIR_PROTOCOL */ -/* Description: indicates a directory protocol error captured */ -#define SH_MISC_ERR_HDR_UPPER_DIR_PROTOCOL_SHFT 0 -#define SH_MISC_ERR_HDR_UPPER_DIR_PROTOCOL_MASK 0x0000000000000001 - -/* SH_MISC_ERR_HDR_UPPER_ILLEGAL_CMD */ -/* Description: indicates an illegal command error captured */ -#define SH_MISC_ERR_HDR_UPPER_ILLEGAL_CMD_SHFT 1 -#define SH_MISC_ERR_HDR_UPPER_ILLEGAL_CMD_MASK 0x0000000000000002 - -/* SH_MISC_ERR_HDR_UPPER_NONEXIST_ADDR */ -/* Description: indicates a non-existent memory error captured */ -#define SH_MISC_ERR_HDR_UPPER_NONEXIST_ADDR_SHFT 2 -#define SH_MISC_ERR_HDR_UPPER_NONEXIST_ADDR_MASK 0x0000000000000004 - -/* SH_MISC_ERR_HDR_UPPER_RMW_UC */ -/* Description: indicates an uncorrectable store rmw */ -#define SH_MISC_ERR_HDR_UPPER_RMW_UC_SHFT 3 -#define SH_MISC_ERR_HDR_UPPER_RMW_UC_MASK 0x0000000000000008 - -/* SH_MISC_ERR_HDR_UPPER_RMW_COR */ -/* Description: indicates a correctable store rmw */ -#define SH_MISC_ERR_HDR_UPPER_RMW_COR_SHFT 4 -#define SH_MISC_ERR_HDR_UPPER_RMW_COR_MASK 0x0000000000000010 - -/* SH_MISC_ERR_HDR_UPPER_DIR_ACC */ -/* Description: indicates a data request to directory memory error */ -/* captured */ -#define SH_MISC_ERR_HDR_UPPER_DIR_ACC_SHFT 5 -#define SH_MISC_ERR_HDR_UPPER_DIR_ACC_MASK 0x0000000000000020 - -/* SH_MISC_ERR_HDR_UPPER_PI_PKT_SIZE */ -/* Description: indicates a pkt size error from pi */ -#define SH_MISC_ERR_HDR_UPPER_PI_PKT_SIZE_SHFT 6 -#define SH_MISC_ERR_HDR_UPPER_PI_PKT_SIZE_MASK 0x0000000000000040 - -/* SH_MISC_ERR_HDR_UPPER_XN_PKT_SIZE */ -/* Description: indicates a pkt size error from xn */ -#define SH_MISC_ERR_HDR_UPPER_XN_PKT_SIZE_SHFT 7 -#define SH_MISC_ERR_HDR_UPPER_XN_PKT_SIZE_MASK 0x0000000000000080 - -/* SH_MISC_ERR_HDR_UPPER_ECHO */ -#define SH_MISC_ERR_HDR_UPPER_ECHO_SHFT 20 -#define SH_MISC_ERR_HDR_UPPER_ECHO_MASK 0x000000001ff00000 - -/* ==================================================================== */ -/* Register "SH_DIR_UC_ERR_HDR_LOWER" */ -/* Header capture register */ -/* ==================================================================== */ - -#define SH_DIR_UC_ERR_HDR_LOWER 0x0000000100000098 -#define SH_DIR_UC_ERR_HDR_LOWER_MASK 0x93fffffffffffff8 -#define SH_DIR_UC_ERR_HDR_LOWER_INIT 0x0000000000000000 - -/* SH_DIR_UC_ERR_HDR_LOWER_ADDR */ -/* Description: upper bits of reference address */ -#define SH_DIR_UC_ERR_HDR_LOWER_ADDR_SHFT 3 -#define SH_DIR_UC_ERR_HDR_LOWER_ADDR_MASK 0x0000000ffffffff8 - -/* SH_DIR_UC_ERR_HDR_LOWER_CMD */ -/* Description: command of reference */ -#define SH_DIR_UC_ERR_HDR_LOWER_CMD_SHFT 36 -#define SH_DIR_UC_ERR_HDR_LOWER_CMD_MASK 0x00000ff000000000 - -/* SH_DIR_UC_ERR_HDR_LOWER_SRC */ -/* Description: source node of reference */ -#define SH_DIR_UC_ERR_HDR_LOWER_SRC_SHFT 44 -#define SH_DIR_UC_ERR_HDR_LOWER_SRC_MASK 0x03fff00000000000 - -/* SH_DIR_UC_ERR_HDR_LOWER_WRITE */ -/* Description: reference is a write */ -#define SH_DIR_UC_ERR_HDR_LOWER_WRITE_SHFT 60 -#define SH_DIR_UC_ERR_HDR_LOWER_WRITE_MASK 0x1000000000000000 - -/* SH_DIR_UC_ERR_HDR_LOWER_VALID */ -/* Description: set when capture occurs */ -#define SH_DIR_UC_ERR_HDR_LOWER_VALID_SHFT 63 -#define SH_DIR_UC_ERR_HDR_LOWER_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_DIR_UC_ERR_HDR_UPPER" */ -/* Error header capture packet and protocol errors */ -/* ==================================================================== */ - -#define SH_DIR_UC_ERR_HDR_UPPER 0x00000001000000a0 -#define SH_DIR_UC_ERR_HDR_UPPER_MASK 0x000000001ff00008 -#define SH_DIR_UC_ERR_HDR_UPPER_INIT 0x0000000000000000 - -/* SH_DIR_UC_ERR_HDR_UPPER_DIR_UC */ -/* Description: indicates uncorrectable directory error captured */ -#define SH_DIR_UC_ERR_HDR_UPPER_DIR_UC_SHFT 3 -#define SH_DIR_UC_ERR_HDR_UPPER_DIR_UC_MASK 0x0000000000000008 - -/* SH_DIR_UC_ERR_HDR_UPPER_ECHO */ -#define SH_DIR_UC_ERR_HDR_UPPER_ECHO_SHFT 20 -#define SH_DIR_UC_ERR_HDR_UPPER_ECHO_MASK 0x000000001ff00000 - -/* ==================================================================== */ -/* Register "SH_DIR_COR_ERR_HDR_LOWER" */ -/* Header capture register */ -/* ==================================================================== */ - -#define SH_DIR_COR_ERR_HDR_LOWER 0x00000001000000a8 -#define SH_DIR_COR_ERR_HDR_LOWER_MASK 0x93fffffffffffff8 -#define SH_DIR_COR_ERR_HDR_LOWER_INIT 0x0000000000000000 - -/* SH_DIR_COR_ERR_HDR_LOWER_ADDR */ -/* Description: upper bits of reference address */ -#define SH_DIR_COR_ERR_HDR_LOWER_ADDR_SHFT 3 -#define SH_DIR_COR_ERR_HDR_LOWER_ADDR_MASK 0x0000000ffffffff8 - -/* SH_DIR_COR_ERR_HDR_LOWER_CMD */ -/* Description: command of reference */ -#define SH_DIR_COR_ERR_HDR_LOWER_CMD_SHFT 36 -#define SH_DIR_COR_ERR_HDR_LOWER_CMD_MASK 0x00000ff000000000 - -/* SH_DIR_COR_ERR_HDR_LOWER_SRC */ -/* Description: source node of reference */ -#define SH_DIR_COR_ERR_HDR_LOWER_SRC_SHFT 44 -#define SH_DIR_COR_ERR_HDR_LOWER_SRC_MASK 0x03fff00000000000 - -/* SH_DIR_COR_ERR_HDR_LOWER_WRITE */ -/* Description: reference is a write */ -#define SH_DIR_COR_ERR_HDR_LOWER_WRITE_SHFT 60 -#define SH_DIR_COR_ERR_HDR_LOWER_WRITE_MASK 0x1000000000000000 - -/* SH_DIR_COR_ERR_HDR_LOWER_VALID */ -/* Description: set when capture occurs */ -#define SH_DIR_COR_ERR_HDR_LOWER_VALID_SHFT 63 -#define SH_DIR_COR_ERR_HDR_LOWER_VALID_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_DIR_COR_ERR_HDR_UPPER" */ -/* Error header capture packet and protocol errors */ -/* ==================================================================== */ - -#define SH_DIR_COR_ERR_HDR_UPPER 0x00000001000000b0 -#define SH_DIR_COR_ERR_HDR_UPPER_MASK 0x000000001ff00100 -#define SH_DIR_COR_ERR_HDR_UPPER_INIT 0x0000000000000000 - -/* SH_DIR_COR_ERR_HDR_UPPER_DIR_COR */ -/* Description: indicates correctable directory error captured */ -#define SH_DIR_COR_ERR_HDR_UPPER_DIR_COR_SHFT 8 -#define SH_DIR_COR_ERR_HDR_UPPER_DIR_COR_MASK 0x0000000000000100 - -/* SH_DIR_COR_ERR_HDR_UPPER_ECHO */ -#define SH_DIR_COR_ERR_HDR_UPPER_ECHO_SHFT 20 -#define SH_DIR_COR_ERR_HDR_UPPER_ECHO_MASK 0x000000001ff00000 - -/* ==================================================================== */ -/* Register "SH_MEM_ERROR_SUMMARY" */ -/* Memory error flags */ -/* ==================================================================== */ - -#define SH_MEM_ERROR_SUMMARY 0x00000001000000b8 -#define SH_MEM_ERROR_SUMMARY_MASK 0x00000007f77777ff -#define SH_MEM_ERROR_SUMMARY_INIT 0x0000000000000000 - -/* SH_MEM_ERROR_SUMMARY_ILLEGAL_CMD */ -/* Description: illegal command error */ -#define SH_MEM_ERROR_SUMMARY_ILLEGAL_CMD_SHFT 0 -#define SH_MEM_ERROR_SUMMARY_ILLEGAL_CMD_MASK 0x0000000000000001 - -/* SH_MEM_ERROR_SUMMARY_NONEXIST_ADDR */ -/* Description: non-existent memory error */ -#define SH_MEM_ERROR_SUMMARY_NONEXIST_ADDR_SHFT 1 -#define SH_MEM_ERROR_SUMMARY_NONEXIST_ADDR_MASK 0x0000000000000002 - -/* SH_MEM_ERROR_SUMMARY_DQLP_DIR_PERR */ -/* Description: directory protocol error in dqlp */ -#define SH_MEM_ERROR_SUMMARY_DQLP_DIR_PERR_SHFT 2 -#define SH_MEM_ERROR_SUMMARY_DQLP_DIR_PERR_MASK 0x0000000000000004 - -/* SH_MEM_ERROR_SUMMARY_DQRP_DIR_PERR */ -/* Description: directory protocol error in dqrp */ -#define SH_MEM_ERROR_SUMMARY_DQRP_DIR_PERR_SHFT 3 -#define SH_MEM_ERROR_SUMMARY_DQRP_DIR_PERR_MASK 0x0000000000000008 - -/* SH_MEM_ERROR_SUMMARY_DQLP_DIR_UC */ -/* Description: uncorrectable directory error in dqlp */ -#define SH_MEM_ERROR_SUMMARY_DQLP_DIR_UC_SHFT 4 -#define SH_MEM_ERROR_SUMMARY_DQLP_DIR_UC_MASK 0x0000000000000010 - -/* SH_MEM_ERROR_SUMMARY_DQLP_DIR_COR */ -/* Description: correctable directory error in dqlp */ -#define SH_MEM_ERROR_SUMMARY_DQLP_DIR_COR_SHFT 5 -#define SH_MEM_ERROR_SUMMARY_DQLP_DIR_COR_MASK 0x0000000000000020 - -/* SH_MEM_ERROR_SUMMARY_DQRP_DIR_UC */ -/* Description: uncorrectable directory error in dqrp */ -#define SH_MEM_ERROR_SUMMARY_DQRP_DIR_UC_SHFT 6 -#define SH_MEM_ERROR_SUMMARY_DQRP_DIR_UC_MASK 0x0000000000000040 - -/* SH_MEM_ERROR_SUMMARY_DQRP_DIR_COR */ -/* Description: correctable directory error in dqrp */ -#define SH_MEM_ERROR_SUMMARY_DQRP_DIR_COR_SHFT 7 -#define SH_MEM_ERROR_SUMMARY_DQRP_DIR_COR_MASK 0x0000000000000080 - -/* SH_MEM_ERROR_SUMMARY_ACX_INT_HW */ -/* Description: hardware interrupt from acx */ -#define SH_MEM_ERROR_SUMMARY_ACX_INT_HW_SHFT 8 -#define SH_MEM_ERROR_SUMMARY_ACX_INT_HW_MASK 0x0000000000000100 - -/* SH_MEM_ERROR_SUMMARY_ACY_INT_HW */ -/* Description: hardware interrupt from acy */ -#define SH_MEM_ERROR_SUMMARY_ACY_INT_HW_SHFT 9 -#define SH_MEM_ERROR_SUMMARY_ACY_INT_HW_MASK 0x0000000000000200 - -/* SH_MEM_ERROR_SUMMARY_DIR_ACC */ -/* Description: directory memory access error */ -#define SH_MEM_ERROR_SUMMARY_DIR_ACC_SHFT 10 -#define SH_MEM_ERROR_SUMMARY_DIR_ACC_MASK 0x0000000000000400 - -/* SH_MEM_ERROR_SUMMARY_DQLP_INT_UC */ -/* Description: uncorrectable interrupt from dqlp */ -#define SH_MEM_ERROR_SUMMARY_DQLP_INT_UC_SHFT 12 -#define SH_MEM_ERROR_SUMMARY_DQLP_INT_UC_MASK 0x0000000000001000 - -/* SH_MEM_ERROR_SUMMARY_DQLP_INT_COR */ -/* Description: correctable interrupt from dqlp */ -#define SH_MEM_ERROR_SUMMARY_DQLP_INT_COR_SHFT 13 -#define SH_MEM_ERROR_SUMMARY_DQLP_INT_COR_MASK 0x0000000000002000 - -/* SH_MEM_ERROR_SUMMARY_DQLP_INT_HW */ -/* Description: hardware interrupt from dqlp */ -#define SH_MEM_ERROR_SUMMARY_DQLP_INT_HW_SHFT 14 -#define SH_MEM_ERROR_SUMMARY_DQLP_INT_HW_MASK 0x0000000000004000 - -/* SH_MEM_ERROR_SUMMARY_DQLS_INT_UC */ -/* Description: uncorrectable interrupt from dqls */ -#define SH_MEM_ERROR_SUMMARY_DQLS_INT_UC_SHFT 16 -#define SH_MEM_ERROR_SUMMARY_DQLS_INT_UC_MASK 0x0000000000010000 - -/* SH_MEM_ERROR_SUMMARY_DQLS_INT_COR */ -/* Description: correctable interrupt from dqls */ -#define SH_MEM_ERROR_SUMMARY_DQLS_INT_COR_SHFT 17 -#define SH_MEM_ERROR_SUMMARY_DQLS_INT_COR_MASK 0x0000000000020000 - -/* SH_MEM_ERROR_SUMMARY_DQLS_INT_HW */ -/* Description: hardware interrupt from dqls */ -#define SH_MEM_ERROR_SUMMARY_DQLS_INT_HW_SHFT 18 -#define SH_MEM_ERROR_SUMMARY_DQLS_INT_HW_MASK 0x0000000000040000 - -/* SH_MEM_ERROR_SUMMARY_DQRP_INT_UC */ -/* Description: uncorrectable interrupt from dqrp */ -#define SH_MEM_ERROR_SUMMARY_DQRP_INT_UC_SHFT 20 -#define SH_MEM_ERROR_SUMMARY_DQRP_INT_UC_MASK 0x0000000000100000 - -/* SH_MEM_ERROR_SUMMARY_DQRP_INT_COR */ -/* Description: correctable interrupt from dqrp */ -#define SH_MEM_ERROR_SUMMARY_DQRP_INT_COR_SHFT 21 -#define SH_MEM_ERROR_SUMMARY_DQRP_INT_COR_MASK 0x0000000000200000 - -/* SH_MEM_ERROR_SUMMARY_DQRP_INT_HW */ -/* Description: hardware interrupt from dqrp */ -#define SH_MEM_ERROR_SUMMARY_DQRP_INT_HW_SHFT 22 -#define SH_MEM_ERROR_SUMMARY_DQRP_INT_HW_MASK 0x0000000000400000 - -/* SH_MEM_ERROR_SUMMARY_DQRS_INT_UC */ -/* Description: uncorrectable interrupt from dqrs */ -#define SH_MEM_ERROR_SUMMARY_DQRS_INT_UC_SHFT 24 -#define SH_MEM_ERROR_SUMMARY_DQRS_INT_UC_MASK 0x0000000001000000 - -/* SH_MEM_ERROR_SUMMARY_DQRS_INT_COR */ -/* Description: correctable interrupt from dqrs */ -#define SH_MEM_ERROR_SUMMARY_DQRS_INT_COR_SHFT 25 -#define SH_MEM_ERROR_SUMMARY_DQRS_INT_COR_MASK 0x0000000002000000 - -/* SH_MEM_ERROR_SUMMARY_DQRS_INT_HW */ -/* Description: hardware interrupt from dqrs */ -#define SH_MEM_ERROR_SUMMARY_DQRS_INT_HW_SHFT 26 -#define SH_MEM_ERROR_SUMMARY_DQRS_INT_HW_MASK 0x0000000004000000 - -/* SH_MEM_ERROR_SUMMARY_PI_REPLY_OVERFLOW */ -/* Description: too many reply packets came from pi */ -#define SH_MEM_ERROR_SUMMARY_PI_REPLY_OVERFLOW_SHFT 28 -#define SH_MEM_ERROR_SUMMARY_PI_REPLY_OVERFLOW_MASK 0x0000000010000000 - -/* SH_MEM_ERROR_SUMMARY_XN_REPLY_OVERFLOW */ -/* Description: too many reply packets came from xn */ -#define SH_MEM_ERROR_SUMMARY_XN_REPLY_OVERFLOW_SHFT 29 -#define SH_MEM_ERROR_SUMMARY_XN_REPLY_OVERFLOW_MASK 0x0000000020000000 - -/* SH_MEM_ERROR_SUMMARY_PI_REQUEST_OVERFLOW */ -/* Description: too many request packets came from pi */ -#define SH_MEM_ERROR_SUMMARY_PI_REQUEST_OVERFLOW_SHFT 30 -#define SH_MEM_ERROR_SUMMARY_PI_REQUEST_OVERFLOW_MASK 0x0000000040000000 - -/* SH_MEM_ERROR_SUMMARY_XN_REQUEST_OVERFLOW */ -/* Description: too many request packets came from xn */ -#define SH_MEM_ERROR_SUMMARY_XN_REQUEST_OVERFLOW_SHFT 31 -#define SH_MEM_ERROR_SUMMARY_XN_REQUEST_OVERFLOW_MASK 0x0000000080000000 - -/* SH_MEM_ERROR_SUMMARY_RED_BLACK_ERR_TIMEOUT */ -/* Description: red black scheme did not clean up soon enough */ -#define SH_MEM_ERROR_SUMMARY_RED_BLACK_ERR_TIMEOUT_SHFT 32 -#define SH_MEM_ERROR_SUMMARY_RED_BLACK_ERR_TIMEOUT_MASK 0x0000000100000000 - -/* SH_MEM_ERROR_SUMMARY_PI_PKT_SIZE */ -/* Description: received data bearing packet from pi with wrong siz */ -#define SH_MEM_ERROR_SUMMARY_PI_PKT_SIZE_SHFT 33 -#define SH_MEM_ERROR_SUMMARY_PI_PKT_SIZE_MASK 0x0000000200000000 - -/* SH_MEM_ERROR_SUMMARY_XN_PKT_SIZE */ -/* Description: received data bearing packet from xn with wrong siz */ -#define SH_MEM_ERROR_SUMMARY_XN_PKT_SIZE_SHFT 34 -#define SH_MEM_ERROR_SUMMARY_XN_PKT_SIZE_MASK 0x0000000400000000 - -/* ==================================================================== */ -/* Register "SH_MEM_ERROR_SUMMARY_ALIAS" */ -/* Memory error flags clear alias */ -/* ==================================================================== */ - -#define SH_MEM_ERROR_SUMMARY_ALIAS 0x00000001000000c0 - -/* ==================================================================== */ -/* Register "SH_MEM_ERROR_OVERFLOW" */ -/* Memory error flags */ -/* ==================================================================== */ - -#define SH_MEM_ERROR_OVERFLOW 0x00000001000000c8 -#define SH_MEM_ERROR_OVERFLOW_MASK 0x00000007f77777ff -#define SH_MEM_ERROR_OVERFLOW_INIT 0x0000000000000000 - -/* SH_MEM_ERROR_OVERFLOW_ILLEGAL_CMD */ -/* Description: illegal command error */ -#define SH_MEM_ERROR_OVERFLOW_ILLEGAL_CMD_SHFT 0 -#define SH_MEM_ERROR_OVERFLOW_ILLEGAL_CMD_MASK 0x0000000000000001 - -/* SH_MEM_ERROR_OVERFLOW_NONEXIST_ADDR */ -/* Description: non-existent memory error */ -#define SH_MEM_ERROR_OVERFLOW_NONEXIST_ADDR_SHFT 1 -#define SH_MEM_ERROR_OVERFLOW_NONEXIST_ADDR_MASK 0x0000000000000002 - -/* SH_MEM_ERROR_OVERFLOW_DQLP_DIR_PERR */ -/* Description: directory protocol error in dqlp */ -#define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_PERR_SHFT 2 -#define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_PERR_MASK 0x0000000000000004 - -/* SH_MEM_ERROR_OVERFLOW_DQRP_DIR_PERR */ -/* Description: directory protocol error in dqrp */ -#define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_PERR_SHFT 3 -#define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_PERR_MASK 0x0000000000000008 - -/* SH_MEM_ERROR_OVERFLOW_DQLP_DIR_UC */ -/* Description: uncorrectable directory error in dqlp */ -#define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_UC_SHFT 4 -#define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_UC_MASK 0x0000000000000010 - -/* SH_MEM_ERROR_OVERFLOW_DQLP_DIR_COR */ -/* Description: correctable directory error in dqlp */ -#define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_COR_SHFT 5 -#define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_COR_MASK 0x0000000000000020 - -/* SH_MEM_ERROR_OVERFLOW_DQRP_DIR_UC */ -/* Description: uncorrectable directory error in dqrp */ -#define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_UC_SHFT 6 -#define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_UC_MASK 0x0000000000000040 - -/* SH_MEM_ERROR_OVERFLOW_DQRP_DIR_COR */ -/* Description: correctable directory error in dqrp */ -#define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_COR_SHFT 7 -#define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_COR_MASK 0x0000000000000080 - -/* SH_MEM_ERROR_OVERFLOW_ACX_INT_HW */ -/* Description: hardware interrupt from acx */ -#define SH_MEM_ERROR_OVERFLOW_ACX_INT_HW_SHFT 8 -#define SH_MEM_ERROR_OVERFLOW_ACX_INT_HW_MASK 0x0000000000000100 - -/* SH_MEM_ERROR_OVERFLOW_ACY_INT_HW */ -/* Description: hardware interrupt from acy */ -#define SH_MEM_ERROR_OVERFLOW_ACY_INT_HW_SHFT 9 -#define SH_MEM_ERROR_OVERFLOW_ACY_INT_HW_MASK 0x0000000000000200 - -/* SH_MEM_ERROR_OVERFLOW_DIR_ACC */ -/* Description: directory memory access error */ -#define SH_MEM_ERROR_OVERFLOW_DIR_ACC_SHFT 10 -#define SH_MEM_ERROR_OVERFLOW_DIR_ACC_MASK 0x0000000000000400 - -/* SH_MEM_ERROR_OVERFLOW_DQLP_INT_UC */ -/* Description: uncorrectable interrupt from dqlp */ -#define SH_MEM_ERROR_OVERFLOW_DQLP_INT_UC_SHFT 12 -#define SH_MEM_ERROR_OVERFLOW_DQLP_INT_UC_MASK 0x0000000000001000 - -/* SH_MEM_ERROR_OVERFLOW_DQLP_INT_COR */ -/* Description: correctable interrupt from dqlp */ -#define SH_MEM_ERROR_OVERFLOW_DQLP_INT_COR_SHFT 13 -#define SH_MEM_ERROR_OVERFLOW_DQLP_INT_COR_MASK 0x0000000000002000 - -/* SH_MEM_ERROR_OVERFLOW_DQLP_INT_HW */ -/* Description: hardware interrupt from dqlp */ -#define SH_MEM_ERROR_OVERFLOW_DQLP_INT_HW_SHFT 14 -#define SH_MEM_ERROR_OVERFLOW_DQLP_INT_HW_MASK 0x0000000000004000 - -/* SH_MEM_ERROR_OVERFLOW_DQLS_INT_UC */ -/* Description: uncorrectable interrupt from dqls */ -#define SH_MEM_ERROR_OVERFLOW_DQLS_INT_UC_SHFT 16 -#define SH_MEM_ERROR_OVERFLOW_DQLS_INT_UC_MASK 0x0000000000010000 - -/* SH_MEM_ERROR_OVERFLOW_DQLS_INT_COR */ -/* Description: correctable interrupt from dqls */ -#define SH_MEM_ERROR_OVERFLOW_DQLS_INT_COR_SHFT 17 -#define SH_MEM_ERROR_OVERFLOW_DQLS_INT_COR_MASK 0x0000000000020000 - -/* SH_MEM_ERROR_OVERFLOW_DQLS_INT_HW */ -/* Description: hardware interrupt from dqls */ -#define SH_MEM_ERROR_OVERFLOW_DQLS_INT_HW_SHFT 18 -#define SH_MEM_ERROR_OVERFLOW_DQLS_INT_HW_MASK 0x0000000000040000 - -/* SH_MEM_ERROR_OVERFLOW_DQRP_INT_UC */ -/* Description: uncorrectable interrupt from dqrp */ -#define SH_MEM_ERROR_OVERFLOW_DQRP_INT_UC_SHFT 20 -#define SH_MEM_ERROR_OVERFLOW_DQRP_INT_UC_MASK 0x0000000000100000 - -/* SH_MEM_ERROR_OVERFLOW_DQRP_INT_COR */ -/* Description: correctable interrupt from dqrp */ -#define SH_MEM_ERROR_OVERFLOW_DQRP_INT_COR_SHFT 21 -#define SH_MEM_ERROR_OVERFLOW_DQRP_INT_COR_MASK 0x0000000000200000 - -/* SH_MEM_ERROR_OVERFLOW_DQRP_INT_HW */ -/* Description: hardware interrupt from dqrp */ -#define SH_MEM_ERROR_OVERFLOW_DQRP_INT_HW_SHFT 22 -#define SH_MEM_ERROR_OVERFLOW_DQRP_INT_HW_MASK 0x0000000000400000 - -/* SH_MEM_ERROR_OVERFLOW_DQRS_INT_UC */ -/* Description: uncorrectable interrupt from dqrs */ -#define SH_MEM_ERROR_OVERFLOW_DQRS_INT_UC_SHFT 24 -#define SH_MEM_ERROR_OVERFLOW_DQRS_INT_UC_MASK 0x0000000001000000 - -/* SH_MEM_ERROR_OVERFLOW_DQRS_INT_COR */ -/* Description: correctable interrupt from dqrs */ -#define SH_MEM_ERROR_OVERFLOW_DQRS_INT_COR_SHFT 25 -#define SH_MEM_ERROR_OVERFLOW_DQRS_INT_COR_MASK 0x0000000002000000 - -/* SH_MEM_ERROR_OVERFLOW_DQRS_INT_HW */ -/* Description: hardware interrupt from dqrs */ -#define SH_MEM_ERROR_OVERFLOW_DQRS_INT_HW_SHFT 26 -#define SH_MEM_ERROR_OVERFLOW_DQRS_INT_HW_MASK 0x0000000004000000 - -/* SH_MEM_ERROR_OVERFLOW_PI_REPLY_OVERFLOW */ -/* Description: too many reply packets came from pi */ -#define SH_MEM_ERROR_OVERFLOW_PI_REPLY_OVERFLOW_SHFT 28 -#define SH_MEM_ERROR_OVERFLOW_PI_REPLY_OVERFLOW_MASK 0x0000000010000000 - -/* SH_MEM_ERROR_OVERFLOW_XN_REPLY_OVERFLOW */ -/* Description: too many reply packets came from xn */ -#define SH_MEM_ERROR_OVERFLOW_XN_REPLY_OVERFLOW_SHFT 29 -#define SH_MEM_ERROR_OVERFLOW_XN_REPLY_OVERFLOW_MASK 0x0000000020000000 - -/* SH_MEM_ERROR_OVERFLOW_PI_REQUEST_OVERFLOW */ -/* Description: too many request packets came from pi */ -#define SH_MEM_ERROR_OVERFLOW_PI_REQUEST_OVERFLOW_SHFT 30 -#define SH_MEM_ERROR_OVERFLOW_PI_REQUEST_OVERFLOW_MASK 0x0000000040000000 - -/* SH_MEM_ERROR_OVERFLOW_XN_REQUEST_OVERFLOW */ -/* Description: too many request packets came from xn */ -#define SH_MEM_ERROR_OVERFLOW_XN_REQUEST_OVERFLOW_SHFT 31 -#define SH_MEM_ERROR_OVERFLOW_XN_REQUEST_OVERFLOW_MASK 0x0000000080000000 - -/* SH_MEM_ERROR_OVERFLOW_RED_BLACK_ERR_TIMEOUT */ -/* Description: red black scheme did not clean up soon enough */ -#define SH_MEM_ERROR_OVERFLOW_RED_BLACK_ERR_TIMEOUT_SHFT 32 -#define SH_MEM_ERROR_OVERFLOW_RED_BLACK_ERR_TIMEOUT_MASK 0x0000000100000000 - -/* SH_MEM_ERROR_OVERFLOW_PI_PKT_SIZE */ -/* Description: received data bearing packet from pi with wrong siz */ -#define SH_MEM_ERROR_OVERFLOW_PI_PKT_SIZE_SHFT 33 -#define SH_MEM_ERROR_OVERFLOW_PI_PKT_SIZE_MASK 0x0000000200000000 - -/* SH_MEM_ERROR_OVERFLOW_XN_PKT_SIZE */ -/* Description: received data bearing packet from xn with wrong siz */ -#define SH_MEM_ERROR_OVERFLOW_XN_PKT_SIZE_SHFT 34 -#define SH_MEM_ERROR_OVERFLOW_XN_PKT_SIZE_MASK 0x0000000400000000 - -/* ==================================================================== */ -/* Register "SH_MEM_ERROR_OVERFLOW_ALIAS" */ -/* Memory error flags clear alias */ -/* ==================================================================== */ - -#define SH_MEM_ERROR_OVERFLOW_ALIAS 0x00000001000000d0 - -/* ==================================================================== */ -/* Register "SH_MEM_ERROR_MASK" */ -/* Memory error flags */ -/* ==================================================================== */ - -#define SH_MEM_ERROR_MASK 0x00000001000000d8 -#define SH_MEM_ERROR_MASK_MASK 0x00000007f77777ff -#define SH_MEM_ERROR_MASK_INIT 0x00000007f77773ff - -/* SH_MEM_ERROR_MASK_ILLEGAL_CMD */ -/* Description: illegal command error */ -#define SH_MEM_ERROR_MASK_ILLEGAL_CMD_SHFT 0 -#define SH_MEM_ERROR_MASK_ILLEGAL_CMD_MASK 0x0000000000000001 - -/* SH_MEM_ERROR_MASK_NONEXIST_ADDR */ -/* Description: non-existent memory error */ -#define SH_MEM_ERROR_MASK_NONEXIST_ADDR_SHFT 1 -#define SH_MEM_ERROR_MASK_NONEXIST_ADDR_MASK 0x0000000000000002 - -/* SH_MEM_ERROR_MASK_DQLP_DIR_PERR */ -/* Description: directory protocol error in dqlp */ -#define SH_MEM_ERROR_MASK_DQLP_DIR_PERR_SHFT 2 -#define SH_MEM_ERROR_MASK_DQLP_DIR_PERR_MASK 0x0000000000000004 - -/* SH_MEM_ERROR_MASK_DQRP_DIR_PERR */ -/* Description: directory protocol error in dqrp */ -#define SH_MEM_ERROR_MASK_DQRP_DIR_PERR_SHFT 3 -#define SH_MEM_ERROR_MASK_DQRP_DIR_PERR_MASK 0x0000000000000008 - -/* SH_MEM_ERROR_MASK_DQLP_DIR_UC */ -/* Description: uncorrectable directory error in dqlp */ -#define SH_MEM_ERROR_MASK_DQLP_DIR_UC_SHFT 4 -#define SH_MEM_ERROR_MASK_DQLP_DIR_UC_MASK 0x0000000000000010 - -/* SH_MEM_ERROR_MASK_DQLP_DIR_COR */ -/* Description: correctable directory error in dqlp */ -#define SH_MEM_ERROR_MASK_DQLP_DIR_COR_SHFT 5 -#define SH_MEM_ERROR_MASK_DQLP_DIR_COR_MASK 0x0000000000000020 - -/* SH_MEM_ERROR_MASK_DQRP_DIR_UC */ -/* Description: uncorrectable directory error in dqrp */ -#define SH_MEM_ERROR_MASK_DQRP_DIR_UC_SHFT 6 -#define SH_MEM_ERROR_MASK_DQRP_DIR_UC_MASK 0x0000000000000040 - -/* SH_MEM_ERROR_MASK_DQRP_DIR_COR */ -/* Description: correctable directory error in dqrp */ -#define SH_MEM_ERROR_MASK_DQRP_DIR_COR_SHFT 7 -#define SH_MEM_ERROR_MASK_DQRP_DIR_COR_MASK 0x0000000000000080 - -/* SH_MEM_ERROR_MASK_ACX_INT_HW */ -/* Description: hardware interrupt from acx */ -#define SH_MEM_ERROR_MASK_ACX_INT_HW_SHFT 8 -#define SH_MEM_ERROR_MASK_ACX_INT_HW_MASK 0x0000000000000100 - -/* SH_MEM_ERROR_MASK_ACY_INT_HW */ -/* Description: hardware interrupt from acy */ -#define SH_MEM_ERROR_MASK_ACY_INT_HW_SHFT 9 -#define SH_MEM_ERROR_MASK_ACY_INT_HW_MASK 0x0000000000000200 - -/* SH_MEM_ERROR_MASK_DIR_ACC */ -/* Description: directory memory access error */ -#define SH_MEM_ERROR_MASK_DIR_ACC_SHFT 10 -#define SH_MEM_ERROR_MASK_DIR_ACC_MASK 0x0000000000000400 - -/* SH_MEM_ERROR_MASK_DQLP_INT_UC */ -/* Description: uncorrectable interrupt from dqlp */ -#define SH_MEM_ERROR_MASK_DQLP_INT_UC_SHFT 12 -#define SH_MEM_ERROR_MASK_DQLP_INT_UC_MASK 0x0000000000001000 - -/* SH_MEM_ERROR_MASK_DQLP_INT_COR */ -/* Description: correctable interrupt from dqlp */ -#define SH_MEM_ERROR_MASK_DQLP_INT_COR_SHFT 13 -#define SH_MEM_ERROR_MASK_DQLP_INT_COR_MASK 0x0000000000002000 - -/* SH_MEM_ERROR_MASK_DQLP_INT_HW */ -/* Description: hardware interrupt from dqlp */ -#define SH_MEM_ERROR_MASK_DQLP_INT_HW_SHFT 14 -#define SH_MEM_ERROR_MASK_DQLP_INT_HW_MASK 0x0000000000004000 - -/* SH_MEM_ERROR_MASK_DQLS_INT_UC */ -/* Description: uncorrectable interrupt from dqls */ -#define SH_MEM_ERROR_MASK_DQLS_INT_UC_SHFT 16 -#define SH_MEM_ERROR_MASK_DQLS_INT_UC_MASK 0x0000000000010000 - -/* SH_MEM_ERROR_MASK_DQLS_INT_COR */ -/* Description: correctable interrupt from dqls */ -#define SH_MEM_ERROR_MASK_DQLS_INT_COR_SHFT 17 -#define SH_MEM_ERROR_MASK_DQLS_INT_COR_MASK 0x0000000000020000 - -/* SH_MEM_ERROR_MASK_DQLS_INT_HW */ -/* Description: hardware interrupt from dqls */ -#define SH_MEM_ERROR_MASK_DQLS_INT_HW_SHFT 18 -#define SH_MEM_ERROR_MASK_DQLS_INT_HW_MASK 0x0000000000040000 - -/* SH_MEM_ERROR_MASK_DQRP_INT_UC */ -/* Description: uncorrectable interrupt from dqrp */ -#define SH_MEM_ERROR_MASK_DQRP_INT_UC_SHFT 20 -#define SH_MEM_ERROR_MASK_DQRP_INT_UC_MASK 0x0000000000100000 - -/* SH_MEM_ERROR_MASK_DQRP_INT_COR */ -/* Description: correctable interrupt from dqrp */ -#define SH_MEM_ERROR_MASK_DQRP_INT_COR_SHFT 21 -#define SH_MEM_ERROR_MASK_DQRP_INT_COR_MASK 0x0000000000200000 - -/* SH_MEM_ERROR_MASK_DQRP_INT_HW */ -/* Description: hardware interrupt from dqrp */ -#define SH_MEM_ERROR_MASK_DQRP_INT_HW_SHFT 22 -#define SH_MEM_ERROR_MASK_DQRP_INT_HW_MASK 0x0000000000400000 - -/* SH_MEM_ERROR_MASK_DQRS_INT_UC */ -/* Description: uncorrectable interrupt from dqrs */ -#define SH_MEM_ERROR_MASK_DQRS_INT_UC_SHFT 24 -#define SH_MEM_ERROR_MASK_DQRS_INT_UC_MASK 0x0000000001000000 - -/* SH_MEM_ERROR_MASK_DQRS_INT_COR */ -/* Description: correctable interrupt from dqrs */ -#define SH_MEM_ERROR_MASK_DQRS_INT_COR_SHFT 25 -#define SH_MEM_ERROR_MASK_DQRS_INT_COR_MASK 0x0000000002000000 - -/* SH_MEM_ERROR_MASK_DQRS_INT_HW */ -/* Description: hardware interrupt from dqrs */ -#define SH_MEM_ERROR_MASK_DQRS_INT_HW_SHFT 26 -#define SH_MEM_ERROR_MASK_DQRS_INT_HW_MASK 0x0000000004000000 - -/* SH_MEM_ERROR_MASK_PI_REPLY_OVERFLOW */ -/* Description: too many reply packets came from pi */ -#define SH_MEM_ERROR_MASK_PI_REPLY_OVERFLOW_SHFT 28 -#define SH_MEM_ERROR_MASK_PI_REPLY_OVERFLOW_MASK 0x0000000010000000 - -/* SH_MEM_ERROR_MASK_XN_REPLY_OVERFLOW */ -/* Description: too many reply packets came from xn */ -#define SH_MEM_ERROR_MASK_XN_REPLY_OVERFLOW_SHFT 29 -#define SH_MEM_ERROR_MASK_XN_REPLY_OVERFLOW_MASK 0x0000000020000000 - -/* SH_MEM_ERROR_MASK_PI_REQUEST_OVERFLOW */ -/* Description: too many request packets came from pi */ -#define SH_MEM_ERROR_MASK_PI_REQUEST_OVERFLOW_SHFT 30 -#define SH_MEM_ERROR_MASK_PI_REQUEST_OVERFLOW_MASK 0x0000000040000000 - -/* SH_MEM_ERROR_MASK_XN_REQUEST_OVERFLOW */ -/* Description: too many request packets came from xn */ -#define SH_MEM_ERROR_MASK_XN_REQUEST_OVERFLOW_SHFT 31 -#define SH_MEM_ERROR_MASK_XN_REQUEST_OVERFLOW_MASK 0x0000000080000000 - -/* SH_MEM_ERROR_MASK_RED_BLACK_ERR_TIMEOUT */ -/* Description: red black scheme did not clean up soon enough */ -#define SH_MEM_ERROR_MASK_RED_BLACK_ERR_TIMEOUT_SHFT 32 -#define SH_MEM_ERROR_MASK_RED_BLACK_ERR_TIMEOUT_MASK 0x0000000100000000 - -/* SH_MEM_ERROR_MASK_PI_PKT_SIZE */ -/* Description: received data bearing packet from pi with wrong siz */ -#define SH_MEM_ERROR_MASK_PI_PKT_SIZE_SHFT 33 -#define SH_MEM_ERROR_MASK_PI_PKT_SIZE_MASK 0x0000000200000000 - -/* SH_MEM_ERROR_MASK_XN_PKT_SIZE */ -/* Description: received data bearing packet from xn with wrong siz */ -#define SH_MEM_ERROR_MASK_XN_PKT_SIZE_SHFT 34 -#define SH_MEM_ERROR_MASK_XN_PKT_SIZE_MASK 0x0000000400000000 - -/* ==================================================================== */ -/* Register "SH_X_DIMM_CFG" */ -/* AC Mem Config Registers */ -/* ==================================================================== */ - -#define SH_X_DIMM_CFG 0x0000000100010000 -#define SH_X_DIMM_CFG_MASK 0x0000000f7f7f7f7f -#define SH_X_DIMM_CFG_INIT 0x000000026f4f2f0f - -/* SH_X_DIMM_CFG_DIMM0_SIZE */ -/* Description: DIMM 0 DRAM size */ -#define SH_X_DIMM_CFG_DIMM0_SIZE_SHFT 0 -#define SH_X_DIMM_CFG_DIMM0_SIZE_MASK 0x0000000000000007 - -/* SH_X_DIMM_CFG_DIMM0_2BK */ -/* Description: DIMM 0 has two physical banks */ -#define SH_X_DIMM_CFG_DIMM0_2BK_SHFT 3 -#define SH_X_DIMM_CFG_DIMM0_2BK_MASK 0x0000000000000008 - -/* SH_X_DIMM_CFG_DIMM0_REV */ -/* Description: DIMM 0 physical banks reversed */ -#define SH_X_DIMM_CFG_DIMM0_REV_SHFT 4 -#define SH_X_DIMM_CFG_DIMM0_REV_MASK 0x0000000000000010 - -/* SH_X_DIMM_CFG_DIMM0_CS */ -/* Description: DIMM 0 chip select, addr[35:34] match */ -#define SH_X_DIMM_CFG_DIMM0_CS_SHFT 5 -#define SH_X_DIMM_CFG_DIMM0_CS_MASK 0x0000000000000060 - -/* SH_X_DIMM_CFG_DIMM1_SIZE */ -/* Description: DIMM 1 DRAM size */ -#define SH_X_DIMM_CFG_DIMM1_SIZE_SHFT 8 -#define SH_X_DIMM_CFG_DIMM1_SIZE_MASK 0x0000000000000700 - -/* SH_X_DIMM_CFG_DIMM1_2BK */ -/* Description: DIMM 1 has two physical banks */ -#define SH_X_DIMM_CFG_DIMM1_2BK_SHFT 11 -#define SH_X_DIMM_CFG_DIMM1_2BK_MASK 0x0000000000000800 - -/* SH_X_DIMM_CFG_DIMM1_REV */ -/* Description: DIMM 1 physical banks reversed */ -#define SH_X_DIMM_CFG_DIMM1_REV_SHFT 12 -#define SH_X_DIMM_CFG_DIMM1_REV_MASK 0x0000000000001000 - -/* SH_X_DIMM_CFG_DIMM1_CS */ -/* Description: DIMM 1 chip select, addr[35:34] match */ -#define SH_X_DIMM_CFG_DIMM1_CS_SHFT 13 -#define SH_X_DIMM_CFG_DIMM1_CS_MASK 0x0000000000006000 - -/* SH_X_DIMM_CFG_DIMM2_SIZE */ -/* Description: DIMM 2 DRAM size */ -#define SH_X_DIMM_CFG_DIMM2_SIZE_SHFT 16 -#define SH_X_DIMM_CFG_DIMM2_SIZE_MASK 0x0000000000070000 - -/* SH_X_DIMM_CFG_DIMM2_2BK */ -/* Description: DIMM 2 has two physical banks */ -#define SH_X_DIMM_CFG_DIMM2_2BK_SHFT 19 -#define SH_X_DIMM_CFG_DIMM2_2BK_MASK 0x0000000000080000 - -/* SH_X_DIMM_CFG_DIMM2_REV */ -/* Description: DIMM 2 physical banks reversed */ -#define SH_X_DIMM_CFG_DIMM2_REV_SHFT 20 -#define SH_X_DIMM_CFG_DIMM2_REV_MASK 0x0000000000100000 - -/* SH_X_DIMM_CFG_DIMM2_CS */ -/* Description: DIMM 2 chip select, addr[35:34] match */ -#define SH_X_DIMM_CFG_DIMM2_CS_SHFT 21 -#define SH_X_DIMM_CFG_DIMM2_CS_MASK 0x0000000000600000 - -/* SH_X_DIMM_CFG_DIMM3_SIZE */ -/* Description: DIMM 3 DRAM size */ -#define SH_X_DIMM_CFG_DIMM3_SIZE_SHFT 24 -#define SH_X_DIMM_CFG_DIMM3_SIZE_MASK 0x0000000007000000 - -/* SH_X_DIMM_CFG_DIMM3_2BK */ -/* Description: DIMM 3 has two physical banks */ -#define SH_X_DIMM_CFG_DIMM3_2BK_SHFT 27 -#define SH_X_DIMM_CFG_DIMM3_2BK_MASK 0x0000000008000000 - -/* SH_X_DIMM_CFG_DIMM3_REV */ -/* Description: DIMM 3 physical banks reversed */ -#define SH_X_DIMM_CFG_DIMM3_REV_SHFT 28 -#define SH_X_DIMM_CFG_DIMM3_REV_MASK 0x0000000010000000 - -/* SH_X_DIMM_CFG_DIMM3_CS */ -/* Description: DIMM 3 chip select, addr[35:34] match */ -#define SH_X_DIMM_CFG_DIMM3_CS_SHFT 29 -#define SH_X_DIMM_CFG_DIMM3_CS_MASK 0x0000000060000000 - -/* SH_X_DIMM_CFG_FREQ */ -/* Description: DIMM frequency select */ -#define SH_X_DIMM_CFG_FREQ_SHFT 32 -#define SH_X_DIMM_CFG_FREQ_MASK 0x0000000f00000000 - -/* ==================================================================== */ -/* Register "SH_Y_DIMM_CFG" */ -/* AC Mem Config Registers */ -/* ==================================================================== */ - -#define SH_Y_DIMM_CFG 0x0000000100010008 -#define SH_Y_DIMM_CFG_MASK 0x0000000f7f7f7f7f -#define SH_Y_DIMM_CFG_INIT 0x000000026f4f2f0f - -/* SH_Y_DIMM_CFG_DIMM0_SIZE */ -/* Description: DIMM 0 DRAM size */ -#define SH_Y_DIMM_CFG_DIMM0_SIZE_SHFT 0 -#define SH_Y_DIMM_CFG_DIMM0_SIZE_MASK 0x0000000000000007 - -/* SH_Y_DIMM_CFG_DIMM0_2BK */ -/* Description: DIMM 0 has two physical banks */ -#define SH_Y_DIMM_CFG_DIMM0_2BK_SHFT 3 -#define SH_Y_DIMM_CFG_DIMM0_2BK_MASK 0x0000000000000008 - -/* SH_Y_DIMM_CFG_DIMM0_REV */ -/* Description: DIMM 0 physical banks reversed */ -#define SH_Y_DIMM_CFG_DIMM0_REV_SHFT 4 -#define SH_Y_DIMM_CFG_DIMM0_REV_MASK 0x0000000000000010 - -/* SH_Y_DIMM_CFG_DIMM0_CS */ -/* Description: DIMM 0 chip select, addr[35:34] match */ -#define SH_Y_DIMM_CFG_DIMM0_CS_SHFT 5 -#define SH_Y_DIMM_CFG_DIMM0_CS_MASK 0x0000000000000060 - -/* SH_Y_DIMM_CFG_DIMM1_SIZE */ -/* Description: DIMM 1 DRAM size */ -#define SH_Y_DIMM_CFG_DIMM1_SIZE_SHFT 8 -#define SH_Y_DIMM_CFG_DIMM1_SIZE_MASK 0x0000000000000700 - -/* SH_Y_DIMM_CFG_DIMM1_2BK */ -/* Description: DIMM 1 has two physical banks */ -#define SH_Y_DIMM_CFG_DIMM1_2BK_SHFT 11 -#define SH_Y_DIMM_CFG_DIMM1_2BK_MASK 0x0000000000000800 - -/* SH_Y_DIMM_CFG_DIMM1_REV */ -/* Description: DIMM 1 physical banks reversed */ -#define SH_Y_DIMM_CFG_DIMM1_REV_SHFT 12 -#define SH_Y_DIMM_CFG_DIMM1_REV_MASK 0x0000000000001000 - -/* SH_Y_DIMM_CFG_DIMM1_CS */ -/* Description: DIMM 1 chip select, addr[35:34] match */ -#define SH_Y_DIMM_CFG_DIMM1_CS_SHFT 13 -#define SH_Y_DIMM_CFG_DIMM1_CS_MASK 0x0000000000006000 - -/* SH_Y_DIMM_CFG_DIMM2_SIZE */ -/* Description: DIMM 2 DRAM size */ -#define SH_Y_DIMM_CFG_DIMM2_SIZE_SHFT 16 -#define SH_Y_DIMM_CFG_DIMM2_SIZE_MASK 0x0000000000070000 - -/* SH_Y_DIMM_CFG_DIMM2_2BK */ -/* Description: DIMM 2 has two physical banks */ -#define SH_Y_DIMM_CFG_DIMM2_2BK_SHFT 19 -#define SH_Y_DIMM_CFG_DIMM2_2BK_MASK 0x0000000000080000 - -/* SH_Y_DIMM_CFG_DIMM2_REV */ -/* Description: DIMM 2 physical banks reversed */ -#define SH_Y_DIMM_CFG_DIMM2_REV_SHFT 20 -#define SH_Y_DIMM_CFG_DIMM2_REV_MASK 0x0000000000100000 - -/* SH_Y_DIMM_CFG_DIMM2_CS */ -/* Description: DIMM 2 chip select, addr[35:34] match */ -#define SH_Y_DIMM_CFG_DIMM2_CS_SHFT 21 -#define SH_Y_DIMM_CFG_DIMM2_CS_MASK 0x0000000000600000 - -/* SH_Y_DIMM_CFG_DIMM3_SIZE */ -/* Description: DIMM 3 DRAM size */ -#define SH_Y_DIMM_CFG_DIMM3_SIZE_SHFT 24 -#define SH_Y_DIMM_CFG_DIMM3_SIZE_MASK 0x0000000007000000 - -/* SH_Y_DIMM_CFG_DIMM3_2BK */ -/* Description: DIMM 3 has two physical banks */ -#define SH_Y_DIMM_CFG_DIMM3_2BK_SHFT 27 -#define SH_Y_DIMM_CFG_DIMM3_2BK_MASK 0x0000000008000000 - -/* SH_Y_DIMM_CFG_DIMM3_REV */ -/* Description: DIMM 3 physical banks reversed */ -#define SH_Y_DIMM_CFG_DIMM3_REV_SHFT 28 -#define SH_Y_DIMM_CFG_DIMM3_REV_MASK 0x0000000010000000 - -/* SH_Y_DIMM_CFG_DIMM3_CS */ -/* Description: DIMM 3 chip select, addr[35:34] match */ -#define SH_Y_DIMM_CFG_DIMM3_CS_SHFT 29 -#define SH_Y_DIMM_CFG_DIMM3_CS_MASK 0x0000000060000000 - -/* SH_Y_DIMM_CFG_FREQ */ -/* Description: DIMM frequency select */ -#define SH_Y_DIMM_CFG_FREQ_SHFT 32 -#define SH_Y_DIMM_CFG_FREQ_MASK 0x0000000f00000000 - -/* ==================================================================== */ -/* Register "SH_JNR_DIMM_CFG" */ -/* AC Mem Config Registers */ -/* ==================================================================== */ - -#define SH_JNR_DIMM_CFG 0x0000000100010010 -#define SH_JNR_DIMM_CFG_MASK 0x0000000f7f7f7f7f -#define SH_JNR_DIMM_CFG_INIT 0x000000026f4f2f0f - -/* SH_JNR_DIMM_CFG_DIMM0_SIZE */ -/* Description: DIMM 0 DRAM size */ -#define SH_JNR_DIMM_CFG_DIMM0_SIZE_SHFT 0 -#define SH_JNR_DIMM_CFG_DIMM0_SIZE_MASK 0x0000000000000007 - -/* SH_JNR_DIMM_CFG_DIMM0_2BK */ -/* Description: DIMM 0 has two physical banks */ -#define SH_JNR_DIMM_CFG_DIMM0_2BK_SHFT 3 -#define SH_JNR_DIMM_CFG_DIMM0_2BK_MASK 0x0000000000000008 - -/* SH_JNR_DIMM_CFG_DIMM0_REV */ -/* Description: DIMM 0 physical banks reversed */ -#define SH_JNR_DIMM_CFG_DIMM0_REV_SHFT 4 -#define SH_JNR_DIMM_CFG_DIMM0_REV_MASK 0x0000000000000010 - -/* SH_JNR_DIMM_CFG_DIMM0_CS */ -/* Description: DIMM 0 chip select, addr[35:34] match */ -#define SH_JNR_DIMM_CFG_DIMM0_CS_SHFT 5 -#define SH_JNR_DIMM_CFG_DIMM0_CS_MASK 0x0000000000000060 - -/* SH_JNR_DIMM_CFG_DIMM1_SIZE */ -/* Description: DIMM 1 DRAM size */ -#define SH_JNR_DIMM_CFG_DIMM1_SIZE_SHFT 8 -#define SH_JNR_DIMM_CFG_DIMM1_SIZE_MASK 0x0000000000000700 - -/* SH_JNR_DIMM_CFG_DIMM1_2BK */ -/* Description: DIMM 1 has two physical banks */ -#define SH_JNR_DIMM_CFG_DIMM1_2BK_SHFT 11 -#define SH_JNR_DIMM_CFG_DIMM1_2BK_MASK 0x0000000000000800 - -/* SH_JNR_DIMM_CFG_DIMM1_REV */ -/* Description: DIMM 1 physical banks reversed */ -#define SH_JNR_DIMM_CFG_DIMM1_REV_SHFT 12 -#define SH_JNR_DIMM_CFG_DIMM1_REV_MASK 0x0000000000001000 - -/* SH_JNR_DIMM_CFG_DIMM1_CS */ -/* Description: DIMM 1 chip select, addr[35:34] match */ -#define SH_JNR_DIMM_CFG_DIMM1_CS_SHFT 13 -#define SH_JNR_DIMM_CFG_DIMM1_CS_MASK 0x0000000000006000 - -/* SH_JNR_DIMM_CFG_DIMM2_SIZE */ -/* Description: DIMM 2 DRAM size */ -#define SH_JNR_DIMM_CFG_DIMM2_SIZE_SHFT 16 -#define SH_JNR_DIMM_CFG_DIMM2_SIZE_MASK 0x0000000000070000 - -/* SH_JNR_DIMM_CFG_DIMM2_2BK */ -/* Description: DIMM 2 has two physical banks */ -#define SH_JNR_DIMM_CFG_DIMM2_2BK_SHFT 19 -#define SH_JNR_DIMM_CFG_DIMM2_2BK_MASK 0x0000000000080000 - -/* SH_JNR_DIMM_CFG_DIMM2_REV */ -/* Description: DIMM 2 physical banks reversed */ -#define SH_JNR_DIMM_CFG_DIMM2_REV_SHFT 20 -#define SH_JNR_DIMM_CFG_DIMM2_REV_MASK 0x0000000000100000 - -/* SH_JNR_DIMM_CFG_DIMM2_CS */ -/* Description: DIMM 2 chip select, addr[35:34] match */ -#define SH_JNR_DIMM_CFG_DIMM2_CS_SHFT 21 -#define SH_JNR_DIMM_CFG_DIMM2_CS_MASK 0x0000000000600000 - -/* SH_JNR_DIMM_CFG_DIMM3_SIZE */ -/* Description: DIMM 3 DRAM size */ -#define SH_JNR_DIMM_CFG_DIMM3_SIZE_SHFT 24 -#define SH_JNR_DIMM_CFG_DIMM3_SIZE_MASK 0x0000000007000000 - -/* SH_JNR_DIMM_CFG_DIMM3_2BK */ -/* Description: DIMM 3 has two physical banks */ -#define SH_JNR_DIMM_CFG_DIMM3_2BK_SHFT 27 -#define SH_JNR_DIMM_CFG_DIMM3_2BK_MASK 0x0000000008000000 - -/* SH_JNR_DIMM_CFG_DIMM3_REV */ -/* Description: DIMM 3 physical banks reversed */ -#define SH_JNR_DIMM_CFG_DIMM3_REV_SHFT 28 -#define SH_JNR_DIMM_CFG_DIMM3_REV_MASK 0x0000000010000000 - -/* SH_JNR_DIMM_CFG_DIMM3_CS */ -/* Description: DIMM 3 chip select, addr[35:34] match */ -#define SH_JNR_DIMM_CFG_DIMM3_CS_SHFT 29 -#define SH_JNR_DIMM_CFG_DIMM3_CS_MASK 0x0000000060000000 - -/* SH_JNR_DIMM_CFG_FREQ */ -/* Description: DIMM frequency select */ -#define SH_JNR_DIMM_CFG_FREQ_SHFT 32 -#define SH_JNR_DIMM_CFG_FREQ_MASK 0x0000000f00000000 - -/* ==================================================================== */ -/* Register "SH_X_PHASE_CFG" */ -/* AC Phase Config Registers */ -/* ==================================================================== */ - -#define SH_X_PHASE_CFG 0x0000000100010018 -#define SH_X_PHASE_CFG_MASK 0x7fffffffffffffff -#define SH_X_PHASE_CFG_INIT 0x0000000000000000 - -/* SH_X_PHASE_CFG_LD_A */ -/* Description: Address, control load core clock A latch */ -#define SH_X_PHASE_CFG_LD_A_SHFT 0 -#define SH_X_PHASE_CFG_LD_A_MASK 0x000000000000001f - -/* SH_X_PHASE_CFG_LD_B */ -/* Description: Address, control load core clock B latch */ -#define SH_X_PHASE_CFG_LD_B_SHFT 5 -#define SH_X_PHASE_CFG_LD_B_MASK 0x00000000000003e0 - -/* SH_X_PHASE_CFG_DQ_LD_A */ -/* Description: DATA MCI load core clock A latch */ -#define SH_X_PHASE_CFG_DQ_LD_A_SHFT 10 -#define SH_X_PHASE_CFG_DQ_LD_A_MASK 0x0000000000007c00 - -/* SH_X_PHASE_CFG_DQ_LD_B */ -/* Description: DATA MCI load core clock B latch */ -#define SH_X_PHASE_CFG_DQ_LD_B_SHFT 15 -#define SH_X_PHASE_CFG_DQ_LD_B_MASK 0x00000000000f8000 - -/* SH_X_PHASE_CFG_HOLD */ -/* Description: Hold request on core clock phase */ -#define SH_X_PHASE_CFG_HOLD_SHFT 20 -#define SH_X_PHASE_CFG_HOLD_MASK 0x0000000001f00000 - -/* SH_X_PHASE_CFG_HOLD_REQ */ -/* Description: Hold next request on core clock phase */ -#define SH_X_PHASE_CFG_HOLD_REQ_SHFT 25 -#define SH_X_PHASE_CFG_HOLD_REQ_MASK 0x000000003e000000 - -/* SH_X_PHASE_CFG_ADD_CP */ -/* Description: add delay clock period to dqct delay chain on phase */ -#define SH_X_PHASE_CFG_ADD_CP_SHFT 30 -#define SH_X_PHASE_CFG_ADD_CP_MASK 0x00000007c0000000 - -/* SH_X_PHASE_CFG_BUBBLE_EN */ -/* Description: bubble, idle core clock to wait for memory clock */ -#define SH_X_PHASE_CFG_BUBBLE_EN_SHFT 35 -#define SH_X_PHASE_CFG_BUBBLE_EN_MASK 0x000000f800000000 - -/* SH_X_PHASE_CFG_PHA_BUBBLE */ -/* Description: MMR phaseA bubble value */ -#define SH_X_PHASE_CFG_PHA_BUBBLE_SHFT 40 -#define SH_X_PHASE_CFG_PHA_BUBBLE_MASK 0x0000070000000000 - -/* SH_X_PHASE_CFG_PHB_BUBBLE */ -/* Description: MMR phaseB bubble value */ -#define SH_X_PHASE_CFG_PHB_BUBBLE_SHFT 43 -#define SH_X_PHASE_CFG_PHB_BUBBLE_MASK 0x0000380000000000 - -/* SH_X_PHASE_CFG_PHC_BUBBLE */ -/* Description: MMR phaseC bubble value */ -#define SH_X_PHASE_CFG_PHC_BUBBLE_SHFT 46 -#define SH_X_PHASE_CFG_PHC_BUBBLE_MASK 0x0001c00000000000 - -/* SH_X_PHASE_CFG_PHD_BUBBLE */ -/* Description: MMR phaseD bubble value */ -#define SH_X_PHASE_CFG_PHD_BUBBLE_SHFT 49 -#define SH_X_PHASE_CFG_PHD_BUBBLE_MASK 0x000e000000000000 - -/* SH_X_PHASE_CFG_PHE_BUBBLE */ -/* Description: MMR phaseE bubble value */ -#define SH_X_PHASE_CFG_PHE_BUBBLE_SHFT 52 -#define SH_X_PHASE_CFG_PHE_BUBBLE_MASK 0x0070000000000000 - -/* SH_X_PHASE_CFG_SEL_A */ -/* Description: address,control select A memory clock latch */ -#define SH_X_PHASE_CFG_SEL_A_SHFT 55 -#define SH_X_PHASE_CFG_SEL_A_MASK 0x0780000000000000 - -/* SH_X_PHASE_CFG_DQ_SEL_A */ -/* Description: DATA MCI select A memory clock latch */ -#define SH_X_PHASE_CFG_DQ_SEL_A_SHFT 59 -#define SH_X_PHASE_CFG_DQ_SEL_A_MASK 0x7800000000000000 - -/* ==================================================================== */ -/* Register "SH_X_CFG" */ -/* AC Config Registers */ -/* ==================================================================== */ - -#define SH_X_CFG 0x0000000100010020 -#define SH_X_CFG_MASK 0xffffffffffffffff -#define SH_X_CFG_INIT 0x108443103322100c - -/* SH_X_CFG_MODE_SERIAL */ -/* Description: Arbque arbitration in serial mode */ -#define SH_X_CFG_MODE_SERIAL_SHFT 0 -#define SH_X_CFG_MODE_SERIAL_MASK 0x0000000000000001 - -/* SH_X_CFG_DIRC_RANDOM_REPLACEMENT */ -/* Description: Directory cache random replacement */ -#define SH_X_CFG_DIRC_RANDOM_REPLACEMENT_SHFT 1 -#define SH_X_CFG_DIRC_RANDOM_REPLACEMENT_MASK 0x0000000000000002 - -/* SH_X_CFG_DIR_COUNTER_INIT */ -/* Description: Dir counter initial value */ -#define SH_X_CFG_DIR_COUNTER_INIT_SHFT 2 -#define SH_X_CFG_DIR_COUNTER_INIT_MASK 0x00000000000000fc - -/* SH_X_CFG_TA_DLYS */ -/* Description: Turn around delays */ -#define SH_X_CFG_TA_DLYS_SHFT 8 -#define SH_X_CFG_TA_DLYS_MASK 0x000000ffffffff00 - -/* SH_X_CFG_DA_BB_CLR */ -/* Description: Bank busy CPs for a data read request */ -#define SH_X_CFG_DA_BB_CLR_SHFT 40 -#define SH_X_CFG_DA_BB_CLR_MASK 0x00000f0000000000 - -/* SH_X_CFG_DC_BB_CLR */ -/* Description: Bank busy CPs for a directory cache read request */ -#define SH_X_CFG_DC_BB_CLR_SHFT 44 -#define SH_X_CFG_DC_BB_CLR_MASK 0x0000f00000000000 - -/* SH_X_CFG_WT_BB_CLR */ -/* Description: Bank busy CPs for all write request */ -#define SH_X_CFG_WT_BB_CLR_SHFT 48 -#define SH_X_CFG_WT_BB_CLR_MASK 0x000f000000000000 - -/* SH_X_CFG_SSO_WT_EN */ -/* Description: Simultaneous switching enabled on output data pins */ -#define SH_X_CFG_SSO_WT_EN_SHFT 52 -#define SH_X_CFG_SSO_WT_EN_MASK 0x0010000000000000 - -/* SH_X_CFG_TRCD2_EN */ -/* Description: Trcd, ras to cas delay of 2 CPs enabled */ -#define SH_X_CFG_TRCD2_EN_SHFT 53 -#define SH_X_CFG_TRCD2_EN_MASK 0x0020000000000000 - -/* SH_X_CFG_TRCD4_EN */ -/* Description: Trcd, ras to case delay of 4 CPs enabled */ -#define SH_X_CFG_TRCD4_EN_SHFT 54 -#define SH_X_CFG_TRCD4_EN_MASK 0x0040000000000000 - -/* SH_X_CFG_REQ_CNTR_DIS */ -/* Description: Request delay counter disabled */ -#define SH_X_CFG_REQ_CNTR_DIS_SHFT 55 -#define SH_X_CFG_REQ_CNTR_DIS_MASK 0x0080000000000000 - -/* SH_X_CFG_REQ_CNTR_VAL */ -/* Description: Request counter delay value in CPs */ -#define SH_X_CFG_REQ_CNTR_VAL_SHFT 56 -#define SH_X_CFG_REQ_CNTR_VAL_MASK 0x3f00000000000000 - -/* SH_X_CFG_INV_CAS_ADDR */ -/* Description: Invert cas address bits 3 to 7 */ -#define SH_X_CFG_INV_CAS_ADDR_SHFT 62 -#define SH_X_CFG_INV_CAS_ADDR_MASK 0x4000000000000000 - -/* SH_X_CFG_CLR_DIR_CACHE */ -/* Description: Clear directory cache tags */ -#define SH_X_CFG_CLR_DIR_CACHE_SHFT 63 -#define SH_X_CFG_CLR_DIR_CACHE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_X_DQCT_CFG" */ -/* AC Config Registers */ -/* ==================================================================== */ - -#define SH_X_DQCT_CFG 0x0000000100010028 -#define SH_X_DQCT_CFG_MASK 0x0000000000ffffff -#define SH_X_DQCT_CFG_INIT 0x0000000000585418 - -/* SH_X_DQCT_CFG_RD_SEL */ -/* Description: Read data select */ -#define SH_X_DQCT_CFG_RD_SEL_SHFT 0 -#define SH_X_DQCT_CFG_RD_SEL_MASK 0x000000000000000f - -/* SH_X_DQCT_CFG_WT_SEL */ -/* Description: Write data select */ -#define SH_X_DQCT_CFG_WT_SEL_SHFT 4 -#define SH_X_DQCT_CFG_WT_SEL_MASK 0x00000000000000f0 - -/* SH_X_DQCT_CFG_DTA_RD_SEL */ -/* Description: Data ready read select */ -#define SH_X_DQCT_CFG_DTA_RD_SEL_SHFT 8 -#define SH_X_DQCT_CFG_DTA_RD_SEL_MASK 0x0000000000000f00 - -/* SH_X_DQCT_CFG_DTA_WT_SEL */ -/* Description: Data ready write select */ -#define SH_X_DQCT_CFG_DTA_WT_SEL_SHFT 12 -#define SH_X_DQCT_CFG_DTA_WT_SEL_MASK 0x000000000000f000 - -/* SH_X_DQCT_CFG_DIR_RD_SEL */ -/* Description: Dir ready read select */ -#define SH_X_DQCT_CFG_DIR_RD_SEL_SHFT 16 -#define SH_X_DQCT_CFG_DIR_RD_SEL_MASK 0x00000000000f0000 - -/* SH_X_DQCT_CFG_MDIR_RD_SEL */ -/* Description: Dir ready read select */ -#define SH_X_DQCT_CFG_MDIR_RD_SEL_SHFT 20 -#define SH_X_DQCT_CFG_MDIR_RD_SEL_MASK 0x0000000000f00000 - -/* ==================================================================== */ -/* Register "SH_X_REFRESH_CONTROL" */ -/* Refresh Control Register */ -/* ==================================================================== */ - -#define SH_X_REFRESH_CONTROL 0x0000000100010030 -#define SH_X_REFRESH_CONTROL_MASK 0x000000000fffffff -#define SH_X_REFRESH_CONTROL_INIT 0x00000000009cc300 - -/* SH_X_REFRESH_CONTROL_ENABLE */ -/* Description: Refresh enable */ -#define SH_X_REFRESH_CONTROL_ENABLE_SHFT 0 -#define SH_X_REFRESH_CONTROL_ENABLE_MASK 0x00000000000000ff - -/* SH_X_REFRESH_CONTROL_INTERVAL */ -/* Description: Refresh interval in core CPs */ -#define SH_X_REFRESH_CONTROL_INTERVAL_SHFT 8 -#define SH_X_REFRESH_CONTROL_INTERVAL_MASK 0x000000000001ff00 - -/* SH_X_REFRESH_CONTROL_HOLD */ -/* Description: Refresh hold */ -#define SH_X_REFRESH_CONTROL_HOLD_SHFT 17 -#define SH_X_REFRESH_CONTROL_HOLD_MASK 0x00000000007e0000 - -/* SH_X_REFRESH_CONTROL_INTERLEAVE */ -/* Description: Refresh interleave */ -#define SH_X_REFRESH_CONTROL_INTERLEAVE_SHFT 23 -#define SH_X_REFRESH_CONTROL_INTERLEAVE_MASK 0x0000000000800000 - -/* SH_X_REFRESH_CONTROL_HALF_RATE */ -/* Description: Refresh half rate */ -#define SH_X_REFRESH_CONTROL_HALF_RATE_SHFT 24 -#define SH_X_REFRESH_CONTROL_HALF_RATE_MASK 0x000000000f000000 - -/* ==================================================================== */ -/* Register "SH_Y_PHASE_CFG" */ -/* AC Phase Config Registers */ -/* ==================================================================== */ - -#define SH_Y_PHASE_CFG 0x0000000100010038 -#define SH_Y_PHASE_CFG_MASK 0x7fffffffffffffff -#define SH_Y_PHASE_CFG_INIT 0x0000000000000000 - -/* SH_Y_PHASE_CFG_LD_A */ -/* Description: Address, control load core clock A latch */ -#define SH_Y_PHASE_CFG_LD_A_SHFT 0 -#define SH_Y_PHASE_CFG_LD_A_MASK 0x000000000000001f - -/* SH_Y_PHASE_CFG_LD_B */ -/* Description: Address, control load core clock B latch */ -#define SH_Y_PHASE_CFG_LD_B_SHFT 5 -#define SH_Y_PHASE_CFG_LD_B_MASK 0x00000000000003e0 - -/* SH_Y_PHASE_CFG_DQ_LD_A */ -/* Description: DATA MCI load core clock A latch */ -#define SH_Y_PHASE_CFG_DQ_LD_A_SHFT 10 -#define SH_Y_PHASE_CFG_DQ_LD_A_MASK 0x0000000000007c00 - -/* SH_Y_PHASE_CFG_DQ_LD_B */ -/* Description: DATA MCI load core clock B latch */ -#define SH_Y_PHASE_CFG_DQ_LD_B_SHFT 15 -#define SH_Y_PHASE_CFG_DQ_LD_B_MASK 0x00000000000f8000 - -/* SH_Y_PHASE_CFG_HOLD */ -/* Description: Hold request on core clock phase */ -#define SH_Y_PHASE_CFG_HOLD_SHFT 20 -#define SH_Y_PHASE_CFG_HOLD_MASK 0x0000000001f00000 - -/* SH_Y_PHASE_CFG_HOLD_REQ */ -/* Description: Hold next request on core clock phase */ -#define SH_Y_PHASE_CFG_HOLD_REQ_SHFT 25 -#define SH_Y_PHASE_CFG_HOLD_REQ_MASK 0x000000003e000000 - -/* SH_Y_PHASE_CFG_ADD_CP */ -/* Description: add delay clock period to dqct delay chain on phase */ -#define SH_Y_PHASE_CFG_ADD_CP_SHFT 30 -#define SH_Y_PHASE_CFG_ADD_CP_MASK 0x00000007c0000000 - -/* SH_Y_PHASE_CFG_BUBBLE_EN */ -/* Description: bubble, idle core clock to wait for memory clock */ -#define SH_Y_PHASE_CFG_BUBBLE_EN_SHFT 35 -#define SH_Y_PHASE_CFG_BUBBLE_EN_MASK 0x000000f800000000 - -/* SH_Y_PHASE_CFG_PHA_BUBBLE */ -/* Description: MMR phaseA bubble value */ -#define SH_Y_PHASE_CFG_PHA_BUBBLE_SHFT 40 -#define SH_Y_PHASE_CFG_PHA_BUBBLE_MASK 0x0000070000000000 - -/* SH_Y_PHASE_CFG_PHB_BUBBLE */ -/* Description: MMR phaseB bubble value */ -#define SH_Y_PHASE_CFG_PHB_BUBBLE_SHFT 43 -#define SH_Y_PHASE_CFG_PHB_BUBBLE_MASK 0x0000380000000000 - -/* SH_Y_PHASE_CFG_PHC_BUBBLE */ -/* Description: MMR phaseC bubble value */ -#define SH_Y_PHASE_CFG_PHC_BUBBLE_SHFT 46 -#define SH_Y_PHASE_CFG_PHC_BUBBLE_MASK 0x0001c00000000000 - -/* SH_Y_PHASE_CFG_PHD_BUBBLE */ -/* Description: MMR phaseD bubble value */ -#define SH_Y_PHASE_CFG_PHD_BUBBLE_SHFT 49 -#define SH_Y_PHASE_CFG_PHD_BUBBLE_MASK 0x000e000000000000 - -/* SH_Y_PHASE_CFG_PHE_BUBBLE */ -/* Description: MMR phaseE bubble value */ -#define SH_Y_PHASE_CFG_PHE_BUBBLE_SHFT 52 -#define SH_Y_PHASE_CFG_PHE_BUBBLE_MASK 0x0070000000000000 - -/* SH_Y_PHASE_CFG_SEL_A */ -/* Description: address,control select A memory clock latch */ -#define SH_Y_PHASE_CFG_SEL_A_SHFT 55 -#define SH_Y_PHASE_CFG_SEL_A_MASK 0x0780000000000000 - -/* SH_Y_PHASE_CFG_DQ_SEL_A */ -/* Description: DATA MCI select A memory clock latch */ -#define SH_Y_PHASE_CFG_DQ_SEL_A_SHFT 59 -#define SH_Y_PHASE_CFG_DQ_SEL_A_MASK 0x7800000000000000 - -/* ==================================================================== */ -/* Register "SH_Y_CFG" */ -/* AC Config Registers */ -/* ==================================================================== */ - -#define SH_Y_CFG 0x0000000100010040 -#define SH_Y_CFG_MASK 0xffffffffffffffff -#define SH_Y_CFG_INIT 0x108443103322100c - -/* SH_Y_CFG_MODE_SERIAL */ -/* Description: Arbque arbitration in serial mode */ -#define SH_Y_CFG_MODE_SERIAL_SHFT 0 -#define SH_Y_CFG_MODE_SERIAL_MASK 0x0000000000000001 - -/* SH_Y_CFG_DIRC_RANDOM_REPLACEMENT */ -/* Description: Directory cache random replacement */ -#define SH_Y_CFG_DIRC_RANDOM_REPLACEMENT_SHFT 1 -#define SH_Y_CFG_DIRC_RANDOM_REPLACEMENT_MASK 0x0000000000000002 - -/* SH_Y_CFG_DIR_COUNTER_INIT */ -/* Description: Dir counter initial value */ -#define SH_Y_CFG_DIR_COUNTER_INIT_SHFT 2 -#define SH_Y_CFG_DIR_COUNTER_INIT_MASK 0x00000000000000fc - -/* SH_Y_CFG_TA_DLYS */ -/* Description: Turn around delays */ -#define SH_Y_CFG_TA_DLYS_SHFT 8 -#define SH_Y_CFG_TA_DLYS_MASK 0x000000ffffffff00 - -/* SH_Y_CFG_DA_BB_CLR */ -/* Description: Bank busy CPs for a data read request */ -#define SH_Y_CFG_DA_BB_CLR_SHFT 40 -#define SH_Y_CFG_DA_BB_CLR_MASK 0x00000f0000000000 - -/* SH_Y_CFG_DC_BB_CLR */ -/* Description: Bank busy CPs for a directory cache read request */ -#define SH_Y_CFG_DC_BB_CLR_SHFT 44 -#define SH_Y_CFG_DC_BB_CLR_MASK 0x0000f00000000000 - -/* SH_Y_CFG_WT_BB_CLR */ -/* Description: Bank busy CPs for all write request */ -#define SH_Y_CFG_WT_BB_CLR_SHFT 48 -#define SH_Y_CFG_WT_BB_CLR_MASK 0x000f000000000000 - -/* SH_Y_CFG_SSO_WT_EN */ -/* Description: Simultaneous switching enabled on output data pins */ -#define SH_Y_CFG_SSO_WT_EN_SHFT 52 -#define SH_Y_CFG_SSO_WT_EN_MASK 0x0010000000000000 - -/* SH_Y_CFG_TRCD2_EN */ -/* Description: Trcd, ras to cas delay of 2 CPs enabled */ -#define SH_Y_CFG_TRCD2_EN_SHFT 53 -#define SH_Y_CFG_TRCD2_EN_MASK 0x0020000000000000 - -/* SH_Y_CFG_TRCD4_EN */ -/* Description: Trcd, ras to case delay of 4 CPs enabled */ -#define SH_Y_CFG_TRCD4_EN_SHFT 54 -#define SH_Y_CFG_TRCD4_EN_MASK 0x0040000000000000 - -/* SH_Y_CFG_REQ_CNTR_DIS */ -/* Description: Request delay counter disabled */ -#define SH_Y_CFG_REQ_CNTR_DIS_SHFT 55 -#define SH_Y_CFG_REQ_CNTR_DIS_MASK 0x0080000000000000 - -/* SH_Y_CFG_REQ_CNTR_VAL */ -/* Description: Request counter delay value in CPs */ -#define SH_Y_CFG_REQ_CNTR_VAL_SHFT 56 -#define SH_Y_CFG_REQ_CNTR_VAL_MASK 0x3f00000000000000 - -/* SH_Y_CFG_INV_CAS_ADDR */ -/* Description: Invert cas address bits 3 to 7 */ -#define SH_Y_CFG_INV_CAS_ADDR_SHFT 62 -#define SH_Y_CFG_INV_CAS_ADDR_MASK 0x4000000000000000 - -/* SH_Y_CFG_CLR_DIR_CACHE */ -/* Description: Clear directory cache tags */ -#define SH_Y_CFG_CLR_DIR_CACHE_SHFT 63 -#define SH_Y_CFG_CLR_DIR_CACHE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_Y_DQCT_CFG" */ -/* AC Config Registers */ -/* ==================================================================== */ - -#define SH_Y_DQCT_CFG 0x0000000100010048 -#define SH_Y_DQCT_CFG_MASK 0x0000000000ffffff -#define SH_Y_DQCT_CFG_INIT 0x0000000000585418 - -/* SH_Y_DQCT_CFG_RD_SEL */ -/* Description: Read data select */ -#define SH_Y_DQCT_CFG_RD_SEL_SHFT 0 -#define SH_Y_DQCT_CFG_RD_SEL_MASK 0x000000000000000f - -/* SH_Y_DQCT_CFG_WT_SEL */ -/* Description: Write data select */ -#define SH_Y_DQCT_CFG_WT_SEL_SHFT 4 -#define SH_Y_DQCT_CFG_WT_SEL_MASK 0x00000000000000f0 - -/* SH_Y_DQCT_CFG_DTA_RD_SEL */ -/* Description: Data ready read select */ -#define SH_Y_DQCT_CFG_DTA_RD_SEL_SHFT 8 -#define SH_Y_DQCT_CFG_DTA_RD_SEL_MASK 0x0000000000000f00 - -/* SH_Y_DQCT_CFG_DTA_WT_SEL */ -/* Description: Data ready write select */ -#define SH_Y_DQCT_CFG_DTA_WT_SEL_SHFT 12 -#define SH_Y_DQCT_CFG_DTA_WT_SEL_MASK 0x000000000000f000 - -/* SH_Y_DQCT_CFG_DIR_RD_SEL */ -/* Description: Dir ready read select */ -#define SH_Y_DQCT_CFG_DIR_RD_SEL_SHFT 16 -#define SH_Y_DQCT_CFG_DIR_RD_SEL_MASK 0x00000000000f0000 - -/* SH_Y_DQCT_CFG_MDIR_RD_SEL */ -/* Description: Dir ready read select */ -#define SH_Y_DQCT_CFG_MDIR_RD_SEL_SHFT 20 -#define SH_Y_DQCT_CFG_MDIR_RD_SEL_MASK 0x0000000000f00000 - -/* ==================================================================== */ -/* Register "SH_Y_REFRESH_CONTROL" */ -/* Refresh Control Register */ -/* ==================================================================== */ - -#define SH_Y_REFRESH_CONTROL 0x0000000100010050 -#define SH_Y_REFRESH_CONTROL_MASK 0x000000000fffffff -#define SH_Y_REFRESH_CONTROL_INIT 0x00000000009cc300 - -/* SH_Y_REFRESH_CONTROL_ENABLE */ -/* Description: Refresh enable */ -#define SH_Y_REFRESH_CONTROL_ENABLE_SHFT 0 -#define SH_Y_REFRESH_CONTROL_ENABLE_MASK 0x00000000000000ff - -/* SH_Y_REFRESH_CONTROL_INTERVAL */ -/* Description: Refresh interval in core CPs */ -#define SH_Y_REFRESH_CONTROL_INTERVAL_SHFT 8 -#define SH_Y_REFRESH_CONTROL_INTERVAL_MASK 0x000000000001ff00 - -/* SH_Y_REFRESH_CONTROL_HOLD */ -/* Description: Refresh hold */ -#define SH_Y_REFRESH_CONTROL_HOLD_SHFT 17 -#define SH_Y_REFRESH_CONTROL_HOLD_MASK 0x00000000007e0000 - -/* SH_Y_REFRESH_CONTROL_INTERLEAVE */ -/* Description: Refresh interleave */ -#define SH_Y_REFRESH_CONTROL_INTERLEAVE_SHFT 23 -#define SH_Y_REFRESH_CONTROL_INTERLEAVE_MASK 0x0000000000800000 - -/* SH_Y_REFRESH_CONTROL_HALF_RATE */ -/* Description: Refresh half rate */ -#define SH_Y_REFRESH_CONTROL_HALF_RATE_SHFT 24 -#define SH_Y_REFRESH_CONTROL_HALF_RATE_MASK 0x000000000f000000 - -/* ==================================================================== */ -/* Register "SH_MEM_RED_BLACK" */ -/* MD fairness watchdog timers */ -/* ==================================================================== */ - -#define SH_MEM_RED_BLACK 0x0000000100010058 -#define SH_MEM_RED_BLACK_MASK 0x000fffffffffffff -#define SH_MEM_RED_BLACK_INIT 0x0000000040000400 - -/* SH_MEM_RED_BLACK_TIME */ -/* Description: Clocks to tag references with a given color */ -#define SH_MEM_RED_BLACK_TIME_SHFT 0 -#define SH_MEM_RED_BLACK_TIME_MASK 0x000000000000ffff - -/* SH_MEM_RED_BLACK_ERR_TIME */ -/* Description: Max clocks to wait after red/black change for old c */ -/* olor to clear. */ -#define SH_MEM_RED_BLACK_ERR_TIME_SHFT 16 -#define SH_MEM_RED_BLACK_ERR_TIME_MASK 0x000fffffffff0000 - -/* ==================================================================== */ -/* Register "SH_MISC_MEM_CFG" */ -/* ==================================================================== */ - -#define SH_MISC_MEM_CFG 0x0000000100010060 -#define SH_MISC_MEM_CFG_MASK 0x0013f1f1fff3f3ff -#define SH_MISC_MEM_CFG_INIT 0x0000000000010107 - -/* SH_MISC_MEM_CFG_EXPRESS_HEADER_ENABLE */ -/* Description: enables the use of express headers from md to pi */ -#define SH_MISC_MEM_CFG_EXPRESS_HEADER_ENABLE_SHFT 0 -#define SH_MISC_MEM_CFG_EXPRESS_HEADER_ENABLE_MASK 0x0000000000000001 - -/* SH_MISC_MEM_CFG_SPEC_HEADER_ENABLE */ -/* Description: enables the use of speculative headers from md to p */ -#define SH_MISC_MEM_CFG_SPEC_HEADER_ENABLE_SHFT 1 -#define SH_MISC_MEM_CFG_SPEC_HEADER_ENABLE_MASK 0x0000000000000002 - -/* SH_MISC_MEM_CFG_JNR_BYPASS_ENABLE */ -/* Description: enables bypass path for requests going through ac */ -#define SH_MISC_MEM_CFG_JNR_BYPASS_ENABLE_SHFT 2 -#define SH_MISC_MEM_CFG_JNR_BYPASS_ENABLE_MASK 0x0000000000000004 - -/* SH_MISC_MEM_CFG_XN_RD_SAME_AS_PI */ -/* Description: disables a one clock delay of XN read data */ -#define SH_MISC_MEM_CFG_XN_RD_SAME_AS_PI_SHFT 3 -#define SH_MISC_MEM_CFG_XN_RD_SAME_AS_PI_MASK 0x0000000000000008 - -/* SH_MISC_MEM_CFG_LOW_WRITE_BUFFER_THRESHOLD */ -/* Description: point at which data writes get higher priority */ -#define SH_MISC_MEM_CFG_LOW_WRITE_BUFFER_THRESHOLD_SHFT 4 -#define SH_MISC_MEM_CFG_LOW_WRITE_BUFFER_THRESHOLD_MASK 0x00000000000003f0 - -/* SH_MISC_MEM_CFG_LOW_VICTIM_BUFFER_THRESHOLD */ -/* Description: point at which dir cache writes get higher priority */ -#define SH_MISC_MEM_CFG_LOW_VICTIM_BUFFER_THRESHOLD_SHFT 12 -#define SH_MISC_MEM_CFG_LOW_VICTIM_BUFFER_THRESHOLD_MASK 0x000000000003f000 - -/* SH_MISC_MEM_CFG_THROTTLE_CNT */ -/* Description: number of clocks between accepting references */ -#define SH_MISC_MEM_CFG_THROTTLE_CNT_SHFT 20 -#define SH_MISC_MEM_CFG_THROTTLE_CNT_MASK 0x000000000ff00000 - -/* SH_MISC_MEM_CFG_DISABLED_READ_TNUMS */ -/* Description: number of read tnums to take out of circulation */ -#define SH_MISC_MEM_CFG_DISABLED_READ_TNUMS_SHFT 28 -#define SH_MISC_MEM_CFG_DISABLED_READ_TNUMS_MASK 0x00000001f0000000 - -/* SH_MISC_MEM_CFG_DISABLED_WRITE_TNUMS */ -/* Description: number of write tnums to take out of circulation */ -#define SH_MISC_MEM_CFG_DISABLED_WRITE_TNUMS_SHFT 36 -#define SH_MISC_MEM_CFG_DISABLED_WRITE_TNUMS_MASK 0x000001f000000000 - -/* SH_MISC_MEM_CFG_DISABLED_VICTIMS */ -/* Description: number of dir cache victim buffers to take out of c */ -/* irculation in each quadrant of the MD */ -#define SH_MISC_MEM_CFG_DISABLED_VICTIMS_SHFT 44 -#define SH_MISC_MEM_CFG_DISABLED_VICTIMS_MASK 0x0003f00000000000 - -/* SH_MISC_MEM_CFG_ALTERNATE_XN_RP_PLANE */ -/* Description: enables plane alternating for replies to XN */ -#define SH_MISC_MEM_CFG_ALTERNATE_XN_RP_PLANE_SHFT 52 -#define SH_MISC_MEM_CFG_ALTERNATE_XN_RP_PLANE_MASK 0x0010000000000000 - -/* ==================================================================== */ -/* Register "SH_PIO_RQ_CRD_CTL" */ -/* pio_rq Credit Circulation Control */ -/* ==================================================================== */ - -#define SH_PIO_RQ_CRD_CTL 0x0000000100010068 -#define SH_PIO_RQ_CRD_CTL_MASK 0x000000000000003f -#define SH_PIO_RQ_CRD_CTL_INIT 0x0000000000000002 - -/* SH_PIO_RQ_CRD_CTL_DEPTH */ -/* Description: Total depth of buffering (in sic packets) */ -#define SH_PIO_RQ_CRD_CTL_DEPTH_SHFT 0 -#define SH_PIO_RQ_CRD_CTL_DEPTH_MASK 0x000000000000003f - -/* ==================================================================== */ -/* Register "SH_PI_MD_RQ_CRD_CTL" */ -/* pi_md_rq Credit Circulation Control */ -/* ==================================================================== */ - -#define SH_PI_MD_RQ_CRD_CTL 0x0000000100010070 -#define SH_PI_MD_RQ_CRD_CTL_MASK 0x000000000000003f -#define SH_PI_MD_RQ_CRD_CTL_INIT 0x0000000000000008 - -/* SH_PI_MD_RQ_CRD_CTL_DEPTH */ -/* Description: Total depth of buffering (in sic packets) */ -#define SH_PI_MD_RQ_CRD_CTL_DEPTH_SHFT 0 -#define SH_PI_MD_RQ_CRD_CTL_DEPTH_MASK 0x000000000000003f - -/* ==================================================================== */ -/* Register "SH_PI_MD_RP_CRD_CTL" */ -/* pi_md_rp Credit Circulation Control */ -/* ==================================================================== */ - -#define SH_PI_MD_RP_CRD_CTL 0x0000000100010078 -#define SH_PI_MD_RP_CRD_CTL_MASK 0x000000000000003f -#define SH_PI_MD_RP_CRD_CTL_INIT 0x0000000000000004 - -/* SH_PI_MD_RP_CRD_CTL_DEPTH */ -/* Description: Total depth of buffering (in sic packets) */ -#define SH_PI_MD_RP_CRD_CTL_DEPTH_SHFT 0 -#define SH_PI_MD_RP_CRD_CTL_DEPTH_MASK 0x000000000000003f - -/* ==================================================================== */ -/* Register "SH_XN_MD_RQ_CRD_CTL" */ -/* xn_md_rq Credit Circulation Control */ -/* ==================================================================== */ - -#define SH_XN_MD_RQ_CRD_CTL 0x0000000100010080 -#define SH_XN_MD_RQ_CRD_CTL_MASK 0x000000000000003f -#define SH_XN_MD_RQ_CRD_CTL_INIT 0x0000000000000008 - -/* SH_XN_MD_RQ_CRD_CTL_DEPTH */ -/* Description: Total depth of buffering (in sic packets) */ -#define SH_XN_MD_RQ_CRD_CTL_DEPTH_SHFT 0 -#define SH_XN_MD_RQ_CRD_CTL_DEPTH_MASK 0x000000000000003f - -/* ==================================================================== */ -/* Register "SH_XN_MD_RP_CRD_CTL" */ -/* xn_md_rp Credit Circulation Control */ -/* ==================================================================== */ - -#define SH_XN_MD_RP_CRD_CTL 0x0000000100010088 -#define SH_XN_MD_RP_CRD_CTL_MASK 0x000000000000003f -#define SH_XN_MD_RP_CRD_CTL_INIT 0x0000000000000004 - -/* SH_XN_MD_RP_CRD_CTL_DEPTH */ -/* Description: Total depth of buffering (in sic packets) */ -#define SH_XN_MD_RP_CRD_CTL_DEPTH_SHFT 0 -#define SH_XN_MD_RP_CRD_CTL_DEPTH_MASK 0x000000000000003f - -/* ==================================================================== */ -/* Register "SH_X_TAG0" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_X_TAG0 0x0000000100020000 -#define SH_X_TAG0_MASK 0x00000000000fffff -#define SH_X_TAG0_INIT 0x0000000000000000 - -/* SH_X_TAG0_TAG */ -/* Description: Valid + Tag Address */ -#define SH_X_TAG0_TAG_SHFT 0 -#define SH_X_TAG0_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_X_TAG1" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_X_TAG1 0x0000000100020008 -#define SH_X_TAG1_MASK 0x00000000000fffff -#define SH_X_TAG1_INIT 0x0000000000000000 - -/* SH_X_TAG1_TAG */ -/* Description: Valid + Tag Address */ -#define SH_X_TAG1_TAG_SHFT 0 -#define SH_X_TAG1_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_X_TAG2" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_X_TAG2 0x0000000100020010 -#define SH_X_TAG2_MASK 0x00000000000fffff -#define SH_X_TAG2_INIT 0x0000000000000000 - -/* SH_X_TAG2_TAG */ -/* Description: Valid + Tag Address */ -#define SH_X_TAG2_TAG_SHFT 0 -#define SH_X_TAG2_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_X_TAG3" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_X_TAG3 0x0000000100020018 -#define SH_X_TAG3_MASK 0x00000000000fffff -#define SH_X_TAG3_INIT 0x0000000000000000 - -/* SH_X_TAG3_TAG */ -/* Description: Valid + Tag Address */ -#define SH_X_TAG3_TAG_SHFT 0 -#define SH_X_TAG3_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_X_TAG4" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_X_TAG4 0x0000000100020020 -#define SH_X_TAG4_MASK 0x00000000000fffff -#define SH_X_TAG4_INIT 0x0000000000000000 - -/* SH_X_TAG4_TAG */ -/* Description: Valid + Tag Address */ -#define SH_X_TAG4_TAG_SHFT 0 -#define SH_X_TAG4_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_X_TAG5" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_X_TAG5 0x0000000100020028 -#define SH_X_TAG5_MASK 0x00000000000fffff -#define SH_X_TAG5_INIT 0x0000000000000000 - -/* SH_X_TAG5_TAG */ -/* Description: Valid + Tag Address */ -#define SH_X_TAG5_TAG_SHFT 0 -#define SH_X_TAG5_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_X_TAG6" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_X_TAG6 0x0000000100020030 -#define SH_X_TAG6_MASK 0x00000000000fffff -#define SH_X_TAG6_INIT 0x0000000000000000 - -/* SH_X_TAG6_TAG */ -/* Description: Valid + Tag Address */ -#define SH_X_TAG6_TAG_SHFT 0 -#define SH_X_TAG6_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_X_TAG7" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_X_TAG7 0x0000000100020038 -#define SH_X_TAG7_MASK 0x00000000000fffff -#define SH_X_TAG7_INIT 0x0000000000000000 - -/* SH_X_TAG7_TAG */ -/* Description: Valid + Tag Address */ -#define SH_X_TAG7_TAG_SHFT 0 -#define SH_X_TAG7_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_Y_TAG0" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_Y_TAG0 0x0000000100020040 -#define SH_Y_TAG0_MASK 0x00000000000fffff -#define SH_Y_TAG0_INIT 0x0000000000000000 - -/* SH_Y_TAG0_TAG */ -/* Description: Valid + Tag Address */ -#define SH_Y_TAG0_TAG_SHFT 0 -#define SH_Y_TAG0_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_Y_TAG1" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_Y_TAG1 0x0000000100020048 -#define SH_Y_TAG1_MASK 0x00000000000fffff -#define SH_Y_TAG1_INIT 0x0000000000000000 - -/* SH_Y_TAG1_TAG */ -/* Description: Valid + Tag Address */ -#define SH_Y_TAG1_TAG_SHFT 0 -#define SH_Y_TAG1_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_Y_TAG2" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_Y_TAG2 0x0000000100020050 -#define SH_Y_TAG2_MASK 0x00000000000fffff -#define SH_Y_TAG2_INIT 0x0000000000000000 - -/* SH_Y_TAG2_TAG */ -/* Description: Valid + Tag Address */ -#define SH_Y_TAG2_TAG_SHFT 0 -#define SH_Y_TAG2_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_Y_TAG3" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_Y_TAG3 0x0000000100020058 -#define SH_Y_TAG3_MASK 0x00000000000fffff -#define SH_Y_TAG3_INIT 0x0000000000000000 - -/* SH_Y_TAG3_TAG */ -/* Description: Valid + Tag Address */ -#define SH_Y_TAG3_TAG_SHFT 0 -#define SH_Y_TAG3_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_Y_TAG4" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_Y_TAG4 0x0000000100020060 -#define SH_Y_TAG4_MASK 0x00000000000fffff -#define SH_Y_TAG4_INIT 0x0000000000000000 - -/* SH_Y_TAG4_TAG */ -/* Description: Valid + Tag Address */ -#define SH_Y_TAG4_TAG_SHFT 0 -#define SH_Y_TAG4_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_Y_TAG5" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_Y_TAG5 0x0000000100020068 -#define SH_Y_TAG5_MASK 0x00000000000fffff -#define SH_Y_TAG5_INIT 0x0000000000000000 - -/* SH_Y_TAG5_TAG */ -/* Description: Valid + Tag Address */ -#define SH_Y_TAG5_TAG_SHFT 0 -#define SH_Y_TAG5_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_Y_TAG6" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_Y_TAG6 0x0000000100020070 -#define SH_Y_TAG6_MASK 0x00000000000fffff -#define SH_Y_TAG6_INIT 0x0000000000000000 - -/* SH_Y_TAG6_TAG */ -/* Description: Valid + Tag Address */ -#define SH_Y_TAG6_TAG_SHFT 0 -#define SH_Y_TAG6_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_Y_TAG7" */ -/* AC tag Registers */ -/* ==================================================================== */ - -#define SH_Y_TAG7 0x0000000100020078 -#define SH_Y_TAG7_MASK 0x00000000000fffff -#define SH_Y_TAG7_INIT 0x0000000000000000 - -/* SH_Y_TAG7_TAG */ -/* Description: Valid + Tag Address */ -#define SH_Y_TAG7_TAG_SHFT 0 -#define SH_Y_TAG7_TAG_MASK 0x00000000000fffff - -/* ==================================================================== */ -/* Register "SH_MMRBIST_BASE" */ -/* mmr/bist base address */ -/* ==================================================================== */ - -#define SH_MMRBIST_BASE 0x0000000100020080 -#define SH_MMRBIST_BASE_MASK 0x0003fffffffffff8 -#define SH_MMRBIST_BASE_INIT 0x0000000000000000 - -/* SH_MMRBIST_BASE_DWORD_ADDR */ -/* Description: bits 49:3 of the memory address */ -#define SH_MMRBIST_BASE_DWORD_ADDR_SHFT 3 -#define SH_MMRBIST_BASE_DWORD_ADDR_MASK 0x0003fffffffffff8 - -/* ==================================================================== */ -/* Register "SH_MMRBIST_CTL" */ -/* Bist base address */ -/* ==================================================================== */ - -#define SH_MMRBIST_CTL 0x0000000100020088 -#define SH_MMRBIST_CTL_MASK 0x0000177f7fffffff -#define SH_MMRBIST_CTL_INIT 0x0000000000000000 - -/* SH_MMRBIST_CTL_BLOCK_LENGTH */ -/* Description: number of dwords in operation */ -#define SH_MMRBIST_CTL_BLOCK_LENGTH_SHFT 0 -#define SH_MMRBIST_CTL_BLOCK_LENGTH_MASK 0x000000007fffffff - -/* SH_MMRBIST_CTL_CMD */ -/* Description: mmr/bist function */ -#define SH_MMRBIST_CTL_CMD_SHFT 32 -#define SH_MMRBIST_CTL_CMD_MASK 0x0000007f00000000 - -/* SH_MMRBIST_CTL_IN_PROGRESS */ -/* Description: writing a 1 starts operation, hardware clears on co */ -/* mpletion */ -#define SH_MMRBIST_CTL_IN_PROGRESS_SHFT 40 -#define SH_MMRBIST_CTL_IN_PROGRESS_MASK 0x0000010000000000 - -/* SH_MMRBIST_CTL_FAIL */ -/* Description: mmr/bist had a data or address error */ -#define SH_MMRBIST_CTL_FAIL_SHFT 41 -#define SH_MMRBIST_CTL_FAIL_MASK 0x0000020000000000 - -/* SH_MMRBIST_CTL_MEM_IDLE */ -/* Description: all memory activity is complete */ -#define SH_MMRBIST_CTL_MEM_IDLE_SHFT 42 -#define SH_MMRBIST_CTL_MEM_IDLE_MASK 0x0000040000000000 - -/* SH_MMRBIST_CTL_RESET_STATE */ -/* Description: writing a 1 resets mmrbist hardware, hardware clear */ -/* s on completion */ -#define SH_MMRBIST_CTL_RESET_STATE_SHFT 44 -#define SH_MMRBIST_CTL_RESET_STATE_MASK 0x0000100000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DBUG_DATA_CFG" */ -/* configuration for md debug data muxes */ -/* ==================================================================== */ - -#define SH_MD_DBUG_DATA_CFG 0x0000000100020100 -#define SH_MD_DBUG_DATA_CFG_MASK 0x7777777777777777 -#define SH_MD_DBUG_DATA_CFG_INIT 0x0000000000000000 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE0_CHIPLET */ -/* Description: selects which md chiplet drives nibble0 */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE0_CHIPLET_SHFT 0 -#define SH_MD_DBUG_DATA_CFG_NIBBLE0_CHIPLET_MASK 0x0000000000000007 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE0_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE0_NIBBLE_SHFT 4 -#define SH_MD_DBUG_DATA_CFG_NIBBLE0_NIBBLE_MASK 0x0000000000000070 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE1_CHIPLET */ -/* Description: selects which md chiplet drives nibble1 */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE1_CHIPLET_SHFT 8 -#define SH_MD_DBUG_DATA_CFG_NIBBLE1_CHIPLET_MASK 0x0000000000000700 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE1_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE1_NIBBLE_SHFT 12 -#define SH_MD_DBUG_DATA_CFG_NIBBLE1_NIBBLE_MASK 0x0000000000007000 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE2_CHIPLET */ -/* Description: selects which md chiplet drives nibble2 */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE2_CHIPLET_SHFT 16 -#define SH_MD_DBUG_DATA_CFG_NIBBLE2_CHIPLET_MASK 0x0000000000070000 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE2_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE2_NIBBLE_SHFT 20 -#define SH_MD_DBUG_DATA_CFG_NIBBLE2_NIBBLE_MASK 0x0000000000700000 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE3_CHIPLET */ -/* Description: selects which md chiplet drives nibble3 */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE3_CHIPLET_SHFT 24 -#define SH_MD_DBUG_DATA_CFG_NIBBLE3_CHIPLET_MASK 0x0000000007000000 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE3_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE3_NIBBLE_SHFT 28 -#define SH_MD_DBUG_DATA_CFG_NIBBLE3_NIBBLE_MASK 0x0000000070000000 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE4_CHIPLET */ -/* Description: selects which md chiplet drives nibble4 */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE4_CHIPLET_SHFT 32 -#define SH_MD_DBUG_DATA_CFG_NIBBLE4_CHIPLET_MASK 0x0000000700000000 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE4_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE4_NIBBLE_SHFT 36 -#define SH_MD_DBUG_DATA_CFG_NIBBLE4_NIBBLE_MASK 0x0000007000000000 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE5_CHIPLET */ -/* Description: selects which md chiplet drives nibble5 */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE5_CHIPLET_SHFT 40 -#define SH_MD_DBUG_DATA_CFG_NIBBLE5_CHIPLET_MASK 0x0000070000000000 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE5_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE5_NIBBLE_SHFT 44 -#define SH_MD_DBUG_DATA_CFG_NIBBLE5_NIBBLE_MASK 0x0000700000000000 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE6_CHIPLET */ -/* Description: selects which md chiplet drives nibble6 */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE6_CHIPLET_SHFT 48 -#define SH_MD_DBUG_DATA_CFG_NIBBLE6_CHIPLET_MASK 0x0007000000000000 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE6_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE6_NIBBLE_SHFT 52 -#define SH_MD_DBUG_DATA_CFG_NIBBLE6_NIBBLE_MASK 0x0070000000000000 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE7_CHIPLET */ -/* Description: selects which md chiplet drives nibble7 */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE7_CHIPLET_SHFT 56 -#define SH_MD_DBUG_DATA_CFG_NIBBLE7_CHIPLET_MASK 0x0700000000000000 - -/* SH_MD_DBUG_DATA_CFG_NIBBLE7_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_DATA_CFG_NIBBLE7_NIBBLE_SHFT 60 -#define SH_MD_DBUG_DATA_CFG_NIBBLE7_NIBBLE_MASK 0x7000000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DBUG_TRIGGER_CFG" */ -/* configuration for md debug triggers */ -/* ==================================================================== */ - -#define SH_MD_DBUG_TRIGGER_CFG 0x0000000100020108 -#define SH_MD_DBUG_TRIGGER_CFG_MASK 0xf777777777777777 -#define SH_MD_DBUG_TRIGGER_CFG_INIT 0x0000000000000000 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_CHIPLET */ -/* Description: selects which md chiplet drives nibble0 */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_CHIPLET_SHFT 0 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_CHIPLET_MASK 0x0000000000000007 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_NIBBLE_SHFT 4 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_NIBBLE_MASK 0x0000000000000070 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_CHIPLET */ -/* Description: selects which md chiplet drives nibble1 */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_CHIPLET_SHFT 8 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_CHIPLET_MASK 0x0000000000000700 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_NIBBLE_SHFT 12 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_NIBBLE_MASK 0x0000000000007000 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_CHIPLET */ -/* Description: selects which md chiplet drives nibble2 */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_CHIPLET_SHFT 16 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_CHIPLET_MASK 0x0000000000070000 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_NIBBLE_SHFT 20 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_NIBBLE_MASK 0x0000000000700000 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_CHIPLET */ -/* Description: selects which md chiplet drives nibble3 */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_CHIPLET_SHFT 24 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_CHIPLET_MASK 0x0000000007000000 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_NIBBLE_SHFT 28 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_NIBBLE_MASK 0x0000000070000000 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_CHIPLET */ -/* Description: selects which md chiplet drives nibble4 */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_CHIPLET_SHFT 32 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_CHIPLET_MASK 0x0000000700000000 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_NIBBLE_SHFT 36 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_NIBBLE_MASK 0x0000007000000000 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_CHIPLET */ -/* Description: selects which md chiplet drives nibble5 */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_CHIPLET_SHFT 40 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_CHIPLET_MASK 0x0000070000000000 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_NIBBLE_SHFT 44 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_NIBBLE_MASK 0x0000700000000000 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_CHIPLET */ -/* Description: selects which md chiplet drives nibble6 */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_CHIPLET_SHFT 48 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_CHIPLET_MASK 0x0007000000000000 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_NIBBLE_SHFT 52 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_NIBBLE_MASK 0x0070000000000000 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_CHIPLET */ -/* Description: selects which md chiplet drives nibble7 */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_CHIPLET_SHFT 56 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_CHIPLET_MASK 0x0700000000000000 - -/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_NIBBLE */ -/* Description: selects which nibble from selected chiplet drives n */ -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_NIBBLE_SHFT 60 -#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_NIBBLE_MASK 0x7000000000000000 - -/* SH_MD_DBUG_TRIGGER_CFG_ENABLE */ -/* Description: enables triggering on pattern match */ -#define SH_MD_DBUG_TRIGGER_CFG_ENABLE_SHFT 63 -#define SH_MD_DBUG_TRIGGER_CFG_ENABLE_MASK 0x8000000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DBUG_COMPARE" */ -/* md debug compare pattern and mask */ -/* ==================================================================== */ - -#define SH_MD_DBUG_COMPARE 0x0000000100020110 -#define SH_MD_DBUG_COMPARE_MASK 0xffffffffffffffff -#define SH_MD_DBUG_COMPARE_INIT 0x0000000000000000 - -/* SH_MD_DBUG_COMPARE_PATTERN */ -/* Description: pattern against which to compare dbug data for trig */ -#define SH_MD_DBUG_COMPARE_PATTERN_SHFT 0 -#define SH_MD_DBUG_COMPARE_PATTERN_MASK 0x00000000ffffffff - -/* SH_MD_DBUG_COMPARE_MASK */ -/* Description: bits to include in compare of dbug data for trigger */ -#define SH_MD_DBUG_COMPARE_MASK_SHFT 32 -#define SH_MD_DBUG_COMPARE_MASK_MASK 0xffffffff00000000 - -/* ==================================================================== */ -/* Register "SH_X_MOD_DBUG_SEL" */ -/* MD acx debug select */ -/* ==================================================================== */ - -#define SH_X_MOD_DBUG_SEL 0x0000000100020118 -#define SH_X_MOD_DBUG_SEL_MASK 0x03ffffffffffffff -#define SH_X_MOD_DBUG_SEL_INIT 0x0000000000000000 - -/* SH_X_MOD_DBUG_SEL_TAG_SEL */ -/* Description: tagmgr select */ -#define SH_X_MOD_DBUG_SEL_TAG_SEL_SHFT 0 -#define SH_X_MOD_DBUG_SEL_TAG_SEL_MASK 0x00000000000000ff - -/* SH_X_MOD_DBUG_SEL_WBQ_SEL */ -/* Description: wbqtg select */ -#define SH_X_MOD_DBUG_SEL_WBQ_SEL_SHFT 8 -#define SH_X_MOD_DBUG_SEL_WBQ_SEL_MASK 0x000000000000ff00 - -/* SH_X_MOD_DBUG_SEL_ARB_SEL */ -/* Description: arbque select */ -#define SH_X_MOD_DBUG_SEL_ARB_SEL_SHFT 16 -#define SH_X_MOD_DBUG_SEL_ARB_SEL_MASK 0x0000000000ff0000 - -/* SH_X_MOD_DBUG_SEL_ATL_SEL */ -/* Description: aintl select */ -#define SH_X_MOD_DBUG_SEL_ATL_SEL_SHFT 24 -#define SH_X_MOD_DBUG_SEL_ATL_SEL_MASK 0x00000007ff000000 - -/* SH_X_MOD_DBUG_SEL_ATR_SEL */ -/* Description: aintr select */ -#define SH_X_MOD_DBUG_SEL_ATR_SEL_SHFT 35 -#define SH_X_MOD_DBUG_SEL_ATR_SEL_MASK 0x00003ff800000000 - -/* SH_X_MOD_DBUG_SEL_DQL_SEL */ -/* Description: dqctr select */ -#define SH_X_MOD_DBUG_SEL_DQL_SEL_SHFT 46 -#define SH_X_MOD_DBUG_SEL_DQL_SEL_MASK 0x000fc00000000000 - -/* SH_X_MOD_DBUG_SEL_DQR_SEL */ -/* Description: dqctl select */ -#define SH_X_MOD_DBUG_SEL_DQR_SEL_SHFT 52 -#define SH_X_MOD_DBUG_SEL_DQR_SEL_MASK 0x03f0000000000000 - -/* ==================================================================== */ -/* Register "SH_X_DBUG_SEL" */ -/* MD acx debug select */ -/* ==================================================================== */ - -#define SH_X_DBUG_SEL 0x0000000100020120 -#define SH_X_DBUG_SEL_MASK 0x0000000000ffffff -#define SH_X_DBUG_SEL_INIT 0x0000000000000000 - -/* SH_X_DBUG_SEL_DBG_SEL */ -/* Description: debug select */ -#define SH_X_DBUG_SEL_DBG_SEL_SHFT 0 -#define SH_X_DBUG_SEL_DBG_SEL_MASK 0x0000000000ffffff - -/* ==================================================================== */ -/* Register "SH_X_LADDR_CMP" */ -/* MD acx address compare */ -/* ==================================================================== */ - -#define SH_X_LADDR_CMP 0x0000000100020128 -#define SH_X_LADDR_CMP_MASK 0x0fffffff0fffffff -#define SH_X_LADDR_CMP_INIT 0x0000000000000000 - -/* SH_X_LADDR_CMP_CMP_VAL */ -/* Description: Compare value */ -#define SH_X_LADDR_CMP_CMP_VAL_SHFT 0 -#define SH_X_LADDR_CMP_CMP_VAL_MASK 0x000000000fffffff - -/* SH_X_LADDR_CMP_MASK_VAL */ -/* Description: Mask value */ -#define SH_X_LADDR_CMP_MASK_VAL_SHFT 32 -#define SH_X_LADDR_CMP_MASK_VAL_MASK 0x0fffffff00000000 - -/* ==================================================================== */ -/* Register "SH_X_RADDR_CMP" */ -/* MD acx address compare */ -/* ==================================================================== */ - -#define SH_X_RADDR_CMP 0x0000000100020130 -#define SH_X_RADDR_CMP_MASK 0x0fffffff0fffffff -#define SH_X_RADDR_CMP_INIT 0x0000000000000000 - -/* SH_X_RADDR_CMP_CMP_VAL */ -/* Description: Compare value */ -#define SH_X_RADDR_CMP_CMP_VAL_SHFT 0 -#define SH_X_RADDR_CMP_CMP_VAL_MASK 0x000000000fffffff - -/* SH_X_RADDR_CMP_MASK_VAL */ -/* Description: Mask value */ -#define SH_X_RADDR_CMP_MASK_VAL_SHFT 32 -#define SH_X_RADDR_CMP_MASK_VAL_MASK 0x0fffffff00000000 - -/* ==================================================================== */ -/* Register "SH_X_TAG_CMP" */ -/* MD acx tagmgr compare */ -/* ==================================================================== */ - -#define SH_X_TAG_CMP 0x0000000100020138 -#define SH_X_TAG_CMP_MASK 0x007fffffffffffff -#define SH_X_TAG_CMP_INIT 0x0000000000000000 - -/* SH_X_TAG_CMP_CMD */ -/* Description: Command compare value */ -#define SH_X_TAG_CMP_CMD_SHFT 0 -#define SH_X_TAG_CMP_CMD_MASK 0x00000000000000ff - -/* SH_X_TAG_CMP_ADDR */ -/* Description: Address compare value */ -#define SH_X_TAG_CMP_ADDR_SHFT 8 -#define SH_X_TAG_CMP_ADDR_MASK 0x000001ffffffff00 - -/* SH_X_TAG_CMP_SRC */ -/* Description: Source compare value */ -#define SH_X_TAG_CMP_SRC_SHFT 41 -#define SH_X_TAG_CMP_SRC_MASK 0x007ffe0000000000 - -/* ==================================================================== */ -/* Register "SH_X_TAG_MASK" */ -/* MD acx tagmgr mask */ -/* ==================================================================== */ - -#define SH_X_TAG_MASK 0x0000000100020140 -#define SH_X_TAG_MASK_MASK 0x007fffffffffffff -#define SH_X_TAG_MASK_INIT 0x0000000000000000 - -/* SH_X_TAG_MASK_CMD */ -/* Description: Command compare value */ -#define SH_X_TAG_MASK_CMD_SHFT 0 -#define SH_X_TAG_MASK_CMD_MASK 0x00000000000000ff - -/* SH_X_TAG_MASK_ADDR */ -/* Description: Address compare value */ -#define SH_X_TAG_MASK_ADDR_SHFT 8 -#define SH_X_TAG_MASK_ADDR_MASK 0x000001ffffffff00 - -/* SH_X_TAG_MASK_SRC */ -/* Description: Source compare value */ -#define SH_X_TAG_MASK_SRC_SHFT 41 -#define SH_X_TAG_MASK_SRC_MASK 0x007ffe0000000000 - -/* ==================================================================== */ -/* Register "SH_Y_MOD_DBUG_SEL" */ -/* MD acy debug select */ -/* ==================================================================== */ - -#define SH_Y_MOD_DBUG_SEL 0x0000000100020148 -#define SH_Y_MOD_DBUG_SEL_MASK 0x03ffffffffffffff -#define SH_Y_MOD_DBUG_SEL_INIT 0x0000000000000000 - -/* SH_Y_MOD_DBUG_SEL_TAG_SEL */ -/* Description: tagmgr select */ -#define SH_Y_MOD_DBUG_SEL_TAG_SEL_SHFT 0 -#define SH_Y_MOD_DBUG_SEL_TAG_SEL_MASK 0x00000000000000ff - -/* SH_Y_MOD_DBUG_SEL_WBQ_SEL */ -/* Description: wbqtg select */ -#define SH_Y_MOD_DBUG_SEL_WBQ_SEL_SHFT 8 -#define SH_Y_MOD_DBUG_SEL_WBQ_SEL_MASK 0x000000000000ff00 - -/* SH_Y_MOD_DBUG_SEL_ARB_SEL */ -/* Description: arbque select */ -#define SH_Y_MOD_DBUG_SEL_ARB_SEL_SHFT 16 -#define SH_Y_MOD_DBUG_SEL_ARB_SEL_MASK 0x0000000000ff0000 - -/* SH_Y_MOD_DBUG_SEL_ATL_SEL */ -/* Description: aintl select */ -#define SH_Y_MOD_DBUG_SEL_ATL_SEL_SHFT 24 -#define SH_Y_MOD_DBUG_SEL_ATL_SEL_MASK 0x00000007ff000000 - -/* SH_Y_MOD_DBUG_SEL_ATR_SEL */ -/* Description: aintr select */ -#define SH_Y_MOD_DBUG_SEL_ATR_SEL_SHFT 35 -#define SH_Y_MOD_DBUG_SEL_ATR_SEL_MASK 0x00003ff800000000 - -/* SH_Y_MOD_DBUG_SEL_DQL_SEL */ -/* Description: dqctr select */ -#define SH_Y_MOD_DBUG_SEL_DQL_SEL_SHFT 46 -#define SH_Y_MOD_DBUG_SEL_DQL_SEL_MASK 0x000fc00000000000 - -/* SH_Y_MOD_DBUG_SEL_DQR_SEL */ -/* Description: dqctl select */ -#define SH_Y_MOD_DBUG_SEL_DQR_SEL_SHFT 52 -#define SH_Y_MOD_DBUG_SEL_DQR_SEL_MASK 0x03f0000000000000 - -/* ==================================================================== */ -/* Register "SH_Y_DBUG_SEL" */ -/* MD acy debug select */ -/* ==================================================================== */ - -#define SH_Y_DBUG_SEL 0x0000000100020150 -#define SH_Y_DBUG_SEL_MASK 0x0000000000ffffff -#define SH_Y_DBUG_SEL_INIT 0x0000000000000000 - -/* SH_Y_DBUG_SEL_DBG_SEL */ -/* Description: debug select */ -#define SH_Y_DBUG_SEL_DBG_SEL_SHFT 0 -#define SH_Y_DBUG_SEL_DBG_SEL_MASK 0x0000000000ffffff - -/* ==================================================================== */ -/* Register "SH_Y_LADDR_CMP" */ -/* MD acy address compare */ -/* ==================================================================== */ - -#define SH_Y_LADDR_CMP 0x0000000100020158 -#define SH_Y_LADDR_CMP_MASK 0x0fffffff0fffffff -#define SH_Y_LADDR_CMP_INIT 0x0000000000000000 - -/* SH_Y_LADDR_CMP_CMP_VAL */ -/* Description: Compare value */ -#define SH_Y_LADDR_CMP_CMP_VAL_SHFT 0 -#define SH_Y_LADDR_CMP_CMP_VAL_MASK 0x000000000fffffff - -/* SH_Y_LADDR_CMP_MASK_VAL */ -/* Description: Mask value */ -#define SH_Y_LADDR_CMP_MASK_VAL_SHFT 32 -#define SH_Y_LADDR_CMP_MASK_VAL_MASK 0x0fffffff00000000 - -/* ==================================================================== */ -/* Register "SH_Y_RADDR_CMP" */ -/* MD acy address compare */ -/* ==================================================================== */ - -#define SH_Y_RADDR_CMP 0x0000000100020160 -#define SH_Y_RADDR_CMP_MASK 0x0fffffff0fffffff -#define SH_Y_RADDR_CMP_INIT 0x0000000000000000 - -/* SH_Y_RADDR_CMP_CMP_VAL */ -/* Description: Compare value */ -#define SH_Y_RADDR_CMP_CMP_VAL_SHFT 0 -#define SH_Y_RADDR_CMP_CMP_VAL_MASK 0x000000000fffffff - -/* SH_Y_RADDR_CMP_MASK_VAL */ -/* Description: Mask value */ -#define SH_Y_RADDR_CMP_MASK_VAL_SHFT 32 -#define SH_Y_RADDR_CMP_MASK_VAL_MASK 0x0fffffff00000000 - -/* ==================================================================== */ -/* Register "SH_Y_TAG_CMP" */ -/* MD acy tagmgr compare */ -/* ==================================================================== */ - -#define SH_Y_TAG_CMP 0x0000000100020168 -#define SH_Y_TAG_CMP_MASK 0x007fffffffffffff -#define SH_Y_TAG_CMP_INIT 0x0000000000000000 - -/* SH_Y_TAG_CMP_CMD */ -/* Description: Command compare value */ -#define SH_Y_TAG_CMP_CMD_SHFT 0 -#define SH_Y_TAG_CMP_CMD_MASK 0x00000000000000ff - -/* SH_Y_TAG_CMP_ADDR */ -/* Description: Address compare value */ -#define SH_Y_TAG_CMP_ADDR_SHFT 8 -#define SH_Y_TAG_CMP_ADDR_MASK 0x000001ffffffff00 - -/* SH_Y_TAG_CMP_SRC */ -/* Description: Source compare value */ -#define SH_Y_TAG_CMP_SRC_SHFT 41 -#define SH_Y_TAG_CMP_SRC_MASK 0x007ffe0000000000 - -/* ==================================================================== */ -/* Register "SH_Y_TAG_MASK" */ -/* MD acy tagmgr mask */ -/* ==================================================================== */ - -#define SH_Y_TAG_MASK 0x0000000100020170 -#define SH_Y_TAG_MASK_MASK 0x007fffffffffffff -#define SH_Y_TAG_MASK_INIT 0x0000000000000000 - -/* SH_Y_TAG_MASK_CMD */ -/* Description: Command compare value */ -#define SH_Y_TAG_MASK_CMD_SHFT 0 -#define SH_Y_TAG_MASK_CMD_MASK 0x00000000000000ff - -/* SH_Y_TAG_MASK_ADDR */ -/* Description: Address compare value */ -#define SH_Y_TAG_MASK_ADDR_SHFT 8 -#define SH_Y_TAG_MASK_ADDR_MASK 0x000001ffffffff00 - -/* SH_Y_TAG_MASK_SRC */ -/* Description: Source compare value */ -#define SH_Y_TAG_MASK_SRC_SHFT 41 -#define SH_Y_TAG_MASK_SRC_MASK 0x007ffe0000000000 - -/* ==================================================================== */ -/* Register "SH_MD_JNR_DBUG_DATA_CFG" */ -/* configuration for md jnr debug data muxes */ -/* ==================================================================== */ - -#define SH_MD_JNR_DBUG_DATA_CFG 0x0000000100020178 -#define SH_MD_JNR_DBUG_DATA_CFG_MASK 0x0000000077777777 -#define SH_MD_JNR_DBUG_DATA_CFG_INIT 0x0000000000000000 - -/* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE0_SEL */ -/* Description: selects which nibble drives nibble0 */ -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE0_SEL_SHFT 0 -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE0_SEL_MASK 0x0000000000000007 - -/* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE1_SEL */ -/* Description: selects which nibble drives nibble1 */ -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE1_SEL_SHFT 4 -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE1_SEL_MASK 0x0000000000000070 - -/* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE2_SEL */ -/* Description: selects which nibble drives nibble2 */ -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE2_SEL_SHFT 8 -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE2_SEL_MASK 0x0000000000000700 - -/* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE3_SEL */ -/* Description: selects which nibble drives nibble3 */ -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE3_SEL_SHFT 12 -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE3_SEL_MASK 0x0000000000007000 - -/* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE4_SEL */ -/* Description: selects which nibble drives nibble4 */ -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE4_SEL_SHFT 16 -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE4_SEL_MASK 0x0000000000070000 - -/* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE5_SEL */ -/* Description: selects which nibble drives nibble5 */ -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE5_SEL_SHFT 20 -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE5_SEL_MASK 0x0000000000700000 - -/* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE6_SEL */ -/* Description: selects which nibble drives nibble6 */ -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE6_SEL_SHFT 24 -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE6_SEL_MASK 0x0000000007000000 - -/* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE7_SEL */ -/* Description: selects which nibble drives nibble7 */ -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE7_SEL_SHFT 28 -#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE7_SEL_MASK 0x0000000070000000 - -/* ==================================================================== */ -/* Register "SH_MD_LAST_CREDIT" */ -/* captures last credit values on reset */ -/* ==================================================================== */ - -#define SH_MD_LAST_CREDIT 0x0000000100020180 -#define SH_MD_LAST_CREDIT_MASK 0x0000003f3f3f3f3f -#define SH_MD_LAST_CREDIT_INIT 0x0000000000000000 - -/* SH_MD_LAST_CREDIT_RQ_TO_PI */ -/* Description: capture of request credits to pi */ -#define SH_MD_LAST_CREDIT_RQ_TO_PI_SHFT 0 -#define SH_MD_LAST_CREDIT_RQ_TO_PI_MASK 0x000000000000003f - -/* SH_MD_LAST_CREDIT_RP_TO_PI */ -/* Description: capture of reply credits to pi */ -#define SH_MD_LAST_CREDIT_RP_TO_PI_SHFT 8 -#define SH_MD_LAST_CREDIT_RP_TO_PI_MASK 0x0000000000003f00 - -/* SH_MD_LAST_CREDIT_RQ_TO_XN */ -/* Description: capture of request credits to xn */ -#define SH_MD_LAST_CREDIT_RQ_TO_XN_SHFT 16 -#define SH_MD_LAST_CREDIT_RQ_TO_XN_MASK 0x00000000003f0000 - -/* SH_MD_LAST_CREDIT_RP_TO_XN */ -/* Description: capture of reply credits to xn */ -#define SH_MD_LAST_CREDIT_RP_TO_XN_SHFT 24 -#define SH_MD_LAST_CREDIT_RP_TO_XN_MASK 0x000000003f000000 - -/* SH_MD_LAST_CREDIT_TO_LB */ -/* Description: capture of credits to pi */ -#define SH_MD_LAST_CREDIT_TO_LB_SHFT 32 -#define SH_MD_LAST_CREDIT_TO_LB_MASK 0x0000003f00000000 - -/* ==================================================================== */ -/* Register "SH_MEM_CAPTURE_ADDR" */ -/* Address capture address register */ -/* ==================================================================== */ - -#define SH_MEM_CAPTURE_ADDR 0x0000000100020300 -#define SH_MEM_CAPTURE_ADDR_MASK 0x00000ffffffffff8 -#define SH_MEM_CAPTURE_ADDR_INIT 0x0000000000000000 - -/* SH_MEM_CAPTURE_ADDR_ADDR */ -/* Description: upper bits of address */ -#define SH_MEM_CAPTURE_ADDR_ADDR_SHFT 3 -#define SH_MEM_CAPTURE_ADDR_ADDR_MASK 0x0000000ffffffff8 - -/* SH_MEM_CAPTURE_ADDR_CMD */ -/* Description: command of reference */ -#define SH_MEM_CAPTURE_ADDR_CMD_SHFT 36 -#define SH_MEM_CAPTURE_ADDR_CMD_MASK 0x00000ff000000000 - -/* ==================================================================== */ -/* Register "SH_MEM_CAPTURE_MASK" */ -/* Address capture mask register */ -/* ==================================================================== */ - -#define SH_MEM_CAPTURE_MASK 0x0000000100020308 -#define SH_MEM_CAPTURE_MASK_MASK 0x00003ffffffffff8 -#define SH_MEM_CAPTURE_MASK_INIT 0x0000000000000000 - -/* SH_MEM_CAPTURE_MASK_ADDR */ -/* Description: upper bits of address */ -#define SH_MEM_CAPTURE_MASK_ADDR_SHFT 3 -#define SH_MEM_CAPTURE_MASK_ADDR_MASK 0x0000000ffffffff8 - -/* SH_MEM_CAPTURE_MASK_CMD */ -/* Description: command of reference */ -#define SH_MEM_CAPTURE_MASK_CMD_SHFT 36 -#define SH_MEM_CAPTURE_MASK_CMD_MASK 0x00000ff000000000 - -/* SH_MEM_CAPTURE_MASK_ENABLE_LOCAL */ -/* Description: capture references originating locally */ -#define SH_MEM_CAPTURE_MASK_ENABLE_LOCAL_SHFT 44 -#define SH_MEM_CAPTURE_MASK_ENABLE_LOCAL_MASK 0x0000100000000000 - -/* SH_MEM_CAPTURE_MASK_ENABLE_REMOTE */ -/* Description: capture references originating remotely */ -#define SH_MEM_CAPTURE_MASK_ENABLE_REMOTE_SHFT 45 -#define SH_MEM_CAPTURE_MASK_ENABLE_REMOTE_MASK 0x0000200000000000 - -/* ==================================================================== */ -/* Register "SH_MEM_CAPTURE_HDR" */ -/* Address capture header register */ -/* ==================================================================== */ - -#define SH_MEM_CAPTURE_HDR 0x0000000100020310 -#define SH_MEM_CAPTURE_HDR_MASK 0xfffffffffffffff8 -#define SH_MEM_CAPTURE_HDR_INIT 0x0000000000000000 - -/* SH_MEM_CAPTURE_HDR_ADDR */ -/* Description: upper bits of reference address */ -#define SH_MEM_CAPTURE_HDR_ADDR_SHFT 3 -#define SH_MEM_CAPTURE_HDR_ADDR_MASK 0x0000000ffffffff8 - -/* SH_MEM_CAPTURE_HDR_CMD */ -/* Description: command of reference */ -#define SH_MEM_CAPTURE_HDR_CMD_SHFT 36 -#define SH_MEM_CAPTURE_HDR_CMD_MASK 0x00000ff000000000 - -/* SH_MEM_CAPTURE_HDR_SRC */ -/* Description: source node of reference */ -#define SH_MEM_CAPTURE_HDR_SRC_SHFT 44 -#define SH_MEM_CAPTURE_HDR_SRC_MASK 0x03fff00000000000 - -/* SH_MEM_CAPTURE_HDR_CNTR */ -/* Description: increments on every capture */ -#define SH_MEM_CAPTURE_HDR_CNTR_SHFT 58 -#define SH_MEM_CAPTURE_HDR_CNTR_MASK 0xfc00000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_CONFIG" */ -/* DQ directory config register */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_CONFIG 0x0000000100030000 -#define SH_MD_DQLP_MMR_DIR_CONFIG_MASK 0x000000000000001f -#define SH_MD_DQLP_MMR_DIR_CONFIG_INIT 0x0000000000000010 - -/* SH_MD_DQLP_MMR_DIR_CONFIG_SYS_SIZE */ -/* Description: system size code */ -#define SH_MD_DQLP_MMR_DIR_CONFIG_SYS_SIZE_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_CONFIG_SYS_SIZE_MASK 0x0000000000000007 - -/* SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRECC */ -/* Description: enable directory ecc correction */ -#define SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRECC_SHFT 3 -#define SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRECC_MASK 0x0000000000000008 - -/* SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRPOIS */ -/* Description: enable local poisoning for dir table fall-through */ -#define SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRPOIS_SHFT 4 -#define SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRPOIS_MASK 0x0000000000000010 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRESVEC0" */ -/* node [63:0] presence bits */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_PRESVEC0 0x0000000100030100 -#define SH_MD_DQLP_MMR_DIR_PRESVEC0_MASK 0xffffffffffffffff -#define SH_MD_DQLP_MMR_DIR_PRESVEC0_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_PRESVEC0_VEC */ -/* Description: node presence bits, 1=present */ -#define SH_MD_DQLP_MMR_DIR_PRESVEC0_VEC_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_PRESVEC0_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRESVEC1" */ -/* node [127:64] presence bits */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_PRESVEC1 0x0000000100030110 -#define SH_MD_DQLP_MMR_DIR_PRESVEC1_MASK 0xffffffffffffffff -#define SH_MD_DQLP_MMR_DIR_PRESVEC1_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_PRESVEC1_VEC */ -/* Description: node presence bits, 1=present */ -#define SH_MD_DQLP_MMR_DIR_PRESVEC1_VEC_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_PRESVEC1_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRESVEC2" */ -/* node [191:128] presence bits */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_PRESVEC2 0x0000000100030120 -#define SH_MD_DQLP_MMR_DIR_PRESVEC2_MASK 0xffffffffffffffff -#define SH_MD_DQLP_MMR_DIR_PRESVEC2_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_PRESVEC2_VEC */ -/* Description: node presence bits, 1=present */ -#define SH_MD_DQLP_MMR_DIR_PRESVEC2_VEC_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_PRESVEC2_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRESVEC3" */ -/* node [255:192] presence bits */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_PRESVEC3 0x0000000100030130 -#define SH_MD_DQLP_MMR_DIR_PRESVEC3_MASK 0xffffffffffffffff -#define SH_MD_DQLP_MMR_DIR_PRESVEC3_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_PRESVEC3_VEC */ -/* Description: node presence bits, 1=present */ -#define SH_MD_DQLP_MMR_DIR_PRESVEC3_VEC_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_PRESVEC3_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC0" */ -/* local vector for acc=0 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_LOCVEC0 0x0000000100030200 -#define SH_MD_DQLP_MMR_DIR_LOCVEC0_MASK 0xffffffffffffffff -#define SH_MD_DQLP_MMR_DIR_LOCVEC0_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_LOCVEC0_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQLP_MMR_DIR_LOCVEC0_VEC_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_LOCVEC0_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC1" */ -/* local vector for acc=1 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_LOCVEC1 0x0000000100030210 -#define SH_MD_DQLP_MMR_DIR_LOCVEC1_MASK 0xffffffffffffffff -#define SH_MD_DQLP_MMR_DIR_LOCVEC1_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_LOCVEC1_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQLP_MMR_DIR_LOCVEC1_VEC_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_LOCVEC1_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC2" */ -/* local vector for acc=2 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_LOCVEC2 0x0000000100030220 -#define SH_MD_DQLP_MMR_DIR_LOCVEC2_MASK 0xffffffffffffffff -#define SH_MD_DQLP_MMR_DIR_LOCVEC2_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_LOCVEC2_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQLP_MMR_DIR_LOCVEC2_VEC_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_LOCVEC2_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC3" */ -/* local vector for acc=3 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_LOCVEC3 0x0000000100030230 -#define SH_MD_DQLP_MMR_DIR_LOCVEC3_MASK 0xffffffffffffffff -#define SH_MD_DQLP_MMR_DIR_LOCVEC3_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_LOCVEC3_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQLP_MMR_DIR_LOCVEC3_VEC_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_LOCVEC3_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC4" */ -/* local vector for acc=4 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_LOCVEC4 0x0000000100030240 -#define SH_MD_DQLP_MMR_DIR_LOCVEC4_MASK 0xffffffffffffffff -#define SH_MD_DQLP_MMR_DIR_LOCVEC4_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_LOCVEC4_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQLP_MMR_DIR_LOCVEC4_VEC_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_LOCVEC4_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC5" */ -/* local vector for acc=5 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_LOCVEC5 0x0000000100030250 -#define SH_MD_DQLP_MMR_DIR_LOCVEC5_MASK 0xffffffffffffffff -#define SH_MD_DQLP_MMR_DIR_LOCVEC5_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_LOCVEC5_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQLP_MMR_DIR_LOCVEC5_VEC_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_LOCVEC5_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC6" */ -/* local vector for acc=6 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_LOCVEC6 0x0000000100030260 -#define SH_MD_DQLP_MMR_DIR_LOCVEC6_MASK 0xffffffffffffffff -#define SH_MD_DQLP_MMR_DIR_LOCVEC6_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_LOCVEC6_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQLP_MMR_DIR_LOCVEC6_VEC_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_LOCVEC6_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC7" */ -/* local vector for acc=7 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_LOCVEC7 0x0000000100030270 -#define SH_MD_DQLP_MMR_DIR_LOCVEC7_MASK 0xffffffffffffffff -#define SH_MD_DQLP_MMR_DIR_LOCVEC7_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_LOCVEC7_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQLP_MMR_DIR_LOCVEC7_VEC_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_LOCVEC7_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC0" */ -/* privilege vector for acc=0 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_PRIVEC0 0x0000000100030300 -#define SH_MD_DQLP_MMR_DIR_PRIVEC0_MASK 0x000000000fffffff -#define SH_MD_DQLP_MMR_DIR_PRIVEC0_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_PRIVEC0_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC0_IN_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_PRIVEC0_IN_MASK 0x0000000000003fff - -/* SH_MD_DQLP_MMR_DIR_PRIVEC0_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC0_OUT_SHFT 14 -#define SH_MD_DQLP_MMR_DIR_PRIVEC0_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC1" */ -/* privilege vector for acc=1 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_PRIVEC1 0x0000000100030310 -#define SH_MD_DQLP_MMR_DIR_PRIVEC1_MASK 0x000000000fffffff -#define SH_MD_DQLP_MMR_DIR_PRIVEC1_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_PRIVEC1_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC1_IN_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_PRIVEC1_IN_MASK 0x0000000000003fff - -/* SH_MD_DQLP_MMR_DIR_PRIVEC1_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC1_OUT_SHFT 14 -#define SH_MD_DQLP_MMR_DIR_PRIVEC1_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC2" */ -/* privilege vector for acc=2 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_PRIVEC2 0x0000000100030320 -#define SH_MD_DQLP_MMR_DIR_PRIVEC2_MASK 0x000000000fffffff -#define SH_MD_DQLP_MMR_DIR_PRIVEC2_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_PRIVEC2_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC2_IN_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_PRIVEC2_IN_MASK 0x0000000000003fff - -/* SH_MD_DQLP_MMR_DIR_PRIVEC2_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC2_OUT_SHFT 14 -#define SH_MD_DQLP_MMR_DIR_PRIVEC2_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC3" */ -/* privilege vector for acc=3 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_PRIVEC3 0x0000000100030330 -#define SH_MD_DQLP_MMR_DIR_PRIVEC3_MASK 0x000000000fffffff -#define SH_MD_DQLP_MMR_DIR_PRIVEC3_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_PRIVEC3_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC3_IN_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_PRIVEC3_IN_MASK 0x0000000000003fff - -/* SH_MD_DQLP_MMR_DIR_PRIVEC3_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC3_OUT_SHFT 14 -#define SH_MD_DQLP_MMR_DIR_PRIVEC3_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC4" */ -/* privilege vector for acc=4 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_PRIVEC4 0x0000000100030340 -#define SH_MD_DQLP_MMR_DIR_PRIVEC4_MASK 0x000000000fffffff -#define SH_MD_DQLP_MMR_DIR_PRIVEC4_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_PRIVEC4_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC4_IN_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_PRIVEC4_IN_MASK 0x0000000000003fff - -/* SH_MD_DQLP_MMR_DIR_PRIVEC4_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC4_OUT_SHFT 14 -#define SH_MD_DQLP_MMR_DIR_PRIVEC4_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC5" */ -/* privilege vector for acc=5 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_PRIVEC5 0x0000000100030350 -#define SH_MD_DQLP_MMR_DIR_PRIVEC5_MASK 0x000000000fffffff -#define SH_MD_DQLP_MMR_DIR_PRIVEC5_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_PRIVEC5_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC5_IN_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_PRIVEC5_IN_MASK 0x0000000000003fff - -/* SH_MD_DQLP_MMR_DIR_PRIVEC5_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC5_OUT_SHFT 14 -#define SH_MD_DQLP_MMR_DIR_PRIVEC5_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC6" */ -/* privilege vector for acc=6 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_PRIVEC6 0x0000000100030360 -#define SH_MD_DQLP_MMR_DIR_PRIVEC6_MASK 0x000000000fffffff -#define SH_MD_DQLP_MMR_DIR_PRIVEC6_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_PRIVEC6_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC6_IN_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_PRIVEC6_IN_MASK 0x0000000000003fff - -/* SH_MD_DQLP_MMR_DIR_PRIVEC6_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC6_OUT_SHFT 14 -#define SH_MD_DQLP_MMR_DIR_PRIVEC6_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC7" */ -/* privilege vector for acc=7 */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_PRIVEC7 0x0000000100030370 -#define SH_MD_DQLP_MMR_DIR_PRIVEC7_MASK 0x000000000fffffff -#define SH_MD_DQLP_MMR_DIR_PRIVEC7_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_PRIVEC7_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC7_IN_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_PRIVEC7_IN_MASK 0x0000000000003fff - -/* SH_MD_DQLP_MMR_DIR_PRIVEC7_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQLP_MMR_DIR_PRIVEC7_OUT_SHFT 14 -#define SH_MD_DQLP_MMR_DIR_PRIVEC7_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_TIMER" */ -/* MD SXRO timer */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_TIMER 0x0000000100030400 -#define SH_MD_DQLP_MMR_DIR_TIMER_MASK 0x00000000003fffff -#define SH_MD_DQLP_MMR_DIR_TIMER_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_TIMER_TIMER_DIV */ -/* Description: timer divide register */ -#define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_DIV_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_DIV_MASK 0x0000000000000fff - -/* SH_MD_DQLP_MMR_DIR_TIMER_TIMER_EN */ -/* Description: timer enable */ -#define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_EN_SHFT 12 -#define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_EN_MASK 0x0000000000001000 - -/* SH_MD_DQLP_MMR_DIR_TIMER_TIMER_CUR */ -/* Description: value of current timer */ -#define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_CUR_SHFT 13 -#define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_CUR_MASK 0x00000000003fe000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY" */ -/* directory pio write data */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY 0x0000000100031000 -#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_MASK 0x03ffffffffffffff -#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRA */ -/* Description: directory entry A */ -#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRA_SHFT 0 -#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRA_MASK 0x0000000003ffffff - -/* SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRB */ -/* Description: directory entry B */ -#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRB_SHFT 26 -#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRB_MASK 0x000ffffffc000000 - -/* SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_PRI */ -/* Description: directory priority */ -#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_PRI_SHFT 52 -#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_PRI_MASK 0x0070000000000000 - -/* SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_ACC */ -/* Description: directory access bits */ -#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_ACC_SHFT 55 -#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_ACC_MASK 0x0380000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_PIOWD_DIR_ECC" */ -/* directory ecc register */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC 0x0000000100031010 -#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_MASK 0x0000000000003fff -#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCA */ -/* Description: XOR bits for directory ECC group 1 */ -#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCA_SHFT 0 -#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCA_MASK 0x000000000000007f - -/* SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCB */ -/* Description: XOR bits for directory ECC group 2 */ -#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCB_SHFT 7 -#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCB_MASK 0x0000000000003f80 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY" */ -/* x directory pio read data */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY 0x0000000100032000 -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_MASK 0x0fffffffffffffff -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRA */ -/* Description: directory entry A */ -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRA_SHFT 0 -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRA_MASK 0x0000000003ffffff - -/* SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRB */ -/* Description: directory entry B */ -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRB_SHFT 26 -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRB_MASK 0x000ffffffc000000 - -/* SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_PRI */ -/* Description: directory priority */ -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_PRI_SHFT 52 -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_PRI_MASK 0x0070000000000000 - -/* SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_ACC */ -/* Description: directory access bits */ -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_ACC_SHFT 55 -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_ACC_MASK 0x0380000000000000 - -/* SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_COR */ -/* Description: correctable ecc error */ -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_COR_SHFT 58 -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_COR_MASK 0x0400000000000000 - -/* SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_UNC */ -/* Description: uncorrectable ecc error */ -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_UNC_SHFT 59 -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_UNC_MASK 0x0800000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XPIORD_XDIR_ECC" */ -/* x directory ecc */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC 0x0000000100032010 -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_MASK 0x0000000000003fff -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCA */ -/* Description: group 1 ecc */ -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCA_SHFT 0 -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCA_MASK 0x000000000000007f - -/* SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCB */ -/* Description: group 2 ecc */ -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCB_SHFT 7 -#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCB_MASK 0x0000000000003f80 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY" */ -/* y directory pio read data */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY 0x0000000100032800 -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_MASK 0x0fffffffffffffff -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRA */ -/* Description: directory entry A */ -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRA_SHFT 0 -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRA_MASK 0x0000000003ffffff - -/* SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRB */ -/* Description: directory entry B */ -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRB_SHFT 26 -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRB_MASK 0x000ffffffc000000 - -/* SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_PRI */ -/* Description: directory priority */ -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_PRI_SHFT 52 -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_PRI_MASK 0x0070000000000000 - -/* SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_ACC */ -/* Description: directory access bits */ -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_ACC_SHFT 55 -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_ACC_MASK 0x0380000000000000 - -/* SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_COR */ -/* Description: correctable ecc error */ -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_COR_SHFT 58 -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_COR_MASK 0x0400000000000000 - -/* SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_UNC */ -/* Description: uncorrectable ecc error */ -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_UNC_SHFT 59 -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_UNC_MASK 0x0800000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YPIORD_YDIR_ECC" */ -/* y directory ecc */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC 0x0000000100032810 -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_MASK 0x0000000000003fff -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCA */ -/* Description: group 1 ecc */ -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCA_SHFT 0 -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCA_MASK 0x000000000000007f - -/* SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCB */ -/* Description: group 2 ecc */ -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCB_SHFT 7 -#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCB_MASK 0x0000000000003f80 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XCERR1" */ -/* correctable dir ecc group 1 error register */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_XCERR1 0x0000000100033000 -#define SH_MD_DQLP_MMR_XCERR1_MASK 0x0000007fffffffff -#define SH_MD_DQLP_MMR_XCERR1_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_XCERR1_GRP1 */ -/* Description: ecc group 1 bits */ -#define SH_MD_DQLP_MMR_XCERR1_GRP1_SHFT 0 -#define SH_MD_DQLP_MMR_XCERR1_GRP1_MASK 0x0000000fffffffff - -/* SH_MD_DQLP_MMR_XCERR1_VAL */ -/* Description: correctable ecc error in group 1 bits */ -#define SH_MD_DQLP_MMR_XCERR1_VAL_SHFT 36 -#define SH_MD_DQLP_MMR_XCERR1_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQLP_MMR_XCERR1_MORE */ -/* Description: more than one correctable ecc error in group 1 */ -#define SH_MD_DQLP_MMR_XCERR1_MORE_SHFT 37 -#define SH_MD_DQLP_MMR_XCERR1_MORE_MASK 0x0000002000000000 - -/* SH_MD_DQLP_MMR_XCERR1_ARM */ -/* Description: writing 1 arms uncorrectable ecc error capture */ -#define SH_MD_DQLP_MMR_XCERR1_ARM_SHFT 38 -#define SH_MD_DQLP_MMR_XCERR1_ARM_MASK 0x0000004000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XCERR2" */ -/* correctable dir ecc group 2 error register */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_XCERR2 0x0000000100033010 -#define SH_MD_DQLP_MMR_XCERR2_MASK 0x0000003fffffffff -#define SH_MD_DQLP_MMR_XCERR2_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_XCERR2_GRP2 */ -/* Description: ecc group 2 bits */ -#define SH_MD_DQLP_MMR_XCERR2_GRP2_SHFT 0 -#define SH_MD_DQLP_MMR_XCERR2_GRP2_MASK 0x0000000fffffffff - -/* SH_MD_DQLP_MMR_XCERR2_VAL */ -/* Description: correctable ecc error in group 2 bits */ -#define SH_MD_DQLP_MMR_XCERR2_VAL_SHFT 36 -#define SH_MD_DQLP_MMR_XCERR2_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQLP_MMR_XCERR2_MORE */ -/* Description: more than one correctable ecc error in group 2 */ -#define SH_MD_DQLP_MMR_XCERR2_MORE_SHFT 37 -#define SH_MD_DQLP_MMR_XCERR2_MORE_MASK 0x0000002000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XUERR1" */ -/* uncorrectable dir ecc group 1 error register */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_XUERR1 0x0000000100033020 -#define SH_MD_DQLP_MMR_XUERR1_MASK 0x0000007fffffffff -#define SH_MD_DQLP_MMR_XUERR1_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_XUERR1_GRP1 */ -/* Description: ecc group 1 bits */ -#define SH_MD_DQLP_MMR_XUERR1_GRP1_SHFT 0 -#define SH_MD_DQLP_MMR_XUERR1_GRP1_MASK 0x0000000fffffffff - -/* SH_MD_DQLP_MMR_XUERR1_VAL */ -/* Description: uncorrectable ecc error in group 1 bits */ -#define SH_MD_DQLP_MMR_XUERR1_VAL_SHFT 36 -#define SH_MD_DQLP_MMR_XUERR1_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQLP_MMR_XUERR1_MORE */ -/* Description: more than one uncorrectable ecc error in group 1 */ -#define SH_MD_DQLP_MMR_XUERR1_MORE_SHFT 37 -#define SH_MD_DQLP_MMR_XUERR1_MORE_MASK 0x0000002000000000 - -/* SH_MD_DQLP_MMR_XUERR1_ARM */ -/* Description: writing 1 arms uncorrectable ecc error capture */ -#define SH_MD_DQLP_MMR_XUERR1_ARM_SHFT 38 -#define SH_MD_DQLP_MMR_XUERR1_ARM_MASK 0x0000004000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XUERR2" */ -/* uncorrectable dir ecc group 2 error register */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_XUERR2 0x0000000100033030 -#define SH_MD_DQLP_MMR_XUERR2_MASK 0x0000003fffffffff -#define SH_MD_DQLP_MMR_XUERR2_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_XUERR2_GRP2 */ -/* Description: ecc group 2 bits */ -#define SH_MD_DQLP_MMR_XUERR2_GRP2_SHFT 0 -#define SH_MD_DQLP_MMR_XUERR2_GRP2_MASK 0x0000000fffffffff - -/* SH_MD_DQLP_MMR_XUERR2_VAL */ -/* Description: uncorrectable ecc error in group 2 bits */ -#define SH_MD_DQLP_MMR_XUERR2_VAL_SHFT 36 -#define SH_MD_DQLP_MMR_XUERR2_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQLP_MMR_XUERR2_MORE */ -/* Description: more than one uncorrectable ecc error in group 2 */ -#define SH_MD_DQLP_MMR_XUERR2_MORE_SHFT 37 -#define SH_MD_DQLP_MMR_XUERR2_MORE_MASK 0x0000002000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XPERR" */ -/* protocol error register */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_XPERR 0x0000000100033040 -#define SH_MD_DQLP_MMR_XPERR_MASK 0x7fffffffffffffff -#define SH_MD_DQLP_MMR_XPERR_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_XPERR_DIR */ -/* Description: directory entry */ -#define SH_MD_DQLP_MMR_XPERR_DIR_SHFT 0 -#define SH_MD_DQLP_MMR_XPERR_DIR_MASK 0x0000000003ffffff - -/* SH_MD_DQLP_MMR_XPERR_CMD */ -/* Description: incoming command */ -#define SH_MD_DQLP_MMR_XPERR_CMD_SHFT 26 -#define SH_MD_DQLP_MMR_XPERR_CMD_MASK 0x00000003fc000000 - -/* SH_MD_DQLP_MMR_XPERR_SRC */ -/* Description: source node of dir operation */ -#define SH_MD_DQLP_MMR_XPERR_SRC_SHFT 34 -#define SH_MD_DQLP_MMR_XPERR_SRC_MASK 0x0000fffc00000000 - -/* SH_MD_DQLP_MMR_XPERR_PRIGE */ -/* Description: priority was greater-equal */ -#define SH_MD_DQLP_MMR_XPERR_PRIGE_SHFT 48 -#define SH_MD_DQLP_MMR_XPERR_PRIGE_MASK 0x0001000000000000 - -/* SH_MD_DQLP_MMR_XPERR_PRIV */ -/* Description: access privilege bit */ -#define SH_MD_DQLP_MMR_XPERR_PRIV_SHFT 49 -#define SH_MD_DQLP_MMR_XPERR_PRIV_MASK 0x0002000000000000 - -/* SH_MD_DQLP_MMR_XPERR_COR */ -/* Description: correctable ecc error */ -#define SH_MD_DQLP_MMR_XPERR_COR_SHFT 50 -#define SH_MD_DQLP_MMR_XPERR_COR_MASK 0x0004000000000000 - -/* SH_MD_DQLP_MMR_XPERR_UNC */ -/* Description: uncorrectable ecc error */ -#define SH_MD_DQLP_MMR_XPERR_UNC_SHFT 51 -#define SH_MD_DQLP_MMR_XPERR_UNC_MASK 0x0008000000000000 - -/* SH_MD_DQLP_MMR_XPERR_MYBIT */ -/* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */ -#define SH_MD_DQLP_MMR_XPERR_MYBIT_SHFT 52 -#define SH_MD_DQLP_MMR_XPERR_MYBIT_MASK 0x0ff0000000000000 - -/* SH_MD_DQLP_MMR_XPERR_VAL */ -/* Description: protocol error info valid */ -#define SH_MD_DQLP_MMR_XPERR_VAL_SHFT 60 -#define SH_MD_DQLP_MMR_XPERR_VAL_MASK 0x1000000000000000 - -/* SH_MD_DQLP_MMR_XPERR_MORE */ -/* Description: more than one protocol error */ -#define SH_MD_DQLP_MMR_XPERR_MORE_SHFT 61 -#define SH_MD_DQLP_MMR_XPERR_MORE_MASK 0x2000000000000000 - -/* SH_MD_DQLP_MMR_XPERR_ARM */ -/* Description: writing 1 arms error capture */ -#define SH_MD_DQLP_MMR_XPERR_ARM_SHFT 62 -#define SH_MD_DQLP_MMR_XPERR_ARM_MASK 0x4000000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YCERR1" */ -/* correctable dir ecc group 1 error register */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_YCERR1 0x0000000100033800 -#define SH_MD_DQLP_MMR_YCERR1_MASK 0x0000007fffffffff -#define SH_MD_DQLP_MMR_YCERR1_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_YCERR1_GRP1 */ -/* Description: ecc group 1 bits */ -#define SH_MD_DQLP_MMR_YCERR1_GRP1_SHFT 0 -#define SH_MD_DQLP_MMR_YCERR1_GRP1_MASK 0x0000000fffffffff - -/* SH_MD_DQLP_MMR_YCERR1_VAL */ -/* Description: correctable ecc error in group 1 bits */ -#define SH_MD_DQLP_MMR_YCERR1_VAL_SHFT 36 -#define SH_MD_DQLP_MMR_YCERR1_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQLP_MMR_YCERR1_MORE */ -/* Description: more than one correctable ecc error in group 1 */ -#define SH_MD_DQLP_MMR_YCERR1_MORE_SHFT 37 -#define SH_MD_DQLP_MMR_YCERR1_MORE_MASK 0x0000002000000000 - -/* SH_MD_DQLP_MMR_YCERR1_ARM */ -/* Description: writing 1 arms uncorrectable ecc error capture */ -#define SH_MD_DQLP_MMR_YCERR1_ARM_SHFT 38 -#define SH_MD_DQLP_MMR_YCERR1_ARM_MASK 0x0000004000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YCERR2" */ -/* correctable dir ecc group 2 error register */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_YCERR2 0x0000000100033810 -#define SH_MD_DQLP_MMR_YCERR2_MASK 0x0000003fffffffff -#define SH_MD_DQLP_MMR_YCERR2_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_YCERR2_GRP2 */ -/* Description: ecc group 2 bits */ -#define SH_MD_DQLP_MMR_YCERR2_GRP2_SHFT 0 -#define SH_MD_DQLP_MMR_YCERR2_GRP2_MASK 0x0000000fffffffff - -/* SH_MD_DQLP_MMR_YCERR2_VAL */ -/* Description: correctable ecc error in group 2 bits */ -#define SH_MD_DQLP_MMR_YCERR2_VAL_SHFT 36 -#define SH_MD_DQLP_MMR_YCERR2_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQLP_MMR_YCERR2_MORE */ -/* Description: more than one correctable ecc error in group 2 */ -#define SH_MD_DQLP_MMR_YCERR2_MORE_SHFT 37 -#define SH_MD_DQLP_MMR_YCERR2_MORE_MASK 0x0000002000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YUERR1" */ -/* uncorrectable dir ecc group 1 error register */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_YUERR1 0x0000000100033820 -#define SH_MD_DQLP_MMR_YUERR1_MASK 0x0000007fffffffff -#define SH_MD_DQLP_MMR_YUERR1_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_YUERR1_GRP1 */ -/* Description: ecc group 1 bits */ -#define SH_MD_DQLP_MMR_YUERR1_GRP1_SHFT 0 -#define SH_MD_DQLP_MMR_YUERR1_GRP1_MASK 0x0000000fffffffff - -/* SH_MD_DQLP_MMR_YUERR1_VAL */ -/* Description: uncorrectable ecc error in group 1 bits */ -#define SH_MD_DQLP_MMR_YUERR1_VAL_SHFT 36 -#define SH_MD_DQLP_MMR_YUERR1_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQLP_MMR_YUERR1_MORE */ -/* Description: more than one uncorrectable ecc error in group 1 */ -#define SH_MD_DQLP_MMR_YUERR1_MORE_SHFT 37 -#define SH_MD_DQLP_MMR_YUERR1_MORE_MASK 0x0000002000000000 - -/* SH_MD_DQLP_MMR_YUERR1_ARM */ -/* Description: writing 1 arms uncorrectable ecc error capture */ -#define SH_MD_DQLP_MMR_YUERR1_ARM_SHFT 38 -#define SH_MD_DQLP_MMR_YUERR1_ARM_MASK 0x0000004000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YUERR2" */ -/* uncorrectable dir ecc group 2 error register */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_YUERR2 0x0000000100033830 -#define SH_MD_DQLP_MMR_YUERR2_MASK 0x0000003fffffffff -#define SH_MD_DQLP_MMR_YUERR2_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_YUERR2_GRP2 */ -/* Description: ecc group 2 bits */ -#define SH_MD_DQLP_MMR_YUERR2_GRP2_SHFT 0 -#define SH_MD_DQLP_MMR_YUERR2_GRP2_MASK 0x0000000fffffffff - -/* SH_MD_DQLP_MMR_YUERR2_VAL */ -/* Description: uncorrectable ecc error in group 2 bits */ -#define SH_MD_DQLP_MMR_YUERR2_VAL_SHFT 36 -#define SH_MD_DQLP_MMR_YUERR2_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQLP_MMR_YUERR2_MORE */ -/* Description: more than one uncorrectable ecc error in group 2 */ -#define SH_MD_DQLP_MMR_YUERR2_MORE_SHFT 37 -#define SH_MD_DQLP_MMR_YUERR2_MORE_MASK 0x0000002000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YPERR" */ -/* protocol error register */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_YPERR 0x0000000100033840 -#define SH_MD_DQLP_MMR_YPERR_MASK 0x7fffffffffffffff -#define SH_MD_DQLP_MMR_YPERR_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_YPERR_DIR */ -/* Description: directory entry */ -#define SH_MD_DQLP_MMR_YPERR_DIR_SHFT 0 -#define SH_MD_DQLP_MMR_YPERR_DIR_MASK 0x0000000003ffffff - -/* SH_MD_DQLP_MMR_YPERR_CMD */ -/* Description: incoming command */ -#define SH_MD_DQLP_MMR_YPERR_CMD_SHFT 26 -#define SH_MD_DQLP_MMR_YPERR_CMD_MASK 0x00000003fc000000 - -/* SH_MD_DQLP_MMR_YPERR_SRC */ -/* Description: source node of dir operation */ -#define SH_MD_DQLP_MMR_YPERR_SRC_SHFT 34 -#define SH_MD_DQLP_MMR_YPERR_SRC_MASK 0x0000fffc00000000 - -/* SH_MD_DQLP_MMR_YPERR_PRIGE */ -/* Description: priority was greater-equal */ -#define SH_MD_DQLP_MMR_YPERR_PRIGE_SHFT 48 -#define SH_MD_DQLP_MMR_YPERR_PRIGE_MASK 0x0001000000000000 - -/* SH_MD_DQLP_MMR_YPERR_PRIV */ -/* Description: access privilege bit */ -#define SH_MD_DQLP_MMR_YPERR_PRIV_SHFT 49 -#define SH_MD_DQLP_MMR_YPERR_PRIV_MASK 0x0002000000000000 - -/* SH_MD_DQLP_MMR_YPERR_COR */ -/* Description: correctable ecc error */ -#define SH_MD_DQLP_MMR_YPERR_COR_SHFT 50 -#define SH_MD_DQLP_MMR_YPERR_COR_MASK 0x0004000000000000 - -/* SH_MD_DQLP_MMR_YPERR_UNC */ -/* Description: uncorrectable ecc error */ -#define SH_MD_DQLP_MMR_YPERR_UNC_SHFT 51 -#define SH_MD_DQLP_MMR_YPERR_UNC_MASK 0x0008000000000000 - -/* SH_MD_DQLP_MMR_YPERR_MYBIT */ -/* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */ -#define SH_MD_DQLP_MMR_YPERR_MYBIT_SHFT 52 -#define SH_MD_DQLP_MMR_YPERR_MYBIT_MASK 0x0ff0000000000000 - -/* SH_MD_DQLP_MMR_YPERR_VAL */ -/* Description: protocol error info valid */ -#define SH_MD_DQLP_MMR_YPERR_VAL_SHFT 60 -#define SH_MD_DQLP_MMR_YPERR_VAL_MASK 0x1000000000000000 - -/* SH_MD_DQLP_MMR_YPERR_MORE */ -/* Description: more than one protocol error */ -#define SH_MD_DQLP_MMR_YPERR_MORE_SHFT 61 -#define SH_MD_DQLP_MMR_YPERR_MORE_MASK 0x2000000000000000 - -/* SH_MD_DQLP_MMR_YPERR_ARM */ -/* Description: writing 1 arms error capture */ -#define SH_MD_DQLP_MMR_YPERR_ARM_SHFT 62 -#define SH_MD_DQLP_MMR_YPERR_ARM_MASK 0x4000000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_CMDTRIG" */ -/* cmd triggers */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_CMDTRIG 0x0000000100034000 -#define SH_MD_DQLP_MMR_DIR_CMDTRIG_MASK 0x00000000ffffffff -#define SH_MD_DQLP_MMR_DIR_CMDTRIG_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD0 */ -/* Description: command trigger 0 */ -#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD0_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD0_MASK 0x00000000000000ff - -/* SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD1 */ -/* Description: command trigger 1 */ -#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD1_SHFT 8 -#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD1_MASK 0x000000000000ff00 - -/* SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD2 */ -/* Description: command trigger 2 */ -#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD2_SHFT 16 -#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD2_MASK 0x0000000000ff0000 - -/* SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD3 */ -/* Description: command trigger 3 */ -#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD3_SHFT 24 -#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD3_MASK 0x00000000ff000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_TBLTRIG" */ -/* dir table trigger */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_TBLTRIG 0x0000000100034010 -#define SH_MD_DQLP_MMR_DIR_TBLTRIG_MASK 0x000003ffffffffff -#define SH_MD_DQLP_MMR_DIR_TBLTRIG_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_TBLTRIG_SRC */ -/* Description: source of request */ -#define SH_MD_DQLP_MMR_DIR_TBLTRIG_SRC_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_TBLTRIG_SRC_MASK 0x0000000000003fff - -/* SH_MD_DQLP_MMR_DIR_TBLTRIG_CMD */ -/* Description: incoming request */ -#define SH_MD_DQLP_MMR_DIR_TBLTRIG_CMD_SHFT 14 -#define SH_MD_DQLP_MMR_DIR_TBLTRIG_CMD_MASK 0x00000000003fc000 - -/* SH_MD_DQLP_MMR_DIR_TBLTRIG_ACC */ -/* Description: uncorrectable error, privilege bit */ -#define SH_MD_DQLP_MMR_DIR_TBLTRIG_ACC_SHFT 22 -#define SH_MD_DQLP_MMR_DIR_TBLTRIG_ACC_MASK 0x0000000000c00000 - -/* SH_MD_DQLP_MMR_DIR_TBLTRIG_PRIGE */ -/* Description: priority greater-equal */ -#define SH_MD_DQLP_MMR_DIR_TBLTRIG_PRIGE_SHFT 24 -#define SH_MD_DQLP_MMR_DIR_TBLTRIG_PRIGE_MASK 0x0000000001000000 - -/* SH_MD_DQLP_MMR_DIR_TBLTRIG_DIRST */ -/* Description: shrd,sxro,sub-state */ -#define SH_MD_DQLP_MMR_DIR_TBLTRIG_DIRST_SHFT 25 -#define SH_MD_DQLP_MMR_DIR_TBLTRIG_DIRST_MASK 0x00000003fe000000 - -/* SH_MD_DQLP_MMR_DIR_TBLTRIG_MYBIT */ -/* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */ -#define SH_MD_DQLP_MMR_DIR_TBLTRIG_MYBIT_SHFT 34 -#define SH_MD_DQLP_MMR_DIR_TBLTRIG_MYBIT_MASK 0x000003fc00000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_DIR_TBLMASK" */ -/* dir table trigger mask */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_DIR_TBLMASK 0x0000000100034020 -#define SH_MD_DQLP_MMR_DIR_TBLMASK_MASK 0x000003ffffffffff -#define SH_MD_DQLP_MMR_DIR_TBLMASK_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_DIR_TBLMASK_SRC */ -/* Description: source of request */ -#define SH_MD_DQLP_MMR_DIR_TBLMASK_SRC_SHFT 0 -#define SH_MD_DQLP_MMR_DIR_TBLMASK_SRC_MASK 0x0000000000003fff - -/* SH_MD_DQLP_MMR_DIR_TBLMASK_CMD */ -/* Description: incoming request */ -#define SH_MD_DQLP_MMR_DIR_TBLMASK_CMD_SHFT 14 -#define SH_MD_DQLP_MMR_DIR_TBLMASK_CMD_MASK 0x00000000003fc000 - -/* SH_MD_DQLP_MMR_DIR_TBLMASK_ACC */ -/* Description: uncorrectable error, privilege bit */ -#define SH_MD_DQLP_MMR_DIR_TBLMASK_ACC_SHFT 22 -#define SH_MD_DQLP_MMR_DIR_TBLMASK_ACC_MASK 0x0000000000c00000 - -/* SH_MD_DQLP_MMR_DIR_TBLMASK_PRIGE */ -/* Description: priority greater-equal */ -#define SH_MD_DQLP_MMR_DIR_TBLMASK_PRIGE_SHFT 24 -#define SH_MD_DQLP_MMR_DIR_TBLMASK_PRIGE_MASK 0x0000000001000000 - -/* SH_MD_DQLP_MMR_DIR_TBLMASK_DIRST */ -/* Description: shrd,sxro,sub-state */ -#define SH_MD_DQLP_MMR_DIR_TBLMASK_DIRST_SHFT 25 -#define SH_MD_DQLP_MMR_DIR_TBLMASK_DIRST_MASK 0x00000003fe000000 - -/* SH_MD_DQLP_MMR_DIR_TBLMASK_MYBIT */ -/* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */ -#define SH_MD_DQLP_MMR_DIR_TBLMASK_MYBIT_SHFT 34 -#define SH_MD_DQLP_MMR_DIR_TBLMASK_MYBIT_MASK 0x000003fc00000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XBIST_H" */ -/* rising edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_XBIST_H 0x0000000100038000 -#define SH_MD_DQLP_MMR_XBIST_H_MASK 0x00000700ffffffff -#define SH_MD_DQLP_MMR_XBIST_H_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_XBIST_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLP_MMR_XBIST_H_PAT_SHFT 0 -#define SH_MD_DQLP_MMR_XBIST_H_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQLP_MMR_XBIST_H_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQLP_MMR_XBIST_H_INV_SHFT 40 -#define SH_MD_DQLP_MMR_XBIST_H_INV_MASK 0x0000010000000000 - -/* SH_MD_DQLP_MMR_XBIST_H_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQLP_MMR_XBIST_H_ROT_SHFT 41 -#define SH_MD_DQLP_MMR_XBIST_H_ROT_MASK 0x0000020000000000 - -/* SH_MD_DQLP_MMR_XBIST_H_ARM */ -/* Description: writing 1 arms data miscompare capture */ -#define SH_MD_DQLP_MMR_XBIST_H_ARM_SHFT 42 -#define SH_MD_DQLP_MMR_XBIST_H_ARM_MASK 0x0000040000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XBIST_L" */ -/* falling edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_XBIST_L 0x0000000100038010 -#define SH_MD_DQLP_MMR_XBIST_L_MASK 0x00000300ffffffff -#define SH_MD_DQLP_MMR_XBIST_L_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_XBIST_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLP_MMR_XBIST_L_PAT_SHFT 0 -#define SH_MD_DQLP_MMR_XBIST_L_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQLP_MMR_XBIST_L_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQLP_MMR_XBIST_L_INV_SHFT 40 -#define SH_MD_DQLP_MMR_XBIST_L_INV_MASK 0x0000010000000000 - -/* SH_MD_DQLP_MMR_XBIST_L_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQLP_MMR_XBIST_L_ROT_SHFT 41 -#define SH_MD_DQLP_MMR_XBIST_L_ROT_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XBIST_ERR_H" */ -/* rising edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_XBIST_ERR_H 0x0000000100038020 -#define SH_MD_DQLP_MMR_XBIST_ERR_H_MASK 0x00000300ffffffff -#define SH_MD_DQLP_MMR_XBIST_ERR_H_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_XBIST_ERR_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLP_MMR_XBIST_ERR_H_PAT_SHFT 0 -#define SH_MD_DQLP_MMR_XBIST_ERR_H_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQLP_MMR_XBIST_ERR_H_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQLP_MMR_XBIST_ERR_H_VAL_SHFT 40 -#define SH_MD_DQLP_MMR_XBIST_ERR_H_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQLP_MMR_XBIST_ERR_H_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQLP_MMR_XBIST_ERR_H_MORE_SHFT 41 -#define SH_MD_DQLP_MMR_XBIST_ERR_H_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_XBIST_ERR_L" */ -/* falling edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_XBIST_ERR_L 0x0000000100038030 -#define SH_MD_DQLP_MMR_XBIST_ERR_L_MASK 0x00000300ffffffff -#define SH_MD_DQLP_MMR_XBIST_ERR_L_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_XBIST_ERR_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLP_MMR_XBIST_ERR_L_PAT_SHFT 0 -#define SH_MD_DQLP_MMR_XBIST_ERR_L_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQLP_MMR_XBIST_ERR_L_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQLP_MMR_XBIST_ERR_L_VAL_SHFT 40 -#define SH_MD_DQLP_MMR_XBIST_ERR_L_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQLP_MMR_XBIST_ERR_L_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQLP_MMR_XBIST_ERR_L_MORE_SHFT 41 -#define SH_MD_DQLP_MMR_XBIST_ERR_L_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YBIST_H" */ -/* rising edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_YBIST_H 0x0000000100038800 -#define SH_MD_DQLP_MMR_YBIST_H_MASK 0x00000700ffffffff -#define SH_MD_DQLP_MMR_YBIST_H_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_YBIST_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLP_MMR_YBIST_H_PAT_SHFT 0 -#define SH_MD_DQLP_MMR_YBIST_H_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQLP_MMR_YBIST_H_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQLP_MMR_YBIST_H_INV_SHFT 40 -#define SH_MD_DQLP_MMR_YBIST_H_INV_MASK 0x0000010000000000 - -/* SH_MD_DQLP_MMR_YBIST_H_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQLP_MMR_YBIST_H_ROT_SHFT 41 -#define SH_MD_DQLP_MMR_YBIST_H_ROT_MASK 0x0000020000000000 - -/* SH_MD_DQLP_MMR_YBIST_H_ARM */ -/* Description: writing 1 arms data miscompare capture */ -#define SH_MD_DQLP_MMR_YBIST_H_ARM_SHFT 42 -#define SH_MD_DQLP_MMR_YBIST_H_ARM_MASK 0x0000040000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YBIST_L" */ -/* falling edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_YBIST_L 0x0000000100038810 -#define SH_MD_DQLP_MMR_YBIST_L_MASK 0x00000300ffffffff -#define SH_MD_DQLP_MMR_YBIST_L_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_YBIST_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLP_MMR_YBIST_L_PAT_SHFT 0 -#define SH_MD_DQLP_MMR_YBIST_L_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQLP_MMR_YBIST_L_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQLP_MMR_YBIST_L_INV_SHFT 40 -#define SH_MD_DQLP_MMR_YBIST_L_INV_MASK 0x0000010000000000 - -/* SH_MD_DQLP_MMR_YBIST_L_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQLP_MMR_YBIST_L_ROT_SHFT 41 -#define SH_MD_DQLP_MMR_YBIST_L_ROT_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YBIST_ERR_H" */ -/* rising edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_YBIST_ERR_H 0x0000000100038820 -#define SH_MD_DQLP_MMR_YBIST_ERR_H_MASK 0x00000300ffffffff -#define SH_MD_DQLP_MMR_YBIST_ERR_H_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_YBIST_ERR_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLP_MMR_YBIST_ERR_H_PAT_SHFT 0 -#define SH_MD_DQLP_MMR_YBIST_ERR_H_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQLP_MMR_YBIST_ERR_H_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQLP_MMR_YBIST_ERR_H_VAL_SHFT 40 -#define SH_MD_DQLP_MMR_YBIST_ERR_H_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQLP_MMR_YBIST_ERR_H_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQLP_MMR_YBIST_ERR_H_MORE_SHFT 41 -#define SH_MD_DQLP_MMR_YBIST_ERR_H_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLP_MMR_YBIST_ERR_L" */ -/* falling edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLP_MMR_YBIST_ERR_L 0x0000000100038830 -#define SH_MD_DQLP_MMR_YBIST_ERR_L_MASK 0x00000300ffffffff -#define SH_MD_DQLP_MMR_YBIST_ERR_L_INIT 0x0000000000000000 - -/* SH_MD_DQLP_MMR_YBIST_ERR_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLP_MMR_YBIST_ERR_L_PAT_SHFT 0 -#define SH_MD_DQLP_MMR_YBIST_ERR_L_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQLP_MMR_YBIST_ERR_L_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQLP_MMR_YBIST_ERR_L_VAL_SHFT 40 -#define SH_MD_DQLP_MMR_YBIST_ERR_L_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQLP_MMR_YBIST_ERR_L_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQLP_MMR_YBIST_ERR_L_MORE_SHFT 41 -#define SH_MD_DQLP_MMR_YBIST_ERR_L_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLS_MMR_XBIST_H" */ -/* rising edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLS_MMR_XBIST_H 0x0000000100048000 -#define SH_MD_DQLS_MMR_XBIST_H_MASK 0x000007ffffffffff -#define SH_MD_DQLS_MMR_XBIST_H_INIT 0x0000000000000000 - -/* SH_MD_DQLS_MMR_XBIST_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLS_MMR_XBIST_H_PAT_SHFT 0 -#define SH_MD_DQLS_MMR_XBIST_H_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQLS_MMR_XBIST_H_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQLS_MMR_XBIST_H_INV_SHFT 40 -#define SH_MD_DQLS_MMR_XBIST_H_INV_MASK 0x0000010000000000 - -/* SH_MD_DQLS_MMR_XBIST_H_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQLS_MMR_XBIST_H_ROT_SHFT 41 -#define SH_MD_DQLS_MMR_XBIST_H_ROT_MASK 0x0000020000000000 - -/* SH_MD_DQLS_MMR_XBIST_H_ARM */ -/* Description: writing 1 arms data miscompare capture */ -#define SH_MD_DQLS_MMR_XBIST_H_ARM_SHFT 42 -#define SH_MD_DQLS_MMR_XBIST_H_ARM_MASK 0x0000040000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLS_MMR_XBIST_L" */ -/* falling edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLS_MMR_XBIST_L 0x0000000100048010 -#define SH_MD_DQLS_MMR_XBIST_L_MASK 0x000003ffffffffff -#define SH_MD_DQLS_MMR_XBIST_L_INIT 0x0000000000000000 - -/* SH_MD_DQLS_MMR_XBIST_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLS_MMR_XBIST_L_PAT_SHFT 0 -#define SH_MD_DQLS_MMR_XBIST_L_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQLS_MMR_XBIST_L_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQLS_MMR_XBIST_L_INV_SHFT 40 -#define SH_MD_DQLS_MMR_XBIST_L_INV_MASK 0x0000010000000000 - -/* SH_MD_DQLS_MMR_XBIST_L_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQLS_MMR_XBIST_L_ROT_SHFT 41 -#define SH_MD_DQLS_MMR_XBIST_L_ROT_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLS_MMR_XBIST_ERR_H" */ -/* rising edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLS_MMR_XBIST_ERR_H 0x0000000100048020 -#define SH_MD_DQLS_MMR_XBIST_ERR_H_MASK 0x000003ffffffffff -#define SH_MD_DQLS_MMR_XBIST_ERR_H_INIT 0x0000000000000000 - -/* SH_MD_DQLS_MMR_XBIST_ERR_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLS_MMR_XBIST_ERR_H_PAT_SHFT 0 -#define SH_MD_DQLS_MMR_XBIST_ERR_H_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQLS_MMR_XBIST_ERR_H_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQLS_MMR_XBIST_ERR_H_VAL_SHFT 40 -#define SH_MD_DQLS_MMR_XBIST_ERR_H_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQLS_MMR_XBIST_ERR_H_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQLS_MMR_XBIST_ERR_H_MORE_SHFT 41 -#define SH_MD_DQLS_MMR_XBIST_ERR_H_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLS_MMR_XBIST_ERR_L" */ -/* falling edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLS_MMR_XBIST_ERR_L 0x0000000100048030 -#define SH_MD_DQLS_MMR_XBIST_ERR_L_MASK 0x000003ffffffffff -#define SH_MD_DQLS_MMR_XBIST_ERR_L_INIT 0x0000000000000000 - -/* SH_MD_DQLS_MMR_XBIST_ERR_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLS_MMR_XBIST_ERR_L_PAT_SHFT 0 -#define SH_MD_DQLS_MMR_XBIST_ERR_L_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQLS_MMR_XBIST_ERR_L_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQLS_MMR_XBIST_ERR_L_VAL_SHFT 40 -#define SH_MD_DQLS_MMR_XBIST_ERR_L_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQLS_MMR_XBIST_ERR_L_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQLS_MMR_XBIST_ERR_L_MORE_SHFT 41 -#define SH_MD_DQLS_MMR_XBIST_ERR_L_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLS_MMR_YBIST_H" */ -/* rising edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLS_MMR_YBIST_H 0x0000000100048800 -#define SH_MD_DQLS_MMR_YBIST_H_MASK 0x000007ffffffffff -#define SH_MD_DQLS_MMR_YBIST_H_INIT 0x0000000000000000 - -/* SH_MD_DQLS_MMR_YBIST_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLS_MMR_YBIST_H_PAT_SHFT 0 -#define SH_MD_DQLS_MMR_YBIST_H_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQLS_MMR_YBIST_H_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQLS_MMR_YBIST_H_INV_SHFT 40 -#define SH_MD_DQLS_MMR_YBIST_H_INV_MASK 0x0000010000000000 - -/* SH_MD_DQLS_MMR_YBIST_H_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQLS_MMR_YBIST_H_ROT_SHFT 41 -#define SH_MD_DQLS_MMR_YBIST_H_ROT_MASK 0x0000020000000000 - -/* SH_MD_DQLS_MMR_YBIST_H_ARM */ -/* Description: writing 1 arms data miscompare capture */ -#define SH_MD_DQLS_MMR_YBIST_H_ARM_SHFT 42 -#define SH_MD_DQLS_MMR_YBIST_H_ARM_MASK 0x0000040000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLS_MMR_YBIST_L" */ -/* falling edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLS_MMR_YBIST_L 0x0000000100048810 -#define SH_MD_DQLS_MMR_YBIST_L_MASK 0x000003ffffffffff -#define SH_MD_DQLS_MMR_YBIST_L_INIT 0x0000000000000000 - -/* SH_MD_DQLS_MMR_YBIST_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLS_MMR_YBIST_L_PAT_SHFT 0 -#define SH_MD_DQLS_MMR_YBIST_L_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQLS_MMR_YBIST_L_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQLS_MMR_YBIST_L_INV_SHFT 40 -#define SH_MD_DQLS_MMR_YBIST_L_INV_MASK 0x0000010000000000 - -/* SH_MD_DQLS_MMR_YBIST_L_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQLS_MMR_YBIST_L_ROT_SHFT 41 -#define SH_MD_DQLS_MMR_YBIST_L_ROT_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLS_MMR_YBIST_ERR_H" */ -/* rising edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLS_MMR_YBIST_ERR_H 0x0000000100048820 -#define SH_MD_DQLS_MMR_YBIST_ERR_H_MASK 0x000003ffffffffff -#define SH_MD_DQLS_MMR_YBIST_ERR_H_INIT 0x0000000000000000 - -/* SH_MD_DQLS_MMR_YBIST_ERR_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLS_MMR_YBIST_ERR_H_PAT_SHFT 0 -#define SH_MD_DQLS_MMR_YBIST_ERR_H_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQLS_MMR_YBIST_ERR_H_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQLS_MMR_YBIST_ERR_H_VAL_SHFT 40 -#define SH_MD_DQLS_MMR_YBIST_ERR_H_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQLS_MMR_YBIST_ERR_H_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQLS_MMR_YBIST_ERR_H_MORE_SHFT 41 -#define SH_MD_DQLS_MMR_YBIST_ERR_H_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLS_MMR_YBIST_ERR_L" */ -/* falling edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQLS_MMR_YBIST_ERR_L 0x0000000100048830 -#define SH_MD_DQLS_MMR_YBIST_ERR_L_MASK 0x000003ffffffffff -#define SH_MD_DQLS_MMR_YBIST_ERR_L_INIT 0x0000000000000000 - -/* SH_MD_DQLS_MMR_YBIST_ERR_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQLS_MMR_YBIST_ERR_L_PAT_SHFT 0 -#define SH_MD_DQLS_MMR_YBIST_ERR_L_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQLS_MMR_YBIST_ERR_L_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQLS_MMR_YBIST_ERR_L_VAL_SHFT 40 -#define SH_MD_DQLS_MMR_YBIST_ERR_L_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQLS_MMR_YBIST_ERR_L_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQLS_MMR_YBIST_ERR_L_MORE_SHFT 41 -#define SH_MD_DQLS_MMR_YBIST_ERR_L_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQLS_MMR_JNR_DEBUG" */ -/* joiner/fct debug configuration */ -/* ==================================================================== */ - -#define SH_MD_DQLS_MMR_JNR_DEBUG 0x0000000100049000 -#define SH_MD_DQLS_MMR_JNR_DEBUG_MASK 0x0000000000000003 -#define SH_MD_DQLS_MMR_JNR_DEBUG_INIT 0x0000000000000000 - -/* SH_MD_DQLS_MMR_JNR_DEBUG_PX */ -/* Description: select 0=pi 1=xn side */ -#define SH_MD_DQLS_MMR_JNR_DEBUG_PX_SHFT 0 -#define SH_MD_DQLS_MMR_JNR_DEBUG_PX_MASK 0x0000000000000001 - -/* SH_MD_DQLS_MMR_JNR_DEBUG_RW */ -/* Description: select 0=read 1=write side */ -#define SH_MD_DQLS_MMR_JNR_DEBUG_RW_SHFT 1 -#define SH_MD_DQLS_MMR_JNR_DEBUG_RW_MASK 0x0000000000000002 - -/* ==================================================================== */ -/* Register "SH_MD_DQLS_MMR_XAMOPW_ERR" */ -/* amo/partial rmw ecc error register */ -/* ==================================================================== */ - -#define SH_MD_DQLS_MMR_XAMOPW_ERR 0x000000010004a000 -#define SH_MD_DQLS_MMR_XAMOPW_ERR_MASK 0x0000000103ff03ff -#define SH_MD_DQLS_MMR_XAMOPW_ERR_INIT 0x0000000000000000 - -/* SH_MD_DQLS_MMR_XAMOPW_ERR_SSYN */ -/* Description: store data syndrome */ -#define SH_MD_DQLS_MMR_XAMOPW_ERR_SSYN_SHFT 0 -#define SH_MD_DQLS_MMR_XAMOPW_ERR_SSYN_MASK 0x00000000000000ff - -/* SH_MD_DQLS_MMR_XAMOPW_ERR_SCOR */ -/* Description: correctable ecc errror on store data */ -#define SH_MD_DQLS_MMR_XAMOPW_ERR_SCOR_SHFT 8 -#define SH_MD_DQLS_MMR_XAMOPW_ERR_SCOR_MASK 0x0000000000000100 - -/* SH_MD_DQLS_MMR_XAMOPW_ERR_SUNC */ -/* Description: uncorrectable ecc errror on store data */ -#define SH_MD_DQLS_MMR_XAMOPW_ERR_SUNC_SHFT 9 -#define SH_MD_DQLS_MMR_XAMOPW_ERR_SUNC_MASK 0x0000000000000200 - -/* SH_MD_DQLS_MMR_XAMOPW_ERR_RSYN */ -/* Description: memory read data syndrome */ -#define SH_MD_DQLS_MMR_XAMOPW_ERR_RSYN_SHFT 16 -#define SH_MD_DQLS_MMR_XAMOPW_ERR_RSYN_MASK 0x0000000000ff0000 - -/* SH_MD_DQLS_MMR_XAMOPW_ERR_RCOR */ -/* Description: correctable ecc errror on read data */ -#define SH_MD_DQLS_MMR_XAMOPW_ERR_RCOR_SHFT 24 -#define SH_MD_DQLS_MMR_XAMOPW_ERR_RCOR_MASK 0x0000000001000000 - -/* SH_MD_DQLS_MMR_XAMOPW_ERR_RUNC */ -/* Description: uncorrectable ecc errror on read data */ -#define SH_MD_DQLS_MMR_XAMOPW_ERR_RUNC_SHFT 25 -#define SH_MD_DQLS_MMR_XAMOPW_ERR_RUNC_MASK 0x0000000002000000 - -/* SH_MD_DQLS_MMR_XAMOPW_ERR_ARM */ -/* Description: writing 1 arms ecc error capture */ -#define SH_MD_DQLS_MMR_XAMOPW_ERR_ARM_SHFT 32 -#define SH_MD_DQLS_MMR_XAMOPW_ERR_ARM_MASK 0x0000000100000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_CONFIG" */ -/* DQ directory config register */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_CONFIG 0x0000000100050000 -#define SH_MD_DQRP_MMR_DIR_CONFIG_MASK 0x000000000000001f -#define SH_MD_DQRP_MMR_DIR_CONFIG_INIT 0x0000000000000010 - -/* SH_MD_DQRP_MMR_DIR_CONFIG_SYS_SIZE */ -/* Description: system size code */ -#define SH_MD_DQRP_MMR_DIR_CONFIG_SYS_SIZE_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_CONFIG_SYS_SIZE_MASK 0x0000000000000007 - -/* SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRECC */ -/* Description: enable directory ecc correction */ -#define SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRECC_SHFT 3 -#define SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRECC_MASK 0x0000000000000008 - -/* SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRPOIS */ -/* Description: enable local poisoning for dir table fall-through */ -#define SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRPOIS_SHFT 4 -#define SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRPOIS_MASK 0x0000000000000010 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRESVEC0" */ -/* node [63:0] presence bits */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_PRESVEC0 0x0000000100050100 -#define SH_MD_DQRP_MMR_DIR_PRESVEC0_MASK 0xffffffffffffffff -#define SH_MD_DQRP_MMR_DIR_PRESVEC0_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_PRESVEC0_VEC */ -/* Description: node presence bits, 1=present */ -#define SH_MD_DQRP_MMR_DIR_PRESVEC0_VEC_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_PRESVEC0_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRESVEC1" */ -/* node [127:64] presence bits */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_PRESVEC1 0x0000000100050110 -#define SH_MD_DQRP_MMR_DIR_PRESVEC1_MASK 0xffffffffffffffff -#define SH_MD_DQRP_MMR_DIR_PRESVEC1_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_PRESVEC1_VEC */ -/* Description: node presence bits, 1=present */ -#define SH_MD_DQRP_MMR_DIR_PRESVEC1_VEC_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_PRESVEC1_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRESVEC2" */ -/* node [191:128] presence bits */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_PRESVEC2 0x0000000100050120 -#define SH_MD_DQRP_MMR_DIR_PRESVEC2_MASK 0xffffffffffffffff -#define SH_MD_DQRP_MMR_DIR_PRESVEC2_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_PRESVEC2_VEC */ -/* Description: node presence bits, 1=present */ -#define SH_MD_DQRP_MMR_DIR_PRESVEC2_VEC_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_PRESVEC2_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRESVEC3" */ -/* node [255:192] presence bits */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_PRESVEC3 0x0000000100050130 -#define SH_MD_DQRP_MMR_DIR_PRESVEC3_MASK 0xffffffffffffffff -#define SH_MD_DQRP_MMR_DIR_PRESVEC3_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_PRESVEC3_VEC */ -/* Description: node presence bits, 1=present */ -#define SH_MD_DQRP_MMR_DIR_PRESVEC3_VEC_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_PRESVEC3_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC0" */ -/* local vector for acc=0 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_LOCVEC0 0x0000000100050200 -#define SH_MD_DQRP_MMR_DIR_LOCVEC0_MASK 0xffffffffffffffff -#define SH_MD_DQRP_MMR_DIR_LOCVEC0_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_LOCVEC0_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQRP_MMR_DIR_LOCVEC0_VEC_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_LOCVEC0_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC1" */ -/* local vector for acc=1 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_LOCVEC1 0x0000000100050210 -#define SH_MD_DQRP_MMR_DIR_LOCVEC1_MASK 0xffffffffffffffff -#define SH_MD_DQRP_MMR_DIR_LOCVEC1_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_LOCVEC1_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQRP_MMR_DIR_LOCVEC1_VEC_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_LOCVEC1_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC2" */ -/* local vector for acc=2 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_LOCVEC2 0x0000000100050220 -#define SH_MD_DQRP_MMR_DIR_LOCVEC2_MASK 0xffffffffffffffff -#define SH_MD_DQRP_MMR_DIR_LOCVEC2_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_LOCVEC2_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQRP_MMR_DIR_LOCVEC2_VEC_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_LOCVEC2_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC3" */ -/* local vector for acc=3 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_LOCVEC3 0x0000000100050230 -#define SH_MD_DQRP_MMR_DIR_LOCVEC3_MASK 0xffffffffffffffff -#define SH_MD_DQRP_MMR_DIR_LOCVEC3_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_LOCVEC3_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQRP_MMR_DIR_LOCVEC3_VEC_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_LOCVEC3_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC4" */ -/* local vector for acc=4 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_LOCVEC4 0x0000000100050240 -#define SH_MD_DQRP_MMR_DIR_LOCVEC4_MASK 0xffffffffffffffff -#define SH_MD_DQRP_MMR_DIR_LOCVEC4_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_LOCVEC4_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQRP_MMR_DIR_LOCVEC4_VEC_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_LOCVEC4_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC5" */ -/* local vector for acc=5 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_LOCVEC5 0x0000000100050250 -#define SH_MD_DQRP_MMR_DIR_LOCVEC5_MASK 0xffffffffffffffff -#define SH_MD_DQRP_MMR_DIR_LOCVEC5_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_LOCVEC5_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQRP_MMR_DIR_LOCVEC5_VEC_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_LOCVEC5_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC6" */ -/* local vector for acc=6 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_LOCVEC6 0x0000000100050260 -#define SH_MD_DQRP_MMR_DIR_LOCVEC6_MASK 0xffffffffffffffff -#define SH_MD_DQRP_MMR_DIR_LOCVEC6_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_LOCVEC6_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQRP_MMR_DIR_LOCVEC6_VEC_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_LOCVEC6_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC7" */ -/* local vector for acc=7 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_LOCVEC7 0x0000000100050270 -#define SH_MD_DQRP_MMR_DIR_LOCVEC7_MASK 0xffffffffffffffff -#define SH_MD_DQRP_MMR_DIR_LOCVEC7_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_LOCVEC7_VEC */ -/* Description: 1 node is local */ -#define SH_MD_DQRP_MMR_DIR_LOCVEC7_VEC_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_LOCVEC7_VEC_MASK 0xffffffffffffffff - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC0" */ -/* privilege vector for acc=0 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_PRIVEC0 0x0000000100050300 -#define SH_MD_DQRP_MMR_DIR_PRIVEC0_MASK 0x000000000fffffff -#define SH_MD_DQRP_MMR_DIR_PRIVEC0_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_PRIVEC0_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC0_IN_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_PRIVEC0_IN_MASK 0x0000000000003fff - -/* SH_MD_DQRP_MMR_DIR_PRIVEC0_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC0_OUT_SHFT 14 -#define SH_MD_DQRP_MMR_DIR_PRIVEC0_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC1" */ -/* privilege vector for acc=1 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_PRIVEC1 0x0000000100050310 -#define SH_MD_DQRP_MMR_DIR_PRIVEC1_MASK 0x000000000fffffff -#define SH_MD_DQRP_MMR_DIR_PRIVEC1_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_PRIVEC1_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC1_IN_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_PRIVEC1_IN_MASK 0x0000000000003fff - -/* SH_MD_DQRP_MMR_DIR_PRIVEC1_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC1_OUT_SHFT 14 -#define SH_MD_DQRP_MMR_DIR_PRIVEC1_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC2" */ -/* privilege vector for acc=2 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_PRIVEC2 0x0000000100050320 -#define SH_MD_DQRP_MMR_DIR_PRIVEC2_MASK 0x000000000fffffff -#define SH_MD_DQRP_MMR_DIR_PRIVEC2_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_PRIVEC2_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC2_IN_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_PRIVEC2_IN_MASK 0x0000000000003fff - -/* SH_MD_DQRP_MMR_DIR_PRIVEC2_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC2_OUT_SHFT 14 -#define SH_MD_DQRP_MMR_DIR_PRIVEC2_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC3" */ -/* privilege vector for acc=3 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_PRIVEC3 0x0000000100050330 -#define SH_MD_DQRP_MMR_DIR_PRIVEC3_MASK 0x000000000fffffff -#define SH_MD_DQRP_MMR_DIR_PRIVEC3_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_PRIVEC3_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC3_IN_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_PRIVEC3_IN_MASK 0x0000000000003fff - -/* SH_MD_DQRP_MMR_DIR_PRIVEC3_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC3_OUT_SHFT 14 -#define SH_MD_DQRP_MMR_DIR_PRIVEC3_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC4" */ -/* privilege vector for acc=4 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_PRIVEC4 0x0000000100050340 -#define SH_MD_DQRP_MMR_DIR_PRIVEC4_MASK 0x000000000fffffff -#define SH_MD_DQRP_MMR_DIR_PRIVEC4_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_PRIVEC4_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC4_IN_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_PRIVEC4_IN_MASK 0x0000000000003fff - -/* SH_MD_DQRP_MMR_DIR_PRIVEC4_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC4_OUT_SHFT 14 -#define SH_MD_DQRP_MMR_DIR_PRIVEC4_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC5" */ -/* privilege vector for acc=5 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_PRIVEC5 0x0000000100050350 -#define SH_MD_DQRP_MMR_DIR_PRIVEC5_MASK 0x000000000fffffff -#define SH_MD_DQRP_MMR_DIR_PRIVEC5_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_PRIVEC5_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC5_IN_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_PRIVEC5_IN_MASK 0x0000000000003fff - -/* SH_MD_DQRP_MMR_DIR_PRIVEC5_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC5_OUT_SHFT 14 -#define SH_MD_DQRP_MMR_DIR_PRIVEC5_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC6" */ -/* privilege vector for acc=6 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_PRIVEC6 0x0000000100050360 -#define SH_MD_DQRP_MMR_DIR_PRIVEC6_MASK 0x000000000fffffff -#define SH_MD_DQRP_MMR_DIR_PRIVEC6_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_PRIVEC6_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC6_IN_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_PRIVEC6_IN_MASK 0x0000000000003fff - -/* SH_MD_DQRP_MMR_DIR_PRIVEC6_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC6_OUT_SHFT 14 -#define SH_MD_DQRP_MMR_DIR_PRIVEC6_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC7" */ -/* privilege vector for acc=7 */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_PRIVEC7 0x0000000100050370 -#define SH_MD_DQRP_MMR_DIR_PRIVEC7_MASK 0x000000000fffffff -#define SH_MD_DQRP_MMR_DIR_PRIVEC7_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_PRIVEC7_IN */ -/* Description: in partition privileges, locvec bit=1 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC7_IN_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_PRIVEC7_IN_MASK 0x0000000000003fff - -/* SH_MD_DQRP_MMR_DIR_PRIVEC7_OUT */ -/* Description: out of partition privileges, locvec bit=0 */ -#define SH_MD_DQRP_MMR_DIR_PRIVEC7_OUT_SHFT 14 -#define SH_MD_DQRP_MMR_DIR_PRIVEC7_OUT_MASK 0x000000000fffc000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_TIMER" */ -/* MD SXRO timer */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_TIMER 0x0000000100050400 -#define SH_MD_DQRP_MMR_DIR_TIMER_MASK 0x00000000003fffff -#define SH_MD_DQRP_MMR_DIR_TIMER_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_TIMER_TIMER_DIV */ -/* Description: timer divide register */ -#define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_DIV_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_DIV_MASK 0x0000000000000fff - -/* SH_MD_DQRP_MMR_DIR_TIMER_TIMER_EN */ -/* Description: timer enable */ -#define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_EN_SHFT 12 -#define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_EN_MASK 0x0000000000001000 - -/* SH_MD_DQRP_MMR_DIR_TIMER_TIMER_CUR */ -/* Description: value of current timer */ -#define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_CUR_SHFT 13 -#define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_CUR_MASK 0x00000000003fe000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY" */ -/* directory pio write data */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY 0x0000000100051000 -#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_MASK 0x03ffffffffffffff -#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRA */ -/* Description: directory entry A */ -#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRA_SHFT 0 -#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRA_MASK 0x0000000003ffffff - -/* SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRB */ -/* Description: directory entry B */ -#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRB_SHFT 26 -#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRB_MASK 0x000ffffffc000000 - -/* SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_PRI */ -/* Description: directory priority */ -#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_PRI_SHFT 52 -#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_PRI_MASK 0x0070000000000000 - -/* SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_ACC */ -/* Description: directory access bits */ -#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_ACC_SHFT 55 -#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_ACC_MASK 0x0380000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_PIOWD_DIR_ECC" */ -/* directory ecc register */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC 0x0000000100051010 -#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_MASK 0x0000000000003fff -#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCA */ -/* Description: XOR bits for directory ECC group 1 */ -#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCA_SHFT 0 -#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCA_MASK 0x000000000000007f - -/* SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCB */ -/* Description: XOR bits for directory ECC group 2 */ -#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCB_SHFT 7 -#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCB_MASK 0x0000000000003f80 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY" */ -/* x directory pio read data */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY 0x0000000100052000 -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_MASK 0x0fffffffffffffff -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRA */ -/* Description: directory entry A */ -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRA_SHFT 0 -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRA_MASK 0x0000000003ffffff - -/* SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRB */ -/* Description: directory entry B */ -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRB_SHFT 26 -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRB_MASK 0x000ffffffc000000 - -/* SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_PRI */ -/* Description: directory priority */ -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_PRI_SHFT 52 -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_PRI_MASK 0x0070000000000000 - -/* SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_ACC */ -/* Description: directory access bits */ -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_ACC_SHFT 55 -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_ACC_MASK 0x0380000000000000 - -/* SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_COR */ -/* Description: correctable ecc error */ -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_COR_SHFT 58 -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_COR_MASK 0x0400000000000000 - -/* SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_UNC */ -/* Description: uncorrectable ecc error */ -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_UNC_SHFT 59 -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_UNC_MASK 0x0800000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XPIORD_XDIR_ECC" */ -/* x directory ecc */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC 0x0000000100052010 -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_MASK 0x0000000000003fff -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCA */ -/* Description: group 1 ecc */ -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCA_SHFT 0 -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCA_MASK 0x000000000000007f - -/* SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCB */ -/* Description: group 2 ecc */ -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCB_SHFT 7 -#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCB_MASK 0x0000000000003f80 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY" */ -/* y directory pio read data */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY 0x0000000100052800 -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_MASK 0x0fffffffffffffff -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRA */ -/* Description: directory entry A */ -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRA_SHFT 0 -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRA_MASK 0x0000000003ffffff - -/* SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRB */ -/* Description: directory entry B */ -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRB_SHFT 26 -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRB_MASK 0x000ffffffc000000 - -/* SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_PRI */ -/* Description: directory priority */ -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_PRI_SHFT 52 -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_PRI_MASK 0x0070000000000000 - -/* SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_ACC */ -/* Description: directory access bits */ -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_ACC_SHFT 55 -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_ACC_MASK 0x0380000000000000 - -/* SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_COR */ -/* Description: correctable ecc error */ -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_COR_SHFT 58 -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_COR_MASK 0x0400000000000000 - -/* SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_UNC */ -/* Description: uncorrectable ecc error */ -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_UNC_SHFT 59 -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_UNC_MASK 0x0800000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YPIORD_YDIR_ECC" */ -/* y directory ecc */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC 0x0000000100052810 -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_MASK 0x0000000000003fff -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCA */ -/* Description: group 1 ecc */ -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCA_SHFT 0 -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCA_MASK 0x000000000000007f - -/* SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCB */ -/* Description: group 2 ecc */ -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCB_SHFT 7 -#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCB_MASK 0x0000000000003f80 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XCERR1" */ -/* correctable dir ecc group 1 error register */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_XCERR1 0x0000000100053000 -#define SH_MD_DQRP_MMR_XCERR1_MASK 0x0000007fffffffff -#define SH_MD_DQRP_MMR_XCERR1_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_XCERR1_GRP1 */ -/* Description: ecc group 1 bits */ -#define SH_MD_DQRP_MMR_XCERR1_GRP1_SHFT 0 -#define SH_MD_DQRP_MMR_XCERR1_GRP1_MASK 0x0000000fffffffff - -/* SH_MD_DQRP_MMR_XCERR1_VAL */ -/* Description: correctable ecc error in group 1 bits */ -#define SH_MD_DQRP_MMR_XCERR1_VAL_SHFT 36 -#define SH_MD_DQRP_MMR_XCERR1_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQRP_MMR_XCERR1_MORE */ -/* Description: more than one correctable ecc error in group 1 */ -#define SH_MD_DQRP_MMR_XCERR1_MORE_SHFT 37 -#define SH_MD_DQRP_MMR_XCERR1_MORE_MASK 0x0000002000000000 - -/* SH_MD_DQRP_MMR_XCERR1_ARM */ -/* Description: writing 1 arms uncorrectable ecc error capture */ -#define SH_MD_DQRP_MMR_XCERR1_ARM_SHFT 38 -#define SH_MD_DQRP_MMR_XCERR1_ARM_MASK 0x0000004000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XCERR2" */ -/* correctable dir ecc group 2 error register */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_XCERR2 0x0000000100053010 -#define SH_MD_DQRP_MMR_XCERR2_MASK 0x0000003fffffffff -#define SH_MD_DQRP_MMR_XCERR2_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_XCERR2_GRP2 */ -/* Description: ecc group 2 bits */ -#define SH_MD_DQRP_MMR_XCERR2_GRP2_SHFT 0 -#define SH_MD_DQRP_MMR_XCERR2_GRP2_MASK 0x0000000fffffffff - -/* SH_MD_DQRP_MMR_XCERR2_VAL */ -/* Description: correctable ecc error in group 2 bits */ -#define SH_MD_DQRP_MMR_XCERR2_VAL_SHFT 36 -#define SH_MD_DQRP_MMR_XCERR2_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQRP_MMR_XCERR2_MORE */ -/* Description: more than one correctable ecc error in group 2 */ -#define SH_MD_DQRP_MMR_XCERR2_MORE_SHFT 37 -#define SH_MD_DQRP_MMR_XCERR2_MORE_MASK 0x0000002000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XUERR1" */ -/* uncorrectable dir ecc group 1 error register */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_XUERR1 0x0000000100053020 -#define SH_MD_DQRP_MMR_XUERR1_MASK 0x0000007fffffffff -#define SH_MD_DQRP_MMR_XUERR1_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_XUERR1_GRP1 */ -/* Description: ecc group 1 bits */ -#define SH_MD_DQRP_MMR_XUERR1_GRP1_SHFT 0 -#define SH_MD_DQRP_MMR_XUERR1_GRP1_MASK 0x0000000fffffffff - -/* SH_MD_DQRP_MMR_XUERR1_VAL */ -/* Description: uncorrectable ecc error in group 1 bits */ -#define SH_MD_DQRP_MMR_XUERR1_VAL_SHFT 36 -#define SH_MD_DQRP_MMR_XUERR1_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQRP_MMR_XUERR1_MORE */ -/* Description: more than one uncorrectable ecc error in group 1 */ -#define SH_MD_DQRP_MMR_XUERR1_MORE_SHFT 37 -#define SH_MD_DQRP_MMR_XUERR1_MORE_MASK 0x0000002000000000 - -/* SH_MD_DQRP_MMR_XUERR1_ARM */ -/* Description: writing 1 arms uncorrectable ecc error capture */ -#define SH_MD_DQRP_MMR_XUERR1_ARM_SHFT 38 -#define SH_MD_DQRP_MMR_XUERR1_ARM_MASK 0x0000004000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XUERR2" */ -/* uncorrectable dir ecc group 2 error register */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_XUERR2 0x0000000100053030 -#define SH_MD_DQRP_MMR_XUERR2_MASK 0x0000003fffffffff -#define SH_MD_DQRP_MMR_XUERR2_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_XUERR2_GRP2 */ -/* Description: ecc group 2 bits */ -#define SH_MD_DQRP_MMR_XUERR2_GRP2_SHFT 0 -#define SH_MD_DQRP_MMR_XUERR2_GRP2_MASK 0x0000000fffffffff - -/* SH_MD_DQRP_MMR_XUERR2_VAL */ -/* Description: uncorrectable ecc error in group 2 bits */ -#define SH_MD_DQRP_MMR_XUERR2_VAL_SHFT 36 -#define SH_MD_DQRP_MMR_XUERR2_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQRP_MMR_XUERR2_MORE */ -/* Description: more than one uncorrectable ecc error in group 2 */ -#define SH_MD_DQRP_MMR_XUERR2_MORE_SHFT 37 -#define SH_MD_DQRP_MMR_XUERR2_MORE_MASK 0x0000002000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XPERR" */ -/* protocol error register */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_XPERR 0x0000000100053040 -#define SH_MD_DQRP_MMR_XPERR_MASK 0x7fffffffffffffff -#define SH_MD_DQRP_MMR_XPERR_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_XPERR_DIR */ -/* Description: directory entry */ -#define SH_MD_DQRP_MMR_XPERR_DIR_SHFT 0 -#define SH_MD_DQRP_MMR_XPERR_DIR_MASK 0x0000000003ffffff - -/* SH_MD_DQRP_MMR_XPERR_CMD */ -/* Description: incoming command */ -#define SH_MD_DQRP_MMR_XPERR_CMD_SHFT 26 -#define SH_MD_DQRP_MMR_XPERR_CMD_MASK 0x00000003fc000000 - -/* SH_MD_DQRP_MMR_XPERR_SRC */ -/* Description: source node of dir operation */ -#define SH_MD_DQRP_MMR_XPERR_SRC_SHFT 34 -#define SH_MD_DQRP_MMR_XPERR_SRC_MASK 0x0000fffc00000000 - -/* SH_MD_DQRP_MMR_XPERR_PRIGE */ -/* Description: priority was greater-equal */ -#define SH_MD_DQRP_MMR_XPERR_PRIGE_SHFT 48 -#define SH_MD_DQRP_MMR_XPERR_PRIGE_MASK 0x0001000000000000 - -/* SH_MD_DQRP_MMR_XPERR_PRIV */ -/* Description: access privilege bit */ -#define SH_MD_DQRP_MMR_XPERR_PRIV_SHFT 49 -#define SH_MD_DQRP_MMR_XPERR_PRIV_MASK 0x0002000000000000 - -/* SH_MD_DQRP_MMR_XPERR_COR */ -/* Description: correctable ecc error */ -#define SH_MD_DQRP_MMR_XPERR_COR_SHFT 50 -#define SH_MD_DQRP_MMR_XPERR_COR_MASK 0x0004000000000000 - -/* SH_MD_DQRP_MMR_XPERR_UNC */ -/* Description: uncorrectable ecc error */ -#define SH_MD_DQRP_MMR_XPERR_UNC_SHFT 51 -#define SH_MD_DQRP_MMR_XPERR_UNC_MASK 0x0008000000000000 - -/* SH_MD_DQRP_MMR_XPERR_MYBIT */ -/* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */ -#define SH_MD_DQRP_MMR_XPERR_MYBIT_SHFT 52 -#define SH_MD_DQRP_MMR_XPERR_MYBIT_MASK 0x0ff0000000000000 - -/* SH_MD_DQRP_MMR_XPERR_VAL */ -/* Description: protocol error info valid */ -#define SH_MD_DQRP_MMR_XPERR_VAL_SHFT 60 -#define SH_MD_DQRP_MMR_XPERR_VAL_MASK 0x1000000000000000 - -/* SH_MD_DQRP_MMR_XPERR_MORE */ -/* Description: more than one protocol error */ -#define SH_MD_DQRP_MMR_XPERR_MORE_SHFT 61 -#define SH_MD_DQRP_MMR_XPERR_MORE_MASK 0x2000000000000000 - -/* SH_MD_DQRP_MMR_XPERR_ARM */ -/* Description: writing 1 arms error capture */ -#define SH_MD_DQRP_MMR_XPERR_ARM_SHFT 62 -#define SH_MD_DQRP_MMR_XPERR_ARM_MASK 0x4000000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YCERR1" */ -/* correctable dir ecc group 1 error register */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_YCERR1 0x0000000100053800 -#define SH_MD_DQRP_MMR_YCERR1_MASK 0x0000007fffffffff -#define SH_MD_DQRP_MMR_YCERR1_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_YCERR1_GRP1 */ -/* Description: ecc group 1 bits */ -#define SH_MD_DQRP_MMR_YCERR1_GRP1_SHFT 0 -#define SH_MD_DQRP_MMR_YCERR1_GRP1_MASK 0x0000000fffffffff - -/* SH_MD_DQRP_MMR_YCERR1_VAL */ -/* Description: correctable ecc error in group 1 bits */ -#define SH_MD_DQRP_MMR_YCERR1_VAL_SHFT 36 -#define SH_MD_DQRP_MMR_YCERR1_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQRP_MMR_YCERR1_MORE */ -/* Description: more than one correctable ecc error in group 1 */ -#define SH_MD_DQRP_MMR_YCERR1_MORE_SHFT 37 -#define SH_MD_DQRP_MMR_YCERR1_MORE_MASK 0x0000002000000000 - -/* SH_MD_DQRP_MMR_YCERR1_ARM */ -/* Description: writing 1 arms uncorrectable ecc error capture */ -#define SH_MD_DQRP_MMR_YCERR1_ARM_SHFT 38 -#define SH_MD_DQRP_MMR_YCERR1_ARM_MASK 0x0000004000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YCERR2" */ -/* correctable dir ecc group 2 error register */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_YCERR2 0x0000000100053810 -#define SH_MD_DQRP_MMR_YCERR2_MASK 0x0000003fffffffff -#define SH_MD_DQRP_MMR_YCERR2_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_YCERR2_GRP2 */ -/* Description: ecc group 2 bits */ -#define SH_MD_DQRP_MMR_YCERR2_GRP2_SHFT 0 -#define SH_MD_DQRP_MMR_YCERR2_GRP2_MASK 0x0000000fffffffff - -/* SH_MD_DQRP_MMR_YCERR2_VAL */ -/* Description: correctable ecc error in group 2 bits */ -#define SH_MD_DQRP_MMR_YCERR2_VAL_SHFT 36 -#define SH_MD_DQRP_MMR_YCERR2_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQRP_MMR_YCERR2_MORE */ -/* Description: more than one correctable ecc error in group 2 */ -#define SH_MD_DQRP_MMR_YCERR2_MORE_SHFT 37 -#define SH_MD_DQRP_MMR_YCERR2_MORE_MASK 0x0000002000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YUERR1" */ -/* uncorrectable dir ecc group 1 error register */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_YUERR1 0x0000000100053820 -#define SH_MD_DQRP_MMR_YUERR1_MASK 0x0000007fffffffff -#define SH_MD_DQRP_MMR_YUERR1_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_YUERR1_GRP1 */ -/* Description: ecc group 1 bits */ -#define SH_MD_DQRP_MMR_YUERR1_GRP1_SHFT 0 -#define SH_MD_DQRP_MMR_YUERR1_GRP1_MASK 0x0000000fffffffff - -/* SH_MD_DQRP_MMR_YUERR1_VAL */ -/* Description: uncorrectable ecc error in group 1 bits */ -#define SH_MD_DQRP_MMR_YUERR1_VAL_SHFT 36 -#define SH_MD_DQRP_MMR_YUERR1_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQRP_MMR_YUERR1_MORE */ -/* Description: more than one uncorrectable ecc error in group 1 */ -#define SH_MD_DQRP_MMR_YUERR1_MORE_SHFT 37 -#define SH_MD_DQRP_MMR_YUERR1_MORE_MASK 0x0000002000000000 - -/* SH_MD_DQRP_MMR_YUERR1_ARM */ -/* Description: writing 1 arms uncorrectable ecc error capture */ -#define SH_MD_DQRP_MMR_YUERR1_ARM_SHFT 38 -#define SH_MD_DQRP_MMR_YUERR1_ARM_MASK 0x0000004000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YUERR2" */ -/* uncorrectable dir ecc group 2 error register */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_YUERR2 0x0000000100053830 -#define SH_MD_DQRP_MMR_YUERR2_MASK 0x0000003fffffffff -#define SH_MD_DQRP_MMR_YUERR2_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_YUERR2_GRP2 */ -/* Description: ecc group 2 bits */ -#define SH_MD_DQRP_MMR_YUERR2_GRP2_SHFT 0 -#define SH_MD_DQRP_MMR_YUERR2_GRP2_MASK 0x0000000fffffffff - -/* SH_MD_DQRP_MMR_YUERR2_VAL */ -/* Description: uncorrectable ecc error in group 2 bits */ -#define SH_MD_DQRP_MMR_YUERR2_VAL_SHFT 36 -#define SH_MD_DQRP_MMR_YUERR2_VAL_MASK 0x0000001000000000 - -/* SH_MD_DQRP_MMR_YUERR2_MORE */ -/* Description: more than one uncorrectable ecc error in group 2 */ -#define SH_MD_DQRP_MMR_YUERR2_MORE_SHFT 37 -#define SH_MD_DQRP_MMR_YUERR2_MORE_MASK 0x0000002000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YPERR" */ -/* protocol error register */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_YPERR 0x0000000100053840 -#define SH_MD_DQRP_MMR_YPERR_MASK 0x7fffffffffffffff -#define SH_MD_DQRP_MMR_YPERR_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_YPERR_DIR */ -/* Description: directory entry */ -#define SH_MD_DQRP_MMR_YPERR_DIR_SHFT 0 -#define SH_MD_DQRP_MMR_YPERR_DIR_MASK 0x0000000003ffffff - -/* SH_MD_DQRP_MMR_YPERR_CMD */ -/* Description: incoming command */ -#define SH_MD_DQRP_MMR_YPERR_CMD_SHFT 26 -#define SH_MD_DQRP_MMR_YPERR_CMD_MASK 0x00000003fc000000 - -/* SH_MD_DQRP_MMR_YPERR_SRC */ -/* Description: source node of dir operation */ -#define SH_MD_DQRP_MMR_YPERR_SRC_SHFT 34 -#define SH_MD_DQRP_MMR_YPERR_SRC_MASK 0x0000fffc00000000 - -/* SH_MD_DQRP_MMR_YPERR_PRIGE */ -/* Description: priority was greater-equal */ -#define SH_MD_DQRP_MMR_YPERR_PRIGE_SHFT 48 -#define SH_MD_DQRP_MMR_YPERR_PRIGE_MASK 0x0001000000000000 - -/* SH_MD_DQRP_MMR_YPERR_PRIV */ -/* Description: access privilege bit */ -#define SH_MD_DQRP_MMR_YPERR_PRIV_SHFT 49 -#define SH_MD_DQRP_MMR_YPERR_PRIV_MASK 0x0002000000000000 - -/* SH_MD_DQRP_MMR_YPERR_COR */ -/* Description: correctable ecc error */ -#define SH_MD_DQRP_MMR_YPERR_COR_SHFT 50 -#define SH_MD_DQRP_MMR_YPERR_COR_MASK 0x0004000000000000 - -/* SH_MD_DQRP_MMR_YPERR_UNC */ -/* Description: uncorrectable ecc error */ -#define SH_MD_DQRP_MMR_YPERR_UNC_SHFT 51 -#define SH_MD_DQRP_MMR_YPERR_UNC_MASK 0x0008000000000000 - -/* SH_MD_DQRP_MMR_YPERR_MYBIT */ -/* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */ -#define SH_MD_DQRP_MMR_YPERR_MYBIT_SHFT 52 -#define SH_MD_DQRP_MMR_YPERR_MYBIT_MASK 0x0ff0000000000000 - -/* SH_MD_DQRP_MMR_YPERR_VAL */ -/* Description: protocol error info valid */ -#define SH_MD_DQRP_MMR_YPERR_VAL_SHFT 60 -#define SH_MD_DQRP_MMR_YPERR_VAL_MASK 0x1000000000000000 - -/* SH_MD_DQRP_MMR_YPERR_MORE */ -/* Description: more than one protocol error */ -#define SH_MD_DQRP_MMR_YPERR_MORE_SHFT 61 -#define SH_MD_DQRP_MMR_YPERR_MORE_MASK 0x2000000000000000 - -/* SH_MD_DQRP_MMR_YPERR_ARM */ -/* Description: writing 1 arms error capture */ -#define SH_MD_DQRP_MMR_YPERR_ARM_SHFT 62 -#define SH_MD_DQRP_MMR_YPERR_ARM_MASK 0x4000000000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_CMDTRIG" */ -/* cmd triggers */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_CMDTRIG 0x0000000100054000 -#define SH_MD_DQRP_MMR_DIR_CMDTRIG_MASK 0x00000000ffffffff -#define SH_MD_DQRP_MMR_DIR_CMDTRIG_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD0 */ -/* Description: command trigger 0 */ -#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD0_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD0_MASK 0x00000000000000ff - -/* SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD1 */ -/* Description: command trigger 1 */ -#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD1_SHFT 8 -#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD1_MASK 0x000000000000ff00 - -/* SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD2 */ -/* Description: command trigger 2 */ -#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD2_SHFT 16 -#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD2_MASK 0x0000000000ff0000 - -/* SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD3 */ -/* Description: command trigger 3 */ -#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD3_SHFT 24 -#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD3_MASK 0x00000000ff000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_TBLTRIG" */ -/* dir table trigger */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_TBLTRIG 0x0000000100054010 -#define SH_MD_DQRP_MMR_DIR_TBLTRIG_MASK 0x000003ffffffffff -#define SH_MD_DQRP_MMR_DIR_TBLTRIG_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_TBLTRIG_SRC */ -/* Description: source of request */ -#define SH_MD_DQRP_MMR_DIR_TBLTRIG_SRC_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_TBLTRIG_SRC_MASK 0x0000000000003fff - -/* SH_MD_DQRP_MMR_DIR_TBLTRIG_CMD */ -/* Description: incoming request */ -#define SH_MD_DQRP_MMR_DIR_TBLTRIG_CMD_SHFT 14 -#define SH_MD_DQRP_MMR_DIR_TBLTRIG_CMD_MASK 0x00000000003fc000 - -/* SH_MD_DQRP_MMR_DIR_TBLTRIG_ACC */ -/* Description: uncorrectable error, privilege bit */ -#define SH_MD_DQRP_MMR_DIR_TBLTRIG_ACC_SHFT 22 -#define SH_MD_DQRP_MMR_DIR_TBLTRIG_ACC_MASK 0x0000000000c00000 - -/* SH_MD_DQRP_MMR_DIR_TBLTRIG_PRIGE */ -/* Description: priority greater-equal */ -#define SH_MD_DQRP_MMR_DIR_TBLTRIG_PRIGE_SHFT 24 -#define SH_MD_DQRP_MMR_DIR_TBLTRIG_PRIGE_MASK 0x0000000001000000 - -/* SH_MD_DQRP_MMR_DIR_TBLTRIG_DIRST */ -/* Description: shrd,sxro,sub-state */ -#define SH_MD_DQRP_MMR_DIR_TBLTRIG_DIRST_SHFT 25 -#define SH_MD_DQRP_MMR_DIR_TBLTRIG_DIRST_MASK 0x00000003fe000000 - -/* SH_MD_DQRP_MMR_DIR_TBLTRIG_MYBIT */ -/* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */ -#define SH_MD_DQRP_MMR_DIR_TBLTRIG_MYBIT_SHFT 34 -#define SH_MD_DQRP_MMR_DIR_TBLTRIG_MYBIT_MASK 0x000003fc00000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_DIR_TBLMASK" */ -/* dir table trigger mask */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_DIR_TBLMASK 0x0000000100054020 -#define SH_MD_DQRP_MMR_DIR_TBLMASK_MASK 0x000003ffffffffff -#define SH_MD_DQRP_MMR_DIR_TBLMASK_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_DIR_TBLMASK_SRC */ -/* Description: source of request */ -#define SH_MD_DQRP_MMR_DIR_TBLMASK_SRC_SHFT 0 -#define SH_MD_DQRP_MMR_DIR_TBLMASK_SRC_MASK 0x0000000000003fff - -/* SH_MD_DQRP_MMR_DIR_TBLMASK_CMD */ -/* Description: incoming request */ -#define SH_MD_DQRP_MMR_DIR_TBLMASK_CMD_SHFT 14 -#define SH_MD_DQRP_MMR_DIR_TBLMASK_CMD_MASK 0x00000000003fc000 - -/* SH_MD_DQRP_MMR_DIR_TBLMASK_ACC */ -/* Description: uncorrectable error, privilege bit */ -#define SH_MD_DQRP_MMR_DIR_TBLMASK_ACC_SHFT 22 -#define SH_MD_DQRP_MMR_DIR_TBLMASK_ACC_MASK 0x0000000000c00000 - -/* SH_MD_DQRP_MMR_DIR_TBLMASK_PRIGE */ -/* Description: priority greater-equal */ -#define SH_MD_DQRP_MMR_DIR_TBLMASK_PRIGE_SHFT 24 -#define SH_MD_DQRP_MMR_DIR_TBLMASK_PRIGE_MASK 0x0000000001000000 - -/* SH_MD_DQRP_MMR_DIR_TBLMASK_DIRST */ -/* Description: shrd,sxro,sub-state */ -#define SH_MD_DQRP_MMR_DIR_TBLMASK_DIRST_SHFT 25 -#define SH_MD_DQRP_MMR_DIR_TBLMASK_DIRST_MASK 0x00000003fe000000 - -/* SH_MD_DQRP_MMR_DIR_TBLMASK_MYBIT */ -/* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */ -#define SH_MD_DQRP_MMR_DIR_TBLMASK_MYBIT_SHFT 34 -#define SH_MD_DQRP_MMR_DIR_TBLMASK_MYBIT_MASK 0x000003fc00000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XBIST_H" */ -/* rising edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_XBIST_H 0x0000000100058000 -#define SH_MD_DQRP_MMR_XBIST_H_MASK 0x00000700ffffffff -#define SH_MD_DQRP_MMR_XBIST_H_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_XBIST_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRP_MMR_XBIST_H_PAT_SHFT 0 -#define SH_MD_DQRP_MMR_XBIST_H_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQRP_MMR_XBIST_H_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQRP_MMR_XBIST_H_INV_SHFT 40 -#define SH_MD_DQRP_MMR_XBIST_H_INV_MASK 0x0000010000000000 - -/* SH_MD_DQRP_MMR_XBIST_H_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQRP_MMR_XBIST_H_ROT_SHFT 41 -#define SH_MD_DQRP_MMR_XBIST_H_ROT_MASK 0x0000020000000000 - -/* SH_MD_DQRP_MMR_XBIST_H_ARM */ -/* Description: writing 1 arms data miscompare capture */ -#define SH_MD_DQRP_MMR_XBIST_H_ARM_SHFT 42 -#define SH_MD_DQRP_MMR_XBIST_H_ARM_MASK 0x0000040000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XBIST_L" */ -/* falling edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_XBIST_L 0x0000000100058010 -#define SH_MD_DQRP_MMR_XBIST_L_MASK 0x00000300ffffffff -#define SH_MD_DQRP_MMR_XBIST_L_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_XBIST_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRP_MMR_XBIST_L_PAT_SHFT 0 -#define SH_MD_DQRP_MMR_XBIST_L_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQRP_MMR_XBIST_L_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQRP_MMR_XBIST_L_INV_SHFT 40 -#define SH_MD_DQRP_MMR_XBIST_L_INV_MASK 0x0000010000000000 - -/* SH_MD_DQRP_MMR_XBIST_L_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQRP_MMR_XBIST_L_ROT_SHFT 41 -#define SH_MD_DQRP_MMR_XBIST_L_ROT_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XBIST_ERR_H" */ -/* rising edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_XBIST_ERR_H 0x0000000100058020 -#define SH_MD_DQRP_MMR_XBIST_ERR_H_MASK 0x00000300ffffffff -#define SH_MD_DQRP_MMR_XBIST_ERR_H_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_XBIST_ERR_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRP_MMR_XBIST_ERR_H_PAT_SHFT 0 -#define SH_MD_DQRP_MMR_XBIST_ERR_H_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQRP_MMR_XBIST_ERR_H_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQRP_MMR_XBIST_ERR_H_VAL_SHFT 40 -#define SH_MD_DQRP_MMR_XBIST_ERR_H_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQRP_MMR_XBIST_ERR_H_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQRP_MMR_XBIST_ERR_H_MORE_SHFT 41 -#define SH_MD_DQRP_MMR_XBIST_ERR_H_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_XBIST_ERR_L" */ -/* falling edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_XBIST_ERR_L 0x0000000100058030 -#define SH_MD_DQRP_MMR_XBIST_ERR_L_MASK 0x00000300ffffffff -#define SH_MD_DQRP_MMR_XBIST_ERR_L_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_XBIST_ERR_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRP_MMR_XBIST_ERR_L_PAT_SHFT 0 -#define SH_MD_DQRP_MMR_XBIST_ERR_L_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQRP_MMR_XBIST_ERR_L_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQRP_MMR_XBIST_ERR_L_VAL_SHFT 40 -#define SH_MD_DQRP_MMR_XBIST_ERR_L_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQRP_MMR_XBIST_ERR_L_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQRP_MMR_XBIST_ERR_L_MORE_SHFT 41 -#define SH_MD_DQRP_MMR_XBIST_ERR_L_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YBIST_H" */ -/* rising edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_YBIST_H 0x0000000100058800 -#define SH_MD_DQRP_MMR_YBIST_H_MASK 0x00000700ffffffff -#define SH_MD_DQRP_MMR_YBIST_H_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_YBIST_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRP_MMR_YBIST_H_PAT_SHFT 0 -#define SH_MD_DQRP_MMR_YBIST_H_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQRP_MMR_YBIST_H_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQRP_MMR_YBIST_H_INV_SHFT 40 -#define SH_MD_DQRP_MMR_YBIST_H_INV_MASK 0x0000010000000000 - -/* SH_MD_DQRP_MMR_YBIST_H_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQRP_MMR_YBIST_H_ROT_SHFT 41 -#define SH_MD_DQRP_MMR_YBIST_H_ROT_MASK 0x0000020000000000 - -/* SH_MD_DQRP_MMR_YBIST_H_ARM */ -/* Description: writing 1 arms data miscompare capture */ -#define SH_MD_DQRP_MMR_YBIST_H_ARM_SHFT 42 -#define SH_MD_DQRP_MMR_YBIST_H_ARM_MASK 0x0000040000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YBIST_L" */ -/* falling edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_YBIST_L 0x0000000100058810 -#define SH_MD_DQRP_MMR_YBIST_L_MASK 0x00000300ffffffff -#define SH_MD_DQRP_MMR_YBIST_L_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_YBIST_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRP_MMR_YBIST_L_PAT_SHFT 0 -#define SH_MD_DQRP_MMR_YBIST_L_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQRP_MMR_YBIST_L_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQRP_MMR_YBIST_L_INV_SHFT 40 -#define SH_MD_DQRP_MMR_YBIST_L_INV_MASK 0x0000010000000000 - -/* SH_MD_DQRP_MMR_YBIST_L_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQRP_MMR_YBIST_L_ROT_SHFT 41 -#define SH_MD_DQRP_MMR_YBIST_L_ROT_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YBIST_ERR_H" */ -/* rising edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_YBIST_ERR_H 0x0000000100058820 -#define SH_MD_DQRP_MMR_YBIST_ERR_H_MASK 0x00000300ffffffff -#define SH_MD_DQRP_MMR_YBIST_ERR_H_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_YBIST_ERR_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRP_MMR_YBIST_ERR_H_PAT_SHFT 0 -#define SH_MD_DQRP_MMR_YBIST_ERR_H_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQRP_MMR_YBIST_ERR_H_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQRP_MMR_YBIST_ERR_H_VAL_SHFT 40 -#define SH_MD_DQRP_MMR_YBIST_ERR_H_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQRP_MMR_YBIST_ERR_H_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQRP_MMR_YBIST_ERR_H_MORE_SHFT 41 -#define SH_MD_DQRP_MMR_YBIST_ERR_H_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRP_MMR_YBIST_ERR_L" */ -/* falling edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRP_MMR_YBIST_ERR_L 0x0000000100058830 -#define SH_MD_DQRP_MMR_YBIST_ERR_L_MASK 0x00000300ffffffff -#define SH_MD_DQRP_MMR_YBIST_ERR_L_INIT 0x0000000000000000 - -/* SH_MD_DQRP_MMR_YBIST_ERR_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRP_MMR_YBIST_ERR_L_PAT_SHFT 0 -#define SH_MD_DQRP_MMR_YBIST_ERR_L_PAT_MASK 0x00000000ffffffff - -/* SH_MD_DQRP_MMR_YBIST_ERR_L_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQRP_MMR_YBIST_ERR_L_VAL_SHFT 40 -#define SH_MD_DQRP_MMR_YBIST_ERR_L_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQRP_MMR_YBIST_ERR_L_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQRP_MMR_YBIST_ERR_L_MORE_SHFT 41 -#define SH_MD_DQRP_MMR_YBIST_ERR_L_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRS_MMR_XBIST_H" */ -/* rising edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRS_MMR_XBIST_H 0x0000000100068000 -#define SH_MD_DQRS_MMR_XBIST_H_MASK 0x000007ffffffffff -#define SH_MD_DQRS_MMR_XBIST_H_INIT 0x0000000000000000 - -/* SH_MD_DQRS_MMR_XBIST_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRS_MMR_XBIST_H_PAT_SHFT 0 -#define SH_MD_DQRS_MMR_XBIST_H_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQRS_MMR_XBIST_H_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQRS_MMR_XBIST_H_INV_SHFT 40 -#define SH_MD_DQRS_MMR_XBIST_H_INV_MASK 0x0000010000000000 - -/* SH_MD_DQRS_MMR_XBIST_H_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQRS_MMR_XBIST_H_ROT_SHFT 41 -#define SH_MD_DQRS_MMR_XBIST_H_ROT_MASK 0x0000020000000000 - -/* SH_MD_DQRS_MMR_XBIST_H_ARM */ -/* Description: writing 1 arms data miscompare capture */ -#define SH_MD_DQRS_MMR_XBIST_H_ARM_SHFT 42 -#define SH_MD_DQRS_MMR_XBIST_H_ARM_MASK 0x0000040000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRS_MMR_XBIST_L" */ -/* falling edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRS_MMR_XBIST_L 0x0000000100068010 -#define SH_MD_DQRS_MMR_XBIST_L_MASK 0x000003ffffffffff -#define SH_MD_DQRS_MMR_XBIST_L_INIT 0x0000000000000000 - -/* SH_MD_DQRS_MMR_XBIST_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRS_MMR_XBIST_L_PAT_SHFT 0 -#define SH_MD_DQRS_MMR_XBIST_L_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQRS_MMR_XBIST_L_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQRS_MMR_XBIST_L_INV_SHFT 40 -#define SH_MD_DQRS_MMR_XBIST_L_INV_MASK 0x0000010000000000 - -/* SH_MD_DQRS_MMR_XBIST_L_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQRS_MMR_XBIST_L_ROT_SHFT 41 -#define SH_MD_DQRS_MMR_XBIST_L_ROT_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRS_MMR_XBIST_ERR_H" */ -/* rising edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRS_MMR_XBIST_ERR_H 0x0000000100068020 -#define SH_MD_DQRS_MMR_XBIST_ERR_H_MASK 0x000003ffffffffff -#define SH_MD_DQRS_MMR_XBIST_ERR_H_INIT 0x0000000000000000 - -/* SH_MD_DQRS_MMR_XBIST_ERR_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRS_MMR_XBIST_ERR_H_PAT_SHFT 0 -#define SH_MD_DQRS_MMR_XBIST_ERR_H_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQRS_MMR_XBIST_ERR_H_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQRS_MMR_XBIST_ERR_H_VAL_SHFT 40 -#define SH_MD_DQRS_MMR_XBIST_ERR_H_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQRS_MMR_XBIST_ERR_H_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQRS_MMR_XBIST_ERR_H_MORE_SHFT 41 -#define SH_MD_DQRS_MMR_XBIST_ERR_H_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRS_MMR_XBIST_ERR_L" */ -/* falling edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRS_MMR_XBIST_ERR_L 0x0000000100068030 -#define SH_MD_DQRS_MMR_XBIST_ERR_L_MASK 0x000003ffffffffff -#define SH_MD_DQRS_MMR_XBIST_ERR_L_INIT 0x0000000000000000 - -/* SH_MD_DQRS_MMR_XBIST_ERR_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRS_MMR_XBIST_ERR_L_PAT_SHFT 0 -#define SH_MD_DQRS_MMR_XBIST_ERR_L_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQRS_MMR_XBIST_ERR_L_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQRS_MMR_XBIST_ERR_L_VAL_SHFT 40 -#define SH_MD_DQRS_MMR_XBIST_ERR_L_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQRS_MMR_XBIST_ERR_L_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQRS_MMR_XBIST_ERR_L_MORE_SHFT 41 -#define SH_MD_DQRS_MMR_XBIST_ERR_L_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRS_MMR_YBIST_H" */ -/* rising edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRS_MMR_YBIST_H 0x0000000100068800 -#define SH_MD_DQRS_MMR_YBIST_H_MASK 0x000007ffffffffff -#define SH_MD_DQRS_MMR_YBIST_H_INIT 0x0000000000000000 - -/* SH_MD_DQRS_MMR_YBIST_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRS_MMR_YBIST_H_PAT_SHFT 0 -#define SH_MD_DQRS_MMR_YBIST_H_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQRS_MMR_YBIST_H_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQRS_MMR_YBIST_H_INV_SHFT 40 -#define SH_MD_DQRS_MMR_YBIST_H_INV_MASK 0x0000010000000000 - -/* SH_MD_DQRS_MMR_YBIST_H_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQRS_MMR_YBIST_H_ROT_SHFT 41 -#define SH_MD_DQRS_MMR_YBIST_H_ROT_MASK 0x0000020000000000 - -/* SH_MD_DQRS_MMR_YBIST_H_ARM */ -/* Description: writing 1 arms data miscompare capture */ -#define SH_MD_DQRS_MMR_YBIST_H_ARM_SHFT 42 -#define SH_MD_DQRS_MMR_YBIST_H_ARM_MASK 0x0000040000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRS_MMR_YBIST_L" */ -/* falling edge bist/fill pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRS_MMR_YBIST_L 0x0000000100068810 -#define SH_MD_DQRS_MMR_YBIST_L_MASK 0x000003ffffffffff -#define SH_MD_DQRS_MMR_YBIST_L_INIT 0x0000000000000000 - -/* SH_MD_DQRS_MMR_YBIST_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRS_MMR_YBIST_L_PAT_SHFT 0 -#define SH_MD_DQRS_MMR_YBIST_L_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQRS_MMR_YBIST_L_INV */ -/* Description: invert data pattern in next cycle */ -#define SH_MD_DQRS_MMR_YBIST_L_INV_SHFT 40 -#define SH_MD_DQRS_MMR_YBIST_L_INV_MASK 0x0000010000000000 - -/* SH_MD_DQRS_MMR_YBIST_L_ROT */ -/* Description: rotate left data pattern in next cycle */ -#define SH_MD_DQRS_MMR_YBIST_L_ROT_SHFT 41 -#define SH_MD_DQRS_MMR_YBIST_L_ROT_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRS_MMR_YBIST_ERR_H" */ -/* rising edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRS_MMR_YBIST_ERR_H 0x0000000100068820 -#define SH_MD_DQRS_MMR_YBIST_ERR_H_MASK 0x000003ffffffffff -#define SH_MD_DQRS_MMR_YBIST_ERR_H_INIT 0x0000000000000000 - -/* SH_MD_DQRS_MMR_YBIST_ERR_H_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRS_MMR_YBIST_ERR_H_PAT_SHFT 0 -#define SH_MD_DQRS_MMR_YBIST_ERR_H_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQRS_MMR_YBIST_ERR_H_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQRS_MMR_YBIST_ERR_H_VAL_SHFT 40 -#define SH_MD_DQRS_MMR_YBIST_ERR_H_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQRS_MMR_YBIST_ERR_H_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQRS_MMR_YBIST_ERR_H_MORE_SHFT 41 -#define SH_MD_DQRS_MMR_YBIST_ERR_H_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRS_MMR_YBIST_ERR_L" */ -/* falling edge bist error pattern */ -/* ==================================================================== */ - -#define SH_MD_DQRS_MMR_YBIST_ERR_L 0x0000000100068830 -#define SH_MD_DQRS_MMR_YBIST_ERR_L_MASK 0x000003ffffffffff -#define SH_MD_DQRS_MMR_YBIST_ERR_L_INIT 0x0000000000000000 - -/* SH_MD_DQRS_MMR_YBIST_ERR_L_PAT */ -/* Description: data pattern */ -#define SH_MD_DQRS_MMR_YBIST_ERR_L_PAT_SHFT 0 -#define SH_MD_DQRS_MMR_YBIST_ERR_L_PAT_MASK 0x000000ffffffffff - -/* SH_MD_DQRS_MMR_YBIST_ERR_L_VAL */ -/* Description: bist data miscompare */ -#define SH_MD_DQRS_MMR_YBIST_ERR_L_VAL_SHFT 40 -#define SH_MD_DQRS_MMR_YBIST_ERR_L_VAL_MASK 0x0000010000000000 - -/* SH_MD_DQRS_MMR_YBIST_ERR_L_MORE */ -/* Description: more than one bist data miscompare */ -#define SH_MD_DQRS_MMR_YBIST_ERR_L_MORE_SHFT 41 -#define SH_MD_DQRS_MMR_YBIST_ERR_L_MORE_MASK 0x0000020000000000 - -/* ==================================================================== */ -/* Register "SH_MD_DQRS_MMR_JNR_DEBUG" */ -/* joiner/fct debug configuration */ -/* ==================================================================== */ - -#define SH_MD_DQRS_MMR_JNR_DEBUG 0x0000000100069000 -#define SH_MD_DQRS_MMR_JNR_DEBUG_MASK 0x0000000000000003 -#define SH_MD_DQRS_MMR_JNR_DEBUG_INIT 0x0000000000000000 - -/* SH_MD_DQRS_MMR_JNR_DEBUG_PX */ -/* Description: select 0=pi 1=xn side */ -#define SH_MD_DQRS_MMR_JNR_DEBUG_PX_SHFT 0 -#define SH_MD_DQRS_MMR_JNR_DEBUG_PX_MASK 0x0000000000000001 - -/* SH_MD_DQRS_MMR_JNR_DEBUG_RW */ -/* Description: select 0=read 1=write side */ -#define SH_MD_DQRS_MMR_JNR_DEBUG_RW_SHFT 1 -#define SH_MD_DQRS_MMR_JNR_DEBUG_RW_MASK 0x0000000000000002 - -/* ==================================================================== */ -/* Register "SH_MD_DQRS_MMR_YAMOPW_ERR" */ -/* amo/partial rmw ecc error register */ -/* ==================================================================== */ - -#define SH_MD_DQRS_MMR_YAMOPW_ERR 0x000000010006a000 -#define SH_MD_DQRS_MMR_YAMOPW_ERR_MASK 0x0000000103ff03ff -#define SH_MD_DQRS_MMR_YAMOPW_ERR_INIT 0x0000000000000000 - -/* SH_MD_DQRS_MMR_YAMOPW_ERR_SSYN */ -/* Description: store data syndrome */ -#define SH_MD_DQRS_MMR_YAMOPW_ERR_SSYN_SHFT 0 -#define SH_MD_DQRS_MMR_YAMOPW_ERR_SSYN_MASK 0x00000000000000ff - -/* SH_MD_DQRS_MMR_YAMOPW_ERR_SCOR */ -/* Description: correctable ecc errror on store data */ -#define SH_MD_DQRS_MMR_YAMOPW_ERR_SCOR_SHFT 8 -#define SH_MD_DQRS_MMR_YAMOPW_ERR_SCOR_MASK 0x0000000000000100 - -/* SH_MD_DQRS_MMR_YAMOPW_ERR_SUNC */ -/* Description: uncorrectable ecc errror on store data */ -#define SH_MD_DQRS_MMR_YAMOPW_ERR_SUNC_SHFT 9 -#define SH_MD_DQRS_MMR_YAMOPW_ERR_SUNC_MASK 0x0000000000000200 - -/* SH_MD_DQRS_MMR_YAMOPW_ERR_RSYN */ -/* Description: memory read data syndrome */ -#define SH_MD_DQRS_MMR_YAMOPW_ERR_RSYN_SHFT 16 -#define SH_MD_DQRS_MMR_YAMOPW_ERR_RSYN_MASK 0x0000000000ff0000 - -/* SH_MD_DQRS_MMR_YAMOPW_ERR_RCOR */ -/* Description: correctable ecc errror on read data */ -#define SH_MD_DQRS_MMR_YAMOPW_ERR_RCOR_SHFT 24 -#define SH_MD_DQRS_MMR_YAMOPW_ERR_RCOR_MASK 0x0000000001000000 - -/* SH_MD_DQRS_MMR_YAMOPW_ERR_RUNC */ -/* Description: uncorrectable ecc errror on read data */ -#define SH_MD_DQRS_MMR_YAMOPW_ERR_RUNC_SHFT 25 -#define SH_MD_DQRS_MMR_YAMOPW_ERR_RUNC_MASK 0x0000000002000000 - -/* SH_MD_DQRS_MMR_YAMOPW_ERR_ARM */ -/* Description: writing 1 arms ecc error capture */ -#define SH_MD_DQRS_MMR_YAMOPW_ERR_ARM_SHFT 32 -#define SH_MD_DQRS_MMR_YAMOPW_ERR_ARM_MASK 0x0000000100000000 - - #endif /* _ASM_IA64_SN_SHUB_MMR_H */ diff --git a/include/asm-ia64/topology.h b/include/asm-ia64/topology.h index 1062f02b088e..5b0dd8cc6bd4 100644 --- a/include/asm-ia64/topology.h +++ b/include/asm-ia64/topology.h @@ -58,7 +58,26 @@ void build_cpu_to_node_map(void); | SD_BALANCE_EXEC \ | SD_WAKE_BALANCE, \ .last_balance = jiffies, \ - .balance_interval = 10, \ + .balance_interval = 1, \ + .nr_balance_failed = 0, \ +} + +/* sched_domains SD_ALLNODES_INIT for IA64 NUMA machines */ +#define SD_ALLNODES_INIT (struct sched_domain) { \ + .span = CPU_MASK_NONE, \ + .parent = NULL, \ + .groups = NULL, \ + .min_interval = 80, \ + .max_interval = 320, \ + .busy_factor = 320, \ + .imbalance_pct = 125, \ + .cache_hot_time = (10*1000000), \ + .cache_nice_tries = 1, \ + .per_cpu_gain = 100, \ + .flags = SD_LOAD_BALANCE \ + | SD_BALANCE_EXEC, \ + .last_balance = jiffies, \ + .balance_interval = 100*(63+num_online_cpus())/64, \ .nr_balance_failed = 0, \ } |