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| author | Brett Creeley <brett.creeley@intel.com> | 2019-11-08 06:23:23 -0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2019-12-31 16:45:47 +0100 |
| commit | 3e3e341d1f4584beffbf276d00adf6e2c35bda92 (patch) | |
| tree | 45f74f27aa25a92181cfc6b7d54d08cfdcea5294 /kernel/workqueue_internal.h | |
| parent | b533200b40334bd86caa737b0ff033ecc391d071 (diff) | |
ice: Fix setting coalesce to handle DCB configuration
[ Upstream commit e25f9152bc07de534b2b590ce6c052ea25dd8900 ]
Currently there can be a case where a DCB map is applied and there are
more interrupt vectors (vsi->num_q_vectors) than Rx queues (vsi->num_rxq)
and Tx queues (vsi->num_txq). If we try to set coalesce settings in this
case it will report a false failure. Fix this by checking if vector index
is valid with respect to the number of Tx and Rx queues configured.
Signed-off-by: Brett Creeley <brett.creeley@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'kernel/workqueue_internal.h')
0 files changed, 0 insertions, 0 deletions