diff options
| author | Stephen Boyd <sboyd@kernel.org> | 2025-10-06 12:56:46 -0500 | 
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2025-10-06 12:56:46 -0500 | 
| commit | 3aae991cc2ce76deb1034d37021e3ab511c02b3a (patch) | |
| tree | 9166f74ef20617136dc0ce87bcde11b7326fb7ba /rust/kernel/platform.rs | |
| parent | ec7336475d52575381149aa67f9526c2f6d45e0d (diff) | |
| parent | 823699ccbf0f3794d89031f68385936eddaccf0e (diff) | |
| parent | ccd74beccdacda1533ad6f2de747e8f267276061 (diff) | |
| parent | 7e2e4e32cd47a4129bf25c21e7049ff0571b7b90 (diff) | |
Merge branches 'clk-samsung', 'clk-tegra' and 'clk-amlogic' into clk-next
* clk-samsung:
  clk: s2mps11: add support for S2MPG10 PMIC clock
  dt-bindings: clock: samsung,s2mps11: add s2mpg10
  clk: samsung: exynos990: Add PERIC0 and PERIC1 clock support
  dt-bindings: clock: exynos990: Add PERIC0 and PERIC1 clock units
  clk: samsung: exynos990: Add missing USB clock registers to HSI0
  clk: samsung: exynos990: Add LHS_ACEL gate clock for HSI0 and update CLK_NR_TOP
  dt-bindings: clock: exynos990: Add LHS_ACEL clock ID for HSI0 block
  clk: samsung: artpec-8: Add initial clock support for ARTPEC-8 SoC
  clk: samsung: Add clock PLL support for ARTPEC-8 SoC
  dt-bindings: clock: Add ARTPEC-8 clock controller
  clk: samsung: exynos990: Add DPU_BUS and CMUREF mux/div and update CLKS_NR_TOP
  dt-bindings: clock: exynos990: Extend clocks IDs
  clk: samsung: exynos990: Replace bogus divs with fixed-factor clocks
  clk: samsung: exynos990: Fix CMU_TOP mux/div bit widths
  clk: samsung: exynos990: Use PLL_CON0 for PLL parent muxes
  clk: samsung: pll: convert from round_rate() to determine_rate()
  clk: samsung: cpu: convert from round_rate() to determine_rate()
  clk: samsung: fsd: Add clk id for PCLK and PLL in CAM_CSI block
  dt-bindings: clock: Add CAM_CSI clock macro for FSD
* clk-tegra:
  clk: tegra: dfll: Add CVB tables for Tegra114
  clk: tegra: Add DFLL DVCO reset control for Tegra114
  dt-bindings: arm: tegra: Add ASUS TF101G and SL101
  dt-bindings: reset: Add Tegra114 CAR header
  dt-bindings: arm: tegra: Add Xiaomi Mi Pad (A0101)
  dt-bindings: clock: tegra30: Add IDs for CSI pad clocks
  dt-bindings: display: tegra: Move avdd-dsi-csi-supply from VI to CSI
  dt-bindings: i2c: nvidia,tegra20-i2c: Document Tegra264 I2C
* clk-amlogic:
  clk: amlogic: fix recent code refactoring
  clk: amlogic: c3-peripherals: use helper for basic composite clocks
  clk: amlogic: align s4 and c3 pwm clock descriptions
  clk: amlogic: add composite clock helpers
  clk: amlogic: use the common pclk definition
  clk: amlogic: introduce a common pclk definition
  clk: amlogic: pclk explicitly use CLK_IGNORE_UNUSED
  clk: amlogic: drop CLK_SET_RATE_PARENT from peripheral clocks
  clk: amlogic: move PCLK definition to clkc-utils
  clk: amlogic: aoclk: use clkc-utils syscon probe
  clk: amlogic: use probe helper in mmio based controllers
  clk: amlogic: add probe helper for mmio based controllers
  clk: amlogic: drop meson-clkcee
  clk: amlogic: naming consistency alignment
