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authorQiuxu Zhuo <qiuxu.zhuo@intel.com>2025-11-19 12:11:40 -0800
committerTony Luck <tony.luck@intel.com>2025-11-21 10:20:51 -0800
commit39abdcbdad597b1ac3dabd44a757de91b87c683a (patch)
tree508fe824de3e9ac3ebb2a992da84cf3b32d3e277 /scripts/lib/kdoc/kdoc_files.py
parent9fc67b11703fe9d8a5617ccacec2a452e455fa52 (diff)
EDAC/skx_common: Extend the maximum number of DRAM chip row bits
The allowed maximum number of row bits for DRAM chips in the Diamond Rapids server processor is up to 19. Extend the current maximum row bits from 18 to 19. Tested-by: Yi Lai <yi1.lai@intel.com> Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20251119134132.2389472-6-qiuxu.zhuo@intel.com
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