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| author | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2020-09-11 20:00:20 -0400 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2020-09-11 20:00:20 -0400 |
| commit | 0ea8a56de21be24cb79abb03dee79aabcd60a316 (patch) | |
| tree | 71ad6c51064e4948b5c90e84c86da52457e2cfb2 /scripts/recordmcount.c | |
| parent | 0560c2173e3f12bc39ef5d61b26d43307cab8694 (diff) | |
| parent | 166774a2c2c6b82da5d984f587567071ff00c1f3 (diff) | |
Merge drm/drm-next into drm-intel-next-queued
Sync drm-intel-gt-next here so we can have an unified fixes flow.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'scripts/recordmcount.c')
| -rw-r--r-- | scripts/recordmcount.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/scripts/recordmcount.c b/scripts/recordmcount.c index 7225107a9aaf..b9c2ee7ab43f 100644 --- a/scripts/recordmcount.c +++ b/scripts/recordmcount.c @@ -42,6 +42,8 @@ #define R_ARM_THM_CALL 10 #define R_ARM_CALL 28 +#define R_AARCH64_CALL26 283 + static int fd_map; /* File descriptor for file being modified. */ static int mmap_failed; /* Boolean flag. */ static char gpfx; /* prefix for global symbol name (sometimes '_') */ @@ -434,6 +436,11 @@ static int arm_is_fake_mcount(Elf32_Rel const *rp) return 1; } +static int arm64_is_fake_mcount(Elf64_Rel const *rp) +{ + return ELF64_R_TYPE(w(rp->r_info)) != R_AARCH64_CALL26; +} + /* 64-bit EM_MIPS has weird ELF64_Rela.r_info. * http://techpubs.sgi.com/library/manuals/4000/007-4658-001/pdf/007-4658-001.pdf * We interpret Table 29 Relocation Operation (Elf64_Rel, Elf64_Rela) [p.40] @@ -547,6 +554,7 @@ static int do_file(char const *const fname) make_nop = make_nop_arm64; rel_type_nop = R_AARCH64_NONE; ideal_nop = ideal_nop4_arm64; + is_fake_mcount64 = arm64_is_fake_mcount; break; case EM_IA_64: reltype = R_IA64_IMM64; break; case EM_MIPS: /* reltype: e_class */ break; |