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authorMarc Zyngier <maz@kernel.org>2024-02-13 10:12:04 +0000
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2024-02-23 09:24:59 +0100
commitf7e84c8e196b7126161856881de49da171e6a02f (patch)
treea70f55085d906b2997d14012c5332f5269987580 /scripts
parentfcb82e9739f261138852e0a4a0e149a93be3458b (diff)
irqchip/gic-v3-its: Handle non-coherent GICv4 redistributors
[ Upstream commit 846297e11e8ae428f8b00156a0cfe2db58100702 ] Although the GICv3 code base has gained some handling of systems failing to handle the shareability attributes, the GICv4 side of things has been firmly ignored. This is unfortunate, as the new recent addition of the "dma-noncoherent" is supposed to apply to all of the GICR tables, and not just the ones that are common to v3 and v4. Add some checks to handle the VPROPBASE/VPENDBASE shareability and cacheability attributes in the same way we deal with the other GICR_BASE registers, wrapping the flag check in a helper for improved readability. Note that this has been found by inspection only, as I don't have access to HW that suffers from this particular issue. Fixes: 3a0fff0fb6a3 ("irqchip/gic-v3: Enable non-coherent redistributors/ITSes DT probing") Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Link: https://lore.kernel.org/r/20240213101206.2137483-2-maz@kernel.org Signed-off-by: Sasha Levin <sashal@kernel.org>
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