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| author | Catalin Marinas <catalin.marinas@arm.com> | 2025-11-28 15:47:53 +0000 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2025-11-28 15:47:53 +0000 |
| commit | 52c4d1d62424c574fa048235598ce37bd4ed1e32 (patch) | |
| tree | a63e8649e6258a9fa49a651c8f7227a8f45eda5c /tools/docs/parse-headers.py | |
| parent | 17c05cb0ef212d1a3c1bbbb67693a89cd9f0fb44 (diff) | |
| parent | 27abb1ee5a4e02a5314423371dafaf41499314a5 (diff) | |
Merge branch 'for-next/sysreg' into for-next/core
* for-next/sysreg:
: arm64 sysreg updates/cleanups
arm64/sysreg: Remove unused define ARM64_FEATURE_FIELD_BITS
KVM: arm64: selftests: Consider all 7 possible levels of cache
KVM: arm64: selftests: Remove ARM64_FEATURE_FIELD_BITS and its last user
arm64/sysreg: Add ICH_VMCR_EL2
arm64/sysreg: Move generation of RES0/RES1/UNKN to function
arm64/sysreg: Support feature-specific fields with 'Prefix' descriptor
arm64/sysreg: Fix checks for incomplete sysreg definitions
arm64/sysreg: Replace TCR_EL1 field macros
Diffstat (limited to 'tools/docs/parse-headers.py')
0 files changed, 0 insertions, 0 deletions