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| author | Stephen Boyd <sboyd@kernel.org> | 2025-11-19 11:40:56 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2025-11-19 11:40:56 -0700 |
| commit | f700b882a7aedec69a7dc3762c63b7c04ebdfb91 (patch) | |
| tree | e91d40eb0cca14162d8a6c77b0c6862f71879edf /tools/lib/python/jobserver.py | |
| parent | 1f2d68c354131e70af30388157703a0a678d52de (diff) | |
| parent | 5fb2f67341bd4b7c482f2bbda6b78244a51c3923 (diff) | |
Merge tag 'renesas-clk-for-v6.19-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add GPU clocks on R-Car V3U
- Add USB3.0 clocks and resets on RZ/V2H and RZ/V2N
- Add more serial (RSCI) clocks and resets on RZ/G3E
- Add SPI clocks on RZ/T2H and RZ/N2H
* tag 'renesas-clk-for-v6.19-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r9a09g077: Add SPI module clocks
clk: renesas: r9a09g056: Add USB3.0 clocks/resets
clk: renesas: r9a09g057: Add USB3.0 clocks/resets
clk: renesas: r9a09g047: Add RSCI clocks/resets
dt-bindings: clock: renesas,r9a09g056-cpg: Add USB3.0 core clocks
dt-bindings: clock: renesas,r9a09g057-cpg: Add USB3.0 core clocks
clk: renesas: r9a06g032: Fix memory leak in error path
clk: renesas: r9a09g077: Use devm_ helpers for divider clock registration
clk: renesas: r9a09g077: Remove stray blank line
clk: renesas: r9a09g077: Propagate rate changes to parent clocks
clk: renesas: r8a779a0: Add 3DGE module clock
clk: renesas: r8a779a0: Add ZG Core clock
clk: renesas: rcar-gen4: Add support for clock dividers in FRQCRB
dt-bindings: clock: r8a779a0: Add ZG core clock
Diffstat (limited to 'tools/lib/python/jobserver.py')
0 files changed, 0 insertions, 0 deletions
