diff options
| author | Chu Guangqing <chuguangqing@inspur.com> | 2025-10-31 10:58:10 +0800 |
|---|---|---|
| committer | Namhyung Kim <namhyung@kernel.org> | 2025-10-31 12:28:17 -0700 |
| commit | 0d1e63183d5ce63f7a57a99cbee1018f2a72d202 (patch) | |
| tree | 24a2c23602584de26019de8d15aae0d423a9fa5b /tools/perf | |
| parent | 1d7f783809fc5fdd60c9cc4f5c880d0c9e47857d (diff) | |
perf vendor events AmpereOneX: Fix spelling typo in the metrics file
The json file incorrectly used "acceses" instead of "accesses".
Signed-off-by: Chu Guangqing <chuguangqing@inspur.com>
Reviewed-by: James Clark <james.clark@linaro.org>
Reviewed-by: Ilkka Koskinen <ilkka@os.amperecomputing.com>
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Diffstat (limited to 'tools/perf')
| -rw-r--r-- | tools/perf/pmu-events/arch/arm64/ampere/ampereonex/metrics.json | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/metrics.json b/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/metrics.json index 6817cac149e0..a29aadc9b2e3 100644 --- a/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/metrics.json +++ b/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/metrics.json @@ -388,55 +388,55 @@ "MetricExpr": "L1D_CACHE_RW / L1D_CACHE", "BriefDescription": "L1D cache access - demand", "MetricGroup": "Cache", - "ScaleUnit": "100percent of cache acceses" + "ScaleUnit": "100percent of cache accesses" }, { "MetricName": "l1d_cache_access_prefetches", "MetricExpr": "L1D_CACHE_PRFM / L1D_CACHE", "BriefDescription": "L1D cache access - prefetch", "MetricGroup": "Cache", - "ScaleUnit": "100percent of cache acceses" + "ScaleUnit": "100percent of cache accesses" }, { "MetricName": "l1d_cache_demand_misses", "MetricExpr": "L1D_CACHE_REFILL_RW / L1D_CACHE", "BriefDescription": "L1D cache demand misses", "MetricGroup": "Cache", - "ScaleUnit": "100percent of cache acceses" + "ScaleUnit": "100percent of cache accesses" }, { "MetricName": "l1d_cache_demand_misses_read", "MetricExpr": "L1D_CACHE_REFILL_RD / L1D_CACHE", "BriefDescription": "L1D cache demand misses - read", "MetricGroup": "Cache", - "ScaleUnit": "100percent of cache acceses" + "ScaleUnit": "100percent of cache accesses" }, { "MetricName": "l1d_cache_demand_misses_write", "MetricExpr": "L1D_CACHE_REFILL_WR / L1D_CACHE", "BriefDescription": "L1D cache demand misses - write", "MetricGroup": "Cache", - "ScaleUnit": "100percent of cache acceses" + "ScaleUnit": "100percent of cache accesses" }, { "MetricName": "l1d_cache_prefetch_misses", "MetricExpr": "L1D_CACHE_REFILL_PRFM / L1D_CACHE", "BriefDescription": "L1D cache prefetch misses", "MetricGroup": "Cache", - "ScaleUnit": "100percent of cache acceses" + "ScaleUnit": "100percent of cache accesses" }, { "MetricName": "ase_scalar_mix", "MetricExpr": "ASE_SCALAR_SPEC / OP_SPEC", "BriefDescription": "Proportion of advanced SIMD data processing operations (excluding DP_SPEC/LD_SPEC) scalar operations", "MetricGroup": "Instructions", - "ScaleUnit": "100percent of cache acceses" + "ScaleUnit": "100percent of cache accesses" }, { "MetricName": "ase_vector_mix", "MetricExpr": "ASE_VECTOR_SPEC / OP_SPEC", "BriefDescription": "Proportion of advanced SIMD data processing operations (excluding DP_SPEC/LD_SPEC) vector operations", "MetricGroup": "Instructions", - "ScaleUnit": "100percent of cache acceses" + "ScaleUnit": "100percent of cache accesses" } ] |