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| author | Uma Shankar <uma.shankar@intel.com> | 2025-12-03 14:22:11 +0530 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2025-12-04 19:44:36 +0200 |
| commit | 860daa4b0d09a398a0ac9ae6fe67efd73a275968 (patch) | |
| tree | 07fbc7aac4085d39a939ae52877557f457ac5bc8 /tools/testing/selftests/net/lib/py/utils.py | |
| parent | 65db7a1f9cf772d733358de032fee60ad770c1e8 (diff) | |
drm/i915/color: Enable Plane Color Pipelines
Expose color pipeline and add ability to program it.
v2: Set bit to enable multisegmented lut
v3: s/drm_color_lut_32/drm_color_lut32 (Simon)
v4: - Fix dsb programming
- Remove multi-segment LUT, they will be added in later patches
- Add pipeline only to TGL+
- Code Refactor
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patch.msgid.link/20251203085211.3663374-16-uma.shankar@intel.com
Diffstat (limited to 'tools/testing/selftests/net/lib/py/utils.py')
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