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-rw-r--r--arch/ppc/kernel/cpu_setup_6xx.S20
-rw-r--r--arch/ppc/kernel/cputable.c34
-rw-r--r--arch/ppc/kernel/head.S24
-rw-r--r--include/asm-ppc/cputable.h1
-rw-r--r--include/asm-ppc/processor.h33
5 files changed, 92 insertions, 20 deletions
diff --git a/arch/ppc/kernel/cpu_setup_6xx.S b/arch/ppc/kernel/cpu_setup_6xx.S
index cb0701cb24d0..be11b8010276 100644
--- a/arch/ppc/kernel/cpu_setup_6xx.S
+++ b/arch/ppc/kernel/cpu_setup_6xx.S
@@ -16,6 +16,7 @@
#include <asm/cputable.h>
#include <asm/ppc_asm.h>
#include <asm/offsets.h>
+#include <asm/cache.h>
_GLOBAL(__setup_cpu_601)
blr
@@ -63,13 +64,7 @@ _GLOBAL(__setup_cpu_7410)
mtspr SPRN_L2CR2,r3
mtlr r4
blr
-_GLOBAL(__setup_cpu_7450)
- mflr r4
- bl setup_common_caches
- bl setup_745x_specifics
- mtlr r4
- blr
-_GLOBAL(__setup_cpu_7455)
+_GLOBAL(__setup_cpu_745x)
mflr r4
bl setup_common_caches
bl setup_745x_specifics
@@ -265,9 +260,10 @@ END_FTR_SECTION_IFCLR(CPU_FTR_NO_DPM)
#define CS_SIZE 28
.data
- .balign 4
+ .balign L1_CACHE_LINE_SIZE
cpu_state_storage:
.space CS_SIZE
+ .balign L1_CACHE_LINE_SIZE,0
.text
/* Called in normal context to backup CPU 0 state. This
@@ -277,6 +273,9 @@ cpu_state_storage:
* like HID0, HID1, MSSCR0, etc...
*/
_GLOBAL(__save_cpu_setup)
+ /* Some CR fields are volatile, we back it up all */
+ mfcr r7
+
/* Get storage ptr */
lis r5,cpu_state_storage@h
ori r5,r5,cpu_state_storage@l
@@ -322,6 +321,7 @@ _GLOBAL(__save_cpu_setup)
mfspr r4,SPRN_HID1
stw r4,CS_HID1(r5)
1:
+ mtcr r7
blr
/* Called with no MMU context (typically MSR:IR/DR off) to
@@ -329,6 +329,9 @@ _GLOBAL(__save_cpu_setup)
* function. This does not include cache setting
*/
_GLOBAL(__restore_cpu_setup)
+ /* Some CR fields are volatile, we back it up all */
+ mfcr r7
+
/* Get storage ptr */
lis r5,(cpu_state_storage-KERNELBASE)@h
ori r5,r5,cpu_state_storage@l
@@ -411,5 +414,6 @@ _GLOBAL(__restore_cpu_setup)
/* Setup final PLL */
mtspr SPRN_HID1,r4
1:
+ mtcr r7
blr
diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c
index 3bc08629ccf1..c2f5e7e8dee7 100644
--- a/arch/ppc/kernel/cputable.c
+++ b/arch/ppc/kernel/cputable.c
@@ -26,8 +26,7 @@ extern void __setup_cpu_750cx(unsigned long offset, int cpu_nr, struct cpu_spec*
extern void __setup_cpu_750fx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
extern void __setup_cpu_7400(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
extern void __setup_cpu_7410(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
-extern void __setup_cpu_7450(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
-extern void __setup_cpu_7455(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
+extern void __setup_cpu_745x(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
extern void __setup_cpu_power3(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
extern void __setup_cpu_8xx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
@@ -168,7 +167,7 @@ struct cpu_spec cpu_specs[] = {
0xffff0000, 0x70000000, "750FX",
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
- CPU_FTR_DUAL_PLL_750FX,
+ CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
COMMON_PPC,
32, 32,
__setup_cpu_750fx
@@ -216,7 +215,7 @@ struct cpu_spec cpu_specs[] = {
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450,
COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC,
32, 32,
- __setup_cpu_7450
+ __setup_cpu_745x
},
{ /* 7450 2.1 */
0xffffffff, 0x80000201, "7450",
@@ -226,7 +225,7 @@ struct cpu_spec cpu_specs[] = {
CPU_FTR_L3_DISABLE_NAP,
COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC,
32, 32,
- __setup_cpu_7450
+ __setup_cpu_745x
},
{ /* 7450 2.3 and newer */
0xffff0000, 0x80000000, "7450",
@@ -235,35 +234,46 @@ struct cpu_spec cpu_specs[] = {
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR,
COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC,
32, 32,
- __setup_cpu_7450
+ __setup_cpu_745x
},
{ /* 7455 rev 1.x */
0xffffff00, 0x80010100, "7455",
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
- CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450,
+ CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS,
COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC,
32, 32,
- __setup_cpu_7455
+ __setup_cpu_745x
},
{ /* 7455 rev 2.0 */
0xffffffff, 0x80010200, "7455",
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
- CPU_FTR_L3_DISABLE_NAP,
+ CPU_FTR_L3_DISABLE_NAP | CPU_FTR_HAS_HIGH_BATS,
COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC,
32, 32,
- __setup_cpu_7455
+ __setup_cpu_745x
},
{ /* 7455 others */
0xffff0000, 0x80010000, "7455",
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
- CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR,
+ CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
+ CPU_FTR_HAS_HIGH_BATS,
+ COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC,
+ 32, 32,
+ __setup_cpu_745x
+ },
+ { /* 7457 */
+ 0xffff0000, 0x80020000, "7457",
+ CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
+ CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
+ CPU_FTR_HAS_HIGH_BATS,
COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC,
32, 32,
- __setup_cpu_7455
+ __setup_cpu_745x
},
{ /* 82xx (8240, 8245, 8260 are all 603e cores) */
0x7fff0000, 0x00810000, "82xx",
diff --git a/arch/ppc/kernel/head.S b/arch/ppc/kernel/head.S
index 68b4f262db4d..ca2584c93e26 100644
--- a/arch/ppc/kernel/head.S
+++ b/arch/ppc/kernel/head.S
@@ -1451,6 +1451,30 @@ clear_bats:
mtspr IBAT2L,r10
mtspr IBAT3U,r10
mtspr IBAT3L,r10
+BEGIN_FTR_SECTION
+ /* Here's a tweak: at this point, CPU setup have
+ * not been called yet, so HIGH_BAT_EN may not be
+ * set in HID0 for the 745x processors. However, it
+ * seems that doesn't affect our ability to actually
+ * write to these SPRs.
+ */
+ mtspr SPRN_DBAT4U,r20
+ mtspr SPRN_DBAT4L,r20
+ mtspr SPRN_DBAT5U,r20
+ mtspr SPRN_DBAT5L,r20
+ mtspr SPRN_DBAT6U,r20
+ mtspr SPRN_DBAT6L,r20
+ mtspr SPRN_DBAT7U,r20
+ mtspr SPRN_DBAT7L,r20
+ mtspr SPRN_IBAT4U,r20
+ mtspr SPRN_IBAT4L,r20
+ mtspr SPRN_IBAT5U,r20
+ mtspr SPRN_IBAT5L,r20
+ mtspr SPRN_IBAT6U,r20
+ mtspr SPRN_IBAT6L,r20
+ mtspr SPRN_IBAT7U,r20
+ mtspr SPRN_IBAT7L,r20
+END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)
blr
flush_tlbs:
diff --git a/include/asm-ppc/cputable.h b/include/asm-ppc/cputable.h
index 0818267600b1..4f82095103b9 100644
--- a/include/asm-ppc/cputable.h
+++ b/include/asm-ppc/cputable.h
@@ -74,6 +74,7 @@ extern struct cpu_spec *cur_cpu_spec[];
#define CPU_FTR_NAP_DISABLE_L2_PR 0x00002000
#define CPU_FTR_DUAL_PLL_750FX 0x00004000
#define CPU_FTR_NO_DPM 0x00008000
+#define CPU_FTR_HAS_HIGH_BATS 0x00010000
#ifdef __ASSEMBLY__
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index da0dff483ba7..c40d33d55f80 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -104,6 +104,15 @@
#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */
#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */
#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */
+#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */
+#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */
+#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */
+#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */
+#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */
+#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */
+#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */
+#define SPRN_DBAT7U 0x23E /* Data BAT 7 Upper Register */
+
#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
#define DBCR_EDM 0x80000000
#define DBCR_IDM 0x40000000
@@ -267,6 +276,14 @@
#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */
#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */
#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */
+#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */
+#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */
+#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */
+#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */
+#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */
+#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */
+#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */
+#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */
#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
#define ICCR_NOCACHE 0 /* Noncacheable */
#define ICCR_CACHE 1 /* Cacheable */
@@ -448,6 +465,14 @@
#define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */
#define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */
#define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */
+#define DBAT4L SPRN_DBAT4L /* Data BAT 4 Lower Register */
+#define DBAT4U SPRN_DBAT4U /* Data BAT 4 Upper Register */
+#define DBAT5L SPRN_DBAT5L /* Data BAT 5 Lower Register */
+#define DBAT5U SPRN_DBAT5U /* Data BAT 5 Upper Register */
+#define DBAT6L SPRN_DBAT6L /* Data BAT 6 Lower Register */
+#define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */
+#define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */
+#define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */
#define DCMP SPRN_DCMP /* Data TLB Compare Register */
#define DEC SPRN_DEC /* Decrement Register */
#define DMISS SPRN_DMISS /* Data TLB Miss Register */
@@ -466,6 +491,14 @@
#define IBAT2U SPRN_IBAT2U /* Instruction BAT 2 Upper Register */
#define IBAT3L SPRN_IBAT3L /* Instruction BAT 3 Lower Register */
#define IBAT3U SPRN_IBAT3U /* Instruction BAT 3 Upper Register */
+#define IBAT4L SPRN_IBAT4L /* Instruction BAT 4 Lower Register */
+#define IBAT4U SPRN_IBAT4U /* Instruction BAT 4 Upper Register */
+#define IBAT5L SPRN_IBAT5L /* Instruction BAT 5 Lower Register */
+#define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */
+#define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */
+#define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */
+#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */
+#define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Upper Register */
#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
generated by cgit v1.2.3 (git 2.46.0) at 2026-01-29 18:56:02 +0000