diff options
52 files changed, 725 insertions, 458 deletions
diff --git a/arch/ppc/8260_io/Config.help b/arch/ppc/8260_io/Config.help index a03f3933ffd5..6be82a97454e 100644 --- a/arch/ppc/8260_io/Config.help +++ b/arch/ppc/8260_io/Config.help @@ -22,3 +22,6 @@ CONFIG_SCC1_ENET CONFIG_SCC2_ENET Use MPC8xx serial communications controller 2 to drive Ethernet. +CONFIG_DCACHE_DISABLE + This option allows you to run the kernel with data cache disabled. + Say Y if you experience CPM lock-ups. diff --git a/arch/ppc/8260_io/Config.in b/arch/ppc/8260_io/Config.in index 157c8228eff8..20eeaeae50fc 100644 --- a/arch/ppc/8260_io/Config.in +++ b/arch/ppc/8260_io/Config.in @@ -2,7 +2,7 @@ # MPC8260 Communication options # mainmenu_option next_comment -comment 'MPC8260 Communication Options' +comment 'MPC8260 CPM Options' bool 'Enable SCC Console' CONFIG_SCC_CONSOLE if [ "$CONFIG_NET_ETHERNET" = "y" ]; then bool 'CPM SCC Ethernet' CONFIG_SCC_ENET @@ -30,4 +30,7 @@ if [ "$CONFIG_NET_ETHERNET" = "y" ]; then fi fi fi + +comment 'Generic MPC8260 Options' +bool 'Disable data cache' CONFIG_DCACHE_DISABLE endmenu diff --git a/arch/ppc/Config.help b/arch/ppc/Config.help index 40a9633e06bf..f570362e43e4 100644 --- a/arch/ppc/Config.help +++ b/arch/ppc/Config.help @@ -1023,3 +1023,7 @@ CONFIG_BOOT_LOAD_BOOL which has a small amount of memory. Say N here unless you know what you are doing. + +CONFIG_DEBUG_SPINLOCK + Say Y here and to CONFIG_SMP to include code to check for missing + spinlock initialization and some other common spinlock errors. diff --git a/arch/ppc/Makefile b/arch/ppc/Makefile index 582527e71c1a..458476b851f1 100644 --- a/arch/ppc/Makefile +++ b/arch/ppc/Makefile @@ -108,7 +108,7 @@ $(BOOT_TARGETS): vmlinux %_config: arch/ppc/configs/%_defconfig rm -f .config arch/ppc/defconfig - cp -f arch/ppc/configs/$(@:config=defconfig) arch/ppc/defconfig + cp -f arch/ppc/configs/$(@:config=defconfig) .config archclean: rm -f arch/ppc/kernel/{mk_defs,asm-offsets.h,find_name} @@ -116,3 +116,24 @@ archclean: @$(MAKEBOOT) clean archmrproper: + +prepare: checkbin + +ifdef CONFIG_6xx +# Ensure this is binutils 2.12.1 (or 2.12.90.0.7) or later +NEW_AS := $(shell echo dssall | $(AS) -o /dev/null >/dev/null 2>&1 ; echo $$?) +GOODVER := 2.12.1 +else +NEW_AS := 0 +endif + +ifneq ($(NEW_AS),0) +checkbin: + @echo -n '*** ${VERSION}.${PATCHLEVEL} kernels no longer build' + @echo 'correctly with old versions of binutils.' + @echo '*** Please upgrade your binutils to ${GOODVER} or newer' + @false +else +checkbin: + @true +endif diff --git a/arch/ppc/boot/chrp/Makefile b/arch/ppc/boot/chrp/Makefile index 0f2e8b6f49e2..33139e52e79c 100644 --- a/arch/ppc/boot/chrp/Makefile +++ b/arch/ppc/boot/chrp/Makefile @@ -11,7 +11,11 @@ LD_ARGS = -T ../ld.script -Ttext 0x00400000 OBJS = ../common/crt0.o start.o main.o misc.o ../common/string.o image.o \ ../common/ofcommon.o + +EXTRA_TARGETS := $(OBJS) LIBS = $(TOPDIR)/lib/lib.a ../lib/zlib.a + +# Utils ADDNOTE = ../utils/addnote PIGGYBACK = ../utils/piggyback diff --git a/arch/ppc/boot/pmac/Makefile b/arch/ppc/boot/pmac/Makefile index 8277856ce0f2..4881a0158aff 100644 --- a/arch/ppc/boot/pmac/Makefile +++ b/arch/ppc/boot/pmac/Makefile @@ -15,6 +15,8 @@ CHRP_LD_ARGS = -T ../ld.script -Ttext 0x01000000 COMMONOBJS = start.o misc.o ../common/string.o ../common/ofcommon.o COFFOBJS = ../common/coffcrt0.o $(COMMONOBJS) coffmain.o CHRPOBJS = ../common/crt0.o $(COMMONOBJS) chrpmain.o + +EXTRA_TARGETS := $(COFFOBJS) $(CHRPOBJS) LIBS = $(TOPDIR)/lib/lib.a ../lib/zlib.a MKNOTE := ../utils/mknote diff --git a/arch/ppc/boot/prep/Makefile b/arch/ppc/boot/prep/Makefile index f94848f1c45d..52b55da1ae19 100644 --- a/arch/ppc/boot/prep/Makefile +++ b/arch/ppc/boot/prep/Makefile @@ -21,14 +21,16 @@ TFTPIMAGE = $(TFTPBOOT).smp endif LD_ARGS = -T ../ld.script -Ttext 0x00800000 -Bstatic -obj-y := head.o ../simple/legacy.o misc.o of1275.o \ +boot-y := head.o ../simple/legacy.o misc.o of1275.o \ ../common/util.o ../common/string.o \ ../common/misc-common.o OBJCOPY_ARGS = -O elf32-powerpc LIBS = ../lib/zlib.a -obj-$(CONFIG_SERIAL_CONSOLE) += ../common/ns16550.o -obj-$(CONFIG_VGA_CONSOLE) += vreset.o kbd.o +boot-$(CONFIG_SERIAL_CONSOLE) += ../common/ns16550.o +boot-$(CONFIG_VGA_CONSOLE) += vreset.o kbd.o + +EXTRA_TARGETS := $(boot-y) # Tools MKPREP := ../utils/mkprep @@ -40,18 +42,18 @@ CFLAGS_kbd.o += -I$(TOPDIR)/drivers/char all: zImage -zImage: $(obj-y) $(LIBS) ../ld.script ../images/vmlinux.gz ../common/dummy.o \ +zImage: $(boot-y) $(LIBS) ../ld.script ../images/vmlinux.gz ../common/dummy.o \ $(MKPREP) $(OBJCOPY) $(OBJCOPY_ARGS) -R .comment \ --add-section=.image=../images/vmlinux.gz \ --set-section-flags=.image=contents,alloc,load,readonly,data \ ../common/dummy.o image.o - $(LD) $(LD_ARGS) -o $@ $(obj-y) image.o $(LIBS) + $(LD) $(LD_ARGS) -o $@ $(boot-y) image.o $(LIBS) $(OBJCOPY) $(OBJCOPY_ARGS) $@ $@ -R .comment -R .stab -R .stabstr $(MKPREP) -pbp $@ ../images/$@.prep rm -f $@ -zImage.initrd: $(obj-y) $(LIBS) ../ld.script ../images/vmlinux.gz $(MKPREP) \ +zImage.initrd: $(boot-y) $(LIBS) ../ld.script ../images/vmlinux.gz $(MKPREP) \ ../common/dummy.o $(OBJCOPY) $(OBJCOPY_ARGS) -R .comment \ --add-section=.ramdisk=../images/ramdisk.image.gz \ @@ -59,7 +61,7 @@ zImage.initrd: $(obj-y) $(LIBS) ../ld.script ../images/vmlinux.gz $(MKPREP) \ --add-section=.image=../images/vmlinux.gz \ --set-section-flags=.image=contents,alloc,load,readonly,data \ ../common/dummy.o image.o - $(LD) $(LD_ARGS) -o $@ $(obj-y) image.o $(LIBS) + $(LD) $(LD_ARGS) -o $@ $(boot-y) image.o $(LIBS) $(OBJCOPY) $(OBJCOPY_ARGS) $@ $@ -R .comment -R .stab -R .stabstr $(MKPREP) -pbp $@ ../images/$@.prep rm -f $@ diff --git a/arch/ppc/boot/simple/Makefile b/arch/ppc/boot/simple/Makefile index 5d91c93abfd8..8428333266f9 100644 --- a/arch/ppc/boot/simple/Makefile +++ b/arch/ppc/boot/simple/Makefile @@ -122,24 +122,25 @@ endif OBJCOPY_ARGS := -O elf32-powerpc # head.o and ../common/relocate.o must be at the start. -obj-y := head.o ../common/relocate.o $(HEADHELP) \ +boot-y := head.o ../common/relocate.o $(HEADHELP) \ $(MISC) ../common/misc-common.o \ ../common/string.o ../common/util.o -obj-$(CONFIG_4xx) += embed_config.o -obj-$(CONFIG_8xx) += embed_config.o -obj-$(CONFIG_8260) += embed_config.o -obj-$(CONFIG_BSEIP) += iic.o -obj-$(CONFIG_MBX) += iic.o pci.o qspan_pci.o -obj-$(CONFIG_RPXCLASSIC) += iic.o pci.o qspan_pci.o -obj-$(CONFIG_RPXLITE) += iic.o +boot-$(CONFIG_4xx) += embed_config.o +boot-$(CONFIG_8xx) += embed_config.o +boot-$(CONFIG_8260) += embed_config.o +boot-$(CONFIG_BSEIP) += iic.o +boot-$(CONFIG_MBX) += iic.o pci.o qspan_pci.o +boot-$(CONFIG_RPXCLASSIC) += iic.o pci.o qspan_pci.o +boot-$(CONFIG_RPXLITE) += iic.o # Different boards need different serial implementations. ifeq ($(CONFIG_SERIAL_CONSOLE),y) -obj-$(CONFIG_8xx) += m8xx_tty.o -obj-$(CONFIG_8260) += m8260_tty.o -obj-$(CONFIG_GT64260_CONSOLE) += gt64260_tty.o -obj-$(CONFIG_SERIAL) += ../common/ns16550.o +boot-$(CONFIG_8xx) += m8xx_tty.o +boot-$(CONFIG_8260) += m8260_tty.o +boot-$(CONFIG_GT64260_CONSOLE) += gt64260_tty.o +boot-$(CONFIG_SERIAL) += ../common/ns16550.o endif +EXTRA_TARGETS := $(boot-y) LIBS := ../lib/zlib.a # Tools @@ -147,16 +148,16 @@ MKBUGBOOT := ../utils/mkbugboot MKPREP := ../utils/mkprep MKTREE := ../utils/mktree -zvmlinux: $(obj-y) $(LIBS) ../ld.script ../images/vmlinux.gz ../common/dummy.o +zvmlinux: $(boot-y) $(LIBS) ../ld.script ../images/vmlinux.gz ../common/dummy.o $(OBJCOPY) $(OBJCOPY_ARGS) \ --add-section=.image=../images/vmlinux.gz \ --set-section-flags=.image=contents,alloc,load,readonly,data \ ../common/dummy.o image.o - $(LD) $(LD_ARGS) -o $@ $(obj-y) image.o $(LIBS) + $(LD) $(LD_ARGS) -o $@ $(boot-y) image.o $(LIBS) $(OBJCOPY) $(OBJCOPY_ARGS) $@ $@ -R .comment -R .stab -R .stabstr \ -R .ramdisk -R .sysmap -zvmlinux.initrd: $(obj-y) $(LIBS) ../ld.script ../images/vmlinux.gz \ +zvmlinux.initrd: $(boot-y) $(LIBS) ../ld.script ../images/vmlinux.gz \ ../common/dummy.o $(OBJCOPY) $(OBJCOPY_ARGS) \ --add-section=.ramdisk=../images/ramdisk.image.gz \ @@ -164,7 +165,7 @@ zvmlinux.initrd: $(obj-y) $(LIBS) ../ld.script ../images/vmlinux.gz \ --add-section=.image=../images/vmlinux.gz \ --set-section-flags=.image=contents,alloc,load,readonly,data \ ../common/dummy.o image.o - $(LD) $(LD_ARGS) -o $@ $(obj-y) image.o $(LIBS) + $(LD) $(LD_ARGS) -o $@ $(boot-y) image.o $(LIBS) $(OBJCOPY) $(OBJCOPY_ARGS) $@ $@ -R .comment -R .stab -R .stabstr \ -R .sysmap diff --git a/arch/ppc/config.in b/arch/ppc/config.in index 09fbbde6bb4a..dddff7e6c876 100644 --- a/arch/ppc/config.in +++ b/arch/ppc/config.in @@ -288,9 +288,6 @@ if [ "$CONFIG_ADVANCED_OPTIONS" = "y" ]; then if [ "$CONFIG_8xx" = "y" ]; then bool "Pinned Kernel TLBs (860 ONLY)" CONFIG_PIN_TLB fi - if [ "$CONFIG_40x" = "y" ]; then - bool "Pinned Kernel TLBs" CONFIG_PIN_TLB - fi if [ "$CONFIG_ALL_PPC" != "y" ]; then bool "Set the boot link/load address" CONFIG_BOOT_LOAD_BOOL if [ "$CONFIG_BOOT_LOAD_BOOL" = "y" ]; then @@ -605,6 +602,7 @@ mainmenu_option next_comment comment 'Kernel hacking' bool 'Magic SysRq key' CONFIG_MAGIC_SYSRQ +bool 'Spinlock debugging' CONFIG_DEBUG_SPINLOCK bool 'Include kgdb kernel debugger' CONFIG_KGDB if [ "$CONFIG_KGDB" = "y" ]; then choice 'Serial Port' \ diff --git a/arch/ppc/configs/est8260_defconfig b/arch/ppc/configs/est8260_defconfig index 0b0c3ee46a38..a7bc8538f9a8 100644 --- a/arch/ppc/configs/est8260_defconfig +++ b/arch/ppc/configs/est8260_defconfig @@ -421,6 +421,7 @@ CONFIG_PARTITION_ADVANCED=y CONFIG_SCC_ENET=y CONFIG_SCC1_ENET=y # CONFIG_FEC_ENET is not set +# CONFIG_DCACHE_DISABLE is not set # # USB support diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c index 2f948b3d6155..729e0bac40a4 100644 --- a/arch/ppc/kernel/cputable.c +++ b/arch/ppc/kernel/cputable.c @@ -204,7 +204,7 @@ struct cpu_spec cpu_specs[] = { { /* 7450 2.1 */ 0xffffffff, 0x80000201, "7450", CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP | - CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | + CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450, COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC, 32, 32, @@ -213,7 +213,7 @@ struct cpu_spec cpu_specs[] = { { /* 7450 2.3 and newer */ 0xffff0000, 0x80000000, "7450", CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP | - CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | + CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450, COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC, 32, 32, @@ -222,7 +222,7 @@ struct cpu_spec cpu_specs[] = { { /* 7455 */ 0xffff0000, 0x80010000, "7455", CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP | - CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | + CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450, COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC, 32, 32, diff --git a/arch/ppc/kernel/entry.S b/arch/ppc/kernel/entry.S index 1414c7e02b91..51bad8f074cb 100644 --- a/arch/ppc/kernel/entry.S +++ b/arch/ppc/kernel/entry.S @@ -164,7 +164,6 @@ ret_from_syscall: andi. r0,r9,(_TIF_SYSCALL_TRACE|_TIF_SIGPENDING|_TIF_NEED_RESCHED) bne- syscall_exit_work syscall_exit_cont: - PPC405_ERR77(0,r1) stwcx. r0,0,r1 /* to clear the reservation */ lwz r4,_LINK(r1) lwz r5,_CCR(r1) @@ -568,6 +567,7 @@ exc_exit_start: exc_exit_restart_end: PPC405_ERR77_SYNC rfi + b . /* prevent prefetch past rfi */ crit_exc_exit: mtcrf 0xff,r10 /* avoid any possible TLB misses here by turning off MSR.DR, we @@ -576,18 +576,40 @@ crit_exc_exit: mtmsr r10 isync tophys(r1, r1) - lwz r9,_SRR0(r1) - lwz r10,_SRR1(r1) - mtspr SRR0,r9 + lwz r9,_DEAR(r1) + lwz r10,_ESR(r1) + mtspr SPRN_DEAR,r9 + mtspr SPRN_ESR,r10 lwz r11,_NIP(r1) - mtspr SRR1,r10 lwz r12,_MSR(r1) mtspr SRR2,r11 mtspr SRR3,r12 - REST_4GPRS(9, r1) + lwz r9,GPR9(r1) + lwz r12,GPR12(r1) + lwz r10,crit_sprg0@l(0) + mtspr SPRN_SPRG0,r10 + lwz r10,crit_sprg1@l(0) + mtspr SPRN_SPRG1,r10 + lwz r10,crit_sprg4@l(0) + mtspr SPRN_SPRG4,r10 + lwz r10,crit_sprg5@l(0) + mtspr SPRN_SPRG5,r10 + lwz r10,crit_sprg6@l(0) + mtspr SPRN_SPRG6,r10 + lwz r10,crit_sprg7@l(0) + mtspr SPRN_SPRG7,r10 + lwz r10,crit_srr0@l(0) + mtspr SRR0,r10 + lwz r10,crit_srr1@l(0) + mtspr SRR1,r10 + lwz r10,crit_pid@l(0) + mtspr SPRN_PID,r10 + lwz r10,crit_r10@l(0) + lwz r11,crit_r11@l(0) lwz r1,GPR1(r1) PPC405_ERR77_SYNC rfci + b . /* prevent prefetch past rfci */ #endif /* CONFIG_4xx */ recheck: @@ -650,6 +672,10 @@ nonrecoverable: mr r12,r11 /* restart at exc_exit_restart */ blr 3: /* OK, we can't recover, kill this process */ + /* but the 601 doesn't implement the RI bit, so assume it's OK */ +BEGIN_FTR_SECTION + blr +END_FTR_SECTION_IFSET(CPU_FTR_601) lwz r3,TRAP(r1) andi. r0,r3,1 beq 4f diff --git a/arch/ppc/kernel/head.S b/arch/ppc/kernel/head.S index cdd0807b90ef..175a7983959a 100644 --- a/arch/ppc/kernel/head.S +++ b/arch/ppc/kernel/head.S @@ -832,7 +832,12 @@ fast_exception_return: /* aargh, a nonrecoverable interrupt, panic */ /* aargh, we don't know which trap this is */ -3: li r10,0 +/* but the 601 doesn't implement the RI bit, so assume it's OK */ +3: +BEGIN_FTR_SECTION + b 2b +END_FTR_SECTION_IFSET(CPU_FTR_601) + li r10,-1 stw r10,TRAP(r11) addi r3,r1,STACK_FRAME_OVERHEAD li r10,MSR_KERNEL @@ -887,9 +892,9 @@ load_up_altivec: add r4,r4,r6 addi r4,r4,THREAD /* want THREAD of last_task_used_altivec */ SAVE_32VR(0,r10,r4) - MFVSCR(vr0) + mfvscr vr0 li r10,THREAD_VSCR - STVX(vr0,r10,r4) + stvx vr0,r10,r4 lwz r5,PT_REGS(r4) add r5,r5,r6 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) @@ -902,8 +907,8 @@ load_up_altivec: oris r9,r9,MSR_VEC@h mfspr r5,SPRG3 /* current task's THREAD (phys) */ li r10,THREAD_VSCR - LVX(vr0,r10,r5) - MTVSCR(vr0) + lvx vr0,r10,r5 + mtvscr vr0 REST_32VR(0,r10,r5) #ifndef CONFIG_SMP subi r4,r5,THREAD @@ -951,9 +956,9 @@ giveup_altivec: lwz r5,PT_REGS(r3) cmpi 0,r5,0 SAVE_32VR(0, r4, r3) - MFVSCR(vr0) + mfvscr vr0 li r4,THREAD_VSCR - STVX(vr0, r4, r3) + stvx vr0,r4,r3 beq 1f lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) lis r3,MSR_VEC@h @@ -1272,7 +1277,11 @@ _GLOBAL(__setup_cpu_generic) setup_common_caches: mfspr r11,HID0 andi. r0,r11,HID0_DCE +#ifdef CONFIG_DCACHE_DISABLE + ori r11,r11,HID0_ICE +#else ori r11,r11,HID0_ICE|HID0_DCE +#endif ori r8,r11,HID0_ICFI bne 1f /* don't invalidate the D-cache */ ori r8,r8,HID0_DCI /* unless it wasn't enabled */ @@ -1362,7 +1371,7 @@ setup_7450_23_hid0: isync blr -/* 7450 +/* 7455 * Enable Store Gathering (SGE), Branch Folding (FOLD) * Branch History Table (BHTE), Branch Target ICache (BTIC) * Dynamic Power Management (DPM), Speculative (SPD) @@ -1546,7 +1555,7 @@ _GLOBAL(set_context) #endif li r4,0 BEGIN_FTR_SECTION - dssall 0 + dssall sync END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 3: diff --git a/arch/ppc/kernel/head_4xx.S b/arch/ppc/kernel/head_4xx.S index 69e9398df14b..beae3cee8672 100644 --- a/arch/ppc/kernel/head_4xx.S +++ b/arch/ppc/kernel/head_4xx.S @@ -82,6 +82,7 @@ turn_on_mmu: mtspr SRR0,r0 SYNC rfi /* enables MMU */ + b . /* prevent prefetch past rfi */ /* * This area is used for temporarily saving registers during the @@ -89,7 +90,28 @@ turn_on_mmu: */ . = 0xc0 crit_save: - .space 8 +_GLOBAL(crit_r10) + .space 4 +_GLOBAL(crit_r11) + .space 4 +_GLOBAL(crit_sprg0) + .space 4 +_GLOBAL(crit_sprg1) + .space 4 +_GLOBAL(crit_sprg4) + .space 4 +_GLOBAL(crit_sprg5) + .space 4 +_GLOBAL(crit_sprg6) + .space 4 +_GLOBAL(crit_sprg7) + .space 4 +_GLOBAL(crit_pid) + .space 4 +_GLOBAL(crit_srr0) + .space 4 +_GLOBAL(crit_srr1) + .space 4 /* * Exception vector entry code. This code runs with address translation @@ -140,6 +162,59 @@ crit_save: * This is OK since we don't support SMP on these processors. */ #define CRITICAL_EXCEPTION_PROLOG \ + stw r10,crit_r10@l(0); /* save two registers to work with */\ + stw r11,crit_r11@l(0); \ + mfspr r10,SPRG0; \ + stw r10,crit_sprg0@l(0); \ + mfspr r10,SPRG1; \ + stw r10,crit_sprg1@l(0); \ + mfspr r10,SPRG4; \ + stw r10,crit_sprg4@l(0); \ + mfspr r10,SPRG5; \ + stw r10,crit_sprg5@l(0); \ + mfspr r10,SPRG6; \ + stw r10,crit_sprg6@l(0); \ + mfspr r10,SPRG7; \ + stw r10,crit_sprg7@l(0); \ + mfspr r10,SPRN_PID; \ + stw r10,crit_pid@l(0); \ + mfspr r10,SRR0; \ + stw r10,crit_srr0@l(0); \ + mfspr r10,SRR1; \ + stw r10,crit_srr1@l(0); \ + mfcr r10; /* save CR in r10 for now */\ + mfspr r11,SPRN_SRR3; /* check whether user or kernel */\ + andi. r11,r11,MSR_PR; \ + lis r11,critical_stack_top@h; \ + ori r11,r11,critical_stack_top@l; \ + beq 1f; \ + /* COMING FROM USER MODE */ \ + mfspr r11,SPRG3; /* if from user, start at top of */\ + lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\ + addi r11,r11,THREAD_SIZE; \ +1: subi r11,r11,INT_FRAME_SIZE; /* Allocate an exception frame */\ + tophys(r11,r11); \ + stw r10,_CCR(r11); /* save various registers */\ + stw r12,GPR12(r11); \ + stw r9,GPR9(r11); \ + mflr r10; \ + stw r10,_LINK(r11); \ + mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\ + stw r12,_DEAR(r11); /* since they may have had stuff */\ + mfspr r9,SPRN_ESR; /* in them at the point where the */\ + stw r9,_ESR(r11); /* exception was taken */\ + mfspr r12,SRR2; \ + stw r1,GPR1(r11); \ + mfspr r9,SRR3; \ + stw r1,0(r11); \ + tovirt(r1,r11); \ + rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ + stw r0,GPR0(r11); \ + SAVE_4GPRS(3, r11); \ + SAVE_2GPRS(7, r11) + +#if 0 +#define CRITICAL_EXCEPTION_PROLOG \ stw r10,crit_save@l(0); /* save two registers to work with */\ stw r11,4+crit_save@l(0); \ mfcr r10; /* save CR in r10 for now */\ @@ -173,6 +248,7 @@ crit_save: stw r0,GPR0(r11); \ SAVE_4GPRS(3, r11); \ SAVE_2GPRS(7, r11) +#endif /* * Exception vectors. @@ -197,13 +273,14 @@ label: START_EXCEPTION(n, label); \ CRITICAL_EXCEPTION_PROLOG; \ addi r3,r1,STACK_FRAME_OVERHEAD; \ - EXC_XFER_TEMPLATE(hdlr, n+2, NOCOPY, transfer_to_handler_full, \ + EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ + NOCOPY, transfer_to_handler_full, \ ret_from_except_full) -#define EXC_XFER_TEMPLATE(hdlr, trap, copyee, tfer, ret) \ +#define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret) \ li r10,trap; \ stw r10,TRAP(r11); \ - li r10,MSR_KERNEL; \ + li r10,msr; \ copyee(r10, r9); \ bl tfer; \ .long hdlr; \ @@ -213,19 +290,19 @@ label: #define NOCOPY(d, s) #define EXC_XFER_STD(n, hdlr) \ - EXC_XFER_TEMPLATE(hdlr, n, NOCOPY, transfer_to_handler_full, \ + EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \ ret_from_except_full) #define EXC_XFER_LITE(n, hdlr) \ - EXC_XFER_TEMPLATE(hdlr, n+1, NOCOPY, transfer_to_handler, \ + EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \ ret_from_except) #define EXC_XFER_EE(n, hdlr) \ - EXC_XFER_TEMPLATE(hdlr, n, COPY_EE, transfer_to_handler_full, \ + EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \ ret_from_except_full) #define EXC_XFER_EE_LITE(n, hdlr) \ - EXC_XFER_TEMPLATE(hdlr, n+1, COPY_EE, transfer_to_handler, \ + EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \ ret_from_except) @@ -347,6 +424,7 @@ label: mfspr r10, SPRG0 PPC405_ERR77_SYNC rfi /* Should sync shadow TLBs */ + b . /* prevent prefetch past rfi */ 2: /* The bailout. Restore registers to pre-exception conditions @@ -615,6 +693,7 @@ label: mfspr r10, SPRG0 PPC405_ERR77_SYNC rfi /* Should sync shadow TLBs */ + b . /* prevent prefetch past rfi */ 2: /* The bailout. Restore registers to pre-exception conditions @@ -721,6 +800,7 @@ check_single_step_in_exception: sync rfci /* return to the exception handler */ + b . /* prevent prefetch past rfi */ 2: mtcrf 0xff,r10 /* restore registers */ @@ -746,31 +826,18 @@ check_single_step_in_exception: * Actually, it will fit now, but oh well.....a common place * to load the TLB. */ +tlb_4xx_index: + .long 0 finish_tlb_load: - - /* Since it has a unified TLB, and we can take data faults on - * instruction pages by copying data, we have to check if the - * EPN is already in the TLB. - */ - tlbsx. r9, 0, r10 - beq 6f - /* load the next available TLB index. */ - lis r12, tlb_4xx_index@h - ori r12, r12, tlb_4xx_index@l - tophys(r12, r12) - lwz r9, 0(r12) + lwz r9, tlb_4xx_index@l(0) addi r9, r9, 1 -#ifdef CONFIG_PIN_TLB cmpwi 0, r9, 61 /* reserve entries 62, 63 for kernel */ ble 7f li r9, 0 7: -#else - andi. r9, r9, (PPC4XX_TLB_SIZE-1) -#endif - stw r9, 0(r12) + stw r9, tlb_4xx_index@l(0) 6: tlbwe r11, r9, TLB_DATA /* Load TLB LO */ @@ -804,6 +871,7 @@ finish_tlb_load: mfspr r10, SPRG0 PPC405_ERR77_SYNC rfi /* Should sync shadow TLBs */ + b . /* prevent prefetch past rfi */ /* extern void giveup_fpu(struct task_struct *prev) * @@ -857,14 +925,11 @@ start_here: mtspr SRR0,r4 mtspr SRR1,r3 rfi + b . /* prevent prefetch past rfi */ /* Load up the kernel context */ 2: SYNC /* Force all PTE updates to finish */ -#ifndef CONFIG_PIN_TLB - tlbia /* Clear all TLB entries */ - sync /* wait for tlbia/tlbie to finish */ -#endif /* set up the PTE pointers for the Abatron bdiGDB. */ @@ -883,6 +948,7 @@ start_here: mtspr SRR0,r3 mtspr SRR1,r4 rfi /* enable MMU and jump to start_kernel */ + b . /* prevent prefetch past rfi */ /* Set up the initial MMU state so we can do the first level of * kernel initialization. This maps the first 16 MBytes of memory 1:1 @@ -956,7 +1022,10 @@ _GLOBAL(set_context) lwz r5, 0xf0(r5) stw r4, 0x4(r5) #endif + sync mtspr SPRN_PID,r3 + isync /* Need an isync to flush shadow */ + /* TLBs after changing PID */ blr /* We put a few things here that have to be page-aligned. This stuff @@ -969,6 +1038,14 @@ _GLOBAL(empty_zero_page) _GLOBAL(swapper_pg_dir) .space 4096 + +/* Stack for handling critical exceptions from kernel mode */ + .section .bss +critical_stack_bottom: + .space 4096 +critical_stack_top: + .previous + /* This space gets a copy of optional info passed to us by the bootstrap * which is used to pass parameters into the kernel like root=/dev/sda1, etc. */ diff --git a/arch/ppc/kernel/l2cr.S b/arch/ppc/kernel/l2cr.S index b5bdc1e18e23..dd50c3d50ea6 100644 --- a/arch/ppc/kernel/l2cr.S +++ b/arch/ppc/kernel/l2cr.S @@ -255,7 +255,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_L3CR) isync /* Stop DST streams */ - dssall 0 + dssall /* Get the current enable bit of the L3CR into r4 */ mfspr r4,SPRN_L3CR diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S index 8fbabdf5985e..f0fb7c7bb1ea 100644 --- a/arch/ppc/kernel/misc.S +++ b/arch/ppc/kernel/misc.S @@ -354,7 +354,7 @@ _GLOBAL(_nmask_and_or_msr) * Flush MMU TLB */ _GLOBAL(_tlbia) -#if defined(CONFIG_40x) && defined(CONFIG_PIN_TLB) +#if defined(CONFIG_40x) /* This needs to be coordinated with other pinning functions since * we don't keep a memory location of number of entries to reduce * cache pollution during these operations. @@ -367,7 +367,7 @@ _GLOBAL(_tlbia) cmpwi 0, r3, 61 /* reserve last two entries */ ble 1b isync -#else +#else /* ! defined(CONFIG_40x) */ #if defined(CONFIG_SMP) rlwinm r8,r1,0,0,18 lwz r8,TI_CPU(r8) @@ -401,7 +401,7 @@ _GLOBAL(_tlbia) tlbia sync #endif /* CONFIG_SMP */ -#endif /* defined(CONFIG_40x) && defined(CONFIG_PIN_TLB) */ +#endif /* ! defined(CONFIG_40x) */ blr /* @@ -412,7 +412,7 @@ _GLOBAL(_tlbie) tlbsx. r3, 0, r3 bne 10f sync - /* There are only 64 TLB entries, so r3 < 64, which means bit 25, is clear. + /* There are only 64 TLB entries, so r3 < 64, which means bit 25 is clear. * Since 25 is the V bit in the TLB_TAG, loading this value will invalidate * the TLB entry. */ tlbwe r3, r3, TLB_TAG diff --git a/arch/ppc/kernel/mk_defs.c b/arch/ppc/kernel/mk_defs.c index d4cce91f178c..99bfc3b087b8 100644 --- a/arch/ppc/kernel/mk_defs.c +++ b/arch/ppc/kernel/mk_defs.c @@ -112,8 +112,6 @@ main(void) */ DEFINE(_DEAR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dar)); DEFINE(_ESR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dsisr)); - DEFINE(_SRR0, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dar)); - DEFINE(_SRR1, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dsisr)); DEFINE(ORIG_GPR3, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, orig_gpr3)); DEFINE(RESULT, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, result)); DEFINE(TRAP, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, trap)); diff --git a/arch/ppc/kernel/open_pic.c b/arch/ppc/kernel/open_pic.c index 97908db5f032..9727f59e8f95 100644 --- a/arch/ppc/kernel/open_pic.c +++ b/arch/ppc/kernel/open_pic.c @@ -302,7 +302,7 @@ void openpic_set_sources(int first_irq, int num_irqs, void *first_ISR) ISR[i] = src; } -void __init openpic_init(int main_pic, int offset, int programmer_switch_irq) +void __init openpic_init(int linux_irq_offset) { u_int t, i; u_int timerfreq; @@ -351,16 +351,13 @@ void __init openpic_init(int main_pic, int offset, int programmer_switch_irq) printk("OpenPIC timer frequency is %d.%06d MHz\n", timerfreq / 1000000, timerfreq % 1000000); - if (!main_pic) - return; - - open_pic_irq_offset = offset; + open_pic_irq_offset = linux_irq_offset; /* Initialize timer interrupts */ if ( ppc_md.progress ) ppc_md.progress("openpic timer",0x3ba); for (i = 0; i < OPENPIC_NUM_TIMERS; i++) { /* Disabled, Priority 0 */ - openpic_inittimer(i, 0, OPENPIC_VEC_TIMER+i+offset); + openpic_inittimer(i, 0, OPENPIC_VEC_TIMER+i+linux_irq_offset); /* No processor */ openpic_maptimer(i, 0); } @@ -370,10 +367,12 @@ void __init openpic_init(int main_pic, int offset, int programmer_switch_irq) if ( ppc_md.progress ) ppc_md.progress("openpic ipi",0x3bb); for (i = 0; i < OPENPIC_NUM_IPI; i++) { /* Disabled, Priority 10..13 */ - openpic_initipi(i, 10+i, OPENPIC_VEC_IPI+i+offset); + openpic_initipi(i, 10+i, OPENPIC_VEC_IPI+i+linux_irq_offset); /* IPIs are per-CPU */ - irq_desc[OPENPIC_VEC_IPI+i+offset].status |= IRQ_PER_CPU; - irq_desc[OPENPIC_VEC_IPI+i+offset].handler = &open_pic_ipi; + irq_desc[OPENPIC_VEC_IPI+i+linux_irq_offset].status |= + IRQ_PER_CPU; + irq_desc[OPENPIC_VEC_IPI+i+linux_irq_offset].handler = + &open_pic_ipi; } #endif @@ -384,15 +383,14 @@ void __init openpic_init(int main_pic, int offset, int programmer_switch_irq) /* Init all external sources, including possibly the cascade. */ for (i = 0; i < NumSources; i++) { - int pri, sense; + int sense; if (ISR[i] == 0) continue; /* the bootloader may have left it enabled (bad !) */ - openpic_disable_irq(i+offset); + openpic_disable_irq(i+linux_irq_offset); - pri = (i == programmer_switch_irq)? 9: 8; /* * We find the vale from either the InitSenses table * or assume a negative polarity level interrupt. @@ -400,26 +398,27 @@ void __init openpic_init(int main_pic, int offset, int programmer_switch_irq) sense = (i < OpenPIC_NumInitSenses)? OpenPIC_InitSenses[i]: 1; if ((sense & IRQ_SENSE_MASK) == 1) - irq_desc[i+offset].status = IRQ_LEVEL; + irq_desc[i+linux_irq_offset].status = IRQ_LEVEL; - /* Enabled, Priority 8 or 9 */ - openpic_initirq(i, pri, i+offset, (sense & IRQ_POLARITY_MASK), + /* Enabled, Priority 8 */ + openpic_initirq(i, 8, i + linux_irq_offset, + (sense & IRQ_POLARITY_MASK), (sense & IRQ_SENSE_MASK)); /* Processor 0 */ openpic_mapirq(i, 1<<0, 0); } /* Init descriptors */ - for (i = offset; i < NumSources + offset; i++) + for (i = linux_irq_offset; i < NumSources + linux_irq_offset; i++) irq_desc[i].handler = &open_pic; /* Initialize the spurious interrupt */ if (ppc_md.progress) ppc_md.progress("openpic spurious",0x3bd); - openpic_set_spurious(OPENPIC_VEC_SPURIOUS+offset); + openpic_set_spurious(OPENPIC_VEC_SPURIOUS+linux_irq_offset); /* Initialize the cascade */ - if (offset) { - if (request_irq(offset, no_action, SA_INTERRUPT, + if (linux_irq_offset) { + if (request_irq(linux_irq_offset, no_action, SA_INTERRUPT, "82c59 cascade", NULL)) printk("Unable to get OpenPIC IRQ 0 for cascade\n"); } @@ -653,6 +652,31 @@ static void __init openpic_maptimer(u_int timer, u_int cpumask) physmask(cpumask)); } +/* + * Initalize the interrupt source which will generate an NMI (and disable it). + * + * irq: The logical IRQ which generates an NMI. + */ +void __init +openpic_init_nmi_irq(u_int irq) +{ + int sense; + + /* If this wasn't given, assume a level, negative polarity interrupt. */ + sense = (irq < OpenPIC_NumInitSenses) ? OpenPIC_InitSenses[irq] : + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE); + + openpic_safe_writefield(&ISR[irq]->Vector_Priority, + OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK | + OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK, + (9 << OPENPIC_PRIORITY_SHIFT) | + (irq + open_pic_irq_offset) | + ((sense & IRQ_POLARITY_MASK) ? + OPENPIC_POLARITY_POSITIVE : + OPENPIC_POLARITY_NEGATIVE) | + ((sense & IRQ_SENSE_MASK) ? OPENPIC_SENSE_LEVEL + : OPENPIC_SENSE_EDGE)); +} /* * diff --git a/arch/ppc/kernel/pci.c b/arch/ppc/kernel/pci.c index 1d20f1f4409a..a47335985996 100644 --- a/arch/ppc/kernel/pci.c +++ b/arch/ppc/kernel/pci.c @@ -923,6 +923,7 @@ pci_process_bridge_OF_ranges(struct pci_controller *hose, struct device_node *dev, int primary) { unsigned int *ranges, *prev; + unsigned int size; int rlen = 0; int memno = 0; struct resource *res; @@ -963,12 +964,16 @@ pci_process_bridge_OF_ranges(struct pci_controller *hose, ranges = (unsigned int *) get_property(dev, "ranges", &rlen); while ((rlen -= np * sizeof(unsigned int)) >= 0) { res = NULL; + size = ranges[na+4]; switch (ranges[0] >> 24) { case 1: /* I/O space */ if (ranges[2] != 0) break; hose->io_base_phys = ranges[na+2]; - hose->io_base_virt = ioremap(ranges[na+2], ranges[na+4]); + /* limit I/O space to 16MB */ + if (size > 0x01000000) + size = 0x01000000; + hose->io_base_virt = ioremap(ranges[na+2], size); if (primary) isa_io_base = (unsigned long) hose->io_base_virt; res = &hose->io_resource; @@ -997,7 +1002,7 @@ pci_process_bridge_OF_ranges(struct pci_controller *hose, } if (res != NULL) { res->name = dev->full_name; - res->end = res->start + ranges[na+4] - 1; + res->end = res->start + size - 1; res->parent = NULL; res->sibling = NULL; res->child = NULL; diff --git a/arch/ppc/kernel/ppc4xx_pic.c b/arch/ppc/kernel/ppc4xx_pic.c index ae96d1c722e9..6619898dbe97 100644 --- a/arch/ppc/kernel/ppc4xx_pic.c +++ b/arch/ppc/kernel/ppc4xx_pic.c @@ -15,10 +15,14 @@ * there are eight internal interrupts for the on-chip serial port * (SPU), DMA controller, and JTAG controller. * - * The PowerPC 405 cores' Universal Interrupt Controller (UIC) has 32 - * possible interrupts as well. There are seven, configurable external - * interrupt pins and there are 17 internal interrupts for the on-chip - * serial port, DMA controller, on-chip Ethernet controller, PCI, etc. + * The PowerPC 405/440 cores' Universal Interrupt Controller (UIC) has + * 32 possible interrupts as well. Depending on the core and SoC + * implementation, a portion of the interrrupts are used for on-chip + * peripherals and a portion of the interrupts are available to be + * configured for external devices generating interrupts. + * + * The PowerNP and 440GP (and most likely future implementations) have + * cascaded UICs. * */ @@ -30,11 +34,9 @@ #include <asm/processor.h> #include <asm/system.h> #include <asm/irq.h> -#include <asm/ibm4xx.h> #include <asm/ppc4xx_pic.h> /* Global Variables */ - struct hw_interrupt_type *ppc4xx_pic; /* Six of one, half dozen of the other....#ifdefs, separate files, @@ -128,7 +130,11 @@ ppc403_aic_disable_and_ack(unsigned int irq) mtdcr(DCRN_EXISR, (1 << (31 - bit))); } -#else /* !CONFIG_403 */ +#else + +#ifndef UIC1 +#define UIC1 UIC0 +#endif static void ppc405_uic_enable(unsigned int irq) @@ -137,9 +143,18 @@ ppc405_uic_enable(unsigned int irq) bit = irq & 0x1f; word = irq >> 5; - +#ifdef UIC_DEBUG + printk("ppc405_uic_enable - irq %d word %d bit 0x%x\n",irq, word , bit); +#endif ppc_cached_irq_mask[word] |= 1 << (31 - bit); - mtdcr(DCRN_UIC0_ER, ppc_cached_irq_mask[word]); + switch (word){ + case 0: + mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[word]); + break; + case 1: + mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]); + break; + } } static void @@ -149,9 +164,18 @@ ppc405_uic_disable(unsigned int irq) bit = irq & 0x1f; word = irq >> 5; - +#ifdef UIC_DEBUG + printk("ppc405_uic_disable - irq %d word %d bit 0x%x\n",irq, word , bit); +#endif ppc_cached_irq_mask[word] &= ~(1 << (31 - bit)); - mtdcr(DCRN_UIC0_ER, ppc_cached_irq_mask[word]); + switch (word){ + case 0: + mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[word]); + break; + case 1: + mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]); + break; + } } static void @@ -162,9 +186,20 @@ ppc405_uic_disable_and_ack(unsigned int irq) bit = irq & 0x1f; word = irq >> 5; +#ifdef UIC_DEBUG +printk("ppc405_uic_disable_and_ack - irq %d word %d bit 0x%x\n",irq, word , bit); +#endif ppc_cached_irq_mask[word] &= ~(1 << (31 - bit)); - mtdcr(DCRN_UIC0_ER, ppc_cached_irq_mask[word]); - mtdcr(DCRN_UIC0_SR, (1 << (31 - bit))); + switch (word){ + case 0: + mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[word]); + mtdcr(DCRN_UIC_SR(UIC0), (1 << (31 - bit))); + break; + case 1: + mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]); + mtdcr(DCRN_UIC_SR(UIC1), (1 << (31 - bit))); + break; + } } static void @@ -176,23 +211,49 @@ ppc405_uic_end(unsigned int irq) bit = irq & 0x1f; word = irq >> 5; - tr_bits = mfdcr(DCRN_UIC0_TR); +#ifdef UIC_DEBUG + printk("ppc405_uic_end - irq %d word %d bit 0x%x\n",irq, word , bit); +#endif + + switch (word){ + case 0: + tr_bits = mfdcr(DCRN_UIC_TR(UIC0)); + break; + case 1: + tr_bits = mfdcr(DCRN_UIC_TR(UIC1)); + break; + } + if ((tr_bits & (1 << (31 - bit))) == 0) { /* level trigger */ - mtdcr(DCRN_UIC0_SR, 1 << (31 - bit)); + switch (word){ + case 0: + mtdcr(DCRN_UIC_SR(UIC0), 1 << (31 - bit)); + break; + case 1: + mtdcr(DCRN_UIC_SR(UIC1), 1 << (31 - bit)); + break; + } } if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { ppc_cached_irq_mask[word] |= 1 << (31 - bit); - mtdcr(DCRN_UIC0_ER, ppc_cached_irq_mask[word]); + switch (word){ + case 0: + mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[word]); + break; + case 1: + mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]); + break; + } } } static struct hw_interrupt_type ppc405_uic = { -#if defined (CONFIG_405GP) - "405GP UIC", +#if (NR_UICS == 1) + "IBM UIC", #else - "NP405 UIC", + "IBM UIC Cascade", #endif NULL, NULL, @@ -206,16 +267,27 @@ static struct hw_interrupt_type ppc405_uic = { int ppc405_pic_get_irq(struct pt_regs *regs) { - int irq; + int irq, cas_irq; unsigned long bits; - + cas_irq = 0; /* * Only report the status of those interrupts that are actually * enabled. */ - bits = mfdcr(DCRN_UIC0_MSR); - + bits = mfdcr(DCRN_UIC_MSR(UIC0)); + +#if (NR_UICS > 1) + if (bits & UIC_CASCADE_MASK){ + bits = mfdcr(DCRN_UIC_MSR(UIC1)); + cas_irq = 32 - ffs(bits); + irq = 32 + cas_irq; + } else { + irq = 32 - ffs(bits); + if (irq == 32) + irq= -1; + } +#else /* * Walk through the interrupts from highest priority to lowest, and * report the first pending interrupt found. @@ -223,10 +295,14 @@ ppc405_pic_get_irq(struct pt_regs *regs) * result from 32. */ irq = 32 - ffs(bits); - - if (irq == NR_AIC_IRQS) +#endif + if (irq == (NR_UIC_IRQS * NR_UICS)) irq = -1; +#ifdef UIC_DEBUG +printk("ppc405_pic_get_irq - irq %d bit 0x%x\n",irq, bits); +#endif + return (irq); } #endif @@ -239,18 +315,31 @@ ppc4xx_pic_init(void) * explicity requested. */ ppc_cached_irq_mask[0] = 0; + ppc_cached_irq_mask[1] = 0; -#ifdef CONFIG_403 +#if defined CONFIG_403 mtdcr(DCRN_EXIER, ppc_cached_irq_mask[0]); ppc4xx_pic = &ppc403_aic; ppc_md.get_irq = ppc403_pic_get_irq; #else - mtdcr(DCRN_UIC0_ER, ppc_cached_irq_mask[0]); +#if (NR_UICS > 1) + ppc_cached_irq_mask[0] |= 1 << (31 - UIC0_UIC1NC ); /* enable cascading interrupt */ + mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[0]); + mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[1]); + + /* Set all interrupts to non-critical. + */ + mtdcr(DCRN_UIC_CR(UIC0), 0); + mtdcr(DCRN_UIC_CR(UIC1), 0); + +#else + mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[0]); /* Set all interrupts to non-critical. */ - mtdcr(DCRN_UIC0_CR, 0); + mtdcr(DCRN_UIC_CR(UIC0), 0); +#endif ppc4xx_pic = &ppc405_uic; ppc_md.get_irq = ppc405_pic_get_irq; diff --git a/arch/ppc/kernel/ppc_ksyms.c b/arch/ppc/kernel/ppc_ksyms.c index eef23f3c55dd..6e732fbcd3da 100644 --- a/arch/ppc/kernel/ppc_ksyms.c +++ b/arch/ppc/kernel/ppc_ksyms.c @@ -77,10 +77,6 @@ extern unsigned char __res[]; extern unsigned long mm_ptov (unsigned long paddr); -extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *dma_handle); -extern void consistent_free(void *vaddr); -extern void consistent_sync(void *vaddr, size_t size, int direction); - EXPORT_SYMBOL(clear_page); EXPORT_SYMBOL(do_signal); EXPORT_SYMBOL(do_syscall_trace); diff --git a/arch/ppc/kernel/process.c b/arch/ppc/kernel/process.c index 843586742026..a63d75944635 100644 --- a/arch/ppc/kernel/process.c +++ b/arch/ppc/kernel/process.c @@ -197,7 +197,7 @@ dump_fpu(struct pt_regs *regs, elf_fpregset_t *fpregs) return 1; } -void switch_to(struct task_struct *prev, struct task_struct *new) +void __switch_to(struct task_struct *prev, struct task_struct *new) { struct thread_struct *new_thread, *old_thread; unsigned long s; diff --git a/arch/ppc/kernel/prom.c b/arch/ppc/kernel/prom.c index c0be2375cfa4..3a3b36040be7 100644 --- a/arch/ppc/kernel/prom.c +++ b/arch/ppc/kernel/prom.c @@ -520,6 +520,38 @@ prom_n_size_cells(struct device_node* np) } static unsigned long __init +map_addr(struct device_node *np, unsigned long space, unsigned long addr) +{ + int na; + unsigned int *ranges; + int rlen = 0; + unsigned int type; + + type = (space >> 24) & 3; + if (type == 0) + return addr; + + while ((np = np->parent) != NULL) { + if (strcmp(np->type, "pci") != 0) + continue; + /* PCI bridge: map the address through the ranges property */ + na = prom_n_addr_cells(np); + ranges = (unsigned int *) get_property(np, "ranges", &rlen); + while ((rlen -= (na + 5) * sizeof(unsigned int)) >= 0) { + if (((ranges[0] >> 24) & 3) == type + && ranges[2] <= addr + && addr - ranges[2] < ranges[na+4]) { + /* ok, this matches, translate it */ + addr += ranges[na+2] - ranges[2]; + break; + } + ranges += na + 5; + } + } + return addr; +} + +static unsigned long __init interpret_pci_props(struct device_node *np, unsigned long mem_start, int naddrc, int nsizec) { @@ -533,9 +565,9 @@ interpret_pci_props(struct device_node *np, unsigned long mem_start, i = 0; adr = (struct address_range *) mem_start; while ((l -= sizeof(struct pci_reg_property)) >= 0) { - /* XXX assumes PCI addresses mapped 1-1 to physical */ adr[i].space = pci_addrs[i].addr.a_hi; - adr[i].address = pci_addrs[i].addr.a_lo; + adr[i].address = map_addr(np, pci_addrs[i].addr.a_hi, + pci_addrs[i].addr.a_lo); adr[i].size = pci_addrs[i].size_lo; ++i; } @@ -772,13 +804,14 @@ prom_get_irq_senses(unsigned char *senses, int off, int max) for (np = allnodes; np != 0; np = np->allnext) { for (j = 0; j < np->n_intrs; j++) { i = np->intrs[j].line; - if (i >= off && i < max) + if (i >= off && i < max) { if (np->intrs[j].sense == 1) senses[i-off] = (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE); else senses[i-off] = (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE); + } } } } diff --git a/arch/ppc/kernel/syscalls.c b/arch/ppc/kernel/syscalls.c index 87540676a5e4..6a439c76e134 100644 --- a/arch/ppc/kernel/syscalls.c +++ b/arch/ppc/kernel/syscalls.c @@ -117,7 +117,7 @@ sys_ipc (uint call, int first, int second, int third, void *ptr, long fifth) if ((ret = verify_area (VERIFY_READ, ptr, sizeof(tmp))) || (ret = copy_from_user(&tmp, (struct ipc_kludge *) ptr, - sizeof (tmp)) ? -EFAULT : 0) + sizeof (tmp)) ? -EFAULT : 0)) break; ret = sys_msgrcv (first, tmp.msgp, second, tmp.msgtyp, third); diff --git a/arch/ppc/kernel/traps.c b/arch/ppc/kernel/traps.c index d2b0124f3177..c4c412e95222 100644 --- a/arch/ppc/kernel/traps.c +++ b/arch/ppc/kernel/traps.c @@ -123,6 +123,7 @@ MachineCheckException(struct pt_regs *regs) unsigned long msr = regs->msr; if (user_mode(regs)) { + regs->msr |= MSR_RI; _exception(SIGSEGV, regs); return; } @@ -134,6 +135,7 @@ MachineCheckException(struct pt_regs *regs) #endif if (debugger_fault_handler) { debugger_fault_handler(regs); + regs->msr |= MSR_RI; return; } diff --git a/arch/ppc/lib/string.S b/arch/ppc/lib/string.S index efab9d80b436..87bee0dbb84a 100644 --- a/arch/ppc/lib/string.S +++ b/arch/ppc/lib/string.S @@ -461,7 +461,7 @@ _GLOBAL(__copy_tofrom_user) 53: #if !defined(CONFIG_8xx) dcbt r3,r4 - dcbz r11,r6 +54: dcbz r11,r6 #endif /* had to move these to keep extable in order */ .section __ex_table,"a" @@ -470,7 +470,9 @@ _GLOBAL(__copy_tofrom_user) .long 71b,101f .long 72b,102f .long 73b,103f - .long 53b,105f +#if !defined(CONFIG_8xx) + .long 54b,105f +#endif .text /* the main body of the cacheline loop */ COPY_16_BYTES_WITHEX(0) @@ -613,11 +615,11 @@ _GLOBAL(__clear_user) add r4,r0,r4 subf r6,r0,r6 srwi r0,r4,2 + andi. r4,r4,3 mtctr r0 - bdz 6f + bdz 7f 1: stwu r5,4(r6) bdnz 1b -6: andi. r4,r4,3 /* clear byte sized chunks */ 7: cmpwi 0,r4,0 beqlr @@ -626,14 +628,20 @@ _GLOBAL(__clear_user) 8: stbu r5,1(r6) bdnz 8b blr -99: li r3,-EFAULT +90: mr r3,r4 + blr +91: mfctr r3 + slwi r3,r3,2 + add r3,r3,r4 + blr +92: mfctr r3 blr .section __ex_table,"a" .align 2 - .long 11b,99b - .long 1b,99b - .long 8b,99b + .long 11b,90b + .long 1b,91b + .long 8b,92b .text _GLOBAL(__strncpy_from_user) diff --git a/arch/ppc/mm/4xx_mmu.c b/arch/ppc/mm/4xx_mmu.c index bed7823c620e..22c54bbfc9c9 100644 --- a/arch/ppc/mm/4xx_mmu.c +++ b/arch/ppc/mm/4xx_mmu.c @@ -54,11 +54,6 @@ #include <asm/machdep.h> #include <asm/setup.h> -/* Used by the 4xx TLB replacement exception handler. - * Just needed it declared someplace (and initialized to zero). - */ -unsigned int tlb_4xx_index; - /* * MMU_init_hw does the chip-specific initialization of the MMU hardware. */ diff --git a/arch/ppc/mm/cachemap.c b/arch/ppc/mm/cachemap.c index 562cd9560de2..522f4cd67cdf 100644 --- a/arch/ppc/mm/cachemap.c +++ b/arch/ppc/mm/cachemap.c @@ -50,6 +50,8 @@ #include <asm/smp.h> #include <asm/machdep.h> +int map_page(unsigned long va, unsigned long pa, int flags); + /* This function will allocate the requested contiguous pages and * map them into the kernel's vmalloc() space. This is done so we * get unique mapping for these pages, outside of the kernel's 1:1 @@ -96,7 +98,7 @@ void *consistent_alloc(int gfp, size_t size, dma_addr_t *dma_handle) /* This gives us the real physical address of the first page. */ - *dma_handle = pa = virt_to_bus(page); + *dma_handle = pa = virt_to_bus((void *)page); flags = _PAGE_KERNEL | _PAGE_NO_CACHE; @@ -151,10 +153,10 @@ void consistent_sync(void *vaddr, size_t size, int direction) */ void consistent_sync_page(struct page *page, unsigned long offset, -size_t size, int direction) + size_t size, int direction) { unsigned long start; start = page_address(page) + offset; - consistent_sync(start, size, direction); + consistent_sync((void *)start, size, direction); } diff --git a/arch/ppc/mm/init.c b/arch/ppc/mm/init.c index 3ab677a690e4..b251dca15905 100644 --- a/arch/ppc/mm/init.c +++ b/arch/ppc/mm/init.c @@ -559,18 +559,19 @@ void flush_icache_page(struct vm_area_struct *vma, struct page *page) if (page->mapping && !PageReserved(page) && !test_bit(PG_arch_1, &page->flags)) { - phys = ((page - mem_map) << PAGE_SHIFT) + PPC_MEMSTART; + phys = page_to_pfn(page) << PAGE_SHIFT; __flush_dcache_icache_phys(phys); set_bit(PG_arch_1, &page->flags); } } -void clear_user_page(void *page, unsigned long vaddr) +void clear_user_page(void *page, unsigned long vaddr, struct page *pg) { clear_page(page); } -void copy_user_page(void *vto, void *vfrom, unsigned long vaddr) +void copy_user_page(void *vto, void *vfrom, unsigned long vaddr, + struct page *pg) { copy_page(vto, vfrom); __flush_dcache_icache(vto); diff --git a/arch/ppc/platforms/chrp_setup.c b/arch/ppc/platforms/chrp_setup.c index 0f5b93bc7457..a531cfdbf254 100644 --- a/arch/ppc/platforms/chrp_setup.c +++ b/arch/ppc/platforms/chrp_setup.c @@ -389,7 +389,6 @@ void __init chrp_init_IRQ(void) int i; unsigned long chrp_int_ack; unsigned char init_senses[NR_IRQS - NUM_8259_INTERRUPTS]; - int nmi_irq = -1; #if defined(CONFIG_VT) && defined(CONFIG_ADB_KEYBOARD) && defined(XMON) struct device_node *kbd; #endif @@ -412,7 +411,7 @@ void __init chrp_init_IRQ(void) OpenPIC_InitSenses = init_senses; OpenPIC_NumInitSenses = NR_IRQS - NUM_8259_INTERRUPTS; - openpic_init(1, NUM_8259_INTERRUPTS, nmi_irq); + openpic_init(NUM_8259_INTERRUPTS); for (i = 0; i < NUM_8259_INTERRUPTS; i++) irq_desc[i].handler = &i8259_pic; @@ -465,35 +464,6 @@ chrp_init2(void) #endif /* CONFIG_VT && (CONFIG_ADB_KEYBOARD || CONFIG_INPUT) */ } -/* - * One of the main thing these mappings are needed for is so that - * xmon can get to the serial port early on. We probably should - * handle the machines with the mpc106 as well as the python (F50) - * and the GG2 (longtrail). Actually we should look in the device - * tree and do the right thing. - */ -static void __init -chrp_map_io(void) -{ - char *name; - - /* - * The code below tends to get removed, please don't take it out. - * The F50 needs this mapping and it you take it out I'll track you - * down and slap your hands. If it causes problems please email me. - * -- Cort <cort@fsmlabs.com> - */ - name = get_property(find_path_device("/"), "name", NULL); - if (name && strncmp(name, "IBM-70", 6) == 0 - && strstr(name, "-F50")) { - io_block_mapping(0x80000000, 0x80000000, 0x10000000, _PAGE_IO); - io_block_mapping(0x90000000, 0x90000000, 0x10000000, _PAGE_IO); - return; - } else { - io_block_mapping(0xf8000000, 0xf8000000, 0x04000000, _PAGE_IO); - } -} - void __init chrp_init(unsigned long r3, unsigned long r4, unsigned long r5, unsigned long r6, unsigned long r7) @@ -531,7 +501,6 @@ chrp_init(unsigned long r3, unsigned long r4, unsigned long r5, ppc_md.calibrate_decr = chrp_calibrate_decr; ppc_md.find_end_of_memory = pmac_find_end_of_memory; - ppc_md.setup_io_mappings = chrp_map_io; #ifdef CONFIG_VT /* these are adjusted in chrp_init2 if we have an ADB keyboard */ diff --git a/arch/ppc/platforms/ep405.c b/arch/ppc/platforms/ep405.c index c6e41fb508c3..c4a67dec932f 100644 --- a/arch/ppc/platforms/ep405.c +++ b/arch/ppc/platforms/ep405.c @@ -65,12 +65,10 @@ board_setup_arch(void) { bd_t *bip = (bd_t *) __res; -#ifdef CONFIG_PPC_RTC if (bip->bi_nvramsize == 512*1024) { /* FIXME: we should properly handle NVRTCs of different sizes */ TODC_INIT(TODC_TYPE_DS1557, ep405_nvram, ep405_nvram, ep405_nvram, 8); } -#endif } void __init @@ -178,9 +176,9 @@ board_setup_irq(void) void __init board_init(void) { +#ifdef CONFIG_PPC_RTC bd_t *bip = (bd_t *) __res; -#ifdef CONFIG_PPC_RTC /* FIXME: we should be able to access the NVRAM even if PPC_RTC is not configured */ ppc_md.nvram_read_val = todc_direct_read_val; ppc_md.nvram_write_val = todc_direct_write_val; diff --git a/arch/ppc/platforms/lopec_setup.c b/arch/ppc/platforms/lopec_setup.c index 6d26d22826ee..2c63c6f8ad5c 100644 --- a/arch/ppc/platforms/lopec_setup.c +++ b/arch/ppc/platforms/lopec_setup.c @@ -207,7 +207,7 @@ lopec_init_IRQ(void) /* Skip reserved space and map Message Unit Interrupt (I2O) */ openpic_set_sources(19, 1, OpenPIC_Addr + 0x110C0); - openpic_init(1, NUM_8259_INTERRUPTS, -1); + openpic_init(NUM_8259_INTERRUPTS); /* Map i8259 interrupts */ for(i = 0; i < NUM_8259_INTERRUPTS; i++) diff --git a/arch/ppc/platforms/mbx.h b/arch/ppc/platforms/mbx.h index e4896dd357f3..6ef7a37ea9b9 100644 --- a/arch/ppc/platforms/mbx.h +++ b/arch/ppc/platforms/mbx.h @@ -88,11 +88,33 @@ typedef struct bd_info { #define ISA_BRIDGE_INT SIU_IRQ3 /* All those PC things */ #define COMM_L_INT SIU_IRQ6 /* MBX Comm expansion connector pin */ #define STOP_ABRT_INT SIU_IRQ7 /* Stop/Abort header pin */ -#endif /* !__ASSEMBLY__ */ + +/* CPM Ethernet through SCCx. + * + * Bits in parallel I/O port registers that have to be set/cleared + * to configure the pins for SCC1 use. The TCLK and RCLK seem unique + * to the MBX860 board. Any two of the four available clocks could be + * used, and the MPC860 cookbook manual has an example using different + * clock pins. + */ +#define PA_ENET_RXD ((ushort)0x0001) +#define PA_ENET_TXD ((ushort)0x0002) +#define PA_ENET_TCLK ((ushort)0x0200) +#define PA_ENET_RCLK ((ushort)0x0800) +#define PC_ENET_TENA ((ushort)0x0001) +#define PC_ENET_CLSN ((ushort)0x0010) +#define PC_ENET_RENA ((ushort)0x0020) + +/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to + * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. + */ +#define SICR_ENET_MASK ((uint)0x000000ff) +#define SICR_ENET_CLKRT ((uint)0x0000003d) /* The MBX uses the 8259. */ #define NR_8259_INTS 16 -#endif +#endif /* !__ASSEMBLY__ */ +#endif /* __MACH_MBX_DEFS */ #endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/pmac_nvram.c b/arch/ppc/platforms/pmac_nvram.c index eebac822e709..a6a73475c342 100644 --- a/arch/ppc/platforms/pmac_nvram.c +++ b/arch/ppc/platforms/pmac_nvram.c @@ -18,6 +18,7 @@ #include <linux/module.h> #include <linux/kernel.h> #include <linux/stddef.h> +#include <linux/string.h> #include <linux/nvram.h> #include <linux/init.h> #include <linux/slab.h> diff --git a/arch/ppc/platforms/pmac_pic.c b/arch/ppc/platforms/pmac_pic.c index afb8c61eb554..5ee8e42e0bdd 100644 --- a/arch/ppc/platforms/pmac_pic.c +++ b/arch/ppc/platforms/pmac_pic.c @@ -375,26 +375,28 @@ pmac_pic_init(void) printk("PowerMac using OpenPIC irq controller\n"); if (irqctrler->n_addrs > 0) { - int nmi_irq = -1; unsigned char senses[NR_IRQS]; -#ifdef CONFIG_XMON - struct device_node* pswitch; - pswitch = find_devices("programmer-switch"); - if (pswitch && pswitch->n_intrs) - nmi_irq = pswitch->intrs[0].line; -#endif /* CONFIG_XMON */ prom_get_irq_senses(senses, 0, NR_IRQS); OpenPIC_InitSenses = senses; OpenPIC_NumInitSenses = NR_IRQS; ppc_md.get_irq = openpic_get_irq; OpenPIC_Addr = ioremap(irqctrler->addrs[0].address, irqctrler->addrs[0].size); - openpic_init(1, 0, nmi_irq); + openpic_init(0); #ifdef CONFIG_XMON - if (nmi_irq >= 0) - request_irq(nmi_irq, xmon_irq, 0, - "NMI - XMON", 0); + { + struct device_node* pswitch; + int nmi_irq; + + pswitch = find_devices("programmer-switch"); + if (pswitch && pswitch->n_intrs) { + nmi_irq = pswitch->intrs[0].line; + openpic_init_nmi_irq(nmi_irq); + request_irq(nmi_irq, xmon_irq, 0, + "NMI - XMON", 0); + } + } #endif /* CONFIG_XMON */ return; } diff --git a/arch/ppc/platforms/prep_pci.c b/arch/ppc/platforms/prep_pci.c index 410355095d9c..d7462ee15c98 100644 --- a/arch/ppc/platforms/prep_pci.c +++ b/arch/ppc/platforms/prep_pci.c @@ -665,9 +665,9 @@ static struct pci_ops prep_pci_ops = #define MPIC_HAWK_ID 0x48030000 #define MOT_PROC2_BIT 0x800 -static u_char mvme2600_openpic_initsenses[] __initdata = { - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_SIO */ - (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* MVME2600_INT_FALCN_ECC_ERR */ +static u_char prep_openpic_initsenses[] __initdata = { + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* MVME2600_INT_SIO */ + (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_FALCON_ECC_ERR */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_ETHERNET */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_SCSI */ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_GRAPHICS */ @@ -737,8 +737,8 @@ raven_init(void) /* Map the Raven MPIC registers to virtual memory. */ OpenPIC_Addr = ioremap(pci_membase+0xC0000000, 0x22000); - OpenPIC_InitSenses = mvme2600_openpic_initsenses; - OpenPIC_NumInitSenses = sizeof(mvme2600_openpic_initsenses); + OpenPIC_InitSenses = prep_openpic_initsenses; + OpenPIC_NumInitSenses = sizeof(prep_openpic_initsenses); ppc_md.get_irq = openpic_get_irq; @@ -821,6 +821,9 @@ ibm_prep_init(void) addr += PREP_ISA_MEM_BASE; OpenPIC_Addr = ioremap(addr, 0x40000); ppc_md.get_irq = openpic_get_irq; + + OpenPIC_InitSenses = prep_openpic_initsenses; + OpenPIC_NumInitSenses = sizeof(prep_openpic_initsenses); } } diff --git a/arch/ppc/platforms/prep_setup.c b/arch/ppc/platforms/prep_setup.c index 1b49c2542bcd..ce9b00fe4eff 100644 --- a/arch/ppc/platforms/prep_setup.c +++ b/arch/ppc/platforms/prep_setup.c @@ -692,7 +692,7 @@ prep_init_IRQ(void) int i; if (OpenPIC_Addr != NULL) - openpic_init(1, NUM_8259_INTERRUPTS, -1); + openpic_init(NUM_8259_INTERRUPTS); for ( i = 0 ; i < NUM_8259_INTERRUPTS ; i++ ) irq_desc[i].handler = &i8259_pic; i8259_init(MPC10X_MAPA_PCI_INTACK_ADDR); diff --git a/arch/ppc/platforms/rpxclassic.h b/arch/ppc/platforms/rpxclassic.h index 8d994808d547..6de25d1e8d56 100644 --- a/arch/ppc/platforms/rpxclassic.h +++ b/arch/ppc/platforms/rpxclassic.h @@ -94,11 +94,31 @@ extern bd_t m8xx_board_info; */ #define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ -#endif /* !__ASSEMBLY__ */ + +/* CPM Ethernet through SCCx. + * + * Bits in parallel I/O port registers that have to be set/cleared + * to configure the pins for SCC1 use. + */ +#define PA_ENET_RXD ((ushort)0x0001) +#define PA_ENET_TXD ((ushort)0x0002) +#define PA_ENET_TCLK ((ushort)0x0200) +#define PA_ENET_RCLK ((ushort)0x0800) +#define PB_ENET_TENA ((uint)0x00001000) +#define PC_ENET_CLSN ((ushort)0x0010) +#define PC_ENET_RENA ((ushort)0x0020) + +/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to + * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. + */ +#define SICR_ENET_MASK ((uint)0x000000ff) +#define SICR_ENET_CLKRT ((uint)0x0000003d) /* We don't use the 8259. */ + #define NR_8259_INTS 0 -#endif +#endif /* !__ASSEMBLY__ */ +#endif /* __MACH_RPX_DEFS */ #endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/rpxlite.h b/arch/ppc/platforms/rpxlite.h index e5fb50376ec6..3f4ddc38c123 100644 --- a/arch/ppc/platforms/rpxlite.h +++ b/arch/ppc/platforms/rpxlite.h @@ -65,7 +65,6 @@ extern bd_t m8xx_board_info; #if defined(CONFIG_HTDMSOUND) #include <platforms/rpxhiox.h> #endif -#endif /* !__ASSEMBLY__ */ /* define IO_BASE for pcmcia */ #define _IO_BASE 0x80000000 @@ -76,9 +75,27 @@ extern bd_t m8xx_board_info; # define request_irq(irq,hand,flg,dev,id) request_8xxirq((irq),(hand),(flg),(dev),(id)) #endif +/* CPM Ethernet through SCCx. + * + * This ENET stuff is for the MPC850 with ethernet on SCC2. Some of + * this may be unique to the RPX-Lite configuration. + * Note TENA is on Port B. + */ +#define PA_ENET_RXD ((ushort)0x0004) +#define PA_ENET_TXD ((ushort)0x0008) +#define PA_ENET_TCLK ((ushort)0x0200) +#define PA_ENET_RCLK ((ushort)0x0800) +#define PB_ENET_TENA ((uint)0x00002000) +#define PC_ENET_CLSN ((ushort)0x0040) +#define PC_ENET_RENA ((ushort)0x0080) + +#define SICR_ENET_MASK ((uint)0x0000ff00) +#define SICR_ENET_CLKRT ((uint)0x00003d00) + /* We don't use the 8259. */ #define NR_8259_INTS 0 -#endif +#endif /* !__ASSEMBLY__ */ +#endif /* __MACH_RPX_DEFS */ #endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/spd8xx.h b/arch/ppc/platforms/spd8xx.h index b6c93bdfd10f..378840573585 100644 --- a/arch/ppc/platforms/spd8xx.h +++ b/arch/ppc/platforms/spd8xx.h @@ -15,6 +15,7 @@ #include <asm/ppcboot.h> +#ifndef __ASSEMBLY__ #define SPD_IMMR_BASE 0xFFF00000 /* phys. addr of IMMR */ #define SPD_IMAP_SIZE (64 * 1024) /* size of mapped area */ @@ -61,9 +62,34 @@ #define IDE1_CONTROL_REG_OFFSET 0x0106 #define IDE1_IRQ_REG_OFFSET 0x000A /* not used */ +/* CPM Ethernet through SCCx. + * + * Bits in parallel I/O port registers that have to be set/cleared + * to configure the pins for SCC2 use. + */ +#define PA_ENET_MDC ((ushort)0x0001) /* PA 15 !!! */ +#define PA_ENET_MDIO ((ushort)0x0002) /* PA 14 !!! */ +#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ +#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ +#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ +#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ + +#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ + +#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ +#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ +#define PC_ENET_RESET ((ushort)0x0100) /* PC 7 !!! */ + +/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to + * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. + */ +#define SICR_ENET_MASK ((uint)0x0000ff00) +#define SICR_ENET_CLKRT ((uint)0x00002E00) + /* We don't use the 8259. */ #define NR_8259_INTS 0 +#endif /* !__ASSEMBLY__ */ #endif /* __ASM_SPD8XX_H__ */ #endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/tqm8xx.h b/arch/ppc/platforms/tqm8xx.h index fb5b4df54e8a..4df3328ae015 100644 --- a/arch/ppc/platforms/tqm8xx.h +++ b/arch/ppc/platforms/tqm8xx.h @@ -7,6 +7,7 @@ * Copyright (c) 1999,2000,2001 Wolfgang Denk (wd@denx.de) */ +#ifdef __KERNEL__ #ifndef __MACH_TQM8xx_H #define __MACH_TQM8xx_H @@ -14,6 +15,7 @@ #include <asm/ppcboot.h> +#ifndef __ASSEMBLY__ #define TQM_IMMR_BASE 0xFFF00000 /* phys. addr of IMMR */ #define TQM_IMAP_SIZE (64 * 1024) /* size of mapped area */ @@ -47,8 +49,106 @@ #define IDE0_INTERRUPT 13 +/*----------------------------------------------------------------------- + * CPM Ethernet through SCCx. + *----------------------------------------------------------------------- + * + */ + +/*** TQM823L, TQM850L ***********************************************/ + +#if defined(CONFIG_TQM823L) || defined(CONFIG_TQM850L) +/* Bits in parallel I/O port registers that have to be set/cleared + * to configure the pins for SCC1 use. + */ +#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ +#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ +#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ +#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ + +#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ + +#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ +#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ + +/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to + * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. + */ +#define SICR_ENET_MASK ((uint)0x0000ff00) +#define SICR_ENET_CLKRT ((uint)0x00002600) +#endif /* CONFIG_TQM823L, CONFIG_TQM850L */ + +/*** TQM860L ********************************************************/ + +#ifdef CONFIG_TQM860L +/* Bits in parallel I/O port registers that have to be set/cleared + * to configure the pins for SCC1 use. + */ +#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ +#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ +#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ +#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ + +#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ +#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ +#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ + +/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to + * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. + */ +#define SICR_ENET_MASK ((uint)0x000000ff) +#define SICR_ENET_CLKRT ((uint)0x00000026) +#endif /* CONFIG_TQM860L */ + +/*** FPS850L *********************************************************/ + +#ifdef CONFIG_FPS850L +/* Bits in parallel I/O port registers that have to be set/cleared + * to configure the pins for SCC1 use. + */ +#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ +#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ +#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ +#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ + +#define PC_ENET_TENA ((ushort)0x0002) /* PC 14 */ +#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ +#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ + +/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to + * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. + */ +#define SICR_ENET_MASK ((uint)0x0000ff00) +#define SICR_ENET_CLKRT ((uint)0x00002600) +#endif /* CONFIG_FPS850L */ + +/*** SM850 *********************************************************/ + +/* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */ + +#ifdef CONFIG_SM850 +#define PB_ENET_RXD ((uint)0x00000004) /* PB 29 */ +#define PB_ENET_TXD ((uint)0x00000002) /* PB 30 */ +#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ +#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ + +#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */ +#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */ + +#define PC_ENET_RENA ((ushort)0x0800) /* PC 4 */ +#define PC_ENET_CLSN ((ushort)0x0400) /* PC 5 */ + +/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to + * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero. + */ +#define SICR_ENET_MASK ((uint)0x00FF0000) +#define SICR_ENET_CLKRT ((uint)0x00260000) +#endif /* CONFIG_SM850 */ + /* We don't use the 8259. */ #define NR_8259_INTS 0 +#endif /* !__ASSEMBLY__ */ #endif /* __MACH_TQM8xx_H */ +#endif /* __KERNEL__ */ diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h index 31e598b27c58..457c183a0601 100644 --- a/drivers/char/drm/radeon_drv.h +++ b/drivers/char/drm/radeon_drv.h @@ -477,6 +477,7 @@ extern int radeon_cp_flip( struct inode *inode, struct file *filp, # define RADEON_CNTL_HOSTDATA_BLT 0x00009400 # define RADEON_CNTL_PAINT_MULTI 0x00009A00 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00 +# define RADEON_CNTL_SET_SCISSORS 0xC0001E00 #define RADEON_CP_PACKET_MASK 0xC0000000 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 diff --git a/drivers/char/drm/radeon_state.c b/drivers/char/drm/radeon_state.c index 3a73c5e563ac..db7bc9109e40 100644 --- a/drivers/char/drm/radeon_state.c +++ b/drivers/char/drm/radeon_state.c @@ -48,12 +48,10 @@ static inline void radeon_emit_clip_rect( drm_radeon_private_t *dev_priv, DRM_DEBUG( " box: x1=%d y1=%d x2=%d y2=%d\n", box->x1, box->y1, box->x2, box->y2 ); - BEGIN_RING( 4 ); - OUT_RING( CP_PACKET0( RADEON_RE_TOP_LEFT, 0 ) ); + BEGIN_RING( 3 ); + OUT_RING( CP_PACKET3( RADEON_CNTL_SET_SCISSORS, 1 )); OUT_RING( (box->y1 << 16) | box->x1 ); - OUT_RING( CP_PACKET0( RADEON_RE_WIDTH_HEIGHT, 0 ) ); -/* OUT_RING( ((box->y2 - 1) << 16) | (box->x2 - 1) );*/ - OUT_RING( (box->y2 << 16) | box->x2 ); + OUT_RING( ((box->y2 - 1) << 16) | (box->x2 - 1) ); ADVANCE_RING(); } diff --git a/drivers/ide/probe.c b/drivers/ide/probe.c index 3081e8b76cf1..b1b026f76cfc 100644 --- a/drivers/ide/probe.c +++ b/drivers/ide/probe.c @@ -1143,6 +1143,7 @@ static void channel_init(struct ata_channel *ch) if (!gd) goto err_kmalloc_gd; + memset(gd, 0, sizeof(struct gendisk)); gd->sizes = kmalloc(ATA_MINORS * sizeof(int), GFP_KERNEL); if (!gd->sizes) goto err_kmalloc_gd_sizes; diff --git a/include/asm-ppc/commproc.h b/include/asm-ppc/commproc.h index 46284e91f571..5b80101564ee 100644 --- a/include/asm-ppc/commproc.h +++ b/include/asm-ppc/commproc.h @@ -382,213 +382,6 @@ typedef struct scc_enet { ushort sen_taddrl; /* temp address (LSB) */ } scc_enet_t; -/*** MBX ************************************************************/ - -#ifdef CONFIG_MBX -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. The TCLK and RCLK seem unique - * to the MBX860 board. Any two of the four available clocks could be - * used, and the MPC860 cookbook manual has an example using different - * clock pins. - */ -#define PA_ENET_RXD ((ushort)0x0001) -#define PA_ENET_TXD ((ushort)0x0002) -#define PA_ENET_TCLK ((ushort)0x0200) -#define PA_ENET_RCLK ((ushort)0x0800) -#define PC_ENET_TENA ((ushort)0x0001) -#define PC_ENET_CLSN ((ushort)0x0010) -#define PC_ENET_RENA ((ushort)0x0020) - -/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to - * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. - */ -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x0000003d) -#endif /* CONFIG_MBX */ - -/*** RPXLITE ********************************************************/ - -#ifdef CONFIG_RPXLITE -/* This ENET stuff is for the MPC850 with ethernet on SCC2. Some of - * this may be unique to the RPX-Lite configuration. - * Note TENA is on Port B. - */ -#define PA_ENET_RXD ((ushort)0x0004) -#define PA_ENET_TXD ((ushort)0x0008) -#define PA_ENET_TCLK ((ushort)0x0200) -#define PA_ENET_RCLK ((ushort)0x0800) -#define PB_ENET_TENA ((uint)0x00002000) -#define PC_ENET_CLSN ((ushort)0x0040) -#define PC_ENET_RENA ((ushort)0x0080) - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00003d00) -#endif /* CONFIG_RPXLITE */ - -/*** BSEIP **********************************************************/ - -#ifdef CONFIG_BSEIP -/* This ENET stuff is for the MPC823 with ethernet on SCC2. - * This is unique to the BSE ip-Engine board. - */ -#define PA_ENET_RXD ((ushort)0x0004) -#define PA_ENET_TXD ((ushort)0x0008) -#define PA_ENET_TCLK ((ushort)0x0100) -#define PA_ENET_RCLK ((ushort)0x0200) -#define PB_ENET_TENA ((uint)0x00002000) -#define PC_ENET_CLSN ((ushort)0x0040) -#define PC_ENET_RENA ((ushort)0x0080) - -/* BSE uses port B and C bits for PHY control also. -*/ -#define PB_BSE_POWERUP ((uint)0x00000004) -#define PB_BSE_FDXDIS ((uint)0x00008000) -#define PC_BSE_LOOPBACK ((ushort)0x0800) - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002c00) -#endif /* CONFIG_BSEIP */ - -/*** RPXCLASSIC *****************************************************/ - -#ifdef CONFIG_RPXCLASSIC -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. - */ -#define PA_ENET_RXD ((ushort)0x0001) -#define PA_ENET_TXD ((ushort)0x0002) -#define PA_ENET_TCLK ((ushort)0x0200) -#define PA_ENET_RCLK ((ushort)0x0800) -#define PB_ENET_TENA ((uint)0x00001000) -#define PC_ENET_CLSN ((ushort)0x0010) -#define PC_ENET_RENA ((ushort)0x0020) - -/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to - * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. - */ -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x0000003d) -#endif /* CONFIG_RPXCLASSIC */ - -/*** TQM823L, TQM850L ***********************************************/ - -#if defined(CONFIG_TQM823L) || defined(CONFIG_TQM850L) -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. - */ -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ - -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to - * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - */ -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002600) -#endif /* CONFIG_TQM823L, CONFIG_TQM850L */ - -/*** FPS850L *********************************************************/ - -#ifdef CONFIG_FPS850L -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. - */ -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PC_ENET_TENA ((ushort)0x0002) /* PC 14 */ -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ - -/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to - * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - */ -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002600) -#endif /* CONFIG_FPS850L */ - -/*** TQM860L ********************************************************/ - -#ifdef CONFIG_TQM860L -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. - */ -#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ -#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ -#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ -#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ -#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to - * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. - */ -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x00000026) -#endif /* CONFIG_TQM860L */ - -/*** SPD823TS *******************************************************/ - -#ifdef CONFIG_SPD823TS -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC2 use. - */ -#define PA_ENET_MDC ((ushort)0x0001) /* PA 15 !!! */ -#define PA_ENET_MDIO ((ushort)0x0002) /* PA 14 !!! */ -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ - -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ -#define PC_ENET_RESET ((ushort)0x0100) /* PC 7 !!! */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to - * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - */ -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002E00) -#endif /* CONFIG_SPD823TS */ - - -/*** SM850 *********************************************************/ - -/* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */ - -#ifdef CONFIG_SM850 -#define PB_ENET_RXD ((uint)0x00000004) /* PB 29 */ -#define PB_ENET_TXD ((uint)0x00000002) /* PB 30 */ -#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */ -#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */ - -#define PC_ENET_RENA ((ushort)0x0800) /* PC 4 */ -#define PC_ENET_CLSN ((ushort)0x0400) /* PC 5 */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to - * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero. - */ -#define SICR_ENET_MASK ((uint)0x00FF0000) -#define SICR_ENET_CLKRT ((uint)0x00260000) -#endif /* CONFIG_SM850 */ - -/*********************************************************************/ - /* SCC Event register as used by Ethernet. */ #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ diff --git a/include/asm-ppc/open_pic.h b/include/asm-ppc/open_pic.h index e7469eae6796..b22bf942b63d 100644 --- a/include/asm-ppc/open_pic.h +++ b/include/asm-ppc/open_pic.h @@ -55,7 +55,8 @@ extern void* OpenPIC_Addr; /* Exported functions */ extern void openpic_set_sources(int first_irq, int num_irqs, void *isr); -extern void openpic_init(int, int, int); +extern void openpic_init(int linux_irq_offset); +extern void openpic_init_nmi_irq(u_int irq); extern u_int openpic_irq(void); extern void openpic_eoi(void); extern void openpic_request_IPIs(void); diff --git a/include/asm-ppc/page.h b/include/asm-ppc/page.h index 3c24d005f8e4..4a2d88d43724 100644 --- a/include/asm-ppc/page.h +++ b/include/asm-ppc/page.h @@ -85,10 +85,12 @@ typedef unsigned long pgprot_t; /* to align the pointer to the (next) page boundary */ #define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK) +struct page; extern void clear_page(void *page); extern void copy_page(void *to, void *from); -extern void clear_user_page(void *page, unsigned long vaddr); -extern void copy_user_page(void *to, void *from, unsigned long vaddr); +extern void clear_user_page(void *page, unsigned long vaddr, struct page *pg); +extern void copy_user_page(void *to, void *from, unsigned long vaddr, + struct page *pg); #ifndef CONFIG_APUS #define PPC_MEMSTART 0 diff --git a/include/asm-ppc/param.h b/include/asm-ppc/param.h index 259af01bbe8d..3d399e0f5b07 100644 --- a/include/asm-ppc/param.h +++ b/include/asm-ppc/param.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.param.h 1.8 08/20/01 22:50:29 paulus + * BK Id: %F% %I% %G% %U% %#% */ #ifndef _ASM_PPC_PARAM_H #define _ASM_PPC_PARAM_H @@ -8,6 +8,12 @@ #define HZ 100 #endif +#ifdef __KERNEL__ +#define HZ 100 /* internal timer frequency */ +#define USER_HZ 100 /* for user interfaces in "ticks" */ +#define CLOCKS_PER_SEC (USER_HZ) /* frequency at which times() counts */ +#endif + #define EXEC_PAGESIZE 4096 #ifndef NGROUPS @@ -20,8 +26,4 @@ #define MAXHOSTNAMELEN 64 /* max length of hostname */ -#ifdef __KERNEL__ -# define CLOCKS_PER_SEC HZ /* frequency at which times() counts */ -#endif - #endif diff --git a/include/asm-ppc/ppc_asm.h b/include/asm-ppc/ppc_asm.h index 0c33c12f3939..fc8516cb4f12 100644 --- a/include/asm-ppc/ppc_asm.h +++ b/include/asm-ppc/ppc_asm.h @@ -49,22 +49,13 @@ #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base) #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) -/* - * Once a version of gas that understands the AltiVec instructions - * is freely available, we can do this the normal way... - paulus - */ -#define LVX(r,a,b) .long (31<<26)+((r)<<21)+((a)<<16)+((b)<<11)+(103<<1) -#define STVX(r,a,b) .long (31<<26)+((r)<<21)+((a)<<16)+((b)<<11)+(231<<1) -#define MFVSCR(r) .long (4<<26)+((r)<<21)+(770<<1) -#define MTVSCR(r) .long (4<<26)+((r)<<11)+(802<<1) - -#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); STVX(n,b,base) +#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base #define SAVE_2VR(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) #define SAVE_4VR(n,b,base) SAVE_2VR(n,b,base); SAVE_2VR(n+2,b,base) #define SAVE_8VR(n,b,base) SAVE_4VR(n,b,base); SAVE_4VR(n+4,b,base) #define SAVE_16VR(n,b,base) SAVE_8VR(n,b,base); SAVE_8VR(n+8,b,base) #define SAVE_32VR(n,b,base) SAVE_16VR(n,b,base); SAVE_16VR(n+16,b,base) -#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); LVX(n,b,base) +#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base #define REST_2VR(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) #define REST_4VR(n,b,base) REST_2VR(n,b,base); REST_2VR(n+2,b,base) #define REST_8VR(n,b,base) REST_4VR(n,b,base); REST_4VR(n+4,b,base) @@ -169,7 +160,11 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601) #else #define FIX_SRR1(ra, rb) +#ifndef CONFIG_40x #define RFI rfi +#else +#define RFI rfi; b . /* Prevent prefetch past rfi */ +#endif #define MTMSRD(r) mtmsr r #define CLR_TOP32(r) #endif /* CONFIG_PPC64BRIDGE */ diff --git a/include/asm-ppc/system.h b/include/asm-ppc/system.h index abd9620c9950..920752c47576 100644 --- a/include/asm-ppc/system.h +++ b/include/asm-ppc/system.h @@ -57,10 +57,14 @@ extern void hard_reset_now(void); extern void poweroff_now(void); #ifdef CONFIG_6xx extern long _get_L2CR(void); +extern long _get_L3CR(void); extern void _set_L2CR(unsigned long); +extern void _set_L3CR(unsigned long); #else #define _get_L2CR() 0L +#define _get_L3CR() 0L #define _set_L2CR(val) do { } while(0) +#define _set_L3CR(val) do { } while(0) #endif extern void via_cuda_init(void); extern void pmac_nvram_init(void); @@ -79,9 +83,14 @@ extern void cacheable_memzero(void *p, unsigned int nb); struct device_node; extern void note_scsi_host(struct device_node *, void *); +#define prepare_arch_schedule(prev) do { } while(0) +#define finish_arch_schedule(prev) do { } while(0) +#define prepare_arch_switch(rq) do { } while(0) +#define finish_arch_switch(rq) spin_unlock_irq(&(rq)->lock) + struct task_struct; -#define prepare_to_switch() do { } while(0) -extern void switch_to(struct task_struct *, struct task_struct *); +extern void __switch_to(struct task_struct *, struct task_struct *); +#define switch_to(prev, next, last) __switch_to((prev), (next)) struct thread_struct; extern struct task_struct *_switch(struct thread_struct *prev, diff --git a/include/asm-ppc/tlbflush.h b/include/asm-ppc/tlbflush.h index 83e6f1ae6c35..af4295e46861 100644 --- a/include/asm-ppc/tlbflush.h +++ b/include/asm-ppc/tlbflush.h @@ -21,21 +21,20 @@ extern void _tlbie(unsigned long address); extern void _tlbia(void); #if defined(CONFIG_4xx) -#define __tlbia() asm volatile ("tlbia; sync" : : : "memory") static inline void flush_tlb_all(void) - { __tlbia(); } + { _tlbia(); } static inline void flush_tlb_mm(struct mm_struct *mm) - { __tlbia(); } + { _tlbia(); } static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr) { _tlbie(vmaddr); } static inline void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) - { __tlbia(); } + { _tlbia(); } static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end) - { __tlbia(); } + { _tlbia(); } #define update_mmu_cache(vma, addr, pte) do { } while (0) #elif defined(CONFIG_8xx) diff --git a/include/asm-ppc/uaccess.h b/include/asm-ppc/uaccess.h index 21462ee88b4b..0087efbb0d6a 100644 --- a/include/asm-ppc/uaccess.h +++ b/include/asm-ppc/uaccess.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.uaccess.h 1.8 09/11/01 18:10:06 paulus + * BK Id: %F% %I% %G% %U% %#% */ #ifdef __KERNEL__ #ifndef _PPC_UACCESS_H @@ -272,7 +272,11 @@ clear_user(void *addr, unsigned long size) { if (access_ok(VERIFY_WRITE, addr, size)) return __clear_user(addr, size); - return size? -EFAULT: 0; + if ((unsigned long)addr < TASK_SIZE) { + unsigned long over = (unsigned long)addr + size - TASK_SIZE; + return __clear_user(addr, size - over) + over; + } + return size; } extern int __strncpy_from_user(char *dst, const char *src, long count); |