diff options
Diffstat (limited to 'Documentation/devicetree/bindings/fpga/fpga-region.yaml')
| -rw-r--r-- | Documentation/devicetree/bindings/fpga/fpga-region.yaml | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/Documentation/devicetree/bindings/fpga/fpga-region.yaml b/Documentation/devicetree/bindings/fpga/fpga-region.yaml index 7d2d3b7aa4b7..55acf0ecfa3f 100644 --- a/Documentation/devicetree/bindings/fpga/fpga-region.yaml +++ b/Documentation/devicetree/bindings/fpga/fpga-region.yaml @@ -18,7 +18,6 @@ description: | - Supported Use Models - Constraints - Introduction ============ @@ -31,7 +30,6 @@ description: | document isn't a replacement for any manufacturers specifications for FPGA usage. - Terminology =========== @@ -108,7 +106,6 @@ description: | a soft logic bridge (Bridge0-2) in the FPGA. The contents of each PRR can be reprogrammed independently while the rest of the system continues to function. - Sequence ======== @@ -124,7 +121,6 @@ description: | When the overlay is removed, the child nodes will be removed and the FPGA Region will disable the bridges. - FPGA Region =========== @@ -170,7 +166,6 @@ description: | hardware bridges remain enabled. The PR regions' bridges will be FPGA bridges within the static image of the FPGA. - Supported Use Models ==================== @@ -215,9 +210,9 @@ description: | FPGA Bridges that exist on the FPGA fabric prior to the partial reconfiguration. -- - [1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf + [1] https://www.intel.com/programmable/technical-pdfs/683404.pdf [2] tspace.library.utoronto.ca/bitstream/1807/67932/1/Byma_Stuart_A_201411_MAS_thesis.pdf - [3] https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf + [3] https://docs.amd.com/v/u/en-US/ug702 properties: $nodename: |