diff options
Diffstat (limited to 'arch/arm64')
680 files changed, 54499 insertions, 13128 deletions
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index b1d1f2ff2493..6663ffd23f25 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -100,7 +100,7 @@ config ARM64 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN select ARCH_SUPPORTS_LTO_CLANG_THIN - select ARCH_SUPPORTS_CFI_CLANG + select ARCH_SUPPORTS_CFI select ARCH_SUPPORTS_ATOMIC_RMW select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 select ARCH_SUPPORTS_NUMA_BALANCING @@ -108,6 +108,9 @@ config ARM64 select ARCH_SUPPORTS_PER_VMA_LOCK select ARCH_SUPPORTS_HUGE_PFNMAP if TRANSPARENT_HUGEPAGE select ARCH_SUPPORTS_RT + select ARCH_SUPPORTS_SCHED_SMT + select ARCH_SUPPORTS_SCHED_CLUSTER + select ARCH_SUPPORTS_SCHED_MC select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT select ARCH_WANT_DEFAULT_BPF_JIT @@ -151,6 +154,7 @@ config ARM64 select GENERIC_EARLY_IOREMAP select GENERIC_IDLE_POLL_SETUP select GENERIC_IOREMAP + select GENERIC_IRQ_ENTRY select GENERIC_IRQ_IPI select GENERIC_IRQ_KEXEC_CLEAR_VM_FORWARD select GENERIC_IRQ_PROBE @@ -162,8 +166,6 @@ config ARM64 select GENERIC_SMP_IDLE_THREAD select GENERIC_TIME_VSYSCALL select GENERIC_GETTIMEOFDAY - select GENERIC_VDSO_DATA_STORE - select GENERIC_VDSO_TIME_NS select HARDIRQS_SW_RESEND select HAS_IOPORT select HAVE_MOVE_PMD @@ -212,7 +214,7 @@ config ARM64 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \ if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \ - if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \ + if (DYNAMIC_FTRACE_WITH_ARGS && !CFI && \ (CC_IS_CLANG || !CC_OPTIMIZE_FOR_SIZE)) select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ if DYNAMIC_FTRACE_WITH_ARGS @@ -1138,6 +1140,7 @@ config ARM64_ERRATUM_3194386 * ARM Neoverse-V1 erratum 3324341 * ARM Neoverse V2 erratum 3324336 * ARM Neoverse-V3 erratum 3312417 + * ARM Neoverse-V3AE erratum 3312417 On affected cores "MSR SSBS, #0" instructions may not affect subsequent speculative instructions, which may permit unexepected @@ -1492,8 +1495,7 @@ choice config CPU_BIG_ENDIAN bool "Build big-endian kernel" - # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c - depends on AS_IS_GNU || AS_VERSION >= 150000 + depends on BROKEN help Say Y if you plan on running a kernel with a big-endian userspace. @@ -1505,29 +1507,6 @@ config CPU_LITTLE_ENDIAN endchoice -config SCHED_MC - bool "Multi-core scheduler support" - help - Multi-core scheduler support improves the CPU scheduler's decision - making when dealing with multi-core CPU chips at a cost of slightly - increased overhead in some places. If unsure say N here. - -config SCHED_CLUSTER - bool "Cluster scheduler support" - help - Cluster scheduler support improves the CPU scheduler's decision - making when dealing with machines that have clusters of CPUs. - Cluster usually means a couple of CPUs which are placed closely - by sharing mid-level caches, last-level cache tags or internal - busses. - -config SCHED_SMT - bool "SMT scheduler support" - help - Improves the CPU scheduler's decision making when dealing with - MultiThreading at a cost of slightly increased overhead in some - places. If unsure say N here. - config NR_CPUS int "Maximum number of CPUs (2-4096)" range 2 4096 @@ -1697,20 +1676,6 @@ config MITIGATE_SPECTRE_BRANCH_HISTORY When taking an exception from user-space, a sequence of branches or a firmware call overwrites the branch history. -config RODATA_FULL_DEFAULT_ENABLED - bool "Apply r/o permissions of VM areas also to their linear aliases" - default y - help - Apply read-only attributes of VM areas to the linear alias of - the backing pages as well. This prevents code or read-only data - from being modified (inadvertently or intentionally) via another - mapping of the same memory page. This additional enhancement can - be turned off at runtime by passing rodata=[off|on] (and turned on - with rodata=full if this option is set to 'n') - - This requires the linear region to be mapped down to pages, - which may adversely affect performance in some cases. - config ARM64_SW_TTBR0_PAN bool "Emulate Privileged Access Never using TTBR0_EL1 switching" depends on !KCSAN @@ -1781,7 +1746,6 @@ config COMPAT_VDSO bool "Enable vDSO for 32-bit applications" depends on !CPU_BIG_ENDIAN depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" - select GENERIC_COMPAT_VDSO default y help Place in the process address space of 32-bit applications an @@ -2217,14 +2181,13 @@ config ARM64_HAFT endmenu # "ARMv8.9 architectural features" -menu "v9.4 architectural features" +menu "ARMv9.4 architectural features" config ARM64_GCS bool "Enable support for Guarded Control Stack (GCS)" default y select ARCH_HAS_USER_SHADOW_STACK select ARCH_USES_HIGH_VMA_FLAGS - depends on !UPROBES help Guarded Control Stack (GCS) provides support for a separate stack with restricted access which contains only return @@ -2236,7 +2199,7 @@ config ARM64_GCS The feature is detected at runtime, and will remain disabled if the system does not implement the feature. -endmenu # "v9.4 architectural features" +endmenu # "ARMv9.4 architectural features" config ARM64_SVE bool "ARM Scalable Vector Extension support" @@ -2362,8 +2325,7 @@ config STACKPROTECTOR_PER_TASK config UNWIND_PATCH_PAC_INTO_SCS bool "Enable shadow call stack dynamically using code patching" - # needs Clang with https://github.com/llvm/llvm-project/commit/de07cde67b5d205d58690be012106022aea6d2b3 incorporated - depends on CC_IS_CLANG && CLANG_VERSION >= 150000 + depends on CC_IS_CLANG depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET depends on SHADOW_CALL_STACK select UNWIND_TABLES diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index a88f5ad9328c..13173795c43d 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -40,6 +40,13 @@ config ARCH_APPLE This enables support for Apple's in-house ARM SoC family, such as the Apple M1. +config ARCH_ARTPEC + bool "Axis Communications ARTPEC SoC Family" + depends on ARCH_EXYNOS + select ARM_GIC + help + This enables support for the ARMv8 based ARTPEC SoC Family. + config ARCH_AXIADO bool "Axiado SoC Family" select GPIOLIB @@ -131,20 +138,6 @@ config ARCH_EXYNOS help This enables support for ARMv8 based Samsung Exynos SoC family. -config ARCH_SPARX5 - bool "Microchip Sparx5 SoC family" - select PINCTRL - select DW_APB_TIMER_OF - help - This enables support for the Microchip Sparx5 ARMv8-based - SoC family of TSN-capable gigabit switches. - - The SparX-5 Ethernet switch family provides a rich set of - switching features such as advanced TCAM-based VLAN and QoS - processing enabling delivery of differentiated services, and - security through TCAM-based frame processing using versatile - content aware processor (VCAP). - config ARCH_K3 bool "Texas Instruments Inc. K3 multicore SoC architecture" select SOC_TI @@ -186,6 +179,43 @@ config ARCH_MESON This enables support for the arm64 based Amlogic SoCs such as the s905, S905X/D, S912, A113X/D or S905X/D2 +menu "Microchip SoC support" + +config ARCH_MICROCHIP + bool + +config ARCH_LAN969X + bool "Microchip LAN969X SoC family" + select PINCTRL + select DW_APB_TIMER_OF + select ARCH_MICROCHIP + help + This enables support for the Microchip LAN969X ARMv8-based + SoC family of TSN-capable gigabit switches. + + The LAN969X Ethernet switch family provides a rich set of + switching features such as advanced TCAM-based VLAN and QoS + processing enabling delivery of differentiated services, and + security through TCAM-based frame processing using versatile + content aware processor (VCAP). + +config ARCH_SPARX5 + bool "Microchip Sparx5 SoC family" + select PINCTRL + select DW_APB_TIMER_OF + select ARCH_MICROCHIP + help + This enables support for the Microchip Sparx5 ARMv8-based + SoC family of TSN-capable gigabit switches. + + The SparX-5 Ethernet switch family provides a rich set of + switching features such as advanced TCAM-based VLAN and QoS + processing enabling delivery of differentiated services, and + security through TCAM-based frame processing using versatile + content aware processor (VCAP). + +endmenu + config ARCH_MMP bool "Marvell MMP SoC Family" select PINCTRL diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index 780aeba0f3a4..2edfa7bf4ab3 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -41,6 +41,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h313-tanix-tx1.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h313-x96q.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-manta.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-pi.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h313-x96q.dts b/arch/arm64/boot/dts/allwinner/sun50i-h313-x96q.dts new file mode 100644 index 000000000000..b2275eb3d55b --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h313-x96q.dts @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2025 J. Neuschäfer <j.ne@posteo.net> + */ + +/dts-v1/; + +#include "sun50i-h616.dtsi" +#include "sun50i-h616-cpu-opp.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "X96Q"; + compatible = "amediatech,x96q", "allwinner,sun50i-h616"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the DC input */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-recovery { + label = "Recovery"; + linux,code = <KEY_VENDOR>; + gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + color = <LED_COLOR_ID_BLUE>; + gpios = <&pio 7 6 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; +}; + +&codec { + allwinner,audio-routing = "Line Out", "LINEOUT"; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdca>; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + +/* TODO: EMAC1 connected to AC200 PHY */ + +&gpu { + mali-supply = <®_dcdcc>; + status = "okay"; +}; + +&ir { + status = "okay"; +}; + +&mmc0 { + /* microSD */ + vmmc-supply = <®_aldo1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + disable-wp; + bus-width = <4>; + status = "okay"; +}; + +/* TODO: XRadio XR819 WLAN @ mmc1 */ + +&mmc2 { + /* eMMC */ + vmmc-supply = <®_aldo1>; + vqmmc-supply = <®_bldo1>; + non-removable; + cap-mmc-hw-reset; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <100000000>; /* required for stable operation */ + bus-width = <8>; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + +&r_i2c { + status = "okay"; + + axp305: pmic@36 { + compatible = "x-powers,axp305", "x-powers,axp805", + "x-powers,axp806"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x36>; + + x-powers,self-working-mode; + vina-supply = <®_vcc5v>; + vinb-supply = <®_vcc5v>; + vinc-supply = <®_vcc5v>; + vind-supply = <®_vcc5v>; + vine-supply = <®_vcc5v>; + aldoin-supply = <®_vcc5v>; + bldoin-supply = <®_vcc5v>; + cldoin-supply = <®_vcc5v>; + + regulators { + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpu"; + }; + + dcdcb { + /* unused */ + }; + + reg_dcdcc: dcdcc { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <990000>; + regulator-name = "vdd-gpu-sys"; + }; + + dcdcd { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd-dram"; + }; + + dcdce { + /* unused */ + }; + + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3"; + }; + + aldo2 { + /* unused */ + }; + + aldo3 { + /* unused */ + }; + + reg_bldo1: bldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8"; + }; + + bldo2 { + /* unused */ + }; + + bldo3 { + /* unused */ + }; + + bldo4 { + /* unused */ + }; + + cldo1 { + /* unused */ + }; + + cldo2 { + /* unused */ + }; + + cldo3 { + /* unused */ + }; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +&usbotg { + dr_mode = "host"; /* USB A type receptacle */ + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi index 6b6f2296bdff..7b36c47a3a13 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -4,8 +4,10 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/sun6i-rtc.h> #include <dt-bindings/clock/sun55i-a523-ccu.h> +#include <dt-bindings/clock/sun55i-a523-mcu-ccu.h> #include <dt-bindings/clock/sun55i-a523-r-ccu.h> #include <dt-bindings/reset/sun55i-a523-ccu.h> +#include <dt-bindings/reset/sun55i-a523-mcu-ccu.h> #include <dt-bindings/reset/sun55i-a523-r-ccu.h> #include <dt-bindings/power/allwinner,sun55i-a523-ppu.h> #include <dt-bindings/power/allwinner,sun55i-a523-pck-600.h> @@ -624,6 +626,8 @@ "pll-audio"; #clock-cells = <1>; #reset-cells = <1>; + assigned-clocks = <&r_ccu CLK_R_AHB>, <&r_ccu CLK_R_APB0>; + assigned-clock-rates = <200000000>, <100000000>; }; nmi_intc: interrupt-controller@7010320 { @@ -690,5 +694,42 @@ clock-names = "bus", "hosc", "ahb"; #clock-cells = <1>; }; + + mcu_ccu: clock-controller@7102000 { + compatible = "allwinner,sun55i-a523-mcu-ccu"; + reg = <0x7102000 0x200>; + clocks = <&osc24M>, + <&rtc CLK_OSC32K>, + <&rtc CLK_IOSC>, + <&ccu CLK_PLL_AUDIO0_4X>, + <&ccu CLK_PLL_PERIPH0_300M>, + <&ccu CLK_DSP>, + <&ccu CLK_MBUS>, + <&r_ccu CLK_R_AHB>, + <&r_ccu CLK_R_APB0>; + clock-names = "hosc", + "losc", + "iosc", + "pll-audio0-4x", + "pll-periph0-300m", + "dsp", + "mbus", + "r-ahb", + "r-apb0"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + npu: npu@7122000 { + compatible = "vivante,gc"; + reg = <0x07122000 0x1000>; + interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mcu_ccu CLK_BUS_MCU_NPU_ACLK>, + <&ccu CLK_NPU>, + <&mcu_ccu CLK_BUS_MCU_NPU_HCLK>; + clock-names = "bus", "core", "reg"; + resets = <&mcu_ccu RST_BUS_MCU_NPU>; + power-domains = <&ppu PD_NPU>; + }; }; }; diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts index 553ad774ed13..f82a8d121697 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts @@ -6,6 +6,7 @@ #include "sun55i-a523.dtsi" #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> / { model = "Radxa Cubie A5E"; @@ -20,11 +21,28 @@ stdout-path = "serial0:115200n8"; }; - ext_osc32k: ext-osc32k-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "ext_osc32k"; + leds { + compatible = "gpio-leds"; + + power-led { + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_GREEN>; + gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; /* PL4 */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + use-led { + function = LED_FUNCTION_ACTIVITY; + color = <LED_COLOR_ID_BLUE>; + gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */ + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&axp717_adc 3>, /* vsys_v */ + <&axp717_adc 4>; /* pmic_temp */ }; reg_vcc5v: vcc5v { @@ -75,6 +93,9 @@ ext_rgmii_phy: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; + reset-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ + reset-assert-us = <10000>; + reset-deassert-us = <150000>; }; }; @@ -125,6 +146,17 @@ bldoin-supply = <®_vcc5v>; cldoin-supply = <®_vcc5v>; + axp717_adc: adc { + compatible = "x-powers,axp717-adc"; + #io-channel-cells = <1>; + }; + + battery-power { + compatible = "x-powers,axp717-battery-power-supply"; + /* charger mode design but has no battery terminal */ + status = "disabled"; + }; + regulators { /* Supplies the "little" cluster (1.4 GHz cores) */ reg_dcdc1: dcdc1 { @@ -228,6 +260,10 @@ regulator-name = "vdd-cpus"; }; }; + + usb-power { + compatible = "x-powers,axp717-usb-power-supply"; + }; }; axp323: pmic@36 { diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts index b9eeb6753e9e..1b054fa8ef74 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts @@ -27,6 +27,12 @@ clock-output-names = "ext_osc32k"; }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&axp717_adc 3>, /* vsys_v */ + <&axp717_adc 4>; /* pmic_temp */ + }; + reg_vcc12v: vcc12v { /* DC input jack */ compatible = "regulator-fixed"; @@ -85,6 +91,9 @@ ext_rgmii_phy: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; + reset-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ + reset-assert-us = <10000>; + reset-deassert-us = <150000>; }; }; @@ -146,6 +155,17 @@ bldoin-supply = <®_vcc5v>; cldoin-supply = <®_vcc5v>; + axp717_adc: adc { + compatible = "x-powers,axp717-adc"; + #io-channel-cells = <1>; + }; + + battery-power { + compatible = "x-powers,axp717-battery-power-supply"; + /* no battery; output used for dcdc4 instead */ + status = "disabled"; + }; + regulators { /* Supplies the "little" cluster (1.4 GHz cores) */ reg_dcdc1: dcdc1 { @@ -252,6 +272,12 @@ regulator-name = "vdd-cpus"; }; }; + + usb-power { + compatible = "x-powers,axp717-usb-power-supply"; + /* 12V-5V buck converter can supply up to 5A */ + input-current-limit-microamp = <3250000>; + }; }; axp323: pmic@36 { @@ -306,6 +332,14 @@ vcc-pm-supply = <®_aldo3>; }; +&rtc { + clocks = <&r_ccu CLK_BUS_R_RTC>, <&osc24M>, + <&r_ccu CLK_R_AHB>, <&ext_osc32k>; + clock-names = "bus", "hosc", "ahb", "ext-osc32k"; + assigned-clocks = <&rtc CLK_OSC32K>; + assigned-clock-rates = <32768>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts index d07bb9193b43..39a4e194712a 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts @@ -40,6 +40,13 @@ }; }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&axp717_adc 3>, /* vsys_v */ + <&axp717_adc 4>, /* pmic_temp */ + <&axp717_adc 7>; /* bkup_batt_v */ + }; + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 1 1 GPIO_ACTIVE_LOW>; /* PM1 */ @@ -174,6 +181,17 @@ bldoin-supply = <®_vcc5v>; cldoin-supply = <®_vcc5v>; + axp717_adc: adc { + compatible = "x-powers,axp717-adc"; + #io-channel-cells = <1>; + }; + + battery-power { + compatible = "x-powers,axp717-battery-power-supply"; + /* no battery; output used for dcdc4 instead */ + status = "disabled"; + }; + regulators { /* Supplies the "little" cluster (1.4 GHz cores) */ reg_dcdc1: dcdc1 { @@ -288,6 +306,11 @@ regulator-name = "vdd-cpus-usb-0v9"; }; }; + + usb-power { + compatible = "x-powers,axp717-usb-power-supply"; + input-current-limit-microamp = <3000000>; + }; }; axp323: pmic@36 { @@ -346,6 +369,14 @@ vcc-pm-supply = <®_bldo2>; }; +&rtc { + clocks = <&r_ccu CLK_BUS_R_RTC>, <&osc24M>, + <&r_ccu CLK_R_AHB>, <&ext_osc32k>; + clock-names = "bus", "hosc", "ahb", "ext-osc32k"; + assigned-clocks = <&rtc CLK_OSC32K>; + assigned-clock-rates = <32768>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; diff --git a/arch/arm64/boot/dts/amazon/alpine-v2.dtsi b/arch/arm64/boot/dts/amazon/alpine-v2.dtsi index 5a72f0b64247..f49209fddbbb 100644 --- a/arch/arm64/boot/dts/amazon/alpine-v2.dtsi +++ b/arch/arm64/boot/dts/amazon/alpine-v2.dtsi @@ -123,6 +123,7 @@ <0x0 0xf0120000 0x0 0x2000>; /* GICH */ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; + #address-cells = <0>; #interrupt-cells = <3>; }; diff --git a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi index dea60d136c2e..bd35e0e9d0ab 100644 --- a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi +++ b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi @@ -320,6 +320,7 @@ gic: interrupt-controller@f0800000 { compatible = "arm,gic-v3"; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0xf0800000 0 0x10000>, /* GICD */ diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi index 563bc2e662fa..fce45933fa28 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi @@ -17,6 +17,13 @@ compatible = "arm,cortex-a53"; reg = <0x0 0x0>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; }; cpu1: cpu@1 { @@ -24,6 +31,13 @@ compatible = "arm,cortex-a53"; reg = <0x0 0x1>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; }; cpu2: cpu@2 { @@ -31,6 +45,13 @@ compatible = "arm,cortex-a53"; reg = <0x0 0x2>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; }; cpu3: cpu@3 { @@ -38,6 +59,22 @@ compatible = "arm,cortex-a53"; reg = <0x0 0x3>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; + }; + + l2: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x80000>; /* L2. 512 KB */ + cache-line-size = <64>; + cache-sets = <512>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi index cb9ea3ca6ee0..07aaaf71ea9a 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi @@ -23,6 +23,13 @@ compatible = "arm,cortex-a35"; reg = <0x0 0x0>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; }; cpu1: cpu@1 { @@ -30,6 +37,22 @@ compatible = "arm,cortex-a35"; reg = <0x0 0x1>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; + }; + + l2: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x7d000>; /* L2. 512 KB */ + cache-line-size = <64>; + cache-sets = <512>; }; }; @@ -53,6 +76,13 @@ #clock-cells = <0>; }; + xtal_32k: xtal-clk-32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xtal_32k"; + #clock-cells = <0>; + }; + sm: secure-monitor { compatible = "amlogic,meson-gxbb-sm"; @@ -792,7 +822,7 @@ pwm_mn: pwm@54000 { compatible = "amlogic,c3-pwm", "amlogic,meson-s4-pwm"; - reg = <0x0 54000 0x0 0x24>; + reg = <0x0 0x54000 0x0 0x24>; clocks = <&clkc_periphs CLKID_PWM_M>, <&clkc_periphs CLKID_PWM_N>; #pwm-cells = <3>; @@ -967,6 +997,15 @@ clock-names = "core", "device"; status = "disabled"; }; + + rtc@9a000 { + compatible = "amlogic,c3-rtc", + "amlogic,a5-rtc"; + reg = <0x0 0x9a000 0x0 0x38>; + interrupts = <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>; + clocks = <&xtal_32k>, <&clkc_periphs CLKID_SYS_RTC>; + clock-names = "osc", "sys"; + }; }; ethmac: ethernet@fdc00000 { diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi index 260918b37b9a..d262c0b66e4b 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi @@ -18,6 +18,13 @@ compatible = "arm,cortex-a55"; reg = <0x0 0x0>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; }; cpu1: cpu@100 { @@ -25,6 +32,13 @@ compatible = "arm,cortex-a55"; reg = <0x0 0x100>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; }; cpu2: cpu@200 { @@ -32,6 +46,13 @@ compatible = "arm,cortex-a55"; reg = <0x0 0x200>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; }; cpu3: cpu@300 { @@ -39,8 +60,23 @@ compatible = "arm,cortex-a55"; reg = <0x0 0x300>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; }; + l2: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x40000>; /* L2. 256 KB */ + cache-line-size = <64>; + cache-sets = <512>; + }; }; timer { diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi index ec743cad57db..6510068bcff9 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi @@ -53,6 +53,13 @@ compatible = "arm,cortex-a53"; reg = <0x0 0x100>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2_cache_l>; }; cpu101: cpu@101 { @@ -60,6 +67,13 @@ compatible = "arm,cortex-a53"; reg = <0x0 0x101>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2_cache_l>; }; cpu102: cpu@102 { @@ -67,6 +81,13 @@ compatible = "arm,cortex-a53"; reg = <0x0 0x102>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2_cache_l>; }; cpu103: cpu@103 { @@ -74,6 +95,13 @@ compatible = "arm,cortex-a53"; reg = <0x0 0x103>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2_cache_l>; }; cpu0: cpu@0 { @@ -81,6 +109,13 @@ compatible = "arm,cortex-a73"; reg = <0x0 0x0>; enable-method = "psci"; + d-cache-line-size = <64>; + d-cache-size = <0x10000>; + d-cache-sets = <64>; + i-cache-line-size = <64>; + i-cache-size = <0x10000>; + i-cache-sets = <64>; + next-level-cache = <&l2_cache_b>; }; cpu1: cpu@1 { @@ -88,6 +123,13 @@ compatible = "arm,cortex-a73"; reg = <0x0 0x1>; enable-method = "psci"; + d-cache-line-size = <64>; + d-cache-size = <0x10000>; + d-cache-sets = <64>; + i-cache-line-size = <64>; + i-cache-size = <0x10000>; + i-cache-sets = <64>; + next-level-cache = <&l2_cache_b>; }; cpu2: cpu@2 { @@ -95,6 +137,13 @@ compatible = "arm,cortex-a73"; reg = <0x0 0x2>; enable-method = "psci"; + d-cache-line-size = <64>; + d-cache-size = <0x10000>; + d-cache-sets = <64>; + i-cache-line-size = <64>; + i-cache-size = <0x10000>; + i-cache-sets = <64>; + next-level-cache = <&l2_cache_b>; }; cpu3: cpu@3 { @@ -102,6 +151,31 @@ compatible = "arm,cortex-a73"; reg = <0x0 0x3>; enable-method = "psci"; + d-cache-line-size = <64>; + d-cache-size = <0x10000>; + d-cache-sets = <64>; + i-cache-line-size = <64>; + i-cache-size = <0x10000>; + i-cache-sets = <64>; + next-level-cache = <&l2_cache_b>; + }; + + l2_cache_l: l2-cache-cluster0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x40000>; /* L2. 256 KB */ + cache-line-size = <64>; + cache-sets = <512>; + }; + + l2_cache_b: l2-cache-cluster1 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x100000>; /* L2. 1 Mb */ + cache-line-size = <64>; + cache-sets = <512>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index f7f25a10f409..27b68ed85c4c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -27,6 +27,12 @@ compatible = "arm,cortex-a35"; reg = <0x0 0x0>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -36,6 +42,12 @@ compatible = "arm,cortex-a35"; reg = <0x0 0x1>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -44,6 +56,9 @@ compatible = "cache"; cache-level = <2>; cache-unified; + cache-size = <0x80000>; /* L2. 512 KB */ + cache-line-size = <64>; + cache-sets = <512>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 2df143aa77ce..04fb130ac7c6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -83,6 +83,12 @@ compatible = "arm,cortex-a53"; reg = <0x0 0x1>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; dynamic-power-coefficient = <140>; @@ -94,6 +100,12 @@ compatible = "arm,cortex-a53"; reg = <0x0 0x2>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; dynamic-power-coefficient = <140>; @@ -105,6 +117,12 @@ compatible = "arm,cortex-a53"; reg = <0x0 0x3>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; dynamic-power-coefficient = <140>; @@ -115,6 +133,9 @@ compatible = "cache"; cache-level = <2>; cache-unified; + cache-size = <0x80000>; /* L2. 512 KB */ + cache-line-size = <64>; + cache-sets = <512>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi index deee61dbe074..1321ad95923d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi @@ -17,6 +17,12 @@ compatible = "arm,cortex-a53"; reg = <0x0 0x0>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -26,6 +32,12 @@ compatible = "arm,cortex-a53"; reg = <0x0 0x1>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -35,6 +47,12 @@ compatible = "arm,cortex-a53"; reg = <0x0 0x2>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -44,6 +62,12 @@ compatible = "arm,cortex-a53"; reg = <0x0 0x3>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -52,6 +76,9 @@ compatible = "cache"; cache-level = <2>; cache-unified; + cache-size = <0x80000>; /* L2. 512 KB */ + cache-line-size = <64>; + cache-sets = <512>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi index 86e6ceb31d5e..f04efa828256 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi @@ -49,7 +49,13 @@ reg = <0x0 0x0>; enable-method = "psci"; capacity-dmips-mhz = <592>; - next-level-cache = <&l2>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2_cache_l>; #cooling-cells = <2>; }; @@ -59,7 +65,13 @@ reg = <0x0 0x1>; enable-method = "psci"; capacity-dmips-mhz = <592>; - next-level-cache = <&l2>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2_cache_l>; #cooling-cells = <2>; }; @@ -69,7 +81,13 @@ reg = <0x0 0x100>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2_cache_l>; #cooling-cells = <2>; }; @@ -79,7 +97,13 @@ reg = <0x0 0x101>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2_cache_l>; #cooling-cells = <2>; }; @@ -89,7 +113,13 @@ reg = <0x0 0x102>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; + d-cache-line-size = <64>; + d-cache-size = <0x10000>; + d-cache-sets = <64>; + i-cache-line-size = <64>; + i-cache-size = <0x10000>; + i-cache-sets = <64>; + next-level-cache = <&l2_cache_b>; #cooling-cells = <2>; }; @@ -99,14 +129,32 @@ reg = <0x0 0x103>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; + d-cache-line-size = <64>; + d-cache-size = <0x10000>; + d-cache-sets = <64>; + i-cache-line-size = <64>; + i-cache-size = <0x10000>; + i-cache-sets = <64>; + next-level-cache = <&l2_cache_b>; #cooling-cells = <2>; }; - l2: l2-cache0 { + l2_cache_l: l2-cache-cluster0 { compatible = "cache"; cache-level = <2>; cache-unified; + cache-size = <0x40000>; /* L2. 256 KB */ + cache-line-size = <64>; + cache-sets = <512>; + }; + + l2_cache_b: l2-cache-cluster1 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x100000>; /* L2. 1MB */ + cache-line-size = <64>; + cache-sets = <512>; }; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index 7d99ca44e660..c1d8e81d95cb 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -95,6 +95,12 @@ compatible = "arm,cortex-a53"; reg = <0x0 0x0>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; #cooling-cells = <2>; @@ -105,6 +111,12 @@ compatible = "arm,cortex-a53"; reg = <0x0 0x1>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; #cooling-cells = <2>; @@ -115,6 +127,12 @@ compatible = "arm,cortex-a53"; reg = <0x0 0x2>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; #cooling-cells = <2>; @@ -125,6 +143,12 @@ compatible = "arm,cortex-a53"; reg = <0x0 0x3>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; #cooling-cells = <2>; @@ -134,6 +158,9 @@ compatible = "cache"; cache-level = <2>; cache-unified; + cache-size = <0x80000>; /* L2. 512 KB */ + cache-line-size = <64>; + cache-sets = <512>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts index 959bd8d77a82..12e26f99d4f0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts @@ -348,10 +348,6 @@ bus-width = <4>; cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-ddr50; max-frequency = <100000000>; disable-wp; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi index 411cc312fc62..514c9bea6423 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi @@ -64,6 +64,12 @@ reg = <0x0 0x100>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 1>; #cooling-cells = <2>; @@ -75,6 +81,12 @@ reg = <0x0 0x101>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 1>; #cooling-cells = <2>; @@ -86,6 +98,12 @@ reg = <0x0 0x102>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 1>; #cooling-cells = <2>; @@ -97,6 +115,12 @@ reg = <0x0 0x103>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 1>; #cooling-cells = <2>; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi index 538b35036954..5e07f0f9538e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi @@ -380,11 +380,10 @@ bus-width = <4>; cap-sd-highspeed; - max-frequency = <50000000>; + /* Boot failures are observed at 50MHz */ + max-frequency = <35000000>; disable-wp; - /* TOFIX: SD card is barely usable in SDR modes */ - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; vmmc-supply = <&tflash_vdd>; vqmmc-supply = <&vddio_c>; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi index 966ebb19cc55..e5db8ce94062 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi @@ -55,6 +55,12 @@ compatible = "arm,cortex-a55"; reg = <0x0 0x0>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -64,6 +70,12 @@ compatible = "arm,cortex-a55"; reg = <0x0 0x1>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -73,6 +85,12 @@ compatible = "arm,cortex-a55"; reg = <0x0 0x2>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -82,6 +100,12 @@ compatible = "arm,cortex-a55"; reg = <0x0 0x3>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -90,6 +114,9 @@ compatible = "cache"; cache-level = <2>; cache-unified; + cache-size = <0x40000>; /* L2. 256 KB */ + cache-line-size = <64>; + cache-sets = <256>; }; }; diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index 5a64239b4708..5bbedb0a7107 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -22,7 +22,6 @@ enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; next-level-cache = <&xgene_L2_0>; - #clock-cells = <1>; clocks = <&pmd0clk 0>; }; cpu@1 { @@ -32,7 +31,6 @@ enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; next-level-cache = <&xgene_L2_0>; - #clock-cells = <1>; clocks = <&pmd0clk 0>; }; cpu@100 { @@ -42,7 +40,6 @@ enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; next-level-cache = <&xgene_L2_1>; - #clock-cells = <1>; clocks = <&pmd1clk 0>; }; cpu@101 { @@ -52,7 +49,6 @@ enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; next-level-cache = <&xgene_L2_1>; - #clock-cells = <1>; clocks = <&pmd1clk 0>; }; cpu@200 { @@ -62,7 +58,6 @@ enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; next-level-cache = <&xgene_L2_2>; - #clock-cells = <1>; clocks = <&pmd2clk 0>; }; cpu@201 { @@ -72,7 +67,6 @@ enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; next-level-cache = <&xgene_L2_2>; - #clock-cells = <1>; clocks = <&pmd2clk 0>; }; cpu@300 { @@ -82,7 +76,6 @@ enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; next-level-cache = <&xgene_L2_3>; - #clock-cells = <1>; clocks = <&pmd3clk 0>; }; cpu@301 { @@ -92,7 +85,6 @@ enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; next-level-cache = <&xgene_L2_3>; - #clock-cells = <1>; clocks = <&pmd3clk 0>; }; xgene_L2_0: l2-cache-0 { @@ -211,9 +203,9 @@ }; }; - refclk: refclk { + refclk: clock-100000000 { compatible = "fixed-clock"; - #clock-cells = <1>; + #clock-cells = <0>; clock-frequency = <100000000>; clock-output-names = "refclk"; }; @@ -232,6 +224,16 @@ clock-frequency = <50000000>; }; + i2cslimpro { + compatible = "apm,xgene-slimpro-i2c"; + mboxes = <&mailbox 0>; + }; + + hwmonslimpro { + compatible = "apm,xgene-slimpro-hwmon"; + mboxes = <&mailbox 7>; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -246,7 +248,7 @@ pmdpll: pmdpll@170000f0 { compatible = "apm,xgene-pcppll-v2-clock"; #clock-cells = <1>; - clocks = <&refclk 0>; + clocks = <&refclk>; reg = <0x0 0x170000f0 0x0 0x10>; clock-output-names = "pmdpll"; }; @@ -286,7 +288,7 @@ socpll: socpll@17000120 { compatible = "apm,xgene-socpll-v2-clock"; #clock-cells = <1>; - clocks = <&refclk 0>; + clocks = <&refclk>; reg = <0x0 0x17000120 0x0 0x1000>; clock-output-names = "socpll"; }; @@ -585,16 +587,6 @@ 0x0 0x7 0x4>; }; - i2cslimpro { - compatible = "apm,xgene-slimpro-i2c"; - mboxes = <&mailbox 0>; - }; - - hwmonslimpro { - compatible = "apm,xgene-slimpro-hwmon"; - mboxes = <&mailbox 7>; - }; - serial0: serial@10600000 { compatible = "ns16550"; reg = <0 0x10600000 0x0 0x1000>; @@ -617,7 +609,7 @@ pcie0: pcie@1f2b0000 { status = "disabled"; device_type = "pci"; - compatible = "apm,xgene-pcie", "apm,xgene2-pcie"; + compatible = "apm,xgene-pcie"; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; @@ -643,7 +635,7 @@ pcie1: pcie@1f2c0000 { status = "disabled"; device_type = "pci"; - compatible = "apm,xgene-pcie", "apm,xgene2-pcie"; + compatible = "apm,xgene-pcie"; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 872093b05ce1..4ca0ead120c1 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -103,6 +103,7 @@ gic: interrupt-controller@78010000 { compatible = "arm,cortex-a15-gic"; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */ @@ -112,9 +113,9 @@ interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ }; - refclk: refclk { + refclk: clock-100000000 { compatible = "fixed-clock"; - #clock-cells = <1>; + #clock-cells = <0>; clock-frequency = <100000000>; clock-output-names = "refclk"; }; @@ -133,6 +134,16 @@ interrupts = <1 12 0xff04>; }; + i2cslimpro { + compatible = "apm,xgene-slimpro-i2c"; + mboxes = <&mailbox 0>; + }; + + hwmonslimpro { + compatible = "apm,xgene-slimpro-hwmon"; + mboxes = <&mailbox 7>; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -148,28 +159,25 @@ pcppll: pcppll@17000100 { compatible = "apm,xgene-pcppll-clock"; #clock-cells = <1>; - clocks = <&refclk 0>; + clocks = <&refclk>; clock-names = "pcppll"; reg = <0x0 0x17000100 0x0 0x1000>; clock-output-names = "pcppll"; - type = <0>; }; socpll: socpll@17000120 { compatible = "apm,xgene-socpll-clock"; #clock-cells = <1>; - clocks = <&refclk 0>; + clocks = <&refclk>; clock-names = "socpll"; reg = <0x0 0x17000120 0x0 0x1000>; clock-output-names = "socpll"; - type = <1>; }; socplldiv2: socplldiv2 { compatible = "fixed-factor-clock"; - #clock-cells = <1>; + #clock-cells = <0>; clocks = <&socpll 0>; - clock-names = "socplldiv2"; clock-mult = <1>; clock-div = <2>; clock-output-names = "socplldiv2"; @@ -178,7 +186,7 @@ ahbclk: ahbclk@17000000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x17000000 0x0 0x2000>; reg-names = "div-reg"; divider-offset = <0x164>; @@ -190,7 +198,7 @@ sdioclk: sdioclk@1f2ac000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f2ac000 0x0 0x1000 0x0 0x17000000 0x0 0x2000>; reg-names = "csr-reg", "div-reg"; @@ -207,7 +215,7 @@ ethclk: ethclk { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; clock-names = "ethclk"; reg = <0x0 0x17000000 0x0 0x1000>; reg-names = "div-reg"; @@ -229,7 +237,7 @@ sge0clk: sge0clk@1f21c000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f21c000 0x0 0x1000>; reg-names = "csr-reg"; csr-mask = <0xa>; @@ -240,7 +248,7 @@ xge0clk: xge0clk@1f61c000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f61c000 0x0 0x1000>; reg-names = "csr-reg"; csr-mask = <0x3>; @@ -251,7 +259,7 @@ compatible = "apm,xgene-device-clock"; status = "disabled"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f62c000 0x0 0x1000>; reg-names = "csr-reg"; csr-mask = <0x3>; @@ -261,7 +269,7 @@ sataphy1clk: sataphy1clk@1f21c000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f21c000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "sataphy1clk"; @@ -275,7 +283,7 @@ sataphy2clk: sataphy1clk@1f22c000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f22c000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "sataphy2clk"; @@ -289,7 +297,7 @@ sataphy3clk: sataphy1clk@1f23c000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f23c000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "sataphy3clk"; @@ -303,7 +311,7 @@ sata01clk: sata01clk@1f21c000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f21c000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "sata01clk"; @@ -316,7 +324,7 @@ sata23clk: sata23clk@1f22c000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f22c000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "sata23clk"; @@ -329,7 +337,7 @@ sata45clk: sata45clk@1f23c000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f23c000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "sata45clk"; @@ -342,7 +350,7 @@ rtcclk: rtcclk@17000000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x17000000 0x0 0x2000>; reg-names = "csr-reg"; csr-offset = <0xc>; @@ -355,7 +363,7 @@ rngpkaclk: rngpkaclk@17000000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x17000000 0x0 0x2000>; reg-names = "csr-reg"; csr-offset = <0xc>; @@ -369,7 +377,7 @@ status = "disabled"; compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f2bc000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "pcie0clk"; @@ -379,7 +387,7 @@ status = "disabled"; compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f2cc000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "pcie1clk"; @@ -389,7 +397,7 @@ status = "disabled"; compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f2dc000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "pcie2clk"; @@ -399,7 +407,7 @@ status = "disabled"; compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f50c000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "pcie3clk"; @@ -409,7 +417,7 @@ status = "disabled"; compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f51c000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "pcie4clk"; @@ -418,7 +426,7 @@ dmaclk: dmaclk@1f27c000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f27c000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "dmaclk"; @@ -760,16 +768,6 @@ <0x0 0x7 0x4>; }; - i2cslimpro { - compatible = "apm,xgene-slimpro-i2c"; - mboxes = <&mailbox 0>; - }; - - hwmonslimpro { - compatible = "apm,xgene-slimpro-hwmon"; - mboxes = <&mailbox 7>; - }; - serial0: serial@1c020000 { status = "disabled"; compatible = "ns16550a"; @@ -849,7 +847,6 @@ compatible = "snps,designware-i2c"; reg = <0x0 0x10512000 0x0 0x1000>; interrupts = <0 0x44 0x4>; - #clock-cells = <1>; clocks = <&ahbclk 0>; }; diff --git a/arch/arm64/boot/dts/apple/Makefile b/arch/arm64/boot/dts/apple/Makefile index 4f337bff36cd..4eebcd85c90f 100644 --- a/arch/arm64/boot/dts/apple/Makefile +++ b/arch/arm64/boot/dts/apple/Makefile @@ -79,6 +79,15 @@ dtb-$(CONFIG_ARCH_APPLE) += t6000-j316s.dtb dtb-$(CONFIG_ARCH_APPLE) += t6001-j316c.dtb dtb-$(CONFIG_ARCH_APPLE) += t6001-j375c.dtb dtb-$(CONFIG_ARCH_APPLE) += t6002-j375d.dtb +dtb-$(CONFIG_ARCH_APPLE) += t6022-j180d.dtb +dtb-$(CONFIG_ARCH_APPLE) += t6020-j414s.dtb +dtb-$(CONFIG_ARCH_APPLE) += t6021-j414c.dtb +dtb-$(CONFIG_ARCH_APPLE) += t6020-j416s.dtb +dtb-$(CONFIG_ARCH_APPLE) += t6021-j416c.dtb +dtb-$(CONFIG_ARCH_APPLE) += t6020-j474s.dtb +dtb-$(CONFIG_ARCH_APPLE) += t6021-j475c.dtb +dtb-$(CONFIG_ARCH_APPLE) += t6022-j475d.dtb dtb-$(CONFIG_ARCH_APPLE) += t8112-j413.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8112-j415.dtb dtb-$(CONFIG_ARCH_APPLE) += t8112-j473.dtb dtb-$(CONFIG_ARCH_APPLE) += t8112-j493.dtb diff --git a/arch/arm64/boot/dts/apple/s5l8960x.dtsi b/arch/arm64/boot/dts/apple/s5l8960x.dtsi index 5b5175d6978c..462ffdd348fc 100644 --- a/arch/arm64/boot/dts/apple/s5l8960x.dtsi +++ b/arch/arm64/boot/dts/apple/s5l8960x.dtsi @@ -89,6 +89,62 @@ status = "disabled"; }; + i2c0: i2c@20a110000 { + compatible = "apple,s5l8960x-i2c", "apple,i2c"; + reg = <0x2 0x0a110000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 154 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@20a111000 { + compatible = "apple,s5l8960x-i2c", "apple,i2c"; + reg = <0x2 0x0a111000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 155 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@20a112000 { + compatible = "apple,s5l8960x-i2c", "apple,i2c"; + reg = <0x2 0x0a112000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 156 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@20a113000 { + compatible = "apple,s5l8960x-i2c", "apple,i2c"; + reg = <0x2 0x0a113000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 157 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pmgr: power-management@20e000000 { compatible = "apple,s5l8960x-pmgr", "apple,pmgr", "syscon", "simple-mfd"; #address-cells = <1>; @@ -140,6 +196,26 @@ <AIC_IRQ 112 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 113 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 114 IRQ_TYPE_LEVEL_HIGH>; + + i2c0_pins: i2c0-pins { + pinmux = <APPLE_PINMUX(81, 1)>, + <APPLE_PINMUX(80, 1)>; + }; + + i2c1_pins: i2c1-pins { + pinmux = <APPLE_PINMUX(83, 1)>, + <APPLE_PINMUX(82, 1)>; + }; + + i2c2_pins: i2c2-pins { + pinmux = <APPLE_PINMUX(101, 1)>, + <APPLE_PINMUX(100, 1)>; + }; + + i2c3_pins: i2c3-pins { + pinmux = <APPLE_PINMUX(172, 1)>, + <APPLE_PINMUX(171, 1)>; + }; }; }; diff --git a/arch/arm64/boot/dts/apple/s800-0-3.dtsi b/arch/arm64/boot/dts/apple/s800-0-3.dtsi index 09db4ed64054..bb38662b7d2e 100644 --- a/arch/arm64/boot/dts/apple/s800-0-3.dtsi +++ b/arch/arm64/boot/dts/apple/s800-0-3.dtsi @@ -88,6 +88,48 @@ status = "disabled"; }; + i2c0: i2c@20a110000 { + compatible = "apple,s8000-i2c", "apple,i2c"; + reg = <0x2 0x0a110000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 206 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@20a111000 { + compatible = "apple,s8000-i2c", "apple,i2c"; + reg = <0x2 0x0a111000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 207 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@20a112000 { + compatible = "apple,s8000-i2c", "apple,i2c"; + reg = <0x2 0x0a112000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 208 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pmgr: power-management@20e000000 { compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; #address-cells = <1>; @@ -131,6 +173,21 @@ <AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH>; + + i2c0_pins: i2c0-pins { + pinmux = <APPLE_PINMUX(46, 1)>, + <APPLE_PINMUX(45, 1)>; + }; + + i2c1_pins: i2c1-pins { + pinmux = <APPLE_PINMUX(115, 1)>, + <APPLE_PINMUX(114, 1)>; + }; + + i2c2_pins: i2c2-pins { + pinmux = <APPLE_PINMUX(23, 1)>, + <APPLE_PINMUX(22, 1)>; + }; }; pinctrl_aop: pinctrl@2100f0000 { diff --git a/arch/arm64/boot/dts/apple/s8001.dtsi b/arch/arm64/boot/dts/apple/s8001.dtsi index fee350765894..b5b00dca6ffa 100644 --- a/arch/arm64/boot/dts/apple/s8001.dtsi +++ b/arch/arm64/boot/dts/apple/s8001.dtsi @@ -137,6 +137,62 @@ status = "disabled"; }; + i2c0: i2c@20a110000 { + compatible = "apple,s8000-i2c", "apple,i2c"; + reg = <0x2 0x0a110000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 232 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@20a111000 { + compatible = "apple,s8000-i2c", "apple,i2c"; + reg = <0x2 0x0a111000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 233 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@20a112000 { + compatible = "apple,s8000-i2c", "apple,i2c"; + reg = <0x2 0x0a112000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 234 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@20a113000 { + compatible = "apple,s8000-i2c", "apple,i2c"; + reg = <0x2 0x0a113000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 235 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pmgr: power-management@20e000000 { compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; #address-cells = <1>; @@ -173,6 +229,26 @@ <AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH>; + + i2c0_pins: i2c0-pins { + pinmux = <APPLE_PINMUX(165, 1)>, + <APPLE_PINMUX(164, 1)>; + }; + + i2c1_pins: i2c1-pins { + pinmux = <APPLE_PINMUX(178, 1)>, + <APPLE_PINMUX(177, 1)>; + }; + + i2c2_pins: i2c2-pins { + pinmux = <APPLE_PINMUX(132, 1)>, + <APPLE_PINMUX(131, 1)>; + }; + + i2c3_pins: i2c3-pins { + pinmux = <APPLE_PINMUX(115, 1)>, + <APPLE_PINMUX(114, 1)>; + }; }; pinctrl_aop: pinctrl@2100f0000 { diff --git a/arch/arm64/boot/dts/apple/t6000-j314s.dts b/arch/arm64/boot/dts/apple/t6000-j314s.dts index c9e192848fe3..1430b91ff1b1 100644 --- a/arch/arm64/boot/dts/apple/t6000-j314s.dts +++ b/arch/arm64/boot/dts/apple/t6000-j314s.dts @@ -16,3 +16,11 @@ compatible = "apple,j314s", "apple,t6000", "apple,arm-platform"; model = "Apple MacBook Pro (14-inch, M1 Pro, 2021)"; }; + +&wifi0 { + brcm,board-type = "apple,maldives"; +}; + +&bluetooth0 { + brcm,board-type = "apple,maldives"; +}; diff --git a/arch/arm64/boot/dts/apple/t6000-j316s.dts b/arch/arm64/boot/dts/apple/t6000-j316s.dts index ff1803ce2300..da0cbe7d9673 100644 --- a/arch/arm64/boot/dts/apple/t6000-j316s.dts +++ b/arch/arm64/boot/dts/apple/t6000-j316s.dts @@ -16,3 +16,11 @@ compatible = "apple,j316s", "apple,t6000", "apple,arm-platform"; model = "Apple MacBook Pro (16-inch, M1 Pro, 2021)"; }; + +&wifi0 { + brcm,board-type = "apple,madagascar"; +}; + +&bluetooth0 { + brcm,board-type = "apple,madagascar"; +}; diff --git a/arch/arm64/boot/dts/apple/t6001-j314c.dts b/arch/arm64/boot/dts/apple/t6001-j314c.dts index 1761d15b98c1..c37097dcfdb3 100644 --- a/arch/arm64/boot/dts/apple/t6001-j314c.dts +++ b/arch/arm64/boot/dts/apple/t6001-j314c.dts @@ -16,3 +16,11 @@ compatible = "apple,j314c", "apple,t6001", "apple,arm-platform"; model = "Apple MacBook Pro (14-inch, M1 Max, 2021)"; }; + +&wifi0 { + brcm,board-type = "apple,maldives"; +}; + +&bluetooth0 { + brcm,board-type = "apple,maldives"; +}; diff --git a/arch/arm64/boot/dts/apple/t6001-j316c.dts b/arch/arm64/boot/dts/apple/t6001-j316c.dts index 750e9beeffc0..3bc6e0c3294c 100644 --- a/arch/arm64/boot/dts/apple/t6001-j316c.dts +++ b/arch/arm64/boot/dts/apple/t6001-j316c.dts @@ -16,3 +16,11 @@ compatible = "apple,j316c", "apple,t6001", "apple,arm-platform"; model = "Apple MacBook Pro (16-inch, M1 Max, 2021)"; }; + +&wifi0 { + brcm,board-type = "apple,madagascar"; +}; + +&bluetooth0 { + brcm,board-type = "apple,madagascar"; +}; diff --git a/arch/arm64/boot/dts/apple/t6001-j375c.dts b/arch/arm64/boot/dts/apple/t6001-j375c.dts index 62ea437b58b2..2e7c23714d4d 100644 --- a/arch/arm64/boot/dts/apple/t6001-j375c.dts +++ b/arch/arm64/boot/dts/apple/t6001-j375c.dts @@ -16,3 +16,11 @@ compatible = "apple,j375c", "apple,t6001", "apple,arm-platform"; model = "Apple Mac Studio (M1 Max, 2022)"; }; + +&wifi0 { + brcm,board-type = "apple,okinawa"; +}; + +&bluetooth0 { + brcm,board-type = "apple,okinawa"; +}; diff --git a/arch/arm64/boot/dts/apple/t6002-j375d.dts b/arch/arm64/boot/dts/apple/t6002-j375d.dts index 3365429bdc8b..2b7f80119618 100644 --- a/arch/arm64/boot/dts/apple/t6002-j375d.dts +++ b/arch/arm64/boot/dts/apple/t6002-j375d.dts @@ -38,6 +38,14 @@ }; }; +&wifi0 { + brcm,board-type = "apple,okinawa"; +}; + +&bluetooth0 { + brcm,board-type = "apple,okinawa"; +}; + /* delete unused always-on power-domains on die 1 */ /delete-node/ &ps_atc2_usb_aon_die1; diff --git a/arch/arm64/boot/dts/apple/t600x-die0.dtsi b/arch/arm64/boot/dts/apple/t600x-die0.dtsi index 1563b3ce1ff6..3603b276a2ab 100644 --- a/arch/arm64/boot/dts/apple/t600x-die0.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-die0.dtsi @@ -24,6 +24,41 @@ power-domains = <&ps_aic>; }; + smc: smc@290400000 { + compatible = "apple,t6000-smc", "apple,smc"; + reg = <0x2 0x90400000 0x0 0x4000>, + <0x2 0x91e00000 0x0 0x100000>; + reg-names = "smc", "sram"; + mboxes = <&smc_mbox>; + + smc_gpio: gpio { + compatible = "apple,smc-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + smc_reboot: reboot { + compatible = "apple,smc-reboot"; + nvmem-cells = <&shutdown_flag>, <&boot_stage>, + <&boot_error_count>, <&panic_count>; + nvmem-cell-names = "shutdown_flag", "boot_stage", + "boot_error_count", "panic_count"; + }; + }; + + smc_mbox: mbox@290408000 { + compatible = "apple,t6000-asc-mailbox", "apple,asc-mailbox-v4"; + reg = <0x2 0x90408000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 754 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 755 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 756 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 757 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "send-empty", "send-not-empty", + "recv-empty", "recv-not-empty"; + #mbox-cells = <0>; + }; + pinctrl_smc: pinctrl@290820000 { compatible = "apple,t6000-pinctrl", "apple,pinctrl"; reg = <0x2 0x90820000 0x0 0x4000>; diff --git a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi index 22ebc78e120b..c0aac59a6fae 100644 --- a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi @@ -13,6 +13,7 @@ / { aliases { + bluetooth0 = &bluetooth0; serial0 = &serial0; wifi0 = &wifi0; }; @@ -99,9 +100,18 @@ /* WLAN */ bus-range = <1 1>; wifi0: wifi@0,0 { + compatible = "pci14e4,4433"; reg = <0x10000 0x0 0x0 0x0 0x0>; /* To be filled by the loader */ local-mac-address = [00 10 18 00 00 10]; + apple,antenna-sku = "XX"; + }; + + bluetooth0: bluetooth@0,1 { + compatible = "pci14e4,5f71"; + reg = <0x10100 0x0 0x0 0x0 0x0>; + /* To be filled by the loader */ + local-bd-address = [00 00 00 00 00 00]; }; }; diff --git a/arch/arm64/boot/dts/apple/t600x-j375.dtsi b/arch/arm64/boot/dts/apple/t600x-j375.dtsi index d5b985ad5679..c0fb93ae72f4 100644 --- a/arch/arm64/boot/dts/apple/t600x-j375.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-j375.dtsi @@ -11,6 +11,8 @@ / { aliases { + bluetooth0 = &bluetooth0; + ethernet0 = ðernet0; serial0 = &serial0; wifi0 = &wifi0; }; @@ -84,9 +86,18 @@ /* WLAN */ bus-range = <1 1>; wifi0: wifi@0,0 { + compatible = "pci14e4,4433"; reg = <0x10000 0x0 0x0 0x0 0x0>; /* To be filled by the loader */ local-mac-address = [00 10 18 00 00 10]; + apple,antenna-sku = "XX"; + }; + + bluetooth0: bluetooth@0,1 { + compatible = "pci14e4,5f71"; + reg = <0x10100 0x0 0x0 0x0 0x0>; + /* To be filled by the loader */ + local-bd-address = [00 00 00 00 00 00]; }; }; diff --git a/arch/arm64/boot/dts/apple/t6020-j414s.dts b/arch/arm64/boot/dts/apple/t6020-j414s.dts new file mode 100644 index 000000000000..631c54c5f03d --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6020-j414s.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * MacBook Pro (14-inch, M2 Pro, 2023) + * + * target-type: J414s + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6020.dtsi" +#include "t602x-j414-j416.dtsi" + +/ { + compatible = "apple,j414s", "apple,t6020", "apple,arm-platform"; + model = "Apple MacBook Pro (14-inch, M2 Pro, 2023)"; +}; + +&wifi0 { + brcm,board-type = "apple,tokara"; +}; + +&bluetooth0 { + brcm,board-type = "apple,tokara"; +}; diff --git a/arch/arm64/boot/dts/apple/t6020-j416s.dts b/arch/arm64/boot/dts/apple/t6020-j416s.dts new file mode 100644 index 000000000000..c277ed5889a2 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6020-j416s.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * MacBook Pro (16-inch, M2 Pro, 2023) + * + * target-type: J416s + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6020.dtsi" +#include "t602x-j414-j416.dtsi" + +/ { + compatible = "apple,j416s", "apple,t6020", "apple,arm-platform"; + model = "Apple MacBook Pro (16-inch, M2 Pro, 2023)"; +}; + +&wifi0 { + brcm,board-type = "apple,amami"; +}; + +&bluetooth0 { + brcm,board-type = "apple,amami"; +}; diff --git a/arch/arm64/boot/dts/apple/t6020-j474s.dts b/arch/arm64/boot/dts/apple/t6020-j474s.dts new file mode 100644 index 000000000000..7c7ad5b8ad18 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6020-j474s.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Mac mini (M2 Pro, 2023) + * + * target-type: J474s + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6020.dtsi" + +/* + * This model is very similar to M1 and M2 Mac Studio models so base it on those + * and remove the missing SDHCI controller. + */ + +#include "t602x-j474-j475.dtsi" + +/ { + compatible = "apple,j474s", "apple,t6020", "apple,arm-platform"; + model = "Apple Mac mini (M2 Pro, 2023)"; +}; + +/* PCIe devices */ +&wifi0 { + compatible = "pci14e4,4434"; + brcm,board-type = "apple,tasmania"; +}; + +&bluetooth0 { + compatible = "pci14e4,5f72"; + brcm,board-type = "apple,tasmania"; +}; + +/* + * port01 is unused, remove the PCIe sdhci0 node from t600x-j375.dtsi and adjust + * the iommu-map. + */ +/delete-node/ &sdhci0; + +&pcie0 { + iommu-map = <0x100 &pcie0_dart_0 1 1>, + <0x200 &pcie0_dart_2 1 1>, + <0x300 &pcie0_dart_3 1 1>; +}; diff --git a/arch/arm64/boot/dts/apple/t6020.dtsi b/arch/arm64/boot/dts/apple/t6020.dtsi new file mode 100644 index 000000000000..bffa66a3ffff --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6020.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T6020 "M2 Pro" SoC + * + * Other names: H14J, "Rhodes Chop" + * + * Copyright The Asahi Linux Contributors + */ + +/* This chip is just a cut down version of t6021, so include it and disable the missing parts */ + +#include "t6021.dtsi" + +/ { + compatible = "apple,t6020", "apple,arm-platform"; +}; + +/delete-node/ &pmgr_south; + +&gpu { + compatible = "apple,agx-g14s"; +}; diff --git a/arch/arm64/boot/dts/apple/t6021-j414c.dts b/arch/arm64/boot/dts/apple/t6021-j414c.dts new file mode 100644 index 000000000000..cdcf0740714d --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6021-j414c.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * MacBook Pro (14-inch, M2 Max, 2023) + * + * target-type: J414c + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6021.dtsi" +#include "t602x-j414-j416.dtsi" + +/ { + compatible = "apple,j414c", "apple,t6021", "apple,arm-platform"; + model = "Apple MacBook Pro (14-inch, M2 Max, 2023)"; +}; + +&wifi0 { + brcm,board-type = "apple,tokara"; +}; + +&bluetooth0 { + brcm,board-type = "apple,tokara"; +}; diff --git a/arch/arm64/boot/dts/apple/t6021-j416c.dts b/arch/arm64/boot/dts/apple/t6021-j416c.dts new file mode 100644 index 000000000000..6d8146b94170 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6021-j416c.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * MacBook Pro (16-inch, M2 Max, 2022) + * + * target-type: J416c + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6021.dtsi" +#include "t602x-j414-j416.dtsi" + +/ { + compatible = "apple,j416c", "apple,t6021", "apple,arm-platform"; + model = "Apple MacBook Pro (16-inch, M2 Max, 2023)"; +}; + +&wifi0 { + brcm,board-type = "apple,amami"; +}; + +&bluetooth0 { + brcm,board-type = "apple,amami"; +}; diff --git a/arch/arm64/boot/dts/apple/t6021-j475c.dts b/arch/arm64/boot/dts/apple/t6021-j475c.dts new file mode 100644 index 000000000000..533e35774874 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6021-j475c.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Mac Studio (M2 Max, 2023) + * + * target-type: J475c + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6021.dtsi" +#include "t602x-j474-j475.dtsi" + +/ { + compatible = "apple,j475c", "apple,t6021", "apple,arm-platform"; + model = "Apple Mac Studio (M2 Max, 2023)"; +}; + +&wifi0 { + compatible = "pci14e4,4434"; + brcm,board-type = "apple,canary"; +}; + +&bluetooth0 { + compatible = "pci14e4,5f72"; + brcm,board-type = "apple,canary"; +}; + +/* enable PCIe port01 with SDHCI */ +&port01 { + status = "okay"; +}; + +&pcie0_dart_1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t6021.dtsi b/arch/arm64/boot/dts/apple/t6021.dtsi new file mode 100644 index 000000000000..62907ad6a546 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6021.dtsi @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T6021 "M2 Max" SoC + * + * Other names: H14J, "Rhodes" + * + * Copyright The Asahi Linux Contributors + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/apple-aic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/apple.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/spmi/spmi.h> + +#include "multi-die-cpp.h" + +#include "t602x-common.dtsi" + +/ { + compatible = "apple,t6021", "apple,arm-platform"; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + + ranges; + nonposted-mmio; + + // filled via templated includes at the end of the file + }; +}; + +#define DIE +#define DIE_NO 0 + +&{/soc} { + #include "t602x-die0.dtsi" + #include "t602x-dieX.dtsi" + #include "t602x-nvme.dtsi" +}; + +#include "t602x-gpio-pins.dtsi" +#include "t602x-pmgr.dtsi" + +#undef DIE +#undef DIE_NO + + +&aic { + affinities { + e-core-pmu-affinity { + apple,fiq-index = <AIC_CPU_PMU_E>; + cpus = <&cpu_e00 &cpu_e01 &cpu_e02 &cpu_e03>; + }; + + p-core-pmu-affinity { + apple,fiq-index = <AIC_CPU_PMU_P>; + cpus = <&cpu_p00 &cpu_p01 &cpu_p02 &cpu_p03 + &cpu_p10 &cpu_p11 &cpu_p12 &cpu_p13>; + }; + }; +}; + +&gpu { + compatible = "apple,agx-g14c", "apple,agx-g14s"; +}; diff --git a/arch/arm64/boot/dts/apple/t6022-j180d.dts b/arch/arm64/boot/dts/apple/t6022-j180d.dts new file mode 100644 index 000000000000..dca6bd167c22 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6022-j180d.dts @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Mac Pro (M2 Ultra, 2023) + * + * target-type: J180d + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6022.dtsi" +#include "t6022-jxxxd.dtsi" + +/ { + compatible = "apple,j180d", "apple,t6022", "apple,arm-platform"; + model = "Apple Mac Pro (M2 Ultra, 2023)"; + aliases { + nvram = &nvram; + serial0 = &serial0; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0"; + + framebuffer0: framebuffer@0 { + compatible = "apple,simple-framebuffer", "simple-framebuffer"; + reg = <0 0 0 0>; /* To be filled by loader */ + /* Format properties will be added by loader */ + status = "disabled"; + power-domains = <&ps_dispext0_cpu0_die1>, <&ps_dptx_phy_ps_die1>; + }; + }; + + memory@10000000000 { + device_type = "memory"; + reg = <0x100 0 0x2 0>; /* To be filled by loader */ + }; +}; + +&serial0 { + status = "okay"; +}; + +/* USB Type C Rear */ +&i2c0 { + hpm2: usb-pd@3b { + compatible = "apple,cd321x"; + reg = <0x3b>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; + + hpm3: usb-pd@3c { + compatible = "apple,cd321x"; + reg = <0x3c>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; + + /* hpm4 and hpm5 included from t6022-jxxxd.dtsi */ + + hpm6: usb-pd@3d { + compatible = "apple,cd321x"; + reg = <0x3d>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; + + hpm7: usb-pd@3e { + compatible = "apple,cd321x"; + reg = <0x3e>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; +}; + +/* USB Type C Front */ +&i2c3 { + status = "okay"; + + hpm0: usb-pd@38 { + compatible = "apple,cd321x"; + reg = <0x38>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <60 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; + + hpm1: usb-pd@3f { + compatible = "apple,cd321x"; + reg = <0x3f>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <60 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; +}; + +/* + * Delete unused PCIe nodes, the Mac Pro uses slightly different PCIe + * controllers with a single port connected to a PM40100 PCIe switch + */ +/delete-node/ &pcie0; +/delete-node/ &pcie0_dart_0; +/delete-node/ &pcie0_dart_1; +/delete-node/ &pcie0_dart_2; +/delete-node/ &pcie0_dart_3; + +&nco_clkref { + clock-frequency = <1068000000>; +}; + +#include "spi1-nvram.dtsi" diff --git a/arch/arm64/boot/dts/apple/t6022-j475d.dts b/arch/arm64/boot/dts/apple/t6022-j475d.dts new file mode 100644 index 000000000000..736594544f79 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6022-j475d.dts @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Mac Studio (M2 Ultra, 2023) + * + * target-type: J475d + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6022.dtsi" +#include "t602x-j474-j475.dtsi" +#include "t6022-jxxxd.dtsi" + +/ { + compatible = "apple,j475d", "apple,t6022", "apple,arm-platform"; + model = "Apple Mac Studio (M2 Ultra, 2023)"; +}; + +&framebuffer0 { + power-domains = <&ps_dispext0_cpu0_die1>, <&ps_dptx_phy_ps_die1>; +}; + +/* enable PCIe port01 with SDHCI */ +&port01 { + status = "okay"; +}; + +&pcie0_dart_1 { + status = "okay"; +}; + +&wifi0 { + compatible = "pci14e4,4434"; + brcm,board-type = "apple,canary"; +}; + +&bluetooth0 { + compatible = "pci14e4,5f72"; + brcm,board-type = "apple,canary"; +}; diff --git a/arch/arm64/boot/dts/apple/t6022-jxxxd.dtsi b/arch/arm64/boot/dts/apple/t6022-jxxxd.dtsi new file mode 100644 index 000000000000..4f7bf2ebfe39 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6022-jxxxd.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Mac Pro (M2 Ultra, 2023) and Mac Studio (M2 Ultra, 2023) + * + * This file contains the parts common to J180 and J475 devices with t6022. + * + * target-type: J180d / J475d + * + * Copyright The Asahi Linux Contributors + */ + +/* delete power-domains for missing disp0 / disp0_die1 */ +/delete-node/ &ps_disp0_cpu0; +/delete-node/ &ps_disp0_fe; + +/delete-node/ &ps_disp0_cpu0_die1; +/delete-node/ &ps_disp0_fe_die1; + +/* USB Type C */ +&i2c0 { + /* front-right */ + hpm4: usb-pd@39 { + compatible = "apple,cd321x"; + reg = <0x39>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; + + /* front-left */ + hpm5: usb-pd@3a { + compatible = "apple,cd321x"; + reg = <0x3a>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t6022.dtsi b/arch/arm64/boot/dts/apple/t6022.dtsi new file mode 100644 index 000000000000..e73bf2f7510a --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6022.dtsi @@ -0,0 +1,349 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T6022 "M2 Ultra" SoC + * + * Other names: H14J, "Rhodes 2C" + * + * Copyright The Asahi Linux Contributors + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/apple-aic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/apple.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/spmi/spmi.h> + +#include "multi-die-cpp.h" + +#include "t602x-common.dtsi" + +/ { + compatible = "apple,t6022", "apple,arm-platform"; + + #address-cells = <2>; + #size-cells = <2>; + + cpus { + cpu-map { + cluster3 { + core0 { + cpu = <&cpu_e10>; + }; + core1 { + cpu = <&cpu_e11>; + }; + core2 { + cpu = <&cpu_e12>; + }; + core3 { + cpu = <&cpu_e13>; + }; + }; + + cluster4 { + core0 { + cpu = <&cpu_p20>; + }; + core1 { + cpu = <&cpu_p21>; + }; + core2 { + cpu = <&cpu_p22>; + }; + core3 { + cpu = <&cpu_p23>; + }; + }; + + cluster5 { + core0 { + cpu = <&cpu_p30>; + }; + core1 { + cpu = <&cpu_p31>; + }; + core2 { + cpu = <&cpu_p32>; + }; + core3 { + cpu = <&cpu_p33>; + }; + }; + }; + + cpu_e10: cpu@800 { + compatible = "apple,blizzard"; + device_type = "cpu"; + reg = <0x0 0x800>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* to be filled by loader */ + next-level-cache = <&l2_cache_3>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + operating-points-v2 = <&blizzard_opp>; + capacity-dmips-mhz = <756>; + performance-domains = <&cpufreq_e_die1>; + }; + + cpu_e11: cpu@801 { + compatible = "apple,blizzard"; + device_type = "cpu"; + reg = <0x0 0x801>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* to be filled by loader */ + next-level-cache = <&l2_cache_3>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + operating-points-v2 = <&blizzard_opp>; + capacity-dmips-mhz = <756>; + performance-domains = <&cpufreq_e_die1>; + }; + + cpu_e12: cpu@802 { + compatible = "apple,blizzard"; + device_type = "cpu"; + reg = <0x0 0x802>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* to be filled by loader */ + next-level-cache = <&l2_cache_3>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + operating-points-v2 = <&blizzard_opp>; + capacity-dmips-mhz = <756>; + performance-domains = <&cpufreq_e_die1>; + }; + + cpu_e13: cpu@803 { + compatible = "apple,blizzard"; + device_type = "cpu"; + reg = <0x0 0x803>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* to be filled by loader */ + next-level-cache = <&l2_cache_3>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + operating-points-v2 = <&blizzard_opp>; + capacity-dmips-mhz = <756>; + performance-domains = <&cpufreq_e_die1>; + }; + + cpu_p20: cpu@10900 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10900>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_4>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p0_die1>; + }; + + cpu_p21: cpu@10901 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10901>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_4>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p0_die1>; + }; + + cpu_p22: cpu@10902 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10902>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_4>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p0_die1>; + }; + + cpu_p23: cpu@10903 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10903>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_4>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p0_die1>; + }; + + cpu_p30: cpu@10a00 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10a00>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_5>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p1_die1>; + }; + + cpu_p31: cpu@10a01 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10a01>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_5>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p1_die1>; + }; + + cpu_p32: cpu@10a02 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10a02>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_5>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p1_die1>; + }; + + cpu_p33: cpu@10a03 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10a03>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_5>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p1_die1>; + }; + + l2_cache_3: l2-cache-3 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x400000>; + }; + + l2_cache_4: l2-cache-4 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x1000000>; + }; + + l2_cache_5: l2-cache-5 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x1000000>; + }; + }; + + die0: soc@200000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x02 0x00000000 0x02 0x00000000 0x4 0x00000000>, + <0x05 0x80000000 0x05 0x80000000 0x1 0x80000000>, + <0x07 0x00000000 0x07 0x00000000 0xf 0x80000000>, + <0x16 0x80000000 0x16 0x80000000 0x5 0x80000000>; + nonposted-mmio; + /* Required to get >32-bit DMA via DARTs */ + dma-ranges = <0 0 0 0 0xffffffff 0xffffc000>; + + // filled via templated includes at the end of the file + }; + + die1: soc@2200000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x02 0x00000000 0x22 0x00000000 0x4 0x00000000>, + <0x07 0x00000000 0x27 0x00000000 0xf 0x80000000>, + <0x16 0x80000000 0x36 0x80000000 0x5 0x80000000>; + nonposted-mmio; + /* Required to get >32-bit DMA via DARTs */ + dma-ranges = <0 0 0 0 0xffffffff 0xffffc000>; + + // filled via templated includes at the end of the file + }; +}; + +#define DIE +#define DIE_NO 0 + +&die0 { + #include "t602x-die0.dtsi" + #include "t602x-dieX.dtsi" +}; + +#include "t602x-pmgr.dtsi" +#include "t602x-gpio-pins.dtsi" + +#undef DIE +#undef DIE_NO + +#define DIE _die1 +#define DIE_NO 1 + +&die1 { + #include "t602x-dieX.dtsi" + #include "t602x-nvme.dtsi" +}; + +#include "t602x-pmgr.dtsi" + +/delete-node/ &ps_pmp_die1; + +#undef DIE +#undef DIE_NO + +&aic { + affinities { + e-core-pmu-affinity { + apple,fiq-index = <AIC_CPU_PMU_E>; + cpus = <&cpu_e00 &cpu_e01 &cpu_e02 &cpu_e03 + &cpu_e10 &cpu_e11 &cpu_e12 &cpu_e13>; + }; + + p-core-pmu-affinity { + apple,fiq-index = <AIC_CPU_PMU_P>; + cpus = <&cpu_p00 &cpu_p01 &cpu_p02 &cpu_p03 + &cpu_p10 &cpu_p11 &cpu_p12 &cpu_p13 + &cpu_p20 &cpu_p21 &cpu_p22 &cpu_p23 + &cpu_p30 &cpu_p31 &cpu_p32 &cpu_p33>; + }; + }; +}; + +&ps_gfx { + // On t6022, the die0 GPU power domain needs both AFR power domains + power-domains = <&ps_afr>, <&ps_afr_die1>; +}; + +&gpu { + compatible = "apple,agx-g14d", "apple,agx-g14s"; +}; diff --git a/arch/arm64/boot/dts/apple/t602x-common.dtsi b/arch/arm64/boot/dts/apple/t602x-common.dtsi new file mode 100644 index 000000000000..9c800a391e7e --- /dev/null +++ b/arch/arm64/boot/dts/apple/t602x-common.dtsi @@ -0,0 +1,465 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Nodes common to all T602x family SoCs (M2 Pro/Max/Ultra) + * + * Other names: H14J, "Rhodes Chop", "Rhodes", "Rhodes 2C" + * + * Copyright The Asahi Linux Contributors + */ + +/ { + #address-cells = <2>; + #size-cells = <2>; + + aliases { + gpu = &gpu; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu_e00>; + }; + core1 { + cpu = <&cpu_e01>; + }; + core2 { + cpu = <&cpu_e02>; + }; + core3 { + cpu = <&cpu_e03>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu_p00>; + }; + core1 { + cpu = <&cpu_p01>; + }; + core2 { + cpu = <&cpu_p02>; + }; + core3 { + cpu = <&cpu_p03>; + }; + }; + + cluster2 { + core0 { + cpu = <&cpu_p10>; + }; + core1 { + cpu = <&cpu_p11>; + }; + core2 { + cpu = <&cpu_p12>; + }; + core3 { + cpu = <&cpu_p13>; + }; + }; + }; + + cpu_e00: cpu@0 { + compatible = "apple,blizzard"; + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* to be filled by loader */ + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + operating-points-v2 = <&blizzard_opp>; + capacity-dmips-mhz = <756>; + performance-domains = <&cpufreq_e>; + }; + + cpu_e01: cpu@1 { + compatible = "apple,blizzard"; + device_type = "cpu"; + reg = <0x0 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* to be filled by loader */ + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + operating-points-v2 = <&blizzard_opp>; + capacity-dmips-mhz = <756>; + performance-domains = <&cpufreq_e>; + }; + + cpu_e02: cpu@2 { + compatible = "apple,blizzard"; + device_type = "cpu"; + reg = <0x0 0x2>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* to be filled by loader */ + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + operating-points-v2 = <&blizzard_opp>; + capacity-dmips-mhz = <756>; + performance-domains = <&cpufreq_e>; + }; + + cpu_e03: cpu@3 { + compatible = "apple,blizzard"; + device_type = "cpu"; + reg = <0x0 0x3>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* to be filled by loader */ + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + operating-points-v2 = <&blizzard_opp>; + capacity-dmips-mhz = <756>; + performance-domains = <&cpufreq_e>; + }; + + cpu_p00: cpu@10100 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10100>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p0>; + }; + + cpu_p01: cpu@10101 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10101>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p0>; + }; + + cpu_p02: cpu@10102 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10102>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p0>; + }; + + cpu_p03: cpu@10103 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10103>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p0>; + }; + + cpu_p10: cpu@10200 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10200>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_2>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p1>; + }; + + cpu_p11: cpu@10201 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10201>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_2>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p1>; + }; + + cpu_p12: cpu@10202 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10202>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_2>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p1>; + }; + + cpu_p13: cpu@10203 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10203>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_2>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p1>; + }; + + l2_cache_0: l2-cache-0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x400000>; + }; + + l2_cache_1: l2-cache-1 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x1000000>; + }; + + l2_cache_2: l2-cache-2 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x1000000>; + }; + }; + + blizzard_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + /* pstate #1 is a dummy clone of #2 */ + opp02 { + opp-hz = /bits/ 64 <912000000>; + opp-level = <2>; + clock-latency-ns = <7700>; + }; + opp03 { + opp-hz = /bits/ 64 <1284000000>; + opp-level = <3>; + clock-latency-ns = <25000>; + }; + opp04 { + opp-hz = /bits/ 64 <1752000000>; + opp-level = <4>; + clock-latency-ns = <33000>; + }; + opp05 { + opp-hz = /bits/ 64 <2004000000>; + opp-level = <5>; + clock-latency-ns = <38000>; + }; + opp06 { + opp-hz = /bits/ 64 <2256000000>; + opp-level = <6>; + clock-latency-ns = <44000>; + }; + opp07 { + opp-hz = /bits/ 64 <2424000000>; + opp-level = <7>; + clock-latency-ns = <48000>; + }; + }; + + avalanche_opp: opp-table-1 { + compatible = "operating-points-v2"; + opp-shared; + + opp01 { + opp-hz = /bits/ 64 <702000000>; + opp-level = <1>; + clock-latency-ns = <7400>; + }; + opp02 { + opp-hz = /bits/ 64 <948000000>; + opp-level = <2>; + clock-latency-ns = <18000>; + }; + opp03 { + opp-hz = /bits/ 64 <1188000000>; + opp-level = <3>; + clock-latency-ns = <21000>; + }; + opp04 { + opp-hz = /bits/ 64 <1452000000>; + opp-level = <4>; + clock-latency-ns = <24000>; + }; + opp05 { + opp-hz = /bits/ 64 <1704000000>; + opp-level = <5>; + clock-latency-ns = <28000>; + }; + opp06 { + opp-hz = /bits/ 64 <1968000000>; + opp-level = <6>; + clock-latency-ns = <31000>; + }; + opp07 { + opp-hz = /bits/ 64 <2208000000>; + opp-level = <7>; + clock-latency-ns = <33000>; + }; + opp08 { + opp-hz = /bits/ 64 <2400000000>; + opp-level = <8>; + clock-latency-ns = <45000>; + }; + opp09 { + opp-hz = /bits/ 64 <2568000000>; + opp-level = <9>; + clock-latency-ns = <47000>; + }; + opp10 { + opp-hz = /bits/ 64 <2724000000>; + opp-level = <10>; + clock-latency-ns = <50000>; + }; + opp11 { + opp-hz = /bits/ 64 <2868000000>; + opp-level = <11>; + clock-latency-ns = <52000>; + }; + opp12 { + opp-hz = /bits/ 64 <3000000000>; + opp-level = <12>; + clock-latency-ns = <57000>; + }; + opp13 { + opp-hz = /bits/ 64 <3132000000>; + opp-level = <13>; + clock-latency-ns = <60000>; + }; + opp14 { + opp-hz = /bits/ 64 <3264000000>; + opp-level = <14>; + clock-latency-ns = <64000>; + }; + opp15 { + opp-hz = /bits/ 64 <3360000000>; + opp-level = <15>; + clock-latency-ns = <64000>; + turbo-mode; + }; + opp16 { + opp-hz = /bits/ 64 <3408000000>; + opp-level = <16>; + clock-latency-ns = <64000>; + turbo-mode; + }; + opp17 { + opp-hz = /bits/ 64 <3504000000>; + opp-level = <17>; + clock-latency-ns = <64000>; + turbo-mode; + }; + }; + + pmu-e { + compatible = "apple,blizzard-pmu"; + interrupt-parent = <&aic>; + interrupts = <AIC_FIQ 0 AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>; + }; + + pmu-p { + compatible = "apple,avalanche-pmu"; + interrupt-parent = <&aic>; + interrupts = <AIC_FIQ 0 AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&aic>; + interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; + interrupts = <AIC_FIQ 0 AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, + <AIC_FIQ 0 AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>, + <AIC_FIQ 0 AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>, + <AIC_FIQ 0 AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>; + }; + + clkref: clock-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "clkref"; + }; + + clk_200m: clock-200m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "clk_200m"; + }; + + /* + * This is a fabulated representation of the input clock + * to NCO since we don't know the true clock tree. + */ + nco_clkref: clock-ref-nco { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "nco_ref"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpu_globals: globals { + status = "disabled"; + }; + + gpu_hw_cal_a: hw-cal-a { + status = "disabled"; + }; + + gpu_hw_cal_b: hw-cal-b { + status = "disabled"; + }; + + uat_handoff: uat-handoff { + status = "disabled"; + }; + + uat_pagetables: uat-pagetables { + status = "disabled"; + }; + + uat_ttbs: uat-ttbs { + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t602x-die0.dtsi b/arch/arm64/boot/dts/apple/t602x-die0.dtsi new file mode 100644 index 000000000000..2e7d2bf08ddc --- /dev/null +++ b/arch/arm64/boot/dts/apple/t602x-die0.dtsi @@ -0,0 +1,575 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Devices used on die 0 on the Apple T6022 "M2 Ultra" SoC and present on + * Apple T6020 / T6021 "M2 Pro" / "M2 Max". + * + * Copyright The Asahi Linux Contributors + */ + + nco: clock-controller@28e03c000 { + compatible = "apple,t6020-nco", "apple,t8103-nco"; + reg = <0x2 0x8e03c000 0x0 0x14000>; + clocks = <&nco_clkref>; + #clock-cells = <1>; + }; + + aic: interrupt-controller@28e100000 { + compatible = "apple,t6020-aic", "apple,aic2"; + #interrupt-cells = <4>; + interrupt-controller; + reg = <0x2 0x8e100000 0x0 0xc000>, + <0x2 0x8e10c000 0x0 0x1000>; + reg-names = "core", "event"; + power-domains = <&ps_aic>; + }; + + nub_spmi0: spmi@29e114000 { + compatible = "apple,t6020-spmi", "apple,t8103-spmi"; + reg = <0x2 0x9e114000 0x0 0x100>; + #address-cells = <2>; + #size-cells = <0>; + + pmic1: pmic@f { + compatible = "apple,maverick-pmic", "apple,spmi-nvmem"; + reg = <0xb SPMI_USID>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + pm_setting: pm-setting@1405 { + reg = <0x1405 0x1>; + }; + + rtc_offset: rtc-offset@1411 { + reg = <0x1411 0x6>; + }; + + boot_stage: boot-stage@6001 { + reg = <0x6001 0x1>; + }; + + boot_error_count: boot-error-count@6002,0 { + reg = <0x6002 0x1>; + bits = <0 4>; + }; + + panic_count: panic-count@6002,4 { + reg = <0x6002 0x1>; + bits = <4 4>; + }; + + boot_error_stage: boot-error-stage@6003 { + reg = <0x6003 0x1>; + }; + + shutdown_flag: shutdown-flag@600f,3 { + reg = <0x600f 0x1>; + bits = <3 1>; + }; + + fault_shadow: fault-shadow@867b { + reg = <0x867b 0x10>; + }; + + socd: socd@8b00 { + reg = <0x8b00 0x400>; + }; + }; + }; + }; + + wdt: watchdog@29e2c4000 { + compatible = "apple,t6020-wdt", "apple,t8103-wdt"; + reg = <0x2 0x9e2c4000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 719 IRQ_TYPE_LEVEL_HIGH>; + }; + + smc_mbox: mbox@2a2408000 { + compatible = "apple,t6020-asc-mailbox", "apple,asc-mailbox-v4"; + reg = <0x2 0xa2408000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 862 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 863 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 864 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 865 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "send-empty", "send-not-empty", + "recv-empty", "recv-not-empty"; + #mbox-cells = <0>; + }; + + smc: smc@2a2400000 { + compatible = "apple,t6020-smc", "apple,t8103-smc"; + reg = <0x2 0xa2400000 0x0 0x4000>, + <0x2 0xa3e00000 0x0 0x100000>; + reg-names = "smc", "sram"; + mboxes = <&smc_mbox>; + + smc_gpio: gpio { + compatible = "apple,smc-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + smc_reboot: reboot { + compatible = "apple,smc-reboot"; + nvmem-cells = <&shutdown_flag>, <&boot_stage>, + <&boot_error_count>, <&panic_count>; + nvmem-cell-names = "shutdown_flag", "boot_stage", + "boot_error_count", "panic_count"; + }; + }; + + pinctrl_smc: pinctrl@2a2820000 { + compatible = "apple,t6020-pinctrl", "apple,t8103-pinctrl"; + reg = <0x2 0xa2820000 0x0 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_smc 0 0 30>; + apple,npins = <30>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 851 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 852 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 853 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 854 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 855 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 856 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 857 IRQ_TYPE_LEVEL_HIGH>; + }; + + sio_dart: iommu@39b008000 { + compatible = "apple,t6020-dart", "apple,t8110-dart"; + reg = <0x3 0x9b008000 0x0 0x8000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1231 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + power-domains = <&ps_sio_cpu>; + }; + + fpwm0: pwm@39b030000 { + compatible = "apple,t6020-fpwm", "apple,s5l-fpwm"; + reg = <0x3 0x9b030000 0x0 0x4000>; + power-domains = <&ps_fpwm0>; + clocks = <&clkref>; + #pwm-cells = <2>; + status = "disabled"; + }; + + i2c0: i2c@39b040000 { + compatible = "apple,t6020-i2c", "apple,t8103-i2c"; + reg = <0x3 0x9b040000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1219 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c0>; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + i2c1: i2c@39b044000 { + compatible = "apple,t6020-i2c", "apple,t8103-i2c"; + reg = <0x3 0x9b044000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1220 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c1>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + i2c2: i2c@39b048000 { + compatible = "apple,t6020-i2c", "apple,t8103-i2c"; + reg = <0x3 0x9b048000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1221 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c2>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + i2c3: i2c@39b04c000 { + compatible = "apple,t6020-i2c", "apple,t8103-i2c"; + reg = <0x3 0x9b04c000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1222 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c3>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + i2c4: i2c@39b050000 { + compatible = "apple,t6020-i2c", "apple,t8103-i2c"; + reg = <0x3 0x9b050000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1223 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c4>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + i2c5: i2c@39b054000 { + compatible = "apple,t6020-i2c", "apple,t8103-i2c"; + reg = <0x3 0x9b054000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1224 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c5_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c5>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + i2c6: i2c@39b054000 { + compatible = "apple,t6020-i2c", "apple,t8103-i2c"; + reg = <0x3 0x9b054000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1225 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c6_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c6>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + i2c7: i2c@39b054000 { + compatible = "apple,t6020-i2c", "apple,t8103-i2c"; + reg = <0x3 0x9b054000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1226 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c7_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c7>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + i2c8: i2c@39b054000 { + compatible = "apple,t6020-i2c", "apple,t8103-i2c"; + reg = <0x3 0x9b054000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1227 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c8_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c8>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + spi1: spi@39b104000 { + compatible = "apple,t6020-spi", "apple,t8103-spi"; + reg = <0x3 0x9b104000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1206 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk_200m>; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + power-domains = <&ps_spi1>; + status = "disabled"; + }; + + spi2: spi@39b108000 { + compatible = "apple,t6020-spi", "apple,t8103-spi"; + reg = <0x3 0x9b108000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1207 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkref>; + pinctrl-0 = <&spi2_pins>; + pinctrl-names = "default"; + power-domains = <&ps_spi2>; + status = "disabled"; + }; + + spi4: spi@39b110000 { + compatible = "apple,t6020-spi", "apple,t8103-spi"; + reg = <0x3 0x9b110000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1209 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkref>; + pinctrl-0 = <&spi4_pins>; + pinctrl-names = "default"; + power-domains = <&ps_spi4>; + status = "disabled"; + }; + + serial0: serial@39b200000 { + compatible = "apple,s5l-uart"; + reg = <0x3 0x9b200000 0x0 0x4000>; + reg-io-width = <4>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1198 IRQ_TYPE_LEVEL_HIGH>; + /* + * TODO: figure out the clocking properly, there may + * be a third selectable clock. + */ + clocks = <&clkref>, <&clkref>; + clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart0>; + status = "disabled"; + }; + + admac: dma-controller@39b400000 { + compatible = "apple,t6020-admac", "apple,t8103-admac"; + reg = <0x3 0x9b400000 0x0 0x34000>; + #dma-cells = <1>; + dma-channels = <16>; + interrupts-extended = <0>, + <&aic AIC_IRQ 0 1218 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>; + iommus = <&sio_dart 2>; + power-domains = <&ps_sio_adma>; + resets = <&ps_audio_p>; + }; + + mca: mca@39b600000 { + compatible = "apple,t6020-mca", "apple,t8103-mca"; + reg = <0x3 0x9b600000 0x0 0x10000>, + <0x3 0x9b500000 0x0 0x20000>; + clocks = <&nco 0>, <&nco 1>, <&nco 2>, <&nco 3>; + dmas = <&admac 0>, <&admac 1>, <&admac 2>, <&admac 3>, + <&admac 4>, <&admac 5>, <&admac 6>, <&admac 7>, + <&admac 8>, <&admac 9>, <&admac 10>, <&admac 11>, + <&admac 12>, <&admac 13>, <&admac 14>, <&admac 15>; + dma-names = "tx0a", "rx0a", "tx0b", "rx0b", + "tx1a", "rx1a", "tx1b", "rx1b", + "tx2a", "rx2a", "tx2b", "rx2b", + "tx3a", "rx3a", "tx3b", "rx3b"; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1211 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 1212 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 1213 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 1214 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>, + <&ps_mca2>, <&ps_mca3>; + resets = <&ps_audio_p>; + #sound-dai-cells = <1>; + }; + + gpu: gpu@406400000 { + compatible = "apple,agx-g14s"; + reg = <0x4 0x6400000 0 0x40000>, + <0x4 0x4000000 0 0x1000000>; + reg-names = "asc", "sgx"; + mboxes = <&agx_mbox>; + power-domains = <&ps_gfx>; + memory-region = <&uat_ttbs>, <&uat_pagetables>, <&uat_handoff>, + <&gpu_hw_cal_a>, <&gpu_hw_cal_b>, <&gpu_globals>; + memory-region-names = "ttbs", "pagetables", "handoff", + "hw-cal-a", "hw-cal-b", "globals"; + + apple,firmware-abi = <0 0 0>; + }; + + agx_mbox: mbox@406408000 { + compatible = "apple,t6020-asc-mailbox", "apple,asc-mailbox-v4"; + reg = <0x4 0x6408000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1143 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 1144 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 1145 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 1146 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "send-empty", "send-not-empty", + "recv-empty", "recv-not-empty"; + #mbox-cells = <0>; + }; + + pcie0: pcie@580000000 { + compatible = "apple,t6020-pcie"; + device_type = "pci"; + + reg = <0x5 0x80000000 0x0 0x1000000>, /* config */ + <0x5 0x91000000 0x0 0x4000>, /* rc */ + <0x5 0x94008000 0x0 0x4000>, /* port0 */ + <0x5 0x95008000 0x0 0x4000>, /* port1 */ + <0x5 0x96008000 0x0 0x4000>, /* port2 */ + <0x5 0x97008000 0x0 0x4000>, /* port3 */ + <0x5 0x9e00c000 0x0 0x4000>, /* phy0 */ + <0x5 0x9e010000 0x0 0x4000>, /* phy1 */ + <0x5 0x9e014000 0x0 0x4000>, /* phy2 */ + <0x5 0x9e018000 0x0 0x4000>; /* phy3 */ + reg-names = "config", "rc", + "port0", "port1", "port2", "port3", + "phy0", "phy1", "phy2", "phy3"; + + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1340 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 1344 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 1348 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 1352 IRQ_TYPE_LEVEL_HIGH>; + + msi-controller; + msi-parent = <&pcie0>; + msi-ranges = <&aic AIC_IRQ 0 1672 IRQ_TYPE_EDGE_RISING 32>; + + iommu-map = <0x100 &pcie0_dart_0 1 1>, + <0x200 &pcie0_dart_1 1 1>, + <0x300 &pcie0_dart_2 1 1>, + <0x400 &pcie0_dart_3 1 1>; + iommu-map-mask = <0xff00>; + + bus-range = <0 4>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x43000000 0x5 0xa0000000 0x5 0xa0000000 0x0 0x20000000>, + <0x02000000 0x0 0xc0000000 0x5 0xc0000000 0x0 0x40000000>; + + power-domains = <&ps_apcie_gp_sys>; + pinctrl-0 = <&pcie_pins>; + pinctrl-names = "default"; + + port00: pci@0,0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 4 GPIO_ACTIVE_LOW>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &port00 0 0 0 0>, + <0 0 0 2 &port00 0 0 0 1>, + <0 0 0 3 &port00 0 0 0 2>, + <0 0 0 4 &port00 0 0 0 3>; + }; + + port01: pci@1,0 { + device_type = "pci"; + reg = <0x800 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 5 GPIO_ACTIVE_LOW>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &port01 0 0 0 0>, + <0 0 0 2 &port01 0 0 0 1>, + <0 0 0 3 &port01 0 0 0 2>, + <0 0 0 4 &port01 0 0 0 3>; + status = "disabled"; + }; + + port02: pci@2,0 { + device_type = "pci"; + reg = <0x1000 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 6 GPIO_ACTIVE_LOW>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &port02 0 0 0 0>, + <0 0 0 2 &port02 0 0 0 1>, + <0 0 0 3 &port02 0 0 0 2>, + <0 0 0 4 &port02 0 0 0 3>; + status = "disabled"; + }; + + port03: pci@3,0 { + device_type = "pci"; + reg = <0x1800 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 7 GPIO_ACTIVE_LOW>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &port03 0 0 0 0>, + <0 0 0 2 &port03 0 0 0 1>, + <0 0 0 3 &port03 0 0 0 2>, + <0 0 0 4 &port03 0 0 0 3>; + status = "disabled"; + }; + }; + + pcie0_dart_0: iommu@594000000 { + compatible = "apple,t6020-dart", "apple,t8110-dart"; + reg = <0x5 0x94000000 0x0 0x4000>; + #iommu-cells = <1>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1341 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&ps_apcie_gp_sys>; + }; + + pcie0_dart_1: iommu@595000000 { + compatible = "apple,t6020-dart", "apple,t8110-dart"; + reg = <0x5 0x95000000 0x0 0x4000>; + #iommu-cells = <1>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1345 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&ps_apcie_gp_sys>; + status = "disabled"; + }; + + pcie0_dart_2: iommu@596000000 { + compatible = "apple,t6020-dart", "apple,t8110-dart"; + reg = <0x5 0x96000000 0x0 0x4000>; + #iommu-cells = <1>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1349 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&ps_apcie_gp_sys>; + status = "disabled"; + }; + + pcie0_dart_3: iommu@597000000 { + compatible = "apple,t6020-dart", "apple,t8110-dart"; + reg = <0x5 0x97000000 0x0 0x4000>; + #iommu-cells = <1>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1353 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&ps_apcie_gp_sys>; + status = "disabled"; + }; diff --git a/arch/arm64/boot/dts/apple/t602x-dieX.dtsi b/arch/arm64/boot/dts/apple/t602x-dieX.dtsi new file mode 100644 index 000000000000..cb07fd82b32e --- /dev/null +++ b/arch/arm64/boot/dts/apple/t602x-dieX.dtsi @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Nodes present on both dies of T6022 (M2 Ultra) and present on M2 Pro/Max. + * + * Copyright The Asahi Linux Contributors + */ + + DIE_NODE(cpufreq_e): cpufreq@210e20000 { + compatible = "apple,t6020-cluster-cpufreq", "apple,t8112-cluster-cpufreq"; + reg = <0x2 0x10e20000 0 0x1000>; + #performance-domain-cells = <0>; + }; + + DIE_NODE(cpufreq_p0): cpufreq@211e20000 { + compatible = "apple,t6020-cluster-cpufreq", "apple,t8112-cluster-cpufreq"; + reg = <0x2 0x11e20000 0 0x1000>; + #performance-domain-cells = <0>; + }; + + DIE_NODE(cpufreq_p1): cpufreq@212e20000 { + compatible = "apple,t6020-cluster-cpufreq", "apple,t8112-cluster-cpufreq"; + reg = <0x2 0x12e20000 0 0x1000>; + #performance-domain-cells = <0>; + }; + + DIE_NODE(pmgr): power-management@28e080000 { + compatible = "apple,t6020-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0x8e080000 0 0x8000>; + }; + + DIE_NODE(pmgr_south): power-management@28e680000 { + compatible = "apple,t6020-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0x8e680000 0 0x8000>; + }; + + DIE_NODE(pmgr_east): power-management@290280000 { + compatible = "apple,t6020-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0x90280000 0 0xc000>; + }; + + DIE_NODE(pinctrl_nub): pinctrl@29e1f0000 { + compatible = "apple,t6020-pinctrl", "apple,t8103-pinctrl"; + reg = <0x2 0x9e1f0000 0x0 0x4000>; + power-domains = <&DIE_NODE(ps_nub_gpio)>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&DIE_NODE(pinctrl_nub) 0 0 30>; + apple,npins = <30>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 711 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 712 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 713 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 714 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 715 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 716 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 717 IRQ_TYPE_LEVEL_HIGH>; + }; + + DIE_NODE(pmgr_mini): power-management@29e280000 { + compatible = "apple,t6020-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0x9e280000 0 0x4000>; + }; + + DIE_NODE(pinctrl_aop): pinctrl@2a6820000 { + compatible = "apple,t6020-pinctrl", "apple,t8103-pinctrl"; + reg = <0x2 0xa6820000 0x0 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&DIE_NODE(pinctrl_aop) 0 0 72>; + apple,npins = <72>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 598 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 599 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 600 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 601 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 602 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 603 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 604 IRQ_TYPE_LEVEL_HIGH>; + }; + + DIE_NODE(pinctrl_ap): pinctrl@39b028000 { + compatible = "apple,t6020-pinctrl", "apple,t8103-pinctrl"; + reg = <0x3 0x9b028000 0x0 0x4000>; + + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 458 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 459 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 460 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 461 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 462 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 463 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 464 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&clkref>; + power-domains = <&DIE_NODE(ps_gpio)>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&DIE_NODE(pinctrl_ap) 0 0 255>; + apple,npins = <255>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + DIE_NODE(pmgr_gfx): power-management@404e80000 { + compatible = "apple,t6020-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x4 0x4e80000 0 0x4000>; + }; diff --git a/arch/arm64/boot/dts/apple/t602x-gpio-pins.dtsi b/arch/arm64/boot/dts/apple/t602x-gpio-pins.dtsi new file mode 100644 index 000000000000..e41b6475f792 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t602x-gpio-pins.dtsi @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * GPIO pin mappings for Apple T602x SoCs. + * + * Copyright The Asahi Linux Contributors + */ + +&pinctrl_ap { + i2c0_pins: i2c0-pins { + pinmux = <APPLE_PINMUX(63, 1)>, + <APPLE_PINMUX(64, 1)>; + }; + + i2c1_pins: i2c1-pins { + pinmux = <APPLE_PINMUX(65, 1)>, + <APPLE_PINMUX(66, 1)>; + }; + + i2c2_pins: i2c2-pins { + pinmux = <APPLE_PINMUX(67, 1)>, + <APPLE_PINMUX(68, 1)>; + }; + + i2c3_pins: i2c3-pins { + pinmux = <APPLE_PINMUX(69, 1)>, + <APPLE_PINMUX(70, 1)>; + }; + + i2c4_pins: i2c4-pins { + pinmux = <APPLE_PINMUX(71, 1)>, + <APPLE_PINMUX(72, 1)>; + }; + + i2c5_pins: i2c5-pins { + pinmux = <APPLE_PINMUX(73, 1)>, + <APPLE_PINMUX(74, 1)>; + }; + + i2c6_pins: i2c6-pins { + pinmux = <APPLE_PINMUX(75, 1)>, + <APPLE_PINMUX(76, 1)>; + }; + + i2c7_pins: i2c7-pins { + pinmux = <APPLE_PINMUX(77, 1)>, + <APPLE_PINMUX(78, 1)>; + }; + + i2c8_pins: i2c8-pins { + pinmux = <APPLE_PINMUX(79, 1)>, + <APPLE_PINMUX(80, 1)>; + }; + + spi1_pins: spi1-pins { + pinmux = <APPLE_PINMUX(155, 1)>, /* SDI */ + <APPLE_PINMUX(156, 1)>, /* SDO */ + <APPLE_PINMUX(157, 1)>, /* SCK */ + <APPLE_PINMUX(158, 1)>; /* CS */ + }; + + spi2_pins: spi2-pins { + pinmux = <APPLE_PINMUX(159, 1)>, /* SDI */ + <APPLE_PINMUX(160, 1)>, /* SDO */ + <APPLE_PINMUX(161, 1)>, /* SCK */ + <APPLE_PINMUX(162, 1)>; /* CS */ + }; + + spi4_pins: spi4-pins { + pinmux = <APPLE_PINMUX(167, 1)>, /* SDI */ + <APPLE_PINMUX(168, 1)>, /* SDO */ + <APPLE_PINMUX(169, 1)>, /* SCK */ + <APPLE_PINMUX(170, 1)>; /* CS */ + }; + + pcie_pins: pcie-pins { + pinmux = <APPLE_PINMUX(0, 1)>, + <APPLE_PINMUX(1, 1)>, + <APPLE_PINMUX(2, 1)>, + <APPLE_PINMUX(3, 1)>; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t602x-j414-j416.dtsi b/arch/arm64/boot/dts/apple/t602x-j414-j416.dtsi new file mode 100644 index 000000000000..0e806d8ddf81 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t602x-j414-j416.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * MacBook Pro (14/16-inch, 2022) + * + * This file contains the parts common to J414 and J416 devices with both t6020 and t6021. + * + * target-type: J414s / J414c / J416s / J416c + * + * Copyright The Asahi Linux Contributors + */ + +/* + * These models are essentially identical to the previous generation, other than + * the GPIO indices. + */ + +#include "t600x-j314-j316.dtsi" + +&framebuffer0 { + power-domains = <&ps_disp0_cpu0>, <&ps_dptx_phy_ps>; +}; + +&hpm0 { + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; +}; + +&hpm1 { + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; +}; + +&hpm2 { + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; +}; + +&hpm5 { + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; +}; + +&wifi0 { + compatible = "pci14e4,4434"; +}; + +&bluetooth0 { + compatible = "pci14e4,5f72"; +}; diff --git a/arch/arm64/boot/dts/apple/t602x-j474-j475.dtsi b/arch/arm64/boot/dts/apple/t602x-j474-j475.dtsi new file mode 100644 index 000000000000..ee12fea5b12c --- /dev/null +++ b/arch/arm64/boot/dts/apple/t602x-j474-j475.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Mac mini (M2 Pro, 2023) and Mac Studio (2023) + * + * This file contains the parts common to J474 and J475 devices with t6020, + * t6021 and t6022. + * + * target-type: J474s / J475c / J475d + * + * Copyright The Asahi Linux Contributors + */ + +/* + * These models are very similar to the previous generation Mac Studio, other + * than GPIO indices. + */ + +#include "t600x-j375.dtsi" + +&framebuffer0 { + power-domains = <&ps_dispext0_cpu0>, <&ps_dptx_phy_ps>; +}; + +&hpm0 { + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; +}; + +&hpm1 { + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; +}; + +&hpm2 { + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; +}; + +&hpm3 { + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; +}; diff --git a/arch/arm64/boot/dts/apple/t602x-nvme.dtsi b/arch/arm64/boot/dts/apple/t602x-nvme.dtsi new file mode 100644 index 000000000000..590cec8ac804 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t602x-nvme.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * NVMe related devices for Apple T602x SoCs. + * + * Copyright The Asahi Linux Contributors + */ + + DIE_NODE(ans_mbox): mbox@347408000 { + compatible = "apple,t6020-asc-mailbox", "apple,asc-mailbox-v4"; + reg = <0x3 0x47408000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 1169 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 1170 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 1171 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 1172 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "send-empty", "send-not-empty", + "recv-empty", "recv-not-empty"; + power-domains = <&DIE_NODE(ps_ans2)>; + #mbox-cells = <0>; + }; + + DIE_NODE(sart): sart@34bc50000 { + compatible = "apple,t6020-sart", "apple,t6000-sart"; + reg = <0x3 0x4bc50000 0x0 0x10000>; + power-domains = <&DIE_NODE(ps_ans2)>; + }; + + DIE_NODE(nvme): nvme@34bcc0000 { + compatible = "apple,t6020-nvme-ans2", "apple,t8103-nvme-ans2"; + reg = <0x3 0x4bcc0000 0x0 0x40000>, <0x3 0x47400000 0x0 0x4000>; + reg-names = "nvme", "ans"; + interrupt-parent = <&aic>; + /* The NVME interrupt is always routed to die 0 */ + interrupts = <AIC_IRQ 0 1832 IRQ_TYPE_LEVEL_HIGH>; + mboxes = <&DIE_NODE(ans_mbox)>; + apple,sart = <&DIE_NODE(sart)>; + power-domains = <&DIE_NODE(ps_ans2)>, + <&DIE_NODE(ps_apcie_st_sys)>, + <&DIE_NODE(ps_apcie_st1_sys)>; + power-domain-names = "ans", "apcie0", "apcie1"; + resets = <&DIE_NODE(ps_ans2)>; + }; diff --git a/arch/arm64/boot/dts/apple/t602x-pmgr.dtsi b/arch/arm64/boot/dts/apple/t602x-pmgr.dtsi new file mode 100644 index 000000000000..f5382a2faf0b --- /dev/null +++ b/arch/arm64/boot/dts/apple/t602x-pmgr.dtsi @@ -0,0 +1,2265 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for Apple T602x "M2 Pro/Max/Ultra" SoC + * + * Copyright The Asahi Linux Contributors + */ + +&DIE_NODE(pmgr) { + DIE_NODE(ps_afi): power-controller@100 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afi); + apple,always-on; /* Apple Fabric, CPU interface is here */ + }; + + DIE_NODE(ps_aic): power-controller@108 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(aic); + apple,always-on; /* Core device */ + }; + + DIE_NODE(ps_dwi): power-controller@110 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dwi); + }; + + DIE_NODE(ps_pms): power-controller@118 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(pms); + apple,always-on; /* Core device */ + }; + + DIE_NODE(ps_gpio): power-controller@120 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(gpio); + power-domains = <&DIE_NODE(ps_sio)>, <&DIE_NODE(ps_pms)>; + }; + + DIE_NODE(ps_soc_dpe): power-controller@128 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(soc_dpe); + apple,always-on; /* Core device */ + }; + + DIE_NODE(ps_pms_c1ppt): power-controller@130 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(pms_c1ppt); + apple,always-on; /* Core device */ + }; + + DIE_NODE(ps_pmgr_soc_ocla): power-controller@138 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(pmgr_soc_ocla); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_amcc0): power-controller@168 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc0); + apple,always-on; /* Memory controller */ + }; + + DIE_NODE(ps_amcc2): power-controller@170 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc2); + apple,always-on; /* Memory controller */ + }; + + DIE_NODE(ps_dcs_00): power-controller@178 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_00); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_01): power-controller@180 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_01); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_02): power-controller@188 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_02); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_03): power-controller@190 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_03); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_08): power-controller@198 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_08); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_09): power-controller@1a0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_09); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_10): power-controller@1a8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_10); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_11): power-controller@1b0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_11); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_afnc1_ioa): power-controller@1b8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc1_ioa); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afi)>; + }; + + DIE_NODE(ps_afc): power-controller@1d0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afc); + apple,always-on; /* Apple Fabric, CPU interface is here */ + }; + + DIE_NODE(ps_afnc0_ioa): power-controller@1e8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc0_ioa); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afi)>; + }; + + DIE_NODE(ps_afnc1_ls): power-controller@1f0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc1_ls); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc1_ioa)>; + }; + + DIE_NODE(ps_afnc0_ls): power-controller@1f8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc0_ls); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc0_ioa)>; + }; + + DIE_NODE(ps_afnc1_lw0): power-controller@200 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x200 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc1_lw0); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc1_ls)>; + }; + + DIE_NODE(ps_afnc1_lw1): power-controller@208 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x208 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc1_lw1); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc1_ls)>; + }; + + DIE_NODE(ps_afnc1_lw2): power-controller@210 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x210 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc1_lw2); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc1_ls)>; + }; + + DIE_NODE(ps_afnc0_lw0): power-controller@218 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x218 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc0_lw0); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc0_ls)>; + }; + + DIE_NODE(ps_scodec): power-controller@220 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x220 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(scodec); + power-domains = <&DIE_NODE(ps_afnc1_lw0)>; + }; + + DIE_NODE(ps_atc0_common): power-controller@228 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x228 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc0_common); + power-domains = <&DIE_NODE(ps_afnc1_lw1)>; + }; + + DIE_NODE(ps_atc1_common): power-controller@230 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x230 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc1_common); + power-domains = <&DIE_NODE(ps_afnc1_lw1)>; + }; + + DIE_NODE(ps_atc2_common): power-controller@238 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x238 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc2_common); + power-domains = <&DIE_NODE(ps_afnc1_lw1)>; + }; + + DIE_NODE(ps_atc3_common): power-controller@240 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x240 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc3_common); + power-domains = <&DIE_NODE(ps_afnc1_lw1)>; + }; + + DIE_NODE(ps_dispext1_sys): power-controller@248 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x248 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext1_sys); + power-domains = <&DIE_NODE(ps_afnc1_lw2)>; + }; + + DIE_NODE(ps_pms_bridge): power-controller@250 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x250 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(pms_bridge); + apple,always-on; /* Core device */ + power-domains = <&DIE_NODE(ps_afnc0_lw0)>; + }; + + DIE_NODE(ps_dispext0_sys): power-controller@258 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x258 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext0_sys); + power-domains = <&DIE_NODE(ps_afnc0_lw0)>, <&DIE_NODE(ps_afr)>; + }; + + DIE_NODE(ps_ane_sys): power-controller@260 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ane_sys); + power-domains = <&DIE_NODE(ps_afnc0_lw0)>; + }; + + DIE_NODE(ps_avd_sys): power-controller@268 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x268 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(avd_sys); + power-domains = <&DIE_NODE(ps_afnc0_lw0)>; + }; + + DIE_NODE(ps_atc0_cio): power-controller@270 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x270 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc0_cio); + power-domains = <&DIE_NODE(ps_atc0_common)>; + }; + + DIE_NODE(ps_atc0_pcie): power-controller@278 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x278 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc0_pcie); + power-domains = <&DIE_NODE(ps_atc0_common)>; + }; + + DIE_NODE(ps_atc1_cio): power-controller@280 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x280 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc1_cio); + power-domains = <&DIE_NODE(ps_atc1_common)>; + }; + + DIE_NODE(ps_atc1_pcie): power-controller@288 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x288 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc1_pcie); + power-domains = <&DIE_NODE(ps_atc1_common)>; + }; + + DIE_NODE(ps_atc2_cio): power-controller@290 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x290 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc2_cio); + power-domains = <&DIE_NODE(ps_atc2_common)>; + }; + + DIE_NODE(ps_atc2_pcie): power-controller@298 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x298 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc2_pcie); + power-domains = <&DIE_NODE(ps_atc2_common)>; + }; + + DIE_NODE(ps_atc3_cio): power-controller@2a0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc3_cio); + power-domains = <&DIE_NODE(ps_atc3_common)>; + }; + + DIE_NODE(ps_atc3_pcie): power-controller@2a8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc3_pcie); + power-domains = <&DIE_NODE(ps_atc3_common)>; + }; + + DIE_NODE(ps_dispext1_fe): power-controller@2b0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext1_fe); + power-domains = <&DIE_NODE(ps_dispext1_sys)>; + }; + + DIE_NODE(ps_dispext1_cpu0): power-controller@2b8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext1_cpu0); + power-domains = <&DIE_NODE(ps_dispext1_fe)>; + apple,min-state = <4>; + }; + + DIE_NODE(ps_dispext0_fe): power-controller@2c0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext0_fe); + power-domains = <&DIE_NODE(ps_dispext0_sys)>; + }; + + DIE_NODE(ps_pmp): power-controller@2c8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(pmp); + }; + + DIE_NODE(ps_pms_sram): power-controller@2d0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(pms_sram); + }; + + DIE_NODE(ps_dispext0_cpu0): power-controller@2d8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext0_cpu0); + power-domains = <&DIE_NODE(ps_dispext0_fe)>; + apple,min-state = <4>; + }; + + DIE_NODE(ps_ane_cpu): power-controller@2e0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ane_cpu); + power-domains = <&DIE_NODE(ps_ane_sys)>; + }; + + DIE_NODE(ps_atc0_cio_pcie): power-controller@2e8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc0_cio_pcie); + power-domains = <&DIE_NODE(ps_atc0_cio)>; + }; + + DIE_NODE(ps_atc0_cio_usb): power-controller@2f0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc0_cio_usb); + power-domains = <&DIE_NODE(ps_atc0_cio)>; + }; + + DIE_NODE(ps_atc1_cio_pcie): power-controller@2f8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc1_cio_pcie); + power-domains = <&DIE_NODE(ps_atc1_cio)>; + }; + + DIE_NODE(ps_atc1_cio_usb): power-controller@300 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x300 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc1_cio_usb); + power-domains = <&DIE_NODE(ps_atc1_cio)>; + }; + + DIE_NODE(ps_atc2_cio_pcie): power-controller@308 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x308 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc2_cio_pcie); + power-domains = <&DIE_NODE(ps_atc2_cio)>; + }; + + DIE_NODE(ps_atc2_cio_usb): power-controller@310 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x310 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc2_cio_usb); + power-domains = <&DIE_NODE(ps_atc2_cio)>; + }; + + DIE_NODE(ps_atc3_cio_pcie): power-controller@318 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x318 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc3_cio_pcie); + power-domains = <&DIE_NODE(ps_atc3_cio)>; + }; + + DIE_NODE(ps_atc3_cio_usb): power-controller@320 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x320 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc3_cio_usb); + power-domains = <&DIE_NODE(ps_atc3_cio)>; + }; + + DIE_NODE(ps_trace_fab): power-controller@390 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x390 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(trace_fab); + }; + + DIE_NODE(ps_ane_sys_mpm): power-controller@4000 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ane_sys_mpm); + power-domains = <&DIE_NODE(ps_ane_sys)>; + }; + + DIE_NODE(ps_ane_td): power-controller@4008 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ane_td); + power-domains = <&DIE_NODE(ps_ane_sys)>; + }; + + DIE_NODE(ps_ane_base): power-controller@4010 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ane_base); + power-domains = <&DIE_NODE(ps_ane_td)>; + }; + + DIE_NODE(ps_ane_set1): power-controller@4018 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ane_set1); + power-domains = <&DIE_NODE(ps_ane_base)>; + }; + + DIE_NODE(ps_ane_set2): power-controller@4020 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ane_set2); + power-domains = <&DIE_NODE(ps_ane_set1)>; + }; + + DIE_NODE(ps_ane_set3): power-controller@4028 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4028 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ane_set3); + power-domains = <&DIE_NODE(ps_ane_set2)>; + }; + + DIE_NODE(ps_ane_set4): power-controller@4030 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4030 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ane_set4); + power-domains = <&DIE_NODE(ps_ane_set3)>; + }; +}; + +&DIE_NODE(pmgr_south) { + DIE_NODE(ps_amcc4): power-controller@100 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc4); + apple,always-on; + }; + + DIE_NODE(ps_amcc5): power-controller@108 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc5); + apple,always-on; + }; + + DIE_NODE(ps_amcc6): power-controller@110 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc6); + apple,always-on; + }; + + DIE_NODE(ps_amcc7): power-controller@118 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc7); + apple,always-on; + }; + + DIE_NODE(ps_dcs_16): power-controller@120 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_16); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_17): power-controller@128 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_17); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_18): power-controller@130 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_18); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_19): power-controller@138 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_19); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_20): power-controller@140 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_20); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_21): power-controller@148 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_21); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_22): power-controller@150 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x150 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_22); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_23): power-controller@158 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x158 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_23); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_24): power-controller@160 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x160 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_24); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_25): power-controller@168 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_25); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_26): power-controller@170 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_26); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_27): power-controller@178 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_27); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_28): power-controller@180 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_28); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_29): power-controller@188 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_29); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_30): power-controller@190 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_30); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_31): power-controller@198 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_31); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_afnc4_ioa): power-controller@1a0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc4_ioa); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afi)>; + }; + + DIE_NODE(ps_afnc4_ls): power-controller@1a8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc4_ls); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc4_ioa)>; + }; + + DIE_NODE(ps_afnc4_lw0): power-controller@1b0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc4_lw0); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc4_ls)>; + }; + + DIE_NODE(ps_afnc5_ioa): power-controller@1b8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc5_ioa); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afi)>; + }; + + DIE_NODE(ps_afnc5_ls): power-controller@1c0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc5_ls); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc5_ioa)>; + }; + + DIE_NODE(ps_afnc5_lw0): power-controller@1c8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc5_lw0); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc5_ls)>; + }; + + DIE_NODE(ps_dispext2_sys): power-controller@1d0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext2_sys); + }; + + DIE_NODE(ps_msr1): power-controller@1d8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(msr1); + }; + + DIE_NODE(ps_dispext2_fe): power-controller@1e0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext2_fe); + power-domains = <&DIE_NODE(ps_dispext2_sys)>; + }; + + DIE_NODE(ps_dispext2_cpu0): power-controller@1e8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext2_cpu0); + power-domains = <&DIE_NODE(ps_dispext2_fe)>; + apple,min-state = <4>; + }; + + DIE_NODE(ps_msr1_ase_core): power-controller@1f0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(msr1_ase_core); + power-domains = <&DIE_NODE(ps_msr1)>; + }; + + DIE_NODE(ps_dispext3_sys): power-controller@220 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x220 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext3_sys); + }; + + DIE_NODE(ps_venc1_sys): power-controller@228 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x228 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc1_sys); + }; + + DIE_NODE(ps_dispext3_fe): power-controller@230 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x230 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext3_fe); + power-domains = <&DIE_NODE(ps_dispext3_sys)>; + }; + + DIE_NODE(ps_dispext3_cpu0): power-controller@238 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x238 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext3_cpu0); + power-domains = <&DIE_NODE(ps_dispext3_fe)>; + apple,min-state = <4>; + }; + + DIE_NODE(ps_venc1_dma): power-controller@4000 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc1_dma); + power-domains = <&DIE_NODE(ps_venc1_sys)>; + }; + + DIE_NODE(ps_venc1_pipe4): power-controller@4008 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc1_pipe4); + power-domains = <&DIE_NODE(ps_venc1_dma)>; + }; + + DIE_NODE(ps_venc1_pipe5): power-controller@4010 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc1_pipe5); + power-domains = <&DIE_NODE(ps_venc1_dma)>; + }; + + DIE_NODE(ps_venc1_me0): power-controller@4018 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc1_me0); + power-domains = <&DIE_NODE(ps_venc1_pipe5)>, <&DIE_NODE(ps_venc1_pipe4)>; + }; + + DIE_NODE(ps_venc1_me1): power-controller@4020 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc1_me1); + power-domains = <&DIE_NODE(ps_venc1_me0)>; + }; +}; + +&DIE_NODE(pmgr_east) { + DIE_NODE(ps_clvr_spmi0): power-controller@100 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(clvr_spmi0); + apple,always-on; /* PCPU voltage regulator interface (used by SMC) */ + }; + + DIE_NODE(ps_clvr_spmi1): power-controller@108 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(clvr_spmi1); + apple,always-on; /* GPU voltage regulator interface (used by SMC) */ + }; + + DIE_NODE(ps_clvr_spmi2): power-controller@110 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(clvr_spmi2); + apple,always-on; /* ANE, fabric, AFR voltage regulator interface (used by SMC) */ + }; + + DIE_NODE(ps_clvr_spmi3): power-controller@118 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(clvr_spmi3); + apple,always-on; /* Additional voltage regulator, probably used on T6021 (SMC) */ + }; + + DIE_NODE(ps_clvr_spmi4): power-controller@120 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(clvr_spmi4); + apple,always-on; /* Additional voltage regulator, probably used on T6021 (SMC) */ + }; + + DIE_NODE(ps_ispsens0): power-controller@128 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ispsens0); + }; + + DIE_NODE(ps_ispsens1): power-controller@130 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ispsens1); + }; + + DIE_NODE(ps_ispsens2): power-controller@138 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ispsens2); + }; + + DIE_NODE(ps_ispsens3): power-controller@140 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ispsens3); + }; + + DIE_NODE(ps_afnc6_ioa): power-controller@148 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc6_ioa); + apple,always-on; + power-domains = <&DIE_NODE(ps_afi)>; + }; + + DIE_NODE(ps_afnc6_ls): power-controller@150 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x150 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc6_ls); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc6_ioa)>; + }; + + DIE_NODE(ps_afnc6_lw0): power-controller@158 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x158 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc6_lw0); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc6_ls)>; + }; + + DIE_NODE(ps_afnc2_ioa): power-controller@160 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x160 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc2_ioa); + apple,always-on; + power-domains = <&DIE_NODE(ps_dcs_10)>; + }; + + DIE_NODE(ps_afnc2_ls): power-controller@168 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc2_ls); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc2_ioa)>; + }; + + DIE_NODE(ps_afnc2_lw0): power-controller@170 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc2_lw0); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc2_ls)>; + }; + + DIE_NODE(ps_afnc2_lw1): power-controller@178 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc2_lw1); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc2_ls)>; + }; + + DIE_NODE(ps_afnc3_ioa): power-controller@180 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc3_ioa); + apple,always-on; + power-domains = <&DIE_NODE(ps_afi)>; + }; + + DIE_NODE(ps_afnc3_ls): power-controller@188 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc3_ls); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc3_ioa)>; + }; + + DIE_NODE(ps_afnc3_lw0): power-controller@190 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc3_lw0); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc3_ls)>; + }; + + DIE_NODE(ps_apcie_gp): power-controller@198 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(apcie_gp); + power-domains = <&DIE_NODE(ps_afnc6_lw0)>; + }; + + DIE_NODE(ps_apcie_st): power-controller@1a0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(apcie_st); + power-domains = <&DIE_NODE(ps_afnc6_lw0)>; + }; + + DIE_NODE(ps_ans2): power-controller@1a8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ans2); + power-domains = <&DIE_NODE(ps_afnc6_lw0)>; + }; + + DIE_NODE(ps_disp0_sys): power-controller@1b0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(disp0_sys); + power-domains = <&DIE_NODE(ps_afnc2_lw0)>; + }; + + DIE_NODE(ps_jpg): power-controller@1b8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(jpg); + power-domains = <&DIE_NODE(ps_afnc2_lw0)>; + }; + + DIE_NODE(ps_sio): power-controller@1c0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(sio); + power-domains = <&DIE_NODE(ps_afnc2_lw1)>; + }; + + DIE_NODE(ps_isp_sys): power-controller@1c8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(isp_sys); + power-domains = <&DIE_NODE(ps_afnc2_lw1)>; + status = "disabled"; + }; + + DIE_NODE(ps_disp0_fe): power-controller@1d0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(disp0_fe); + power-domains = <&DIE_NODE(ps_disp0_sys)>; + }; + + DIE_NODE(ps_disp0_cpu0): power-controller@1d8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(disp0_cpu0); + power-domains = <&DIE_NODE(ps_disp0_fe)>; + apple,min-state = <4>; + }; + + DIE_NODE(ps_sio_cpu): power-controller@1e0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(sio_cpu); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_fpwm0): power-controller@1e8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(fpwm0); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_fpwm1): power-controller@1f0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(fpwm1); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_fpwm2): power-controller@1f8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(fpwm2); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c0): power-controller@200 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x200 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c0); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c1): power-controller@208 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x208 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c1); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c2): power-controller@210 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x210 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c2); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c3): power-controller@218 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x218 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c3); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c4): power-controller@220 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x220 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c4); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c5): power-controller@228 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x228 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c5); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c6): power-controller@230 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x230 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c6); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c7): power-controller@238 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x238 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c7); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c8): power-controller@240 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x240 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c8); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_spi_p): power-controller@248 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x248 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(spi_p); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_sio_spmi0): power-controller@250 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x250 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(sio_spmi0); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_sio_spmi1): power-controller@258 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x258 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(sio_spmi1); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_sio_spmi2): power-controller@260 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(sio_spmi2); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_uart_p): power-controller@268 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x268 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart_p); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_audio_p): power-controller@270 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x270 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(audio_p); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_sio_adma): power-controller@278 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x278 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(sio_adma); + power-domains = <&DIE_NODE(ps_audio_p)>, <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_aes): power-controller@280 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x280 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(aes); + apple,always-on; + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_dptx_phy_ps): power-controller@288 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x288 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dptx_phy_ps); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_spi0): power-controller@2d8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(spi0); + power-domains = <&DIE_NODE(ps_spi_p)>; + }; + + DIE_NODE(ps_spi1): power-controller@2e0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(spi1); + power-domains = <&DIE_NODE(ps_spi_p)>; + }; + + DIE_NODE(ps_spi2): power-controller@2e8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(spi2); + power-domains = <&DIE_NODE(ps_spi_p)>; + }; + + DIE_NODE(ps_spi3): power-controller@2f0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(spi3); + power-domains = <&DIE_NODE(ps_spi_p)>; + }; + + DIE_NODE(ps_spi4): power-controller@2f8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(spi4); + power-domains = <&DIE_NODE(ps_spi_p)>; + }; + + DIE_NODE(ps_spi5): power-controller@300 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x300 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(spi5); + power-domains = <&DIE_NODE(ps_spi_p)>; + }; + + DIE_NODE(ps_uart_n): power-controller@308 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x308 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart_n); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart0): power-controller@310 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x310 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart0); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_amcc1): power-controller@318 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x318 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc1); + apple,always-on; + }; + + DIE_NODE(ps_amcc3): power-controller@320 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x320 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc3); + apple,always-on; + }; + + DIE_NODE(ps_dcs_04): power-controller@328 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x328 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_04); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_05): power-controller@330 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x330 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_05); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_06): power-controller@338 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x338 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_06); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_07): power-controller@340 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x340 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_07); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_12): power-controller@348 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x348 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_12); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_13): power-controller@350 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x350 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_13); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_14): power-controller@358 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x358 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_14); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_15): power-controller@360 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x360 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_15); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_uart1): power-controller@368 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x368 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart1); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart2): power-controller@370 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x370 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart2); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart3): power-controller@378 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x378 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart3); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart4): power-controller@380 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x380 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart4); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart5): power-controller@388 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x388 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart5); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart6): power-controller@390 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x390 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart6); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_mca0): power-controller@398 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x398 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mca0); + power-domains = <&DIE_NODE(ps_audio_p)>, <&DIE_NODE(ps_sio_adma)>; + }; + + DIE_NODE(ps_mca1): power-controller@3a0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mca1); + power-domains = <&DIE_NODE(ps_audio_p)>, <&DIE_NODE(ps_sio_adma)>; + }; + + DIE_NODE(ps_mca2): power-controller@3a8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mca2); + power-domains = <&DIE_NODE(ps_audio_p)>, <&DIE_NODE(ps_sio_adma)>; + }; + + DIE_NODE(ps_mca3): power-controller@3b0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mca3); + power-domains = <&DIE_NODE(ps_audio_p)>, <&DIE_NODE(ps_sio_adma)>; + }; + + DIE_NODE(ps_dpa0): power-controller@3b8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dpa0); + power-domains = <&DIE_NODE(ps_audio_p)>; + }; + + DIE_NODE(ps_dpa1): power-controller@3c0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dpa1); + power-domains = <&DIE_NODE(ps_audio_p)>; + }; + + DIE_NODE(ps_dpa2): power-controller@3c8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dpa2); + power-domains = <&DIE_NODE(ps_audio_p)>; + }; + + DIE_NODE(ps_dpa3): power-controller@3d0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dpa3); + power-domains = <&DIE_NODE(ps_audio_p)>; + }; + + DIE_NODE(ps_msr0): power-controller@3d8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(msr0); + }; + + DIE_NODE(ps_venc_sys): power-controller@3e0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc_sys); + }; + + DIE_NODE(ps_dpa4): power-controller@3e8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dpa4); + power-domains = <&DIE_NODE(ps_audio_p)>; + }; + + DIE_NODE(ps_msr0_ase_core): power-controller@3f0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(msr0_ase_core); + power-domains = <&DIE_NODE(ps_msr0)>; + }; + + DIE_NODE(ps_apcie_gpshr_sys): power-controller@3f8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(apcie_gpshr_sys); + power-domains = <&DIE_NODE(ps_apcie_gp)>; + }; + + DIE_NODE(ps_apcie_st_sys): power-controller@408 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x408 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(apcie_st_sys); + power-domains = <&DIE_NODE(ps_apcie_st)>, <&DIE_NODE(ps_ans2)>; + }; + + DIE_NODE(ps_apcie_st1_sys): power-controller@410 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x410 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(apcie_st1_sys); + power-domains = <&DIE_NODE(ps_apcie_st_sys)>; + }; + + DIE_NODE(ps_apcie_gp_sys): power-controller@418 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x418 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(apcie_gp_sys); + power-domains = <&DIE_NODE(ps_apcie_gpshr_sys)>; + apple,always-on; /* Breaks things if shut down */ + }; + + DIE_NODE(ps_apcie_ge_sys): power-controller@420 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x420 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(apcie_ge_sys); + power-domains = <&DIE_NODE(ps_apcie_gpshr_sys)>; + }; + + DIE_NODE(ps_apcie_phy_sw): power-controller@428 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x428 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(apcie_phy_sw); + apple,always-on; /* macOS does not turn this off */ + }; + + DIE_NODE(ps_sep): power-controller@c00 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xc00 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(sep); + apple,always-on; /* Locked on */ + }; + + /* There is a dependency tree involved with these PDs, + * but we do not express it here since the ISP driver + * is supposed to sequence them in the right order anyway. + * + * This also works around spurious parent PD activation + * on machines with ISP disabled (desktops), so we don't + * have to enable/disable everything in the per-model DTs. + */ + DIE_NODE(ps_isp_cpu): power-controller@4000 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(isp_cpu); + /* power-domains = <&DIE_NODE(ps_isp_sys)>; */ + }; + + DIE_NODE(ps_isp_fe): power-controller@4008 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(isp_fe); + /* power-domains = <&DIE_NODE(ps_isp_sys)>; */ + }; + + DIE_NODE(ps_dprx): power-controller@4010 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dprx); + /* power-domains = <&DIE_NODE(ps_isp_sys)>; */ + }; + + DIE_NODE(ps_isp_vis): power-controller@4018 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(isp_vis); + /* power-domains = <&DIE_NODE(ps_isp_fe)>; */ + }; + + DIE_NODE(ps_isp_be): power-controller@4020 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(isp_be); + /* power-domains = <&DIE_NODE(ps_isp_fe)>; */ + }; + + DIE_NODE(ps_isp_raw): power-controller@4028 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4028 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(isp_raw); + /* power-domains = <&DIE_NODE(ps_isp_fe)>; */ + }; + + DIE_NODE(ps_isp_clr): power-controller@4030 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4030 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(isp_clr); + /* power-domains = <&DIE_NODE(ps_isp_be)>; */ + }; + + DIE_NODE(ps_venc_dma): power-controller@8000 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x8000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc_dma); + power-domains = <&DIE_NODE(ps_venc_sys)>; + }; + + DIE_NODE(ps_venc_pipe4): power-controller@8008 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x8008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc_pipe4); + power-domains = <&DIE_NODE(ps_venc_dma)>; + }; + + DIE_NODE(ps_venc_pipe5): power-controller@8010 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x8010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc_pipe5); + power-domains = <&DIE_NODE(ps_venc_dma)>; + }; + + DIE_NODE(ps_venc_me0): power-controller@8018 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x8018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc_me0); + power-domains = <&DIE_NODE(ps_venc_pipe5)>, <&DIE_NODE(ps_venc_pipe4)>; + }; + + DIE_NODE(ps_venc_me1): power-controller@8020 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x8020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc_me1); + power-domains = <&DIE_NODE(ps_venc_me0)>; + }; + + DIE_NODE(ps_prores): power-controller@c000 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xc000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(prores); + power-domains = <&DIE_NODE(ps_afnc3_lw0)>; + }; +}; + +&DIE_NODE(pmgr_mini) { + DIE_NODE(ps_debug): power-controller@58 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x58 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(debug); + apple,always-on; /* Core AON device */ + }; + + DIE_NODE(ps_nub_spmi0): power-controller@60 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x60 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_spmi0); + apple,always-on; /* Core AON device */ + }; + + DIE_NODE(ps_nub_spmi1): power-controller@68 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x68 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_spmi1); + apple,always-on; /* Core AON device */ + }; + + DIE_NODE(ps_nub_aon): power-controller@70 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x70 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_aon); + apple,always-on; /* Core AON device */ + }; + + DIE_NODE(ps_msg): power-controller@78 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x78 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(msg); + apple,always-on; /* Core AON device? */ + }; + + DIE_NODE(ps_nub_gpio): power-controller@80 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x80 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_gpio); + apple,always-on; /* Core AON device */ + }; + + DIE_NODE(ps_nub_fabric): power-controller@88 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x88 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_fabric); + apple,always-on; /* Core AON device */ + }; + + DIE_NODE(ps_atc0_usb_aon): power-controller@90 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x90 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc0_usb_aon); + apple,always-on; /* Needs to stay on for dwc3 to work */ + }; + + DIE_NODE(ps_atc1_usb_aon): power-controller@98 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x98 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc1_usb_aon); + apple,always-on; /* Needs to stay on for dwc3 to work */ + }; + + DIE_NODE(ps_atc2_usb_aon): power-controller@a0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xa0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc2_usb_aon); + apple,always-on; /* Needs to stay on for dwc3 to work */ + }; + + DIE_NODE(ps_atc3_usb_aon): power-controller@a8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xa8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc3_usb_aon); + apple,always-on; /* Needs to stay on for dwc3 to work */ + }; + + DIE_NODE(ps_mtp_fabric): power-controller@b0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xb0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_fabric); + apple,always-on; + power-domains = <&DIE_NODE(ps_nub_fabric)>; + status = "disabled"; + }; + + DIE_NODE(ps_nub_sram): power-controller@b8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xb8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_sram); + apple,always-on; /* Core AON device */ + }; + + DIE_NODE(ps_debug_switch): power-controller@c0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xc0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(debug_switch); + apple,always-on; /* Core AON device */ + }; + + DIE_NODE(ps_atc0_usb): power-controller@c8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xc8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc0_usb); + power-domains = <&DIE_NODE(ps_atc0_common)>; + }; + + DIE_NODE(ps_atc1_usb): power-controller@d0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xd0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc1_usb); + power-domains = <&DIE_NODE(ps_atc1_common)>; + }; + + DIE_NODE(ps_atc2_usb): power-controller@d8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xd8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc2_usb); + power-domains = <&DIE_NODE(ps_atc2_common)>; + }; + + DIE_NODE(ps_atc3_usb): power-controller@e0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xe0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc3_usb); + power-domains = <&DIE_NODE(ps_atc3_common)>; + }; + +#if 0 + /* MTP stuff is self-managed */ + DIE_NODE(ps_mtp_gpio): power-controller@e8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xe8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_gpio); + apple,always-on; /* MTP always stays on */ + power-domains = <&DIE_NODE(ps_mtp_fabric)>; + }; + + DIE_NODE(ps_mtp_base): power-controller@f0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xf0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_base); + apple,always-on; /* MTP always stays on */ + power-domains = <&DIE_NODE(ps_mtp_fabric)>; + }; + + DIE_NODE(ps_mtp_periph): power-controller@f8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xf8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_periph); + apple,always-on; /* MTP always stays on */ + power-domains = <&DIE_NODE(ps_mtp_fabric)>; + }; + + DIE_NODE(ps_mtp_spi0): power-controller@100 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_spi0); + apple,always-on; /* MTP always stays on */ + power-domains = <&DIE_NODE(ps_mtp_fabric)>; + }; + + DIE_NODE(ps_mtp_i2cm0): power-controller@108 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_i2cm0); + apple,always-on; /* MTP always stays on */ + power-domains = <&DIE_NODE(ps_mtp_fabric)>; + }; + + DIE_NODE(ps_mtp_uart0): power-controller@110 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_uart0); + apple,always-on; /* MTP always stays on */ + power-domains = <&DIE_NODE(ps_mtp_fabric)>; + }; + + DIE_NODE(ps_mtp_cpu): power-controller@118 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_cpu); + apple,always-on; /* MTP always stays on */ + power-domains = <&DIE_NODE(ps_mtp_fabric)>; + }; + + DIE_NODE(ps_mtp_scm_fabric): power-controller@120 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_scm_fabric); + apple,always-on; /* MTP always stays on */ + power-domains = <&DIE_NODE(ps_mtp_periph)>; + }; + + DIE_NODE(ps_mtp_sram): power-controller@128 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_sram); + apple,always-on; /* MTP always stays on */ + power-domains = <&DIE_NODE(ps_mtp_scm_fabric)>, <&DIE_NODE(ps_mtp_cpu)>; + }; + + DIE_NODE(ps_mtp_dma): power-controller@130 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_dma); + apple,always-on; /* MTP always stays on */ + power-domains = <&DIE_NODE(ps_mtp_sram)>; + }; +#endif +}; + +&DIE_NODE(pmgr_gfx) { + DIE_NODE(ps_gpx): power-controller@0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(gpx); + apple,min-state = <4>; + apple,always-on; + }; + + DIE_NODE(ps_afr): power-controller@100 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afr); + /* Apple Fabric, media stuff: this can power down */ + apple,min-state = <4>; + }; + + DIE_NODE(ps_gfx): power-controller@108 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(gfx); + power-domains = <&DIE_NODE(ps_afr)>, <&DIE_NODE(ps_gpx)>; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t7000.dtsi b/arch/arm64/boot/dts/apple/t7000.dtsi index 52edc8d776a9..0342455d3444 100644 --- a/arch/arm64/boot/dts/apple/t7000.dtsi +++ b/arch/arm64/boot/dts/apple/t7000.dtsi @@ -144,6 +144,62 @@ status = "disabled"; }; + i2c0: i2c@20a110000 { + compatible = "apple,t7000-i2c", "apple,i2c"; + reg = <0x2 0x0a110000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 174 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@20a111000 { + compatible = "apple,t7000-i2c", "apple,i2c"; + reg = <0x2 0x0a111000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 175 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@20a112000 { + compatible = "apple,t7000-i2c", "apple,i2c"; + reg = <0x2 0x0a112000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 176 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@20a113000 { + compatible = "apple,t7000-i2c", "apple,i2c"; + reg = <0x2 0x0a113000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 177 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pmgr: power-management@20e000000 { compatible = "apple,t7000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; #address-cells = <1>; @@ -195,6 +251,26 @@ <AIC_IRQ 66 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 67 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 68 IRQ_TYPE_LEVEL_HIGH>; + + i2c0_pins: i2c0-pins { + pinmux = <APPLE_PINMUX(97, 1)>, + <APPLE_PINMUX(96, 1)>; + }; + + i2c1_pins: i2c1-pins { + pinmux = <APPLE_PINMUX(139, 1)>, + <APPLE_PINMUX(138, 1)>; + }; + + i2c2_pins: i2c2-pins { + pinmux = <APPLE_PINMUX(65, 1)>, + <APPLE_PINMUX(64, 1)>; + }; + + i2c3_pins: i2c3-pins { + pinmux = <APPLE_PINMUX(87, 1)>, + <APPLE_PINMUX(86, 1)>; + }; }; }; diff --git a/arch/arm64/boot/dts/apple/t7001.dtsi b/arch/arm64/boot/dts/apple/t7001.dtsi index a2efa81305df..e1afb0542369 100644 --- a/arch/arm64/boot/dts/apple/t7001.dtsi +++ b/arch/arm64/boot/dts/apple/t7001.dtsi @@ -144,6 +144,62 @@ status = "disabled"; }; + i2c0: i2c@20a110000 { + compatible = "apple,t7000-i2c", "apple,i2c"; + reg = <0x2 0x0a110000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 174 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@20a111000 { + compatible = "apple,t7000-i2c", "apple,i2c"; + reg = <0x2 0x0a111000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 175 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@20a112000 { + compatible = "apple,t7000-i2c", "apple,i2c"; + reg = <0x2 0x0a112000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 176 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@20a113000 { + compatible = "apple,t7000-i2c", "apple,i2c"; + reg = <0x2 0x0a113000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 177 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pmgr: power-management@20e000000 { compatible = "apple,t7000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; #address-cells = <1>; @@ -188,6 +244,26 @@ <AIC_IRQ 66 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 67 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 68 IRQ_TYPE_LEVEL_HIGH>; + + i2c0_pins: i2c0-pins { + pinmux = <APPLE_PINMUX(38, 1)>, + <APPLE_PINMUX(37, 1)>; + }; + + i2c1_pins: i2c1-pins { + pinmux = <APPLE_PINMUX(66, 1)>, + <APPLE_PINMUX(65, 1)>; + }; + + i2c2_pins: i2c2-pins { + pinmux = <APPLE_PINMUX(133, 1)>, + <APPLE_PINMUX(132, 1)>; + }; + + i2c3_pins: i2c3-pins { + pinmux = <APPLE_PINMUX(135, 1)>, + <APPLE_PINMUX(134, 1)>; + }; }; }; diff --git a/arch/arm64/boot/dts/apple/t8010.dtsi b/arch/arm64/boot/dts/apple/t8010.dtsi index b961d4f65bc3..522b3896aa87 100644 --- a/arch/arm64/boot/dts/apple/t8010.dtsi +++ b/arch/arm64/boot/dts/apple/t8010.dtsi @@ -164,6 +164,62 @@ status = "disabled"; }; + i2c0: i2c@20a110000 { + compatible = "apple,t8010-i2c", "apple,i2c"; + reg = <0x2 0x0a110000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 232 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@20a111000 { + compatible = "apple,t8010-i2c", "apple,i2c"; + reg = <0x2 0x0a111000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 233 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@20a112000 { + compatible = "apple,t8010-i2c", "apple,i2c"; + reg = <0x2 0x0a112000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 234 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@20a113000 { + compatible = "apple,t8010-i2c", "apple,i2c"; + reg = <0x2 0x0a113000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 235 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pmgr: power-management@20e000000 { compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; #address-cells = <1>; @@ -207,6 +263,26 @@ <AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH>; + + i2c0_pins: i2c0-pins { + pinmux = <APPLE_PINMUX(197, 1)>, + <APPLE_PINMUX(196, 1)>; + }; + + i2c1_pins: i2c1-pins { + pinmux = <APPLE_PINMUX(40, 1)>, + <APPLE_PINMUX(39, 1)>; + }; + + i2c2_pins: i2c2-pins { + pinmux = <APPLE_PINMUX(132, 1)>, + <APPLE_PINMUX(133, 1)>; + }; + + i2c3_pins: i2c3-pins { + pinmux = <APPLE_PINMUX(41, 1)>, + <APPLE_PINMUX(42, 1)>; + }; }; pinctrl_aop: pinctrl@2100f0000 { diff --git a/arch/arm64/boot/dts/apple/t8011.dtsi b/arch/arm64/boot/dts/apple/t8011.dtsi index 974f78cc77cf..039aa4d1e887 100644 --- a/arch/arm64/boot/dts/apple/t8011.dtsi +++ b/arch/arm64/boot/dts/apple/t8011.dtsi @@ -168,6 +168,62 @@ status = "disabled"; }; + i2c0: i2c@20a110000 { + compatible = "apple,t8010-i2c", "apple,i2c"; + reg = <0x2 0x0a110000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 230 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@20a111000 { + compatible = "apple,t8010-i2c", "apple,i2c"; + reg = <0x2 0x0a111000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 231 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@20a112000 { + compatible = "apple,t8010-i2c", "apple,i2c"; + reg = <0x2 0x0a112000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 232 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@20a113000 { + compatible = "apple,t8010-i2c", "apple,i2c"; + reg = <0x2 0x0a113000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 233 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pmgr: power-management@20e000000 { compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; #address-cells = <1>; @@ -204,6 +260,26 @@ <AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH>; + + i2c0_pins: i2c0-pins { + pinmux = <APPLE_PINMUX(211, 1)>, + <APPLE_PINMUX(210, 1)>; + }; + + i2c1_pins: i2c1-pins { + pinmux = <APPLE_PINMUX(156, 1)>, + <APPLE_PINMUX(155, 1)>; + }; + + i2c2_pins: i2c2-pins { + pinmux = <APPLE_PINMUX(58, 1)>, + <APPLE_PINMUX(57, 1)>; + }; + + i2c3_pins: i2c3-pins { + pinmux = <APPLE_PINMUX(158, 1)>, + <APPLE_PINMUX(157, 1)>; + }; }; pinctrl_aop: pinctrl@2100f0000 { diff --git a/arch/arm64/boot/dts/apple/t8012.dtsi b/arch/arm64/boot/dts/apple/t8012.dtsi index a259e5735d93..e7923814169b 100644 --- a/arch/arm64/boot/dts/apple/t8012.dtsi +++ b/arch/arm64/boot/dts/apple/t8012.dtsi @@ -11,6 +11,7 @@ #include <dt-bindings/interrupt-controller/apple-aic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pinctrl/apple.h> +#include <dt-bindings/spmi/spmi.h> / { interrupt-parent = <&aic>; @@ -220,6 +221,13 @@ <AIC_IRQ 137 IRQ_TYPE_LEVEL_HIGH>; }; + spmi: spmi@211180700 { + compatible = "apple,t8012-spmi", "apple,t8103-spmi"; + reg = <0x2 0x11180700 0x0 0x100>; + #address-cells = <2>; + #size-cells = <0>; + }; + pinctrl_nub: pinctrl@2111f0000 { compatible = "apple,t8010-pinctrl", "apple,pinctrl"; reg = <0x2 0x111f0000 0x0 0x1000>; diff --git a/arch/arm64/boot/dts/apple/t8015-pmgr.dtsi b/arch/arm64/boot/dts/apple/t8015-pmgr.dtsi index e238c2d2732f..1d8da9c7863e 100644 --- a/arch/arm64/boot/dts/apple/t8015-pmgr.dtsi +++ b/arch/arm64/boot/dts/apple/t8015-pmgr.dtsi @@ -658,6 +658,7 @@ #power-domain-cells = <0>; #reset-cells = <0>; label = "pcie"; + power-domains = <&ps_pcie_aux>, <&ps_pcie_direct>, <&ps_pcie_ref>; }; ps_pcie_aux: power-controller@80320 { diff --git a/arch/arm64/boot/dts/apple/t8015.dtsi b/arch/arm64/boot/dts/apple/t8015.dtsi index 12acf8fc8bc6..586d3cf1f375 100644 --- a/arch/arm64/boot/dts/apple/t8015.dtsi +++ b/arch/arm64/boot/dts/apple/t8015.dtsi @@ -11,6 +11,7 @@ #include <dt-bindings/interrupt-controller/apple-aic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pinctrl/apple.h> +#include <dt-bindings/spmi/spmi.h> / { interrupt-parent = <&aic>; @@ -265,6 +266,62 @@ #performance-domain-cells = <0>; }; + i2c0: i2c@22e200000 { + compatible = "apple,t8015-i2c", "apple,i2c"; + reg = <0x2 0x2e200000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 304 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@22e204000 { + compatible = "apple,t8015-i2c", "apple,i2c"; + reg = <0x2 0x2e204000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 305 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@22e208000 { + compatible = "apple,t8015-i2c", "apple,i2c"; + reg = <0x2 0x2e208000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 306 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@22e20c000 { + compatible = "apple,t8015-i2c", "apple,i2c"; + reg = <0x2 0x2e20c000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 307 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + serial0: serial@22e600000 { compatible = "apple,s5l-uart"; reg = <0x2 0x2e600000 0x0 0x4000>; @@ -321,6 +378,26 @@ <AIC_IRQ 54 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 55 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 56 IRQ_TYPE_LEVEL_HIGH>; + + i2c0_pins: i2c0-pins { + pinmux = <APPLE_PINMUX(73, 1)>, + <APPLE_PINMUX(72, 1)>; + }; + + i2c1_pins: i2c1-pins { + pinmux = <APPLE_PINMUX(182, 1)>, + <APPLE_PINMUX(181, 1)>; + }; + + i2c2_pins: i2c2-pins { + pinmux = <APPLE_PINMUX(4, 1)>, + <APPLE_PINMUX(3, 1)>; + }; + + i2c3_pins: i2c3-pins { + pinmux = <APPLE_PINMUX(184, 1)>, + <APPLE_PINMUX(183, 1)>; + }; }; pinctrl_aop: pinctrl@2340f0000 { @@ -344,6 +421,13 @@ <AIC_IRQ 141 IRQ_TYPE_LEVEL_HIGH>; }; + spmi: spmi@235180700 { + compatible = "apple,t8015-spmi", "apple,t8103-spmi"; + reg = <0x2 0x35180700 0x0 0x100>; + #address-cells = <2>; + #size-cells = <0>; + }; + pinctrl_nub: pinctrl@2351f0000 { compatible = "apple,t8015-pinctrl", "apple,pinctrl"; reg = <0x2 0x351f0000 0x0 0x4000>; @@ -402,6 +486,40 @@ */ status = "disabled"; }; + + ans_mbox: mbox@257008000 { + compatible = "apple,t8015-asc-mailbox"; + reg = <0x2 0x57008000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 265 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 266 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 267 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "send-empty", "send-not-empty", + "recv-empty", "recv-not-empty"; + #mbox-cells = <0>; + power-domains = <&ps_ans2>; + }; + + sart: iommu@259c50000 { + compatible = "apple,t8015-sart"; + reg = <0x2 0x59c50000 0x0 0x10000>; + power-domains = <&ps_ans2>; + }; + + nvme@259cc0000 { + compatible = "apple,t8015-nvme-ans2"; + reg = <0x2 0x59cc0000 0x0 0x40000>, + <0x2 0x59d20000 0x0 0x2000>; + reg-names = "nvme", "ans"; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>; + mboxes = <&ans_mbox>; + apple,sart = <&sart>; + power-domains = <&ps_ans2>, <&ps_pcie>; + power-domain-names = "ans", "apcie0"; + resets = <&ps_ans2>; + }; }; timer { diff --git a/arch/arm64/boot/dts/apple/t8103-j457.dts b/arch/arm64/boot/dts/apple/t8103-j457.dts index 152f95fd49a2..7089ccf3ce55 100644 --- a/arch/arm64/boot/dts/apple/t8103-j457.dts +++ b/arch/arm64/boot/dts/apple/t8103-j457.dts @@ -21,6 +21,14 @@ }; }; +/* + * Adjust pcie0's iommu-map to account for the disabled port01. + */ +&pcie0 { + iommu-map = <0x100 &pcie0_dart_0 1 1>, + <0x200 &pcie0_dart_2 1 1>; +}; + &bluetooth0 { brcm,board-type = "apple,santorini"; }; @@ -36,10 +44,10 @@ */ &port02 { - bus-range = <3 3>; + bus-range = <2 2>; status = "okay"; ethernet0: ethernet@0,0 { - reg = <0x30000 0x0 0x0 0x0 0x0>; + reg = <0x20000 0x0 0x0 0x0 0x0>; /* To be filled by the loader */ local-mac-address = [00 10 18 00 00 00]; }; diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index 589ddc039799..8b7b27887968 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -896,6 +896,41 @@ interrupts = <AIC_IRQ 338 IRQ_TYPE_LEVEL_HIGH>; }; + smc: smc@23e400000 { + compatible = "apple,t8103-smc", "apple,smc"; + reg = <0x2 0x3e400000 0x0 0x4000>, + <0x2 0x3fe00000 0x0 0x100000>; + reg-names = "smc", "sram"; + mboxes = <&smc_mbox>; + + smc_gpio: gpio { + compatible = "apple,smc-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + smc_reboot: reboot { + compatible = "apple,smc-reboot"; + nvmem-cells = <&shutdown_flag>, <&boot_stage>, + <&boot_error_count>, <&panic_count>; + nvmem-cell-names = "shutdown_flag", "boot_stage", + "boot_error_count", "panic_count"; + }; + }; + + smc_mbox: mbox@23e408000 { + compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4"; + reg = <0x2 0x3e408000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 400 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 401 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 402 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 403 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "send-empty", "send-not-empty", + "recv-empty", "recv-not-empty"; + #mbox-cells = <0>; + }; + pinctrl_smc: pinctrl@23e820000 { compatible = "apple,t8103-pinctrl", "apple,pinctrl"; reg = <0x2 0x3e820000 0x0 0x4000>; diff --git a/arch/arm64/boot/dts/apple/t8112-j415.dts b/arch/arm64/boot/dts/apple/t8112-j415.dts new file mode 100644 index 000000000000..b54e218e5384 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8112-j415.dts @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple MacBook Air (15-inch, M2, 2023) + * + * target-type: J415 + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t8112.dtsi" +#include "t8112-jxxx.dtsi" +#include <dt-bindings/leds/common.h> + +/ { + compatible = "apple,j415", "apple,t8112", "apple,arm-platform"; + model = "Apple MacBook Air (15-inch, M2, 2023)"; + + aliases { + bluetooth0 = &bluetooth0; + wifi0 = &wifi0; + }; + + led-controller { + compatible = "pwm-leds"; + led-0 { + pwms = <&fpwm1 0 40000>; + label = "kbd_backlight"; + function = LED_FUNCTION_KBD_BACKLIGHT; + color = <LED_COLOR_ID_WHITE>; + max-brightness = <255>; + default-state = "keep"; + }; + }; +}; + +/* + * Force the bus number assignments so that we can declare some of the + * on-board devices and properties that are populated by the bootloader + * (such as MAC addresses). + */ +&port00 { + bus-range = <1 1>; + wifi0: wifi@0,0 { + compatible = "pci14e4,4433"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + /* To be filled by the loader */ + local-mac-address = [00 10 18 00 00 10]; + apple,antenna-sku = "XX"; + brcm,board-type = "apple,snake"; + }; + + bluetooth0: bluetooth@0,1 { + compatible = "pci14e4,5f71"; + reg = <0x10100 0x0 0x0 0x0 0x0>; + /* To be filled by the loader */ + local-bd-address = [00 00 00 00 00 00]; + brcm,board-type = "apple,snake"; + }; +}; + +&i2c0 { + /* MagSafe port */ + hpm5: usb-pd@3a { + compatible = "apple,cd321x"; + reg = <0x3a>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; +}; + +&i2c4 { + status = "okay"; +}; + +&fpwm1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t8112.dtsi b/arch/arm64/boot/dts/apple/t8112.dtsi index b36b345861b6..3f79878b25af 100644 --- a/arch/arm64/boot/dts/apple/t8112.dtsi +++ b/arch/arm64/boot/dts/apple/t8112.dtsi @@ -899,6 +899,41 @@ }; }; + smc: smc@23e400000 { + compatible = "apple,t8112-smc", "apple,smc"; + reg = <0x2 0x3e400000 0x0 0x4000>, + <0x2 0x3fe00000 0x0 0x100000>; + reg-names = "smc", "sram"; + mboxes = <&smc_mbox>; + + smc_gpio: gpio { + compatible = "apple,smc-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + smc_reboot: reboot { + compatible = "apple,smc-reboot"; + nvmem-cells = <&shutdown_flag>, <&boot_stage>, + <&boot_error_count>, <&panic_count>; + nvmem-cell-names = "shutdown_flag", "boot_stage", + "boot_error_count", "panic_count"; + }; + }; + + smc_mbox: mbox@23e408000 { + compatible = "apple,t8112-asc-mailbox", "apple,asc-mailbox-v4"; + reg = <0x2 0x3e408000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 499 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 500 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 501 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 502 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "send-empty", "send-not-empty", + "recv-empty", "recv-not-empty"; + #mbox-cells = <0>; + }; + pinctrl_smc: pinctrl@23e820000 { compatible = "apple,t8112-pinctrl", "apple,pinctrl"; reg = <0x2 0x3e820000 0x0 0x4000>; diff --git a/arch/arm64/boot/dts/axiado/ax3000-evk.dts b/arch/arm64/boot/dts/axiado/ax3000-evk.dts index 92101c5b534b..b86e96962557 100644 --- a/arch/arm64/boot/dts/axiado/ax3000-evk.dts +++ b/arch/arm64/boot/dts/axiado/ax3000-evk.dts @@ -14,6 +14,9 @@ #size-cells = <2>; aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; serial3 = &uart3; }; diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts index 6ea3c102e0d6..04738bf281eb 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts @@ -2,6 +2,7 @@ /dts-v1/; #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> #include "bcm2712.dtsi" / { @@ -29,6 +30,20 @@ reg = <0 0 0 0x28000000>; }; + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_button_default>; + status = "okay"; + + power_button: power-button { + label = "pwr_button"; + linux,code = <KEY_POWER>; + gpios = <&gio 20 GPIO_ACTIVE_LOW>; + debounce-interval = <50>; + }; + }; + sd_io_1v8_reg: sd-io-1v8-reg { compatible = "regulator-gpio"; regulator-name = "vdd-sd-io"; @@ -51,6 +66,90 @@ enable-active-high; gpios = <&gio_aon 4 GPIO_ACTIVE_HIGH>; }; + + wl_on_reg: wl-on-reg { + compatible = "regulator-fixed"; + regulator-name = "wl-on-regulator"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-0 = <&wl_on_default>; + pinctrl-names = "default"; + gpio = <&gio 28 GPIO_ACTIVE_HIGH>; + startup-delay-us = <150000>; + enable-active-high; + }; +}; + +&pinctrl { + bt_shutdown_default: bt-shutdown-default-state { + function = "gpio"; + pins = "gpio29"; + }; + + emmc_sd_default: emmc-sd-default-state { + pins = "emmc_cmd", "emmc_dat0", "emmc_dat1", "emmc_dat2", "emmc_dat3"; + bias-pull-up; + }; + + pwr_button_default: pwr-button-default-state { + function = "gpio"; + pins = "gpio20"; + bias-pull-up; + }; + + sdio2_30_default: sdio2-30-default-state { + clk-pins { + function = "sd2"; + pins = "gpio30"; + bias-disable; + }; + cmd-pins { + function = "sd2"; + pins = "gpio31"; + bias-pull-up; + }; + dat-pins { + function = "sd2"; + pins = "gpio32", "gpio33", "gpio34", "gpio35"; + bias-pull-up; + }; + }; + + uarta_24_default: uarta-24-default-state { + rts-pins { + function = "uart0"; + pins = "gpio24"; + bias-disable; + }; + cts-pins { + function = "uart0"; + pins = "gpio25"; + bias-pull-up; + }; + txd-pins { + function = "uart0"; + pins = "gpio26"; + bias-disable; + }; + rxd-pins { + function = "uart0"; + pins = "gpio27"; + bias-pull-up; + }; + }; + + wl_on_default: wl-on-default-state { + function = "gpio"; + pins = "gpio28"; + }; +}; + +&pinctrl_aon { + emmc_aon_cd_default: emmc-aon-cd-default-state { + function = "sd_card_g"; + pins = "aon_gpio5"; + bias-pull-up; + }; }; /* The Debug UART, on Rpi5 it's on JST-SH 1.0mm 3-pin connector @@ -62,12 +161,32 @@ /* SDIO1 is used to drive the SD card */ &sdio1 { + pinctrl-0 = <&emmc_sd_default>, <&emmc_aon_cd_default>; + pinctrl-names = "default"; vqmmc-supply = <&sd_io_1v8_reg>; vmmc-supply = <&sd_vcc_reg>; bus-width = <4>; sd-uhs-sdr50; sd-uhs-ddr50; sd-uhs-sdr104; + cd-gpios = <&gio_aon 5 GPIO_ACTIVE_LOW>; +}; + +&sdio2 { + pinctrl-0 = <&sdio2_30_default>; + pinctrl-names = "default"; + bus-width = <4>; + vmmc-supply = <&wl_on_reg>; + sd-uhs-ddr50; + non-removable; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + wifi: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; }; &soc { @@ -97,6 +216,20 @@ }; }; +/* uarta communicates with the BT module */ +&uarta { + uart-has-rtscts; + pinctrl-0 = <&uarta_24_default &bt_shutdown_default>; + pinctrl-names = "default"; + status = "okay"; + + bluetooth: bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <3000000>; + shutdown-gpios = <&gio 29 GPIO_ACTIVE_HIGH>; + }; +}; + &hvs { clocks = <&firmware_clocks 4>, <&firmware_clocks 16>; clock-names = "core", "disp"; diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts index a70a9b158df3..b8f256545022 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts @@ -4,8 +4,14 @@ * the RP1 driver to load the RP1 dtb overlay at runtime, while * bcm2712-rpi-5-b.dts (this file) is the fully defined one (i.e. it * already contains RP1 node, so no overlay is loaded nor needed). - * This file is not intended to be modified, nodes should be added - * to the included bcm2712-rpi-5-b-ovl-rp1.dts. + * This file is intended to host the override nodes for the RP1 peripherals, + * e.g. to declare the phy of the ethernet interface or the custom pin setup + * for several RP1 peripherals. + * This in turn is due to the fact that there's no current generic + * infrastructure to reference nodes (i.e. the nodes in rp1-common.dtsi) that + * are not yet defined in the DT since they are loaded at runtime via overlay. + * All other nodes that do not have anything to do with RP1 should be added + * to the included bcm2712-rpi-5-b-ovl-rp1.dts instead. */ /dts-v1/; @@ -16,10 +22,37 @@ #include "rp1-nexus.dtsi" }; -&pcie1 { +&rp1_eth { status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <&phy1>; + + mdio { + reg = <0x1>; + reset-gpios = <&rp1_gpio 32 GPIO_ACTIVE_LOW>; + reset-delay-us = <5000>; + #address-cells = <1>; + #size-cells = <0>; + + phy1: ethernet-phy@1 { + reg = <0x1>; + }; + }; }; -&pcie2 { +&rp1_gpio { + usb_vbus_default_state: usb-vbus-default-state { + function = "vbus1"; + groups = "vbus1"; + }; +}; + +&rp1_usb0 { + pinctrl-0 = <&usb_vbus_default_state>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rp1_usb1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi index 0a9212d3106f..e77a66adc22a 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -38,6 +38,13 @@ clock-frequency = <200000000>; clock-output-names = "emmc2-clock"; }; + + clk_sw_baud: clk-sw-baud { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <96000000>; + clock-output-names = "sw-baud"; + }; }; cpus: cpus { @@ -243,6 +250,39 @@ status = "disabled"; }; + pinctrl: pinctrl@7d504100 { + compatible = "brcm,bcm2712c0-pinctrl"; + reg = <0x7d504100 0x30>; + }; + + gio: gpio@7d508500 { + compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; + reg = <0x7d508500 0x40>; + interrupt-parent = <&main_irq>; + interrupts = <0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + brcm,gpio-bank-widths = <32 22>; + }; + + uarta: serial@7d50c000 { + compatible = "brcm,bcm7271-uart"; + reg = <0x7d50c000 0x20>; + reg-names = "uart"; + clocks = <&clk_sw_baud>; + clock-names = "sw_baud"; + interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uart"; + status = "disabled"; + }; + + pinctrl_aon: pinctrl@7d510700 { + compatible = "brcm,bcm2712c0-aon-pinctrl"; + reg = <0x7d510700 0x20>; + }; + interrupt-controller@7d517000 { compatible = "brcm,bcm7271-l2-intc"; reg = <0x7d517000 0x10>; @@ -263,6 +303,21 @@ */ }; + sdio2: mmc@1100000 { + compatible = "brcm,bcm2712-sdhci", + "brcm,sdhci-brcmstb"; + reg = <0x01100000 0x260>, + <0x01100400 0x200>; + reg-names = "host", "cfg"; + interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_emmc2>; + clock-names = "sw_sdio"; + sdhci-caps-mask = <0x0000C000 0x0>; + sdhci-caps = <0x0 0x0>; + mmc-ddr-3_3v; + status = "disabled"; + }; + gicv2: interrupt-controller@7fff9000 { compatible = "arm,gic-400"; reg = <0x7fff9000 0x1000>, @@ -270,6 +325,7 @@ <0x7fffc000 0x2000>, <0x7fffe000 0x2000>; interrupt-controller; + #address-cells = <0>; #interrupt-cells = <3>; }; diff --git a/arch/arm64/boot/dts/broadcom/rp1-common.dtsi b/arch/arm64/boot/dts/broadcom/rp1-common.dtsi index 5002a375eb0b..5a815c379794 100644 --- a/arch/arm64/boot/dts/broadcom/rp1-common.dtsi +++ b/arch/arm64/boot/dts/broadcom/rp1-common.dtsi @@ -39,4 +39,48 @@ pci_ep_bus: pci-ep-bus@1 { <1 IRQ_TYPE_LEVEL_HIGH>, <2 IRQ_TYPE_LEVEL_HIGH>; }; + + rp1_eth: ethernet@40100000 { + compatible = "raspberrypi,rp1-gem"; + reg = <0x00 0x40100000 0x0 0x4000>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_SYS>, + <&rp1_clocks RP1_CLK_SYS>, + <&rp1_clocks RP1_CLK_ETH>, + <&rp1_clocks RP1_CLK_ETH_TSU>; + clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + rp1_usb0: usb@40200000 { + compatible = "snps,dwc3"; + reg = <0x00 0x40200000 0x0 0x100000>; + interrupts = <31 IRQ_TYPE_EDGE_RISING>; + dr_mode = "host"; + usb3-lpm-capable; + snps,dis_rxdet_inp3_quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + snps,tx-max-burst = /bits/ 8 <8>; + snps,tx-thr-num-pkt = /bits/ 8 <2>; + status = "disabled"; + }; + + rp1_usb1: usb@40300000 { + compatible = "snps,dwc3"; + reg = <0x00 0x40300000 0x0 0x100000>; + interrupts = <36 IRQ_TYPE_EDGE_RISING>; + dr_mode = "host"; + usb3-lpm-capable; + snps,dis_rxdet_inp3_quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + snps,tx-max-burst = /bits/ 8 <8>; + snps,tx-thr-num-pkt = /bits/ 8 <2>; + status = "disabled"; + }; }; diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi index 7dfe7677e649..2fb2c99c0796 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -192,6 +192,78 @@ #address-cells = <2>; #size-cells = <2>; + i2c0: i2c@4010000 { + compatible = "cdns,i2c-r1p14"; + reg = <0x0 0x04010000 0x0 0x10000>; + clock-frequency = <400000>; + clocks = <&scmi_clk CLK_TREE_FCH_I2C0_APB>; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH 0>; + status = "disabled"; + }; + + i2c1: i2c@4020000 { + compatible = "cdns,i2c-r1p14"; + reg = <0x0 0x04020000 0x0 0x10000>; + clock-frequency = <400000>; + clocks = <&scmi_clk CLK_TREE_FCH_I2C1_APB>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH 0>; + status = "disabled"; + }; + + i2c2: i2c@4030000 { + compatible = "cdns,i2c-r1p14"; + reg = <0x0 0x04030000 0x0 0x10000>; + clock-frequency = <400000>; + clocks = <&scmi_clk CLK_TREE_FCH_I2C2_APB>; + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH 0>; + status = "disabled"; + }; + + i2c3: i2c@4040000 { + compatible = "cdns,i2c-r1p14"; + reg = <0x0 0x04040000 0x0 0x10000>; + clock-frequency = <400000>; + clocks = <&scmi_clk CLK_TREE_FCH_I2C3_APB>; + interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>; + status = "disabled"; + }; + + i2c4: i2c@4050000 { + compatible = "cdns,i2c-r1p14"; + reg = <0x0 0x04050000 0x0 0x10000>; + clock-frequency = <400000>; + clocks = <&scmi_clk CLK_TREE_FCH_I2C4_APB>; + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH 0>; + status = "disabled"; + }; + + i2c5: i2c@4060000 { + compatible = "cdns,i2c-r1p14"; + reg = <0x0 0x04060000 0x0 0x10000>; + clock-frequency = <400000>; + clocks = <&scmi_clk CLK_TREE_FCH_I2C5_APB>; + interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH 0>; + status = "disabled"; + }; + + i2c6: i2c@4070000 { + compatible = "cdns,i2c-r1p14"; + reg = <0x0 0x04070000 0x0 0x10000>; + clock-frequency = <400000>; + clocks = <&scmi_clk CLK_TREE_FCH_I2C6_APB>; + interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH 0>; + status = "disabled"; + }; + + i2c7: i2c@4080000 { + compatible = "cdns,i2c-r1p14"; + reg = <0x0 0x04080000 0x0 0x10000>; + clock-frequency = <400000>; + clocks = <&scmi_clk CLK_TREE_FCH_I2C7_APB>; + interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>; + status = "disabled"; + }; + uart0: serial@40b0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0x040b0000 0x0 0x1000>; @@ -228,6 +300,34 @@ status = "disabled"; }; + i3c0: i3c@40f0000 { + compatible = "cdns,i3c-master"; + reg = <0x0 0x040f0000 0x0 0x10000>; + #address-cells = <3>; + #size-cells = <0>; + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&scmi_clk CLK_TREE_FCH_I3C0_APB>, + <&scmi_clk CLK_TREE_FCH_I3C0_FUNC>; + clock-names = "pclk", "sysclk"; + i3c-scl-hz = <400000>; + i2c-scl-hz = <100000>; + status = "disabled"; + }; + + i3c1: i3c@4100000 { + compatible = "cdns,i3c-master"; + reg = <0x0 0x04100000 0x0 0x10000>; + #address-cells = <3>; + #size-cells = <0>; + interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&scmi_clk CLK_TREE_FCH_I3C1_APB>, + <&scmi_clk CLK_TREE_FCH_I3C1_FUNC>; + clock-names = "pclk", "sysclk"; + i3c-scl-hz = <400000>; + i2c-scl-hz = <100000>; + status = "disabled"; + }; + mbox_ap2se: mailbox@5060000 { compatible = "cix,sky1-mbox"; reg = <0x0 0x05060000 0x0 0x10000>; diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile index bdb9e9813e50..bcca63136557 100644 --- a/arch/arm64/boot/dts/exynos/Makefile +++ b/arch/arm64/boot/dts/exynos/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +subdir-y += axis subdir-y += google dtb-$(CONFIG_ARCH_EXYNOS) += \ diff --git a/arch/arm64/boot/dts/exynos/axis/Makefile b/arch/arm64/boot/dts/exynos/axis/Makefile new file mode 100644 index 000000000000..ccf00de64016 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/axis/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +dtb-$(CONFIG_ARCH_ARTPEC) += \ + artpec8-grizzly.dtb diff --git a/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h b/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h new file mode 100644 index 000000000000..2c151aa98c96 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Axis ARTPEC-8 SoC device tree pinctrl constants + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2025 Axis Communications AB. + * https://www.axis.com + */ + +#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ +#define __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ + +#define ARTPEC_PIN_PULL_NONE 0 +#define ARTPEC_PIN_PULL_DOWN 1 +#define ARTPEC_PIN_PULL_UP 3 + +#define ARTPEC_PIN_FUNC_INPUT 0 +#define ARTPEC_PIN_FUNC_OUTPUT 1 +#define ARTPEC_PIN_FUNC_2 2 +#define ARTPEC_PIN_FUNC_3 3 +#define ARTPEC_PIN_FUNC_4 4 +#define ARTPEC_PIN_FUNC_5 5 +#define ARTPEC_PIN_FUNC_6 6 +#define ARTPEC_PIN_FUNC_EINT 0xf +#define ARTPEC_PIN_FUNC_F ARTPEC_PIN_FUNC_EINT + +/* Drive strength for ARTPEC */ +#define ARTPEC_PIN_DRV_SR1 0x8 +#define ARTPEC_PIN_DRV_SR2 0x9 +#define ARTPEC_PIN_DRV_SR3 0xa +#define ARTPEC_PIN_DRV_SR4 0xb +#define ARTPEC_PIN_DRV_SR5 0xc +#define ARTPEC_PIN_DRV_SR6 0xd + +#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ */ diff --git a/arch/arm64/boot/dts/exynos/axis/artpec8-grizzly.dts b/arch/arm64/boot/dts/exynos/axis/artpec8-grizzly.dts new file mode 100644 index 000000000000..5ae864ec3193 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/axis/artpec8-grizzly.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Axis ARTPEC-8 Grizzly board device tree source + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2025 Axis Communications AB. + * https://www.axis.com + */ + +/dts-v1/; +#include "artpec8.dtsi" +#include "artpec8-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> +/ { + model = "ARTPEC-8 grizzly board"; + compatible = "axis,artpec8-grizzly", "axis,artpec8"; + + aliases { + serial0 = &serial_0; + }; + + chosen { + stdout-path = &serial_0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; +}; + +&osc_clk { + clock-frequency = <50000000>; +}; diff --git a/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi new file mode 100644 index 000000000000..8d239a70f1b4 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Axis ARTPEC-8 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2025 Axis Communications AB. + * https://www.axis.com + */ + +#include "artpec-pinctrl.h" + +&pinctrl_fsys { + gpe0: gpe0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe1: gpe1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe2: gpe2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf2: gpf2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf3: gpf3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf4: gpf4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gps0: gps0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gps1: gps1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + serial0_bus: serial0-bus-pins { + samsung,pins = "gpf4-4", "gpf4-5"; + samsung,pin-function = <ARTPEC_PIN_FUNC_2>; + samsung,pin-pud = <ARTPEC_PIN_PULL_UP>; + samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>; + }; +}; + +&pinctrl_peric { + gpa0: gpa0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa2: gpa2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk0: gpk0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/axis/artpec8.dtsi b/arch/arm64/boot/dts/exynos/axis/artpec8.dtsi new file mode 100644 index 000000000000..db9833297982 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/axis/artpec8.dtsi @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Axis ARTPEC-8 SoC device tree source + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2025 Axis Communications AB. + * https://www.axis.com + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/axis,artpec8-clk.h> + +/ { + compatible = "axis,artpec8"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + pinctrl0 = &pinctrl_fsys; + pinctrl1 = &pinctrl_peric; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + cpu-idle-states = <&cpu_sleep>; + clocks = <&cmu_cpucl CLK_GOUT_CPUCL_CLUSTER_CPU>; + clock-names = "cpu"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + cpu-idle-states = <&cpu_sleep>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + enable-method = "psci"; + cpu-idle-states = <&cpu_sleep>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + enable-method = "psci"; + cpu-idle-states = <&cpu_sleep>; + }; + + idle-states { + entry-method = "psci"; + + cpu_sleep: cpu-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <300>; + exit-latency-us = <1200>; + min-residency-us = <2000>; + }; + }; + }; + + fin_pll: clock-finpll { + compatible = "fixed-factor-clock"; + clocks = <&osc_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "fin_pll"; + }; + + osc_clk: clock-osc { + /* XXTI */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "osc_clk"; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + soc: soc@0 { + compatible = "simple-bus"; + ranges = <0x0 0x0 0x0 0x17000000>; + #address-cells = <1>; + #size-cells = <1>; + + cmu_imem: clock-controller@10010000 { + compatible = "axis,artpec8-cmu-imem"; + reg = <0x10010000 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_IMEM_ACLK>, + <&cmu_cmu CLK_DOUT_CMU_IMEM_JPEG>; + clock-names = "fin_pll", "aclk", "jpeg"; + }; + + timer@10040000 { + compatible = "axis,artpec8-mct", "samsung,exynos4210-mct"; + reg = <0x10040000 0x1000>; + clocks = <&fin_pll>, <&cmu_imem CLK_GOUT_IMEM_MCT_PCLK>; + clock-names = "fin_pll", "mct"; + interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; + }; + + gic: interrupt-controller@10201000 { + compatible = "arm,gic-400"; + reg = <0x10201000 0x1000>, + <0x10202000 0x2000>, + <0x10204000 0x2000>, + <0x10206000 0x2000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + cmu_cpucl: clock-controller@11410000 { + compatible = "axis,artpec8-cmu-cpucl"; + reg = <0x11410000 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_CPUCL_SWITCH>; + clock-names = "fin_pll", "switch"; + }; + + cmu_cmu: clock-controller@12400000 { + compatible = "axis,artpec8-cmu-cmu"; + reg = <0x12400000 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>; + clock-names = "fin_pll"; + }; + + cmu_core: clock-controller@12410000 { + compatible = "axis,artpec8-cmu-core"; + reg = <0x12410000 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_CORE_MAIN>, + <&cmu_cmu CLK_DOUT_CMU_CORE_DLP>; + clock-names = "fin_pll", "main", "dlp"; + }; + + cmu_bus: clock-controller@12c10000 { + compatible = "axis,artpec8-cmu-bus"; + reg = <0x12c10000 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_BUS>, + <&cmu_cmu CLK_DOUT_CMU_BUS_DLP>; + clock-names = "fin_pll", "bus", "dlp"; + }; + + cmu_peri: clock-controller@16410000 { + compatible = "axis,artpec8-cmu-peri"; + reg = <0x16410000 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_PERI_IP>, + <&cmu_cmu CLK_DOUT_CMU_PERI_AUDIO>, + <&cmu_cmu CLK_DOUT_CMU_PERI_DISP>; + clock-names = "fin_pll", "ip", "audio", "disp"; + }; + + pinctrl_peric: pinctrl@165f0000 { + compatible = "axis,artpec8-pinctrl"; + reg = <0x165f0000 0x1000>; + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + }; + + cmu_fsys: clock-controller@16c10000 { + compatible = "axis,artpec8-cmu-fsys"; + reg = <0x16c10000 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN0>, + <&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN1>, + <&cmu_cmu CLK_DOUT_CMU_FSYS_BUS>, + <&cmu_cmu CLK_DOUT_CMU_FSYS_IP>; + clock-names = "fin_pll", "scan0", "scan1", "bus", "ip"; + }; + + pinctrl_fsys: pinctrl@16c30000 { + compatible = "axis,artpec8-pinctrl"; + reg = <0x16c30000 0x1000>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + }; + + serial_0: serial@16cc0000 { + compatible = "axis,artpec8-uart"; + reg = <0x16cc0000 0x100>; + clocks = <&cmu_fsys CLK_GOUT_FSYS_UART0_PCLK>, + <&cmu_fsys CLK_GOUT_FSYS_UART0_SCLK_UART>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&serial0_bus>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi index f618ff290604..5877da7baf5c 100644 --- a/arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi @@ -1438,7 +1438,7 @@ samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; - hsi223_bus: hsi2c23-bus-pins { + hsi2c23_bus: hsi2c23-bus-pins { samsung,pins = "gpp11-2", "gpp11-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/dts/exynos/exynos2200.dtsi index 6b5ac02d010f..6487ccb58ae7 100644 --- a/arch/arm64/boot/dts/exynos/exynos2200.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi @@ -7,6 +7,7 @@ #include <dt-bindings/clock/samsung,exynos2200-cmu.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/soc/samsung,exynos-usi.h> / { compatible = "samsung,exynos2200"; @@ -221,22 +222,22 @@ method = "smc"; }; - soc { + soc@0 { compatible = "simple-bus"; - ranges; + ranges = <0x0 0x0 0x0 0x20000000>; - #address-cells = <2>; - #size-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; chipid@10000000 { compatible = "samsung,exynos2200-chipid", "samsung,exynos850-chipid"; - reg = <0x0 0x10000000 0x0 0x24>; + reg = <0x10000000 0x24>; }; cmu_peris: clock-controller@10020000 { compatible = "samsung,exynos2200-cmu-peris"; - reg = <0x0 0x10020000 0x0 0x8000>; + reg = <0x10020000 0x8000>; #clock-cells = <1>; clocks = <&cmu_top CLK_DOUT_TCXO_DIV3>, @@ -250,7 +251,7 @@ mct_peris: timer@10040000 { compatible = "samsung,exynos2200-mct-peris", "samsung,exynos4210-mct"; - reg = <0x0 0x10040000 0x0 0x800>; + reg = <0x10040000 0x800>; clocks = <&cmu_top CLK_DOUT_TCXO_DIV3>, <&cmu_peris CLK_MOUT_PERIS_GIC>; clock-names = "fin_pll", "mct"; interrupts = <GIC_SPI 943 IRQ_TYPE_LEVEL_HIGH 0>, @@ -270,9 +271,10 @@ gic: interrupt-controller@10200000 { compatible = "arm,gic-v3"; - reg = <0x0 0x10200000 0x0 0x10000>, /* GICD */ - <0x0 0x10240000 0x0 0x200000>; /* GICR * 8 */ + reg = <0x10200000 0x10000>, /* GICD */ + <0x10240000 0x200000>; /* GICR * 8 */ + #address-cells = <0>; #interrupt-cells = <4>; interrupt-controller; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; @@ -294,7 +296,7 @@ cmu_peric0: clock-controller@10400000 { compatible = "samsung,exynos2200-cmu-peric0"; - reg = <0x0 0x10400000 0x0 0x8000>; + reg = <0x10400000 0x8000>; #clock-cells = <1>; clocks = <&xtcxo>, @@ -306,17 +308,87 @@ syscon_peric0: syscon@10420000 { compatible = "samsung,exynos2200-peric0-sysreg", "syscon"; - reg = <0x0 0x10420000 0x0 0x2000>; + reg = <0x10420000 0x10000>; }; pinctrl_peric0: pinctrl@10430000 { compatible = "samsung,exynos2200-pinctrl"; - reg = <0x0 0x10430000 0x0 0x1000>; + reg = <0x10430000 0x1000>; + }; + + usi4: usi@105000c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x105000c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric0 CLK_DOUT_PERIC0_USI04>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric0 0x1024>; + status = "disabled"; + + hsi2c_8: i2c@10500000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10500000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_DOUT_PERIC0_USI04>, + <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c8_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_6: serial@10500000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x10500000 0xc0>; + clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric0 CLK_DOUT_PERIC0_USI04>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart6_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi4_i2c: usi@105100c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x105100c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric0 CLK_DOUT_PERIC0_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_peric0 0x1024>; + status = "disabled"; + + hsi2c_9: i2c@10510000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10510000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_DOUT_PERIC0_I2C>, + <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c9_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; }; cmu_peric1: clock-controller@10700000 { compatible = "samsung,exynos2200-cmu-peric1"; - reg = <0x0 0x10700000 0x0 0x8000>; + reg = <0x10700000 0x8000>; #clock-cells = <1>; clocks = <&xtcxo>, @@ -328,23 +400,304 @@ syscon_peric1: syscon@10720000 { compatible = "samsung,exynos2200-peric1-sysreg", "syscon"; - reg = <0x0 0x10720000 0x0 0x2000>; + reg = <0x10720000 0x10000>; }; pinctrl_peric1: pinctrl@10730000 { compatible = "samsung,exynos2200-pinctrl"; - reg = <0x0 0x10730000 0x0 0x1000>; + reg = <0x10730000 0x1000>; + }; + + usi7: usi@109000c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x109000c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI07>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric1 0x2030>; + status = "disabled"; + + hsi2c_14: i2c@10900000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10900000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_DOUT_PERIC1_USI07>, + <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c14_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_9: serial@10900000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x10900000 0xc0>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI07>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart9_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi7_i2c: usi@109100c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x109100c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI07_SPI_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_peric1 0x2034>; + status = "disabled"; + + hsi2c_15: i2c@10910000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10910000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_DOUT_PERIC1_USI07_SPI_I2C>, + <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c15_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi8: usi@109200c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x109200c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI08>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric1 0x2038>; + status = "disabled"; + + hsi2c_16: i2c@10920000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10920000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_DOUT_PERIC1_USI08>, + <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c16_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_10: serial@10920000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x10920000 0xc0>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI08>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart10_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi8_i2c: usi@109300c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x109300c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI08_SPI_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_peric1 0x203c>; + status = "disabled"; + + hsi2c_17: i2c@10930000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10930000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_DOUT_PERIC1_USI08_SPI_I2C>, + <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c17_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi9: usi@109400c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x109400c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI09>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric1 0x2040>; + status = "disabled"; + + hsi2c_18: i2c@10940000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10940000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_DOUT_PERIC1_USI09>, + <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c18_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_11: serial@10940000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x10940000 0xc0>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI09>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart11_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi9_i2c: usi@109500c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x109500c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_peric1 0x2044>; + status = "disabled"; + + hsi2c_19: i2c@10950000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10950000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_DOUT_PERIC1_I2C>, + <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c19_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi10: usi@109600c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x109600c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI10>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric1 0x2048>; + status = "disabled"; + + hsi2c_20: i2c@10960000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10960000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_DOUT_PERIC1_USI10>, + <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c20_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_12: serial@10960000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x10960000 0xc0>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI10>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart12_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi10_i2c: usi@109700c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x109700c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_peric1 0x204c>; + status = "disabled"; + + hsi2c_21: i2c@10970000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10970000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_DOUT_PERIC1_I2C>, + <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c21_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; cmu_hsi0: clock-controller@10a00000 { compatible = "samsung,exynos2200-cmu-hsi0"; - reg = <0x0 0x10a00000 0x0 0x8000>; + reg = <0x10a00000 0x8000>; #clock-cells = <1>; }; usb32drd: phy@10aa0000 { compatible = "samsung,exynos2200-usb32drd-phy"; - reg = <0x0 0x10aa0000 0x0 0x10000>; + reg = <0x10aa0000 0x10000>; clocks = <&cmu_hsi0 CLK_MOUT_HSI0_NOC>; clock-names = "phy"; @@ -360,7 +713,7 @@ usb_hsphy: phy@10ab0000 { compatible = "samsung,exynos2200-eusb2-phy"; - reg = <0x0 0x10ab0000 0x0 0x10000>; + reg = <0x10ab0000 0x10000>; clocks = <&cmu_hsi0 CLK_MOUT_HSI0_USB32DRD>, <&cmu_hsi0 CLK_MOUT_HSI0_NOC>, @@ -374,7 +727,7 @@ usb: usb@10b00000 { compatible = "samsung,exynos2200-dwusb3"; - ranges = <0x0 0x0 0x10b00000 0x10000>; + ranges = <0x0 0x10b00000 0x10000>; clocks = <&cmu_hsi0 CLK_MOUT_HSI0_NOC>; clock-names = "link_aclk"; @@ -406,7 +759,7 @@ cmu_ufs: clock-controller@11000000 { compatible = "samsung,exynos2200-cmu-ufs"; - reg = <0x0 0x11000000 0x0 0x8000>; + reg = <0x11000000 0x8000>; #clock-cells = <1>; clocks = <&xtcxo>, @@ -418,27 +771,27 @@ syscon_ufs: syscon@11020000 { compatible = "samsung,exynos2200-ufs-sysreg", "syscon"; - reg = <0x0 0x11020000 0x0 0x2000>; + reg = <0x11020000 0x10000>; }; pinctrl_ufs: pinctrl@11040000 { compatible = "samsung,exynos2200-pinctrl"; - reg = <0x0 0x11040000 0x0 0x1000>; + reg = <0x11040000 0x1000>; }; pinctrl_hsi1ufs: pinctrl@11060000 { compatible = "samsung,exynos2200-pinctrl"; - reg = <0x0 0x11060000 0x0 0x1000>; + reg = <0x11060000 0x1000>; }; pinctrl_hsi1: pinctrl@11240000 { compatible = "samsung,exynos2200-pinctrl"; - reg = <0x0 0x11240000 0x0 0x1000>; + reg = <0x11240000 0x1000>; }; cmu_peric2: clock-controller@11c00000 { compatible = "samsung,exynos2200-cmu-peric2"; - reg = <0x0 0x11c00000 0x0 0x8000>; + reg = <0x11c00000 0x8000>; #clock-cells = <1>; clocks = <&xtcxo>, @@ -450,17 +803,507 @@ syscon_peric2: syscon@11c20000 { compatible = "samsung,exynos2200-peric2-sysreg", "syscon"; - reg = <0x0 0x11c20000 0x0 0x4000>; + reg = <0x11c20000 0x10000>; }; pinctrl_peric2: pinctrl@11c30000 { compatible = "samsung,exynos2200-pinctrl"; - reg = <0x0 0x11c30000 0x0 0x1000>; + reg = <0x11c30000 0x1000>; + }; + + usi0: usi@11d000c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11d000c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI00>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric2 0x2000>; + status = "disabled"; + + hsi2c_0: i2c@11d00000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11d00000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_USI00>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c0_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_2: serial@11d00000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x11d00000 0xc0>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI00>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart2_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi0_i2c: usi@11d100c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11d100c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI00_SPI_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_peric2 0x2004>; + status = "disabled"; + + hsi2c_1: i2c@11d10000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11d10000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_USI00_SPI_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c1_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi1: usi@11d200c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11d200c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI01>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric2 0x2008>; + status = "disabled"; + + hsi2c_2: i2c@11d20000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11d20000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_USI01>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c2_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_3: serial@11d20000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x11d20000 0xc0>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI01>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart3_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi1_i2c: usi@11d300c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11d300c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI01_SPI_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_peric2 0x200c>; + status = "disabled"; + + hsi2c_3: i2c@11d30000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11d30000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_USI01_SPI_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 705 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c3_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi2: usi@11d400c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11d400c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI02>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric2 0x2010>; + status = "disabled"; + + hsi2c_4: i2c@11d40000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11d40000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_USI02>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c4_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_4: serial@11d40000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x11d40000 0xc0>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI02>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart4_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + }; + + usi2_i2c: usi@11d500c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11d500c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_peric2 0x2014>; + status = "disabled"; + + hsi2c_5: i2c@11d50000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11d50000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c5_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi3: usi@11d600c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11d600c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI03>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric2 0x2018>; + status = "disabled"; + + hsi2c_6: i2c@11d60000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11d60000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_USI03>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c6_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_5: serial@11d60000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x11d60000 0xc0>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI03>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart5_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + }; + + usi3_i2c: usi@11d700c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11d700c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_peric2 0x201c>; + status = "disabled"; + + hsi2c_7: i2c@11d70000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11d70000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c7_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi5_i2c: usi@11d800c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11d800c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_peric2 0x102c>; + status = "disabled"; + + hsi2c_11: i2c@11d80000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11d80000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c11_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi6_i2c: usi@11d900c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11d900c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_peric2 0x1004>; + status = "disabled"; + + hsi2c_13: i2c@11d90000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11d90000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c13_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi11: usi@11da00c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11da00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI11>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric2 0x1058>; + status = "disabled"; + + hsi2c_22: i2c@11da0000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11da0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_USI11>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c22_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_13: serial@11da0000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x11da0000 0xc0>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI11>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart13_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi11_i2c: usi@11db00c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11db00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_peric2 0x105c>; + status = "disabled"; + + hsi2c_23: i2c@11db0000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11db0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c23_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi5: usi@11dd00c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11dd00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI05>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric2 0x117c>; + status = "disabled"; + + hsi2c_10: i2c@11dd0000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11dd0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_USI05>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c10_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_7: serial@11dd0000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x11dd0000 0xc0>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI05>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart7_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + }; + + usi6: usi@11de00c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11de00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI06>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric2 0x1180>; + status = "disabled"; + + hsi2c_12: i2c@11de0000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11de0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_USI06>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c12_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_8: serial@11de0000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x11de0000 0xc0>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI06>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart8_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; }; cmu_cmgp: clock-controller@14e00000 { compatible = "samsung,exynos2200-cmu-cmgp"; - reg = <0x0 0x14e00000 0x0 0x8000>; + reg = <0x14e00000 0x8000>; #clock-cells = <1>; clocks = <&xtcxo>, @@ -471,12 +1314,12 @@ syscon_cmgp: syscon@14e20000 { compatible = "samsung,exynos2200-cmgp-sysreg", "syscon"; - reg = <0x0 0x14e20000 0x0 0x2000>; + reg = <0x14e20000 0x10000>; }; pinctrl_cmgp: pinctrl@14e30000 { compatible = "samsung,exynos2200-pinctrl"; - reg = <0x0 0x14e30000 0x0 0x1000>; + reg = <0x14e30000 0x1000>; wakeup-interrupt-controller { compatible = "samsung,exynos2200-wakeup-eint", @@ -485,9 +1328,528 @@ }; }; + usi_cmgp0: usi@14f000c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14f000c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI0>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_cmgp 0x2000>; + status = "disabled"; + + hsi2c_24: i2c@14f00000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14f00000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_USI0>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c24_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_14: serial@14f00000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x14f00000 0xc0>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI0>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart14_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_cmgp0: usi@14f100c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14f100c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_SPI_I2C0>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_cmgp 0x2070>; + status = "disabled"; + + hsi2c_25: i2c@14f10000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14f10000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_SPI_I2C0>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c25_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi_cmgp1: usi@14f200c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14f200c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI1>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_cmgp 0x2010>; + status = "disabled"; + + hsi2c_26: i2c@14f20000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14f20000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_USI1>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c26_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_15: serial@14f20000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x14f20000 0xc0>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI1>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart15_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_cmgp1: usi@14f300c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14f300c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_SPI_I2C1>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_cmgp 0x2074>; + status = "disabled"; + + hsi2c_27: i2c@14f30000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14f30000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_SPI_I2C1>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c27_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi_cmgp2: usi@14f400c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14f400c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI2>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_cmgp 0x2020>; + status = "disabled"; + + hsi2c_28: i2c@14f40000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14f40000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_USI2>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c28_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_16: serial@14f40000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x14f40000 0xc0>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI2>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart16_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_cmgp2: usi@14f500c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14f500c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_cmgp 0x2024>; + status = "disabled"; + + hsi2c_29: i2c@14f50000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14f50000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_I2C>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c29_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi_cmgp3: usi@14f600c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14f600c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI3>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_cmgp 0x2030>; + status = "disabled"; + + hsi2c_30: i2c@14f60000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14f60000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_USI3>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c30_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_17: serial@14f60000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x14f60000 0xc0>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI3>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart17_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_cmgp3: usi@14f700c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14f700c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_cmgp 0x2034>; + status = "disabled"; + + hsi2c_31: i2c@14f70000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14f70000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_I2C>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c31_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi_cmgp4: usi@14f800c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14f800c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI4>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_cmgp 0x2040>; + status = "disabled"; + + hsi2c_32: i2c@14f80000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14f80000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_USI4>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c32_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_18: serial@14f80000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x14f80000 0xc0>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI4>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart18_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_cmgp4: usi@14f900c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14f900c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_cmgp 0x2044>; + status = "disabled"; + + hsi2c_33: i2c@14f90000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14f90000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_I2C>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c33_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi_cmgp5: usi@14fa00c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14fa00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI5>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_cmgp 0x2050>; + status = "disabled"; + + hsi2c_34: i2c@14fa0000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14fa0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_USI5>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c34_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_19: serial@14fa0000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x14fa0000 0xc0>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI5>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart19_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_cmgp5: usi@14fb00c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14fb00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_cmgp 0x2054>; + status = "disabled"; + + hsi2c_35: i2c@14fb0000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14fb0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_I2C>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c35_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi_cmgp6: usi@14fc00c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14fc00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI6>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_cmgp 0x2060>; + status = "disabled"; + + hsi2c_36: i2c@14fc0000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14fc0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_USI6>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c36_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_20: serial@14fc0000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x14fc0000 0xc0>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI6>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart20_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_cmgp6: usi@14fd00c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14fd00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_cmgp 0x2064>; + status = "disabled"; + + hsi2c_37: i2c@14fd0000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14fd0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_I2C>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c37_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi_i2c_cmgp7: usi@14fe00c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14fe00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_cmgp 0x2080>; + status = "disabled"; + + hsi2c_38: i2c@14fe0000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14fe0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_I2C>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c38_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + cmu_vts: clock-controller@15300000 { compatible = "samsung,exynos2200-cmu-vts"; - reg = <0x0 0x15300000 0x0 0x8000>; + reg = <0x15300000 0x8000>; #clock-cells = <1>; clocks = <&xtcxo>, @@ -497,12 +1859,12 @@ pinctrl_vts: pinctrl@15320000 { compatible = "samsung,exynos2200-pinctrl"; - reg = <0x0 0x15320000 0x0 0x1000>; + reg = <0x15320000 0x1000>; }; cmu_alive: clock-controller@15800000 { compatible = "samsung,exynos2200-cmu-alive"; - reg = <0x0 0x15800000 0x0 0x8000>; + reg = <0x15800000 0x8000>; #clock-cells = <1>; clocks = <&xtcxo>, @@ -512,7 +1874,7 @@ pinctrl_alive: pinctrl@15850000 { compatible = "samsung,exynos2200-pinctrl"; - reg = <0x0 0x15850000 0x0 0x1000>; + reg = <0x15850000 0x1000>; wakeup-interrupt-controller { compatible = "samsung,exynos2200-wakeup-eint", @@ -524,7 +1886,7 @@ pmu_system_controller: system-controller@15860000 { compatible = "samsung,exynos2200-pmu", "samsung,exynos7-pmu", "syscon"; - reg = <0x0 0x15860000 0x0 0x10000>; + reg = <0x15860000 0x10000>; reboot: syscon-reboot { compatible = "syscon-reboot"; @@ -536,7 +1898,7 @@ cmu_top: clock-controller@1a320000 { compatible = "samsung,exynos2200-cmu-top"; - reg = <0x0 0x1a320000 0x0 0x8000>; + reg = <0x1a320000 0x8000>; #clock-cells = <1>; clocks = <&xtcxo>; diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 0b9053b9b2b5..fa2029e280a5 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -937,6 +937,7 @@ gic: interrupt-controller@11001000 { compatible = "arm,gic-400"; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; reg = <0x11001000 0x1000>, diff --git a/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts b/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts index 7d70a32e75b2..ab076d326a49 100644 --- a/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts +++ b/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts @@ -21,6 +21,7 @@ compatible = "winlink,e850-96", "samsung,exynos850"; aliases { + ethernet0 = ðernet; mmc0 = &mmc_0; serial0 = &serial_0; }; @@ -241,10 +242,24 @@ }; &usbdrd_dwc3 { + #address-cells = <1>; + #size-cells = <0>; dr_mode = "otg"; usb-role-switch; role-switch-default-mode = "host"; + hub@1 { + compatible = "usb424,9514"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet: ethernet@1 { + compatible = "usb424,ec00"; + reg = <1>; + }; + }; + port { usb1_drd_sw: endpoint { remote-endpoint = <&usb_dr_connector>; diff --git a/arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi index 51e9c9c4b166..16903ce63a32 100644 --- a/arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi @@ -202,7 +202,7 @@ }; bt_en: bt-en-pins { - samsung,pins ="gpj1-7"; + samsung,pins = "gpj1-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; diff --git a/arch/arm64/boot/dts/exynos/exynos990-c1s.dts b/arch/arm64/boot/dts/exynos/exynos990-c1s.dts index 36a6f1377e92..9f0ad4f9673a 100644 --- a/arch/arm64/boot/dts/exynos/exynos990-c1s.dts +++ b/arch/arm64/boot/dts/exynos/exynos990-c1s.dts @@ -44,6 +44,12 @@ <0x8 0x80000000 0x1 0x7ec00000>; }; + /* TODO: Remove this once PMIC is implemented */ + reg_dummy: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "dummy_reg"; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -113,3 +119,13 @@ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; }; + +&usbdrd { + status = "okay"; + vdd10-supply = <®_dummy>; + vdd33-supply = <®_dummy>; +}; + +&usbdrd_phy { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/exynos/exynos990-r8s.dts b/arch/arm64/boot/dts/exynos/exynos990-r8s.dts index 6bae3c0ecc1c..55342db61979 100644 --- a/arch/arm64/boot/dts/exynos/exynos990-r8s.dts +++ b/arch/arm64/boot/dts/exynos/exynos990-r8s.dts @@ -44,6 +44,12 @@ <0x8 0x80000000 0x0 0xc0000000>; }; + /* TODO: Remove this once PMIC is implemented */ + reg_dummy: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "dummy_reg"; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -113,3 +119,13 @@ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; }; + +&usbdrd { + status = "okay"; + vdd10-supply = <®_dummy>; + vdd33-supply = <®_dummy>; +}; + +&usbdrd_phy { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/exynos/exynos990-x1s-common.dtsi b/arch/arm64/boot/dts/exynos/exynos990-x1s-common.dtsi index 55fa8e9e05db..7b97220cccb7 100644 --- a/arch/arm64/boot/dts/exynos/exynos990-x1s-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos990-x1s-common.dtsi @@ -27,6 +27,12 @@ }; }; + /* TODO: Remove this once PMIC is implemented */ + reg_dummy: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "dummy_reg"; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -96,3 +102,13 @@ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; }; + +&usbdrd { + status = "okay"; + vdd10-supply = <®_dummy>; + vdd33-supply = <®_dummy>; +}; + +&usbdrd_phy { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/exynos/exynos990.dtsi b/arch/arm64/boot/dts/exynos/exynos990.dtsi index dd7f99f51a75..7179109c49d0 100644 --- a/arch/arm64/boot/dts/exynos/exynos990.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos990.dtsi @@ -211,6 +211,30 @@ <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; }; + watchdog_cl0: watchdog@10050000 { + compatible = "samsung,exynos990-wdt"; + reg = <0x10050000 0x100>; + interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cmu_peris CLK_GOUT_PERIS_WDT_CLUSTER0_PCLK>, + <&oscclk>; + clock-names = "watchdog", + "watchdog_src"; + samsung,syscon-phandle = <&pmu_system_controller>; + samsung,cluster-index = <0>; + }; + + watchdog_cl2: watchdog@10060000 { + compatible = "samsung,exynos990-wdt"; + reg = <0x10060000 0x100>; + interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cmu_peris CLK_GOUT_PERIS_WDT_CLUSTER2_PCLK>, + <&oscclk>; + clock-names = "watchdog", + "watchdog_src"; + samsung,syscon-phandle = <&pmu_system_controller>; + samsung,cluster-index = <2>; + }; + gic: interrupt-controller@10101000 { compatible = "arm,gic-400"; reg = <0x10101000 0x1000>, @@ -225,12 +249,34 @@ #size-cells = <1>; }; + cmu_peric0: clock-controller@10400000 { + compatible = "samsung,exynos990-cmu-peric0"; + reg = <0x10400000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>, + <&cmu_top CLK_DOUT_CMU_PERIC0_IP>; + clock-names = "oscclk", "bus", "ip"; + }; + pinctrl_peric0: pinctrl@10430000 { compatible = "samsung,exynos990-pinctrl"; reg = <0x10430000 0x1000>; interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; }; + cmu_peric1: clock-controller@10700000 { + compatible = "samsung,exynos990-cmu-peric1"; + reg = <0x10700000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>, + <&cmu_top CLK_DOUT_CMU_PERIC1_IP>; + clock-names = "oscclk", "bus", "ip"; + }; + pinctrl_peric1: pinctrl@10730000 { compatible = "samsung,exynos990-pinctrl"; reg = <0x10730000 0x1000>; @@ -254,6 +300,37 @@ "dpgtc"; }; + usbdrd_phy: phy@10c00000 { + compatible = "samsung,exynos990-usbdrd-phy"; + reg = <0x10c00000 0x100>; + clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL>, + <&oscclk>; + clock-names = "phy", "ref"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <1>; + status = "disabled"; + }; + + usbdrd: usb@10e00000 { + compatible = "samsung,exynos990-dwusb3", + "samsung,exynos850-dwusb3"; + ranges = <0x0 0x10e00000 0x10000>; + clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY>, + <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_USB31DRD_REF_CLK_40>; + clock-names = "bus_early", "ref"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + usbdrd_dwc3: usb@0 { + compatible = "snps,dwc3"; + reg = <0x0 0x10000>; + interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usbdrd_phy 0>; + phy-names = "usb2-phy"; + }; + }; + pinctrl_hsi1: pinctrl@13040000 { compatible = "samsung,exynos990-pinctrl"; reg = <0x13040000 0x1000>; diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index c0f8c25861a9..31c99526470d 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -341,6 +341,7 @@ gic: interrupt-controller@10400000 { compatible = "arm,gic-v3"; + #address-cells = <0>; #interrupt-cells = <4>; interrupt-controller; reg = <0x10400000 0x10000>, /* GICD */ diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 23535ed47631..525ef180481d 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -5,6 +5,8 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-oxalis.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-tqmls1012al-mbls1012al.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-tqmls1012al-mbls1012al-emmc.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-kbox-a-230-ls.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var1.dtb @@ -194,6 +196,7 @@ imx8mp-aristainetos3-helios-lvds-dtbs += imx8mp-aristainetos3-helios.dtb imx8mp- dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-helios-lvds.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-proton2s.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-beacon-kit.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-cubox-m.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-data-modul-edm-sbc.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-model-a.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-som-a-bmb-08.dtb @@ -201,7 +204,12 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-drc02.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-picoitx.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-edm-g-wb.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-mate.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pro.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pulse.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-ripple.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-iota2-lumpy.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-bl-osm-s.dtb @@ -237,6 +245,7 @@ imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17-dtbs += imx8mp-tx8p-ml81-modu dtb-$(CONFIG_ARCH_MXC) += imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-ultra-mach-sbc.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw71xx-2x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw72xx-2x.dtb @@ -332,7 +341,10 @@ dtb-${CONFIG_ARCH_MXC} += imx8qxp-mek-ov5640-csi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqps-mb-smarc-2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8ulp-9x9-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb imx93-9x9-qsb-i3c-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-i3c.dtbo @@ -371,8 +383,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-pcie0-ep.dtb imx95-19x19-evk-pcie1-ep. dtb-$(CONFIG_ARCH_MXC) += imx95-libra-rdk-fpsc.dtb imx8mm-kontron-dl-dtbs := imx8mm-kontron-bl.dtb imx8mm-kontron-dl.dtbo +imx8mm-kontron-bl-lte-dtbs := imx8mm-kontron-bl.dtb imx8mm-kontron-bl-lte.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-dl.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-bl-lte.dtb imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-imx219.dtbo imx8mm-venice-gw72xx-0x-rpidsi-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rpidsi.dtbo diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al-mbls1012al-emmc.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al-mbls1012al-emmc.dts new file mode 100644 index 000000000000..07026b067320 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al-mbls1012al-emmc.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2018-2025 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Matthias Schiffer + * Author: Max Merchel + */ + +#include "fsl-ls1012a-tqmls1012al-mbls1012al.dts" + +&esdhc0 { + vqmmc-supply = <®_1v8>; + /delete-property/ no-mmc; + /delete-property/ sd-uhs-sdr12; + /delete-property/ sd-uhs-sdr25; + /delete-property/ sd-uhs-sdr50; + /delete-property/ sd-uhs-sdr104; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + no-sd; + voltage-ranges = <1800 1800>; + non-removable; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al-mbls1012al.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al-mbls1012al.dts new file mode 100644 index 000000000000..e46cc1a07f0c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al-mbls1012al.dts @@ -0,0 +1,366 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2018-2025 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Matthias Schiffer + * Author: Max Merchel + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/net/ti-dp83867.h> +#include "fsl-ls1012a-tqmls1012al.dtsi" + +/ { + model = "TQ-Systems TQMLS1012AL on MBLS1012AL"; + compatible = "tq,ls1012a-tqmls1012al-mbls1012al", "tq,ls1012a-tqmls1012al", "fsl,ls1012a"; + chassis-type = "embedded"; + + aliases { + /* use MAC from U-Boot environment */ + /* TODO: PFE */ + ethernet2 = &swport0; + ethernet3 = &swport1; + ethernet4 = &swport2; + ethernet5 = &swport3; + serial0 = &duart0; + spi0 = &qspi; + }; + + chosen { + stdout-path = &duart0; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + switch-1 { + label = "S2"; + linux,code = <BTN_0>; + gpios = <&gpio_exp_3p3v 13 GPIO_ACTIVE_LOW>; + }; + + switch-2 { + label = "X15"; + linux,code = <BTN_1>; + gpios = <&gpio_exp_1p8v 5 GPIO_ACTIVE_LOW>; + }; + + switch-3 { + label = "X16"; + linux,code = <BTN_2>; + gpios = <&gpio_exp_1p8v 4 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-0 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio_exp_3p3v 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + gpios = <&gpio_exp_3p3v 15 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + /* 64 MiB */ + size = <0 0x04000000>; + /* 512 - 128 MiB, our minimum RAM config will be 512 MiB */ + alloc-ranges = <0 0x80000000 0 0x98000000>; + linux,cma-default; + }; + }; + + reg_1v5: regulator-1v5 { + compatible = "regulator-fixed"; + regulator-name = "V_1V5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + reg_1p5v_pcie: regulator-1p5v-pcie { + compatible = "regulator-fixed"; + regulator-name = "V_1V5_PCIE"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio_exp_1p8v 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_1v5>; + }; + + reg_1p5v_wlan: regulator-1p5v-wlan { + compatible = "regulator-fixed"; + regulator-name = "V_1V5_WLAN"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio_exp_1p8v 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_1v5>; + }; + + reg_1v8: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "V_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3v3: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_3v3_pcie: regulator-3v3-pcie { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_PCIE"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio_exp_3p3v 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_3v3>; + }; + + reg_3v3_wlan: regulator-3v3-wlan { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_WLAN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio_exp_3p3v 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_3v3>; + }; +}; + +&duart0 { + status = "okay"; +}; + +&esdhc0 { + vmmc-supply = <®_3v3>; + no-mmc; + no-sdio; + disable-wp; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&i2c0 { + gpio_exp_3p3v: gpio@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_3v3>; + interrupt-parent = <&gpio0>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-line-names = "", "", "GPIO_3V3_3", "", + "", "", "", "", + "", "GPIO_3V3_1", "GPIO_3V3_2", "", + "", "", "", ""; + + wlan-disable-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "WLAN_DISABLE#"; + }; + + pcie-rst-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PCIE_RST#"; + }; + + wlan-rst-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "WLAN_RST#"; + }; + + pcie-dis-hog { + gpio-hog; + gpios = <11 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PCIE_DIS#"; + }; + + pcie-wake-hog { + gpio-hog; + gpios = <12 GPIO_ACTIVE_HIGH>; + input; + line-name = "PCIE_WAKE#"; + }; + }; + + lm75_48: temperature-sensor@48 { + compatible = "national,lm75a"; + reg = <0x48>; + vs-supply = <®_3v3>; + }; + + switch@5f { + compatible = "microchip,ksz9897"; + reg = <0x5f>; + reset-gpios = <&gpio_exp_3p3v 7 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + swport0: port@0 { + reg = <0>; + label = "swp0"; + phy-mode = "internal"; + }; + + swport1: port@1 { + reg = <1>; + label = "swp1"; + phy-mode = "internal"; + }; + + swport2: port@2 { + reg = <2>; + label = "swp2"; + phy-mode = "internal"; + }; + + swport3: port@3 { + reg = <3>; + label = "swp3"; + phy-mode = "internal"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + /* TODO: PFE */ + phy-mode = "rgmii-id"; + rx-internal-delay-ps = <1500>; + tx-internal-delay-ps = <1500>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + + gpio_exp_1p8v: gpio@70 { + compatible = "nxp,pca9538"; + reg = <0x70>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_1v8>; + interrupt-parent = <&gpio0>; + interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-line-names = "PCIE_CLK_PD#", "PMIC_INT#", "ETH_SW_INT#", "", + "", "", "", "", + "", "GPIO_3V3_1", "GPIO_3V3_2", "", + "", "", "", ""; + + /* do not change PCIE_CLK_PD */ + pcie-clk-pd-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PCIE_CLK_PD#"; + }; + + pmic-int-hog { + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + input; + line-name = "PMIC_INT#"; + }; + + eth-sw-int-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + input; + line-name = "ETH_SW_INT#"; + }; + + eth-link-pwrdwn-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; + input; + line-name = "ETH_LINK_PWRDWN#"; + }; + }; +}; + +&pcie1 { + status = "okay"; +}; + +/* TODO: PFE */ + +&sata { + status = "okay"; +}; + +&usb0 { + #address-cells = <1>; + #size-cells = <0>; + + hub_2_0: hub@1 { + compatible = "usb451,8142"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpio_exp_3p3v 6 GPIO_ACTIVE_LOW>; + vdd-supply = <®_vcc_3v3>; + }; + + hub_3_0: hub@2 { + compatible = "usb451,8140"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpio_exp_3p3v 6 GPIO_ACTIVE_LOW>; + vdd-supply = <®_vcc_3v3>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al.dtsi new file mode 100644 index 000000000000..7c5a3dee91b9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al.dtsi @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2018-2025 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Matthias Schiffer + * Author: Max Merchel + */ + +#include "fsl-ls1012a.dtsi" + +/ { + compatible = "tq,ls1012a-tqmls1012al", "fsl,ls1012a"; + + memory@80000000 { + device_type = "memory"; + /* our minimum RAM config will be 512 MiB */ + reg = <0x00000000 0x80000000 0 0x20000000>; + }; + + reg_vcc_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_vcc_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&i2c0 { + status = "okay"; + + jc42_19: temperature-sensor@19 { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x19>; + }; + + m24c64_50: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + vcc-supply = <®_vcc_3v3>; + }; + + m24c02_51: eeprom@51 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + read-only; + vcc-supply = <®_vcc_3v3>; + }; + + rtc1: rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&qspi { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <39000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + vcc-supply = <®_vcc_1v8>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index dd479889658d..fc3e138077b8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -87,6 +87,7 @@ gic: interrupt-controller@1400000 { compatible = "arm,gic-400"; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x1401000 0 0x1000>, /* GICD */ diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 26bea88cb967..73315c517039 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -289,6 +289,7 @@ gic: interrupt-controller@1400000 { compatible = "arm,gic-400"; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x1401000 0 0x1000>, /* GICD */ diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 4a22fde38bea..770d91ef0310 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -260,6 +260,7 @@ gic: interrupt-controller@1400000 { compatible = "arm,gic-400"; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x1410000 0 0x10000>, /* GICD */ diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi index e4b727070814..eec2cd6c6d32 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi @@ -41,6 +41,7 @@ rgmii_phy1: ethernet-phy@1 { reg = <1>; qca,smarteee-tw-us-1g = <24>; + interrupts-extended = <&gpio2 4 IRQ_TYPE_EDGE_FALLING>; }; }; @@ -156,6 +157,7 @@ rtc@51 { compatible = "nxp,pcf2129"; reg = <0x51>; + interrupts-extended = <&gpio2 8 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi index a7dcbecc1f41..af6258b2fe82 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi @@ -96,6 +96,14 @@ status = "okay"; }; +&pcie3 { + status = "okay"; +}; + +&pcie5 { + status = "okay"; +}; + &pcs_mdio7 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi index 6f27a9cc2494..86d018f470c1 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi @@ -256,7 +256,7 @@ }; &asrc0 { - fsl,asrc-rate = <48000>; + fsl,asrc-rate = <48000>; }; &adc0 { diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi index 9b8b1380c4c2..469de8b536b5 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi @@ -68,10 +68,10 @@ hsio_subsys: bus@5f000000 { clock-names = "dbi", "mstr", "slv"; bus-range = <0x00 0xff>; device_type = "pci"; - interrupt-map = <0 0 0 1 &gic 0 105 4>, - <0 0 0 2 &gic 0 106 4>, - <0 0 0 3 &gic 0 107 4>, - <0 0 0 4 &gic 0 108 4>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; interrupt-map-mask = <0 0 0 0x7>; num-lanes = <1>; num-viewport = <4>; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index b6d64d3906ea..25a77cac6f0b 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -652,7 +652,7 @@ status = "okay"; }; -&pcie0_ep{ +&pcie0_ep { phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; phy-names = "pcie-phy"; pinctrl-0 = <&pinctrl_pcieb>; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi index 9b114bed084b..a66ba6d0a8c0 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi @@ -5,6 +5,8 @@ /delete-node/ &enet1_lpcg; /delete-node/ &fec2; +/delete-node/ &usbotg3; +/delete-node/ &usb3_phy; / { conn_enet0_root_clk: clock-conn-enet0-root { diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi index bbc6abb0fdf2..ec466e4d7df5 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi @@ -42,10 +42,10 @@ #interrupt-cells = <1>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; - interrupt-map = <0 0 0 1 &gic 0 47 4>, - <0 0 0 2 &gic 0 48 4>, - <0 0 0 3 &gic 0 49 4>, - <0 0 0 4 &gic 0 50 4>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; interrupt-map-mask = <0 0 0 0x7>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi index a71d8b32c192..8d60827822ed 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi @@ -92,6 +92,7 @@ compatible = "arm,gic-v3"; reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts b/arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts index 90e638b8e92a..87fe3ebedb8d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts @@ -333,7 +333,7 @@ >; }; - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp{ + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index 622caaa78eaf..ff7ca2075230 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -147,6 +147,7 @@ simple-audio-card,format = "i2s"; simple-audio-card,frame-master = <&cpudai>; simple-audio-card,bitclock-master = <&cpudai>; + simple-audio-card,mclk-fs = <256>; simple-audio-card,widgets = "Line", "Left Line Out Jack", "Line", "Right Line Out Jack"; @@ -158,11 +159,11 @@ sound-dai = <&sai3>; dai-tdm-slot-num = <2>; dai-tdm-slot-width = <32>; + system-clock-direction-out; }; simple-audio-card,codec { sound-dai = <&wm8524>; - clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; }; }; @@ -570,9 +571,17 @@ &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MM_CLK_SAI3>; - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; + assigned-clocks = <&clk IMX8MM_AUDIO_PLL1>, + <&clk IMX8MM_AUDIO_PLL2>, + <&clk IMX8MM_CLK_SAI3>; + assigned-clock-parents = <0>, <0>, <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <393216000>, <361267200>, <24576000>; + fsl,sai-mclk-direction-output; + clocks = <&clk IMX8MM_CLK_SAI3_IPG>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI3_ROOT>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-lte.dtso b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-lte.dtso new file mode 100644 index 000000000000..324004b0eca3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-lte.dtso @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2025 Kontron Electronics GmbH + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/leds/common.h> +#include "imx8mm-pinfunc.h" + +&{/} { + compatible = "kontron,imx8mm-bl", "kontron,imx8mm-sl", "fsl,imx8mm"; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + key-user { + label = "user"; + linux,code = <BTN_0>; + gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led_lte>; + + lte-led1-b { + label = "lte-led1-blue"; + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; + }; + + lte-led1-g { + label = "lte-led1-green"; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; + }; + + lte-led1-r { + label = "lte-led1-red"; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; + }; + + lte-led2-b { + label = "lte-led2-blue"; + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; + }; + + lte-led2-g { + label = "lte-led2-green"; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; + }; + + lte-led2-r { + label = "lte-led2-red"; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&ecspi3 { + status = "disabled"; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + tpm@2e { + compatible = "infineon,slb9673", "tcg,tpm-tis-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm>; + reg = <0x2e>; + interrupt-parent = <&gpio3>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&gpio3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio3>; + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "VDD_IO_REF", "TPM_PIRQ#", + "TPM_RESET# ", "", "", "", + "", "LTE_LED1_B", "LTE_LED1_G", "", + ""; + + vdd-io-ref-hog { + gpio-hog; + gpios = <10 GPIO_ACTIVE_HIGH>; + line-name = "VDD_IO_REF"; + output-high; + }; + + tpm-reset-hog { + gpio-hog; + gpios = <12 GPIO_ACTIVE_LOW>; + line-name = "TPM_RESET#"; + output-low; + }; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio4>; + gpio-line-names = "", "", "LTE_RESET", "", + "", "", "", "", + "", "", "", "LTE_PWRKEY", + "", "", "", "", + "", "", "", "", + "LTE_PWR_EN"; +}; + +&gpio5 { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "LTE_LED2_G", "LTE_LED1_R", + "LTE_LED2_R", "LTE_LED2_B"; +}; + +&iomuxc { + pinctrl_gpio3: gpio3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* VDD_IO_REF */ + >; + }; + + pinctrl_gpio4: gpio4grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x19 /* LTE_RESET */ + MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x19 /* LTE_PWRKEY */ + MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x19 /* LTE_PWR_EN */ + >; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x19 /* Pushbutton */ + >; + }; + + pinctrl_gpio_led_lte: gpioledltegrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19 /* LTE_LED1_B */ + MX8MM_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* LTE_LED1_G */ + MX8MM_IOMUXC_UART1_TXD_GPIO5_IO23 0x19 /* LTE_LED1_R */ + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19 /* LTE_LED2_B */ + MX8MM_IOMUXC_UART1_RXD_GPIO5_IO22 0x19 /* LTE_LED2_G */ + MX8MM_IOMUXC_UART2_RXD_GPIO5_IO24 0x19 /* LTE_LED2_R */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000083 /* I2C_A_SCL */ + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000083 /* I2C_A_SDA */ + >; + }; + + pinctrl_tpm: tpmgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* TPM_PIRQ# */ + MX8MM_IOMUXC_NAND_DATA06_GPIO3_IO12 0x39 /* TPM_RESET# */ + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts index 33f8d7d1970e..3a166cf0afcb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts @@ -48,14 +48,6 @@ pwms = <&pwm2 0 5000 0>; }; - reg_rst_eth2: regulator-rst-eth2 { - compatible = "regulator-fixed"; - gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - regulator-name = "rst-usb-eth2"; - }; - reg_vdd_5v: regulator-5v { compatible = "regulator-fixed"; regulator-always-on; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts index d16490d87687..e756fe5db56b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts @@ -268,8 +268,16 @@ &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; + /* + * During bootup the CTS needs to stay LOW, which is only possible if this + * pin is controlled by a GPIO. The UART IP always sets CTS to HIGH if not + * running. So using 'uart-has-rtscts' is not a good choice here! There are + * workarounds for this, but they introduce unnecessary complexity and are + * therefore avoided here. For more information about this see: + * https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit?id=79d0224f6bf296d04cd843cfc49921b19c97bb09 + */ + rts-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; linux,rs485-enabled-at-boot-time; - uart-has-rtscts; status = "okay"; }; @@ -439,7 +447,7 @@ MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x0 MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x0 MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x0 - MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x0 + MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-dl.dtso b/arch/arm64/boot/dts/freescale/imx8mm-kontron-dl.dtso index 1db27731b581..57d0739fcce3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-dl.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-dl.dtso @@ -107,7 +107,7 @@ #size-cells = <0>; status = "okay"; - touchscreen@5d { + gt911: touchscreen@5d { compatible = "goodix,gt928"; reg = <0x5d>; pinctrl-names = "default"; @@ -117,6 +117,17 @@ reset-gpios = <&gpio3 23 0>; irq-gpios = <&gpio3 22 0>; }; + + st1633: touchscreen@55 { + compatible = "sitronix,st1633"; + reg = <0x55>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + interrupts = <22 8>; + interrupt-parent = <&gpio3>; + gpios = <&gpio3 22 0>; + status = "disabled"; + }; }; &lvds { diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi index d45542965230..96987910609f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi @@ -30,29 +30,6 @@ stdout-path = &uart3; }; - reg_vdd_carrier: regulator-vdd-carrier { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_vdd_carrier>; - gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - regulator-name = "VDD_CARRIER"; - - regulator-state-standby { - regulator-on-in-suspend; - }; - - regulator-state-mem { - regulator-off-in-suspend; - }; - - regulator-state-disk { - regulator-off-in-suspend; - }; - }; - reg_usb1_vbus: regulator-usb1-vbus { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -61,7 +38,7 @@ gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - regulator-name = "VBUS_USB1"; + regulator-name = "VBUS_USB_A"; }; reg_usb2_vbus: regulator-usb2-vbus { @@ -72,7 +49,7 @@ gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - regulator-name = "VBUS_USB2"; + regulator-name = "VBUS_USB_B"; }; reg_usdhc2_vcc: regulator-usdhc2-vcc { @@ -96,6 +73,29 @@ regulator-max-microvolt = <3300000>; regulator-name = "VCC_SDIO_B"; }; + + reg_vdd_carrier: regulator-vdd-carrier { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_vdd_carrier>; + gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + regulator-name = "VDD_CARRIER"; + + regulator-state-standby { + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + + regulator-state-disk { + regulator-off-in-suspend; + }; + }; }; &A53_0 { diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso index e5ca5a664b61..79e4c3710ac3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso @@ -20,7 +20,7 @@ pwms = <&pwm4 0 50000 0>; power-supply = <®_vdd_3v3_s>; enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - brightness-levels= <0 4 8 16 32 64 128 255>; + brightness-levels = <0 4 8 16 32 64 128 255>; }; panel { diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi index 672baba4c8d0..921a7f58fd41 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi @@ -340,10 +340,10 @@ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16 - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16 + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x12 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x12 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x12 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x12 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x10 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index ded89b046970..fc3cd639310e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1467,6 +1467,7 @@ compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, /* GIC Dist */ <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */ + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index 33d73f3dc187..145355ff91b4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -387,6 +387,11 @@ assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; assigned-clock-rates = <24576000>; fsl,sai-mclk-direction-output; + clocks = <&clk IMX8MN_CLK_SAI3_IPG>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI3_ROOT>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_AUDIO_PLL1_OUT>, + <&clk IMX8MN_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-proton2s.dts b/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-proton2s.dts index 2a736dbe96b4..58e36de7a2cd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-proton2s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-proton2s.dts @@ -36,7 +36,7 @@ max-speed = <100>; }; -&ecspi1{ +&ecspi1 { pinctrl-0 = <&pinctrl_ecspi1>; cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi index 231e480acfd4..f654d866e58c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi @@ -167,7 +167,7 @@ <&clk IMX8MP_VIDEO_PLL1>; }; -&ecspi1{ +&ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs2>; cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW &gpio1 6 GPIO_ACTIVE_LOW>; @@ -565,7 +565,7 @@ status = "disabled"; }; -&pcie{ +&pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; reset-gpio = <&gpio4 20 GPIO_ACTIVE_LOW>; @@ -574,7 +574,7 @@ status = "okay"; }; -&pcie_phy{ +&pcie_phy { fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; clocks = <&pcie0_refclk>; clock-names = "ref"; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts b/arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts new file mode 100644 index 000000000000..8290f187b79f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer <josua@solid-run.com> + */ + +/dts-v1/; + +#include <dt-bindings/leds/common.h> + +#include "imx8mp-sr-som.dtsi" + +/ { + model = "SolidRun i.MX8MP CuBox-M"; + compatible = "solidrun,imx8mp-cubox-m", + "solidrun,imx8mp-sr-som", "fsl,imx8mp"; + + aliases { + ethernet0 = &eqos; + /delete-property/ ethernet1; + rtc0 = &carrier_rtc; + rtc1 = &snvs_rtc; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_pins>; + linux,autosuspend-period = <125>; + wakeup-source; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + status { + label = "status"; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + function = LED_FUNCTION_HEARTBEAT; + }; + }; + + sound-hdmi { + compatible = "fsl,imx-audio-hdmi"; + model = "audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + }; + + vbus: regulator-vbus { + compatible = "regulator-fixed"; + regulator-name = "vbus"; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&vbus_pins>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vmmc: regulator-mmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&vmmc_pins>; + regulator-name = "vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + startup-delay-us = <250>; + }; +}; + +&aud2htx { + status = "okay"; +}; + +&fec { + /* this board does not use second phy / ethernet on SoM */ + status = "disabled"; +}; + +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + status = "okay"; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + +&i2c3 { + carrier_rtc: rtc@32 { + compatible = "epson,rx8130"; + reg = <0x32>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins>; + + hdmi_pins: pinctrl-hdmi-grp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x154 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x154 + >; + }; + + ir_pins: pinctrl-ir-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x4f + >; + }; + + led_pins: pinctrl-led-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x0 + >; + }; + + usdhc2_pins: pinctrl-usdhc2-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140 + MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140 + >; + }; + + usdhc2_100mhz_pins: pinctrl-usdhc2-100mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140 + MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140 + >; + }; + + usdhc2_200mhz_pins: pinctrl-usdhc2-200mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140 + MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140 + >; + }; + + vbus_pins: pinctrl-vbus-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x100 + >; + }; + + vmmc_pins: pinctrl-vmmc-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x0 + >; + }; +}; + +&lcdif3 { + status = "okay"; +}; + +&usb3_phy0 { + fsl,phy-tx-preemp-amp-tune-microamp = <1200>; + vbus-supply = <&vbus>; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_phy1 { + fsl,phy-tx-preemp-amp-tune-microamp = <1200>; + vbus-supply = <&vbus>; + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "host"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&usdhc2_pins>; + pinctrl-1 = <&usdhc2_100mhz_pins>; + pinctrl-2 = <&usdhc2_200mhz_pins>; + vmmc-supply = <&vmmc>; + bus-width = <4>; + cap-power-off-card; + full-pwr-cycle; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts index d0fc5977258f..16078ff60ef0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts @@ -555,6 +555,7 @@ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <&ldo5>; bus-width = <4>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi index 7f754e0a5d69..68c2e0156a5c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi @@ -609,6 +609,7 @@ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <&ldo5>; bus-width = <4>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts b/arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts new file mode 100644 index 000000000000..138f21e257aa --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts @@ -0,0 +1,359 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2024 TechNexion Ltd. + * + * Author: Ray Chang <ray.chang@technexion.com> + */ + +/dts-v1/; + +#include <dt-bindings/phy/phy-imx8-pcie.h> +#include "imx8mp-edm-g.dtsi" + +/ { + compatible = "technexion,edm-g-imx8mp-wb", "technexion,edm-g-imx8mp", "fsl,imx8mp"; + model = "TechNexion EDM-G-IMX8MP SOM on WB-EDM-G"; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hs_ep: endpoint { + remote-endpoint = <&usb3_hs_ep>; + }; + }; + + port@1 { + reg = <1>; + + ss_ep: endpoint { + remote-endpoint = <&hd3ss3220_in_ep>; + }; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + label = "HDMI OUT"; + type = "a"; + + port { + hdmi_in: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led { + default-state = "on"; + gpios = <&expander2 1 GPIO_ACTIVE_HIGH>; + label = "gpio-led"; + }; + }; + + pcie0_refclk: clock-pcie-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + reg_pwr_3v3: regulator-pwr-3v3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "pwr-3v3"; + }; + + reg_pwr_5v: regulator-pwr-5v { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "pwr-5v"; + }; + + sound-hdmi { + compatible = "fsl,imx-audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + model = "audio-hdmi"; + }; + + sound-wm8960 { + compatible = "fsl,imx-audio-wm8960"; + audio-asrc = <&easrc>; + audio-codec = <&wm8960>; + audio-cpu = <&sai3>; + audio-routing = "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB"; + model = "wm8960-audio"; + }; +}; + +&aud2htx { + status = "okay"; +}; + +&easrc { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&flexcan1 { + status = "okay"; +}; + +&gpio1 { + gpio-line-names = + "", "", "", "", "", "", "DSI_RST", "", + "", "", "", "", "", "PCIE_CLKREQ_N", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; + pinctrl-0 = <&pinctrl_gpio1>; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "GPIO_P249", "GPIO_P251", + "", "GPIO_P255", "", "", "", "", "", "", + "DSI_BL_EN", "DSI_VDDEN", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; + pinctrl-0 = <&pinctrl_gpio4>; +}; + +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + pinctrl-0 = <&pinctrl_hdmi>; + pinctrl-names = "default"; + status = "okay"; + + ports { + port@1 { + hdmi_tx_out: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; + }; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + wm8960: audio-codec@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + AVDD-supply = <®_pwr_3v3>; + DBVDD-supply = <®_pwr_3v3>; + DCVDD-supply = <®_pwr_3v3>; + SPKVDD1-supply = <®_pwr_5v>; + SPKVDD2-supply = <®_pwr_5v>; + wlf,gpio-cfg = <1 2>; + wlf,hp-cfg = <2 2 3>; + wlf,shared-lrclk; + }; + + expander1: gpio@21 { + compatible = "nxp,pca9555"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = "EXPOSURE_TRIG_IN1", "FLASH_OUT1", + "INFO_TRIG_IN1", "CAM_SHUTTER1", "XVS1", + "PWR1_TIME0", "PWR1_TIME1", "PWR1_TIME2", + "EXPOSURE_TRIG_IN2", "FLASH_OUT2", + "INFO_TRIG_IN2", "CAM_SHUTTER2", "XVS2", + "PWR2_TIME0", "PWR2_TIME1", "PWR2_TIME2"; + }; + + expander2: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio4>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = "M2_DISABLE_N", "LED_EN", "", "", + "", "", "", "USB_OTG_OC", + "EXT_GPIO8", "EXT_GPIO9", "", "", + "", "CSI1_PDB", "CSI2_PDB", "PD_FAULT"; + pinctrl-0 = <&pinctrl_expander2_irq>; + pinctrl-names = "default"; + }; + + usb_typec: usb-typec@67 { + compatible = "ti,hd3ss3220"; + reg = <0x67>; + interrupt-parent = <&gpio4>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_hd3ss3220_irq>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hd3ss3220_in_ep: endpoint { + remote-endpoint = <&ss_ep>; + }; + }; + + port@1 { + reg = <1>; + + hd3ss3220_out_ep: endpoint { + remote-endpoint = <&usb3_role_switch>; + }; + }; + }; + }; +}; + +&i2c_0 { + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; +}; + +&lcdif3 { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&pcie_phy { + clocks = <&pcie0_refclk>; + clock-names = "ref"; + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb_dwc3_0 { + /* dual role is implemented but not a full featured OTG */ + adp-disable; + dr_mode = "otg"; + hnp-disable; + role-switch-default-mode = "peripheral"; + srp-disable; + usb-role-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb3_hs_ep: endpoint { + remote-endpoint = <&hs_ep>; + }; + }; + + port@1 { + reg = <1>; + + usb3_role_switch: endpoint { + remote-endpoint = <&hd3ss3220_out_ep>; + }; + }; + }; +}; + +&usb_dwc3_1 { + dr_mode = "host"; +}; + +&iomuxc { + pinctrl_expander2_irq: expander2-irqgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x140 /* GPIO_P247 */ + >; + }; + + pinctrl_gpio1: gpio1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x16 /* DSI_RST */ + >; + }; + + pinctrl_gpio4: gpio4grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD4__GPIO4_IO06 0x16 /* GPIO_P249 */ + MX8MP_IOMUXC_SAI1_RXD5__GPIO4_IO07 0x16 /* GPIO_P251 */ + MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 0x16 /* GPIO_P255 */ + MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x16 /* DSI_BL_EN */ + MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0x16 /* DSI_VDDEN */ + >; + }; + + pinctrl_hd3ss3220_irq: hd3ss3220-irqgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x41 /* GPIO_P253 */ + >; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c2 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-edm-g.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-edm-g.dtsi new file mode 100644 index 000000000000..3f1e0837f349 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-edm-g.dtsi @@ -0,0 +1,786 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2024 TechNexion Ltd. + * + * Author: Ray Chang <ray.chang@technexion.com> + */ + +#include "imx8mp.dtsi" + +/ { + chosen { + stdout-path = &uart2; + }; + + i2c_0: i2c { + compatible = "i2c-gpio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-0 = <&pinctrl_i2c_brd_conf>; + pinctrl-names = "default"; + scl-gpios = <&gpio4 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + eeprom: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + }; + + memory@40000000 { + reg = <0x0 0x40000000 0 0xc0000000>, + <0x1 0x00000000 0 0xc0000000>; + device_type = "memory"; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + off-on-delay-us = <12000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VSD_3V3"; + startup-delay-us = <100>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + rfkill { + compatible = "rfkill-gpio"; + name = "rfkill"; + pinctrl-0 = <&pinctrl_bt_ctrl>; + pinctrl-names = "default"; + radio-type = "bluetooth"; + shutdown-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + }; + + wl_reg_on: regulator-wl-reg-on { + compatible = "regulator-fixed"; + off-on-delay-us = <20000>; + pinctrl-0 = <&pinctrl_wifi_ctrl>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "WL_REG_ON"; + startup-delay-us = <100>; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&A53_0 { + cpu-supply = <®_arm>; +}; + +&A53_1 { + cpu-supply = <®_arm>; +}; + +&A53_2 { + cpu-supply = <®_arm>; +}; + +&A53_3 { + cpu-supply = <®_arm>; +}; + +&ecspi1 { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + num-cs = <1>; + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; + pinctrl-names = "default"; +}; + +&eqos { + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_eqos>; + pinctrl-names = "default"; + snps,force_thresh_dma_mode; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + reset-assert-us = <35000>; + reset-deassert-us = <75000>; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + realtek,clkout-disable; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <5>; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0>; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <1>; + snps,priority = <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <2>; + snps,priority = <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <3>; + snps,priority = <0x8>; + }; + + queue4 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <4>; + snps,priority = <0xf0>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <5>; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + }; + }; +}; + +&flexcan1 { + pinctrl-0 = <&pinctrl_flexcan1>; + pinctrl-names = "default"; +}; + +&flexcan2 { + pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-names = "default"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-names = "default"; + status = "okay"; + + pmic: pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + + regulators { + BUCK1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <720000>; + regulator-name = "BUCK1"; + regulator-ramp-delay = <3125>; + }; + + reg_arm: BUCK2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1025000>; + regulator-min-microvolt = <720000>; + regulator-name = "BUCK2"; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + BUCK4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3600000>; + regulator-min-microvolt = <3000000>; + regulator-name = "BUCK4"; + }; + + reg_buck5: BUCK5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1950000>; + regulator-min-microvolt = <1650000>; + regulator-name = "BUCK5"; + }; + + BUCK6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1155000>; + regulator-min-microvolt = <1045000>; + regulator-name = "BUCK6"; + }; + + LDO1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1950000>; + regulator-min-microvolt = <1650000>; + regulator-name = "LDO1"; + }; + + LDO3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1890000>; + regulator-min-microvolt = <1710000>; + regulator-name = "LDO3"; + }; + + LDO5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "LDO5"; + }; + }; + }; +}; + +&i2c2 { + /* I2C_B on EDMG */ + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-names = "default"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-names = "default"; +}; + +&i2c4 { + /* I2C_A on EDMG */ + clock-frequency = <100000>; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-names = "default"; +}; + +&i2c5 { + /* I2C_C on EDMG */ + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_i2c5>; + pinctrl-names = "default"; +}; + +&pcie { + pinctrl-0 = <&pinctrl_pcie>; + pinctrl-names = "default"; + reset-gpio = <&gpio1 1 GPIO_ACTIVE_LOW>; +}; + +&pwm1 { + pinctrl-0 = <&pinctrl_pwm1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm2 { + pinctrl-0 = <&pinctrl_pwm2>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm3 { + pinctrl-0 = <&pinctrl_pwm3>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm4 { + pinctrl-0 = <&pinctrl_pwm4>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sai2 { + /* AUD_B on EDMG */ + assigned-clocks = <&clk IMX8MP_CLK_SAI2>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + pinctrl-0 = <&pinctrl_sai2>; + pinctrl-names = "default"; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&sai3 { + /* AUD_A on EDMG */ + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + pinctrl-0 = <&pinctrl_sai3>; + pinctrl-names = "default"; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&uart1 { + /* BT */ + assigned-clocks = <&clk IMX8MP_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + /* UART_A on EDMG, console */ + pinctrl-0 = <&pinctrl_uart2>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart3 { + /* UART_C on EDMG */ + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + pinctrl-0 = <&pinctrl_uart3>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + /* UART_B on EDMG */ + assigned-clocks = <&clk IMX8MP_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + pinctrl-0 = <&pinctrl_uart4>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; +}; + +&usdhc1 { + /* WIFI SDIO */ + assigned-clocks = <&clk IMX8MP_CLK_USDHC1>; + assigned-clock-rates = <200000000>; + bus-width = <4>; + keep-power-in-suspend; + non-removable; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + vmmc-supply = <&wl_reg_on>; + status = "okay"; +}; + +&usdhc2 { + /* SD card on baseboard */ + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + /* eMMC on SOM */ + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + status = "okay"; +}; + +&wdog1 { + pinctrl-0 = <&pinctrl_wdog>; + pinctrl-names = "default"; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_hog>; + pinctrl-names = "default"; + + pinctrl_bt_ctrl: bt-ctrlgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x41 /* BT_REG_ON */ + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x41 /* BT_WAKE_HOST */ + >; + }; + + pinctrl_ecspi1_cs: ecspi1csgrp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40000 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82 + MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82 + MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x23 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x19 + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x19 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001a3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001a3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001a3 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001a3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_i2c5: i2c5grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001a3 + MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001a3 + >; + }; + + pinctrl_i2c_brd_conf: i2cbrdconfgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1c3 /* BRD_CONF_SCL, bitbang */ + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1c3 /* BRD_CONF_SDA, bitbang */ + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x41 /* PCIE CLKREQ */ + MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x41 /* PCIE WAKE */ + MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x41 /* PCIE RST */ + >; + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x116 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x116 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x116 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0xd6 + MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 + MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + MX8MP_IOMUXC_UART4_RXD__UART2_DCE_CTS 0x140 + MX8MP_IOMUXC_UART4_TXD__UART2_DCE_RTS 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x140 + MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS 0x140 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x140 + MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x140 + MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_wifi_ctrl: wifi-ctrlgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x41 /* WL_REG_ON */ + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x41 /* WL_WAKE_HOST */ + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index c0cc5611048e..3730792daf50 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -309,7 +309,7 @@ }; &easrc { - fsl,asrc-rate = <48000>; + fsl,asrc-rate = <48000>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-mate.dts b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-mate.dts new file mode 100644 index 000000000000..00614f5d58ea --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-mate.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer <josua@solid-run.com> + */ + +/dts-v1/; + +#include "imx8mp-sr-som.dtsi" +#include "imx8mp-hummingboard-pulse-common.dtsi" +#include "imx8mp-hummingboard-pulse-hdmi.dtsi" + +/ { + model = "SolidRun i.MX8MP HummingBoard Mate"; + compatible = "solidrun,imx8mp-hummingboard-mate", + "solidrun,imx8mp-sr-som", "fsl,imx8mp"; + + aliases { + ethernet0 = &eqos; + /delete-property/ ethernet1; + }; +}; + +&fec { + /* this board does not use second phy / ethernet on SoM */ + status = "disabled"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&mikro_pwm_pins>, <&mikro_int_pins>, <&mikro_rst_pins>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pro.dts b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pro.dts new file mode 100644 index 000000000000..36cd452f1583 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pro.dts @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer <josua@solid-run.com> + */ + +/dts-v1/; + +#include <dt-bindings/phy/phy-imx8-pcie.h> + +#include "imx8mp-sr-som.dtsi" +#include "imx8mp-hummingboard-pulse-codec.dtsi" +#include "imx8mp-hummingboard-pulse-common.dtsi" +#include "imx8mp-hummingboard-pulse-hdmi.dtsi" +#include "imx8mp-hummingboard-pulse-m2con.dtsi" +#include "imx8mp-hummingboard-pulse-mini-hdmi.dtsi" + +/ { + model = "SolidRun i.MX8MP HummingBoard Pro"; + compatible = "solidrun,imx8mp-hummingboard-pro", + "solidrun,imx8mp-sr-som", "fsl,imx8mp"; + + aliases { + ethernet0 = &eqos; + ethernet1 = &fec; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&mikro_pwm_pins>, <&mikro_int_pins>, <&hdmi_pins>, + <&m2_wwan_wake_pins>; +}; + +&pcie { + pinctrl-0 = <&m2_reset_pins>; + pinctrl-names = "default"; + reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie_phy { + clocks = <&hsio_blk_ctrl>; + clock-names = "ref"; + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; + status = "okay"; +}; + +&phy0 { + leds { + /* ADIN1300 LED_0 pin */ + led@0 { + reg = <0>; + color = <LED_COLOR_ID_ORANGE>; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + /delete-node/ led@1; + }; +}; + +&phy1 { + leds { + #address-cells = <1>; + #size-cells = <0>; + + /* ADIN1300 LED_0 pin */ + led@0 { + reg = <0>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-codec.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-codec.dtsi new file mode 100644 index 000000000000..77402a3db9ef --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-codec.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer <josua@solid-run.com> + */ + +/ { + sound-wm8904 { + compatible = "fsl,imx-audio-wm8904"; + model = "audio-wm8904"; + audio-cpu = <&sai3>; + audio-codec = <&codec>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "AMIC", "MICBIAS", + "IN2R", "AMIC"; + }; +}; + +&i2c2 { + codec: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; + clock-names = "mclk"; + AVDD-supply = <&v_1_8>; + CPVDD-supply = <&v_1_8>; + DBVDD-supply = <&v_3_3>; + DCVDD-supply = <&v_1_8>; + MICVDD-supply = <&v_3_3>; + }; +}; + +&iomuxc { + sai3_pins: pinctrl-sai3-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + >; + }; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&sai3_pins>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + fsl,sai-mclk-direction-output; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi new file mode 100644 index 000000000000..825ad6a2ba14 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi @@ -0,0 +1,384 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer <josua@solid-run.com> + */ + +#include <dt-bindings/leds/common.h> + +/ { + aliases { + rtc0 = &carrier_rtc; + rtc1 = &snvs_rtc; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + led-0 { + label = "D30"; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio5 28 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-1 { + label = "D31"; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-2 { + label = "D32"; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-3 { + label = "D33"; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-4 { + label = "D34"; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + rfkill-mpcie-wifi { + /* + * The mpcie connector only has USB, + * therefore this rfkill is for cellular radios only. + */ + compatible = "rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&mpcie_rfkill_pins>; + label = "mpcie radio"; + radio-type = "wwan"; + /* rfkill-gpio inverts internally */ + shutdown-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + }; + + vmmc: regulator-mmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&vmmc_pins>; + regulator-name = "vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + startup-delay-us = <250>; + }; + + vbus1: regulator-vbus-1 { + compatible = "regulator-fixed"; + regulator-name = "vbus1"; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&vbus1_pins>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vbus2: regulator-vbus-2 { + compatible = "regulator-fixed"; + regulator-name = "vbus2"; + gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&vbus2_pins>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + v_1_2: regulator-1-2 { + compatible = "regulator-fixed"; + regulator-name = "1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vmpcie { + /* supplies mpcie and m2 connectors */ + compatible = "regulator-fixed"; + regulator-name = "vmpcie"; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&vmpcie_pins>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +/* mikrobus spi */ +&ecspi2 { + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&mikro_spi_pins>; + status = "okay"; +}; + +&gpio1 { + pinctrl-0 = <&mpcie_reset_pins>; + pinctrl-names = "default"; + + mpcie-reset-hog { + gpio-hog; + gpios = <1 GPIO_ACTIVE_LOW>; + output-low; + line-name = "mpcie-reset"; + }; +}; + +&i2c3 { + carrier_eeprom: eeprom@57{ + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; + + carrier_rtc: rtc@69 { + compatible = "abracon,ab1805"; + reg = <0x69>; + abracon,tc-diode = "schottky"; + abracon,tc-resistor = <3>; + }; +}; + +&iomuxc { + csi_pins: pinctrl-csi-grp { + fsl,pins = < + /* Pin 24: STROBE */ + MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x0 + >; + }; + + led_pins: pinctrl-led-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x0 + MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x0 + MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x0 + MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x0 + MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x0 + >; + }; + + mikro_int_pins: pinctrl-mikro-int-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x0 + >; + }; + + mikro_pwm_pins: pinctrl-mikro-pwm-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x0 + >; + }; + + mikro_rst_pins: pinctrl-mikro-rst-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x0 + >; + }; + + mikro_spi_pins: pinctrl-mikro-spi-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0 0x40000 + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 + >; + }; + + mikro_uart_pins: pinctrl-mikro-uart-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 + >; + }; + + mpcie_reset_pins: pinctrl-mpcie-reset-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x0 + >; + }; + + mpcie_rfkill_pins: pinctrl-pcie-rfkill-grp { + fsl,pins = < + /* weak i/o, open drain */ + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x20 + >; + }; + + usb_hub_pins: pinctrl-usb-hub-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x0 + >; + }; + + usdhc2_pins: pinctrl-usdhc2-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140 + MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140 + >; + }; + + usdhc2_100mhz_pins: pinctrl-usdhc2-100mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140 + MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140 + >; + }; + + usdhc2_200mhz_pins: pinctrl-usdhc2-200mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140 + MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140 + >; + }; + + vbus1_pins: pinctrl-vbus-1-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x20 + >; + }; + + vbus2_pins: pinctrl-vbus-2-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x20 + >; + }; + + vmmc_pins: pinctrl-vmmc-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + >; + }; + + vmpcie_pins: pinctrl-vmpcie-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x0 + >; + }; +}; + +&phy0 { + leds { + #address-cells = <1>; + #size-cells = <0>; + + /* ADIN1300 LED_0 pin */ + led@0 { + reg = <0>; + color = <LED_COLOR_ID_ORANGE>; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + /* ADIN1300 LINK_ST pin */ + led@1 { + reg = <1>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +/* mikrobus uart */ +&uart3 { + status = "okay"; +}; + +&usb3_phy0 { + fsl,phy-tx-preemp-amp-tune-microamp = <1200>; + vbus-supply = <&vbus2>; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_phy1 { + vbus-supply = <&vbus1>; + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "host"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_hub_pins>; + + hub_2_0: hub@1 { + compatible = "usb4b4,6502", "usb4b4,6506"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + vdd-supply = <&v_1_2>; + vdd2-supply = <&v_3_3>; + }; + + hub_3_0: hub@2 { + compatible = "usb4b4,6500", "usb4b4,6504"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + vdd-supply = <&v_1_2>; + vdd2-supply = <&v_3_3>; + }; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&usdhc2_pins>; + pinctrl-1 = <&usdhc2_100mhz_pins>; + pinctrl-2 = <&usdhc2_200mhz_pins>; + vmmc-supply = <&vmmc>; + bus-width = <4>; + cap-power-off-card; + full-pwr-cycle; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-hdmi.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-hdmi.dtsi new file mode 100644 index 000000000000..d7a999c0d7e0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-hdmi.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer <josua@solid-run.com> + */ + +/ { + sound-hdmi { + compatible = "fsl,imx-audio-hdmi"; + model = "audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + }; +}; + +&aud2htx { + status = "okay"; +}; + +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + status = "okay"; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + +&iomuxc { + hdmi_pins: pinctrl-hdmi-grp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x154 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x154 + >; + }; +}; + +&lcdif3 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-m2con.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-m2con.dtsi new file mode 100644 index 000000000000..8d8d8d2e3da8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-m2con.dtsi @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer <josua@solid-run.com> + */ + +/ { + rfkill-m2-gnss { + compatible = "rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&m2_gnss_rfkill_pins>; + label = "m.2 GNSS"; + radio-type = "gps"; + /* rfkill-gpio inverts internally */ + shutdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; + + /* M.2 is B-keyed, so w-disable is for WWAN */ + rfkill-m2-wwan { + compatible = "rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&m2_wwan_rfkill_pins>; + label = "m.2 WWAN"; + radio-type = "wwan"; + /* rfkill-gpio inverts internally */ + shutdown-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + }; +}; + +&iomuxc { + m2_gnss_rfkill_pins: pinctrl-m2-gnss-rfkill-grp { + fsl,pins = < + /* weak i/o, open drain */ + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x20 + >; + }; + + m2_reset_pins: pinctrl-m2-reset-grp { + fsl,pins = < + /* + * 3.3V domain on SoC, set open-drain to ensure + * 1.8V logic on connector + */ + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x20 + >; + }; + + m2_wwan_rfkill_pins: pinctrl-m2-wwan-rfkill-grp { + fsl,pins = < + /* weak i/o, open drain */ + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x20 + >; + }; + + m2_wwan_wake_pins: pinctrl-m2-wwan-wake-grp { + fsl,pins = < + /* weak i/o, open drain */ + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x20 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi new file mode 100644 index 000000000000..46916ddc0533 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer <josua@solid-run.com> + */ + +/ { + hdmi-connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "c"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&adv7535_out>; + }; + }; + }; +}; + +&i2c3 { + hdmi@3d { + compatible = "adi,adv7535"; + reg = <0x3d>, <0x3f>, <0x3c>, <0x38>; + reg-names = "main", "edid", "cec", "packet"; + adi,dsi-lanes = <4>; + avdd-supply = <&v_1_8>; + dvdd-supply = <&v_1_8>; + pvdd-supply = <&v_1_8>; + a2vdd-supply = <&v_1_8>; + v3p3-supply = <&v_3_3>; + pinctrl-names = "default"; + pinctrl-0 = <&mini_hdmi_pins>; + interrupt-parent = <&gpio4>; + interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adv7535_from_dsim: endpoint { + remote-endpoint = <&dsim_to_adv7535>; + }; + }; + + port@1 { + reg = <1>; + + adv7535_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + +&iomuxc { + mini_hdmi_pins: pinctrl-mini-hdmi-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x0 + >; + }; +}; + +&lcdif1 { + status = "okay"; +}; + +&mipi_dsi { + samsung,esc-clock-frequency = <10000000>; + status = "okay"; + + port@1 { + dsim_to_adv7535: endpoint { + remote-endpoint = <&adv7535_from_dsim>; + attach-bridge; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse.dts b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse.dts new file mode 100644 index 000000000000..d32844c3af05 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse.dts @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer <josua@solid-run.com> + */ + +/dts-v1/; + +#include <dt-bindings/phy/phy-imx8-pcie.h> + +#include "imx8mp-sr-som.dtsi" +#include "imx8mp-hummingboard-pulse-codec.dtsi" +#include "imx8mp-hummingboard-pulse-common.dtsi" +#include "imx8mp-hummingboard-pulse-hdmi.dtsi" +#include "imx8mp-hummingboard-pulse-m2con.dtsi" +#include "imx8mp-hummingboard-pulse-mini-hdmi.dtsi" + +/ { + model = "SolidRun i.MX8MP HummingBoard Pulse"; + compatible = "solidrun,imx8mp-hummingboard-pulse", + "solidrun,imx8mp-sr-som", "fsl,imx8mp"; + + aliases { + ethernet0 = &eqos; + ethernet1 = &pcie_eth; + }; +}; + +&fec { + /* this board does not use second phy / ethernet on SoM */ + status = "disabled"; +}; + +&gpio1 { + pinctrl-0 = <&mpcie_reset_pins>, <&m2_reset_pins>; + pinctrl-names = "default"; + + m2-reset-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_LOW>; + output-low; + line-name = "m2-reset"; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&mikro_pwm_pins>, <&mikro_int_pins>, <&hdmi_pins>, + <&m2_wwan_wake_pins>; + + pcie_eth_pins: pinctrl-pcie-eth-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x0 + >; + }; +}; + +&pcie { + pinctrl-0 = <&pcie_eth_pins>; + pinctrl-names = "default"; + reset-gpio = <&gpio4 28 GPIO_ACTIVE_LOW>; + status = "okay"; + + root@0,0 { + compatible = "pci16c3,abcd"; + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + /* Intel i210 */ + pcie_eth: ethernet@1,0 { + compatible = "pci8086,157b"; + reg = <0x00010000 0 0 0 0>; + }; + }; +}; + +&pcie_phy { + clocks = <&hsio_blk_ctrl>; + clock-names = "ref"; + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-ripple.dts b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-ripple.dts new file mode 100644 index 000000000000..4ce5b799b6ab --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-ripple.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer <josua@solid-run.com> + */ + +/dts-v1/; + +#include "imx8mp-sr-som.dtsi" +#include "imx8mp-hummingboard-pulse-common.dtsi" +#include "imx8mp-hummingboard-pulse-mini-hdmi.dtsi" + +/ { + model = "SolidRun i.MX8MP HummingBoard Ripple"; + compatible = "solidrun,imx8mp-hummingboard-ripple", + "solidrun,imx8mp-sr-som", "fsl,imx8mp"; + + aliases { + ethernet0 = &eqos; + /delete-property/ ethernet1; + }; +}; + +&fec { + /* this board does not use second phy / ethernet on SoM */ + status = "disabled"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&mikro_pwm_pins>, <&mikro_int_pins>, <&mikro_rst_pins>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts b/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts index 0eb9e726a9b8..614b4ce330b1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts @@ -123,40 +123,54 @@ /* * Rename SoM signals according to board usage: - * SPI_A_WP -> CAN_ADDR0 - * SPI_A_HOLD -> CAN_ADDR1 - * GPIO_B_0 -> DIO1_OUT - * GPIO_B_1 -> DIO2_OUT + * GPIO_B_0 -> IO_EXP_INT + * GPIO_B_1 -> IO_EXP_RST */ &gpio3 { gpio-line-names = "PCIE_WAKE", "PCIE_CLKREQ", "PCIE_A_PERST", "SDIO_B_D5", - "SDIO_B_D6", "SDIO_B_D7", "CAN_ADDR0", "CAN_ADDR1", + "SDIO_B_D6", "SDIO_B_D7", "SPI_A_WP", "SPI_A_HOLD", "UART_B_RTS", "UART_B_CTS", "SDIO_B_D0", "SDIO_B_D1", "SDIO_B_D2", "SDIO_B_D3", "SDIO_B_WP", "SDIO_B_D4", - "PCIE_SM_ALERT", "SDIO_B_CLK", "SDIO_B_CMD", "DIO1_OUT", - "DIO2_OUT", "", "BOOT_SEL0", "BOOT_SEL1", + "PCIE_SM_ALERT", "SDIO_B_CLK", "SDIO_B_CMD", "IO_EXP_INT", + "IO_EXP_RST", "", "BOOT_SEL0", "BOOT_SEL1", "", "", "SDIO_B_CD", "SDIO_B_PWR_EN", "HDMI_CEC", "HDMI_HPD"; }; /* - * Rename SoM signals according to board usage: - * GPIO_B_5 -> DIO2_IN - * GPIO_B_6 -> DIO3_IN - * GPIO_B_7 -> DIO4_IN - * GPIO_B_3 -> DIO4_OUT - * GPIO_B_4 -> DIO1_IN - * GPIO_B_2 -> DIO3_OUT + * Rename SoM signals according to board usage and remove labels for unsed pins: + * GPIO_A_6 -> TFT_RESET + * GPIO_A_7 -> TFT_STBY + * GPIO_B_3 -> CSI_ENABLE + * GPIO_B_2 -> USB_HUB_RST */ &gpio4 { - gpio-line-names = "DIO2_IN", "DIO3_IN", "DIO4_IN", "GPIO_C_0", + gpio-line-names = "", "", "", "", "ETH_A_MDC", "ETH_A_MDIO", "ETH_A_RXD0", "ETH_A_RXD1", "ETH_A_RXD2", "ETH_A_RXD3", "ETH_A_RX_DV", "ETH_A_RX_CLK", "ETH_A_TXD0", "ETH_A_TXD1", "ETH_A_TXD2", "ETH_A_TXD3", - "ETH_A_TX_EN", "ETH_A_TX_CLK", "DIO4_OUT", "DIO1_IN", - "DIO3_OUT", "GPIO_A_6", "CAN_A_TX", "UART_A_CTS", + "ETH_A_TX_EN", "ETH_A_TX_CLK", "CSI_ENABLE", "", + "USB_HUB_RST", "TFT_RESET", "CAN_A_TX", "UART_A_CTS", "UART_A_RTS", "CAN_A_RX", "CAN_B_TX", "CAN_B_RX", - "GPIO_A_7", "CARRIER_PWR_EN", "I2S_A_DATA_IN", "I2S_LRCLK"; + "TFT_STBY", "CARRIER_PWR_EN", "I2S_A_DATA_IN", "I2S_LRCLK"; +}; + +/* + * Rename SoM signals according to board usage: + * SPI_A_SDI -> CAN_ADDR0 + * SPI_A_SDO -> CAN_ADDR1 + */ +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio5>; + gpio-line-names = "I2S_BITCLK", "I2S_A_DATA_OUT", "I2S_MCLK", "PWM_2", + "PWM_1", "PWM_0", "SPI_A_SCK", "CAN_ADDR1", + "CAN_ADDR0", "SPI_A_CS0", "SPI_B_SCK", "SPI_B_SDO", + "SPI_B_SDI", "SPI_B_CS0", "I2C_A_SCL", "I2C_A_SDA", + "I2C_B_SCL", "I2C_B_SDA", "PCIE_SMCLK", "PCIE_SMDAT", + "I2C_CAM_SCL", "I2C_CAM_SDA", "UART_A_RX", "UART_A_TX", + "UART_C_RX", "UART_C_TX", "UART_CON_RX", "UART_CON_TX", + "UART_B_RX", "UART_B_TX"; }; &hdmi_pvi { @@ -236,8 +250,6 @@ }; &usb_dwc3_1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_hub>; #address-cells = <1>; #size-cells = <0>; dr_mode = "host"; @@ -246,7 +258,7 @@ usb-hub@1 { compatible = "usb424,2514"; reg = <1>; - reset-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; }; }; @@ -297,9 +309,10 @@ >; }; - pinctrl_usb_hub: usbhubgrp { + pinctrl_gpio5: gpio5grp { fsl,pins = < - MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x46 + MX8MP_IOMUXC_ECSPI1_MOSI__GPIO5_IO07 0x46 /* CAN_ADR0 */ + MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x46 /* CAN_ADR1 */ >; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-lt6.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-lt6.dts index baecf768a2ee..e602c1c96143 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-lt6.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-lt6.dts @@ -83,7 +83,7 @@ compatible = "ti,tsc2046e-adc"; reg = <0>; pinctrl-0 = <&pinctrl_touch>; - pinctrl-names ="default"; + pinctrl-names = "default"; spi-max-frequency = <1000000>; interrupts-extended = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>; #io-channel-cells = <1>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi new file mode 100644 index 000000000000..4e6629f940bf --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi @@ -0,0 +1,591 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer <josua@solid-run.com> + */ + +#include "imx8mp.dtsi" + +/ { + model = "SolidRun i.MX8MP SoM"; + compatible = "solidrun,imx8mp-sr-som", "fsl,imx8mp"; + + chosen { + bootargs = "earlycon=ec_imx6q,0x30890000,115200"; + stdout-path = &uart2; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0xc0000000>, + <0x1 0x00000000 0 0xc0000000>; + }; + + usdhc1_pwrseq: usdhc1-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + }; + + v_1_8: regulator-1-8 { + compatible = "regulator-fixed"; + regulator-name = "1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + v_3_3: regulator-3-3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +/* + * Reserve all physical memory from within the first 1GB of DDR address + * space to avoid panic on low memory systems. + */ +&dsp_reserved { + reg = <0 0x6f000000 0 0x1000000>; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&eqos_pins>, <&phy0_pins>; + phy-mode = "rgmii-id"; + phy = <&phy0>; + snps,force_thresh_dma_mode; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <5>; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <5>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + snps,map-to-dma-channel = <4>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&fec_pins>, <&phy1_pins>; + phy-mode = "rgmii-id"; + phy = <&phy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio4>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c1_pins>; + pinctrl-1 = <&i2c1_gpio_pins>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic: pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-0 = <&pmic_pins>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = <3 GPIO_ACTIVE_LOW>; + nxp,i2c-lt-enable; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + som_eeprom: eeprom@50{ + compatible = "st,24c01", "atmel,24c01"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c2_pins>; + pinctrl-1 = <&i2c2_gpio_pins>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c3_pins>; + pinctrl-1 = <&i2c3_gpio_pins>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c4 { + /* routed to basler camera connector */ + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c4_pins>; + pinctrl-1 = <&i2c4_gpio_pins>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&iomuxc { + eqos_pins: pinctrl-eqos-grp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + >; + }; + + fec_pins: pinctrl-fec-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f + >; + }; + + i2c1_pins: pinctrl-i2c1-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + >; + }; + + i2c1_gpio_pins: pinctrl-i2c1-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c3 + >; + }; + + i2c2_pins: pinctrl-i2c2-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 + >; + }; + + i2c2_gpio_pins: pinctrl-i2c2-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c3 + >; + }; + + i2c3_pins: pinctrl-i2c3-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 + >; + }; + + i2c3_gpio_pins: pinctrl-i2c3-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c3 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c3 + >; + }; + + i2c4_pins: pinctrl-i2c4-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 + >; + }; + + i2c4_gpio_pins: pinctrl-i2c4-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c3 + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c3 + >; + }; + + phy0_pins: pinctrl-phy0-grp { + fsl,pins = < + /* RESET_N: weak i/o, open drain, external 1k pull-up */ + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x20 + /* INT_N: weak i/o, open drain, internal pull-up */ + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x160 + >; + }; + + phy1_pins: pinctrl-phy-1-grp { + fsl,pins = < + /* RESET_N: weak i/o, open drain, external 1k pull-up */ + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x20 + /* INT_N: weak i/o, open drain, internal pull-up */ + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x160 + >; + }; + + pmic_pins: pinctrl-pmic-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + >; + }; + + uart1_pins: pinctrl-uart1-grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 + MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 + /* BT_REG_ON */ + MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x0 + /* BT_WAKE_DEV */ + MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x0 + /* BT_WAKE_HOST */ + MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x100 + >; + }; + + uart2_pins: pinctrl-uart2-grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 + >; + }; + + usdhc1_pins: pinctrl-usdhc1-grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + /* WL_REG_ON */ + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x0 + /* WL_WAKE_HOST */ + MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x100 + >; + }; + + usdhc1_100mhz_pins: pinctrl-usdhc1g-100mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + >; + }; + + usdhc1_200mhz_pins: pinctrl-usdhc1-200mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + >; + }; + + usdhc3_pins: pinctrl-usdhc3-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + usdhc3_100mhz_pins: pinctrl-usdhc3-100mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + usdhc3_200mhz_pins: pinctrl-usdhc3-200mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + wdog1_pins: pinctrl-wdog1-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x140 + >; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + uart-has-rtscts; + /* select 80MHz parent clock to support maximum baudrate 4Mbps */ + assigned-clocks = <&clk IMX8MP_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + /* Murata 1MW module supports max. 3M baud */ + max-speed = <3000000>; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&usdhc1_pins>; + pinctrl-1 = <&usdhc1_100mhz_pins>; + pinctrl-2 = <&usdhc1_200mhz_pins>; + vmmc-supply = <&v_3_3>; + vqmmc-supply = <&v_1_8>; + bus-width = <4>; + mmc-pwrseq = <&usdhc1_pwrseq>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&usdhc3_pins>; + pinctrl-1 = <&usdhc3_100mhz_pins>; + pinctrl-2 = <&usdhc3_200mhz_pins>; + vmmc-supply = <&v_3_3>; + vqmmc-supply = <&v_1_8>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&wdog1_pins>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts index d7fd9d36f824..f7346b3d35fe 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts @@ -467,6 +467,10 @@ status = "okay"; }; +®_usdhc2_vqmmc { + status = "okay"; +}; + &sai5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai5>; @@ -876,8 +880,7 @@ <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>, <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>, <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>, - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>, - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { @@ -886,8 +889,7 @@ <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { @@ -896,8 +898,7 @@ <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; }; pinctrl_usdhc2_gpio: usdhc2-gpiogrp { diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index 33cd92e63c5d..4eedd00d83b9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -604,6 +604,10 @@ status = "okay"; }; +®_usdhc2_vqmmc { + status = "okay"; +}; + &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; @@ -983,8 +987,7 @@ <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>, <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>, <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>, - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>, - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { @@ -993,8 +996,7 @@ <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { @@ -1003,8 +1005,7 @@ <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; }; pinctrl_usdhc2_gpio: usdhc2-gpiogrp { diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi index fd70b686e7ef..9716f24f7c6e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi @@ -16,13 +16,18 @@ reg = <0x0 0x40000000 0 0x80000000>; }; - /* identical to buck4_reg, but should never change */ - reg_vcc3v3: regulator-vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC3V3"; - regulator-min-microvolt = <3300000>; + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vqmmc>; + regulator-name = "V_SD2"; + regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; - regulator-always-on; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1>, + <3300000 0x0>; + vin-supply = <&ldo5_reg>; + status = "disabled"; }; }; @@ -173,17 +178,21 @@ read-only; reg = <0x53>; pagesize = <16>; - vcc-supply = <®_vcc3v3>; + vcc-supply = <&buck4_reg>; }; m24c64: eeprom@57 { compatible = "atmel,24c64"; reg = <0x57>; pagesize = <32>; - vcc-supply = <®_vcc3v3>; + vcc-supply = <&buck4_reg>; }; }; +&usdhc2 { + vqmmc-supply = <®_usdhc2_vqmmc>; +}; + &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; @@ -193,7 +202,7 @@ non-removable; no-sd; no-sdio; - vmmc-supply = <®_vcc3v3>; + vmmc-supply = <&buck4_reg>; vqmmc-supply = <&buck5_reg>; status = "okay"; }; @@ -233,6 +242,10 @@ fsl,pins = <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x10>; }; + pinctrl_reg_usdhc2_vqmmc: regusdhc2vqmmcgrp { + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0xc0>; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>, diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dts b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dts index afd886dd590f..88ad422c2760 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dts @@ -36,6 +36,24 @@ vout-supply = <®_5v0_sensor>; }; + flexcan1_phy: can-phy0 { + compatible = "ti,tcan1051", "ti,tcan1042"; + #phy-cells = <0>; + pinctrl-0 = <&pinctrl_flexcan1_stby>; + pinctrl-names = "default"; + max-bitrate = <5000000>; + standby-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; + }; + + flexcan2_phy: can-phy1 { + compatible = "ti,tcan1051", "ti,tcan1042"; + #phy-cells = <0>; + pinctrl-0 = <&pinctrl_flexcan2_stby>; + pinctrl-names = "default"; + max-bitrate = <5000000>; + standby-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + }; + reg_1v8_per: regulator-1v8-per { compatible = "regulator-fixed"; pinctrl-0 = <&pinctrl_reg_1v8>; @@ -85,26 +103,6 @@ regulator-name = "6v4"; }; - reg_can1_stby: regulator-can1-stby { - compatible = "regulator-fixed"; - pinctrl-0 = <&pinctrl_flexcan1_reg>; - pinctrl-names = "default"; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "can1-stby"; - gpio = <&gpio4 3 GPIO_ACTIVE_LOW>; - }; - - reg_can2_stby: regulator-can2-stby { - compatible = "regulator-fixed"; - pinctrl-0 = <&pinctrl_flexcan2_reg>; - pinctrl-names = "default"; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "can2-stby"; - gpio = <&gpio5 9 GPIO_ACTIVE_LOW>; - }; - sound { compatible = "simple-audio-card"; simple-audio-card,bitclock-master = <&cpudai>; @@ -180,16 +178,16 @@ }; &flexcan1 { + phys = <&flexcan1_phy>; pinctrl-0 = <&pinctrl_flexcan1>; pinctrl-names = "default"; - xceiver-supply = <®_can1_stby>; status = "okay"; }; &flexcan2 { + phys = <&flexcan2_phy>; pinctrl-0 = <&pinctrl_flexcan2>; pinctrl-names = "default"; - xceiver-supply = <®_can2_stby>; status = "okay"; }; @@ -278,7 +276,7 @@ >; }; - pinctrl_flexcan1_reg: flexcan1reggrp { + pinctrl_flexcan1_stby: flexcan1stbygrp { fsl,pins = < MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) @@ -294,7 +292,7 @@ >; }; - pinctrl_flexcan2_reg: flexcan2reggrp { + pinctrl_flexcan2_stby: flexcan2stbygrp { fsl,pins = < MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts new file mode 100644 index 000000000000..9ecec1a41878 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts @@ -0,0 +1,907 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2025 Ultratronik + */ + +/dts-v1/; + +#include <dt-bindings/usb/pd.h> +#include "imx8mp.dtsi" + +/ { + model = "NXP i.MX8MPlus Ultratronik MMI_A53 board"; + compatible = "ultratronik,imx8mp-ultra-mach-sbc", "fsl,imx8mp"; + + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + rtc0 = &hwrtc; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = &uart2; + }; + + gpio-sbu-mux { + compatible = "nxp,cbdtu02043", "gpio-sbu-mux"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbu_mux>; + select-gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + orientation-switch; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-0 { + gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; /* Wakeup */ + label = "Wakeup"; + linux,code = <KEY_WAKEUP>; + pinctrl-0 = <&pinctrl_gpio_key_wakeup>; + pinctrl-names = "default"; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led1 { + label = "red"; + gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led2 { + label = "green"; + gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led3 { + label = "yellow"; + gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + reg_usba_vbus: regulator-usba-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + regulator-name = "usb-A-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&ecspi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; + + slb9670: tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <32000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_slb9670>; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, + <&gpio1 8 GPIO_ACTIVE_LOW>, + <&gpio1 9 GPIO_ACTIVE_LOW>; + status = "okay"; + + nfc-transceiver@1 { + compatible = "st,st95hf"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nfc>; + spi-max-frequency = <100000>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + enable-gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>; + }; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x2>; + interrupt-parent = <&gpio4>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&gpio1 { + gpio-line-names = + "#TPM_IRQ", "GPIO1", "", "#PMIC_INT", + "SD2_VSEL", "#TOUCH_IRQ", "#NFC_INT_I", "#NFC_INT", + "#SPI2_CS2", "#SPI2_CS3", "#RTS4", "", + "USB_PWR", "GPIO2", "GPIO3", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "#SD2_CD", "", "", "", + "", "", "", "", "#USB-C_EN", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "DISP_POW", "GPIO4", + "#", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "BKL_POW", "#ETH1_INT", "#TPM_RES", "#PCAP_RES", + "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "#ETH0_INT", "#USB-C_ALERT", + "#USB-C_SEL", "", "", "", + "LED_RED", "LED_GREEN", "LED_YELLOW", "#WAKEUP", + "", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "#SPI1_CS", "", "", "", "#SPI2_CS1", "", "", + "", "", "", "", "ENA_KAM", "ENA_LED", "", "", + "", "", "", "", "", "", "", ""; +}; + +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + ddc-i2c-bus = <&i2c5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + status = "okay"; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 GPIO_ACTIVE_LOW>; + + /* + * i.MX 8M Plus Data Sheet for Consumer Products + * 3.1.4 Operating ranges + * MIMX8ML8DVNLZAB + */ + regulators { + buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */ + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { /* VDD_ARM */ + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + buck4: BUCK4 { /* +3V3 */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck5: BUCK5 { /* +1V8 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6: BUCK6 { /* DRAM_1V1 */ + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1: LDO1 { /* NVCC_SNVS_1V8 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo3: LDO3 { /* VDDA_1P8 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4: LDO4 { /* ENET_2V5 */ + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo5: LDO5 { /* NVCC_SD2 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + + crypto@35 { + compatible = "atmel,atecc508a"; + reg = <0x35>; + }; + + eeprom@50 { + compatible = "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + hwrtc: rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + epson,vdet-disable; + trickle-diode-disable; + }; + + tcpc@52 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x52>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ptn5110>; + interrupt-parent = <&gpio4>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 5000, 3000)>; + op-sink-microwatt = <15000000>; + self-powered; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec_dr_sw: endpoint { + remote-endpoint = <&usb3_drd_sw>; + }; + }; + + port@1 { + reg = <1>; + + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c5 { /* HDMI EDID bus */ + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c5>; + pinctrl-1 = <&pinctrl_i2c5_gpio>; + scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&lcdif3 { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart2 { + /* system console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + /* expansion port serial connection */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + status = "okay"; + + port { + usb3_drd_sw: endpoint { + remote-endpoint = <&typec_dr_sw>; + }; + }; +}; + +&usb3_phy1 { + vbus-supply = <®_usba_vbus>; + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + snps,hsphy_interface = "utmi"; + status = "okay"; +}; + +&usdhc2 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <&ldo5>; + status = "okay"; +}; + +&usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + vmmc-supply = <&buck4>; + vqmmc-supply = <&buck5>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_ecspi1_cs: ecspi1-cs-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40 /* #SPI1_CS */ + >; + }; + + pinctrl_ecspi1: ecspi1-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82 + MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82 + MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82 + >; + }; + + pinctrl_ecspi2_cs: ecspi2-cs-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40 /* #SPI2_CS */ + MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x40 /* #SPI2_CS2 */ + MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40 /* #SPI2_CS3 */ + >; + }; + + pinctrl_ecspi2: ecspi2-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 + >; + }; + + pinctrl_eqos: eqos-grp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x0 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x0 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x10 /* #ETH0_INT */ + >; + }; + + pinctrl_fec: fec-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x0 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x0 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x10 /* #ETH1_INT */ + >; + }; + + pinctrl_flexcan1: flexcan1-grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 + >; + }; + + pinctrl_gpio_key_wakeup: gpio-key-wakeup-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40 /* #WAKEUP */ + >; + }; + + pinctrl_gpio_leds: gpio-leds-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x40 /* LED_RED */ + MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x40 /* LED_GREEN */ + MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x40 /* LED_YELLOW */ + >; + }; + + pinctrl_hdmi: hdmi-grp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x154 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x154 + >; + }; + + pinctrl_hog: hog-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x40 /* GPIO1 */ + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x40 /* GPIO2 */ + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x40 /* GPIO3 */ + MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x40 /* GPIO4 */ + MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x40 /* ENA_KAM */ + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x40 /* ENA_LED */ + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x40 /* #PCAP_RES */ + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x40 /* #RTS4 */ + >; + }; + + pinctrl_i2c1: i2c1-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c0 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c0 + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0xc0 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0xc0 + >; + }; + + pinctrl_i2c2: i2c2-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c0 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c0 + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0xc0 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0xc0 + >; + }; + + pinctrl_i2c3: i2c3-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0xc2 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0xc2 + >; + }; + + pinctrl_i2c5: i2c5-grp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x400000c4 + MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x400000c4 + >; + }; + + pinctrl_i2c5_gpio: i2c5-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0xc4 + MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0xc4 + >; + }; + + pinctrl_nfc: nfc-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x40 /* NFC_INT_I */ + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x40 /* NFC_INT */ + >; + }; + + pinctrl_pmic: pmic-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40 /* #PMIC_INT */ + >; + }; + + pinctrl_ptn5110: ptn5110-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c4 /* #USB-C_ALERT */ + >; + }; + + pinctrl_pwm1: pwm1-grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x116 + >; + }; + + pinctrl_pwm2: pwm2-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x116 /* EXT_PWM */ + >; + }; + + pinctrl_reg_usdhc2_vmmc: reg-usdhc2-vmmc-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 + >; + }; + + pinctrl_sbu_mux: sbu-mux-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x16 /* #USB-C_SEL */ + MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x16 /* #USB-C_EN */ + >; + }; + + pinctrl_slb9670: slb9670-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x40 /* #TPM_IRQ */ + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x40 /* #TPM_RES */ + >; + }; + + pinctrl_uart2: uart2-grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40 + >; + }; + + pinctrl_uart3: uart3-grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x40 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x40 + >; + }; + + pinctrl_uart4: uart4-grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x40 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x40 + >; + }; + + pinctrl_usb1: usb1-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x40 /* USB_PWR */ + >; + }; + + pinctrl_usdhc2: usdhc2-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 /* SD2_VSEL */ + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 /* SD2_VSEL */ + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 /* SD2_VSEL */ + >; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc3: usdhc3-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x40 /* #SD3_RESET */ + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x192 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d2 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x192 + >; + }; + + pinctrl_wdog: wdog-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 /* #WDOG */ + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index bb24dba7338e..a3de6604e29f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -298,7 +298,7 @@ cpu-thermal { polling-delay-passive = <250>; polling-delay = <2000>; - thermal-sensors = <&tmu 0>; + thermal-sensors = <&tmu 1>; trips { cpu_alert0: trip0 { temperature = <85000>; @@ -331,7 +331,7 @@ soc-thermal { polling-delay-passive = <250>; polling-delay = <2000>; - thermal-sensors = <&tmu 1>; + thermal-sensors = <&tmu 0>; trips { soc_alert0: trip0 { temperature = <85000>; @@ -1701,9 +1701,12 @@ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, - <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; - clock-names = "isp", "aclk", "hclk"; - power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>; + clock-names = "isp", "aclk", "hclk", "pclk"; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>, + <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>; + power-domain-names = "isp", "csi2"; fsl,blk-ctrl = <&media_blk_ctrl 0>; status = "disabled"; @@ -1723,9 +1726,12 @@ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, - <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; - clock-names = "isp", "aclk", "hclk"; - power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>; + clock-names = "isp", "aclk", "hclk", "pclk"; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>, + <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>; + power-domain-names = "isp", "csi2"; fsl,blk-ctrl = <&media_blk_ctrl 1>; status = "disabled"; @@ -2045,6 +2051,10 @@ "pai", "pvi", "trng", "hdmi-tx", "hdmi-tx-phy", "hdcp", "hrv"; + interconnects = <&noc IMX8MP_ICM_HRV &noc IMX8MP_ICN_HDMI>, + <&noc IMX8MP_ICM_LCDIF_HDMI &noc IMX8MP_ICN_HDMI>, + <&noc IMX8MP_ICM_HDCP &noc IMX8MP_ICN_HDMI>; + interconnect-names = "hrv", "lcdif-hdmi", "hdcp"; #power-domain-cells = <1>; }; @@ -2317,6 +2327,7 @@ compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, <0x38880000 0xc0000>; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 43e45b0bd0d1..a88bc9034663 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -108,6 +108,7 @@ simple-audio-card,format = "i2s"; simple-audio-card,frame-master = <&cpudai>; simple-audio-card,bitclock-master = <&cpudai>; + simple-audio-card,mclk-fs = <256>; simple-audio-card,widgets = "Line", "Left Line Out Jack", "Line", "Right Line Out Jack"; @@ -117,11 +118,11 @@ cpudai: simple-audio-card,cpu { sound-dai = <&sai2>; + system-clock-direction-out; }; link_codec: simple-audio-card,codec { sound-dai = <&wm8524>; - clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; }; }; @@ -440,6 +441,11 @@ assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>; assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>; assigned-clock-rates = <0>, <24576000>; + clocks = <&clk IMX8MQ_CLK_SAI2_IPG>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI2_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>, + <&clk IMX8MQ_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index c9040d1131a8..607962f807be 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1890,6 +1890,7 @@ <0x31000000 0x2000>, /* GICC */ <0x31010000 0x2000>, /* GICV */ <0x31020000 0x2000>; /* GICH */ + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index 95523c538135..202d5c67ac40 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -406,8 +406,8 @@ model = "wm8960-audio"; audio-cpu = <&sai1>; audio-codec = <&wm8960>; - hp-det-gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; - audio-routing = "Headphone Jack", "HP_L", + hp-det-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; + audio-routing = "Headphone Jack", "HP_L", "Headphone Jack", "HP_R", "Ext Spk", "SPK_LP", "Ext Spk", "SPK_LN", diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi index 50c0f6b0f0bd..bd6e0aa27efe 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi @@ -30,10 +30,10 @@ clock-names = "dbi", "mstr", "slv"; bus-range = <0x00 0xff>; device_type = "pci"; - interrupt-map = <0 0 0 1 &gic 0 73 4>, - <0 0 0 2 &gic 0 74 4>, - <0 0 0 3 &gic 0 75 4>, - <0 0 0 4 &gic 0 76 4>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; interrupt-map-mask = <0 0 0 0x7>; num-lanes = <1>; num-viewport = <4>; @@ -80,10 +80,10 @@ clock-names = "dbi", "mstr", "slv"; bus-range = <0x00 0xff>; device_type = "pci"; - interrupt-map = <0 0 0 1 &gic 0 105 4>, - <0 0 0 2 &gic 0 106 4>, - <0 0 0 3 &gic 0 107 4>, - <0 0 0 4 &gic 0 108 4>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; interrupt-map-mask = <0 0 0 0x7>; num-lanes = <1>; num-viewport = <4>; diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index 827e1365b5da..5206ca82eaf6 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -245,6 +245,7 @@ <0x0 0x52000000 0 0x2000>, /* GICC */ <0x0 0x52010000 0 0x1000>, /* GICH */ <0x0 0x52020000 0 0x20000>; /* GICV */ + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index e54be7f649ff..7b0337445541 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -333,7 +333,7 @@ model = "wm8960-audio"; audio-cpu = <&sai1>; audio-codec = <&wm8960>; - hp-det-gpio = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>; + hp-det-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>; audio-routing = "Headphone Jack", "HP_L", "Headphone Jack", "HP_R", "Ext Spk", "SPK_LP", diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 9e46e16a8dc0..95edab058276 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -159,6 +159,7 @@ compatible = "arm,gic-v3"; reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts new file mode 100644 index 000000000000..5497e3d78136 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +/dts-v1/; + +#include "imx8ulp-evk.dts" + +/ { + model = "NXP i.MX8ULP EVK9"; + compatible = "fsl,imx8ulp-9x9-evk", "fsl,imx8ulp"; +}; + +&btcpu { + sound-dai = <&sai6>; +}; + +&iomuxc1 { + pinctrl_sai6: sai6grp { + fsl,pins = < + MX8ULP_PAD_PTE10__I2S6_TX_BCLK 0x43 + MX8ULP_PAD_PTE11__I2S6_TX_FS 0x43 + MX8ULP_PAD_PTE14__I2S6_TXD2 0x43 + MX8ULP_PAD_PTE6__I2S6_RXD0 0x43 + >; + }; +}; + +&pinctrl_enet { + fsl,pins = < + MX8ULP_PAD_PTF9__ENET0_MDC 0x43 + MX8ULP_PAD_PTF8__ENET0_MDIO 0x43 + MX8ULP_PAD_PTF5__ENET0_RXER 0x43 + MX8ULP_PAD_PTF6__ENET0_CRS_DV 0x43 + MX8ULP_PAD_PTF1__ENET0_RXD0 0x43 + MX8ULP_PAD_PTF0__ENET0_RXD1 0x43 + MX8ULP_PAD_PTF4__ENET0_TXEN 0x43 + MX8ULP_PAD_PTF3__ENET0_TXD0 0x43 + MX8ULP_PAD_PTF2__ENET0_TXD1 0x43 + MX8ULP_PAD_PTF7__ENET0_REFCLK 0x43 + MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43 + >; +}; + +&pinctrl_usb1 { + fsl,pins = < + MX8ULP_PAD_PTE16__USB0_ID 0x10003 + MX8ULP_PAD_PTE18__USB0_OC 0x10003 + >; +}; + +&pinctrl_usb2 { + fsl,pins = < + MX8ULP_PAD_PTD23__USB1_ID 0x10003 + MX8ULP_PAD_PTE20__USB1_OC 0x10003 + >; +}; + +&sai6 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sai6>; + pinctrl-1 = <&pinctrl_sai6>; + assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>, <&cgc2 IMX8ULP_CLK_SAI6_SEL>; + assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>; + assigned-clock-rates = <12288000>; + fsl,dataline = <1 0x01 0x04>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index e602d147e39b..8e9e841cc828 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -462,11 +462,11 @@ /* VPU Mailboxes */ &mu_m0 { - status="okay"; + status = "okay"; }; &mu1_m0 { - status="okay"; + status = "okay"; }; /* TODO MIPI CSI */ diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts new file mode 100644 index 000000000000..aca78768dbd4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts @@ -0,0 +1,674 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +/dts-v1/; + +#include <dt-bindings/usb/pd.h> +#include "imx91.dtsi" + +/ { + compatible = "fsl,imx91-11x11-evk", "fsl,imx91"; + model = "NXP i.MX91 11X11 EVK board"; + + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + rtc0 = &bbnsm_rtc; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + }; + + chosen { + stdout-path = &lpuart1; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vref_1v8"; + }; + + reg_audio_pwr: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "audio-pwr"; + gpio = <&adp5585 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + off-on-delay-us = <12000>; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VSD_3V3"; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x40000000>; + reusable; + size = <0 0x10000000>; + linux,cma-default; + }; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&eqos { + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_eqos>; + pinctrl-1 = <&pinctrl_eqos_sleep>; + pinctrl-names = "default", "sleep"; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + realtek,clkout-disable; + }; + }; +}; + +&fec { + phy-handle = <ðphy2>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_fec>; + pinctrl-1 = <&pinctrl_fec_sleep>; + pinctrl-names = "default", "sleep"; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy2: ethernet-phy@2 { + reg = <2>; + realtek,clkout-disable; + }; + }; +}; + +&lpi2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-names = "default"; + status = "okay"; + + audio_codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clk IMX93_CLK_SAI3_GATE>; + AVDD-supply = <®_audio_pwr>; + CPVDD-supply = <®_audio_pwr>; + DBVDD-supply = <®_audio_pwr>; + DCVDD-supply = <®_audio_pwr>; + MICVDD-supply = <®_audio_pwr>; + PLLVDD-supply = <®_audio_pwr>; + SPKVDD1-supply = <®_audio_pwr>; + SPKVDD2-supply = <®_audio_pwr>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; + + inertial-meter@6a { + compatible = "st,lsm6dso"; + reg = <0x6a>; + }; +}; + +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-names = "default"; + status = "okay"; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + #interrupt-cells = <2>; + interrupt-controller; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio3>; + pinctrl-0 = <&pinctrl_pcal6524>; + pinctrl-names = "default"; + }; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&pcal6524>; + + regulators { + buck1: BUCK1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2237500>; + regulator-min-microvolt = <650000>; + regulator-name = "BUCK1"; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2187500>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK2"; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK4"; + }; + + buck5: BUCK5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK5"; + }; + + buck6: BUCK6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK6"; + }; + + ldo1: LDO1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1600000>; + regulator-name = "LDO1"; + }; + + ldo4: LDO4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <800000>; + regulator-name = "LDO4"; + }; + + ldo5: LDO5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "LDO5"; + }; + }; + }; + + adp5585: io-expander@34 { + compatible = "adi,adp5585-00", "adi,adp5585"; + reg = <0x34>; + #gpio-cells = <2>; + gpio-controller; + #pwm-cells = <3>; + gpio-reserved-ranges = <5 1>; + + exp-sel-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-low; + }; + }; +}; + +&lpi2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-names = "default"; + status = "okay"; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio3>; + + typec1_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <15000000>; + power-role = "dual"; + self-powered; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + }; + }; + + ptn5110_2: tcpc@51 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x51>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio3>; + status = "okay"; + + typec2_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <15000000>; + power-role = "dual"; + self-powered; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec2_dr_sw: endpoint { + remote-endpoint = <&usb2_drd_sw>; + }; + }; + }; + }; + }; + + pcf2131: rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&pcal6524>; + status = "okay"; + }; +}; + +&lpuart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&lpuart5 { + pinctrl-0 = <&pinctrl_uart5>; + pinctrl-names = "default"; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&usbotg1 { + adp-disable; + disable-over-current; + dr_mode = "otg"; + hnp-disable; + srp-disable; + usb-role-switch; + samsung,picophy-dc-vol-level-adjust = <7>; + samsung,picophy-pre-emp-curr-control = <3>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + adp-disable; + disable-over-current; + dr_mode = "otg"; + hnp-disable; + srp-disable; + usb-role-switch; + samsung,picophy-dc-vol-level-adjust = <7>; + samsung,picophy-pre-emp-curr-control = <3>; + status = "okay"; + + port { + usb2_drd_sw: endpoint { + remote-endpoint = <&typec2_dr_sw>; + }; + }; +}; + +&usdhc1 { + bus-width = <8>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + status = "okay"; +}; + +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&wdog3 { + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e + MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe + MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e + MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe + MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_eqos_sleep: eqossleepgrp { + fsl,pins = < + MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e + MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e + MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e + MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e + MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e + MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e + MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e + MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e + MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e + MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e + MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e + MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e + MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e + MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX91_PAD_ENET2_MDC__ENET2_MDC 0x57e + MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x57e + MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x57e + MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x57e + MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x57e + MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x57e + MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x5fe + MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e + MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x57e + MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x57e + MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x57e + MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x57e + MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x5fe + MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_fec_sleep: fecsleepgrp { + fsl,pins = < + MX91_PAD_ENET2_MDC__GPIO4_IO14 0x51e + MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x51e + MX91_PAD_ENET2_RD0__GPIO4_IO24 0x51e + MX91_PAD_ENET2_RD1__GPIO4_IO25 0x51e + MX91_PAD_ENET2_RD2__GPIO4_IO26 0x51e + MX91_PAD_ENET2_RD3__GPIO4_IO27 0x51e + MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e + MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e + MX91_PAD_ENET2_TD0__GPIO4_IO19 0x51e + MX91_PAD_ENET2_TD1__GPIO4_IO18 0x51e + MX91_PAD_ENET2_TD2__GPIO4_IO17 0x51e + MX91_PAD_ENET2_TD3__GPIO4_IO16 0x51e + MX91_PAD_ENET2_TXC__GPIO4_IO21 0x51e + MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX91_PAD_UART1_RXD__LPUART1_RX 0x31e + MX91_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX91_PAD_DAP_TDI__LPUART5_RX 0x31e + MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e + MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582 + MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382 + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382 + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382 + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382 + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382 + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382 + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382 + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382 + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382 + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e + >; + }; + + pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { + fsl,pins = < + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582 + MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382 + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382 + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382 + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382 + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382 + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_sleep: usdhc2sleepgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e + MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e + MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e + MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e + MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e + MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e + MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e + >; + }; + +}; diff --git a/arch/arm64/boot/dts/freescale/imx91-pinfunc.h b/arch/arm64/boot/dts/freescale/imx91-pinfunc.h new file mode 100644 index 000000000000..3e19945f5ce3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-pinfunc.h @@ -0,0 +1,770 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright 2025 NXP + */ + +#ifndef __DTS_IMX91_PINFUNC_H +#define __DTS_IMX91_PINFUNC_H + +/* + * The pin function ID is a tuple of + * <mux_reg conf_reg input_reg mux_mode input_val> + */ +#define MX91_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01b0 0x03d8 0x00 0x00 +#define MX91_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01b0 0x0000 0x01 0x00 +#define MX91_PAD_DAP_TDI__CAN2_TX 0x0000 0x01b0 0x0000 0x03 0x00 +#define MX91_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01b0 0x0000 0x04 0x00 +#define MX91_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01b0 0x0000 0x05 0x00 +#define MX91_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01b0 0x0488 0x06 0x00 + +#define MX91_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01b4 0x03dc 0x00 0x00 +#define MX91_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01b4 0x0000 0x04 0x00 +#define MX91_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01b4 0x0000 0x05 0x00 +#define MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01b4 0x0000 0x06 0x00 + +#define MX91_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x01b8 0x03d4 0x00 0x00 +#define MX91_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x0008 0x01b8 0x0000 0x04 0x00 +#define MX91_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x0008 0x01b8 0x0000 0x05 0x00 +#define MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x01b8 0x0484 0x06 0x00 + +#define MX91_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000c 0x01bc 0x0000 0x00 0x00 +#define MX91_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x000c 0x01bc 0x0000 0x01 0x00 +#define MX91_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000c 0x01bc 0x0364 0x03 0x00 +#define MX91_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x000c 0x01bc 0x0000 0x04 0x00 +#define MX91_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x000c 0x01bc 0x0000 0x05 0x00 +#define MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000c 0x01bc 0x048c 0x06 0x00 + +#define MX91_PAD_GPIO_IO00__GPIO2_IO0 0x0010 0x01c0 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x01c0 0x03f4 0x01 0x00 +#define MX91_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x0010 0x01c0 0x04bc 0x02 0x00 +#define MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x0010 0x01c0 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x01c0 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x01c0 0x048c 0x05 0x01 +#define MX91_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x01c0 0x0404 0x06 0x00 +#define MX91_PAD_GPIO_IO00__FLEXIO1_FLEXIO0 0x0010 0x01c0 0x036c 0x07 0x00 + +#define MX91_PAD_GPIO_IO01__GPIO2_IO1 0x0014 0x01c4 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x01c4 0x03f0 0x01 0x00 +#define MX91_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA0 0x0014 0x01c4 0x0490 0x02 0x00 +#define MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x0014 0x01c4 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x01c4 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x01c4 0x0488 0x05 0x01 +#define MX91_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x01c4 0x0400 0x06 0x00 +#define MX91_PAD_GPIO_IO01__FLEXIO1_FLEXIO1 0x0014 0x01c4 0x0370 0x07 0x00 + +#define MX91_PAD_GPIO_IO02__GPIO2_IO2 0x0018 0x01c8 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x01c8 0x03fc 0x01 0x00 +#define MX91_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0x0018 0x01c8 0x04c0 0x02 0x00 +#define MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x0018 0x01c8 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x01c8 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x01c8 0x0484 0x05 0x01 +#define MX91_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x01c8 0x040c 0x06 0x00 +#define MX91_PAD_GPIO_IO02__FLEXIO1_FLEXIO2 0x0018 0x01c8 0x0374 0x07 0x00 + +#define MX91_PAD_GPIO_IO03__GPIO2_IO3 0x001c 0x01cc 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO03__LPI2C4_SCL 0x001c 0x01cc 0x03f8 0x01 0x00 +#define MX91_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0x001c 0x01cc 0x04b8 0x02 0x00 +#define MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x001c 0x01cc 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO03__LPSPI6_SCK 0x001c 0x01cc 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO03__LPUART5_RTS_B 0x001c 0x01cc 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO03__LPI2C6_SCL 0x001c 0x01cc 0x0408 0x06 0x00 +#define MX91_PAD_GPIO_IO03__FLEXIO1_FLEXIO3 0x001c 0x01cc 0x0378 0x07 0x00 + +#define MX91_PAD_GPIO_IO04__GPIO2_IO4 0x0020 0x01d0 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x01d0 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO04__PDM_CLK 0x0020 0x01d0 0x0000 0x02 0x00 +#define MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0 0x0020 0x01d0 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x01d0 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x01d0 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x01d0 0x040c 0x06 0x01 +#define MX91_PAD_GPIO_IO04__FLEXIO1_FLEXIO4 0x0020 0x01d0 0x037c 0x07 0x00 + +#define MX91_PAD_GPIO_IO05__GPIO2_IO5 0x0024 0x01d4 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x01d4 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO05__PDM_BIT_STREAM0 0x0024 0x01d4 0x04c4 0x02 0x00 +#define MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1 0x0024 0x01d4 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x01d4 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x01d4 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x01d4 0x0408 0x06 0x01 +#define MX91_PAD_GPIO_IO05__FLEXIO1_FLEXIO5 0x0024 0x01d4 0x0380 0x07 0x00 + +#define MX91_PAD_GPIO_IO06__GPIO2_IO6 0x0028 0x01d8 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x01d8 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO06__PDM_BIT_STREAM1 0x0028 0x01d8 0x04c8 0x02 0x00 +#define MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2 0x0028 0x01d8 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x01d8 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x01d8 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x01d8 0x0414 0x06 0x00 +#define MX91_PAD_GPIO_IO06__FLEXIO1_FLEXIO6 0x0028 0x01d8 0x0384 0x07 0x00 + +#define MX91_PAD_GPIO_IO07__GPIO2_IO7 0x002c 0x01dc 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO07__LPSPI3_PCS1 0x002c 0x01dc 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA1 0x002c 0x01dc 0x0494 0x02 0x00 +#define MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3 0x002c 0x01dc 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO07__LPSPI7_SCK 0x002c 0x01dc 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO07__LPUART6_RTS_B 0x002c 0x01dc 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO07__LPI2C7_SCL 0x002c 0x01dc 0x0410 0x06 0x00 +#define MX91_PAD_GPIO_IO07__FLEXIO1_FLEXIO7 0x002c 0x01dc 0x0388 0x07 0x00 + +#define MX91_PAD_GPIO_IO08__GPIO2_IO8 0x0030 0x01e0 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x01e0 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA2 0x0030 0x01e0 0x0498 0x02 0x00 +#define MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4 0x0030 0x01e0 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x01e0 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x01e0 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x01e0 0x0414 0x06 0x01 +#define MX91_PAD_GPIO_IO08__FLEXIO1_FLEXIO8 0x0030 0x01e0 0x038c 0x07 0x00 + +#define MX91_PAD_GPIO_IO09__GPIO2_IO9 0x0034 0x01e4 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x01e4 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA3 0x0034 0x01e4 0x049c 0x02 0x00 +#define MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5 0x0034 0x01e4 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x01e4 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x01e4 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x01e4 0x0410 0x06 0x01 +#define MX91_PAD_GPIO_IO09__FLEXIO1_FLEXIO9 0x0034 0x01e4 0x0390 0x07 0x00 + +#define MX91_PAD_GPIO_IO10__GPIO2_IO10 0x0038 0x01e8 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x01e8 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA4 0x0038 0x01e8 0x04a0 0x02 0x00 +#define MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6 0x0038 0x01e8 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x01e8 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x01e8 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x01e8 0x041c 0x06 0x00 +#define MX91_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x0038 0x01e8 0x0394 0x07 0x00 + +#define MX91_PAD_GPIO_IO11__GPIO2_IO11 0x003c 0x01ec 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO11__LPSPI3_SCK 0x003c 0x01ec 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA5 0x003c 0x01ec 0x04a4 0x02 0x00 +#define MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7 0x003c 0x01ec 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO11__TPM5_EXTCLK 0x003c 0x01ec 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO11__LPUART7_RTS_B 0x003c 0x01ec 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO11__LPI2C8_SCL 0x003c 0x01ec 0x0418 0x06 0x00 +#define MX91_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x003c 0x01ec 0x0398 0x07 0x00 + +#define MX91_PAD_GPIO_IO12__GPIO2_IO12 0x0040 0x01f0 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x01f0 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO12__PDM_BIT_STREAM2 0x0040 0x01f0 0x04cc 0x02 0x00 +#define MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8 0x0040 0x01f0 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x01f0 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x01f0 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x01f0 0x041c 0x06 0x01 +#define MX91_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x01f0 0x04dc 0x07 0x00 + +#define MX91_PAD_GPIO_IO13__GPIO2_IO13 0x0044 0x01f4 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x01f4 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO13__PDM_BIT_STREAM3 0x0044 0x01f4 0x04d0 0x02 0x00 +#define MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9 0x0044 0x01f4 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x01f4 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x01f4 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x01f4 0x0418 0x06 0x01 +#define MX91_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x0044 0x01f4 0x039c 0x07 0x00 + +#define MX91_PAD_GPIO_IO14__GPIO2_IO14 0x0048 0x01f8 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x01f8 0x0474 0x01 0x00 +#define MX91_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA6 0x0048 0x01f8 0x04a8 0x02 0x00 +#define MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x0048 0x01f8 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x01f8 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x01f8 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x01f8 0x0480 0x06 0x00 +#define MX91_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x0048 0x01f8 0x03a0 0x07 0x00 + +#define MX91_PAD_GPIO_IO15__GPIO2_IO15 0x004c 0x01fc 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO15__LPUART3_RX 0x004c 0x01fc 0x0470 0x01 0x00 +#define MX91_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA7 0x004c 0x01fc 0x04ac 0x02 0x00 +#define MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x004c 0x01fc 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO15__LPSPI8_SCK 0x004c 0x01fc 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO15__LPUART8_RTS_B 0x004c 0x01fc 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO15__LPUART4_RX 0x004c 0x01fc 0x047c 0x06 0x00 +#define MX91_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x004c 0x01fc 0x03a4 0x07 0x00 + +#define MX91_PAD_GPIO_IO16__GPIO2_IO16 0x0050 0x0200 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO16__SAI3_TX_BCLK 0x0050 0x0200 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO16__PDM_BIT_STREAM2 0x0050 0x0200 0x04cc 0x02 0x01 +#define MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x0050 0x0200 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0200 0x046c 0x04 0x00 +#define MX91_PAD_GPIO_IO16__LPSPI4_PCS2 0x0050 0x0200 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0200 0x0478 0x06 0x00 +#define MX91_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 0x0050 0x0200 0x03a8 0x07 0x00 + +#define MX91_PAD_GPIO_IO17__GPIO2_IO17 0x0054 0x0204 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO17__SAI3_MCLK 0x0054 0x0204 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA8 0x0054 0x0204 0x04b0 0x02 0x00 +#define MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x0054 0x0204 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO17__LPUART3_RTS_B 0x0054 0x0204 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO17__LPSPI4_PCS1 0x0054 0x0204 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO17__LPUART4_RTS_B 0x0054 0x0204 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 0x0054 0x0204 0x03ac 0x07 0x00 + +#define MX91_PAD_GPIO_IO18__GPIO2_IO18 0x0058 0x0208 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x0208 0x04d8 0x01 0x00 +#define MX91_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA9 0x0058 0x0208 0x04b4 0x02 0x00 +#define MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x0058 0x0208 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO18__LPSPI5_PCS0 0x0058 0x0208 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO18__LPSPI4_PCS0 0x0058 0x0208 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO18__TPM5_CH2 0x0058 0x0208 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 0x0058 0x0208 0x03b0 0x07 0x00 + +#define MX91_PAD_GPIO_IO19__GPIO2_IO19 0x005c 0x020c 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005c 0x020c 0x04dc 0x01 0x01 +#define MX91_PAD_GPIO_IO19__PDM_BIT_STREAM3 0x005c 0x020c 0x04d0 0x02 0x01 +#define MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x005c 0x020c 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO19__LPSPI5_SIN 0x005c 0x020c 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO19__LPSPI4_SIN 0x005c 0x020c 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO19__TPM6_CH2 0x005c 0x020c 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO19__SAI3_TX_DATA0 0x005c 0x020c 0x0000 0x07 0x00 + +#define MX91_PAD_GPIO_IO20__GPIO2_IO20 0x0060 0x0210 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO20__SAI3_RX_DATA0 0x0060 0x0210 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO20__PDM_BIT_STREAM0 0x0060 0x0210 0x04c4 0x02 0x01 +#define MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x0060 0x0210 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO20__LPSPI5_SOUT 0x0060 0x0210 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO20__LPSPI4_SOUT 0x0060 0x0210 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO20__TPM3_CH1 0x0060 0x0210 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 0x0060 0x0210 0x03b4 0x07 0x00 + +#define MX91_PAD_GPIO_IO21__GPIO2_IO21 0x0064 0x0214 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO21__SAI3_TX_DATA0 0x0064 0x0214 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO21__PDM_CLK 0x0064 0x0214 0x0000 0x02 0x00 +#define MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x0064 0x0214 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO21__LPSPI5_SCK 0x0064 0x0214 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO21__LPSPI4_SCK 0x0064 0x0214 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO21__TPM4_CH1 0x0064 0x0214 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0214 0x04d8 0x07 0x01 + +#define MX91_PAD_GPIO_IO22__GPIO2_IO22 0x0068 0x0218 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x0218 0x04e8 0x01 0x00 +#define MX91_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x0218 0x04e4 0x02 0x00 +#define MX91_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x0068 0x0218 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO22__TPM5_CH1 0x0068 0x0218 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO22__TPM6_EXTCLK 0x0068 0x0218 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x0218 0x0404 0x06 0x01 +#define MX91_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 0x0068 0x0218 0x03b8 0x07 0x00 + +#define MX91_PAD_GPIO_IO23__GPIO2_IO23 0x006c 0x021c 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO23__USDHC3_CMD 0x006c 0x021c 0x04ec 0x01 0x00 +#define MX91_PAD_GPIO_IO23__SPDIF_OUT 0x006c 0x021c 0x0000 0x02 0x00 +#define MX91_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x006c 0x021c 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO23__TPM6_CH1 0x006c 0x021c 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO23__LPI2C5_SCL 0x006c 0x021c 0x0400 0x06 0x01 +#define MX91_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 0x006c 0x021c 0x03bc 0x07 0x00 + +#define MX91_PAD_GPIO_IO24__GPIO2_IO24 0x0070 0x0220 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0220 0x04f0 0x01 0x00 +#define MX91_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x0070 0x0220 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO24__TPM3_CH3 0x0070 0x0220 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO24__JTAG_MUX_TDO 0x0070 0x0220 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO24__LPSPI6_PCS1 0x0070 0x0220 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 0x0070 0x0220 0x03c0 0x07 0x00 + +#define MX91_PAD_GPIO_IO25__GPIO2_IO25 0x0074 0x0224 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0224 0x04f4 0x01 0x00 +#define MX91_PAD_GPIO_IO25__CAN2_TX 0x0074 0x0224 0x0000 0x02 0x00 +#define MX91_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x0074 0x0224 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO25__TPM4_CH3 0x0074 0x0224 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0224 0x03d4 0x05 0x01 +#define MX91_PAD_GPIO_IO25__LPSPI7_PCS1 0x0074 0x0224 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 0x0074 0x0224 0x03c4 0x07 0x00 + +#define MX91_PAD_GPIO_IO26__GPIO2_IO26 0x0078 0x0228 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x0228 0x04f8 0x01 0x00 +#define MX91_PAD_GPIO_IO26__PDM_BIT_STREAM1 0x0078 0x0228 0x04c8 0x02 0x01 +#define MX91_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x0078 0x0228 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO26__TPM5_CH3 0x0078 0x0228 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x0228 0x03d8 0x05 0x01 +#define MX91_PAD_GPIO_IO26__LPSPI8_PCS1 0x0078 0x0228 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO26__SAI3_TX_SYNC 0x0078 0x0228 0x04e0 0x07 0x00 + +#define MX91_PAD_GPIO_IO27__GPIO2_IO27 0x007c 0x022c 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO27__USDHC3_DATA3 0x007c 0x022c 0x04fc 0x01 0x00 +#define MX91_PAD_GPIO_IO27__CAN2_RX 0x007c 0x022c 0x0364 0x02 0x01 +#define MX91_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x007c 0x022c 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO27__TPM6_CH3 0x007c 0x022c 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007c 0x022c 0x03dc 0x05 0x01 +#define MX91_PAD_GPIO_IO27__LPSPI5_PCS1 0x007c 0x022c 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 0x007c 0x022c 0x03c8 0x07 0x00 + +#define MX91_PAD_GPIO_IO28__GPIO2_IO28 0x0080 0x0230 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0230 0x03f4 0x01 0x01 +#define MX91_PAD_GPIO_IO28__CAN1_TX 0x0080 0x0230 0x0000 0x02 0x00 +#define MX91_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 0x0080 0x0230 0x0000 0x07 0x00 + +#define MX91_PAD_GPIO_IO29__GPIO2_IO29 0x0084 0x0234 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0234 0x03f0 0x01 0x01 +#define MX91_PAD_GPIO_IO29__CAN1_RX 0x0084 0x0234 0x0360 0x02 0x00 +#define MX91_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 0x0084 0x0234 0x0000 0x07 0x00 + +#define MX91_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 0x0088 0x0238 0x0000 0x00 0x00 +#define MX91_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 0x0088 0x0238 0x0000 0x04 0x00 +#define MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x0088 0x0238 0x0000 0x05 0x00 + +#define MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x008c 0x023c 0x0000 0x05 0x00 +#define MX91_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 0x008c 0x023c 0x0000 0x00 0x00 +#define MX91_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 0x008c 0x023c 0x03c8 0x04 0x01 + +#define MX91_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x0090 0x0240 0x0000 0x00 0x00 +#define MX91_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 0x0090 0x0240 0x0000 0x04 0x00 +#define MX91_PAD_CCM_CLKO3__GPIO4_IO28 0x0090 0x0240 0x0000 0x05 0x00 + +#define MX91_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 0x0094 0x0244 0x0000 0x00 0x00 +#define MX91_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 0x0094 0x0244 0x0000 0x04 0x00 +#define MX91_PAD_CCM_CLKO4__GPIO4_IO29 0x0094 0x0244 0x0000 0x05 0x00 + +#define MX91_PAD_ENET1_MDC__ENET1_MDC 0x0098 0x0248 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_MDC__LPUART3_DCB_B 0x0098 0x0248 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_MDC__I3C2_SCL 0x0098 0x0248 0x03cc 0x02 0x00 +#define MX91_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 0x0098 0x0248 0x0000 0x03 0x00 +#define MX91_PAD_ENET1_MDC__FLEXIO2_FLEXIO0 0x0098 0x0248 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_MDC__GPIO4_IO0 0x0098 0x0248 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_MDC__LPI2C1_SCL 0x0098 0x0248 0x03e0 0x06 0x00 + +#define MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x009c 0x024c 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_MDIO__LPUART3_RIN_B 0x009c 0x024c 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_MDIO__I3C2_SDA 0x009c 0x024c 0x03d0 0x02 0x00 +#define MX91_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 0x009c 0x024c 0x0000 0x03 0x00 +#define MX91_PAD_ENET1_MDIO__FLEXIO2_FLEXIO1 0x009c 0x024c 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x009c 0x024c 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_MDIO__LPI2C1_SDA 0x009c 0x024c 0x03e4 0x06 0x00 + +#define MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x00a0 0x0250 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_TD3__CAN2_TX 0x00a0 0x0250 0x0000 0x02 0x00 +#define MX91_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 0x00a0 0x0250 0x0000 0x03 0x00 +#define MX91_PAD_ENET1_TD3__FLEXIO2_FLEXIO2 0x00a0 0x0250 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_TD3__GPIO4_IO2 0x00a0 0x0250 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_TD3__LPI2C2_SCL 0x00a0 0x0250 0x03e8 0x06 0x00 + +#define MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x00a4 0x0254 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_TD2__ENET_QOS_CLOCK_GENERATE_CLK 0x00a4 0x0254 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_TD2__CAN2_RX 0x00a4 0x0254 0x0364 0x02 0x02 +#define MX91_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 0x00a4 0x0254 0x0000 0x03 0x00 +#define MX91_PAD_ENET1_TD2__FLEXIO2_FLEXIO3 0x00a4 0x0254 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_TD2__GPIO4_IO3 0x00a4 0x0254 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_TD2__LPI2C2_SDA 0x00a4 0x0254 0x03ec 0x06 0x00 + +#define MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x00a8 0x0258 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_TD1__LPUART3_RTS_B 0x00a8 0x0258 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_TD1__I3C2_PUR 0x00a8 0x0258 0x0000 0x02 0x00 +#define MX91_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 0x00a8 0x0258 0x0000 0x03 0x00 +#define MX91_PAD_ENET1_TD1__FLEXIO2_FLEXIO4 0x00a8 0x0258 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_TD1__GPIO4_IO4 0x00a8 0x0258 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_TD1__I3C2_PUR_B 0x00a8 0x0258 0x0000 0x06 0x00 + +#define MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x00ac 0x025c 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_TD0__LPUART3_TX 0x00ac 0x025c 0x0474 0x01 0x01 +#define MX91_PAD_ENET1_TD0__FLEXIO2_FLEXIO5 0x00ac 0x025c 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_TD0__GPIO4_IO5 0x00ac 0x025c 0x0000 0x05 0x00 + +#define MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x00b0 0x0260 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x00b0 0x0260 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO6 0x00b0 0x0260 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x00b0 0x0260 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_TX_CTL__LPSPI2_SCK 0x00b0 0x0260 0x043c 0x02 0x00 + +#define MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x00b4 0x0264 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_TXC__ENET_QOS_TX_ER 0x00b4 0x0264 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_TXC__FLEXIO2_FLEXIO7 0x00b4 0x0264 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_TXC__GPIO4_IO7 0x00b4 0x0264 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_TXC__LPSPI2_SIN 0x00b4 0x0264 0x0440 0x02 0x00 + +#define MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x00b8 0x0268 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x00b8 0x0268 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 0x00b8 0x0268 0x0000 0x03 0x00 +#define MX91_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO8 0x00b8 0x0268 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x00b8 0x0268 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_RX_CTL__LPSPI2_PCS0 0x00b8 0x0268 0x0434 0x02 0x00 + +#define MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x00bc 0x026c 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x00bc 0x026c 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_RXC__FLEXIO2_FLEXIO9 0x00bc 0x026c 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_RXC__GPIO4_IO9 0x00bc 0x026c 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_RXC__LPSPI2_SOUT 0x00bc 0x026c 0x0444 0x02 0x00 + +#define MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x00c0 0x0270 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_RD0__LPUART3_RX 0x00c0 0x0270 0x0470 0x01 0x01 +#define MX91_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 0x00c0 0x0270 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_RD0__GPIO4_IO10 0x00c0 0x0270 0x0000 0x05 0x00 + +#define MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x00c4 0x0274 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_RD1__LPUART3_CTS_B 0x00c4 0x0274 0x046c 0x01 0x01 +#define MX91_PAD_ENET1_RD1__LPTMR2_ALT1 0x00c4 0x0274 0x0448 0x03 0x00 +#define MX91_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 0x00c4 0x0274 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_RD1__GPIO4_IO11 0x00c4 0x0274 0x0000 0x05 0x00 + +#define MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x00c8 0x0278 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_RD2__LPTMR2_ALT2 0x00c8 0x0278 0x044c 0x03 0x00 +#define MX91_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 0x00c8 0x0278 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_RD2__GPIO4_IO12 0x00c8 0x0278 0x0000 0x05 0x00 + +#define MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x00cc 0x027c 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER 0x00cc 0x027c 0x0000 0x02 0x00 +#define MX91_PAD_ENET1_RD3__LPTMR2_ALT3 0x00cc 0x027c 0x0450 0x03 0x00 +#define MX91_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 0x00cc 0x027c 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_RD3__GPIO4_IO13 0x00cc 0x027c 0x0000 0x05 0x00 + +#define MX91_PAD_ENET2_MDC__ENET2_MDC 0x00d0 0x0280 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_MDC__LPUART4_DCB_B 0x00d0 0x0280 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_MDC__SAI2_RX_SYNC 0x00d0 0x0280 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 0x00d0 0x0280 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_MDC__GPIO4_IO14 0x00d0 0x0280 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_MDC__MEDIAMIX_CAM_CLK 0x00d0 0x0280 0x04bc 0x06 0x01 + +#define MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x00d4 0x0284 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_MDIO__LPUART4_RIN_B 0x00d4 0x0284 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_MDIO__SAI2_RX_BCLK 0x00d4 0x0284 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 0x00d4 0x0284 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x00d4 0x0284 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_MDIO__MEDIAMIX_CAM_DATA0 0x00d4 0x0284 0x0490 0x06 0x01 + +#define MX91_PAD_ENET2_TD3__SAI2_RX_DATA0 0x00d8 0x0288 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 0x00d8 0x0288 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_TD3__GPIO4_IO16 0x00d8 0x0288 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_TD3__MEDIAMIX_CAM_VSYNC 0x00d8 0x0288 0x04c0 0x06 0x01 +#define MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x00d8 0x0288 0x0000 0x00 0x00 + +#define MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x00dc 0x028c 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_TD2__ENET2_TX_CLK2 0x00dc 0x028c 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 0x00dc 0x028c 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_TD2__GPIO4_IO17 0x00dc 0x028c 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_TD2__MEDIAMIX_CAM_HSYNC 0x00dc 0x028c 0x04b8 0x06 0x01 + +#define MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x00e0 0x0290 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_TD1__LPUART4_RTS_B 0x00e0 0x0290 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 0x00e0 0x0290 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_TD1__GPIO4_IO18 0x00e0 0x0290 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_TD1__MEDIAMIX_CAM_DATA1 0x00e0 0x0290 0x0494 0x06 0x01 + +#define MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x00e4 0x0294 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_TD0__LPUART4_TX 0x00e4 0x0294 0x0480 0x01 0x01 +#define MX91_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 0x00e4 0x0294 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_TD0__GPIO4_IO19 0x00e4 0x0294 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_TD0__MEDIAMIX_CAM_DATA2 0x00e4 0x0294 0x0498 0x06 0x01 + +#define MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x00e8 0x0298 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x00e8 0x0298 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_TX_CTL__SAI2_TX_SYNC 0x00e8 0x0298 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 0x00e8 0x0298 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x00e8 0x0298 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_TX_CTL__MEDIAMIX_CAM_DATA3 0x00e8 0x0298 0x049c 0x06 0x01 + +#define MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x00ec 0x029c 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_TXC__ENET2_TX_ER 0x00ec 0x029c 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_TXC__SAI2_TX_BCLK 0x00ec 0x029c 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 0x00ec 0x029c 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_TXC__GPIO4_IO21 0x00ec 0x029c 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_TXC__MEDIAMIX_CAM_DATA4 0x00ec 0x029c 0x04a0 0x06 0x01 + +#define MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x00f0 0x02a0 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x00f0 0x02a0 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_RX_CTL__SAI2_TX_DATA0 0x00f0 0x02a0 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 0x00f0 0x02a0 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x00f0 0x02a0 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_RX_CTL__MEDIAMIX_CAM_DATA5 0x00f0 0x02a0 0x04a4 0x06 0x01 + +#define MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x00f4 0x02a4 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_RXC__ENET2_RX_ER 0x00f4 0x02a4 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 0x00f4 0x02a4 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_RXC__GPIO4_IO23 0x00f4 0x02a4 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_RXC__MEDIAMIX_CAM_DATA6 0x00f4 0x02a4 0x04a8 0x06 0x01 + +#define MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x00f8 0x02a8 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_RD0__LPUART4_RX 0x00f8 0x02a8 0x047c 0x01 0x01 +#define MX91_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 0x00f8 0x02a8 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_RD0__GPIO4_IO24 0x00f8 0x02a8 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_RD0__MEDIAMIX_CAM_DATA7 0x00f8 0x02a8 0x04ac 0x06 0x01 + +#define MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x00fc 0x02ac 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_RD1__SPDIF_IN 0x00fc 0x02ac 0x04e4 0x01 0x01 +#define MX91_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 0x00fc 0x02ac 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_RD1__GPIO4_IO25 0x00fc 0x02ac 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_RD1__MEDIAMIX_CAM_DATA8 0x00fc 0x02ac 0x04b0 0x06 0x01 + +#define MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x0100 0x02b0 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_RD2__LPUART4_CTS_B 0x0100 0x02b0 0x0478 0x01 0x01 +#define MX91_PAD_ENET2_RD2__SAI2_MCLK 0x0100 0x02b0 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_RD2__MQS2_RIGHT 0x0100 0x02b0 0x0000 0x03 0x00 +#define MX91_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 0x0100 0x02b0 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_RD2__GPIO4_IO26 0x0100 0x02b0 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_RD2__MEDIAMIX_CAM_DATA9 0x0100 0x02b0 0x04b4 0x06 0x01 + +#define MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x0104 0x02b4 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_RD3__SPDIF_OUT 0x0104 0x02b4 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_RD3__SPDIF_IN 0x0104 0x02b4 0x04e4 0x02 0x02 +#define MX91_PAD_ENET2_RD3__MQS2_LEFT 0x0104 0x02b4 0x0000 0x03 0x00 +#define MX91_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 0x0104 0x02b4 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_RD3__GPIO4_IO27 0x0104 0x02b4 0x0000 0x05 0x00 + +#define MX91_PAD_SD1_CLK__FLEXIO1_FLEXIO8 0x0108 0x02b8 0x038c 0x04 0x01 +#define MX91_PAD_SD1_CLK__GPIO3_IO8 0x0108 0x02b8 0x0000 0x05 0x00 +#define MX91_PAD_SD1_CLK__USDHC1_CLK 0x0108 0x02b8 0x0000 0x00 0x00 +#define MX91_PAD_SD1_CLK__LPSPI2_SCK 0x0108 0x02b8 0x043c 0x03 0x01 + +#define MX91_PAD_SD1_CMD__USDHC1_CMD 0x010c 0x02bc 0x0000 0x00 0x00 +#define MX91_PAD_SD1_CMD__FLEXIO1_FLEXIO9 0x010c 0x02bc 0x0390 0x04 0x01 +#define MX91_PAD_SD1_CMD__GPIO3_IO9 0x010c 0x02bc 0x0000 0x05 0x00 +#define MX91_PAD_SD1_CMD__LPSPI2_SIN 0x010c 0x02bc 0x0440 0x03 0x01 + +#define MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x0110 0x02c0 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 0x0110 0x02c0 0x0394 0x04 0x01 +#define MX91_PAD_SD1_DATA0__GPIO3_IO10 0x0110 0x02c0 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA0__LPSPI2_PCS0 0x0110 0x02c0 0x0434 0x03 0x01 + +#define MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x0114 0x02c4 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 0x0114 0x02c4 0x0398 0x04 0x01 +#define MX91_PAD_SD1_DATA1__GPIO3_IO11 0x0114 0x02c4 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT 0x0114 0x02c4 0x0000 0x06 0x00 +#define MX91_PAD_SD1_DATA1__LPSPI2_SOUT 0x0114 0x02c4 0x0444 0x03 0x01 + +#define MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x0118 0x02c8 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 0x0118 0x02c8 0x0000 0x04 0x00 +#define MX91_PAD_SD1_DATA2__GPIO3_IO12 0x0118 0x02c8 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY 0x0118 0x02c8 0x0000 0x06 0x00 +#define MX91_PAD_SD1_DATA2__LPSPI2_PCS1 0x0118 0x02c8 0x0438 0x03 0x00 + +#define MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x011c 0x02cc 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x011c 0x02cc 0x0000 0x01 0x00 +#define MX91_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 0x011c 0x02cc 0x039c 0x04 0x01 +#define MX91_PAD_SD1_DATA3__GPIO3_IO13 0x011c 0x02cc 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA3__LPSPI1_PCS1 0x011c 0x02cc 0x0424 0x03 0x00 + +#define MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x0120 0x02d0 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA4__FLEXSPI1_A_DATA4 0x0120 0x02d0 0x0000 0x01 0x00 +#define MX91_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 0x0120 0x02d0 0x03a0 0x04 0x01 +#define MX91_PAD_SD1_DATA4__GPIO3_IO14 0x0120 0x02d0 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA4__LPSPI1_PCS0 0x0120 0x02d0 0x0420 0x03 0x00 + +#define MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x0124 0x02d4 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA5__FLEXSPI1_A_DATA5 0x0124 0x02d4 0x0000 0x01 0x00 +#define MX91_PAD_SD1_DATA5__USDHC1_RESET_B 0x0124 0x02d4 0x0000 0x02 0x00 +#define MX91_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 0x0124 0x02d4 0x03a4 0x04 0x01 +#define MX91_PAD_SD1_DATA5__GPIO3_IO15 0x0124 0x02d4 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA5__LPSPI1_SIN 0x0124 0x02d4 0x042c 0x03 0x00 + +#define MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x0128 0x02d8 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA6__FLEXSPI1_A_DATA6 0x0128 0x02d8 0x0000 0x01 0x00 +#define MX91_PAD_SD1_DATA6__USDHC1_CD_B 0x0128 0x02d8 0x0000 0x02 0x00 +#define MX91_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 0x0128 0x02d8 0x03a8 0x04 0x01 +#define MX91_PAD_SD1_DATA6__GPIO3_IO16 0x0128 0x02d8 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA6__LPSPI1_SCK 0x0128 0x02d8 0x0428 0x03 0x00 + +#define MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x012c 0x02dc 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA7__FLEXSPI1_A_DATA7 0x012c 0x02dc 0x0000 0x01 0x00 +#define MX91_PAD_SD1_DATA7__USDHC1_WP 0x012c 0x02dc 0x0000 0x02 0x00 +#define MX91_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 0x012c 0x02dc 0x03ac 0x04 0x01 +#define MX91_PAD_SD1_DATA7__GPIO3_IO17 0x012c 0x02dc 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA7__LPSPI1_SOUT 0x012c 0x02dc 0x0430 0x03 0x00 + +#define MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x0130 0x02e0 0x0000 0x00 0x00 +#define MX91_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x0130 0x02e0 0x0000 0x01 0x00 +#define MX91_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 0x0130 0x02e0 0x03b0 0x04 0x01 +#define MX91_PAD_SD1_STROBE__GPIO3_IO18 0x0130 0x02e0 0x0000 0x05 0x00 + +#define MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x0134 0x02e4 0x0000 0x00 0x00 +#define MX91_PAD_SD2_VSELECT__USDHC2_WP 0x0134 0x02e4 0x0000 0x01 0x00 +#define MX91_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0134 0x02e4 0x0450 0x02 0x01 +#define MX91_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 0x0134 0x02e4 0x0000 0x04 0x00 +#define MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x0134 0x02e4 0x0000 0x05 0x00 +#define MX91_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 0x0134 0x02e4 0x0368 0x06 0x00 + +#define MX91_PAD_SD3_CLK__USDHC3_CLK 0x0138 0x02e8 0x04e8 0x00 0x01 +#define MX91_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x0138 0x02e8 0x0000 0x01 0x00 +#define MX91_PAD_SD3_CLK__LPUART1_CTS_B 0x0138 0x02e8 0x0454 0x02 0x00 +#define MX91_PAD_SD3_CLK__FLEXIO1_FLEXIO20 0x0138 0x02e8 0x03b4 0x04 0x01 +#define MX91_PAD_SD3_CLK__GPIO3_IO20 0x0138 0x02e8 0x0000 0x05 0x00 + +#define MX91_PAD_SD3_CMD__USDHC3_CMD 0x013c 0x02ec 0x04ec 0x00 0x01 +#define MX91_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x013c 0x02ec 0x0000 0x01 0x00 +#define MX91_PAD_SD3_CMD__LPUART1_RTS_B 0x013c 0x02ec 0x0000 0x02 0x00 +#define MX91_PAD_SD3_CMD__FLEXIO1_FLEXIO21 0x013c 0x02ec 0x0000 0x04 0x00 +#define MX91_PAD_SD3_CMD__GPIO3_IO21 0x013c 0x02ec 0x0000 0x05 0x00 + +#define MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x0140 0x02f0 0x04f0 0x00 0x01 +#define MX91_PAD_SD3_DATA0__FLEXSPI1_A_DATA0 0x0140 0x02f0 0x0000 0x01 0x00 +#define MX91_PAD_SD3_DATA0__LPUART2_CTS_B 0x0140 0x02f0 0x0460 0x02 0x00 +#define MX91_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 0x0140 0x02f0 0x03b8 0x04 0x01 +#define MX91_PAD_SD3_DATA0__GPIO3_IO22 0x0140 0x02f0 0x0000 0x05 0x00 + +#define MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x0144 0x02f4 0x04f4 0x00 0x01 +#define MX91_PAD_SD3_DATA1__FLEXSPI1_A_DATA1 0x0144 0x02f4 0x0000 0x01 0x00 +#define MX91_PAD_SD3_DATA1__LPUART2_RTS_B 0x0144 0x02f4 0x0000 0x02 0x00 +#define MX91_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 0x0144 0x02f4 0x03bc 0x04 0x01 +#define MX91_PAD_SD3_DATA1__GPIO3_IO23 0x0144 0x02f4 0x0000 0x05 0x00 + +#define MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x0148 0x02f8 0x04f8 0x00 0x01 +#define MX91_PAD_SD3_DATA2__LPI2C4_SDA 0x0148 0x02f8 0x03fc 0x02 0x01 +#define MX91_PAD_SD3_DATA2__FLEXSPI1_A_DATA2 0x0148 0x02f8 0x0000 0x01 0x00 +#define MX91_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 0x0148 0x02f8 0x03c0 0x04 0x01 +#define MX91_PAD_SD3_DATA2__GPIO3_IO24 0x0148 0x02f8 0x0000 0x05 0x00 + +#define MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x014c 0x02fc 0x04fc 0x00 0x01 +#define MX91_PAD_SD3_DATA3__FLEXSPI1_A_DATA3 0x014c 0x02fc 0x0000 0x01 0x00 +#define MX91_PAD_SD3_DATA3__LPI2C4_SCL 0x014c 0x02fc 0x03f8 0x02 0x01 +#define MX91_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 0x014c 0x02fc 0x03c4 0x04 0x01 +#define MX91_PAD_SD3_DATA3__GPIO3_IO25 0x014c 0x02fc 0x0000 0x05 0x00 + +#define MX91_PAD_SD2_CD_B__USDHC2_CD_B 0x0150 0x0300 0x0000 0x00 0x00 +#define MX91_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN 0x0150 0x0300 0x0000 0x01 0x00 +#define MX91_PAD_SD2_CD_B__I3C2_SCL 0x0150 0x0300 0x03cc 0x02 0x01 +#define MX91_PAD_SD2_CD_B__FLEXIO1_FLEXIO0 0x0150 0x0300 0x036c 0x04 0x01 +#define MX91_PAD_SD2_CD_B__GPIO3_IO0 0x0150 0x0300 0x0000 0x05 0x00 +#define MX91_PAD_SD2_CD_B__LPI2C1_SCL 0x0150 0x0300 0x03e0 0x03 0x01 + +#define MX91_PAD_SD2_CLK__USDHC2_CLK 0x0154 0x0304 0x0000 0x00 0x00 +#define MX91_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT 0x0154 0x0304 0x0000 0x01 0x00 +#define MX91_PAD_SD2_CLK__I2C1_SDA 0x0154 0x0304 0x0000 0x03 0x00 +#define MX91_PAD_SD2_CLK__I3C2_SDA 0x0154 0x0304 0x03d0 0x02 0x01 +#define MX91_PAD_SD2_CLK__FLEXIO1_FLEXIO1 0x0154 0x0304 0x0370 0x04 0x01 +#define MX91_PAD_SD2_CLK__GPIO3_IO1 0x0154 0x0304 0x0000 0x05 0x00 +#define MX91_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0154 0x0304 0x0000 0x06 0x00 +#define MX91_PAD_SD2_CLK__LPI2C1_SDA 0x0154 0x0304 0x03e4 0x03 0x01 + +#define MX91_PAD_SD2_CMD__USDHC2_CMD 0x0158 0x0308 0x0000 0x00 0x00 +#define MX91_PAD_SD2_CMD__ENET2_1588_EVENT0_IN 0x0158 0x0308 0x0000 0x01 0x00 +#define MX91_PAD_SD2_CMD__I3C2_PUR 0x0158 0x0308 0x0000 0x02 0x00 +#define MX91_PAD_SD2_CMD__I3C2_PUR_B 0x0158 0x0308 0x0000 0x03 0x00 +#define MX91_PAD_SD2_CMD__FLEXIO1_FLEXIO2 0x0158 0x0308 0x0374 0x04 0x01 +#define MX91_PAD_SD2_CMD__GPIO3_IO2 0x0158 0x0308 0x0000 0x05 0x00 +#define MX91_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x0158 0x0308 0x0000 0x06 0x00 + +#define MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x015c 0x030c 0x0000 0x00 0x00 +#define MX91_PAD_SD2_DATA0__ENET2_1588_EVENT0_OUT 0x015c 0x030c 0x0000 0x01 0x00 +#define MX91_PAD_SD2_DATA0__CAN2_TX 0x015c 0x030c 0x0000 0x02 0x00 +#define MX91_PAD_SD2_DATA0__FLEXIO1_FLEXIO3 0x015c 0x030c 0x0378 0x04 0x01 +#define MX91_PAD_SD2_DATA0__GPIO3_IO3 0x015c 0x030c 0x0000 0x05 0x00 +#define MX91_PAD_SD2_DATA0__LPUART1_TX 0x015c 0x030c 0x045c 0x03 0x00 +#define MX91_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x015c 0x030c 0x0000 0x06 0x00 + +#define MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x0160 0x0310 0x0000 0x00 0x00 +#define MX91_PAD_SD2_DATA1__ENET2_1588_EVENT1_IN 0x0160 0x0310 0x0000 0x01 0x00 +#define MX91_PAD_SD2_DATA1__CAN2_RX 0x0160 0x0310 0x0364 0x02 0x03 +#define MX91_PAD_SD2_DATA1__FLEXIO1_FLEXIO4 0x0160 0x0310 0x037c 0x04 0x01 +#define MX91_PAD_SD2_DATA1__GPIO3_IO4 0x0160 0x0310 0x0000 0x05 0x00 +#define MX91_PAD_SD2_DATA1__LPUART1_RX 0x0160 0x0310 0x0458 0x03 0x00 +#define MX91_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x0160 0x0310 0x0000 0x06 0x00 + +#define MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x0164 0x0314 0x0000 0x00 0x00 +#define MX91_PAD_SD2_DATA2__ENET2_1588_EVENT1_OUT 0x0164 0x0314 0x0000 0x01 0x00 +#define MX91_PAD_SD2_DATA2__MQS2_RIGHT 0x0164 0x0314 0x0000 0x02 0x00 +#define MX91_PAD_SD2_DATA2__FLEXIO1_FLEXIO5 0x0164 0x0314 0x0380 0x04 0x01 +#define MX91_PAD_SD2_DATA2__GPIO3_IO5 0x0164 0x0314 0x0000 0x05 0x00 +#define MX91_PAD_SD2_DATA2__LPUART2_TX 0x0164 0x0314 0x0468 0x03 0x00 +#define MX91_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0164 0x0314 0x0000 0x06 0x00 + +#define MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x0168 0x0318 0x0000 0x00 0x00 +#define MX91_PAD_SD2_DATA3__LPTMR2_ALT1 0x0168 0x0318 0x0448 0x01 0x01 +#define MX91_PAD_SD2_DATA3__MQS2_LEFT 0x0168 0x0318 0x0000 0x02 0x00 +#define MX91_PAD_SD2_DATA3__FLEXIO1_FLEXIO6 0x0168 0x0318 0x0384 0x04 0x01 +#define MX91_PAD_SD2_DATA3__GPIO3_IO6 0x0168 0x0318 0x0000 0x05 0x00 +#define MX91_PAD_SD2_DATA3__LPUART2_RX 0x0168 0x0318 0x0464 0x03 0x00 +#define MX91_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0168 0x0318 0x0000 0x06 0x00 + +#define MX91_PAD_SD2_RESET_B__USDHC2_RESET_B 0x016c 0x031c 0x0000 0x00 0x00 +#define MX91_PAD_SD2_RESET_B__LPTMR2_ALT2 0x016c 0x031c 0x044c 0x01 0x01 +#define MX91_PAD_SD2_RESET_B__FLEXIO1_FLEXIO7 0x016c 0x031c 0x0388 0x04 0x01 +#define MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x016c 0x031c 0x0000 0x05 0x00 +#define MX91_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x016c 0x031c 0x0000 0x06 0x00 + +#define MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x0170 0x0320 0x03e0 0x00 0x02 +#define MX91_PAD_I2C1_SCL__I3C1_SCL 0x0170 0x0320 0x0000 0x01 0x00 +#define MX91_PAD_I2C1_SCL__LPUART1_DCB_B 0x0170 0x0320 0x0000 0x02 0x00 +#define MX91_PAD_I2C1_SCL__TPM2_CH0 0x0170 0x0320 0x0000 0x03 0x00 +#define MX91_PAD_I2C1_SCL__GPIO1_IO0 0x0170 0x0320 0x0000 0x05 0x00 + +#define MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x0174 0x0324 0x03e4 0x00 0x02 +#define MX91_PAD_I2C1_SDA__I3C1_SDA 0x0174 0x0324 0x0000 0x01 0x00 +#define MX91_PAD_I2C1_SDA__LPUART1_RIN_B 0x0174 0x0324 0x0000 0x02 0x00 +#define MX91_PAD_I2C1_SDA__TPM2_CH1 0x0174 0x0324 0x0000 0x03 0x00 +#define MX91_PAD_I2C1_SDA__GPIO1_IO1 0x0174 0x0324 0x0000 0x05 0x00 + +#define MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x0178 0x0328 0x03e8 0x00 0x01 +#define MX91_PAD_I2C2_SCL__I3C1_PUR 0x0178 0x0328 0x0000 0x01 0x00 +#define MX91_PAD_I2C2_SCL__LPUART2_DCB_B 0x0178 0x0328 0x0000 0x02 0x00 +#define MX91_PAD_I2C2_SCL__TPM2_CH2 0x0178 0x0328 0x0000 0x03 0x00 +#define MX91_PAD_I2C2_SCL__SAI1_RX_SYNC 0x0178 0x0328 0x0000 0x04 0x00 +#define MX91_PAD_I2C2_SCL__GPIO1_IO2 0x0178 0x0328 0x0000 0x05 0x00 +#define MX91_PAD_I2C2_SCL__I3C1_PUR_B 0x0178 0x0328 0x0000 0x06 0x00 + +#define MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x017c 0x032c 0x03ec 0x00 0x01 +#define MX91_PAD_I2C2_SDA__LPUART2_RIN_B 0x017c 0x032c 0x0000 0x02 0x00 +#define MX91_PAD_I2C2_SDA__TPM2_CH3 0x017c 0x032c 0x0000 0x03 0x00 +#define MX91_PAD_I2C2_SDA__SAI1_RX_BCLK 0x017c 0x032c 0x0000 0x04 0x00 +#define MX91_PAD_I2C2_SDA__GPIO1_IO3 0x017c 0x032c 0x0000 0x05 0x00 + +#define MX91_PAD_UART1_RXD__LPUART1_RX 0x0180 0x0330 0x0458 0x00 0x01 +#define MX91_PAD_UART1_RXD__ELE_UART_RX 0x0180 0x0330 0x0000 0x01 0x00 +#define MX91_PAD_UART1_RXD__LPSPI2_SIN 0x0180 0x0330 0x0440 0x02 0x02 +#define MX91_PAD_UART1_RXD__TPM1_CH0 0x0180 0x0330 0x0000 0x03 0x00 +#define MX91_PAD_UART1_RXD__GPIO1_IO4 0x0180 0x0330 0x0000 0x05 0x00 + +#define MX91_PAD_UART1_TXD__LPUART1_TX 0x0184 0x0334 0x045c 0x00 0x01 +#define MX91_PAD_UART1_TXD__ELE_UART_TX 0x0184 0x0334 0x0000 0x01 0x00 +#define MX91_PAD_UART1_TXD__LPSPI2_PCS0 0x0184 0x0334 0x0434 0x02 0x02 +#define MX91_PAD_UART1_TXD__TPM1_CH1 0x0184 0x0334 0x0000 0x03 0x00 +#define MX91_PAD_UART1_TXD__GPIO1_IO5 0x0184 0x0334 0x0000 0x05 0x00 + +#define MX91_PAD_UART2_RXD__LPUART2_RX 0x0188 0x0338 0x0464 0x00 0x01 +#define MX91_PAD_UART2_RXD__LPUART1_CTS_B 0x0188 0x0338 0x0454 0x01 0x01 +#define MX91_PAD_UART2_RXD__LPSPI2_SOUT 0x0188 0x0338 0x0444 0x02 0x02 +#define MX91_PAD_UART2_RXD__TPM1_CH2 0x0188 0x0338 0x0000 0x03 0x00 +#define MX91_PAD_UART2_RXD__SAI1_MCLK 0x0188 0x0338 0x04d4 0x04 0x00 +#define MX91_PAD_UART2_RXD__GPIO1_IO6 0x0188 0x0338 0x0000 0x05 0x00 + +#define MX91_PAD_UART2_TXD__LPUART2_TX 0x018c 0x033c 0x0468 0x00 0x01 +#define MX91_PAD_UART2_TXD__LPUART1_RTS_B 0x018c 0x033c 0x0000 0x01 0x00 +#define MX91_PAD_UART2_TXD__LPSPI2_SCK 0x018c 0x033c 0x043c 0x02 0x02 +#define MX91_PAD_UART2_TXD__TPM1_CH3 0x018c 0x033c 0x0000 0x03 0x00 +#define MX91_PAD_UART2_TXD__GPIO1_IO7 0x018c 0x033c 0x0000 0x05 0x00 +#define MX91_PAD_UART2_TXD__SAI3_TX_SYNC 0x018c 0x033c 0x04e0 0x07 0x02 + +#define MX91_PAD_PDM_CLK__PDM_CLK 0x0190 0x0340 0x0000 0x00 0x00 +#define MX91_PAD_PDM_CLK__MQS1_LEFT 0x0190 0x0340 0x0000 0x01 0x00 +#define MX91_PAD_PDM_CLK__LPTMR1_ALT1 0x0190 0x0340 0x0000 0x04 0x00 +#define MX91_PAD_PDM_CLK__GPIO1_IO8 0x0190 0x0340 0x0000 0x05 0x00 +#define MX91_PAD_PDM_CLK__CAN1_TX 0x0190 0x0340 0x0000 0x06 0x00 + +#define MX91_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 0x0194 0x0344 0x04c4 0x00 0x02 +#define MX91_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x0194 0x0344 0x0000 0x01 0x00 +#define MX91_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x0194 0x0344 0x0424 0x02 0x01 +#define MX91_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x0194 0x0344 0x0000 0x03 0x00 +#define MX91_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x0194 0x0344 0x0000 0x04 0x00 +#define MX91_PAD_PDM_BIT_STREAM0__GPIO1_IO9 0x0194 0x0344 0x0000 0x05 0x00 +#define MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x0194 0x0344 0x0360 0x06 0x01 + +#define MX91_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 0x0198 0x0348 0x04c8 0x00 0x02 +#define MX91_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x0198 0x0348 0x0438 0x02 0x01 +#define MX91_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x0198 0x0348 0x0000 0x03 0x00 +#define MX91_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 0x0198 0x0348 0x0000 0x04 0x00 +#define MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x0198 0x0348 0x0000 0x05 0x00 +#define MX91_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 0x0198 0x0348 0x0368 0x06 0x01 + +#define MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x019c 0x034c 0x0000 0x00 0x00 +#define MX91_PAD_SAI1_TXFS__SAI1_TX_DATA1 0x019c 0x034c 0x0000 0x01 0x00 +#define MX91_PAD_SAI1_TXFS__LPSPI1_PCS0 0x019c 0x034c 0x0420 0x02 0x01 +#define MX91_PAD_SAI1_TXFS__LPUART2_DTR_B 0x019c 0x034c 0x0000 0x03 0x00 +#define MX91_PAD_SAI1_TXFS__MQS1_LEFT 0x019c 0x034c 0x0000 0x04 0x00 +#define MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x019c 0x034c 0x0000 0x05 0x00 + +#define MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x01a0 0x0350 0x0000 0x00 0x00 +#define MX91_PAD_SAI1_TXC__LPUART2_CTS_B 0x01a0 0x0350 0x0460 0x01 0x01 +#define MX91_PAD_SAI1_TXC__LPSPI1_SIN 0x01a0 0x0350 0x042c 0x02 0x01 +#define MX91_PAD_SAI1_TXC__LPUART1_DSR_B 0x01a0 0x0350 0x0000 0x03 0x00 +#define MX91_PAD_SAI1_TXC__CAN1_RX 0x01a0 0x0350 0x0360 0x04 0x02 +#define MX91_PAD_SAI1_TXC__GPIO1_IO12 0x01a0 0x0350 0x0000 0x05 0x00 + +#define MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x01a4 0x0354 0x0000 0x00 0x00 +#define MX91_PAD_SAI1_TXD0__LPUART2_RTS_B 0x01a4 0x0354 0x0000 0x01 0x00 +#define MX91_PAD_SAI1_TXD0__LPSPI1_SCK 0x01a4 0x0354 0x0428 0x02 0x01 +#define MX91_PAD_SAI1_TXD0__LPUART1_DTR_B 0x01a4 0x0354 0x0000 0x03 0x00 +#define MX91_PAD_SAI1_TXD0__CAN1_TX 0x01a4 0x0354 0x0000 0x04 0x00 +#define MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x01a4 0x0354 0x0000 0x05 0x00 +#define MX91_PAD_SAI1_TXD0__SAI1_MCLK 0x01a4 0x0354 0x04d4 0x06 0x01 + +#define MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x01a8 0x0358 0x0000 0x00 0x00 +#define MX91_PAD_SAI1_RXD0__SAI1_MCLK 0x01a8 0x0358 0x04d4 0x01 0x02 +#define MX91_PAD_SAI1_RXD0__LPSPI1_SOUT 0x01a8 0x0358 0x0430 0x02 0x01 +#define MX91_PAD_SAI1_RXD0__LPUART2_DSR_B 0x01a8 0x0358 0x0000 0x03 0x00 +#define MX91_PAD_SAI1_RXD0__MQS1_RIGHT 0x01a8 0x0358 0x0000 0x04 0x00 +#define MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x01a8 0x0358 0x0000 0x05 0x00 + +#define MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x01ac 0x035c 0x0000 0x00 0x00 +#define MX91_PAD_WDOG_ANY__GPIO1_IO15 0x01ac 0x035c 0x0000 0x05 0x00 +#endif /* __DTS_IMX91_PINFUNC_H */ diff --git a/arch/arm64/boot/dts/freescale/imx91-tqma9131-mba91xxca.dts b/arch/arm64/boot/dts/freescale/imx91-tqma9131-mba91xxca.dts new file mode 100644 index 000000000000..5c430e6fca65 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-tqma9131-mba91xxca.dts @@ -0,0 +1,739 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2022-2025 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + * Author: Alexander Stein + */ +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/net/ti-dp83867.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/usb/pd.h> +#include "imx91-tqma9131.dtsi" + +/{ + model = "TQ-Systems i.MX91 TQMa91xxLA/TQMa91xxCA on MBa91xxCA starter kit"; + compatible = "tq,imx91-tqma9131-mba91xxca", "tq,imx91-tqma9131", "fsl,imx91"; + chassis-type = "embedded"; + + chosen { + stdout-path = &lpuart1; + }; + + aliases { + eeprom0 = &eeprom0; + ethernet0 = &eqos; + ethernet1 = &fec; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &lpuart1; + serial1 = &lpuart2; + rtc0 = &pcf85063; + rtc1 = &bbnsm_rtc; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&tpm2 2 5000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_12v0>; + enable-gpios = <&expander2 2 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + display: display { + /* + * Display is not fixed, so compatible has to be added from + * DT overlay + */ + power-supply = <®_3v3>; + enable-gpios = <&expander2 1 GPIO_ACTIVE_HIGH>; + backlight = <&backlight>; + status = "disabled"; + + port { + panel_in: endpoint { + }; + }; + }; + + fan0: gpio-fan { + compatible = "gpio-fan"; + gpios = <&expander2 4 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0>, <10000 1>; + fan-supply = <®_12v0>; + #cooling-cells = <2>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + switch-a { + label = "switcha"; + linux,code = <BTN_0>; + gpios = <&expander0 6 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + switch-b { + label = "switchb"; + linux,code = <BTN_1>; + gpios = <&expander0 7 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-1 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + gpios = <&expander2 6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-2 { + color = <LED_COLOR_ID_AMBER>; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&expander2 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>; + }; + + lvds_encoder: lvds-encoder { + compatible = "ti,sn75lvds83", "lvds-encoder"; + powerdown-gpios = <&expander2 3 GPIO_ACTIVE_LOW>; + power-supply = <®_3v3>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_encoder_input: endpoint { + }; + }; + + port@1 { + reg = <1>; + + lvds_encoder_output: endpoint { + }; + }; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_MB"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "V_5V0_MB"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_12v0: regulator-12v0 { + compatible = "regulator-fixed"; + regulator-name = "V_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&expander1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_mpcie_1v5: regulator-mpcie-1v5 { + compatible = "regulator-fixed"; + regulator-name = "V_1V5_MPCIE"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&expander0 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_mpcie_3v3: regulator-mpcie-3v3 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_MPCIE"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&expander0 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; +}; + +&adc1 { + status = "okay"; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy_eqos>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy_eqos: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos_phy>; + reset-gpios = <&expander1 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + enet-phy-lane-no-swap; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy_fec>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy_fec: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_phy>; + reset-gpios = <&expander1 1 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + enet-phy-lane-no-swap; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_3v3>; + status = "okay"; +}; + +&gpio1 { + gpio-line-names = + /* 00 */ "", "", "", "PMIC_IRQ#", + /* 04 */ "", "", "", "", + /* 08 */ "", "", "USB_C_ALERT#", "BM2_LCD_INT#", + /* 12 */ "PEX_INT#", "", "RTC_EVENT#", "", + /* 16 */ "", "", "", "", + /* 20 */ "", "", "", "", + /* 24 */ "", "", "", "", + /* 28 */ "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + /* 00 */ "", "", "", "", + /* 04 */ "", "", "", "", + /* 08 */ "", "", "", "", + /* 12 */ "", "", "", "", + /* 16 */ "", "", "", "", + /* 20 */ "", "", "", "", + /* 24 */ "", "", "", "", + /* 28 */ "", "", "", ""; +}; + +&gpio3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_jtag>; + gpio-line-names = + /* 00 */ "SD2_CD#", "", "", "", + /* 04 */ "", "", "", "SD2_RST#", + /* 08 */ "", "", "", "", + /* 12 */ "", "", "", "", + /* 16 */ "", "", "", "", + /* 20 */ "", "", "", "", + /* 24 */ "", "", "ENET1_INT#", "ENET2_INT#", + /* 28 */ "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* 00 */ "", "", "", "", + /* 04 */ "", "", "", "", + /* 08 */ "", "", "", "", + /* 12 */ "", "", "", "", + /* 16 */ "", "", "", "", + /* 20 */ "", "", "", "", + /* 24 */ "", "", "", "", + /* 28 */ "", "", "", ""; +}; + +&lpi2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3>; + status = "okay"; + + temperature-sensor@1c { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x1c>; + }; + + ptn5110: usb-typec@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; + + connector { + compatible = "usb-c-connector"; + label = "X17"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + typec-power-opmode = "default"; + pd-disable; + self-powered; + + port { + typec_con_hs: endpoint { + remote-endpoint = <&typec_hs>; + }; + }; + }; + }; + + eeprom2: eeprom@54 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x54>; + pagesize = <16>; + vcc-supply = <®_3v3>; + }; + + expander0: gpio@70 { + compatible = "nxp,pca9538"; + reg = <0x70>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pexp_irq>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_3v3>; + gpio-line-names = "TEMP_EVENT_MOD#", "MPCIE_WAKE#", + "MPCIE_1V5_EN", "MPCIE_3V3_EN", + "MPCIE_PERST#", "MPCIE_WDISABLE#", + "BUTTON_A#", "BUTTON_B#"; + + temp-event-mod-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_LOW>; + input; + line-name = "TEMP_EVENT_MOD#"; + }; + + mpcie-wake-hog { + gpio-hog; + gpios = <1 GPIO_ACTIVE_LOW>; + input; + line-name = "MPCIE_WAKE#"; + }; + + /* + * Controls the mPCIE slot reset which is low active as + * reset signal. The output-low states, the signal is + * inactive, e.g. not in reset + */ + mpcie_rst_hog: mpcie-rst-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + output-low; + line-name = "MPCIE_PERST#"; + }; + + /* + * Controls the mPCIE slot WDISABLE pin which is low active + * as disable signal. The output-low states, the signal is + * inactive, e.g. not disabled + */ + mpcie_wdisable_hog: mpcie-wdisable-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + output-low; + line-name = "MPCIE_WDISABLE#"; + }; + }; + + expander1: gpio@71 { + compatible = "nxp,pca9538"; + reg = <0x71>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_3v3>; + gpio-line-names = "ENET1_RESET#", "ENET2_RESET#", + "USB_RESET#", "", + "WLAN_PD#", "WLAN_W_DISABLE#", + "WLAN_PERST#", "12V_EN"; + + /* + * Controls the WiFi card PD pin which is low active + * as power down signal. The output-low states, the signal + * is inactive, e.g. not power down + */ + wlan-pd-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + output-low; + line-name = "WLAN_PD#"; + }; + + /* + * Controls the WiFi card disable pin which is low active + * as disable signal. The output-low states, the signal + * is inactive, e.g. not disabled + */ + wlan-wdisable-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + output-low; + line-name = "WLAN_W_DISABLE#"; + }; + + /* + * Controls the WiFi card reset pin which is low active + * as reset signal. The output-low states, the signal + * is inactive, e.g. not in reset + */ + wlan-perst-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_LOW>; + output-low; + line-name = "WLAN_PERST#"; + }; + }; + + expander2: gpio@72 { + compatible = "nxp,pca9538"; + reg = <0x72>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_3v3>; + gpio-line-names = "LCD_RESET#", "LCD_PWR_EN", + "LCD_BLT_EN", "LVDS_SHDN#", + "FAN_PWR_EN", "", + "USER_LED1", "USER_LED2"; + }; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&pcf85063 { + /* RTC_EVENT# from SoM is connected on mainboard */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcf85063>; + interrupt-parent = <&gpio1>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; +}; + +&se97_som { + /* TEMP_EVENT# from SoM is connected on mainboard */ + interrupt-parent = <&expander0>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +}; + +&tpm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm2>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + status = "okay"; + + port { + typec_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&usbotg2 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + disable-over-current; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb424,2517"; + reg = <1>; + reset-gpios = <&expander1 2 GPIO_ACTIVE_LOW>; + vdd-supply = <®_3v3>; + }; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + no-sdio; + no-mmc; + disable-wp; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = /* PD | FSEL_2 | DSE X4 */ + <MX91_PAD_ENET1_MDC__ENET1_MDC 0x51e>, + /* SION | HYS | FSEL_2 | DSE X4 */ + <MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000111e>, + /* HYS | FSEL_0 | DSE no drive */ + <MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x1000>, + <MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x1000>, + <MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x1000>, + <MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x1000>, + <MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x1000>, + /* HYS | PD | FSEL_0 | DSE no drive */ + <MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x1400>, + /* PD | FSEL_2 | DSE X4 */ + <MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e>, + <MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x51e>, + <MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x51e>, + <MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x51e>, + <MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x51e>, + /* PD | FSEL_3 | DSE X3 */ + <MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e>; + }; + + pinctrl_eqos_phy: eqosphygrp { + fsl,pins = /* HYS | FSEL_0 | DSE no drive */ + <MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x1000>; + }; + + pinctrl_fec: fecgrp { + fsl,pins = /* PD | FSEL_2 | DSE X4 */ + <MX91_PAD_ENET2_MDC__ENET2_MDC 0x51e>, + /* SION | HYS | FSEL_2 | DSE X4 */ + <MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x4000111e>, + /* HYS | FSEL_0 | DSE no drive */ + <MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x1000>, + <MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x1000>, + <MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x1000>, + <MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x1000>, + <MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x1000>, + /* HYS | PD | FSEL_0 | DSE no drive */ + <MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x1400>, + /* PD | FSEL_2 | DSE X4 */ + <MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x51e>, + <MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x51e>, + <MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x51e>, + <MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x51e>, + <MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x51e>, + /* PD | FSEL_3 | DSE X3 */ + <MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x58e>; + }; + + pinctrl_fec_phy: fecphygrp { + fsl,pins = /* HYS | FSEL_0 | DSE no drive */ + <MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x1000>; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = /* HYS | PU | FSEL_0 | DSE no drive */ + <MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x1200>, + /* PU | FSEL_3 | DSE X4 */ + <MX91_PAD_PDM_CLK__CAN1_TX 0x039e>; + }; + + pinctrl_jtag: jtaggrp { + fsl,pins = <MX91_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x051e>, + <MX91_PAD_DAP_TDI__JTAG_MUX_TDI 0x1200>, + <MX91_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x031e>, + <MX91_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x1200>; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = /* SION | HYS | OD | FSEL_3 | DSE X4 */ + <MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x4000199e>, + <MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x4000199e>; + }; + + pinctrl_pcf85063: pcf85063grp { + fsl,pins = <MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x1000>; + }; + + pinctrl_pexp_irq: pexpirqgrp { + fsl,pins = /* HYS | FSEL_0 | No DSE */ + <MX91_PAD_SAI1_TXC__GPIO1_IO12 0x1000>; + }; + + pinctrl_rgbdisp: rgbdispgrp { + fsl,pins = <MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x31e>, + <MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x31e>, + <MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x31e>, + <MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x31e>, + <MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0 0x31e>, + <MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1 0x31e>, + <MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2 0x31e>, + <MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3 0x31e>, + <MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4 0x31e>, + <MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5 0x31e>, + <MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6 0x31e>, + <MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7 0x31e>, + <MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8 0x31e>, + <MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9 0x31e>, + <MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x31e>, + <MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x31e>, + <MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x31e>, + <MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x31e>, + <MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x31e>, + <MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x31e>, + <MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x31e>, + <MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x31e>, + <MX91_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x31e>, + <MX91_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x31e>, + <MX91_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x31e>, + <MX91_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x31e>, + <MX91_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x31e>, + <MX91_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x31e>; + }; + + pinctrl_touch: touchgrp { + fsl,pins = /* HYS | FSEL_0 | No DSE */ + <MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x1000>; + }; + + pinctrl_tpm2: tpm2grp { + fsl,pins = <MX91_PAD_I2C2_SCL__TPM2_CH2 0x57e>; + }; + + pinctrl_typec: typecgrp { + fsl,pins = /* HYS | FSEL_0 | No DSE */ + <MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x1000>; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = /* HYS | FSEL_0 | No DSE */ + <MX91_PAD_UART1_RXD__LPUART1_RX 0x1000>, + /* FSEL_2 | DSE X4 */ + <MX91_PAD_UART1_TXD__LPUART1_TX 0x011e>; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = /* HYS | FSEL_0 | No DSE */ + <MX91_PAD_UART2_RXD__LPUART2_RX 0x1000>, + /* FSEL_2 | DSE X4 */ + <MX91_PAD_UART2_TXD__LPUART2_TX 0x011e>, + /* FSEL_2 | DSE X4 */ + <MX91_PAD_SAI1_TXD0__LPUART2_RTS_B 0x011e>; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = /* HYS | FSEL_0 | No DSE */ + <MX91_PAD_SD2_CD_B__GPIO3_IO0 0x1000>; + }; + + /* enable SION for data and cmd pad due to ERR052021 */ + pinctrl_usdhc2_hs: usdhc2hsgrp { + fsl,pins = /* PD | FSEL_3 | DSE X5 */ + <MX91_PAD_SD2_CLK__USDHC2_CLK 0x05be>, + /* HYS | PU | FSEL_3 | DSE X4 */ + <MX91_PAD_SD2_CMD__USDHC2_CMD 0x4000139e>, + /* HYS | PU | FSEL_3 | DSE X3 */ + <MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e>, + <MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e>, + <MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e>, + <MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e>, + /* FSEL_2 | DSE X3 */ + <MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x010e>; + }; + + /* enable SION for data and cmd pad due to ERR052021 */ + pinctrl_usdhc2_uhs: usdhc2uhsgrp { + fsl,pins = /* PD | FSEL_3 | DSE X6 */ + <MX91_PAD_SD2_CLK__USDHC2_CLK 0x05fe>, + /* HYS | PU | FSEL_3 | DSE X4 */ + <MX91_PAD_SD2_CMD__USDHC2_CMD 0x4000139e>, + <MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e>, + <MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e>, + <MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e>, + <MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e>, + /* FSEL_2 | DSE X3 */ + <MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x010e>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi b/arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi new file mode 100644 index 000000000000..5792952b7a8e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi @@ -0,0 +1,295 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2022-2025 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + * Author: Alexander Stein + */ + +#include "imx91.dtsi" + +/{ + model = "TQ-Systems i.MX91 TQMa91xxCA / TQMa91xxLA SOM"; + compatible = "tq,imx91-tqma9131", "fsl,imx91"; + + memory@80000000 { + device_type = "memory"; + /* our minimum RAM config will be 1024 MiB */ + reg = <0x00000000 0x80000000 0 0x40000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* default CMA, must not exceed assembled memory */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0 0x80000000 0 0x40000000>; + size = <0 0x10000000>; + linux,cma-default; + }; + + /* EdgeLock secure enclave */ + ele_reserved: ele-reserved@a4120000 { + compatible = "shared-dma-pool"; + reg = <0 0xa4120000 0 0x100000>; + no-map; + }; + }; + + /* SD2 RST# via PMIC SW_EN */ + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&buck4>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&adc1 { + vref-supply = <&buck5>; +}; + +&flexspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi1>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + /* + * no DQS, RXCLKSRC internal loop back, max 66 MHz + * clk framework uses CLK_DIVIDER_ROUND_CLOSEST + * selected value together with root from + * IMX91_CLK_SYS_PLL_PFD1 @ 800.000.000 Hz helps to + * respect the maximum value. + */ + spi-max-frequency = <62000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + vcc-supply = <&buck5>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; + +&lpi2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-1 = <&pinctrl_lpi2c1>; + status = "okay"; + + se97_som: temperature-sensor@1b { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x1b>; + }; + + pca9451a: pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca9451>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + /* V_0V8_SOC - hw developer guide: 0.75 .. 0.9 */ + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + /* V_DDRQ - 1.1 V for LPDDR4 */ + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + /* V_3V3 - EEPROM, RTC, ... */ + buck4: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8 - SPI NOR, eMMC, RAM VDD1... */ + buck5: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V1 - RAM VDD2*/ + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8_BBSM, fix 1.8 */ + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_0V8_ANA */ + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_SD2 - 3.3/1.8V USDHC2 io Voltage */ + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + pcf85063: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + quartz-load-femtofarads = <7000>; + }; + + eeprom0: eeprom@53 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + read-only; + vcc-supply = <&buck4>; + }; + + eeprom1: eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + vcc-supply = <&buck4>; + }; + + /* protectable identification memory (part of M24C64-D @57) */ + eeprom@5f { + compatible = "atmel,24c64d-wl"; + reg = <0x5f>; + vcc-supply = <&buck4>; + }; + + accelerometer@6a { + compatible = "st,ism330dhcx"; + reg = <0x6a>; + vdd-supply = <&buck4>; + vddio-supply = <&buck4>; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + vmmc-supply = <&buck4>; + vqmmc-supply = <&buck5>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&wdog3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_flexspi1: flexspi1grp { + fsl,pins = /* FSEL 3 | DSE X6 */ + <MX91_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x01fe>, + <MX91_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x01fe>, + /* HYS | PU | FSEL 3 | DSE X6 */ + <MX91_PAD_SD3_DATA0__FLEXSPI1_A_DATA0 0x13fe>, + <MX91_PAD_SD3_DATA1__FLEXSPI1_A_DATA1 0x13fe>, + /* HYS | FSEL 3 | DSE X6 (external PU) */ + <MX91_PAD_SD3_DATA2__FLEXSPI1_A_DATA2 0x11fe>, + <MX91_PAD_SD3_DATA3__FLEXSPI1_A_DATA3 0x11fe>; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = /* SION | OD | FSEL 3 | DSE X4 */ + <MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x4000199e>, + <MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x4000199e>; + }; + + pinctrl_pca9451: pca9451grp { + fsl,pins = /* HYS | PU */ + <MX91_PAD_I2C2_SDA__GPIO1_IO3 0x1200>; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = /* FSEL 2 | DSE X2 */ + <MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x106>; + }; + + /* enable SION for data and cmd pad due to ERR052021 */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = /* PD | FSEL 3 | DSE X5 */ + <MX91_PAD_SD1_CLK__USDHC1_CLK 0x5be>, + /* HYS | FSEL 0 | no drive */ + <MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1000>, + /* HYS | FSEL 3 | X5 */ + <MX91_PAD_SD1_CMD__USDHC1_CMD 0x400011be>, + /* HYS | FSEL 3 | X4 */ + <MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x4000119e>, + <MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x4000119e>, + <MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x4000119e>, + <MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x4000119e>, + <MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x4000119e>, + <MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x4000119e>, + <MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x4000119e>, + <MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x4000119e>; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = /* PU | FSEL 1 | DSE X4 */ + <MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx91.dtsi b/arch/arm64/boot/dts/freescale/imx91.dtsi new file mode 100644 index 000000000000..4d8300b2a7bc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +#include "imx91-pinfunc.h" +#include "imx91_93_common.dtsi" + +&clk { + compatible = "fsl,imx91-ccm"; +}; + +&ddr_pmu { + compatible = "fsl,imx91-ddr-pmu", "fsl,imx93-ddr-pmu"; +}; + +&eqos { + clocks = <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>, + <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>, + <&clk IMX91_CLK_ENET_TIMER>, + <&clk IMX91_CLK_ENET1_QOS_TSN>, + <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>; + assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>, + <&clk IMX91_CLK_ENET1_QOS_TSN>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; + assigned-clock-rates = <100000000>, <250000000>; +}; + +&fec { + clocks = <&clk IMX91_CLK_ENET2_REGULAR_GATE>, + <&clk IMX91_CLK_ENET2_REGULAR_GATE>, + <&clk IMX91_CLK_ENET_TIMER>, + <&clk IMX91_CLK_ENET2_REGULAR>, + <&clk IMX93_CLK_DUMMY>; + assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>, + <&clk IMX91_CLK_ENET2_REGULAR>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; + assigned-clock-rates = <100000000>, <250000000>; +}; + +&i3c1 { + clocks = <&clk IMX93_CLK_BUS_AON>, + <&clk IMX93_CLK_I3C1_GATE>, + <&clk IMX93_CLK_DUMMY>; +}; + +&i3c2 { + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_I3C2_GATE>, + <&clk IMX93_CLK_DUMMY>; +}; + +&iomuxc { + compatible = "fsl,imx91-iomuxc"; +}; + +&media_blk_ctrl { + compatible = "fsl,imx91-media-blk-ctrl", "syscon"; + clocks = <&clk IMX93_CLK_MEDIA_APB>, + <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_NIC_MEDIA_GATE>, + <&clk IMX93_CLK_MEDIA_DISP_PIX>, + <&clk IMX93_CLK_CAM_PIX>, + <&clk IMX93_CLK_LCDIF_GATE>, + <&clk IMX93_CLK_ISI_GATE>, + <&clk IMX93_CLK_MIPI_CSI_GATE>; + clock-names = "apb", "axi", "nic", "disp", "cam", + "lcdif", "isi", "csi"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi new file mode 100644 index 000000000000..52da571f26c4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi @@ -0,0 +1,1187 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022,2025 NXP + */ + +#include <dt-bindings/clock/imx93-clock.h> +#include <dt-bindings/dma/fsl-edma.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/fsl,imx93-power.h> +#include <dt-bindings/thermal/thermal.h> + +#include "imx93-pinfunc.h" + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + + idle-states { + entry-method = "psci"; + + cpu_pd_wait: cpu-pd-wait { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010033>; + local-timer-stop; + entry-latency-us = <10000>; + exit-latency-us = <7000>; + min-residency-us = <27000>; + wakeup-latency-us = <15000>; + }; + }; + + A55_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + }; + }; + + osc_32k: clock-osc-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "osc_32k"; + }; + + osc_24m: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + clk_ext1: clock-ext1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext1"; + }; + + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <24000000>; + arm,no-tick-in-suspend; + interrupt-parent = <&gic>; + }; + + gic: interrupt-controller@48000000 { + compatible = "arm,gic-v3"; + reg = <0 0x48000000 0 0x10000>, + <0 0x48040000 0 0xc0000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + }; + + mqs1: mqs1 { + compatible = "fsl,imx93-mqs"; + gpr = <&aonmix_ns_gpr>; + status = "disabled"; + }; + + mqs2: mqs2 { + compatible = "fsl,imx93-mqs"; + gpr = <&wakeupmix_gpr>; + status = "disabled"; + }; + + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; + clock-names = "main_clk"; + }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; + clock-names = "main_clk"; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x80000000>, + <0x28000000 0x0 0x28000000 0x10000000>; + + aips1: bus@44000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x44000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + edma1: dma-controller@44000000 { + compatible = "fsl,imx93-edma3"; + reg = <0x44000000 0x200000>; + #dma-cells = <3>; + dma-channels = <31>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, // 0: Reserved + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, // 1: CANFD1 + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, // 2: Reserved + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, // 3: GPIO1 CH0 + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, // 4: GPIO1 CH1 + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, // 5: I3C1 TO Bus + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, // 6: I3C1 From Bus + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, // 7: LPI2C1 M TX + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, // 8: LPI2C1 S TX + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, // 9: LPI2C2 M RX + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, // 10: LPI2C2 S RX + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, // 11: LPSPI1 TX + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, // 12: LPSPI1 RX + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, // 13: LPSPI2 TX + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, // 14: LPSPI2 RX + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, // 15: LPTMR1 + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, // 16: LPUART1 TX + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, // 17: LPUART1 RX + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, // 18: LPUART2 TX + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, // 19: LPUART2 RX + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, // 20: S400 + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, // 21: SAI TX + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, // 22: SAI RX + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, // 23: TPM1 CH0/CH2 + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, // 24: TPM1 CH1/CH3 + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, // 25: TPM1 Overflow + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, // 26: TMP2 CH0/CH2 + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, // 27: TMP2 CH1/CH3 + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, // 28: TMP2 Overflow + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, // 29: PDM + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, // 30: ADC1 + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; // err + clocks = <&clk IMX93_CLK_EDMA1_GATE>; + clock-names = "dma"; + }; + + aonmix_ns_gpr: syscon@44210000 { + compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon"; + reg = <0x44210000 0x1000>; + }; + + system_counter: timer@44290000 { + compatible = "nxp,sysctr-timer"; + reg = <0x44290000 0x30000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc_24m>; + clock-names = "per"; + nxp,no-divider; + }; + + wdog1: watchdog@442d0000 { + compatible = "fsl,imx93-wdt"; + reg = <0x442d0000 0x10000>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_WDOG1_GATE>; + timeout-sec = <40>; + status = "disabled"; + }; + + wdog2: watchdog@442e0000 { + compatible = "fsl,imx93-wdt"; + reg = <0x442e0000 0x10000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_WDOG2_GATE>; + timeout-sec = <40>; + status = "disabled"; + }; + + tpm1: pwm@44310000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x44310000 0x1000>; + clocks = <&clk IMX93_CLK_TPM1_GATE>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm2: pwm@44320000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x44320000 0x10000>; + clocks = <&clk IMX93_CLK_TPM2_GATE>; + #pwm-cells = <3>; + status = "disabled"; + }; + + i3c1: i3c@44330000 { + compatible = "silvaco,i3c-master-v1"; + reg = <0x44330000 0x10000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&clk IMX93_CLK_BUS_AON>, + <&clk IMX93_CLK_I3C1_GATE>, + <&clk IMX93_CLK_I3C1_SLOW>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; + }; + + lpi2c1: i2c@44340000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x44340000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C1_GATE>, + <&clk IMX93_CLK_BUS_AON>; + clock-names = "per", "ipg"; + dmas = <&edma1 7 0 0>, <&edma1 8 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c2: i2c@44350000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x44350000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C2_GATE>, + <&clk IMX93_CLK_BUS_AON>; + clock-names = "per", "ipg"; + dmas = <&edma1 9 0 0>, <&edma1 10 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi1: spi@44360000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x44360000 0x10000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI1_GATE>, + <&clk IMX93_CLK_BUS_AON>; + clock-names = "per", "ipg"; + dmas = <&edma1 11 0 0>, <&edma1 12 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi2: spi@44370000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x44370000 0x10000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI2_GATE>, + <&clk IMX93_CLK_BUS_AON>; + clock-names = "per", "ipg"; + dmas = <&edma1 13 0 0>, <&edma1 14 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpuart1: serial@44380000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x44380000 0x1000>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART1_GATE>; + clock-names = "ipg"; + dmas = <&edma1 17 0 FSL_EDMA_RX>, <&edma1 16 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart2: serial@44390000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x44390000 0x1000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART2_GATE>; + clock-names = "ipg"; + dmas = <&edma1 19 0 FSL_EDMA_RX>, <&edma1 18 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + flexcan1: can@443a0000 { + compatible = "fsl,imx93-flexcan"; + reg = <0x443a0000 0x10000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_BUS_AON>, + <&clk IMX93_CLK_CAN1_GATE>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX93_CLK_CAN1>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + fsl,stop-mode = <&aonmix_ns_gpr 0x14 0>; + status = "disabled"; + }; + + sai1: sai@443b0000 { + compatible = "fsl,imx93-sai"; + reg = <0x443b0000 0x10000>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma1 22 0 FSL_EDMA_RX>, <&edma1 21 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + iomuxc: pinctrl@443c0000 { + compatible = "fsl,imx93-iomuxc"; + reg = <0x443c0000 0x10000>; + status = "okay"; + }; + + bbnsm: bbnsm@44440000 { + compatible = "nxp,imx93-bbnsm", "syscon", "simple-mfd"; + reg = <0x44440000 0x10000>; + + bbnsm_rtc: rtc { + compatible = "nxp,imx93-bbnsm-rtc"; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + }; + + bbnsm_pwrkey: pwrkey { + compatible = "nxp,imx93-bbnsm-pwrkey"; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + linux,code = <KEY_POWER>; + }; + }; + + clk: clock-controller@44450000 { + compatible = "fsl,imx93-ccm"; + reg = <0x44450000 0x10000>; + #clock-cells = <1>; + clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>; + clock-names = "osc_32k", "osc_24m", "clk_ext1"; + assigned-clocks = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <393216000>; + status = "okay"; + }; + + src: system-controller@44460000 { + compatible = "fsl,imx93-src", "syscon"; + reg = <0x44460000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mediamix: power-domain@44462400 { + compatible = "fsl,imx93-src-slice"; + reg = <0x44462400 0x400>, <0x44465800 0x400>; + #power-domain-cells = <0>; + clocks = <&clk IMX93_CLK_NIC_MEDIA_GATE>, + <&clk IMX93_CLK_MEDIA_APB>; + }; + }; + + clock-controller@44480000 { + compatible = "fsl,imx93-anatop"; + reg = <0x44480000 0x2000>; + #clock-cells = <1>; + }; + + micfil: micfil@44520000 { + compatible = "fsl,imx93-micfil"; + reg = <0x44520000 0x10000>; + interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_PDM_IPG>, + <&clk IMX93_CLK_PDM_GATE>, + <&clk IMX93_CLK_AUDIO_PLL>; + clock-names = "ipg_clk", "ipg_clk_app", "pll8k"; + dmas = <&edma1 29 0 5>; + dma-names = "rx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + adc1: adc@44530000 { + compatible = "nxp,imx93-adc"; + reg = <0x44530000 0x10000>; + interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_ADC1_GATE>; + clock-names = "ipg"; + #io-channel-cells = <1>; + status = "disabled"; + }; + }; + + aips2: bus@42000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x42000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + edma2: dma-controller@42000000 { + compatible = "fsl,imx93-edma4"; + reg = <0x42000000 0x210000>; + #dma-cells = <3>; + dma-channels = <64>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_EDMA2_GATE>; + clock-names = "dma"; + }; + + wakeupmix_gpr: syscon@42420000 { + compatible = "fsl,imx93-wakeupmix-syscfg", "syscon"; + reg = <0x42420000 0x1000>; + }; + + wdog3: watchdog@42490000 { + compatible = "fsl,imx93-wdt"; + reg = <0x42490000 0x10000>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_WDOG3_GATE>; + timeout-sec = <40>; + status = "disabled"; + }; + + wdog4: watchdog@424a0000 { + compatible = "fsl,imx93-wdt"; + reg = <0x424a0000 0x10000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_WDOG4_GATE>; + timeout-sec = <40>; + status = "disabled"; + }; + + wdog5: watchdog@424b0000 { + compatible = "fsl,imx93-wdt"; + reg = <0x424b0000 0x10000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_WDOG5_GATE>; + timeout-sec = <40>; + status = "disabled"; + }; + + tpm3: pwm@424e0000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x424e0000 0x1000>; + clocks = <&clk IMX93_CLK_TPM3_GATE>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm4: pwm@424f0000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x424f0000 0x10000>; + clocks = <&clk IMX93_CLK_TPM4_GATE>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm5: pwm@42500000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42500000 0x10000>; + clocks = <&clk IMX93_CLK_TPM5_GATE>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm6: pwm@42510000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42510000 0x10000>; + clocks = <&clk IMX93_CLK_TPM6_GATE>; + #pwm-cells = <3>; + status = "disabled"; + }; + + i3c2: i3c@42520000 { + compatible = "silvaco,i3c-master-v1"; + reg = <0x42520000 0x10000>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_I3C2_GATE>, + <&clk IMX93_CLK_I3C2_SLOW>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; + }; + + lpi2c3: i2c@42530000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x42530000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C3_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c4: i2c@42540000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x42540000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C4_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi3: spi@42550000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42550000 0x10000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI3_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi4: spi@42560000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42560000 0x10000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI4_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpuart3: serial@42570000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x42570000 0x1000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART3_GATE>; + clock-names = "ipg"; + dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart4: serial@42580000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x42580000 0x1000>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART4_GATE>; + clock-names = "ipg"; + dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart5: serial@42590000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x42590000 0x1000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART5_GATE>; + clock-names = "ipg"; + dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart6: serial@425a0000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x425a0000 0x1000>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART6_GATE>; + clock-names = "ipg"; + dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + flexcan2: can@425b0000 { + compatible = "fsl,imx93-flexcan"; + reg = <0x425b0000 0x10000>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_CAN2_GATE>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX93_CLK_CAN2>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + fsl,stop-mode = <&wakeupmix_gpr 0x0c 2>; + status = "disabled"; + }; + + flexspi1: spi@425e0000 { + compatible = "nxp,imx8mm-fspi"; + reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_FLEXSPI1_GATE>, + <&clk IMX93_CLK_FLEXSPI1_GATE>; + clock-names = "fspi_en", "fspi"; + assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + status = "disabled"; + }; + + sai2: sai@42650000 { + compatible = "fsl,imx93-sai"; + reg = <0x42650000 0x10000>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_SAI2_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI2_GATE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma2 59 0 FSL_EDMA_RX>, <&edma2 58 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + sai3: sai@42660000 { + compatible = "fsl,imx93-sai"; + reg = <0x42660000 0x10000>; + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_SAI3_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI3_GATE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma2 61 0 FSL_EDMA_RX>, <&edma2 60 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + xcvr: xcvr@42680000 { + compatible = "fsl,imx93-xcvr"; + reg = <0x42680000 0x800>, + <0x42680800 0x400>, + <0x42680c00 0x080>, + <0x42680e00 0x080>; + reg-names = "ram", "regs", "rxfifo", "txfifo"; + interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_SPDIF_IPG>, + <&clk IMX93_CLK_SPDIF_GATE>, + <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_AUD_XCVR_GATE>; + clock-names = "ipg", "phy", "spba", "pll_ipg"; + dmas = <&edma2 65 0 FSL_EDMA_RX>, <&edma2 66 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + lpuart7: serial@42690000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x42690000 0x1000>; + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART7_GATE>; + clock-names = "ipg"; + dmas = <&edma2 88 0 FSL_EDMA_RX>, <&edma2 87 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart8: serial@426a0000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x426a0000 0x1000>; + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART8_GATE>; + clock-names = "ipg"; + dmas = <&edma2 90 0 FSL_EDMA_RX>, <&edma2 89 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpi2c5: i2c@426b0000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426b0000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C5_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c6: i2c@426c0000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426c0000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C6_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c7: i2c@426d0000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426d0000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C7_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c8: i2c@426e0000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426e0000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C8_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi5: spi@426f0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x426f0000 0x10000>; + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI5_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi6: spi@42700000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42700000 0x10000>; + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI6_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi7: spi@42710000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42710000 0x10000>; + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI7_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi8: spi@42720000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42720000 0x10000>; + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI8_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + }; + + aips3: bus@42800000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x42800000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usdhc1: mmc@42850000 { + compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42850000 0x10000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_WAKEUP_AXI>, + <&clk IMX93_CLK_USDHC1_GATE>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX93_CLK_USDHC1>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + fsl,tuning-start-tap = <1>; + fsl,tuning-step = <2>; + status = "disabled"; + }; + + usdhc2: mmc@42860000 { + compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42860000 0x10000>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_WAKEUP_AXI>, + <&clk IMX93_CLK_USDHC2_GATE>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX93_CLK_USDHC2>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <400000000>; + bus-width = <4>; + fsl,tuning-start-tap = <1>; + fsl,tuning-step = <2>; + status = "disabled"; + }; + + fec: ethernet@42890000 { + compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; + reg = <0x42890000 0x10000>; + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_ENET1_GATE>, + <&clk IMX93_CLK_ENET1_GATE>, + <&clk IMX93_CLK_ENET_TIMER1>, + <&clk IMX93_CLK_ENET_REF>, + <&clk IMX93_CLK_ENET_REF_PHY>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, + <&clk IMX93_CLK_ENET_REF>, + <&clk IMX93_CLK_ENET_REF_PHY>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <100000000>, <250000000>, <50000000>; + fsl,num-tx-queues = <3>; + fsl,num-rx-queues = <3>; + fsl,stop-mode = <&wakeupmix_gpr 0x0c 1>; + nvmem-cells = <ð_mac1>; + nvmem-cell-names = "mac-address"; + status = "disabled"; + }; + + eqos: ethernet@428a0000 { + compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a"; + reg = <0x428a0000 0x10000>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq"; + clocks = <&clk IMX93_CLK_ENET_QOS_GATE>, + <&clk IMX93_CLK_ENET_QOS_GATE>, + <&clk IMX93_CLK_ENET_TIMER2>, + <&clk IMX93_CLK_ENET>, + <&clk IMX93_CLK_ENET_QOS_GATE>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; + assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, + <&clk IMX93_CLK_ENET>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; + assigned-clock-rates = <100000000>, <250000000>; + intf_mode = <&wakeupmix_gpr 0x28>; + snps,clk-csr = <6>; + nvmem-cells = <ð_mac2>; + nvmem-cell-names = "mac-address"; + status = "disabled"; + }; + + usdhc3: mmc@428b0000 { + compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x428b0000 0x10000>; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_WAKEUP_AXI>, + <&clk IMX93_CLK_USDHC3_GATE>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX93_CLK_USDHC3>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <400000000>; + bus-width = <4>; + fsl,tuning-start-tap = <1>; + fsl,tuning-step = <2>; + status = "disabled"; + }; + }; + + gpio2: gpio@43810000 { + compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; + reg = <0x43810000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clk IMX93_CLK_GPIO2_GATE>, + <&clk IMX93_CLK_GPIO2_GATE>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc 0 4 30>; + ngpios = <30>; + }; + + gpio3: gpio@43820000 { + compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; + reg = <0x43820000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clk IMX93_CLK_GPIO3_GATE>, + <&clk IMX93_CLK_GPIO3_GATE>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>, + <&iomuxc 26 34 2>, <&iomuxc 28 0 4>; + ngpios = <32>; + }; + + gpio4: gpio@43830000 { + compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; + reg = <0x43830000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clk IMX93_CLK_GPIO4_GATE>, + <&clk IMX93_CLK_GPIO4_GATE>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>; + ngpios = <30>; + }; + + gpio1: gpio@47400000 { + compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; + reg = <0x47400000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clk IMX93_CLK_GPIO1_GATE>, + <&clk IMX93_CLK_GPIO1_GATE>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc 0 92 16>; + ngpios = <16>; + }; + + ocotp: efuse@47510000 { + compatible = "fsl,imx93-ocotp", "syscon"; + reg = <0x47510000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + eth_mac1: mac-address@4ec { + reg = <0x4ec 0x6>; + }; + + eth_mac2: mac-address@4f2 { + reg = <0x4f2 0x6>; + }; + + }; + + s4muap: mailbox@47520000 { + compatible = "fsl,imx93-mu-s4"; + reg = <0x47520000 0x10000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx", "rx"; + #mbox-cells = <2>; + }; + + media_blk_ctrl: system-controller@4ac10000 { + compatible = "fsl,imx93-media-blk-ctrl", "syscon"; + reg = <0x4ac10000 0x10000>; + power-domains = <&mediamix>; + clocks = <&clk IMX93_CLK_MEDIA_APB>, + <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_NIC_MEDIA_GATE>, + <&clk IMX93_CLK_MEDIA_DISP_PIX>, + <&clk IMX93_CLK_CAM_PIX>, + <&clk IMX93_CLK_PXP_GATE>, + <&clk IMX93_CLK_LCDIF_GATE>, + <&clk IMX93_CLK_ISI_GATE>, + <&clk IMX93_CLK_MIPI_CSI_GATE>, + <&clk IMX93_CLK_MIPI_DSI_GATE>; + clock-names = "apb", "axi", "nic", "disp", "cam", + "pxp", "lcdif", "isi", "csi", "dsi"; + #power-domain-cells = <1>; + status = "disabled"; + }; + + usbotg1: usb@4c100000 { + compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x4c100000 0x200>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, + <&clk IMX93_CLK_HSIO_32K_GATE>; + clock-names = "usb_ctrl_root", "usb_wakeup"; + assigned-clocks = <&clk IMX93_CLK_HSIO>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <133000000>; + phys = <&usbphynop1>; + fsl,usbmisc = <&usbmisc1 0>; + status = "disabled"; + }; + + usbmisc1: usbmisc@4c100200 { + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", + "fsl,imx6q-usbmisc"; + reg = <0x4c100200 0x200>; + #index-cells = <1>; + }; + + usbotg2: usb@4c200000 { + compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x4c200000 0x200>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, + <&clk IMX93_CLK_HSIO_32K_GATE>; + clock-names = "usb_ctrl_root", "usb_wakeup"; + assigned-clocks = <&clk IMX93_CLK_HSIO>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <133000000>; + phys = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + status = "disabled"; + }; + + usbmisc2: usbmisc@4c200200 { + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", + "fsl,imx6q-usbmisc"; + reg = <0x4c200200 0x200>; + #index-cells = <1>; + }; + + memory-controller@4e300000 { + compatible = "nxp,imx9-memory-controller"; + reg = <0x4e300000 0x800>, <0x4e301000 0x1000>; + reg-names = "ctrl", "inject"; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + little-endian; + }; + + ddr_pmu: ddr-pmu@4e300dc0 { + compatible = "fsl,imx93-ddr-pmu"; + reg = <0x4e300dc0 0x200>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts index e24e12f04526..b94a24193e19 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts @@ -12,6 +12,25 @@ model = "NXP i.MX93 11X11 EVK board"; compatible = "fsl,imx93-11x11-evk", "fsl,imx93"; + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + rtc0 = &bbnsm_rtc; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + }; + chosen { stdout-path = &lpuart1; }; @@ -272,7 +291,6 @@ ethphy2: ethernet-phy@2 { reg = <2>; - eee-broken-1000t; reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; reset-deassert-us = <80000>; diff --git a/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts b/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts index c5d86b54ad33..f9eebd27d640 100644 --- a/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts @@ -12,6 +12,21 @@ model = "NXP i.MX93 14X14 EVK board"; compatible = "fsl,imx93-14x14-evk", "fsl,imx93"; + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + rtc0 = &bbnsm_rtc; + serial0 = &lpuart1; + }; + chosen { stdout-path = &lpuart1; }; @@ -276,7 +291,7 @@ regulator-ramp-delay = <3125>; }; - buck4: BUCK4{ + buck4: BUCK4 { regulator-name = "BUCK4"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <3400000>; @@ -284,7 +299,7 @@ regulator-always-on; }; - buck5: BUCK5{ + buck5: BUCK5 { regulator-name = "BUCK5"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <3400000>; diff --git a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts index f6f8d105b737..0852067eab2c 100644 --- a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts +++ b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts @@ -17,6 +17,24 @@ compatible = "linux,bt-sco"; }; + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + rtc0 = &bbnsm_rtc; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + }; + chosen { stdout-path = &lpuart1; }; diff --git a/arch/arm64/boot/dts/freescale/imx93-kontron-bl-osm-s.dts b/arch/arm64/boot/dts/freescale/imx93-kontron-bl-osm-s.dts index 89e97c604bd3..4620c070f4d7 100644 --- a/arch/arm64/boot/dts/freescale/imx93-kontron-bl-osm-s.dts +++ b/arch/arm64/boot/dts/freescale/imx93-kontron-bl-osm-s.dts @@ -14,6 +14,27 @@ aliases { ethernet0 = &fec; ethernet1 = &eqos; + gpio0 = &gpio1; + gpio1 = &gpio2; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + serial5 = &lpuart6; + serial6 = &lpuart7; + spi0 = &lpspi1; + spi1 = &lpspi2; + spi2 = &lpspi3; + spi3 = &lpspi4; + spi4 = &lpspi5; + spi5 = &lpspi6; + spi6 = &lpspi7; + spi7 = &lpspi8; }; leds { @@ -33,7 +54,9 @@ reg_vcc_panel: regulator-vcc-panel { compatible = "regulator-fixed"; - gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_vcc_panel>; + gpio = <&gpio2 21 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-max-microvolt = <3300000>; regulator-min-microvolt = <3300000>; @@ -135,6 +158,16 @@ }; &usbotg1 { + adp-disable; + hnp-disable; + srp-disable; + disable-over-current; + dr_mode = "otg"; + usb-role-switch; + status = "okay"; +}; + +&usbotg2 { #address-cells = <1>; #size-cells = <0>; disable-over-current; @@ -147,17 +180,15 @@ }; }; -&usbotg2 { - adp-disable; - hnp-disable; - srp-disable; - disable-over-current; - dr_mode = "otg"; - usb-role-switch; - status = "okay"; -}; - &usdhc2 { vmmc-supply = <®_vdd_3v3>; status = "okay"; }; + +&iomuxc { + pinctrl_reg_vcc_panel: regvccpanelgrp { + fsl,pins = < + MX93_PAD_GPIO_IO21__GPIO2_IO21 0x31e /* PWM_2 */ + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi index 119a16207059..c79b1df339db 100644 --- a/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi @@ -205,6 +205,9 @@ rv3028: rtc@52 { compatible = "microcrystal,rv3028"; reg = <0x52>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupts-extended = <&gpio3 19 IRQ_TYPE_LEVEL_LOW>; }; }; @@ -468,6 +471,12 @@ >; }; + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x31e + >; + }; + pinctrl_sai3: sai3grp { fsl,pins = < MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e /* I2S_A_DATA_IN */ diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts index 475913cf0cb9..5599e296919f 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts @@ -19,14 +19,44 @@ aliases { ethernet1 = &eqos; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + mmc0 = &usdhc1; + mmc1 = &usdhc2; rtc0 = &i2c_rtc; rtc1 = &bbnsm_rtc; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + serial5 = &lpuart6; + serial6 = &lpuart7; + spi0 = &lpspi1; + spi1 = &lpspi2; + spi2 = &lpspi3; + spi3 = &lpspi4; + spi4 = &lpspi5; + spi5 = &lpspi6; }; chosen { stdout-path = &lpuart1; }; + curr_sens: current-sense { + compatible = "current-sense-amplifier"; + #io-channel-cells = <0>; + io-channels = <&adc1 1>; + sense-gain-div = <2>; + sense-gain-mult = <50>; + sense-resistor-micro-ohms = <35000>; + }; + flexcan1_tc: can-phy0 { compatible = "ti,tcan1042"; #phy-cells = <0>; @@ -36,6 +66,11 @@ standby-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&curr_sens 0>; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts index 6f1374f5757f..802d96b19e4c 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts @@ -19,8 +19,17 @@ aliases { ethernet1 = &eqos; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + mmc0 = &usdhc1; + mmc1 = &usdhc2; rtc0 = &i2c_rtc; rtc1 = &bbnsm_rtc; + serial0 = &lpuart1; }; chosen { diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi index c6f5aa38ebf9..3f069905cf0b 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi @@ -67,7 +67,6 @@ pinctrl-0 = <&pinctrl_fec>; phy-mode = "rmii"; phy-handle = <ðphy1>; - fsl,magic-packet; assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, <&clk IMX93_CLK_ENET_REF>, <&clk IMX93_CLK_ENET_REF_PHY>; @@ -85,6 +84,8 @@ ethphy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; + reset-gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; + reset-assert-us = <30>; }; }; }; @@ -206,14 +207,17 @@ fsl,pins = < MX93_PAD_ENET2_MDC__ENET1_MDC 0x50e MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x502 - MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e - MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e - MX93_PAD_ENET2_RXC__ENET1_RX_ER 0x5fe + /* the three pins below are connected to PHYs straps, + * that is what the pull-up/down setting is for. + */ + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x37e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x37e MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x50e MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x50e MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x50e MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x4000050e + MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e >; }; diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts index 9dbf41cf394b..2673d9dccbf4 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts @@ -27,8 +27,19 @@ eeprom0 = &eeprom0; ethernet0 = &eqos; ethernet1 = &fec; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; rtc0 = &pcf85063; rtc1 = &bbnsm_rtc; + serial0 = &lpuart1; + serial1 = &lpuart2; }; backlight: backlight { diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts index 137b8ed242a2..4760d07ea24b 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts @@ -28,8 +28,33 @@ eeprom0 = &eeprom0; ethernet0 = &eqos; ethernet1 = &fec; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + i2c3 = &lpi2c4; + i2c4 = &lpi2c5; + mmc0 = &usdhc1; + mmc1 = &usdhc2; rtc0 = &pcf85063; rtc1 = &bbnsm_rtc; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + serial5 = &lpuart6; + serial6 = &lpuart7; + serial7 = &lpuart8; + spi0 = &lpspi1; + spi1 = &lpspi2; + spi2 = &lpspi3; + spi3 = &lpspi4; + spi4 = &lpspi5; + spi5 = &lpspi6; }; backlight_lvds: backlight { diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts index 219f49a4f87f..8a88c98ac05a 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts @@ -28,8 +28,33 @@ eeprom0 = &eeprom0; ethernet0 = &eqos; ethernet1 = &fec; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + i2c3 = &lpi2c4; + i2c4 = &lpi2c5; + mmc0 = &usdhc1; + mmc1 = &usdhc2; rtc0 = &pcf85063; rtc1 = &bbnsm_rtc; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + serial5 = &lpuart6; + serial6 = &lpuart7; + serial7 = &lpuart8; + spi0 = &lpspi1; + spi1 = &lpspi2; + spi2 = &lpspi3; + spi3 = &lpspi4; + spi4 = &lpspi5; + spi5 = &lpspi6; }; backlight_lvds: backlight { diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts index 576d6982a4a0..c789c1f24bdc 100644 --- a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts @@ -17,8 +17,25 @@ aliases { ethernet0 = &eqos; ethernet1 = &fec; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + i2c3 = &lpi2c4; + i2c4 = &lpi2c5; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + serial5 = &lpuart6; }; + chosen { stdout-path = &lpuart1; }; diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 8a7f1cd76c76..7b27012dfcb5 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -1,187 +1,15 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright 2022 NXP + * Copyright 2022,2025 NXP */ -#include <dt-bindings/clock/imx93-clock.h> -#include <dt-bindings/dma/fsl-edma.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/power/fsl,imx93-power.h> -#include <dt-bindings/thermal/thermal.h> +#include "imx91_93_common.dtsi" -#include "imx93-pinfunc.h" - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - i2c0 = &lpi2c1; - i2c1 = &lpi2c2; - i2c2 = &lpi2c3; - i2c3 = &lpi2c4; - i2c4 = &lpi2c5; - i2c5 = &lpi2c6; - i2c6 = &lpi2c7; - i2c7 = &lpi2c8; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - serial0 = &lpuart1; - serial1 = &lpuart2; - serial2 = &lpuart3; - serial3 = &lpuart4; - serial4 = &lpuart5; - serial5 = &lpuart6; - serial6 = &lpuart7; - serial7 = &lpuart8; - spi0 = &lpspi1; - spi1 = &lpspi2; - spi2 = &lpspi3; - spi3 = &lpspi4; - spi4 = &lpspi5; - spi5 = &lpspi6; - spi6 = &lpspi7; - spi7 = &lpspi8; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - idle-states { - entry-method = "psci"; - - cpu_pd_wait: cpu-pd-wait { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010033>; - local-timer-stop; - entry-latency-us = <10000>; - exit-latency-us = <7000>; - min-residency-us = <27000>; - wakeup-latency-us = <15000>; - }; - }; - - A55_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0>; - enable-method = "psci"; - #cooling-cells = <2>; - cpu-idle-states = <&cpu_pd_wait>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l0>; - }; - - A55_1: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x100>; - enable-method = "psci"; - #cooling-cells = <2>; - cpu-idle-states = <&cpu_pd_wait>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l1>; - }; - - l2_cache_l0: l2-cache-l0 { - compatible = "cache"; - cache-size = <65536>; - cache-line-size = <64>; - cache-sets = <256>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_l1: l2-cache-l1 { - compatible = "cache"; - cache-size = <65536>; - cache-line-size = <64>; - cache-sets = <256>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l3_cache: l3-cache { - compatible = "cache"; - cache-size = <262144>; - cache-line-size = <64>; - cache-sets = <256>; - cache-level = <3>; - cache-unified; - }; - }; - - osc_32k: clock-osc-32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "osc_32k"; - }; - - osc_24m: clock-osc-24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc_24m"; - }; - - clk_ext1: clock-ext1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext1"; - }; - - pmu { - compatible = "arm,cortex-a55-pmu"; - interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; - clock-frequency = <24000000>; - arm,no-tick-in-suspend; - interrupt-parent = <&gic>; - }; - - gic: interrupt-controller@48000000 { - compatible = "arm,gic-v3"; - reg = <0 0x48000000 0 0x10000>, - <0 0x48040000 0 0xc0000>; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gic>; +/{ + cm33: remoteproc-cm33 { + compatible = "fsl,imx93-cm33"; + clocks = <&clk IMX93_CLK_CM33_GATE>; + status = "disabled"; }; thermal-zones { @@ -215,1143 +43,119 @@ }; }; }; +}; - cm33: remoteproc-cm33 { - compatible = "fsl,imx93-cm33"; - clocks = <&clk IMX93_CLK_CM33_GATE>; +&aips1 { + mu1: mailbox@44230000 { + compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; + reg = <0x44230000 0x10000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_MU1_B_GATE>; + #mbox-cells = <2>; status = "disabled"; }; - mqs1: mqs1 { - compatible = "fsl,imx93-mqs"; - gpr = <&aonmix_ns_gpr>; - status = "disabled"; + tmu: tmu@44482000 { + compatible = "fsl,qoriq-tmu"; + reg = <0x44482000 0x1000>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_TMC_GATE>; + #thermal-sensor-cells = <1>; + little-endian; + fsl,tmu-range = <0x800000da 0x800000e9 + 0x80000102 0x8000012a + 0x80000166 0x800001a7 + 0x800001b6>; + fsl,tmu-calibration = <0x00000000 0x0000000e + 0x00000001 0x00000029 + 0x00000002 0x00000056 + 0x00000003 0x000000a2 + 0x00000004 0x00000116 + 0x00000005 0x00000195 + 0x00000006 0x000001b2>; }; +}; - mqs2: mqs2 { - compatible = "fsl,imx93-mqs"; - gpr = <&wakeupmix_gpr>; +&aips2 { + mu2: mailbox@42440000 { + compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; + reg = <0x42440000 0x10000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_MU2_B_GATE>; + #mbox-cells = <2>; status = "disabled"; }; +}; - usbphynop1: usbphynop1 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; - clock-names = "main_clk"; - }; - - usbphynop2: usbphynop2 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; - clock-names = "main_clk"; +&cpus { + A55_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l0>; + }; + + A55_1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l1>; + }; + + l2_cache_l0: l2-cache-l0 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l1: l2-cache-l1 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l3_cache: l3-cache { + compatible = "cache"; + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <3>; + cache-unified; }; +}; - soc@0 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x80000000>, - <0x28000000 0x0 0x28000000 0x10000000>; - - aips1: bus@44000000 { - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x44000000 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - edma1: dma-controller@44000000 { - compatible = "fsl,imx93-edma3"; - reg = <0x44000000 0x200000>; - #dma-cells = <3>; - dma-channels = <31>; - interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, // 0: Reserved - <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, // 1: CANFD1 - <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, // 2: Reserved - <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, // 3: GPIO1 CH0 - <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, // 4: GPIO1 CH1 - <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, // 5: I3C1 TO Bus - <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, // 6: I3C1 From Bus - <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, // 7: LPI2C1 M TX - <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, // 8: LPI2C1 S TX - <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, // 9: LPI2C2 M RX - <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, // 10: LPI2C2 S RX - <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, // 11: LPSPI1 TX - <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, // 12: LPSPI1 RX - <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, // 13: LPSPI2 TX - <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, // 14: LPSPI2 RX - <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, // 15: LPTMR1 - <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, // 16: LPUART1 TX - <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, // 17: LPUART1 RX - <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, // 18: LPUART2 TX - <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, // 19: LPUART2 RX - <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, // 20: S400 - <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, // 21: SAI TX - <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, // 22: SAI RX - <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, // 23: TPM1 CH0/CH2 - <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, // 24: TPM1 CH1/CH3 - <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, // 25: TPM1 Overflow - <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, // 26: TMP2 CH0/CH2 - <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, // 27: TMP2 CH1/CH3 - <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, // 28: TMP2 Overflow - <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, // 29: PDM - <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, // 30: ADC1 - <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; // err - clocks = <&clk IMX93_CLK_EDMA1_GATE>; - clock-names = "dma"; - }; - - aonmix_ns_gpr: syscon@44210000 { - compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon"; - reg = <0x44210000 0x1000>; - }; - - mu1: mailbox@44230000 { - compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; - reg = <0x44230000 0x10000>; - interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_MU1_B_GATE>; - #mbox-cells = <2>; - status = "disabled"; - }; - - system_counter: timer@44290000 { - compatible = "nxp,sysctr-timer"; - reg = <0x44290000 0x30000>; - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc_24m>; - clock-names = "per"; - nxp,no-divider; - }; - - wdog1: watchdog@442d0000 { - compatible = "fsl,imx93-wdt"; - reg = <0x442d0000 0x10000>; - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_WDOG1_GATE>; - timeout-sec = <40>; - status = "disabled"; - }; - - wdog2: watchdog@442e0000 { - compatible = "fsl,imx93-wdt"; - reg = <0x442e0000 0x10000>; - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_WDOG2_GATE>; - timeout-sec = <40>; - status = "disabled"; - }; - - tpm1: pwm@44310000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x44310000 0x1000>; - clocks = <&clk IMX93_CLK_TPM1_GATE>; - #pwm-cells = <3>; - status = "disabled"; - }; - - tpm2: pwm@44320000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x44320000 0x10000>; - clocks = <&clk IMX93_CLK_TPM2_GATE>; - #pwm-cells = <3>; - status = "disabled"; - }; - - i3c1: i3c@44330000 { - compatible = "silvaco,i3c-master-v1"; - reg = <0x44330000 0x10000>; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <3>; - #size-cells = <0>; - clocks = <&clk IMX93_CLK_BUS_AON>, - <&clk IMX93_CLK_I3C1_GATE>, - <&clk IMX93_CLK_I3C1_SLOW>; - clock-names = "pclk", "fast_clk", "slow_clk"; - status = "disabled"; - }; - - lpi2c1: i2c@44340000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x44340000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C1_GATE>, - <&clk IMX93_CLK_BUS_AON>; - clock-names = "per", "ipg"; - dmas = <&edma1 7 0 0>, <&edma1 8 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpi2c2: i2c@44350000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x44350000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C2_GATE>, - <&clk IMX93_CLK_BUS_AON>; - clock-names = "per", "ipg"; - dmas = <&edma1 9 0 0>, <&edma1 10 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpspi1: spi@44360000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x44360000 0x10000>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI1_GATE>, - <&clk IMX93_CLK_BUS_AON>; - clock-names = "per", "ipg"; - dmas = <&edma1 11 0 0>, <&edma1 12 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpspi2: spi@44370000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x44370000 0x10000>; - interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI2_GATE>, - <&clk IMX93_CLK_BUS_AON>; - clock-names = "per", "ipg"; - dmas = <&edma1 13 0 0>, <&edma1 14 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpuart1: serial@44380000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x44380000 0x1000>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART1_GATE>; - clock-names = "ipg"; - dmas = <&edma1 17 0 FSL_EDMA_RX>, <&edma1 16 0 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - lpuart2: serial@44390000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x44390000 0x1000>; - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART2_GATE>; - clock-names = "ipg"; - dmas = <&edma1 19 0 FSL_EDMA_RX>, <&edma1 18 0 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - flexcan1: can@443a0000 { - compatible = "fsl,imx93-flexcan"; - reg = <0x443a0000 0x10000>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_BUS_AON>, - <&clk IMX93_CLK_CAN1_GATE>; - clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX93_CLK_CAN1>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; - assigned-clock-rates = <40000000>; - fsl,clk-source = /bits/ 8 <0>; - fsl,stop-mode = <&aonmix_ns_gpr 0x14 0>; - status = "disabled"; - }; - - sai1: sai@443b0000 { - compatible = "fsl,imx93-sai"; - reg = <0x443b0000 0x10000>; - interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>, - <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, - <&clk IMX93_CLK_DUMMY>; - clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&edma1 22 0 FSL_EDMA_RX>, <&edma1 21 0 0>; - dma-names = "rx", "tx"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - iomuxc: pinctrl@443c0000 { - compatible = "fsl,imx93-iomuxc"; - reg = <0x443c0000 0x10000>; - status = "okay"; - }; - - bbnsm: bbnsm@44440000 { - compatible = "nxp,imx93-bbnsm", "syscon", "simple-mfd"; - reg = <0x44440000 0x10000>; - - bbnsm_rtc: rtc { - compatible = "nxp,imx93-bbnsm-rtc"; - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - }; - - bbnsm_pwrkey: pwrkey { - compatible = "nxp,imx93-bbnsm-pwrkey"; - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - linux,code = <KEY_POWER>; - }; - }; - - clk: clock-controller@44450000 { - compatible = "fsl,imx93-ccm"; - reg = <0x44450000 0x10000>; - #clock-cells = <1>; - clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>; - clock-names = "osc_32k", "osc_24m", "clk_ext1"; - assigned-clocks = <&clk IMX93_CLK_AUDIO_PLL>; - assigned-clock-rates = <393216000>; - status = "okay"; - }; - - src: system-controller@44460000 { - compatible = "fsl,imx93-src", "syscon"; - reg = <0x44460000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mlmix: power-domain@44461800 { - compatible = "fsl,imx93-src-slice"; - reg = <0x44461800 0x400>, <0x44464800 0x400>; - #power-domain-cells = <0>; - clocks = <&clk IMX93_CLK_ML_APB>, - <&clk IMX93_CLK_ML>; - }; - - mediamix: power-domain@44462400 { - compatible = "fsl,imx93-src-slice"; - reg = <0x44462400 0x400>, <0x44465800 0x400>; - #power-domain-cells = <0>; - clocks = <&clk IMX93_CLK_NIC_MEDIA_GATE>, - <&clk IMX93_CLK_MEDIA_APB>; - }; - }; - - clock-controller@44480000 { - compatible = "fsl,imx93-anatop"; - reg = <0x44480000 0x2000>; - #clock-cells = <1>; - }; - - tmu: tmu@44482000 { - compatible = "fsl,qoriq-tmu"; - reg = <0x44482000 0x1000>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_TMC_GATE>; - little-endian; - fsl,tmu-range = <0x800000da 0x800000e9 - 0x80000102 0x8000012a - 0x80000166 0x800001a7 - 0x800001b6>; - fsl,tmu-calibration = <0x00000000 0x0000000e - 0x00000001 0x00000029 - 0x00000002 0x00000056 - 0x00000003 0x000000a2 - 0x00000004 0x00000116 - 0x00000005 0x00000195 - 0x00000006 0x000001b2>; - #thermal-sensor-cells = <1>; - }; - - micfil: micfil@44520000 { - compatible = "fsl,imx93-micfil"; - reg = <0x44520000 0x10000>; - interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_PDM_IPG>, - <&clk IMX93_CLK_PDM_GATE>, - <&clk IMX93_CLK_AUDIO_PLL>; - clock-names = "ipg_clk", "ipg_clk_app", "pll8k"; - dmas = <&edma1 29 0 5>; - dma-names = "rx"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - adc1: adc@44530000 { - compatible = "nxp,imx93-adc"; - reg = <0x44530000 0x10000>; - interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_ADC1_GATE>; - clock-names = "ipg"; - #io-channel-cells = <1>; - status = "disabled"; - }; - }; - - aips2: bus@42000000 { - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x42000000 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - edma2: dma-controller@42000000 { - compatible = "fsl,imx93-edma4"; - reg = <0x42000000 0x210000>; - #dma-cells = <3>; - dma-channels = <64>; - interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_EDMA2_GATE>; - clock-names = "dma"; - }; - - wakeupmix_gpr: syscon@42420000 { - compatible = "fsl,imx93-wakeupmix-syscfg", "syscon"; - reg = <0x42420000 0x1000>; - }; - - mu2: mailbox@42440000 { - compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; - reg = <0x42440000 0x10000>; - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_MU2_B_GATE>; - #mbox-cells = <2>; - status = "disabled"; - }; - - wdog3: watchdog@42490000 { - compatible = "fsl,imx93-wdt"; - reg = <0x42490000 0x10000>; - interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_WDOG3_GATE>; - timeout-sec = <40>; - status = "disabled"; - }; - - wdog4: watchdog@424a0000 { - compatible = "fsl,imx93-wdt"; - reg = <0x424a0000 0x10000>; - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_WDOG4_GATE>; - timeout-sec = <40>; - status = "disabled"; - }; - - wdog5: watchdog@424b0000 { - compatible = "fsl,imx93-wdt"; - reg = <0x424b0000 0x10000>; - interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_WDOG5_GATE>; - timeout-sec = <40>; - status = "disabled"; - }; - - tpm3: pwm@424e0000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x424e0000 0x1000>; - clocks = <&clk IMX93_CLK_TPM3_GATE>; - #pwm-cells = <3>; - status = "disabled"; - }; - - tpm4: pwm@424f0000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x424f0000 0x10000>; - clocks = <&clk IMX93_CLK_TPM4_GATE>; - #pwm-cells = <3>; - status = "disabled"; - }; - - tpm5: pwm@42500000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x42500000 0x10000>; - clocks = <&clk IMX93_CLK_TPM5_GATE>; - #pwm-cells = <3>; - status = "disabled"; - }; - - tpm6: pwm@42510000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x42510000 0x10000>; - clocks = <&clk IMX93_CLK_TPM6_GATE>; - #pwm-cells = <3>; - status = "disabled"; - }; - - i3c2: i3c@42520000 { - compatible = "silvaco,i3c-master-v1"; - reg = <0x42520000 0x10000>; - interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <3>; - #size-cells = <0>; - clocks = <&clk IMX93_CLK_BUS_WAKEUP>, - <&clk IMX93_CLK_I3C2_GATE>, - <&clk IMX93_CLK_I3C2_SLOW>; - clock-names = "pclk", "fast_clk", "slow_clk"; - status = "disabled"; - }; - - lpi2c3: i2c@42530000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x42530000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C3_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpi2c4: i2c@42540000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x42540000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C4_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpspi3: spi@42550000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x42550000 0x10000>; - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI3_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpspi4: spi@42560000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x42560000 0x10000>; - interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI4_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpuart3: serial@42570000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x42570000 0x1000>; - interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART3_GATE>; - clock-names = "ipg"; - dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - lpuart4: serial@42580000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x42580000 0x1000>; - interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART4_GATE>; - clock-names = "ipg"; - dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - lpuart5: serial@42590000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x42590000 0x1000>; - interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART5_GATE>; - clock-names = "ipg"; - dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - lpuart6: serial@425a0000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x425a0000 0x1000>; - interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART6_GATE>; - clock-names = "ipg"; - dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - flexcan2: can@425b0000 { - compatible = "fsl,imx93-flexcan"; - reg = <0x425b0000 0x10000>; - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_BUS_WAKEUP>, - <&clk IMX93_CLK_CAN2_GATE>; - clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX93_CLK_CAN2>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; - assigned-clock-rates = <40000000>; - fsl,clk-source = /bits/ 8 <0>; - fsl,stop-mode = <&wakeupmix_gpr 0x0c 2>; - status = "disabled"; - }; - - flexspi1: spi@425e0000 { - compatible = "nxp,imx8mm-fspi"; - reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>; - reg-names = "fspi_base", "fspi_mmap"; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_FLEXSPI1_GATE>, - <&clk IMX93_CLK_FLEXSPI1_GATE>; - clock-names = "fspi_en", "fspi"; - assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; - status = "disabled"; - }; - - sai2: sai@42650000 { - compatible = "fsl,imx93-sai"; - reg = <0x42650000 0x10000>; - interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_SAI2_IPG>, <&clk IMX93_CLK_DUMMY>, - <&clk IMX93_CLK_SAI2_GATE>, <&clk IMX93_CLK_DUMMY>, - <&clk IMX93_CLK_DUMMY>; - clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&edma2 59 0 FSL_EDMA_RX>, <&edma2 58 0 0>; - dma-names = "rx", "tx"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - sai3: sai@42660000 { - compatible = "fsl,imx93-sai"; - reg = <0x42660000 0x10000>; - interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_SAI3_IPG>, <&clk IMX93_CLK_DUMMY>, - <&clk IMX93_CLK_SAI3_GATE>, <&clk IMX93_CLK_DUMMY>, - <&clk IMX93_CLK_DUMMY>; - clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&edma2 61 0 FSL_EDMA_RX>, <&edma2 60 0 0>; - dma-names = "rx", "tx"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - xcvr: xcvr@42680000 { - compatible = "fsl,imx93-xcvr"; - reg = <0x42680000 0x800>, - <0x42680800 0x400>, - <0x42680c00 0x080>, - <0x42680e00 0x080>; - reg-names = "ram", "regs", "rxfifo", "txfifo"; - interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_SPDIF_IPG>, - <&clk IMX93_CLK_SPDIF_GATE>, - <&clk IMX93_CLK_DUMMY>, - <&clk IMX93_CLK_AUD_XCVR_GATE>; - clock-names = "ipg", "phy", "spba", "pll_ipg"; - dmas = <&edma2 65 0 FSL_EDMA_RX>, <&edma2 66 0 0>; - dma-names = "rx", "tx"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - lpuart7: serial@42690000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x42690000 0x1000>; - interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART7_GATE>; - clock-names = "ipg"; - dmas = <&edma2 88 0 FSL_EDMA_RX>, <&edma2 87 0 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - lpuart8: serial@426a0000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x426a0000 0x1000>; - interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART8_GATE>; - clock-names = "ipg"; - dmas = <&edma2 90 0 FSL_EDMA_RX>, <&edma2 89 0 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - lpi2c5: i2c@426b0000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x426b0000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C5_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpi2c6: i2c@426c0000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x426c0000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C6_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpi2c7: i2c@426d0000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x426d0000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C7_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpi2c8: i2c@426e0000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x426e0000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C8_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpspi5: spi@426f0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x426f0000 0x10000>; - interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI5_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpspi6: spi@42700000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x42700000 0x10000>; - interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI6_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpspi7: spi@42710000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x42710000 0x10000>; - interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI7_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpspi8: spi@42720000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x42720000 0x10000>; - interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI8_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - }; - - aips3: bus@42800000 { - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x42800000 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usdhc1: mmc@42850000 { - compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; - reg = <0x42850000 0x10000>; - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_BUS_WAKEUP>, - <&clk IMX93_CLK_WAKEUP_AXI>, - <&clk IMX93_CLK_USDHC1_GATE>; - clock-names = "ipg", "ahb", "per"; - assigned-clocks = <&clk IMX93_CLK_USDHC1>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; - assigned-clock-rates = <400000000>; - bus-width = <8>; - fsl,tuning-start-tap = <1>; - fsl,tuning-step = <2>; - status = "disabled"; - }; - - usdhc2: mmc@42860000 { - compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; - reg = <0x42860000 0x10000>; - interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_BUS_WAKEUP>, - <&clk IMX93_CLK_WAKEUP_AXI>, - <&clk IMX93_CLK_USDHC2_GATE>; - clock-names = "ipg", "ahb", "per"; - assigned-clocks = <&clk IMX93_CLK_USDHC2>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; - assigned-clock-rates = <400000000>; - bus-width = <4>; - fsl,tuning-start-tap = <1>; - fsl,tuning-step = <2>; - status = "disabled"; - }; - - fec: ethernet@42890000 { - compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; - reg = <0x42890000 0x10000>; - interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_ENET1_GATE>, - <&clk IMX93_CLK_ENET1_GATE>, - <&clk IMX93_CLK_ENET_TIMER1>, - <&clk IMX93_CLK_ENET_REF>, - <&clk IMX93_CLK_ENET_REF_PHY>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, - <&clk IMX93_CLK_ENET_REF>, - <&clk IMX93_CLK_ENET_REF_PHY>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, - <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>, - <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; - assigned-clock-rates = <100000000>, <250000000>, <50000000>; - fsl,num-tx-queues = <3>; - fsl,num-rx-queues = <3>; - fsl,stop-mode = <&wakeupmix_gpr 0x0c 1>; - nvmem-cells = <ð_mac1>; - nvmem-cell-names = "mac-address"; - status = "disabled"; - }; - - eqos: ethernet@428a0000 { - compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a"; - reg = <0x428a0000 0x10000>; - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq", "eth_wake_irq"; - clocks = <&clk IMX93_CLK_ENET_QOS_GATE>, - <&clk IMX93_CLK_ENET_QOS_GATE>, - <&clk IMX93_CLK_ENET_TIMER2>, - <&clk IMX93_CLK_ENET>, - <&clk IMX93_CLK_ENET_QOS_GATE>; - clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; - assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, - <&clk IMX93_CLK_ENET>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, - <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; - assigned-clock-rates = <100000000>, <250000000>; - intf_mode = <&wakeupmix_gpr 0x28>; - snps,clk-csr = <6>; - nvmem-cells = <ð_mac2>; - nvmem-cell-names = "mac-address"; - status = "disabled"; - }; - - usdhc3: mmc@428b0000 { - compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; - reg = <0x428b0000 0x10000>; - interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_BUS_WAKEUP>, - <&clk IMX93_CLK_WAKEUP_AXI>, - <&clk IMX93_CLK_USDHC3_GATE>; - clock-names = "ipg", "ahb", "per"; - assigned-clocks = <&clk IMX93_CLK_USDHC3>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; - assigned-clock-rates = <400000000>; - bus-width = <4>; - fsl,tuning-start-tap = <1>; - fsl,tuning-step = <2>; - status = "disabled"; - }; - }; - - gpio2: gpio@43810000 { - compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; - reg = <0x43810000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clk IMX93_CLK_GPIO2_GATE>, - <&clk IMX93_CLK_GPIO2_GATE>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc 0 4 30>; - ngpios = <30>; - }; - - gpio3: gpio@43820000 { - compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; - reg = <0x43820000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clk IMX93_CLK_GPIO3_GATE>, - <&clk IMX93_CLK_GPIO3_GATE>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>, - <&iomuxc 26 34 2>, <&iomuxc 28 0 4>; - ngpios = <32>; - }; - - gpio4: gpio@43830000 { - compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; - reg = <0x43830000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clk IMX93_CLK_GPIO4_GATE>, - <&clk IMX93_CLK_GPIO4_GATE>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>; - ngpios = <30>; - }; - - gpio1: gpio@47400000 { - compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; - reg = <0x47400000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clk IMX93_CLK_GPIO1_GATE>, - <&clk IMX93_CLK_GPIO1_GATE>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc 0 92 16>; - ngpios = <16>; - }; - - ocotp: efuse@47510000 { - compatible = "fsl,imx93-ocotp", "syscon"; - reg = <0x47510000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - - eth_mac1: mac-address@4ec { - reg = <0x4ec 0x6>; - }; - - eth_mac2: mac-address@4f2 { - reg = <0x4f2 0x6>; - }; - - }; - - s4muap: mailbox@47520000 { - compatible = "fsl,imx93-mu-s4"; - reg = <0x47520000 0x10000>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - #mbox-cells = <2>; - }; - - media_blk_ctrl: system-controller@4ac10000 { - compatible = "fsl,imx93-media-blk-ctrl", "syscon"; - reg = <0x4ac10000 0x10000>; - power-domains = <&mediamix>; - clocks = <&clk IMX93_CLK_MEDIA_APB>, - <&clk IMX93_CLK_MEDIA_AXI>, - <&clk IMX93_CLK_NIC_MEDIA_GATE>, - <&clk IMX93_CLK_MEDIA_DISP_PIX>, - <&clk IMX93_CLK_CAM_PIX>, - <&clk IMX93_CLK_PXP_GATE>, - <&clk IMX93_CLK_LCDIF_GATE>, - <&clk IMX93_CLK_ISI_GATE>, - <&clk IMX93_CLK_MIPI_CSI_GATE>, - <&clk IMX93_CLK_MIPI_DSI_GATE>; - clock-names = "apb", "axi", "nic", "disp", "cam", - "pxp", "lcdif", "isi", "csi", "dsi"; - #power-domain-cells = <1>; - status = "disabled"; - }; - - usbotg1: usb@4c100000 { - compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; - reg = <0x4c100000 0x200>; - interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, - <&clk IMX93_CLK_HSIO_32K_GATE>; - clock-names = "usb_ctrl_root", "usb_wakeup"; - assigned-clocks = <&clk IMX93_CLK_HSIO>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; - assigned-clock-rates = <133000000>; - phys = <&usbphynop1>; - fsl,usbmisc = <&usbmisc1 0>; - status = "disabled"; - }; - - usbmisc1: usbmisc@4c100200 { - compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", - "fsl,imx6q-usbmisc"; - reg = <0x4c100200 0x200>; - #index-cells = <1>; - }; - - usbotg2: usb@4c200000 { - compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; - reg = <0x4c200000 0x200>; - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, - <&clk IMX93_CLK_HSIO_32K_GATE>; - clock-names = "usb_ctrl_root", "usb_wakeup"; - assigned-clocks = <&clk IMX93_CLK_HSIO>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; - assigned-clock-rates = <133000000>; - phys = <&usbphynop2>; - fsl,usbmisc = <&usbmisc2 0>; - status = "disabled"; - }; - - usbmisc2: usbmisc@4c200200 { - compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", - "fsl,imx6q-usbmisc"; - reg = <0x4c200200 0x200>; - #index-cells = <1>; - }; - - memory-controller@4e300000 { - compatible = "nxp,imx9-memory-controller"; - reg = <0x4e300000 0x800>, <0x4e301000 0x1000>; - reg-names = "ctrl", "inject"; - interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; - little-endian; - }; - - ddr-pmu@4e300dc0 { - compatible = "fsl,imx93-ddr-pmu"; - reg = <0x4e300dc0 0x200>; - interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; - }; +&src { + mlmix: power-domain@44461800 { + compatible = "fsl,imx93-src-slice"; + reg = <0x44461800 0x400>, <0x44464800 0x400>; + clocks = <&clk IMX93_CLK_ML_APB>, + <&clk IMX93_CLK_ML>; + #power-domain-cells = <0>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi index 44dee2cbd42d..d4a880496b0e 100644 --- a/arch/arm64/boot/dts/freescale/imx94.dtsi +++ b/arch/arm64/boot/dts/freescale/imx94.dtsi @@ -212,7 +212,8 @@ <&a55_irqsteer 88>, <&a55_irqsteer 89>, <&a55_irqsteer 90>, <&a55_irqsteer 91>, <&a55_irqsteer 92>, <&a55_irqsteer 93>, - <&a55_irqsteer 94>, <&a55_irqsteer 95>; + <&a55_irqsteer 94>, <&a55_irqsteer 95>, + <&gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; }; mu10: mailbox@42430000 { @@ -619,7 +620,8 @@ <&a55_irqsteer 216>, <&a55_irqsteer 217>, <&a55_irqsteer 218>, <&a55_irqsteer 219>, <&a55_irqsteer 220>, <&a55_irqsteer 221>, - <&a55_irqsteer 222>, <&a55_irqsteer 223>; + <&a55_irqsteer 222>, <&a55_irqsteer 223>, + <&gic GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts index 46f6e0fbf2b0..148243470dd4 100644 --- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts @@ -28,7 +28,24 @@ aliases { ethernet0 = &enetc_port0; ethernet1 = &enetc_port1; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + i2c3 = &lpi2c4; + i2c4 = &lpi2c5; + i2c5 = &lpi2c6; + i2c6 = &lpi2c7; + i2c7 = &lpi2c8; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; serial0 = &lpuart1; + serial4 = &lpuart5; }; bt_sco_codec: bt-sco-codec { @@ -864,12 +881,12 @@ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < - IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe - IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe - IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe - IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe - IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe - IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e >; }; @@ -1082,6 +1099,7 @@ fsl,phy-pcs-tx-swing-full-percent = <100>; fsl,phy-tx-preemp-amp-tune-microamp = <600>; fsl,phy-tx-vboost-level-microvolt = <1156>; + fsl,phy-tx-vref-tune-percent = <100>; status = "okay"; port { diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts index 2f949a0d48d2..9f968feccef6 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -40,6 +40,7 @@ mmc0 = &usdhc1; mmc1 = &usdhc2; serial0 = &lpuart1; + serial4 = &lpuart5; }; bt_sco_codec: audio-codec-bt-sco { @@ -80,17 +81,17 @@ flexcan1_phy: can-phy0 { compatible = "nxp,tjr1443"; #phy-cells = <0>; - max-bitrate = <1000000>; + max-bitrate = <8000000>; enable-gpios = <&i2c6_pcal6416 6 GPIO_ACTIVE_HIGH>; - standby-gpios = <&i2c6_pcal6416 5 GPIO_ACTIVE_HIGH>; + standby-gpios = <&i2c6_pcal6416 5 GPIO_ACTIVE_LOW>; }; flexcan2_phy: can-phy1 { compatible = "nxp,tjr1443"; #phy-cells = <0>; - max-bitrate = <1000000>; - enable-gpios = <&i2c6_pcal6416 4 GPIO_ACTIVE_HIGH>; - standby-gpios = <&i2c6_pcal6416 3 GPIO_ACTIVE_HIGH>; + max-bitrate = <8000000>; + enable-gpios = <&i2c4_gpio_expander_21 4 GPIO_ACTIVE_HIGH>; + standby-gpios = <&i2c4_gpio_expander_21 3 GPIO_ACTIVE_LOW>; }; reg_vref_1v8: regulator-1p8v { @@ -135,6 +136,13 @@ regulator-max-microvolt = <3300000>; gpio = <&i2c7_pcal6524 20 GPIO_ACTIVE_HIGH>; enable-active-high; + /* + * M.2 device only can be enabled(W_DISABLE1#) after all Power + * Rails reach their minimum operating voltage (PCI Express M.2 + * Specification r5.1 3.1.4 Power-up Timing). + * Set a delay equal to the max value of Tsettle here. + */ + startup-delay-us = <5000>; }; reg_pcie0: regulator-pcie { @@ -216,7 +224,7 @@ model = "wm8962-audio"; audio-cpu = <&sai3>; audio-codec = <&wm8962>; - hp-det-gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + hp-det-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; audio-routing = "Headphone Jack", "HPOUTL", "Headphone Jack", "HPOUTR", "Ext Spk", "SPKOUTL", @@ -302,6 +310,19 @@ reg = <0x20>; vcc-supply = <®_3p3v>; }; + + pca9632: pca9632@62 { + compatible = "nxp,pca9632"; + reg = <0x62>; + #address-cells = <1>; + #size-cells = <0>; + + led_baclklight: led@0 { + reg = <0>; + label = "backlight"; + linux,default-trigger = "none"; + }; + }; }; &lpi2c4 { @@ -622,6 +643,7 @@ fsl,phy-pcs-tx-swing-full-percent = <100>; fsl,phy-tx-preemp-amp-tune-microamp = <600>; fsl,phy-tx-vboost-level-microvolt = <1156>; + fsl,phy-tx-vref-tune-percent = <100>; orientation-switch; status = "okay"; @@ -671,7 +693,7 @@ }; &scmi_iomuxc { - pinctrl_emdio: emdiogrp{ + pinctrl_emdio: emdiogrp { fsl,pins = < IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x50e IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e @@ -1037,6 +1059,79 @@ }; }; }; + + pf09-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 2>; + + trips { + pf09_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf09_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + pf53arm-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 4>; + + cooling-maps { + map0 { + trip = <&pf5301_alert>; + cooling-device = + <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + pf5301_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf5301_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + pf53soc-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 3>; + + trips { + pf5302_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf5302_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; }; &tpm6 { diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 4ca6a7ea586e..1292677cbe4e 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -260,35 +260,35 @@ sai1_mclk: clock-sai-mclk1 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency= <0>; + clock-frequency = <0>; clock-output-names = "sai1_mclk"; }; sai2_mclk: clock-sai-mclk2 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency= <0>; + clock-frequency = <0>; clock-output-names = "sai2_mclk"; }; sai3_mclk: clock-sai-mclk3 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency= <0>; + clock-frequency = <0>; clock-output-names = "sai3_mclk"; }; sai4_mclk: clock-sai-mclk4 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency= <0>; + clock-frequency = <0>; clock-output-names = "sai4_mclk"; }; sai5_mclk: clock-sai-mclk5 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency= <0>; + clock-frequency = <0>; clock-output-names = "sai5_mclk"; }; @@ -351,10 +351,18 @@ reg = <0x19>; }; + scmi_lmm: protocol@80 { + reg = <0x80>; + }; + scmi_bbm: protocol@81 { reg = <0x81>; }; + scmi_cpu: protocol@82 { + reg = <0x82>; + }; + scmi_misc: protocol@84 { reg = <0x84>; }; @@ -484,6 +492,110 @@ #size-cells = <2>; ranges; + etm0: etm@40840000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0 0x40840000 0x0 0x10000>; + arm,primecell-periphid = <0xbb95d>; + cpu = <&A55_0>; + clocks = <&scmi_clk IMX95_CLK_A55PERIPH>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + etm0_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port0>; + }; + }; + }; + }; + + funnel0: funnel { + /* + * non-configurable funnel don't show up on the AMBA + * bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-static-funnel"; + status = "disabled"; + + in-ports { + port { + ca_funnel_in_port0: endpoint { + remote-endpoint = <&etm0_out_port>; + }; + }; + }; + + out-ports { + port { + ca_funnel_out_port0: endpoint { + remote-endpoint = <&hugo_funnel_in_port0>; + }; + }; + }; + }; + + funnel1: funnel-sys { + compatible = "arm,coresight-static-funnel"; + status = "disabled"; + + in-ports { + port { + hugo_funnel_in_port0: endpoint { + remote-endpoint = <&ca_funnel_out_port0>; + }; + }; + }; + + out-ports { + port { + hugo_funnel_out_port0: endpoint { + remote-endpoint = <&etf_in_port>; + }; + }; + }; + }; + + etf: etf@41030000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x41030000 0x0 0x1000>; + clocks = <&scmi_clk IMX95_CLK_A55PERIPH>; + clock-names = "apb_pclk"; + status = "disabled"; + + in-ports { + port { + etf_in_port: endpoint { + remote-endpoint = <&hugo_funnel_out_port0>; + }; + }; + }; + + out-ports { + port { + etf_out_port: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + }; + }; + + etr: etr@41040000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x41040000 0x0 0x1000>; + clocks = <&scmi_clk IMX95_CLK_A55PERIPH>; + clock-names = "apb_pclk"; + status = "disabled"; + + in-ports { + port { + etr_in_port: endpoint { + remote-endpoint = <&etf_out_port>; + }; + }; + }; + }; + aips2: bus@42000000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x0 0x42000000 0x0 0x800000>; @@ -913,7 +1025,7 @@ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; clocks = <&scmi_clk IMX95_CLK_LPUART7>; clock-names = "ipg"; - dmas = <&edma2 26 0 FSL_EDMA_RX>, <&edma2 25 0 0>; + dmas = <&edma2 88 0 FSL_EDMA_RX>, <&edma2 87 0 0>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -925,7 +1037,7 @@ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; clocks = <&scmi_clk IMX95_CLK_LPUART8>; clock-names = "ipg"; - dmas = <&edma2 28 0 FSL_EDMA_RX>, <&edma2 27 0 0>; + dmas = <&edma2 90 0 FSL_EDMA_RX>, <&edma2 89 0 0>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -1100,7 +1212,7 @@ assigned-clock-rates = <400000000>; bus-width = <8>; fsl,tuning-start-tap = <1>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; status = "disabled"; }; @@ -1117,7 +1229,7 @@ assigned-clock-rates = <400000000>; bus-width = <4>; fsl,tuning-start-tap = <1>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; status = "disabled"; }; @@ -1134,7 +1246,7 @@ assigned-clock-rates = <400000000>; bus-width = <4>; fsl,tuning-start-tap = <1>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; status = "disabled"; }; }; @@ -1260,6 +1372,15 @@ status = "disabled"; }; + system_counter: timer@44290000 { + compatible = "nxp,imx95-sysctr-timer"; + reg = <0x44290000 0x30000>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc_24m>; + clock-names = "per"; + nxp,no-divider; + }; + tpm1: pwm@44310000 { compatible = "fsl,imx7ulp-pwm"; reg = <0x44310000 0x1000>; @@ -1483,6 +1604,13 @@ }; }; + mailbox@47300000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47300000 0x0 0x10000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + }; + mailbox@47320000 { compatible = "fsl,imx95-mu-v2x"; reg = <0x0 0x47320000 0x0 0x10000>; @@ -1490,6 +1618,20 @@ #mbox-cells = <2>; }; + mailbox@47330000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47330000 0x0 0x10000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + }; + + mailbox@47340000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47340000 0x0 0x10000>; + interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + }; + mailbox@47350000 { compatible = "fsl,imx95-mu-v2x"; reg = <0x0 0x47350000 0x0 0x10000>; @@ -1515,6 +1657,25 @@ status = "disabled"; }; + ocotp: efuse@47510000 { + compatible = "fsl,imx95-ocotp", "syscon"; + reg = <0x0 0x47510000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + eth_mac0: mac-address@0 { + reg = <0x0514 0x6>; + }; + + eth_mac1: mac-address@1 { + reg = <0x1514 0x6>; + }; + + eth_mac2: mac-address@2 { + reg = <0x2514 0x6>; + }; + }; + elemu0: mailbox@47520000 { compatible = "fsl,imx95-mu-ele"; reg = <0x0 0x47520000 0x0 0x10000>; @@ -1685,9 +1846,9 @@ <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, <&hsio_blk_ctl 0>; clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; - assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, - <&scmi_clk IMX95_CLK_HSIOPLL>, - <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; + assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_HSIOPLL>, + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; assigned-clock-rates = <3600000000>, <100000000>, <10000000>; assigned-clock-parents = <0>, <0>, <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; @@ -1719,12 +1880,13 @@ <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; - assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, - <&scmi_clk IMX95_CLK_HSIOPLL>, - <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; + assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_HSIOPLL>, + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; assigned-clock-rates = <3600000000>, <100000000>, <10000000>; assigned-clock-parents = <0>, <0>, <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; + msi-map = <0x0 &its 0x98 0x1>; power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; status = "disabled"; }; @@ -1759,9 +1921,9 @@ <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, <&hsio_blk_ctl 0>; clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; - assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, - <&scmi_clk IMX95_CLK_HSIOPLL>, - <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; + assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_HSIOPLL>, + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; assigned-clock-rates = <3600000000>, <100000000>, <10000000>; assigned-clock-parents = <0>, <0>, <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; @@ -1795,9 +1957,9 @@ <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; - assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, - <&scmi_clk IMX95_CLK_HSIOPLL>, - <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; + assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_HSIOPLL>, + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; assigned-clock-rates = <3600000000>, <100000000>, <10000000>; assigned-clock-parents = <0>, <0>, <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; @@ -1843,7 +2005,7 @@ <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>; clocks = <&scmi_clk IMX95_CLK_VPU>, <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_ENC>; - assigned-clocks = <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_DEC>; + assigned-clocks = <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_ENC>; assigned-clock-parents = <&scmi_clk IMX95_CLK_VPUJPEG>; power-domains = <&scmi_devpd IMX95_PD_VPU>; }; @@ -1948,6 +2110,7 @@ }; netc_timer: ethernet@18,0 { + compatible = "pci1131,ee02"; reg = <0x00c000 0 0 0 0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index 09d2fbbe1d8c..d167624d1f0c 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -325,6 +325,81 @@ }; }; + ocotp: nvmem@400a4000 { + compatible = "nxp,s32g2-ocotp"; + reg = <0x400a4000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + }; + + swt0: watchdog@40100000 { + compatible = "nxp,s32g2-swt"; + reg = <0x40100000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt1: watchdog@40104000 { + compatible = "nxp,s32g2-swt"; + reg = <0x40104000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt2: watchdog@40108000 { + compatible = "nxp,s32g2-swt"; + reg = <0x40108000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt3: watchdog@4010c000 { + compatible = "nxp,s32g2-swt"; + reg = <0x4010c000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + stm0: timer@4011c000 { + compatible = "nxp,s32g2-stm"; + reg = <0x4011c000 0x3000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + stm1: timer@40120000 { + compatible = "nxp,s32g2-stm"; + reg = <0x40120000 0x3000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + stm2: timer@40124000 { + compatible = "nxp,s32g2-stm"; + reg = <0x40124000 0x3000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + stm3: timer@40128000 { + compatible = "nxp,s32g2-stm"; + reg = <0x40128000 0x3000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + edma0: dma-controller@40144000 { compatible = "nxp,s32g2-edma"; reg = <0x40144000 0x24000>, @@ -479,6 +554,57 @@ status = "disabled"; }; + swt4: watchdog@40200000 { + compatible = "nxp,s32g2-swt"; + reg = <0x40200000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt5: watchdog@40204000 { + compatible = "nxp,s32g2-swt"; + reg = <0x40204000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt6: watchdog@40208000 { + compatible = "nxp,s32g2-swt"; + reg = <0x40208000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + stm4: timer@4021c000 { + compatible = "nxp,s32g2-stm"; + reg = <0x4021c000 0x3000>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + stm5: timer@40220000 { + compatible = "nxp,s32g2-stm"; + reg = <0x40220000 0x3000>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + stm6: timer@40224000 { + compatible = "nxp,s32g2-stm"; + reg = <0x40224000 0x3000>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + edma1: dma-controller@40244000 { compatible = "nxp,s32g2-edma"; reg = <0x40244000 0x24000>, diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts index b5ba51696f43..4f58be68c818 100644 --- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts +++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts @@ -40,6 +40,26 @@ status = "okay"; }; +&stm0 { + status = "okay"; +}; + +&stm1 { + status = "okay"; +}; + +&stm2 { + status = "okay"; +}; + +&stm3 { + status = "okay"; +}; + +&swt0 { + status = "okay"; +}; + &usdhc0 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc0>; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index 39effbe8217c..be3a582ebc1b 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -383,6 +383,81 @@ }; }; + ocotp: nvmem@400a4000 { + compatible = "nxp,s32g3-ocotp", "nxp,s32g2-ocotp"; + reg = <0x400a4000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + }; + + swt0: watchdog@40100000 { + compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg = <0x40100000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt1: watchdog@40104000 { + compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg = <0x40104000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt2: watchdog@40108000 { + compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg = <0x40108000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt3: watchdog@4010c000 { + compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg = <0x4010c000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + stm0: timer@4011c000 { + compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; + reg = <0x4011c000 0x3000>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + stm1: timer@40120000 { + compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; + reg = <0x40120000 0x3000>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + stm2: timer@40124000 { + compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; + reg = <0x40124000 0x3000>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + stm3: timer@40128000 { + compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; + reg = <0x40128000 0x3000>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + edma0: dma-controller@40144000 { compatible = "nxp,s32g3-edma", "nxp,s32g2-edma"; reg = <0x40144000 0x24000>, @@ -542,6 +617,65 @@ status = "disabled"; }; + swt4: watchdog@40200000 { + compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg = <0x40200000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt5: watchdog@40204000 { + compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg = <0x40204000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt6: watchdog@40208000 { + compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg = <0x40208000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt7: watchdog@4020C000 { + compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg = <0x4020C000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + stm4: timer@4021c000 { + compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; + reg = <0x4021c000 0x3000>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + stm5: timer@40220000 { + compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; + reg = <0x40220000 0x3000>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + stm6: timer@40224000 { + compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; + reg = <0x40224000 0x3000>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + edma1: dma-controller@40244000 { compatible = "nxp,s32g3-edma", "nxp,s32g2-edma"; reg = <0x40244000 0x24000>, @@ -670,6 +804,74 @@ status = "disabled"; }; + swt8: watchdog@40500000 { + compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg = <40500000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt9: watchdog@40504000 { + compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg = <0x40504000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt10: watchdog@40508000 { + compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg = <0x40508000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt11: watchdog@4050c000 { + compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg = <0x4050c000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + stm8: timer@40520000 { + compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; + reg = <0x40520000 0x3000>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + stm9: timer@40524000 { + compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; + reg = <0x40524000 0x3000>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + stm10: timer@40528000 { + compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; + reg = <0x40528000 0x3000>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + stm11: timer@4052c000 { + compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; + reg = <0x4052c000 0x3000>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + gic: interrupt-controller@50800000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; diff --git a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts index 802f543cae4a..e94f70ad82d9 100644 --- a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts +++ b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts @@ -40,6 +40,42 @@ status = "okay"; }; +&stm0 { + status = "okay"; +}; + +&stm1 { + status = "okay"; +}; + +&stm2 { + status = "okay"; +}; + +&stm3 { + status = "okay"; +}; + +&stm4 { + status = "okay"; +}; + +&stm5 { + status = "okay"; +}; + +&stm6 { + status = "okay"; +}; + +&stm8 { + status = "okay"; +}; + +&swt0 { + status = "okay"; +}; + &i2c4 { current-sensor@40 { compatible = "ti,ina231"; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index 7d9394a04302..04e99cd7e74b 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -486,5 +486,341 @@ clocks = <&qspi_clk>; status = "disabled"; }; + + gmac0: ethernet@10810000 { + compatible = "altr,socfpga-stmmac-agilex5", + "snps,dwxgmac-2.10"; + reg = <0x10810000 0x3500>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; + reset-names = "stmmaceth", "ahb"; + clocks = <&clkmgr AGILEX5_EMAC0_CLK>, + <&clkmgr AGILEX5_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; + mac-address = [00 00 00 00 00 00]; + tx-fifo-depth = <32768>; + rx-fifo-depth = <16384>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <64>; + snps,axi-config = <&stmmac_axi_emac0_setup>; + snps,mtl-rx-config = <&mtl_rx_emac0_setup>; + snps,mtl-tx-config = <&mtl_tx_emac0_setup>; + snps,pbl = <32>; + snps,tso; + altr,sysmgr-syscon = <&sysmgr 0x44 0>; + snps,clk-csr = <0>; + status = "disabled"; + + stmmac_axi_emac0_setup: stmmac-axi-config { + snps,wr_osr_lmt = <31>; + snps,rd_osr_lmt = <31>; + snps,blen = <0 0 0 32 16 8 4>; + }; + + mtl_rx_emac0_setup: rx-queues-config { + snps,rx-queues-to-use = <8>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x2>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x3>; + }; + queue4 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x4>; + }; + queue5 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x5>; + }; + queue6 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x6>; + }; + queue7 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x7>; + }; + }; + + mtl_tx_emac0_setup: tx-queues-config { + snps,tx-queues-to-use = <8>; + snps,tx-sched-wrr; + queue0 { + snps,weight = <0x09>; + snps,dcb-algorithm; + }; + queue1 { + snps,weight = <0x0A>; + snps,dcb-algorithm; + }; + queue2 { + snps,weight = <0x0B>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue3 { + snps,weight = <0x0C>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue4 { + snps,weight = <0x0D>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue5 { + snps,weight = <0x0E>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue6 { + snps,weight = <0x0F>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue7 { + snps,weight = <0x10>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + }; + }; + + gmac1: ethernet@10820000 { + compatible = "altr,socfpga-stmmac-agilex5", + "snps,dwxgmac-2.10"; + reg = <0x10820000 0x3500>; + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; + reset-names = "stmmaceth", "ahb"; + clocks = <&clkmgr AGILEX5_EMAC1_CLK>, + <&clkmgr AGILEX5_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; + mac-address = [00 00 00 00 00 00]; + tx-fifo-depth = <32768>; + rx-fifo-depth = <16384>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <64>; + snps,axi-config = <&stmmac_axi_emac1_setup>; + snps,mtl-rx-config = <&mtl_rx_emac1_setup>; + snps,mtl-tx-config = <&mtl_tx_emac1_setup>; + snps,pbl = <32>; + snps,tso; + altr,sysmgr-syscon = <&sysmgr 0x48 0>; + snps,clk-csr = <0>; + status = "disabled"; + + stmmac_axi_emac1_setup: stmmac-axi-config { + snps,wr_osr_lmt = <31>; + snps,rd_osr_lmt = <31>; + snps,blen = <0 0 0 32 16 8 4>; + }; + + mtl_rx_emac1_setup: rx-queues-config { + snps,rx-queues-to-use = <8>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x2>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x3>; + }; + queue4 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x4>; + }; + queue5 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x5>; + }; + queue6 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x6>; + }; + queue7 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x7>; + }; + }; + + mtl_tx_emac1_setup: tx-queues-config { + snps,tx-queues-to-use = <8>; + snps,tx-sched-wrr; + queue0 { + snps,weight = <0x09>; + snps,dcb-algorithm; + }; + queue1 { + snps,weight = <0x0A>; + snps,dcb-algorithm; + }; + queue2 { + snps,weight = <0x0B>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue3 { + snps,weight = <0x0C>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue4 { + snps,weight = <0x0D>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue5 { + snps,weight = <0x0E>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue6 { + snps,weight = <0x0F>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue7 { + snps,weight = <0x10>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + }; + }; + + gmac2: ethernet@10830000 { + compatible = "altr,socfpga-stmmac-agilex5", + "snps,dwxgmac-2.10"; + reg = <0x10830000 0x3500>; + interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; + reset-names = "stmmaceth", "ahb"; + clocks = <&clkmgr AGILEX5_EMAC2_CLK>, + <&clkmgr AGILEX5_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; + mac-address = [00 00 00 00 00 00]; + tx-fifo-depth = <32768>; + rx-fifo-depth = <16384>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <64>; + snps,axi-config = <&stmmac_axi_emac2_setup>; + snps,mtl-rx-config = <&mtl_rx_emac2_setup>; + snps,mtl-tx-config = <&mtl_tx_emac2_setup>; + snps,pbl = <32>; + snps,tso; + altr,sysmgr-syscon = <&sysmgr 0x4c 0>; + snps,clk-csr = <0>; + status = "disabled"; + + stmmac_axi_emac2_setup: stmmac-axi-config { + snps,wr_osr_lmt = <31>; + snps,rd_osr_lmt = <31>; + snps,blen = <0 0 0 32 16 8 4>; + }; + + mtl_rx_emac2_setup: rx-queues-config { + snps,rx-queues-to-use = <8>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x2>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x3>; + }; + queue4 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x4>; + }; + queue5 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x5>; + }; + queue6 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x6>; + }; + queue7 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x7>; + }; + }; + + mtl_tx_emac2_setup: tx-queues-config { + snps,tx-queues-to-use = <8>; + snps,tx-sched-wrr; + queue0 { + snps,weight = <0x09>; + snps,dcb-algorithm; + }; + queue1 { + snps,weight = <0x0A>; + snps,dcb-algorithm; + }; + queue2 { + snps,weight = <0x0B>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue3 { + snps,weight = <0x0C>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue4 { + snps,weight = <0x0D>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue5 { + snps,weight = <0x0E>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue6 { + snps,weight = <0x0F>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue7 { + snps,weight = <0x10>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts index d3b913b7902c..e9776e1cdc9a 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts @@ -10,6 +10,9 @@ aliases { serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; }; chosen { @@ -37,6 +40,23 @@ status = "okay"; }; +&gmac2 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <&emac2_phy0>; + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + emac2_phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + &gpio1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile index 40e5ac6cd468..a774bc74a0a0 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 # Mvebu SoC Family +dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-atlas-v5.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-eDPU.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin.dtb diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi index 605f5be1538c..4878773883c9 100644 --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi @@ -322,7 +322,7 @@ nand: nand-controller@805b0000 { compatible = "marvell,ac5-nand-controller"; - reg = <0x0 0x805b0000 0x0 0x00000054>; + reg = <0x0 0x805b0000 0x0 0x00000054>; #address-cells = <0x1>; #size-cells = <0x0>; interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-atlas-v5.dts b/arch/arm64/boot/dts/marvell/armada-3720-atlas-v5.dts new file mode 100644 index 000000000000..070d10a705bb --- /dev/null +++ b/arch/arm64/boot/dts/marvell/armada-3720-atlas-v5.dts @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for RIPE Atlas Probe v5 + * 2025 by Marek Behún <kabel@kernel.org> + */ + +/dts-v1/; + +#include <dt-bindings/bus/moxtet.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include "armada-372x.dtsi" + +/ { + model = "RIPE Atlas Probe v5"; + compatible = "ripe,atlas-v5", "marvell,armada3720", + "marvell,armada3710"; + + aliases { + ethernet0 = ð0; + mmc0 = &sdhci0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x20000000>; + }; + + leds { + compatible = "gpio-leds"; + + led { + gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>; + function = LED_FUNCTION_ACTIVITY; + color = <LED_COLOR_ID_RED>; + linux,default-trigger = "default-on"; + }; + }; + + vsdc_reg: vsdc-reg { + compatible = "regulator-gpio"; + regulator-name = "vsdc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + + gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1 + 3300000 0x0>; + enable-active-high; + }; + + firmware { + armada-3700-rwtm { + compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm"; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +ð0 { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii-id"; + phy-handle = <&phy1>; + status = "okay"; +}; + +&sdhci0 { + non-removable; + bus-width = <4>; + mmc-ddr-1_8v; + mmc-hs400-1_8v; + sd-uhs-sdr104; + marvell,xenon-emmc; + marvell,xenon-tun-count = <9>; + marvell,pad-type = "fixed-1-8v"; + vqmmc-supply = <&vsdc_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&mmc_pins>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + mmccard: mmccard@0 { + compatible = "mmc-card"; + reg = <0>; + }; +}; + +&mdio { + pinctrl-names = "default"; + pinctrl-0 = <&smi_pins>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 75b0fdc3efb2..c612317043ea 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -524,6 +524,7 @@ pcie_intc: interrupt-controller { interrupt-controller; #interrupt-cells = <1>; + #address-cells = <0>; }; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi index 0d4a5fd9503f..f2d278d171eb 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi @@ -345,11 +345,13 @@ /* CPS Lane 1 - U32 */ sata-port@0 { phys = <&cp1_comphy1 0>; + status = "okay"; }; /* CPS Lane 3 - U31 */ sata-port@1 { phys = <&cp1_comphy3 1>; + status = "okay"; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi index a057e119492f..d9d409eac259 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi @@ -202,6 +202,7 @@ CP11X_LABEL(icu_nsr): interrupt-controller@10 { compatible = "marvell,cp110-icu-nsr"; reg = <0x10 0x20>; + #address-cells = <0>; #interrupt-cells = <2>; interrupt-controller; msi-parent = <&gicp>; diff --git a/arch/arm64/boot/dts/marvell/cn9130-cf.dtsi b/arch/arm64/boot/dts/marvell/cn9130-cf.dtsi index ad0ab34b6602..bd42bfbe408b 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-cf.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-cf.dtsi @@ -152,11 +152,12 @@ /* SRDS #0 - SATA on M.2 connector */ &cp0_sata0 { - phys = <&cp0_comphy0 1>; status = "okay"; - /* only port 1 is available */ - /delete-node/ sata-port@0; + sata-port@1 { + phys = <&cp0_comphy0 1>; + status = "okay"; + }; }; /* microSD */ diff --git a/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi b/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi index a997bbabedd8..f95202decfce 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi @@ -61,6 +61,8 @@ pinctrl-0 = <&ap_mmc0_pins>; pinctrl-names = "default"; vqmmc-supply = <&v_1_8>; + no-sdio; + non-removable; status = "okay"; }; diff --git a/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts b/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts index 47234d0858dd..338853d3b179 100644 --- a/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts +++ b/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts @@ -563,11 +563,13 @@ /* SRDS #1 - SATA on M.2 (J44) */ &cp1_sata0 { - phys = <&cp1_comphy1 0>; status = "okay"; /* only port 0 is available */ - /delete-node/ sata-port@1; + sata-port@0 { + phys = <&cp1_comphy1 0>; + status = "okay"; + }; }; &cp1_syscon0 { diff --git a/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts b/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts index 0f53745a6fa0..5cf83d8ca1f5 100644 --- a/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts +++ b/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts @@ -413,7 +413,13 @@ /* SRDS #0,#1,#2,#3 - PCIe */ &cp0_pcie0 { num-lanes = <4>; - phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>; + /* + * The mvebu-comphy driver does not currently know how to pass correct + * lane-count to ATF while configuring the serdes lanes. + * Rely on bootloader configuration only. + * + * phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>; + */ status = "okay"; }; @@ -475,7 +481,13 @@ /* SRDS #0,#1 - PCIe */ &cp1_pcie0 { num-lanes = <2>; - phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>; + /* + * The mvebu-comphy driver does not currently know how to pass correct + * lane-count to ATF while configuring the serdes lanes. + * Rely on bootloader configuration only. + * + * phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>; + */ status = "okay"; }; @@ -512,10 +524,9 @@ status = "okay"; /* only port 1 is available */ - /delete-node/ sata-port@0; - sata-port@1 { phys = <&cp1_comphy3 1>; + status = "okay"; }; }; @@ -559,7 +570,7 @@ }; &cp2_ethernet { - status = "okay"; + status = "okay"; }; /* SRDS #2 - 5GE */ @@ -572,7 +583,7 @@ }; &cp2_gpio1 { - pinctrl-names= "default"; + pinctrl-names = "default"; pinctrl-0 = <&cp2_rsvd9_pins>; /* J21 */ @@ -631,9 +642,8 @@ status = "okay"; /* only port 1 is available */ - /delete-node/ sata-port@0; - sata-port@1 { + status = "okay"; phys = <&cp2_comphy3 1>; }; }; diff --git a/arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi b/arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi index afc041c1c448..91ba5f7dc9b4 100644 --- a/arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi @@ -137,6 +137,14 @@ pinctrl-0 = <&ap_mmc0_pins>; pinctrl-names = "default"; vqmmc-supply = <&v_1_8>; + /* + * Not stable in HS modes - phy needs "more calibration", so disable + * UHS (by preventing voltage switch), SDR104, SDR50 and DDR50 modes. + */ + no-1-8-v; + no-sd; + no-sdio; + non-removable; status = "okay"; }; @@ -442,7 +450,7 @@ reg = <0>; compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; spi-max-frequency = <10000000>; - pinctrl-names = "default"; + pinctrl-names = "default"; pinctrl-0 = <&cp1_tpm_irq_pins>; interrupt-parent = <&cp1_gpio1>; interrupts = <17 IRQ_TYPE_LEVEL_LOW>; diff --git a/arch/arm64/boot/dts/mediatek/mt6331.dtsi b/arch/arm64/boot/dts/mediatek/mt6331.dtsi index d89858c73ab1..243afbffa21f 100644 --- a/arch/arm64/boot/dts/mediatek/mt6331.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6331.dtsi @@ -6,12 +6,12 @@ #include <dt-bindings/input/input.h> &pwrap { - pmic: mt6331 { + pmic: pmic { compatible = "mediatek,mt6331"; interrupt-controller; #interrupt-cells = <2>; - mt6331regulator: mt6331regulator { + mt6331regulator: regulators { compatible = "mediatek,mt6331-regulator"; mt6331_vdvfs11_reg: buck-vdvfs11 { @@ -258,7 +258,7 @@ }; mt6331_vdig18_reg: ldo-vdig18 { - regulator-name = "dvdd18_dig"; + regulator-name = "vdig18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-ramp-delay = <0>; @@ -266,11 +266,11 @@ }; }; - mt6331rtc: mt6331rtc { + mt6331rtc: rtc { compatible = "mediatek,mt6331-rtc"; }; - mt6331keys: mt6331keys { + mt6331keys: keys { compatible = "mediatek,mt6331-keys"; power { linux,keycodes = <KEY_POWER>; diff --git a/arch/arm64/boot/dts/mediatek/mt6755.dtsi b/arch/arm64/boot/dts/mediatek/mt6755.dtsi index b55d3fac9bd4..8da5c0a56a02 100644 --- a/arch/arm64/boot/dts/mediatek/mt6755.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6755.dtsi @@ -98,7 +98,7 @@ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; }; - sysirq: intpol-controller@10200620 { + sysirq: interrupt-controller@10200620 { compatible = "mediatek,mt6755-sysirq", "mediatek,mt6577-sysirq"; interrupt-controller; diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi index 5c579e88e749..70f3375916e8 100644 --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi @@ -138,7 +138,7 @@ }; - sysirq: intpol-controller@c53a650 { + sysirq: interrupt-controller@c53a650 { compatible = "mediatek,mt6779-sysirq", "mediatek,mt6577-sysirq"; interrupt-controller; diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts index 91de920c2245..fccb948cfa45 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts +++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts @@ -212,7 +212,7 @@ &mmc0 { /* eMMC controller */ - mediatek,latch-ck = <0x14>; /* hs400 */ + mediatek,latch-ck = <4>; /* hs400 */ mediatek,hs200-cmd-int-delay = <1>; mediatek,hs400-cmd-int-delay = <1>; mediatek,hs400-ds-dly3 = <0x1a>; @@ -227,6 +227,8 @@ &mmc1 { /* MicroSD card slot */ + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; vmmc-supply = <&mt6331_vmc_reg>; vqmmc-supply = <&mt6331_vmch_reg>; status = "okay"; @@ -234,6 +236,8 @@ &mmc2 { /* SDIO WiFi on MMC2 */ + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_default>; vmmc-supply = <&mt6331_vmc_reg>; vqmmc-supply = <&mt6331_vmch_reg>; status = "okay"; @@ -311,6 +315,40 @@ }; }; + mmc1_pins_default: microsd-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO171__FUNC_MSDC1_DAT0>, + <PINMUX_GPIO172__FUNC_MSDC1_DAT1>, + <PINMUX_GPIO173__FUNC_MSDC1_DAT2>, + <PINMUX_GPIO174__FUNC_MSDC1_DAT3>, + <PINMUX_GPIO170__FUNC_MSDC1_CMD>; + input-enable; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-clk { + pinmux = <PINMUX_GPIO175__FUNC_MSDC1_CLK>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + }; + + mmc2_pins_default: sdio-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO100__FUNC_MSDC2_DAT0>, + <PINMUX_GPIO101__FUNC_MSDC2_DAT1>, + <PINMUX_GPIO102__FUNC_MSDC2_DAT2>, + <PINMUX_GPIO103__FUNC_MSDC2_DAT3>, + <PINMUX_GPIO105__FUNC_MSDC2_CMD>; + input-enable; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-clk { + pinmux = <PINMUX_GPIO104__FUNC_MSDC2_CLK>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + }; + nfc_pins: nfc-pins { pins-irq { pinmux = <PINMUX_GPIO3__FUNC_GPIO3>; diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index e5e269a660b1..58833e5135c8 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -404,7 +404,7 @@ clock-names = "spi", "wrap"; }; - sysirq: intpol-controller@10200620 { + sysirq: interrupt-controller@10200620 { compatible = "mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq"; interrupt-controller; @@ -427,6 +427,7 @@ clocks = <&infracfg CLK_INFRA_M4U>; clock-names = "bclk"; interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_LOW>; + mediatek,infracfg = <&infracfg>; mediatek,larbs = <&larb0 &larb1 &larb2 &larb3>; power-domains = <&spm MT6795_POWER_DOMAIN_MM>; #iommu-cells = <1>; diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi b/arch/arm64/boot/dts/mediatek/mt6797.dtsi index 0e9d11b4585b..8ac98a378fd6 100644 --- a/arch/arm64/boot/dts/mediatek/mt6797.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6797.dtsi @@ -135,71 +135,71 @@ gpio-controller; #gpio-cells = <2>; - uart0_pins_a: uart0 { - pins0 { + uart0_pins_a: uart0-pins { + pins-bus { pinmux = <MT6797_GPIO234__FUNC_UTXD0>, <MT6797_GPIO235__FUNC_URXD0>; }; }; - uart1_pins_a: uart1 { - pins1 { + uart1_pins_a: uart1-pins { + pins-bus { pinmux = <MT6797_GPIO232__FUNC_URXD1>, <MT6797_GPIO233__FUNC_UTXD1>; }; }; - i2c0_pins_a: i2c0 { - pins0 { + i2c0_pins_a: i2c0-pins { + pins-bus { pinmux = <MT6797_GPIO37__FUNC_SCL0_0>, <MT6797_GPIO38__FUNC_SDA0_0>; }; }; - i2c1_pins_a: i2c1 { - pins1 { + i2c1_pins_a: i2c1-pins { + pins-bus { pinmux = <MT6797_GPIO55__FUNC_SCL1_0>, <MT6797_GPIO56__FUNC_SDA1_0>; }; }; - i2c2_pins_a: i2c2 { - pins2 { + i2c2_pins_a: i2c2-pins { + pins-bus { pinmux = <MT6797_GPIO96__FUNC_SCL2_0>, <MT6797_GPIO95__FUNC_SDA2_0>; }; }; - i2c3_pins_a: i2c3 { - pins3 { + i2c3_pins_a: i2c3-pins { + pins-bus { pinmux = <MT6797_GPIO75__FUNC_SDA3_0>, <MT6797_GPIO74__FUNC_SCL3_0>; }; }; - i2c4_pins_a: i2c4 { - pins4 { + i2c4_pins_a: i2c4-pins { + pins-bus { pinmux = <MT6797_GPIO238__FUNC_SDA4_0>, <MT6797_GPIO239__FUNC_SCL4_0>; }; }; - i2c5_pins_a: i2c5 { - pins5 { + i2c5_pins_a: i2c5-pins { + pins-bus { pinmux = <MT6797_GPIO240__FUNC_SDA5_0>, <MT6797_GPIO241__FUNC_SCL5_0>; }; }; - i2c6_pins_a: i2c6 { - pins6 { + i2c6_pins_a: i2c6-pins { + pins-bus { pinmux = <MT6797_GPIO152__FUNC_SDA6_0>, <MT6797_GPIO151__FUNC_SCL6_0>; }; }; - i2c7_pins_a: i2c7 { - pins7 { + i2c7_pins_a: i2c7-pins { + pins-bus { pinmux = <MT6797_GPIO154__FUNC_SDA7_0>, <MT6797_GPIO153__FUNC_SCL7_0>; }; @@ -228,7 +228,7 @@ #clock-cells = <1>; }; - sysirq: intpol-controller@10200620 { + sysirq: interrupt-controller@10200620 { compatible = "mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq"; interrupt-controller; @@ -285,7 +285,6 @@ i2c0: i2c@11007000 { compatible = "mediatek,mt6797-i2c", "mediatek,mt6577-i2c"; - id = <0>; reg = <0 0x11007000 0 0x1000>, <0 0x11000100 0 0x80>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; @@ -301,7 +300,6 @@ i2c1: i2c@11008000 { compatible = "mediatek,mt6797-i2c", "mediatek,mt6577-i2c"; - id = <1>; reg = <0 0x11008000 0 0x1000>, <0 0x11000180 0 0x80>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; @@ -317,7 +315,6 @@ i2c8: i2c@11009000 { compatible = "mediatek,mt6797-i2c", "mediatek,mt6577-i2c"; - id = <8>; reg = <0 0x11009000 0 0x1000>, <0 0x11000200 0 0x80>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; @@ -334,7 +331,6 @@ i2c9: i2c@1100d000 { compatible = "mediatek,mt6797-i2c", "mediatek,mt6577-i2c"; - id = <9>; reg = <0 0x1100d000 0 0x1000>, <0 0x11000280 0 0x80>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; @@ -351,7 +347,6 @@ i2c6: i2c@1100e000 { compatible = "mediatek,mt6797-i2c", "mediatek,mt6577-i2c"; - id = <6>; reg = <0 0x1100e000 0 0x1000>, <0 0x11000500 0 0x80>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; @@ -367,7 +362,6 @@ i2c7: i2c@11010000 { compatible = "mediatek,mt6797-i2c", "mediatek,mt6577-i2c"; - id = <7>; reg = <0 0x11010000 0 0x1000>, <0 0x11000580 0 0x80>; interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; @@ -383,7 +377,6 @@ i2c4: i2c@11011000 { compatible = "mediatek,mt6797-i2c", "mediatek,mt6577-i2c"; - id = <4>; reg = <0 0x11011000 0 0x1000>, <0 0x11000300 0 0x80>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>; @@ -399,7 +392,6 @@ i2c2: i2c@11013000 { compatible = "mediatek,mt6797-i2c", "mediatek,mt6577-i2c"; - id = <2>; reg = <0 0x11013000 0 0x1000>, <0 0x11000400 0 0x80>; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>; @@ -416,7 +408,6 @@ i2c3: i2c@11014000 { compatible = "mediatek,mt6797-i2c", "mediatek,mt6577-i2c"; - id = <3>; reg = <0 0x11014000 0 0x1000>, <0 0x11000480 0 0x80>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>; @@ -433,7 +424,6 @@ i2c5: i2c@1101c000 { compatible = "mediatek,mt6797-i2c", "mediatek,mt6577-i2c"; - id = <5>; reg = <0 0x1101c000 0 0x1000>, <0 0x11000380 0 0x80>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 5cbea9cd411f..277c11247c13 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -76,7 +76,7 @@ #reset-cells = <1>; }; - clock-controller@1001e000 { + apmixedsys: clock-controller@1001e000 { compatible = "mediatek,mt7981-apmixedsys"; reg = <0 0x1001e000 0 0x1000>; #clock-cells = <1>; @@ -184,6 +184,31 @@ status = "disabled"; }; + thermal@1100c800 { + compatible = "mediatek,mt7981-thermal", + "mediatek,mt7986-thermal"; + reg = <0 0x1100c800 0 0x800>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg CLK_INFRA_THERM_CK>, + <&infracfg CLK_INFRA_ADC_26M_CK>; + clock-names = "therm", "auxadc"; + nvmem-cells = <&thermal_calibration>; + nvmem-cell-names = "calibration-data"; + #thermal-sensor-cells = <1>; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + }; + + auxadc: adc@1100d000 { + compatible = "mediatek,mt7981-auxadc", + "mediatek,mt7986-auxadc"; + reg = <0 0x1100d000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_ADC_26M_CK>; + clock-names = "main"; + #io-channel-cells = <1>; + status = "disabled"; + }; + pio: pinctrl@11d00000 { compatible = "mediatek,mt7981-pinctrl"; reg = <0 0x11d00000 0 0x1000>, @@ -211,6 +236,10 @@ reg = <0 0x11f20000 0 0x1000>; #address-cells = <1>; #size-cells = <1>; + + thermal_calibration: thermal-calib@274 { + reg = <0x274 0xc>; + }; }; clock-controller@15000000 { diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-acelink-ew-7886cax.dts b/arch/arm64/boot/dts/mediatek/mt7986a-acelink-ew-7886cax.dts index 08b3b0827436..30805a610262 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-acelink-ew-7886cax.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-acelink-ew-7886cax.dts @@ -98,8 +98,6 @@ flash@0 { compatible = "spi-nand"; reg = <0>; - #address-cells = <1>; - #size-cells = <1>; spi-max-frequency = <52000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts index ed79ad1ae871..e7654dc9a1c9 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts @@ -64,23 +64,19 @@ }; /* i2c of the left SFP cage (wan) */ - i2c_sfp1: i2c-gpio-0 { + i2c_sfp1: i2c-0 { compatible = "i2c-gpio"; sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; }; /* i2c of the right SFP cage (lan) */ - i2c_sfp2: i2c-gpio-1 { + i2c_sfp2: i2c-1 { compatible = "i2c-gpio"; sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; }; leds { @@ -204,8 +200,9 @@ compatible = "mediatek,mt7531"; reg = <31>; interrupt-controller; + interrupt-parent = <&pio>; + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; - interrupts-extended = <&pio 66 IRQ_TYPE_LEVEL_HIGH>; reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index 559990dcd1d1..a8972330a7b8 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -428,16 +428,16 @@ }; }; - pcie_phy: t-phy { + pcie_phy: t-phy@11c00000 { compatible = "mediatek,mt7986-tphy", "mediatek,generic-tphy-v2"; - ranges; - #address-cells = <2>; - #size-cells = <2>; + ranges = <0 0 0x11c00000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; status = "disabled"; - pcie_port: pcie-phy@11c00000 { - reg = <0 0x11c00000 0 0x20000>; + pcie_port: pcie-phy@0 { + reg = <0 0x20000>; clocks = <&clk40m>; clock-names = "ref"; #phy-cells = <1>; @@ -523,11 +523,17 @@ eth: ethernet@15100000 { compatible = "mediatek,mt7986-eth"; - reg = <0 0x15100000 0 0x80000>; + reg = <0 0x15100000 0 0x40000>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "fe0", "fe1", "fe2", "fe3", "pdma0", + "pdma1", "pdma2", "pdma3"; clocks = <ðsys CLK_ETH_FE_EN>, <ðsys CLK_ETH_GP2_EN>, <ðsys CLK_ETH_GP1_EN>, @@ -553,6 +559,7 @@ <&topckgen CLK_TOP_SGM_325M_SEL>; assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, <&apmixedsys CLK_APMIXED_SGMPLL>; + sram = <ð_sram>; #address-cells = <1>; #size-cells = <0>; mediatek,ethsys = <ðsys>; @@ -562,6 +569,15 @@ status = "disabled"; }; + /*15100000+0x40000*/ + eth_sram: sram@15140000 { + compatible = "mmio-sram"; + reg = <0 0x15140000 0 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x15140000 0 0x40000>; + }; + wo_ccif0: syscon@151a5000 { compatible = "mediatek,mt7986-wo-ccif", "syscon"; reg = <0 0x151a5000 0 0x1000>; diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts index 53de9c113f60..6f0c81e3fd94 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts @@ -9,3 +9,14 @@ model = "Banana Pi BPI-R4 (1x SFP+, 1x 2.5GbE)"; chassis-type = "embedded"; }; + +&gmac1 { + phy = <&int_2p5g_phy>; + phy-mode = "internal"; + status = "okay"; +}; + +&int_2p5g_phy { + pinctrl-0 = <&i2p5gbe_led0_pins>; + pinctrl-names = "i2p5gbe-led"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts index 36bd1ef2efab..4b3796ba82e3 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts @@ -8,6 +8,25 @@ compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; model = "Banana Pi BPI-R4 (2x SFP+)"; chassis-type = "embedded"; + + /* SFP2 cage (LAN) */ + sfp2: sfp2 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp2>; + maximum-power-milliwatt = <3000>; + + los-gpios = <&pio 2 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&pio 83 GPIO_ACTIVE_LOW>; + rate-select0-gpios = <&pio 3 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&pio 0 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&pio 1 GPIO_ACTIVE_HIGH>; + }; +}; + +&gmac1 { + managed = "in-band-status"; + phy-mode = "usxgmii"; + sfp = <&sfp2>; }; &pca9545 { diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi index 5fd222df440d..0ff69dae45d3 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi @@ -5,10 +5,17 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/leds/common.h> #include <dt-bindings/regulator/richtek,rt5190a-regulator.h> +#include <dt-bindings/leds/common.h> #include "mt7988a.dtsi" / { + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -58,6 +65,19 @@ regulator-boot-on; regulator-always-on; }; + + /* SFP1 cage (WAN) */ + sfp1: sfp1 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp1>; + maximum-power-milliwatt = <3000>; + + los-gpios = <&pio 54 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>; + rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>; + }; }; &cci { @@ -128,6 +148,72 @@ }; }; +&gmac2 { + managed = "in-band-status"; + phy-mode = "usxgmii"; + sfp = <&sfp1>; +}; + +&gsw_phy0 { + pinctrl-0 = <&gbe0_led0_pins>; + pinctrl-names = "gbe-led"; +}; + +&gsw_phy0_led0 { + function = LED_FUNCTION_WAN; + color = <LED_COLOR_ID_GREEN>; + status = "okay"; +}; + +&gsw_port0 { + label = "wan"; +}; + +&gsw_phy1 { + pinctrl-0 = <&gbe1_led0_pins>; + pinctrl-names = "gbe-led"; +}; + +&gsw_phy1_led0 { + function = LED_FUNCTION_LAN; + color = <LED_COLOR_ID_GREEN>; + status = "okay"; +}; + +&gsw_port1 { + label = "lan1"; +}; + +&gsw_phy2 { + pinctrl-0 = <&gbe2_led0_pins>; + pinctrl-names = "gbe-led"; +}; + +&gsw_phy2_led0 { + function = LED_FUNCTION_LAN; + color = <LED_COLOR_ID_GREEN>; + status = "okay"; +}; + +&gsw_port2 { + label = "lan2"; +}; + +&gsw_phy3 { + pinctrl-0 = <&gbe3_led0_pins>; + pinctrl-names = "gbe-led"; +}; + +&gsw_phy3_led0 { + function = LED_FUNCTION_LAN; + color = <LED_COLOR_ID_GREEN>; + status = "okay"; +}; + +&gsw_port3 { + label = "lan3"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 560ec86dbec0..366203a72d6d 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -680,7 +680,28 @@ }; }; - clock-controller@11f40000 { + xfi_tphy0: phy@11f20000 { + compatible = "mediatek,mt7988-xfi-tphy"; + reg = <0 0x11f20000 0 0x10000>; + clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, + <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>; + clock-names = "xfipll", "topxtal"; + resets = <&watchdog 14>; + mediatek,usxgmii-performance-errata; + #phy-cells = <0>; + }; + + xfi_tphy1: phy@11f30000 { + compatible = "mediatek,mt7988-xfi-tphy"; + reg = <0 0x11f30000 0 0x10000>; + clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, + <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>; + clock-names = "xfipll", "topxtal"; + resets = <&watchdog 15>; + #phy-cells = <0>; + }; + + xfi_pll: clock-controller@11f40000 { compatible = "mediatek,mt7988-xfi-pll"; reg = <0 0x11f40000 0 0x1000>; resets = <&watchdog 16>; @@ -714,19 +735,277 @@ }; }; - clock-controller@15000000 { + ethsys: clock-controller@15000000 { compatible = "mediatek,mt7988-ethsys", "syscon"; reg = <0 0x15000000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; - clock-controller@15031000 { + switch: switch@15020000 { + compatible = "mediatek,mt7988-switch"; + reg = <0 0x15020000 0 0x8000>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; + resets = <ðwarp MT7988_ETHWARP_RST_SWITCH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + gsw_port0: port@0 { + reg = <0>; + phy-handle = <&gsw_phy0>; + phy-mode = "internal"; + }; + + gsw_port1: port@1 { + reg = <1>; + phy-handle = <&gsw_phy1>; + phy-mode = "internal"; + }; + + gsw_port2: port@2 { + reg = <2>; + phy-handle = <&gsw_phy2>; + phy-mode = "internal"; + }; + + gsw_port3: port@3 { + reg = <3>; + phy-handle = <&gsw_phy3>; + phy-mode = "internal"; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "internal"; + + fixed-link { + speed = <10000>; + full-duplex; + pause; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + mediatek,pio = <&pio>; + + gsw_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + interrupts = <0>; + nvmem-cells = <&phy_calibration_p0>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy0_led0: led@0 { + reg = <0>; + status = "disabled"; + }; + + gsw_phy0_led1: led@1 { + reg = <1>; + status = "disabled"; + }; + }; + }; + + gsw_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + interrupts = <1>; + nvmem-cells = <&phy_calibration_p1>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy1_led0: led@0 { + reg = <0>; + status = "disabled"; + }; + + gsw_phy1_led1: led@1 { + reg = <1>; + status = "disabled"; + }; + }; + }; + + gsw_phy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + interrupts = <2>; + nvmem-cells = <&phy_calibration_p2>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy2_led0: led@0 { + reg = <0>; + status = "disabled"; + }; + + gsw_phy2_led1: led@1 { + reg = <1>; + status = "disabled"; + }; + }; + }; + + gsw_phy3: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + interrupts = <3>; + nvmem-cells = <&phy_calibration_p3>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy3_led0: led@0 { + reg = <0>; + status = "disabled"; + }; + + gsw_phy3_led1: led@1 { + reg = <1>; + status = "disabled"; + }; + }; + }; + }; + }; + + ethwarp: clock-controller@15031000 { compatible = "mediatek,mt7988-ethwarp"; reg = <0 0x15031000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; + + eth: ethernet@15100000 { + compatible = "mediatek,mt7988-eth"; + reg = <0 0x15100000 0 0x40000>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "fe0", "fe1", "fe2", "fe3", "pdma0", + "pdma1", "pdma2", "pdma3"; + clocks = <ðsys CLK_ETHDMA_CRYPT0_EN>, + <ðsys CLK_ETHDMA_FE_EN>, + <ðsys CLK_ETHDMA_GP2_EN>, + <ðsys CLK_ETHDMA_GP1_EN>, + <ðsys CLK_ETHDMA_GP3_EN>, + <ðwarp CLK_ETHWARP_WOCPU2_EN>, + <ðwarp CLK_ETHWARP_WOCPU1_EN>, + <ðwarp CLK_ETHWARP_WOCPU0_EN>, + <ðsys CLK_ETHDMA_ESW_EN>, + <&topckgen CLK_TOP_ETH_GMII_SEL>, + <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>, + <&topckgen CLK_TOP_ETH_SYS_200M_SEL>, + <&topckgen CLK_TOP_ETH_SYS_SEL>, + <&topckgen CLK_TOP_ETH_XGMII_SEL>, + <&topckgen CLK_TOP_ETH_MII_SEL>, + <&topckgen CLK_TOP_NETSYS_SEL>, + <&topckgen CLK_TOP_NETSYS_500M_SEL>, + <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>, + <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>, + <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>, + <&topckgen CLK_TOP_NETSYS_WARP_SEL>, + <ðsys CLK_ETHDMA_XGP1_EN>, + <ðsys CLK_ETHDMA_XGP2_EN>, + <ðsys CLK_ETHDMA_XGP3_EN>; + clock-names = "crypto", "fe", "gp2", "gp1", "gp3", + "ethwarp_wocpu2", "ethwarp_wocpu1", + "ethwarp_wocpu0", "esw", "top_eth_gmii_sel", + "top_eth_refck_50m_sel", "top_eth_sys_200m_sel", + "top_eth_sys_sel", "top_eth_xgmii_sel", + "top_eth_mii_sel", "top_netsys_sel", + "top_netsys_500m_sel", "top_netsys_pao_2x_sel", + "top_netsys_sync_250m_sel", + "top_netsys_ppefb_250m_sel", + "top_netsys_warp_sel","xgp1", "xgp2", "xgp3"; + assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, + <&topckgen CLK_TOP_NETSYS_GSW_SEL>, + <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>, + <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>, + <&topckgen CLK_TOP_SGM_0_SEL>, + <&topckgen CLK_TOP_SGM_1_SEL>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, + <&topckgen CLK_TOP_NET1PLL_D4>, + <&topckgen CLK_TOP_NET1PLL_D8_D4>, + <&topckgen CLK_TOP_NET1PLL_D8_D4>, + <&apmixedsys CLK_APMIXED_SGMPLL>, + <&apmixedsys CLK_APMIXED_SGMPLL>; + sram = <ð_sram>; + #address-cells = <1>; + #size-cells = <0>; + mediatek,ethsys = <ðsys>; + mediatek,infracfg = <&topmisc>; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "internal"; + + /* Connected to internal switch */ + fixed-link { + speed = <10000>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + status = "disabled"; + }; + + gmac2: mac@2 { + compatible = "mediatek,eth-mac"; + reg = <2>; + status = "disabled"; + }; + + mdio_bus: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + /* internal 2.5G PHY */ + int_2p5g_phy: ethernet-phy@15 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <15>; + }; + }; + }; + + eth_sram: sram@15400000 { + compatible = "mmio-sram"; + reg = <0 0x15400000 0 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x15400000 0 0x200000>; + }; }; thermal-zones { diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi index 586eee79c73c..f69ffcb9792a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi @@ -39,8 +39,8 @@ }; &pio { - da7219_pins: da7219_pins { - pins1 { + da7219_pins: da7219-pins { + pins-intn { pinmux = <PINMUX_GPIO165__FUNC_GPIO165>; input-enable; bias-pull-up; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e.dtsi index 548e22c194a2..c4aedf8cbfcd 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e.dtsi @@ -17,7 +17,7 @@ }; &pio { - ts3a227e_pins: ts3a227e_pins { + ts3a227e_pins: ts3a227e-pins { pins1 { pinmux = <PINMUX_GPIO157__FUNC_GPIO157>; input-enable; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi index 80888bd4ad82..1b74ec171c10 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi @@ -93,11 +93,6 @@ }; }; -&dsi0 { - status = "okay"; - /delete-node/panel@0; -}; - &dsi_out { remote-endpoint = <&anx7625_in>; }; @@ -395,14 +390,14 @@ "", ""; - pp1000_mipibrdg_en: pp1000-mipibrdg-en { + pp1000_mipibrdg_en: pp1000-mipibrdg-en-pins { pins1 { pinmux = <PINMUX_GPIO54__FUNC_GPIO54>; output-low; }; }; - pp1800_mipibrdg_en: pp1800-mipibrdg-en { + pp1800_mipibrdg_en: pp1800-mipibrdg-en-pins { pins1 { pinmux = <PINMUX_GPIO36__FUNC_GPIO36>; output-low; @@ -410,20 +405,20 @@ }; pp3300_panel_pins: pp3300-panel-pins { - panel_3v3_enable: panel-3v3-enable { + panel_3v3_enable: pins-panel-en { pinmux = <PINMUX_GPIO35__FUNC_GPIO35>; output-low; }; }; - ppvarp_lcd_en: ppvarp-lcd-en { + ppvarp_lcd_en: ppvarp-lcd-en-pins { pins1 { pinmux = <PINMUX_GPIO66__FUNC_GPIO66>; output-low; }; }; - ppvarn_lcd_en: ppvarn-lcd-en { + ppvarn_lcd_en: ppvarn-lcd-en-pins { pins1 { pinmux = <PINMUX_GPIO166__FUNC_GPIO166>; output-low; @@ -444,27 +439,27 @@ }; touchscreen_pins: touchscreen-pins { - touch-int-odl { + pins-intn { pinmux = <PINMUX_GPIO155__FUNC_GPIO155>; input-enable; bias-pull-up; }; - touch-rst-l { + pins-rst { pinmux = <PINMUX_GPIO156__FUNC_GPIO156>; output-high; }; }; trackpad_pins: trackpad-pins { - trackpad-int { + pins-intn { pinmux = <PINMUX_GPIO7__FUNC_GPIO7>; input-enable; bias-disable; /* pulled externally */ }; }; - pp3300_mipibrdg_en: pp3300-mipibrdg-en { + pp3300_mipibrdg_en: pp3300-mipibrdg-en-pins { pins1 { pinmux = <PINMUX_GPIO37__FUNC_GPIO37>; output-low; @@ -472,13 +467,13 @@ }; volume_button_pins: volume-button-pins { - voldn-btn-odl { + pins-voldn { pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; input-enable; bias-pull-up; }; - volup-btn-odl { + pins-volup { pinmux = <PINMUX_GPIO5__FUNC_GPIO5>; input-enable; bias-pull-up; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi index ff02f63bac29..d71972c94e42 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi @@ -61,6 +61,33 @@ firmware-name = "nvm_00440302_i2s_eu.bin"; }; +&dsi0 { + #address-cells = <1>; + #size-cells = <0>; + + panel: panel@0 { + /* compatible will be set in board dts */ + reg = <0>; + enable-gpios = <&pio 45 0>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_pins_default>; + avdd-supply = <&ppvarn_lcd>; + avee-supply = <&ppvarp_lcd>; + pp1800-supply = <&pp1800_lcd>; + backlight = <&backlight_lcd0>; + rotation = <270>; + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +&dsi_out { + remote-endpoint = <&panel_in>; +}; + &i2c0 { status = "okay"; }; @@ -304,35 +331,35 @@ "", ""; - ppvarp_lcd_en: ppvarp-lcd-en { + ppvarp_lcd_en: ppvarp-lcd-en-pins { pins1 { pinmux = <PINMUX_GPIO66__FUNC_GPIO66>; output-low; }; }; - ppvarn_lcd_en: ppvarn-lcd-en { + ppvarn_lcd_en: ppvarn-lcd-en-pins { pins1 { pinmux = <PINMUX_GPIO166__FUNC_GPIO166>; output-low; }; }; - pp1800_lcd_en: pp1800-lcd-en { + pp1800_lcd_en: pp1800-lcd-en-pins { pins1 { pinmux = <PINMUX_GPIO36__FUNC_GPIO36>; output-low; }; }; - open_touch: open_touch { - irq_pin { + open_touch: opentouch-pins { + pins-intn { pinmux = <PINMUX_GPIO155__FUNC_GPIO155>; input-enable; bias-pull-up; }; - rst_pin { + pins-rst { pinmux = <PINMUX_GPIO156__FUNC_GPIO156>; /* @@ -349,8 +376,8 @@ }; }; - pen_eject: peneject { - pen_eject { + pen_eject: pen-pins { + pins-eject { pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; input-enable; /* External pull-up. */ diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi index da6e767b4cee..b702ff066636 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi @@ -42,6 +42,34 @@ }; }; +&dsi0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel: panel@0 { + /* compatible will be set in board dts */ + reg = <0>; + enable-gpios = <&pio 45 0>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_pins_default>; + avdd-supply = <&ppvarn_lcd>; + avee-supply = <&ppvarp_lcd>; + pp1800-supply = <&pp1800_lcd>; + backlight = <&backlight_lcd0>; + rotation = <270>; + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +&dsi_out { + remote-endpoint = <&panel_in>; +}; + &i2c0 { status = "okay"; @@ -292,35 +320,35 @@ "", ""; - ppvarp_lcd_en: ppvarp-lcd-en { + ppvarp_lcd_en: ppvarp-lcd-en-pins { pins1 { pinmux = <PINMUX_GPIO66__FUNC_GPIO66>; output-low; }; }; - ppvarn_lcd_en: ppvarn-lcd-en { + ppvarn_lcd_en: ppvarn-lcd-en-pins { pins1 { pinmux = <PINMUX_GPIO166__FUNC_GPIO166>; output-low; }; }; - pp1800_lcd_en: pp1800-lcd-en { + pp1800_lcd_en: pp1800-lcd-en-pins { pins1 { pinmux = <PINMUX_GPIO36__FUNC_GPIO36>; output-low; }; }; - touch_default: touchdefault { - pin_irq { + touch_default: touch-pins { + pins-intn { pinmux = <PINMUX_GPIO155__FUNC_GPIO155>; input-enable; bias-pull-up; }; - touch_pin_reset: pin_reset { + touch_pin_reset: pins-rst { pinmux = <PINMUX_GPIO156__FUNC_GPIO156>; /* diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi index 8b56b8564ed7..b6cfcafd8b06 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi @@ -45,6 +45,34 @@ firmware-name = "nvm_00440302_i2s_eu.bin"; }; +&dsi0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel: panel@0 { + /* compatible will be set in board dts */ + reg = <0>; + enable-gpios = <&pio 45 0>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_pins_default>; + avdd-supply = <&ppvarn_lcd>; + avee-supply = <&ppvarp_lcd>; + pp1800-supply = <&pp1800_lcd>; + backlight = <&backlight_lcd0>; + rotation = <270>; + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +&dsi_out { + remote-endpoint = <&panel_in>; +}; + &i2c0 { status = "okay"; @@ -296,35 +324,35 @@ "", ""; - ppvarp_lcd_en: ppvarp-lcd-en { + ppvarp_lcd_en: ppvarp-lcd-en-pins { pins1 { pinmux = <PINMUX_GPIO66__FUNC_GPIO66>; output-low; }; }; - ppvarn_lcd_en: ppvarn-lcd-en { + ppvarn_lcd_en: ppvarn-lcd-en-pins { pins1 { pinmux = <PINMUX_GPIO166__FUNC_GPIO166>; output-low; }; }; - pp1800_lcd_en: pp1800-lcd-en { + pp1800_lcd_en: pp1800-lcd-en-pins { pins1 { pinmux = <PINMUX_GPIO36__FUNC_GPIO36>; output-low; }; }; - open_touch: open_touch { - irq_pin { + open_touch: opentouch-pins { + pins-intn { pinmux = <PINMUX_GPIO155__FUNC_GPIO155>; input-enable; bias-pull-up; }; - rst_pin { + pins-rst { pinmux = <PINMUX_GPIO156__FUNC_GPIO156>; /* diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 400c61d11035..4b87d4940c8c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -252,29 +252,6 @@ &dsi0 { status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - panel: panel@0 { - /* compatible will be set in board dts */ - reg = <0>; - enable-gpios = <&pio 45 0>; - pinctrl-names = "default"; - pinctrl-0 = <&panel_pins_default>; - avdd-supply = <&ppvarn_lcd>; - avee-supply = <&ppvarp_lcd>; - pp1800-supply = <&pp1800_lcd>; - backlight = <&backlight_lcd0>; - rotation = <270>; - port { - panel_in: endpoint { - remote-endpoint = <&dsi_out>; - }; - }; - }; -}; - -&dsi_out { - remote-endpoint = <&panel_in>; }; &gic { @@ -435,7 +412,7 @@ }; &pio { - aud_pins_default: audiopins { + aud_pins_default: audio-pins { pins-bus { pinmux = <PINMUX_GPIO97__FUNC_I2S2_MCK>, <PINMUX_GPIO98__FUNC_I2S2_BCK>, @@ -457,7 +434,7 @@ }; }; - aud_pins_tdm_out_on: audiotdmouton { + aud_pins_tdm_out_on: audio-tdmout-on-pins { pins-bus { pinmux = <PINMUX_GPIO169__FUNC_TDM_BCK_2ND>, <PINMUX_GPIO170__FUNC_TDM_LRCK_2ND>, @@ -469,7 +446,7 @@ }; }; - aud_pins_tdm_out_off: audiotdmoutoff { + aud_pins_tdm_out_off: audio-tdmout-off-pins { pins-bus { pinmux = <PINMUX_GPIO169__FUNC_GPIO169>, <PINMUX_GPIO170__FUNC_GPIO170>, @@ -490,22 +467,22 @@ }; }; - ec_ap_int_odl: ec-ap-int-odl { - pins1 { + ec_ap_int_odl: ec-ap-int-odl-pins { + pins-intn { pinmux = <PINMUX_GPIO151__FUNC_GPIO151>; input-enable; bias-pull-up; }; }; - h1_int_od_l: h1-int-od-l { - pins1 { + h1_int_od_l: h1-int-od-l-pins { + pins-intn { pinmux = <PINMUX_GPIO153__FUNC_GPIO153>; input-enable; }; }; - i2c0_pins: i2c0 { + i2c0_pins: i2c0-pins { pins-bus { pinmux = <PINMUX_GPIO82__FUNC_SDA0>, <PINMUX_GPIO83__FUNC_SCL0>; @@ -513,7 +490,7 @@ }; }; - i2c1_pins: i2c1 { + i2c1_pins: i2c1-pins { pins-bus { pinmux = <PINMUX_GPIO81__FUNC_SDA1>, <PINMUX_GPIO84__FUNC_SCL1>; @@ -521,7 +498,7 @@ }; }; - i2c2_pins: i2c2 { + i2c2_pins: i2c2-pins { pins-bus { pinmux = <PINMUX_GPIO103__FUNC_SCL2>, <PINMUX_GPIO104__FUNC_SDA2>; @@ -529,7 +506,7 @@ }; }; - i2c3_pins: i2c3 { + i2c3_pins: i2c3-pins { pins-bus { pinmux = <PINMUX_GPIO50__FUNC_SCL3>, <PINMUX_GPIO51__FUNC_SDA3>; @@ -537,7 +514,7 @@ }; }; - i2c4_pins: i2c4 { + i2c4_pins: i2c4-pins { pins-bus { pinmux = <PINMUX_GPIO105__FUNC_SCL4>, <PINMUX_GPIO106__FUNC_SDA4>; @@ -545,7 +522,7 @@ }; }; - i2c5_pins: i2c5 { + i2c5_pins: i2c5-pins { pins-bus { pinmux = <PINMUX_GPIO48__FUNC_SCL5>, <PINMUX_GPIO49__FUNC_SDA5>; @@ -553,7 +530,7 @@ }; }; - i2c6_pins: i2c6 { + i2c6_pins: i2c6-pins { pins-bus { pinmux = <PINMUX_GPIO11__FUNC_SCL6>, <PINMUX_GPIO12__FUNC_SDA6>; @@ -561,7 +538,7 @@ }; }; - mmc0_pins_default: mmc0-pins-default { + mmc0_pins_default: mmc0-default-pins { pins-cmd-dat { pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, @@ -580,7 +557,7 @@ pins-clk { pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; drive-strength = <MTK_DRIVE_14mA>; - mediatek,pull-down-adv = <10>; + mediatek,pull-down-adv = <2>; }; pins-rst { @@ -609,13 +586,13 @@ pins-clk { pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; drive-strength = <MTK_DRIVE_14mA>; - mediatek,pull-down-adv = <10>; + mediatek,pull-down-adv = <2>; }; pins-ds { pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>; drive-strength = <MTK_DRIVE_14mA>; - mediatek,pull-down-adv = <10>; + mediatek,pull-down-adv = <2>; }; pins-rst { @@ -625,7 +602,7 @@ }; }; - mmc1_pins_default: mmc1-pins-default { + mmc1_pins_default: mmc1-default-pins { pins-cmd-dat { pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, @@ -633,17 +610,17 @@ <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; input-enable; - mediatek,pull-up-adv = <10>; + mediatek,pull-up-adv = <2>; }; pins-clk { pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; input-enable; - mediatek,pull-down-adv = <10>; + mediatek,pull-down-adv = <2>; }; }; - mmc1_pins_uhs: mmc1-pins-uhs { + mmc1_pins_uhs: mmc1-uhs-pins { pins-cmd-dat { pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, @@ -652,26 +629,26 @@ <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; drive-strength = <6>; input-enable; - mediatek,pull-up-adv = <10>; + mediatek,pull-up-adv = <2>; }; pins-clk { pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; drive-strength = <8>; - mediatek,pull-down-adv = <10>; + mediatek,pull-down-adv = <2>; input-enable; }; }; - panel_pins_default: panel-pins-default { - panel-reset { + panel_pins_default: panel-pins { + pins-panel-reset { pinmux = <PINMUX_GPIO45__FUNC_GPIO45>; output-low; bias-pull-up; }; }; - pwm0_pin_default: pwm0-pin-default { + pwm0_pin_default: pwm0-pins { pins1 { pinmux = <PINMUX_GPIO176__FUNC_GPIO176>; output-high; @@ -682,15 +659,15 @@ }; }; - scp_pins: scp { + scp_pins: scp-pins { pins-scp-uart { pinmux = <PINMUX_GPIO110__FUNC_TP_URXD1_AO>, <PINMUX_GPIO112__FUNC_TP_UTXD1_AO>; }; }; - spi0_pins: spi0 { - pins-spi { + spi0_pins: spi0-pins { + pins-bus { pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>, <PINMUX_GPIO86__FUNC_GPIO86>, <PINMUX_GPIO87__FUNC_SPI0_MO>, @@ -699,8 +676,8 @@ }; }; - spi1_pins: spi1 { - pins-spi { + spi1_pins: spi1-pins { + pins-bus { pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>, <PINMUX_GPIO162__FUNC_SPI1_A_CSB>, <PINMUX_GPIO163__FUNC_SPI1_A_MO>, @@ -709,21 +686,21 @@ }; }; - spi2_pins: spi2 { - pins-spi { + spi2_pins: spi2-pins { + pins-bus { pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>, <PINMUX_GPIO1__FUNC_SPI2_MO>, <PINMUX_GPIO2__FUNC_SPI2_CLK>; bias-disable; }; - pins-spi-mi { + pins-miso { pinmux = <PINMUX_GPIO94__FUNC_SPI2_MI>; mediatek,pull-down-adv = <00>; }; }; - spi3_pins: spi3 { - pins-spi { + spi3_pins: spi3-pins { + pins-bus { pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>, <PINMUX_GPIO22__FUNC_SPI3_CSB>, <PINMUX_GPIO23__FUNC_SPI3_MO>, @@ -732,8 +709,8 @@ }; }; - spi4_pins: spi4 { - pins-spi { + spi4_pins: spi4-pins { + pins-bus { pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>, <PINMUX_GPIO18__FUNC_SPI4_CSB>, <PINMUX_GPIO19__FUNC_SPI4_MO>, @@ -742,8 +719,8 @@ }; }; - spi5_pins: spi5 { - pins-spi { + spi5_pins: spi5-pins { + pins-bus { pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>, <PINMUX_GPIO14__FUNC_SPI5_CSB>, <PINMUX_GPIO15__FUNC_SPI5_MO>, @@ -752,7 +729,7 @@ }; }; - uart0_pins_default: uart0-pins-default { + uart0_pins_default: uart0-pins { pins-rx { pinmux = <PINMUX_GPIO95__FUNC_URXD0>; input-enable; @@ -763,7 +740,7 @@ }; }; - uart1_pins_default: uart1-pins-default { + uart1_pins_default: uart1-pins { pins-rx { pinmux = <PINMUX_GPIO121__FUNC_URXD1>; input-enable; @@ -781,7 +758,7 @@ }; }; - uart1_pins_sleep: uart1-pins-sleep { + uart1_pins_sleep: uart1-sleep-pins { pins-rx { pinmux = <PINMUX_GPIO121__FUNC_GPIO121>; input-enable; @@ -799,14 +776,14 @@ }; }; - wifi_pins_pwrseq: wifi-pins-pwrseq { + wifi_pins_pwrseq: wifi-pwr-pins { pins-wifi-enable { pinmux = <PINMUX_GPIO119__FUNC_GPIO119>; output-low; }; }; - wifi_pins_wakeup: wifi-pins-wakeup { + wifi_pins_wakeup: wifi-wake-pins { pins-wifi-wakeup { pinmux = <PINMUX_GPIO113__FUNC_GPIO113>; input-enable; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts index dbdee604edab..f60ef3e53a09 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts @@ -324,7 +324,7 @@ pins_clk { pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; drive-strength = <MTK_DRIVE_14mA>; - mediatek,pull-down-adv = <10>; + mediatek,pull-down-adv = <2>; }; pins_rst { @@ -353,13 +353,13 @@ pins_clk { pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; drive-strength = <MTK_DRIVE_14mA>; - mediatek,pull-down-adv = <10>; + mediatek,pull-down-adv = <2>; }; pins_ds { pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>; drive-strength = <MTK_DRIVE_14mA>; - mediatek,pull-down-adv = <10>; + mediatek,pull-down-adv = <2>; }; pins_rst { @@ -377,13 +377,13 @@ <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; input-enable; - mediatek,pull-up-adv = <10>; + mediatek,pull-up-adv = <2>; }; pins_clk { pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; input-enable; - mediatek,pull-down-adv = <10>; + mediatek,pull-down-adv = <2>; }; pins_pmu { @@ -401,13 +401,13 @@ <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; drive-strength = <6>; input-enable; - mediatek,pull-up-adv = <10>; + mediatek,pull-up-adv = <2>; }; pins_clk { pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; drive-strength = <8>; - mediatek,pull-down-adv = <10>; + mediatek,pull-down-adv = <2>; input-enable; }; }; @@ -482,6 +482,10 @@ domain-supply = <&mt6358_vgpu_reg>; }; +&cci { + proc-supply = <&mt6358_vproc12_reg>; +}; + &cpu0 { proc-supply = <&mt6358_vproc12_reg>; }; @@ -527,10 +531,8 @@ pinctrl-0 = <&dpi_func_pins>; pinctrl-1 = <&dpi_idle_pins>; status = "okay"; +}; - port { - dpi_out: endpoint { - remote-endpoint = <&it66121_in>; - }; - }; +&dpi_out { + remote-endpoint = <&it66121_in>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 3c1fe80e64b9..960d8955d018 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1667,6 +1667,21 @@ mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, <&gce 1 CMDQ_THR_PRIO_HIGHEST>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + mmsys_ep_main: endpoint@0 { + reg = <0>; + remote-endpoint = <&ovl0_in>; + }; + + mmsys_ep_ext: endpoint@1 { + reg = <1>; + remote-endpoint = <&ovl_2l1_in>; + }; + }; }; dma-controller0@14001000 { @@ -1733,6 +1748,25 @@ clocks = <&mmsys CLK_MM_DISP_OVL0>; iommus = <&iommu M4U_PORT_DISP_OVL0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ovl0_in: endpoint { + remote-endpoint = <&mmsys_ep_main>; + }; + }; + + port@1 { + reg = <1>; + ovl0_out: endpoint { + remote-endpoint = <&ovl_2l0_in>; + }; + }; + }; }; ovl_2l0: ovl@14009000 { @@ -1743,6 +1777,25 @@ clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ovl_2l0_in: endpoint { + remote-endpoint = <&ovl0_out>; + }; + }; + + port@1 { + reg = <1>; + ovl_2l0_out: endpoint { + remote-endpoint = <&rdma0_in>; + }; + }; + }; }; ovl_2l1: ovl@1400a000 { @@ -1753,6 +1806,25 @@ clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ovl_2l1_in: endpoint { + remote-endpoint = <&mmsys_ep_ext>; + }; + }; + + port@1 { + reg = <1>; + ovl_2l1_out: endpoint { + remote-endpoint = <&rdma1_in>; + }; + }; + }; }; rdma0: rdma@1400b000 { @@ -1764,6 +1836,25 @@ iommus = <&iommu M4U_PORT_DISP_RDMA0>; mediatek,rdma-fifo-size = <5120>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rdma0_in: endpoint { + remote-endpoint = <&ovl_2l0_out>; + }; + }; + + port@1 { + reg = <1>; + rdma0_out: endpoint { + remote-endpoint = <&color0_in>; + }; + }; + }; }; rdma1: rdma@1400c000 { @@ -1775,6 +1866,25 @@ iommus = <&iommu M4U_PORT_DISP_RDMA1>; mediatek,rdma-fifo-size = <2048>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rdma1_in: endpoint { + remote-endpoint = <&ovl_2l1_out>; + }; + }; + + port@1 { + reg = <1>; + rdma1_out: endpoint { + remote-endpoint = <&dpi_in>; + }; + }; + }; }; color0: color@1400e000 { @@ -1785,6 +1895,25 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_COLOR0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + color0_in: endpoint { + remote-endpoint = <&rdma0_out>; + }; + }; + + port@1 { + reg = <1>; + color0_out: endpoint { + remote-endpoint = <&ccorr0_in>; + }; + }; + }; }; ccorr0: ccorr@1400f000 { @@ -1794,6 +1923,25 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_CCORR0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ccorr0_in: endpoint { + remote-endpoint = <&color0_out>; + }; + }; + + port@1 { + reg = <1>; + ccorr0_out: endpoint { + remote-endpoint = <&aal0_in>; + }; + }; + }; }; aal0: aal@14010000 { @@ -1803,6 +1951,25 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_AAL0>; mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + aal0_in: endpoint { + remote-endpoint = <&ccorr0_out>; + }; + }; + + port@1 { + reg = <1>; + aal0_out: endpoint { + remote-endpoint = <&gamma0_in>; + }; + }; + }; }; gamma0: gamma@14011000 { @@ -1812,6 +1979,25 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_GAMMA0>; mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + gamma0_in: endpoint { + remote-endpoint = <&aal0_out>; + }; + }; + + port@1 { + reg = <1>; + gamma0_out: endpoint { + remote-endpoint = <&dither0_in>; + }; + }; + }; }; dither0: dither@14012000 { @@ -1821,6 +2007,25 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_DITHER0>; mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dither0_in: endpoint { + remote-endpoint = <&gamma0_out>; + }; + }; + + port@1 { + reg = <1>; + dither0_out: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; + }; }; dsi0: dsi@14014000 { @@ -1837,8 +2042,21 @@ phy-names = "dphy"; status = "disabled"; - port { - dsi_out: endpoint { }; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <&dither0_out>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { }; + }; }; }; @@ -1853,8 +2071,21 @@ clock-names = "pixel", "engine", "pll"; status = "disabled"; - port { - dpi_out: endpoint { }; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpi_in: endpoint { + remote-endpoint = <&rdma1_out>; + }; + }; + + port@1 { + reg = <1>; + dpi_out: endpoint { }; + }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-krabby.dtsi b/arch/arm64/boot/dts/mediatek/mt8186-corsola-krabby.dtsi index 7c971198fa95..72a2a2bff0a9 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186-corsola-krabby.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-krabby.dtsi @@ -71,14 +71,14 @@ i2c-scl-internal-delay-ns = <10000>; touchscreen: touchscreen@10 { - compatible = "hid-over-i2c"; + compatible = "elan,ekth6915"; reg = <0x10>; interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&touchscreen_pins>; - post-power-on-delay-ms = <10>; - hid-descr-addr = <0x0001>; - vdd-supply = <&pp3300_s3>; + reset-gpios = <&pio 60 GPIO_ACTIVE_LOW>; + vcc33-supply = <&pp3300_s3>; + no-reset-on-power-off; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-sku262144.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-sku262144.dts index 26d3451a5e47..24d9ede63eaa 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-sku262144.dts +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-sku262144.dts @@ -42,3 +42,7 @@ CROS_STD_MAIN_KEYMAP >; }; + +&touchscreen { + compatible = "elan,ekth6a12nay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi index c5254ae0bb99..7fedbacdac44 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi @@ -164,6 +164,12 @@ #size-cells = <2>; ranges; + scp_mem_reserved: memory@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x800000>; + no-map; + }; + apu_mem: memory@55000000 { compatible = "shared-dma-pool"; reg = <0 0x55000000 0 0x1400000>; @@ -1077,6 +1083,13 @@ }; }; + scp_pins: scp-pins { + pins-scp-vreq { + pinmux = <PINMUX_GPIO98__FUNC_O_SCP_VREQ_VAO>; + bias-disable; + }; + }; + spi0_pins: spi0-pins { pins-bus { pinmux = <PINMUX_GPIO69__FUNC_O_SPIM0_CSB>, @@ -1146,6 +1159,18 @@ remote-endpoint = <&dither0_in>; }; +&scp_cluster { + status = "okay"; +}; + +&scp_c0 { + pinctrl-names = "default"; + pinctrl-0 = <&scp_pins>; + firmware-name = "mediatek/mt8188/scp.img"; + memory-region = <&scp_mem_reserved>; + status = "okay"; +}; + &sound { pinctrl-names = "aud_etdm_hp_on", "aud_etdm_hp_off", "aud_etdm_spk_on", "aud_etdm_spk_off", diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index 202478407727..90c388f1890f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -2183,7 +2183,7 @@ }; efuse: efuse@11f20000 { - compatible = "mediatek,mt8188-efuse", "mediatek,efuse"; + compatible = "mediatek,mt8188-efuse", "mediatek,mt8186-efuse"; reg = <0 0x11f20000 0 0x1000>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts index a82d716f10d4..a50b4e8efaba 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts @@ -13,6 +13,7 @@ &audio_codec { compatible = "realtek,rt5682i"; realtek,btndet-delay = <16>; + VBAT-supply = <&pp3300_z5>; }; &sound { diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts index 2d6522c144b7..a8657c0068d5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts @@ -13,6 +13,7 @@ &audio_codec { compatible = "realtek,rt5682i"; realtek,btndet-delay = <16>; + VBAT-supply = <&pp3300_z5>; }; &pio_default { diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index e70599807bb1..b3761b80cac7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -534,8 +534,9 @@ realtek,jd-src = <1>; AVDD-supply = <&mt6359_vio18_ldo_reg>; + DBVDD-supply = <&mt6359_vio18_ldo_reg>; MICVDD-supply = <&pp3300_z2>; - VBAT-supply = <&pp3300_z5>; + LDO1-IN-supply = <&mt6359_vio18_ldo_reg>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 8877953ce292..ec452d657031 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1588,9 +1588,6 @@ power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>; - resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>; - reset-names = "mac"; - #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie_intc0 0>, @@ -3039,7 +3036,7 @@ #size-cells = <2>; }; - jpgdec-master { + jpeg-decoder@1a040000 { compatible = "mediatek,mt8195-jpgdec"; power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, @@ -3050,11 +3047,12 @@ <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; #address-cells = <2>; #size-cells = <2>; - ranges; + ranges = <0 0 0 0x1a040000 0 0x20000>, + <1 0 0 0x1b040000 0 0x10000>; - jpgdec@1a040000 { + jpgdec@0,0 { compatible = "mediatek,mt8195-jpgdec-hw"; - reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */ + reg = <0 0 0 0x10000>;/* JPGDEC_C0 */ iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, @@ -3067,9 +3065,9 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; }; - jpgdec@1a050000 { + jpgdec@0,10000 { compatible = "mediatek,mt8195-jpgdec-hw"; - reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */ + reg = <0 0 0x10000 0x10000>;/* JPGDEC_C1 */ iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, @@ -3082,9 +3080,9 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; }; - jpgdec@1b040000 { + jpgdec@1,0 { compatible = "mediatek,mt8195-jpgdec-hw"; - reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */ + reg = <1 0 0 0x10000>;/* JPGDEC_C2 */ iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>, <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>, <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>, @@ -3113,7 +3111,7 @@ }; - jpgenc-master { + jpeg-encoder@1a030000 { compatible = "mediatek,mt8195-jpgenc"; power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, @@ -3122,11 +3120,12 @@ <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; #address-cells = <2>; #size-cells = <2>; - ranges; + ranges = <0 0 0 0x1a030000 0 0x10000>, + <1 0 0 0x1b030000 0 0x10000>; - jpgenc@1a030000 { + jpgenc@0,0 { compatible = "mediatek,mt8195-jpgenc-hw"; - reg = <0 0x1a030000 0 0x10000>; + reg = <0 0 0 0x10000>; iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>, <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>, <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>, @@ -3137,9 +3136,9 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; }; - jpgenc@1b030000 { + jpgenc@1,0 { compatible = "mediatek,mt8195-jpgenc-hw"; - reg = <0 0x1b030000 0 0x10000>; + reg = <1 0 0 0x10000>; iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, diff --git a/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts b/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts index 4985b65925a9..d16f545cbbb2 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts @@ -352,7 +352,7 @@ LDO_VIN2-supply = <&vsys>; LDO_VIN3-supply = <&vsys>; - mt6360_buck1: BUCK1 { + mt6360_buck1: buck1 { regulator-name = "emi_vdd2"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <1800000>; @@ -362,7 +362,7 @@ regulator-always-on; }; - mt6360_buck2: BUCK2 { + mt6360_buck2: buck2 { regulator-name = "emi_vddq"; regulator-min-microvolt = <300000>; regulator-max-microvolt = <1300000>; @@ -372,7 +372,7 @@ regulator-always-on; }; - mt6360_ldo1: LDO1 { + mt6360_ldo1: ldo1 { regulator-name = "mt6360_ldo1"; /* Test point */ regulator-min-microvolt = <1200000>; regulator-max-microvolt = <3600000>; @@ -380,7 +380,7 @@ MT6360_OPMODE_LP>; }; - mt6360_ldo2: LDO2 { + mt6360_ldo2: ldo2 { regulator-name = "panel1_p1v8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -388,7 +388,7 @@ MT6360_OPMODE_LP>; }; - mt6360_ldo3: LDO3 { + mt6360_ldo3: ldo3 { regulator-name = "vmc_pmu"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; @@ -396,7 +396,7 @@ MT6360_OPMODE_LP>; }; - mt6360_ldo5: LDO5 { + mt6360_ldo5: ldo5 { regulator-name = "vmch_pmu"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -404,7 +404,7 @@ MT6360_OPMODE_LP>; }; - mt6360_ldo6: LDO6 { + mt6360_ldo6: ldo6 { regulator-name = "mt6360_ldo6"; /* Test point */ regulator-min-microvolt = <500000>; regulator-max-microvolt = <2100000>; @@ -412,7 +412,7 @@ MT6360_OPMODE_LP>; }; - mt6360_ldo7: LDO7 { + mt6360_ldo7: ldo7 { regulator-name = "emi_vmddr_en"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index 329c60cc6a6b..d32f973f5e05 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -8,6 +8,7 @@ #include "mt8195.dtsi" #include "mt6359.dtsi" #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pinctrl/mt8195-pinfunc.h> #include <dt-bindings/regulator/mediatek,mt6360-regulator.h> @@ -60,6 +61,18 @@ status = "disabled"; }; + keys: gpio-keys { + compatible = "gpio-keys"; + + button-volume-up { + wakeup-source; + debounce-interval = <100>; + gpios = <&pio 106 GPIO_ACTIVE_LOW>; + label = "volume_up"; + linux,code = <KEY_VOLUMEUP>; + }; + }; + wifi_vreg: regulator-wifi-3v3-en { compatible = "regulator-fixed"; regulator-name = "wifi_3v3_en"; @@ -626,6 +639,14 @@ }; }; + gpio_key_pins: gpio-keys-pins { + pins { + pinmux = <PINMUX_GPIO106__FUNC_GPIO106>; + bias-pull-up; + input-enable; + }; + }; + i2c2_pins: i2c2-pins { pins-bus { pinmux = <PINMUX_GPIO12__FUNC_SDA2>, @@ -880,6 +901,21 @@ &pmic { interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; + + mt6359keys: keys { + compatible = "mediatek,mt6359-keys"; + mediatek,long-press-mode = <1>; + power-off-time-sec = <0>; + + power-key { + linux,keycodes = <KEY_POWER>; + wakeup-source; + }; + + home { + linux,keycodes = <KEY_HOME>; + }; + }; }; &scp { @@ -990,6 +1026,16 @@ status = "okay"; }; +&ufshci { + vcc-supply = <&mt6359_vemc_1_ldo_reg>; + vccq2-supply = <&mt6359_vufs_ldo_reg>; + status = "okay"; +}; + +&ufsphy { + status = "okay"; +}; + &ssusb0 { pinctrl-names = "default"; pinctrl-0 = <&usb3_port0_pins>; diff --git a/arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts index cce642c53812..3d3db33a64dc 100644 --- a/arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts +++ b/arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts @@ -11,7 +11,7 @@ / { model = "Pumpkin MT8516"; - compatible = "mediatek,mt8516"; + compatible = "mediatek,mt8516-pumpkin", "mediatek,mt8516"; memory@40000000 { device_type = "memory"; diff --git a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi index a356db5fcc5f..805fb82138a8 100644 --- a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi @@ -198,8 +198,8 @@ }; &pio { - gpio_keys_default: gpiodefault { - pins_cmd_dat { + gpio_keys_default: gpio-keys-pins { + pins-cmd-dat { pinmux = <MT8516_PIN_42_KPCOL0__FUNC_GPIO42>, <MT8516_PIN_43_KPCOL1__FUNC_GPIO43>; bias-pull-up; @@ -207,7 +207,7 @@ }; }; - i2c0_pins_a: i2c0 { + i2c0_pins_a: i2c0-pins { pins1 { pinmux = <MT8516_PIN_58_SDA0__FUNC_SDA0_0>, <MT8516_PIN_59_SCL0__FUNC_SCL0_0>; @@ -215,7 +215,7 @@ }; }; - i2c2_pins_a: i2c2 { + i2c2_pins_a: i2c2-pins { pins1 { pinmux = <MT8516_PIN_60_SDA2__FUNC_SDA2_0>, <MT8516_PIN_61_SCL2__FUNC_SCL2_0>; @@ -223,21 +223,21 @@ }; }; - tca6416_pins: pinmux_tca6416_pins { - gpio_mux_rst_n_pin { + tca6416_pins: tca6416-pins { + pins-mux-rstn { pinmux = <MT8516_PIN_65_UTXD1__FUNC_GPIO65>; output-high; }; - gpio_mux_int_n_pin { + pins-mux-intn { pinmux = <MT8516_PIN_64_URXD1__FUNC_GPIO64>; input-enable; bias-pull-up; }; }; - ethernet_pins_default: ethernet { - pins_ethernet { + ethernet_pins_default: ethernet-pins { + pins-eth { pinmux = <MT8516_PIN_0_EINT0__FUNC_EXT_TXD0>, <MT8516_PIN_1_EINT1__FUNC_EXT_TXD1>, <MT8516_PIN_5_EINT5__FUNC_EXT_RXER>, diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi index acd3137d2464..24133528b8e9 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi @@ -42,17 +42,13 @@ interrupt-parent = <&gic>; ranges; - rstc: reset-controller@f0801000 { + clk: rstc: reset-controller@f0801000 { compatible = "nuvoton,npcm845-reset"; - reg = <0x0 0xf0801000 0x0 0x78>; - #reset-cells = <2>; + reg = <0x0 0xf0801000 0x0 0xC4>; nuvoton,sysgcr = <&gcr>; - }; - - clk: clock-controller@f0801000 { - compatible = "nuvoton,npcm845-clk"; + #reset-cells = <2>; + clocks = <&refclk>; #clock-cells = <1>; - reg = <0x0 0xf0801000 0x0 0x1000>; }; apb { @@ -76,7 +72,7 @@ compatible = "nuvoton,npcm845-timer"; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; reg = <0x8000 0x1C>; - clocks = <&clk NPCM8XX_CLK_REFCLK>; + clocks = <&refclk>; clock-names = "refclk"; }; @@ -148,7 +144,7 @@ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; reg = <0x801c 0x4>; status = "disabled"; - clocks = <&clk NPCM8XX_CLK_REFCLK>; + clocks = <&refclk>; syscon = <&gcr>; }; @@ -157,7 +153,7 @@ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; reg = <0x901c 0x4>; status = "disabled"; - clocks = <&clk NPCM8XX_CLK_REFCLK>; + clocks = <&refclk>; syscon = <&gcr>; }; @@ -166,7 +162,7 @@ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; reg = <0xa01c 0x4>; status = "disabled"; - clocks = <&clk NPCM8XX_CLK_REFCLK>; + clocks = <&refclk>; syscon = <&gcr>; }; }; @@ -235,5 +231,654 @@ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; gpio-ranges = <&pinctrl 0 224 32>; }; + + iox1_pins: iox1-mux { + groups = "iox1"; + function = "iox1"; + }; + iox2_pins: iox2-mux { + groups = "iox2"; + function = "iox2"; + }; + smb1d_pins: smb1d-mux { + groups = "smb1d"; + function = "smb1d"; + }; + smb2d_pins: smb2d-mux { + groups = "smb2d"; + function = "smb2d"; + }; + lkgpo1_pins: lkgpo1-mux { + groups = "lkgpo1"; + function = "lkgpo1"; + }; + lkgpo2_pins: lkgpo2-mux { + groups = "lkgpo2"; + function = "lkgpo2"; + }; + ioxh_pins: ioxh-mux { + groups = "ioxh"; + function = "ioxh"; + }; + gspi_pins: gspi-mux { + groups = "gspi"; + function = "gspi"; + }; + smb5b_pins: smb5b-mux { + groups = "smb5b"; + function = "smb5b"; + }; + smb5c_pins: smb5c-mux { + groups = "smb5c"; + function = "smb5c"; + }; + lkgpo0_pins: lkgpo0-mux { + groups = "lkgpo0"; + function = "lkgpo0"; + }; + pspi_pins: pspi-mux { + groups = "pspi"; + function = "pspi"; + }; + jm1_pins: jm1-mux { + groups = "jm1"; + function = "jm1"; + }; + jm2_pins: jm2-mux { + groups = "jm2"; + function = "jm2"; + }; + smb4b_pins: smb4b-mux { + groups = "smb4b"; + function = "smb4b"; + }; + smb4c_pins: smb4c-mux { + groups = "smb4c"; + function = "smb4c"; + }; + smb15_pins: smb15-mux { + groups = "smb15"; + function = "smb15"; + }; + smb16_pins: smb16-mux { + groups = "smb16"; + function = "smb16"; + }; + smb17_pins: smb17-mux { + groups = "smb17"; + function = "smb17"; + }; + smb18_pins: smb18-mux { + groups = "smb18"; + function = "smb18"; + }; + smb19_pins: smb19-mux { + groups = "smb19"; + function = "smb19"; + }; + smb20_pins: smb20-mux { + groups = "smb20"; + function = "smb20"; + }; + smb21_pins: smb21-mux { + groups = "smb21"; + function = "smb21"; + }; + smb22_pins: smb22-mux { + groups = "smb22"; + function = "smb22"; + }; + smb23_pins: smb23-mux { + groups = "smb23"; + function = "smb23"; + }; + smb23b_pins: smb23b-mux { + groups = "smb23b"; + function = "smb23b"; + }; + smb4d_pins: smb4d-mux { + groups = "smb4d"; + function = "smb4d"; + }; + smb14_pins: smb14-mux { + groups = "smb14"; + function = "smb14"; + }; + smb5_pins: smb5-mux { + groups = "smb5"; + function = "smb5"; + }; + smb4_pins: smb4-mux { + groups = "smb4"; + function = "smb4"; + }; + smb3_pins: smb3-mux { + groups = "smb3"; + function = "smb3"; + }; + spi0cs1_pins: spi0cs1-mux { + groups = "spi0cs1"; + function = "spi0cs1"; + }; + spi1cs0_pins: spi1cs0-mux { + groups = "spi1cs0"; + function = "spi1cs0"; + }; + spi1cs1_pins: spi1cs1-mux { + groups = "spi1cs1"; + function = "spi1cs1"; + }; + spi1cs2_pins: spi1cs2-mux { + groups = "spi1cs2"; + function = "spi1cs2"; + }; + spi1cs3_pins: spi1cs3-mux { + groups = "spi1cs3"; + function = "spi1cs3"; + }; + smb3c_pins: smb3c-mux { + groups = "smb3c"; + function = "smb3c"; + }; + smb3b_pins: smb3b-mux { + groups = "smb3b"; + function = "smb3b"; + }; + bmcuart0a_pins: bmcuart0a-mux { + groups = "bmcuart0a"; + function = "bmcuart0a"; + }; + uart1_pins: uart1-mux { + groups = "uart1"; + function = "uart1"; + }; + jtag2_pins: jtag2-mux { + groups = "jtag2"; + function = "jtag2"; + }; + bmcuart1_pins: bmcuart1-mux { + groups = "bmcuart1"; + function = "bmcuart1"; + }; + uart2_pins: uart2-mux { + groups = "uart2"; + function = "uart2"; + }; + bmcuart0b_pins: bmcuart0b-mux { + groups = "bmcuart0b"; + function = "bmcuart0b"; + }; + r1err_pins: r1err-mux { + groups = "r1err"; + function = "r1err"; + }; + r1md_pins: r1md-mux { + groups = "r1md"; + function = "r1md"; + }; + r1oen_pins: r1oen-mux { + groups = "r1oen"; + function = "r1oen"; + }; + r2oen_pins: r2oen-mux { + groups = "r2oen"; + function = "r2oen"; + }; + rmii3_pins: rmii3-mux { + groups = "rmii3"; + function = "rmii3"; + }; + r3oen_pins: r3oen-mux { + groups = "r3oen"; + function = "r3oen"; + }; + smb3d_pins: smb3d-mux { + groups = "smb3d"; + function = "smb3d"; + }; + fanin0_pins: fanin0-mux { + groups = "fanin0"; + function = "fanin0"; + }; + fanin1_pins: fanin1-mux { + groups = "fanin1"; + function = "fanin1"; + }; + fanin2_pins: fanin2-mux { + groups = "fanin2"; + function = "fanin2"; + }; + fanin3_pins: fanin3-mux { + groups = "fanin3"; + function = "fanin3"; + }; + fanin4_pins: fanin4-mux { + groups = "fanin4"; + function = "fanin4"; + }; + fanin5_pins: fanin5-mux { + groups = "fanin5"; + function = "fanin5"; + }; + fanin6_pins: fanin6-mux { + groups = "fanin6"; + function = "fanin6"; + }; + fanin7_pins: fanin7-mux { + groups = "fanin7"; + function = "fanin7"; + }; + fanin8_pins: fanin8-mux { + groups = "fanin8"; + function = "fanin8"; + }; + fanin9_pins: fanin9-mux { + groups = "fanin9"; + function = "fanin9"; + }; + fanin10_pins: fanin10-mux { + groups = "fanin10"; + function = "fanin10"; + }; + fanin11_pins: fanin11-mux { + groups = "fanin11"; + function = "fanin11"; + }; + fanin12_pins: fanin12-mux { + groups = "fanin12"; + function = "fanin12"; + }; + fanin13_pins: fanin13-mux { + groups = "fanin13"; + function = "fanin13"; + }; + fanin14_pins: fanin14-mux { + groups = "fanin14"; + function = "fanin14"; + }; + fanin15_pins: fanin15-mux { + groups = "fanin15"; + function = "fanin15"; + }; + pwm0_pins: pwm0-mux { + groups = "pwm0"; + function = "pwm0"; + }; + pwm1_pins: pwm1-mux { + groups = "pwm1"; + function = "pwm1"; + }; + pwm2_pins: pwm2-mux { + groups = "pwm2"; + function = "pwm2"; + }; + pwm3_pins: pwm3-mux { + groups = "pwm3"; + function = "pwm3"; + }; + r2_pins: r2-mux { + groups = "r2"; + function = "r2"; + }; + r2err_pins: r2err-mux { + groups = "r2err"; + function = "r2err"; + }; + r2md_pins: r2md-mux { + groups = "r2md"; + function = "r2md"; + }; + r3rxer_pins: r3rxer-mux { + groups = "r3rxer"; + function = "r3rxer"; + }; + ga20kbc_pins: ga20kbc-mux { + groups = "ga20kbc"; + function = "ga20kbc"; + }; + smb5d_pins: smb5d-mux { + groups = "smb5d"; + function = "smb5d"; + }; + lpc_pins: lpc-mux { + groups = "lpc"; + function = "lpc"; + }; + espi_pins: espi-mux { + groups = "espi"; + function = "espi"; + }; + sg1mdio_pins: sg1mdio-mux { + groups = "sg1mdio"; + function = "sg1mdio"; + }; + rg2_pins: rg2-mux { + groups = "rg2"; + function = "rg2"; + }; + ddr_pins: ddr-mux { + groups = "ddr"; + function = "ddr"; + }; + i3c0_pins: i3c0-mux { + groups = "i3c0"; + function = "i3c0"; + }; + i3c1_pins: i3c1-mux { + groups = "i3c1"; + function = "i3c1"; + }; + i3c2_pins: i3c2-mux { + groups = "i3c2"; + function = "i3c2"; + }; + i3c3_pins: i3c3-mux { + groups = "i3c3"; + function = "i3c3"; + }; + i3c4_pins: i3c4-mux { + groups = "i3c4"; + function = "i3c4"; + }; + i3c5_pins: i3c5-mux { + groups = "i3c5"; + function = "i3c5"; + }; + smb0_pins: smb0-mux { + groups = "smb0"; + function = "smb0"; + }; + smb1_pins: smb1-mux { + groups = "smb1"; + function = "smb1"; + }; + smb2_pins: smb2-mux { + groups = "smb2"; + function = "smb2"; + }; + smb2c_pins: smb2c-mux { + groups = "smb2c"; + function = "smb2c"; + }; + smb2b_pins: smb2b-mux { + groups = "smb2b"; + function = "smb2b"; + }; + smb1c_pins: smb1c-mux { + groups = "smb1c"; + function = "smb1c"; + }; + smb1b_pins: smb1b-mux { + groups = "smb1b"; + function = "smb1b"; + }; + smb8_pins: smb8-mux { + groups = "smb8"; + function = "smb8"; + }; + smb9_pins: smb9-mux { + groups = "smb9"; + function = "smb9"; + }; + smb10_pins: smb10-mux { + groups = "smb10"; + function = "smb10"; + }; + smb11_pins: smb11-mux { + groups = "smb11"; + function = "smb11"; + }; + sd1_pins: sd1-mux { + groups = "sd1"; + function = "sd1"; + }; + sd1pwr_pins: sd1pwr-mux { + groups = "sd1pwr"; + function = "sd1pwr"; + }; + pwm4_pins: pwm4-mux { + groups = "pwm4"; + function = "pwm4"; + }; + pwm5_pins: pwm5-mux { + groups = "pwm5"; + function = "pwm5"; + }; + pwm6_pins: pwm6-mux { + groups = "pwm6"; + function = "pwm6"; + }; + pwm7_pins: pwm7-mux { + groups = "pwm7"; + function = "pwm7"; + }; + pwm8_pins: pwm8-mux { + groups = "pwm8"; + function = "pwm8"; + }; + pwm9_pins: pwm9-mux { + groups = "pwm9"; + function = "pwm9"; + }; + pwm10_pins: pwm10-mux { + groups = "pwm10"; + function = "pwm10"; + }; + pwm11_pins: pwm11-mux { + groups = "pwm11"; + function = "pwm11"; + }; + mmc8_pins: mmc8-mux { + groups = "mmc8"; + function = "mmc8"; + }; + mmc_pins: mmc-mux { + groups = "mmc"; + function = "mmc"; + }; + mmcwp_pins: mmcwp-mux { + groups = "mmcwp"; + function = "mmcwp"; + }; + mmccd_pins: mmccd-mux { + groups = "mmccd"; + function = "mmccd"; + }; + mmcrst_pins: mmcrst-mux { + groups = "mmcrst"; + function = "mmcrst"; + }; + clkout_pins: clkout-mux { + groups = "clkout"; + function = "clkout"; + }; + serirq_pins: serirq-mux { + groups = "serirq"; + function = "serirq"; + }; + scipme_pins: scipme-mux { + groups = "scipme"; + function = "scipme"; + }; + smb6_pins: smb6-mux { + groups = "smb6"; + function = "smb6"; + }; + smb6b_pins: smb6b-mux { + groups = "smb6b"; + function = "smb6b"; + }; + smb6c_pins: smb6c-mux { + groups = "smb6c"; + function = "smb6c"; + }; + smb6d_pins: smb6d-mux { + groups = "smb6d"; + function = "smb6d"; + }; + smb7_pins: smb7-mux { + groups = "smb7"; + function = "smb7"; + }; + smb7b_pins: smb7b-mux { + groups = "smb7b"; + function = "smb7b"; + }; + smb7c_pins: smb7c-mux { + groups = "smb7c"; + function = "smb7c"; + }; + smb7d_pins: smb7d-mux { + groups = "smb7d"; + function = "smb7d"; + }; + spi1_pins: spi1-mux { + groups = "spi1"; + function = "spi1"; + }; + faninx_pins: faninx-mux { + groups = "faninx"; + function = "faninx"; + }; + r1_pins: r1-mux { + groups = "r1"; + function = "r1"; + }; + spi3_pins: spi3-mux { + groups = "spi3"; + function = "spi3"; + }; + spi3cs1_pins: spi3cs1-mux { + groups = "spi3cs1"; + function = "spi3cs1"; + }; + spi3quad_pins: spi3quad-mux { + groups = "spi3quad"; + function = "spi3quad"; + }; + spi3cs2_pins: spi3cs2-mux { + groups = "spi3cs2"; + function = "spi3cs2"; + }; + spi3cs3_pins: spi3cs3-mux { + groups = "spi3cs3"; + function = "spi3cs3"; + }; + nprd_smi_pins: nprd-smi-mux { + groups = "nprd_smi"; + function = "nprd_smi"; + }; + smi_pins: smi-mux { + groups = "smi"; + function = "smi"; + }; + smb0b_pins: smb0b-mux { + groups = "smb0b"; + function = "smb0b"; + }; + smb0c_pins: smb0c-mux { + groups = "smb0c"; + function = "smb0c"; + }; + smb0den_pins: smb0den-mux { + groups = "smb0den"; + function = "smb0den"; + }; + smb0d_pins: smb0d-mux { + groups = "smb0d"; + function = "smb0d"; + }; + ddc_pins: ddc-mux { + groups = "ddc"; + function = "ddc"; + }; + rg2mdio_pins: rg2mdio-mux { + groups = "rg2mdio"; + function = "rg2mdio"; + }; + wdog1_pins: wdog1-mux { + groups = "wdog1"; + function = "wdog1"; + }; + wdog2_pins: wdog2-mux { + groups = "wdog2"; + function = "wdog2"; + }; + smb12_pins: smb12-mux { + groups = "smb12"; + function = "smb12"; + }; + smb13_pins: smb13-mux { + groups = "smb13"; + function = "smb13"; + }; + spix_pins: spix-mux { + groups = "spix"; + function = "spix"; + }; + spixcs1_pins: spixcs1-mux { + groups = "spixcs1"; + function = "spixcs1"; + }; + clkreq_pins: clkreq-mux { + groups = "clkreq"; + function = "clkreq"; + }; + hgpio0_pins: hgpio0-mux { + groups = "hgpio0"; + function = "hgpio0"; + }; + hgpio1_pins: hgpio1-mux { + groups = "hgpio1"; + function = "hgpio1"; + }; + hgpio2_pins: hgpio2-mux { + groups = "hgpio2"; + function = "hgpio2"; + }; + hgpio3_pins: hgpio3-mux { + groups = "hgpio3"; + function = "hgpio3"; + }; + hgpio4_pins: hgpio4-mux { + groups = "hgpio4"; + function = "hgpio4"; + }; + hgpio5_pins: hgpio5-mux { + groups = "hgpio5"; + function = "hgpio5"; + }; + hgpio6_pins: hgpio6-mux { + groups = "hgpio6"; + function = "hgpio6"; + }; + hgpio7_pins: hgpio7-mux { + groups = "hgpio7"; + function = "hgpio7"; + }; + bu4_pins: bu4-mux { + groups = "bu4"; + function = "bu4"; + }; + bu4b_pins: bu4b-mux { + groups = "bu4b"; + function = "bu4b"; + }; + bu5_pins: bu5-mux { + groups = "bu5"; + function = "bu5"; + }; + bu5b_pins: bu5b-mux { + groups = "bu5b"; + function = "bu5b"; + }; + bu6_pins: bu6-mux { + groups = "bu6"; + function = "bu6"; + }; + gpo187_pins: gpo187-mux { + groups = "gpo187"; + function = "gpo187"; + }; }; }; diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts index eeceb5b292a8..2638ee1c3846 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts @@ -19,6 +19,12 @@ memory@0 { reg = <0x0 0x0 0x0 0x40000000>; }; + + refclk: refclk-25mhz { + compatible = "fixed-clock"; + clock-frequency = <25000000>; + #clock-cells = <0>; + }; }; &serial0 { diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi index e02659efa233..872a69553e3c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -148,6 +148,36 @@ status = "disabled"; }; + i2c2: i2c@c600000 { + compatible = "nvidia,tegra264-i2c"; + reg = <0x0 0x0c600000 0x0 0x10000>; + interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA264_CLK_AON_I2C>, + <&bpmp TEGRA264_CLK_PLLAON>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA264_CLK_AON_I2C>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLAON>; + resets = <&bpmp TEGRA264_RESET_I2C2>; + reset-names = "i2c"; + status = "disabled"; + }; + + i2c3: i2c@c610000 { + compatible = "nvidia,tegra264-i2c"; + reg = <0x0 0x0c610000 0x0 0x10000>; + interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA264_CLK_AON_I2C>, + <&bpmp TEGRA264_CLK_PLLAON>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA264_CLK_AON_I2C>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLAON>; + resets = <&bpmp TEGRA264_RESET_I2C3>; + reset-names = "i2c"; + status = "disabled"; + }; + pmc: pmc@c800000 { compatible = "nvidia,tegra264-pmc"; reg = <0x0 0x0c800000 0x0 0x100000>, @@ -272,6 +302,201 @@ dma-coherent; }; + i2c14: i2c@c410000 { + compatible = "nvidia,tegra264-i2c"; + reg = <0x00 0x0c410000 0x0 0x10000>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA264_RESET_I2C14>; + reset-names = "i2c"; + status = "disabled"; + }; + + i2c15: i2c@c420000 { + compatible = "nvidia,tegra264-i2c"; + reg = <0x00 0x0c420000 0x0 0x10000>; + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA264_RESET_I2C15>; + reset-names = "i2c"; + status = "disabled"; + }; + + i2c16: i2c@c430000 { + compatible = "nvidia,tegra264-i2c"; + reg = <0x00 0x0c430000 0x0 0x10000>; + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA264_RESET_I2C16>; + reset-names = "i2c"; + status = "disabled"; + }; + + i2c0: i2c@c630000 { + compatible = "nvidia,tegra264-i2c"; + reg = <0x00 0x0c630000 0x0 0x10000>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA264_RESET_I2C0>; + reset-names = "i2c"; + status = "disabled"; + }; + + i2c1: i2c@c640000 { + compatible = "nvidia,tegra264-i2c"; + reg = <0x00 0x0c640000 0x0 0x10000>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA264_RESET_I2C1>; + reset-names = "i2c"; + status = "disabled"; + }; + + i2c4: i2c@c650000 { + compatible = "nvidia,tegra264-i2c"; + reg = <0x00 0x0c650000 0x0 0x10000>; + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA264_RESET_I2C4>; + reset-names = "i2c"; + status = "disabled"; + }; + + i2c6: i2c@c670000 { + compatible = "nvidia,tegra264-i2c"; + reg = <0x00 0x0c670000 0x0 0x10000>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA264_RESET_I2C6>; + reset-names = "i2c"; + status = "disabled"; + }; + + i2c7: i2c@c680000 { + compatible = "nvidia,tegra264-i2c"; + reg = <0x00 0x0c680000 0x0 0x10000>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA264_RESET_I2C7>; + reset-names = "i2c"; + status = "disabled"; + }; + + i2c8: i2c@c690000 { + compatible = "nvidia,tegra264-i2c"; + reg = <0x00 0x0c690000 0x0 0x10000>; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA264_RESET_I2C8>; + reset-names = "i2c"; + status = "disabled"; + }; + + i2c9: i2c@c6a0000 { + compatible = "nvidia,tegra264-i2c"; + reg = <0x00 0x0c6a0000 0x0 0x10000>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA264_RESET_I2C9>; + reset-names = "i2c"; + status = "disabled"; + }; + + i2c10: i2c@c6b0000 { + compatible = "nvidia,tegra264-i2c"; + reg = <0x00 0x0c6b0000 0x0 0x10000>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA264_RESET_I2C10>; + reset-names = "i2c"; + status = "disabled"; + }; + + i2c11: i2c@c6c0000 { + compatible = "nvidia,tegra264-i2c"; + reg = <0x00 0x0c6c0000 0x0 0x10000>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA264_RESET_I2C11>; + reset-names = "i2c"; + status = "disabled"; + }; + + i2c12: i2c@c6d0000 { + compatible = "nvidia,tegra264-i2c"; + reg = <0x00 0x0c6d0000 0x0 0x10000>; + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA264_RESET_I2C12>; + reset-names = "i2c"; + status = "disabled"; + }; + gic: interrupt-controller@46000000 { compatible = "arm,gic-v3"; reg = <0x00 0x46000000 0x0 0x010000>, /* GICD */ diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 4bfa926b6a08..296688f7cb26 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8039-t2.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb +dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5018-tplink-archer-ax55-v1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp441.dtb @@ -29,6 +30,12 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp453.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb +dtb-$(CONFIG_ARCH_QCOM) += lemans-evk.dtb + +lemans-evk-camera-csi1-imx577-dtbs := lemans-evk.dtb lemans-evk-camera-csi1-imx577.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camera-csi1-imx577.dtb +dtb-$(CONFIG_ARCH_QCOM) += monaco-evk.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8216-samsung-fortuna3g.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb @@ -71,6 +78,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8939-samsung-a7.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8939-sony-xperia-kanuti-tulip.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8939-wingtech-wt82918.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8939-wingtech-wt82918hd.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8953-flipkart-rimob.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8953-motorola-potter.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-daisy.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-mido.dtb @@ -113,6 +121,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-xiaomi-sagit.dtb dtb-$(CONFIG_ARCH_QCOM) += qcm6490-fairphone-fp5.dtb dtb-$(CONFIG_ARCH_QCOM) += qcm6490-idp.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcm6490-particle-tachyon.dtb dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb @@ -231,9 +240,6 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm632-motorola-ocean.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm670-google-sargo.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb sdm845-db845c-navigation-mezzanine-dtbs := sdm845-db845c.dtb sdm845-db845c-navigation-mezzanine.dtbo @@ -275,6 +281,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8150-sony-xperia-kumano-bahamut.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-sony-xperia-kumano-griffin.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8250-samsung-r8q.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8250-samsung-x1q.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx203.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx206.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-xiaomi-elish-boe.dtb @@ -287,6 +295,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx214.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx215.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8450-samsung-r0q.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx223.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk.dtb @@ -315,6 +324,10 @@ x1e80100-asus-zenbook-a14-el2-dtbs := x1e80100-asus-zenbook-a14.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e80100-asus-zenbook-a14.dtb x1e80100-asus-zenbook-a14-el2.dtb x1e80100-crd-el2-dtbs := x1e80100-crd.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e80100-crd.dtb x1e80100-crd-el2.dtb +x1e80100-dell-inspiron-14-plus-7441-el2-dtbs := x1e80100-dell-inspiron-14-plus-7441.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e80100-dell-inspiron-14-plus-7441.dtb x1e80100-dell-inspiron-14-plus-7441-el2.dtb +x1e80100-dell-latitude-7455-el2-dtbs := x1e80100-dell-latitude-7455.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e80100-dell-latitude-7455.dtb x1e80100-dell-latitude-7455-el2.dtb x1e80100-dell-xps13-9345-el2-dtbs := x1e80100-dell-xps13-9345.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e80100-dell-xps13-9345.dtb x1e80100-dell-xps13-9345-el2.dtb x1e80100-hp-elitebook-ultra-g1q-el2-dtbs := x1e80100-hp-elitebook-ultra-g1q.dtb x1-el2.dtbo @@ -333,3 +346,7 @@ x1p42100-asus-zenbook-a14-el2-dtbs := x1p42100-asus-zenbook-a14.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p42100-asus-zenbook-a14.dtb x1p42100-asus-zenbook-a14-el2.dtb x1p42100-crd-el2-dtbs := x1p42100-crd.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p42100-crd.dtb x1p42100-crd-el2.dtb +x1p42100-hp-omnibook-x14-el2-dtbs := x1p42100-hp-omnibook-x14.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1p42100-hp-omnibook-x14.dtb x1p42100-hp-omnibook-x14-el2.dtb +x1p42100-lenovo-thinkbook-16-el2-dtbs := x1p42100-lenovo-thinkbook-16.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1p42100-lenovo-thinkbook-16.dtb x1p42100-lenovo-thinkbook-16-el2.dtb diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index b0c594c5f236..ba6ccf0db16a 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -157,8 +157,6 @@ status = "okay"; adv_bridge: bridge@39 { - status = "okay"; - compatible = "adi,adv7533"; reg = <0x39>; @@ -181,7 +179,7 @@ pinctrl-names = "default","sleep"; pinctrl-0 = <&adv7533_int_active &adv7533_switch_active>; pinctrl-1 = <&adv7533_int_suspend &adv7533_switch_suspend>; - #sound-dai-cells = <1>; + #sound-dai-cells = <0>; ports { #address-cells = <1>; @@ -346,7 +344,7 @@ sound-dai = <&lpass MI2S_QUATERNARY>; }; codec { - sound-dai = <&adv_bridge 0>; + sound-dai = <&adv_bridge>; }; }; diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts new file mode 100644 index 000000000000..df8d6e5c1f45 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -0,0 +1,1222 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "hamoa-iot-som.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Hamoa IoT EVK"; + compatible = "qcom,hamoa-iot-evk", "qcom,hamoa-iot-som", "qcom,x1e80100"; + chassis-type = "embedded"; + + aliases { + serial0 = &uart21; + serial1 = &uart14; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 + 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>, + <&tlmm 125 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss0_sbu: endpoint { + remote-endpoint = <&usb_1_ss0_sbu_mux>; + }; + }; + }; + }; + + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&retimer_ss1_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss1_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss1_con_sbu_out>; + }; + }; + }; + }; + + connector@2 { + compatible = "usb-c-connector"; + reg = <2>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss2_hs_in: endpoint { + remote-endpoint = <&usb_1_ss2_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss2_ss_in: endpoint { + remote-endpoint = <&retimer_ss2_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss2_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss2_con_sbu_out>; + }; + }; + }; + }; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + /* Left unused as the retimer is not used on this board. */ + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p15: regulator-rtmr1-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p8: regulator-rtmr1-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_3p3: regulator-rtmr1-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr2_1p15: regulator-rtmr2-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR2_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&tlmm 189 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb2_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr2_1p8: regulator-rtmr2-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR2_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 126 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb2_pwr_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr2_3p3: regulator-rtmr2-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR2_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 187 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb2_pwr_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + /* + * TODO: These two regulators are actually part of the removable M.2 + * card and not the EVK mainboard. Need to describe this differently. + * Functionally it works correctly, because all we need to do is to + * turn on the actual 3.3V supply above. + */ + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_wwan: regulator-wwan { + compatible = "regulator-fixed"; + + regulator-name = "SDX_VPH_PWR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 221 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wwan_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E80100-EVK"; + audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT", + "TweeterLeft IN", "WSA WSA_SPK2 OUT", + "WooferRight IN", "WSA2 WSA_SPK2 OUT", + "TweeterRight IN", "WSA2 WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS3", + "VA DMIC1", "MIC BIAS3", + "VA DMIC2", "MIC BIAS1", + "VA DMIC3", "MIC BIAS1", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&left_woofer>, + <&left_tweeter>, + <&swr0 0>, + <&lpass_wsamacro 0>, + <&right_woofer>, + <&right_tweeter>, + <&swr3 0>, + <&lpass_wsa2macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + usb-1-ss0-sbu-mux { + compatible = "onnn,fsusb42", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 168 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 167 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb_1_ss0_sbu_default>; + pinctrl-names = "default"; + + mode-switch; + orientation-switch; + + port { + usb_1_ss0_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_ss0_sbu>; + }; + }; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x08>; + + clocks = <&rpmhcc RPMH_RF_CLK5>; + + vdd-supply = <&vreg_rtmr2_1p15>; + vdd33-supply = <&vreg_rtmr2_3p3>; + vdd33-cap-supply = <&vreg_rtmr2_3p3>; + vddar-supply = <&vreg_rtmr2_1p15>; + vddat-supply = <&vreg_rtmr2_1p15>; + vddio-supply = <&vreg_rtmr2_1p8>; + + reset-gpios = <&tlmm 185 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr2_default>; + pinctrl-names = "default"; + + orientation-switch; + retimer-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss2_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss2_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss2_ss_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss2_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss2_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + eusb3_repeater: redriver@47 { + compatible = "nxp,ptn3222"; + reg = <0x47>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb3_reset_n>; + pinctrl-names = "default"; + }; + + eusb5_repeater: redriver@43 { + compatible = "nxp,ptn3222"; + reg = <0x43>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb5_reset_n>; + pinctrl-names = "default"; + }; + + eusb6_repeater: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb6_reset_n>; + pinctrl-names = "default"; + }; +}; + +&i2c7 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x8>; + + clocks = <&rpmhcc RPMH_RF_CLK4>; + + vdd-supply = <&vreg_rtmr1_1p15>; + vdd33-supply = <&vreg_rtmr1_3p3>; + vdd33-cap-supply = <&vreg_rtmr1_3p3>; + vddar-supply = <&vreg_rtmr1_1p15>; + vddat-supply = <&vreg_rtmr1_1p15>; + vddio-supply = <&vreg_rtmr1_1p8>; + + reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr1_default>; + pinctrl-names = "default"; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss1_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss1_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_con_sbu_in>; + }; + }; + }; + }; +}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + spkr_23_sd_n_active: spkr-23-sd-n-active-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>, <&dmic23_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <4800000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp2 { + status = "okay"; +}; + +&mdss_dp2_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + power-supply = <&vreg_edp_3p3>; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; +}; + +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie6a { + vddpe-3v3-supply = <&vreg_nvme>; +}; + +&pm8550_gpios { + rtmr0_default: rtmr0-reset-n-active-state { + pins = "gpio10"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; + + usb0_3p3_reg_en: usb0-3p3-reg-en-state { + pins = "gpio11"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pm8550ve_9_gpios { + usb0_1p8_reg_en: usb0-1p8-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pmc8380_5_gpios { + usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&smb2360_0 { + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1 { + status = "okay"; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&smb2360_2 { + status = "okay"; +}; + +&smb2360_2_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l8b_3p0>; +}; + +&swr0 { + status = "okay"; + + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Left Woofer */ + left_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Left Tweeter */ + left_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&swr3 { + status = "okay"; + + pinctrl-0 = <&wsa2_swr_active>, <&spkr_23_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Right Woofer */ + right_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Tweeter */ + right_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&tlmm { + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + eusb3_reset_n: eusb3-reset-n-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + eusb5_reset_n: eusb5-reset-n-state { + pins = "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + output-low; + }; + + eusb6_reset_n: eusb6-reset-n-state { + pins = "gpio184"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + output-low; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + rtmr1_default: rtmr1-reset-n-active-state { + pins = "gpio176"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + rtmr2_default: rtmr2-reset-n-active-state { + pins = "gpio185"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb1_pwr_1p15_reg_en: usb1-pwr-1p15-reg-en-state { + pins = "gpio188"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb1_pwr_1p8_reg_en: usb1-pwr-1p8-reg-en-state { + pins = "gpio175"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb1_pwr_3p3_reg_en: usb1-pwr-3p3-reg-en-state { + pins = "gpio186"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb2_pwr_1p15_reg_en: usb2-pwr-1p15-reg-en-state { + pins = "gpio189"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb2_pwr_1p8_reg_en: usb2-pwr-1p8-reg-en-state { + pins = "gpio126"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb2_pwr_3p3_reg_en: usb2-pwr-3p3-reg-en-state { + pins = "gpio187"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb_1_ss0_sbu_default: usb-1-ss0-sbu-state { + mode-pins { + pins = "gpio166"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + output-high; + }; + + oe-n-pins { + pins = "gpio168"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + + sel-pins { + pins = "gpio167"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio191"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + wcn_bt_en: wcn-bt-en-state { + pins = "gpio116"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wwan_sw_en: wwan-sw-en-state { + pins = "gpio221"; + function = "gpio"; + drive-strength = <4>; + bias-disable; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + /* Switches USB signal routing between the USB connector and the Wi-Fi card. */ + wcn_usb_sw_n: wcn-usb-sw-n-state { + pins = "gpio225"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-high; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + +&uart21 { + compatible = "qcom,geni-debug-uart"; + + status = "okay"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_hsphy { + phys = <&smb2360_0_eusb2_repeater>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&pmic_glink_ss0_ss_in>; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_hsphy { + phys = <&smb2360_1_eusb2_repeater>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&retimer_ss1_ss_in>; +}; + +&usb_1_ss2_dwc3_hs { + remote-endpoint = <&pmic_glink_ss2_hs_in>; +}; + +&usb_1_ss2_hsphy { + phys = <&smb2360_2_eusb2_repeater>; +}; + +&usb_1_ss2_qmpphy_out { + remote-endpoint = <&retimer_ss2_ss_in>; +}; + +&usb_2_hsphy { + phys = <&eusb5_repeater>; + + pinctrl-0 = <&wcn_usb_sw_n>; + pinctrl-names = "default"; +}; + +&usb_mp_hsphy0 { + phys = <&eusb3_repeater>; +}; + +&usb_mp_hsphy1 { + phys = <&eusb6_repeater>; +}; diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi new file mode 100644 index 000000000000..1aead50b8920 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi @@ -0,0 +1,619 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include "x1e80100.dtsi" +#include "x1e80100-pmics.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> + +/ { + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; +}; + +&apps_rsc { + /* PMC8380C_B */ + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5b_3p0: ldo5 { + regulator-name = "vreg_l5b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7b_2p8: ldo7 { + regulator-name = "vreg_l7b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name = "vreg_l8b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name = "vreg_l10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-always-on; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-always-on; + }; + + vreg_l16b_2p9: ldo16 { + regulator-name = "vreg_l16b_2p9"; + regulator-min-microvolt = <2912000>; + regulator-max-microvolt = <2912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + /* PMC8380VE_C */ + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name = "vreg_l2c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + /* PMC8380_D */ + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + /* PMC8380_E */ + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + /* PMC8380_F */ + regulators-4 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name = "vreg_s1f_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1f_1p0: ldo1 { + regulator-name = "vreg_l1f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2f_1p0: ldo2 { + regulator-name = "vreg_l2f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3f_1p0: ldo3 { + regulator-name = "vreg_l3f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + /* PMC8380VE_I */ + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + + vreg_s1i_0p9: smps1 { + regulator-name = "vreg_s1i_0p9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s2i_1p0: smps2 { + regulator-name = "vreg_s2i_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1i_1p8: ldo1 { + regulator-name = "vreg_l1i_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + /* PMC8380VE_J */ + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name = "vreg_l1j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +&iris { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/x1e80100/gen70500_zap.mbn"; +}; + +&pcie4 { + perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie6a { + perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie6a_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/adsp.mbn", + "qcom/x1e80100/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/cdsp.mbn", + "qcom/x1e80100/cdsp_dtb.mbn"; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <34 2>, /* TPM LP & INT */ + <44 4>; /* SPI (TPM) */ + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + + }; + }; +}; + +&usb_1_ss0 { + status = "okay"; +}; + +&usb_1_ss0_dwc3 { + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + + status = "okay"; +}; + +&usb_1_ss1 { + status = "okay"; +}; + +&usb_1_ss1_dwc3 { + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_1_ss2 { + status = "okay"; +}; + +&usb_1_ss2_dwc3 { + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_ss2_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&usb_1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_mp { + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts index 43def95e9275..df3cbb7c79c4 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts +++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts @@ -120,5 +120,6 @@ }; &xo_board_clk { - clock-frequency = <24000000>; + clock-div = <4>; + clock-mult = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts b/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts index 5bb021cb29cd..7a25af57749c 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts +++ b/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts @@ -124,5 +124,6 @@ }; &xo_board_clk { - clock-frequency = <24000000>; + clock-div = <4>; + clock-mult = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 130360014c5e..f024b3cba33f 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -2,13 +2,15 @@ /* * IPQ5018 SoC device tree source * - * Copyright (c) 2023 The Linux Foundation. All rights reserved. + * Copyright (c) 2023-2025 The Linux Foundation. All rights reserved. */ #include <dt-bindings/clock/qcom,apss-ipq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-ipq5018.h> +#include <dt-bindings/clock/qcom,ipq5018-cmn-pll.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/reset/qcom,gcc-ipq5018.h> +#include <dt-bindings/thermal/thermal.h> / { interrupt-parent = <&intc>; @@ -16,14 +18,41 @@ #size-cells = <2>; clocks { + gephy_rx_clk: gephy-rx-clk { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + #clock-cells = <0>; + }; + + gephy_tx_clk: gephy-tx-clk { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + #clock-cells = <0>; + }; + + ref_96mhz_clk: ref-96mhz-clk { + compatible = "fixed-factor-clock"; + clocks = <&xo_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <2>; + }; + sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; }; xo_board_clk: xo-board-clk { + compatible = "fixed-factor-clock"; + clocks = <&ref_96mhz_clk>; + #clock-cells = <0>; + }; + + xo_clk: xo-clk { compatible = "fixed-clock"; #clock-cells = <0>; + clock-frequency = <48000000>; }; }; @@ -39,6 +68,7 @@ next-level-cache = <&l2_0>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -49,6 +79,7 @@ next-level-cache = <&l2_0>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; }; l2_0: l2-cache { @@ -182,6 +213,201 @@ status = "disabled"; }; + mdio0: mdio@88000 { + compatible = "qcom,ipq5018-mdio"; + reg = <0x00088000 0x64>, + <0x019475c4 0x4>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&gcc GCC_MDIO0_AHB_CLK>; + clock-names = "gcc_mdio_ahb_clk"; + + status = "disabled"; + + ge_phy: ethernet-phy@7 { + compatible = "ethernet-phy-id004d.d0c0"; + reg = <7>; + + resets = <&gcc GCC_GEPHY_MISC_ARES>; + }; + }; + + mdio1: mdio@90000 { + compatible = "qcom,ipq5018-mdio"; + reg = <0x00090000 0x64>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&gcc GCC_MDIO1_AHB_CLK>; + clock-names = "gcc_mdio_ahb_clk"; + + status = "disabled"; + }; + + cmn_pll: clock-controller@9b000 { + compatible = "qcom,ipq5018-cmn-pll"; + reg = <0x0009b000 0x800>; + clocks = <&ref_96mhz_clk>, + <&gcc GCC_CMN_BLK_AHB_CLK>, + <&gcc GCC_CMN_BLK_SYS_CLK>; + clock-names = "ref", + "ahb", + "sys"; + #clock-cells = <1>; + assigned-clocks = <&cmn_pll IPQ5018_CMN_PLL_CLK>; + assigned-clock-rates-u64 = /bits/ 64 <9600000000>; + }; + + qfprom: qfprom@a0000 { + compatible = "qcom,ipq5018-qfprom", "qcom,qfprom"; + reg = <0x000a0000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + tsens_mode: mode@249 { + reg = <0x249 0x1>; + bits = <0 3>; + }; + + tsens_base1: base1@249 { + reg = <0x249 0x2>; + bits = <3 8>; + }; + + tsens_base2: base2@24a { + reg = <0x24a 0x2>; + bits = <3 8>; + }; + + tsens_s0_p1: s0-p1@24b { + reg = <0x24b 0x2>; + bits = <2 6>; + }; + + tsens_s0_p2: s0-p2@24c { + reg = <0x24c 0x1>; + bits = <1 6>; + }; + + tsens_s1_p1: s1-p1@24c { + reg = <0x24c 0x2>; + bits = <7 6>; + }; + + tsens_s1_p2: s1-p2@24d { + reg = <0x24d 0x2>; + bits = <5 6>; + }; + + tsens_s2_p1: s2-p1@24e { + reg = <0x24e 0x2>; + bits = <3 6>; + }; + + tsens_s2_p2: s2-p2@24f { + reg = <0x24f 0x1>; + bits = <1 6>; + }; + + tsens_s3_p1: s3-p1@24f { + reg = <0x24f 0x2>; + bits = <7 6>; + }; + + tsens_s3_p2: s3-p2@250 { + reg = <0x250 0x2>; + bits = <5 6>; + }; + + tsens_s4_p1: s4-p1@251 { + reg = <0x251 0x2>; + bits = <3 6>; + }; + + tsens_s4_p2: s4-p2@254 { + reg = <0x254 0x1>; + bits = <0 6>; + }; + }; + + prng: rng@e3000 { + compatible = "qcom,prng-ee"; + reg = <0x000e3000 0x1000>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + status = "disabled"; + }; + + tsens: thermal-sensor@4a9000 { + compatible = "qcom,ipq5018-tsens", "qcom,tsens-v1"; + reg = <0x004a9000 0x1000>, + <0x004a8000 0x1000>; + + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, + <&tsens_base2>, + <&tsens_s0_p1>, + <&tsens_s0_p2>, + <&tsens_s1_p1>, + <&tsens_s1_p2>, + <&tsens_s2_p1>, + <&tsens_s2_p2>, + <&tsens_s3_p1>, + <&tsens_s3_p2>, + <&tsens_s4_p1>, + <&tsens_s4_p2>; + + nvmem-cell-names = "mode", + "base1", + "base2", + "s0_p1", + "s0_p2", + "s1_p1", + "s1_p2", + "s2_p1", + "s2_p2", + "s3_p1", + "s3_p2", + "s4_p1", + "s4_p2"; + + interrupts = <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "uplow"; + #qcom,sensors = <5>; + #thermal-sensor-cells = <1>; + }; + + cryptobam: dma-controller@704000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x00704000 0x20000>; + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names = "bam_clk"; + + #dma-cells = <1>; + qcom,ee = <1>; + qcom,controlled-remotely; + }; + + crypto: crypto@73a000 { + compatible = "qcom,crypto-v5.1"; + reg = <0x0073a000 0x6000>; + + clocks = <&gcc GCC_CRYPTO_AHB_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_CLK>; + clock-names = "iface", + "bus", + "core"; + + dmas = <&cryptobam 2>, + <&cryptobam 3>; + dma-names = "rx", + "tx"; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq5018-tlmm"; reg = <0x01000000 0x300000>; @@ -208,8 +434,8 @@ <&pcie0_phy>, <&pcie1_phy>, <0>, - <0>, - <0>, + <&gephy_rx_clk>, + <&gephy_tx_clk>, <0>, <0>; #clock-cells = <1>; @@ -264,6 +490,16 @@ status = "disabled"; }; + blsp1_uart2: serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b0000 0x200>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + blsp1_spi1: spi@78b5000 { compatible = "qcom,spi-qup-v2.2.1"; #address-cells = <1>; @@ -278,6 +514,59 @@ status = "disabled"; }; + blsp1_i2c3: i2c@78b7000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b7000 0x600>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + dmas = <&blsp_dma 9>, <&blsp_dma 8>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qpic_bam: dma-controller@7984000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x07984000 0x1c000>; + + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QPIC_AHB_CLK>; + clock-names = "bam_clk"; + + #dma-cells = <1>; + qcom,ee = <0>; + + status = "disabled"; + }; + + qpic_nand: spi@79b0000 { + compatible = "qcom,ipq5018-snand", "qcom,ipq9574-snand"; + reg = <0x079b0000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>, + <&gcc GCC_QPIC_IO_MACRO_CLK>; + clock-names = "core", + "aon", + "iom"; + + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", + "rx", + "cmd"; + + status = "disabled"; + }; + usb: usb@8af8800 { compatible = "qcom,ipq5018-dwc3", "qcom,dwc3"; reg = <0x08af8800 0x400>; @@ -453,7 +742,7 @@ max-link-speed = <2>; phys = <&pcie1_phy>; - phy-names ="pciephy"; + phy-names = "pciephy"; ranges = <0x01000000 0 0x00000000 0x80200000 0 0x00100000>, <0x02000000 0 0x80300000 0x80300000 0 0x10000000>; @@ -481,10 +770,10 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 142 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 143 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 144 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 145 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, <&gcc GCC_PCIE1_AXI_M_CLK>, @@ -554,7 +843,7 @@ max-link-speed = <2>; phys = <&pcie0_phy>; - phy-names ="pciephy"; + phy-names = "pciephy"; ranges = <0x01000000 0 0x00000000 0xa0200000 0 0x00100000>, <0x02000000 0 0xa0300000 0xa0300000 0 0x10000000>; @@ -582,10 +871,10 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 78 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 79 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, <&gcc GCC_PCIE0_AXI_M_CLK>, @@ -631,6 +920,70 @@ }; }; + thermal-zones { + cpu-thermal { + thermal-sensors = <&tsens 2>; + + trips { + cpu-critical { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + + cpu_alert: cpu-passive { + temperature = <100000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gephy-thermal { + thermal-sensors = <&tsens 4>; + + trips { + gephy-critical { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + top-glue-thermal { + thermal-sensors = <&tsens 3>; + + trips { + top-glue-critical { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + ubi32-thermal { + thermal-sensors = <&tsens 1>; + + trips { + ubi32-critical { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index bd28c490415f..45fc512a3bab 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -632,10 +632,10 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 412 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 413 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 414 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 415 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE3X2_AXI_M_CLK>, <&gcc GCC_PCIE3X2_AXI_S_CLK>, @@ -736,10 +736,10 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 36 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 37 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 38 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE3X1_0_AXI_M_CLK>, <&gcc GCC_PCIE3X1_0_AXI_S_CLK>, diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts index 1f89530cb035..738618551203 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts @@ -2,7 +2,7 @@ /* * IPQ5424 RDP466 board device tree source * - * Copyright (c) 2024 The Linux Foundation. All rights reserved. + * Copyright (c) 2024-2025 The Linux Foundation. All rights reserved. */ /dts-v1/; @@ -224,6 +224,13 @@ }; }; + uart0_pins: uart0-default-state { + pins = "gpio10", "gpio11", "gpio12", "gpio13"; + function = "uart0"; + drive-strength = <8>; + bias-pull-down; + }; + pcie2_default_state: pcie2-default-state { pins = "gpio31"; function = "gpio"; @@ -239,6 +246,17 @@ }; }; +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + /* + * The required initialization for this SE is not handled by the + * bootloader. Therefore, keep the device in "reserved" state until + * linux gains support for configuring the SE. + */ + status = "reserved"; +}; + &uart1 { pinctrl-0 = <&uart1_pins>; pinctrl-names = "default"; @@ -253,6 +271,26 @@ status = "okay"; }; +/* + * The bootstrap pins for the board select the XO clock frequency that + * supports 48 MHZ, 96 MHZ or 192 MHZ. This setting automatically + * enables the right dividers, to ensure the reference clock output + * from WiFi to the CMN PLL is 48 MHZ. + */ +&ref_48mhz_clk { + clock-div = <1>; + clock-mult = <1>; +}; + +/* + * The frequency of xo_board is fixed to 24 MHZ, which is routed + * from WiFi output clock 48 MHZ divided by 2. + */ &xo_board { - clock-frequency = <24000000>; + clock-div = <2>; + clock-mult = <1>; +}; + +&xo_clk { + clock-frequency = <48000000>; }; diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index 66bd2261eb25..ef2b52f3597d 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -3,10 +3,12 @@ * IPQ5424 device tree source * * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,apss-ipq.h> +#include <dt-bindings/clock/qcom,ipq5424-cmn-pll.h> #include <dt-bindings/clock/qcom,ipq5424-gcc.h> #include <dt-bindings/reset/qcom,ipq5424-gcc.h> #include <dt-bindings/interconnect/qcom,ipq5424.h> @@ -18,12 +20,24 @@ interrupt-parent = <&intc>; clocks { + ref_48mhz_clk: ref-48mhz-clk { + compatible = "fixed-factor-clock"; + clocks = <&xo_clk>; + #clock-cells = <0>; + }; + sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; }; xo_board: xo-board-clk { + compatible = "fixed-factor-clock"; + clocks = <&ref_48mhz_clk>; + #clock-cells = <0>; + }; + + xo_clk: xo-clk { compatible = "fixed-clock"; #clock-cells = <0>; }; @@ -39,6 +53,11 @@ reg = <0x0>; enable-method = "psci"; next-level-cache = <&l2_0>; + clocks = <&apss_clk APSS_SILVER_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; + l2_0: l2-cache { compatible = "cache"; cache-level = <2>; @@ -59,6 +78,10 @@ enable-method = "psci"; reg = <0x100>; next-level-cache = <&l2_100>; + clocks = <&apss_clk APSS_SILVER_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; l2_100: l2-cache { compatible = "cache"; @@ -74,6 +97,10 @@ enable-method = "psci"; reg = <0x200>; next-level-cache = <&l2_200>; + clocks = <&apss_clk APSS_SILVER_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; l2_200: l2-cache { compatible = "cache"; @@ -89,6 +116,10 @@ enable-method = "psci"; reg = <0x300>; next-level-cache = <&l2_300>; + clocks = <&apss_clk APSS_SILVER_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; l2_300: l2-cache { compatible = "cache"; @@ -106,6 +137,36 @@ }; }; + cpu_opp_table: opp-table-cpu { + compatible = "operating-points-v2-kryo-cpu"; + opp-shared; + nvmem-cells = <&cpu_speed_bin>; + + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <850000>; + opp-supported-hw = <0x3>; + clock-latency-ns = <200000>; + opp-peak-kBps = <816000>; + }; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <850000>; + opp-supported-hw = <0x3>; + clock-latency-ns = <200000>; + opp-peak-kBps = <984000>; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1000000>; + opp-supported-hw = <0x1>; + clock-latency-ns = <200000>; + opp-peak-kBps = <1272000>; + }; + }; + memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ @@ -150,6 +211,12 @@ hwlocks = <&tcsr_mutex 3>; }; + + tfa@8a832000 { + reg = <0x0 0x8a832000 0x0 0x7d000>; + no-map; + status = "disabled"; + }; }; soc@0 { @@ -210,6 +277,18 @@ status = "disabled"; }; + cmn_pll: clock-controller@9b000 { + compatible = "qcom,ipq5424-cmn-pll"; + reg = <0 0x0009b000 0 0x800>; + clocks = <&ref_48mhz_clk>, + <&gcc GCC_CMN_12GPLL_AHB_CLK>, + <&gcc GCC_CMN_12GPLL_SYS_CLK>; + clock-names = "ref", "ahb", "sys"; + #clock-cells = <1>; + assigned-clocks = <&cmn_pll IPQ5424_CMN_PLL_CLK>; + assigned-clock-rates-u64 = /bits/ 64 <12000000000>; + }; + efuse@a4000 { compatible = "qcom,ipq5424-qfprom", "qcom,qfprom"; reg = <0 0x000a4000 0 0x741>; @@ -363,6 +442,18 @@ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; }; + qfprom@a6000 { + compatible = "qcom,ipq5424-qfprom", "qcom,qfprom"; + reg = <0x0 0x000a6000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + cpu_speed_bin: cpu-speed-bin@234 { + reg = <0x234 0x1>; + bits = <0 8>; + }; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq5424-tlmm"; reg = <0 0x01000000 0 0x300000>; @@ -417,6 +508,15 @@ #address-cells = <2>; #size-cells = <2>; + uart0: serial@1a80000 { + compatible = "qcom,geni-uart"; + reg = <0 0x01a80000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_UART0_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + uart1: serial@1a84000 { compatible = "qcom,geni-debug-uart"; reg = <0 0x01a84000 0 0x4000>; @@ -471,6 +571,7 @@ compatible = "arm,gic-v3"; reg = <0 0xf200000 0 0x10000>, /* GICD */ <0 0xf240000 0 0x80000>; /* GICR * 4 regions */ + #address-cells = <0>; #interrupt-cells = <0x3>; interrupt-controller; #redistributor-regions = <1>; @@ -705,6 +806,15 @@ }; }; + apss_clk: clock-controller@fa80000 { + compatible = "qcom,ipq5424-apss-clk"; + reg = <0x0 0x0fa80000 0x0 0x20000>; + clocks = <&xo_board>, + <&gcc GPLL0>; + #clock-cells = <1>; + #interconnect-cells = <1>; + }; + pcie3: pcie@40000000 { compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574"; reg = <0x0 0x40000000 0x0 0xf1c>, @@ -752,10 +862,10 @@ #interrupt-cells = <1>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 479 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 480 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 481 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 482 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 480 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE3_AXI_M_CLK>, <&gcc GCC_PCIE3_AXI_S_CLK>, @@ -855,10 +965,10 @@ #interrupt-cells = <1>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 464 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 465 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 466 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 467 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE2_AXI_M_CLK>, <&gcc GCC_PCIE2_AXI_S_CLK>, @@ -958,10 +1068,10 @@ #interrupt-cells = <1>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 449 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 450 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 451 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 452 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE1_AXI_M_CLK>, <&gcc GCC_PCIE1_AXI_S_CLK>, @@ -1061,10 +1171,10 @@ #interrupt-cells = <1>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 436 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 437 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE0_AXI_M_CLK>, <&gcc GCC_PCIE0_AXI_S_CLK>, diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index bfe59b020841..40f1c262126e 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -906,10 +906,10 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, <&gcc GCC_PCIE0_AXI_M_CLK>, diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index fffb47ec2448..256e12cf6d54 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -867,13 +867,13 @@ "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 142 + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 143 + <0 0 0 2 &intc 0 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 144 + <0 0 0 3 &intc 0 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 145 + <0 0 0 4 &intc 0 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, @@ -955,13 +955,13 @@ "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 75 + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 78 + <0 0 0 2 &intc 0 GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 79 + <0 0 0 3 &intc 0 GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 83 + <0 0 0 4 &intc 0 GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts index fa7bb521e786..5a546a14998b 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts @@ -128,36 +128,4 @@ bias-pull-up; }; }; - - sdc_default_state: sdc-default-state { - clk-pins { - pins = "gpio5"; - function = "sdc_clk"; - drive-strength = <8>; - bias-disable; - }; - - cmd-pins { - pins = "gpio4"; - function = "sdc_cmd"; - drive-strength = <8>; - bias-pull-up; - }; - - data-pins { - pins = "gpio0", "gpio1", "gpio2", - "gpio3", "gpio6", "gpio7", - "gpio8", "gpio9"; - function = "sdc_data"; - drive-strength = <8>; - bias-pull-up; - }; - - rclk-pins { - pins = "gpio10"; - function = "sdc_rclk"; - drive-strength = <8>; - bias-pull-down; - }; - }; }; diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 815b5f9540b8..86c9cb9fffc9 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -946,10 +946,10 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 49 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 84 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 85 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE1_AXI_M_CLK>, <&gcc GCC_PCIE1_AXI_S_CLK>, @@ -1032,10 +1032,10 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 189 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 190 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 191 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 192 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE3_AXI_M_CLK>, <&gcc GCC_PCIE3_AXI_S_CLK>, @@ -1118,10 +1118,10 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 164 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 165 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 186 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 187 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE2_AXI_M_CLK>, <&gcc GCC_PCIE2_AXI_S_CLK>, @@ -1161,7 +1161,7 @@ status = "disabled"; }; - pcie0: pci@28000000 { + pcie0: pcie@28000000 { compatible = "qcom,pcie-ipq9574"; reg = <0x28000000 0xf1d>, <0x28000f20 0xa8>, @@ -1203,10 +1203,10 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 78 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 79 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE0_AXI_M_CLK>, <&gcc GCC_PCIE0_AXI_S_CLK>, diff --git a/arch/arm64/boot/dts/qcom/lemans-auto.dtsi b/arch/arm64/boot/dts/qcom/lemans-auto.dtsi new file mode 100644 index 000000000000..8db958d60fd1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-auto.dtsi @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +/dts-v1/; + +#include "lemans.dtsi" + +/delete-node/ &pil_camera_mem; +/delete-node/ &pil_adsp_mem; +/delete-node/ &q6_adsp_dtb_mem; +/delete-node/ &q6_gdsp0_dtb_mem; +/delete-node/ &pil_gdsp0_mem; +/delete-node/ &pil_gdsp1_mem; +/delete-node/ &q6_gdsp1_dtb_mem; +/delete-node/ &q6_cdsp0_dtb_mem; +/delete-node/ &pil_cdsp0_mem; +/delete-node/ &pil_gpu_mem; +/delete-node/ &pil_cdsp1_mem; +/delete-node/ &q6_cdsp1_dtb_mem; +/delete-node/ &pil_cvp_mem; +/delete-node/ &pil_video_mem; +/delete-node/ &gunyah_md_mem; + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + tz_ffi_mem: tz-ffi@91c00000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x91c00000 0x0 0x1400000>; + no-map; + }; + + pil_camera_mem: pil-camera@95200000 { + reg = <0x0 0x95200000 0x0 0x500000>; + no-map; + }; + + pil_adsp_mem: pil-adsp@95c00000 { + reg = <0x0 0x95c00000 0x0 0x1e00000>; + no-map; + }; + + pil_gdsp0_mem: pil-gdsp0@97b00000 { + reg = <0x0 0x97b00000 0x0 0x1e00000>; + no-map; + }; + + pil_gdsp1_mem: pil-gdsp1@99900000 { + reg = <0x0 0x99900000 0x0 0x1e00000>; + no-map; + }; + + pil_cdsp0_mem: pil-cdsp0@9b800000 { + reg = <0x0 0x9b800000 0x0 0x1e00000>; + no-map; + }; + + pil_gpu_mem: pil-gpu@9d600000 { + reg = <0x0 0x9d600000 0x0 0x2000>; + no-map; + }; + + pil_cdsp1_mem: pil-cdsp1@9d700000 { + reg = <0x0 0x9d700000 0x0 0x1e00000>; + no-map; + }; + + pil_cvp_mem: pil-cvp@9f500000 { + reg = <0x0 0x9f500000 0x0 0x700000>; + no-map; + }; + + pil_video_mem: pil-video@9fc00000 { + reg = <0x0 0x9fc00000 0x0 0x700000>; + no-map; + }; + + audio_mdf_mem: audio-mdf-region@ae000000 { + reg = <0x0 0xae000000 0x0 0x1000000>; + no-map; + }; + + hyptz_reserved_mem: hyptz-reserved@beb00000 { + reg = <0x0 0xbeb00000 0x0 0x11500000>; + no-map; + }; + + trusted_apps_mem: trusted-apps@d1900000 { + reg = <0x0 0xd1900000 0x0 0x3800000>; + no-map; + }; + }; + + firmware { + scm { + memory-region = <&tz_ffi_mem>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-camera-csi1-imx577.dtso b/arch/arm64/boot/dts/qcom/lemans-evk-camera-csi1-imx577.dtso new file mode 100644 index 000000000000..769befadd4e4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-evk-camera-csi1-imx577.dtso @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/qcom,sa8775p-camcc.h> +#include <dt-bindings/gpio/gpio.h> + +&{/} { + vreg_cam1_1p8: regulator-cam1 { + compatible = "regulator-fixed"; + regulator-name = "vreg_cam1"; + startup-delay-us = <10000>; + enable-active-high; + gpio = <&pmm8654au_0_gpios 8 GPIO_ACTIVE_HIGH>; + }; +}; + +&camss { + vdda-pll-supply = <&vreg_l1c>; + vdda-phy-supply = <&vreg_l4a>; + + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + csiphy1_ep: endpoint { + clock-lanes = <7>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&imx577_ep1>; + }; + }; + }; +}; + +&cci1 { + pinctrl-0 = <&cci1_0_default>; + pinctrl-1 = <&cci1_0_sleep>; + + status = "okay"; +}; + +&cci1_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + camera@1a { + compatible = "sony,imx577"; + reg = <0x1a>; + + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&cam1_default>; + pinctrl-names = "default"; + + clocks = <&camcc CAM_CC_MCLK1_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK1_CLK>; + assigned-clock-rates = <24000000>; + + dovdd-supply = <&vreg_s4a>; + avdd-supply = <&vreg_cam1_1p8>; + + port { + imx577_ep1: endpoint { + clock-lanes = <7>; + link-frequencies = /bits/ 64 <600000000>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&csiphy1_ep>; + }; + }; + }; +}; + +&tlmm { + cam1_default: cam1-default-state { + mclk-pins { + pins = "gpio73"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + rst-pins { + pins = "gpio133"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts new file mode 100644 index 000000000000..c7dc9b8f4457 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -0,0 +1,776 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/sound/qcom,q6afe.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> + +#include "lemans.dtsi" +#include "lemans-pmics.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lemans EVK"; + compatible = "qcom,lemans-evk", "qcom,qcs9100", "qcom,sa8775p"; + + aliases { + ethernet0 = ðernet0; + mmc1 = &sdhc; + serial0 = &uart10; + }; + + dmic: audio-codec-0 { + compatible = "dmic-codec"; + #sound-dai-cells = <0>; + num-channels = <1>; + }; + + max98357a: audio-codec-1 { + compatible = "maxim,max98357a"; + #sound-dai-cells = <0>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + edp0-connector { + compatible = "dp-connector"; + label = "EDP0"; + type = "mini"; + + port { + edp0_connector_in: endpoint { + remote-endpoint = <&mdss0_dp0_out>; + }; + }; + }; + + edp1-connector { + compatible = "dp-connector"; + label = "EDP1"; + type = "mini"; + + port { + edp1_connector_in: endpoint { + remote-endpoint = <&mdss0_dp1_out>; + }; + }; + }; + + sound { + compatible = "qcom,qcs9100-sndcard"; + model = "LEMANS-EVK"; + + pinctrl-0 = <&hs0_mi2s_active>, <&hs2_mi2s_active>; + pinctrl-names = "default"; + + hs0-mi2s-playback-dai-link { + link-name = "HS0 MI2S Playback"; + + codec { + sound-dai = <&max98357a>; + }; + + cpu { + sound-dai = <&q6apmbedai PRIMARY_MI2S_RX>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + hs2-mi2s-capture-dai-link { + link-name = "HS2 MI2S Capture"; + + codec { + sound-dai = <&dmic>; + }; + + cpu { + sound-dai = <&q6apmbedai TERTIARY_MI2S_TX>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + vmmc_sdc: regulator-vmmc-sdc { + compatible = "regulator-fixed"; + + regulator-name = "vmmc_sdc"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + vreg_sdc: regulator-vreg-sdc { + compatible = "regulator-gpio"; + + regulator-name = "vreg_sdc"; + regulator-type = "voltage"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + + gpios = <&expander1 7 GPIO_ACTIVE_HIGH>; + states = <1800000 1>, <2950000 0>; + + startup-delay-us = <100>; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_s4a: smps4 { + regulator-name = "vreg_s4a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1816000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s5a: smps5 { + regulator-name = "vreg_s5a"; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1996000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s9a: smps9 { + regulator-name = "vreg_s9a"; + regulator-min-microvolt = <535000>; + regulator-max-microvolt = <1120000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4a: ldo4 { + regulator-name = "vreg_l4a"; + regulator-min-microvolt = <788000>; + regulator-max-microvolt = <1050000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5a: ldo5 { + regulator-name = "vreg_l5a"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6a: ldo6 { + regulator-name = "vreg_l6a"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7a: ldo7 { + regulator-name = "vreg_l7a"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8a: ldo8 { + regulator-name = "vreg_l8a"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9a: ldo9 { + regulator-name = "vreg_l9a"; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-1 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_l1c: ldo1 { + regulator-name = "vreg_l1c"; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2c: ldo2 { + regulator-name = "vreg_l2c"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3c: ldo3 { + regulator-name = "vreg_l3c"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4c: ldo4 { + regulator-name = "vreg_l4c"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5c: ldo5 { + regulator-name = "vreg_l5c"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6c: ldo6 { + regulator-name = "vreg_l6c"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7c: ldo7 { + regulator-name = "vreg_l7c"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8c: ldo8 { + regulator-name = "vreg_l8c"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9c: ldo9 { + regulator-name = "vreg_l9c"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2700000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-2 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "e"; + + vreg_s4e: smps4 { + regulator-name = "vreg_s4e"; + regulator-min-microvolt = <970000>; + regulator-max-microvolt = <1520000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s7e: smps7 { + regulator-name = "vreg_s7e"; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s9e: smps9 { + regulator-name = "vreg_s9e"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <570000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6e: ldo6 { + regulator-name = "vreg_l6e"; + regulator-min-microvolt = <1280000>; + regulator-max-microvolt = <1450000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8e: ldo8 { + regulator-name = "vreg_l8e"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +ðernet0 { + phy-handle = <&hsgmii_phy0>; + phy-mode = "2500base-x"; + + pinctrl-0 = <ðernet0_default>; + pinctrl-names = "default"; + + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + + nvmem-cells = <&mac_addr0>; + nvmem-cell-names = "mac-address"; + + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + hsgmii_phy0: ethernet-phy@1c { + compatible = "ethernet-phy-id004d.d101"; + reg = <0x1c>; + reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpi_dma2 { + status = "okay"; +}; + +&i2c18 { + status = "okay"; + + expander0: gpio@38 { + compatible = "ti,tca9538"; + reg = <0x38>; + #gpio-cells = <2>; + gpio-controller; + }; + + expander1: gpio@39 { + compatible = "ti,tca9538"; + reg = <0x39>; + #gpio-cells = <2>; + gpio-controller; + }; + + expander2: gpio@3a { + compatible = "ti,tca9538"; + reg = <0x3a>; + #gpio-cells = <2>; + gpio-controller; + }; + + expander3: gpio@3b { + compatible = "ti,tca9538"; + reg = <0x3b>; + #gpio-cells = <2>; + gpio-controller; + }; + + eeprom@50 { + compatible = "giantec,gt24c256c", "atmel,24c256"; + reg = <0x50>; + pagesize = <64>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + mac_addr0: mac-addr@0 { + reg = <0x0 0x6>; + }; + }; + }; +}; + +&iris { + firmware-name = "qcom/vpu/vpu30_p4_s6_16mb.mbn"; + + status = "okay"; +}; + +&mdss0 { + status = "okay"; +}; + +&mdss0_dp0 { + pinctrl-0 = <&dp0_hot_plug_det>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&mdss0_dp0_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp0_connector_in>; +}; + +&mdss0_dp0_phy { + vdda-phy-supply = <&vreg_l1c>; + vdda-pll-supply = <&vreg_l4a>; + + status = "okay"; +}; + +&mdss0_dp1 { + pinctrl-0 = <&dp1_hot_plug_det>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&mdss0_dp1_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp1_connector_in>; +}; + +&mdss0_dp1_phy { + vdda-phy-supply = <&vreg_l1c>; + vdda-pll-supply = <&vreg_l4a>; + + status = "okay"; +}; + +&pcie0 { + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l1c>; + + status = "okay"; +}; + +&pcie1 { + perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie1_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l1c>; + + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&qupv3_id_2 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sa8775p/adsp.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp0 { + firmware-name = "qcom/sa8775p/cdsp0.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp1 { + firmware-name = "qcom/sa8775p/cdsp1.mbn"; + + status = "okay"; +}; + +&remoteproc_gpdsp0 { + firmware-name = "qcom/sa8775p/gpdsp0.mbn"; + + status = "okay"; +}; + +&remoteproc_gpdsp1 { + firmware-name = "qcom/sa8775p/gpdsp1.mbn"; + + status = "okay"; +}; + +&sdhc { + vmmc-supply = <&vmmc_sdc>; + vqmmc-supply = <&vreg_sdc>; + + pinctrl-0 = <&sdc_default>, <&sd_cd>; + pinctrl-1 = <&sdc_sleep>, <&sd_cd>; + pinctrl-names = "default", "sleep"; + + bus-width = <4>; + cd-gpios = <&tlmm 36 GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + + status = "okay"; +}; + +&serdes0 { + phy-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32768>; +}; + +&tlmm { + ethernet0_default: ethernet0-default-state { + ethernet0_mdc: ethernet0-mdc-pins { + pins = "gpio8"; + function = "emac0_mdc"; + drive-strength = <16>; + bias-pull-up; + }; + + ethernet0_mdio: ethernet0-mdio-pins { + pins = "gpio9"; + function = "emac0_mdio"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + pcie0_default_state: pcie0-default-state { + clkreq-pins { + pins = "gpio1"; + function = "pcie0_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio2"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio0"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_default_state: pcie1-default-state { + clkreq-pins { + pins = "gpio3"; + function = "pcie1_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio4"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio5"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sd_cd: sd-cd-state { + pins = "gpio36"; + function = "gpio"; + bias-pull-up; + }; +}; + +&uart10 { + compatible = "qcom,geni-debug-uart"; + pinctrl-0 = <&qup_uart10_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l8a>; + vcc-max-microamp = <1100000>; + vccq-supply = <&vreg_l4c>; + vccq-max-microamp = <1200000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l4a>; + vdda-pll-supply = <&vreg_l1c>; + + status = "okay"; +}; + +&usb_0 { + dr_mode = "peripheral"; + + status = "okay"; +}; + +&usb_0_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l6c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; + +&usb_0_qmpphy { + vdda-phy-supply = <&vreg_l1c>; + vdda-pll-supply = <&vreg_l7a>; + + status = "okay"; +}; + +&xo_board_clk { + clock-frequency = <38400000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi b/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi index 1369c3d43f86..1369c3d43f86 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi index 63b3031cfcc1..c69aa2f41ce2 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi @@ -3,18 +3,11 @@ * Copyright (c) 2023, Linaro Limited */ -/dts-v1/; - #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> -#include "sa8775p.dtsi" -#include "sa8775p-pmics.dtsi" - / { aliases { - ethernet0 = ðernet0; - ethernet1 = ðernet1; i2c11 = &i2c11; i2c18 = &i2c18; serial0 = &uart10; @@ -443,151 +436,6 @@ }; }; -ðernet0 { - phy-handle = <&sgmii_phy0>; - - pinctrl-0 = <ðernet0_default>; - pinctrl-names = "default"; - - snps,mtl-rx-config = <&mtl_rx_setup>; - snps,mtl-tx-config = <&mtl_tx_setup>; - snps,ps-speed = <1000>; - - status = "okay"; - - mdio: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <4>; - snps,rx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x0>; - snps,route-up; - snps,priority = <0x1>; - }; - - queue1 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x1>; - snps,route-ptp; - }; - - queue2 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x2>; - snps,route-avcp; - }; - - queue3 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x3>; - snps,priority = <0xc>; - }; - }; - - mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <4>; - - queue0 { - snps,dcb-algorithm; - }; - - queue1 { - snps,dcb-algorithm; - }; - - queue2 { - snps,avb-algorithm; - snps,send_slope = <0x1000>; - snps,idle_slope = <0x1000>; - snps,high_credit = <0x3e800>; - snps,low_credit = <0xffc18000>; - }; - - queue3 { - snps,avb-algorithm; - snps,send_slope = <0x1000>; - snps,idle_slope = <0x1000>; - snps,high_credit = <0x3e800>; - snps,low_credit = <0xffc18000>; - }; - }; -}; - -ðernet1 { - phy-handle = <&sgmii_phy1>; - - snps,mtl-rx-config = <&mtl_rx_setup1>; - snps,mtl-tx-config = <&mtl_tx_setup1>; - snps,ps-speed = <1000>; - - status = "okay"; - - mtl_rx_setup1: rx-queues-config { - snps,rx-queues-to-use = <4>; - snps,rx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x0>; - snps,route-up; - snps,priority = <0x1>; - }; - - queue1 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x1>; - snps,route-ptp; - }; - - queue2 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x2>; - snps,route-avcp; - }; - - queue3 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x3>; - snps,priority = <0xc>; - }; - }; - - mtl_tx_setup1: tx-queues-config { - snps,tx-queues-to-use = <4>; - - queue0 { - snps,dcb-algorithm; - }; - - queue1 { - snps,dcb-algorithm; - }; - - queue2 { - snps,avb-algorithm; - snps,send_slope = <0x1000>; - snps,idle_slope = <0x1000>; - snps,high_credit = <0x3e800>; - snps,low_credit = <0xffc18000>; - }; - - queue3 { - snps,avb-algorithm; - snps,send_slope = <0x1000>; - snps,idle_slope = <0x1000>; - snps,high_credit = <0x3e800>; - snps,low_credit = <0xffc18000>; - }; - }; -}; - &i2c11 { clock-frequency = <400000>; status = "okay"; @@ -960,22 +808,6 @@ bias-disable; }; - ethernet0_default: ethernet0-default-state { - ethernet0_mdc: ethernet0-mdc-pins { - pins = "gpio8"; - function = "emac0_mdc"; - drive-strength = <16>; - bias-pull-up; - }; - - ethernet0_mdio: ethernet0-mdio-pins { - pins = "gpio9"; - function = "emac0_mdio"; - drive-strength = <16>; - bias-pull-up; - }; - }; - io_expander_intr_active: io-expander-intr-active-state { pins = "gpio98"; function = "gpio"; @@ -1165,14 +997,11 @@ &usb_0 { pinctrl-names = "default"; pinctrl-0 = <&usb0_en_state>; + dr_mode = "peripheral"; status = "okay"; }; -&usb_0_dwc3 { - dr_mode = "peripheral"; -}; - &usb_0_hsphy { vdda-pll-supply = <&vreg_l7a>; vdda18-supply = <&vreg_l6c>; @@ -1191,14 +1020,11 @@ &usb_1 { pinctrl-names = "default"; pinctrl-0 = <&usb1_en_state>; + dr_mode = "host"; status = "okay"; }; -&usb_1_dwc3 { - dr_mode = "host"; -}; - &usb_1_hsphy { vdda-pll-supply = <&vreg_l7a>; vdda18-supply = <&vreg_l6c>; @@ -1217,14 +1043,11 @@ &usb_2 { pinctrl-names = "default"; pinctrl-0 = <&usb2_en_state>; + dr_mode = "host"; status = "okay"; }; -&usb_2_dwc3 { - dr_mode = "host"; -}; - &usb_2_hsphy { vdda-pll-supply = <&vreg_l7a>; vdda18-supply = <&vreg_l6c>; diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-ethernet-88ea1512.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-ethernet-88ea1512.dtsi new file mode 100644 index 000000000000..9d6bbe1447a4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-ride-ethernet-88ea1512.dtsi @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +/* + * Ethernet card for Lemans based Ride boards. + * It supports 2x 1G - SGMII (Marvell 88EA1512-B2) phy for Main domain + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + aliases { + ethernet0 = ðernet0; + ethernet1 = ðernet1; + }; +}; + +&tlmm { + ethernet0_default: ethernet0-default-state { + ethernet0_mdc: ethernet0-mdc-pins { + pins = "gpio8"; + function = "emac0_mdc"; + drive-strength = <16>; + bias-pull-up; + }; + + ethernet0_mdio: ethernet0-mdio-pins { + pins = "gpio9"; + function = "emac0_mdio"; + drive-strength = <16>; + bias-pull-up; + }; + }; +}; + +ðernet0 { + phy-handle = <&sgmii_phy0>; + phy-mode = "sgmii"; + + pinctrl-0 = <ðernet0_default>; + pinctrl-names = "default"; + + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,ps-speed = <1000>; + + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + sgmii_phy0: phy@8 { + compatible = "ethernet-phy-id0141.0dd4"; + reg = <0x8>; + device_type = "ethernet-phy"; + interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + + sgmii_phy1: phy@a { + compatible = "ethernet-phy-id0141.0dd4"; + reg = <0xa>; + device_type = "ethernet-phy"; + interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + +ðernet1 { + phy-handle = <&sgmii_phy1>; + phy-mode = "sgmii"; + + snps,mtl-rx-config = <&mtl_rx_setup1>; + snps,mtl-tx-config = <&mtl_tx_setup1>; + snps,ps-speed = <1000>; + + status = "okay"; + + mtl_rx_setup1: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + mtl_tx_setup1: tx-queues-config { + snps,tx-queues-to-use = <4>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-ethernet-aqr115c.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-ethernet-aqr115c.dtsi new file mode 100644 index 000000000000..2d2d9ee5f0d9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-ride-ethernet-aqr115c.dtsi @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +/* + * Ethernet card for Lemans based Ride r3 boards. + * It supports 2x 2.5G - HSGMII (Marvell hsgmii) phy for Main domain + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + aliases { + ethernet0 = ðernet0; + ethernet1 = ðernet1; + }; +}; + +&tlmm { + ethernet0_default: ethernet0-default-state { + ethernet0_mdc: ethernet0-mdc-pins { + pins = "gpio8"; + function = "emac0_mdc"; + drive-strength = <16>; + bias-pull-up; + }; + + ethernet0_mdio: ethernet0-mdio-pins { + pins = "gpio9"; + function = "emac0_mdio"; + drive-strength = <16>; + bias-pull-up; + }; + }; +}; + +ðernet0 { + phy-handle = <&hsgmii_phy0>; + phy-mode = "2500base-x"; + + pinctrl-0 = <ðernet0_default>; + pinctrl-names = "default"; + + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,ps-speed = <1000>; + + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + hsgmii_phy0: phy@8 { + compatible = "ethernet-phy-id31c3.1c33"; + reg = <0x8>; + device_type = "ethernet-phy"; + interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + + hsgmii_phy1: phy@0 { + compatible = "ethernet-phy-id31c3.1c33"; + reg = <0x0>; + device_type = "ethernet-phy"; + interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + +ðernet1 { + phy-handle = <&hsgmii_phy1>; + phy-mode = "2500base-x"; + + snps,mtl-rx-config = <&mtl_rx_setup1>; + snps,mtl-tx-config = <&mtl_tx_setup1>; + snps,ps-speed = <1000>; + + status = "okay"; + + mtl_rx_setup1: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + mtl_tx_setup1: tx-queues-config { + snps,tx-queues-to-use = <4>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index fed34717460f..cf685cb186ed 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -12,13 +12,14 @@ #include <dt-bindings/clock/qcom,sa8775p-gcc.h> #include <dt-bindings/clock/qcom,sa8775p-gpucc.h> #include <dt-bindings/clock/qcom,sa8775p-videocc.h> +#include <dt-bindings/clock/qcom,sa8775p-camcc.h> #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> #include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/firmware/qcom,scm.h> -#include <dt-bindings/power/qcom,rpmhpd.h> #include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/soc/qcom,gpr.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> / { @@ -514,7 +515,6 @@ scm { compatible = "qcom,scm-sa8775p", "qcom,scm"; qcom,dload-mode = <&tcsr 0x13000>; - memory-region = <&tz_ffi_mem>; }; }; @@ -773,6 +773,11 @@ no-map; }; + gunyah_md_mem: gunyah-md@91a80000 { + reg = <0x0 0x91a80000 0x0 0x80000>; + no-map; + }; + aoss_backup_mem: aoss-backup@91b00000 { reg = <0x0 0x91b00000 0x0 0x40000>; no-map; @@ -798,12 +803,6 @@ no-map; }; - tz_ffi_mem: tz-ffi@91c00000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x91c00000 0x0 0x1400000>; - no-map; - }; - lpass_machine_learning_mem: lpass-machine-learning@93b00000 { reg = <0x0 0x93b00000 0x0 0xf00000>; no-map; @@ -815,62 +814,77 @@ }; pil_camera_mem: pil-camera@95200000 { - reg = <0x0 0x95200000 0x0 0x500000>; + reg = <0x0 0x95200000 0x0 0x700000>; no-map; }; - pil_adsp_mem: pil-adsp@95c00000 { - reg = <0x0 0x95c00000 0x0 0x1e00000>; + pil_adsp_mem: pil-adsp@95900000 { + reg = <0x0 0x95900000 0x0 0x1e00000>; no-map; }; - pil_gdsp0_mem: pil-gdsp0@97b00000 { - reg = <0x0 0x97b00000 0x0 0x1e00000>; + q6_adsp_dtb_mem: q6-adsp-dtb@97700000 { + reg = <0x0 0x97700000 0x0 0x80000>; no-map; }; - pil_gdsp1_mem: pil-gdsp1@99900000 { - reg = <0x0 0x99900000 0x0 0x1e00000>; + q6_gdsp0_dtb_mem: q6-gdsp0-dtb@97780000 { + reg = <0x0 0x97780000 0x0 0x80000>; no-map; }; - pil_cdsp0_mem: pil-cdsp0@9b800000 { - reg = <0x0 0x9b800000 0x0 0x1e00000>; + pil_gdsp0_mem: pil-gdsp0@97800000 { + reg = <0x0 0x97800000 0x0 0x1e00000>; no-map; }; - pil_gpu_mem: pil-gpu@9d600000 { - reg = <0x0 0x9d600000 0x0 0x2000>; + pil_gdsp1_mem: pil-gdsp1@99600000 { + reg = <0x0 0x99600000 0x0 0x1e00000>; no-map; }; - pil_cdsp1_mem: pil-cdsp1@9d700000 { - reg = <0x0 0x9d700000 0x0 0x1e00000>; + q6_gdsp1_dtb_mem: q6-gdsp1-dtb@9b400000 { + reg = <0x0 0x9b400000 0x0 0x80000>; no-map; }; - pil_cvp_mem: pil-cvp@9f500000 { - reg = <0x0 0x9f500000 0x0 0x700000>; + q6_cdsp0_dtb_mem: q6-cdsp0-dtb@9b480000 { + reg = <0x0 0x9b480000 0x0 0x80000>; no-map; }; - pil_video_mem: pil-video@9fc00000 { - reg = <0x0 0x9fc00000 0x0 0x700000>; + pil_cdsp0_mem: pil-cdsp0@9b500000 { + reg = <0x0 0x9b500000 0x0 0x1e00000>; no-map; }; - audio_mdf_mem: audio-mdf-region@ae000000 { - reg = <0x0 0xae000000 0x0 0x1000000>; + pil_gpu_mem: pil-gpu@9d300000 { + reg = <0x0 0x9d300000 0x0 0x2000>; no-map; }; - firmware_mem: firmware-region@b0000000 { - reg = <0x0 0xb0000000 0x0 0x800000>; + q6_cdsp1_dtb_mem: q6-cdsp1-dtb@9d380000 { + reg = <0x0 0x9d380000 0x0 0x80000>; no-map; }; - hyptz_reserved_mem: hyptz-reserved@beb00000 { - reg = <0x0 0xbeb00000 0x0 0x11500000>; + pil_cdsp1_mem: pil-cdsp1@9d400000 { + reg = <0x0 0x9d400000 0x0 0x1e00000>; + no-map; + }; + + pil_cvp_mem: pil-cvp@9f200000 { + reg = <0x0 0x9f200000 0x0 0x700000>; + no-map; + }; + + pil_video_mem: pil-video@9f900000 { + reg = <0x0 0x9f900000 0x0 0x1000000>; + no-map; + }; + + firmware_mem: firmware-region@b0000000 { + reg = <0x0 0xb0000000 0x0 0x800000>; no-map; }; @@ -915,7 +929,7 @@ }; trusted_apps_mem: trusted-apps@d1900000 { - reg = <0x0 0xd1900000 0x0 0x3800000>; + reg = <0x0 0xd1900000 0x0 0x1c00000>; no-map; }; @@ -3822,6 +3836,58 @@ }; }; + sdhc: mmc@87c4000 { + compatible = "qcom,sa8775p-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x087c4000 0x0 0x1000>; + + interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", + "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>; + clock-names = "iface", + "core"; + + interconnects = <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_SDC1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "sdhc-ddr", + "cpu-sdhc"; + + iommus = <&apps_smmu 0x0 0x0>; + dma-coherent; + + operating-points-v2 = <&sdhc_opp_table>; + power-domains = <&rpmhpd SA8775P_CX>; + resets = <&gcc GCC_SDCC1_BCR>; + + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + + status = "disabled"; + + sdhc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1800000 400000>; + opp-avg-kBps = <100000 0>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <5400000 1600000>; + opp-avg-kBps = <390000 0>; + }; + }; + }; + usb_0_hsphy: phy@88e4000 { compatible = "qcom,sa8775p-usb-hs-phy", "qcom,usb-snps-hs-5nm-phy"; @@ -3859,12 +3925,9 @@ status = "disabled"; }; - usb_0: usb@a6f8800 { - compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + usb_0: usb@a600000 { + compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; + reg = <0 0x0a600000 0 0xfc100>; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, @@ -3877,12 +3940,14 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event", + interrupt-names = "dwc_usb3", + "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", @@ -3899,18 +3964,13 @@ wakeup-source; - status = "disabled"; + iommus = <&apps_smmu 0x080 0x0>; + phys = <&usb_0_hsphy>, <&usb_0_qmpphy>; + phy-names = "usb2-phy", "usb3-phy"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; - usb_0_dwc3: usb@a600000 { - compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xe000>; - interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; - iommus = <&apps_smmu 0x080 0x0>; - phys = <&usb_0_hsphy>, <&usb_0_qmpphy>; - phy-names = "usb2-phy", "usb3-phy"; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - }; + status = "disabled"; }; usb_1_hsphy: phy@88e6000 { @@ -3950,12 +4010,9 @@ status = "disabled"; }; - usb_1: usb@a8f8800 { - compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; - reg = <0 0x0a8f8800 0 0x400>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + usb_1: usb@a800000 { + compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; + reg = <0 0x0a800000 0 0xfc100>; clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, <&gcc GCC_USB30_SEC_MASTER_CLK>, @@ -3968,12 +4025,14 @@ <&gcc GCC_USB30_SEC_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, <&pdc 8 IRQ_TYPE_EDGE_BOTH>, <&pdc 7 IRQ_TYPE_EDGE_BOTH>, <&pdc 13 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event", + interrupt-names = "dwc_usb3", + "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", @@ -3990,18 +4049,13 @@ wakeup-source; - status = "disabled"; + iommus = <&apps_smmu 0x0a0 0x0>; + phys = <&usb_1_hsphy>, <&usb_1_qmpphy>; + phy-names = "usb2-phy", "usb3-phy"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; - usb_1_dwc3: usb@a800000 { - compatible = "snps,dwc3"; - reg = <0 0x0a800000 0 0xe000>; - interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; - iommus = <&apps_smmu 0x0a0 0x0>; - phys = <&usb_1_hsphy>, <&usb_1_qmpphy>; - phy-names = "usb2-phy", "usb3-phy"; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - }; + status = "disabled"; }; usb_2_hsphy: phy@88e7000 { @@ -4017,12 +4071,9 @@ status = "disabled"; }; - usb_2: usb@a4f8800 { - compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; - reg = <0 0x0a4f8800 0 0x400>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + usb_2: usb@a400000 { + compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; + reg = <0 0x0a400000 0 0xfc100>; clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, <&gcc GCC_USB20_MASTER_CLK>, @@ -4035,11 +4086,13 @@ <&gcc GCC_USB20_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, <&pdc 10 IRQ_TYPE_EDGE_BOTH>, <&pdc 9 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "pwr_event", + interrupt-names = "dwc_usb3", + "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq"; @@ -4055,18 +4108,13 @@ wakeup-source; - status = "disabled"; + iommus = <&apps_smmu 0x020 0x0>; + phys = <&usb_2_hsphy>; + phy-names = "usb2-phy"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; - usb_2_dwc3: usb@a400000 { - compatible = "snps,dwc3"; - reg = <0 0x0a400000 0 0xe000>; - interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>; - iommus = <&apps_smmu 0x020 0x0>; - phys = <&usb_2_hsphy>; - phy-names = "usb2-phy"; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - }; + status = "disabled"; }; tcsr_mutex: hwlock@1f40000 { @@ -4345,6 +4393,346 @@ #power-domain-cells = <1>; }; + cci0: cci@ac13000 { + compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; + reg = <0x0 0x0ac13000 0x0 0x1000>; + + interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cci"; + + pinctrl-0 = <&cci0_0_default &cci0_1_default>; + pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci1: cci@ac14000 { + compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; + reg = <0x0 0x0ac14000 0x0 0x1000>; + + interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cci"; + + pinctrl-0 = <&cci1_0_default &cci1_1_default>; + pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci2: cci@ac15000 { + compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; + reg = <0x0 0x0ac15000 0x0 0x1000>; + + interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_2_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cci"; + + pinctrl-0 = <&cci2_0_default &cci2_1_default>; + pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci2_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci2_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci3: cci@ac16000 { + compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; + reg = <0x0 0x0ac16000 0x0 0x1000>; + + interrupts = <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_3_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cci"; + + pinctrl-0 = <&cci3_0_default &cci3_1_default>; + pinctrl-1 = <&cci3_0_sleep &cci3_1_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci3_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci3_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + camss: isp@ac78000 { + compatible = "qcom,sa8775p-camss"; + + reg = <0x0 0xac78000 0x0 0x1000>, + <0x0 0xac7a000 0x0 0x0f00>, + <0x0 0xac7c000 0x0 0x0f00>, + <0x0 0xac84000 0x0 0x0f00>, + <0x0 0xac88000 0x0 0x0f00>, + <0x0 0xac8c000 0x0 0x0f00>, + <0x0 0xac90000 0x0 0x0f00>, + <0x0 0xac94000 0x0 0x0f00>, + <0x0 0xac9c000 0x0 0x2000>, + <0x0 0xac9e000 0x0 0x2000>, + <0x0 0xaca0000 0x0 0x2000>, + <0x0 0xaca2000 0x0 0x2000>, + <0x0 0xacac000 0x0 0x0400>, + <0x0 0xacad000 0x0 0x0400>, + <0x0 0xacae000 0x0 0x0400>, + <0x0 0xac4d000 0x0 0xd000>, + <0x0 0xac5a000 0x0 0xd000>, + <0x0 0xac85000 0x0 0x0d00>, + <0x0 0xac89000 0x0 0x0d00>, + <0x0 0xac8d000 0x0 0x0d00>, + <0x0 0xac91000 0x0 0x0d00>, + <0x0 0xac95000 0x0 0x0d00>; + reg-names = "csid_wrapper", + "csid0", + "csid1", + "csid_lite0", + "csid_lite1", + "csid_lite2", + "csid_lite3", + "csid_lite4", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "tpg0", + "tpg1", + "tpg2", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1", + "vfe_lite2", + "vfe_lite3", + "vfe_lite4"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_ICP_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + clock-names = "camnoc_axi", + "core_ahb", + "cpas_ahb", + "cpas_fast_ahb_clk", + "cpas_vfe_lite", + "cpas_vfe0", + "cpas_vfe1", + "csid", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy_rx", + "gcc_axi_hf", + "gcc_axi_sf", + "icp_ahb", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "csid0", + "csid1", + "csid_lite0", + "csid_lite1", + "csid_lite2", + "csid_lite3", + "csid_lite4", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "tpg0", + "tpg1", + "tpg2", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1", + "vfe_lite2", + "vfe_lite3", + "vfe_lite4"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ahb", + "hf_0"; + + iommus = <&apps_smmu 0x3400 0x20>; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "top"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + }; + }; + camcc: clock-controller@ade0000 { compatible = "qcom,sa8775p-camcc"; reg = <0x0 0x0ade0000 0x0 0x20000>; @@ -4405,7 +4793,7 @@ <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>, <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "bus", + clock-names = "nrt_bus", "iface", "lut", "core", @@ -4682,7 +5070,11 @@ <0x0 0x0af54200 0x0 0x0c0>, <0x0 0x0af55000 0x0 0x770>, <0x0 0x0af56000 0x0 0x09c>, - <0x0 0x0af57000 0x0 0x09c>; + <0x0 0x0af57000 0x0 0x09c>, + <0x0 0x0af58000 0x0 0x09c>, + <0x0 0x0af59000 0x0 0x09c>, + <0x0 0x0af5a000 0x0 0x23c>, + <0x0 0x0af5b000 0x0 0x23c>; interrupt-parent = <&mdss0>; interrupts = <12>; @@ -4691,15 +5083,28 @@ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel", + "stream_2_pixel", + "stream_3_pixel"; assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; - assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>; + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; + assigned-clock-parents = <&mdss0_dp0_phy 0>, + <&mdss0_dp0_phy 1>, + <&mdss0_dp0_phy 1>, + <&mdss0_dp0_phy 1>, + <&mdss0_dp0_phy 1>; phys = <&mdss0_dp0_phy>; phy-names = "dp"; @@ -4761,7 +5166,11 @@ <0x0 0x0af5c200 0x0 0x0c0>, <0x0 0x0af5d000 0x0 0x770>, <0x0 0x0af5e000 0x0 0x09c>, - <0x0 0x0af5f000 0x0 0x09c>; + <0x0 0x0af5f000 0x0 0x09c>, + <0x0 0x0af60000 0x0 0x09c>, + <0x0 0x0af61000 0x0 0x09c>, + <0x0 0x0af62000 0x0 0x23c>, + <0x0 0x0af63000 0x0 0x23c>; interrupt-parent = <&mdss0>; interrupts = <13>; @@ -4770,15 +5179,20 @@ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>, <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; - assigned-clock-parents = <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>; + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&mdss0_dp1_phy 0>, + <&mdss0_dp1_phy 1>, + <&mdss0_dp1_phy 1>; phys = <&mdss0_dp1_phy>; phy-names = "dp"; @@ -4992,6 +5406,144 @@ gpio-ranges = <&tlmm 0 0 149>; wakeup-parent = <&pdc>; + dp0_hot_plug_det: dp0-hot-plug-det-state { + pins = "gpio101"; + function = "edp0_hot"; + bias-disable; + }; + + dp1_hot_plug_det: dp1-hot-plug-det-state { + pins = "gpio102"; + function = "edp1_hot"; + bias-disable; + }; + + hs0_mi2s_active: hs0-mi2s-active-state { + pins = "gpio114", "gpio115", "gpio116", "gpio117"; + function = "hs0_mi2s"; + drive-strength = <8>; + bias-disable; + }; + + hs2_mi2s_active: hs2-mi2s-active-state { + pins = "gpio122", "gpio123", "gpio124", "gpio125"; + function = "hs2_mi2s"; + drive-strength = <8>; + bias-disable; + }; + + cci0_0_default: cci0-0-default-state { + pins = "gpio60", "gpio61"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + cci0_0_sleep: cci0-0-sleep-state { + pins = "gpio60", "gpio61"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci0_1_default: cci0-1-default-state { + pins = "gpio52", "gpio53"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + cci0_1_sleep: cci0-1-sleep-state { + pins = "gpio52", "gpio53"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci1_0_default: cci1-0-default-state { + pins = "gpio62", "gpio63"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + cci1_0_sleep: cci1-0-sleep-state { + pins = "gpio62", "gpio63"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci1_1_default: cci1-1-default-state { + pins = "gpio54", "gpio55"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + cci1_1_sleep: cci1-1-sleep-state { + pins = "gpio54", "gpio55"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci2_0_default: cci2-0-default-state { + pins = "gpio64", "gpio65"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + cci2_0_sleep: cci2-0-sleep-state { + pins = "gpio64", "gpio65"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci2_1_default: cci2-1-default-state { + pins = "gpio56", "gpio57"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + cci2_1_sleep: cci2-1-sleep-state { + pins = "gpio56", "gpio57"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci3_0_default: cci3-0-default-state { + pins = "gpio66", "gpio67"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + cci3_0_sleep: cci3-0-sleep-state { + pins = "gpio66", "gpio67"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci3_1_default: cci3-1-default-state { + pins = "gpio58", "gpio59"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + cci3_1_sleep: cci3-1-sleep-state { + pins = "gpio58", "gpio59"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + qup_i2c0_default: qup-i2c0-state { pins = "gpio20", "gpio21"; function = "qup0_se0"; @@ -5619,6 +6171,46 @@ function = "qup3_se0"; }; }; + + sdc_default: sdc-default-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdc_sleep: sdc-sleep-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <2>; + bias-bus-hold; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <2>; + bias-bus-hold; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <2>; + bias-bus-hold; + }; + }; }; sram: sram@146d8000 { @@ -5854,6 +6446,7 @@ reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ interrupt-controller; + #address-cells = <0>; #interrupt-cells = <3>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; #redistributor-regions = <1>; @@ -6055,8 +6648,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd RPMHPD_CX>, - <&rpmhpd RPMHPD_MXC>; + power-domains = <&rpmhpd SA8775P_CX>, + <&rpmhpd SA8775P_MXC>; power-domain-names = "cx", "mxc"; interconnects = <&gpdsp_anoc MASTER_DSP0 0 @@ -6080,6 +6673,35 @@ label = "gpdsp0"; qcom,remote-pid = <17>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "gdsp0"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x38a1 0x0>; + dma-coherent; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x38a2 0x0>; + dma-coherent; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x38a3 0x0>; + dma-coherent; + }; + }; }; }; @@ -6098,8 +6720,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd RPMHPD_CX>, - <&rpmhpd RPMHPD_MXC>; + power-domains = <&rpmhpd SA8775P_CX>, + <&rpmhpd SA8775P_MXC>; power-domain-names = "cx", "mxc"; interconnects = <&gpdsp_anoc MASTER_DSP1 0 @@ -6123,6 +6745,35 @@ label = "gpdsp1"; qcom,remote-pid = <18>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "gdsp1"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x38c1 0x0>; + dma-coherent; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x38c2 0x0>; + dma-coherent; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x38c3 0x0>; + dma-coherent; + }; + }; }; }; @@ -6239,9 +6890,9 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd RPMHPD_CX>, - <&rpmhpd RPMHPD_MXC>, - <&rpmhpd RPMHPD_NSP0>; + power-domains = <&rpmhpd SA8775P_CX>, + <&rpmhpd SA8775P_MXC>, + <&rpmhpd SA8775P_NSP0>; power-domain-names = "cx", "mxc", "nsp"; interconnects = <&nspa_noc MASTER_CDSP_PROC 0 @@ -6371,9 +7022,9 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd RPMHPD_CX>, - <&rpmhpd RPMHPD_MXC>, - <&rpmhpd RPMHPD_NSP1>; + power-domains = <&rpmhpd SA8775P_CX>, + <&rpmhpd SA8775P_MXC>, + <&rpmhpd SA8775P_NSP1>; power-domain-names = "cx", "mxc", "nsp"; interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 @@ -6527,8 +7178,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd RPMHPD_LCX>, - <&rpmhpd RPMHPD_LMX>; + power-domains = <&rpmhpd SA8775P_LCX>, + <&rpmhpd SA8775P_LMX>; power-domain-names = "lcx", "lmx"; interconnects = <&lpass_ag_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; @@ -6584,6 +7235,45 @@ dma-coherent; }; }; + + gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,domain = <GPR_DOMAIN_ID_ADSP>; + qcom,intents = <512 20>; + #address-cells = <1>; + #size-cells = <0>; + + q6apm: service@1 { + compatible = "qcom,q6apm"; + reg = <GPR_APM_MODULE_IID>; + #sound-dai-cells = <0>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6apmbedai: bedais { + compatible = "qcom,q6apm-lpass-dais"; + #sound-dai-cells = <1>; + }; + + q6apmdai: dais { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x3001 0x0>; + }; + }; + + q6prm: service@2 { + compatible = "qcom,q6prm"; + reg = <GPR_PRM_MODULE_IID>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + #clock-cells = <2>; + }; + }; + }; }; }; }; @@ -7635,13 +8325,19 @@ iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, <0x100 &pcie_smmu 0x0001 0x1>; - resets = <&gcc GCC_PCIE_0_BCR>; - reset-names = "pci"; + resets = <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + power-domains = <&gcc PCIE_0_GDSC>; phys = <&pcie0_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55>; + status = "disabled"; pcieport0: pcie@0 { @@ -7696,7 +8392,6 @@ power-domains = <&gcc PCIE_0_GDSC>; phys = <&pcie0_phy>; phy-names = "pciephy"; - max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ num-lanes = <2>; linux,pci-domain = <0>; @@ -7707,16 +8402,18 @@ compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; reg = <0x0 0x1c04000 0x0 0x2000>; - clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_CLKREF_EN>, <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK>, - <&gcc GCC_PCIE_0_PIPEDIV2_CLK>, - <&gcc GCC_PCIE_0_PHY_AUX_CLK>; - - clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", - "pipediv2", "phy_aux"; + <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; @@ -7801,13 +8498,19 @@ iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, <0x100 &pcie_smmu 0x0081 0x1>; - resets = <&gcc GCC_PCIE_1_BCR>; - reset-names = "pci"; + resets = <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + power-domains = <&gcc PCIE_1_GDSC>; phys = <&pcie1_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; + status = "disabled"; pcie@0 { @@ -7862,7 +8565,6 @@ power-domains = <&gcc PCIE_1_GDSC>; phys = <&pcie1_phy>; phy-names = "pciephy"; - max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ num-lanes = <4>; linux,pci-domain = <1>; @@ -7873,16 +8575,18 @@ compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; reg = <0x0 0x1c14000 0x0 0x4000>; - clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_CLKREF_EN>, <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK>, - <&gcc GCC_PCIE_1_PIPEDIV2_CLK>, - <&gcc GCC_PCIE_1_PHY_AUX_CLK>; - - clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", - "pipediv2", "phy_aux"; + <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts new file mode 100644 index 000000000000..e72cf6725a52 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts @@ -0,0 +1,507 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/sound/qcom,q6afe.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> + +#include "qcs8300.dtsi" +#include "qcs8300-pmics.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco EVK"; + compatible = "qcom,monaco-evk", "qcom,qcs8300"; + + aliases { + ethernet0 = ðernet0; + i2c1 = &i2c1; + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + dmic: audio-codec-0 { + compatible = "dmic-codec"; + #sound-dai-cells = <0>; + num-channels = <1>; + }; + + max98357a: audio-codec-1 { + compatible = "maxim,max98357a"; + #sound-dai-cells = <0>; + }; + + sound { + compatible = "qcom,qcs8275-sndcard"; + model = "MONACO-EVK"; + + pinctrl-0 = <&hs0_mi2s_active>, <&mi2s1_active>; + pinctrl-names = "default"; + + hs0-mi2s-playback-dai-link { + link-name = "HS0 MI2S Playback"; + + codec { + sound-dai = <&max98357a>; + }; + + cpu { + sound-dai = <&q6apmbedai PRIMARY_MI2S_RX>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + sec-mi2s-capture-dai-link { + link-name = "Secondary MI2S Capture"; + + codec { + sound-dai = <&dmic>; + }; + + cpu { + sound-dai = <&q6apmbedai SECONDARY_MI2S_TX>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_l3a: ldo3 { + regulator-name = "vreg_l3a"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4a: ldo4 { + regulator-name = "vreg_l4a"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5a: ldo5 { + regulator-name = "vreg_l5a"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6a: ldo6 { + regulator-name = "vreg_l6a"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7a: ldo7 { + regulator-name = "vreg_l7a"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8a: ldo8 { + regulator-name = "vreg_l8a"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9a: ldo9 { + regulator-name = "vreg_l9a"; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-1 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_s5c: smps5 { + regulator-name = "vreg_s5c"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1c: ldo1 { + regulator-name = "vreg_l1c"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <512000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2c: ldo2 { + regulator-name = "vreg_l2c"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4c: ldo4 { + regulator-name = "vreg_l4c"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7c: ldo7 { + regulator-name = "vreg_l7c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8c: ldo8 { + regulator-name = "vreg_l8c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9c: ldo9 { + regulator-name = "vreg_l9c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +ðernet0 { + phy-mode = "2500base-x"; + phy-handle = <&hsgmii_phy0>; + + pinctrl-0 = <ðernet0_default>; + pinctrl-names = "default"; + + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + nvmem-cells = <&mac_addr0>; + nvmem-cell-names = "mac-address"; + + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + hsgmii_phy0: ethernet-phy@1c { + compatible = "ethernet-phy-id004d.d101"; + reg = <0x1c>; + reset-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcs8300/a623_zap.mbn"; +}; + +&i2c1 { + pinctrl-0 = <&qup_i2c1_default>; + pinctrl-names = "default"; + + status = "okay"; + + eeprom0: eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + pagesize = <64>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + mac_addr0: mac-addr@0 { + reg = <0x0 0x6>; + }; + }; + }; +}; + +&i2c15 { + pinctrl-0 = <&qup_i2c15_default>; + pinctrl-names = "default"; + + status = "okay"; + + expander0: gpio@38 { + compatible = "ti,tca9538"; + reg = <0x38>; + #gpio-cells = <2>; + gpio-controller; + }; + + expander1: gpio@39 { + compatible = "ti,tca9538"; + reg = <0x39>; + #gpio-cells = <2>; + gpio-controller; + }; + + expander2: gpio@3a { + compatible = "ti,tca9538"; + reg = <0x3a>; + #gpio-cells = <2>; + gpio-controller; + }; + + expander3: gpio@3b { + compatible = "ti,tca9538"; + reg = <0x3b>; + #gpio-cells = <2>; + gpio-controller; + }; + + expander4: gpio@3c { + compatible = "ti,tca9538"; + reg = <0x3c>; + #gpio-cells = <2>; + gpio-controller; + }; + + expander5: gpio@3d { + compatible = "ti,tca9538"; + reg = <0x3d>; + #gpio-cells = <2>; + gpio-controller; + }; + + expander6: gpio@3e { + compatible = "ti,tca9538"; + reg = <0x3e>; + #gpio-cells = <2>; + gpio-controller; + }; +}; + +&iris { + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/qcs8300/adsp.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcs8300/cdsp0.mbn"; + + status = "okay"; +}; + +&remoteproc_gpdsp { + firmware-name = "qcom/qcs8300/gpdsp0.mbn"; + + status = "okay"; +}; + +&serdes0 { + phy-supply = <&vreg_l4a>; + + status = "okay"; +}; + +&tlmm { + ethernet0_default: ethernet0-default-state { + ethernet0_mdc: ethernet0-mdc-pins { + pins = "gpio5"; + function = "emac0_mdc"; + drive-strength = <16>; + bias-pull-up; + }; + + ethernet0_mdio: ethernet0-mdio-pins { + pins = "gpio6"; + function = "emac0_mdio"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qup_i2c1_default: qup-i2c1-state { + pins = "gpio19", "gpio20"; + function = "qup0_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c15_default: qup-i2c15-state { + pins = "gpio91", "gpio92"; + function = "qup1_se7"; + drive-strength = <2>; + bias-pull-up; + }; +}; + +&uart7 { + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l8a>; + vcc-max-microamp = <1100000>; + vccq-supply = <&vreg_l4c>; + vccq-max-microamp = <1200000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l4a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&usb_1 { + dr_mode = "peripheral"; + + status = "okay"; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l7c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; + +&usb_qmpphy { + vdda-phy-supply = <&vreg_l7a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index de9fdc0dfc5f..d3a25a837488 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1562,6 +1562,8 @@ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + resets = <&gcc GCC_MDSS_BCR>; + interrupt-controller; #interrupt-cells = <1>; @@ -1834,14 +1836,6 @@ iommus = <&apps_iommu 5>; memory-region = <&venus_mem>; status = "disabled"; - - video-decoder { - compatible = "venus-decoder"; - }; - - video-encoder { - compatible = "venus-encoder"; - }; }; apps_iommu: iommu@1ef0000 { @@ -2133,6 +2127,7 @@ <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; clock-names = "iface", "core", "xo"; + resets = <&gcc GCC_SDCC1_BCR>; pinctrl-0 = <&sdc1_default>; pinctrl-1 = <&sdc1_sleep>; pinctrl-names = "default", "sleep"; @@ -2154,6 +2149,7 @@ <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; clock-names = "iface", "core", "xo"; + resets = <&gcc GCC_SDCC2_BCR>; pinctrl-0 = <&sdc2_default>; pinctrl-1 = <&sdc2_sleep>; pinctrl-names = "default", "sleep"; diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index 68b92fdb996c..eb64ec35e7f0 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -1249,6 +1249,8 @@ power-domains = <&gcc MDSS_GDSC>; + resets = <&gcc GCC_MDSS_BCR>; + #address-cells = <1>; #size-cells = <1>; #interrupt-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts b/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts new file mode 100644 index 000000000000..ef4faf763132 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts @@ -0,0 +1,255 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Cristian Cozzolino + */ +/dts-v1/; + +#include "msm8953.dtsi" +#include "pm8953.dtsi" +#include "pmi8950.dtsi" + +/delete-node/ &cont_splash_mem; +/delete-node/ &qseecom_mem; + +/ { + model = "Billion Capture+"; + compatible = "flipkart,rimob", "qcom,msm8953"; + chassis-type = "handset"; + qcom,msm-id = <293 0>; + qcom,board-id = <0x340008 0>; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer@90001000 { + compatible = "simple-framebuffer"; + reg = <0 0x90001000 0 (1920 * 1080 * 3)>; + + width = <1080>; + height = <1920>; + stride = <(1080 * 3)>; + format = "r8g8b8"; + + power-domains = <&gcc MDSS_GDSC>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_key_default>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <15>; + }; + }; + + reserved-memory { + qseecom_mem: qseecom@84a00000 { + reg = <0x0 0x84a00000 0x0 0x1900000>; + no-map; + }; + + cont_splash_mem: cont-splash@90001000 { + reg = <0x0 0x90001000 0x0 (1080 * 1920 * 3)>; + no-map; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-always-on; + regulator-boot-on; + }; +}; + + +&hsusb_phy { + vdd-supply = <&pm8953_l3>; + vdda-pll-supply = <&pm8953_l7>; + vdda-phy-dpdm-supply = <&pm8953_l13>; + + status = "okay"; +}; + +&pm8953_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8953-regulators"; + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + vdd_s7-supply = <&vph_pwr>; + vdd_l1-supply = <&pm8953_s3>; + vdd_l2_l3-supply = <&pm8953_s3>; + vdd_l4_l5_l6_l7_l16_l19-supply = <&pm8953_s4>; + vdd_l8_l11_l12_l13_l14_l15-supply = <&vph_pwr>; + vdd_l9_l10_l17_l18_l22-supply = <&vph_pwr>; + vdd_l23-supply = <&pm8953_s3>; + + pm8953_s1: s1 { + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <1156000>; + }; + + pm8953_s3: s3 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1224000>; + }; + + pm8953_s4: s4 { + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <2050000>; + }; + + pm8953_l1: l1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + pm8953_l2: l2 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1225000>; + }; + + pm8953_l3: l3 { + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + }; + + pm8953_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-set-load; + }; + + pm8953_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + }; + + pm8953_l8: l8 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-allow-set-load; + }; + + pm8953_l9: l9 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pm8953_l10: l10 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l11: l11 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + }; + + pm8953_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + }; + + pm8953_l13: l13 { + regulator-min-microvolt = <3125000>; + regulator-max-microvolt = <3125000>; + }; + + pm8953_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l19: l19 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + }; + + pm8953_l22: l22 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + pm8953_l23: l23 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1225000>; + }; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8953_l8>; + vqmmc-supply = <&pm8953_l5>; + + status = "okay"; +}; + +&sdhc_2 { + vmmc-supply = <&pm8953_l11>; + vqmmc-supply = <&pm8953_l12>; + + cd-gpios = <&tlmm 133 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <135 4>; + + gpio_key_default: gpio-key-default-state { + pins = "gpio85"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts index 336b916729e4..ddd7af616794 100644 --- a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts +++ b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts @@ -296,7 +296,7 @@ vmmc-supply = <&pm8953_l11>; vqmmc-supply = <&pm8953_l12>; - cd-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + cd-gpios = <&tlmm 133 GPIO_ACTIVE_HIGH>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 273e79fb7569..76317c578349 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -775,45 +775,131 @@ }; spi_3_default: spi-3-default-state { - pins = "gpio10", "gpio11"; - function = "blsp_spi3"; - drive-strength = <2>; - bias-disable; + cs-pins { + pins = "gpio10"; + function = "blsp_spi3"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio8", "gpio9", "gpio11"; + function = "blsp_spi3"; + drive-strength = <12>; + bias-disable; + }; }; spi_3_sleep: spi-3-sleep-state { - pins = "gpio10", "gpio11"; - function = "gpio"; - drive-strength = <2>; - bias-disable; + cs-pins { + pins = "gpio10"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio8", "gpio9", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; }; spi_5_default: spi-5-default-state { - pins = "gpio18", "gpio19"; - function = "blsp_spi5"; - drive-strength = <2>; - bias-disable; + cs-pins { + pins = "gpio18"; + function = "blsp_spi5"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio16", "gpio17", "gpio19"; + function = "blsp_spi5"; + drive-strength = <12>; + bias-disable; + }; }; spi_5_sleep: spi-5-sleep-state { - pins = "gpio18", "gpio19"; - function = "gpio"; - drive-strength = <2>; - bias-disable; + cs-pins { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio16", "gpio17", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; }; spi_6_default: spi-6-default-state { - pins = "gpio22", "gpio23"; - function = "blsp_spi6"; - drive-strength = <2>; - bias-disable; + cs-pins { + pins = "gpio22"; + function = "blsp_spi6"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio20", "gpio21", "gpio23"; + function = "blsp_spi6"; + drive-strength = <12>; + bias-disable; + }; }; spi_6_sleep: spi-6-sleep-state { - pins = "gpio22", "gpio23"; - function = "gpio"; - drive-strength = <2>; - bias-disable; + cs-pins { + pins = "gpio22"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio20", "gpio21", "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + spi_7_default: spi-7-default-state { + cs-pins { + pins = "gpio136"; + function = "blsp_spi7"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio135", "gpio137", "gpio138"; + function = "blsp_spi7"; + drive-strength = <12>; + bias-disable; + }; + }; + + spi_7_sleep: spi-7-sleep-state { + cs-pins { + pins = "gpio136"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio135", "gpio137", "gpio138"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; }; uart_5_default: uart-5-default-state { @@ -1147,7 +1233,7 @@ status = "disabled"; - zap-shader { + gpu_zap_shader: zap-shader { memory-region = <&zap_shader_region>; }; @@ -1660,7 +1746,7 @@ reg = <0x078b7000 0x600>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; clock-names = "core", "iface"; - clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; dma-names = "tx", "rx"; @@ -1751,7 +1837,7 @@ reg = <0x07af5000 0x600>; interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; clock-names = "core", "iface"; - clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, + clocks = <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; dma-names = "tx", "rx"; @@ -1791,7 +1877,7 @@ reg = <0x07af6000 0x600>; interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; clock-names = "core", "iface"; - clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, + clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; dma-names = "tx", "rx"; @@ -1826,6 +1912,26 @@ status = "disabled"; }; + spi_7: spi@7af7000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x07af7000 0x600>; + interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "core", "iface"; + clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; + dma-names = "tx", "rx"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi_7_default>; + pinctrl-1 = <&spi_7_sleep>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + i2c_8: i2c@7af8000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x07af8000 0x600>; diff --git a/arch/arm64/boot/dts/qcom/msm8976-longcheer-l9360.dts b/arch/arm64/boot/dts/qcom/msm8976-longcheer-l9360.dts index e524d58cf0a4..18832a3b9a1c 100644 --- a/arch/arm64/boot/dts/qcom/msm8976-longcheer-l9360.dts +++ b/arch/arm64/boot/dts/qcom/msm8976-longcheer-l9360.dts @@ -190,6 +190,12 @@ reg = <0x12>; syna,sensor-type = <1>; }; + + rmi4-f1a@1a { + reg = <0x1a>; + /* Keys listed from right to left */ + linux,keycodes = <KEY_APPSELECT KEY_HOMEPAGE KEY_BACK>; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index f91605de4909..c75b522f6eba 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1928,10 +1928,10 @@ "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ pinctrl-names = "default", "sleep"; pinctrl-0 = <&pcie0_state_on>; @@ -2005,10 +2005,10 @@ "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ pinctrl-names = "default", "sleep"; pinctrl-0 = <&pcie1_state_on>; @@ -2080,10 +2080,10 @@ "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ pinctrl-names = "default", "sleep"; pinctrl-0 = <&pcie2_state_on>; @@ -3766,6 +3766,7 @@ intc: interrupt-controller@9bc0000 { compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; #redistributor-regions = <1>; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 0b0a9379cb05..5c75fba16ce2 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -3082,9 +3082,9 @@ mdss_hdmi: hdmi-tx@c9a0000 { compatible = "qcom,hdmi-tx-8998"; - reg = <0x0c9a0000 0x50c>, - <0x00780000 0x6220>, - <0x0c9e0000 0x2c>; + reg = <0x0c9a0000 0x50c>, + <0x00780000 0x6220>, + <0x0c9e0000 0x2c>; reg-names = "core_physical", "qfprom_physical", "hdcp_physical"; diff --git a/arch/arm64/boot/dts/qcom/pmk8550.dtsi b/arch/arm64/boot/dts/qcom/pmk8550.dtsi index c7ac9b2eaacf..583f61fc16ad 100644 --- a/arch/arm64/boot/dts/qcom/pmk8550.dtsi +++ b/arch/arm64/boot/dts/qcom/pmk8550.dtsi @@ -64,7 +64,7 @@ }; }; - pmk8550_gpios: gpio@8800 { + pmk8550_gpios: gpio@b800 { compatible = "qcom,pmk8550-gpio", "qcom,spmi-gpio"; reg = <0xb800>; gpio-controller; diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index fa24b77a31a7..08141b41de24 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -154,6 +154,7 @@ compatible = "qcom,scm-qcm2290", "qcom,scm"; clocks = <&rpmcc RPM_SMD_CE1_CLK>; clock-names = "core"; + qcom,dload-mode = <&tcsr_regs 0x13000>; #reset-cells = <1>; interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; @@ -565,6 +566,20 @@ bias-disable; }; + cci0_default: cci0-default-state { + pins = "gpio22", "gpio23"; + function = "cci_i2c"; + drive-strength = <2>; + bias-disable; + }; + + cci1_default: cci1-default-state { + pins = "gpio29", "gpio30"; + function = "cci_i2c"; + drive-strength = <2>; + bias-disable; + }; + sdc1_state_on: sdc1-on-state { clk-pins { pins = "sdc1_clk"; @@ -953,6 +968,11 @@ qcom,ddr-config = <0x80040868>; bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "disabled"; sdhc1_opp_table: opp-table { @@ -1454,6 +1474,7 @@ snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; snps,usb3_lpm_capable; + snps,parkmode-disable-ss-quirk; maximum-speed = "super-speed"; dr_mode = "otg"; usb-role-switch; @@ -1628,6 +1649,42 @@ #iommu-cells = <2>; }; + cci: cci@5c1b000 { + compatible = "qcom,qcm2290-cci", "qcom,msm8996-cci"; + reg = <0x0 0x5c1b000 0x0 0x1000>; + + interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>; + + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, <&gcc GCC_CAMSS_CCI_0_CLK>; + clock-names = "ahb", "cci"; + assigned-clocks = <&gcc GCC_CAMSS_CCI_0_CLK>; + assigned-clock-rates = <37500000>; + + power-domains = <&gcc GCC_CAMSS_TOP_GDSC>; + + pinctrl-0 = <&cci0_default &cci1_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + camss: camss@5c6e000 { compatible = "qcom,qcm2290-camss"; @@ -2096,6 +2153,61 @@ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; }; + venus: video-codec@5a00000 { + compatible = "qcom,qcm2290-venus"; + reg = <0 0x5a00000 0 0xf0000>; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + + power-domains = <&gcc GCC_VENUS_GDSC>, + <&gcc GCC_VCODEC0_GDSC>, + <&rpmpd QCM2290_VDDCX>; + power-domain-names = "venus", + "vcodec0", + "cx"; + operating-points-v2 = <&venus_opp_table>; + + clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>, + <&gcc GCC_VIDEO_AHB_CLK>, + <&gcc GCC_VENUS_CTL_AXI_CLK>, + <&gcc GCC_VIDEO_THROTTLE_CORE_CLK>, + <&gcc GCC_VIDEO_VCODEC0_SYS_CLK>, + <&gcc GCC_VCODEC0_AXI_CLK>; + clock-names = "core", + "iface", + "bus", + "throttle", + "vcodec0_core", + "vcodec0_bus"; + + memory-region = <&pil_video_mem>; + iommus = <&apps_smmu 0x860 0x0>, + <&apps_smmu 0x880 0x0>, + <&apps_smmu 0x861 0x04>, + <&apps_smmu 0x863 0x0>, + <&apps_smmu 0x804 0xe0>; + + interconnects = <&mmnrt_virt MASTER_VIDEO_P0 RPM_ALWAYS_TAG + &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, + <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG + &config_noc SLAVE_VENUS_CFG RPM_ACTIVE_TAG>; + interconnect-names = "video-mem", + "cpu-cfg"; + + venus_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-133333333 { + opp-hz = /bits/ 64 <133333333>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmpd_opp_svs>; + }; + }; + }; + wifi: wifi@c800000 { compatible = "qcom,wcn3990-wifi"; reg = <0x0 0x0c800000 0x0 0x800000>; diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index e115b6a52b29..519e458e1a89 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -1176,6 +1176,22 @@ sound-dai = <&q6routing>; }; }; + + usb-dai-link { + link-name = "USB Playback"; + + codec { + sound-dai = <&q6usbdai USB_RX>; + }; + + cpu { + sound-dai = <&q6afedai USB_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + }; }; &spi13 { @@ -1364,12 +1380,10 @@ }; &usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { dr_mode = "otg"; usb-role-switch; + + status = "okay"; }; &usb_1_dwc3_hs { diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts index 7a155ef6492e..73fce639370c 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -18,6 +18,7 @@ #include "pm7325.dtsi" #include "pm8350c.dtsi" #include "pmk8350.dtsi" +#include "qcs6490-audioreach.dtsi" /delete-node/ &ipa_fw_mem; /delete-node/ &rmtfs_mem; @@ -169,6 +170,30 @@ regulator-min-microvolt = <3700000>; regulator-max-microvolt = <3700000>; }; + + wcd9370: audio-codec-0 { + compatible = "qcom,wcd9370-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + reset-gpios = <&tlmm 83 GPIO_ACTIVE_HIGH>; + + vdd-buck-supply = <&vreg_l17b_1p7>; + vdd-rxtx-supply = <&vreg_l18b_1p8>; + vdd-px-supply = <&vreg_l18b_1p8>; + vdd-mic-bias-supply = <&vreg_bob_3p296>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + + qcom,rx-device = <&wcd937x_rx>; + qcom,tx-device = <&wcd937x_tx>; + + #sound-dai-cells = <1>; + }; }; &apps_rsc { @@ -536,6 +561,22 @@ firmware-name = "qcom/qcm6490/a660_zap.mbn"; }; +&lpass_rx_macro { + status = "okay"; +}; + +&lpass_tx_macro { + status = "okay"; +}; + +&lpass_va_macro { + status = "okay"; +}; + +&lpass_wsa_macro { + status = "okay"; +}; + &mdss { status = "okay"; }; @@ -716,6 +757,165 @@ cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; }; +&sound { + compatible = "qcom,qcm6490-idp-sndcard"; + model = "QCM6490-IDP"; + + audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "TX DMIC0", "MIC BIAS1", + "TX DMIC1", "MIC BIAS2", + "TX DMIC2", "MIC BIAS3", + "TX SWR_ADC1", "ADC2_OUTPUT", + "VA DMIC0", "VA MIC BIAS3", + "VA DMIC1", "VA MIC BIAS3", + "VA DMIC2", "VA MIC BIAS1", + "VA DMIC3", "VA MIC BIAS1"; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, + <&swr2 0>, <&lpass_wsa_macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + codec { + sound-dai = <&wcd9370 0>, <&swr0 0>, <&lpass_rx_macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + codec { + sound-dai = <&wcd9370 1>, <&swr1 0>, <&lpass_tx_macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_va_macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; +}; + +&swr0 { + status = "okay"; + + wcd937x_rx: codec@0,4 { + compatible = "sdw20217010a00"; + reg = <0 4>; + + /* + * WCD9370 RX Port 1 (HPH_L/R) <==> SWR1 Port 1 (HPH_L/R) + * WCD9370 RX Port 2 (CLSH) <==> SWR1 Port 2 (CLSH) + * WCD9370 RX Port 3 (COMP_L/R) <==> SWR1 Port 3 (COMP_L/R) + * WCD9370 RX Port 4 (LO) <==> SWR1 Port 4 (LO) + * WCD9370 RX Port 5 (DSD_L/R) <==> SWR1 Port 5 (DSD) + */ + qcom,rx-port-mapping = <1 2 3 4 5>; + + /* + * Static channels mapping between slave and master rx port channels. + * In the order of slave port channels, which is + * hph_l, hph_r, clsh, comp_l, comp_r, lo, dsd_r, dsd_l. + */ + qcom,rx-channel-mapping = /bits/ 8 <1 2 1 1 2 1 1 2>; + }; +}; + +&swr1 { + status = "okay"; + + wcd937x_tx: codec@0,3 { + compatible = "sdw20217010a00"; + reg = <0 3>; + + /* + * WCD9370 TX Port 1 (ADC1) <=> SWR2 Port 2 + * WCD9370 TX Port 2 (ADC2, 3) <=> SWR2 Port 2 + * WCD9370 TX Port 3 (DMIC0,1,2,3 & MBHC) <=> SWR2 Port 3 + * WCD9370 TX Port 4 (DMIC4,5,6,7) <=> SWR2 Port 4 + */ + qcom,tx-port-mapping = <1 1 2 3>; + + /* + * Static channel mapping between slave and master tx port channels. + * In the order of slave port channels which is adc1, adc2, adc3, + * mic0, dmic1, mbhc, dmic2, dmic3, dmci4, dmic5, dmic6, dmic7. + */ + qcom,tx-channel-mapping = /bits/ 8 <1 2 1 1 2 3 3 4 1 2 3 4>; + }; +}; + +&swr2 { + status = "okay"; + + left_spkr: speaker@0,1 { + compatible = "sdw10217020200"; + reg = <0 1>; + powerdown-gpios = <&tlmm 63 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + #thermal-sensor-cells = <0>; + vdd-supply = <&vreg_l18b_1p8>; + qcom,port-mapping = <1 2 3 7>; + }; + + right_spkr: speaker@0,2 { + compatible = "sdw10217020200"; + reg = <0 2>; + powerdown-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + #thermal-sensor-cells = <0>; + vdd-supply = <&vreg_l18b_1p8>; + qcom,port-mapping = <4 5 6 8>; + }; +}; + &tlmm { gpio-reserved-ranges = <32 2>, /* ADSP */ <48 4>; /* NFC */ @@ -725,6 +925,13 @@ function = "gpio"; bias-pull-up; }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio83"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; }; &uart5 { @@ -751,12 +958,9 @@ }; &usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { - /delete-property/ usb-role-switch; dr_mode = "peripheral"; + + status = "okay"; }; &usb_1_hsphy { diff --git a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts new file mode 100644 index 000000000000..251e72f11428 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts @@ -0,0 +1,864 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2023, Luca Weiss <luca.weiss@fairphone.com> + */ + +/dts-v1/; + +#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h> +#include <dt-bindings/iio/qcom,spmi-adc7-pm7325.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include "sc7280.dtsi" +#include "pm8350c.dtsi" +#include "pmk8350.dtsi" + +/delete-node/ &ipa_fw_mem; +/delete-node/ &rmtfs_mem; +/delete-node/ &xbl_mem; +/delete-node/ &adsp_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &wpss_mem; + +/ { + model = "Particle Tachyon"; + compatible = "particle,tachyon", "qcom,qcm6490"; + chassis-type = "embedded"; + + aliases { + serial0 = &uart5; + serial1 = &uart12; + serial2 = &uart7; + serial3 = &uart8; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&activity_led_state>; + pinctrl-names = "default"; + + led-activity { + function = LED_FUNCTION_ACTIVITY; + color = <LED_COLOR_ID_RED>; + gpios = <&tlmm 14 GPIO_ACTIVE_HIGH>; + default-state = "on"; + panic-indicator; + }; + }; + + pmic-glink { + compatible = "qcom,qcm6490-pmic-glink", "qcom,pmic-glink"; + + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 140 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu_in: endpoint { + remote-endpoint = <&usbdp_sbu_mux>; + }; + }; + }; + }; + }; + + vreg_power_5v: regulator-power-5v { + compatible = "regulator-fixed"; + regulator-name = "power_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&tlmm 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + reserved-memory { + xbl_mem: xbl@80700000 { + reg = <0x0 0x80700000 0x0 0x100000>; + no-map; + }; + + tz_stat_mem: tz-stat@c0000000 { + reg = <0x0 0xc0000000 0x0 0x100000>; + no-map; + }; + + tags_mem: tags@c0100000 { + reg = <0x0 0xc0100000 0x0 0x1200000>; + no-map; + }; + + qtee_mem: qtee@c1300000 { + reg = <0x0 0xc1300000 0x0 0x500000>; + no-map; + }; + + trusted_apps_mem: trusted-apps@c1800000 { + reg = <0x0 0xc1800000 0x0 0x1c00000>; + no-map; + }; + + debug_vm_mem: debug-vm@d0600000 { + reg = <0x0 0xd0600000 0x0 0x100000>; + no-map; + }; + + adsp_mem: adsp@86100000 { + reg = <0x0 0x86700000 0x0 0x2800000>; + no-map; + }; + + cdsp_mem: cdsp@88900000 { + reg = <0x0 0x88f00000 0x0 0x1e00000>; + no-map; + }; + + wpss_mem: wpss@9ae00000 { + reg = <0x0 0x9ae00000 0x0 0x1900000>; + no-map; + }; + + mpss_mem: mpss@8b800000 { + reg = <0x0 0x8b800000 0x0 0xf600000>; + no-map; + }; + + ipa_fw_mem: ipa-fw@8b300000 { + reg = <0x0 0x8b700000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi@8b310000 { + reg = <0x0 0x8b710000 0x0 0xa000>; + no-map; + }; + + rmtfs_mem: memory@f8500000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0xf8500000 0x0 0x600000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>, <QCOM_SCM_VMID_NAV>; + }; + }; + + + usbdp-sbu-mux { + compatible = "pericom,pi3usb102", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 108 GPIO_ACTIVE_HIGH>; + select-gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usbdp_sbu_default>; + pinctrl-names = "default"; + + mode-switch; + orientation-switch; + + port { + usbdp_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu_in>; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm7325-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p972>; + vdd-l2-l7-supply = <&vreg_bob_3p296>; + vdd-l6-l9-l10-supply = <&vreg_s8b_1p272>; + vdd-l8-supply = <&vreg_s7b_0p972>; + vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p872>; + vdd-l13-supply = <&vreg_s7b_0p972>; + vdd-l14-l16-supply = <&vreg_s8b_1p272>; + + vreg_s1b_1p872: smps1 { + regulator-name = "vreg_s1b_1p872"; + regulator-min-microvolt = <1840000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7b_0p972: smps7 { + regulator-name = "vreg_s7b_0p972"; + regulator-min-microvolt = <535000>; + regulator-max-microvolt = <1120000>; + }; + + vreg_s8b_1p272: smps8 { + regulator-name = "vreg_s8b_1p272"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_RET>; + }; + + vreg_l1b_0p912: ldo1 { + regulator-name = "vreg_l1b_0p912"; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <925000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2b_3p072: ldo2 { + regulator-name = "vreg_l2b_3p072"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3b_0p504: ldo3 { + regulator-name = "vreg_l3b_0p504"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <910000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6b_1p2: ldo6 { + regulator-name = "vreg_l6b_1p2"; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7b_2p952: ldo7 { + regulator-name = "vreg_l7b_2p952"; + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <2952000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8b_0p904: ldo8 { + regulator-name = "vreg_l8b_0p904"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9b_1p2: ldo9 { + regulator-name = "vreg_l9b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11b_1p504: ldo11 { + regulator-name = "vreg_l11b_1p504"; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l12b_0p751: ldo12 { + regulator-name = "vreg_l12b_0p751"; + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l13b_0p53: ldo13 { + regulator-name = "vreg_l13b_0p53"; + regulator-min-microvolt = <530000>; + regulator-max-microvolt = <824000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l14b_1p08: ldo14 { + regulator-name = "vreg_l14b_1p08"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l15b_0p765: ldo15 { + regulator-name = "vreg_l15b_0p765"; + regulator-min-microvolt = <765000>; + regulator-max-microvolt = <1020000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l16b_1p1: ldo16 { + regulator-name = "vreg_l16b_1p1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l17b_1p7: ldo17 { + regulator-name = "vreg_l17b_1p7"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l18b_1p8: ldo18 { + regulator-name = "vreg_l18b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l19b_1p8: ldo19 { + regulator-name = "vreg_l19b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-1 { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-l1-l12-supply = <&vreg_s1b_1p872>; + vdd-l2-l8-supply = <&vreg_s1b_1p872>; + vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob_3p296>; + vdd-l6-l9-l11-supply = <&vreg_bob_3p296>; + vdd-l10-supply = <&vreg_s7b_0p972>; + vdd-bob-supply = <&vph_pwr>; + + vreg_s1c_2p19: smps1 { + regulator-name = "vreg_s1c_2p19"; + regulator-min-microvolt = <2190000>; + regulator-max-microvolt = <2210000>; + }; + + vreg_s9c_1p084: smps9 { + regulator-name = "vreg_s9c_1p084"; + regulator-min-microvolt = <1084000>; + regulator-max-microvolt = <1170000>; + }; + + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2c_1p62: ldo2 { + regulator-name = "vreg_l2c_1p62"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3c_2p8: ldo3 { + regulator-name = "vreg_l3c_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3540000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4c_1p62: ldo4 { + regulator-name = "vreg_l4c_1p62"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5c_1p62: ldo5 { + regulator-name = "vreg_l5c_1p62"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6c_2p96: ldo6 { + regulator-name = "vreg_l6c_2p96"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7c_3p0: ldo7 { + regulator-name = "vreg_l7c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8c_1p62: ldo8 { + regulator-name = "vreg_l8c_1p62"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9c_2p96: ldo9 { + regulator-name = "vreg_l9c_2p96"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l10c_0p88: ldo10 { + regulator-name = "vreg_l10c_0p88"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11c_2p8: ldo11 { + regulator-name = "vreg_l11c_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l12c_1p65: ldo12 { + regulator-name = "vreg_l12c_1p65"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l13c_2p7: ldo13 { + regulator-name = "vreg_l13c_2p7"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_bob_3p296: bob { + regulator-name = "vreg_bob_3p296"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + + status = "okay"; +}; + +&ipa { + firmware-name = "qcom/qcm6490/particle/tachyon/ipa_fws.mbn"; + qcom,gsi-loader = "self"; + memory-region = <&ipa_fw_mem>; + + status = "okay"; +}; + +&gcc { + protected-clocks = <GCC_CFG_NOC_LPASS_CLK>, + <GCC_MSS_CFG_AHB_CLK>, + <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>, + <GCC_MSS_OFFLINE_AXI_CLK>, + <GCC_MSS_Q6SS_BOOT_CLK_SRC>, + <GCC_MSS_Q6_MEMNOC_AXI_CLK>, + <GCC_MSS_SNOC_AXI_CLK>, + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, + <GCC_QSPI_CORE_CLK>, + <GCC_QSPI_CORE_CLK_SRC>, + <GCC_SEC_CTRL_CLK_SRC>, + <GCC_WPSS_AHB_BDG_MST_CLK>, + <GCC_WPSS_AHB_CLK>, + <GCC_WPSS_RSCP_CLK>; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcm6490/particle/tachyon/a660_zap.mbn"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp { + status = "okay"; +}; + +&mdss_dp_out { + data-lanes = <0 1>; +}; + +&pcie0 { + perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&pcie1 { + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>; + pinctrl-names = "default"; + + vddpe-3v3-supply = <&vreg_power_5v>; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&pmk8350_adc_tm { + status = "okay"; + + xo-therm@0 { + reg = <0>; + io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pmk8350_rtc { + status = "okay"; +}; + +&pmk8350_vadc { + status = "okay"; + + channel@44 { + reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pmk8350_xo_therm"; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/qcm6490/particle/tachyon/adsp.mbn"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcm6490/particle/tachyon/cdsp.mbn"; + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/qcm6490/particle/tachyon/modem.mbn"; + status = "okay"; +}; + +&sdc2_clk { + bias-disable; + drive-strength = <16>; +}; + +&sdc2_cmd { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc2_data { + bias-pull-up; + drive-strength = <10>; +}; + +&sdhc_2 { + vmmc-supply = <&vreg_l9c_2p96>; + vqmmc-supply = <&vreg_l6c_2p96>; + + cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&tlmm { + activity_led_state: activity-led-state { + pins = "gpio14"; + function = "gpio"; + bias-disable; + }; + + bt_en_state: bt-default-state { + pins = "gpio84"; + function = "gpio"; + drive-strength = <16>; + output-low; + bias-pull-up; + }; + + pcie0_reset_n: pcie0-reset-n-state { + pins = "gpio87"; + function = "gpio"; + drive-strength = <16>; + output-low; + bias-disable; + }; + + pcie0_wake_n: pcie0-wake-n-state { + pins = "gpio89"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + pcie1_reset_n: pcie1-reset-n-state { + pins = "gpio2"; + function = "gpio"; + drive-strength = <16>; + output-low; + bias-disable; + }; + + pcie1_wake_n: pcie1-wake-n-state { + pins = "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_uart7_sleep_cts: qup-uart7-sleep-cts-state { + pins = "gpio28"; + function = "gpio"; + /* + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. + */ + bias-bus-hold; + }; + + qup_uart7_sleep_rts: qup-uart7-sleep-rts-state { + pins = "gpio29"; + function = "gpio"; + /* + * Configure pull-down on RTS. As RTS is active low + * signal, pull it low to indicate the BT SoC that it + * can wakeup the system anytime from suspend state by + * pulling RX low (by sending wakeup bytes). + */ + bias-pull-down; + }; + + qup_uart7_sleep_tx: qup-uart7-sleep-tx-state { + pins = "gpio30"; + function = "gpio"; + /* + * Configure pull-up on TX when it isn't actively driven + * to prevent BT SoC from receiving garbage during sleep. + */ + bias-pull-up; + }; + + qup_uart7_sleep_rx: qup-uart7-sleep-rx-state { + pins = "gpio31"; + function = "gpio"; + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module + * is floating which may cause spurious wakeups. + */ + bias-pull-up; + }; + + usbdp_sbu_default: usbdp-sbu-state { + oe-n-pins { + pins = "gpio108"; + function = "gpio"; + bias-disable; + drive-strength = <16>; + output-high; + }; + + sel-pins { + pins = "gpio42"; + function = "gpio"; + bias-disable; + drive-strength = <16>; + }; + }; + + wlan_en_state: wlan-default-state { + pins = "gpio85"; + function = "gpio"; + drive-strength = <16>; + output-low; + bias-pull-up; + }; +}; + +&uart5 { + status = "okay"; +}; + +&uart7 { + /delete-property/ interrupts; + interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-1 = <&qup_uart7_sleep_cts>, + <&qup_uart7_sleep_rts>, + <&qup_uart7_sleep_tx>, + <&qup_uart7_sleep_rx>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&uart8 { + status = "okay"; +}; + +&uart12 { + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l7b_2p952>; + vcc-max-microamp = <800000>; + vccq-supply = <&vreg_l9b_1p2>; + vccq-max-microamp = <900000>; + vccq2-supply = <&vreg_l9b_1p2>; + vccq2-max-microamp = <900000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&usb_1 { + dr_mode = "otg"; + usb-role-switch; + + status = "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l10c_0p88>; + vdda33-supply = <&vreg_l2b_3p072>; + vdda18-supply = <&vreg_l1c_1p8>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l6b_1p2>; + vdda-pll-supply = <&vreg_l1b_0p912>; + + status = "okay"; +}; + +&usb_2 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_2_hsphy { + vdda-pll-supply = <&vreg_l10c_0p88>; + vdda18-supply = <&vreg_l1c_1p8>; + vdda33-supply = <&vreg_l2b_3p072>; + + status = "okay"; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; diff --git a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts index b9a0f7ac4d9c..eb8efba1b9dd 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts @@ -910,12 +910,10 @@ }; &usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { dr_mode = "otg"; usb-role-switch; + + status = "okay"; }; &usb_1_dwc3_hs { diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 5a9df6b12305..4328c1dda898 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -1312,6 +1312,7 @@ intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; + #address-cells = <0>; #interrupt-cells = <3>; reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index a6652e4817d1..705ea71b07a1 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -7,17 +7,18 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include <dt-bindings/gpio/gpio.h> -#include "qcs615.dtsi" +#include "sm6150.dtsi" #include "pm8150.dtsi" / { model = "Qualcomm Technologies, Inc. QCS615 Ride"; - compatible = "qcom,qcs615-ride", "qcom,qcs615"; + compatible = "qcom,qcs615-ride", "qcom,qcs615", "qcom,sm6150"; chassis-type = "embedded"; aliases { mmc0 = &sdhc_1; mmc1 = &sdhc_2; serial0 = &uart0; + serial1 = &uart7; }; chosen { @@ -38,6 +39,22 @@ }; }; + vreg_conn_1p8: regulator-conn-1p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_1p8"; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&pm8150_gpios 1 GPIO_ACTIVE_HIGH>; + }; + + vreg_conn_pa: regulator-conn-pa { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_pa"; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&pm8150_gpios 6 GPIO_ACTIVE_HIGH>; + }; + regulator-usb2-vbus { compatible = "regulator-fixed"; regulator-name = "USB2_VBUS"; @@ -47,6 +64,69 @@ enable-active-high; regulator-always-on; }; + + wcn6855-pmu { + compatible = "qcom,wcn6855-pmu"; + + pinctrl-0 = <&bt_en_state>, <&wlan_en_state>; + pinctrl-names = "default"; + + bt-enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>; + wlan-enable-gpios = <&tlmm 98 GPIO_ACTIVE_HIGH>; + + vddio-supply = <&vreg_conn_pa>; + vddaon-supply = <&vreg_s5a>; + vddpmu-supply = <&vreg_conn_1p8>; + vddpmumx-supply = <&vreg_conn_1p8>; + vddpmucx-supply = <&vreg_conn_pa>; + vddrfa0p95-supply = <&vreg_s5a>; + vddrfa1p3-supply = <&vreg_s6a>; + vddrfa1p9-supply = <&vreg_l15a>; + vddpcie1p3-supply = <&vreg_s6a>; + vddpcie1p9-supply = <&vreg_l15a>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p7: ldo7 { + regulator-name = "vreg_pmu_rfa_1p7"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &apps_rsc { @@ -166,10 +246,7 @@ regulator-name = "vreg_l12a"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1890000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; - regulator-allow-set-load; - regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM - RPMH_REGULATOR_MODE_HPM>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l13a: ldo13 { @@ -211,10 +288,40 @@ }; }; -&gcc { - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&rpmhcc RPMH_CXO_CLK_A>, - <&sleep_clk>; +&pcie { + perst-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l12a>; + + status = "okay"; +}; + +&pcie_port0 { + wifi@0 { + compatible = "pci17cb,1103"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + qcom,calibration-variant = "QC_QCS615_Ride"; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; }; &pm8150_gpios { @@ -240,6 +347,10 @@ status = "okay"; }; +&qupv3_id_1 { + status = "okay"; +}; + &remoteproc_adsp { firmware-name = "qcom/qcs615/adsp.mbn"; @@ -252,8 +363,43 @@ status = "okay"; }; -&rpmhcc { - clocks = <&xo_board_clk>; +&tlmm { + bt_en_state: bt-en-state { + pins = "gpio85"; + function = "gpio"; + bias-pull-down; + output-low; + }; + + pcie_default_state: pcie-default-state { + clkreq-pins { + pins = "gpio90"; + function = "pcie_clk_req"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio101"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-pins { + pins = "gpio100"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + wlan_en_state: wlan-en-state { + pins = "gpio98"; + function = "gpio"; + bias-pull-down; + output-low; + }; }; &sdhc_1 { @@ -294,6 +440,24 @@ status = "okay"; }; +&uart7 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn6855-bt"; + firmware-name = "QCA6698/hpnv21", "QCA6698/hpbtfw21.tlv"; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + }; +}; + &usb_1_hsphy { vdd-supply = <&vreg_l5a>; vdda-pll-supply = <&vreg_l12a>; @@ -350,6 +514,6 @@ status = "okay"; }; -&watchdog { - clocks = <&sleep_clk>; +&venus { + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi b/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi new file mode 100644 index 000000000000..c1867711298b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * Common definitions for SC7280-based boards with AudioReach. + */ + +#include <dt-bindings/clock/qcom,lpass-sc7280.h> +#include <dt-bindings/soc/qcom,gpr.h> +#include <dt-bindings/sound/qcom,q6afe.h> +#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> + +&lpass_rx_macro { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_va_macro>; + clock-names = "mclk", + "npl", + "macro", + "dcodec", + "fsgen"; +}; + +&lpass_tlmm { + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", + "audio"; +}; + +&lpass_tx_macro { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_va_macro>; + clock-names = "mclk", + "npl", + "macro", + "dcodec", + "fsgen"; +}; + +&lpass_va_macro { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + clocks = <&q6prmcc LPASS_CLK_ID_VA_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk", + "macro", + "dcodec"; + + pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>, + <&lpass_dmic23_clk>, <&lpass_dmic23_data>; + pinctrl-names = "default"; + + qcom,dmic-sample-rate = <4800000>; +}; + +&lpass_wsa_macro { + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_va_macro>; + clock-names = "mclk", + "npl", + "macro", + "dcodec", + "fsgen"; +}; + +&remoteproc_adsp_glink { + /delete-node/ apr; + + gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,domain = <GPR_DOMAIN_ID_ADSP>; + qcom,intents = <512 20>; + #address-cells = <1>; + #size-cells = <0>; + + q6apm: service@1 { + compatible = "qcom,q6apm"; + reg = <GPR_APM_MODULE_IID>; + #sound-dai-cells = <0>; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + + q6apmdai: dais { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x1801 0x0>; + }; + + q6apmbedai: bedais { + compatible = "qcom,q6apm-lpass-dais"; + #sound-dai-cells = <1>; + }; + }; + + q6prm: service@2 { + compatible = "qcom,q6prm"; + reg = <GPR_PRM_MODULE_IID>; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + #clock-cells = <2>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 5fbcd48f2e2d..18cea8812001 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -19,6 +19,7 @@ #include "pm7325.dtsi" #include "pm8350c.dtsi" #include "pmk8350.dtsi" +#include "qcs6490-audioreach.dtsi" /delete-node/ &ipa_fw_mem; /delete-node/ &rmtfs_mem; @@ -765,6 +766,14 @@ }; }; +&lpass_va_macro { + status = "okay"; +}; + +&lpass_wsa_macro { + status = "okay"; +}; + &mdss { status = "okay"; }; @@ -811,7 +820,7 @@ &pcie1 { perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>; + pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>; pinctrl-names = "default"; iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, @@ -1039,6 +1048,77 @@ status = "okay"; }; +&sound { + compatible = "qcom,qcs6490-rb3gen2-sndcard"; + model = "QCS6490-RB3Gen2"; + + audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "VA DMIC0", "vdd-micb", + "VA DMIC1", "vdd-micb", + "VA DMIC2", "vdd-micb", + "VA DMIC3", "vdd-micb"; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, + <&swr2 0>, <&lpass_wsa_macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_va_macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; +}; + +&swr2 { + status = "okay"; + + left_spkr: speaker@0,1 { + compatible = "sdw10217020200"; + reg = <0 1>; + reset-gpios = <&tlmm 158 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + #thermal-sensor-cells = <0>; + vdd-supply = <&vreg_l18b_1p8>; + qcom,port-mapping = <1 2 3 7>; + }; + + right_spkr: speaker@0,2 { + compatible = "sdw10217020200"; + reg = <0 2>; + reset-gpios = <&tlmm 158 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + #thermal-sensor-cells = <0>; + vdd-supply = <&vreg_l18b_1p8>; + qcom,port-mapping = <4 5 6 8>; + }; +}; + &tlmm { gpio-reserved-ranges = <32 2>, /* ADSP */ <48 4>; /* NFC */ @@ -1127,12 +1207,10 @@ }; &usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { dr_mode = "otg"; usb-role-switch; + + status = "okay"; }; &usb_1_dwc3_hs { diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index 8c166ead912c..cabb3f508704 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -17,6 +17,7 @@ aliases { serial0 = &uart7; + mmc0 = &sdhc_1; }; chosen { @@ -295,6 +296,14 @@ }; }; +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcs8300/a623_zap.mbn"; +}; + &pmm8650au_1_gpios { usb2_en: usb2-en-state { pins = "gpio7"; @@ -332,6 +341,26 @@ status = "okay"; }; +&sdhc_1 { + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + pinctrl-names = "default", "sleep"; + + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + vmmc-supply = <&vreg_l8a>; + vqmmc-supply = <&vreg_s4a>; + + non-removable; + no-sd; + no-sdio; + + status = "okay"; +}; + &tlmm { ethernet0_default: ethernet0-default-state { ethernet0_mdc: ethernet0-mdc-pins { @@ -393,17 +422,13 @@ }; &usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { dr_mode = "peripheral"; -}; -&usb_2 { status = "okay"; }; -&usb_2_dwc3 { +&usb_2 { dr_mode = "host"; + + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 7ada029c32c1..8d78ccac411e 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -12,11 +12,13 @@ #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/firmware/qcom,scm.h> #include <dt-bindings/interconnect/qcom,icc.h> +#include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/power/qcom,rpmhpd.h> #include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/soc/qcom,gpr.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> / { @@ -53,6 +55,11 @@ capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <472>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; l2_0: l2-cache { compatible = "cache"; @@ -73,6 +80,11 @@ capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <472>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; l2_1: l2-cache { compatible = "cache"; @@ -93,6 +105,11 @@ capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <507>; qcom,freq-domain = <&cpufreq_hw 2>; + operating-points-v2 = <&cpu2_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; l2_2: l2-cache { compatible = "cache"; @@ -113,6 +130,11 @@ capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <507>; qcom,freq-domain = <&cpufreq_hw 2>; + operating-points-v2 = <&cpu2_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; l2_3: l2-cache { compatible = "cache"; @@ -133,6 +155,11 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; l2_4: l2-cache { compatible = "cache"; @@ -153,6 +180,11 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; l2_5: l2-cache { compatible = "cache"; @@ -173,6 +205,11 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; l2_6: l2-cache { compatible = "cache"; @@ -193,6 +230,11 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; l2_7: l2-cache { compatible = "cache"; @@ -323,6 +365,248 @@ }; }; + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + opp-peak-kBps = <(681600 * 4) (921600 * 32)>; + }; + + opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + opp-peak-kBps = <(1017600 * 4) (921600 * 32)>; + }; + + opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + opp-peak-kBps = <(1708800 * 4) (921600 * 32)>; + }; + + opp-1267200000 { + opp-hz = /bits/ 64 <1267200000>; + opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; + }; + + opp-1344000000 { + opp-hz = /bits/ 64 <1344000000>; + opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>; + }; + + opp-1420800000 { + opp-hz = /bits/ 64 <1420800000>; + opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>; + }; + + opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>; + }; + + opp-1574400000 { + opp-hz = /bits/ 64 <1574400000>; + opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; + }; + + opp-1670400000 { + opp-hz = /bits/ 64 <1670400000>; + opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; + }; + + opp-1747200000 { + opp-hz = /bits/ 64 <1747200000>; + opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; + }; + + opp-1824000000 { + opp-hz = /bits/ 64 <1824000000>; + opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; + }; + + opp-1900800000 { + opp-hz = /bits/ 64 <1900800000>; + opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; + }; + + opp-1977600000 { + opp-hz = /bits/ 64 <1977600000>; + opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; + }; + + opp-2054400000 { + opp-hz = /bits/ 64 <2054400000>; + opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; + }; + + opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; + }; + + }; + + cpu2_opp_table: opp-table-cpu2 { + compatible = "operating-points-v2"; + opp-shared; + + opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + opp-peak-kBps = <(681600 * 4) (921600 * 32)>; + }; + + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + opp-peak-kBps = <(1017600 * 4) (921600 * 32)>; + }; + + opp-1267200000 { + opp-hz = /bits/ 64 <1267200000>; + opp-peak-kBps = <(1708800 * 4) (921600 * 32)>; + }; + + opp-1344000000 { + opp-hz = /bits/ 64 <1344000000>; + opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; + }; + + opp-1420800000 { + opp-hz = /bits/ 64 <1420800000>; + opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; + }; + + opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>; + }; + + opp-1574400000 { + opp-hz = /bits/ 64 <1574400000>; + opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>; + }; + + opp-1632000000 { + opp-hz = /bits/ 64 <1632000000>; + opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>; + }; + + opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; + }; + + opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; + }; + + opp-1900800000 { + opp-hz = /bits/ 64 <1900800000>; + opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; + }; + + opp-1977600000 { + opp-hz = /bits/ 64 <1977600000>; + opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; + }; + + opp-2054400000 { + opp-hz = /bits/ 64 <2054400000>; + opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; + }; + + opp-2131200000 { + opp-hz = /bits/ 64 <2131200000>; + opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; + }; + + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; + }; + + opp-2284800000 { + opp-hz = /bits/ 64 <2284800000>; + opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; + }; + + opp-2361600000 { + opp-hz = /bits/ 64 <2361600000>; + opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; + }; + + }; + + cpu4_opp_table: opp-table-cpu4 { + compatible = "operating-points-v2"; + opp-shared; + + opp-844800000 { + opp-hz = /bits/ 64 <844800000>; + opp-peak-kBps = <(681600 * 4) (921600 * 32)>; + }; + + opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + opp-peak-kBps = <(1708800 * 4) (921600 * 32)>; + }; + + opp-1209600000 { + opp-hz = /bits/ 64 <1209600000>; + opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; + }; + + opp-1305600000 { + opp-hz = /bits/ 64 <1305600000>; + opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>; + }; + + opp-1382400000 { + opp-hz = /bits/ 64 <1382400000>; + opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>; + }; + + opp-1459200000 { + opp-hz = /bits/ 64 <1459200000>; + opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>; + }; + + opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; + }; + + opp-1574400000 { + opp-hz = /bits/ 64 <1574400000>; + opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; + }; + + opp-1651200000 { + opp-hz = /bits/ 64 <1651200000>; + opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; + }; + + opp-1728000000 { + opp-hz = /bits/ 64 <1728000000>; + opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; + }; + + opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; + }; + + opp-1881600000 { + opp-hz = /bits/ 64 <1881600000>; + opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; + }; + + opp-1958400000 { + opp-hz = /bits/ 64 <1958400000>; + opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; + }; + }; + dummy_eud: dummy-sink { compatible = "arm,coresight-dummy-sink"; @@ -640,9 +924,14 @@ qfprom: efuse@784000 { compatible = "qcom,qcs8300-qfprom", "qcom,qfprom"; - reg = <0x0 0x00784000 0x0 0x1200>; + reg = <0x0 0x00784000 0x0 0x2410>; #address-cells = <1>; #size-cells = <1>; + + gpu_speed_bin: gpu_speed_bin@240c { + reg = <0x240c 0x1>; + bits = <0 8>; + }; }; gpi_dma0: dma-controller@900000 { @@ -817,7 +1106,7 @@ <&qup_uart1_tx>, <&qup_uart1_rx>; pinctrl-names = "default"; interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; @@ -984,7 +1273,7 @@ interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, @@ -1057,7 +1346,7 @@ interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, @@ -1130,7 +1419,7 @@ interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, @@ -2144,6 +2433,45 @@ dma-coherent; }; }; + + gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,domain = <GPR_DOMAIN_ID_ADSP>; + qcom,intents = <512 20>; + #address-cells = <1>; + #size-cells = <0>; + + q6apm: service@1 { + compatible = "qcom,q6apm"; + reg = <GPR_APM_MODULE_IID>; + #sound-dai-cells = <0>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6apmbedai: bedais { + compatible = "qcom,q6apm-lpass-dais"; + #sound-dai-cells = <1>; + }; + + q6apmdai: dais { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x2001 0x0>; + }; + }; + + q6prm: service@2 { + compatible = "qcom,q6prm"; + reg = <GPR_PRM_MODULE_IID>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + #clock-cells = <2>; + }; + }; + }; }; }; @@ -3837,6 +4165,69 @@ clock-names = "apb_pclk"; }; + sdhc_1: mmc@87c4000 { + compatible = "qcom,qcs8300-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x087c4000 0x0 0x1000>, + <0x0 0x087c5000 0x0 0x1000>; + reg-names = "hc", + "cqhci"; + + interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", + "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "core", + "xo"; + + resets = <&gcc GCC_SDCC1_BCR>; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&sdhc1_opp_table>; + iommus = <&apps_smmu 0x0 0x0>; + interconnects = <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_SDC1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "sdhc-ddr", + "cpu-sdhc"; + + qcom,dll-config = <0x000f64ee>; + qcom,ddr-config = <0x80040868>; + supports-cqe; + dma-coherent; + + status = "disabled"; + + sdhc1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + usb_1_hsphy: phy@8904000 { compatible = "qcom,qcs8300-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; @@ -3903,6 +4294,104 @@ status = "disabled"; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-623.0", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&adreno_smmu 0 0xc00>, + <&adreno_smmu 1 0xc00>; + operating-points-v2 = <&gpu_opp_table>; + qcom,gmu = <&gmu>; + interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "gfx-mem"; + #cooling-cells = <2>; + + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + + status = "disabled"; + + gpu_zap_shader: zap-shader { + memory-region = <&gpu_microcode_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-877000000 { + opp-hz = /bits/ 64 <877000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + opp-peak-kBps = <12484375>; + opp-supported-hw = <0x1>; + }; + + opp-780000000 { + opp-hz = /bits/ 64 <780000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + opp-peak-kBps = <10687500>; + opp-supported-hw = <0x1>; + }; + + opp-599000000 { + opp-hz = /bits/ 64 <599000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + opp-peak-kBps = <8171875>; + opp-supported-hw = <0x3>; + }; + + opp-479000000 { + opp-hz = /bits/ 64 <479000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + opp-peak-kBps = <5285156>; + opp-supported-hw = <0x3>; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-623.0", "qcom,adreno-gmu"; + reg = <0x0 0x03d6a000 0x0 0x34000>, + <0x0 0x03de0000 0x0 0x10000>, + <0x0 0x0b290000 0x0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>; + clock-names = "gmu", + "cxo", + "axi", + "memnoc", + "ahb", + "hub"; + power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_GX_GDSC>; + power-domain-names = "cx", + "gx"; + iommus = <&adreno_smmu 5 0xc00>; + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,qcs8300-gpucc"; reg = <0x0 0x03d90000 0x0 0xa000>; @@ -4081,9 +4570,9 @@ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; }; - usb_1: usb@a6f8800 { - compatible = "qcom,qcs8300-dwc3", "qcom,dwc3"; - reg = <0x0 0x0a6f8800 0x0 0x400>; + usb_1: usb@a600000 { + compatible = "qcom,qcs8300-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a600000 0x0 0xfc100>; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, @@ -4100,12 +4589,14 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event", + interrupt-names = "dwc_usb3", + "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", @@ -4121,32 +4612,23 @@ &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "usb-ddr", "apps-usb"; - wakeup-source; + iommus = <&apps_smmu 0x80 0x0>; + phys = <&usb_1_hsphy>, <&usb_qmpphy>; + phy-names = "usb2-phy", "usb3-phy"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; - #address-cells = <2>; - #size-cells = <2>; - ranges; + wakeup-source; status = "disabled"; - - usb_1_dwc3: usb@a600000 { - compatible = "snps,dwc3"; - reg = <0x0 0x0a600000 0x0 0xe000>; - interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; - iommus = <&apps_smmu 0x80 0x0>; - phys = <&usb_1_hsphy>, <&usb_qmpphy>; - phy-names = "usb2-phy", "usb3-phy"; - snps,dis_enblslpm_quirk; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - snps,dis_u2_susphy_quirk; - snps,dis_u3_susphy_quirk; - }; }; - usb_2: usb@a4f8800 { - compatible = "qcom,qcs8300-dwc3", "qcom,dwc3"; - reg = <0x0 0x0a4f8800 0x0 0x400>; + usb_2: usb@a400000 { + compatible = "qcom,qcs8300-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a400000 0x0 0xfc100>; clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, <&gcc GCC_USB20_MASTER_CLK>, @@ -4163,11 +4645,13 @@ <&gcc GCC_USB20_MASTER_CLK>; assigned-clock-rates = <19200000>, <120000000>; - interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, <&pdc 10 IRQ_TYPE_EDGE_BOTH>, <&pdc 9 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "pwr_event", + interrupt-names = "dwc_usb3", + "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq"; @@ -4183,32 +4667,22 @@ &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "usb-ddr", "apps-usb"; - qcom,select-utmi-as-pipe-clk; - wakeup-source; + iommus = <&apps_smmu 0x20 0x0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + phys = <&usb_2_hsphy>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; - status = "disabled"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis_enblslpm_quirk; - usb_2_dwc3: usb@a400000 { - compatible = "snps,dwc3"; - reg = <0x0 0x0a400000 0x0 0xe000>; - - interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>; - iommus = <&apps_smmu 0x20 0x0>; - - phys = <&usb_2_hsphy>; - phy-names = "usb2-phy"; - maximum-speed = "high-speed"; + qcom,select-utmi-as-pipe-clk; + wakeup-source; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - snps,dis_u2_susphy_quirk; - snps,dis_u3_susphy_quirk; - snps,dis_enblslpm_quirk; - }; + status = "disabled"; }; iris: video-codec@aa00000 { @@ -4418,6 +4892,43 @@ #interrupt-cells = <2>; wakeup-parent = <&pdc>; + hs0_mi2s_active: hs0-mi2s-active-state { + pins = "gpio106", "gpio107", "gpio108", "gpio109"; + function = "hs0_mi2s"; + drive-strength = <8>; + bias-disable; + }; + + mi2s1_active: mi2s1-active-state { + data0-pins { + pins = "gpio100"; + function = "mi2s1_data0"; + drive-strength = <8>; + bias-disable; + }; + + data1-pins { + pins = "gpio101"; + function = "mi2s1_data1"; + drive-strength = <8>; + bias-disable; + }; + + sclk-pins { + pins = "gpio98"; + function = "mi2s1_sck"; + drive-strength = <8>; + bias-disable; + }; + + ws-pins { + pins = "gpio99"; + function = "mi2s1_ws"; + drive-strength = <8>; + bias-disable; + }; + }; + qup_i2c0_data_clk: qup-i2c0-data-clk-state { pins = "gpio17", "gpio18"; function = "qup0_se0"; @@ -5042,6 +5553,56 @@ pins = "gpio13"; function = "qup2_se0"; }; + + sdc1_state_on: sdc1-on-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_state_off: sdc1-off-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <2>; + bias-bus-hold; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <2>; + bias-bus-hold; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <2>; + bias-bus-hold; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-bus-hold; + }; + }; }; sram: sram@146d8000 { @@ -5433,6 +5994,15 @@ }; }; + epss_l3_cl0: interconnect@18590000 { + compatible = "qcom,qcs8300-epss-l3", "qcom,sa8775p-epss-l3", + "qcom,epss-l3"; + reg = <0x0 0x18590000 0x0 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@18591000 { compatible = "qcom,qcs8300-cpufreq-epss", "qcom,cpufreq-epss"; reg = <0x0 0x18591000 0x0 0x1000>, @@ -5455,6 +6025,15 @@ #freq-domain-cells = <1>; }; + epss_l3_cl1: interconnect@18592000 { + compatible = "qcom,qcs8300-epss-l3", "qcom,sa8775p-epss-l3", + "qcom,epss-l3"; + reg = <0x0 0x18592000 0x0 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + remoteproc_gpdsp: remoteproc@20c00000 { compatible = "qcom,qcs8300-gpdsp-pas", "qcom,sa8775p-gpdsp0-pas"; reg = <0x0 0x20c00000 0x0 0x10000>; diff --git a/arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts b/arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts index 759d1ec694b2..7fc2de0d3d5e 100644 --- a/arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts +++ b/arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts @@ -4,8 +4,13 @@ */ /dts-v1/; -#include "sa8775p-ride-r3.dts" +#include "lemans.dtsi" +#include "lemans-pmics.dtsi" + +#include "lemans-ride-common.dtsi" +#include "lemans-ride-ethernet-aqr115c.dtsi" + / { - model = "Qualcomm QCS9100 Ride Rev3"; + model = "Qualcomm Technologies, Inc. Lemans Ride Rev3"; compatible = "qcom,qcs9100-ride-r3", "qcom,qcs9100", "qcom,sa8775p"; }; diff --git a/arch/arm64/boot/dts/qcom/qcs9100-ride.dts b/arch/arm64/boot/dts/qcom/qcs9100-ride.dts index 979462dfec30..b0c5fdde56ae 100644 --- a/arch/arm64/boot/dts/qcom/qcs9100-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs9100-ride.dts @@ -4,8 +4,13 @@ */ /dts-v1/; -#include "sa8775p-ride.dts" +#include "lemans.dtsi" +#include "lemans-pmics.dtsi" + +#include "lemans-ride-common.dtsi" +#include "lemans-ride-ethernet-88ea1512.dtsi" + / { - model = "Qualcomm QCS9100 Ride"; + model = "Qualcomm Technologies, Inc. Lemans Ride"; compatible = "qcom,qcs9100-ride", "qcom,qcs9100", "qcom,sa8775p"; }; diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts index b2e0fc5501c1..67ba508e92ba 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/leds/common.h> #include "qcm2290.dtsi" #include "pm4125.dtsi" @@ -63,8 +64,8 @@ i2c2_gpio: i2c { compatible = "i2c-gpio"; - sda-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; - scl-gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>; + sda-gpios = <&tlmm 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; @@ -698,6 +699,10 @@ remote-endpoint = <&pm4125_ss_in>; }; +&venus { + status = "okay"; +}; + &wifi { vdd-0.8-cx-mx-supply = <&pm4125_l7>; vdd-1.8-xo-supply = <&pm4125_l13>; diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index a37860175d27..bdf2d66e40c6 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/leds/common.h> #include <dt-bindings/sound/qcom,q6afe.h> #include <dt-bindings/sound/qcom,q6asm.h> @@ -65,8 +66,8 @@ i2c2_gpio: i2c { compatible = "i2c-gpio"; - sda-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; - scl-gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>; + sda-gpios = <&tlmm 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 33ecbc81997c..d99448a0732d 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -725,15 +725,11 @@ qcom,dual-dsi-mode; qcom,master-dsi; #endif +}; - ports { - port@1 { - endpoint { - remote-endpoint = <<9611_a>; - data-lanes = <0 1 2 3>; - }; - }; - }; +&mdss_dsi0_out { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; }; &mdss_dsi0_phy { diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index 2fd1dafe63ce..64e59299672c 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -35,7 +35,7 @@ port { dp2_connector_in: endpoint { - remote-endpoint = <&mdss1_dp0_phy_out>; + remote-endpoint = <&mdss1_dp0_out>; }; }; }; @@ -49,7 +49,7 @@ port { dp3_connector_in: endpoint { - remote-endpoint = <&mdss1_dp1_phy_out>; + remote-endpoint = <&mdss1_dp1_out>; }; }; }; @@ -63,7 +63,7 @@ port { edp0_connector_in: endpoint { - remote-endpoint = <&mdss0_dp2_phy_out>; + remote-endpoint = <&mdss0_dp2_out>; }; }; }; @@ -77,7 +77,7 @@ port { edp1_connector_in: endpoint { - remote-endpoint = <&mdss0_dp3_phy_out>; + remote-endpoint = <&mdss0_dp3_out>; }; }; }; @@ -91,7 +91,7 @@ port { edp2_connector_in: endpoint { - remote-endpoint = <&mdss1_dp2_phy_out>; + remote-endpoint = <&mdss1_dp2_out>; }; }; }; @@ -105,7 +105,7 @@ port { edp3_connector_in: endpoint { - remote-endpoint = <&mdss1_dp3_phy_out>; + remote-endpoint = <&mdss1_dp3_out>; }; }; }; @@ -361,18 +361,12 @@ }; &mdss0_dp2 { - data-lanes = <0 1 2 3>; - status = "okay"; +}; - ports { - port@1 { - reg = <1>; - mdss0_dp2_phy_out: endpoint { - remote-endpoint = <&edp0_connector_in>; - }; - }; - }; +&mdss0_dp2_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&edp0_connector_in>; }; &mdss0_dp2_phy { @@ -383,18 +377,12 @@ }; &mdss0_dp3 { - data-lanes = <0 1 2 3>; - status = "okay"; +}; - ports { - port@1 { - reg = <1>; - mdss0_dp3_phy_out: endpoint { - remote-endpoint = <&edp1_connector_in>; - }; - }; - }; +&mdss0_dp3_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&edp1_connector_in>; }; &mdss0_dp3_phy { @@ -409,18 +397,12 @@ }; &mdss1_dp0 { - data-lanes = <0 1 2 3>; - status = "okay"; +}; - ports { - port@1 { - reg = <1>; - mdss1_dp0_phy_out: endpoint { - remote-endpoint = <&dp2_connector_in>; - }; - }; - }; +&mdss1_dp0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&dp2_connector_in>; }; &mdss1_dp0_phy { @@ -431,18 +413,12 @@ }; &mdss1_dp1 { - data-lanes = <0 1 2 3>; - status = "okay"; +}; - ports { - port@1 { - reg = <1>; - mdss1_dp1_phy_out: endpoint { - remote-endpoint = <&dp3_connector_in>; - }; - }; - }; +&mdss1_dp1_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&dp3_connector_in>; }; &mdss1_dp1_phy { @@ -453,18 +429,12 @@ }; &mdss1_dp2 { - data-lanes = <0 1 2 3>; - status = "okay"; +}; - ports { - port@1 { - reg = <1>; - mdss1_dp2_phy_out: endpoint { - remote-endpoint = <&edp2_connector_in>; - }; - }; - }; +&mdss1_dp2_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&edp2_connector_in>; }; &mdss1_dp2_phy { @@ -475,18 +445,12 @@ }; &mdss1_dp3 { - data-lanes = <0 1 2 3>; - status = "okay"; +}; - ports { - port@1 { - reg = <1>; - mdss1_dp3_phy_out: endpoint { - remote-endpoint = <&edp3_connector_in>; - }; - }; - }; +&mdss1_dp3_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&edp3_connector_in>; }; &mdss1_dp3_phy { diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts index ae065ae92478..b25f0b2c9410 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts @@ -5,43 +5,13 @@ /dts-v1/; -#include "sa8775p-ride.dtsi" +#include "lemans-auto.dtsi" + +#include "lemans-pmics.dtsi" +#include "lemans-ride-common.dtsi" +#include "lemans-ride-ethernet-aqr115c.dtsi" / { model = "Qualcomm SA8775P Ride Rev3"; compatible = "qcom,sa8775p-ride-r3", "qcom,sa8775p"; }; - -ðernet0 { - phy-mode = "2500base-x"; -}; - -ðernet1 { - phy-mode = "2500base-x"; -}; - -&mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - sgmii_phy0: phy@8 { - compatible = "ethernet-phy-id31c3.1c33"; - reg = <0x8>; - device_type = "ethernet-phy"; - interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; - reset-assert-us = <11000>; - reset-deassert-us = <70000>; - }; - - sgmii_phy1: phy@0 { - compatible = "ethernet-phy-id31c3.1c33"; - reg = <0x0>; - device_type = "ethernet-phy"; - interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; - reset-assert-us = <11000>; - reset-deassert-us = <70000>; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index 2e87fd760dbd..2d9028cd60be 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -5,43 +5,13 @@ /dts-v1/; -#include "sa8775p-ride.dtsi" +#include "lemans-auto.dtsi" + +#include "lemans-pmics.dtsi" +#include "lemans-ride-common.dtsi" +#include "lemans-ride-ethernet-88ea1512.dtsi" / { model = "Qualcomm SA8775P Ride"; compatible = "qcom,sa8775p-ride", "qcom,sa8775p"; }; - -ðernet0 { - phy-mode = "sgmii"; -}; - -ðernet1 { - phy-mode = "sgmii"; -}; - -&mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - sgmii_phy0: phy@8 { - compatible = "ethernet-phy-id0141.0dd4"; - reg = <0x8>; - device_type = "ethernet-phy"; - interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; - reset-assert-us = <11000>; - reset-deassert-us = <70000>; - }; - - sgmii_phy1: phy@a { - compatible = "ethernet-phy-id0141.0dd4"; - reg = <0xa>; - device_type = "ethernet-phy"; - interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; - reset-assert-us = <11000>; - reset-deassert-us = <70000>; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi index e400ea4cdee8..d65ad0df6865 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi +++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2024, Linaro Limited */ +#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,sar2130p-gcc.h> #include <dt-bindings/clock/qcom,sar2130p-gpucc.h> @@ -1302,10 +1303,10 @@ "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, @@ -1421,10 +1422,10 @@ "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, @@ -2036,8 +2037,8 @@ power-domains = <&dispcc MDSS_GDSC>; - interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ACTIVE_ONLY - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "mdp0-mem", "cpu-cfg"; @@ -2053,7 +2054,7 @@ mdss_mdp: display-controller@ae01000 { compatible = "qcom,sar2130p-dpu"; reg = <0x0 0x0ae01000 0x0 0x8f000>, - <0x0 0x0aeb0000 0x0 0x2008>; + <0x0 0x0aeb0000 0x0 0x3000>; reg-names = "mdp", "vbif"; @@ -2143,16 +2144,20 @@ <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; @@ -2237,8 +2242,8 @@ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&mdss_dsi_opp_table>; @@ -2333,8 +2338,8 @@ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi1_phy 0>, - <&mdss_dsi1_phy 1>; + assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&mdss_dsi_opp_table>; @@ -2392,10 +2397,10 @@ <&rpmhcc RPMH_CXO_CLK_A>, <&gcc GCC_DISP_AHB_CLK>, <&sleep_clk>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi1_phy 0>, - <&mdss_dsi1_phy 1>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <0>, /* dp1 */ diff --git a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts index 672ac4c3afa3..ad342d8b7508 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts @@ -438,15 +438,11 @@ }; &mdss_dp { - data-lanes = <0 1>; - - vdda-1p2-supply = <&vreg_l3c_1p2>; - vdda-0p9-supply = <&vreg_l4a_0p8>; - status = "okay"; }; &mdss_dp_out { + data-lanes = <0 1>; remote-endpoint = <&ec_dp_in>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index 0146fb0036d4..19cf419cf531 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -323,15 +323,11 @@ }; }; }; +}; - ports { - port@1 { - endpoint { - remote-endpoint = <&panel0_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; +&mdss_dsi0_out { + remote-endpoint = <&panel0_in>; + data-lanes = <0 1 2 3>; }; &mdss_dsi0_phy { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi index ff8996b4de4e..4bea97e4246e 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi @@ -90,15 +90,11 @@ }; }; }; +}; - ports { - port@1 { - endpoint { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; +&mdss_dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; }; &sdhc_2 { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi index 17908c936520..6078308694ac 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi @@ -148,15 +148,11 @@ }; }; }; +}; - ports { - port@1 { - endpoint { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; +&mdss_dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; }; &pm6150_adc { diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 3afb69921be3..a0df10a97c7f 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2897,6 +2897,31 @@ #clock-cells = <1>; #phy-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_qmpphy_out: endpoint { }; + }; + + port@1 { + reg = <1>; + + usb_1_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_1_qmpphy_dp_in: endpoint { }; + }; + }; }; pmu@90b6300 { @@ -3070,6 +3095,26 @@ phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; maximum-speed = "super-speed"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; + }; + }; + }; }; }; @@ -3095,14 +3140,6 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; interconnect-names = "video-mem", "cpu-cfg"; - video-decoder { - compatible = "venus-decoder"; - }; - - video-encoder { - compatible = "venus-encoder"; - }; - venus_opp_table: opp-table { compatible = "operating-points-v2"; @@ -3392,8 +3429,10 @@ ports { #address-cells = <1>; #size-cells = <0>; + port@0 { reg = <0>; + dp_in: endpoint { remote-endpoint = <&dpu_intf0_out>; }; @@ -3401,6 +3440,7 @@ port@1 { reg = <1>; + mdss_dp_out: endpoint { }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi index 8b4239f13748..84c6d662b54f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi @@ -44,11 +44,6 @@ reg = <0x0 0x8ad00000 0x0 0x500000>; no-map; }; - - venus_mem: memory@8b200000 { - reg = <0x0 0x8b200000 0x0 0x500000>; - no-map; - }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index 2ba4ea60cb14..5c5e4f1dd221 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -621,15 +621,13 @@ ap_ec_spi: &spi10 { }; &usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { dr_mode = "host"; #address-cells = <1>; #size-cells = <0>; + status = "okay"; + /* 2.x hub on port 1 */ usb_hub_2_x: hub@1 { compatible = "usbbda,5411"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index b5fe7356be48..3103f94cd685 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -81,11 +81,9 @@ }; &usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { dr_mode = "otg"; + + status = "okay"; }; &usb_2_hsphy { diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 90e5b9ab5b84..ccd39a1baeda 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -520,11 +520,9 @@ }; &usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_hsphy { diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 64a2abd30100..4b04dea57ec8 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -28,6 +28,7 @@ #include <dt-bindings/soc/qcom,apr.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> #include <dt-bindings/sound/qcom,lpass.h> +#include <dt-bindings/sound/qcom,q6afe.h> #include <dt-bindings/sound/qcom,q6asm.h> #include <dt-bindings/thermal/thermal.h> @@ -620,12 +621,12 @@ cpu4_opp_2400mhz: opp-2400000000 { opp-hz = /bits/ 64 <2400000000>; - opp-peak-kBps = <8532000 48537600>; + opp-peak-kBps = <12787200 48537600>; }; cpu4_opp_2611mhz: opp-2611200000 { opp-hz = /bits/ 64 <2611200000>; - opp-peak-kBps = <8532000 48537600>; + opp-peak-kBps = <12787200 48537600>; }; }; @@ -685,22 +686,22 @@ cpu7_opp_2400mhz: opp-2400000000 { opp-hz = /bits/ 64 <2400000000>; - opp-peak-kBps = <8532000 48537600>; + opp-peak-kBps = <12787200 48537600>; }; cpu7_opp_2515mhz: opp-2515200000 { opp-hz = /bits/ 64 <2515200000>; - opp-peak-kBps = <8532000 48537600>; + opp-peak-kBps = <12787200 48537600>; }; cpu7_opp_2707mhz: opp-2707200000 { opp-hz = /bits/ 64 <2707200000>; - opp-peak-kBps = <8532000 48537600>; + opp-peak-kBps = <12787200 48537600>; }; cpu7_opp_3014mhz: opp-3014400000 { opp-hz = /bits/ 64 <3014400000>; - opp-peak-kBps = <8532000 48537600>; + opp-peak-kBps = <12787200 48537600>; }; }; @@ -2200,6 +2201,135 @@ qcom,smem-state-names = "wlan-smp2p-out"; }; + pcie0: pcie@1c00000 { + compatible = "qcom,pcie-sc7280"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>, + <0 0x01c03000 0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, + <&pcie0_phy>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; + clock-names = "pipe", + "pipe_mux", + "phy_pipe", + "ref", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ddrss_sf_tbu", + "aggre0", + "aggre1"; + + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + power-domains = <&gcc GCC_PCIE_0_GDSC>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_clkreq_n>; + dma-coherent; + + status = "disabled"; + + pcie0_port: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie0_phy: phy@1c06000 { + compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; + reg = <0 0x01c06000 0 0x1000>; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "refgen", + "pipe"; + + clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; + + #phy-cells = <0>; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + }; + pcie1: pcie@1c08000 { compatible = "qcom,pcie-sc7280"; reg = <0 0x01c08000 0 0x3000>, @@ -2240,10 +2370,10 @@ "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, @@ -2644,6 +2774,66 @@ status = "disabled"; }; + lpass_wsa_macro: codec@3240000 { + compatible = "qcom,sc7280-lpass-wsa-macro"; + reg = <0x0 0x03240000 0x0 0x1000>; + + clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, + <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, + <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_va_macro>; + clock-names = "mclk", + "npl", + "macro", + "dcodec", + "fsgen"; + + pinctrl-0 = <&lpass_wsa_swr_clk>, <&lpass_wsa_swr_data>; + pinctrl-names = "default"; + + #clock-cells = <0>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + + status = "disabled"; + }; + + swr2: soundwire@3250000 { + compatible = "qcom,soundwire-v1.6.0"; + reg = <0x0 0x03250000 0x0 0x2000>; + + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&lpass_wsa_macro>; + clock-names = "iface"; + + resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; + reset-names = "swr_audio_cgcr"; + + qcom,din-ports = <2>; + qcom,dout-ports = <6>; + + qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 + 0x1f 0x3f 0x0f 0x0f>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; + qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 + 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff>; + + #address-cells = <2>; + #size-cells = <0>; + #sound-dai-cells = <1>; + + status = "disabled"; + }; + lpass_audiocc: clock-controller@3300000 { compatible = "qcom,sc7280-lpassaudiocc"; reg = <0 0x03300000 0 0x30000>, @@ -2811,41 +3001,77 @@ lpass_dmic01_clk: dmic01-clk-state { pins = "gpio6"; function = "dmic1_clk"; + drive-strength = <8>; + bias-disable; }; lpass_dmic01_data: dmic01-data-state { pins = "gpio7"; function = "dmic1_data"; + drive-strength = <8>; + bias-pull-down; }; lpass_dmic23_clk: dmic23-clk-state { pins = "gpio8"; function = "dmic2_clk"; + drive-strength = <8>; + bias-disable; }; lpass_dmic23_data: dmic23-data-state { pins = "gpio9"; function = "dmic2_data"; + drive-strength = <8>; + bias-pull-down; }; lpass_rx_swr_clk: rx-swr-clk-state { pins = "gpio3"; function = "swr_rx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; }; lpass_rx_swr_data: rx-swr-data-state { pins = "gpio4", "gpio5"; function = "swr_rx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; }; lpass_tx_swr_clk: tx-swr-clk-state { pins = "gpio0"; function = "swr_tx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; }; lpass_tx_swr_data: tx-swr-data-state { pins = "gpio1", "gpio2", "gpio14"; function = "swr_tx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + + lpass_wsa_swr_clk: wsa-swr-clk-state { + pins = "gpio10"; + function = "wsa_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + lpass_wsa_swr_data: wsa-swr-data-state { + pins = "gpio11"; + function = "wsa_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; }; }; @@ -3711,14 +3937,10 @@ }; }; - usb_2: usb@8cf8800 { - compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; - reg = <0 0x08cf8800 0 0x400>; + usb_2: usb@8c00000 { + compatible = "qcom,sc7280-dwc3", "qcom,snps-dwc3"; + reg = <0 0x08c00000 0 0xfc100>; status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges; clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, <&gcc GCC_USB30_SEC_MASTER_CLK>, @@ -3735,11 +3957,13 @@ <&gcc GCC_USB30_SEC_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, <&pdc 12 IRQ_TYPE_EDGE_BOTH>, <&pdc 13 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "pwr_event", + interrupt-names = "dwc_usb3", + "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq"; @@ -3753,24 +3977,19 @@ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; interconnect-names = "usb-ddr", "apps-usb"; - usb_2_dwc3: usb@8c00000 { - compatible = "snps,dwc3"; - reg = <0 0x08c00000 0 0xe000>; - interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; - iommus = <&apps_smmu 0xa0 0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - phys = <&usb_2_hsphy>; - phy-names = "usb2-phy"; - maximum-speed = "high-speed"; - usb-role-switch; + iommus = <&apps_smmu 0xa0 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + phys = <&usb_2_hsphy>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + usb-role-switch; - port { - usb2_role_switch: endpoint { - remote-endpoint = <&eud_ep>; - }; + port { + usb2_role_switch: endpoint { + remote-endpoint = <&eud_ep>; }; }; }; @@ -3822,7 +4041,7 @@ status = "disabled"; - glink-edge { + remoteproc_adsp_glink: glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; @@ -3862,6 +4081,13 @@ compatible = "qcom,q6afe-clocks"; #clock-cells = <2>; }; + + q6usbdai: usbd { + compatible = "qcom,q6usb"; + iommus = <&apps_smmu 0x180f 0x0>; + #sound-dai-cells = <1>; + qcom,usb-audio-intr-idx = /bits/ 16 <2>; + }; }; q6asm: service@7 { @@ -4013,6 +4239,12 @@ opp-7 { opp-peak-kBps = <8532000>; }; + opp-8 { + opp-peak-kBps = <10944000>; + }; + opp-9 { + opp-peak-kBps = <12787200>; + }; }; }; @@ -4252,14 +4484,10 @@ }; }; - usb_1: usb@a6f8800 { - compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; + usb_1: usb@a600000 { + compatible = "qcom,sc7280-dwc3", "qcom,snps-dwc3"; + reg = <0 0x0a600000 0 0xfc100>; status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, @@ -4276,12 +4504,14 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event", + interrupt-names = "dwc_usb3", + "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", @@ -4298,37 +4528,33 @@ wakeup-source; - usb_1_dwc3: usb@a600000 { - compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xe000>; - interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; - iommus = <&apps_smmu 0xe0 0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,parkmode-disable-ss-quirk; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; - phy-names = "usb2-phy", "usb3-phy"; - maximum-speed = "super-speed"; + iommus = <&apps_smmu 0xe0 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,parkmode-disable-ss-quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + num-hc-interrupters = /bits/ 16 <3>; + phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", "usb3-phy"; + maximum-speed = "super-speed"; - ports { - #address-cells = <1>; - #size-cells = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; - port@0 { - reg = <0>; + port@0 { + reg = <0>; - usb_1_dwc3_hs: endpoint { - }; + usb_1_dwc3_hs: endpoint { }; + }; - port@1 { - reg = <1>; + port@1 { + reg = <1>; - usb_1_dwc3_ss: endpoint { - remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; - }; + usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; }; }; }; @@ -4724,6 +4950,8 @@ iommus = <&apps_smmu 0x900 0x402>; + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -4916,7 +5144,8 @@ reg = <0 0x0aea0000 0 0x200>, <0 0x0aea0200 0 0x200>, <0 0x0aea0400 0 0xc00>, - <0 0x0aea1000 0 0x400>; + <0 0x0aea1000 0 0x400>, + <0 0x0aea1400 0 0x400>; interrupt-parent = <&mdss>; interrupts = <14>; @@ -5285,6 +5514,11 @@ function = "mi2s1_ws"; }; + pcie0_clkreq_n: pcie0-clkreq-n-state { + pins = "gpio88"; + function = "pcie0_clkreqn"; + }; + pcie1_clkreq_n: pcie1-clkreq-n-state { pins = "gpio79"; function = "pcie1_clkreqn"; diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index 21c2d25a2945..08d0784d0cbb 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -436,8 +436,6 @@ }; &mdss_edp { - data-lanes = <0 1 2 3>; - pinctrl-0 = <&edp_hpd_active>; pinctrl-names = "default"; @@ -457,15 +455,11 @@ }; }; }; +}; - ports { - port@1 { - reg = <1>; - mdss_edp_out: endpoint { - remote-endpoint = <&auo_b140han06_in>; - }; - }; - }; +&mdss_edp_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&auo_b140han06_in>; }; &pcie3 { diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts index 7a4bd6955470..93de9fe918eb 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts @@ -531,8 +531,6 @@ }; &mdss_edp { - data-lanes = <0 1 2 3>; - pinctrl-names = "default"; pinctrl-0 = <&edp_hpd_active>; @@ -551,15 +549,11 @@ }; }; }; +}; - ports { - port@1 { - reg = <1>; - mdss_edp_out: endpoint { - remote-endpoint = <&auo_b133han05_in>; - }; - }; - }; +&mdss_edp_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&auo_b133han05_in>; }; &pcie1 { diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index f4f1d6a11960..85c2afcb417d 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -10,6 +10,7 @@ #include <dt-bindings/clock/qcom,gpucc-sm8150.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,sc8180x-camcc.h> +#include <dt-bindings/clock/qcom,videocc-sm8150.h> #include <dt-bindings/interconnect/qcom,icc.h> #include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/interconnect/qcom,sc8180x.h> @@ -1740,10 +1741,10 @@ "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, <&gcc GCC_PCIE_0_AUX_CLK>, @@ -1859,10 +1860,10 @@ "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_3_PIPE_CLK>, <&gcc GCC_PCIE_3_AUX_CLK>, @@ -1979,10 +1980,10 @@ "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_AUX_CLK>, @@ -2099,10 +2100,10 @@ "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, <&gcc GCC_PCIE_2_AUX_CLK>, @@ -2927,6 +2928,20 @@ }; }; + videocc: clock-controller@ab00000 { + compatible = "qcom,sc8180x-videocc", + "qcom,sm8150-videocc"; + reg = <0 0x0ab00000 0 0x10000>; + clocks = <&gcc GCC_VIDEO_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "bi_tcxo"; + power-domains = <&rpmhpd SC8180X_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + camcc: clock-controller@ad00000 { compatible = "qcom,sc8180x-camcc"; reg = <0 0x0ad00000 0 0x20000>; @@ -2940,7 +2955,7 @@ #power-domain-cells = <1>; }; - mdss: mdss@ae00000 { + mdss: display-subsystem@ae00000 { compatible = "qcom,sc8180x-mdss"; reg = <0 0x0ae00000 0 0x1000>; reg-names = "mdss"; @@ -2980,7 +2995,7 @@ status = "disabled"; - mdss_mdp: mdp@ae01000 { + mdss_mdp: display-controller@ae01000 { compatible = "qcom,sc8180x-dpu"; reg = <0 0x0ae01000 0 0x8f000>, <0 0x0aeb0000 0 0x3000>; @@ -3074,7 +3089,8 @@ }; mdss_dsi0: dsi@ae94000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sc8180x-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; reg-names = "dsi_ctrl"; @@ -3140,7 +3156,7 @@ }; }; - mdss_dsi0_phy: dsi-phy@ae94400 { + mdss_dsi0_phy: phy@ae94400 { compatible = "qcom,dsi-phy-7nm"; reg = <0 0x0ae94400 0 0x200>, <0 0x0ae94600 0 0x280>, @@ -3160,7 +3176,8 @@ }; mdss_dsi1: dsi@ae96000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sc8180x-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae96000 0 0x400>; reg-names = "dsi_ctrl"; @@ -3207,7 +3224,7 @@ }; }; - mdss_dsi1_phy: dsi-phy@ae96400 { + mdss_dsi1_phy: phy@ae96400 { compatible = "qcom,dsi-phy-7nm"; reg = <0 0x0ae96400 0 0x200>, <0 0x0ae96600 0 0x280>, @@ -3239,16 +3256,20 @@ <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; assigned-clock-parents = <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; phys = <&usb_prim_qmpphy QMP_USB43DP_DP_PHY>; @@ -3317,16 +3338,20 @@ <&dispcc DISP_CC_MDSS_DP_AUX1_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK1_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>; + <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; assigned-clock-parents = <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; phys = <&usb_sec_qmpphy QMP_USB43DP_DP_PHY>; @@ -3387,7 +3412,8 @@ reg = <0 0xae9a000 0 0x200>, <0 0xae9a200 0 0x200>, <0 0xae9a400 0 0x600>, - <0 0xae9aa00 0 0x400>; + <0 0xae9aa00 0 0x400>, + <0 0xae9b000 0 0x400>; interrupt-parent = <&mdss>; interrupts = <14>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, @@ -3423,6 +3449,13 @@ remote-endpoint = <&dpu_intf5_out>; }; }; + + port@1 { + reg = <1>; + + mdss_edp_out: endpoint { + }; + }; }; edp_opp_table: opp-table { @@ -3714,6 +3747,7 @@ intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; interrupt-controller; + #address-cells = <0>; #interrupt-cells = <3>; reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index 8e2c02497c05..490e970c54a2 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -495,6 +495,18 @@ status = "okay"; }; +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpi_dma2 { + status = "okay"; +}; + &gpu { status = "okay"; @@ -548,15 +560,10 @@ }; }; }; +}; - ports { - port@1 { - reg = <1>; - mdss0_dp3_out: endpoint { - remote-endpoint = <&edp_panel_in>; - }; - }; - }; +&mdss0_dp3_out { + remote-endpoint = <&edp_panel_in>; }; &mdss0_dp3_phy { diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts index 1667c7157057..0374251d3329 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts @@ -586,6 +586,18 @@ status = "okay"; }; +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpi_dma2 { + status = "okay"; +}; + &gpu { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index cefecb7a23cf..637430719e6d 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -708,6 +708,18 @@ status = "okay"; }; +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpi_dma2 { + status = "okay"; +}; + &gpu { status = "okay"; @@ -726,7 +738,7 @@ }; &mdss0_dp0_out { - data-lanes = <0 1>; + data-lanes = <0 1 2 3>; remote-endpoint = <&usb_0_qmpphy_dp_in>; }; @@ -735,7 +747,7 @@ }; &mdss0_dp1_out { - data-lanes = <0 1>; + data-lanes = <0 1 2 3>; remote-endpoint = <&usb_1_qmpphy_dp_in>; }; @@ -761,15 +773,10 @@ }; }; }; +}; - ports { - port@1 { - reg = <1>; - mdss0_dp3_out: endpoint { - remote-endpoint = <&edp_panel_in>; - }; - }; - }; +&mdss0_dp3_out { + remote-endpoint = <&edp_panel_in>; }; &mdss0_dp3_phy { @@ -1360,6 +1367,7 @@ vdda-phy-supply = <&vreg_l9d>; vdda-pll-supply = <&vreg_l4d>; + mode-switch; orientation-switch; status = "okay"; @@ -1397,6 +1405,7 @@ vdda-phy-supply = <&vreg_l4b>; vdda-pll-supply = <&vreg_l3b>; + mode-switch; orientation-switch; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts index d00889fa6f0b..aeed3ef152eb 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts @@ -448,6 +448,18 @@ status = "okay"; }; +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpi_dma2 { + status = "okay"; +}; + &gpu { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts index 812251324002..a40dccd70dfd 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts @@ -63,7 +63,7 @@ port { dp1_connector_in: endpoint { - remote-endpoint = <&mdss0_dp2_phy_out>; + remote-endpoint = <&mdss0_dp2_out>; }; }; }; @@ -565,6 +565,18 @@ status = "okay"; }; +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpi_dma2 { + status = "okay"; +}; + &gpu { status = "okay"; @@ -602,15 +614,10 @@ data-lanes = <0 1 2 3>; status = "okay"; +}; - ports { - port@1 { - reg = <1>; - mdss0_dp2_phy_out: endpoint { - remote-endpoint = <&dp1_connector_in>; - }; - }; - }; +&mdss0_dp2_out { + remote-endpoint = <&dp1_connector_in>; }; &mdss0_dp2_phy { diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 87555a119d94..279e5e6beae2 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -10,6 +10,7 @@ #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,sc8280xp-camcc.h> #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> +#include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/interconnect/qcom,sc8280xp.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -912,6 +913,32 @@ }; }; + gpi_dma2: dma-controller@800000 { + compatible = "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0 0x00800000 0 0x60000>; + + interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; + + dma-channels = <12>; + dma-channel-mask = <0xfff>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0xb6 0x0>; + + status = "disabled"; + }; + qup2: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x008c0000 0 0x2000>; @@ -939,6 +966,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, + <&gpi_dma2 1 6 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -955,6 +988,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -971,6 +1010,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -987,6 +1032,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1017,6 +1068,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1033,6 +1090,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1067,6 +1130,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1083,6 +1152,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1099,6 +1174,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, + <&gpi_dma2 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1115,6 +1196,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1131,6 +1218,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, + <&gpi_dma2 1 5 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1147,6 +1240,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, + <&gpi_dma2 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1163,6 +1262,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, + <&gpi_dma2 1 6 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1179,6 +1284,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, + <&gpi_dma2 1 5 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1195,6 +1306,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, + <&gpi_dma2 1 7 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1211,10 +1328,43 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, + <&gpi_dma2 1 7 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; }; + gpi_dma0: dma-controller@900000 { + compatible = "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0 0x00900000 0 0x60000>; + + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; + + dma-channels = <13>; + dma-channel-mask = <0x1fff>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0x576 0x0>; + + status = "disabled"; + }; + qup0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x009c0000 0 0x6000>; @@ -1242,6 +1392,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, + <&gpi_dma0 1 7 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1258,6 +1414,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1274,6 +1436,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1290,6 +1458,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1306,6 +1480,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1322,6 +1502,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1352,6 +1538,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1368,6 +1560,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1384,6 +1582,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1400,6 +1604,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1416,6 +1626,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1432,6 +1648,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1448,6 +1670,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1464,6 +1692,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1480,6 +1714,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, + <&gpi_dma0 1 6 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1496,10 +1736,42 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, + <&gpi_dma0 1 7 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; }; + gpi_dma1: dma-controller@a00000 { + compatible = "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0 0x00a00000 0 0x60000>; + + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; + + dma-channels = <12>; + dma-channel-mask = <0xfff>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0x96 0x0>; + + status = "disabled"; + }; + qup1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x00ac0000 0 0x6000>; @@ -1527,6 +1799,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, + <&gpi_dma1 1 7 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1543,6 +1821,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1559,6 +1843,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1575,6 +1865,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1591,6 +1887,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1607,6 +1909,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1623,6 +1931,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1639,6 +1953,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1655,6 +1975,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1671,6 +1997,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1687,6 +2019,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1703,6 +2041,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1719,6 +2063,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1735,6 +2085,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1751,6 +2107,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, + <&gpi_dma1 1 6 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1767,6 +2129,12 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, + <&gpi_dma1 1 7 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; }; @@ -1809,10 +2177,10 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_4_AUX_CLK>, <&gcc GCC_PCIE_4_CFG_AHB_CLK>, @@ -1922,10 +2290,10 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, @@ -2033,10 +2401,10 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, @@ -2147,10 +2515,10 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, @@ -2258,10 +2626,10 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, @@ -4338,15 +4706,19 @@ <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; @@ -4417,14 +4789,18 @@ <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, - <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; + <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", - "ctrl_link_iface", "stream_pixel"; + "ctrl_link_iface", "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, - <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; + <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, + <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; @@ -4494,10 +4870,12 @@ <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, - <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", - "ctrl_link_iface", "stream_pixel"; + "ctrl_link_iface", "stream_pixel", + "stream_1_pixel"; interrupt-parent = <&mdss0>; interrupts = <14>; phys = <&mdss0_dp2_phy>; @@ -4505,8 +4883,11 @@ power-domains = <&rpmhpd SC8280XP_MMCX>; assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, - <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; - assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>; + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&mdss0_dp2_phy 0>, + <&mdss0_dp2_phy 1>, + <&mdss0_dp2_phy 1>; operating-points-v2 = <&mdss0_dp2_opp_table>; #sound-dai-cells = <0>; @@ -4526,6 +4907,9 @@ port@1 { reg = <1>; + + mdss0_dp2_out: endpoint { + }; }; }; @@ -4598,6 +4982,9 @@ port@1 { reg = <1>; + + mdss0_dp3_out: endpoint { + }; }; }; @@ -5669,10 +6056,12 @@ <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", - "ctrl_link_iface", "stream_pixel"; + "ctrl_link_iface", "stream_pixel", + "stream_1_pixel"; interrupt-parent = <&mdss1>; interrupts = <12>; phys = <&mdss1_dp0_phy>; @@ -5680,8 +6069,11 @@ power-domains = <&rpmhpd SC8280XP_MMCX>; assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; - assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>; + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&mdss1_dp0_phy 0>, + <&mdss1_dp0_phy 1>, + <&mdss1_dp0_phy 1>; operating-points-v2 = <&mdss1_dp0_opp_table>; #sound-dai-cells = <0>; @@ -5701,6 +6093,9 @@ port@1 { reg = <1>; + + mdss1_dp0_out: endpoint { + }; }; }; @@ -5741,10 +6136,12 @@ <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, - <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", - "ctrl_link_iface", "stream_pixel"; + "ctrl_link_iface", "stream_pixel", + "stream_1_pixel"; interrupt-parent = <&mdss1>; interrupts = <13>; phys = <&mdss1_dp1_phy>; @@ -5752,8 +6149,11 @@ power-domains = <&rpmhpd SC8280XP_MMCX>; assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, - <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; - assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>; + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&mdss1_dp1_phy 0>, + <&mdss1_dp1_phy 1>, + <&mdss1_dp1_phy 1>; operating-points-v2 = <&mdss1_dp1_opp_table>; #sound-dai-cells = <0>; @@ -5773,6 +6173,9 @@ port@1 { reg = <1>; + + mdss1_dp1_out: endpoint { + }; }; }; @@ -5813,10 +6216,12 @@ <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, - <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", - "ctrl_link_iface", "stream_pixel"; + "ctrl_link_iface", "stream_pixel", + "stream_1_pixel"; interrupt-parent = <&mdss1>; interrupts = <14>; phys = <&mdss1_dp2_phy>; @@ -5824,8 +6229,11 @@ power-domains = <&rpmhpd SC8280XP_MMCX>; assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, - <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; - assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>; + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&mdss1_dp2_phy 0>, + <&mdss1_dp2_phy 1>, + <&mdss1_dp2_phy 1>; operating-points-v2 = <&mdss1_dp2_opp_table>; #sound-dai-cells = <0>; @@ -5845,6 +6253,9 @@ port@1 { reg = <1>; + + mdss1_dp2_out: endpoint { + }; }; }; @@ -5917,6 +6328,9 @@ port@1 { reg = <1>; + + mdss1_dp3_out: endpoint { + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts index 31ed26c31e6e..55a45b528bd3 100644 --- a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts +++ b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts @@ -36,6 +36,14 @@ }; }; + /* Dummy regulator until PMI632 has LCDB VSP/VSN support */ + lcdb_dummy: regulator-lcdb-dummy { + compatible = "regulator-fixed"; + regulator-name = "lcdb_dummy"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -44,6 +52,14 @@ }; }; +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/msm8953/fairphone/fp3/a506_zap.mbn"; +}; + &hsusb_phy { vdd-supply = <&pm8953_l3>; vdda-pll-supply = <&pm8953_l7>; @@ -87,6 +103,45 @@ status = "okay"; }; +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&pm8953_s3>; + status = "okay"; + + panel@0 { + compatible = "djn,98-03057-6598b-i"; + reg = <0>; + + reset-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>; + + iovcc-supply = <&pm8953_l6>; + vsn-supply = <&lcdb_dummy>; + vsp-supply = <&lcdb_dummy>; + + pinctrl-0 = <&mdss_te_default>; + pinctrl-names = "default"; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&panel_in>; +}; + +&mdss_dsi0_phy { + vcca-supply = <&pm8953_l3>; + status = "okay"; +}; + &mpss { firmware-name = "qcom/msm8953/fairphone/fp3/mba.mbn", "qcom/msm8953/fairphone/fp3/modem.mbn"; @@ -292,6 +347,13 @@ * 135-138: fingerprint reader (SPI) */ gpio-reserved-ranges = <0 4>, <135 4>; + + mdss_te_default: mdss-te-default-state { + pins = "gpio24"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; }; &uart_0 { diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts index 74b5d9c68eb6..d01422844fbf 100644 --- a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts +++ b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts @@ -33,6 +33,14 @@ aliases { }; + battery: battery { + compatible = "simple-battery"; + + voltage-min-design-microvolt = <3312000>; + voltage-max-design-microvolt = <4400000>; + charge-full-design-microamp-hours = <3000000>; + }; + chosen { stdout-path = "serial0:115200n8"; @@ -478,6 +486,15 @@ status = "okay"; }; +&pm660_charger { + monitored-battery = <&battery>; + status = "okay"; +}; + +&pm660_rradc { + status = "okay"; +}; + &pm660l_flash { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dts b/arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dts deleted file mode 100644 index bd7c25bb8d35..000000000000 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dts +++ /dev/null @@ -1,238 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Cheza board device tree source - * - * Copyright 2018 Google LLC. - */ - -/dts-v1/; - -#include "sdm845-cheza.dtsi" - -/ { - model = "Google Cheza (rev1)"; - compatible = "google,cheza-rev1", "qcom,sdm845"; - - /* - * FIXED REGULATORS (not in sdm845-cheza.dtsi) - parents above children - */ - - /* - * NOTE: Technically pp3500_a is not the exact same signal as - * pp3500_a_vbob (there's a load switch between them and the EC can - * control pp3500_a via "en_pp3300_a"), but from the AP's point of - * view they are the same. - */ - pp3500_a: - pp3500_a_vbob: pp3500-a-vbob-regulator { - compatible = "regulator-fixed"; - regulator-name = "vreg_bob"; - - /* - * Comes on automatically when pp5000_ldo comes on, which - * comes on automatically when ppvar_sys comes on - */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3500000>; - regulator-max-microvolt = <3500000>; - - vin-supply = <&ppvar_sys>; - }; - - pp3300_dx_edp: pp3300-dx-edp-regulator { - /* Yes, it's really 3.5 despite the name of the signal */ - regulator-min-microvolt = <3500000>; - regulator-max-microvolt = <3500000>; - - vin-supply = <&pp3500_a>; - }; -}; - -/* FIXED REGULATOR OVERRIDES (modifications to sdm845-cheza.dtsi) */ - -/* - * L19 and L28 technically go to 3.3V, but most boards have old AOP firmware - * that limits them to 3.0, and trying to run at 3.3V with that old firmware - * prevents the system from booting. - */ -&src_pp3000_l19a { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; -}; - -&src_pp3300_l22a { - /delete-property/regulator-boot-on; - /delete-property/regulator-always-on; -}; - -&src_pp3300_l28a { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; -}; - -&src_vreg_bob { - regulator-min-microvolt = <3500000>; - regulator-max-microvolt = <3500000>; - vin-supply = <&pp3500_a_vbob>; -}; - -/* - * NON-REGULATOR OVERRIDES - * (modifications to sdm845-cheza.dtsi) - alphabetized by dtsi label - */ - -/* PINCTRL - board-specific pinctrl */ - -&tlmm { - gpio-line-names = "AP_SPI_FP_MISO", - "AP_SPI_FP_MOSI", - "AP_SPI_FP_CLK", - "AP_SPI_FP_CS_L", - "UART_AP_TX_DBG_RX", - "UART_DBG_TX_AP_RX", - "", - "FP_RST_L", - "FCAM_EN", - "", - "EDP_BRIJ_IRQ", - "EC_IN_RW_ODL", - "", - "RCAM_MCLK", - "FCAM_MCLK", - "", - "RCAM_EN", - "CCI0_SDA", - "CCI0_SCL", - "CCI1_SDA", - "CCI1_SCL", - "FCAM_RST_L", - "", - "PEN_RST_L", - "PEN_IRQ_L", - "", - "RCAM_VSYNC", - "ESIM_MISO", - "ESIM_MOSI", - "ESIM_CLK", - "ESIM_CS_L", - "AP_PEN_1V8_SDA", - "AP_PEN_1V8_SCL", - "AP_TS_I2C_SDA", - "AP_TS_I2C_SCL", - "RCAM_RST_L", - "", - "AP_EDP_BKLTEN", - "AP_BRD_ID1", - "BOOT_CONFIG_4", - "AMP_IRQ_L", - "EDP_BRIJ_I2C_SDA", - "EDP_BRIJ_I2C_SCL", - "EN_PP3300_DX_EDP", - "SD_CD_ODL", - "BT_UART_RTS", - "BT_UART_CTS", - "BT_UART_RXD", - "BT_UART_TXD", - "AMP_I2C_SDA", - "AMP_I2C_SCL", - "AP_BRD_ID3", - "", - "AP_EC_SPI_CLK", - "AP_EC_SPI_CS_L", - "AP_EC_SPI_MISO", - "AP_EC_SPI_MOSI", - "FORCED_USB_BOOT", - "AMP_BCLK", - "AMP_LRCLK", - "AMP_DOUT", - "AMP_DIN", - "AP_BRD_ID2", - "PEN_PDCT_L", - "HP_MCLK", - "HP_BCLK", - "HP_LRCLK", - "HP_DOUT", - "HP_DIN", - "", - "", - "", - "", - "BT_SLIMBUS_DATA", - "BT_SLIMBUS_CLK", - "AMP_RESET_L", - "", - "FCAM_VSYNC", - "", - "AP_SKU_ID1", - "EC_WOV_BCLK", - "EC_WOV_LRCLK", - "EC_WOV_DOUT", - "", - "", - "AP_H1_SPI_MISO", - "AP_H1_SPI_MOSI", - "AP_H1_SPI_CLK", - "AP_H1_SPI_CS_L", - "", - "AP_SPI_CS0_L", - "AP_SPI_MOSI", - "AP_SPI_MISO", - "", - "", - "AP_SPI_CLK", - "", - "RFFE6_CLK", - "RFFE6_DATA", - "BOOT_CONFIG_1", - "BOOT_CONFIG_2", - "BOOT_CONFIG_0", - "EDP_BRIJ_EN", - "", - "USB_HS_TX_EN", - "UIM2_DATA", - "UIM2_CLK", - "UIM2_RST", - "UIM2_PRESENT", - "UIM1_DATA", - "UIM1_CLK", - "UIM1_RST", - "", - "AP_SKU_ID2", - "SDM_GRFC_8", - "SDM_GRFC_9", - "AP_RST_REQ", - "HP_IRQ", - "TS_RESET_L", - "PEN_EJECT_ODL", - "HUB_RST_L", - "FP_TO_AP_IRQ", - "AP_EC_INT_L", - "", - "", - "TS_INT_L", - "AP_SUSPEND_L", - "SDM_GRFC_3", - "", - "H1_AP_INT_ODL", - "QLINK_REQ", - "QLINK_EN", - "SDM_GRFC_2", - "BOOT_CONFIG_3", - "WMSS_RESET_L", - "SDM_GRFC_0", - "SDM_GRFC_1", - "RFFE3_DATA", - "RFFE3_CLK", - "RFFE4_DATA", - "RFFE4_CLK", - "RFFE5_DATA", - "RFFE5_CLK", - "GNSS_EN", - "WCI2_LTE_COEX_RXD", - "WCI2_LTE_COEX_TXD", - "AP_RAM_ID1", - "AP_RAM_ID2", - "RFFE1_DATA", - "RFFE1_CLK"; -}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dts b/arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dts deleted file mode 100644 index 2b7230594ecb..000000000000 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dts +++ /dev/null @@ -1,238 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Cheza board device tree source - * - * Copyright 2018 Google LLC. - */ - -/dts-v1/; - -#include "sdm845-cheza.dtsi" - -/ { - model = "Google Cheza (rev2)"; - compatible = "google,cheza-rev2", "qcom,sdm845"; - - /* - * FIXED REGULATORS (not in sdm845-cheza.dtsi) - parents above children - */ - - /* - * NOTE: Technically pp3500_a is not the exact same signal as - * pp3500_a_vbob (there's a load switch between them and the EC can - * control pp3500_a via "en_pp3300_a"), but from the AP's point of - * view they are the same. - */ - pp3500_a: - pp3500_a_vbob: pp3500-a-vbob-regulator { - compatible = "regulator-fixed"; - regulator-name = "vreg_bob"; - - /* - * Comes on automatically when pp5000_ldo comes on, which - * comes on automatically when ppvar_sys comes on - */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3500000>; - regulator-max-microvolt = <3500000>; - - vin-supply = <&ppvar_sys>; - }; - - pp3300_dx_edp: pp3300-dx-edp-regulator { - /* Yes, it's really 3.5 despite the name of the signal */ - regulator-min-microvolt = <3500000>; - regulator-max-microvolt = <3500000>; - - vin-supply = <&pp3500_a>; - }; -}; - -/* FIXED REGULATOR OVERRIDES (modifications to sdm845-cheza.dtsi) */ - -/* - * L19 and L28 technically go to 3.3V, but most boards have old AOP firmware - * that limits them to 3.0, and trying to run at 3.3V with that old firmware - * prevents the system from booting. - */ -&src_pp3000_l19a { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; -}; - -&src_pp3300_l22a { - /delete-property/regulator-boot-on; - /delete-property/regulator-always-on; -}; - -&src_pp3300_l28a { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; -}; - -&src_vreg_bob { - regulator-min-microvolt = <3500000>; - regulator-max-microvolt = <3500000>; - vin-supply = <&pp3500_a_vbob>; -}; - -/* - * NON-REGULATOR OVERRIDES - * (modifications to sdm845-cheza.dtsi) - alphabetized by dtsi label - */ - -/* PINCTRL - board-specific pinctrl */ - -&tlmm { - gpio-line-names = "AP_SPI_FP_MISO", - "AP_SPI_FP_MOSI", - "AP_SPI_FP_CLK", - "AP_SPI_FP_CS_L", - "UART_AP_TX_DBG_RX", - "UART_DBG_TX_AP_RX", - "BRIJ_SUSPEND", - "FP_RST_L", - "FCAM_EN", - "", - "EDP_BRIJ_IRQ", - "EC_IN_RW_ODL", - "", - "RCAM_MCLK", - "FCAM_MCLK", - "", - "RCAM_EN", - "CCI0_SDA", - "CCI0_SCL", - "CCI1_SDA", - "CCI1_SCL", - "FCAM_RST_L", - "FPMCU_BOOT0", - "PEN_RST_L", - "PEN_IRQ_L", - "FPMCU_SEL_OD", - "RCAM_VSYNC", - "ESIM_MISO", - "ESIM_MOSI", - "ESIM_CLK", - "ESIM_CS_L", - "AP_PEN_1V8_SDA", - "AP_PEN_1V8_SCL", - "AP_TS_I2C_SDA", - "AP_TS_I2C_SCL", - "RCAM_RST_L", - "", - "AP_EDP_BKLTEN", - "AP_BRD_ID1", - "BOOT_CONFIG_4", - "AMP_IRQ_L", - "EDP_BRIJ_I2C_SDA", - "EDP_BRIJ_I2C_SCL", - "EN_PP3300_DX_EDP", - "SD_CD_ODL", - "BT_UART_RTS", - "BT_UART_CTS", - "BT_UART_RXD", - "BT_UART_TXD", - "AMP_I2C_SDA", - "AMP_I2C_SCL", - "AP_BRD_ID3", - "", - "AP_EC_SPI_CLK", - "AP_EC_SPI_CS_L", - "AP_EC_SPI_MISO", - "AP_EC_SPI_MOSI", - "FORCED_USB_BOOT", - "AMP_BCLK", - "AMP_LRCLK", - "AMP_DOUT", - "AMP_DIN", - "AP_BRD_ID2", - "PEN_PDCT_L", - "HP_MCLK", - "HP_BCLK", - "HP_LRCLK", - "HP_DOUT", - "HP_DIN", - "", - "", - "", - "", - "BT_SLIMBUS_DATA", - "BT_SLIMBUS_CLK", - "AMP_RESET_L", - "", - "FCAM_VSYNC", - "", - "AP_SKU_ID1", - "EC_WOV_BCLK", - "EC_WOV_LRCLK", - "EC_WOV_DOUT", - "", - "", - "AP_H1_SPI_MISO", - "AP_H1_SPI_MOSI", - "AP_H1_SPI_CLK", - "AP_H1_SPI_CS_L", - "", - "AP_SPI_CS0_L", - "AP_SPI_MOSI", - "AP_SPI_MISO", - "", - "", - "AP_SPI_CLK", - "", - "RFFE6_CLK", - "RFFE6_DATA", - "BOOT_CONFIG_1", - "BOOT_CONFIG_2", - "BOOT_CONFIG_0", - "EDP_BRIJ_EN", - "", - "USB_HS_TX_EN", - "UIM2_DATA", - "UIM2_CLK", - "UIM2_RST", - "UIM2_PRESENT", - "UIM1_DATA", - "UIM1_CLK", - "UIM1_RST", - "", - "AP_SKU_ID2", - "SDM_GRFC_8", - "SDM_GRFC_9", - "AP_RST_REQ", - "HP_IRQ", - "TS_RESET_L", - "PEN_EJECT_ODL", - "HUB_RST_L", - "FP_TO_AP_IRQ", - "AP_EC_INT_L", - "", - "", - "TS_INT_L", - "AP_SUSPEND_L", - "SDM_GRFC_3", - "", - "H1_AP_INT_ODL", - "QLINK_REQ", - "QLINK_EN", - "SDM_GRFC_2", - "BOOT_CONFIG_3", - "WMSS_RESET_L", - "SDM_GRFC_0", - "SDM_GRFC_1", - "RFFE3_DATA", - "RFFE3_CLK", - "RFFE4_DATA", - "RFFE4_CLK", - "RFFE5_DATA", - "RFFE5_CLK", - "GNSS_EN", - "WCI2_LTE_COEX_RXD", - "WCI2_LTE_COEX_TXD", - "AP_RAM_ID1", - "AP_RAM_ID2", - "RFFE1_DATA", - "RFFE1_CLK"; -}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dts b/arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dts deleted file mode 100644 index 1ba67be08f81..000000000000 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dts +++ /dev/null @@ -1,174 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Cheza board device tree source - * - * Copyright 2018 Google LLC. - */ - -/dts-v1/; - -#include "sdm845-cheza.dtsi" - -/ { - model = "Google Cheza (rev3+)"; - compatible = "google,cheza", "qcom,sdm845"; -}; - -/* PINCTRL - board-specific pinctrl */ - -&tlmm { - gpio-line-names = "AP_SPI_FP_MISO", - "AP_SPI_FP_MOSI", - "AP_SPI_FP_CLK", - "AP_SPI_FP_CS_L", - "UART_AP_TX_DBG_RX", - "UART_DBG_TX_AP_RX", - "BRIJ_SUSPEND", - "FP_RST_L", - "FCAM_EN", - "", - "EDP_BRIJ_IRQ", - "EC_IN_RW_ODL", - "", - "RCAM_MCLK", - "FCAM_MCLK", - "", - "RCAM_EN", - "CCI0_SDA", - "CCI0_SCL", - "CCI1_SDA", - "CCI1_SCL", - "FCAM_RST_L", - "FPMCU_BOOT0", - "PEN_RST_L", - "PEN_IRQ_L", - "FPMCU_SEL_OD", - "RCAM_VSYNC", - "ESIM_MISO", - "ESIM_MOSI", - "ESIM_CLK", - "ESIM_CS_L", - "AP_PEN_1V8_SDA", - "AP_PEN_1V8_SCL", - "AP_TS_I2C_SDA", - "AP_TS_I2C_SCL", - "RCAM_RST_L", - "", - "AP_EDP_BKLTEN", - "AP_BRD_ID0", - "BOOT_CONFIG_4", - "AMP_IRQ_L", - "EDP_BRIJ_I2C_SDA", - "EDP_BRIJ_I2C_SCL", - "EN_PP3300_DX_EDP", - "SD_CD_ODL", - "BT_UART_RTS", - "BT_UART_CTS", - "BT_UART_RXD", - "BT_UART_TXD", - "AMP_I2C_SDA", - "AMP_I2C_SCL", - "AP_BRD_ID2", - "", - "AP_EC_SPI_CLK", - "AP_EC_SPI_CS_L", - "AP_EC_SPI_MISO", - "AP_EC_SPI_MOSI", - "FORCED_USB_BOOT", - "AMP_BCLK", - "AMP_LRCLK", - "AMP_DOUT", - "AMP_DIN", - "AP_BRD_ID1", - "PEN_PDCT_L", - "HP_MCLK", - "HP_BCLK", - "HP_LRCLK", - "HP_DOUT", - "HP_DIN", - "", - "", - "", - "", - "BT_SLIMBUS_DATA", - "BT_SLIMBUS_CLK", - "AMP_RESET_L", - "", - "FCAM_VSYNC", - "", - "AP_SKU_ID0", - "EC_WOV_BCLK", - "EC_WOV_LRCLK", - "EC_WOV_DOUT", - "", - "", - "AP_H1_SPI_MISO", - "AP_H1_SPI_MOSI", - "AP_H1_SPI_CLK", - "AP_H1_SPI_CS_L", - "", - "AP_SPI_CS0_L", - "AP_SPI_MOSI", - "AP_SPI_MISO", - "", - "", - "AP_SPI_CLK", - "", - "RFFE6_CLK", - "RFFE6_DATA", - "BOOT_CONFIG_1", - "BOOT_CONFIG_2", - "BOOT_CONFIG_0", - "EDP_BRIJ_EN", - "", - "USB_HS_TX_EN", - "UIM2_DATA", - "UIM2_CLK", - "UIM2_RST", - "UIM2_PRESENT", - "UIM1_DATA", - "UIM1_CLK", - "UIM1_RST", - "", - "AP_SKU_ID1", - "SDM_GRFC_8", - "SDM_GRFC_9", - "AP_RST_REQ", - "HP_IRQ", - "TS_RESET_L", - "PEN_EJECT_ODL", - "HUB_RST_L", - "FP_TO_AP_IRQ", - "AP_EC_INT_L", - "", - "", - "TS_INT_L", - "AP_SUSPEND_L", - "SDM_GRFC_3", - /* - * AP_FLASH_WP_L is crossystem ABI. Rev3 schematics - * call it BIOS_FLASH_WP_R_L. - */ - "AP_FLASH_WP_L", - "H1_AP_INT_ODL", - "QLINK_REQ", - "QLINK_EN", - "SDM_GRFC_2", - "BOOT_CONFIG_3", - "WMSS_RESET_L", - "SDM_GRFC_0", - "SDM_GRFC_1", - "RFFE3_DATA", - "RFFE3_CLK", - "RFFE4_DATA", - "RFFE4_CLK", - "RFFE5_DATA", - "RFFE5_CLK", - "GNSS_EN", - "WCI2_LTE_COEX_RXD", - "WCI2_LTE_COEX_TXD", - "AP_RAM_ID0", - "AP_RAM_ID1", - "RFFE1_DATA", - "RFFE1_CLK"; -}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi deleted file mode 100644 index b7e514f81f92..000000000000 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ /dev/null @@ -1,1330 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Cheza device tree source (common between revisions) - * - * Copyright 2018 Google LLC. - */ - -#include <dt-bindings/input/input.h> -#include <dt-bindings/regulator/qcom,rpmh-regulator.h> -#include "sdm845.dtsi" - -/* PMICs depend on spmi_bus label and so must come after SoC */ -#include "pm8005.dtsi" -#include "pm8998.dtsi" - -/ { - aliases { - bluetooth0 = &bluetooth; - serial1 = &uart6; - serial0 = &uart9; - wifi0 = &wifi; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&cros_ec_pwm 0>; - enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; - power-supply = <&ppvar_sys>; - pinctrl-names = "default"; - pinctrl-0 = <&ap_edp_bklten>; - }; - - /* FIXED REGULATORS - parents above children */ - - /* This is the top level supply and variable voltage */ - ppvar_sys: ppvar-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "ppvar_sys"; - regulator-always-on; - regulator-boot-on; - }; - - /* This divides ppvar_sys by 2, so voltage is variable */ - src_vph_pwr: src-vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "src_vph_pwr"; - - /* EC turns on with switchcap_on_l; always on for AP */ - regulator-always-on; - regulator-boot-on; - - vin-supply = <&ppvar_sys>; - }; - - pp5000_a: pp5000-a-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp5000_a"; - - /* EC turns on with en_pp5000_a; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - vin-supply = <&ppvar_sys>; - }; - - src_vreg_bob: src-vreg-bob-regulator { - compatible = "regulator-fixed"; - regulator-name = "src_vreg_bob"; - - /* EC turns on with vbob_en; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3600000>; - regulator-max-microvolt = <3600000>; - - vin-supply = <&ppvar_sys>; - }; - - pp3300_dx_edp: pp3300-dx-edp-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp3300_dx_edp"; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 43 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&en_pp3300_dx_edp>; - }; - - /* - * Apparently RPMh does not provide support for PM8998 S4 because it - * is always-on; model it as a fixed regulator. - */ - src_pp1800_s4a: pm8998-smps4 { - compatible = "regulator-fixed"; - regulator-name = "src_pp1800_s4a"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - - vin-supply = <&src_vph_pwr>; - }; - - /* BOARD-SPECIFIC TOP LEVEL NODES */ - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pen_eject_odl>; - - switch-pen-insert { - label = "Pen Insert"; - /* Insert = low, eject = high */ - gpios = <&tlmm 119 GPIO_ACTIVE_LOW>; - linux,code = <SW_PEN_INSERTED>; - linux,input-type = <EV_SW>; - wakeup-source; - }; - }; - - panel: panel { - compatible = "innolux,p120zdg-bf1"; - power-supply = <&pp3300_dx_edp>; - backlight = <&backlight>; - no-hpd; - - panel_in: port { - panel_in_edp: endpoint { - remote-endpoint = <&sn65dsi86_out>; - }; - }; - }; -}; - -&cpufreq_hw { - /delete-property/ interrupts-extended; /* reference to lmh_cluster[01] */ -}; - -&psci { - /delete-node/ power-domain-cpu0; - /delete-node/ power-domain-cpu1; - /delete-node/ power-domain-cpu2; - /delete-node/ power-domain-cpu3; - /delete-node/ power-domain-cpu4; - /delete-node/ power-domain-cpu5; - /delete-node/ power-domain-cpu6; - /delete-node/ power-domain-cpu7; - /delete-node/ power-domain-cluster; -}; - -&cpus { - /delete-node/ domain-idle-states; -}; - -&cpu_idle_states { - little_cpu_sleep_0: cpu-sleep-0-0 { - compatible = "arm,idle-state"; - idle-state-name = "little-power-down"; - arm,psci-suspend-param = <0x40000003>; - entry-latency-us = <350>; - exit-latency-us = <461>; - min-residency-us = <1890>; - local-timer-stop; - }; - - little_cpu_sleep_1: cpu-sleep-0-1 { - compatible = "arm,idle-state"; - idle-state-name = "little-rail-power-down"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <360>; - exit-latency-us = <531>; - min-residency-us = <3934>; - local-timer-stop; - }; - - big_cpu_sleep_0: cpu-sleep-1-0 { - compatible = "arm,idle-state"; - idle-state-name = "big-power-down"; - arm,psci-suspend-param = <0x40000003>; - entry-latency-us = <264>; - exit-latency-us = <621>; - min-residency-us = <952>; - local-timer-stop; - }; - - big_cpu_sleep_1: cpu-sleep-1-1 { - compatible = "arm,idle-state"; - idle-state-name = "big-rail-power-down"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <702>; - exit-latency-us = <1061>; - min-residency-us = <4488>; - local-timer-stop; - }; - - cluster_sleep_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - idle-state-name = "cluster-power-down"; - arm,psci-suspend-param = <0x400000F4>; - entry-latency-us = <3263>; - exit-latency-us = <6562>; - min-residency-us = <9987>; - local-timer-stop; - }; -}; - -&cpu0 { - /delete-property/ power-domains; - /delete-property/ power-domain-names; - cpu-idle-states = <&little_cpu_sleep_0 - &little_cpu_sleep_1 - &cluster_sleep_0>; -}; - -&cpu1 { - /delete-property/ power-domains; - /delete-property/ power-domain-names; - cpu-idle-states = <&little_cpu_sleep_0 - &little_cpu_sleep_1 - &cluster_sleep_0>; -}; - -&cpu2 { - /delete-property/ power-domains; - /delete-property/ power-domain-names; - cpu-idle-states = <&little_cpu_sleep_0 - &little_cpu_sleep_1 - &cluster_sleep_0>; -}; - -&cpu3 { - /delete-property/ power-domains; - /delete-property/ power-domain-names; - cpu-idle-states = <&little_cpu_sleep_0 - &little_cpu_sleep_1 - &cluster_sleep_0>; -}; - -&cpu4 { - /delete-property/ power-domains; - /delete-property/ power-domain-names; - cpu-idle-states = <&big_cpu_sleep_0 - &big_cpu_sleep_1 - &cluster_sleep_0>; -}; - -&cpu5 { - /delete-property/ power-domains; - /delete-property/ power-domain-names; - cpu-idle-states = <&big_cpu_sleep_0 - &big_cpu_sleep_1 - &cluster_sleep_0>; -}; - -&cpu6 { - /delete-property/ power-domains; - /delete-property/ power-domain-names; - cpu-idle-states = <&big_cpu_sleep_0 - &big_cpu_sleep_1 - &cluster_sleep_0>; -}; - -&cpu7 { - /delete-property/ power-domains; - /delete-property/ power-domain-names; - cpu-idle-states = <&big_cpu_sleep_0 - &big_cpu_sleep_1 - &cluster_sleep_0>; -}; - -&lmh_cluster0 { - status = "disabled"; -}; - -&lmh_cluster1 { - status = "disabled"; -}; - -/* - * Reserved memory changes - * - * Putting this all together (out of order with the rest of the file) to keep - * all modifications to the memory map (from sdm845.dtsi) in one place. - */ - -/* - * Our mpss_region is 8MB bigger than the default one and that conflicts - * with venus_mem and cdsp_mem. - * - * For venus_mem we'll delete and re-create at a different address. - * - * cdsp_mem isn't used on cheza right now so we won't bother re-creating it; but - * that also means we need to delete cdsp_pas. - */ -/delete-node/ &venus_mem; -/delete-node/ &cdsp_mem; -/delete-node/ &cdsp_pas; -/delete-node/ &gpu_mem; - -/* Increase the size from 120 MB to 128 MB */ -&mpss_region { - reg = <0 0x8e000000 0 0x8000000>; -}; - -/* Increase the size from 2MB to 8MB */ -&rmtfs_mem { - reg = <0 0x88f00000 0 0x800000>; -}; - -/ { - reserved-memory { - venus_mem: memory@96000000 { - reg = <0 0x96000000 0 0x500000>; - no-map; - }; - }; -}; - -&qspi { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>; - pinctrl-1 = <&qspi_sleep>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - - /* - * In theory chip supports up to 104 MHz and controller up - * to 80 MHz, but above 25 MHz wasn't reliable so we'll use - * that for now. b:117440651 - */ - spi-max-frequency = <25000000>; - spi-tx-bus-width = <2>; - spi-rx-bus-width = <2>; - }; -}; - - -&apps_rsc { - /delete-property/ power-domains; - - regulators-0 { - compatible = "qcom,pm8998-rpmh-regulators"; - qcom,pmic-id = "a"; - - vdd-s1-supply = <&src_vph_pwr>; - vdd-s2-supply = <&src_vph_pwr>; - vdd-s3-supply = <&src_vph_pwr>; - vdd-s4-supply = <&src_vph_pwr>; - vdd-s5-supply = <&src_vph_pwr>; - vdd-s6-supply = <&src_vph_pwr>; - vdd-s7-supply = <&src_vph_pwr>; - vdd-s8-supply = <&src_vph_pwr>; - vdd-s9-supply = <&src_vph_pwr>; - vdd-s10-supply = <&src_vph_pwr>; - vdd-s11-supply = <&src_vph_pwr>; - vdd-s12-supply = <&src_vph_pwr>; - vdd-s13-supply = <&src_vph_pwr>; - vdd-l1-l27-supply = <&src_pp1025_s7a>; - vdd-l2-l8-l17-supply = <&src_pp1350_s3a>; - vdd-l3-l11-supply = <&src_pp1025_s7a>; - vdd-l4-l5-supply = <&src_pp1025_s7a>; - vdd-l6-supply = <&src_vph_pwr>; - vdd-l7-l12-l14-l15-supply = <&src_pp2040_s5a>; - vdd-l9-supply = <&src_pp2040_s5a>; - vdd-l10-l23-l25-supply = <&src_vreg_bob>; - vdd-l13-l19-l21-supply = <&src_vreg_bob>; - vdd-l16-l28-supply = <&src_vreg_bob>; - vdd-l18-l22-supply = <&src_vreg_bob>; - vdd-l20-l24-supply = <&src_vreg_bob>; - vdd-l26-supply = <&src_pp1350_s3a>; - vin-lvs-1-2-supply = <&src_pp1800_s4a>; - - src_pp1125_s2a: smps2 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - src_pp1350_s3a: smps3 { - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - }; - - src_pp2040_s5a: smps5 { - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2040000>; - }; - - src_pp1025_s7a: smps7 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1028000>; - }; - - vdd_qusb_hs0: - vdda_hp_pcie_core: - vdda_mipi_csi0_0p9: - vdda_mipi_csi1_0p9: - vdda_mipi_csi2_0p9: - vdda_mipi_dsi0_pll: - vdda_mipi_dsi1_pll: - vdda_qlink_lv: - vdda_qlink_lv_ck: - vdda_qrefs_0p875: - vdda_pcie_core: - vdda_pll_cc_ebi01: - vdda_pll_cc_ebi23: - vdda_sp_sensor: - vdda_ufs1_core: - vdda_ufs2_core: - vdda_usb1_ss_core: - vdda_usb2_ss_core: - src_pp875_l1a: ldo1 { - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vddpx_10: - src_pp1200_l2a: ldo2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - - /* TODO: why??? */ - regulator-always-on; - }; - - pp1000_l3a_sdr845: ldo3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vdd_wcss_cx: - vdd_wcss_mx: - vdda_wcss_pll: - src_pp800_l5a: ldo5 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vddpx_13: - src_pp1800_l6a: ldo6 { - regulator-min-microvolt = <1856000>; - regulator-max-microvolt = <1856000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - pp1800_l7a_wcn3990: ldo7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - src_pp1200_l8a: ldo8 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1248000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - pp1800_dx_pen: - src_pp1800_l9a: ldo9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - src_pp1800_l10a: ldo10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - pp1000_l11a_sdr845: ldo11 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1048000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vdd_qfprom: - vdd_qfprom_sp: - vdda_apc1_cs_1p8: - vdda_gfx_cs_1p8: - vdda_qrefs_1p8: - vdda_qusb_hs0_1p8: - vddpx_11: - src_pp1800_l12a: ldo12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vddpx_2: - src_pp2950_l13a: ldo13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - src_pp1800_l14a: ldo14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - src_pp1800_l15a: ldo15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - pp2700_l16a: ldo16 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - src_pp1300_l17a: ldo17 { - regulator-min-microvolt = <1304000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - pp2700_l18a: ldo18 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - /* - * NOTE: this rail should have been called - * src_pp3300_l19a in the schematic - */ - src_pp3000_l19a: ldo19 { - regulator-min-microvolt = <3304000>; - regulator-max-microvolt = <3304000>; - - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - src_pp2950_l20a: ldo20 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - src_pp2950_l21a: ldo21 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - pp3300_hub: - src_pp3300_l22a: ldo22 { - regulator-min-microvolt = <3304000>; - regulator-max-microvolt = <3304000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - /* - * HACK: Should add a usb hub node and driver - * to turn this on and off at suspend/resume time - */ - regulator-boot-on; - regulator-always-on; - }; - - pp3300_l23a_ch1_wcn3990: ldo23 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vdda_qusb_hs0_3p1: - src_pp3075_l24a: ldo24 { - regulator-min-microvolt = <3088000>; - regulator-max-microvolt = <3088000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - pp3300_l25a_ch0_wcn3990: ldo25 { - regulator-min-microvolt = <3304000>; - regulator-max-microvolt = <3304000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - pp1200_hub: - vdda_hp_pcie_1p2: - vdda_hv_ebi0: - vdda_hv_ebi1: - vdda_hv_ebi2: - vdda_hv_ebi3: - vdda_mipi_csi_1p25: - vdda_mipi_dsi0_1p2: - vdda_mipi_dsi1_1p2: - vdda_pcie_1p2: - vdda_ufs1_1p2: - vdda_ufs2_1p2: - vdda_usb1_ss_1p2: - vdda_usb2_ss_1p2: - src_pp1200_l26a: ldo26 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - pp3300_dx_pen: - src_pp3300_l28a: ldo28 { - regulator-min-microvolt = <3304000>; - regulator-max-microvolt = <3304000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - src_pp1800_lvs1: lvs1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - src_pp1800_lvs2: lvs2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - - regulators-1 { - compatible = "qcom,pm8005-rpmh-regulators"; - qcom,pmic-id = "c"; - - vdd-s1-supply = <&src_vph_pwr>; - vdd-s2-supply = <&src_vph_pwr>; - vdd-s3-supply = <&src_vph_pwr>; - vdd-s4-supply = <&src_vph_pwr>; - - src_pp600_s3c: smps3 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <600000>; - }; - }; -}; - -edp_brij_i2c: &i2c3 { - status = "okay"; - clock-frequency = <400000>; - - sn65dsi86_bridge: bridge@2d { - compatible = "ti,sn65dsi86"; - reg = <0x2d>; - pinctrl-names = "default"; - pinctrl-0 = <&edp_brij_en &edp_brij_irq>; - - interrupt-parent = <&tlmm>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; - - enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; - - vpll-supply = <&src_pp1800_s4a>; - vccio-supply = <&src_pp1800_s4a>; - vcca-supply = <&src_pp1200_l2a>; - vcc-supply = <&src_pp1200_l2a>; - - clocks = <&rpmhcc RPMH_LN_BB_CLK2>; - clock-names = "refclk"; - - no-hpd; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - sn65dsi86_in: endpoint { - remote-endpoint = <&mdss_dsi0_out>; - }; - }; - - port@1 { - reg = <1>; - sn65dsi86_out: endpoint { - remote-endpoint = <&panel_in_edp>; - }; - }; - }; - }; -}; - -ap_pen_1v8: &i2c11 { - status = "okay"; - clock-frequency = <400000>; - - digitizer@9 { - compatible = "wacom,w9013", "hid-over-i2c"; - reg = <0x9>; - pinctrl-names = "default"; - pinctrl-0 = <&pen_irq_l>, <&pen_pdct_l>, <&pen_rst_l>; - - vdd-supply = <&pp3300_dx_pen>; - vddl-supply = <&pp1800_dx_pen>; - post-power-on-delay-ms = <100>; - - interrupt-parent = <&tlmm>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; - - hid-descr-addr = <0x1>; - }; -}; - -amp_i2c: &i2c12 { - status = "okay"; - clock-frequency = <400000>; -}; - -ap_ts_i2c: &i2c14 { - status = "okay"; - clock-frequency = <400000>; - - touchscreen@10 { - compatible = "elan,ekth3500"; - reg = <0x10>; - pinctrl-names = "default"; - pinctrl-0 = <&ts_int_l &ts_reset_l>; - - interrupt-parent = <&tlmm>; - interrupts = <125 IRQ_TYPE_LEVEL_LOW>; - - vcc33-supply = <&src_pp3300_l28a>; - - reset-gpios = <&tlmm 118 GPIO_ACTIVE_LOW>; - }; -}; - -&gpu { - status = "okay"; -}; - -&ipa { - qcom,gsi-loader = "modem"; - status = "okay"; -}; - -&lpasscc { - status = "okay"; -}; - -&mdss { - status = "okay"; -}; - -&mdss_dsi0 { - status = "okay"; - vdda-supply = <&vdda_mipi_dsi0_1p2>; - - ports { - port@1 { - endpoint { - remote-endpoint = <&sn65dsi86_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; -}; - -&mdss_dsi0_phy { - status = "okay"; - vdds-supply = <&vdda_mipi_dsi0_pll>; -}; - -/* - * Cheza fw does not properly program the GPU aperture to allow the - * GPU to update the SMMU pagetables for context switches. Work - * around this by dropping the "qcom,adreno-smmu" compat string. - */ -&adreno_smmu { - compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; -}; - -&mss_pil { - status = "okay"; - - iommus = <&apps_smmu 0x781 0x0>, - <&apps_smmu 0x724 0x3>; -}; - -&pm8998_pwrkey { - status = "disabled"; -}; - -&qupv3_id_0 { - status = "okay"; - iommus = <&apps_smmu 0x0 0x3>; -}; - -&qupv3_id_1 { - status = "okay"; - iommus = <&apps_smmu 0x6c0 0x3>; -}; - -&sdhc_2 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_cd_odl>; - - vmmc-supply = <&src_pp2950_l21a>; - vqmmc-supply = <&vddpx_2>; - - cd-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>; -}; - -&spi0 { - status = "okay"; -}; - -&spi5 { - status = "okay"; - - tpm@0 { - compatible = "google,cr50"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&h1_ap_int_odl>; - spi-max-frequency = <800000>; - interrupt-parent = <&tlmm>; - interrupts = <129 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&spi10 { - status = "okay"; - - cros_ec: ec@0 { - compatible = "google,cros-ec-spi"; - reg = <0>; - interrupt-parent = <&tlmm>; - interrupts = <122 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ec_ap_int_l>; - spi-max-frequency = <3000000>; - wakeup-source; - - cros_ec_pwm: pwm { - compatible = "google,cros-ec-pwm"; - #pwm-cells = <1>; - }; - - i2c_tunnel: i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - google,remote-bus = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -#include <arm/cros-ec-keyboard.dtsi> -#include <arm/cros-ec-sbs.dtsi> - -&uart6 { - status = "okay"; - - pinctrl-0 = <&qup_uart6_4pin>; - - bluetooth: bluetooth { - compatible = "qcom,wcn3990-bt"; - vddio-supply = <&src_pp1800_s4a>; - vddxo-supply = <&pp1800_l7a_wcn3990>; - vddrf-supply = <&src_pp1300_l17a>; - vddch0-supply = <&pp3300_l25a_ch0_wcn3990>; - max-speed = <3200000>; - }; -}; - -&uart9 { - status = "okay"; -}; - -&ufs_mem_hc { - status = "okay"; - - reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; - - vcc-supply = <&src_pp2950_l20a>; - vcc-max-microamp = <600000>; -}; - -&ufs_mem_phy { - status = "okay"; - - vdda-phy-supply = <&vdda_ufs1_core>; - vdda-pll-supply = <&vdda_ufs1_1p2>; -}; - -&usb_1 { - status = "okay"; - - /* We'll use this as USB 2.0 only */ - qcom,select-utmi-as-pipe-clk; -}; - -&usb_1_dwc3 { - /* - * The hardware design intends this port to be hooked up in peripheral - * mode, so we'll hardcode it here. Some details: - * - SDM845 expects only a single Type C connector so it has only one - * native Type C port but cheza has two Type C connectors. - * - The only source of DP is the single native Type C port. - * - On cheza we want to be able to hook DP up to _either_ of the - * two Type C connectors and want to be able to achieve 4 lanes of DP. - * - When you configure a Type C port for 4 lanes of DP you lose USB3. - * - In order to make everything work, the native Type C port is always - * configured as 4-lanes DP so it's always available. - * - The extra USB3 port on SDM845 goes to a USB 3 hub which is then - * sent to the two Type C connectors. - * - The extra USB2 lines from the native Type C port are always - * setup as "peripheral" so that we can mux them over to one connector - * or the other if someone needs the connector configured as a gadget - * (but they only get USB2 speeds). - * - * All the hardware muxes would allow us to hook things up in different - * ways to some potential benefit for static configurations (you could - * achieve extra USB2 bandwidth by using two different ports for the - * two connectors or possibly even get USB3 peripheral mode), but in - * each case you end up forcing to disconnect/reconnect an in-use - * USB session in some cases depending on what you hotplug into the - * other connector. Thus hardcoding this as peripheral makes sense. - */ - dr_mode = "peripheral"; - - /* - * We always need the high speed pins as 4-lanes DP in case someone - * hotplugs a DP peripheral. Thus limit this port to a max of high - * speed. - */ - maximum-speed = "high-speed"; - - /* - * We don't need the usb3-phy since we run in highspeed mode always, so - * re-define these properties removing the superspeed USB PHY reference. - */ - phys = <&usb_1_hsphy>; - phy-names = "usb2-phy"; -}; - -&usb_1_hsphy { - status = "okay"; - - vdd-supply = <&vdda_usb1_ss_core>; - vdda-pll-supply = <&vdda_qusb_hs0_1p8>; - vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; - - qcom,imp-res-offset-value = <8>; - qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>; - qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>; - qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>; -}; - -&usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { - /* We have this hooked up to a hub and we always use in host mode */ - dr_mode = "host"; -}; - -&usb_2_hsphy { - status = "okay"; - - vdd-supply = <&vdda_usb2_ss_core>; - vdda-pll-supply = <&vdda_qusb_hs0_1p8>; - vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; - - qcom,imp-res-offset-value = <8>; - qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>; -}; - -&usb_2_qmpphy { - status = "okay"; - - vdda-phy-supply = <&vdda_usb2_ss_1p2>; - vdda-pll-supply = <&vdda_usb2_ss_core>; -}; - -&wifi { - status = "okay"; - - vdd-0.8-cx-mx-supply = <&src_pp800_l5a >; - vdd-1.8-xo-supply = <&pp1800_l7a_wcn3990>; - vdd-1.3-rfa-supply = <&src_pp1300_l17a>; - vdd-3.3-ch0-supply = <&pp3300_l25a_ch0_wcn3990>; -}; - -/* PINCTRL - additions to nodes defined in sdm845.dtsi */ - -&qspi_cs0 { - bias-disable; /* External pullup */ -}; - -&qspi_clk { - bias-disable; /* Rely on Cr50 internal pulldown */ -}; - -&qspi_data0 { - bias-disable; /* Rely on Cr50 internal pulldown */ -}; - -&qspi_data1 { - bias-pull-down; -}; - -&qup_i2c3_default { - drive-strength = <2>; - - /* Has external pullup */ - bias-disable; -}; - -&qup_i2c11_default { - drive-strength = <2>; - - /* Has external pullup */ - bias-disable; -}; - -&qup_i2c12_default { - drive-strength = <2>; - - /* Has external pullup */ - bias-disable; -}; - -&qup_i2c14_default { - drive-strength = <2>; - - /* Has external pullup */ - bias-disable; -}; - -&qup_spi0_default { - drive-strength = <2>; - bias-disable; -}; - -&qup_spi5_default { - drive-strength = <2>; - bias-disable; -}; - -&qup_spi10_default { - drive-strength = <2>; - bias-disable; -}; - -&qup_uart9_rx { - drive-strength = <2>; - bias-pull-up; -}; - -&qup_uart9_tx { - drive-strength = <2>; - bias-disable; -}; - -/* PINCTRL - board-specific pinctrl */ -&pm8005_gpios { - gpio-line-names = "", - "", - "SLB", - ""; -}; - -&pm8998_adc { - channel@4d { - reg = <ADC5_AMUX_THM1_100K_PU>; - label = "sdm_temp"; - }; - - channel@4e { - reg = <ADC5_AMUX_THM2_100K_PU>; - label = "quiet_temp"; - }; - - channel@4f { - reg = <ADC5_AMUX_THM3_100K_PU>; - label = "lte_temp_1"; - }; - - channel@50 { - reg = <ADC5_AMUX_THM4_100K_PU>; - label = "lte_temp_2"; - }; - - channel@51 { - reg = <ADC5_AMUX_THM5_100K_PU>; - label = "charger_temp"; - }; -}; - -&pm8998_gpios { - gpio-line-names = "", - "", - "SW_CTRL", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "CFG_OPT1", - "WCSS_PWR_REQ", - "", - "CFG_OPT2", - "SLB"; -}; - -&tlmm { - /* - * pinctrl settings for pins that have no real owners. - */ - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&bios_flash_wp_r_l>, - <&ap_suspend_l_deassert>; - - pinctrl-1 = <&bios_flash_wp_r_l>, - <&ap_suspend_l_assert>; - - /* - * Hogs prevent usermode from changing the value. A GPIO can be both - * here and in the pinctrl section. - */ - ap-suspend-l-hog { - gpio-hog; - gpios = <126 GPIO_ACTIVE_LOW>; - output-low; - }; - - ap_edp_bklten: ap-edp-bklten-state { - pins = "gpio37"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - bios_flash_wp_r_l: bios-flash-wp-r-l-state { - pins = "gpio128"; - function = "gpio"; - bias-disable; - }; - - ec_ap_int_l: ec-ap-int-l-state { - pins = "gpio122"; - function = "gpio"; - bias-pull-up; - }; - - edp_brij_en: edp-brij-en-state { - pins = "gpio102"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - edp_brij_irq: edp-brij-irq-state { - pins = "gpio10"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - en_pp3300_dx_edp: en-pp3300-dx-edp-state { - pins = "gpio43"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - h1_ap_int_odl: h1-ap-int-odl-state { - pins = "gpio129"; - function = "gpio"; - bias-pull-up; - }; - - pen_eject_odl: pen-eject-odl-state { - pins = "gpio119"; - function = "gpio"; - bias-pull-up; - }; - - pen_irq_l: pen-irq-l-state { - pins = "gpio24"; - function = "gpio"; - - /* Has external pullup */ - bias-disable; - }; - - pen_pdct_l: pen-pdct-l-state { - pins = "gpio63"; - function = "gpio"; - - /* Has external pullup */ - bias-disable; - }; - - pen_rst_l: pen-rst-l-state { - pins = "gpio23"; - function = "gpio"; - bias-disable; - drive-strength = <2>; - - /* - * The pen driver doesn't currently support - * driving this reset line. By specifying - * output-high here we're relying on the fact - * that this pin has a default pulldown at boot - * (which makes sure the pen was in reset if it - * was powered) and then we set it high here to - * take it out of reset. Better would be if the - * pen driver could control this and we could - * remove "output-high" here. - */ - output-high; - }; - - qspi_sleep: qspi-sleep-state { - pins = "gpio90", "gpio91", "gpio92", "gpio95"; - - /* - * When we're not actively transferring we want pins as GPIOs - * with output disabled so that the quad SPI IP block stops - * driving them. We rely on the normal pulls configured in - * the active state and don't redefine them here. Also note - * that we don't need the reverse (output-enable) in the - * normal mode since the "output-enable" only matters for - * GPIO function. - */ - function = "gpio"; - output-disable; - }; - - sdc2_clk: sdc2-clk-state { - pins = "sdc2_clk"; - bias-disable; - - /* - * It seems that mmc_test reports errors if drive - * strength is not 16. - */ - drive-strength = <16>; - }; - - sdc2_cmd: sdc2-cmd-state { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <16>; - }; - - sdc2_data: sdc2-data-state { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <16>; - }; - - sd_cd_odl: sd-cd-odl-state { - pins = "gpio44"; - function = "gpio"; - bias-pull-up; - }; - - ts_int_l: ts-int-l-state { - pins = "gpio125"; - function = "gpio"; - bias-pull-up; - }; - - ts_reset_l: ts-reset-l-state { - pins = "gpio118"; - function = "gpio"; - bias-disable; - drive-strength = <2>; - }; - - ap_suspend_l_assert: ap-suspend-l-assert-state { - pins = "gpio126"; - function = "gpio"; - bias-disable; - drive-strength = <2>; - output-low; - }; - - ap_suspend_l_deassert: ap-suspend-l-deassert-state { - pins = "gpio126"; - function = "gpio"; - bias-disable; - drive-strength = <2>; - output-high; - }; -}; - -&venus { - status = "okay"; - - video-firmware { - iommus = <&apps_smmu 0x10b2 0x0>; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso b/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso index 51f1a4883ab8..dbe1911d8e47 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso @@ -44,7 +44,8 @@ clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; clock-names = "xvclk"; - clock-frequency = <19200000>; + assigned-clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + assigned-clock-rates = <19200000>; /* * The &vreg_s4a_1p8 trace is powered on as a, diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index b5c63fa0365d..8abf3e909502 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include <dt-bindings/arm/qcom,ids.h> #include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> @@ -18,7 +19,7 @@ / { model = "Thundercomm Dragonboard 845c"; compatible = "thundercomm,db845c", "qcom,sdm845"; - qcom,msm-id = <341 0x20001>; + qcom,msm-id = <QCOM_ID_SDA845 0x20001>; qcom,board-id = <8 0>; aliases { @@ -533,15 +534,11 @@ qcom,dual-dsi-mode; qcom,master-dsi; +}; - ports { - port@1 { - endpoint { - remote-endpoint = <<9611_a>; - data-lanes = <0 1 2 3>; - }; - }; - }; +&mdss_dsi0_out { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; }; &mdss_dsi0_phy { @@ -559,15 +556,11 @@ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; status = "okay"; +}; - ports { - port@1 { - endpoint { - remote-endpoint = <<9611_b>; - data-lanes = <0 1 2 3>; - }; - }; - }; +&mdss_dsi1_out { + remote-endpoint = <<9611_b>; + data-lanes = <0 1 2 3>; }; &mdss_dsi1_phy { diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index a98756e8b965..63d2993536ad 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -445,15 +445,6 @@ qcom,dual-dsi-mode; qcom,master-dsi; - ports { - port@1 { - endpoint { - remote-endpoint = <&truly_in_0>; - data-lanes = <0 1 2 3>; - }; - }; - }; - panel@0 { compatible = "truly,nt35597-2K-display"; reg = <0>; @@ -483,6 +474,11 @@ }; }; +&mdss_dsi0_out { + remote-endpoint = <&truly_in_0>; + data-lanes = <0 1 2 3>; +}; + &mdss_dsi0_phy { status = "okay"; vdds-supply = <&vdda_mipi_dsi0_pll>; @@ -497,15 +493,11 @@ /* DSI1 is slave, so use DSI0 clocks */ assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; +}; - ports { - port@1 { - endpoint { - remote-endpoint = <&truly_in_1>; - data-lanes = <0 1 2 3>; - }; - }; - }; +&mdss_dsi1_out { + remote-endpoint = <&truly_in_1>; + data-lanes = <0 1 2 3>; }; &mdss_dsi1_phy { diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index b118d666e535..dcfffb271fcf 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -7,6 +7,7 @@ /dts-v1/; +#include <dt-bindings/arm/qcom,ids.h> #include <dt-bindings/input/linux-event-codes.h> #include <dt-bindings/leds/common.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> @@ -21,6 +22,9 @@ /delete-node/ &rmtfs_mem; / { + chassis-type = "handset"; + qcom,msm-id = <QCOM_ID_SDM845 0x20001>; + aliases { serial0 = &uart9; serial1 = &uart6; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts index 4005e04d998a..a259eb9d45ae 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts @@ -5,13 +5,12 @@ * Copyright (c) 2020, The Linux Foundation. All rights reserved. */ +#include <dt-bindings/leds/common.h> #include "sdm845-oneplus-common.dtsi" / { model = "OnePlus 6"; compatible = "oneplus,enchilada", "qcom,sdm845"; - chassis-type = "handset"; - qcom,msm-id = <0x141 0x20001>; qcom,board-id = <8 0 17819 22>; battery: battery { @@ -20,6 +19,14 @@ charge-full-design-microamp-hours = <3300000>; voltage-min-design-microvolt = <3400000>; voltage-max-design-microvolt = <4400000>; + + /* + * Typical designs have multiple charger ICs which can handle more + * current but the OnePlus 6/T do not, hence the lower limit. This + * does not apply when using the Dash Charger, however this is not + * yet supported. + */ + constant-charge-current-max-microamp = <1800000>; }; }; @@ -55,6 +62,33 @@ monitored-battery = <&battery>; }; +&pmi8998_lpg { + status = "okay"; + + multi-led { + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@3 { + reg = <3>; + color = <LED_COLOR_ID_BLUE>; + }; + + led@4 { + reg = <4>; + color = <LED_COLOR_ID_GREEN>; + }; + + led@5 { + reg = <5>; + color = <LED_COLOR_ID_RED>; + }; + }; +}; + &sound { model = "OnePlus 6"; audio-routing = "RX_BIAS", "MCLK", diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts index 9471ada0d6ad..7e75decfda05 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts @@ -10,8 +10,6 @@ / { model = "OnePlus 6T"; compatible = "oneplus,fajita", "qcom,sdm845"; - chassis-type = "handset"; - qcom,msm-id = <0x141 0x20001>; qcom,board-id = <8 0 18801 41>; battery: battery { @@ -20,6 +18,14 @@ charge-full-design-microamp-hours = <3700000>; voltage-min-design-microvolt = <3400000>; voltage-max-design-microvolt = <4400000>; + + /* + * Typical designs have multiple charger ICs which can handle more + * current but the OnePlus 6/T do not, hence the lower limit. This + * does not apply when using the Dash Charger, however this is not + * yet supported. + */ + constant-charge-current-max-microamp = <1800000>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts index d686531bf4ea..75a53f0bbebd 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts @@ -56,6 +56,21 @@ }; }; + slpi_regulator: slpi-regulator { + compatible = "regulator-fixed"; + pinctrl-0 = <&slpi_ldo_active_state>; + pinctrl-names = "default"; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "slpi"; + + enable-active-high; + gpio = <&tlmm 8 GPIO_ACTIVE_HIGH>; + }; + vib_regulator: gpio-regulator { compatible = "regulator-fixed"; @@ -118,7 +133,7 @@ }; slpi_mem: slpi@96700000 { - reg = <0 0x96700000 0 0xf00000>; + reg = <0 0x96700000 0 0x1000000>; no-map; }; @@ -145,8 +160,8 @@ i2c21 { compatible = "i2c-gpio"; - sda-gpios = <&tlmm 127 GPIO_ACTIVE_HIGH>; - scl-gpios = <&tlmm 128 GPIO_ACTIVE_HIGH>; + sda-gpios = <&tlmm 127 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 128 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <2>; pinctrl-0 = <&i2c21_sda_state &i2c21_scl_state>; pinctrl-names = "default"; @@ -633,7 +648,6 @@ monitored-battery = <&battery>; interrupt-parent = <&pm8998_gpios>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - }; fuel-gauge@36 { @@ -701,7 +715,7 @@ pinctrl-names = "default"; status = "okay"; - audio-routing = "RX_BIAS", "MCLK", + audio-routing = "RX_BIAS", "MCLK", "AMIC2", "MIC BIAS2", /* Headset Mic */ "AMIC3", "MIC BIAS2", /* FM radio left Tx */ "AMIC4", "MIC BIAS2", /* FM radio right Tx */ @@ -903,6 +917,13 @@ status = "okay"; }; +&slpi_pas { + firmware-name = "qcom/sdm845/starqltechn/slpi.mbn"; + cx-supply = <&slpi_regulator>; + + status = "okay"; +}; + &usb_1 { status = "okay"; }; @@ -1029,6 +1050,13 @@ bias-pull-up; }; + slpi_ldo_active_state: slpi-ldo-active-state { + pins = "gpio8"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + touch_irq_state: touch-irq-state { pins = "gpio120"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index 2cf7b5e1243c..89260fce6513 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -7,6 +7,7 @@ /dts-v1/; +#include <dt-bindings/arm/qcom,ids.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/leds/common.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> @@ -17,7 +18,8 @@ / { model = "SHIFT SHIFT6mq"; compatible = "shift,axolotl", "qcom,sdm845"; - qcom,msm-id = <321 0x20001>; + chassis-type = "handset"; + qcom,msm-id = <QCOM_ID_SDM845 0x20001>; qcom,board-id = <11 0>; aliases { diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi index a3a304e1ac87..f3f4c0900572 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> */ +#include <dt-bindings/arm/qcom,ids.h> #include <dt-bindings/input/input.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> @@ -12,7 +13,7 @@ #include "pmi8998.dtsi" / { - qcom,msm-id = <321 0x20001>; /* SDM845 v2.1 */ + qcom,msm-id = <QCOM_ID_SDM845 0x20001>; /* SDM845 v2.1 */ qcom,board-id = <8 0>; aliases { diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index 7810b0ce7591..7480c8d7ac5b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -2,6 +2,7 @@ /dts-v1/; +#include <dt-bindings/arm/qcom,ids.h> #include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> @@ -32,7 +33,7 @@ /* required for bootloader to select correct board */ qcom,board-id = <69 0>; - qcom,msm-id = <321 0x20001>; + qcom,msm-id = <QCOM_ID_SDM845 0x20001>; aliases { serial1 = &uart6; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts index 63cf879a7a29..1c50a0563bc4 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts @@ -6,6 +6,7 @@ /dts-v1/; +#include <dt-bindings/arm/qcom,ids.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> @@ -38,7 +39,7 @@ chassis-type = "handset"; /* required for bootloader to select correct board */ - qcom,msm-id = <0x141 0x20001>; + qcom,msm-id = <QCOM_ID_SDM845 0x20001>; qcom,board-id = <0x2a 0x0>; aliases { diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index c0f466d96630..13c9515260ef 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2347,10 +2347,10 @@ "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, <&gcc GCC_PCIE_0_AUX_CLK>, @@ -2472,10 +2472,10 @@ "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_AUX_CLK>, @@ -4089,7 +4089,7 @@ reg = <2>; usb_1_qmpphy_dp_in: endpoint { - remote-endpoint = <&dp_out>; + remote-endpoint = <&mdss_dp_out>; }; }; }; @@ -4286,14 +4286,6 @@ status = "disabled"; - video-core0 { - compatible = "venus-decoder"; - }; - - video-core1 { - compatible = "venus-encoder"; - }; - venus_opp_table: opp-table { compatible = "operating-points-v2"; @@ -4603,7 +4595,7 @@ port@0 { reg = <0>; dpu_intf0_out: endpoint { - remote-endpoint = <&dp_in>; + remote-endpoint = <&mdss_dp_in>; }; }; @@ -4664,12 +4656,19 @@ <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; - clock-names = "core_iface", "core_aux", "ctrl_link", - "ctrl_link_iface", "stream_pixel"; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; phy-names = "dp"; @@ -4682,14 +4681,14 @@ #size-cells = <0>; port@0 { reg = <0>; - dp_in: endpoint { + mdss_dp_in: endpoint { remote-endpoint = <&dpu_intf0_out>; }; }; port@1 { reg = <1>; - dp_out: endpoint { + mdss_dp_out: endpoint { remote-endpoint = <&usb_1_qmpphy_dp_in>; }; }; @@ -5404,11 +5403,11 @@ compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; qcom,controlled-remotely; reg = <0 0x17184000 0 0x2a000>; - num-channels = <31>; + num-channels = <23>; interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; qcom,ee = <1>; - qcom,num-ees = <2>; + qcom,num-ees = <4>; iommus = <&apps_smmu 0x1806 0x0>; }; diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 8ef6db3be6e3..90efbb7e3799 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -421,9 +421,46 @@ data-role = "host"; /* - * connected to the onboard USB hub, orientation is - * handled by the controller + * connected to the onboard USB hub, each pair of lanes + * (and D+/D- pair) is connected to a separate port on + * the hub. */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + ucsi1_hs_in_1: endpoint@1 { + reg = <1>; + remote-endpoint = <&usb_hub_2_1>; + }; + + ucsi1_hs_in_2: endpoint@2 { + reg = <2>; + remote-endpoint = <&usb_hub_2_2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ucsi1_ss_in_1: endpoint@1 { + reg = <1>; + remote-endpoint = <&usb_hub_3_1>; + }; + + ucsi1_ss_in_2: endpoint@2 { + reg = <2>; + remote-endpoint = <&usb_hub_3_2>; + }; + }; + }; }; }; }; @@ -561,15 +598,11 @@ &mdss_dsi0 { status = "okay"; vdda-supply = <&vreg_l26a_1p2>; +}; - ports { - port@1 { - endpoint { - remote-endpoint = <&sn65dsi86_in_a>; - data-lanes = <0 1 2 3>; - }; - }; - }; +&mdss_dsi0_out { + remote-endpoint = <&sn65dsi86_in_a>; + data-lanes = <0 1 2 3>; }; &mdss_dsi0_phy { @@ -842,6 +875,69 @@ &usb_2_dwc3 { dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + + usb_hub_2_x: hub@1 { + compatible = "usb5e3,610"; + reg = <1>; + peer-hub = <&usb_hub_3_x>; + #address-cells = <1>; + #size-cells = <0>; + + camera@3 { + compatible = "usb4f2,b61e"; + reg = <3>; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + usb_hub_2_1: endpoint { + remote-endpoint = <&ucsi1_hs_in_1>; + }; + }; + + port@2 { + reg = <2>; + + usb_hub_2_2: endpoint { + remote-endpoint = <&ucsi1_hs_in_2>; + }; + }; + }; + }; + + usb_hub_3_x: hub@2 { + compatible = "usb5e3,620"; + reg = <2>; + peer-hub = <&usb_hub_2_x>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + usb_hub_3_1: endpoint { + remote-endpoint = <&ucsi1_ss_in_1>; + }; + }; + + port@2 { + reg = <2>; + + usb_hub_3_2: endpoint { + remote-endpoint = <&ucsi1_ss_in_2>; + }; + }; + }; + }; }; &usb_2_hsphy { diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/sm6150.dtsi index bfbb21035492..3d2a1cb02b62 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi @@ -3,7 +3,11 @@ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. */ +#include <dt-bindings/clock/qcom,qcs615-camcc.h> +#include <dt-bindings/clock/qcom,qcs615-dispcc.h> #include <dt-bindings/clock/qcom,qcs615-gcc.h> +#include <dt-bindings/clock/qcom,qcs615-gpucc.h> +#include <dt-bindings/clock/qcom,qcs615-videocc.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/interconnect/qcom,icc.h> @@ -32,6 +36,8 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&l2_0>; + clocks = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; l2_0: l2-cache { @@ -52,6 +58,8 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&l2_100>; + clocks = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; l2_100: l2-cache { compatible = "cache"; @@ -71,6 +79,8 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&l2_200>; + clocks = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; l2_200: l2-cache { compatible = "cache"; @@ -90,6 +100,8 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&l2_300>; + clocks = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; l2_300: l2-cache { compatible = "cache"; @@ -109,6 +121,8 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&l2_400>; + clocks = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; l2_400: l2-cache { compatible = "cache"; @@ -128,6 +142,8 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&l2_500>; + clocks = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; l2_500: l2-cache { compatible = "cache"; @@ -147,6 +163,8 @@ capacity-dmips-mhz = <1740>; dynamic-power-coefficient = <404>; next-level-cache = <&l2_600>; + clocks = <&cpufreq_hw 1>; + qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; l2_600: l2-cache { @@ -167,6 +185,8 @@ capacity-dmips-mhz = <1740>; dynamic-power-coefficient = <404>; next-level-cache = <&l2_700>; + clocks = <&cpufreq_hw 1>; + qcom,freq-domain = <&cpufreq_hw 1>; l2_700: l2-cache { compatible = "cache"; @@ -474,6 +494,11 @@ hwlocks = <&tcsr_mutex 3>; }; + pil_video_mem: pil-video@93400000 { + reg = <0x0 0x93400000 0x0 0x500000>; + no-map; + }; + rproc_cdsp_mem: rproc-cdsp@93b00000 { reg = <0x0 0x93b00000 0x0 0x1e00000>; no-map; @@ -495,6 +520,9 @@ gcc: clock-controller@100000 { compatible = "qcom,qcs615-gcc"; reg = <0 0x00100000 0 0x1f0000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; #clock-cells = <1>; #reset-cells = <1>; @@ -631,6 +659,7 @@ interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -654,6 +683,7 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, <&gpi_dma0 1 1 QCOM_GPI_I2C>; dma-names = "tx", @@ -681,6 +711,7 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, <&gpi_dma0 1 2 QCOM_GPI_I2C>; dma-names = "tx", @@ -703,6 +734,7 @@ interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, <&gpi_dma0 1 2 QCOM_GPI_SPI>; dma-names = "tx", @@ -728,6 +760,7 @@ interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -751,6 +784,7 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, <&gpi_dma0 1 3 QCOM_GPI_I2C>; dma-names = "tx", @@ -1066,6 +1100,153 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + pcie: pcie@1c08000 { + device_type = "pci"; + compatible = "qcom,pcie-qcs615", "qcom,pcie-sm8150"; + reg = <0x0 0x01c08000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf1d>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x1000>, + <0x0 0x40100000 0x0 0x100000>, + <0x0 0x01c0b000 0x0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <0>; + num-lanes = <1>; + + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&aggre1_noc MASTER_PCIE QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + iommu-map = <0x0 &apps_smmu 0x400 0x1>, + <0x100 &apps_smmu 0x401 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_0_GDSC>; + + phys = <&pcie_phy>; + phy-names = "pciephy"; + + max-link-speed = <2>; + + operating-points-v2 = <&pcie_opp_table>; + + status = "disabled"; + + pcie_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + }; + + /* GEN 2 x1 */ + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + }; + }; + + pcie_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + bus-range = <0x01 0xff>; + }; + }; + + pcie_phy: phy@1c0e000 { + compatible = "qcom,qcs615-qmp-gen3x1-pcie-phy"; + reg = <0x0 0x01c0e000 0x0 0x1000>; + + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "refgen", + "pipe"; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; + assigned-clock-rates = <100000000>; + + #clock-cells = <0>; + clock-output-names = "pcie_0_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0x0 0x01d84000 0x0 0x3000>, @@ -1506,6 +1687,19 @@ }; }; + gpucc: clock-controller@5090000 { + compatible = "qcom,qcs615-gpucc"; + reg = <0 0x05090000 0 0x9000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GPLL0>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + stm@6002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0x0 0x06002000 0x0 0x1000>, @@ -3166,6 +3360,56 @@ mboxes = <&apss_shared 4>; label = "cdsp"; qcom,remote-pid = <5>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x1081 0x0>; + dma-coherent; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x1082 0x0>; + dma-coherent; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1083 0x0>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1084 0x0>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1085 0x0>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1086 0x0>; + dma-coherent; + }; + }; }; }; @@ -3317,6 +3561,119 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + venus: video-codec@aa00000 { + compatible = "qcom,qcs615-venus", "qcom,sc7180-venus"; + reg = <0x0 0x0aa00000 0x0 0x100000>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, + <&videocc VIDEO_CC_VENUS_AHB_CLK>, + <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, + <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, + <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; + clock-names = "core", + "iface", + "bus", + "vcodec0_core", + "vcodec0_bus"; + + power-domains = <&videocc VENUS_GDSC>, + <&videocc VCODEC0_GDSC>, + <&rpmhpd RPMHPD_CX>; + power-domain-names = "venus", + "vcodec0", + "cx"; + + operating-points-v2 = <&venus_opp_table>; + + interconnects = <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "video-mem", + "cpu-cfg"; + + iommus = <&apps_smmu 0xe60 0x20>; + + memory-region = <&pil_video_mem>; + + status = "disabled"; + + venus_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-133330000 { + opp-hz = /bits/ 64 <133330000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-380000000 { + opp-hz = /bits/ 64 <380000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-410000000 { + opp-hz = /bits/ 64 <410000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + }; + + videocc: clock-controller@ab00000 { + compatible = "qcom,qcs615-videocc"; + reg = <0 0x0ab00000 0 0x10000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + camcc: clock-controller@ad00000 { + compatible = "qcom,qcs615-camcc"; + reg = <0 0x0ad00000 0 0x10000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,qcs615-dispcc"; + reg = <0 0x0af00000 0 0x20000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <0>, + <0>, + <0>, + <0>, + <0>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,qcs615-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x30000>, @@ -3456,6 +3813,7 @@ reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; #redistributor-regions = <1>; @@ -3473,6 +3831,7 @@ compatible = "qcom,apss-wdt-qcs615", "qcom,kpss-wdt"; reg = <0x0 0x17c10000 0x0 0x1000>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sleep_clk>; }; timer@17c20000 { @@ -3562,6 +3921,7 @@ rpmhcc: clock-controller { compatible = "qcom,qcs615-rpmh-clk"; + clocks = <&xo_board_clk>; clock-names = "xo"; #clock-cells = <1>; @@ -3803,6 +4163,17 @@ }; }; + tsens0: thermal-sensor@c263000 { + compatible = "qcom,qcs615-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c263000 0x0 0x1000>, + <0x0 0x0c222000 0x0 0x1000>; + interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + remoteproc_adsp: remoteproc@62400000 { compatible = "qcom,qcs615-adsp-pas", "qcom,sm8150-adsp-pas"; reg = <0x0 0x62400000 0x0 0x4040>; @@ -3838,8 +4209,57 @@ mboxes = <&apss_shared 24>; label = "lpass"; qcom,remote-pid = <2>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1723 0x0>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1724 0x0>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1725 0x0>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1726 0x0>; + qcom,nsessions = <5>; + dma-coherent; + }; + }; }; }; + + cpufreq_hw: cpufreq@18323000 { + compatible = "qcom,qcs615-cpufreq-hw", "qcom,cpufreq-hw"; + reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; + reg-names = "freq-domain0", "freq-domain1"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + #clock-cells = <1>; + }; }; arch_timer: timer { @@ -3849,4 +4269,198 @@ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; }; + + thermal-zones { + aoss-thermal { + thermal-sensors = <&tsens0 0>; + + trips { + aoss-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss-0-thermal { + thermal-sensors = <&tsens0 1>; + + trips { + cpuss0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss-1-thermal { + thermal-sensors = <&tsens0 2>; + + trips { + cpuss1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss-2-thermal { + thermal-sensors = <&tsens0 3>; + + trips { + cpuss2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss-3-thermal { + thermal-sensors = <&tsens0 4>; + + trips { + cpuss3-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-0-thermal { + thermal-sensors = <&tsens0 5>; + + trips { + cpu-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-1-thermal { + thermal-sensors = <&tsens0 6>; + + trips { + cpu-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-2-thermal { + thermal-sensors = <&tsens0 7>; + + trips { + cpu-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-3-thermal { + thermal-sensors = <&tsens0 8>; + + trips { + cpu-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-thermal { + thermal-sensors = <&tsens0 9>; + + trips { + gpu-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + q6-hvx-thermal { + thermal-sensors = <&tsens0 10>; + + trips { + q6-hvx-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + mdm-core-thermal { + thermal-sensors = <&tsens0 11>; + + trips { + mdm-core-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + camera-thermal { + thermal-sensors = <&tsens0 12>; + + trips { + camera-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + wlan-thermal { + thermal-sensors = <&tsens0 13>; + + trips { + wlan-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + display-thermal { + thermal-sensors = <&tsens0 14>; + + trips { + display-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + video-thermal { + thermal-sensors = <&tsens0 15>; + + trips { + video-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index ff1eb2c53e7b..8459b27cacc7 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1351,6 +1351,13 @@ compatible = "qcom,q6afe-clocks"; #clock-cells = <2>; }; + + q6usbdai: usbd { + compatible = "qcom,q6usb"; + iommus = <&apps_smmu 0x100f 0x0>; + #sound-dai-cells = <1>; + qcom,usb-audio-intr-idx = /bits/ 16 <2>; + }; }; q6asm: service@7 { @@ -1979,6 +1986,7 @@ reg = <0x0 0x0a600000 0x0 0xcd00>; interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; iommus = <&apps_smmu 0x540 0x0>; + num-hc-interrupters = /bits/ 16 <3>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; snps,has-lpm-erratum; @@ -2241,7 +2249,7 @@ }; mdss_dp: displayport-controller@ae90000 { - compatible = "qcom,sm6350-dp", "qcom,sm8350-dp"; + compatible = "qcom,sm6350-dp", "qcom,sc7180-dp"; reg = <0x0 0xae90000 0x0 0x200>, <0x0 0xae90200 0x0 0x200>, <0x0 0xae90400 0x0 0x600>, @@ -2479,6 +2487,11 @@ #clock-cells = <0>; }; + sram@c3f0000 { + compatible = "qcom,rpmh-stats"; + reg = <0x0 0x0c3f0000 0x0 0x400>; + }; + spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0 0x0c440000 0x0 0x1100>, @@ -2962,6 +2975,9 @@ }; }; + sound: sound { + }; + thermal-zones { aoss0-thermal { thermal-sensors = <&tsens0 0>; diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index 52b16a4fdc43..4afbab570ca1 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -19,6 +19,7 @@ #include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include <dt-bindings/sound/qcom,q6asm.h> #include <dt-bindings/usb/pd.h> #include "sm7225.dtsi" #include "pm6150l.dtsi" @@ -938,6 +939,12 @@ }; }; +&q6asmdai { + dai@0 { + reg = <MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; +}; + &qup_uart1_cts { /* * Configure a bias-bus-hold on CTS to lower power @@ -1006,6 +1013,35 @@ status = "okay"; }; +&sound { + compatible = "fairphone,fp4-sndcard"; + model = "Fairphone 4"; + + mm1-dai-link { + link-name = "MultiMedia1"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; + }; + + usb-dai-link { + link-name = "USB Playback"; + + codec { + sound-dai = <&q6usbdai USB_RX>; + }; + + cpu { + sound-dai = <&q6afedai USB_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + }; +}; + &tlmm { gpio-reserved-ranges = <13 4>, <56 2>; diff --git a/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts b/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts index befbb40228b5..f16b47b6a74c 100644 --- a/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts +++ b/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts @@ -1425,16 +1425,14 @@ &usb_1 { /* USB 2.0 only */ qcom,select-utmi-as-pipe-clk; - status = "okay"; -}; - -&usb_1_dwc3 { dr_mode = "otg"; usb-role-switch; maximum-speed = "high-speed"; /* Remove USB3 phy */ phys = <&usb_1_hsphy>; phy-names = "usb2-phy"; + + status = "okay"; }; &usb_1_dwc3_hs { diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts index e1e294f0f462..0339a572f34d 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts @@ -478,15 +478,11 @@ qcom,dual-dsi-mode; qcom,master-dsi; +}; - ports { - port@1 { - endpoint { - remote-endpoint = <<9611_a>; - data-lanes = <0 1 2 3>; - }; - }; - }; +&mdss_dsi0_out { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; }; &mdss_dsi0_phy { @@ -504,15 +500,11 @@ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; status = "okay"; +}; - ports { - port@1 { - endpoint { - remote-endpoint = <<9611_b>; - data-lanes = <0 1 2 3>; - }; - }; - }; +&mdss_dsi1_out { + remote-endpoint = <<9611_b>; + data-lanes = <0 1 2 3>; }; &mdss_dsi1_phy { diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index abf12e10d33f..acdba79612aa 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1866,10 +1866,10 @@ "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, <&gcc GCC_PCIE_0_AUX_CLK>, @@ -1981,10 +1981,10 @@ "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_AUX_CLK>, @@ -3890,16 +3890,20 @@ <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; @@ -3908,7 +3912,7 @@ #sound-dai-cells = <0>; operating-points-v2 = <&dp_opp_table>; - power-domains = <&rpmhpd SM8250_MMCX>; + power-domains = <&rpmhpd SM8150_MMCX>; status = "disabled"; @@ -4366,6 +4370,7 @@ intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; interrupt-controller; + #address-cells = <0>; #interrupt-cells = <3>; reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ @@ -4419,7 +4424,7 @@ frame@17c27000 { frame-number = <3>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x17c26000 0x1000>; + reg = <0x17c27000 0x1000>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250-samsung-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-samsung-common.dtsi new file mode 100644 index 000000000000..cf3d917addd8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8250-samsung-common.dtsi @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include "sm8250.dtsi" +#include "pm8150.dtsi" + +/ { + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer: framebuffer@9c000000 { + compatible = "simple-framebuffer"; + reg = <0x0 0x9c000000 0x0 0x2300000>; + width = <1080>; + height = <2400>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + }; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&vol_up_n>; + + key-vol-up { + label = "Volume Up"; + gpios = <&pm8150_gpios 3 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + reserved-memory { + cont_splash_mem: memory@9c000000 { + reg = <0x0 0x9c000000 0x0 0x2300000>; + no-map; + }; + + ramoops@9fa00000 { + compatible = "ramoops"; + reg = <0x0 0x9fa00000 0x0 0x100000>; + record-size = <0x4000>; + console-size = <0x40000>; + ftrace-size = <0x40000>; + pmsg-size = <0x40000>; + no-map; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vreg_s4a_1p8: smps4 { + regulator-name = "vreg_s4a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2a_3p1: ldo2 { + regulator-name = "vreg_l2a_3p1"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5a_0p88: ldo5 { + regulator-name = "vreg_l5a_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6a_1p2: ldo6 { + regulator-name = "vreg_l6a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9a_1p2: ldo9 { + regulator-name = "vreg_l9a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l12a_1p8: ldo12 { + regulator-name = "vreg_l12a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l17a_3p0: ldo17 { + regulator-name = "vreg_l17a_3p0"; + regulator-min-microvolt = <2496000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +&pm8150_gpios { + vol_up_n: vol-up-n-state { + pins = "gpio3"; + function = "normal"; + power-source = <0>; + input-enable; + bias-pull-up; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <40 4>; /* I2C (Unused) */ +}; + +&usb_1 { + /* Limit to USB 2.0 for now */ + qcom,select-utmi-as-pipe-clk; + + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + /* Remove USB3 phy */ + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l5a_0p88>; + vdda18-supply = <&vreg_l12a_1p8>; + vdda33-supply = <&vreg_l2a_3p1>; + + status = "okay"; +}; + +&ufs_mem_hc { + vcc-supply = <&vreg_l17a_3p0>; + vcc-max-microamp = <800000>; + vccq-supply = <&vreg_l6a_1p2>; + vccq-max-microamp = <800000>; + vccq2-supply = <&vreg_s4a_1p8>; + vccq2-max-microamp = <800000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l5a_0p88>; + vdda-pll-supply = <&vreg_l9a_1p2>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8250-samsung-r8q.dts b/arch/arm64/boot/dts/qcom/sm8250-samsung-r8q.dts new file mode 100644 index 000000000000..dc7c3816f156 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8250-samsung-r8q.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "sm8250-samsung-common.dtsi" + +/ { + model = "Samsung Galaxy S20 FE"; + compatible = "samsung,r8q", "qcom,sm8250"; + chassis-type = "handset"; +}; + +&adsp { + firmware-name = "qcom/sm8250/Samsung/r8q/adsp.mbn"; + status = "okay"; +}; + +&cdsp { + firmware-name = "qcom/sm8250/Samsung/r8q/cdsp.mbn"; + status = "okay"; +}; + +&slpi { + firmware-name = "qcom/sm8250/Samsung/r8q/slpi.mbn"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8250-samsung-x1q.dts b/arch/arm64/boot/dts/qcom/sm8250-samsung-x1q.dts new file mode 100644 index 000000000000..d6aeb5af2ba4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8250-samsung-x1q.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "sm8250-samsung-common.dtsi" + +/ { + model = "Samsung Galaxy S20"; + compatible = "samsung,x1q", "qcom,sm8250"; + chassis-type = "handset"; +}; + +&adsp { + firmware-name = "qcom/sm8250/Samsung/x1q/adsp.mbn"; + status = "okay"; +}; + +&cdsp { + firmware-name = "qcom/sm8250/Samsung/x1q/cdsp.mbn"; + status = "okay"; +}; + +&slpi { + firmware-name = "qcom/sm8250/Samsung/x1q/slpi.mbn"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts index 668078ea4f04..4ad24974c09f 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts @@ -12,7 +12,6 @@ #include "pm8150.dtsi" #include "pm8150b.dtsi" #include "pm8150l.dtsi" -#include "pm8009.dtsi" /* * Delete following upstream (sm8250.dtsi) reserved @@ -50,18 +49,12 @@ }; }; - battery_l: battery-l { + battery: battery { compatible = "simple-battery"; - voltage-min-design-microvolt = <3870000>; - energy-full-design-microwatt-hours = <16700000>; - charge-full-design-microamp-hours = <4420000>; - }; - - battery_r: battery-r { - compatible = "simple-battery"; - voltage-min-design-microvolt = <3870000>; - energy-full-design-microwatt-hours = <16700000>; - charge-full-design-microamp-hours = <4420000>; + charge-full-design-microamp-hours = <8840000>; + energy-full-design-microwatt-hours = <34300000>; + voltage-min-design-microvolt = <3400000>; + voltage-max-design-microvolt = <4370000>; }; bl_vddpos_5p5: bl-vddpos-regulator { @@ -406,63 +399,6 @@ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; }; - - regulators-2 { - compatible = "qcom,pm8009-rpmh-regulators"; - qcom,pmic-id = "f"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vreg_bob>; - vdd-l2-supply = <&vreg_s8c_1p35>; - vdd-l5-l6-supply = <&vreg_bob>; - vdd-l7-supply = <&vreg_s4a_1p8>; - - vreg_s1f_1p2: smps1 { - regulator-name = "vreg_s1f_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_s2f_0p5: smps2 { - regulator-name = "vreg_s2f_0p5"; - regulator-min-microvolt = <512000>; - regulator-max-microvolt = <1100000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - /* L1 is unused. */ - - vreg_l2f_1p3: ldo2 { - regulator-name = "vreg_l2f_1p3"; - regulator-min-microvolt = <1056000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - /* L3 & L4 are unused. */ - - vreg_l5f_2p8: ldo5 { - regulator-name = "vreg_l5f_2p85"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3000000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l6f_2p8: ldo6 { - regulator-name = "vreg_l6f_2p8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3000000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l7f_1p8: ldo7 { - regulator-name = "vreg_l7f_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - }; }; &cdsp { @@ -495,17 +431,6 @@ }; }; -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - fuel-gauge@55 { - compatible = "ti,bq27z561"; - reg = <0x55>; - monitored-battery = <&battery_r>; - }; -}; - &i2c11 { clock-frequency = <400000>; status = "okay"; @@ -523,17 +448,6 @@ }; }; -&i2c13 { - clock-frequency = <400000>; - status = "okay"; - - fuel-gauge@55 { - compatible = "ti,bq27z561"; - reg = <0x55>; - monitored-battery = <&battery_l>; - }; -}; - &pcie0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index b30aea8b0540..50dd11432bb2 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1030,7 +1030,7 @@ dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, <&gpi_dma2 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1075,7 +1075,7 @@ dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, <&gpi_dma2 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1120,7 +1120,7 @@ dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, <&gpi_dma2 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1165,7 +1165,7 @@ dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, <&gpi_dma2 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1227,7 +1227,7 @@ dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, <&gpi_dma2 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1289,7 +1289,7 @@ dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, <&gpi_dma2 1 5 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1370,7 +1370,7 @@ dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, <&gpi_dma0 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1415,7 +1415,7 @@ dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, <&gpi_dma0 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1460,7 +1460,7 @@ dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, <&gpi_dma0 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1522,7 +1522,7 @@ dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, <&gpi_dma0 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1567,7 +1567,7 @@ dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, <&gpi_dma0 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1612,7 +1612,7 @@ dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, <&gpi_dma0 1 5 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1657,7 +1657,7 @@ dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, <&gpi_dma0 1 6 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1719,7 +1719,7 @@ dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, <&gpi_dma0 1 7 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1797,7 +1797,7 @@ dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, <&gpi_dma1 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1842,7 +1842,7 @@ dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, <&gpi_dma1 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1887,7 +1887,7 @@ dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, <&gpi_dma1 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1932,7 +1932,7 @@ dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, <&gpi_dma1 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1977,7 +1977,7 @@ dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, <&gpi_dma1 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -2039,7 +2039,7 @@ dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, <&gpi_dma1 1 5 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -2163,10 +2163,10 @@ "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, <&gcc GCC_PCIE_0_AUX_CLK>, @@ -2285,10 +2285,10 @@ "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_AUX_CLK>, @@ -2412,10 +2412,10 @@ "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, <&gcc GCC_PCIE_2_AUX_CLK>, @@ -4338,14 +4338,6 @@ status = "disabled"; - video-decoder { - compatible = "venus-decoder"; - }; - - video-encoder { - compatible = "venus-encoder"; - }; - venus_opp_table: opp-table { compatible = "operating-points-v2"; @@ -4779,16 +4771,20 @@ <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; @@ -4797,7 +4793,7 @@ #sound-dai-cells = <0>; operating-points-v2 = <&dp_opp_table>; - power-domains = <&rpmhpd SM8250_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; status = "disabled"; @@ -6092,6 +6088,7 @@ intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index f9de0e49fa24..24a8c91e9f70 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -385,15 +385,11 @@ &mdss_dsi0 { vdda-supply = <&vreg_l6b_1p2>; status = "okay"; +}; - ports { - port@1 { - endpoint { - remote-endpoint = <<9611_a>; - data-lanes = <0 1 2 3>; - }; - }; - }; +&mdss_dsi0_out { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; }; &mdss_dsi0_phy { diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 9a4207ead615..fc4ce9d4977e 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1551,10 +1551,10 @@ "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, @@ -1662,10 +1662,10 @@ "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, @@ -2876,16 +2876,20 @@ <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; @@ -3544,6 +3548,7 @@ intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; #redistributor-regions = <1>; diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 2ff40a120aad..0c6aa7ddf432 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -1199,11 +1199,6 @@ status = "okay"; }; -&usb_1_dwc3 { - dr_mode = "otg"; - usb-role-switch; -}; - &usb_1_dwc3_hs { remote-endpoint = <&pmic_glink_hs_in>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 8c39fbcaad80..56db5f79f59d 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -28,6 +28,49 @@ stdout-path = "serial0:115200n8"; }; + pmic-glink { + compatible = "qcom,sm8450-pmic-glink", "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 91 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + }; + }; + + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -461,8 +504,8 @@ status = "okay"; }; -&usb_1_dwc3 { - dr_mode = "peripheral"; +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; }; &usb_1_hsphy { @@ -487,3 +530,7 @@ vdda-phy-supply = <&vreg_l6b_1p2>; vdda-pll-supply = <&vreg_l1b_0p91>; }; + +&usb_1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8450-samsung-r0q.dts b/arch/arm64/boot/dts/qcom/sm8450-samsung-r0q.dts new file mode 100644 index 000000000000..880d74ae6032 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8450-samsung-r0q.dts @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> + +#include "sm8450.dtsi" +#include "pm8350.dtsi" +#include "pm8350c.dtsi" + +/ { + model = "Samsung Galaxy S22 5G"; + compatible = "samsung,r0q", "qcom,sm8450"; + chassis-type = "handset"; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer: framebuffer@b8000000 { + compatible = "simple-framebuffer"; + reg = <0x0 0xb8000000 0x0 0x2b00000>; + width = <1080>; + height = <2340>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + }; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + regulator-boot-on; + }; + + reserved-memory { + /* + * The bootloader will only keep display hardware enabled + * if this memory region is named exactly 'splash_region' + */ + splash-region@b8000000 { + reg = <0x0 0xb8000000 0x0 0x2b00000>; + no-map; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8350-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-s11-supply = <&vph_pwr>; + vdd-s12-supply = <&vph_pwr>; + + vdd-l2-l7-supply = <&vreg_bob>; + vdd-l3-l5-supply = <&vreg_bob>; + + vreg_l2b_3p07: ldo2 { + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5b_0p88: ldo5 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <888000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-1 { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l12-supply = <&vreg_bob>; + vdd-l2-l8-supply = <&vreg_bob>; + vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>; + vdd-l6-l9-l11-supply = <&vreg_bob>; + + vdd-bob-supply = <&vph_pwr>; + + vreg_bob: bob { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_l1c_1p8: ldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +&tlmm { + gpio-reserved-ranges = <36 4>; /* SPI (not linked to anything) */ +}; + +&usb_1 { + /* Keep USB 2.0 only for now */ + qcom,select-utmi-as-pipe-clk; + + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + /* Remove USB3 phy */ + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; + + status = "okay"; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l5b_0p88>; + vdda18-supply = <&vreg_l1c_1p8>; + vdda33-supply = <&vreg_l2b_3p07>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi index cc1335a07a35..6bd315e10992 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi @@ -781,11 +781,8 @@ }; &usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { dr_mode = "peripheral"; + status = "okay"; }; &usb_1_hsphy { diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 33574ad706b9..23420e692472 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1987,10 +1987,10 @@ "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, @@ -2151,10 +2151,10 @@ "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, @@ -3199,8 +3199,10 @@ reg = <0 0x0aaf0000 0 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_VIDEO_AHB_CLK>; - power-domains = <&rpmhpd RPMHPD_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; @@ -3291,12 +3293,13 @@ <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; - power-domains = <&rpmhpd RPMHPD_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - status = "disabled"; }; mdss: display-subsystem@ae00000 { @@ -3431,16 +3434,20 @@ <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; @@ -5417,13 +5424,10 @@ }; }; - usb_1: usb@a6f8800 { - compatible = "qcom,sm8450-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; + usb_1: usb@a600000 { + compatible = "qcom,sm8450-dwc3", "qcom,snps-dwc3"; + reg = <0 0x0a600000 0 0xfc100>; status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, @@ -5442,12 +5446,14 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event", + interrupt-names = "dwc_usb3", + "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", @@ -5461,36 +5467,32 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; interconnect-names = "usb-ddr", "apps-usb"; - usb_1_dwc3: usb@a600000 { - compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xcd00>; - interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; - iommus = <&apps_smmu 0x0 0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_u3_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; - phy-names = "usb2-phy", "usb3-phy"; + iommus = <&apps_smmu 0x0 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", "usb3-phy"; + usb-role-switch; - ports { - #address-cells = <1>; - #size-cells = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; - port@0 { - reg = <0>; + port@0 { + reg = <0>; - usb_1_dwc3_hs: endpoint { - }; + usb_1_dwc3_hs: endpoint { }; + }; - port@1 { - reg = <1>; + port@1 { + reg = <1>; - usb_1_dwc3_ss: endpoint { - remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; - }; + usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts index 9dfb248f9ab5..b5d7f0cd443a 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -859,8 +859,8 @@ vreg_l6n_3p3: ldo6 { regulator-name = "vreg_l6n_3p3"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3304000>; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; @@ -1002,10 +1002,6 @@ status = "okay"; }; -&mdss_dp0_out { - data-lanes = <0 1>; -}; - &pcie0 { wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index fdcecd41297d..38f2928f23cc 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -626,8 +626,8 @@ vreg_l6n_3p3: ldo6 { regulator-name = "vreg_l6n_3p3"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3304000>; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; @@ -738,10 +738,6 @@ status = "okay"; }; -&mdss_dp0_out { - data-lanes = <0 1>; -}; - &pcie0 { wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index 49438a7e77ce..a3f4200a1145 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -702,8 +702,8 @@ vreg_l6n_3p3: ldo6 { regulator-name = "vreg_l6n_3p3"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3304000>; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; @@ -857,10 +857,6 @@ status = "okay"; }; -&mdss_dp0_out { - data-lanes = <0 1>; -}; - &pcie0 { wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts index 7d29a57a2b54..b4ef40ae2cd9 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts @@ -487,8 +487,8 @@ vreg_l6n_3p3: ldo6 { regulator-name = "vreg_l6n_3p3"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3304000>; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 45713d46f3c5..7724dba75db7 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -399,22 +399,22 @@ pmu-a510 { compatible = "arm,cortex-a510-pmu"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; }; pmu-a710 { compatible = "arm,cortex-a710-pmu"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; }; pmu-a715 { compatible = "arm,cortex-a715-pmu"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster2>; }; pmu-x3 { compatible = "arm,cortex-x3-pmu"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster3>; }; psci { @@ -842,7 +842,7 @@ ipcc: mailbox@408000 { compatible = "qcom,sm8550-ipcc", "qcom,ipcc"; reg = <0 0x00408000 0 0x1000>; - interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-controller; #interrupt-cells = <3>; #mbox-cells = <2>; @@ -852,18 +852,18 @@ compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; #dma-cells = <3>; reg = <0 0x00800000 0 0x60000>; - interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH 0>; dma-channels = <12>; dma-channel-mask = <0x3e>; iommus = <&apps_smmu 0x436 0>; @@ -891,7 +891,7 @@ clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c8_data_clk>; - interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -914,7 +914,7 @@ reg = <0 0x00880000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; - interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -941,7 +941,7 @@ clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c9_data_clk>; - interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -964,7 +964,7 @@ reg = <0 0x00884000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; - interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -991,7 +991,7 @@ clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c10_data_clk>; - interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -1014,7 +1014,7 @@ reg = <0 0x00888000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; - interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -1041,7 +1041,7 @@ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c11_data_clk>; - interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -1064,7 +1064,7 @@ reg = <0 0x0088c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; - interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -1091,7 +1091,7 @@ clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c12_data_clk>; - interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -1114,7 +1114,7 @@ reg = <0 0x00890000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; - interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -1141,7 +1141,7 @@ clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c13_data_clk>; - interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -1164,7 +1164,7 @@ reg = <0 0x00894000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; - interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -1191,7 +1191,7 @@ clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; - interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH 0>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY @@ -1209,7 +1209,7 @@ clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c15_data_clk>; - interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -1232,7 +1232,7 @@ reg = <0 0x0089c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; - interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -1271,7 +1271,7 @@ <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names = "default"; pinctrl-0 = <&hub_i2c0_data_clk>; - interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS @@ -1292,7 +1292,7 @@ <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names = "default"; pinctrl-0 = <&hub_i2c1_data_clk>; - interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS @@ -1313,7 +1313,7 @@ <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names = "default"; pinctrl-0 = <&hub_i2c2_data_clk>; - interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS @@ -1334,7 +1334,7 @@ <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names = "default"; pinctrl-0 = <&hub_i2c3_data_clk>; - interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS @@ -1355,7 +1355,7 @@ <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names = "default"; pinctrl-0 = <&hub_i2c4_data_clk>; - interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS @@ -1376,7 +1376,7 @@ <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names = "default"; pinctrl-0 = <&hub_i2c5_data_clk>; - interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS @@ -1397,7 +1397,7 @@ <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names = "default"; pinctrl-0 = <&hub_i2c6_data_clk>; - interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS @@ -1418,7 +1418,7 @@ <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names = "default"; pinctrl-0 = <&hub_i2c7_data_clk>; - interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS @@ -1439,7 +1439,7 @@ <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names = "default"; pinctrl-0 = <&hub_i2c8_data_clk>; - interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS @@ -1460,7 +1460,7 @@ <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names = "default"; pinctrl-0 = <&hub_i2c9_data_clk>; - interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS @@ -1478,18 +1478,18 @@ compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; #dma-cells = <3>; reg = <0 0x00a00000 0 0x60000>; - interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>; dma-channels = <12>; dma-channel-mask = <0x1e>; iommus = <&apps_smmu 0xb6 0>; @@ -1520,7 +1520,7 @@ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c0_data_clk>; - interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1543,7 +1543,7 @@ reg = <0 0x00a80000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1570,7 +1570,7 @@ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c1_data_clk>; - interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1593,7 +1593,7 @@ reg = <0 0x00a84000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1620,7 +1620,7 @@ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c2_data_clk>; - interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1643,7 +1643,7 @@ reg = <0 0x00a88000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1670,7 +1670,7 @@ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c3_data_clk>; - interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1693,7 +1693,7 @@ reg = <0 0x00a8c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1720,7 +1720,7 @@ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c4_data_clk>; - interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1743,7 +1743,7 @@ reg = <0 0x00a90000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1770,7 +1770,7 @@ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c5_data_clk>; - interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY @@ -1793,7 +1793,7 @@ reg = <0 0x00a94000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1820,7 +1820,7 @@ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c6_data_clk>; - interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY @@ -1843,7 +1843,7 @@ reg = <0 0x00a98000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; - interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1870,7 +1870,7 @@ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart7_default>; - interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH 0>; interconnect-names = "qup-core", "qup-config"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, @@ -1961,15 +1961,15 @@ linux,pci-domain = <0>; num-lanes = <2>; - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "msi0", "msi1", "msi2", @@ -1981,10 +1981,10 @@ "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>, /* int_a */ + <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>, /* int_b */ + <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>, /* int_c */ + <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; /* int_d */ clocks = <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, @@ -2122,15 +2122,15 @@ linux,pci-domain = <1>; num-lanes = <2>; - interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "msi0", "msi1", "msi2", @@ -2142,10 +2142,10 @@ "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH 0>, /* int_a */ + <0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>, /* int_b */ + <0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>, /* int_c */ + <0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>; /* int_d */ clocks = <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, @@ -2280,7 +2280,7 @@ cryptobam: dma-controller@1dc4000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0x0 0x01dc4000 0x0 0x28000>; - interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <1>; qcom,ee = <0>; qcom,num-ees = <4>; @@ -2327,7 +2327,7 @@ compatible = "qcom,sm8550-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0x0 0x01d84000 0x0 0x3000>; - interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; phys = <&ufs_mem_phy>; phy-names = "ufsphy"; lanes-per-direction = <2>; @@ -2440,7 +2440,7 @@ "cx_mem", "cx_dbgc"; - interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>; iommus = <&adreno_smmu 0 0x0>, <&adreno_smmu 1 0x0>; @@ -2521,8 +2521,8 @@ <0x0 0x0b280000 0x0 0x10000>; reg-names = "gmu", "rscc", "gmu_pdc"; - interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "hfi", "gmu"; clocks = <&gpucc GPU_CC_AHB_CLK>, @@ -2583,32 +2583,32 @@ reg = <0x0 0x03da0000 0x0 0x40000>; #iommu-cells = <2>; #global-interrupts = <1>; - interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, @@ -2633,8 +2633,8 @@ "ipa-shared", "gsi"; - interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, - <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING 0>, + <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH 0>, <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; interrupt-names = "ipa", @@ -2666,7 +2666,7 @@ compatible = "qcom,sm8550-mpss-pas"; reg = <0x0 0x04080000 0x0 0x10000>; - interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, + interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING 0>, <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, @@ -2854,7 +2854,7 @@ swr3: soundwire@6ab0000 { compatible = "qcom,soundwire-v2.0.0"; reg = <0 0x06ab0000 0 0x10000>; - interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&lpass_wsa2macro>; clock-names = "iface"; label = "WSA2"; @@ -2898,7 +2898,7 @@ swr1: soundwire@6ad0000 { compatible = "qcom,soundwire-v2.0.0"; reg = <0 0x06ad0000 0 0x10000>; - interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&lpass_rxmacro>; clock-names = "iface"; label = "RX"; @@ -2956,7 +2956,7 @@ swr0: soundwire@6b10000 { compatible = "qcom,soundwire-v2.0.0"; reg = <0 0x06b10000 0 0x10000>; - interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&lpass_wsamacro>; clock-names = "iface"; label = "WSA"; @@ -2986,8 +2986,8 @@ swr2: soundwire@6d30000 { compatible = "qcom,soundwire-v2.0.0"; reg = <0 0x06d30000 0 0x10000>; - interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "core", "wakeup"; clocks = <&lpass_txmacro>; clock-names = "iface"; @@ -3169,8 +3169,8 @@ compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; - interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC2_AHB_CLK>, @@ -3225,7 +3225,7 @@ compatible = "qcom,sm8550-iris"; reg = <0 0x0aa00000 0 0xf0000>; - interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, <&videocc VIDEO_CC_MVS0_GDSC>, @@ -3262,7 +3262,7 @@ /* * IRIS firmware is signed by vendors, only - * enable in boards where the proper signed firmware + * enable on boards where the proper signed firmware * is available. */ status = "disabled"; @@ -3307,8 +3307,10 @@ reg = <0 0x0aaf0000 0 0x10000>; clocks = <&bi_tcxo_div2>, <&gcc GCC_VIDEO_AHB_CLK>; - power-domains = <&rpmhpd RPMHPD_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; @@ -3317,7 +3319,7 @@ cci0: cci@ac15000 { compatible = "qcom,sm8550-cci", "qcom,msm8996-cci"; reg = <0 0x0ac15000 0 0x1000>; - interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING>; + interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING 0>; power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, <&camcc CAM_CC_CPAS_AHB_CLK>, @@ -3350,7 +3352,7 @@ cci1: cci@ac16000 { compatible = "qcom,sm8550-cci", "qcom,msm8996-cci"; reg = <0 0x0ac16000 0 0x1000>; - interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING>; + interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING 0>; power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, <&camcc CAM_CC_CPAS_AHB_CLK>, @@ -3376,7 +3378,7 @@ cci2: cci@ac17000 { compatible = "qcom,sm8550-cci", "qcom,msm8996-cci"; reg = <0 0x0ac17000 0 0x1000>; - interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING>; + interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING 0>; power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, <&camcc CAM_CC_CPAS_AHB_CLK>, @@ -3521,24 +3523,24 @@ "vfe_lite_cphy_rx", "vfe_lite_csid"; - interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 278 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 602 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 688 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>; + interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 603 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 431 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 605 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 376 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 89 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 278 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 277 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 602 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 604 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 688 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 606 IRQ_TYPE_EDGE_RISING 0>, + <GIC_SPI 377 IRQ_TYPE_EDGE_RISING 0>; interrupt-names = "csid0", "csid1", "csid2", @@ -3623,8 +3625,10 @@ <&bi_tcxo_div2>, <&bi_tcxo_ao_div2>, <&sleep_clk>; - power-domains = <&rpmhpd SM8550_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; @@ -3635,7 +3639,7 @@ reg = <0 0x0ae00000 0 0x1000>; reg-names = "mdss"; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-controller; #interrupt-cells = <1>; @@ -3755,16 +3759,20 @@ <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; @@ -3791,6 +3799,7 @@ port@1 { reg = <1>; mdss_dp0_out: endpoint { + data-lanes = <0 1 2 3>; remote-endpoint = <&usb_dp_qmpphy_dp_in>; }; }; @@ -4051,6 +4060,7 @@ #clock-cells = <1>; #phy-cells = <1>; + mode-switch; orientation-switch; status = "disabled"; @@ -4084,12 +4094,11 @@ }; }; - usb_1: usb@a6f8800 { - compatible = "qcom,sm8550-dwc3", "qcom,dwc3"; - reg = <0x0 0x0a6f8800 0x0 0x400>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + usb_1: usb@a600000 { + compatible = "qcom,sm8550-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a600000 0x0 0xfc100>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, @@ -4108,12 +4117,14 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event", + interrupt-names = "dwc_usb3", + "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", @@ -4130,47 +4141,46 @@ &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "usb-ddr", "apps-usb"; - status = "disabled"; + iommus = <&apps_smmu 0x40 0x0>; - usb_1_dwc3: usb@a600000 { - compatible = "snps,dwc3"; - reg = <0x0 0x0a600000 0x0 0xcd00>; - interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; - iommus = <&apps_smmu 0x40 0x0>; - phys = <&usb_1_hsphy>, - <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; - phy-names = "usb2-phy", "usb3-phy"; - snps,hird-threshold = /bits/ 8 <0x0>; - snps,usb2-gadget-lpm-disable; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - snps,is-utmi-l1-suspend; - snps,usb3_lpm_capable; - snps,usb2-lpm-disable; - snps,has-lpm-erratum; - tx-fifo-resize; - dma-coherent; - usb-role-switch; + phys = <&usb_1_hsphy>, + <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", "usb3-phy"; - ports { - #address-cells = <1>; - #size-cells = <0>; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,usb2-gadget-lpm-disable; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,usb2-lpm-disable; + snps,has-lpm-erratum; + tx-fifo-resize; - port@0 { - reg = <0>; + dma-coherent; - usb_1_dwc3_hs: endpoint { - }; + usb-role-switch; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { }; + }; - port@1 { - reg = <1>; + port@1 { + reg = <1>; - usb_1_dwc3_ss: endpoint { - remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; - }; + usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; }; }; }; @@ -4192,8 +4202,8 @@ reg = <0 0x0c271000 0 0x1000>, /* TM */ <0 0x0c222000 0 0x1000>; /* SROT */ #qcom,sensors = <16>; - interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; }; @@ -4203,8 +4213,8 @@ reg = <0 0x0c272000 0 0x1000>, /* TM */ <0 0x0c223000 0 0x1000>; /* SROT */ #qcom,sensors = <16>; - interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; }; @@ -4214,8 +4224,8 @@ reg = <0 0x0c273000 0 0x1000>, /* TM */ <0 0x0c224000 0 0x1000>; /* SROT */ #qcom,sensors = <16>; - interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; }; @@ -4259,7 +4269,7 @@ tlmm: pinctrl@f100000 { compatible = "qcom,sm8550-tlmm"; reg = <0 0x0f100000 0 0x300000>; - interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 0>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -4953,103 +4963,103 @@ reg = <0 0x15000000 0 0x100000>; #iommu-cells = <2>; #global-interrupts = <1>; - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH 0>; dma-coherent; }; @@ -5058,14 +5068,32 @@ reg = <0 0x17100000 0 0x10000>, /* GICD */ <0 0x17180000 0 0x200000>; /* GICR * 8 */ ranges; - #interrupt-cells = <3>; + #interrupt-cells = <4>; interrupt-controller; #redistributor-regions = <1>; redistributor-stride = <0 0x40000>; - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW 0>; #address-cells = <2>; #size-cells = <2>; + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu3 &cpu4>; + }; + + ppi_cluster2: interrupt-partition-2 { + affinity = <&cpu5 &cpu6>; + }; + + ppi_cluster3: interrupt-partition-3 { + affinity = <&cpu7>; + }; + }; + gic_its: msi-controller@17140000 { compatible = "arm,gic-v3-its"; reg = <0 0x17140000 0 0x20000>; @@ -5085,49 +5113,49 @@ reg = <0x17421000 0x1000>, <0x17422000 0x1000>; frame-number = <0>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; }; frame@17423000 { reg = <0x17423000 0x1000>; frame-number = <1>; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; status = "disabled"; }; frame@17425000 { reg = <0x17425000 0x1000>; frame-number = <2>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; status = "disabled"; }; frame@17427000 { reg = <0x17427000 0x1000>; frame-number = <3>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; status = "disabled"; }; frame@17429000 { reg = <0x17429000 0x1000>; frame-number = <4>; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; status = "disabled"; }; frame@1742b000 { reg = <0x1742b000 0x1000>; frame-number = <5>; - interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>; status = "disabled"; }; frame@1742d000 { reg = <0x1742d000 0x1000>; frame-number = <6>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; status = "disabled"; }; }; @@ -5140,9 +5168,9 @@ <0 0x17a20000 0 0x10000>, <0 0x17a30000 0 0x10000>; reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>; qcom,tcs-offset = <0xd00>; qcom,drv-id = <2>; qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, @@ -5239,9 +5267,9 @@ reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; clock-names = "xo", "alternate"; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; #freq-domain-cells = <1>; #clock-cells = <1>; @@ -5250,7 +5278,7 @@ pmu@24091000 { compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; reg = <0 0x24091000 0 0x1000>; - interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; @@ -5300,7 +5328,7 @@ pmu@240b6400 { compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon"; reg = <0 0x240b6400 0 0x600>; - interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH 0>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; @@ -5356,7 +5384,7 @@ "llcc3_base", "llcc_broadcast_base", "llcc_broadcast_and_base"; - interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH 0>; }; nsp_noc: interconnect@320c0000 { @@ -5370,7 +5398,7 @@ compatible = "qcom,sm8550-cdsp-pas"; reg = <0x0 0x32300000 0x0 0x10000>; - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>, <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, @@ -6552,9 +6580,9 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk-display-card.dtso b/arch/arm64/boot/dts/qcom/sm8650-hdk-display-card.dtso index cb102535838d..5a594d7311a7 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk-display-card.dtso +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk-display-card.dtso @@ -60,19 +60,10 @@ }; }; }; +}; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - mdss_dsi0_out: endpoint { - remote-endpoint = <&panel0_in>; - }; - }; - }; +&mdss_dsi0_out { + remote-endpoint = <&panel0_in>; }; &spi4 { diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts index 259649d7dcd7..87d7190dc991 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -941,10 +941,6 @@ status = "okay"; }; -&mdss_dp0_out { - data-lanes = <0 1>; -}; - &pcie0 { wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; @@ -1050,10 +1046,6 @@ vdd3-supply = <&vreg_l5b_3p1>; }; -&pmk8550_rtc { - status = "okay"; -}; - &pon_pwrkey { status = "okay"; }; @@ -1310,12 +1302,10 @@ */ &usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { dr_mode = "otg"; usb-role-switch; + + status = "okay"; }; &usb_1_dwc3_hs { diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts index 8a957adbfb38..c67bbace2743 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -857,12 +857,10 @@ */ &usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { dr_mode = "otg"; usb-role-switch; + + status = "okay"; }; &usb_1_dwc3_hs { diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index 7552d5d3fb40..9e790cf44804 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -892,10 +892,6 @@ status = "okay"; }; -&mdss_dp0_out { - data-lanes = <0 1>; -}; - &pcie0 { wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; @@ -1006,10 +1002,6 @@ vdd3-supply = <&vreg_l5b_3p1>; }; -&pmk8550_rtc { - status = "okay"; -}; - &qup_i2c3_data_clk { /* Use internal I2C pull-up */ bias-pull-up = <2200>; @@ -1293,12 +1285,10 @@ */ &usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { dr_mode = "otg"; usb-role-switch; + + status = "okay"; }; &usb_1_dwc3_hs { diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index e14d3d778b71..ebf1971b1bfb 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -3490,6 +3490,11 @@ }; }; + rng: rng@10c3000 { + compatible = "qcom,sm8650-trng", "qcom,trng"; + reg = <0 0x010c3000 0 0x1000>; + }; + cnoc_main: interconnect@1500000 { compatible = "qcom,sm8650-cnoc-main"; reg = <0 0x01500000 0 0x14080>; @@ -3561,11 +3566,6 @@ #interconnect-cells = <2>; }; - rng: rng@10c3000 { - compatible = "qcom,sm8650-trng", "qcom,trng"; - reg = <0 0x010c3000 0 0x1000>; - }; - pcie0: pcie@1c00000 { device_type = "pci"; compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; @@ -3629,10 +3629,10 @@ iommu-map = <0 &apps_smmu 0x1400 0x1>, <0x100 &apps_smmu 0x1401 0x1>; - interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH 0>, - <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH 0>, - <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH 0>, - <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-map-mask = <0 0 0 0x7>; #interrupt-cells = <1>; @@ -3809,10 +3809,10 @@ iommu-map = <0 &apps_smmu 0x1480 0x1>, <0x100 &apps_smmu 0x1481 0x1>; - interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH 0>, - <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH 0>, - <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH 0>, - <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-map-mask = <0 0 0 0x7>; #interrupt-cells = <1>; @@ -3926,38 +3926,6 @@ status = "disabled"; }; - cryptobam: dma-controller@1dc4000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0 0x01dc4000 0 0x28000>; - - interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>; - - #dma-cells = <1>; - - iommus = <&apps_smmu 0x480 0>, - <&apps_smmu 0x481 0>; - - qcom,ee = <0>; - qcom,num-ees = <4>; - num-channels = <20>; - qcom,controlled-remotely; - }; - - crypto: crypto@1dfa000 { - compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce"; - reg = <0 0x01dfa000 0 0x6000>; - - interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "memory"; - - dmas = <&cryptobam 4>, <&cryptobam 5>; - dma-names = "rx", "tx"; - - iommus = <&apps_smmu 0x480 0>, - <&apps_smmu 0x481 0>; - }; - ufs_mem_phy: phy@1d80000 { compatible = "qcom,sm8650-qmp-ufs-phy"; reg = <0 0x01d80000 0 0x2000>; @@ -4079,6 +4047,38 @@ clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0 0x01dc4000 0 0x28000>; + + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>; + + #dma-cells = <1>; + + iommus = <&apps_smmu 0x480 0>, + <&apps_smmu 0x481 0>; + + qcom,ee = <0>; + qcom,num-ees = <4>; + num-channels = <20>; + qcom,controlled-remotely; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0 0x01dfa000 0 0x6000>; + + interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "memory"; + + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + + iommus = <&apps_smmu 0x480 0>, + <&apps_smmu 0x481 0>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0 0x01f40000 0 0x20000>; @@ -4127,72 +4127,84 @@ /* Speedbin needs more work on A740+, keep only lower freqs */ gpu_opp_table: opp-table { - compatible = "operating-points-v2"; + compatible = "operating-points-v2-adreno", + "operating-points-v2"; opp-231000000 { opp-hz = /bits/ 64 <231000000>; opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0xc82f5ffd>; }; opp-310000000 { opp-hz = /bits/ 64 <310000000>; opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0xc82c5ffd>; }; opp-366000000 { opp-hz = /bits/ 64 <366000000>; opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; opp-peak-kBps = <6074218>; + qcom,opp-acd-level = <0xc02e5ffd>; }; opp-422000000 { opp-hz = /bits/ 64 <422000000>; opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; opp-peak-kBps = <8171875>; + qcom,opp-acd-level = <0xc02d5ffd>; }; opp-500000000 { opp-hz = /bits/ 64 <500000000>; opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; opp-peak-kBps = <8171875>; + qcom,opp-acd-level = <0xc02a5ffd>; }; opp-578000000 { opp-hz = /bits/ 64 <578000000>; opp-level = <RPMH_REGULATOR_LEVEL_SVS>; opp-peak-kBps = <8171875>; + qcom,opp-acd-level = <0x882c5ffd>; }; opp-629000000 { opp-hz = /bits/ 64 <629000000>; opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; opp-peak-kBps = <10687500>; + qcom,opp-acd-level = <0x882a5ffd>; }; opp-680000000 { opp-hz = /bits/ 64 <680000000>; opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; opp-peak-kBps = <12449218>; + qcom,opp-acd-level = <0x882a5ffd>; }; opp-720000000 { opp-hz = /bits/ 64 <720000000>; opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; opp-peak-kBps = <12449218>; + qcom,opp-acd-level = <0x882a5ffd>; }; opp-770000000 { opp-hz = /bits/ 64 <770000000>; opp-level = <RPMH_REGULATOR_LEVEL_NOM>; opp-peak-kBps = <12449218>; + qcom,opp-acd-level = <0x882a5ffd>; }; opp-834000000 { opp-hz = /bits/ 64 <834000000>; opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; opp-peak-kBps = <14398437>; + qcom,opp-acd-level = <0x882a5ffd>; }; }; }; @@ -4962,6 +4974,171 @@ }; }; + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,sm8650-snps-eusb2-phy", + "qcom,sm8550-snps-eusb2-phy"; + reg = <0 0x088e3000 0 0x154>; + + clocks = <&tcsr TCSR_USB2_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_dp_qmpphy: phy@88e8000 { + compatible = "qcom,sm8650-qmp-usb3-dp-phy"; + reg = <0 0x088e8000 0 0x3000>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe"; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; + reset-names = "phy", + "common"; + + power-domains = <&gcc USB3_PHY_GDSC>; + + #clock-cells = <1>; + #phy-cells = <1>; + + mode-switch; + orientation-switch; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dp_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_dp_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_dp_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; + }; + }; + }; + }; + + usb_1: usb@a600000 { + compatible = "qcom,sm8650-dwc3", "qcom,snps-dwc3"; + reg = <0 0x0a600000 0 0xfc100>; + + interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, + <&pdc 14 IRQ_TYPE_EDGE_RISING>, + <&pdc 15 IRQ_TYPE_EDGE_RISING>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dwc_usb3", + "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&tcsr TCSR_USB3_CLKREF_EN>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + phys = <&usb_1_hsphy>, + <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "usb-ddr", + "apps-usb"; + + iommus = <&apps_smmu 0x40 0>; + + power-domains = <&gcc USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + snps,hird-threshold = /bits/ 8 <0x0>; + snps,usb2-gadget-lpm-disable; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,usb2-lpm-disable; + snps,has-lpm-erratum; + tx-fifo-resize; + + dma-coherent; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; + }; + }; + }; + }; + iris: video-codec@aa00000 { compatible = "qcom,sm8650-iris"; reg = <0 0x0aa00000 0 0xf0000>; @@ -5009,7 +5186,7 @@ /* * IRIS firmware is signed by vendors, only - * enable in boards where the proper signed firmware + * enable on boards where the proper signed firmware * is available. */ status = "disabled"; @@ -5060,7 +5237,8 @@ reg = <0 0x0aaf0000 0 0x10000>; clocks = <&bi_tcxo_div2>, <&gcc GCC_VIDEO_AHB_CLK>; - power-domains = <&rpmhpd RPMHPD_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; @@ -5172,7 +5350,8 @@ <&bi_tcxo_div2>, <&bi_tcxo_ao_div2>, <&sleep_clk>; - power-domains = <&rpmhpd RPMHPD_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; @@ -5481,16 +5660,20 @@ <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; operating-points-v2 = <&dp_opp_table>; @@ -5544,6 +5727,7 @@ reg = <1>; mdss_dp0_out: endpoint { + data-lanes = <0 1 2 3>; remote-endpoint = <&usb_dp_qmpphy_dp_in>; }; }; @@ -5580,176 +5764,6 @@ #power-domain-cells = <1>; }; - usb_1_hsphy: phy@88e3000 { - compatible = "qcom,sm8650-snps-eusb2-phy", - "qcom,sm8550-snps-eusb2-phy"; - reg = <0 0x088e3000 0 0x154>; - - clocks = <&tcsr TCSR_USB2_CLKREF_EN>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - - #phy-cells = <0>; - - status = "disabled"; - }; - - usb_dp_qmpphy: phy@88e8000 { - compatible = "qcom,sm8650-qmp-usb3-dp-phy"; - reg = <0 0x088e8000 0 0x3000>; - - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, - <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "aux", - "ref", - "com_aux", - "usb3_pipe"; - - resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, - <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; - reset-names = "phy", - "common"; - - power-domains = <&gcc USB3_PHY_GDSC>; - - #clock-cells = <1>; - #phy-cells = <1>; - - orientation-switch; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usb_dp_qmpphy_out: endpoint { - }; - }; - - port@1 { - reg = <1>; - - usb_dp_qmpphy_usb_ss_in: endpoint { - remote-endpoint = <&usb_1_dwc3_ss>; - }; - }; - - port@2 { - reg = <2>; - - usb_dp_qmpphy_dp_in: endpoint { - remote-endpoint = <&mdss_dp0_out>; - }; - }; - }; - }; - - usb_1: usb@a6f8800 { - compatible = "qcom,sm8650-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; - - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, - <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, - <&pdc 14 IRQ_TYPE_EDGE_RISING>, - <&pdc 15 IRQ_TYPE_EDGE_RISING>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event", - "hs_phy_irq", - "dp_hs_phy_irq", - "dm_hs_phy_irq", - "ss_phy_irq"; - - clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&tcsr TCSR_USB3_CLKREF_EN>; - clock-names = "cfg_noc", - "core", - "iface", - "sleep", - "mock_utmi", - "xo"; - - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - - resets = <&gcc GCC_USB30_PRIM_BCR>; - - interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "usb-ddr", - "apps-usb"; - - power-domains = <&gcc USB30_PRIM_GDSC>; - required-opps = <&rpmhpd_opp_nom>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - status = "disabled"; - - usb_1_dwc3: usb@a600000 { - compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xcd00>; - - interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>; - - iommus = <&apps_smmu 0x40 0>; - - phys = <&usb_1_hsphy>, - <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; - phy-names = "usb2-phy", - "usb3-phy"; - - snps,hird-threshold = /bits/ 8 <0x0>; - snps,usb2-gadget-lpm-disable; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - snps,is-utmi-l1-suspend; - snps,usb3_lpm_capable; - snps,usb2-lpm-disable; - snps,has-lpm-erratum; - tx-fifo-resize; - - dma-coherent; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usb_1_dwc3_hs: endpoint { - }; - }; - - port@1 { - reg = <1>; - - usb_1_dwc3_ss: endpoint { - remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; - }; - }; - }; - }; - }; - pdc: interrupt-controller@b220000 { compatible = "qcom,sm8650-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts index 75cfbb510be5..3bbb53b7c71f 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts @@ -201,6 +201,74 @@ regulator-always-on; regulator-boot-on; }; + + /* + * MTPs rev 2.0 (power grid v8) come with two different WiFi chips: + * WCN7850 and WCN786x. + * Device nodes here for the PMU, WiFi and Bluetooth describe the MTP + * variant with WCN7850. + */ + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_en>, <&bt_default>; + + wlan-enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&pm8550ve_f_gpios 3 GPIO_ACTIVE_HIGH>; + + vdd-supply = <&vreg_s5f_0p85>; + vddio-supply = <&vreg_l3f_1p8>; + vddio1p2-supply = <&vreg_l2f_1p2>; + vddaon-supply = <&vreg_s4d_0p85>; + vdddig-supply = <&vreg_s1d_0p97>; + vddrfa1p2-supply = <&vreg_s7i_1p2>; + vddrfa1p8-supply = <&vreg_s3g_1p8>; + + clocks = <&rpmhcc RPMH_RF_CLK1>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &apps_rsc { @@ -426,7 +494,7 @@ vreg_s4d_0p85: smps4 { regulator-name = "vreg_s4d_0p85"; - regulator-min-microvolt = <500000>; + regulator-min-microvolt = <852000>; regulator-max-microvolt = <1036000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; @@ -472,9 +540,9 @@ qcom,pmic-id = "f"; - vreg_s5f_0p5: smps5 { - regulator-name = "vreg_s5f_0p5"; - regulator-min-microvolt = <500000>; + vreg_s5f_0p85: smps5 { + regulator-name = "vreg_s5f_0p85"; + regulator-min-microvolt = <852000>; regulator-max-microvolt = <1000000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; @@ -891,6 +959,40 @@ status = "okay"; }; +&pcie0 { + wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l1f_0p88>; + vdda-pll-supply = <&vreg_l3g_1p2>; + + status = "okay"; +}; + +&pcieport0 { + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + &pmih0108_eusb2_repeater { status = "okay"; @@ -902,6 +1004,10 @@ status = "okay"; }; +&qupv3_2 { + status = "okay"; +}; + &remoteproc_adsp { firmware-name = "qcom/sm8750/adsp.mbn", "qcom/sm8750/adsp_dtb.mbn"; @@ -938,6 +1044,13 @@ sound-name-prefix = "SpkrLeft"; #thermal-sensor-cells = <0>; vdd-supply = <&vreg_l15b_1p8>; + /* + * WSA8835 Port 1 (DAC) <=> SWR0 Port 1 (SPKR_L) + * WSA8835 Port 2 (COMP) <=> SWR0 Port 2 (SPKR_L_COMP) + * WSA8835 Port 3 (BOOST) <=> SWR0 Port 3 (SPKR_L_BOOST) + * WSA8835 Port 4 (VISENSE) <=> SWR0 Port 10 (SPKR_L_VI) + */ + qcom,port-mapping = <1 2 3 10>; }; /* WSA883x, right/back speaker */ @@ -951,6 +1064,13 @@ sound-name-prefix = "SpkrRight"; #thermal-sensor-cells = <0>; vdd-supply = <&vreg_l15b_1p8>; + /* + * WSA8835 Port 1 (DAC) <=> SWR0 Port 4 (SPKR_R) + * WSA8835 Port 2 (COMP) <=> SWR0 Port 5 (SPKR_R_COMP) + * WSA8835 Port 3 (BOOST) <=> SWR0 Port 6 (SPKR_R_BOOST) + * WSA8835 Port 4 (VISENSE) <=> SWR0 Port 11 (SPKR_R_VI) + */ + qcom,port-mapping = <4 5 6 11>; }; }; @@ -1021,6 +1141,14 @@ }; &tlmm { + bt_default: bt-default-state { + sw-ctrl-pins { + pins = "gpio18"; + function = "gpio"; + bias-pull-down; + }; + }; + wcd_default: wcd-reset-n-active-state { pins = "gpio101"; function = "gpio"; @@ -1028,6 +1156,31 @@ bias-disable; output-low; }; + + wlan_en: wlan-en-state { + pins = "gpio16"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + + max-speed = <3200000>; + }; }; &ufs_mem_phy { diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 4643705021c6..a82d9867c7cb 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -631,7 +631,7 @@ clocks = <&bi_tcxo_div2>, <0>, <&sleep_clk>, - <0>, + <&pcie0_phy>, <0>, <0>, <0>, @@ -3304,6 +3304,184 @@ }; }; + pcie0: pcie@1c00000 { + device_type = "pci"; + compatible = "qcom,pcie-sm8750", "qcom,pcie-sm8550"; + reg = <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf1d>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x1000>, + <0x0 0x40100000 0x0 0x100000>, + <0x0 0x01C03000 0x0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x23d00000>, + <0x03000000 0x4 0x00000000 0x4 0x00000000 0x3 0x00000000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <0>; + + msi-map = <0x0 &gic_its 0x1400 0x1>, + <0x100 &gic_its 0x1401 0x1>; + msi-map-mask = <0xff00>; + + num-lanes = <2>; + + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "noc_aggr", + "cnoc_sf_axi"; + + interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + iommu-map = <0x0 &apps_smmu 0x1400 0x1>, + <0x100 &apps_smmu 0x1401 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + power-domains = <&gcc GCC_PCIE_0_GDSC>; + + operating-points-v2 = <&pcie0_opp_table>; + + status = "disabled"; + + pcie0_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + }; + + /* GEN 2 x2 */ + opp-10000000 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <984500 1>; + }; + + /* GEN 3 x2 */ + opp-16000000 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <1969000 1>; + }; + + }; + + pcieport0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + phys = <&pcie0_phy>; + }; + }; + + pcie0_phy: phy@1c06000 { + compatible = "qcom,sm8750-qmp-gen3x2-pcie-phy"; + reg = <0 0x01c06000 0 0x2000>; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&tcsrcc TCSR_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe"; + + assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + power-domains = <&gcc GCC_PCIE_0_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie0_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + ufs_mem_phy: phy@1d80000 { compatible = "qcom,sm8750-qmp-ufs-phy"; reg = <0x0 0x01d80000 0x0 0x2000>; @@ -3617,6 +3795,82 @@ }; }; + /* cluster0 */ + pmu@240b3400 { + compatible = "qcom,sm8750-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0x0 0x240b3400 0x0 0x600>; + + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + + nonposted-mmio; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <800000>; + }; + + opp-1 { + opp-peak-kBps = <2188000>; + }; + + opp-2 { + opp-peak-kBps = <5414400>; + }; + + opp-3 { + opp-peak-kBps = <6220800>; + }; + + opp-4 { + opp-peak-kBps = <6835200>; + }; + + opp-5 { + opp-peak-kBps = <8371200>; + }; + + opp-6 { + opp-peak-kBps = <10944000>; + }; + + opp-7 { + opp-peak-kBps = <12748800>; + }; + + opp-8 { + opp-peak-kBps = <14745600>; + }; + + opp-9 { + opp-peak-kBps = <16896000>; + }; + + opp-10 { + opp-peak-kBps = <19046400>; + }; + }; + }; + + /* cluster1 */ + pmu@240b7400 { + compatible = "qcom,sm8750-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0x0 0x240b7400 0x0 0x600>; + + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + }; + gem_noc: interconnect@24100000 { compatible = "qcom,sm8750-gem-noc"; reg = <0x0 0x24100000 0x0 0x14b080>; diff --git a/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi b/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi index c771fd1d8029..ee3c8c5e2c50 100644 --- a/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi @@ -985,7 +985,6 @@ }; &mdss_dp0_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; @@ -994,13 +993,15 @@ }; &mdss_dp1_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; &mdss_dp3 { /delete-property/ #sound-dai-cells; + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + status = "okay"; aux-bus { @@ -1019,19 +1020,13 @@ }; }; }; +}; - ports { - port@1 { - reg = <1>; - - mdss_dp3_out: endpoint { - data-lanes = <0 1 2 3>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - remote-endpoint = <&edp_panel_in>; - }; - }; - }; + remote-endpoint = <&edp_panel_in>; }; &mdss_dp3_phy { diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi index c9f0d5052670..3c9455fede5c 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -1016,6 +1016,27 @@ }; }; +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + eusb6_repeater: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + + vdd1v8-supply = <&vreg_l4b_1p8>; + vdd3v3-supply = <&vreg_l13b_3p0>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb6_reset_n>; + pinctrl-names = "default"; + + #phy-cells = <0>; + }; +}; + &i2c7 { clock-frequency = <400000>; @@ -1128,7 +1149,7 @@ }; &mdss_dp0_out { - data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; &mdss_dp1 { @@ -1136,7 +1157,7 @@ }; &mdss_dp1_out { - data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; &mdss_dp2 { @@ -1144,12 +1165,15 @@ }; &mdss_dp2_out { - data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; &mdss_dp3 { /delete-property/ #sound-dai-cells; + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + status = "okay"; aux-bus { @@ -1168,18 +1192,13 @@ }; }; }; +}; - ports { - port@1 { - reg = <1>; - mdss_dp3_out: endpoint { - data-lanes = <0 1 2 3>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - remote-endpoint = <&edp_panel_in>; - }; - }; - }; + remote-endpoint = <&edp_panel_in>; }; &mdss_dp3_phy { @@ -1466,6 +1485,14 @@ bias-disable; }; + eusb6_reset_n: eusb6-reset-n-state { + pins = "gpio184"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + hall_int_n_default: hall-int-n-state { pins = "gpio92"; function = "gpio"; @@ -1747,3 +1774,38 @@ &usb_1_ss2_qmpphy_out { remote-endpoint = <&retimer_ss2_ss_in>; }; + +&usb_mp { + /* Only second port is used with USB 2.0 maximum speed */ + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb6_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi new file mode 100644 index 000000000000..cc64558ed5e6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi @@ -0,0 +1,1666 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024 Aleksandrs Vinarskis <alex.vinarskis@gmail.com> + * Copyright (c) 2025 Bryan O'Donoghue <bryan.odonoghue@linaro.org> + * Copyright (c) 2025 Val Packett <val@packett.cool> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/gpio-keys.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> + +#include "x1e80100-pmics.dtsi" + +/ { + chassis-type = "laptop"; + + aliases { + serial0 = &uart14; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <40000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&hall_int_n_default>; + pinctrl-names = "default"; + + switch-lid { + gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; + linux,input-type = <EV_SW>; + linux,code = <SW_LID>; + wakeup-source; + wakeup-event-action = <EV_ACT_DEASSERTED>; + }; + }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + /* Display-adjacent port */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&retimer_ss0_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss0_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss0_con_sbu_out>; + }; + }; + }; + }; + + /* User-adjacent port */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&retimer_ss1_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss1_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss1_con_sbu_out>; + }; + }; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&cam_indicator_en>; + pinctrl-names = "default"; + + led-camera-indicator { + label = "white:camera-indicator"; + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_WHITE>; + gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + /* Reuse as a panic indicator until we get a "camera on" trigger */ + panic-indicator; + }; + }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + sound: sound { + compatible = "qcom,x1e80100-sndcard"; + audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT", + "TweeterLeft IN", "WSA WSA_SPK2 OUT", + "WooferRight IN", "WSA2 WSA_SPK1 OUT", + "TweeterRight IN", "WSA2 WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS1", + "VA DMIC1", "MIC BIAS1", + "VA DMIC0", "VA MIC BIAS1", + "VA DMIC1", "VA MIC BIAS1", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&left_woofer>, <&left_tweeter>, + <&swr0 0>, <&lpass_wsamacro 0>, + <&right_woofer>, <&right_tweeter>, + <&swr3 0>, <&lpass_wsa2macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + vreg_cam_1p8: regulator-cam-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_CAM_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 91 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&cam_ldo_en>; + pinctrl-names = "default"; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p15: regulator-rtmr1-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p8: regulator-rtmr1-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_3p3: regulator-rtmr1-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7b_2p8: ldo7 { + regulator-name = "vreg_l7b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name = "vreg_l8b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name = "vreg_l2c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-4 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name = "vreg_s1f_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + + vreg_l1i_1p8: ldo1 { + regulator-name = "vreg_l1i_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name = "vreg_l1j_0p8"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +&i2c0 { + clock-frequency = <400000>; + + status = "okay"; + + keyboard@5 { + compatible = "hid-over-i2c"; + reg = <0x5>; + + hid-descr-addr = <0x20>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&kybd_default>; + pinctrl-names = "default"; + + wakeup-source; + }; + + touchpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + + hid-descr-addr = <0x20>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&tpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8833", "parade,ps8830"; + reg = <0x8>; + + clocks = <&rpmhcc RPMH_RF_CLK3>; + + vdd-supply = <&vreg_rtmr0_1p15>; + vdd33-supply = <&vreg_rtmr0_3p3>; + vdd33-cap-supply = <&vreg_rtmr0_3p3>; + vddar-supply = <&vreg_rtmr0_1p15>; + vddat-supply = <&vreg_rtmr0_1p15>; + vddio-supply = <&vreg_rtmr0_1p8>; + + reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr0_default>; + pinctrl-names = "default"; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss0_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss0_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + /* EC @0x3b */ + + /* Type A Port */ + eusb3_typea_repeater: redriver@43 { + compatible = "nxp,ptn3222"; + reg = <0x43>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb3_reset_n>; + pinctrl-names = "default"; + }; + + /* Fingerprint scanner */ + eusb5_frp_repeater: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb5_reset_n>; + pinctrl-names = "default"; + }; +}; + +&i2c7 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8833", "parade,ps8830"; + reg = <0x8>; + + clocks = <&rpmhcc RPMH_RF_CLK4>; + + vdd-supply = <&vreg_rtmr1_1p15>; + vdd33-supply = <&vreg_rtmr1_3p3>; + vdd33-cap-supply = <&vreg_rtmr1_3p3>; + vddar-supply = <&vreg_rtmr1_1p15>; + vddat-supply = <&vreg_rtmr1_1p15>; + vddio-supply = <&vreg_rtmr1_1p8>; + + reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr1_default>; + pinctrl-names = "default"; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss1_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss1_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c8 { + clock-frequency = <400000>; + + status = "okay"; +}; + +&i2c20 { + clock-frequency = <400000>; + + status = "okay"; +}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + spkr_23_sd_n_active: spkr-23-sd-n-active-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <4800000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + enable-gpios = <&tlmm 74 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_3p3>; + + pinctrl-0 = <&edp_bl_en>; + pinctrl-names = "default"; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + + mdss_dp3_out: endpoint { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; + }; + }; + }; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie4 { + perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie4_port0 { + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie6a { + perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie6a_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pm8550_gpios { + rtmr0_default: rtmr0-reset-n-active-state { + pins = "gpio10"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; + + usb0_3p3_reg_en: usb0-3p3-reg-en-state { + pins = "gpio11"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pm8550ve_9_gpios { + usb0_1p8_reg_en: usb0-1p8-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pmc8380_5_gpios { + usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 71 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l6b_1p8>; + bus-width = <4>; + no-sdio; + no-mmc; + + status = "okay"; +}; + +&smb2360_0 { + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1 { + status = "okay"; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&swr0 { + status = "okay"; + + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Left Woofer */ + left_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Left Tweeter */ + left_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&swr3 { + status = "okay"; + + pinctrl-0 = <&wsa2_swr_active>, <&spkr_23_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Right Woofer */ + right_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Tweeter */ + right_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&tlmm { + gpio-reserved-ranges = <44 4>, /* SPI11 (TPM) */ + <76 4>, /* SPI19 (TZ Protected) */ + <238 1>; /* UFS Reset */ + + cam_rgb_default: cam-rgb-default-state { + mclk-pins { + pins = "gpio100"; + function = "cam_aon"; + drive-strength = <16>; + bias-disable; + }; + + reset-n-pins { + pins = "gpio237"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + cam_indicator_en: cam-indicator-en-state { + pins = "gpio110"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + cam_ldo_en: cam-ldo-en-state { + pins = "gpio91"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + edp_bl_en: edp-bl-en-state { + pins = "gpio74"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + eusb3_reset_n: eusb3-reset-n-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + eusb5_reset_n: eusb5-reset-n-state { + pins = "gpio184"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + hall_int_n_default: hall-int-n-state { + pins = "gpio92"; + function = "gpio"; + + bias-disable; + }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-pull-up; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + rtmr1_default: rtmr1-reset-n-active-state { + pins = "gpio176"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + sdc2_card_det_n: sdc2-card-det-state { + pins = "gpio71"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + tpad_default: tpad-default-state { + disable-pins { + pins = "gpio38"; + function = "gpio"; + output-high; + }; + + int-n-pins { + pins = "gpio3"; + function = "gpio"; + bias-pull-up; + }; + + reset-n-pins { + pins = "gpio52"; + function = "gpio"; + bias-disable; + }; + }; + + ts0_default: ts0-default-state { + disable-pins { + pins = "gpio75"; + function = "gpio"; + output-high; + }; + + int-n-pins { + pins = "gpio51"; + function = "gpio"; + bias-pull-up; + }; + + reset-n-pins { + /* Technically should be High-Z input */ + pins = "gpio48"; + function = "gpio"; + output-low; + drive-strength = <2>; + }; + }; + + usb1_pwr_1p15_reg_en: usb1-pwr-1p15-reg-en-state { + pins = "gpio188"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb1_pwr_1p8_reg_en: usb1-pwr-1p8-reg-en-state { + pins = "gpio175"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb1_pwr_3p3_reg_en: usb1-pwr-3p3-reg-en-state { + pins = "gpio186"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio191"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + +&usb_1_ss0 { + status = "okay"; +}; + +&usb_1_ss0_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_0_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&retimer_ss0_ss_in>; +}; + +&usb_1_ss1 { + status = "okay"; +}; + +&usb_1_ss1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_1_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&retimer_ss1_ss_in>; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb5_frp_repeater>; + + status = "okay"; +}; + +&usb_mp { + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb3_typea_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1-el2.dtso b/arch/arm64/boot/dts/qcom/x1-el2.dtso index 380441deca65..2d1c9151cf1b 100644 --- a/arch/arm64/boot/dts/qcom/x1-el2.dtso +++ b/arch/arm64/boot/dts/qcom/x1-el2.dtso @@ -12,6 +12,11 @@ status = "disabled"; }; +&iris { + /* TODO: Add video-firmware iommus to start IRIS from EL2 */ + status = "disabled"; +}; + /* * When running under Gunyah, this IOMMU is controlled by the firmware, * however when we take ownership of it in EL2, we need to configure diff --git a/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi b/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi new file mode 100644 index 000000000000..a4075434162a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi @@ -0,0 +1,1544 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024, Xilin Wu <wuxilin123@gmail.com> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/gpio-keys.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> + +/ { + aliases { + serial0 = &uart21; + serial1 = &uart14; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-names = "default"; + pinctrl-0 = <&wcd_default>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pmk8550_pwm 0 5000000>; + + brightness-levels = <0 2048 4096 8192 16384 65535>; + num-interpolated-steps = <20>; + default-brightness-level = <80>; + + enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_bl>; + + pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>; + pinctrl-names = "default"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&hall_int_n_default>; + pinctrl-names = "default"; + + switch-lid { + gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; + linux,input-type = <EV_SW>; + linux,code = <SW_LID>; + wakeup-source; + wakeup-event-action = <EV_ACT_DEASSERTED>; + }; + }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + /* Left-side port, closer to the screen */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&retimer_ss0_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss0_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss0_con_sbu_out>; + }; + }; + }; + }; + + /* Left-side port, farther from the screen */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss1_sbu: endpoint { + remote-endpoint = <&usb_1_ss1_sbu_mux>; + }; + }; + }; + }; + }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + sound: sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E80100-HP-OMNIBOOK-X14"; + audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT", + "SpkrRight IN", "WSA WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS3", + "VA DMIC1", "MIC BIAS3", + "VA DMIC2", "MIC BIAS1", + "VA DMIC3", "MIC BIAS1", + "VA DMIC0", "VA MIC BIAS3", + "VA DMIC1", "VA MIC BIAS3", + "VA DMIC2", "VA MIC BIAS1", + "VA DMIC3", "VA MIC BIAS1", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_edp_bl: regulator-edp-bl { + compatible = "regulator-fixed"; + + regulator-name = "VBL9"; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + + gpio = <&pmc8380_3_gpios 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&edp_bl_reg_en>; + + regulator-boot-on; + }; + + vreg_misc_3p3: regulator-misc-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_MISC_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550ve_8_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&misc_3p3_reg_en>; + + regulator-boot-on; + regulator-always-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vreg_vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + /* + * TODO: These two regulators are actually part of the removable M.2 + * card and not the CRD mainboard. Need to describe this differently. + * Functionally it works correctly, because all we need to do is to + * turn on the actual 3.3V supply above. + */ + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + wcn6855-pmu { + compatible = "qcom,wcn6855-pmu"; + + vddaon-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_wcn_1p9>; + vddpcie1p3-supply = <&vreg_wcn_1p9>; + vddpcie1p9-supply = <&vreg_wcn_1p9>; + vddpmu-supply = <&vreg_wcn_0p95>; + vddpmumx-supply = <&vreg_wcn_0p95>; + vddpmucx-supply = <&vreg_wcn_0p95>; + vddrfa0p95-supply = <&vreg_wcn_0p95>; + vddrfa1p3-supply = <&vreg_wcn_1p9>; + vddrfa1p9-supply = <&vreg_wcn_1p9>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn_0p8: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn_0p8"; + }; + + vreg_pmu_aon_0p8: ldo1 { + regulator-name = "vreg_pmu_aon_0p8"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p8: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p8"; + }; + + vreg_pmu_btcmx_0p8: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p8"; + }; + + vreg_pmu_pcie_1p8: ldo5 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo6 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_rfa_0p8: ldo7 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo8 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p7: ldo9 { + regulator-name = "vreg_pmu_rfa_1p7"; + }; + }; + }; + + usb-1-ss1-sbu-mux { + compatible = "onnn,fsusb42", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 179 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 178 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb_1_ss1_sbu_default>; + pinctrl-names = "default"; + + mode-switch; + orientation-switch; + + port { + usb_1_ss1_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_ss1_sbu>; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vreg_vph_pwr>; + vdd-bob2-supply = <&vreg_vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5b_3p0: ldo5 { + regulator-name = "vreg_l5b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7b_2p8: ldo7 { + regulator-name = "vreg_l7b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name = "vreg_l8b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name = "vreg_l10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-always-on; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-always-on; + }; + + vreg_l16b_2p9: ldo16 { + regulator-name = "vreg_l16b_2p9"; + regulator-min-microvolt = <2912000>; + regulator-max-microvolt = <2912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s4-supply = <&vreg_vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name = "vreg_l2c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vreg_vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-4 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vreg_vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name = "vreg_s1f_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1f_1p0: ldo1 { + regulator-name = "vreg_l1f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2f_1p0: ldo2 { + regulator-name = "vreg_l2f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3f_1p0: ldo3 { + regulator-name = "vreg_l3f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s1-supply = <&vreg_vph_pwr>; + vdd-s2-supply = <&vreg_vph_pwr>; + + vreg_s1i_0p9: smps1 { + regulator-name = "vreg_s1i_0p9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s2i_1p0: smps2 { + regulator-name = "vreg_s2i_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1i_1p8: ldo1 { + regulator-name = "vreg_l1i_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s5-supply = <&vreg_vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name = "vreg_l1j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +&gpu { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + + status = "okay"; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + pinctrl-0 = <&kybd_default>; + pinctrl-names = "default"; + + wakeup-source; + }; + + touchpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + pinctrl-0 = <&tpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x08>; + + clocks = <&rpmhcc RPMH_RF_CLK3>; + + vdd-supply = <&vreg_rtmr0_1p15>; + vdd33-supply = <&vreg_rtmr0_3p3>; + vdd33-cap-supply = <&vreg_rtmr0_3p3>; + vddar-supply = <&vreg_rtmr0_1p15>; + vddat-supply = <&vreg_rtmr0_1p15>; + vddio-supply = <&vreg_rtmr0_1p8>; + + reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr0_default>; + pinctrl-names = "default"; + + orientation-switch; + retimer-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss0_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss0_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + status = "okay"; + + eusb3_repeater: redriver@47 { + compatible = "nxp,ptn3222"; + reg = <0x47>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb3_reset_n>; + pinctrl-names = "default"; + + }; +}; + +&i2c8 { + clock-frequency = <400000>; + + status = "okay"; + + touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l15b_1p8>; + + pinctrl-0 = <&ts0_default>; + pinctrl-names = "default"; + }; +}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>, <&dmic23_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <4800000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + power-supply = <&vreg_edp_3p3>; + + backlight = <&backlight>; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; +}; + +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie4 { + perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie4_port0 { + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p8>; + }; +}; + +&pcie6a { + perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie6a_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pm8550_gpios { + rtmr0_default: rtmr0-reset-n-active-state { + pins = "gpio10"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; + + usb0_3p3_reg_en: usb0-3p3-reg-en-state { + pins = "gpio11"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pm8550ve_8_gpios { + misc_3p3_reg_en: misc-3p3-reg-en-state { + pins = "gpio6"; + function = "normal"; + bias-disable; + drive-push-pull; + input-disable; + output-enable; + power-source = <1>; /* 1.8 V */ + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; + }; +}; + +&pm8550ve_9_gpios { + usb0_1p8_reg_en: usb0-1p8-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pmc8380_3_gpios { + edp_bl_en: edp-bl-en-state { + pins = "gpio4"; + function = "normal"; + power-source = <1>; /* 1.8V */ + input-disable; + output-enable; + }; + + edp_bl_reg_en: edp-bl-reg-en-state { + pins = "gpio10"; + function = "normal"; + }; + +}; + +&pmc8380_5_gpios { + usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pmk8550_gpios { + edp_bl_pwm: edp-bl-pwm-state { + pins = "gpio5"; + function = "func3"; + }; +}; + +&pmk8550_pwm { + status = "okay"; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&smb2360_0 { + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1 { + status = "okay"; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&swr0 { + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + status = "okay"; + + /* WSA8845, Left Speaker */ + left_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Speaker */ + right_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&tlmm { + gpio-reserved-ranges = <34 2>, /* Unused */ + <44 4>, /* SPI (TPM) */ + <72 2>, /* Secure EC I2C connection (?) */ + <238 1>; /* UFS Reset */ + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + eusb3_reset_n: eusb3-reset-n-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + hall_int_n_default: hall-int-n-state { + pins = "gpio92"; + function = "gpio"; + bias-disable; + }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-pull-up; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-pull-up; + }; + + ts0_default: ts0-default-state { + int-n-pins { + pins = "gpio51"; + function = "gpio"; + bias-pull-up; + }; + + reset-n-pins { + pins = "gpio48"; + function = "gpio"; + output-high; + drive-strength = <16>; + }; + }; + + usb_1_ss1_sbu_default: usb-1-ss1-sbu-state { + mode-pins { + pins = "gpio177"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + output-high; + }; + + oe-n-pins { + pins = "gpio179"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + + sel-pins { + pins = "gpio178"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio191"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn6855-bt"; + max-speed = <3200000>; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>; + vddaon-supply = <&vreg_pmu_aon_0p8>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p8>; + vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + }; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_0_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + + status = "okay"; +}; + +&usb_1_ss0 { + status = "okay"; +}; + +&usb_1_ss0_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&retimer_ss0_ss_in>; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_1_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_1_ss1 { + status = "okay"; +}; + +&usb_1_ss1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss1_ss_in>; +}; + +&usb_mp { + status = "okay"; +}; + +&usb_mp_dwc3 { + phys = <&usb_mp_hsphy0>, <&usb_mp_qmpphy0>; + phy-names = "usb2-0", "usb3-0"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb3_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts index 2d9627e6c798..bfc649d4b643 100644 --- a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts +++ b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts @@ -983,7 +983,6 @@ }; &mdss_dp0_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; @@ -992,7 +991,6 @@ }; &mdss_dp1_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; @@ -1001,7 +999,6 @@ }; &mdss_dp2_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; @@ -1474,7 +1471,7 @@ vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; - phys = <&eusb6_repeater>; + phys = <&eusb3_repeater>; status = "okay"; }; @@ -1483,7 +1480,7 @@ vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; - phys = <&eusb3_repeater>; + phys = <&eusb6_repeater>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s-oled.dts b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s-oled.dts index be65fafafa73..d524afa12d19 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s-oled.dts +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s-oled.dts @@ -10,3 +10,11 @@ compatible = "lenovo,thinkpad-t14s-oled", "lenovo,thinkpad-t14s", "qcom,x1e78100", "qcom,x1e80100"; }; + +&panel { + compatible = "samsung,atna40yk20", "samsung,atna33xc20"; + enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&edp_bl_en>; + pinctrl-names = "default"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi index ac1dddf27da3..654cbce9d6ec 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi @@ -887,6 +887,24 @@ }; }; +&i2c6 { + clock-frequency = <400000>; + + status = "okay"; + + embedded-controller@28 { + compatible = "lenovo,thinkpad-t14s-ec"; + reg = <0x28>; + + interrupts-extended = <&tlmm 66 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&ec_int_n_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + &i2c7 { clock-frequency = <400000>; @@ -967,6 +985,11 @@ /* TODO: second-sourced touchscreen @ 0x41 */ }; +&iris { + firmware-name = "qcom/x1e80100/LENOVO/21N1/qcvss8380.mbn"; + status = "okay"; +}; + &lpass_tlmm { spkr_01_sd_n_active: spkr-01-sd-n-active-state { pins = "gpio12"; @@ -994,7 +1017,7 @@ }; &mdss_dp0_out { - data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; &mdss_dp1 { @@ -1002,12 +1025,15 @@ }; &mdss_dp1_out { - data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; &mdss_dp3 { /delete-property/ #sound-dai-cells; + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + status = "okay"; aux-bus { @@ -1022,19 +1048,13 @@ }; }; }; +}; - ports { - port@1 { - reg = <1>; - - mdss_dp3_out: endpoint { - data-lanes = <0 1 2 3>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - remote-endpoint = <&edp_panel_in>; - }; - }; - }; + remote-endpoint = <&edp_panel_in>; }; &mdss_dp3_phy { @@ -1267,6 +1287,12 @@ <72 2>, /* Secure EC I2C connection (?) */ <238 1>; /* UFS Reset */ + ec_int_n_default: ec-int-n-state { + pins = "gpio66"; + function = "gpio"; + bias-disable; + }; + eusb3_reset_n: eusb3-reset-n-state { pins = "gpio6"; function = "gpio"; @@ -1547,7 +1573,7 @@ vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; - phys = <&eusb6_repeater>; + phys = <&eusb3_repeater>; status = "okay"; }; @@ -1556,7 +1582,7 @@ vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; - phys = <&eusb3_repeater>; + phys = <&eusb6_repeater>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts index 71b2cc6c392f..0113d856b3ad 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts @@ -593,6 +593,9 @@ &mdss_dp3 { /delete-property/ #sound-dai-cells; + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + status = "okay"; aux-bus { @@ -611,19 +614,13 @@ }; }; }; +}; - ports { - port@1 { - reg = <1>; - - mdss_dp3_out: endpoint { - data-lanes = <0 1 2 3>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - remote-endpoint = <&edp_panel_in>; - }; - }; - }; + remote-endpoint = <&edp_panel_in>; }; &mdss_dp3_phy { @@ -977,7 +974,7 @@ vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; - phys = <&eusb6_repeater>; + phys = <&eusb3_repeater>; status = "okay"; }; @@ -986,7 +983,7 @@ vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; - phys = <&eusb3_repeater>; + phys = <&eusb6_repeater>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts index 976b8e44b576..dfc378e1a056 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts @@ -16,3 +16,7 @@ &gpu_zap_shader { firmware-name = "qcom/x1e80100/gen70500_zap.mbn"; }; + +&iris { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-dell-inspiron-14-plus-7441.dts b/arch/arm64/boot/dts/qcom/x1e80100-dell-inspiron-14-plus-7441.dts new file mode 100644 index 000000000000..cf2a7c262888 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1e80100-dell-inspiron-14-plus-7441.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Val Packett <val@packett.cool> + */ +/dts-v1/; + +#include "x1e80100.dtsi" +#include "x1-dell-thena.dtsi" + +/ { + model = "Dell Inspiron 14 Plus 7441"; + compatible = "dell,inspiron-14-plus-7441", "qcom,x1e80100"; +}; + +&sound { + model = "X1E80100-Dell-Inspiron-14p-7441"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/x1e80100/dell/inspiron-14-plus-7441/qcdxkmsuc8380.mbn"; +}; + +&i2c8 { + touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&ts0_default>; + pinctrl-names = "default"; + }; +}; + +&iris { + firmware-name = "qcom/x1e80100/dell/inspiron-14-plus-7441/qcvss8380.mbn"; + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/dell/inspiron-14-plus-7441/qcadsp8380.mbn", + "qcom/x1e80100/dell/inspiron-14-plus-7441/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/dell/inspiron-14-plus-7441/qccdsp8380.mbn", + "qcom/x1e80100/dell/inspiron-14-plus-7441/cdsp_dtbs.elf"; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-dell-latitude-7455.dts b/arch/arm64/boot/dts/qcom/x1e80100-dell-latitude-7455.dts new file mode 100644 index 000000000000..32ad9679550e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1e80100-dell-latitude-7455.dts @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Val Packett <val@packett.cool> + */ +/dts-v1/; + +#include "x1e80100.dtsi" +#include "x1-dell-thena.dtsi" + +/ { + model = "Dell Latitude 7455"; + compatible = "dell,latitude-7455", "qcom,x1e80100"; +}; + +&sound { + model = "X1E80100-Dell-Latitude-7455"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/x1e80100/dell/latitude-7455/qcdxkmsuc8380.mbn"; +}; + +&i2c8 { + /* LXST2021 */ + touchscreen@9 { + compatible = "hid-over-i2c"; + reg = <0x09>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&ts0_default>; + pinctrl-names = "default"; + }; +}; + +&iris { + firmware-name = "qcom/x1e80100/dell/latitude-7455/qcvss8380.mbn"; + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/dell/latitude-7455/qcadsp8380.mbn", + "qcom/x1e80100/dell/latitude-7455/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/dell/latitude-7455/qccdsp8380.mbn", + "qcom/x1e80100/dell/latitude-7455/cdsp_dtbs.elf"; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts index fd00d1bf12e1..58f8caaa7258 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts @@ -875,6 +875,11 @@ }; }; +&iris { + firmware-name = "qcom/x1e80100/dell/xps13-9345/qcvss8380.mbn"; + status = "okay"; +}; + &mdss { status = "okay"; }; @@ -884,7 +889,6 @@ }; &mdss_dp0_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; @@ -893,13 +897,15 @@ }; &mdss_dp1_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; &mdss_dp3 { /delete-property/ #sound-dai-cells; + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + status = "okay"; aux-bus { @@ -918,19 +924,13 @@ }; }; }; +}; - ports { - port@1 { - reg = <1>; - - mdss_dp3_out: endpoint { - data-lanes = <0 1 2 3>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - remote-endpoint = <&edp_panel_in>; - }; - }; - }; + remote-endpoint = <&edp_panel_in>; }; &mdss_dp3_phy { diff --git a/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts b/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts index 8d2a9b7f4730..e5a839d45840 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts @@ -6,1227 +6,18 @@ /dts-v1/; -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/gpio-keys.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> -#include <dt-bindings/regulator/qcom,rpmh-regulator.h> - #include "x1e80100.dtsi" #include "x1e80100-pmics.dtsi" +#include "x1-hp-omnibook-x14.dtsi" / { - model = "HP Omnibook X 14"; + model = "HP Omnibook X 14-fe0"; compatible = "hp,omnibook-x14", "qcom,x1e80100"; chassis-type = "laptop"; - - aliases { - serial0 = &uart21; - serial1 = &uart14; - }; - - wcd938x: audio-codec { - compatible = "qcom,wcd9385-codec"; - - pinctrl-names = "default"; - pinctrl-0 = <&wcd_default>; - - qcom,micbias1-microvolt = <1800000>; - qcom,micbias2-microvolt = <1800000>; - qcom,micbias3-microvolt = <1800000>; - qcom,micbias4-microvolt = <1800000>; - qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; - qcom,mbhc-headset-vthreshold-microvolt = <1700000>; - qcom,mbhc-headphone-vthreshold-microvolt = <50000>; - qcom,rx-device = <&wcd_rx>; - qcom,tx-device = <&wcd_tx>; - - reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; - - vdd-buck-supply = <&vreg_l15b_1p8>; - vdd-rxtx-supply = <&vreg_l15b_1p8>; - vdd-io-supply = <&vreg_l15b_1p8>; - vdd-mic-bias-supply = <&vreg_bob1>; - - #sound-dai-cells = <1>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pmk8550_pwm 0 5000000>; - - brightness-levels = <0 2048 4096 8192 16384 65535>; - num-interpolated-steps = <20>; - default-brightness-level = <80>; - - enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; - power-supply = <&vreg_edp_bl>; - - pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>; - pinctrl-names = "default"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-0 = <&hall_int_n_default>; - pinctrl-names = "default"; - - switch-lid { - gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; - linux,input-type = <EV_SW>; - linux,code = <SW_LID>; - wakeup-source; - wakeup-event-action = <EV_ACT_DEASSERTED>; - }; - }; - - pmic-glink { - compatible = "qcom,x1e80100-pmic-glink", - "qcom,sm8550-pmic-glink", - "qcom,pmic-glink"; - orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, - <&tlmm 123 GPIO_ACTIVE_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - - /* Left-side port, closer to the screen */ - connector@0 { - compatible = "usb-c-connector"; - reg = <0>; - power-role = "dual"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - pmic_glink_ss0_hs_in: endpoint { - remote-endpoint = <&usb_1_ss0_dwc3_hs>; - }; - }; - - port@1 { - reg = <1>; - - pmic_glink_ss0_ss_in: endpoint { - remote-endpoint = <&retimer_ss0_ss_out>; - }; - }; - - port@2 { - reg = <2>; - - pmic_glink_ss0_con_sbu_in: endpoint { - remote-endpoint = <&retimer_ss0_con_sbu_out>; - }; - }; - }; - }; - - /* Left-side port, farther from the screen */ - connector@1 { - compatible = "usb-c-connector"; - reg = <1>; - power-role = "dual"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - pmic_glink_ss1_hs_in: endpoint { - remote-endpoint = <&usb_1_ss1_dwc3_hs>; - }; - }; - - port@1 { - reg = <1>; - - pmic_glink_ss1_ss_in: endpoint { - remote-endpoint = <&usb_1_ss1_qmpphy_out>; - }; - }; - - port@2 { - reg = <2>; - - pmic_glink_ss1_sbu: endpoint { - remote-endpoint = <&usb_1_ss1_sbu_mux>; - }; - }; - }; - }; - }; - - reserved-memory { - linux,cma { - compatible = "shared-dma-pool"; - size = <0x0 0x8000000>; - reusable; - linux,cma-default; - }; - }; - - sound: sound { - compatible = "qcom,x1e80100-sndcard"; - model = "X1E80100-HP-OMNIBOOK-X14"; - audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT", - "SpkrRight IN", "WSA WSA_SPK2 OUT", - "IN1_HPHL", "HPHL_OUT", - "IN2_HPHR", "HPHR_OUT", - "AMIC2", "MIC BIAS2", - "VA DMIC0", "MIC BIAS3", - "VA DMIC1", "MIC BIAS3", - "VA DMIC2", "MIC BIAS1", - "VA DMIC3", "MIC BIAS1", - "VA DMIC0", "VA MIC BIAS3", - "VA DMIC1", "VA MIC BIAS3", - "VA DMIC2", "VA MIC BIAS1", - "VA DMIC3", "VA MIC BIAS1", - "TX SWR_INPUT1", "ADC2_OUTPUT"; - - wcd-playback-dai-link { - link-name = "WCD Playback"; - - cpu { - sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; - }; - - codec { - sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; - }; - - platform { - sound-dai = <&q6apm>; - }; - }; - - wcd-capture-dai-link { - link-name = "WCD Capture"; - - cpu { - sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; - }; - - codec { - sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; - }; - - platform { - sound-dai = <&q6apm>; - }; - }; - - wsa-dai-link { - link-name = "WSA Playback"; - - cpu { - sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; - }; - - codec { - sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>; - }; - - platform { - sound-dai = <&q6apm>; - }; - }; - - va-dai-link { - link-name = "VA Capture"; - - cpu { - sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; - }; - - codec { - sound-dai = <&lpass_vamacro 0>; - }; - - platform { - sound-dai = <&q6apm>; - }; - }; - }; - - vreg_edp_3p3: regulator-edp-3p3 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_EDP_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&edp_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_edp_bl: regulator-edp-bl { - compatible = "regulator-fixed"; - - regulator-name = "VBL9"; - regulator-min-microvolt = <3600000>; - regulator-max-microvolt = <3600000>; - - gpio = <&pmc8380_3_gpios 10 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&edp_bl_reg_en>; - - regulator-boot-on; - }; - - vreg_misc_3p3: regulator-misc-3p3 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_MISC_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&pm8550ve_8_gpios 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&misc_3p3_reg_en>; - - regulator-boot-on; - regulator-always-on; - }; - - vreg_nvme: regulator-nvme { - compatible = "regulator-fixed"; - - regulator-name = "VREG_NVME_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&nvme_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_rtmr0_1p15: regulator-rtmr0-1p15 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_RTMR0_1P15"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - - gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&usb0_pwr_1p15_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_rtmr0_1p8: regulator-rtmr0-1p8 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_RTMR0_1P8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&usb0_1p8_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_rtmr0_3p3: regulator-rtmr0-3p3 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_RTMR0_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&usb0_3p3_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_vph_pwr: regulator-vph-pwr { - compatible = "regulator-fixed"; - - regulator-name = "vreg_vph_pwr"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - - regulator-always-on; - regulator-boot-on; - }; - - vreg_wcn_3p3: regulator-wcn-3p3 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_WCN_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&wcn_sw_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - /* - * TODO: These two regulators are actually part of the removable M.2 - * card and not the CRD mainboard. Need to describe this differently. - * Functionally it works correctly, because all we need to do is to - * turn on the actual 3.3V supply above. - */ - vreg_wcn_0p95: regulator-wcn-0p95 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_WCN_0P95"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <950000>; - - vin-supply = <&vreg_wcn_3p3>; - }; - - vreg_wcn_1p9: regulator-wcn-1p9 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_WCN_1P9"; - regulator-min-microvolt = <1900000>; - regulator-max-microvolt = <1900000>; - - vin-supply = <&vreg_wcn_3p3>; - }; - - wcn6855-pmu { - compatible = "qcom,wcn6855-pmu"; - - vddaon-supply = <&vreg_wcn_0p95>; - vddio-supply = <&vreg_wcn_1p9>; - vddpcie1p3-supply = <&vreg_wcn_1p9>; - vddpcie1p9-supply = <&vreg_wcn_1p9>; - vddpmu-supply = <&vreg_wcn_0p95>; - vddpmumx-supply = <&vreg_wcn_0p95>; - vddpmucx-supply = <&vreg_wcn_0p95>; - vddrfa0p95-supply = <&vreg_wcn_0p95>; - vddrfa1p3-supply = <&vreg_wcn_1p9>; - vddrfa1p9-supply = <&vreg_wcn_1p9>; - - wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; - bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; - - pinctrl-0 = <&wcn_wlan_bt_en>; - pinctrl-names = "default"; - - regulators { - vreg_pmu_rfa_cmn_0p8: ldo0 { - regulator-name = "vreg_pmu_rfa_cmn_0p8"; - }; - - vreg_pmu_aon_0p8: ldo1 { - regulator-name = "vreg_pmu_aon_0p8"; - }; - - vreg_pmu_wlcx_0p8: ldo2 { - regulator-name = "vreg_pmu_wlcx_0p8"; - }; - - vreg_pmu_wlmx_0p8: ldo3 { - regulator-name = "vreg_pmu_wlmx_0p8"; - }; - - vreg_pmu_btcmx_0p8: ldo4 { - regulator-name = "vreg_pmu_btcmx_0p8"; - }; - - vreg_pmu_pcie_1p8: ldo5 { - regulator-name = "vreg_pmu_pcie_1p8"; - }; - - vreg_pmu_pcie_0p9: ldo6 { - regulator-name = "vreg_pmu_pcie_0p9"; - }; - - vreg_pmu_rfa_0p8: ldo7 { - regulator-name = "vreg_pmu_rfa_0p8"; - }; - - vreg_pmu_rfa_1p2: ldo8 { - regulator-name = "vreg_pmu_rfa_1p2"; - }; - - vreg_pmu_rfa_1p7: ldo9 { - regulator-name = "vreg_pmu_rfa_1p7"; - }; - }; - }; - - usb-1-ss1-sbu-mux { - compatible = "onnn,fsusb42", "gpio-sbu-mux"; - - enable-gpios = <&tlmm 179 GPIO_ACTIVE_LOW>; - select-gpios = <&tlmm 178 GPIO_ACTIVE_HIGH>; - - pinctrl-0 = <&usb_1_ss1_sbu_default>; - pinctrl-names = "default"; - - mode-switch; - orientation-switch; - - port { - usb_1_ss1_sbu_mux: endpoint { - remote-endpoint = <&pmic_glink_ss1_sbu>; - }; - }; - }; }; -&apps_rsc { - regulators-0 { - compatible = "qcom,pm8550-rpmh-regulators"; - qcom,pmic-id = "b"; - - vdd-bob1-supply = <&vreg_vph_pwr>; - vdd-bob2-supply = <&vreg_vph_pwr>; - vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; - vdd-l2-l13-l14-supply = <&vreg_bob1>; - vdd-l5-l16-supply = <&vreg_bob1>; - vdd-l6-l7-supply = <&vreg_bob2>; - vdd-l8-l9-supply = <&vreg_bob1>; - vdd-l12-supply = <&vreg_s5j_1p2>; - vdd-l15-supply = <&vreg_s4c_1p8>; - vdd-l17-supply = <&vreg_bob2>; - - vreg_bob1: bob1 { - regulator-name = "vreg_bob1"; - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3960000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_bob2: bob2 { - regulator-name = "vreg_bob2"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <3008000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l1b_1p8: ldo1 { - regulator-name = "vreg_l1b_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l2b_3p0: ldo2 { - regulator-name = "vreg_l2b_3p0"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3100000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l4b_1p8: ldo4 { - regulator-name = "vreg_l4b_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l5b_3p0: ldo5 { - regulator-name = "vreg_l5b_3p0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l6b_1p8: ldo6 { - regulator-name = "vreg_l6b_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l7b_2p8: ldo7 { - regulator-name = "vreg_l7b_2p8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l8b_3p0: ldo8 { - regulator-name = "vreg_l8b_3p0"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3072000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l9b_2p9: ldo9 { - regulator-name = "vreg_l9b_2p9"; - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l10b_1p8: ldo10 { - regulator-name = "vreg_l10b_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l12b_1p2: ldo12 { - regulator-name = "vreg_l12b_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-always-on; - }; - - vreg_l13b_3p0: ldo13 { - regulator-name = "vreg_l13b_3p0"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3100000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l14b_3p0: ldo14 { - regulator-name = "vreg_l14b_3p0"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3072000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l15b_1p8: ldo15 { - regulator-name = "vreg_l15b_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-always-on; - }; - - vreg_l16b_2p9: ldo16 { - regulator-name = "vreg_l16b_2p9"; - regulator-min-microvolt = <2912000>; - regulator-max-microvolt = <2912000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l17b_2p5: ldo17 { - regulator-name = "vreg_l17b_2p5"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <2504000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - }; - - regulators-1 { - compatible = "qcom,pm8550ve-rpmh-regulators"; - qcom,pmic-id = "c"; - - vdd-l1-supply = <&vreg_s5j_1p2>; - vdd-l2-supply = <&vreg_s1f_0p7>; - vdd-l3-supply = <&vreg_s1f_0p7>; - vdd-s4-supply = <&vreg_vph_pwr>; - - vreg_s4c_1p8: smps4 { - regulator-name = "vreg_s4c_1p8"; - regulator-min-microvolt = <1856000>; - regulator-max-microvolt = <2000000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l1c_1p2: ldo1 { - regulator-name = "vreg_l1c_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l2c_0p8: ldo2 { - regulator-name = "vreg_l2c_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l3c_0p8: ldo3 { - regulator-name = "vreg_l3c_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - }; - - regulators-2 { - compatible = "qcom,pmc8380-rpmh-regulators"; - qcom,pmic-id = "d"; - - vdd-l1-supply = <&vreg_s1f_0p7>; - vdd-l2-supply = <&vreg_s1f_0p7>; - vdd-l3-supply = <&vreg_s4c_1p8>; - vdd-s1-supply = <&vreg_vph_pwr>; - - vreg_l1d_0p8: ldo1 { - regulator-name = "vreg_l1d_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l2d_0p9: ldo2 { - regulator-name = "vreg_l2d_0p9"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l3d_1p8: ldo3 { - regulator-name = "vreg_l3d_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - }; - - regulators-3 { - compatible = "qcom,pmc8380-rpmh-regulators"; - qcom,pmic-id = "e"; - - vdd-l2-supply = <&vreg_s1f_0p7>; - vdd-l3-supply = <&vreg_s5j_1p2>; - - vreg_l2e_0p8: ldo2 { - regulator-name = "vreg_l2e_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l3e_1p2: ldo3 { - regulator-name = "vreg_l3e_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - }; - - regulators-4 { - compatible = "qcom,pmc8380-rpmh-regulators"; - qcom,pmic-id = "f"; - - vdd-l1-supply = <&vreg_s5j_1p2>; - vdd-l2-supply = <&vreg_s5j_1p2>; - vdd-l3-supply = <&vreg_s5j_1p2>; - vdd-s1-supply = <&vreg_vph_pwr>; - - vreg_s1f_0p7: smps1 { - regulator-name = "vreg_s1f_0p7"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l1f_1p0: ldo1 { - regulator-name = "vreg_l1f_1p0"; - regulator-min-microvolt = <1024000>; - regulator-max-microvolt = <1024000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l2f_1p0: ldo2 { - regulator-name = "vreg_l2f_1p0"; - regulator-min-microvolt = <1024000>; - regulator-max-microvolt = <1024000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l3f_1p0: ldo3 { - regulator-name = "vreg_l3f_1p0"; - regulator-min-microvolt = <1024000>; - regulator-max-microvolt = <1024000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - }; - - regulators-6 { - compatible = "qcom,pm8550ve-rpmh-regulators"; - qcom,pmic-id = "i"; - - vdd-l1-supply = <&vreg_s4c_1p8>; - vdd-l2-supply = <&vreg_s5j_1p2>; - vdd-l3-supply = <&vreg_s1f_0p7>; - vdd-s1-supply = <&vreg_vph_pwr>; - vdd-s2-supply = <&vreg_vph_pwr>; - - vreg_s1i_0p9: smps1 { - regulator-name = "vreg_s1i_0p9"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_s2i_1p0: smps2 { - regulator-name = "vreg_s2i_1p0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1100000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l1i_1p8: ldo1 { - regulator-name = "vreg_l1i_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l2i_1p2: ldo2 { - regulator-name = "vreg_l2i_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l3i_0p8: ldo3 { - regulator-name = "vreg_l3i_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - }; - - regulators-7 { - compatible = "qcom,pm8550ve-rpmh-regulators"; - qcom,pmic-id = "j"; - - vdd-l1-supply = <&vreg_s1f_0p7>; - vdd-l2-supply = <&vreg_s5j_1p2>; - vdd-l3-supply = <&vreg_s1f_0p7>; - vdd-s5-supply = <&vreg_vph_pwr>; - - vreg_s5j_1p2: smps5 { - regulator-name = "vreg_s5j_1p2"; - regulator-min-microvolt = <1256000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l1j_0p8: ldo1 { - regulator-name = "vreg_l1j_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l2j_1p2: ldo2 { - regulator-name = "vreg_l2j_1p2"; - regulator-min-microvolt = <1256000>; - regulator-max-microvolt = <1256000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l3j_0p8: ldo3 { - regulator-name = "vreg_l3j_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - }; -}; - -&gpu { - status = "okay"; - - zap-shader { - firmware-name = "qcom/x1e80100/hp/omnibook-x14/qcdxkmsuc8380.mbn"; - }; -}; - -&i2c0 { - clock-frequency = <400000>; - - status = "okay"; - - keyboard@3a { - compatible = "hid-over-i2c"; - reg = <0x3a>; - - hid-descr-addr = <0x1>; - interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; - - vdd-supply = <&vreg_misc_3p3>; - vddl-supply = <&vreg_l12b_1p2>; - - pinctrl-0 = <&kybd_default>; - pinctrl-names = "default"; - - wakeup-source; - }; - - touchpad@15 { - compatible = "hid-over-i2c"; - reg = <0x15>; - - hid-descr-addr = <0x1>; - interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; - - vdd-supply = <&vreg_misc_3p3>; - vddl-supply = <&vreg_l12b_1p2>; - - pinctrl-0 = <&tpad_default>; - pinctrl-names = "default"; - - wakeup-source; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - - status = "okay"; - - typec-mux@8 { - compatible = "parade,ps8830"; - reg = <0x08>; - - clocks = <&rpmhcc RPMH_RF_CLK3>; - - vdd-supply = <&vreg_rtmr0_1p15>; - vdd33-supply = <&vreg_rtmr0_3p3>; - vdd33-cap-supply = <&vreg_rtmr0_3p3>; - vddar-supply = <&vreg_rtmr0_1p15>; - vddat-supply = <&vreg_rtmr0_1p15>; - vddio-supply = <&vreg_rtmr0_1p8>; - - reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&rtmr0_default>; - pinctrl-names = "default"; - - orientation-switch; - retimer-switch; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - retimer_ss0_ss_out: endpoint { - remote-endpoint = <&pmic_glink_ss0_ss_in>; - }; - }; - - port@1 { - reg = <1>; - - retimer_ss0_ss_in: endpoint { - remote-endpoint = <&usb_1_ss0_qmpphy_out>; - }; - }; - - port@2 { - reg = <2>; - - retimer_ss0_con_sbu_out: endpoint { - remote-endpoint = <&pmic_glink_ss0_con_sbu_in>; - }; - }; - }; - }; -}; - -&i2c5 { - clock-frequency = <400000>; - status = "okay"; - - eusb3_repeater: redriver@47 { - compatible = "nxp,ptn3222"; - reg = <0x47>; - #phy-cells = <0>; - - vdd3v3-supply = <&vreg_l13b_3p0>; - vdd1v8-supply = <&vreg_l4b_1p8>; - - reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&eusb3_reset_n>; - pinctrl-names = "default"; - - }; -}; - -&i2c8 { - clock-frequency = <400000>; - - status = "okay"; - - touchscreen@10 { - compatible = "hid-over-i2c"; - reg = <0x10>; - - hid-descr-addr = <0x1>; - interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; - - vdd-supply = <&vreg_misc_3p3>; - vddl-supply = <&vreg_l15b_1p8>; - - pinctrl-0 = <&ts0_default>; - pinctrl-names = "default"; - }; -}; - -&lpass_tlmm { - spkr_01_sd_n_active: spkr-01-sd-n-active-state { - pins = "gpio12"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - output-low; - }; -}; - -&lpass_vamacro { - pinctrl-0 = <&dmic01_default>, <&dmic23_default>; - pinctrl-names = "default"; - - vdd-micb-supply = <&vreg_l1b_1p8>; - qcom,dmic-sample-rate = <4800000>; -}; - -&mdss { - status = "okay"; -}; - -&mdss_dp0 { - status = "okay"; -}; - -&mdss_dp0_out { - data-lanes = <0 1>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; -}; - -&mdss_dp1 { - status = "okay"; -}; - -&mdss_dp1_out { - data-lanes = <0 1>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; -}; - -&mdss_dp3 { - /delete-property/ #sound-dai-cells; - - status = "okay"; - - aux-bus { - panel { - compatible = "edp-panel"; - power-supply = <&vreg_edp_3p3>; - - backlight = <&backlight>; - - port { - edp_panel_in: endpoint { - remote-endpoint = <&mdss_dp3_out>; - }; - }; - }; - }; - - ports { - port@1 { - reg = <1>; - - mdss_dp3_out: endpoint { - data-lanes = <0 1 2 3>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - - remote-endpoint = <&edp_panel_in>; - }; - }; - }; -}; - -&mdss_dp3_phy { - vdda-phy-supply = <&vreg_l3j_0p8>; - vdda-pll-supply = <&vreg_l2j_1p2>; - - status = "okay"; -}; - -&pcie4 { - perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&pcie4_default>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pcie4_phy { - vdda-phy-supply = <&vreg_l3i_0p8>; - vdda-pll-supply = <&vreg_l3e_1p2>; - - status = "okay"; -}; - -&pcie4_port0 { - wifi@0 { - compatible = "pci17cb,1107"; - reg = <0x10000 0x0 0x0 0x0 0x0>; - - vddaon-supply = <&vreg_pmu_aon_0p8>; - vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; - vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; - vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; - vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; - vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>; - vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; - vddwlmx-supply = <&vreg_pmu_wlmx_0p8>; - }; -}; - -&pcie6a { - perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; - - vddpe-3v3-supply = <&vreg_nvme>; - - pinctrl-0 = <&pcie6a_default>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pcie6a_phy { - vdda-phy-supply = <&vreg_l1d_0p8>; - vdda-pll-supply = <&vreg_l2j_1p2>; - - status = "okay"; -}; - -&pm8550_gpios { - rtmr0_default: rtmr0-reset-n-active-state { - pins = "gpio10"; - function = "normal"; - power-source = <1>; /* 1.8V */ - bias-disable; - input-disable; - output-enable; - }; - - usb0_3p3_reg_en: usb0-3p3-reg-en-state { - pins = "gpio11"; - function = "normal"; - power-source = <1>; /* 1.8V */ - bias-disable; - input-disable; - output-enable; - }; -}; - -&pm8550ve_8_gpios { - misc_3p3_reg_en: misc-3p3-reg-en-state { - pins = "gpio6"; - function = "normal"; - bias-disable; - drive-push-pull; - input-disable; - output-enable; - power-source = <1>; /* 1.8 V */ - qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; - }; -}; - -&pm8550ve_9_gpios { - usb0_1p8_reg_en: usb0-1p8-reg-en-state { - pins = "gpio8"; - function = "normal"; - power-source = <1>; /* 1.8V */ - bias-disable; - input-disable; - output-enable; - }; -}; - -&pmc8380_3_gpios { - edp_bl_en: edp-bl-en-state { - pins = "gpio4"; - function = "normal"; - power-source = <1>; /* 1.8V */ - input-disable; - output-enable; - }; - - edp_bl_reg_en: edp-bl-reg-en-state { - pins = "gpio10"; - function = "normal"; - }; - -}; - -&pmc8380_5_gpios { - usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { - pins = "gpio8"; - function = "normal"; - power-source = <1>; /* 1.8V */ - bias-disable; - input-disable; - output-enable; - }; -}; - -&pmk8550_gpios { - edp_bl_pwm: edp-bl-pwm-state { - pins = "gpio5"; - function = "func3"; - }; -}; - -&pmk8550_pwm { - status = "okay"; -}; - -&qupv3_0 { - status = "okay"; -}; - -&qupv3_1 { - status = "okay"; -}; - -&qupv3_2 { - status = "okay"; +&gpu_zap_shader { + firmware-name = "qcom/x1e80100/hp/omnibook-x14/qcdxkmsuc8380.mbn"; }; &remoteproc_adsp { @@ -1242,335 +33,3 @@ status = "okay"; }; - -&smb2360_0 { - status = "okay"; -}; - -&smb2360_0_eusb2_repeater { - vdd18-supply = <&vreg_l3d_1p8>; - vdd3-supply = <&vreg_l2b_3p0>; -}; - -&smb2360_1 { - status = "okay"; -}; - -&smb2360_1_eusb2_repeater { - vdd18-supply = <&vreg_l3d_1p8>; - vdd3-supply = <&vreg_l14b_3p0>; -}; - -&swr0 { - pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; - pinctrl-names = "default"; - - status = "okay"; - - /* WSA8845, Left Speaker */ - left_spkr: speaker@0,0 { - compatible = "sdw20217020400"; - reg = <0 0>; - reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; - #sound-dai-cells = <0>; - sound-name-prefix = "SpkrLeft"; - vdd-1p8-supply = <&vreg_l15b_1p8>; - vdd-io-supply = <&vreg_l12b_1p2>; - qcom,port-mapping = <1 2 3 7 10 13>; - }; - - /* WSA8845, Right Speaker */ - right_spkr: speaker@0,1 { - compatible = "sdw20217020400"; - reg = <0 1>; - reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; - #sound-dai-cells = <0>; - sound-name-prefix = "SpkrRight"; - vdd-1p8-supply = <&vreg_l15b_1p8>; - vdd-io-supply = <&vreg_l12b_1p2>; - qcom,port-mapping = <4 5 6 7 11 13>; - }; -}; - -&swr1 { - status = "okay"; - - /* WCD9385 RX */ - wcd_rx: codec@0,4 { - compatible = "sdw20217010d00"; - reg = <0 4>; - qcom,rx-port-mapping = <1 2 3 4 5>; - }; -}; - -&swr2 { - status = "okay"; - - /* WCD9385 TX */ - wcd_tx: codec@0,3 { - compatible = "sdw20217010d00"; - reg = <0 3>; - qcom,tx-port-mapping = <2 2 3 4>; - }; -}; - -&tlmm { - gpio-reserved-ranges = <34 2>, /* Unused */ - <44 4>, /* SPI (TPM) */ - <72 2>, /* Secure EC I2C connection (?) */ - <238 1>; /* UFS Reset */ - - edp_reg_en: edp-reg-en-state { - pins = "gpio70"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - }; - - eusb3_reset_n: eusb3-reset-n-state { - pins = "gpio6"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - output-low; - }; - - hall_int_n_default: hall-int-n-state { - pins = "gpio92"; - function = "gpio"; - bias-disable; - }; - - kybd_default: kybd-default-state { - pins = "gpio67"; - function = "gpio"; - bias-pull-up; - }; - - nvme_reg_en: nvme-reg-en-state { - pins = "gpio18"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - pcie4_default: pcie4-default-state { - clkreq-n-pins { - pins = "gpio147"; - function = "pcie4_clk"; - drive-strength = <2>; - bias-pull-up; - }; - - perst-n-pins { - pins = "gpio146"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wake-n-pins { - pins = "gpio148"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie6a_default: pcie6a-default-state { - clkreq-n-pins { - pins = "gpio153"; - function = "pcie6a_clk"; - drive-strength = <2>; - bias-pull-up; - }; - - perst-n-pins { - pins = "gpio152"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wake-n-pins { - pins = "gpio154"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - tpad_default: tpad-default-state { - pins = "gpio3"; - function = "gpio"; - bias-pull-up; - }; - - ts0_default: ts0-default-state { - int-n-pins { - pins = "gpio51"; - function = "gpio"; - bias-pull-up; - }; - - reset-n-pins { - pins = "gpio48"; - function = "gpio"; - output-high; - drive-strength = <16>; - }; - }; - - usb_1_ss1_sbu_default: usb-1-ss1-sbu-state { - mode-pins { - pins = "gpio177"; - function = "gpio"; - bias-disable; - drive-strength = <2>; - output-high; - }; - - oe-n-pins { - pins = "gpio179"; - function = "gpio"; - bias-disable; - drive-strength = <2>; - }; - - sel-pins { - pins = "gpio178"; - function = "gpio"; - bias-disable; - drive-strength = <2>; - }; - }; - - wcd_default: wcd-reset-n-active-state { - pins = "gpio191"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - output-low; - }; - - wcn_sw_en: wcn-sw-en-state { - pins = "gpio214"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wcn_wlan_bt_en: wcn-wlan-bt-en-state { - pins = "gpio116", "gpio117"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; -}; - -&uart14 { - status = "okay"; - - bluetooth { - compatible = "qcom,wcn6855-bt"; - max-speed = <3200000>; - - vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>; - vddaon-supply = <&vreg_pmu_aon_0p8>; - vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; - vddwlmx-supply = <&vreg_pmu_wlmx_0p8>; - vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>; - vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; - vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; - }; -}; - -&usb_1_ss0_hsphy { - vdd-supply = <&vreg_l3j_0p8>; - vdda12-supply = <&vreg_l2j_1p2>; - - phys = <&smb2360_0_eusb2_repeater>; - - status = "okay"; -}; - -&usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; - - status = "okay"; -}; - -&usb_1_ss0 { - status = "okay"; -}; - -&usb_1_ss0_dwc3 { - dr_mode = "host"; -}; - -&usb_1_ss0_dwc3_hs { - remote-endpoint = <&pmic_glink_ss0_hs_in>; -}; - -&usb_1_ss0_qmpphy_out { - remote-endpoint = <&retimer_ss0_ss_in>; -}; - -&usb_1_ss1_hsphy { - vdd-supply = <&vreg_l3j_0p8>; - vdda12-supply = <&vreg_l2j_1p2>; - - phys = <&smb2360_1_eusb2_repeater>; - - status = "okay"; -}; - -&usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; - - status = "okay"; -}; - -&usb_1_ss1 { - status = "okay"; -}; - -&usb_1_ss1_dwc3 { - dr_mode = "host"; -}; - -&usb_1_ss1_dwc3_hs { - remote-endpoint = <&pmic_glink_ss1_hs_in>; -}; - -&usb_1_ss1_qmpphy_out { - remote-endpoint = <&pmic_glink_ss1_ss_in>; -}; - -&usb_mp { - status = "okay"; -}; - -&usb_mp_dwc3 { - phys = <&usb_mp_hsphy0>, <&usb_mp_qmpphy0>; - phy-names = "usb2-0", "usb3-0"; -}; - -&usb_mp_hsphy0 { - vdd-supply = <&vreg_l2e_0p8>; - vdda12-supply = <&vreg_l3e_1p2>; - - phys = <&eusb3_repeater>; - - status = "okay"; -}; - -&usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; - - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts index dad0f11e8e85..e0642fe8343f 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts @@ -18,6 +18,7 @@ aliases { serial0 = &uart21; + serial1 = &uart14; }; chosen { @@ -404,6 +405,107 @@ regulator-always-on; regulator-boot-on; }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + /* + * TODO: These two regulators are actually part of the removable M.2 + * card and not the CRD mainboard. Need to describe this differently. + * Functionally it works correctly, because all we need to do is to + * turn on the actual 3.3V supply above. + */ + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &apps_rsc { @@ -924,6 +1026,11 @@ }; }; +&iris { + firmware-name = "qcom/x1e80100/LENOVO/83ED/qcvss8380.mbn"; + status = "okay"; +}; + &lpass_tlmm { spkr_01_sd_n_active: spkr-01-sd-n-active-state { pins = "gpio12"; @@ -959,7 +1066,6 @@ }; &mdss_dp0_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; @@ -968,7 +1074,6 @@ }; &mdss_dp1_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; @@ -977,13 +1082,15 @@ }; &mdss_dp2_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; &mdss_dp3 { /delete-property/ #sound-dai-cells; + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + status = "okay"; aux-bus { @@ -1002,19 +1109,13 @@ }; }; }; +}; - ports { - port@1 { - reg = <1>; - - mdss_dp3_out: endpoint { - data-lanes = <0 1 2 3>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - remote-endpoint = <&edp_panel_in>; - }; - }; - }; + remote-endpoint = <&edp_panel_in>; }; &mdss_dp3_phy { @@ -1045,6 +1146,16 @@ wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; }; }; @@ -1403,6 +1514,37 @@ drive-strength = <2>; bias-disable; }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; }; &uart21 { diff --git a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi index 0fd8516580b2..ed468b93ba50 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi @@ -331,6 +331,42 @@ regulator-boot-on; }; + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + sound { compatible = "qcom,x1e80100-sndcard"; model = "X1E80100-Romulus"; @@ -410,6 +446,65 @@ }; }; }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &apps_rsc { @@ -949,7 +1044,6 @@ }; &mdss_dp0_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; @@ -958,13 +1052,15 @@ }; &mdss_dp1_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; &mdss_dp3 { /delete-property/ #sound-dai-cells; + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + status = "okay"; aux-bus { @@ -981,19 +1077,13 @@ }; }; }; +}; - ports { - port@1 { - reg = <1>; - - mdss_dp3_out: endpoint { - data-lanes = <0 1 2 3>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - remote-endpoint = <&edp_panel_in>; - }; - }; - }; + remote-endpoint = <&edp_panel_in>; }; &mdss_dp3_phy { @@ -1033,6 +1123,23 @@ status = "okay"; }; +&pcie4_port0 { + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + &pcie6a { perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; @@ -1239,6 +1346,13 @@ bias-disable; }; + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + pcie3_default: pcie3-default-state { perst-n-pins { pins = "gpio143"; @@ -1314,6 +1428,13 @@ output-low; }; + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + cam_indicator_en: cam-indicator-en-state { pins = "gpio225"; function = "gpio"; @@ -1337,6 +1458,23 @@ }; }; +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + &usb_1_ss0_hsphy { vdd-supply = <&vreg_l3j>; vdda12-supply = <&vreg_l2j>; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi index e3888bc143a0..621890ada153 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi @@ -475,6 +475,8 @@ #address-cells = <1>; #size-cells = <0>; + status = "disabled"; + pm8010_temp_alarm: temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; reg = <0x2400>; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index 4dfba835af6a..4a9b6d791e7f 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -318,6 +318,48 @@ regulator-boot-on; }; + vreg_pcie_12v: regulator-pcie-12v { + compatible = "regulator-fixed"; + + regulator-name = "VREG_PCIE_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + + gpio = <&pm8550ve_8_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&pcie_x8_12v>; + pinctrl-names = "default"; + }; + + vreg_pcie_3v3_aux: regulator-pcie-3v3-aux { + compatible = "regulator-fixed"; + + regulator-name = "VREG_PCIE_3P3_AUX"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmc8380_3_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&pm_sde7_aux_3p3_en>; + pinctrl-names = "default"; + }; + + vreg_pcie_3v3: regulator-pcie-3v3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_PCIE_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmc8380_3_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&pm_sde7_main_3p3_en>; + pinctrl-names = "default"; +}; + usb-1-ss0-sbu-mux { compatible = "onnn,fsusb42", "gpio-sbu-mux"; @@ -848,7 +890,6 @@ }; &mdss_dp0_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; @@ -857,7 +898,6 @@ }; &mdss_dp1_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; @@ -866,13 +906,15 @@ }; &mdss_dp2_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; &mdss_dp3 { /delete-property/ #sound-dai-cells; + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + status = "okay"; aux-bus { @@ -887,18 +929,13 @@ }; }; }; +}; - ports { - port@1 { - reg = <1>; - mdss_dp3_out: endpoint { - data-lanes = <0 1 2 3>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - remote-endpoint = <&edp_panel_in>; - }; - }; - }; + remote-endpoint = <&edp_panel_in>; }; &mdss_dp3_phy { @@ -908,6 +945,59 @@ status = "okay"; }; +&pm8550ve_8_gpios { + pcie_x8_12v: pcie-12v-default-state { + pins = "gpio8"; + function = "normal"; + output-enable; + output-high; + bias-pull-down; + power-source = <0>; + }; +}; + +&pmc8380_3_gpios { + pm_sde7_aux_3p3_en: pcie-aux-3p3-default-state { + pins = "gpio8"; + function = "normal"; + output-enable; + output-high; + bias-pull-down; + power-source = <0>; + }; + + pm_sde7_main_3p3_en: pcie-main-3p3-default-state { + pins = "gpio6"; + function = "normal"; + output-enable; + output-high; + bias-pull-down; + power-source = <0>; + }; +}; + +&pcie3 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_default>; + perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&pcie3_phy { + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie3_port { + vpcie12v-supply = <&vreg_pcie_12v>; + vpcie3v3-supply = <&vreg_pcie_3v3>; + vpcie3v3aux-supply = <&vreg_pcie_3v3_aux>; +}; + &pcie4 { perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; @@ -1119,6 +1209,29 @@ bias-disable; }; + pcie3_default: pcie3-default-state { + clkreq-n-pins { + pins = "gpio144"; + function = "pcie3_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio143"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio145"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + pcie4_default: pcie4-default-state { clkreq-n-pins { pins = "gpio147"; @@ -1394,7 +1507,7 @@ vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; - phys = <&eusb6_repeater>; + phys = <&eusb3_repeater>; status = "okay"; }; @@ -1403,7 +1516,7 @@ vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; - phys = <&eusb3_repeater>; + phys = <&eusb6_repeater>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index a9a7bb676c6f..51576d9c935d 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5,6 +5,7 @@ #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> +#include <dt-bindings/clock/qcom,sm8450-videocc.h> #include <dt-bindings/clock/qcom,x1e80100-dispcc.h> #include <dt-bindings/clock/qcom,x1e80100-gcc.h> #include <dt-bindings/clock/qcom,x1e80100-gpucc.h> @@ -2856,6 +2857,7 @@ #clock-cells = <1>; #phy-cells = <1>; + mode-switch; orientation-switch; status = "disabled"; @@ -2926,6 +2928,7 @@ #clock-cells = <1>; #phy-cells = <1>; + mode-switch; orientation-switch; status = "disabled"; @@ -2996,6 +2999,7 @@ #clock-cells = <1>; #phy-cells = <1>; + mode-switch; orientation-switch; status = "disabled"; @@ -3306,6 +3310,17 @@ opp-peak-kBps = <15753000 1>; }; }; + + pcie3_port: pcie@0 { + device_type = "pci"; + compatible = "pciclass,0604"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie3_phy: phy@1be0000 { @@ -3392,10 +3407,10 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 844 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 845 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 772 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_6A_AUX_CLK>, <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, @@ -3524,10 +3539,10 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 71 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 72 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_5_AUX_CLK>, <&gcc GCC_PCIE_5_CFG_AHB_CLK>, @@ -3654,10 +3669,10 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_4_AUX_CLK>, <&gcc GCC_PCIE_4_CFG_AHB_CLK>, @@ -3779,6 +3794,9 @@ qcom,gmu = <&gmu>; #cooling-cells = <2>; + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "gfx-mem"; @@ -3791,11 +3809,28 @@ gpu_opp_table: opp-table { compatible = "operating-points-v2-adreno", "operating-points-v2"; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L5>; + opp-peak-kBps = <16500000>; + qcom,opp-acd-level = <0xa82a5ffd>; + opp-supported-hw = <0x03>; + }; + + opp-1375000000 { + opp-hz = /bits/ 64 <1375000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>; + opp-peak-kBps = <16500000>; + qcom,opp-acd-level = <0xa82a5ffd>; + opp-supported-hw = <0x03>; + }; + opp-1250000000 { opp-hz = /bits/ 64 <1250000000>; opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>; opp-peak-kBps = <16500000>; qcom,opp-acd-level = <0xa82a5ffd>; + opp-supported-hw = <0x07>; }; opp-1175000000 { @@ -3803,13 +3838,24 @@ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>; opp-peak-kBps = <14398438>; qcom,opp-acd-level = <0xa82a5ffd>; + opp-supported-hw = <0x07>; }; - opp-1100000000 { + opp-1100000000-0 { opp-hz = /bits/ 64 <1100000000>; opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; opp-peak-kBps = <14398438>; qcom,opp-acd-level = <0xa82a5ffd>; + opp-supported-hw = <0x07>; + }; + + /* Only applicable for SKUs which has 1100Mhz as Fmax */ + opp-1100000000-1 { + opp-hz = /bits/ 64 <1100000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + opp-peak-kBps = <16500000>; + qcom,opp-acd-level = <0xa82a5ffd>; + opp-supported-hw = <0x08>; }; opp-1000000000 { @@ -3817,6 +3863,7 @@ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; opp-peak-kBps = <14398438>; qcom,opp-acd-level = <0xa82b5ffd>; + opp-supported-hw = <0x0f>; }; opp-925000000 { @@ -3824,6 +3871,7 @@ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; opp-peak-kBps = <14398438>; qcom,opp-acd-level = <0xa82b5ffd>; + opp-supported-hw = <0x0f>; }; opp-800000000 { @@ -3831,6 +3879,7 @@ opp-level = <RPMH_REGULATOR_LEVEL_NOM>; opp-peak-kBps = <12449219>; qcom,opp-acd-level = <0xa82c5ffd>; + opp-supported-hw = <0x0f>; }; opp-744000000 { @@ -3838,13 +3887,24 @@ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; opp-peak-kBps = <10687500>; qcom,opp-acd-level = <0x882e5ffd>; + opp-supported-hw = <0x0f>; }; - opp-687000000 { + opp-687000000-0 { opp-hz = /bits/ 64 <687000000>; opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; opp-peak-kBps = <8171875>; qcom,opp-acd-level = <0x882e5ffd>; + opp-supported-hw = <0x0f>; + }; + + /* Only applicable for SKUs which has 687Mhz as Fmax */ + opp-687000000-1 { + opp-hz = /bits/ 64 <687000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + opp-peak-kBps = <16500000>; + qcom,opp-acd-level = <0x882e5ffd>; + opp-supported-hw = <0x10>; }; opp-550000000 { @@ -3852,6 +3912,7 @@ opp-level = <RPMH_REGULATOR_LEVEL_SVS>; opp-peak-kBps = <6074219>; qcom,opp-acd-level = <0xc0285ffd>; + opp-supported-hw = <0x1f>; }; opp-390000000 { @@ -3859,6 +3920,7 @@ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; opp-peak-kBps = <3000000>; qcom,opp-acd-level = <0xc0285ffd>; + opp-supported-hw = <0x1f>; }; opp-300000000 { @@ -3866,6 +3928,7 @@ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; opp-peak-kBps = <2136719>; qcom,opp-acd-level = <0xc02b5ffd>; + opp-supported-hw = <0x1f>; }; }; }; @@ -5171,6 +5234,107 @@ }; }; + iris: video-codec@aa00000 { + compatible = "qcom,x1e80100-iris", "qcom,sm8550-iris"; + + reg = <0 0x0aa00000 0 0xf0000>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + + power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, + <&videocc VIDEO_CC_MVS0_GDSC>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names = "venus", + "vcodec0", + "mxc", + "mmcx"; + operating-points-v2 = <&iris_opp_table>; + + clocks = <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>; + clock-names = "iface", + "core", + "vcodec0_core"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cpu-cfg", + "video-mem"; + + memory-region = <&video_mem>; + + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; + reset-names = "bus"; + + iommus = <&apps_smmu 0x1940 0>, + <&apps_smmu 0x1947 0>; + dma-coherent; + + /* + * IRIS firmware is signed by vendors, only + * enable on boards where the proper signed firmware + * is available. + */ + status = "disabled"; + + iris_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-192000000 { + opp-hz = /bits/ 64 <192000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>, + <&rpmhpd_opp_low_svs_d1>; + }; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-338000000 { + opp-hz = /bits/ 64 <338000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-366000000 { + opp-hz = /bits/ 64 <366000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-444000000 { + opp-hz = /bits/ 64 <444000000>; + required-opps = <&rpmhpd_opp_nom>, + <&rpmhpd_opp_nom>; + }; + + opp-481000000 { + opp-hz = /bits/ 64 <481000000>; + required-opps = <&rpmhpd_opp_turbo>, + <&rpmhpd_opp_turbo>; + }; + }; + }; + + videocc: clock-controller@aaf0000 { + compatible = "qcom,x1e80100-videocc"; + reg = <0 0x0aaf0000 0 0x10000>; + clocks = <&bi_tcxo_div2>, + <&gcc GCC_VIDEO_AHB_CLK>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: display-subsystem@ae00000 { compatible = "qcom,x1e80100-mdss"; reg = <0 0x0ae00000 0 0x1000>; @@ -5312,16 +5476,20 @@ <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; operating-points-v2 = <&mdss_dp0_opp_table>; @@ -5351,6 +5519,7 @@ reg = <1>; mdss_dp0_out: endpoint { + data-lanes = <0 1 2 3>; remote-endpoint = <&usb_1_ss0_qmpphy_dp_in>; }; }; @@ -5395,16 +5564,20 @@ <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; operating-points-v2 = <&mdss_dp1_opp_table>; @@ -5434,6 +5607,7 @@ reg = <1>; mdss_dp1_out: endpoint { + data-lanes = <0 1 2 3>; remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>; }; }; @@ -5478,16 +5652,20 @@ <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; operating-points-v2 = <&mdss_dp2_opp_table>; @@ -5516,6 +5694,7 @@ reg = <1>; mdss_dp2_out: endpoint { + data-lanes = <0 1 2 3>; remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>; }; }; @@ -5597,6 +5776,9 @@ port@1 { reg = <1>; + + mdss_dp3_out: endpoint { + }; }; }; @@ -5779,6 +5961,12 @@ gpio-ranges = <&tlmm 0 0 239>; wakeup-parent = <&pdc>; + edp0_hpd_default: edp0-hpd-default-state { + pins = "gpio119"; + function = "edp0_hot"; + bias-disable; + }; + qup_i2c0_data_clk: qup-i2c0-data-clk-state { /* SDA, SCL */ pins = "gpio0", "gpio1"; @@ -8251,6 +8439,18 @@ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; }; + qfprom: efuse@221c8000 { + compatible = "qcom,x1e80100-qfprom", "qcom,qfprom"; + reg = <0 0x221c8000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + gpu_speed_bin: gpu-speed-bin@119 { + reg = <0x119 0x2>; + bits = <7 8>; + }; + }; + pmu@24091000 { compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; reg = <0 0x24091000 0 0x1000>; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts index cf07860a63e9..cf999c2cf8d4 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts @@ -15,3 +15,7 @@ model = "Qualcomm Technologies, Inc. X1P42100 CRD"; compatible = "qcom,x1p42100-crd", "qcom,x1p42100"; }; + +&gpu_zap_shader { + firmware-name = "qcom/x1p42100/gen71500_zap.mbn"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts b/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts new file mode 100644 index 000000000000..6696cab2de3e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/dts-v1/; + +#include "x1p42100.dtsi" +#include "x1e80100-pmics.dtsi" +#include "x1-hp-omnibook-x14.dtsi" +/delete-node/ &pmc8380_6; +/delete-node/ &pmc8380_6_thermal; + +/ { + model = "HP Omnibook X 14-fe1"; + compatible = "hp,omnibook-x14-fe1", "qcom,x1p42100"; + chassis-type = "laptop"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/x1p42100/hp/omnibook-x14/qcdxkmsucpurwa.mbn"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1p42100/hp/omnibook-x14/qcadsp8380.mbn", + "qcom/x1p42100/hp/omnibook-x14/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1p42100/hp/omnibook-x14/qccdsp8380.mbn", + "qcom/x1p42100/hp/omnibook-x14/cdsp_dtbs.elf"; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts new file mode 100644 index 000000000000..1ac46cdc4386 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts @@ -0,0 +1,1625 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024, Linaro Limited + * Copyright (c) 2025, Jens Glathe + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/gpio-keys.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> + +#include "x1p42100.dtsi" +#include "x1e80100-pmics.dtsi" + +/delete-node/ &pmc8380_6; +/delete-node/ &pmc8380_6_thermal; + +/ { + model = "Lenovo ThinkBook 16 Gen 7 QOY"; + compatible = "lenovo,thinkbook-16", "qcom,x1p42100"; + chassis-type = "laptop"; + + aliases { + serial0 = &uart21; + serial1 = &uart14; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pm8550_pwm 3 500000>; + + power-supply = <&vreg_edp_bl>; + }; + + /* + * This is an odd one. The camera is physically behind the eusb9 repeater (confirmed) but + * if it is placed below the usb_2_dwc3 node, it will be switched off after ~30 seconds. + * The reason seems to be that the dwc3 driver does not probe for child nodes when in + * host-only mode. But that's the default setting for the xhci controllers due to issues + * when in OTG mode. https://lore.kernel.org/all/20241210111444.26240-1-johan+linaro@kernel.org/ + * The whole reason it is described in the dt (as an USB device) is its requirement for + * that additional regulator, and to get power management to switch it off when suspended. + * Defining it stand-alone does work. + */ + camera { + compatible = "usb5986,1198"; + + vdd-supply = <&vreg_cam_5p0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&hall_int_n_default>; + pinctrl-names = "default"; + + switch-lid { + gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; + linux,input-type = <EV_SW>; + linux,code = <SW_LID>; + wakeup-source; + wakeup-event-action = <EV_ACT_DEASSERTED>; + }; + }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>; + + /* Display-adjacent port */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "host"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss0_sbu: endpoint { + remote-endpoint = <&usb_1_ss0_sbu_mux>; + }; + }; + }; + }; + + /* User-adjacent port */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "host"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss1_sbu: endpoint { + remote-endpoint = <&usb_1_ss1_sbu_mux>; + }; + }; + }; + }; + }; + + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E80100-LENOVO-ThinkBook-16"; + audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT", + "SpkrRight IN", "WSA WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS3", + "VA DMIC1", "MIC BIAS3", + "VA DMIC2", "MIC BIAS1", + "VA DMIC3", "MIC BIAS1", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + usb-1-ss0-sbu-mux { + compatible = "onnn,fsusb42", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 167 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 168 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb_1_ss0_sbu_default>; + pinctrl-names = "default"; + + mode-switch; + orientation-switch; + + port { + usb_1_ss0_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_ss0_sbu>; + }; + }; + }; + + usb-1-ss1-sbu-mux { + compatible = "onnn,fsusb42", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 178 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 179 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb_1_ss1_sbu_default>; + pinctrl-names = "default"; + + mode-switch; + orientation-switch; + + port { + usb_1_ss1_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_ss1_sbu>; + }; + }; + }; + + vreg_cam_5p0: regulator-cam-5p0 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_CAM_5P0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&tlmm 44 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&cam_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_edp_bl: regulator-edp-bl { + compatible = "regulator-fixed"; + + regulator-name = "VBL9"; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + + gpio = <&pmc8380_3_gpios 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_bl_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_misc_3p3: regulator-misc-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_MISC_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550ve_8_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&misc_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + regulator-always-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5b_3p0: ldo5 { + regulator-name = "vreg_l5b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7b_2p8: ldo7 { + regulator-name = "vreg_l7b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name = "vreg_l8b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name = "vreg_l10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-always-on; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-always-on; + }; + + vreg_l16b_2p9: ldo16 { + regulator-name = "vreg_l16b_2p9"; + regulator-min-microvolt = <2912000>; + regulator-max-microvolt = <2912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name = "vreg_l2c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-4 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name = "vreg_s1f_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1f_1p0: ldo1 { + regulator-name = "vreg_l1f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2f_1p0: ldo2 { + regulator-name = "vreg_l2f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3f_1p0: ldo3 { + regulator-name = "vreg_l3f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + + vreg_l1i_1p8: ldo1 { + regulator-name = "vreg_l1i_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-always-on; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s1i_0p9: smps1 { + regulator-name = "vreg_s1i_0p9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s2i_1p0: smps2 { + regulator-name = "vreg_s2i_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name = "vreg_l1j_0p8"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/x1p42100/LENOVO/21NH/qcdxkmsucpurwa.mbn"; +}; + +&i2c2 { + clock-frequency = <400000>; + + pinctrl-0 = <&qup_i2c2_data_clk>, <&tpad_default>, <&kybd_default>; + pinctrl-names = "default"; + status = "okay"; + + /* ELAN06FA */ + touchpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + wakeup-source; + }; + + /* CIRQ1080 or SYNA2BA6 */ + touchpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + + hid-descr-addr = <0x20>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + wakeup-source; + }; + + /* FTCS0038 */ + touchpad@38 { + compatible = "hid-over-i2c"; + reg = <0x38>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + wakeup-source; + }; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + wakeup-source; + }; + + /* GXTP5100 */ + touchpad@5d { + compatible = "hid-over-i2c"; + reg = <0x5d>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + wakeup-source; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + eusb5_repeater: redriver@43 { + compatible = "nxp,ptn3222"; + reg = <0x43>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + }; + + eusb3_repeater: redriver@47 { + compatible = "nxp,ptn3222"; + reg = <0x47>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb3_reset_n>; + pinctrl-names = "default"; + }; + + eusb9_repeater: redriver@4b { + compatible = "nxp,ptn3222"; + reg = <0x4b>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb9_reset_n>; + pinctrl-names = "default"; + }; + + eusb6_repeater: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb6_reset_n>; + pinctrl-names = "default"; + }; +}; + +&i2c8 { + clock-frequency = <400000>; + + status = "okay"; + + /* ILIT2911 or GTCH1563 */ + touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l15b_1p8>; + + pinctrl-0 = <&ts0_default>; + pinctrl-names = "default"; + }; +}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>, <&dmic23_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <4800000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + pinctrl-0 = <&edp_hpd_default>; + pinctrl-names = "default"; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + + backlight = <&backlight>; + + enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&edp_bl_en>; + pinctrl-names = "default"; + + power-supply = <&vreg_edp_3p3>; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; +}; + +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie4 { + perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie4_port0 { + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie6a { + perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie6a_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pm8550_pwm { + status = "okay"; +}; + +&pm8550ve_8_gpios { + misc_3p3_reg_en: misc-3p3-reg-en-state { + pins = "gpio6"; + function = "normal"; + bias-disable; + input-disable; + output-enable; + drive-push-pull; + power-source = <1>; /* 1.8 V */ + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; + }; +}; + +&pmc8380_3_gpios { + edp_bl_en: edp-bl-en-state { + pins = "gpio4"; + function = "normal"; + power-source = <1>; /* 1.8V */ + input-disable; + output-enable; + }; + + edp_bl_reg_en: edp-bl-reg-en-state { + pins = "gpio10"; + function = "normal"; + }; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1p42100/LENOVO/21NH/qcadsp8380.mbn", + "qcom/x1p42100/LENOVO/21NH/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1p42100/LENOVO/21NH/qccdsp8380.mbn", + "qcom/x1p42100/LENOVO/21NH/cdsp_dtbs.elf"; + + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 71 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l6b_1p8>; + status = "okay"; +}; + +&smb2360_0 { + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1 { + status = "okay"; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&swr0 { + status = "okay"; + + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Left Speaker */ + left_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Speaker */ + right_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&tlmm { + gpio-reserved-ranges = <34 2>, /* Unused */ + <72 2>; /* Secure EC I2C connection (?) */ + + edp_hpd_default: edp-hpd-default-state { + pins = "gpio119"; + function = "edp0_hot"; + bias-disable; + }; + + cam_reg_en: cam-reg-en-state { + pins = "gpio44"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + eusb3_reset_n: eusb3-reset-n-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + eusb6_reset_n: eusb6-reset-n-state { + pins = "gpio184"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + eusb9_reset_n: eusb9-reset-n-state { + pins = "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + hall_int_n_default: hall-int-n-state { + pins = "gpio92"; + function = "gpio"; + bias-disable; + }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_card_det_n: sdc2-card-det-state { + pins = "gpio71"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-pull-up; + }; + + ts0_default: ts0-default-state { + int-n-pins { + pins = "gpio51"; + function = "gpio"; + bias-disable; + }; + + reset-n-pins { + pins = "gpio48"; + function = "gpio"; + output-high; + drive-strength = <16>; + }; + }; + + usb_1_ss0_sbu_default: usb-1-ss0-sbu-state { + oe-n-pins { + pins = "gpio167"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + + sel-pins { + pins = "gpio168"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + + }; + + usb_1_ss1_sbu_default: usb-1-ss1-sbu-state { + oe-n-pins { + pins = "gpio178"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + + sel-pins { + pins = "gpio179"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio191"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_0_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + + status = "okay"; +}; + +&usb_1_ss0 { + status = "okay"; +}; + +&usb_1_ss0_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&pmic_glink_ss0_ss_in>; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_1_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_1_ss1 { + status = "okay"; +}; + +&usb_1_ss1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss1_ss_in>; +}; + +&usb_1_ss2 { + status = "okay"; +}; + +&usb_1_ss2_dwc3 { + dr_mode = "host"; + maximum-speed = "high-speed"; + phys = <&usb_1_ss2_hsphy>; + phy-names = "usb2-phy"; +}; + +&usb_1_ss2_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&eusb5_repeater>; + + status = "okay"; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb9_repeater>; + + status = "okay"; +}; + +&usb_mp { + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb6_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb3_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1p42100.dtsi b/arch/arm64/boot/dts/qcom/x1p42100.dtsi index 9af9e707f982..10d26958d3c6 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1p42100.dtsi @@ -17,6 +17,8 @@ /delete-node/ &cpu_pd9; /delete-node/ &cpu_pd10; /delete-node/ &cpu_pd11; +/delete-node/ &gpu_opp_table; +/delete-node/ &gpu_speed_bin; /delete-node/ &pcie3_phy; /delete-node/ &thermal_zones; @@ -24,9 +26,117 @@ compatible = "qcom,x1p42100-gcc", "qcom,x1e80100-gcc"; }; -/* The GPU is physically different and will be brought up later */ +&gmu { + compatible = "qcom,adreno-gmu-x145.0", "qcom,adreno-gmu"; +}; + &gpu { - /delete-property/ compatible; + compatible = "qcom,adreno-43030c00", "qcom,adreno"; + + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2-adreno", "operating-points-v2"; + + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>; + opp-peak-kBps = <16500000>; + qcom,opp-acd-level = <0xa8295ffd>; + opp-supported-hw = <0x3>; + }; + + opp-1250000000 { + opp-hz = /bits/ 64 <1250000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>; + opp-peak-kBps = <16500000>; + qcom,opp-acd-level = <0x882a5ffd>; + opp-supported-hw = <0x7>; + }; + + opp-1107000000 { + opp-hz = /bits/ 64 <1107000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + opp-peak-kBps = <16500000>; + qcom,opp-acd-level = <0x882a5ffd>; + opp-supported-hw = <0xf>; + }; + + opp-1014000000 { + opp-hz = /bits/ 64 <1014000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + opp-peak-kBps = <14398438>; + qcom,opp-acd-level = <0xa82a5ffd>; + opp-supported-hw = <0xf>; + }; + + opp-940000000 { + opp-hz = /bits/ 64 <940000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + opp-peak-kBps = <14398438>; + qcom,opp-acd-level = <0xa82a5ffd>; + opp-supported-hw = <0xf>; + }; + + opp-825000000 { + opp-hz = /bits/ 64 <825000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + opp-peak-kBps = <12449219>; + qcom,opp-acd-level = <0x882b5ffd>; + opp-supported-hw = <0xf>; + }; + + opp-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; + opp-peak-kBps = <10687500>; + qcom,opp-acd-level = <0xa82c5ffd>; + opp-supported-hw = <0xf>; + }; + + opp-666000000-0 { + opp-hz = /bits/ 64 <666000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + opp-peak-kBps = <8171875>; + qcom,opp-acd-level = <0xa82d5ffd>; + opp-supported-hw = <0xf>; + }; + + /* Only applicable for SKUs which has 666Mhz as Fmax */ + opp-666000000-1 { + opp-hz = /bits/ 64 <666000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + opp-peak-kBps = <16500000>; + qcom,opp-acd-level = <0xa82d5ffd>; + opp-supported-hw = <0x10>; + }; + + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + opp-peak-kBps = <6074219>; + qcom,opp-acd-level = <0x882e5ffd>; + opp-supported-hw = <0x1f>; + }; + + opp-380000000 { + opp-hz = /bits/ 64 <380000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + opp-peak-kBps = <3000000>; + qcom,opp-acd-level = <0xc82f5ffd>; + opp-supported-hw = <0x1f>; + }; + + opp-280000000 { + opp-hz = /bits/ 64 <280000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; + opp-peak-kBps = <2136719>; + qcom,opp-acd-level = <0xc82f5ffd>; + opp-supported-hw = <0x1f>; + }; + }; + }; &gpucc { @@ -42,6 +152,13 @@ compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy"; }; +&qfprom { + gpu_speed_bin: gpu-speed-bin@119 { + reg = <0x119 0x2>; + bits = <7 9>; + }; +}; + &soc { /* The PCIe3 PHY on X1P42100 uses a different IP block */ pcie3_phy: phy@1bd4000 { diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 6093d5f6e548..ccdf7aaeca13 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -96,6 +96,18 @@ dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g2-white-hawk-single-ard-audio-da7212.dtb DTC_FLAGS_r8a779g3-sparrow-hawk += -Wno-spi_bus_bridge dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk.dtb +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j1-imx219.dtbo +r8a779g3-sparrow-hawk-camera-j1-imx219-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-camera-j1-imx219.dtbo +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j1-imx219.dtb +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j1-imx462.dtbo +r8a779g3-sparrow-hawk-camera-j1-imx462-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-camera-j1-imx462.dtbo +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j1-imx462.dtb +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j2-imx219.dtbo +r8a779g3-sparrow-hawk-camera-j2-imx219-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-camera-j2-imx219.dtbo +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j2-imx219.dtb +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j2-imx462.dtbo +r8a779g3-sparrow-hawk-camera-j2-imx462-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-camera-j2-imx462.dtbo +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j2-imx462.dtb dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-fan-pwm.dtbo r8a779g3-sparrow-hawk-fan-pwm-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-fan-pwm.dtbo dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-fan-pwm.dtb @@ -180,5 +192,9 @@ r9a09g057h44-rzv2h-evk-cn15-sd-dtbs := r9a09g057h44-rzv2h-evk.dtb rzv2-evk-cn15- dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-rzv2h-evk-cn15-sd.dtb dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h48-kakip.dtb +dtb-$(CONFIG_ARCH_R9A09G077) += r9a09g077m44-rzt2h-evk.dtb + +dtb-$(CONFIG_ARCH_R9A09G087) += r9a09g087m44-rzn2h-evk.dtb + dtb-$(CONFIG_ARCH_RCAR_GEN3) += draak-ebisu-panel-aa104xd12.dtbo dtb-$(CONFIG_ARCH_RCAR_GEN3) += salvator-panel-aa104xd12.dtbo diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index c8b87aed92a3..6b737d91b320 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -1186,7 +1186,7 @@ <&can_clk>; clock-names = "fck", "canfd", "can_clk"; assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; - assigned-clock-rates = <40000000>; + assigned-clock-rates = <80000000>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 914>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index f2fc2a2035a1..3f15d656215e 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -1070,7 +1070,7 @@ <&can_clk>; clock-names = "fck", "canfd", "can_clk"; assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>; - assigned-clock-rates = <40000000>; + assigned-clock-rates = <80000000>; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 914>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 530ffd29cf13..55df063cb323 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1029,7 +1029,7 @@ <&can_clk>; clock-names = "fck", "canfd", "can_clk"; assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; - assigned-clock-rates = <40000000>; + assigned-clock-rates = <80000000>; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 914>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index e4dbda8c34d9..5d730b488d46 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -1298,7 +1298,7 @@ <&can_clk>; clock-names = "fck", "canfd", "can_clk"; assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; - assigned-clock-rates = <40000000>; + assigned-clock-rates = <80000000>; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 914>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 6ee9cdeb5a3a..c389ebc7e6ce 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -1373,7 +1373,7 @@ <&can_clk>; clock-names = "fck", "canfd", "can_clk"; assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; - assigned-clock-rates = <40000000>; + assigned-clock-rates = <80000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 914>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index a323ac47ca70..6d039019905d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -1245,7 +1245,7 @@ <&can_clk>; clock-names = "fck", "canfd", "can_clk"; assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; - assigned-clock-rates = <40000000>; + assigned-clock-rates = <80000000>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 914>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 49f6d31c5903..1637b534fc68 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -1245,7 +1245,7 @@ <&can_clk>; clock-names = "fck", "canfd", "can_clk"; assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>; - assigned-clock-rates = <40000000>; + assigned-clock-rates = <80000000>; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 914>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 136a22ca50b7..353a77187089 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -1108,7 +1108,7 @@ <&can_clk>; clock-names = "fck", "canfd", "can_clk"; assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>; - assigned-clock-rates = <40000000>; + assigned-clock-rates = <80000000>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 914>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 01744496805c..e7a5800bf742 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -568,7 +568,7 @@ <&can_clk>; clock-names = "fck", "canfd", "can_clk"; assigned-clocks = <&cpg CPG_CORE R8A77970_CLK_CANFD>; - assigned-clock-rates = <40000000>; + assigned-clock-rates = <80000000>; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 914>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index f7e506ad7a21..964aa14f3e65 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -621,7 +621,7 @@ <&can_clk>; clock-names = "fck", "canfd", "can_clk"; assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>; - assigned-clock-rates = <40000000>; + assigned-clock-rates = <80000000>; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 914>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 6b8742045836..e16ede6eb379 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -1061,7 +1061,7 @@ <&can_clk>; clock-names = "fck", "canfd", "can_clk"; assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>; - assigned-clock-rates = <40000000>; + assigned-clock-rates = <80000000>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 914>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 95ff69339991..2c3fb34abb28 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -2949,7 +2949,7 @@ }; }; - dsi0: dsi-encoder@fed80000 { + dsi0: dsi@fed80000 { compatible = "renesas,r8a779a0-dsi-csi2-tx"; reg = <0 0xfed80000 0 0x10000>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -2977,7 +2977,7 @@ }; }; - dsi1: dsi-encoder@fed90000 { + dsi1: dsi@fed90000 { compatible = "renesas,r8a779a0-dsi-csi2-tx"; reg = <0 0xfed90000 0 0x10000>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 8d9ca30c299c..4fae063bf91b 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -2476,7 +2476,7 @@ }; }; - dsi0: dsi-encoder@fed80000 { + dsi0: dsi@fed80000 { compatible = "renesas,r8a779g0-dsi-csi2-tx"; reg = <0 0xfed80000 0 0x10000>; clocks = <&cpg CPG_MOD 415>, @@ -2505,7 +2505,7 @@ }; }; - dsi1: dsi-encoder@fed90000 { + dsi1: dsi@fed90000 { compatible = "renesas,r8a779g0-dsi-csi2-tx"; reg = <0 0xfed90000 0 0x10000>; clocks = <&cpg CPG_MOD 416>, diff --git a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j1-imx219.dtso b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j1-imx219.dtso new file mode 100644 index 000000000000..3acaf714cf24 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j1-imx219.dtso @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Overlay for an IMX219 camera sensor on connector J1 on R-Car V4H + * ES3.0 Sparrow Hawk board. + * + * Copyright 2025 Renesas Electronics Corp. + * Copyright 2025 Niklas Söderlund <niklas.soderlund@ragnatech.se> + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/media/video-interfaces.h> + +&{/} { + clk_cam_j1: clk-cam-j1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + /* Page 29 / CSI_IF_CN / J1 */ + reg_cam_j1: reg-cam-j1 { + compatible = "regulator-fixed"; + regulator-name = "cam-J1"; + enable-active-high; + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + cam@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_cam_j1>; + + VANA-supply = <®_cam_j1>; + VDIG-supply = <®_cam_j1>; + VDDL-supply = <®_cam_j1>; + + orientation = <2>; + rotation = <0>; + + port { + imx219_j1_out: endpoint { + clock-noncontinuous; + link-frequencies = /bits/ 64 <456000000>; + data-lanes = <1 2>; + remote-endpoint = <&csi40_in>; + }; + }; + }; +}; + +/* Page 29 / CSI_IF_CN */ +&csi40 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi40_in: endpoint { + bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>; + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&imx219_j1_out>; + }; + }; + }; +}; + +&isp0 { + status = "okay"; +}; + +&vin00 { + status = "okay"; +}; + +&vin01 { + status = "okay"; +}; + +&vin02 { + status = "okay"; +}; + +&vin03 { + status = "okay"; +}; + +&vin04 { + status = "okay"; +}; + +&vin05 { + status = "okay"; +}; + +&vin06 { + status = "okay"; +}; + +&vin07 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j1-imx462.dtso b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j1-imx462.dtso new file mode 100644 index 000000000000..a19bc0840392 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j1-imx462.dtso @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Overlay for an IMX462 camera sensor on connector J1 on R-Car V4H + * ES3.0 Sparrow Hawk board. + * + * Copyright 2025 Renesas Electronics Corp. + * Copyright 2025 Niklas Söderlund <niklas.soderlund@ragnatech.se> + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/media/video-interfaces.h> + +&{/} { + clk_cam_j1: clk-cam-j1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <37125000>; + }; + + /* Page 29 / CSI_IF_CN / J1 */ + reg_cam_j1: reg-cam-j1 { + compatible = "regulator-fixed"; + regulator-name = "cam-J1"; + enable-active-high; + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + cam@1a { + compatible = "sony,imx462lqr"; + reg = <0x1a>; + + clocks = <&clk_cam_j1>; + clock-names = "xclk"; + clock-frequency = <37125000>; + + vdddo-supply = <®_cam_j1>; + vdda-supply = <®_cam_j1>; + vddd-supply = <®_cam_j1>; + + orientation = <2>; + rotation = <0>; + + port { + imx462_j1_out: endpoint { + link-frequencies = /bits/ 64 <222750000 148500000>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi40_in>; + }; + }; + }; +}; + +/* Page 29 / CSI_IF_CN */ +&csi40 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi40_in: endpoint { + bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&imx462_j1_out>; + }; + }; + }; +}; + +&isp0 { + status = "okay"; +}; + +&vin00 { + status = "okay"; +}; + +&vin01 { + status = "okay"; +}; + +&vin02 { + status = "okay"; +}; + +&vin03 { + status = "okay"; +}; + +&vin04 { + status = "okay"; +}; + +&vin05 { + status = "okay"; +}; + +&vin06 { + status = "okay"; +}; + +&vin07 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j2-imx219.dtso b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j2-imx219.dtso new file mode 100644 index 000000000000..512810b861aa --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j2-imx219.dtso @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Overlay for an IMX219 camera sensor on connector J2 on R-Car V4H + * ES3.0 Sparrow Hawk board. + * + * Copyright 2025 Renesas Electronics Corp. + * Copyright 2025 Niklas Söderlund <niklas.soderlund@ragnatech.se> + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/media/video-interfaces.h> + +&{/} { + clk_cam_j2: clk-cam-j2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + /* Page 29 / CSI_IF_CN / J2 */ + reg_cam_j2: reg-cam-j2 { + compatible = "regulator-fixed"; + regulator-name = "cam-J2"; + enable-active-high; + gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + cam@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_cam_j2>; + + VANA-supply = <®_cam_j2>; + VDIG-supply = <®_cam_j2>; + VDDL-supply = <®_cam_j2>; + + orientation = <2>; + rotation = <0>; + + port { + imx219_j2_out: endpoint { + clock-noncontinuous; + link-frequencies = /bits/ 64 <456000000>; + data-lanes = <1 2>; + remote-endpoint = <&csi41_in>; + }; + }; + }; +}; + +/* Page 29 / CSI_IF_CN */ +&csi41 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi41_in: endpoint { + bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>; + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&imx219_j2_out>; + }; + }; + }; +}; + +&isp1 { + status = "okay"; +}; + +&vin08 { + status = "okay"; +}; + +&vin09 { + status = "okay"; +}; + +&vin10 { + status = "okay"; +}; + +&vin11 { + status = "okay"; +}; + +&vin12 { + status = "okay"; +}; + +&vin13 { + status = "okay"; +}; + +&vin14 { + status = "okay"; +}; + +&vin15 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j2-imx462.dtso b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j2-imx462.dtso new file mode 100644 index 000000000000..a31524b59834 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j2-imx462.dtso @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Overlay for an IMX462 camera sensor on connector J2 on R-Car V4H + * ES3.0 Sparrow Hawk board. + * + * Copyright 2025 Renesas Electronics Corp. + * Copyright 2025 Niklas Söderlund <niklas.soderlund@ragnatech.se> + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/media/video-interfaces.h> + +&{/} { + clk_cam_j2: clk-cam-j2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <37125000>; + }; + + /* Page 29 / CSI_IF_CN / J2 */ + reg_cam_j2: reg-cam-j2 { + compatible = "regulator-fixed"; + regulator-name = "cam-J2"; + enable-active-high; + gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + cam@1a { + compatible = "sony,imx462lqr"; + reg = <0x1a>; + + clocks = <&clk_cam_j2>; + clock-names = "xclk"; + clock-frequency = <37125000>; + + vdddo-supply = <®_cam_j2>; + vdda-supply = <®_cam_j2>; + vddd-supply = <®_cam_j2>; + + orientation = <2>; + rotation = <0>; + + port { + imx462_j2_out: endpoint { + link-frequencies = /bits/ 64 <222750000 148500000>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi41_in>; + }; + }; + }; +}; + +/* Page 29 / CSI_IF_CN */ +&csi41 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi41_in: endpoint { + bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&imx462_j2_out>; + }; + }; + }; +}; + +&isp1 { + status = "okay"; +}; + +&vin08 { + status = "okay"; +}; + +&vin09 { + status = "okay"; +}; + +&vin10 { + status = "okay"; +}; + +&vin11 { + status = "okay"; +}; + +&vin12 { + status = "okay"; +}; + +&vin13 { + status = "okay"; +}; + +&vin14 { + status = "okay"; +}; + +&vin15 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-fan-pwm.dtso b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-fan-pwm.dtso index 50d53c8d76c5..fbfec57db11e 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-fan-pwm.dtso +++ b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-fan-pwm.dtso @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* - * Device Tree Overlay for the PWM controlled blower fan in connector J3:FAN + * Device Tree Overlay for the PWM controlled blower fan on connector J3:FAN * on R-Car V4H ES3.0 Sparrow Hawk board * * Copyright (C) 2025 Marek Vasut <marek.vasut+renesas@mailbox.org> @@ -9,21 +9,16 @@ * * # Localize hwmon sysfs directory that matches the PWM fan, * # enable the PWM fan, and configure the fan speed manually. - * r8a779g3-sparrow-hawk$ grep -H . /sys/class/hwmon/hwmon?/name - * /sys/class/hwmon/hwmon0/name:sensor1_thermal - * /sys/class/hwmon/hwmon1/name:sensor2_thermal - * /sys/class/hwmon/hwmon2/name:sensor3_thermal - * /sys/class/hwmon/hwmon3/name:sensor4_thermal - * /sys/class/hwmon/hwmon4/name:pwmfan - * ^ ^^^^^^ + * r8a779g3-sparrow-hawk$ ls -1 /sys/devices/platform/pwm-fan/hwmon/hwmon?/pwm?_enable + * /sys/devices/platform/pwm-fan/hwmon/hwmon4/pwm1_enable * * # Select mode 2 , enable fan PWM and regulator and keep them enabled. * # For details, see Linux Documentation/hwmon/pwm-fan.rst - * r8a779g3-sparrow-hawk$ echo 2 > /sys/class/hwmon/hwmon4/pwm1_enable + * r8a779g3-sparrow-hawk$ echo 2 > /sys/devices/platform/pwm-fan/hwmon/hwmon4/pwm1_enable * * # Configure PWM fan speed in range 0..255 , 0 is stopped , 255 is full speed . * # Fan speed 101 is about 2/5 of the PWM fan speed: - * r8a779g3-sparrow-hawk$ echo 101 > /sys/class/hwmon/hwmon4/pwm1 + * r8a779g3-sparrow-hawk$ echo 101 > /sys/devices/platform/pwm-fan/hwmon/hwmon4/pwm1 */ /dts-v1/; diff --git a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts index 9ba23129e65e..1da8e476b219 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts +++ b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts @@ -38,6 +38,7 @@ /dts-v1/; #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/thermal/thermal.h> #include "r8a779g3.dtsi" @@ -185,7 +186,42 @@ regulator-max-microvolt = <3300000>; gpios = <&gpio8 13 GPIO_ACTIVE_HIGH>; gpios-states = <1>; - states = <3300000 0>, <1800000 1>; + states = <1800000 0>, <3300000 1>; + }; +}; + +/* Use thermal-idle cooling for all SoC cores */ +&a76_0 { + #cooling-cells = <2>; + + a76_0_thermal_idle: thermal-idle { + #cooling-cells = <2>; + duration-us = <10000>; + exit-latency-us = <500>; + }; +}; + +&a76_1 { + a76_1_thermal_idle: thermal-idle { + #cooling-cells = <2>; + duration-us = <10000>; + exit-latency-us = <500>; + }; +}; + +&a76_2 { + a76_2_thermal_idle: thermal-idle { + #cooling-cells = <2>; + duration-us = <10000>; + exit-latency-us = <500>; + }; +}; + +&a76_3 { + a76_3_thermal_idle: thermal-idle { + #cooling-cells = <2>; + duration-us = <10000>; + exit-latency-us = <500>; }; }; @@ -556,6 +592,10 @@ drive-strength = <21>; }; + pins-vddq18-25-avb { + pins = "PIN_VDDQ_AVB0", "PIN_VDDQ_AVB1", "PIN_VDDQ_AVB2", "PIN_VDDQ_TSN0"; + power-source = <1800>; + }; }; /* Page 28 / CANFD_IF */ @@ -756,7 +796,11 @@ status = "okay"; flash@0 { - compatible = "spansion,s25fs512s", "jedec,spi-nor"; + /* + * EVTA1 is populated with Spansion S25FS512S + * EVTB1 is populated with Winbond W77Q51NW + */ + compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <40000000>; spi-rx-bus-width = <4>; @@ -797,3 +841,104 @@ &scif_clk { /* X12 */ clock-frequency = <24000000>; }; + +/* THS sensors in SoC, critical temperature trip point is 100C */ +&sensor1_crit { + temperature = <100000>; +}; + +&sensor2_crit { + temperature = <100000>; +}; + +&sensor3_crit { + temperature = <100000>; +}; + +&sensor4_crit { + temperature = <100000>; +}; + +/* THS sensor in SoC near CA76 cores does more progressive cooling. */ +&sensor_thermal_ca76 { + critical-action = "shutdown"; + + cooling-maps { + /* + * The cooling-device minimum and maximum parameters inversely + * match opp-table-0 {} node entries in r8a779g0.dtsi, in other + * words, 0 refers to 1.8 GHz OPP and 4 refers to 500 MHz OPP. + * This is because they refer to cooling levels, where maximum + * cooling level happens at 500 MHz OPP, when the CPU core is + * running slowly and therefore generates least heat. + */ + map0 { + /* At 68C, inhibit 1.7 GHz and 1.8 GHz modes */ + trip = <&sensor3_passive_low>; + cooling-device = <&a76_0 2 4>; + contribution = <128>; + }; + + map1 { + /* At 72C, inhibit 1.5 GHz mode */ + trip = <&sensor3_passive_mid>; + cooling-device = <&a76_0 3 4>; + contribution = <256>; + }; + + map2 { + /* At 76C, start injecting idle states 0..80% of time */ + trip = <&sensor3_passive_hi>; + cooling-device = <&a76_0_thermal_idle 0 80>, + <&a76_1_thermal_idle 0 80>, + <&a76_2_thermal_idle 0 80>, + <&a76_3_thermal_idle 0 80>; + contribution = <512>; + }; + + map3 { + /* At 80C, inhibit 1.0 GHz mode */ + trip = <&sensor3_passive_crit>; + cooling-device = <&a76_0 4 4>; + contribution = <1024>; + }; + }; + + trips { + sensor3_passive_low: sensor3-passive-low { + temperature = <68000>; + hysteresis = <2000>; + type = "passive"; + }; + + sensor3_passive_mid: sensor3-passive-mid { + temperature = <72000>; + hysteresis = <2000>; + type = "passive"; + }; + + sensor3_passive_hi: sensor3-passive-hi { + temperature = <76000>; + hysteresis = <2000>; + type = "passive"; + }; + + sensor3_passive_crit: sensor3-passive-crit { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + }; +}; + +&sensor_thermal_cnn { + critical-action = "shutdown"; +}; + +&sensor_thermal_cr52 { + critical-action = "shutdown"; +}; + +&sensor_thermal_ddr1 { + critical-action = "shutdown"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index ed1eefa3515d..0f20a2d23983 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -2144,7 +2144,7 @@ }; }; - dsi0: dsi-encoder@fed80000 { + dsi0: dsi@fed80000 { compatible = "renesas,r8a779h0-dsi-csi2-tx"; reg = <0 0xfed80000 0 0x10000>; clocks = <&cpg CPG_MOD 415>, diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 0364f89776e6..16e6ac614417 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -272,6 +272,42 @@ }; }; + i3c: i3c@1005b000 { + compatible = "renesas,r9a08g045-i3c"; + reg = <0 0x1005b000 0 0x1000>; + clocks = <&cpg CPG_MOD R9A08G045_I3C_PCLK>, + <&cpg CPG_MOD R9A08G045_I3C_TCLK>; + clock-names = "pclk", "tclk"; + interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 294 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ierr", "terr", "abort", "resp", + "cmd", "ibi", "rx", "tx", "rcv", + "st", "sp", "tend", "nack", "al", + "tmo", "wu", "exit"; + resets = <&cpg R9A08G045_I3C_PRESETN>, + <&cpg R9A08G045_I3C_TRESETN>; + reset-names = "presetn", "tresetn"; + power-domains = <&cpg>; + #address-cells = <3>; + #size-cells = <0>; + status = "disabled"; + }; + vbattb: clock-controller@1005c000 { compatible = "renesas,r9a08g045-vbattb"; reg = <0 0x1005c000 0 0x1000>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index e4fac7e0d764..47d843c79021 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -301,6 +301,176 @@ status = "disabled"; }; + dmac0: dma-controller@11400000 { + compatible = "renesas,r9a09g047-dmac", + "renesas,r9a09g057-dmac"; + reg = <0 0x11400000 0 0x10000>; + interrupts = <GIC_SPI 499 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 91 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 94 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 95 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 101 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 104 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 0x0>; + power-domains = <&cpg>; + resets = <&cpg 0x31>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 4>; + }; + + dmac1: dma-controller@14830000 { + compatible = "renesas,r9a09g047-dmac", + "renesas,r9a09g057-dmac"; + reg = <0 0x14830000 0 0x10000>; + interrupts = <GIC_SPI 495 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 0x1>; + power-domains = <&cpg>; + resets = <&cpg 0x32>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 0>; + }; + + dmac2: dma-controller@14840000 { + compatible = "renesas,r9a09g047-dmac", + "renesas,r9a09g057-dmac"; + reg = <0 0x14840000 0 0x10000>; + interrupts = <GIC_SPI 496 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 0x2>; + power-domains = <&cpg>; + resets = <&cpg 0x33>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 1>; + }; + + dmac3: dma-controller@12000000 { + compatible = "renesas,r9a09g047-dmac", + "renesas,r9a09g057-dmac"; + reg = <0 0x12000000 0 0x10000>; + interrupts = <GIC_SPI 497 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 0x3>; + power-domains = <&cpg>; + resets = <&cpg 0x34>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 2>; + }; + + dmac4: dma-controller@12010000 { + compatible = "renesas,r9a09g047-dmac", + "renesas,r9a09g057-dmac"; + reg = <0 0x12010000 0 0x10000>; + interrupts = <GIC_SPI 498 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 0x4>; + power-domains = <&cpg>; + resets = <&cpg 0x35>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 3>; + }; + scif0: serial@11c01400 { compatible = "renesas,scif-r9a09g047", "renesas,scif-r9a09g057"; reg = <0 0x11c01400 0 0x400>; @@ -322,6 +492,41 @@ status = "disabled"; }; + i3c: i3c@12400000 { + compatible = "renesas,r9a09g047-i3c"; + reg = <0 0x12400000 0 0x10000>; + clocks = <&cpg CPG_MOD 0x91>, + <&cpg CPG_MOD 0x92>, + <&cpg CPG_MOD 0x90>; + clock-names = "pclk", "tclk", "pclkrw"; + interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 677 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 678 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 679 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 680 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 681 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 682 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ierr", "terr", "abort", "resp", + "cmd", "ibi", "rx", "tx", "rcv", + "st", "sp", "tend", "nack", "al", + "tmo", "wu"; + resets = <&cpg 0x96>, <&cpg 0x97>; + reset-names = "presetn", "tresetn"; + power-domains = <&cpg>; + #address-cells = <3>; + #size-cells = <0>; + status = "disabled"; + }; + canfd: can@12440000 { compatible = "renesas,r9a09g047-canfd"; reg = <0 0x12440000 0 0x40000>; @@ -722,9 +927,8 @@ snps,perfect-filter-entries = <128>; rx-fifo-depth = <8192>; tx-fifo-depth = <8192>; - snps,fixed-burst; - snps,no-pbl-x8; - snps,force_thresh_dma_mode; + snps,mixed-burst; + snps,force_sf_dma_mode; snps,axi-config = <&stmmac_axi_setup>; snps,mtl-rx-config = <&mtl_rx_setup0>; snps,mtl-tx-config = <&mtl_tx_setup0>; @@ -823,9 +1027,8 @@ snps,perfect-filter-entries = <128>; rx-fifo-depth = <8192>; tx-fifo-depth = <8192>; - snps,fixed-burst; - snps,no-pbl-x8; - snps,force_thresh_dma_mode; + snps,mixed-burst; + snps,force_sf_dma_mode; snps,axi-config = <&stmmac_axi_setup>; snps,mtl-rx-config = <&mtl_rx_setup1>; snps,mtl-tx-config = <&mtl_tx_setup1>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts index 1e67f0a2a945..08e814c03fa8 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -90,10 +90,10 @@ }; &keys { - key-sleep { - pinctrl-0 = <&nmi_pins>; - pinctrl-names = "default"; + pinctrl-0 = <&nmi_pins>; + pinctrl-names = "default"; + key-sleep { interrupts-extended = <&icu 0 IRQ_TYPE_EDGE_FALLING>; linux,code = <KEY_SLEEP>; label = "SLEEP"; @@ -132,6 +132,7 @@ nmi_pins: nmi { pinmux = <RZG3E_PORT_PINMUX(S, 0, 0)>; /* NMI */ + input-schmitt-enable; }; scif_pins: scif { diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index 10d3b9727ea5..887110878906 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -369,6 +369,39 @@ status = "disabled"; }; + i3c: i3c@12400000 { + compatible = "renesas,r9a09g056-i3c", "renesas,r9a09g047-i3c"; + reg = <0 0x12400000 0 0x10000>; + clocks = <&cpg CPG_MOD 0x91>, <&cpg CPG_MOD 0x92>, <&cpg CPG_MOD 0x90>; + clock-names = "pclk", "tclk", "pclkrw"; + interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 677 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 678 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 679 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 680 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 681 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 682 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ierr", "terr", "abort", "resp", + "cmd", "ibi", "rx", "tx", "rcv", + "st", "sp", "tend", "nack", + "al", "tmo", "wu"; + resets = <&cpg 0x96>, <&cpg 0x97>; + reset-names = "presetn", "tresetn"; + power-domains = <&cpg>; + #address-cells = <3>; + #size-cells = <0>; + status = "disabled"; + }; + i2c0: i2c@14400400 { compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; reg = <0 0x14400400 0 0x400>; @@ -735,10 +768,10 @@ "rx-queue-0", "rx-queue-1", "rx-queue-2", "rx-queue-3", "tx-queue-0", "tx-queue-1", "tx-queue-2", "tx-queue-3"; - clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, - <&cpg CPG_CORE R9A09G056_GBETH_0_CLK_PTP_REF_I>, - <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, - <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; + clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, + <&cpg CPG_CORE R9A09G056_GBETH_0_CLK_PTP_REF_I>, + <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, + <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "rx", "tx-180", "rx-180"; resets = <&cpg 0xb0>; @@ -836,10 +869,10 @@ "rx-queue-0", "rx-queue-1", "rx-queue-2", "rx-queue-3", "tx-queue-0", "tx-queue-1", "tx-queue-2", "tx-queue-3"; - clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, - <&cpg CPG_CORE R9A09G056_GBETH_1_CLK_PTP_REF_I>, - <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, - <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; + clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, + <&cpg CPG_CORE R9A09G056_GBETH_1_CLK_PTP_REF_I>, + <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, + <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "rx", "tx-180", "rx-180"; resets = <&cpg 0xb1>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts index 03aeea781186..066e66b5d51a 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts @@ -334,7 +334,7 @@ usb20_pins: usb20 { ovc { - pinmux = <RZV2N_PORT_PINMUX(9, 6, 14)>; /* OVC */ + pinmux = <RZV2N_PORT_PINMUX(9, 6, 14)>; /* OVC */ }; vbus { diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 044f2a22f161..630f7a98df38 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -607,6 +607,102 @@ status = "disabled"; }; + i3c: i3c@12400000 { + compatible = "renesas,r9a09g057-i3c", "renesas,r9a09g047-i3c"; + reg = <0 0x12400000 0 0x10000>; + clocks = <&cpg CPG_MOD 0x91>, <&cpg CPG_MOD 0x92>, <&cpg CPG_MOD 0x90>; + clock-names = "pclk", "tclk", "pclkrw"; + interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 677 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 678 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 679 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 680 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 681 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 682 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ierr", "terr", "abort", "resp", + "cmd", "ibi", "rx", "tx", "rcv", + "st", "sp", "tend", "nack", + "al", "tmo", "wu"; + resets = <&cpg 0x96>, <&cpg 0x97>; + reset-names = "presetn", "tresetn"; + power-domains = <&cpg>; + #address-cells = <3>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi0: spi@12800000 { + compatible = "renesas,r9a09g057-rspi"; + reg = <0x0 0x12800000 0x0 0x400>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 500 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 501 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_MOD 0x54>, + <&cpg CPG_MOD 0x55>, + <&cpg CPG_MOD 0x56>; + clock-names = "pclk", "pclk_sfr", "tclk"; + resets = <&cpg 0x7b>, <&cpg 0x7c>; + reset-names = "presetn", "tresetn"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi1: spi@12800400 { + compatible = "renesas,r9a09g057-rspi"; + reg = <0x0 0x12800400 0x0 0x400>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 502 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 503 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_MOD 0x57>, + <&cpg CPG_MOD 0x58>, + <&cpg CPG_MOD 0x59>; + clock-names = "pclk", "pclk_sfr", "tclk"; + resets = <&cpg 0x7d>, <&cpg 0x7e>; + reset-names = "presetn", "tresetn"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi2: spi@12800800 { + compatible = "renesas,r9a09g057-rspi"; + reg = <0x0 0x12800800 0x0 0x400>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 504 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 505 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_MOD 0x5a>, + <&cpg CPG_MOD 0x5b>, + <&cpg CPG_MOD 0x5c>; + clock-names = "pclk", "pclk_sfr", "tclk"; + resets = <&cpg 0x7f>, <&cpg 0x80>; + reset-names = "presetn", "tresetn"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c0: i2c@14400400 { compatible = "renesas,riic-r9a09g057"; reg = <0 0x14400400 0 0x400>; @@ -1020,10 +1116,10 @@ "rx-queue-0", "rx-queue-1", "rx-queue-2", "rx-queue-3", "tx-queue-0", "tx-queue-1", "tx-queue-2", "tx-queue-3"; - clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, - <&cpg CPG_CORE R9A09G057_GBETH_0_CLK_PTP_REF_I>, - <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, - <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; + clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, + <&cpg CPG_CORE R9A09G057_GBETH_0_CLK_PTP_REF_I>, + <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, + <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "rx", "tx-180", "rx-180"; resets = <&cpg 0xb0>; @@ -1121,10 +1217,10 @@ "rx-queue-0", "rx-queue-1", "rx-queue-2", "rx-queue-3", "tx-queue-0", "tx-queue-1", "tx-queue-2", "tx-queue-3"; - clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, - <&cpg CPG_CORE R9A09G057_GBETH_1_CLK_PTP_REF_I>, - <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, - <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; + clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, + <&cpg CPG_CORE R9A09G057_GBETH_1_CLK_PTP_REF_I>, + <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, + <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "rx", "tx-180", "rx-180"; resets = <&cpg 0xb1>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts index 5c3f4e471e3d..5c06bce3d5b4 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts @@ -353,7 +353,7 @@ usb20_pins: usb20 { ovc { - pinmux = <RZV2H_PORT_PINMUX(9, 6, 14)>; /* OVC */ + pinmux = <RZV2H_PORT_PINMUX(9, 6, 14)>; /* OVC */ }; vbus { diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts b/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts index d2586d278769..adf3ab8aef2b 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* - * Device Tree Source for Yuridenki-Shokai the Kakip board + * Device Tree Source for the Yuridenki-Shokai Kakip board * * Copyright (C) 2024 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> */ @@ -84,7 +84,7 @@ &pinctrl { scif_pins: scif { - pins = "SCIF_RXD", "SCIF_TXD"; + pins = "SCIF_RXD", "SCIF_TXD"; }; sd0-pwr-en-hog { diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi new file mode 100644 index 000000000000..7f1aca218c9f --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -0,0 +1,399 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/T2H SoC + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "renesas,r9a09g077"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + cpu1: cpu@100 { + compatible = "arm,cortex-a55"; + reg = <0x100>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + cpu2: cpu@200 { + compatible = "arm,cortex-a55"; + reg = <0x200>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + cpu3: cpu@300 { + compatible = "arm,cortex-a55"; + reg = <0x300>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + L3_CA55: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-size = <0x100000>; + cache-level = <3>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + sci0: serial@80005000 { + compatible = "renesas,r9a09g077-rsci"; + reg = <0 0x80005000 0 0x400>; + interrupts = <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 591 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 592 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 8>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + + sci1: serial@80005400 { + compatible = "renesas,r9a09g077-rsci"; + reg = <0 0x80005400 0 0x400>; + interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 595 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 596 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 9>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + + sci2: serial@80005800 { + compatible = "renesas,r9a09g077-rsci"; + reg = <0 0x80005800 0 0x400>; + interrupts = <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 599 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 600 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 10>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + + sci3: serial@80005c00 { + compatible = "renesas,r9a09g077-rsci"; + reg = <0 0x80005c00 0 0x400>; + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 11>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + + sci4: serial@80006000 { + compatible = "renesas,r9a09g077-rsci"; + reg = <0 0x80006000 0 0x400>; + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 607 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 608 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 12>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + + sci5: serial@81005000 { + compatible = "renesas,r9a09g077-rsci"; + reg = <0 0x81005000 0 0x400>; + interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 611 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 612 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 600>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt0: watchdog@80082000 { + compatible = "renesas,r9a09g077-wdt"; + reg = <0 0x80082000 0 0x400>, + <0 0x81295100 0 0x04>; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; + clock-names = "pclk"; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt1: watchdog@80082400 { + compatible = "renesas,r9a09g077-wdt"; + reg = <0 0x80082400 0 0x400>, + <0 0x81295104 0 0x04>; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; + clock-names = "pclk"; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt2: watchdog@80082800 { + compatible = "renesas,r9a09g077-wdt"; + reg = <0 0x80082800 0 0x400>, + <0 0x81295108 0 0x04>; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; + clock-names = "pclk"; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt3: watchdog@80082c00 { + compatible = "renesas,r9a09g077-wdt"; + reg = <0 0x80082c00 0 0x400>, + <0 0x8129510c 0 0x04>; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; + clock-names = "pclk"; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt4: watchdog@80083000 { + compatible = "renesas,r9a09g077-wdt"; + reg = <0 0x80083000 0 0x400>, + <0 0x81295110 0 0x04>; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; + clock-names = "pclk"; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt5: watchdog@80083400 { + compatible = "renesas,r9a09g077-wdt"; + reg = <0 0x80083400 0 0x400>, + <0 0x81295114 0 0x04>; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; + clock-names = "pclk"; + power-domains = <&cpg>; + status = "disabled"; + }; + + i2c0: i2c@80088000 { + compatible = "renesas,riic-r9a09g077"; + reg = <0 0x80088000 0 0x400>; + interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 615 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 616 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eei", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 100>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@80088400 { + compatible = "renesas,riic-r9a09g077"; + reg = <0 0x80088400 0 0x400>; + interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 619 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 620 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eei", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 101>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@81008000 { + compatible = "renesas,riic-r9a09g077"; + reg = <0 0x81008000 0 0x400>; + interrupts = <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 623 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 624 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eei", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 601>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + cpg: clock-controller@80280000 { + compatible = "renesas,r9a09g077-cpg-mssr"; + reg = <0 0x80280000 0 0x1000>, + <0 0x81280000 0 0x9000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + pinctrl: pinctrl@802c0000 { + compatible = "renesas,r9a09g077-pinctrl"; + reg = <0 0x802c0000 0 0x10000>, + <0 0x812c0000 0 0x10000>, + <0 0x802b0000 0 0x10000>; + reg-names = "nsr", "srs", "srn"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 288>; + power-domains = <&cpg>; + }; + + gic: interrupt-controller@83000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x83000000 0 0x40000>, + <0x0 0x83040000 0 0x160000>; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; + }; + + ohci: usb@92040000 { + compatible = "generic-ohci"; + reg = <0 0x92040000 0 0x100>; + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 408>; + phys = <&usb2_phy 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ehci: usb@92040100 { + compatible = "generic-ehci"; + reg = <0 0x92040100 0 0x100>; + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 408>; + phys = <&usb2_phy 2>; + phy-names = "usb"; + companion = <&ohci>; + power-domains = <&cpg>; + status = "disabled"; + }; + + usb2_phy: usb-phy@92040200 { + compatible = "renesas,usb2-phy-r9a09g077"; + reg = <0 0x92040200 0 0x700>; + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 408>, + <&cpg CPG_CORE R9A09G077_USB_CLK>; + #phy-cells = <1>; + power-domains = <&cpg>; + status = "disabled"; + }; + + hsusb: usb@92041000 { + compatible = "renesas,usbhs-r9a09g077"; + reg = <0 0x92041000 0 0x1000>; + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 408>; + phys = <&usb2_phy 3>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + sdhi0: mmc@92080000 { + compatible = "renesas,sdhi-r9a09g077", + "renesas,sdhi-r9a09g057"; + reg = <0x0 0x92080000 0 0x10000>; + interrupts = <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1212>, + <&cpg CPG_CORE R9A09G077_SDHI_CLKHS>; + clock-names = "aclk", "clkh"; + power-domains = <&cpg>; + status = "disabled"; + + sdhi0_vqmmc: vqmmc-regulator { + regulator-name = "SDHI0-VQMMC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + status = "disabled"; + }; + }; + + sdhi1: mmc@92090000 { + compatible = "renesas,sdhi-r9a09g077", + "renesas,sdhi-r9a09g057"; + reg = <0x0 0x92090000 0 0x10000>; + interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1213>, + <&cpg CPG_CORE R9A09G077_SDHI_CLKHS>; + clock-names = "aclk", "clkh"; + power-domains = <&cpg>; + status = "disabled"; + + sdhi1_vqmmc: vqmmc-regulator { + regulator-name = "SDHI1-VQMMC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + status = "disabled"; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts new file mode 100644 index 000000000000..2bf867273ad0 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/T2H EVK board + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +/dts-v1/; + +#include "r9a09g077m44.dtsi" + +/* + * SD0 can be connected to either eMMC (IC49) or SD card slot CN31 + * Lets by default enable the eMMC, note we need the below SW settings + * for eMMC. + * SW2[1] = ON; SW2[2] = ON + * + * To enable SD card and disable eMMC on SDHI0 disable the below macro + * and set the below switch setting: + * SW2[1] = OFF; SW2[2] = ON + */ +#define SD0_EMMC 1 +#define SD0_SD (!SD0_EMMC) + +/* + * P17_4 = SD1_CD; SW2[3] = ON + * P08_5 = SD1_PWEN; SW2[3] = ON + * P08_6 = SD1_IOVS; SW2[3] = ON; SW5[3] = OFF; SW5[4] = ON + */ +#define SD1_MICRO_SD 1 + +/* + * USB Pin Configuration: + * + * This board is equipped with three USB connectors: Type-A (CN80), Mini-B + * (CN79), and Micro-AB (CN33). The RZ/T2H SoC has a single USB channel, so + * either the USB host interface or the USB function interface can be used, + * but not both simultaneously when using the CN79 and CN80 connectors. + * + * By default, the Type-A (CN80) and Mini-B (CN79) connectors are enabled. + * Configure the switches as follows: + * - P00_0 - P00_2 (control signals for USB power supply): SW1[5] = ON + * - USB_VBUSIN (used for USB function): SW7[7] = OFF; SW7[8] = ON + * - USB_VBUSEN (used for USB_HF_VBUSEN): SW7[9] = OFF; SW7[10] = ON + * + * To enable the Micro-AB (CN33) USB OTG connector, set the following macro + * to 1 and configure the switches as follows: + * - P00_0 - P00_2 (control signals for USB power supply): SW1[5] = ON + * - USB_VBUSIN (used for USB OTG): SW7[7] = ON; SW7[8] = OFF + * - USB_VBUSEN (used for USB_OTG_VBUSEN): SW7[9] = ON; SW7[10] = OFF + */ +#define USB_OTG 0 + +#include "rzt2h-n2h-evk-common.dtsi" + +/ { + model = "Renesas RZ/T2H EVK Board based on r9a09g077m44"; + compatible = "renesas,rzt2h-evk", "renesas,r9a09g077m44", "renesas,r9a09g077"; + + leds { + compatible = "gpio-leds"; + + led-0 { + /* SW8-9: ON, SW8-10: OFF */ + gpios = <&pinctrl RZT2H_GPIO(23, 1) GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_DEBUG; + function-enumerator = <0>; + }; + + led-1 { + /* SW5-1: OFF, SW5-2: ON */ + gpios = <&pinctrl RZT2H_GPIO(32, 2) GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + }; + + led-2 { + gpios = <&pinctrl RZT2H_GPIO(6, 7) GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_YELLOW>; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + }; + +#if (!SD1_MICRO_SD) + led-3 { + /* SW2-3: OFF */ + gpios = <&pinctrl RZT2H_GPIO(8, 5) GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_DEBUG; + function-enumerator = <3>; + }; +#endif + + led-4 { + /* SW8-3: ON, SW8-4: OFF */ + gpios = <&pinctrl RZT2H_GPIO(18, 0) GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_DEBUG; + function-enumerator = <4>; + }; + + led-5 { + /* SW8-1: ON, SW8-2: OFF */ + gpios = <&pinctrl RZT2H_GPIO(18, 1) GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_DEBUG; + function-enumerator = <5>; + }; + + led-6 { + /* SW5-9: OFF, SW5-10: ON */ + gpios = <&pinctrl RZT2H_GPIO(22, 7) GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_DEBUG; + function-enumerator = <6>; + }; + + led-7 { + /* SW5-7: OFF, SW5-8: ON */ + gpios = <&pinctrl RZT2H_GPIO(23, 0) GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_DEBUG; + function-enumerator = <7>; + }; + + led-8 { + /* SW7-5: OFF, SW7-6: ON */ + gpios = <&pinctrl RZT2H_GPIO(23, 5) GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_DEBUG; + function-enumerator = <8>; + }; + }; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; + +&pinctrl { + /* + * I2C0 Pin Configuration: + * ------------------------ + * Signal | Pin | SW6 + * -------|---------|-------------- + * SCL | P23_3 | 7: ON, 8: OFF + * SDA | P23_4 | 9: ON, 10: OFF + */ + i2c0_pins: i2c0-pins { + pinmux = <RZT2H_PORT_PINMUX(23, 3, 0x17)>, + <RZT2H_PORT_PINMUX(23, 4, 0x17)>; + }; + + i2c1_pins: i2c1-pins { + pinmux = <RZT2H_PORT_PINMUX(5, 0, 0x17)>, /* SDA */ + <RZT2H_PORT_PINMUX(4, 7, 0x17)>; /* SCL */ + }; + +#if USB_OTG + usb-exicen-hog { + gpio-hog; + gpios = <RZT2H_GPIO(0, 2) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "usb_exicen_a"; + }; +#endif + + usb_pins: usb-pins { + pinmux = <RZT2H_PORT_PINMUX(0, 0, 0x13)>, /* VBUSEN */ + <RZT2H_PORT_PINMUX(0, 1, 0x13)>; /* OVRCUR */ + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi new file mode 100644 index 000000000000..6f4a11b39d12 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/T2H 4-core SoC + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a09g077.dtsi" + +/ { + compatible = "renesas,r9a09g077m44", "renesas,r9a09g077"; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi new file mode 100644 index 000000000000..f06c19c73adb --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -0,0 +1,399 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/N2H SoC + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#include <dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "renesas,r9a09g087"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + cpu1: cpu@100 { + compatible = "arm,cortex-a55"; + reg = <0x100>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + cpu2: cpu@200 { + compatible = "arm,cortex-a55"; + reg = <0x200>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + cpu3: cpu@300 { + compatible = "arm,cortex-a55"; + reg = <0x300>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + L3_CA55: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-size = <0x100000>; + cache-level = <3>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + sci0: serial@80005000 { + compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; + reg = <0 0x80005000 0 0x400>; + interrupts = <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 591 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 592 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 8>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + + sci1: serial@80005400 { + compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; + reg = <0 0x80005400 0 0x400>; + interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 595 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 596 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 9>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + + sci2: serial@80005800 { + compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; + reg = <0 0x80005800 0 0x400>; + interrupts = <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 599 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 600 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 10>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + + sci3: serial@80005c00 { + compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; + reg = <0 0x80005c00 0 0x400>; + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 11>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + + sci4: serial@80006000 { + compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; + reg = <0 0x80006000 0 0x400>; + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 607 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 608 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 12>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + + sci5: serial@81005000 { + compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; + reg = <0 0x81005000 0 0x400>; + interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 611 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 612 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 600>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt0: watchdog@80082000 { + compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; + reg = <0 0x80082000 0 0x400>, + <0 0x81295100 0 0x04>; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; + clock-names = "pclk"; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt1: watchdog@80082400 { + compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; + reg = <0 0x80082400 0 0x400>, + <0 0x81295104 0 0x04>; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; + clock-names = "pclk"; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt2: watchdog@80082800 { + compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; + reg = <0 0x80082800 0 0x400>, + <0 0x81295108 0 0x04>; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; + clock-names = "pclk"; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt3: watchdog@80082c00 { + compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; + reg = <0 0x80082c00 0 0x400>, + <0 0x8129510c 0 0x04>; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; + clock-names = "pclk"; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt4: watchdog@80083000 { + compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; + reg = <0 0x80083000 0 0x400>, + <0 0x81295110 0 0x04>; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; + clock-names = "pclk"; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt5: watchdog@80083400 { + compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; + reg = <0 0x80083400 0 0x400>, + <0 0x81295114 0 0x04>; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; + clock-names = "pclk"; + power-domains = <&cpg>; + status = "disabled"; + }; + + i2c0: i2c@80088000 { + compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077"; + reg = <0 0x80088000 0 0x400>; + interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 615 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 616 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eei", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 100>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@80088400 { + compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077"; + reg = <0 0x80088400 0 0x400>; + interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 619 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 620 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eei", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 101>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@81008000 { + compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077"; + reg = <0 0x81008000 0 0x400>; + interrupts = <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 623 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 624 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eei", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 601>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + cpg: clock-controller@80280000 { + compatible = "renesas,r9a09g087-cpg-mssr"; + reg = <0 0x80280000 0 0x1000>, + <0 0x81280000 0 0x9000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + pinctrl: pinctrl@802c0000 { + compatible = "renesas,r9a09g087-pinctrl"; + reg = <0 0x802c0000 0 0x10000>, + <0 0x812c0000 0 0x10000>, + <0 0x802b0000 0 0x10000>; + reg-names = "nsr", "srs", "srn"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 280>; + power-domains = <&cpg>; + }; + + gic: interrupt-controller@83000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x83000000 0 0x40000>, + <0x0 0x83040000 0 0x160000>; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; + }; + + ohci: usb@92040000 { + compatible = "generic-ohci"; + reg = <0 0x92040000 0 0x100>; + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 408>; + phys = <&usb2_phy 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ehci: usb@92040100 { + compatible = "generic-ehci"; + reg = <0 0x92040100 0 0x100>; + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 408>; + phys = <&usb2_phy 2>; + phy-names = "usb"; + companion = <&ohci>; + power-domains = <&cpg>; + status = "disabled"; + }; + + usb2_phy: usb-phy@92040200 { + compatible = "renesas,usb2-phy-r9a09g087", "renesas,usb2-phy-r9a09g077"; + reg = <0 0x92040200 0 0x700>; + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 408>, + <&cpg CPG_CORE R9A09G087_USB_CLK>; + #phy-cells = <1>; + power-domains = <&cpg>; + status = "disabled"; + }; + + hsusb: usb@92041000 { + compatible = "renesas,usbhs-r9a09g087", "renesas,usbhs-r9a09g077"; + reg = <0 0x92041000 0 0x1000>; + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 408>; + phys = <&usb2_phy 3>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + sdhi0: mmc@92080000 { + compatible = "renesas,sdhi-r9a09g087", + "renesas,sdhi-r9a09g057"; + reg = <0x0 0x92080000 0 0x10000>; + interrupts = <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1212>, + <&cpg CPG_CORE R9A09G087_SDHI_CLKHS>; + clock-names = "aclk", "clkh"; + power-domains = <&cpg>; + status = "disabled"; + + sdhi0_vqmmc: vqmmc-regulator { + regulator-name = "SDHI0-VQMMC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + status = "disabled"; + }; + }; + + sdhi1: mmc@92090000 { + compatible = "renesas,sdhi-r9a09g087", + "renesas,sdhi-r9a09g057"; + reg = <0x0 0x92090000 0 0x10000>; + interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1213>, + <&cpg CPG_CORE R9A09G087_SDHI_CLKHS>; + clock-names = "aclk", "clkh"; + power-domains = <&cpg>; + status = "disabled"; + + sdhi1_vqmmc: vqmmc-regulator { + regulator-name = "SDHI1-VQMMC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + status = "disabled"; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts new file mode 100644 index 000000000000..084b3a0c8052 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/N2H EVK board + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +/dts-v1/; + +#include "r9a09g087m44.dtsi" + +/* + * SD0 can be connected to either eMMC (U33) or SD card slot CN21 + * Lets by default enable the eMMC, note we need the below SW settings + * for eMMC. + * DSW5[1] = ON; DSW5[2] = ON + * DSW17[5] = OFF; DSW17[6] = ON + * + * To enable SD card and disable eMMC on SDHI0 disable the below macro + * and set the below switch setting: + * DSW5[1] = OFF; DSW5[2] = ON + * P22_6 = SD0_WP; DSW15[1] = OFF; DSW15[2] = ON + * P22_5 = SD0_CD; DSW15[3] = OFF; DSW15[4] = ON + * P02_6 = SD0_IOVS; DSW17[5] = OFF; DSW17[6] = ON + * P02_5 = SD0_PWEN; DSW17[7] = OFF; DSW17[8] = ON + */ +#define SD0_EMMC 1 +#define SD0_SD (!SD0_EMMC) + +/* + * P17_4 = SD1_CD; DSW5[3] = ON; DSW19[1] = OFF; DSW19[2] = ON + * P08_6 = SD1_IOVS; DSW5[3] = ON + */ +#define SD1_MICRO_SD 1 + +/* + * USB Pin Configuration: + * + * This board is equipped with three USB connectors: Type-A (CN7), Mini-B + * (CN8), and Micro-AB (CN9). The RZ/N2H SoC has a single USB channel, so + * either the USB host interface or the USB function interface can be used, + * but not both simultaneously when using the CN7 and CN8 connectors. + * + * By default, the Type-A (CN7) and Mini-B (CN8) connectors are enabled. + * Configure the switches as follows: + * - P02_2 - P02_3 (control signals for USB power supply): DSW2[6] = OFF; + * - P02_2 (used for VBUSEN): DSW14[5] = OFF; DSW14[6] = ON + * - P02_3 (used for USB_OVRCUR): DSW14[1] = OFF; DSW14[2] = ON + * - USB_VBUSIN (used for VBUS of CN8): DSW16[1] = OFF; DSW16[2] = ON + * - USB_VBUSEN (used for USB_HF_VBUSEN): DSW16[3] = OFF; DSW16[4] = ON + * + * To enable the Micro-AB (CN9) USB OTG connector, set the following macro + * to 1 and configure the switches as follows: + * - P02_2 - P02_3 (control signals for USB power supply): DSW2[6] = OFF; + * - P02_2 (used for VBUSEN): DSW14[5] = OFF; DSW14[6] = ON + * - P02_3 (used for USB_OVRCUR): DSW14[1] = OFF; DSW14[2] = ON + * - USB_VBUSIN (used for VBUS for OTG): DSW16[1] = ON; DSW16[2] = OFF + * - USB_VBUSEN (used for USB_OTG_VBUSEN): DSW16[3] = ON; DSW16[4] = OFF + * - USB_EXICEN (used for USB OTG EXICEN): DSW14[3] = OFF; DSW14[4] = ON + */ +#define USB_OTG 0 + +#include "rzt2h-n2h-evk-common.dtsi" + +/* + * I2C0 and LED8/9 share the same pins use the below + * macro to choose (and set approopriate DIP switches). + */ +#define I2C0 1 +#define LED8 (!I2C0) +#define LED9 (!I2C0) + +/ { + model = "Renesas RZ/N2H EVK Board based on r9a09g087m44"; + compatible = "renesas,rzn2h-evk", "renesas,r9a09g087m44", "renesas,r9a09g087"; + + leds { + compatible = "gpio-leds"; + + led-3 { + /* DSW18-7: ON, DSW18-8: OFF */ + gpios = <&pinctrl RZT2H_GPIO(31, 6) GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_DEBUG; + function-enumerator = <4>; + }; + + led-4 { + /* DSW18-9: ON, DSW18-10: OFF */ + gpios = <&pinctrl RZT2H_GPIO(18, 1) GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_DEBUG; + function-enumerator = <5>; + }; + + led-5 { + /* DSW18-1: ON, DSW18-2: OFF */ + gpios = <&pinctrl RZT2H_GPIO(22, 7) GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_DEBUG; + function-enumerator = <6>; + }; + + led-6 { + /* DSW18-3: ON, DSW18-4: OFF */ + gpios = <&pinctrl RZT2H_GPIO(23, 0) GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_DEBUG; + function-enumerator = <7>; + }; + + led-7 { + /* + * DSW18-5: ON, DSW18-6: OFF + * DSW19-3: OFF, DSW19-4: ON + */ + gpios = <&pinctrl RZT2H_GPIO(14, 3) GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_DEBUG; + function-enumerator = <8>; + }; + +#if LED8 + led-8 { + /* + * USER_LED0 + * DSW15-8: OFF, DSW15-9: OFF, DSW15-10: ON + */ + gpios = <&pinctrl RZT2H_GPIO(14, 6) GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_DEBUG; + function-enumerator = <0>; + }; +#endif + +#if LED9 + led-9 { + /* + * USER_LED1 + * DSW15-5: OFF, DSW15-6: ON + */ + gpios = <&pinctrl RZT2H_GPIO(14, 7) GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + }; +#endif + + led-10 { + /* + * USER_LED2 + * DSW17-3: OFF, DSW17-4: ON + */ + gpios = <&pinctrl RZT2H_GPIO(2, 7) GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_YELLOW>; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + }; + + led-11 { + /* + * USER_LED3 + * DSW17-1: OFF, DSW17-2: ON + */ + gpios = <&pinctrl RZT2H_GPIO(3, 0) GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_DEBUG; + function-enumerator = <3>; + }; + }; +}; + +#if I2C0 +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; +#endif + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; + +&pinctrl { + /* + * I2C0 Pin Configuration: + * ------------------------ + * Signal | Pin | DSW15 + * -------|---------|-------------- + * SCL | P14_6 | 8: OFF, 9: ON, 10: OFF + * SDA | P14_7 | 5: ON, 6: OFF + */ + i2c0_pins: i2c0-pins { + pinmux = <RZT2H_PORT_PINMUX(14, 6, 0x17)>, + <RZT2H_PORT_PINMUX(14, 7, 0x17)>; + }; + + /* + * I2C1 Pin Configuration: + * ------------------------ + * Signal | Pin | DSW7 + * -------|---------|-------------- + * SCL | P03_3 | 1: ON, 2: OFF + * SDA | P03_4 | 3: ON, 4: OFF + */ + i2c1_pins: i2c1-pins { + pinmux = <RZT2H_PORT_PINMUX(3, 3, 0x17)>, + <RZT2H_PORT_PINMUX(3, 4, 0x17)>; + }; + +#if USB_OTG + usb-exicen-hog { + gpio-hog; + gpios = <RZT2H_GPIO(2, 4) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "usb_exicen_a"; + }; +#endif + + usb_pins: usb-pins { + pinmux = <RZT2H_PORT_PINMUX(2, 2, 0x13)>, /* VBUSEN */ + <RZT2H_PORT_PINMUX(2, 3, 0x13)>; /* OVRCUR */ + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087m44.dtsi new file mode 100644 index 000000000000..ef0343b53309 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/N2H 4-core SoC + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a09g087.dtsi" + +/ { + compatible = "renesas,r9a09g087m44", "renesas,r9a09g087"; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index 345b779e4f60..f3d7eff0d2f2 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -48,7 +48,10 @@ #if (SW_SCIF_CAN || SW_RSPI_CAN) &canfd { pinctrl-0 = <&can1_pins>; - /delete-node/ channel@0; + + channel0 { + status = "disabled"; + }; }; #else &canfd { diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi new file mode 100644 index 000000000000..5c91002c99c4 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Common Device Tree Source for the RZ/T2H and RZ/N2H EVK boards. + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h> + +/ { + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhi0; + mmc1 = &sdhi1; + serial0 = &sci0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + +#if SD0_SD + vqmmc_sdhi0: regulator-vqmmc-sdhi0 { + compatible = "regulator-gpio"; + regulator-name = "SDHI0 VqmmC"; + gpios = <&pinctrl RZT2H_GPIO(2, 6) GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios-states = <0>; + states = <3300000 0>, <1800000 1>; + }; +#endif + +#if SD1_MICRO_SD + vccq_sdhi1: regulator-vccq-sdhi1 { + compatible = "regulator-gpio"; + regulator-name = "SDHI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&pinctrl RZT2H_GPIO(8, 6) GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <3300000 0>, <1800000 1>; + }; +#endif +}; + +&ehci { + dr_mode = "otg"; + status = "okay"; +}; + +&extal_clk { + clock-frequency = <25000000>; +}; + +&hsusb { + dr_mode = "otg"; + status = "okay"; +}; + +&i2c0 { + eeprom: eeprom@50 { + compatible = "renesas,r1ex24016", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&ohci { + dr_mode = "otg"; + status = "okay"; +}; + +&pinctrl { + /* + * SCI0 Pin Configuration: + * ------------------------ + * Signal | Pin | RZ/T2H (SW4) | RZ/N2H (DSW9) + * -----------|---------|--------------|--------------- + * SCI0_RXD | P27_4 | 5: ON, 6: OFF| 1: ON, 2: OFF + * SCI0_TXD | P27_5 | 7: ON, 8: OFF| 3: ON, 4: OFF + */ + sci0_pins: sci0-pins { + pinmux = <RZT2H_PORT_PINMUX(27, 4, 0x14)>, + <RZT2H_PORT_PINMUX(27, 5, 0x14)>; + }; + +#if SD0_EMMC + sdhi0-emmc-iovs-hog { + gpio-hog; + gpios = <RZT2H_GPIO(2, 6) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "SD0_IOVS"; + }; +#endif + + sdhi0_emmc_pins: sd0-emmc-group { + data-pins { + pinmux = <RZT2H_PORT_PINMUX(12, 2, 0x29)>, /* SD0_DATA0 */ + <RZT2H_PORT_PINMUX(12, 3, 0x29)>, /* SD0_DATA1 */ + <RZT2H_PORT_PINMUX(12, 4, 0x29)>, /* SD0_DATA2 */ + <RZT2H_PORT_PINMUX(12, 5, 0x29)>, /* SD0_DATA3 */ + <RZT2H_PORT_PINMUX(12, 6, 0x29)>, /* SD0_DATA4 */ + <RZT2H_PORT_PINMUX(12, 7, 0x29)>, /* SD0_DATA5 */ + <RZT2H_PORT_PINMUX(13, 0, 0x29)>, /* SD0_DATA6 */ + <RZT2H_PORT_PINMUX(13, 1, 0x29)>; /* SD0_DATA7 */ + }; + + ctrl-pins { + pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */ + <RZT2H_PORT_PINMUX(12, 1, 0x29)>, /* SD0_CMD */ + <RZT2H_PORT_PINMUX(13, 2, 0x29)>; /* SD0_RST# */ + }; + }; + +#if SD0_SD + sdhi0-pwen-hog { + gpio-hog; + gpios = <RZT2H_GPIO(2, 5) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "SD0_PWEN"; + }; +#endif + + sdhi0_sd_pins: sd0-sd-group { + data-pins { + pinmux = <RZT2H_PORT_PINMUX(12, 2, 0x29)>, /* SD0_DATA0 */ + <RZT2H_PORT_PINMUX(12, 3, 0x29)>, /* SD0_DATA1 */ + <RZT2H_PORT_PINMUX(12, 4, 0x29)>, /* SD0_DATA2 */ + <RZT2H_PORT_PINMUX(12, 5, 0x29)>; /* SD0_DATA3 */ + }; + + ctrl-pins { + pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */ + <RZT2H_PORT_PINMUX(12, 1, 0x29)>, /* SD0_CMD */ + <RZT2H_PORT_PINMUX(22, 5, 0x29)>, /* SD0_CD */ + <RZT2H_PORT_PINMUX(22, 6, 0x29)>; /* SD0_WP */ + }; + }; + +#if SD1_MICRO_SD + sdhi1-pwen-hog { + gpio-hog; + gpios = <RZT2H_GPIO(8, 5) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "SD1_PWEN"; + }; +#endif + + sdhi1_pins: sd1-group { + data-pins { + pinmux = <RZT2H_PORT_PINMUX(16, 7, 0x29)>, /* SD1_DATA0 */ + <RZT2H_PORT_PINMUX(17, 0, 0x29)>, /* SD1_DATA1 */ + <RZT2H_PORT_PINMUX(17, 1, 0x29)>, /* SD1_DATA2 */ + <RZT2H_PORT_PINMUX(17, 2, 0x29)>; /* SD1_DATA3 */ + }; + + ctrl-pins { + pinmux = <RZT2H_PORT_PINMUX(16, 5, 0x29)>, /* SD1_CLK */ + <RZT2H_PORT_PINMUX(16, 6, 0x29)>, /* SD1_CMD */ + <RZT2H_PORT_PINMUX(17, 4, 0x29)>; /* SD1_CD */ + }; + }; +}; + +&sci0 { + pinctrl-0 = <&sci0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +#if SD0_EMMC +&sdhi0 { + pinctrl-0 = <&sdhi0_emmc_pins>; + pinctrl-1 = <&sdhi0_emmc_pins>; + pinctrl-names = "default", "state_uhs"; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + non-removable; + mmc-hs200-1_8v; + fixed-emmc-driver-type = <1>; + status = "okay"; +}; +#endif + +#if SD0_SD +&sdhi0 { + pinctrl-0 = <&sdhi0_sd_pins>; + pinctrl-1 = <&sdhi0_sd_pins>; + pinctrl-names = "default", "state_uhs"; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vqmmc_sdhi0>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; +#endif + +#if SD1_MICRO_SD +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-1 = <&sdhi1_pins>; + pinctrl-names = "default", "state_uhs"; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vccq_sdhi1>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; +#endif + +&usb2_phy { + pinctrl-0 = <&usb_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&wdt2 { + status = "okay"; + timeout-sec = <60>; +}; diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 099520962ffb..ad684e3831bc 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -89,7 +89,11 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64-screen.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-armsom-sige1.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-nanopi-zero2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-radxa-e20c.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-rock-2a.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-rock-2f.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg-arc-d.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg-arc-s.dtb @@ -130,6 +134,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r66s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r68s.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-hinlink-h66k.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-hinlink-h68k.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat-2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-mecsbc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb @@ -175,6 +181,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-max.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-ultra.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-quartzpro64.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-roc-rt.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5-itx.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo diff --git a/arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi b/arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi index b4bd4e34747c..192791993f05 100644 --- a/arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi @@ -72,7 +72,7 @@ }; vcc_cam_avdd: regulator-vcc-cam-avdd { - compatible = "regulator-fixed"; + compatible = "regulator-fixed"; regulator-name = "vcc_cam_avdd"; gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; @@ -83,7 +83,7 @@ }; vcc_cam_dovdd: regulator-vcc-cam-dovdd { - compatible = "regulator-fixed"; + compatible = "regulator-fixed"; regulator-name = "vcc_cam_dovdd"; gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; @@ -94,7 +94,7 @@ }; vcc_cam_dvdd: regulator-vcc-cam-dvdd { - compatible = "regulator-fixed"; + compatible = "regulator-fixed"; regulator-name = "vcc_cam_dvdd"; gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; enable-active-high; @@ -106,7 +106,7 @@ }; vcc_lens_afvdd: regulator-vcc-lens-afvdd { - compatible = "regulator-fixed"; + compatible = "regulator-fixed"; regulator-name = "vcc_lens_afvdd"; gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou-video-demo.dtso b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou-video-demo.dtso index ea5ce919984f..760d5139f95d 100644 --- a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou-video-demo.dtso +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou-video-demo.dtso @@ -26,7 +26,7 @@ }; cam_afvdd_2v8: regulator-cam-afvdd-2v8 { - compatible = "regulator-fixed"; + compatible = "regulator-fixed"; gpio = <&pca9670 2 GPIO_ACTIVE_LOW>; regulator-max-microvolt = <2800000>; regulator-min-microvolt = <2800000>; @@ -35,7 +35,7 @@ }; cam_avdd_2v8: regulator-cam-avdd-2v8 { - compatible = "regulator-fixed"; + compatible = "regulator-fixed"; gpio = <&pca9670 4 GPIO_ACTIVE_LOW>; regulator-max-microvolt = <2800000>; regulator-min-microvolt = <2800000>; @@ -44,7 +44,7 @@ }; cam_dovdd_1v8: regulator-cam-dovdd-1v8 { - compatible = "regulator-fixed"; + compatible = "regulator-fixed"; gpio = <&pca9670 3 GPIO_ACTIVE_LOW>; regulator-max-microvolt = <1800000>; regulator-min-microvolt = <1800000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3308-sakurapi-rk3308b.dts b/arch/arm64/boot/dts/rockchip/rk3308-sakurapi-rk3308b.dts index f9f633aebb64..e5e6b800c2d1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308-sakurapi-rk3308b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3308-sakurapi-rk3308b.dts @@ -260,6 +260,6 @@ status = "okay"; }; -&usb_host_ohci{ +&usb_host_ohci { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts index f7c4578865c5..30bdb38f0727 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts @@ -58,6 +58,24 @@ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; linux,rc-map-name = "rc-beelink-gs1"; }; + + spdif_dit: spdif-dit { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_sound: spdif-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_dit>; + }; + }; }; &analog_sound { @@ -325,6 +343,11 @@ status = "okay"; }; +&spdif { + pinctrl-0 = <&spdifm0_tx>; + status = "okay"; +}; + &tsadc { rockchip,hw-tshut-mode = <0>; rockchip,hw-tshut-polarity = <0>; @@ -358,6 +381,11 @@ status = "okay"; }; +&usbdrd3 { + dr_mode = "host"; + status = "okay"; +}; + &vop { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts index 329d03172433..c0b7b98ff788 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts @@ -44,10 +44,6 @@ mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>; }; -&gpu { - mali-supply = <&vdd_logic>; -}; - &pinctrl { ir { ir_int: ir-int { diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi index b5bd5e7d5748..7d62a3e96b19 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi @@ -84,6 +84,13 @@ regulator-boot-on; }; + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&ir_int>; + pinctrl-names = "default"; + }; + leds { compatible = "gpio-leds"; @@ -160,6 +167,10 @@ status = "okay"; }; +&gpu { + mali-supply = <&vdd_logic>; +}; + &hdmi { status = "okay"; }; @@ -300,6 +311,12 @@ }; &pinctrl { + ir { + ir_int: ir-int { + rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts index 5367e5fa9232..592fd8ca21df 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts @@ -152,6 +152,10 @@ status = "okay"; }; +&gpu { + mali-supply = <&vdd_logic>; +}; + &hdmi { avdd-0v9-supply = <&vdd_10>; avdd-1v8-supply = <&vcc_18>; diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 6438c969f9d7..283d9cbc4368 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -331,6 +331,11 @@ #address-cells = <1>; #size-cells = <0>; + power-domain@RK3328_PD_GPU { + reg = <RK3328_PD_GPU>; + clocks = <&cru ACLK_GPU>; + #power-domain-cells = <0>; + }; power-domain@RK3328_PD_HEVC { reg = <RK3328_PD_HEVC>; clocks = <&cru SCLK_VENC_CORE>; @@ -570,9 +575,13 @@ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; contribution = <4096>; }; + map1 { + trip = <&target>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <4096>; + }; }; }; - }; tsadc: tsadc@ff250000 { @@ -651,7 +660,36 @@ "ppmmu1"; clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; clock-names = "bus", "core"; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&power RK3328_PD_GPU>; resets = <&cru SRST_GPU_A>; + #cooling-cells = <2>; + }; + + gpu_opp_table: opp-table-gpu { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1075000>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1075000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1075000>; + }; + + opp-500000000 { + /* causes stability issues */ + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1150000>; + status = "disabled"; + }; }; h265e_mmu: iommu@ff330200 { diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lba3368.dts b/arch/arm64/boot/dts/rockchip/rk3368-lba3368.dts index b99bb0a5f900..b9801a691b48 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-lba3368.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-lba3368.dts @@ -609,7 +609,7 @@ bluetooth { compatible = "brcm,bcm4345c5"; - interrupts-extended = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + interrupts-extended = <&gpio3 RK_PA7 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "host-wakeup"; clocks = <&rk808 RK808_CLKOUT1>; clock-names = "lpo"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts index 5a8551d9ffe4..eaaca08a7601 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts @@ -883,6 +883,12 @@ }; }; + wifi { + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + wireless-bluetooth { bt_wake_pin: bt-wake-pin { rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; @@ -940,7 +946,19 @@ pinctrl-names = "default"; pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; sd-uhs-sdr104; + #address-cells = <1>; + #size-cells = <0>; status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; }; &sdhci { @@ -959,6 +977,7 @@ reg = <0>; m25p,fast-read; spi-max-frequency = <10000000>; + vcc-supply = <&vcc_3v0>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts index 585ef0fd88ef..2dca1dca20b8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts @@ -689,6 +689,12 @@ }; }; + wifi { + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + wireless-bluetooth { bt_wake_pin: bt-wake-pin { rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; @@ -715,7 +721,19 @@ pinctrl-names = "default"; pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; sd-uhs-sdr104; + #address-cells = <1>; + #size-cells = <0>; status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio4>; + interrupts = <RK_PD0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; }; &pwm0 { @@ -754,6 +772,7 @@ compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <10000000>; + vcc-supply = <&vcc_1v8>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou-video-demo.dtso b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou-video-demo.dtso index d28880b8dd44..5e8f729c2cf2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou-video-demo.dtso +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou-video-demo.dtso @@ -26,7 +26,7 @@ }; cam_afvdd_2v8: regulator-cam-afvdd-2v8 { - compatible = "regulator-fixed"; + compatible = "regulator-fixed"; gpio = <&pca9670 2 GPIO_ACTIVE_LOW>; regulator-max-microvolt = <2800000>; regulator-min-microvolt = <2800000>; @@ -35,7 +35,7 @@ }; cam_avdd_2v8: regulator-cam-avdd-2v8 { - compatible = "regulator-fixed"; + compatible = "regulator-fixed"; gpio = <&pca9670 4 GPIO_ACTIVE_LOW>; regulator-max-microvolt = <2800000>; regulator-min-microvolt = <2800000>; @@ -44,7 +44,7 @@ }; cam_dovdd_1v8: regulator-cam-dovdd-1v8 { - compatible = "regulator-fixed"; + compatible = "regulator-fixed"; gpio = <&pca9670 3 GPIO_ACTIVE_LOW>; regulator-max-microvolt = <1800000>; regulator-min-microvolt = <1800000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts b/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts new file mode 100644 index 000000000000..6e21579365a5 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts @@ -0,0 +1,464 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pwm/pwm.h> +#include "rk3528.dtsi" + +/ { + model = "ArmSoM Sige1"; + compatible = "armsom,sige1", "rockchip,rk3528"; + + aliases { + ethernet0 = &gmac1; + i2c0 = &i2c0; + mmc0 = &sdhci; + mmc1 = &sdmmc; + mmc2 = &sdio0; + serial0 = &uart0; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-maskrom { + label = "MASKROM"; + linux,code = <KEY_SETUP>; + press-threshold-microvolt = <0>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&g_led>, <&r_led>; + + led-0 { + color = <LED_COLOR_ID_GREEN>; + default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + color = <LED_COLOR_ID_RED>; + default-state = "on"; + function = LED_FUNCTION_STATUS; + gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + }; + + vcc0v6_ddr: regulator-0v6-vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc0v6_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_0v9: regulator-0v9-vdd { + compatible = "regulator-fixed"; + regulator-name = "vdd_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_ddr: regulator-1v1-vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v8: regulator-1v8-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + }; + + vcc1v8_ddr: regulator-1v8-vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3: regulator-3v3-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_dcin>; + }; + + vcc3v3_sd: regulator-3v3-vcc-sd { + compatible = "regulator-fixed"; + gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwren_l>; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + }; + + vcc5v0_sys: regulator-5v0-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_dcin>; + }; + + vcc5v0_usb1_host: regulator-5v0-vcc-usb1-host { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_host1_drv_h>; + regulator-name = "vcc5v0_usb1_host"; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb2_host: regulator-5v0-vcc-usb2-host { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_host2_drv_h>; + regulator-name = "vcc5v0_usb2_host"; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb_otg: regulator-5v0-vcc-usb-otg { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_otg0_drv_h>; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_dcin: regulator-vcc-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc_dcin"; + regulator-always-on; + regulator-boot-on; + }; + + vccio_sd: regulator-vccio-sd { + compatible = "regulator-gpio"; + gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_vol_ctrl_h>; + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <1800000 0x0>, <3300000 0x1>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_arm: regulator-vdd-arm { + compatible = "pwm-regulator"; + pwms = <&pwm3 0 5000 PWM_POLARITY_INVERTED>; + pwm-supply = <&vcc5v0_sys>; + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <746000>; + regulator-max-microvolt = <1201000>; + regulator-settling-time-up-us = <250>; + }; + + vdd_logic: regulator-vdd-logic { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 5000 PWM_POLARITY_INVERTED>; + pwm-supply = <&vcc5v0_sys>; + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <705000>; + regulator-max-microvolt = <1006000>; + regulator-settling-time-up-us = <250>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>, <&clkm1_32k_out>; + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_miim>, <&rgmii_tx_bus2>, <&rgmii_rx_bus2>, + <&rgmii_rgmii_clk>, <&rgmii_rgmii_bus>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m0_xfer>; + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + interrupt-parent = <&gpio4>; + interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int_l>; + wakeup-source; + }; +}; + +&mdio1 { + rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_rstn_l>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + bluetooth { + bt_reg_on_h: bt-reg-on-h { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host_h: bt-wake-host-h { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + host_wake_bt_h: host-wake-bt-h { + rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ethernet { + gmac1_rstn_l: gmac1-rstn-l { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + g_led: g-led { + rockchip,pins = <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + r_led: r-led { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtc { + rtc_int_l: rtc-int-l { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc_vol_ctrl_h: sdmmc-vol-ctrl-h { + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + sdmmc_pwren_l: sdmmc-pwren-l { + rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb20_host1_drv_h: usb20-host1-drv-h { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb20_host2_drv_h: usb20-host2-drv-h { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb20_otg0_drv_h: usb20-otg0-drv-h { + rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_reg_on_h: wifi-reg-on-h { + rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_wake_host_h: wifi-wake-host-h { + rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2m0_pins>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m0_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sd; + no-sdio; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + no-mmc; + no-sd; + non-removable; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + clocks = <&cru CLK_DEEPSLOW>; + clock-names = "lpo"; + interrupt-parent = <&gpio1>; + interrupts = <RK_PA7 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_wake_host_h>; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; +}; + +&uart2 { + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer>, <&uart2m1_ctsn>, <&uart2m1_rtsn>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&cru CLK_DEEPSLOW>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio1>; + interrupts = <RK_PC2 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wakeup"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on_h>, <&bt_wake_host_h>, <&host_wake_bt_h>; + shutdown-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + vbat-supply = <&vcc_3v3>; + vddio-supply = <&vcc_1v8>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts b/arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts new file mode 100644 index 000000000000..9f683033c5f3 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts @@ -0,0 +1,340 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pwm/pwm.h> +#include "rk3528.dtsi" + +/ { + model = "FriendlyElec NanoPi Zero2"; + compatible = "friendlyarm,nanopi-zero2", "rockchip,rk3528"; + + aliases { + ethernet0 = &gmac1; + i2c1 = &i2c1; + mmc0 = &sdhci; + mmc1 = &sdmmc; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; + + adc-keys-0 { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-maskrom { + label = "MASK"; + linux,code = <KEY_SETUP>; + press-threshold-microvolt = <0>; + }; + }; + + adc-keys-1 { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-recovery { + label = "RECOVERY"; + linux,code = <KEY_VENDOR>; + press-threshold-microvolt = <0>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led1>, <&led_sys>; + + led-0 { + color = <LED_COLOR_ID_RED>; + default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + color = <LED_COLOR_ID_GREEN>; + default-state = "on"; + function = LED_FUNCTION_STATUS; + gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + }; + + vcc0v6_ddr: regulator-0v6-vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc0v6_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_0v9: regulator-0v9-vdd { + compatible = "regulator-fixed"; + regulator-name = "vdd_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_ddr: regulator-1v1-vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v8: regulator-1v8-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + }; + + vcc_3v3: regulator-3v3-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_sd: regulator-3v3-vcc-sd { + compatible = "regulator-fixed"; + gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwren_l>; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + }; + + vcc5v0_sys: regulator-5v0-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + usb2_host_5v: regulator-5v0-usb2-host { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_host1_pwren>; + regulator-name = "usb2_host_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vccio_sd: regulator-vccio-sd { + compatible = "regulator-gpio"; + gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_vol_ctrl_h>; + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <1800000 0x0>, <3300000 0x1>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_arm: regulator-vdd-arm { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 5000 PWM_POLARITY_INVERTED>; + pwm-supply = <&vcc5v0_sys>; + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <746000>; + regulator-max-microvolt = <1201000>; + regulator-settling-time-up-us = <250>; + }; + + vdd_logic: regulator-vdd-logic { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 5000 PWM_POLARITY_INVERTED>; + pwm-supply = <&vcc5v0_sys>; + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <705000>; + regulator-max-microvolt = <1006000>; + regulator-settling-time-up-us = <250>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_miim>, <&rgmii_tx_bus2>, <&rgmii_rx_bus2>, + <&rgmii_rgmii_clk>, <&rgmii_rgmii_bus>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m0_xfer>; + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + interrupt-parent = <&gpio4>; + interrupts = <RK_PC1 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int_l>; + wakeup-source; + }; +}; + +&mdio1 { + rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_rstn_l>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + ethernet { + gmac1_rstn_l: gmac1-rstn-l { + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + led1: led1 { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + led_sys: led-sys { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtc { + rtc_int_l: rtc-int-l { + rockchip,pins = <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc_vol_ctrl_h: sdmmc-vol-ctrl-h { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + sdmmc_pwren_l: sdmmc-pwren-l { + rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb20_host1_pwren: usb20-host1-pwren { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm1m0_pins>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2m0_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sd; + no-sdio; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi b/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi new file mode 100644 index 000000000000..aedc7ee9ee46 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi @@ -0,0 +1,293 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pwm/pwm.h> +#include "rk3528.dtsi" + +/ { + aliases { + i2c1 = &i2c1; + mmc0 = &sdhci; + mmc1 = &sdmmc; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-maskrom { + label = "MASKROM"; + linux,code = <KEY_SETUP>; + press-threshold-microvolt = <0>; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&state_led_b>; + + led-0 { + color = <LED_COLOR_ID_BLUE>; + default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + vdd_0v9: regulator-0v9-vdd { + compatible = "regulator-fixed"; + regulator-name = "vdd_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_ddr: regulator-1v1-vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v8: regulator-1v8-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + }; + + vcc_3v3: regulator-3v3-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_wifi: regulator-3v3-vcc-wifi { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_wifi_pwr>; + regulator-name = "vcc_wifi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + }; + + vcc5v0_sys: regulator-5v0-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_usb20: regulator-5v0-vcc-usb20 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_en>; + regulator-name = "vcc5v0_usb20"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vccio_sd: regulator-vccio-sd { + compatible = "regulator-gpio"; + gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_vol_ctrl_h>; + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <1800000 0x0>, <3300000 0x1>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_arm: regulator-vdd-arm { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 5000 PWM_POLARITY_INVERTED>; + pwm-supply = <&vcc5v0_sys>; + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <746000>; + regulator-max-microvolt = <1201000>; + regulator-settling-time-up-us = <250>; + }; + + vdd_logic: regulator-vdd-logic { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 5000 PWM_POLARITY_INVERTED>; + pwm-supply = <&vcc5v0_sys>; + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <705000>; + regulator-max-microvolt = <1006000>; + regulator-settling-time-up-us = <250>; + }; + + rfkill { + compatible = "rfkill-gpio"; + label = "rfkill-wlan"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>; + radio-type = "wlan"; + shutdown-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m0_xfer>; + status = "okay"; + + eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&vcc_3v3>; + }; +}; + +&pinctrl { + bluetooth { + bt_wake_host_h: bt-wake-host-h { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + host_wake_bt_h: host-wake-bt-h { + rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + state_led_b: state-led-b { + rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_vol_ctrl_h: sdmmc-vol-ctrl-h { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb_host_en: usb-host-en { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + usb_wifi_pwr: usb-wifi-pwr { + rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_reg_on_h: wifi-reg-on-h { + rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_wake_host_h: wifi-wake-host-h { + rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm1m0_pins>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2m0_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sd; + no-sdio; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <100000000>; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts b/arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts new file mode 100644 index 000000000000..c03ae1dd3456 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3528-rock-2.dtsi" + +/ { + model = "Radxa ROCK 2A"; + compatible = "radxa,rock-2a", "rockchip,rk3528"; + + aliases { + ethernet0 = &gmac1; + }; + + vcc5v0_usb30_otg: regulator-5v0-vcc-usb30-otg { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg_en>; + regulator-name = "vcc5v0_usb30_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_miim>, <&rgmii_tx_bus2>, <&rgmii_rx_bus2>, + <&rgmii_rgmii_clk>, <&rgmii_rgmii_bus>; + status = "okay"; +}; + +&leds { + pinctrl-names = "default"; + pinctrl-0 = <&state_led_b>, <&sys_led_g>; + + led-1 { + color = <LED_COLOR_ID_GREEN>; + default-state = "on"; + function = LED_FUNCTION_STATUS; + gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; +}; + +&mdio1 { + rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_rstn_l>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + ethernet { + gmac1_rstn_l: gmac1-rstn-l { + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + sys_led_g: sys-led-g { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb_otg_en: usb-otg-en { + rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts b/arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts new file mode 100644 index 000000000000..3e2b9b685cb2 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3528-rock-2.dtsi" + +/ { + model = "Radxa ROCK 2F"; + compatible = "radxa,rock-2f", "rockchip,rk3528"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index 001a555c83b7..d5f8f7b9bf01 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/clock/rockchip,rk3528-cru.h> +#include <dt-bindings/power/rockchip,rk3528-power.h> #include <dt-bindings/reset/rockchip,rk3528-cru.h> / { @@ -53,6 +54,7 @@ device_type = "cpu"; enable-method = "psci"; clocks = <&scmi_clk SCMI_CLK_CPU>; + operating-points-v2 = <&cpu_opp_table>; }; cpu1: cpu@1 { @@ -61,6 +63,7 @@ device_type = "cpu"; enable-method = "psci"; clocks = <&scmi_clk SCMI_CLK_CPU>; + operating-points-v2 = <&cpu_opp_table>; }; cpu2: cpu@2 { @@ -69,6 +72,7 @@ device_type = "cpu"; enable-method = "psci"; clocks = <&scmi_clk SCMI_CLK_CPU>; + operating-points-v2 = <&cpu_opp_table>; }; cpu3: cpu@3 { @@ -77,6 +81,7 @@ device_type = "cpu"; enable-method = "psci"; clocks = <&scmi_clk SCMI_CLK_CPU>; + operating-points-v2 = <&cpu_opp_table>; }; }; @@ -95,6 +100,41 @@ }; }; + cpu_opp_table: opp-table-cpu { + compatible = "operating-points-v2"; + opp-shared; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <875000 875000 1100000>; + clock-latency-ns = <40000>; + }; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <925000 925000 1100000>; + clock-latency-ns = <40000>; + }; + + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <975000 975000 1100000>; + clock-latency-ns = <40000>; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1037500 1037500 1100000>; + clock-latency-ns = <40000>; + }; + + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <1100000 1100000 1100000>; + clock-latency-ns = <40000>; + }; + }; + gpu_opp_table: opp-table-gpu { compatible = "operating-points-v2"; @@ -154,6 +194,7 @@ gpio-ranges = <&pinctrl 0 32 32>; interrupt-controller; #interrupt-cells = <2>; + power-domains = <&power RK3528_PD_VPU>; }; gpio2: gpio@ffb00000 { @@ -166,6 +207,7 @@ gpio-ranges = <&pinctrl 0 64 32>; interrupt-controller; #interrupt-cells = <2>; + power-domains = <&power RK3528_PD_VO>; }; gpio3: gpio@ffb10000 { @@ -178,6 +220,7 @@ gpio-ranges = <&pinctrl 0 96 32>; interrupt-controller; #interrupt-cells = <2>; + power-domains = <&power RK3528_PD_VPU>; }; gpio4: gpio@ffb20000 { @@ -190,6 +233,7 @@ gpio-ranges = <&pinctrl 0 128 32>; interrupt-controller; #interrupt-cells = <2>; + power-domains = <&power RK3528_PD_RKVENC>; }; }; @@ -416,6 +460,11 @@ reg = <0x0 0xff340000 0x0 0x8000>; }; + pipe_phy_grf: syscon@ff348000 { + compatible = "rockchip,rk3528-pipe-phy-grf", "syscon"; + reg = <0x0 0xff348000 0x0 0x8000>; + }; + vo_grf: syscon@ff360000 { compatible = "rockchip,rk3528-vo-grf", "syscon"; reg = <0x0 0xff360000 0x0 0x10000>; @@ -480,8 +529,8 @@ #size-cells = <0>; /* These power domains are grouped by VD_GPU */ - power-domain@4 { - reg = <4>; + power-domain@RK3528_PD_GPU { + reg = <RK3528_PD_GPU>; clocks = <&cru ACLK_GPU_MALI>, <&cru PCLK_GPU_ROOT>; pm_qos = <&qos_gpu_m0>, @@ -490,20 +539,19 @@ }; /* These power domains are grouped by VD_LOGIC */ - power-domain@5 { - reg = <5>; + power-domain@RK3528_PD_RKVDEC { + reg = <RK3528_PD_RKVDEC>; pm_qos = <&qos_rkvdec>; #power-domain-cells = <0>; status = "disabled"; }; - power-domain@6 { - reg = <6>; + power-domain@RK3528_PD_RKVENC { + reg = <RK3528_PD_RKVENC>; pm_qos = <&qos_rkvenc>; #power-domain-cells = <0>; - status = "disabled"; }; - power-domain@7 { - reg = <7>; + power-domain@RK3528_PD_VO { + reg = <RK3528_PD_VO>; pm_qos = <&qos_gmac0>, <&qos_hdcp>, <&qos_jpegdec>, @@ -514,10 +562,9 @@ <&qos_vdpp>, <&qos_vop>; #power-domain-cells = <0>; - status = "disabled"; }; - power-domain@8 { - reg = <8>; + power-domain@RK3528_PD_VPU { + reg = <RK3528_PD_VPU>; pm_qos = <&qos_emmc>, <&qos_fspi>, <&qos_gmac1>, @@ -528,7 +575,6 @@ <&qos_usb3otg>, <&qos_vpu>; #power-domain-cells = <0>; - status = "disabled"; }; }; }; @@ -556,7 +602,7 @@ "pp1", "ppmmu1"; operating-points-v2 = <&gpu_opp_table>; - power-domains = <&power 4>; + power-domains = <&power RK3528_PD_GPU>; resets = <&cru SRST_A_GPU>; status = "disabled"; }; @@ -570,6 +616,7 @@ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dmac 25>, <&dmac 24>; dma-names = "tx", "rx"; + power-domains = <&power RK3528_PD_RKVENC>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -584,6 +631,7 @@ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dmac 31>, <&dmac 30>; dma-names = "tx", "rx"; + power-domains = <&power RK3528_PD_VPU>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -608,6 +656,7 @@ clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dmac 11>, <&dmac 10>; + power-domains = <&power RK3528_PD_RKVENC>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -620,6 +669,7 @@ clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dmac 13>, <&dmac 12>; + power-domains = <&power RK3528_PD_VPU>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -632,6 +682,7 @@ clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dmac 15>, <&dmac 14>; + power-domains = <&power RK3528_PD_RKVENC>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -644,6 +695,7 @@ clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dmac 17>, <&dmac 16>; + power-domains = <&power RK3528_PD_VO>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -656,6 +708,7 @@ clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dmac 19>, <&dmac 18>; + power-domains = <&power RK3528_PD_VPU>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -668,6 +721,7 @@ clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dmac 21>, <&dmac 20>; + power-domains = <&power RK3528_PD_VPU>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -680,6 +734,7 @@ clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dmac 23>, <&dmac 22>; + power-domains = <&power RK3528_PD_VPU>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -692,6 +747,7 @@ clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; clock-names = "i2c", "pclk"; interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&power RK3528_PD_RKVENC>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -704,6 +760,7 @@ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; clock-names = "i2c", "pclk"; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&power RK3528_PD_RKVENC>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -730,6 +787,7 @@ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; clock-names = "i2c", "pclk"; interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&power RK3528_PD_VPU>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -744,6 +802,7 @@ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&i2c4_xfer>; + power-domains = <&power RK3528_PD_VO>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -756,6 +815,7 @@ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; clock-names = "i2c", "pclk"; interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&power RK3528_PD_VPU>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -768,6 +828,7 @@ clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; clock-names = "i2c", "pclk"; interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&power RK3528_PD_VPU>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -782,6 +843,7 @@ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&i2c7_xfer>; + power-domains = <&power RK3528_PD_VO>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -873,6 +935,7 @@ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk"; interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&power RK3528_PD_VPU>; resets = <&cru SRST_P_SARADC>; reset-names = "saradc-apb"; #io-channel-cells = <1>; @@ -893,6 +956,7 @@ interrupt-names = "macirq", "eth_wake_irq"; phy-handle = <&rmii0_phy>; phy-mode = "rmii"; + power-domains = <&power RK3528_PD_VO>; resets = <&cru SRST_A_MAC_VO>; reset-names = "stmmaceth"; rockchip,grf = <&vo_grf>; @@ -951,6 +1015,7 @@ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq", "eth_wake_irq"; + power-domains = <&power RK3528_PD_VPU>; resets = <&cru SRST_A_MAC>; reset-names = "stmmaceth"; rockchip,grf = <&vpu_grf>; @@ -1001,6 +1066,7 @@ pinctrl-names = "default"; pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>, <&emmc_strb>; + power-domains = <&power RK3528_PD_VPU>; resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, <&cru SRST_T_EMMC>; @@ -1022,6 +1088,7 @@ max-frequency = <200000000>; pinctrl-names = "default"; pinctrl-0 = <&sdio0_bus4>, <&sdio0_clk>, <&sdio0_cmd>; + power-domains = <&power RK3528_PD_VPU>; resets = <&cru SRST_H_SDIO0>; reset-names = "reset"; status = "disabled"; @@ -1041,6 +1108,7 @@ max-frequency = <200000000>; pinctrl-names = "default"; pinctrl-0 = <&sdio1_bus4>, <&sdio1_clk>, <&sdio1_cmd>; + power-domains = <&power RK3528_PD_VPU>; resets = <&cru SRST_H_SDIO1>; reset-names = "reset"; status = "disabled"; @@ -1061,6 +1129,7 @@ pinctrl-names = "default"; pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_det>; + power-domains = <&power RK3528_PD_VO>; resets = <&cru SRST_H_SDMMC0>; reset-names = "reset"; rockchip,default-sample-phase = <90>; @@ -1084,6 +1153,25 @@ #dma-cells = <1>; arm,pl330-periph-burst; }; + + combphy: phy@ffdc0000 { + compatible = "rockchip,rk3528-naneng-combphy"; + reg = <0x0 0xffdc0000 0x0 0x10000>; + assigned-clocks = <&cru CLK_REF_PCIE_INNER_PHY>; + assigned-clock-rates = <100000000>; + clocks = <&cru CLK_REF_PCIE_INNER_PHY>, + <&cru PCLK_PCIE_PHY>, + <&cru PCLK_PIPE_GRF>; + clock-names = "ref", "apb", "pipe"; + power-domains = <&power RK3528_PD_VPU>; + resets = <&cru SRST_PCIE_PIPE_PHY>, + <&cru SRST_P_PCIE_PHY>; + reset-names = "phy", "apb"; + #phy-cells = <1>; + rockchip,pipe-grf = <&vpu_grf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf>; + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi index e7ba477e75f9..7f578c50b4ad 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi @@ -53,7 +53,7 @@ gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>; linux,default-trigger = "default-on"; pinctrl-names = "default"; - pinctrl-0 =<&blue_led>; + pinctrl-0 = <&blue_led>; }; led-1 { @@ -62,7 +62,7 @@ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; pinctrl-names = "default"; - pinctrl-0 =<&heartbeat_led>; + pinctrl-0 = <&heartbeat_led>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-hinlink-h66k.dts b/arch/arm64/boot/dts/rockchip/rk3568-hinlink-h66k.dts new file mode 100644 index 000000000000..bc51123d53f5 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-hinlink-h66k.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3568-hinlink-opc.dtsi" + +/ { + model = "HINLINK H66K"; + compatible = "hinlink,h66k", "rockchip,rk3568"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-hinlink-h68k.dts b/arch/arm64/boot/dts/rockchip/rk3568-hinlink-h68k.dts new file mode 100644 index 000000000000..793ee651b868 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-hinlink-h68k.dts @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3568-hinlink-opc.dtsi" + +/ { + model = "HINLINK H68K"; + compatible = "hinlink,h68k", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + }; +}; + +&gmac0 { + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc3v3_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus + &gmac0_rstn>; + status = "okay"; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc3v3_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus + &gmac1_rstn>; + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + gmac { + gmac0_rstn: gmac0-rstn { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + gmac1_rstn: gmac1-rstn { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-hinlink-opc.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-hinlink-opc.dtsi new file mode 100644 index 000000000000..14f3839ca091 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-hinlink-opc.dtsi @@ -0,0 +1,666 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3568.dtsi" + +/ { + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc0; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_ir_m0>; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&factory>; + + button-factory { + label = "factory"; + linux,code = <KEY_RESTART>; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + debounce-interval = <50>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&green_led>, <&red_led>, <&work_led>; + + led-0 { + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_WAN; + gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "netdev"; + }; + + led-1 { + color = <LED_COLOR_ID_AMBER>; + function = LED_FUNCTION_DISK; + gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + }; + + led-2 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + }; + + vcc0v9_2g5: regulator-0v9-vcc-2g5 { + compatible = "regulator-fixed"; + regulator-name = "vcc0v9_2g5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc12v_dcinp: regulator-12v-vcc-dcinp { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcinp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_pi6c_05: regulator-3v3-vcc-pi6c-05 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lan_power_en>; + regulator-name = "vcc3v3_pi6c_05"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_sd: regulator-3v3-vcc-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sd_pwren>; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sys: regulator-3v3-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: regulator-5v0-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcinp>; + }; + + vcc5v0_usb30_otg0: regulator-5v0-vcc-usb30-otg0 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_power_en>; + regulator-name = "vcc5v0_usb30_otg0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + #clock-cells = <1>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3: SWITCH_REG2 { + regulator-name = "vcc3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_perstn>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pi6c_05>; + status = "okay"; +}; + +&pcie30phy { + data-lanes = <1 2>; + status = "okay"; +}; + +&pcie3x1 { + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&lan_resetb>; + reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pi6c_05>; + status = "okay"; +}; + +&pcie3x2 { + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&lan_reseta>; + reset-gpios = <&gpio2 RK_PD0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pi6c_05>; + status = "okay"; +}; + +&pinctrl { + keys { + factory: factory { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + green_led: green-led { + rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + red_led: red-led { + rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + work_led: work-led { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ir { + pwm3_ir_m0: pwm3-ir-m0 { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + mmc { + sd_pwren: sd-pwren { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + lan_power_en: lan-power-en { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan_reseta: lan-reseta { + rockchip,pins = <2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan_resetb: lan-resetb { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_perstn: wifi-perstn { + rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + usb_power_en: usb-power-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +/* Via Type-C adapter */ +&sata0 { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <200000000>; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr50; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb30_otg0>; + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_usb30_otg0>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb30_otg0>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts index 101e2ee9766d..3386084f6318 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts @@ -302,8 +302,7 @@ ð1m0_tx_bus2 ð1m0_rx_bus2 ð1m0_rgmii_clk - ð1m0_rgmii_bus - ðm0_clk1_25m_out>; + ð1m0_rgmii_bus>; status = "okay"; }; @@ -784,7 +783,6 @@ rgmii_phy0: phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x1>; - clocks = <&cru REFCLKO25M_GMAC0_OUT>; pinctrl-names = "default"; pinctrl-0 = <&gmac0_rst>; reset-assert-us = <20000>; @@ -797,7 +795,6 @@ rgmii_phy1: phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x1>; - clocks = <&cru REFCLKO25M_GMAC1_OUT>; pinctrl-names = "default"; pinctrl-0 = <&gmac1_rst>; reset-assert-us = <20000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts index 56527c56830e..db8fef7a4f1b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts @@ -232,6 +232,20 @@ regulator-max-microvolt = <3300000>; vin-supply = <&vcc_sys>; }; + + vcc_wifi_reg_on: regulator-wifi-reg-on { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&wifi_reg_on>; + pinctrl-names = "default"; + regulator-name = "wifi_reg_on"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_s3>; + }; }; &cpu_l0 { @@ -242,6 +256,10 @@ cpu-supply = <&vdd_cpu_big_s0>; }; +&combphy0_ps { + status = "okay"; +}; + &combphy1_psu { status = "okay"; }; @@ -257,9 +275,6 @@ ð0m0_rgmii_clk ð0m0_rgmii_bus ðm0_clk0_25m_out>; - snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 20000 100000>; tx_delay = <0x21>; status = "okay"; }; @@ -275,9 +290,6 @@ ð1m0_rgmii_clk ð1m0_rgmii_bus ðm0_clk1_25m_out>; - snps,reset-gpio = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 20000 100000>; tx_delay = <0x20>; status = "okay"; }; @@ -680,19 +692,73 @@ }; }; +&i2c2 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + wakeup-source; + #clock-cells = <0>; + }; +}; + &mdio0 { - rgmii_phy0: phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; + rgmii_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; reg = <0x1>; clocks = <&cru REFCLKO25M_GMAC0_OUT>; + assigned-clocks = <&cru REFCLKO25M_GMAC0_OUT>; + assigned-clock-rates = <25000000>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_phy0_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; }; }; &mdio1 { - rgmii_phy1: phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; reg = <0x1>; clocks = <&cru REFCLKO25M_GMAC1_OUT>; + assigned-clocks = <&cru REFCLKO25M_GMAC1_OUT>; + assigned-clock-rates = <25000000>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_phy1_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_rst>; + reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_s3>; + status = "okay"; + + pcie@0,0 { + reg = <0x0 0 0 0 0>; + bus-range = <0x0 0xf>; + device_type = "pci"; + ranges; + #address-cells = <3>; + #size-cells = <2>; + + wifi: wifi@0,0 { + compatible = "pci14e4,449d"; + reg = <0x10000 0 0 0 0>; + clocks = <&hym8563>; + clock-names = "lpo"; + }; }; }; @@ -708,6 +774,42 @@ }; &pinctrl { + bluetooth { + bt_reg_on: bt-reg-on { + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + bt_wake_host: bt-wake-host { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + host_wake_bt: host-wake-bt { + rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + network { + rgmii_phy0_rst: rgmii-phy0-rst { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + rgmii_phy1_rst: rgmii-phy1-rst { + rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie0 { + pcie0_rst: pcie0-rst { + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + usb { usb_host_pwren: usb-host-pwren { rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; @@ -721,6 +823,28 @@ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; }; }; + + wifi { + wifi_reg_on: wifi-reg-on { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + wifi_wake_host: wifi-wake-host { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&sdhci { + bus-width = <8>; + full-pwr-cycle-in-suspend; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sdio; + no-sd; + non-removable; + status = "okay"; }; &sdmmc { @@ -763,6 +887,27 @@ status = "okay"; }; +&uart4 { + pinctrl-0 = <&uart4m1_xfer &uart4m1_ctsn &uart4m1_rtsn>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&hym8563>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB1 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&bt_reg_on &bt_wake_host &host_wake_bt>; + pinctrl-names = "default"; + shutdown-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; + vbat-supply = <&vcc_3v3_s3>; + vddio-supply = <&vcc_1v8_s3>; + }; +}; + &ufshc { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts index d4e437ea6cd8..d0ab1d1e0e11 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts @@ -107,6 +107,18 @@ vin-supply = <&vcc_1v8_s3>; }; + vcc3v3_lcd_s0: regulator-vcc3v3-lcd-s0 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pwren_h>; + regulator-name = "vcc3v3-lcd-s0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + vcc3v3_pcie: regulator-vcc3v3-pcie { compatible = "regulator-fixed"; enable-active-high; @@ -715,6 +727,10 @@ }; power { + lcd_pwren_h: lcd-pwren-h { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc5vd_en: vcc5vd-en { rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index c3cdae8a5494..fc4e9e07f1cf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -11,6 +11,7 @@ #include <dt-bindings/power/rockchip,rk3576-power.h> #include <dt-bindings/reset/rockchip,rk3576-cru.h> #include <dt-bindings/soc/rockchip,boot-mode.h> +#include <dt-bindings/thermal/thermal.h> / { compatible = "rockchip,rk3576"; @@ -113,9 +114,9 @@ capacity-dmips-mhz = <485>; clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; - #cooling-cells = <2>; dynamic-power-coefficient = <120>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_l1: cpu@1 { @@ -127,6 +128,7 @@ clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_l2: cpu@2 { @@ -138,6 +140,7 @@ clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_l3: cpu@3 { @@ -149,6 +152,7 @@ clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_b0: cpu@100 { @@ -159,9 +163,9 @@ capacity-dmips-mhz = <1024>; clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; - #cooling-cells = <2>; dynamic-power-coefficient = <320>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_b1: cpu@101 { @@ -173,6 +177,7 @@ clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_b2: cpu@102 { @@ -184,6 +189,7 @@ clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_b3: cpu@103 { @@ -195,6 +201,7 @@ clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; idle-states { @@ -520,6 +527,143 @@ method = "smc"; }; + thermal_zones: thermal-zones { + /* sensor near the center of the SoC */ + package_thermal: package-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 0>; + + trips { + package_crit: package-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + /* sensor for cluster1 (big Cortex-A72 cores) */ + bigcore_thermal: bigcore-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&tsadc 1>; + + trips { + bigcore_alert: bigcore-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + bigcore_crit: bigcore-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&bigcore_alert>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + /* sensor for cluster0 (little Cortex-A53 cores) */ + littlecore_thermal: littlecore-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&tsadc 2>; + + trips { + littlecore_alert: littlecore-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + littlecore_crit: littlecore-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&littlecore_alert>; + cooling-device = + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&tsadc 3>; + + trips { + gpu_alert: gpu-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu_crit: gpu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_alert>; + cooling-device = + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + npu_thermal: npu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 4>; + + trips { + npu_crit: npu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + ddr_thermal: ddr-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 5>; + + trips { + ddr_crit: ddr-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, @@ -822,6 +966,12 @@ reg = <0x0 0x26032000 0x0 0x100>; }; + mipidcphy_grf: syscon@26034000 { + compatible = "rockchip,rk3576-dcphy-grf", "syscon"; + reg = <0x0 0x26034000 0x0 0x2000>; + clocks = <&cru PCLK_PMUPHY_ROOT>; + }; + vo1_grf: syscon@26036000 { compatible = "rockchip,rk3576-vo1-grf", "syscon"; reg = <0x0 0x26036000 0x0 0x100>; @@ -1239,6 +1389,34 @@ status = "disabled"; }; + dsi: dsi@27d80000 { + compatible = "rockchip,rk3576-mipi-dsi2"; + reg = <0x0 0x27d80000 0x0 0x10000>; + interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>; + clock-names = "pclk", "sys"; + power-domains = <&power RK3576_PD_VO0>; + resets = <&cru SRST_P_DSIHOST0>; + reset-names = "apb"; + phys = <&mipidcphy PHY_TYPE_DPHY>; + phy-names = "dcphy"; + rockchip,grf = <&vo0_grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dsi_in: port@0 { + reg = <0>; + }; + + dsi_out: port@1 { + reg = <1>; + }; + }; + }; + hdmi: hdmi@27da0000 { compatible = "rockchip,rk3576-dw-hdmi-qp"; reg = <0x0 0x27da0000 0x0 0x20000>; @@ -1793,6 +1971,30 @@ log_leakage: log-leakage@22 { reg = <0x22 0x1>; }; + bigcore_tsadc_trim: bigcore-tsadc-trim@24 { + reg = <0x24 0x2>; + bits = <0 10>; + }; + litcore_tsadc_trim: litcore-tsadc-trim@26 { + reg = <0x26 0x2>; + bits = <0 10>; + }; + ddr_tsadc_trim: ddr-tsadc-trim@28 { + reg = <0x28 0x2>; + bits = <0 10>; + }; + npu_tsadc_trim: npu-tsadc-trim@2a { + reg = <0x2a 0x2>; + bits = <0 10>; + }; + gpu_tsadc_trim: gpu-tsadc-trim@2c { + reg = <0x2c 0x2>; + bits = <0 10>; + }; + soc_tsadc_trim: soc-tsadc-trim@64 { + reg = <0x64 0x2>; + bits = <0 10>; + }; }; sai0: sai@2a600000 { @@ -2073,7 +2275,6 @@ clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; clock-names = "tclk", "pclk"; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; }; spi0: spi@2acf0000 { @@ -2303,6 +2504,55 @@ status = "disabled"; }; + tsadc: tsadc@2ae70000 { + compatible = "rockchip,rk3576-tsadc"; + reg = <0x0 0x2ae70000 0x0 0x400>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru CLK_TSADC>; + assigned-clock-rates = <2000000>; + resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; + reset-names = "tsadc-apb", "tsadc"; + #thermal-sensor-cells = <1>; + rockchip,hw-tshut-temp = <120000>; + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + #address-cells = <1>; + #size-cells = <0>; + + sensor@0 { + reg = <0>; + nvmem-cells = <&soc_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + sensor@1 { + reg = <1>; + nvmem-cells = <&bigcore_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + sensor@2 { + reg = <2>; + nvmem-cells = <&litcore_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + sensor@3 { + reg = <3>; + nvmem-cells = <&ddr_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + sensor@4 { + reg = <4>; + nvmem-cells = <&npu_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + sensor@5 { + reg = <5>; + nvmem-cells = <&gpu_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + }; + i2c9: i2c@2ae80000 { compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; reg = <0x0 0x2ae80000 0x0 0x1000>; @@ -2346,6 +2596,22 @@ status = "disabled"; }; + mipidcphy: phy@2b020000 { + compatible = "rockchip,rk3576-mipi-dcphy"; + reg = <0x0 0x2b020000 0x0 0x10000>; + clocks = <&cru PCLK_MIPI_DCPHY>, + <&cru CLK_PHY_REF_SRC>; + clock-names = "pclk", "ref"; + resets = <&cru SRST_M_MIPI_DCPHY>, + <&cru SRST_P_MIPI_DCPHY>, + <&cru SRST_P_DCPHY_GRF>, + <&cru SRST_S_MIPI_DCPHY>; + reset-names = "m_phy", "apb", "grf", "s_phy"; + rockchip,grf = <&mipidcphy_grf>; + #phy-cells = <1>; + status = "disabled"; + }; + combphy0_ps: phy@2b050000 { compatible = "rockchip,rk3576-naneng-combphy"; reg = <0x0 0x2b050000 0x0 0x100>; diff --git a/arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts b/arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts index e04f21d8c831..854c118418eb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts @@ -42,7 +42,7 @@ keys-1 { compatible = "gpio-keys"; pinctrl-names = "default"; - pinctrl-0 = <&btn_0>; + pinctrl-0 = <&pwm15_ir_m1>; button-1 { label = "User"; @@ -55,7 +55,7 @@ leds-0 { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&led_0>; + pinctrl-0 = <&power_led>; led-0 { color = <LED_COLOR_ID_GREEN>; @@ -71,7 +71,7 @@ led-1 { color = <LED_COLOR_ID_GREEN>; - default-state = "on"; + default-state = "off"; function = LED_FUNCTION_LAN; linux,default-trigger = "netdev"; pwms = <&pwm14 0 1000000 PWM_POLARITY_INVERTED>; @@ -80,7 +80,7 @@ led-2 { color = <LED_COLOR_ID_GREEN>; - default-state = "on"; + default-state = "off"; function = LED_FUNCTION_WAN; linux,default-trigger = "netdev"; pwms = <&pwm11 0 1000000 PWM_POLARITY_INVERTED>; @@ -98,16 +98,6 @@ vin-supply = <&vcc_sysin>; }; - vcc_3v3_pmu: regulator-3v3-0 { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_s3>; - }; - vcc_3v3_s0: regulator-3v3-1 { compatible = "regulator-fixed"; regulator-name = "vcc_3v3_s0"; @@ -250,6 +240,7 @@ compatible = "belling,bl24c16a", "atmel,24c16"; reg = <0x50>; pagesize = <16>; + read-only; vcc-supply = <&vcc_3v3_pmu>; }; }; @@ -311,13 +302,13 @@ &pinctrl { keys { - btn_0: button-0 { + pwm15_ir_m1: pwm15-ir-m1 { rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; leds { - led_0: led-0 { + power_led: power-led { rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; @@ -333,19 +324,19 @@ }; regulators { - vcc_5v0_pwren_h: regulator-5v0-1 { + vcc_5v0_pwren_h: vcc-5v0-pwren-h { rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; rtc { - rtc_int_l: rtc-0 { + rtc_int_l: rtc-int-l { rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; usb { - usb_otg_pwren_h: regulator-5v0-0 { + usb_otg_pwren_h: usb-otg-pwren-h { rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; @@ -537,7 +528,7 @@ }; }; - vcc_3v3_s3: dcdc-reg8 { + vcc_3v3_s3: vcc_3v3_pmu: dcdc-reg8 { regulator-name = "vcc_3v3_s3"; regulator-always-on; regulator-boot-on; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 70f03e68ba55..e2500e31c434 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -621,6 +621,16 @@ reg = <0x0 0xfd5b0000 0x0 0x1000>; }; + csidphy0_grf: syscon@fd5b4000 { + compatible = "rockchip,rk3588-csidphy-grf", "syscon"; + reg = <0x0 0xfd5b4000 0x0 0x1000>; + }; + + csidphy1_grf: syscon@fd5b5000 { + compatible = "rockchip,rk3588-csidphy-grf", "syscon"; + reg = <0x0 0xfd5b5000 0x0 0x1000>; + }; + pipe_phy0_grf: syscon@fd5bc000 { compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; reg = <0x0 0xfd5bc000 0x0 0x100>; @@ -841,7 +851,7 @@ status = "okay"; /* These power domains are grouped by VD_NPU */ - power-domain@RK3588_PD_NPU { + pd_npu: power-domain@RK3588_PD_NPU { reg = <RK3588_PD_NPU>; #power-domain-cells = <0>; #address-cells = <1>; @@ -1140,6 +1150,97 @@ }; }; + rknn_core_0: npu@fdab0000 { + compatible = "rockchip,rk3588-rknn-core"; + reg = <0x0 0xfdab0000 0x0 0x1000>, + <0x0 0xfdab1000 0x0 0x1000>, + <0x0 0xfdab3000 0x0 0x1000>; + reg-names = "pc", "cna", "core"; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>, + <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>; + clock-names = "aclk", "hclk", "npu", "pclk"; + assigned-clocks = <&scmi_clk SCMI_CLK_NPU>; + assigned-clock-rates = <200000000>; + resets = <&cru SRST_A_RKNN0>, <&cru SRST_H_RKNN0>; + reset-names = "srst_a", "srst_h"; + power-domains = <&power RK3588_PD_NPUTOP>; + iommus = <&rknn_mmu_0>; + status = "disabled"; + }; + + rknn_mmu_0: iommu@fdab9000 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdab9000 0x0 0x100>, + <0x0 0xfdaba000 0x0 0x100>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_NPUTOP>; + status = "disabled"; + }; + + rknn_core_1: npu@fdac0000 { + compatible = "rockchip,rk3588-rknn-core"; + reg = <0x0 0xfdac0000 0x0 0x1000>, + <0x0 0xfdac1000 0x0 0x1000>, + <0x0 0xfdac3000 0x0 0x1000>; + reg-names = "pc", "cna", "core"; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_NPU1>, <&cru HCLK_NPU1>, + <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>; + clock-names = "aclk", "hclk", "npu", "pclk"; + assigned-clocks = <&scmi_clk SCMI_CLK_NPU>; + assigned-clock-rates = <200000000>; + resets = <&cru SRST_A_RKNN1>, <&cru SRST_H_RKNN1>; + reset-names = "srst_a", "srst_h"; + power-domains = <&power RK3588_PD_NPU1>; + iommus = <&rknn_mmu_1>; + status = "disabled"; + }; + + rknn_mmu_1: iommu@fdac9000 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdaca000 0x0 0x100>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_NPU1>, <&cru HCLK_NPU1>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_NPU1>; + status = "disabled"; + }; + + rknn_core_2: npu@fdad0000 { + compatible = "rockchip,rk3588-rknn-core"; + reg = <0x0 0xfdad0000 0x0 0x1000>, + <0x0 0xfdad1000 0x0 0x1000>, + <0x0 0xfdad3000 0x0 0x1000>; + reg-names = "pc", "cna", "core"; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_NPU2>, <&cru HCLK_NPU2>, + <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>; + clock-names = "aclk", "hclk", "npu", "pclk"; + assigned-clocks = <&scmi_clk SCMI_CLK_NPU>; + assigned-clock-rates = <200000000>; + resets = <&cru SRST_A_RKNN2>, <&cru SRST_H_RKNN2>; + reset-names = "srst_a", "srst_h"; + power-domains = <&power RK3588_PD_NPU2>; + iommus = <&rknn_mmu_2>; + status = "disabled"; + }; + + rknn_mmu_2: iommu@fdad9000 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdada000 0x0 0x100>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_NPU2>, <&cru HCLK_NPU2>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_NPU2>; + status = "disabled"; + }; + vpu121: video-codec@fdb50000 { compatible = "rockchip,rk3588-vpu121", "rockchip,rk3568-vpu"; reg = <0x0 0xfdb50000 0x0 0x800>; @@ -1472,6 +1573,36 @@ }; }; + dp0: dp@fde50000 { + compatible = "rockchip,rk3588-dp"; + reg = <0x0 0xfde50000 0x0 0x4000>; + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; + assigned-clocks = <&cru CLK_AUX16M_0>; + assigned-clock-rates = <16000000>; + clocks = <&cru PCLK_DP0>, <&cru CLK_AUX16M_0>, + <&cru CLK_DP0>, <&cru MCLK_I2S4_8CH_TX>, + <&cru MCLK_SPDIF2_DP0>; + clock-names = "apb", "aux", "hdcp", "i2s", "spdif"; + phys = <&usbdp_phy0 PHY_TYPE_DP>; + power-domains = <&power RK3588_PD_VO0>; + resets = <&cru SRST_DP0>; + #sound-dai-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dp0_in: port@0 { + reg = <0>; + }; + + dp0_out: port@1 { + reg = <1>; + }; + }; + }; + hdmi0: hdmi@fde80000 { compatible = "rockchip,rk3588-dw-hdmi-qp"; reg = <0x0 0xfde80000 0x0 0x20000>; @@ -3055,6 +3186,30 @@ status = "disabled"; }; + csi_dphy0: phy@fedc0000 { + compatible = "rockchip,rk3588-csi-dphy"; + reg = <0x0 0xfedc0000 0x0 0x8000>; + clocks = <&cru PCLK_CSIPHY0>; + clock-names = "pclk"; + #phy-cells = <0>; + resets = <&cru SRST_P_CSIPHY0>, <&cru SRST_CSIPHY0>; + reset-names = "apb", "phy"; + rockchip,grf = <&csidphy0_grf>; + status = "disabled"; + }; + + csi_dphy1: phy@fedc8000 { + compatible = "rockchip,rk3588-csi-dphy"; + reg = <0x0 0xfedc8000 0x0 0x8000>; + clocks = <&cru PCLK_CSIPHY1>; + clock-names = "pclk"; + #phy-cells = <0>; + resets = <&cru SRST_P_CSIPHY1>, <&cru SRST_CSIPHY1>; + reset-names = "apb", "phy"; + rockchip,grf = <&csidphy1_grf>; + status = "disabled"; + }; + combphy0_ps: phy@fee00000 { compatible = "rockchip,rk3588-naneng-combphy"; reg = <0x0 0xfee00000 0x0 0x100>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi index 90414486e466..6e5a58428bba 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi @@ -210,6 +210,36 @@ status = "disabled"; }; + dp1: dp@fde60000 { + compatible = "rockchip,rk3588-dp"; + reg = <0x0 0xfde60000 0x0 0x4000>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; + assigned-clocks = <&cru CLK_AUX16M_1>; + assigned-clock-rates = <16000000>; + clocks = <&cru PCLK_DP1>, <&cru CLK_AUX16M_1>, + <&cru CLK_DP1>, <&cru MCLK_I2S8_8CH_TX>, + <&cru MCLK_SPDIF5_DP1>; + clock-names = "apb", "aux", "hdcp", "i2s", "spdif"; + phys = <&usbdp_phy1 PHY_TYPE_DP>; + power-domains = <&power RK3588_PD_VO0>; + resets = <&cru SRST_DP1>; + #sound-dai-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dp1_in: port@0 { + reg = <0>; + }; + + dp1_out: port@1 { + reg = <1>; + }; + }; + }; + hdmi1: hdmi@fdea0000 { compatible = "rockchip,rk3588-dw-hdmi-qp"; reg = <0x0 0xfdea0000 0x0 0x20000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi index 3d8b6f0c5541..fafeabe9adf9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi @@ -391,6 +391,17 @@ status = "okay"; }; +&hdmi_receiver_cma { + status = "okay"; +}; + +&hdmi_receiver { + hpd-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>; + pinctrl-names = "default"; + status = "okay"; +}; + &hdptxphy0 { status = "okay"; }; @@ -629,6 +640,12 @@ }; }; + hdmirx { + hdmirx_hpd: hdmirx-5v-detection { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + headphone { hp_det: hp-det { rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; @@ -731,6 +748,7 @@ spi-max-frequency = <104000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <1>; + vcc-supply = <&vcc_1v8_s3>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts index 121e4d1c3fa5..9950d1147e12 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts @@ -77,7 +77,7 @@ pinctrl-names = "default"; pinctrl-0 = <&hp_detect>; simple-audio-card,aux-devs = <&speaker_amp>, <&headphone_amp>; - simple-audio-card,hp-det-gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>; + simple-audio-card,hp-det-gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; simple-audio-card,widgets = "Microphone", "Onboard Microphone", "Microphone", "Microphone Jack", @@ -160,6 +160,17 @@ status = "okay"; }; +&hdmi_receiver_cma { + status = "okay"; +}; + +&hdmi_receiver { + hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>; + pinctrl-names = "default"; + status = "okay"; +}; + &hdptxphy0 { status = "okay"; }; @@ -279,6 +290,12 @@ }; }; + hdmirx { + hdmirx_hpd: hdmirx-5v-detection { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + ir-receiver { ir_receiver_pin: ir-receiver-pin { rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi index 91d56c34a1e4..3bceee948458 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi @@ -258,6 +258,28 @@ }; }; +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + &i2c6 { clock-frequency = <400000>; status = "okay"; @@ -352,6 +374,40 @@ domain-supply = <&vdd_gpu_s0>; }; +&pd_npu { + domain-supply = <&vdd_npu_s0>; +}; + +&rknn_core_0 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_1 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_2 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_mmu_0 { + status = "okay"; +}; + +&rknn_mmu_1 { + status = "okay"; +}; + +&rknn_mmu_2 { + status = "okay"; +}; + &saradc { vref-supply = <&vcc_1v8_s0>; status = "okay"; @@ -365,6 +421,8 @@ max-frequency = <200000000>; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vcc_1v8_s3>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts index 78aaa6635b5d..b2336c36da01 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts @@ -415,6 +415,36 @@ status = "okay"; }; +&rknn_core_0 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknn_core_1 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknn_core_2 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknn_mmu_0 { + status = "okay"; +}; + +&rknn_mmu_1 { + status = "okay"; +}; + +&rknn_mmu_2 { + status = "okay"; +}; + &saradc { vref-supply = <&vcc_1v8_s0>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-roc-rt.dts b/arch/arm64/boot/dts/rockchip/rk3588-roc-rt.dts new file mode 100644 index 000000000000..2d6fed2a84a3 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-roc-rt.dts @@ -0,0 +1,1132 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Firefly Technology Co. Ltd + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include <dt-bindings/usb/pd.h> +#include "rk3588.dtsi" + +/ { + model = "Firefly ROC-RK3588-RT"; + compatible = "firefly,roc-rk3588-rt", "rockchip,rk3588"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + adc-keys-0 { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-recovery { + label = "Recovery"; + linux,code = <KEY_VENDOR>; + press-threshold-microvolt = <17000>; + }; + }; + + analog-sound { + compatible = "simple-audio-card"; + pinctrl-0 = <&hp_detect>; + pinctrl-names = "default"; + simple-audio-card,aux-devs = <&_headphones>; + simple-audio-card,format = "i2s"; + simple-audio-card,hp-det-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + simple-audio-card,mclk-fs = <384>; + simple-audio-card,name = "rockchip-es8388"; + simple-audio-card,pin-switches = "Headphones"; + simple-audio-card,routing = + "Speaker", "LOUT2", + "Speaker", "ROUT2", + "Headphones Amplifier INL", "LOUT1", + "Headphones Amplifier INR", "ROUT1", + "Headphones", "Headphones Amplifier OUTL", + "Headphones", "Headphones Amplifier OUTR", + "LINPUT1", "Microphone Jack", + "RINPUT1", "Microphone Jack", + "LINPUT2", "Onboard Microphone", + "RINPUT2", "Onboard Microphone"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Microphone", "Onboard Microphone", + "Headphone", "Headphones", + "Speaker", "Speaker"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&es8388>; + system-clock-frequency = <12288000>; + }; + }; + + amp_headphones: headphones-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&headphone_amplifier_en>; + sound-name-prefix = "Headphones Amplifier"; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 70 75 80 100>; + #cooling-cells = <2>; + fan-supply = <&vcc5v0_sys>; + pwms = <&pwm15 0 50000 1>; + }; + + hdmi0-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi0_con_in: endpoint { + remote-endpoint = <&hdmi0_out_con>; + }; + }; + }; + + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + power_led { + gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + user_led { + gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "disk-activity"; + }; + }; + + vbus5v0_typec: regulator-vbus5v0-typec { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc12v_dcin: regulator-vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-name = "vcc12v_dcin"; + }; + + vcc3v3_sata2: vcc3v3-sata2 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc3v3_sata2"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sd_s0: regulator-vcc3v3-sd-s0 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc3v3_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc3v3_sys: regulator-vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_wlan: regulator-vcc3v3-wlan { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_pwren>; + regulator-name = "vcc3v3_wlan"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: regulator-vcc5v0-host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host3: regulator-vcc5v0-host3 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host3_en>; + regulator-name = "vcc5v0_host3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac0 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + status = "okay"; +}; + +&gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + sram-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint = <&hdmi0_con_in>; + }; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdmi1 { + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + /* pc9202 watchdog@3c with enable-gpio gpio0-c3 */ + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + fcs,suspend-voltage-selector = <1>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + fcs,suspend-voltage-selector = <1>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + status = "okay"; + + es8388: audio-codec@11 { + compatible = "everest,es8388", "everest,es8328"; + reg = <0x11>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + AVDD-supply = <&vcc_1v8_s0>; + DVDD-supply = <&vcc_1v8_s0>; + HPVDD-supply = <&vcc_3v3_s0>; + PVDD-supply = <&vcc_1v8_s0>; + #sound-dai-cells = <0>; + }; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + + usbc0: usb-typec@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + op-sink-microwatt = <1000000>; + power-role = "dual"; + sink-pdos = + <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>; + source-pdos = + <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + try-power-role = "source"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + + usbc0_role_sw: endpoint { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + + port@2 { + reg = <2>; + + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&i2s0_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8211f_0_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8211f_1_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie2x1l0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_0_rst>, <&pcie2_0_wake>, <&pcie2_0_clkreq>; + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_wlan>; + status = "okay"; +}; + +&pcie2x1l2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_2_rst>; + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + +&pinctrl { + audio { + hp_detect: headphone-detect { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + headphone_amplifier_en: headphone-amplifier-en { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gpio-leds { + led_pins: led-pins { + rockchip,pins = + <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcie2 { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_0_wake: pcie2-0-wake { + rockchip,pins = <4 RK_PA4 4 &pcfg_pull_none>; + }; + + pcie2_0_clkreq: pcie2-0-clkreq { + rockchip,pins = <4 RK_PA3 4 &pcfg_pull_none>; + }; + + pcie2_2_rst: pcie2-2-rst { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtl8211f { + rtl8211f_0_rst: rtl8211f-0-rst { + rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + rtl8211f_1_rst: rtl8211f-1-rst { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_host3_en: vcc5v0-host3-en { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + typec5v_pwren: typec5v-pwren { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wlan { + wifi_pwren: wifi-pwren { + rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm15 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm15m2_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sdio; + no-sd; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd_s0>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name = "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name = "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-name = "avcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-name = "avdd_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + avdd_ddr_pll_s0: nldo-reg2 { + regulator-name = "avdd_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-name = "avdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_0v85_s0: nldo-reg4 { + regulator-name = "avdd_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&sata2 { + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host3>; + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host3>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "otg"; + usb-role-switch; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&usbdp_phy0 { + mode-switch; + orientation-switch; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <2 3>; + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi0_in_vp0>; + }; +}; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = <ROCKCHIP_VOP2_EP_HDMI1>; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts index 7de17117df7a..bc8140883de4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts @@ -57,6 +57,31 @@ "Headphone", "Headphones"; }; + bridge { + compatible = "radxa,ra620"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_bridge_in: endpoint { + remote-endpoint = <&dp1_out_con>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_bridge_out: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; + }; + }; + }; + gpio-leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -73,6 +98,17 @@ }; }; + hdmi0-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_bridge_out>; + }; + }; + }; + hdmi1-con { compatible = "hdmi-connector"; type = "a"; @@ -268,6 +304,24 @@ cpu-supply = <&vdd_cpu_lit_s0>; }; +&dp1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dp1m0_pins>; +}; + +&dp1_in { + dp1_in_vp2: endpoint { + remote-endpoint = <&vp2_out_dp1>; + }; +}; + +&dp1_out { + dp1_out_con: endpoint { + remote-endpoint = <&hdmi_bridge_in>; + }; +}; + &gpu { mali-supply = <&vdd_gpu_s0>; status = "okay"; @@ -1261,3 +1315,10 @@ remote-endpoint = <&hdmi1_in_vp1>; }; }; + +&vp2 { + vp2_out_dp1: endpoint@b { + reg = <ROCKCHIP_VOP2_EP_DP1>; + remote-endpoint = <&dp1_in_vp2>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi index 973d39a7e0e0..3bbe78810ec6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi @@ -5,6 +5,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/leds/common.h> #include <dt-bindings/soc/rockchip,vop2.h> +#include <dt-bindings/usb/pd.h> #include "rk3588.dtsi" / { @@ -55,6 +56,18 @@ shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; }; + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vbus5v0_typec_en>; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 { compatible = "regulator-fixed"; enable-active-high; @@ -268,6 +281,99 @@ }; }; +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-boot-on; + regulator-enable-ramp-delay = <500>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + status = "okay"; + + usbc0: usb-typec@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + /* + * When the board is starting to send power-delivery messages + * too late (5 seconds according to the specification), the + * power-supply reacts with a hard-reset. That removes the + * power from VBUS for some time, which resets te whole board. + */ + status = "fail"; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + /* fusb302 supports PD Rev 2.0 Ver 1.2 */ + pd-revision = /bits/ 8 <0x2 0x0 0x1 0x2>; + power-role = "sink"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>, + <PDO_VAR(5000, 20000, 5000)>; + + altmodes { + displayport { + svid = /bits/ 16 <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_hs: endpoint { + remote-endpoint = <&usb_host0_xhci_to_usbc0>; + }; + }; + + port@1 { + reg = <1>; + usbc0_ss: endpoint { + remote-endpoint = <&usbdp_phy0_ss>; + }; + }; + + port@2 { + reg = <2>; + usbc0_sbu: endpoint { + remote-endpoint = <&usbdp_phy0_sbu>; + }; + }; + }; + }; + }; +}; + &i2c6 { status = "okay"; @@ -392,6 +498,10 @@ domain-supply = <&vdd_gpu_s0>; }; +&pd_npu { + domain-supply = <&vdd_npu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { @@ -418,12 +528,52 @@ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + usb { + usbc0_int: usbc0-int { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vbus5v0_typec_en: vbus5v0-typec-en { + rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pwm1 { status = "okay"; }; +&rknn_core_0 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_1 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_2 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_mmu_0 { + status = "okay"; +}; + +&rknn_mmu_1 { + status = "okay"; +}; + +&rknn_mmu_2 { + status = "okay"; +}; + &saradc { vref-supply = <&avcc_1v8_s0>; status = "okay"; @@ -803,6 +953,14 @@ status = "okay"; }; +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + &u2phy1 { status = "okay"; }; @@ -830,6 +988,27 @@ status = "okay"; }; +&usbdp_phy0 { + mode-switch; + orientation-switch; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy0_ss: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_ss>; + }; + + usbdp_phy0_sbu: endpoint@1 { + reg = <1>; + remote-endpoint = <&usbc0_sbu>; + }; + }; +}; + &usbdp_phy1 { status = "okay"; }; @@ -842,6 +1021,17 @@ status = "okay"; }; +&usb_host0_xhci { + usb-role-switch; + status = "okay"; + + port { + usb_host0_xhci_to_usbc0: endpoint { + remote-endpoint = <&usbc0_hs>; + }; + }; +}; + &usb_host1_ehci { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts index 74c7b6502e4d..5e984a44120e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts @@ -99,12 +99,24 @@ }; usb { + usbc_sbu_dc: usbc-sbu-dc { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc5v0_host_en: vcc5v0-host-en { rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; +&usbdp_phy0 { + pinctrl-names = "default"; + pinctrl-0 = <&usbc_sbu_dc>; + sbu1-dc-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; +}; + &vcc5v0_host { enable-active-high; gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index 9407a7c9910a..8ef01010d985 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -38,12 +38,24 @@ &pinctrl { usb { + usbc_sbu_dc: usbc-sbu-dc { + rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, + <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc5v0_host_en: vcc5v0-host-en { rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; +&usbdp_phy0 { + pinctrl-names = "default"; + pinctrl-0 = <&usbc_sbu_dc>; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; +}; + &vcc5v0_host { enable-active-high; gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts index 258c7400301d..c1763835f53d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts @@ -68,6 +68,22 @@ status = "okay"; }; +&pcie30phy { + data-lanes = <1 1 2 2>; +}; + +&pcie3x2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie3x2_rst>; + reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pcie3x4 { + num-lanes = <2>; +}; + &pinctrl { hdmirx { hdmirx_hpd: hdmirx-5v-detection { @@ -90,11 +106,35 @@ }; }; + pcie3 { + pcie3x2_rst: pcie3x2-rst { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + sound { hp_detect: hp-detect { rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbc_sbu_dc: usbc-sbu-dc { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&usbdp_phy0 { + pinctrl-names = "default"; + pinctrl-0 = <&usbc_sbu_dc>; + sbu1-dc-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; }; &vcc3v3_pcie2x1l0 { @@ -103,3 +143,10 @@ pinctrl-0 = <&pcie2_0_vcc3v3_en>; status = "okay"; }; + +&vcc5v0_host { + enable-active-high; + gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi index 3045cb3bd68c..9884a5df47df 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi @@ -28,7 +28,7 @@ compatible = "operating-points-v2"; opp-shared; - opp-1200000000{ + opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <750000 750000 950000>; clock-latency-ns = <40000>; @@ -49,7 +49,7 @@ compatible = "operating-points-v2"; opp-shared; - opp-1200000000{ + opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <750000 750000 950000>; clock-latency-ns = <40000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts index b2947b36fada..189444d20779 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts @@ -39,6 +39,18 @@ stdout-path = "serial2:1500000n8"; }; + dp-con { + compatible = "dp-connector"; + label = "DP OUT"; + type = "mini"; + + port { + dp_con_in: endpoint { + remote-endpoint = <&dp0_out_con>; + }; + }; + }; + hdmi-con { compatible = "hdmi-connector"; type = "d"; @@ -215,6 +227,24 @@ cpu-supply = <&vdd_cpu_big1_s0>; }; +&dp0 { + pinctrl-0 = <&dp0m0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&dp0_in { + dp0_in_vp2: endpoint { + remote-endpoint = <&vp2_out_dp0>; + }; +}; + +&dp0_out { + dp0_out_con: endpoint { + remote-endpoint = <&dp_con_in>; + }; +}; + &gpu { mali-supply = <&vdd_gpu_s0>; status = "okay"; @@ -890,3 +920,10 @@ remote-endpoint = <&hdmi0_in_vp0>; }; }; + +&vp2 { + vp2_out_dp0: endpoint@a { + reg = <ROCKCHIP_VOP2_EP_DP0>; + remote-endpoint = <&dp0_in_vp2>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts b/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts index 55fc7cbef58d..f5894672fcbd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts @@ -612,6 +612,56 @@ pinctrl-0 = <&i2c6m3_xfer>; status = "okay"; + fusb302: typec@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PC7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&usbc0_int>; + pinctrl-names = "default"; + vbus-supply = <&usb_otg_vbus>; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <1000000>; + power-role = "dual"; + self-powered; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_FIXED(9000, 3000, PDO_FIXED_USB_COMM) + PDO_FIXED(12000, 3000, PDO_FIXED_USB_COMM)>; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + usbc0_role_sw: endpoint { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + + port@2 { + reg = <2>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + rtc_hym8563: rtc@51 { compatible = "haoyu,hym8563"; reg = <0x51>; @@ -640,8 +690,34 @@ 0x2F 0x00 0x64 0xA5 0xB5 0x1C 0xF0 0x49>; cellwise,monitor-interval-ms = <5000>; monitored-battery = <&battery>; + power-supplies = <&bq25703>; status = "okay"; }; + + bq25703: charger@6b { + compatible = "ti,bq25703a"; + reg = <0x6b>; + input-current-limit-microamp = <5000000>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PD5 IRQ_TYPE_LEVEL_LOW>; + monitored-battery = <&battery>; + pinctrl-0 = <&charger_int_h>; + pinctrl-names = "default"; + power-supplies = <&fusb302>; + + regulators { + usb_otg_vbus: vbus { + enable-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&boost_enable_h>; + pinctrl-names = "default"; + regulator-max-microamp = <960000>; + regulator-max-microvolt = <5088000>; + regulator-min-microamp = <512000>; + regulator-min-microvolt = <4992000>; + regulator-name = "usb_otg_vbus"; + }; + }; + }; }; &i2c7 { @@ -853,6 +929,12 @@ rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; }; + + usbc_sbu_dc: usbc-sbu-dc { + rockchip,pins = + <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, + <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; }; vcc3v3-lcd { @@ -1286,6 +1368,46 @@ }; }; +&usb_host0_xhci { + usb-role-switch; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdp_phy0 { + mode-switch; + orientation-switch; + pinctrl-0 = <&usbc_sbu_dc>; + pinctrl-names = "default"; + sbu1-dc-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; + rockchip,dp-lane-mux = <2 3>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + &vop { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi index fbf062ec3bf1..1b6a59f7cabc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi @@ -251,6 +251,10 @@ }; }; +&hdmi0_sound { + status = "okay"; +}; + &hdptxphy0 { status = "okay"; }; @@ -335,6 +339,10 @@ }; }; +&i2s5_8ch { + status = "okay"; +}; + &mdio1 { rgmii_phy1: ethernet-phy@1 { compatible = "ethernet-phy-id001c.c916"; @@ -363,6 +371,10 @@ domain-supply = <&vdd_gpu_s0>; }; +&pd_npu { + domain-supply = <&vdd_npu_s0>; +}; + &pinctrl { gpio-key { key1_pin: key1-pin { @@ -421,6 +433,36 @@ }; }; +&rknn_core_0 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_1 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_2 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_mmu_0 { + status = "okay"; +}; + +&rknn_mmu_1 { + status = "okay"; +}; + +&rknn_mmu_2 { + status = "okay"; +}; + &saradc { vref-supply = <&avcc_1v8_s0>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi index 4fedc50cce8c..dafad29f9854 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi @@ -42,9 +42,8 @@ simple-audio-card,bitclock-master = <&masterdai>; simple-audio-card,format = "i2s"; simple-audio-card,frame-master = <&masterdai>; - simple-audio-card,hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + simple-audio-card,hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; simple-audio-card,mclk-fs = <256>; - simple-audio-card,pin-switches = "Headphones"; simple-audio-card,routing = "Headphones", "LOUT1", "Headphones", "ROUT1", @@ -377,6 +376,10 @@ domain-supply = <&vdd_gpu_s0>; }; +&pd_npu { + domain-supply = <&vdd_npu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { @@ -407,6 +410,36 @@ status = "okay"; }; +&rknn_core_0 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_1 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_2 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_mmu_0 { + status = "okay"; +}; + +&rknn_mmu_1 { + status = "okay"; +}; + +&rknn_mmu_2 { + status = "okay"; +}; + &saradc { vref-supply = <&avcc_1v8_s0>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts index 7434ac39246f..7e179862da6e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts @@ -320,9 +320,9 @@ &i2c3 { status = "okay"; - es8388: audio-codec@10 { + es8388: audio-codec@11 { compatible = "everest,es8388", "everest,es8328"; - reg = <0x10>; + reg = <0x11>; clocks = <&cru I2S1_8CH_MCLKOUT>; AVDD-supply = <&vcc_3v3_s0>; DVDD-supply = <&vcc_1v8_s0>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts index f894742b1ebe..19a08f7794e6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts @@ -58,6 +58,13 @@ gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; + + power-led { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_POWER; + gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; }; fan: pwm-fan { diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts b/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts index de219570bbc9..fc105d420db4 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts @@ -68,7 +68,7 @@ compatible = "linux,spdif-dit"; #sound-dai-cells = <0>; - port@0 { + port { spdif_tx: endpoint { remote-endpoint = <&spdif_hiecout1>; }; @@ -79,7 +79,7 @@ compatible = "linux,spdif-dit"; #sound-dai-cells = <0>; - port@0 { + port { comp_spdif_tx: endpoint { remote-endpoint = <&comp_spdif_hiecout1>; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts index fba454adae7d..10efa747ed8b 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts @@ -74,7 +74,7 @@ compatible = "linux,spdif-dit"; #sound-dai-cells = <0>; - port@0 { + port { spdif_tx: endpoint { remote-endpoint = <&spdif_hiecout1>; }; @@ -85,7 +85,7 @@ compatible = "linux,spdif-dit"; #sound-dai-cells = <0>; - port@0 { + port { comp_spdif_tx: endpoint { remote-endpoint = <&comp_spdif_hiecout1>; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts index 20e5fb724fae..3c4dcfb82ddf 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts @@ -68,7 +68,7 @@ compatible = "linux,spdif-dit"; #sound-dai-cells = <0>; - port@0 { + port { spdif_tx: endpoint { remote-endpoint = <&spdif_hiecout1>; }; @@ -79,7 +79,7 @@ compatible = "linux,spdif-dit"; #sound-dai-cells = <0>; - port@0 { + port { comp_spdif_tx: endpoint { remote-endpoint = <&comp_spdif_hiecout1>; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index 335093da6573..875b93856a64 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -947,6 +947,7 @@ pcie_intc: legacy-interrupt-controller { interrupt-controller; + #address-cells = <0>; #interrupt-cells = <1>; interrupt-parent = <&gic>; interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi index d6e3cc6fdb25..4d6c3c2dbea6 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi @@ -921,6 +921,7 @@ pcie_intc: legacy-interrupt-controller { interrupt-controller; + #address-cells = <0>; #interrupt-cells = <1>; interrupt-parent = <&gic>; interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/st/stm32mp231.dtsi index 75697acd1345..88e214d395ab 100644 --- a/arch/arm64/boot/dts/st/stm32mp231.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi @@ -1064,28 +1064,6 @@ st,bank-name = "GPIOI"; status = "disabled"; }; - - gpioj: gpio@442d0000 { - reg = <0x90000 0x400>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&scmi_clk CK_SCMI_GPIOJ>; - st,bank-name = "GPIOJ"; - status = "disabled"; - }; - - gpiok: gpio@442e0000 { - reg = <0xa0000 0x400>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&scmi_clk CK_SCMI_GPIOK>; - st,bank-name = "GPIOK"; - status = "disabled"; - }; }; rtc: rtc@46000000 { diff --git a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts index 04d1b434c433..c3e688068223 100644 --- a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts @@ -19,6 +19,7 @@ compatible = "st,stm32mp235f-dk", "st,stm32mp235"; aliases { + ethernet0 = ðernet1; serial0 = &usart2; }; @@ -56,7 +57,7 @@ memory@80000000 { device_type = "memory"; - reg = <0x0 0x80000000 0x1 0x0>; + reg = <0x0 0x80000000 0x0 0x80000000>; }; reserved-memory { @@ -77,6 +78,28 @@ status = "okay"; }; +ðernet1 { + pinctrl-0 = <ð1_rgmii_pins_b>; + pinctrl-1 = <ð1_rgmii_sleep_pins_b>; + pinctrl-names = "default", "sleep"; + phy-handle = <&phy1_eth1>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy1_eth1: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <1>; + reset-gpios = <&gpioa 2 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + }; + }; +}; + &scmi_regu { scmi_vddio1: regulator@0 { regulator-min-microvolt = <1800000>; diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi index 5ac9e72478dd..e0d102eb6176 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -6,6 +6,132 @@ #include <dt-bindings/pinctrl/stm32-pinfunc.h> &pinctrl { + eth1_mdio_pins_a: eth1-mdio-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 0, AF10)>; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = <STM32_PINMUX('F', 2, AF10)>; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + eth1_mdio_sleep_pins_a: eth1-mdio-sleep-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* ETH_MDC */ + <STM32_PINMUX('F', 2, ANALOG)>; /* ETH_MDIO */ + }; + }; + + eth1_rgmii_pins_a: eth1-rgmii-0 { + pins1 { + pinmux = <STM32_PINMUX('A', 15, AF10)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('C', 1, AF10)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('H', 10, AF10)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('H', 11, AF10)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('A', 13, AF10)>; /* ETH_RGMII_TX_CTL */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins2 { + pinmux = <STM32_PINMUX('H', 9, AF10)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('C', 0, AF12)>; /* ETH_RGMII_GTX_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins3 { + pinmux = <STM32_PINMUX('F', 1, AF10)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 2, AF10)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('H', 12, AF10)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('H', 13, AF10)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 11, AF10)>; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + pins4 { + pinmux = <STM32_PINMUX('A', 14, AF10)>; /* ETH_RGMII_RX_CLK */ + bias-disable; + }; + }; + + eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A', 15, ANALOG)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('H', 10, ANALOG)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('H', 11, ANALOG)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('A', 13, ANALOG)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('H', 9, ANALOG)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('C', 0, ANALOG)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('F', 1, ANALOG)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('H', 12, ANALOG)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('H', 13, ANALOG)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 11, ANALOG)>, /* ETH_RGMII_RX_CTL */ + <STM32_PINMUX('A', 14, ANALOG)>; /* ETH_RGMII_RX_CLK */ + }; + }; + + eth1_rgmii_pins_b: eth1-rgmii-1 { + pins1 { + pinmux = <STM32_PINMUX('A', 15, AF10)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('C', 1, AF10)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('H', 10, AF10)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('H', 11, AF10)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('A', 13, AF10)>; /* ETH_RGMII_TX_CTL */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins2 { + pinmux = <STM32_PINMUX('H', 9, AF10)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('C', 0, AF12)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('A', 9, AF10)>, /* ETH_MDC */ + <STM32_PINMUX('A', 10, AF10)>; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins3 { + pinmux = <STM32_PINMUX('F', 1, AF10)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 2, AF10)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('H', 12, AF10)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('H', 13, AF10)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 11, AF10)>; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + pins4 { + pinmux = <STM32_PINMUX('A', 14, AF10)>; /* ETH_RGMII_RX_CLK */ + bias-disable; + }; + }; + + eth1_rgmii_sleep_pins_b: eth1-rgmii-sleep-1 { + pins { + pinmux = <STM32_PINMUX('A', 15, ANALOG)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('H', 10, ANALOG)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('H', 11, ANALOG)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('A', 13, ANALOG)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('H', 9, ANALOG)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('C', 0, ANALOG)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('A', 9, ANALOG)>, /* ETH_MDC */ + <STM32_PINMUX('A', 10, ANALOG)>, /* ETH_MDIO */ + <STM32_PINMUX('F', 1, ANALOG)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('H', 12, ANALOG)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('H', 13, ANALOG)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 11, ANALOG)>, /* ETH_RGMII_RX_CTL */ + <STM32_PINMUX('A', 14, AF10)>; /* ETH_RGMII_RX_CLK */ + }; + }; + eth2_rgmii_pins_a: eth2-rgmii-0 { pins1 { pinmux = <STM32_PINMUX('C', 7, AF10)>, /* ETH_RGMII_TXD0 */ @@ -133,6 +259,26 @@ }; }; + pcie_pins_a: pcie-0 { + pins { + pinmux = <STM32_PINMUX('J', 0, AF4)>; + bias-disable; + }; + }; + + pcie_init_pins_a: pcie-init-0 { + pins { + pinmux = <STM32_PINMUX('J', 0, GPIO)>; + output-low; + }; + }; + + pcie_sleep_pins_a: pcie-sleep-0 { + pins { + pinmux = <STM32_PINMUX('J', 0, ANALOG)>; + }; + }; + pwm3_pins_a: pwm3-0 { pins { pinmux = <STM32_PINMUX('B', 15, AF7)>; /* TIM3_CH2 */ diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 303abf915b8e..a8e6e0f77b83 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -52,6 +52,12 @@ compatible = "fixed-clock"; clock-frequency = <64000000>; }; + + clk_flexgen_27_fixed: clk-54000000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <54000000>; + }; }; firmware { @@ -122,6 +128,15 @@ <0x0 0x4ac20000 0x0 0x20000>, <0x0 0x4ac40000 0x0 0x20000>, <0x0 0x4ac60000 0x0 0x20000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + v2m0: v2m@48090000 { + compatible = "arm,gic-v2m-frame"; + reg = <0x0 0x48090000 0x0 0x1000>; + msi-controller; + }; }; psci { @@ -1553,6 +1568,18 @@ }; }; + ltdc: display-controller@48010000 { + compatible = "st,stm32mp251-ltdc"; + reg = <0x48010000 0x400>; + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_LTDC>, <&rcc CK_BUS_LTDC>; + clock-names = "lcd", "bus"; + resets = <&rcc LTDC_R>; + access-controllers = <&rifsc 80>; + status = "disabled"; + }; + csi: csi@48020000 { compatible = "st,stm32mp25-csi"; reg = <0x48020000 0x2000>; @@ -1654,6 +1681,56 @@ snps,wr_osr_lmt = <0x7>; }; }; + + pcie_ep: pcie-ep@48400000 { + compatible = "st,stm32mp25-pcie-ep"; + reg = <0x48400000 0x100000>, + <0x48500000 0x100000>, + <0x48700000 0x80000>, + <0x10000000 0x10000000>; + reg-names = "dbi", "dbi2", "atu", "addr_space"; + clocks = <&rcc CK_BUS_PCIE>; + resets = <&rcc PCIE_R>; + phys = <&combophy PHY_TYPE_PCIE>; + access-controllers = <&rifsc 68>; + power-domains = <&CLUSTER_PD>; + status = "disabled"; + }; + + pcie_rc: pcie@48400000 { + compatible = "st,stm32mp25-pcie-rc"; + device_type = "pci"; + reg = <0x48400000 0x400000>, + <0x10000000 0x10000>; + reg-names = "dbi", "config"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x10010000 0x0 0x10000>, + <0x02000000 0x0 0x10020000 0x10020000 0x0 0x7fe0000>, + <0x42000000 0x0 0x18000000 0x18000000 0x0 0x8000000>; + dma-ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x80000000>; + clocks = <&rcc CK_BUS_PCIE>; + resets = <&rcc PCIE_R>; + msi-parent = <&v2m0>; + access-controllers = <&rifsc 68>; + power-domains = <&CLUSTER_PD>; + status = "disabled"; + + pcie@0,0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + phys = <&combophy PHY_TYPE_PCIE>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; }; bsec: efuse@44000000 { @@ -1672,6 +1749,13 @@ }; }; + hdp: pinctrl@44090000 { + compatible = "st,stm32mp251-hdp"; + reg = <0x44090000 0x400>; + clocks = <&rcc CK_BUS_HDP>; + status = "disabled"; + }; + rcc: clock-controller@44200000 { compatible = "st,stm32mp25-rcc"; reg = <0x44200000 0x10000>; @@ -1856,6 +1940,7 @@ syscfg: syscon@44230000 { compatible = "st,stm32mp25-syscfg", "syscon"; reg = <0x44230000 0x10000>; + #clock-cells = <0>; }; pinctrl: pinctrl@44240000 { diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/st/stm32mp255.dtsi index f689b47c5010..7a598f53a2a0 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -5,7 +5,25 @@ */ #include "stm32mp253.dtsi" +<dc { + compatible = "st,stm32mp255-ltdc"; + clocks = <&clk_flexgen_27_fixed>, <&rcc CK_BUS_LTDC>, <&syscfg>, <&lvds>; + clock-names = "lcd", "bus", "ref", "lvds"; +}; + &rifsc { + lvds: lvds@48060000 { + compatible = "st,stm32mp255-lvds", "st,stm32mp25-lvds"; + reg = <0x48060000 0x2000>; + #clock-cells = <0>; + clocks = <&rcc CK_BUS_LVDS>, <&rcc CK_KER_LVDSPHY>; + clock-names = "pclk", "ref"; + resets = <&rcc LVDS_R>; + access-controllers = <&rifsc 84>; + power-domains = <&CLUSTER_PD>; + status = "disabled"; + }; + vdec: vdec@480d0000 { compatible = "st,stm32mp25-vdec"; reg = <0x480d0000 0x3c8>; diff --git a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts index a278a1e3ce03..e718d888ce21 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts @@ -19,6 +19,7 @@ compatible = "st,stm32mp257f-dk", "st,stm32mp257"; aliases { + ethernet0 = ðernet1; serial0 = &usart2; }; @@ -77,6 +78,28 @@ status = "okay"; }; +ðernet1 { + pinctrl-0 = <ð1_rgmii_pins_b>; + pinctrl-1 = <ð1_rgmii_sleep_pins_b>; + pinctrl-names = "default", "sleep"; + phy-handle = <&phy1_eth1>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy1_eth1: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <1>; + reset-gpios = <&gpioa 2 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + }; + }; +}; + &scmi_regu { scmi_vddio1: regulator@0 { regulator-min-microvolt = <1800000>; diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts index 836b1958ce65..6e165073f732 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -19,6 +19,7 @@ aliases { ethernet0 = ðernet2; + ethernet1 = ðernet1; serial0 = &usart2; serial1 = &usart6; }; @@ -70,6 +71,42 @@ reg = <0x0 0x80000000 0x1 0x0>; }; + panel_lvds: display { + compatible = "edt,etml0700z9ndha", "panel-lvds"; + enable-gpios = <&gpiog 15 GPIO_ACTIVE_HIGH>; + backlight = <&panel_lvds_backlight>; + power-supply = <&scmi_v3v3>; + width-mm = <156>; + height-mm = <92>; + data-mapping = "vesa-24"; + status = "okay"; + + panel-timing { + clock-frequency = <54000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <150>; + hback-porch = <150>; + hsync-len = <21>; + vfront-porch = <24>; + vback-porch = <24>; + vsync-len = <21>; + }; + + port { + lvds_panel_in: endpoint { + remote-endpoint = <&lvds_out0>; + }; + }; + }; + + panel_lvds_backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; + default-on; + status = "okay"; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -100,7 +137,7 @@ }; &csi { - vdd-supply = <&scmi_vddcore>; + vdd-supply = <&scmi_vddcore>; vdda18-supply = <&scmi_v1v8>; status = "okay"; ports { @@ -133,6 +170,29 @@ }; }; +ðernet1 { + pinctrl-0 = <ð1_rgmii_pins_a ð1_mdio_pins_a>; + pinctrl-1 = <ð1_rgmii_sleep_pins_a ð1_mdio_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-handle = <&phy1_eth1>; + phy-mode = "rgmii-id"; + st,ext-phyclk; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy1_eth1: ethernet-phy@4 { + compatible = "ethernet-phy-id001c.c916"; + reg = <4>; + reset-gpios = <&gpioj 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + }; + }; +}; + ðernet2 { pinctrl-names = "default", "sleep"; pinctrl-0 = <ð2_rgmii_pins_a>; @@ -151,7 +211,7 @@ reg = <1>; reset-assert-us = <10000>; reset-deassert-us = <300>; - reset-gpios = <&gpiog 6 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpiog 6 GPIO_ACTIVE_LOW>; }; }; }; @@ -183,6 +243,15 @@ }; }; }; + + ili2511: ili2511@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + interrupt-parent = <&gpioi>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpiog 14 GPIO_ACTIVE_LOW>; + status = "okay"; + }; }; &i2c8 { @@ -230,6 +299,58 @@ }; }; +<dc { + status = "okay"; + port { + ltdc_ep0_out: endpoint { + remote-endpoint = <&lvds_in>; + }; + }; +}; + +&lvds { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + + port@1 { + reg = <1>; + lvds_out0: endpoint { + remote-endpoint = <&lvds_panel_in>; + }; + }; + }; +}; + +&pcie_ep { + pinctrl-names = "default", "init"; + pinctrl-0 = <&pcie_pins_a>; + pinctrl-1 = <&pcie_init_pins_a>; + reset-gpios = <&gpioj 8 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +&pcie_rc { + pinctrl-names = "default", "init", "sleep"; + pinctrl-0 = <&pcie_pins_a>; + pinctrl-1 = <&pcie_init_pins_a>; + pinctrl-2 = <&pcie_sleep_pins_a>; + status = "okay"; + + pcie@0,0 { + reset-gpios = <&gpioj 8 GPIO_ACTIVE_LOW>; + wake-gpios = <&gpioh 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; +}; + &rtc { status = "okay"; }; diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index a5ebb3f9b18f..5b06e2667b89 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -363,6 +363,7 @@ gic: interrupt-controller@10400000 { compatible = "arm,gic-v3"; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x10400000 0x0 0x10000>, /* GICD */ diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index aad9177930e6..743115b849a7 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -28,6 +28,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62x-phyboard-lyra-gpio-fan.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk-nand.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am62-pocketbeagle2.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am6254atl-sk.dtb # Boards with AM62Ax SoC dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb @@ -38,6 +39,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62d2-evm.dtb # Boards with AM62Px SoC dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-var-som-symphony.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-dev.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-ivy.dtb @@ -69,6 +71,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-gpio-fan.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-pcie-usb2.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-peb-c-010.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl.dtb dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo @@ -131,6 +134,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-gesi-exp-board.dtbo k3-j721s2-evm-dtbs := k3-j721s2-common-proc-board.dtb k3-j721s2-evm-gesi-exp-board.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-pcie1-ep.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-usb0-type-a.dtbo # Boards with J722s SoC dtb-$(CONFIG_ARCH_K3) += k3-am67a-beagley-ai.dtb @@ -206,6 +210,8 @@ k3-am642-phyboard-electra-pcie-usb2-dtbs := \ k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-pcie-usb2.dtbo k3-am642-phyboard-electra-x27-gpio1-spi1-uart3-dtbs := \ k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtbo +k3-am642-phyboard-electra-peb-c-010-dtbs := \ + k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-peb-c-010.dtbo k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs := \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs := \ @@ -230,6 +236,8 @@ k3-j721e-sk-csi2-dual-imx219-dtbs := k3-j721e-sk.dtb \ k3-j721e-sk-csi2-dual-imx219.dtbo k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \ k3-j721s2-evm-pcie1-ep.dtbo +k3-j721s2-evm-usb0-type-a-dtbs := k3-j721s2-common-proc-board.dtb \ + k3-j721s2-evm-usb0-type-a.dtbo k3-j722s-evm-csi2-quad-rpi-cam-imx219-dtbs := k3-j722s-evm.dtb \ k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo k3-j722s-evm-csi2-quad-tevi-ov5640-dtbs := k3-j722s-evm.dtb \ @@ -272,6 +280,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-j721e-evm-pcie1-ep.dtb \ k3-j721e-sk-csi2-dual-imx219.dtb \ k3-j721s2-evm-pcie1-ep.dtb \ + k3-j721s2-evm-usb0-type-a.dtb \ k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtb \ k3-j722s-evm-csi2-quad-tevi-ov5640.dtb \ k3-j742s2-evm-usb0-type-a.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts index 4609f366006e..ecfba05fe5c2 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts @@ -7,12 +7,20 @@ /dts-v1/; +#include "k3-am625.dtsi" #include "k3-am62x-sk-common.dtsi" / { compatible = "ti,am62-lp-sk", "ti,am625"; model = "Texas Instruments AM62x LP SK"; + memory@80000000 { + /* 2G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + device_type = "memory"; + bootph-pre-ram; + }; + vmain_pd: regulator-0 { /* TPS65988 PD CONTROLLER OUTPUT */ compatible = "regulator-fixed"; diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index 120ba8f9dd0e..40fb3c9e674c 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -808,6 +808,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; ecap0: pwm@23100000 { @@ -1031,6 +1032,9 @@ cdns_csi2rx0: csi-bridge@30101000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x30101000 0x00 0x1000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi index 10e6b5c08619..eeca643fedbe 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi @@ -46,31 +46,19 @@ pmsg-size = <0x8000>; }; - rtos_ipc_memory_region: ipc-memories@9c800000 { + rtos_ipc_memory_region: memory@9c800000 { compatible = "shared-dma-pool"; reg = <0x00 0x9c800000 0x00 0x00300000>; no-map; }; - mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9cb00000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: m4f-memory@9cc00000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9cc00000 0x00 0xe00000>; - no-map; - }; - - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9da00000 { + wkup_r5fss0_core0_dma_memory_region: memory@9da00000 { compatible = "shared-dma-pool"; reg = <0x00 0x9da00000 0x00 0x100000>; no-map; }; - wkup_r5fss0_core0_memory_region: r5f-memory@9db00000 { + wkup_r5fss0_core0_memory_region: memory@9db00000 { compatible = "shared-dma-pool"; reg = <0x00 0x9db00000 0x00 0xc00000>; no-map; @@ -245,20 +233,6 @@ }; }; -&mailbox0_cluster0 { - status = "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - &main_pktdma { bootph-all; }; @@ -364,13 +338,6 @@ }; }; -&mcu_m4fss { - mboxes = <&mailbox0_cluster0 &mbox_m4_0>; - memory-region = <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status = "okay"; -}; - &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; @@ -399,12 +366,4 @@ status = "okay"; }; -&wkup_r5fss0 { - status = "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_r5_0>; - memory-region = <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; -}; +#include "k3-am62-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts b/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts index 2e4cf65ee323..7a4cffc27bda 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts +++ b/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts @@ -54,18 +54,6 @@ linux,cma-default; }; - mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9cb00000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: m4f-memory@9cc00000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9cc00000 0x00 0xe00000>; - no-map; - }; - secure_tfa_ddr: tfa@9e780000 { reg = <0x00 0x9e780000 0x00 0x80000>; alignment = <0x1000>; @@ -78,7 +66,13 @@ no-map; }; - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { + wkup_r5fss0_core0_dma_memory_region: memory@9da00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9da00000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: memory@9db00000 { compatible = "shared-dma-pool"; reg = <0x00 0x9db00000 0x00 0xc00000>; no-map; @@ -292,13 +286,6 @@ pinctrl-0 = <&epwm2_pins_default>; }; -&mailbox0_cluster0 { - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - &main_uart0 { pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; @@ -349,13 +336,6 @@ status = "okay"; }; -&mcu_m4fss { - mboxes = <&mailbox0_cluster0 &mbox_m4_0>; - memory-region = <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status = "okay"; -}; - &mcu_pmx0 { wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < @@ -519,3 +499,5 @@ }; }; }; + +#include "k3-am62-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am62-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-am62-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..ea69fab9b52b --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-ti-ipc-firmware.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on AM62 SoCs + * + * Copyright (C) 2021-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&reserved_memory { + mcu_m4fss_dma_memory_region: memory@9cb00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9cb00000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: memory@9cc00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9cc00000 0x00 0xe00000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status = "okay"; + + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mcu_m4fss { + mboxes = <&mailbox0_cluster0 &mbox_m4_0>; + memory-region = <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + status = "okay"; +}; + +&wkup_r5fss0 { + status = "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi index bc2289d74774..dc4b228a9fd7 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -189,7 +189,7 @@ regulator-name = "USB_1_EN"; }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; @@ -206,7 +206,13 @@ no-map; }; - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { + wkup_r5fss0_core0_dma_memory_region: memory@9da00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9da00000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: memory@9db00000 { compatible = "shared-dma-pool"; reg = <0x00 0x9db00000 0x00 0xc00000>; no-map; @@ -1316,13 +1322,6 @@ status = "disabled"; }; -&mailbox0_cluster0 { - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - /* Verdin CAN_1 */ &main_mcan0 { pinctrl-names = "default"; @@ -1506,3 +1505,5 @@ pinctrl-0 = <&pinctrl_wkup_uart0>; status = "disabled"; }; + +#include "k3-am62-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi index 6549b7efa656..75aed3a88284 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi @@ -128,6 +128,7 @@ ti,sci = <&dmsc>; ti,sci-dev-id = <121>; ti,sci-proc-ids = <0x01 0xff>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts index 72b09f9c69d8..7028d9835c4a 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts @@ -83,7 +83,7 @@ no-map; }; - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { + wkup_r5fss0_core0_dma_memory_region: memory@9db00000 { compatible = "shared-dma-pool"; reg = <0x00 0x9db00000 0x00 0xc00000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi new file mode 100644 index 000000000000..fe0b98e1d105 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi @@ -0,0 +1,296 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Common dtsi for AM625 SK and derivatives + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-am62x-sk-common.dtsi" + +/ { + opp-table { + /* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; + + vmain_pd: regulator-0 { + /* TPS65988 PD CONTROLLER OUTPUT */ + compatible = "regulator-fixed"; + regulator-name = "vmain_pd"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vcc_5v0: regulator-1 { + /* Output of LM34936 */ + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vcc_3v3_sys: regulator-2 { + /* output of LM61460-Q1 */ + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vdd_mmc1: regulator-3 { + /* TPS22918DBVR */ + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply = <&vcc_3v3_sys>; + gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vdd_sd_dv: regulator-4 { + /* Output of TLV71033 */ + compatible = "regulator-gpio"; + regulator-name = "tlv71033"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vcc_5v0>; + gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + bootph-all; + }; + + vcc_1v8: regulator-5 { + /* output of TPS6282518DMQ */ + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3_sys>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&main_pmx0 { + main_mmc0_pins_default: main-mmc0-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ + AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ + AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ + AM62X_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */ + AM62X_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */ + AM62X_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */ + AM62X_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */ + AM62X_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */ + AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ + AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ + >; + }; + + main_rgmii2_pins_default: main-rgmii2-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ + AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ + AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */ + AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */ + AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */ + AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */ + AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */ + AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */ + AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */ + AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */ + AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */ + AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ + >; + }; + + ospi0_pins_default: ospi0-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ + AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ + AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */ + AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */ + AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */ + AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ + AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */ + AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */ + AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */ + AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ + AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ + >; + }; + + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */ + >; + bootph-all; + }; + + main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ + >; + bootph-all; + }; +}; + +&main_gpio0 { + bootph-all; +}; + +&main_gpio1 { + bootph-all; +}; + +&main_i2c1 { + exp1: gpio@22 { + compatible = "ti,tca6424"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>; + interrupt-parent = <&main_gpio1>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", + "PRU_DETECT", "MMC1_SD_EN", + "VPP_LDO_EN", "EXP_PS_3V3_En", + "EXP_PS_5V0_En", "EXP_HAT_DETECT", + "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn", + "UART1_FET_BUF_EN", "WL_LT_EN", + "GPIO_HDMI_RSTn", "CSI_GPIO1", + "CSI_GPIO2", "PRU_3V3_EN", + "HDMI_INTn", "PD_I2C_IRQ", + "MCASP1_FET_EN", "MCASP1_BUF_BT_EN", + "MCASP1_FET_SEL", "UART1_FET_SEL", + "TSINT#", "IO_EXP_TEST_LED"; + bootph-all; + }; +}; + +&sdhci0 { + bootph-all; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; + disable-wp; +}; + +&sdhci1 { + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv>; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>; +}; + +&cpsw_port2 { + /* PCB provides an internal delay of 2ns */ + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy1>; +}; + +&cpsw3g_mdio { + cpsw3g_phy1: ethernet-phy@1 { + reg = <1>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,min-output-impedance; + }; +}; + +&fss { + bootph-all; +}; + +&ospi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + bootph-pre-ram; + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts index d240165bda9c..52954c77df80 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -7,310 +7,17 @@ /dts-v1/; -#include "k3-am62x-sk-common.dtsi" +#include "k3-am625.dtsi" +#include "k3-am625-sk-common.dtsi" / { compatible = "ti,am625-sk", "ti,am625"; model = "Texas Instruments AM625 SK"; - opp-table { - /* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */ - opp-1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-supported-hw = <0x01 0x0004>; - clock-latency-ns = <6000000>; - }; - }; - memory@80000000 { - device_type = "memory"; /* 2G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>; - - }; - - vmain_pd: regulator-0 { - /* TPS65988 PD CONTROLLER OUTPUT */ - bootph-all; - compatible = "regulator-fixed"; - regulator-name = "vmain_pd"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_5v0: regulator-1 { - /* Output of LM34936 */ - bootph-all; - compatible = "regulator-fixed"; - regulator-name = "vcc_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vmain_pd>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_3v3_sys: regulator-2 { - /* output of LM61460-Q1 */ - bootph-all; - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_sys"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vmain_pd>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_mmc1: regulator-3 { - /* TPS22918DBVR */ - bootph-all; - compatible = "regulator-fixed"; - regulator-name = "vdd_mmc1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - vin-supply = <&vcc_3v3_sys>; - gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; - }; - - vdd_sd_dv: regulator-4 { - /* Output of TLV71033 */ - bootph-all; - compatible = "regulator-gpio"; - regulator-name = "tlv71033"; - pinctrl-names = "default"; - pinctrl-0 = <&vdd_sd_dv_pins_default>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - vin-supply = <&vcc_5v0>; - gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; - states = <1800000 0x0>, - <3300000 0x1>; - }; - - vcc_1v8: regulator-5 { - /* output of TPS6282518DMQ */ - compatible = "regulator-fixed"; - regulator-name = "vcc_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3_sys>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&main_pmx0 { - main_mmc0_pins_default: main-mmc0-default-pins { - bootph-all; - pinctrl-single,pins = < - AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ - AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ - AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ - AM62X_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */ - AM62X_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */ - AM62X_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */ - AM62X_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */ - AM62X_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */ - AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ - AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ - >; - }; - - main_rgmii2_pins_default: main-rgmii2-default-pins { - bootph-all; - pinctrl-single,pins = < - AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ - AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ - AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */ - AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */ - AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */ - AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */ - AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */ - AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */ - AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */ - AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */ - AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */ - AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ - >; - }; - - ospi0_pins_default: ospi0-default-pins { - bootph-all; - pinctrl-single,pins = < - AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ - AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ - AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */ - AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */ - AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */ - AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ - AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */ - AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */ - AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */ - AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ - AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ - >; - }; - - vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { - bootph-all; - pinctrl-single,pins = < - AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */ - >; - }; - - main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins { - bootph-all; - pinctrl-single,pins = < - AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ - >; - }; -}; - -&main_gpio0 { - bootph-all; -}; - -&main_gpio1 { - bootph-all; -}; - -&main_i2c1 { - bootph-all; - exp1: gpio@22 { - bootph-all; - compatible = "ti,tca6424"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", - "PRU_DETECT", "MMC1_SD_EN", - "VPP_LDO_EN", "EXP_PS_3V3_En", - "EXP_PS_5V0_En", "EXP_HAT_DETECT", - "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn", - "UART1_FET_BUF_EN", "WL_LT_EN", - "GPIO_HDMI_RSTn", "CSI_GPIO1", - "CSI_GPIO2", "PRU_3V3_EN", - "HDMI_INTn", "PD_I2C_IRQ", - "MCASP1_FET_EN", "MCASP1_BUF_BT_EN", - "MCASP1_FET_SEL", "UART1_FET_SEL", - "TSINT#", "IO_EXP_TEST_LED"; - - interrupt-parent = <&main_gpio1>; - interrupts = <23 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>; - }; -}; - -&sdhci0 { - bootph-all; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&main_mmc0_pins_default>; - status = "okay"; -}; - -&sdhci1 { - vmmc-supply = <&vdd_mmc1>; - vqmmc-supply = <&vdd_sd_dv>; -}; - -&cpsw3g { - pinctrl-names = "default"; - pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>; -}; - -&cpsw_port2 { - phy-mode = "rgmii-rxid"; - phy-handle = <&cpsw3g_phy1>; -}; - -&cpsw3g_mdio { - cpsw3g_phy1: ethernet-phy@1 { - reg = <1>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - ti,min-output-impedance; - }; -}; - -&fss { - bootph-all; -}; - -&ospi0 { - bootph-all; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ospi0_pins_default>; - - flash@0 { - bootph-all; - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <8>; - spi-rx-bus-width = <8>; - spi-max-frequency = <25000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <4>; - - partitions { - bootph-all; - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "ospi.tiboot3"; - reg = <0x0 0x80000>; - }; - - partition@80000 { - label = "ospi.tispl"; - reg = <0x80000 0x200000>; - }; - - partition@280000 { - label = "ospi.u-boot"; - reg = <0x280000 0x400000>; - }; - - partition@680000 { - label = "ospi.env"; - reg = <0x680000 0x40000>; - }; - - partition@6c0000 { - label = "ospi.env.backup"; - reg = <0x6c0000 0x40000>; - }; - - partition@800000 { - label = "ospi.rootfs"; - reg = <0x800000 0x37c0000>; - }; - - partition@3fc0000 { - bootph-pre-ram; - label = "ospi.phypattern"; - reg = <0x3fc0000 0x40000>; - }; - }; + device_type = "memory"; + bootph-pre-ram; }; }; - -&tlv320aic3106 { - DVDD-supply = <&vcc_1v8>; -}; diff --git a/arch/arm64/boot/dts/ti/k3-am6254atl-sk.dts b/arch/arm64/boot/dts/ti/k3-am6254atl-sk.dts new file mode 100644 index 000000000000..055e63a3fbb1 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am6254atl-sk.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * AM6254atl SiP SK: https://www.ti.com/lit/df/sprr482b/sprr482b.zip + * Webpage: https://www.ti.com/tool/SK-AM62-SIP + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-am6254atl.dtsi" +#include "k3-am625-sk-common.dtsi" + +/ { + model = "Texas Instruments AM6254atl SK"; + compatible = "ti,am6254atl-sk", "ti,am6254atl", "ti,am625"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am6254atl.dtsi b/arch/arm64/boot/dts/ti/k3-am6254atl.dtsi new file mode 100644 index 000000000000..976ad7dc1e71 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am6254atl.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * DTS for AM625 SiP SoC family in Quad core configuration and 512MiB RAM. + * + * Webpage: https://www.ti.com/product/AM625SIP + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-am625.dtsi" + +/ { + model = "Texas Instruments AM6254atl SiP"; + compatible = "ti,am6254atl", "ti,am625"; + + memory@80000000 { + /* 512MiB of integrated RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x20000000>; + device_type = "memory"; + bootph-all; + }; + +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index 44e7e459f176..829f00adea6e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -267,7 +267,7 @@ main_pmx0: pinctrl@f4000 { compatible = "pinctrl-single"; - reg = <0x00 0xf4000 0x00 0x2ac>; + reg = <0x00 0xf4000 0x00 0x25c>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; @@ -804,6 +804,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; mailbox0_cluster1: mailbox@29010000 { @@ -813,6 +814,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; mailbox0_cluster2: mailbox@29020000 { @@ -822,6 +824,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; mailbox0_cluster3: mailbox@29030000 { @@ -831,6 +834,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; main_mcan0: can@20701000 { @@ -1054,6 +1058,9 @@ cdns_csi2rx0: csi-bridge@30101000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x30101000 0x00 0x1000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi index ee961ced7208..d22caa7c346b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi @@ -197,6 +197,7 @@ ti,sci = <&dmsc>; ti,sci-dev-id = <9>; ti,sci-proc-ids = <0x03 0xff>; + status = "disabled"; }; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi index 5dc5d2cb20cc..b3d012a5a26a 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi @@ -45,7 +45,7 @@ bootph-all; }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; @@ -59,37 +59,13 @@ linux,cma-default; }; - c7x_0_dma_memory_region: c7x-dma-memory@99800000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x99800000 0x00 0x100000>; - no-map; - }; - - c7x_0_memory_region: c7x-memory@99900000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x99900000 0x00 0xf00000>; - no-map; - }; - - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9b800000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9b900000 0x00 0xf00000>; - no-map; - }; - - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + wkup_r5fss0_core0_dma_memory_region: memory@9c800000 { compatible = "shared-dma-pool"; reg = <0x00 0x9c800000 0x00 0x100000>; no-map; }; - wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + wkup_r5fss0_core0_memory_region: memory@9c900000 { compatible = "shared-dma-pool"; reg = <0x00 0x9c900000 0x00 0xf00000>; no-map; @@ -200,11 +176,13 @@ }; }; -&c7x_0 { - mboxes = <&mailbox0_cluster1 &mbox_c7x_0>; - memory-region = <&c7x_0_dma_memory_region>, - <&c7x_0_memory_region>; - status = "okay"; +&a53_opp_table { + /* Requires VDD_CORE at 0v85 */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; }; &cpsw3g { @@ -237,33 +215,6 @@ status = "okay"; }; -&mailbox0_cluster0 { - status = "okay"; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - - mbox_c7x_0: mbox-c7x-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - - mbox_mcu_r5_0: mbox-mcu-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - &main_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; @@ -379,26 +330,6 @@ bootph-all; }; -/* main_rti4 is used by C7x DSP */ -&main_rti4 { - status = "reserved"; -}; - -/* main_timer2 is used by C7x DSP */ -&main_timer2 { - status = "reserved"; -}; - -&mcu_r5fss0 { - status = "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster2 &mbox_mcu_r5_0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; @@ -427,12 +358,4 @@ status = "okay"; }; -&wkup_r5fss0 { - status = "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_r5_0>; - memory-region = <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; -}; +#include "k3-am62a-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am62a-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..950f4f37d477 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62a-ti-ipc-firmware.dtsi @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on AM62A SoCs + * + * Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&reserved_memory { + c7x_0_dma_memory_region: memory@99800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x99800000 0x00 0x100000>; + no-map; + }; + + c7x_0_memory_region: memory@99900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x99900000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: memory@9b900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b900000 0x00 0xf00000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status = "okay"; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + + mbox_c7x_0: mbox-c7x-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&wkup_r5fss0 { + status = "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0>, <&mbox_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; + status = "okay"; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster2>, <&mbox_mcu_r5_0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; + status = "okay"; +}; + +&c7x_0 { + mboxes = <&mailbox0_cluster1>, <&mbox_c7x_0>; + memory-region = <&c7x_0_dma_memory_region>, + <&c7x_0_memory_region>; + status = "okay"; +}; + +/* main_rti4 is used by C7x DSP */ +&main_rti4 { + status = "reserved"; +}; + +/* main_timer2 is used by C7x DSP */ +&main_timer2 { + status = "reserved"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi index 9ef1c829a9df..23877dadc98d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -127,6 +127,7 @@ ti,sci = <&dmsc>; ti,sci-dev-id = <121>; ti,sci-proc-ids = <0x01 0xff>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index bceead5e288e..af591fe6ae4f 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -39,7 +39,7 @@ bootph-all; }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; @@ -53,37 +53,13 @@ linux,cma-default; }; - c7x_0_dma_memory_region: c7x-dma-memory@99800000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x99800000 0x00 0x100000>; - no-map; - }; - - c7x_0_memory_region: c7x-memory@99900000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x99900000 0x00 0xf00000>; - no-map; - }; - - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9b800000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9b900000 0x00 0xf00000>; - no-map; - }; - - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + wkup_r5fss0_core0_dma_memory_region: memory@9c800000 { compatible = "shared-dma-pool"; reg = <0x00 0x9c800000 0x00 0x100000>; no-map; }; - wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + wkup_r5fss0_core0_memory_region: memory@9c900000 { compatible = "shared-dma-pool"; reg = <0x00 0x9c900000 0x00 0xf00000>; no-map; @@ -713,11 +689,6 @@ status = "reserved"; }; -/* main_timer2 is used by C7x DSP */ -&main_timer2 { - status = "reserved"; -}; - &usbss0 { status = "okay"; ti,vbus-divider; @@ -734,6 +705,10 @@ }; }; +&usb0_phy_ctrl { + bootph-all; +}; + &usbss1 { status = "okay"; }; @@ -835,65 +810,6 @@ status = "okay"; }; -&mailbox0_cluster0 { - status = "okay"; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - - mbox_c7x_0: mbox-c7x-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - - mbox_mcu_r5_0: mbox-mcu-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&wkup_r5fss0 { - status = "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_r5_0>; - memory-region = <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0 { - status = "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_mcu_r5_0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&c7x_0 { - mboxes = <&mailbox0_cluster1>, <&mbox_c7x_0>; - memory-region = <&c7x_0_dma_memory_region>, - <&c7x_0_memory_region>; - status = "okay"; -}; - -/* main_rti4 is used by C7x DSP */ -&main_rti4 { - status = "reserved"; -}; - &fss { status = "okay"; }; @@ -935,3 +851,5 @@ >; }; }; + +#include "k3-am62a-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts index daea18b0bc61..83af889e790a 100644 --- a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts @@ -25,6 +25,7 @@ rtc0 = &wkup_rtc0; ethernet0 = &cpsw_port1; ethernet1 = &cpsw_port2; + spi0 = &ospi0; }; chosen { @@ -39,7 +40,7 @@ bootph-all; }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; @@ -58,37 +59,13 @@ no-map; }; - c7x_0_dma_memory_region: c7x-dma-memory@99800000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x99800000 0x00 0x100000>; - no-map; - }; - - c7x_0_memory_region: c7x-memory@99900000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x99900000 0x00 0xf00000>; - no-map; - }; - - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9b800000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9b900000 0x00 0xf00000>; - no-map; - }; - - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + wkup_r5fss0_core0_dma_memory_region: memory@9c800000 { compatible = "shared-dma-pool"; reg = <0x00 0x9c800000 0x00 0x100000>; no-map; }; - wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + wkup_r5fss0_core0_memory_region: memory@9c900000 { compatible = "shared-dma-pool"; reg = <0x00 0x9c900000 0x00 0xf00000>; no-map; @@ -100,7 +77,7 @@ no-map; }; - rtos_ipc_memory_region: ipc-memories@a0000000 { + rtos_ipc_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x01000000>; no-map; @@ -367,6 +344,32 @@ AM62DX_IOPAD(0x0244, PIN_INPUT, 7) /* (D18) MMC1_SDWP.GPIO1_49 */ >; }; + + main_usb1_pins_default: main-usb1-default-pins { + pinctrl-single,pins = < + AM62DX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (D19) USB1_DRVVBUS */ + >; + }; + + ospi0_pins_default: ospi0-default-pins { + pinctrl-single,pins = < + AM62DX_IOPAD(0x0000, PIN_OUTPUT, 0) /* (L22) OSPI0_CLK */ + AM62DX_IOPAD(0x002c, PIN_OUTPUT, 0) /* (H21) OSPI0_CSn0 */ + AM62DX_IOPAD(0x0030, PIN_OUTPUT, 0) /* (G19) OSPI0_CSn1 */ + AM62DX_IOPAD(0x0034, PIN_OUTPUT, 0) /* (K20) OSPI0_CSn2 */ + AM62DX_IOPAD(0x0038, PIN_OUTPUT, 0) /* (G20) OSPI0_CSn3 */ + AM62DX_IOPAD(0x000c, PIN_INPUT, 0) /* (J21) OSPI0_D0 */ + AM62DX_IOPAD(0x0010, PIN_INPUT, 0) /* (J18) OSPI0_D1 */ + AM62DX_IOPAD(0x0014, PIN_INPUT, 0) /* (J19) OSPI0_D2 */ + AM62DX_IOPAD(0x0018, PIN_INPUT, 0) /* (H18) OSPI0_D3 */ + AM62DX_IOPAD(0x001c, PIN_INPUT, 0) /* (K21) OSPI0_D4 */ + AM62DX_IOPAD(0x0020, PIN_INPUT, 0) /* (H19) OSPI0_D5 */ + AM62DX_IOPAD(0x0024, PIN_INPUT, 0) /* (J20) OSPI0_D6 */ + AM62DX_IOPAD(0x0028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ + AM62DX_IOPAD(0x0008, PIN_INPUT, 0) /* (L21) OSPI0_DQS */ + >; + bootph-all; + }; }; &mcu_gpio0 { @@ -499,6 +502,11 @@ status = "okay"; }; +&usbss0 { + status = "okay"; + ti,vbus-divider; +}; + &usb0 { usb-role-switch; @@ -509,6 +517,16 @@ }; }; +&usbss1 { + status = "okay"; +}; + +&usb1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&main_usb1_pins_default>; +}; + &cpsw3g { pinctrl-names = "default"; pinctrl-0 = <&main_rgmii1_pins_default>, @@ -551,65 +569,81 @@ }; }; -&mailbox0_cluster0 { +&fss { status = "okay"; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; }; -&mailbox0_cluster1 { +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; status = "okay"; - mbox_c7x_0: mbox-c7x-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; + flash@0{ + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; -&mailbox0_cluster2 { - status = "okay"; + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; - mbox_mcu_r5_0: mbox-mcu-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; -&wkup_r5fss0 { - status = "okay"; + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + bootph-all; + }; + }; + }; }; &wkup_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_r5_0>; - memory-region = <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; bootph-pre-ram; }; -&mcu_r5fss0 { - status = "okay"; -}; - &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster2 &mbox_mcu_r5_0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; firmware-name = "am62d-mcu-r5f0_0-fw"; - status = "okay"; }; &c7x_0 { - mboxes = <&mailbox0_cluster1 &mbox_c7x_0>; - memory-region = <&c7x_0_dma_memory_region>, - <&c7x_0_memory_region>; firmware-name = "am62d-c71_0-fw"; - status = "okay"; }; -/* main_rti4 is used by C7x DSP */ -&main_rti4 { - status = "reserved"; -}; +#include "k3-am62a-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi index 2e5e25a8ca86..0c05bcf1d776 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi @@ -576,15 +576,12 @@ bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; - mmc-hs400-1_8v; ti,clkbuf-sel = <0x7>; - ti,strobe-sel = <0x77>; ti,trm-icp = <0x8>; ti,otap-del-sel-legacy = <0x1>; ti,otap-del-sel-mmc-hs = <0x1>; ti,otap-del-sel-ddr52 = <0x6>; ti,otap-del-sel-hs200 = <0x8>; - ti,otap-del-sel-hs400 = <0x5>; ti,itap-del-sel-legacy = <0x10>; ti,itap-del-sel-mmc-hs = <0xa>; ti,itap-del-sel-ddr52 = <0x3>; @@ -1045,6 +1042,9 @@ cdns_csi2rx0: csi-bridge@30101000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x30101000 0x00 0x1000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi index bd6a00d13aea..5288c959f3c1 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi @@ -205,6 +205,7 @@ ti,atcm-enable = <0>; ti,btcm-enable = <1>; ti,loczrama = <0>; + status = "disabled"; }; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi index 6757b37a9de3..8612b45e665c 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi @@ -136,6 +136,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi index 6aea9d3f134e..908cc0760e7d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi @@ -74,3 +74,9 @@ gpio-reserved-ranges = <32 10>; ti,ngpio = <52>; }; + +&sdhci0 { + mmc-hs400-1_8v; + ti,strobe-sel = <0x66>; + ti,otap-del-sel-hs400 = <0x5>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..d29a5dbe13ef --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on AM62P SoCs + * + * Copyright (C) 2023-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&reserved_memory { + mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: memory@9b900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b900000 0x00 0xf00000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status = "okay"; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&wkup_r5fss0 { + status = "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; + status = "okay"; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi index a2fdc6741da2..99810047614e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi @@ -147,7 +147,7 @@ regulator-name = "+V_SODIMM"; }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; @@ -162,7 +162,13 @@ no-map; }; - wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + wkup_r5fss0_core0_dma_memory_region: memory@9c800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c800000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: memory@9c900000 { compatible = "shared-dma-pool"; reg = <0x00 0x9c900000 0x00 0x01e00000>; no-map; @@ -830,24 +836,6 @@ status = "disabled"; }; -&mailbox0_cluster0 { - status = "okay"; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - - mbox_mcu_r5_0: mbox-mcu-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - &main0_alert { temperature = <95000>; }; @@ -1426,3 +1414,5 @@ uart-has-rtscts; status = "disabled"; }; + +#include "k3-am62p-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index 899da7896563..a064a632680e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -44,30 +44,18 @@ bootph-pre-ram; }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; - mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@9b800000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9b800000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@9b900000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9b900000 0x00 0xf00000>; - no-map; - }; - - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + wkup_r5fss0_core0_dma_memory_region: memory@9c800000 { compatible = "shared-dma-pool"; reg = <0x00 0x9c800000 0x00 0x100000>; no-map; }; - wkup_r5fss0_core0_memory_region: r5f-memory@9c900000 { + wkup_r5fss0_core0_memory_region: memory@9c900000 { compatible = "shared-dma-pool"; reg = <0x00 0x9c900000 0x00 0xf00000>; no-map; @@ -360,7 +348,7 @@ main_usb1_pins_default: main-usb1-default-pins { pinctrl-single,pins = < - AM62PX_IOPAD(0x0258, PIN_INPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP, 0) /* (G21) USB1_DRVVBUS */ + AM62PX_IOPAD(0x0258, PIN_INPUT, 0) /* (G21) USB1_DRVVBUS */ >; }; @@ -607,6 +595,10 @@ }; }; +&usb0_phy_ctrl { + bootph-all; +}; + &usb1 { dr_mode = "host"; pinctrl-names = "default"; @@ -699,44 +691,6 @@ }; }; -&mailbox0_cluster0 { - status = "okay"; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - - mbox_mcu_r5_0: mbox-mcu-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&wkup_r5fss0 { - status = "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_r5_0>; - memory-region = <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0 { - status = "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - &main_uart0 { pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; @@ -808,3 +762,5 @@ pinctrl-0 = <&main_epwm1_pins_default>; status = "okay"; }; + +#include "k3-am62p-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts b/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts new file mode 100644 index 000000000000..4bb92fde6ab8 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts @@ -0,0 +1,500 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Variscite Symphony carrier board for VAR-SOM-AM62P + * + * Link: https://www.variscite.it/product/single-board-computers/symphony-board/ + * + * Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include "k3-am62p5-var-som.dtsi" + +/ { + model = "Variscite VAR-SOM-AM62P on Symphony-Board"; + compatible = "variscite,var-som-am62p-symphony", "variscite,var-som-am62p", "ti,am62p5"; + + aliases { + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + mmc2 = &sdhci2; + serial0 = &main_uart0; + serial2 = &main_uart2; + serial5 = &main_uart5; + serial6 = &main_uart6; + spi5 = &main_spi2; + usb0 = &usb0; + usb1 = &usb1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clk_ov5640_fixed: clock-24000000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-back { + label = "Back"; + linux,code = <KEY_BACK>; + gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; + }; + + button-home { + label = "Home"; + linux,code = <KEY_HOME>; + gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; + }; + + button-menu { + label = "Menu"; + linux,code = <KEY_MENU>; + gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-heartbeat { + label = "Heartbeat"; + linux,default-trigger = "heartbeat"; + gpios = <&pca9534 0 GPIO_ACTIVE_LOW>; + }; + }; + + reg_2p8v: regulator-2p8v { + compatible = "regulator-fixed"; + regulator-name = "2P8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <®_3v3>; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <®_3v3>; + regulator-always-on; + }; + + reg_1p5v: regulator-1p5v { + compatible = "regulator-fixed"; + regulator-name = "1P5V"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + vin-supply = <®_3v3>; + regulator-always-on; + }; + + reg_sdhc1_vmmc: regulator-sdhc1 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_SD"; + vin-supply = <®_sdhc1_vmmc_int>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&main_gpio0 30 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + reg_sdhc1_vmmc_int: regulator-sdhc1-int { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_SD_INT"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1_vmmc>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&main_gpio0 53 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + reg_sdhc1_vqmmc: regulator-sdhci1-vqmmc { + compatible = "regulator-gpio"; + regulator-name = "+V3.3_SD_VQMMC"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1_vqmmc>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + gpios = <&main_gpio0 56 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + bootph-all; + }; + + reg_ov5640_buf_en: regulator-camera-buf-en { + compatible = "regulator-fixed"; + regulator-name = "ov5640_buf_en"; + gpios = <&main_gpio0 21 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + }; + + transceiver1: can-phy { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_extcon>; + label = "USB-C"; + id-gpios = <&main_gpio1 12 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + usb_con_hs: endpoint { + remote-endpoint = <&typec_hs>; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1>, + <&pinctrl_rgmii2>; + status = "okay"; +}; + +&cpsw3g_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio1>; + status = "okay"; + + cpsw3g_phy1: ethernet-phy@5 { + compatible = "ethernet-phy-id0283.bc30"; + reg = <5>; + reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <100000>; + }; +}; + +&cpsw_port2 { + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the Symphony PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + phy-handle = <&cpsw3g_phy1>; + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; + +&main_i2c0{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clock-frequency = <400000>; + status = "okay"; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + AVDD-supply = <®_2p8v>; + DOVDD-supply = <®_1p8v>; + DVDD-supply = <®_1p5v>; + powerdown-gpios = <&main_gpio0 10 GPIO_ACTIVE_HIGH>; + reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + + /* GPIO expander */ + pca9534: gpio@20 { + compatible = "nxp,pca9534"; + reg = <0x20>; + gpio-controller; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca9534>; + interrupt-parent = <&main_gpio1>; + interrupts = <30 IRQ_TYPE_EDGE_FALLING>; + #gpio-cells = <2>; + status = "okay"; + + usb3-sel-hog { + gpio-hog; + gpios = <4 0>; + output-low; + line-name = "usb3_sel"; + }; + + eth-som-vselect-hog { + gpio-hog; + gpios = <6 0>; + output-low; + line-name = "eth-vselect"; + }; + + eth-mdio-enable-hog { + gpio-hog; + gpios = <7 0>; + output-high; + line-name = "eth-mdio-enable"; + }; + }; +}; + +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <400000>; + status = "okay"; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; +}; + +&main_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcan0>; + phys = <&transceiver1>; + status = "okay"; +}; + +&main_pmx0 { + pinctrl_extcon: main-extcon-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01a8, PIN_INPUT, 7) /* (F25) MCASP0_AFSX.GPIO1_12 */ + >; + }; + + pinctrl_i2c0: main-i2c0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B25) I2C0_SCL */ + AM62PX_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A24) I2C0_SDA */ + >; + }; + + pinctrl_i2c1: main-i2c1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (C24) I2C1_SCL */ + AM62PX_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (B24) I2C1_SDA */ + >; + bootph-all; + }; + + pinctrl_mcan0: main-mcan0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01dc, PIN_INPUT, 0) /* (F20) MCAN0_RX */ + AM62PX_IOPAD(0x01d8, PIN_OUTPUT, 0) /* (B23) MCAN0_TX */ + >; + }; + + pinctrl_mmc1: main-mmc1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x023c, PIN_INPUT, 0) /* (H20) MMC1_CMD */ + AM62PX_IOPAD(0x0234, PIN_OUTPUT, 0) /* (J24) MMC1_CLK */ + AM62PX_IOPAD(0x0230, PIN_INPUT, 0) /* (H21) MMC1_DAT0 */ + AM62PX_IOPAD(0x022c, PIN_INPUT, 0) /* (H23) MMC1_DAT1 */ + AM62PX_IOPAD(0x0228, PIN_INPUT, 0) /* (H22) MMC1_DAT2 */ + AM62PX_IOPAD(0x0224, PIN_INPUT, 0) /* (H25) MMC1_DAT3 */ + AM62PX_IOPAD(0x0240, PIN_INPUT, 0) /* (D23) MMC1_SDCD */ + >; + bootph-all; + }; + + pinctrl_rgmii2: main-rgmii2-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0184, PIN_INPUT, 0) /* (E19) RGMII2_RD0 */ + AM62PX_IOPAD(0x0188, PIN_INPUT, 0) /* (E16) RGMII2_RD1 */ + AM62PX_IOPAD(0x018c, PIN_INPUT, 0) /* (E17) RGMII2_RD2 */ + AM62PX_IOPAD(0x0190, PIN_INPUT, 0) /* (C19) RGMII2_RD3 */ + AM62PX_IOPAD(0x0180, PIN_INPUT, 0) /* (D19) RGMII2_RXC */ + AM62PX_IOPAD(0x017c, PIN_INPUT, 0) /* (F19) RGMII2_RX_CTL */ + AM62PX_IOPAD(0x016c, PIN_INPUT, 0) /* (B19) RGMII2_TD0 */ + AM62PX_IOPAD(0x0170, PIN_INPUT, 0) /* (A21) RGMII2_TD1 */ + AM62PX_IOPAD(0x0174, PIN_INPUT, 0) /* (D17) RGMII2_TD2 */ + AM62PX_IOPAD(0x0178, PIN_INPUT, 0) /* (A19) RGMII2_TD3 */ + AM62PX_IOPAD(0x0168, PIN_INPUT_PULLDOWN, 0) /* (D16) RGMII2_TXC */ + AM62PX_IOPAD(0x0164, PIN_INPUT, 0) /* (A20) RGMII2_TX_CTL */ + >; + }; + + pinctrl_spi2: main-spi2-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01b0, PIN_INPUT, 1) /* (G20) MCASP0_ACLKR.SPI2_CLK */ + AM62PX_IOPAD(0x0194, PIN_OUTPUT, 1) /* (D25) MCASP0_AXR3.SPI2_D0 */ + AM62PX_IOPAD(0x0198, PIN_INPUT, 1) /* (E25) MCASP0_AXR2.SPI2_D1 */ + AM62PX_IOPAD(0x01ac, PIN_OUTPUT, 7) /* (G23) MCASP0_AFSR.GPIO1_13 */ + >; + }; + + pinctrl_uart0: main-uart0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x1c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ + AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */ + >; + bootph-all; + }; + + pinctrl_uart2: main-uart2-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x005c, PIN_INPUT_PULLUP, 2) /* (AC25) GPMC0_AD8.UART2_RXD */ + AM62PX_IOPAD(0x0060, PIN_OUTPUT, 2) /* (AB25) GPMC0_AD9.UART2_TXD */ + >; + }; + + pinctrl_uart6: main-uart6-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x009c, PIN_INPUT_PULLUP, 3) /* (AD24) GPMC0_WAIT1.UART6_RXD */ + AM62PX_IOPAD(0x0244, PIN_OUTPUT, 1) /* (D24) MMC1_SDWP.UART6_TXD */ + >; + }; + + pinctrl_usb1: main-usb1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (G21) USB1_DRVVBUS */ + >; + }; + + pinctrl_ov5640: main-ov5640-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0028, PIN_OUTPUT, 7) /* (N20) OSPI0_D7.GPIO0_10 */ + AM62PX_IOPAD(0x0054, PIN_OUTPUT, 7) /* (V24) GPMC0_AD6.GPIO0_21 */ + AM62PX_IOPAD(0x0058, PIN_OUTPUT, 7) /* (W25) GPMC0_AD7.GPIO0_22 */ + >; + }; + + pinctrl_pca9534: main-pca9534-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01f0, PIN_INPUT, 7) /* (C25) EXT_REFCLK1.GPIO1_30 */ + >; + }; + + pinctrl_sd1_vmmc: main-sd1-vmmc-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0078, PIN_OUTPUT, 7) /* (AC24) GPMC0_AD15.GPIO0_30 */ + AM62PX_IOPAD(0x00d8, PIN_OUTPUT, 7) /* (AE22) VOUT0_DATA8.GPIO0_53 */ + >; + bootph-all; + }; + + pinctrl_sd1_vqmmc: main-sd1-vqmmc-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00e4, PIN_OUTPUT, 7) /* (AE21) VOUT0_DATA11.GPIO0_56 */ + >; + bootph-all; + }; +}; + +&main_spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + ti,pindir-d0-out-d1-in; + cs-gpios = <&main_gpio1 13 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; +}; + +&main_uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&main_uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + status = "okay"; +}; + +&sdhci1 { + /* SD Card */ + vmmc-supply = <®_sdhc1_vmmc>; + vqmmc-supply = <®_sdhc1_vqmmc>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1>; + disable-wp; + bootph-all; + status="okay"; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&usb0 { + usb-role-switch; + status = "okay"; + + port { + typec_hs: endpoint { + remote-endpoint = <&usb_con_hs>; + }; + }; +}; + +&usb1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + status = "okay"; +}; + +&usbss0 { + status = "okay"; +}; + +&usbss1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi new file mode 100644 index 000000000000..edaa4f99295d --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi @@ -0,0 +1,387 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common dtsi for Variscite VAR-SOM-AM62P + * + * Link: https://www.variscite.com/product/system-on-module-som/cortex-a53-krait/var-som-am62p-ti-sitara-am62px/ + * + * Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pwm/pwm.h> +#include "k3-am62p5.dtsi" + +/ { + compatible = "variscite,var-som-am62p", "ti,am62p5"; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <10000>; + reset-gpios = <&main_gpio0 54 GPIO_ACTIVE_LOW>, /* WIFI_PWR_EN */ + <&main_gpio0 59 GPIO_ACTIVE_LOW>; /* WIFI_EN */ + }; + + mmc_pwrseq: mmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc_pwrseq>; + reset-gpios = <&main_gpio0 49 GPIO_ACTIVE_LOW>; + }; + + memory@80000000 { + /* 8G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000001 0x80000000>; + device_type = "memory"; + bootph-pre-ram; + }; + + opp-table { + /* Add 1.4GHz OPP for am62p5-sk board. Requires VDD_CORE at 0v85 */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rtos_ipc_memory_region: rtos-ipc-memory@9b500000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b500000 0x00 0x00300000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@9b800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b800000 0x00 0x00100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@9b900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b900000 0x00 0x00f00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c800000 0x00 0x00100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-memory@9c900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c900000 0x00 0x01e00000>; + no-map; + }; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + no-map; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "On-module +V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "On-module +V1.8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <®_3v3>; + regulator-always-on; + regulator-boot-on; + }; + + reg_3v3_phy: regulator-3v3-phy { + compatible = "regulator-fixed"; + regulator-name = "On-module +V3.3_PHY"; + gpios = <&main_gpio0 45 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1>; +}; + +&cpsw3g_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio1>; + status = "okay"; + + cpsw3g_phy0: ethernet-phy@4 { + compatible = "ethernet-phy-id0283.bc30"; + reg = <4>; + reset-gpios = <&main_gpio0 46 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <100000>; + }; +}; + +&cpsw_port1 { + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + phy-handle = <&cpsw3g_phy0>; + status = "okay"; +}; + +&main_i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <400000>; + status = "okay"; +}; + +&main_i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <400000>; + status = "okay"; +}; + +&main_pmx0 { + pinctrl_mmc_pwrseq: main-emmc-pwrseq-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00c8, PIN_OUTPUT, 7) /* (AB23) VOUT0_DATA4.GPIO0_49 */ + >; + }; + + pinctrl_i2c2: main-i2c2-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (T22) GPMC0_CSn2.I2C2_SCL */ + AM62PX_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (U25) GPMC0_CSn3.I2C2_SDA */ + >; + }; + + pinctrl_i2c3: main-i2c3-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A23) UART0_CTSn.I2C3_SCL */ + AM62PX_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (C22) UART0_RTSn.I2C3_SDA */ + >; + }; + + pinctrl_mdio1: main-mdio1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0160, PIN_OUTPUT, 0) /* (F17) MDIO0_MDC */ + AM62PX_IOPAD(0x015c, PIN_INPUT, 0) /* (F16) MDIO0_MDIO */ + >; + }; + + pinctrl_mmc2: main-mmc2-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0120, PIN_INPUT_PULLUP, 0) /* (K24) MMC2_CMD */ + AM62PX_IOPAD(0x0118, PIN_INPUT_PULLDOWN, 0) /* (K21) MMC2_CLK */ + AM62PX_IOPAD(0x011c, PIN_INPUT_PULLUP, 0) /* () MMC2_CLKLB */ + AM62PX_IOPAD(0x0114, PIN_INPUT_PULLUP, 0) /* (K23) MMC2_DAT0 */ + AM62PX_IOPAD(0x0110, PIN_INPUT_PULLUP, 0) /* (K22) MMC2_DAT1 */ + AM62PX_IOPAD(0x010c, PIN_INPUT_PULLUP, 0) /* (L20) MMC2_DAT2 */ + AM62PX_IOPAD(0x0108, PIN_INPUT_PULLUP, 0) /* (L21) MMC2_DAT3 */ + >; + }; + + pinctrl_rgmii1: main-rgmii1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x014c, PIN_INPUT, 0) /* (B15) RGMII1_RD0 */ + AM62PX_IOPAD(0x0150, PIN_INPUT, 0) /* (B16) RGMII1_RD1 */ + AM62PX_IOPAD(0x0154, PIN_INPUT, 0) /* (A14) RGMII1_RD2 */ + AM62PX_IOPAD(0x0158, PIN_INPUT, 0) /* (B14) RGMII1_RD3 */ + AM62PX_IOPAD(0x0148, PIN_INPUT, 0) /* (A16) RGMII1_RXC */ + AM62PX_IOPAD(0x0144, PIN_INPUT, 0) /* (A15) RGMII1_RX_CTL */ + AM62PX_IOPAD(0x0134, PIN_INPUT, 0) /* (A18) RGMII1_TD0 */ + AM62PX_IOPAD(0x0138, PIN_INPUT, 0) /* (C17) RGMII1_TD1 */ + AM62PX_IOPAD(0x013c, PIN_INPUT, 0) /* (A17) RGMII1_TD2 */ + AM62PX_IOPAD(0x0140, PIN_INPUT, 0) /* (C16) RGMII1_TD3 */ + AM62PX_IOPAD(0x0130, PIN_INPUT, 0) /* (B17) RGMII1_TXC */ + AM62PX_IOPAD(0x012c, PIN_INPUT, 0) /* (B18) RGMII1_TX_CTL */ + >; + bootph-all; + }; + + pinctrl_spi0: main-spi0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (B21) SPI0_CLK */ + AM62PX_IOPAD(0x01b4, PIN_OUTPUT, 0) /* (D20) SPI0_CS0 */ + AM62PX_IOPAD(0x01c0, PIN_OUTPUT, 0) /* (B20) SPI0_D0 */ + AM62PX_IOPAD(0x01c4, PIN_INPUT, 0) /* (C21) SPI0_D1 */ + >; + }; + + pinctrl_uart5: main-uart5-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00ec, PIN_INPUT, 4) /* (AC21) VOUT0_DATA13.UART5_CTSn */ + AM62PX_IOPAD(0x00e8, PIN_OUTPUT, 4) /* (AD21) VOUT0_DATA12.UART5_RTSn */ + AM62PX_IOPAD(0x00d0, PIN_INPUT, 4) /* (AC23) VOUT0_DATA6.UART5_RXD */ + AM62PX_IOPAD(0x00d4, PIN_OUTPUT, 4) /* (AE23) VOUT0_DATA7.UART5_TXD */ + >; + }; + + pinctrl_bt: main-btgrp-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00f4, PIN_OUTPUT, 7) /* (Y20) VOUT0_DATA15.GPIO0_60 (BT_EN) */ + >; + }; + + pinctrl_restouch: main-restouch-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00c4, PIN_INPUT_PULLUP, 7) /* (Y23) VOUT0_DATA3.GPIO0_48 */ + >; + }; + + pinctrl_wifi: main-wifi-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00dc, PIN_OUTPUT, 7) /* (AC22) VOUT0_DATA9.GPIO0_54 - WIFI_PWR_EN - */ + AM62PX_IOPAD(0x00f0, PIN_OUTPUT, 7) /* (AA20) VOUT0_DATA14.GPIO0_59 - WIFI_EN - */ + >; + }; +}; + +&mcu_pmx0 { + pinctrl_wkup_clkout0: wkup-clkout0-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (F13) WKUP_CLKOUT0 */ + >; + }; +}; + +&main_spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + ti,pindir-d0-out-d1-in; + status = "okay"; +}; + +&main_uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>, <&pinctrl_bt>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&sdhci0 { + /* On-module eMMC */ + ti,driver-strength-ohm = <50>; + mmc-pwrseq = <&mmc_pwrseq>; + bootph-all; + status = "okay"; +}; + +&sdhci2 { + /* On-module WiFi */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc2>, <&pinctrl_wifi>; + bus-width = <4>; + non-removable; + keep-power-in-suspend; + mmc-pwrseq = <&wifi_pwrseq>; + ti,fails-without-test-cd; + status = "okay"; +}; + +&usbss0 { + ti,vbus-divider; +}; + +&usbss1 { + ti,vbus-divider; +}; + +&mailbox0_cluster0 { + status = "okay"; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&wkup_r5fss0 { + status = "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + +/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */ +&mcu_gpio0 { + status = "reserved"; +}; + +&mcu_gpio_intr { + status = "reserved"; +}; + +&wkup_rtc0 { + status = "disabled"; +}; + +&wkup_rti0 { + /* WKUP RTI0 is used by DM firmware */ + status = "reserved"; +}; + +&wkup_uart0 { + /* WKUP UART0 is used by DM firmware */ + status = "reserved"; +}; + +&main_uart1 { + /* Main UART1 is used by TIFS firmware */ + status = "reserved"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi index 202378d9d5cf..8982a7b9f1a6 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi @@ -135,7 +135,7 @@ opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; - opp-supported-hw = <0x01 0x0006>; + opp-supported-hw = <0x01 0x0007>; clock-latency-ns = <6000000>; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 13e1d36123d5..58f78c0de292 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -8,7 +8,6 @@ #include <dt-bindings/leds/common.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/net/ti-dp83867.h> -#include "k3-am625.dtsi" / { aliases { @@ -29,14 +28,7 @@ stdout-path = "serial2:115200n8"; }; - memory@80000000 { - bootph-pre-ram; - device_type = "memory"; - /* 2G RAM */ - reg = <0x00000000 0x80000000 0x00000000 0x80000000>; - }; - - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; @@ -58,25 +50,13 @@ linux,cma-default; }; - mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9cb00000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: m4f-memory@9cc00000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9cc00000 0x00 0xe00000>; - no-map; - }; - - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9da00000 { + wkup_r5fss0_core0_dma_memory_region: memory@9da00000 { compatible = "shared-dma-pool"; reg = <0x00 0x9da00000 0x00 0x100000>; no-map; }; - wkup_r5fss0_core0_memory_region: r5f-memory@9db00000 { + wkup_r5fss0_core0_memory_region: memory@9db00000 { compatible = "shared-dma-pool"; reg = <0x00 0x9db00000 0x00 0xc00000>; no-map; @@ -249,7 +229,7 @@ main_usb1_pins_default: main-usb1-default-pins { pinctrl-single,pins = < - AM62X_IOPAD(0x0258, PIN_OUTPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP, 0) /* (F18/E16) USB1_DRVVBUS */ + AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18/E16) USB1_DRVVBUS */ >; }; @@ -477,37 +457,6 @@ }; }; -&mailbox0_cluster0 { - status = "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mcu_m4fss { - mboxes = <&mailbox0_cluster0 &mbox_m4_0>; - memory-region = <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status = "okay"; -}; - -&wkup_r5fss0 { - status = "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_r5_0>; - memory-region = <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; -}; - &usbss0 { bootph-all; status = "okay"; @@ -530,6 +479,10 @@ }; }; +&usb0_phy_ctrl { + bootph-all; +}; + &usb1 { dr_mode = "host"; pinctrl-names = "default"; @@ -600,3 +553,5 @@ pinctrl-0 = <&main_epwm1_pins_default>; status = "okay"; }; + +#include "k3-am62-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index c7e5da37486a..d872cc671094 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -921,6 +921,7 @@ <0x78200000 0x00 0x78200000 0x08000>, <0x78300000 0x00 0x78300000 0x08000>; power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; main_r5fss0_core0: r5f@78000000 { compatible = "ti,am64-r5f"; @@ -935,6 +936,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; main_r5fss0_core1: r5f@78200000 { @@ -950,6 +952,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; @@ -963,6 +966,7 @@ <0x78600000 0x00 0x78600000 0x08000>, <0x78700000 0x00 0x78700000 0x08000>; power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; main_r5fss1_core0: r5f@78400000 { compatible = "ti,am64-r5f"; @@ -977,6 +981,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; main_r5fss1_core1: r5f@78600000 { @@ -992,6 +997,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi index d9d491b12c33..02ef1dd92eaa 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -41,71 +41,17 @@ no-map; }; - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + main_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - main_r5fss0_core0_memory_region: r5f-memory@a0100000 { + main_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: m4f-memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a5000000 { - reg = <0x00 0xa5000000 0x00 0x00800000>; - alignment = <0x1000>; - no-map; - }; }; leds { @@ -238,43 +184,6 @@ status = "okay"; }; -&mailbox0_cluster2 { - status = "okay"; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 2>; - ti,mbox-tx = <3 0 2>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 2>; - ti,mbox-tx = <3 0 2>; - }; -}; - -&mailbox0_cluster6 { - status = "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; -}; - &main_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; @@ -349,37 +258,6 @@ bootph-all; }; -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&mcu_m4fss { - mboxes = <&mailbox0_cluster6 &mbox_m4_0>; - memory-region = <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status = "okay"; -}; - &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; @@ -415,3 +293,5 @@ ti,adc-channels = <0 1 2 3 4 5 6 7>; }; }; + +#include "k3-am64-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..6b10646ae64a --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on AM64 SoCs + * + * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&reserved_memory { + main_r5fss0_core1_dma_memory_region: memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + mcu_m4fss_dma_memory_region: memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: memory@a5000000 { + reg = <0x00 0xa5000000 0x00 0x00800000>; + alignment = <0x1000>; + no-map; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 2>; + ti,mbox-tx = <3 0 2>; + }; +}; + +&mailbox0_cluster4 { + status = "okay"; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 2>; + ti,mbox-tx = <3 0 2>; + }; +}; + +&mailbox0_cluster6 { + status = "okay"; + + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; +}; + +/* main_timer8 is used by r5f0-0 */ +&main_timer8 { + status = "reserved"; +}; + +/* main_timer9 is used by r5f0-1 */ +&main_timer9 { + status = "reserved"; +}; + +/* main_timer10 is used by r5f1-0 */ +&main_timer10 { + status = "reserved"; +}; + +/* main_timer11 is used by r5f1-1 */ +&main_timer11 { + status = "reserved"; +}; + +&main_r5fss0 { + status = "okay"; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; + status = "okay"; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; + status = "okay"; +}; + +&main_r5fss1 { + status = "okay"; +}; + +&main_r5fss1_core0 { + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; + status = "okay"; +}; + +&main_r5fss1_core1 { + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; + status = "okay"; +}; + +&mcu_m4fss { + mboxes = <&mailbox0_cluster6 &mbox_m4_0>; + memory-region = <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index e01866372293..85dcff104936 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -42,7 +42,7 @@ reg = <0x00000000 0x80000000 0x00000000 0x80000000>; }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; @@ -53,71 +53,17 @@ no-map; }; - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + main_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - main_r5fss0_core0_memory_region: r5f-memory@a0100000 { + main_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: m4f-memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a5000000 { - reg = <0x00 0xa5000000 0x00 0x00800000>; - alignment = <0x1000>; - no-map; - }; }; evm_12v0: regulator-0 { @@ -727,94 +673,6 @@ }; }; -&mailbox0_cluster2 { - status = "okay"; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 2>; - ti,mbox-tx = <3 0 2>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 2>; - ti,mbox-tx = <3 0 2>; - }; -}; - -&mailbox0_cluster6 { - status = "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&mcu_m4fss { - mboxes = <&mailbox0_cluster6 &mbox_m4_0>; - memory-region = <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status = "okay"; -}; - -/* main_timer8 is used by r5f0-0 */ -&main_timer8 { - status = "reserved"; -}; - -/* main_timer9 is used by r5f0-1 */ -&main_timer9 { - status = "reserved"; -}; - -/* main_timer10 is used by r5f1-0 */ -&main_timer10 { - status = "reserved"; -}; - -/* main_timer11 is used by r5f1-1 */ -&main_timer11 { - status = "reserved"; -}; - &serdes_ln_ctrl { idle-states = <AM64_SERDES0_LANE0_PCIE0>; }; @@ -878,3 +736,5 @@ pinctrl-names = "default"; pinctrl-0 = <&icssg1_iep0_pins_default>; }; + +#include "k3-am64-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-peb-c-010.dtso b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-peb-c-010.dtso new file mode 100644 index 000000000000..7fc73cfacadb --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-peb-c-010.dtso @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2025 PHYTEC America LLC + * Author: Garrett Giordano <ggiordano@phytec.com> + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/net/ti-dp83869.h> +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet3 = "/icssg1-ethernet/ethernet-ports/port@0"; + ethernet4 = "/icssg1-ethernet/ethernet-ports/port@1"; + }; + + icssg1-ethernet { + compatible = "ti,am642-icssg-prueth"; + pinctrl-names = "default"; + pinctrl-0 = <&icssg1_rgmii1_pins_default>, <&icssg1_rgmii2_pins_default>; + + dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */ + <&main_pktdma 0xc201 15>, /* egress slice 0 */ + <&main_pktdma 0xc202 15>, /* egress slice 0 */ + <&main_pktdma 0xc203 15>, /* egress slice 0 */ + <&main_pktdma 0xc204 15>, /* egress slice 1 */ + <&main_pktdma 0xc205 15>, /* egress slice 1 */ + <&main_pktdma 0xc206 15>, /* egress slice 1 */ + <&main_pktdma 0xc207 15>, /* egress slice 1 */ + <&main_pktdma 0x4200 15>, /* ingress slice 0 */ + <&main_pktdma 0x4201 15>, /* ingress slice 1 */ + <&main_pktdma 0x4202 0>, /* mgmnt rsp slice 0 */ + <&main_pktdma 0x4203 0>; /* mgmnt rsp slice 1 */ + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1", + "rxmgm0", "rxmgm1"; + + firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; + + interrupt-parent = <&icssg1_intc>; + interrupts = <24 0 2>, <25 1 3>; + interrupt-names = "tx_ts0", "tx_ts1"; + sram = <&oc_sram>; + + ti,iep = <&icssg1_iep0>, <&icssg1_iep1>; + ti,mii-g-rt = <&icssg1_mii_g_rt>; + ti,mii-rt = <&icssg1_mii_rt>; + ti,pa-stats = <&icssg1_pa_stats>; + ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>; + ti,pruss-gp-mux-sel = <2>, /* MII mode */ + <2>, + <2>, + <2>, /* MII mode */ + <2>, + <2>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + icssg1_emac0: port@0 { + reg = <0>; + phy-handle = <&icssg1_phy1>; + phy-mode = "rgmii-id"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + ti,syscon-rgmii-delay = <&main_conf 0x4110>; + }; + + icssg1_emac1: port@1 { + reg = <1>; + phy-handle = <&icssg1_phy2>; + phy-mode = "rgmii-id"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + ti,syscon-rgmii-delay = <&main_conf 0x4114>; + }; + }; + }; +}; + +&main_pmx0 { + icssg1_mdio_pins_default: icssg1-mdio-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* (Y6) PRG1_MDIO0_MDC */ + AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA6) PRG1_MDIO0_MDIO */ + >; + }; + + icssg1_rgmii1_pins_default: icssg1-rgmii1-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */ + AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */ + AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */ + AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */ + AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */ + AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */ + AM64X_IOPAD(0x00e4, PIN_OUTPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */ + AM64X_IOPAD(0x00e8, PIN_OUTPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */ + AM64X_IOPAD(0x00ec, PIN_OUTPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */ + AM64X_IOPAD(0x00f0, PIN_OUTPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */ + AM64X_IOPAD(0x00f4, PIN_OUTPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */ + AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */ + >; + }; + + icssg1_rgmii2_pins_default: icssg1-rgmii2-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* (W11) PRG1_PRU1_GPO0.PRG1_RGMII2_RD0 */ + AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* (V11) PRG1_PRU1_GPO1.PRG1_RGMII2_RD1 */ + AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* (AA12) PRG1_PRU1_GPO2.PRG1_RGMII2_RD2 */ + AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* (Y12) PRG1_PRU1_GPO3.PRG1_RGMII2_RD3 */ + AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* (W12) PRG1_PRU1_GPO4.PRG1_RGMII2_RX_CTL */ + AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* (U11) PRG1_PRU1_GPO6.PRG1_RGMII2_RXC */ + AM64X_IOPAD(0x0134, PIN_OUTPUT, 2) /* (AA10) PRG1_PRU1_GPO11.PRG1_RGMII2_TD0 */ + AM64X_IOPAD(0x0138, PIN_OUTPUT, 2) /* (V10) PRG1_PRU1_GPO12.PRG1_RGMII2_TD1 */ + AM64X_IOPAD(0x013c, PIN_OUTPUT, 2) /* (U10) PRG1_PRU1_GPO13.PRG1_RGMII2_TD2 */ + AM64X_IOPAD(0x0140, PIN_OUTPUT, 2) /* (AA11) PRG1_PRU1_GPO14.PRG1_RGMII2_TD3 */ + AM64X_IOPAD(0x0144, PIN_OUTPUT, 2) /* (Y11) PRG1_PRU1_GPO15.PRG1_RGMII2_TX_CTL */ + AM64X_IOPAD(0x0148, PIN_INPUT, 2) /* (Y10) PRG1_PRU1_GPO16.PRG1_RGMII2_TXC */ + >; + }; +}; + +&icssg1_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&icssg1_mdio_pins_default>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + icssg1_phy1: ethernet-phy@1 { + reg = <0x1>; + rx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>; + tx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>; + rx-internal-delay-ps = <2000>; + tx-internal-delay-ps = <2000>; + ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>; + ti,min-output-impedance; + }; + + icssg1_phy2: ethernet-phy@2 { + reg = <0x2>; + rx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>; + tx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>; + rx-internal-delay-ps = <2000>; + tx-internal-delay-ps = <2000>; + ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>; + ti,min-output-impedance; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts index 129524eb5b91..e4afa8c0a8ca 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts @@ -100,6 +100,7 @@ ti,mii-g-rt = <&icssg0_mii_g_rt>; ti,mii-rt = <&icssg0_mii_rt>; ti,iep = <&icssg0_iep0>, <&icssg0_iep1>; + ti,pa-stats = <&icssg0_pa_stats>; ethernet-ports { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 1deaa0be0085..1fb1b91a1bad 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -40,7 +40,7 @@ reg = <0x00000000 0x80000000 0x00000000 0x80000000>; }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; @@ -51,71 +51,17 @@ no-map; }; - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + main_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - main_r5fss0_core0_memory_region: r5f-memory@a0100000 { + main_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: m4f-memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a5000000 { - reg = <0x00 0xa5000000 0x00 0x00800000>; - alignment = <0x1000>; - no-map; - }; }; vusb_main: regulator-0 { @@ -642,94 +588,6 @@ }; }; -&mailbox0_cluster2 { - status = "okay"; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 2>; - ti,mbox-tx = <3 0 2>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 2>; - ti,mbox-tx = <3 0 2>; - }; -}; - -&mailbox0_cluster6 { - status = "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&mcu_m4fss { - mboxes = <&mailbox0_cluster6 &mbox_m4_0>; - memory-region = <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status = "okay"; -}; - -/* main_timer8 is used by r5f0-0 */ -&main_timer8 { - status = "reserved"; -}; - -/* main_timer9 is used by r5f0-1 */ -&main_timer9 { - status = "reserved"; -}; - -/* main_timer10 is used by r5f1-0 */ -&main_timer10 { - status = "reserved"; -}; - -/* main_timer11 is used by r5f1-1 */ -&main_timer11 { - status = "reserved"; -}; - &ecap0 { status = "okay"; /* PWM is available on Pin 1 of header J3 */ @@ -743,3 +601,5 @@ pinctrl-names = "default"; pinctrl-0 = <&main_eqep0_pins_default>; }; + +#include "k3-am64-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi index a5cec9a07510..fcbcc04521b8 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi @@ -105,7 +105,7 @@ device_type = "memory"; }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; @@ -115,53 +115,17 @@ no-map; }; - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + main_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - main_r5fss0_core0_memory_region: r5f-memory@a0100000 { + main_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; }; vdd_mmc0: regulator-vdd-mmc0 { @@ -263,34 +227,6 @@ }; }; -&mailbox0_cluster2 { - status = "okay"; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 2>; - ti,mbox-tx = <3 0 2>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 2>; - ti,mbox-tx = <3 0 2>; - }; -}; - &main_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_default_pins>; @@ -488,30 +424,6 @@ }; }; -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - /* SoC default UART console */ &main_uart0 { pinctrl-names = "default"; @@ -590,3 +502,5 @@ ti,vbus-divider; ti,usb2-only; }; + +#include "k3-am64-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi index 828d815d6bdf..ff3b2e0b8dd4 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi @@ -20,7 +20,7 @@ }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; @@ -31,59 +31,17 @@ no-map; }; - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + main_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - main_r5fss0_core0_memory_region: r5f-memory@a0100000 { + main_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a5000000 { - reg = <0x00 0xa5000000 0x00 0x00800000>; - alignment = <0x1000>; - no-map; - }; }; reg_1v8: regulator-1v8 { @@ -130,67 +88,6 @@ }; }; -&mailbox0_cluster2 { - status = "okay"; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 2>; - ti,mbox-tx = <3 0 2>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 2>; - ti,mbox-tx = <3 0 2>; - }; -}; - -&mailbox0_cluster6 { - status = "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - &ospi0 { status = "okay"; pinctrl-names = "default"; @@ -264,3 +161,5 @@ >; }; }; + +#include "k3-am64-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index e5136ed94765..42ba3dab2fc1 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -36,7 +36,7 @@ stdout-path = "serial3:115200n8"; }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; @@ -47,36 +47,18 @@ no-map; }; - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0 0xa0000000 0 0x100000>; no-map; }; - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0 0xa0100000 0 0xf00000>; no-map; }; - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0 0xa1000000 0 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0 0xa1100000 0 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a2000000 { - reg = <0x00 0xa2000000 0x00 0x00200000>; - alignment = <0x1000>; - no-map; - }; - /* To reserve the power-on(PON) reason for watchdog reset */ wdt_reset_memory_region: wdt-memory@a2200000 { reg = <0x00 0xa2200000 0x00 0x1000>; @@ -582,38 +564,6 @@ reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>; }; -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-tx = <1 0 0>; - ti,mbox-rx = <0 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-tx = <1 0 0>; - ti,mbox-rx = <0 0 0>; - }; -}; - -&mcu_r5fss0_core0 { - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; -}; - -&mcu_r5fss0_core1 { - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; - mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; -}; - &mcu_rti1 { memory-region = <&wdt_reset_memory_region>; }; @@ -686,3 +636,9 @@ /* lock-step mode not supported on iot2050 boards */ ti,cluster-mode = <0>; }; + +#include "k3-am65-ti-ipc-firmware.dtsi" + +&rtos_ipc_memory_region { + reg = <0x00 0xa2000000 0x00 0x00200000>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 7cf1f646500a..f6d9a5779918 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -408,6 +408,7 @@ ranges = <0x41000000 0x00 0x41000000 0x20000>, <0x41400000 0x00 0x41400000 0x20000>; power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; mcu_r5fss0_core0: r5f@41000000 { compatible = "ti,am654-r5f"; @@ -422,6 +423,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; mcu_r5fss0_core1: r5f@41400000 { @@ -437,6 +439,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-am65-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..61ab0357fc0d --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am65-ti-ipc-firmware.dtsi @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on AM65 SoCs + * + * Copyright (C) 2016-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&reserved_memory { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0 0xa1000000 0 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0 0xa1100000 0 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: memory@a2000000 { + reg = <0x00 0xa2000000 0x00 0x00100000>; + alignment = <0x1000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status = "okay"; + interrupts = <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-tx = <1 0 0>; + ti,mbox-rx = <0 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + interrupts = <432>; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-tx = <1 0 0>; + ti,mbox-rx = <0 0 0>; + }; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + status = "okay"; +}; + +&mcu_r5fss0_core1 { + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index e589690c7c82..0c42c486d83a 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -39,7 +39,7 @@ <0x00000008 0x80000000 0x00000000 0x80000000>; }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; @@ -50,35 +50,17 @@ no-map; }; - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0 0xa0000000 0 0x100000>; no-map; }; - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0 0xa0100000 0 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0 0xa1000000 0 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0 0xa1100000 0 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a2000000 { - reg = <0x00 0xa2000000 0x00 0x00100000>; - alignment = <0x1000>; - no-map; - }; }; gpio-keys { @@ -521,38 +503,6 @@ status = "disabled"; }; -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-tx = <1 0 0>; - ti,mbox-rx = <0 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-tx = <1 0 0>; - ti,mbox-rx = <0 0 0>; - }; -}; - -&mcu_r5fss0_core0 { - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; -}; - -&mcu_r5fss0_core1 { - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; - mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; -}; - &ospi0 { status = "okay"; pinctrl-names = "default"; @@ -647,3 +597,5 @@ &wkup_gpio0 { bootph-all; }; + +#include "k3-am65-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-sm.dts b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-sm.dts index b829f4bcab69..adf4da7dfa2d 100644 --- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-sm.dts +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-sm.dts @@ -145,7 +145,7 @@ pinctrl-0 = <&main_spi0_pins>; #address-cells = <1>; - #size-cells= <0>; + #size-cells = <0>; }; &mcu_spi0 { diff --git a/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts b/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts index bf9b23df1da2..b697035df04e 100644 --- a/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts +++ b/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts @@ -50,71 +50,17 @@ no-map; }; - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + wkup_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 { + wkup_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: main-r5fss-dma-memory-region@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: main-r5fss-memory-region@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - c7x_0_dma_memory_region: c7x-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - c7x_0_memory_region: c7x-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - c7x_1_dma_memory_region: c7x-dma-memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - c7x_1_memory_region: c7x-memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a5000000 { - reg = <0x00 0xa5000000 0x00 0x1c00000>; - alignment = <0x1000>; - no-map; - }; }; vsys_5v0: regulator-1 { @@ -453,100 +399,4 @@ status = "okay"; }; -&mailbox0_cluster0 { - status = "okay"; - - mbox_wkup_r5_0: mbox-wkup-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - - mbox_mcu_r5_0: mbox-mcu-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - - mbox_c7x_0: mbox-c7x-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster3 { - status = "okay"; - - mbox_main_r5_0: mbox-main-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c7x_1: mbox-c7x-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status = "reserved"; -}; - -&main_timer1 { - status = "reserved"; -}; - -&main_timer2 { - status = "reserved"; -}; - -&wkup_r5fss0 { - status = "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_wkup_r5_0>; - memory-region = <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0 { - status = "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&main_r5fss0 { - status = "okay"; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster3 &mbox_main_r5_0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&c7x_0 { - mboxes = <&mailbox0_cluster2 &mbox_c7x_0>; - memory-region = <&c7x_0_dma_memory_region>, - <&c7x_0_memory_region>; - status = "okay"; -}; - -&c7x_1 { - mboxes = <&mailbox0_cluster3 &mbox_c7x_1>; - memory-region = <&c7x_1_dma_memory_region>, - <&c7x_1_memory_region>; - status = "okay"; -}; +#include "k3-j722s-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi index fd715fee8170..adef02bd8040 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi @@ -49,107 +49,17 @@ no-map; }; - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: c71-dma-memory@a6000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: c71-memory@a6100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - c71_1_dma_memory_region: c71-dma-memory@a7000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c71_1_memory_region: c71-memory@a7100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a8000000 { - reg = <0x00 0xa8000000 0x00 0x01c00000>; - alignment = <0x1000>; - no-map; - }; }; vdd_sd_dv: regulator-sd { @@ -243,80 +153,6 @@ }; }; -&c71_0 { - mboxes = <&mailbox0_cluster4 &mbox_c71_0>; - memory-region = <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; - status = "okay"; -}; - -&c71_1 { - mboxes = <&mailbox0_cluster4 &mbox_c71_1>; - memory-region = <&c71_1_dma_memory_region>, - <&c71_1_memory_region>; - status = "okay"; -}; - -&mailbox0_cluster0 { - interrupts = <436>; - status = "okay"; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - interrupts = <432>; - status = "okay"; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - interrupts = <428>; - status = "okay"; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - interrupts = <420>; - status = "okay"; - - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c71_1: mbox-c71-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - &main_cpsw { pinctrl-names = "default"; pinctrl-0 = <&rgmii1_pins_default>; @@ -367,30 +203,6 @@ status = "okay"; }; -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - /* eMMC */ &main_sdhci0 { non-removable; @@ -405,51 +217,6 @@ bootph-all; }; -&main_r5fss0 { - ti,cluster-mode = <0>; -}; - -&main_r5fss1 { - ti,cluster-mode = <0>; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status = "reserved"; -}; - -&main_timer1 { - status = "reserved"; -}; - -&main_timer2 { - status = "reserved"; -}; - -&main_timer3 { - status = "reserved"; -}; - -&main_timer4 { - status = "reserved"; -}; - -&main_timer5 { - status = "reserved"; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; @@ -599,3 +366,5 @@ pagesize = <32>; }; }; + +#include "k3-j721s2-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index e84c504c87d2..75a107456ce1 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -135,6 +135,34 @@ max-bitrate = <5000000>; }; + edp0_refclk: clock-edp0-refclk { + compatible = "fixed-clock"; + clock-frequency = <19200000>; + #clock-cells = <0>; + }; + + dp0_pwr_3v3: regulator-dp0-pwr { + compatible = "regulator-fixed"; + regulator-name = "dp0-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; /*P0 - DP0_3V3 _EN */ + enable-active-high; + }; + + dp0: dp0-connector { + compatible = "dp-connector"; + label = "DP0"; + type = "full-size"; + dp-pwr-supply = <&dp0_pwr_3v3>; + + port { + dp0_connector_in: endpoint { + remote-endpoint = <&dp0_out>; + }; + }; + }; + connector-hdmi { compatible = "hdmi-connector"; label = "hdmi"; @@ -615,6 +643,39 @@ gpio-line-names = "HDMI_PDn","HDMI_LS_OE", "DP0_3V3_EN","eDP_ENABLE"; }; + + bridge_dsi_edp: bridge-dsi-edp@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + clock-names = "refclk"; + clocks = <&edp0_refclk>; + enable-gpios = <&exp2 3 GPIO_ACTIVE_HIGH>; + vpll-supply = <&vsys_io_1v8>; + vccio-supply = <&vsys_io_1v8>; + vcca-supply = <&vsys_io_1v2>; + vcc-supply = <&vsys_io_1v2>; + + dsi_edp_bridge_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dp0_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + dp0_out: endpoint { + remote-endpoint = <&dp0_connector_in>; + }; + }; + }; + }; }; &main_sdhci1 { @@ -711,6 +772,15 @@ remote-endpoint = <&tfp410_in>; }; }; + + /* DSI */ + port@2 { + reg = <2>; + + dpi0_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; }; &serdes_ln_ctrl { @@ -768,3 +838,30 @@ phys = <&serdes0_usb_link>; phy-names = "cdns3,usb3-phy"; }; + +&dphy_tx0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; +}; + +&dsi0_ports { + + port@0 { + reg = <0>; + + dsi0_out: endpoint { + remote-endpoint = <&dp0_in>; + }; + }; + + port@1 { + reg = <1>; + + dsi0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi index 4ca2d4e2fb9b..6a6dc816b658 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi @@ -27,107 +27,17 @@ no-map; }; - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: c71-dma-memory@a6000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: c71-memory@a6100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - c71_1_dma_memory_region: c71-dma-memory@a7000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c71_1_memory_region: c71-memory@a7100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a8000000 { - reg = <0x00 0xa8000000 0x00 0x01c00000>; - alignment = <0x1000>; - no-map; - }; }; }; @@ -235,141 +145,4 @@ }; }; -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - interrupts = <428>; - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - interrupts = <420>; - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c71_1: mbox-c71-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0 { - ti,cluster-mode = <0>; -}; - -&main_r5fss1 { - ti,cluster-mode = <0>; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status = "reserved"; -}; - -&main_timer1 { - status = "reserved"; -}; - -&main_timer2 { - status = "reserved"; -}; - -&main_timer3 { - status = "reserved"; -}; - -&main_timer4 { - status = "reserved"; -}; - -&main_timer5 { - status = "reserved"; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&c71_0 { - status = "okay"; - mboxes = <&mailbox0_cluster4 &mbox_c71_0>; - memory-region = <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; - -&c71_1 { - status = "okay"; - mboxes = <&mailbox0_cluster4 &mbox_c71_1>; - memory-region = <&c71_1_dma_memory_region>, - <&c71_1_memory_region>; -}; +#include "k3-j721s2-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index 612ac27643d2..5896e57b5b9e 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -49,149 +49,17 @@ no-map; }; - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - main_r5fss2_core0_memory_region: r5f-memory@a6100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - main_r5fss2_core1_memory_region: r5f-memory@a7100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: c71-dma-memory@a8000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: c71-memory@a8100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8100000 0x00 0xf00000>; - no-map; - }; - - c71_1_dma_memory_region: c71-dma-memory@a9000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa9000000 0x00 0x100000>; - no-map; - }; - - c71_1_memory_region: c71-memory@a9100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa9100000 0x00 0xf00000>; - no-map; - }; - - c71_2_dma_memory_region: c71-dma-memory@aa000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xaa000000 0x00 0x100000>; - no-map; - }; - - c71_2_memory_region: c71-memory@aa100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xaa100000 0x00 0xf00000>; - no-map; - }; - - c71_3_dma_memory_region: c71-dma-memory@ab000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xab000000 0x00 0x100000>; - no-map; - }; - - c71_3_memory_region: c71-memory@ab100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xab100000 0x00 0xf00000>; - no-map; - }; }; vusb_main: regulator-vusb-main5v0 { @@ -640,90 +508,6 @@ bootph-all; }; -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - interrupts = <428>; - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster3 { - status = "okay"; - interrupts = <424>; - mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - interrupts = <420>; - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c71_1: mbox-c71-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster5 { - status = "okay"; - interrupts = <416>; - mbox_c71_2: mbox-c71-2 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c71_3: mbox-c71-3 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - &wkup_uart0 { /* Firmware usage */ status = "reserved"; @@ -992,135 +776,6 @@ bootph-all; }; -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0 { - ti,cluster-mode = <0>; -}; - -&main_r5fss1 { - ti,cluster-mode = <0>; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status = "reserved"; -}; - -&main_timer1 { - status = "reserved"; -}; - -&main_timer2 { - status = "reserved"; -}; - -&main_timer3 { - status = "reserved"; -}; - -&main_timer4 { - status = "reserved"; -}; - -&main_timer5 { - status = "reserved"; -}; - -&main_timer6 { - status = "reserved"; -}; - -&main_timer7 { - status = "reserved"; -}; - -&main_timer8 { - status = "reserved"; -}; - -&main_timer9 { - status = "reserved"; -}; - -&main_r5fss2 { - ti,cluster-mode = <0>; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&main_r5fss2_core0 { - mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; - memory-region = <&main_r5fss2_core0_dma_memory_region>, - <&main_r5fss2_core0_memory_region>; -}; - -&main_r5fss2_core1 { - mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; - memory-region = <&main_r5fss2_core1_dma_memory_region>, - <&main_r5fss2_core1_memory_region>; -}; - -&c71_0 { - status = "okay"; - mboxes = <&mailbox0_cluster4 &mbox_c71_0>; - memory-region = <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; - -&c71_1 { - status = "okay"; - mboxes = <&mailbox0_cluster4 &mbox_c71_1>; - memory-region = <&c71_1_dma_memory_region>, - <&c71_1_memory_region>; -}; - -&c71_2 { - status = "okay"; - mboxes = <&mailbox0_cluster5 &mbox_c71_2>; - memory-region = <&c71_2_dma_memory_region>, - <&c71_2_memory_region>; -}; - -&c71_3 { - status = "okay"; - mboxes = <&mailbox0_cluster5 &mbox_c71_3>; - memory-region = <&c71_3_dma_memory_region>, - <&c71_3_memory_region>; -}; - &wkup_gpio_intr { status = "okay"; }; @@ -1321,12 +976,20 @@ &serdes0 { status = "okay"; - serdes0_pcie_link: phy@0 { + serdes0_pcie1_link: phy@0 { reg = <0>; - cdns,num-lanes = <3>; + cdns,num-lanes = <2>; #phy-cells = <0>; cdns,phy-type = <PHY_TYPE_PCIE>; - resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>, <&serdes_wiz0 3>; + resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; + }; + + serdes0_pcie3_link: phy@2 { + reg = <2>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_PCIE>; + resets = <&serdes_wiz0 3>; }; serdes0_usb_link: phy@3 { @@ -1364,7 +1027,7 @@ &pcie1_rc { status = "okay"; reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>; - phys = <&serdes0_pcie_link>; + phys = <&serdes0_pcie1_link>; phy-names = "pcie-phy"; num-lanes = <2>; }; @@ -1372,7 +1035,7 @@ &pcie3_rc { status = "okay"; reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; - phys = <&serdes0_pcie_link>; + phys = <&serdes0_pcie3_link>; phy-names = "pcie-phy"; num-lanes = <1>; }; @@ -1395,3 +1058,6 @@ phys = <&serdes0_usb_link>; phy-names = "cdns3,usb3-phy"; }; + +#include "k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi" +#include "k3-j784s4-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 5ce5f0a3d6f5..628ff89dd72f 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -1516,6 +1516,7 @@ ranges = <0x5c00000 0x00 0x5c00000 0x20000>, <0x5d00000 0x00 0x5d00000 0x20000>; power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; main_r5fss0_core0: r5f@5c00000 { compatible = "ti,j7200-r5f"; @@ -1530,6 +1531,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; main_r5fss0_core1: r5f@5d00000 { @@ -1545,6 +1547,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 56ab144fea07..692c4745040e 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -612,6 +612,7 @@ ranges = <0x41000000 0x00 0x41000000 0x20000>, <0x41400000 0x00 0x41400000 0x20000>; power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; mcu_r5fss0_core0: r5f@41000000 { compatible = "ti,j7200-r5f"; @@ -626,6 +627,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; mcu_r5fss0_core1: r5f@41400000 { @@ -641,6 +643,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index 291ab9bb414d..5a8c2e707fde 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -29,59 +29,17 @@ no-map; }; - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a4000000 { - reg = <0x00 0xa4000000 0x00 0x00800000>; - alignment = <0x1000>; - no-map; - }; }; mux0: mux-controller-0 { @@ -224,77 +182,6 @@ }; }; -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0 { - ti,cluster-mode = <0>; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status = "reserved"; -}; - -&main_timer1 { - status = "reserved"; -}; - -&main_timer2 { - status = "reserved"; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - &main_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; @@ -537,3 +424,5 @@ pinctrl-names = "default"; phys = <&transceiver0>; }; + +#include "k3-j7200-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j7200-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..9477f1efbbc6 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j7200-ti-ipc-firmware.dtsi @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on J7200 SoCs + * + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&reserved_memory { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: memory@a4000000 { + reg = <0x00 0xa4000000 0x00 0x00800000>; + alignment = <0x1000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status = "okay"; + interrupts = <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + interrupts = <432>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +/* Timers are used by Remoteproc firmware */ +&main_timer0 { + status = "reserved"; +}; + +&main_timer1 { + status = "reserved"; +}; + +&main_timer2 { + status = "reserved"; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; + status = "okay"; +}; + +&mcu_r5fss0_core1 { + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; + status = "okay"; +}; + +&main_r5fss0 { + ti,cluster-mode = <0>; + status = "okay"; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; + status = "okay"; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index fb899c99753e..352fb60e6ce8 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -51,119 +51,17 @@ no-map; }; - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - c66_0_dma_memory_region: c66-dma-memory@a6000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c66_0_memory_region: c66-memory@a6100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - c66_1_dma_memory_region: c66-dma-memory@a7000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c66_1_memory_region: c66-memory@a7100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: c71-dma-memory@a8000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: c71-memory@a8100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@aa000000 { - reg = <0x00 0xaa000000 0x00 0x01c00000>; - alignment = <0x1000>; - no-map; - }; }; gpio_keys: gpio-keys { @@ -865,129 +763,4 @@ status = "disabled"; }; -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - interrupts = <428>; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster3 { - status = "okay"; - interrupts = <424>; - - mbox_c66_0: mbox-c66-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c66_1: mbox-c66-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - interrupts = <420>; - - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&c66_0 { - status = "okay"; - mboxes = <&mailbox0_cluster3 &mbox_c66_0>; - memory-region = <&c66_0_dma_memory_region>, - <&c66_0_memory_region>; -}; - -&c66_1 { - status = "okay"; - mboxes = <&mailbox0_cluster3 &mbox_c66_1>; - memory-region = <&c66_1_dma_memory_region>, - <&c66_1_memory_region>; -}; - -&c71_0 { - status = "okay"; - mboxes = <&mailbox0_cluster4 &mbox_c71_0>; - memory-region = <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; +#include "k3-j721e-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 5bd0d36bf33e..d5fd30a01032 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -608,6 +608,9 @@ cdns_csi2rx0: csi-bridge@4504000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x0 0x4504000 0x0 0x1000>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>, <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", @@ -661,6 +664,9 @@ cdns_csi2rx1: csi-bridge@4514000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x0 0x4514000 0x0 0x1000>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>, <&k3_clks 27 2>, <&k3_clks 27 3>, <&k3_clks 27 3>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", @@ -1881,6 +1887,45 @@ }; }; + dphy2: phy@4480000 { + compatible = "ti,j721e-dphy"; + reg = <0x00 0x04480000 0x00 0x1000>; + clocks = <&k3_clks 296 1>, <&k3_clks 296 3>; + clock-names = "psm", "pll_ref"; + #phy-cells = <0>; + power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 296 3>; + assigned-clock-parents = <&k3_clks 296 4>; + assigned-clock-rates = <19200000>; + status = "disabled"; + }; + + dsi0: dsi@4800000 { + compatible = "ti,j721e-dsi"; + reg = <0x00 0x04800000 0x00 0x100000>, <0x00 0x04710000 0x00 0x100>; + clocks = <&k3_clks 150 1>, <&k3_clks 150 5>; + clock-names = "dsi_p_clk", "dsi_sys_clk"; + power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>; + interrupt-parent = <&gic500>; + interrupts = <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; + phys = <&dphy2>; + phy-names = "dphy"; + status = "disabled"; + + dsi0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + }; + }; + dss: dss@4a00000 { compatible = "ti,j721e-dss"; reg = @@ -2176,6 +2221,7 @@ ranges = <0x5c00000 0x00 0x5c00000 0x20000>, <0x5d00000 0x00 0x5d00000 0x20000>; power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; main_r5fss0_core0: r5f@5c00000 { compatible = "ti,j721e-r5f"; @@ -2190,6 +2236,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; main_r5fss0_core1: r5f@5d00000 { @@ -2205,6 +2252,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; @@ -2216,6 +2264,7 @@ ranges = <0x5e00000 0x00 0x5e00000 0x20000>, <0x5f00000 0x00 0x5f00000 0x20000>; power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; main_r5fss1_core0: r5f@5e00000 { compatible = "ti,j721e-r5f"; @@ -2230,6 +2279,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; main_r5fss1_core1: r5f@5f00000 { @@ -2245,6 +2295,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index b02142b2b460..42a21398e389 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -594,6 +594,7 @@ ranges = <0x41000000 0x00 0x41000000 0x20000>, <0x41400000 0x00 0x41400000 0x20000>; power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; mcu_r5fss0_core0: r5f@41000000 { compatible = "ti,j721e-r5f"; @@ -608,6 +609,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; mcu_r5fss0_core1: r5f@41400000 { @@ -623,6 +625,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index ffef3d1cfd55..5e5784ef6f85 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -48,119 +48,17 @@ no-map; }; - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - c66_0_dma_memory_region: c66-dma-memory@a6000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c66_0_memory_region: c66-memory@a6100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - c66_1_dma_memory_region: c66-dma-memory@a7000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c66_1_memory_region: c66-memory@a7100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: c71-dma-memory@a8000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: c71-memory@a8100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@aa000000 { - reg = <0x00 0xaa000000 0x00 0x01c00000>; - alignment = <0x1000>; - no-map; - }; }; vusb_main: fixedregulator-vusb-main5v0 { @@ -1279,166 +1177,4 @@ status = "disabled"; }; -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - interrupts = <428>; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster3 { - status = "okay"; - interrupts = <424>; - - mbox_c66_0: mbox-c66-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c66_1: mbox-c66-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - interrupts = <420>; - - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0 { - ti,cluster-mode = <0>; -}; - -&main_r5fss1 { - ti,cluster-mode = <0>; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status = "reserved"; -}; - -&main_timer1 { - status = "reserved"; -}; - -&main_timer2 { - status = "reserved"; -}; - -&main_timer12 { - status = "reserved"; -}; - -&main_timer13 { - status = "reserved"; -}; - -&main_timer14 { - status = "reserved"; -}; - -&main_timer15 { - status = "reserved"; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&c66_0 { - status = "okay"; - mboxes = <&mailbox0_cluster3 &mbox_c66_0>; - memory-region = <&c66_0_dma_memory_region>, - <&c66_0_memory_region>; -}; - -&c66_1 { - status = "okay"; - mboxes = <&mailbox0_cluster3 &mbox_c66_1>; - memory-region = <&c66_1_dma_memory_region>, - <&c66_1_memory_region>; -}; - -&c71_0 { - status = "okay"; - mboxes = <&mailbox0_cluster4 &mbox_c71_0>; - memory-region = <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; +#include "k3-j721e-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 0722f6361cc8..c8073ee634b7 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -29,119 +29,17 @@ no-map; }; - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - c66_1_dma_memory_region: c66-dma-memory@a6000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c66_0_memory_region: c66-memory@a6100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - c66_0_dma_memory_region: c66-dma-memory@a7000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c66_1_memory_region: c66-memory@a7100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: c71-dma-memory@a8000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: c71-memory@a8100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@aa000000 { - reg = <0x00 0xaa000000 0x00 0x01c00000>; - alignment = <0x1000>; - no-map; - }; }; }; @@ -484,166 +382,4 @@ }; }; -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - interrupts = <428>; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster3 { - status = "okay"; - interrupts = <424>; - - mbox_c66_0: mbox-c66-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c66_1: mbox-c66-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - interrupts = <420>; - - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0 { - ti,cluster-mode = <0>; -}; - -&main_r5fss1 { - ti,cluster-mode = <0>; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status = "reserved"; -}; - -&main_timer1 { - status = "reserved"; -}; - -&main_timer2 { - status = "reserved"; -}; - -&main_timer12 { - status = "reserved"; -}; - -&main_timer13 { - status = "reserved"; -}; - -&main_timer14 { - status = "reserved"; -}; - -&main_timer15 { - status = "reserved"; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&c66_0 { - status = "okay"; - mboxes = <&mailbox0_cluster3 &mbox_c66_0>; - memory-region = <&c66_0_dma_memory_region>, - <&c66_0_memory_region>; -}; - -&c66_1 { - status = "okay"; - mboxes = <&mailbox0_cluster3 &mbox_c66_1>; - memory-region = <&c66_1_dma_memory_region>, - <&c66_1_memory_region>; -}; - -&c71_0 { - status = "okay"; - mboxes = <&mailbox0_cluster4 &mbox_c71_0>; - memory-region = <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; +#include "k3-j721e-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j721e-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..40c6cc99c405 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-ti-ipc-firmware.dtsi @@ -0,0 +1,288 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on J721E SoCs + * + * Copyright (C) 2018-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&reserved_memory { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: memory@a5000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: memory@a5100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + /* Carveout locations are flipped due to caching */ + c66_1_dma_memory_region: memory@a6000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + c66_0_memory_region: memory@a6100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + /* Carveout locations are flipped due to caching */ + c66_0_dma_memory_region: memory@a7000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + c66_1_memory_region: memory@a7100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + + c71_0_dma_memory_region: memory@a8000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: memory@a8100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: memory@aa000000 { + reg = <0x00 0xaa000000 0x00 0x01c00000>; + alignment = <0x1000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status = "okay"; + interrupts = <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + interrupts = <432>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + interrupts = <428>; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster3 { + status = "okay"; + interrupts = <424>; + + mbox_c66_0: mbox-c66-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c66_1: mbox-c66-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster4 { + status = "okay"; + interrupts = <420>; + + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +/* Timers are used by Remoteproc firmware */ +&main_timer0 { + status = "reserved"; +}; + +&main_timer1 { + status = "reserved"; +}; + +&main_timer2 { + status = "reserved"; +}; + +&main_timer12 { + status = "reserved"; +}; + +&main_timer13 { + status = "reserved"; +}; + +&main_timer14 { + status = "reserved"; +}; + +&main_timer15 { + status = "reserved"; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; +}; + +&main_r5fss0 { + status = "okay"; + ti,cluster-mode = <0>; +}; + +&main_r5fss0_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1 { + status = "okay"; + ti,cluster-mode = <0>; +}; + +&main_r5fss1_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +&c66_0 { + status = "okay"; + mboxes = <&mailbox0_cluster3 &mbox_c66_0>; + memory-region = <&c66_0_dma_memory_region>, + <&c66_0_memory_region>; +}; + +&c66_1 { + status = "okay"; + mboxes = <&mailbox0_cluster3 &mbox_c66_1>; + memory-region = <&c66_1_dma_memory_region>, + <&c66_1_memory_region>; +}; + +&c71_0 { + status = "okay"; + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index e2fc1288ed07..9e43dcff8ef2 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -93,6 +93,28 @@ <3300000 0x1>; }; + dp1_pwr_3v3: regulator-dp1-prw { + compatible = "regulator-fixed"; + regulator-name = "dp1-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&exp4 1 GPIO_ACTIVE_HIGH>; /* P1 - DP1_PWR_SW_EN */ + enable-active-high; + }; + + dp1: connector-dp1 { + compatible = "dp-connector"; + label = "DP1"; + type = "full-size"; + dp-pwr-supply = <&dp1_pwr_3v3>; + + port { + dp1_connector_in: endpoint { + remote-endpoint = <&dp1_out>; + }; + }; + }; + transceiver1: can-phy1 { compatible = "ti,tcan1043"; #phy-cells = <0>; @@ -148,6 +170,13 @@ >; }; + main_i2c4_pins_default: main-i2c4-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) I2C4_SCL */ + J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) I2C4_SDA */ + >; + }; + main_i2c5_pins_default: main-i2c5-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x01c, PIN_INPUT, 8) /* (Y24) MCAN15_TX.I2C5_SCL */ @@ -370,6 +399,23 @@ }; }; +&main_i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c4_pins_default>; + clock-frequency = <400000>; + + exp4: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "DP0_PWR_SW_EN", "DP1_PWR_SW_EN", "UB981_PDB", + "UB981_GPIO0", "UB981_GPIO1", "UB981_GPIO2", + "UB981_GPIO3", "PWR_SW_CNTL_DSI0#"; + }; +}; + &main_i2c5 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c5_pins_default>; @@ -539,3 +585,74 @@ pinctrl-0 = <&main_mcan5_pins_default>; phys = <&transceiver4>; }; + +&dss { + /* + * DSS on J721S2-EVM supports DP on VP0 and DSI on VP2. + * These clock assignments are chosen to enable the following outputs: + * VP0 - DisplayPort SST + * VP2 - DSI + */ + status = "okay"; + assigned-clocks = <&k3_clks 158 2>, + <&k3_clks 158 14>; + assigned-clock-parents = <&k3_clks 158 3>, + <&k3_clks 158 16>; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + + dpi2_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; +}; + +&dsi0_ports { + port@0 { + reg = <0>; + + dsi0_out: endpoint { + remote-endpoint = <&dp1_in>; + }; + }; + + port@1 { + reg = <1>; + + dsi0_in: endpoint { + remote-endpoint = <&dpi2_out>; + }; + }; +}; + +&dsi_edp_bridge_ports { + port@0 { + reg = <0>; + + dp1_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + dp1_out: endpoint { + remote-endpoint = <&dp1_connector_in>; + }; + }; +}; + +&dphy_tx0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-evm-usb0-type-a.dtso b/arch/arm64/boot/dts/ti/k3-j721s2-evm-usb0-type-a.dtso new file mode 100644 index 000000000000..fe4a23efe708 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721s2-evm-usb0-type-a.dtso @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for enabling USB0 instance of USB in the Host Mode of operation + * with the Type-A Connector on the J7 common processor board. + * + * J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +&exp_som { + p0-hog { + /* P0 - USB2.0_MUX_SEL */ + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "USB2.0_MUX_SEL"; + }; +}; + +&usb0 { + dr_mode = "host"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 62f45377a2c9..80c51b11ac9f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -1248,6 +1248,9 @@ cdns_csi2rx0: csi-bridge@4504000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x04504000 0x00 0x1000>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 38 3>, <&k3_clks 38 1>, <&k3_clks 38 3>, <&k3_clks 38 3>, <&k3_clks 38 4>, <&k3_clks 38 4>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", @@ -1301,6 +1304,9 @@ cdns_csi2rx1: csi-bridge@4514000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x04514000 0x00 0x1000>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 39 3>, <&k3_clks 39 1>, <&k3_clks 39 3>, <&k3_clks 39 3>, <&k3_clks 39 4>, <&k3_clks 39 4>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", @@ -1431,6 +1437,7 @@ pcie1_intc: interrupt-controller { interrupt-controller; + #address-cells = <0>; #interrupt-cells = <1>; interrupt-parent = <&gic500>; interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>; @@ -1795,6 +1802,45 @@ status = "disabled"; }; + dphy_tx0: phy@4480000 { + compatible = "ti,j721e-dphy"; + reg = <0x00 0x04480000 0x00 0x00001000>; + clocks = <&k3_clks 363 8>, <&k3_clks 363 14>; + clock-names = "psm", "pll_ref"; + #phy-cells = <0>; + power-domains = <&k3_pds 363 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 363 14>; + assigned-clock-parents = <&k3_clks 363 15>; + assigned-clock-rates = <19200000>; + status = "disabled"; + }; + + dsi0: dsi@4800000 { + compatible = "ti,j721e-dsi"; + reg = <0x00 0x04800000 0x00 0x00100000>, + <0x00 0x04710000 0x00 0x00000100>; + clocks = <&k3_clks 154 4>, <&k3_clks 154 1>; + clock-names = "dsi_p_clk", "dsi_sys_clk"; + power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; + interrupts = <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; + phys = <&dphy_tx0>; + phy-names = "dphy"; + status = "disabled"; + + dsi0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + }; + }; + dss: dss@4a00000 { compatible = "ti,j721e-dss"; reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ @@ -1849,6 +1895,7 @@ ranges = <0x5c00000 0x00 0x5c00000 0x20000>, <0x5d00000 0x00 0x5d00000 0x20000>; power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; main_r5fss0_core0: r5f@5c00000 { compatible = "ti,j721s2-r5f"; @@ -1863,6 +1910,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; main_r5fss0_core1: r5f@5d00000 { @@ -1878,6 +1926,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; @@ -1889,6 +1938,7 @@ ranges = <0x5e00000 0x00 0x5e00000 0x20000>, <0x5f00000 0x00 0x5f00000 0x20000>; power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; main_r5fss1_core0: r5f@5e00000 { compatible = "ti,j721s2-r5f"; @@ -1903,6 +1953,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; main_r5fss1_core1: r5f@5f00000 { @@ -1918,6 +1969,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index bc31266126d0..837097751c18 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -690,6 +690,7 @@ ranges = <0x41000000 0x00 0x41000000 0x20000>, <0x41400000 0x00 0x41400000 0x20000>; power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; mcu_r5fss0_core0: r5f@41000000 { compatible = "ti,j721s2-r5f"; @@ -704,6 +705,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; mcu_r5fss0_core1: r5f@41400000 { @@ -719,6 +721,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi index 54fc5c4f8c3f..12a38dd1514b 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -31,107 +31,17 @@ no-map; }; - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: c71-dma-memory@a6000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: c71-memory@a6100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - c71_1_dma_memory_region: c71-dma-memory@a7000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c71_1_memory_region: c71-memory@a7100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a8000000 { - reg = <0x00 0xa8000000 0x00 0x01c00000>; - alignment = <0x1000>; - no-map; - }; }; mux0: mux-controller-0 { @@ -152,6 +62,30 @@ #phy-cells = <0>; max-bitrate = <5000000>; }; + + vsys_io_1v8: regulator-vsys-io-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_io_1v2: regulator-vsys-io-1v2 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + edp1_refclk: clock-edp1-refclk { + compatible = "fixed-clock"; + clock-frequency = <19200000>; + #clock-cells = <0>; + }; }; &wkup_pmx0 { @@ -492,141 +426,31 @@ }; }; -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - interrupts = <428>; - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; +&main_i2c4 { + bridge_dsi_edp: bridge-dsi-edp@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + clock-names = "refclk"; + clocks = <&edp1_refclk>; + enable-gpios = <&exp_som 5 0>; + vpll-supply = <&vsys_io_1v8>; + vccio-supply = <&vsys_io_1v8>; + vcca-supply = <&vsys_io_1v2>; + vcc-supply = <&vsys_io_1v2>; + + dsi_edp_bridge_ports: ports { + #address-cells = <1>; + #size-cells = <0>; -&mailbox0_cluster4 { - status = "okay"; - interrupts = <420>; - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; + port@0 { + reg = <0>; + }; - mbox_c71_1: mbox-c71-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; + port@1 { + reg = <1>; + }; + }; }; }; -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0 { - ti,cluster-mode = <0>; -}; - -&main_r5fss1 { - ti,cluster-mode = <0>; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status = "reserved"; -}; - -&main_timer1 { - status = "reserved"; -}; - -&main_timer2 { - status = "reserved"; -}; - -&main_timer3 { - status = "reserved"; -}; - -&main_timer4 { - status = "reserved"; -}; - -&main_timer5 { - status = "reserved"; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&c71_0 { - status = "okay"; - mboxes = <&mailbox0_cluster4 &mbox_c71_0>; - memory-region = <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; - -&c71_1 { - status = "okay"; - mboxes = <&mailbox0_cluster4 &mbox_c71_1>; - memory-region = <&c71_1_dma_memory_region>, - <&c71_1_memory_region>; -}; +#include "k3-j721s2-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..ebab0cc580bb --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721s2-ti-ipc-firmware.dtsi @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on J721S2 SoCs + * + * Copyright (C) 2021-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&reserved_memory { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: memory@a5000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: memory@a5100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + c71_0_dma_memory_region: memory@a6000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: memory@a6100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + c71_1_dma_memory_region: memory@a7000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + c71_1_memory_region: memory@a7100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: memory@a8000000 { + reg = <0x00 0xa8000000 0x00 0x01c00000>; + alignment = <0x1000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status = "okay"; + interrupts = <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + interrupts = <432>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + interrupts = <428>; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster4 { + status = "okay"; + interrupts = <420>; + + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c71_1: mbox-c71-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +/* Timers are used by Remoteproc firmware */ +&main_timer0 { + status = "reserved"; +}; + +&main_timer1 { + status = "reserved"; +}; + +&main_timer2 { + status = "reserved"; +}; + +&main_timer3 { + status = "reserved"; +}; + +&main_timer4 { + status = "reserved"; +}; + +&main_timer5 { + status = "reserved"; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; + status = "okay"; +}; + +&mcu_r5fss0_core1 { + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; + status = "okay"; +}; + +&main_r5fss0 { + ti,cluster-mode = <0>; + status = "okay"; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; + status = "okay"; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; + status = "okay"; +}; + +&main_r5fss1 { + ti,cluster-mode = <0>; + status = "okay"; +}; + +&main_r5fss1_core0 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; + status = "okay"; +}; + +&main_r5fss1_core1 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; + status = "okay"; +}; + +&c71_0 { + status = "okay"; + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; + +&c71_1 { + status = "okay"; + mboxes = <&mailbox0_cluster4 &mbox_c71_1>; + memory-region = <&c71_1_dma_memory_region>, + <&c71_1_memory_region>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts index 9d8abfa9afd2..e0e303da7e15 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -52,71 +52,17 @@ no-map; }; - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + wkup_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 { + wkup_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: main-r5fss-dma-memory-region@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: main-r5fss-memory-region@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - c7x_0_dma_memory_region: c7x-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - c7x_0_memory_region: c7x-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - c7x_1_dma_memory_region: c7x-dma-memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - c7x_1_memory_region: c7x-memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a5000000 { - reg = <0x00 0xa5000000 0x00 0x1c00000>; - alignment = <0x1000>; - no-map; - }; }; vmain_pd: regulator-0 { @@ -788,104 +734,6 @@ bootph-all; }; -&mailbox0_cluster0 { - status = "okay"; - - mbox_wkup_r5_0: mbox-wkup-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - - mbox_mcu_r5_0: mbox-mcu-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - - mbox_c7x_0: mbox-c7x-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster3 { - status = "okay"; - - mbox_main_r5_0: mbox-main-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c7x_1: mbox-c7x-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status = "reserved"; -}; - -&main_timer1 { - status = "reserved"; -}; - -&main_timer2 { - status = "reserved"; -}; - -&wkup_r5fss0 { - status = "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_wkup_r5_0>; - memory-region = <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0 { - status = "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&main_r5fss0 { - status = "okay"; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster3 &mbox_main_r5_0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&c7x_0 { - mboxes = <&mailbox0_cluster2 &mbox_c7x_0>; - memory-region = <&c7x_0_dma_memory_region>, - <&c7x_0_memory_region>; - status = "okay"; -}; - -&c7x_1 { - mboxes = <&mailbox0_cluster3 &mbox_c7x_1>; - memory-region = <&c7x_1_dma_memory_region>, - <&c7x_1_memory_region>; - status = "okay"; -}; - &serdes_ln_ctrl { idle-states = <J722S_SERDES0_LANE0_USB>, <J722S_SERDES1_LANE0_PCIE0_LANE0>; @@ -936,6 +784,10 @@ usb-role-switch; }; +&usb0_phy_ctrl { + bootph-all; +}; + &usbss1 { pinctrl-names = "default"; pinctrl-0 = <&main_usb1_pins_default>; @@ -996,3 +848,5 @@ clock-frequency = <400000>; status = "okay"; }; + +#include "k3-j722s-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi index 5cfa7bf36641..d57fdd38bdce 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -168,6 +168,9 @@ cdns_csi2rx1: csi-bridge@30121000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x30121000 0x00 0x1000>; + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 247 0>, <&k3_clks 247 3>, <&k3_clks 247 0>, <&k3_clks 247 0>, <&k3_clks 247 4>, <&k3_clks 247 4>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", @@ -221,6 +224,9 @@ cdns_csi2rx2: csi-bridge@30141000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x30141000 0x00 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 248 0>, <&k3_clks 248 3>, <&k3_clks 248 0>, <&k3_clks 248 0>, <&k3_clks 248 4>, <&k3_clks 248 4>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", @@ -274,6 +280,9 @@ cdns_csi2rx3: csi-bridge@30161000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x30161000 0x00 0x1000>; + interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 249 0>, <&k3_clks 249 3>, <&k3_clks 249 0>, <&k3_clks 249 0>, <&k3_clks 249 4>, <&k3_clks 249 4>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", @@ -359,6 +368,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; @@ -385,6 +395,16 @@ ti,sci-proc-ids = <0x31 0xff>; status = "disabled"; }; + + e5010: jpeg-encoder@fd20000 { + compatible = "ti,am62a-jpeg-enc", "img,e5010-jpeg-enc"; + reg = <0x00 0xfd20000 0x00 0x100>, + <0x00 0xfd20200 0x00 0x200>; + reg-names = "core", "mmu"; + clocks = <&k3_clks 201 0>; + power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + }; }; &main_bcdma_csi { diff --git a/arch/arm64/boot/dts/ti/k3-j722s-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..cb7cd385a165 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j722s-ti-ipc-firmware.dtsi @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on J722S SoCs + * + * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&reserved_memory { + mcu_r5fss0_core0_dma_memory_region: memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + c7x_0_dma_memory_region: memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + c7x_0_memory_region: memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + c7x_1_dma_memory_region: memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + c7x_1_memory_region: memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: memory@a5000000 { + reg = <0x00 0xa5000000 0x00 0x1c00000>; + alignment = <0x1000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status = "okay"; + + mbox_wkup_r5_0: mbox-wkup-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + + mbox_c7x_0: mbox-c7x-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster3 { + status = "okay"; + + mbox_main_r5_0: mbox-main-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c7x_1: mbox-c7x-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +/* Timers are used by Remoteproc firmware */ +&main_timer0 { + status = "reserved"; +}; + +&main_timer1 { + status = "reserved"; +}; + +&main_timer2 { + status = "reserved"; +}; + +&wkup_r5fss0 { + status = "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_wkup_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; + status = "okay"; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; + status = "okay"; +}; + +&main_r5fss0 { + status = "okay"; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster3 &mbox_main_r5_0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; + status = "okay"; +}; + +&c7x_0 { + mboxes = <&mailbox0_cluster2 &mbox_c7x_0>; + memory-region = <&c7x_0_dma_memory_region>, + <&c7x_0_memory_region>; + status = "okay"; +}; + +&c7x_1 { + mboxes = <&mailbox0_cluster3 &mbox_c7x_1>; + memory-region = <&c7x_1_dma_memory_region>, + <&c7x_1_memory_region>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi new file mode 100644 index 000000000000..61db2348d6a4 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree Source for J742S2 SoC Family + * + * TRM: https://www.ti.com/lit/pdf/spruje3 + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * + */ + +&mcu_r5fss0_core0 { + firmware-name = "j742s2-mcu-r5f0_0-fw"; +}; + +&mcu_r5fss0_core1 { + firmware-name = "j742s2-mcu-r5f0_1-fw"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j742s2.dtsi b/arch/arm64/boot/dts/ti/k3-j742s2.dtsi index 7a72f82f56d6..d265df1abade 100644 --- a/arch/arm64/boot/dts/ti/k3-j742s2.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j742s2.dtsi @@ -96,3 +96,4 @@ }; #include "k3-j742s2-main.dtsi" +#include "k3-j742s2-mcu-wakeup.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index a84bde08f85e..6c7458c76f53 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -27,31 +27,7 @@ reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; - - c71_3_dma_memory_region: c71-dma-memory@ab000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xab000000 0x00 0x100000>; - no-map; - }; - - c71_3_memory_region: c71-memory@ab100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xab100000 0x00 0xf00000>; - no-map; - }; - }; -}; - -&mailbox0_cluster5 { - mbox_c71_3: mbox-c71-3 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; }; }; -&c71_3 { - mboxes = <&mailbox0_cluster5 &mbox_c71_3>; - memory-region = <&c71_3_dma_memory_region>, - <&c71_3_memory_region>; - status = "okay"; -}; +#include "k3-j784s4-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi index fa656b7b13a1..419c1a70e028 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi @@ -35,137 +35,17 @@ no-map; }; - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - main_r5fss2_core0_memory_region: r5f-memory@a6100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - main_r5fss2_core1_memory_region: r5f-memory@a7100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: c71-dma-memory@a8000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: c71-memory@a8100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8100000 0x00 0xf00000>; - no-map; - }; - - c71_1_dma_memory_region: c71-dma-memory@a9000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa9000000 0x00 0x100000>; - no-map; - }; - - c71_1_memory_region: c71-memory@a9100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa9100000 0x00 0xf00000>; - no-map; - }; - - c71_2_dma_memory_region: c71-dma-memory@aa000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xaa000000 0x00 0x100000>; - no-map; - }; - - c71_2_memory_region: c71-memory@aa100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xaa100000 0x00 0xf00000>; - no-map; - }; }; evm_12v0: regulator-evm12v0 { @@ -301,6 +181,52 @@ clock-names = "cpb-mcasp-auxclk", "cpb-mcasp-auxclk-48000", "cpb-codec-scki", "cpb-codec-scki-48000"; }; + + vsys_io_1v8: regulator-vsys-io-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_io_1v2: regulator-vsys-io-1v2 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + edp1_refclk: clock-edp1-refclk { + compatible = "fixed-clock"; + clock-frequency = <19200000>; + #clock-cells = <0>; + }; + + dp1_pwr_3v3: regulator-dp1-prw { + compatible = "regulator-fixed"; + regulator-name = "dp1-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&exp4 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + dp1: connector-dp1 { + compatible = "dp-connector"; + label = "DP1"; + type = "full-size"; + dp-pwr-supply = <&dp1_pwr_3v3>; + + port { + dp1_connector_in: endpoint { + remote-endpoint = <&dp1_out>; + }; + }; + }; }; &wkup_gpio0 { @@ -1023,221 +949,6 @@ status = "okay"; }; -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - interrupts = <428>; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster3 { - status = "okay"; - interrupts = <424>; - - mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - interrupts = <420>; - - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c71_1: mbox-c71-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster5 { - status = "okay"; - interrupts = <416>; - - mbox_c71_2: mbox-c71-2 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mcu_r5fss0_core0 { - status = "okay"; - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - status = "okay"; - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0 { - ti,cluster-mode = <0>; -}; - -&main_r5fss1 { - ti,cluster-mode = <0>; -}; - -&main_r5fss2 { - ti,cluster-mode = <0>; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status = "reserved"; -}; - -&main_timer1 { - status = "reserved"; -}; - -&main_timer2 { - status = "reserved"; -}; - -&main_timer3 { - status = "reserved"; -}; - -&main_timer4 { - status = "reserved"; -}; - -&main_timer5 { - status = "reserved"; -}; - -&main_timer6 { - status = "reserved"; -}; - -&main_timer7 { - status = "reserved"; -}; - -&main_timer8 { - status = "reserved"; -}; - -&main_timer9 { - status = "reserved"; -}; - -&main_r5fss0_core0 { - status = "okay"; - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - status = "okay"; - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - status = "okay"; - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - status = "okay"; - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&main_r5fss2_core0 { - status = "okay"; - mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; - memory-region = <&main_r5fss2_core0_dma_memory_region>, - <&main_r5fss2_core0_memory_region>; -}; - -&main_r5fss2_core1 { - status = "okay"; - mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; - memory-region = <&main_r5fss2_core1_dma_memory_region>, - <&main_r5fss2_core1_memory_region>; -}; - -&c71_0 { - status = "okay"; - mboxes = <&mailbox0_cluster4 &mbox_c71_0>; - memory-region = <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; - -&c71_1 { - status = "okay"; - mboxes = <&mailbox0_cluster4 &mbox_c71_1>; - memory-region = <&c71_1_dma_memory_region>, - <&c71_1_memory_region>; -}; - -&c71_2 { - status = "okay"; - mboxes = <&mailbox0_cluster5 &mbox_c71_2>; - memory-region = <&c71_2_dma_memory_region>, - <&c71_2_memory_region>; -}; - &tscadc0 { pinctrl-0 = <&mcu_adc0_pins_default>; pinctrl-names = "default"; @@ -1340,12 +1051,26 @@ }; &dss_ports { + #address-cells = <1>; + #size-cells = <0>; + /* DP */ - port { + port@0 { + reg = <0>; + dpi0_out: endpoint { remote-endpoint = <&dp0_in>; }; }; + + /* DSI */ + port@2 { + reg = <2>; + + dpi2_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; }; &main_i2c4 { @@ -1360,6 +1085,65 @@ gpio-controller; #gpio-cells = <2>; }; + + bridge_dsi_edp: bridge-dsi-edp@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + clock-names = "refclk"; + clocks = <&edp1_refclk>; + enable-gpios = <&exp4 2 GPIO_ACTIVE_HIGH>; + vpll-supply = <&vsys_io_1v8>; + vccio-supply = <&vsys_io_1v8>; + vcca-supply = <&vsys_io_1v2>; + vcc-supply = <&vsys_io_1v2>; + + dsi_edp_bridge_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dp1_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + dp1_out: endpoint { + remote-endpoint = <&dp1_connector_in>; + }; + }; + }; + }; +}; + +&dsi0_ports { + port@0 { + reg = <0>; + + dsi0_out: endpoint { + remote-endpoint = <&dp1_in>; + }; + }; + + port@1 { + reg = <1>; + + dsi0_in: endpoint { + remote-endpoint = <&dpi2_out>; + }; + }; +}; + +&dphy_tx0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; }; &dp0_ports { @@ -1493,3 +1277,5 @@ 0 0 0 0 >; }; + +#include "k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi index 7c5b0c69897d..9cc0901d58fb 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi @@ -819,6 +819,9 @@ cdns_csi2rx0: csi-bridge@4504000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x04504000 0x00 0x00001000>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 72 2>, <&k3_clks 72 0>, <&k3_clks 72 2>, <&k3_clks 72 2>, <&k3_clks 72 3>, <&k3_clks 72 3>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", @@ -872,6 +875,9 @@ cdns_csi2rx1: csi-bridge@4514000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x04514000 0x00 0x00001000>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 73 2>, <&k3_clks 73 0>, <&k3_clks 73 2>, <&k3_clks 73 2>, <&k3_clks 73 3>, <&k3_clks 73 3>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", @@ -924,6 +930,9 @@ cdns_csi2rx2: csi-bridge@4524000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x04524000 0x00 0x00001000>; + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 74 2>, <&k3_clks 74 0>, <&k3_clks 74 2>, <&k3_clks 74 2>, <&k3_clks 74 3>, <&k3_clks 74 3>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", @@ -2165,6 +2174,7 @@ ranges = <0x5c00000 0x00 0x5c00000 0x20000>, <0x5d00000 0x00 0x5d00000 0x20000>; power-domains = <&k3_pds 336 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; main_r5fss0_core0: r5f@5c00000 { compatible = "ti,j721s2-r5f"; @@ -2179,6 +2189,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; main_r5fss0_core1: r5f@5d00000 { @@ -2194,6 +2205,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; @@ -2205,6 +2217,7 @@ ranges = <0x5e00000 0x00 0x5e00000 0x20000>, <0x5f00000 0x00 0x5f00000 0x20000>; power-domains = <&k3_pds 337 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; main_r5fss1_core0: r5f@5e00000 { compatible = "ti,j721s2-r5f"; @@ -2219,6 +2232,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; main_r5fss1_core1: r5f@5f00000 { @@ -2234,6 +2248,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; @@ -2245,6 +2260,7 @@ ranges = <0x5900000 0x00 0x5900000 0x20000>, <0x5a00000 0x00 0x5a00000 0x20000>; power-domains = <&k3_pds 338 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; main_r5fss2_core0: r5f@5900000 { compatible = "ti,j721s2-r5f"; @@ -2259,6 +2275,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; main_r5fss2_core1: r5f@5a00000 { @@ -2274,6 +2291,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; @@ -2522,6 +2540,45 @@ status = "reserved"; }; + dphy_tx0: phy@4480000 { + compatible = "ti,j721e-dphy"; + reg = <0x00 0x04480000 0x00 0x00001000>; + clocks = <&k3_clks 402 20>, <&k3_clks 402 3>; + clock-names = "psm", "pll_ref"; + #phy-cells = <0>; + power-domains = <&k3_pds 402 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 402 3>; + assigned-clock-parents = <&k3_clks 402 4>; + assigned-clock-rates = <19200000>; + status = "disabled"; + }; + + dsi0: dsi@4800000 { + compatible = "ti,j721e-dsi"; + reg = <0x00 0x04800000 0x00 0x00100000>, + <0x00 0x04710000 0x00 0x00000100>; + clocks = <&k3_clks 215 2>, <&k3_clks 215 5>; + clock-names = "dsi_p_clk", "dsi_sys_clk"; + power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>; + interrupts = <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; + phys = <&dphy_tx0>; + phy-names = "dphy"; + status = "disabled"; + + dsi0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + }; + }; + mhdp: bridge@a000000 { compatible = "ti,j721e-mhdp8546"; reg = <0x0 0xa000000 0x0 0x30a00>, diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi index 52e2965a3bf5..cc22bfb5f599 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi @@ -595,6 +595,7 @@ ranges = <0x41000000 0x00 0x41000000 0x20000>, <0x41400000 0x00 0x41400000 0x20000>; power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; mcu_r5fss0_core0: r5f@41000000 { compatible = "ti,j721s2-r5f"; @@ -609,6 +610,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; mcu_r5fss0_core1: r5f@41400000 { @@ -624,6 +626,7 @@ ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi new file mode 100644 index 000000000000..455397227d4a --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi @@ -0,0 +1,350 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on J784S4/J742S2 SoCs + * + * Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&reserved_memory { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: memory@a5000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: memory@a5100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss2_core0_dma_memory_region: memory@a6000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + main_r5fss2_core0_memory_region: memory@a6100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss2_core1_dma_memory_region: memory@a7000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + main_r5fss2_core1_memory_region: memory@a7100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + + c71_0_dma_memory_region: memory@a8000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: memory@a8100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8100000 0x00 0xf00000>; + no-map; + }; + + c71_1_dma_memory_region: memory@a9000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa9000000 0x00 0x100000>; + no-map; + }; + + c71_1_memory_region: memory@a9100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa9100000 0x00 0xf00000>; + no-map; + }; + + c71_2_dma_memory_region: memory@aa000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xaa000000 0x00 0x100000>; + no-map; + }; + + c71_2_memory_region: memory@aa100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xaa100000 0x00 0xf00000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status = "okay"; + interrupts = <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + interrupts = <432>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + interrupts = <428>; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster3 { + status = "okay"; + interrupts = <424>; + + mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster4 { + status = "okay"; + interrupts = <420>; + + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c71_1: mbox-c71-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster5 { + status = "okay"; + interrupts = <416>; + + mbox_c71_2: mbox-c71-2 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +/* Timers are used by Remoteproc firmware */ +&main_timer0 { + status = "reserved"; +}; + +&main_timer1 { + status = "reserved"; +}; + +&main_timer2 { + status = "reserved"; +}; + +&main_timer3 { + status = "reserved"; +}; + +&main_timer4 { + status = "reserved"; +}; + +&main_timer5 { + status = "reserved"; +}; + +&main_timer6 { + status = "reserved"; +}; + +&main_timer7 { + status = "reserved"; +}; + +&main_timer8 { + status = "reserved"; +}; + +&main_timer9 { + status = "reserved"; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; +}; + +&main_r5fss0 { + ti,cluster-mode = <0>; + status = "okay"; +}; + +&main_r5fss0_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1 { + ti,cluster-mode = <0>; + status = "okay"; +}; + +&main_r5fss1_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +&main_r5fss2 { + ti,cluster-mode = <0>; + status = "okay"; +}; + +&main_r5fss2_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; + memory-region = <&main_r5fss2_core0_dma_memory_region>, + <&main_r5fss2_core0_memory_region>; +}; + +&main_r5fss2_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; + memory-region = <&main_r5fss2_core1_dma_memory_region>, + <&main_r5fss2_core1_memory_region>; +}; + +&c71_0 { + status = "okay"; + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; + +&c71_1 { + status = "okay"; + mboxes = <&mailbox0_cluster4 &mbox_c71_1>; + memory-region = <&c71_1_dma_memory_region>, + <&c71_1_memory_region>; +}; + +&c71_2 { + status = "okay"; + mboxes = <&mailbox0_cluster5 &mbox_c71_2>; + memory-region = <&c71_2_dma_memory_region>, + <&c71_2_memory_region>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..81b508b9b05e --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-ti-ipc-firmware.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on J784S4 SoCs + * + * Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&reserved_memory { + c71_3_dma_memory_region: memory@ab000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xab000000 0x00 0x100000>; + no-map; + }; + + c71_3_memory_region: memory@ab100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xab100000 0x00 0xf00000>; + no-map; + }; +}; + +&mailbox0_cluster5 { + + mbox_c71_3: mbox-c71-3 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&c71_3 { + mboxes = <&mailbox0_cluster5 &mbox_c71_3>; + memory-region = <&c71_3_dma_memory_region>, + <&c71_3_memory_region>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k3-pinctrl.h index c0f09be8d3f9..e46f7bf52701 100644 --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h @@ -3,15 +3,20 @@ * This header provides constants for pinctrl bindings for TI's K3 SoC * family. * - * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2018-2025 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef DTS_ARM64_TI_K3_PINCTRL_H #define DTS_ARM64_TI_K3_PINCTRL_H +#define WKUP_LVL_EN_SHIFT (7) +#define WKUP_LVL_POL_SHIFT (8) #define ST_EN_SHIFT (14) #define PULLUDEN_SHIFT (16) #define PULLTYPESEL_SHIFT (17) #define RXACTIVE_SHIFT (18) +#define DRV_STR_SHIFT (19) +#define ISO_OVERRIDE_EN_SHIFT (22) +#define ISO_BYPASS_EN_SHIFT (23) #define DEBOUNCE_SHIFT (11) #define FORCE_DS_EN_SHIFT (15) #define DS_EN_SHIFT (24) @@ -19,6 +24,7 @@ #define DS_OUT_VAL_SHIFT (26) #define DS_PULLUD_EN_SHIFT (27) #define DS_PULLTYPE_SEL_SHIFT (28) +#define WKUP_EN_SHIFT (29) /* Schmitt trigger configuration */ #define ST_DISABLE (0 << ST_EN_SHIFT) @@ -33,6 +39,29 @@ #define INPUT_EN (1 << RXACTIVE_SHIFT) #define INPUT_DISABLE (0 << RXACTIVE_SHIFT) +#define DS_PULL_DISABLE (1 << DS_PULLUD_EN_SHIFT) +#define DS_PULL_ENABLE (0 << DS_PULLUD_EN_SHIFT) + +#define DS_PULL_UP (1 << DS_PULLTYPE_SEL_SHIFT | DS_PULL_ENABLE) +#define DS_PULL_DOWN (0 << DS_PULLTYPE_SEL_SHIFT | DS_PULL_ENABLE) + +#define DS_STATE_EN (1 << DS_EN_SHIFT) +#define DS_STATE_DISABLE (0 << DS_EN_SHIFT) + +#define DS_INPUT_EN (1 << DS_OUT_DIS_SHIFT | DS_STATE_EN) +#define DS_INPUT_DISABLE (0 << DS_OUT_DIS_SHIFT | DS_STATE_EN) + +#define DS_OUT_VALUE_ZERO (0 << DS_OUT_VAL_SHIFT) +#define DS_OUT_VALUE_ONE (1 << DS_OUT_VAL_SHIFT) + +/* Configuration to enable wake-up on pin activity */ +#define WKUP_ENABLE (1 << WKUP_EN_SHIFT) +#define WKUP_DISABLE (0 << WKUP_EN_SHIFT) +#define WKUP_ON_LEVEL (1 << WKUP_LVL_EN_SHIFT) +#define WKUP_ON_EDGE (0 << WKUP_LVL_EN_SHIFT) +#define WKUP_LEVEL_LOW (0 << WKUP_LVL_POL_SHIFT) +#define WKUP_LEVEL_HIGH (1 << WKUP_LVL_POL_SHIFT) + /* Only these macros are expected be used directly in device tree files */ #define PIN_OUTPUT (INPUT_DISABLE | PULL_DISABLE) #define PIN_OUTPUT_PULLUP (INPUT_DISABLE | PULL_UP) @@ -53,10 +82,14 @@ #define PIN_DEBOUNCE_CONF5 (5 << DEBOUNCE_SHIFT) #define PIN_DEBOUNCE_CONF6 (6 << DEBOUNCE_SHIFT) +#define PIN_DRIVE_STRENGTH_NOMINAL (0 << DRV_STR_SHIFT) +#define PIN_DRIVE_STRENGTH_SLOW (1 << DRV_STR_SHIFT) +#define PIN_DRIVE_STRENGTH_FAST (2 << DRV_STR_SHIFT) + #define PIN_DS_FORCE_DISABLE (0 << FORCE_DS_EN_SHIFT) #define PIN_DS_FORCE_ENABLE (1 << FORCE_DS_EN_SHIFT) -#define PIN_DS_IO_OVERRIDE_DISABLE (0 << DS_IO_OVERRIDE_EN_SHIFT) -#define PIN_DS_IO_OVERRIDE_ENABLE (1 << DS_IO_OVERRIDE_EN_SHIFT) +#define PIN_DS_ISO_OVERRIDE_DISABLE (0 << ISO_OVERRIDE_EN_SHIFT) +#define PIN_DS_ISO_OVERRIDE_ENABLE (1 << ISO_OVERRIDE_EN_SHIFT) #define PIN_DS_OUT_ENABLE (0 << DS_OUT_DIS_SHIFT) #define PIN_DS_OUT_DISABLE (1 << DS_OUT_DIS_SHIFT) #define PIN_DS_OUT_VALUE_ZERO (0 << DS_OUT_VAL_SHIFT) @@ -65,6 +98,18 @@ #define PIN_DS_PULLUD_DISABLE (1 << DS_PULLUD_EN_SHIFT) #define PIN_DS_PULL_DOWN (0 << DS_PULLTYPE_SEL_SHIFT) #define PIN_DS_PULL_UP (1 << DS_PULLTYPE_SEL_SHIFT) +#define PIN_DS_ISO_BYPASS (1 << ISO_BYPASS_EN_SHIFT) +#define PIN_DS_ISO_BYPASS_DISABLE (0 << ISO_BYPASS_EN_SHIFT) + +#define PIN_DS_OUTPUT_LOW (DS_INPUT_DISABLE | DS_OUT_VALUE_ZERO) +#define PIN_DS_OUTPUT_HIGH (DS_INPUT_DISABLE | DS_OUT_VALUE_ONE) +#define PIN_DS_INPUT (DS_INPUT_EN | DS_PULL_DISABLE) +#define PIN_DS_INPUT_PULLUP (DS_INPUT_EN | DS_PULL_UP) +#define PIN_DS_INPUT_PULLDOWN (DS_INPUT_EN | DS_PULL_DOWN) + +#define PIN_WKUP_EN_LEVEL_LOW (WKUP_ENABLE | WKUP_ON_LEVEL | WKUP_LEVEL_LOW) +#define PIN_WKUP_EN_LEVEL_HIGH (WKUP_ENABLE | WKUP_ON_LEVEL | WKUP_LEVEL_HIGH) +#define PIN_WKUP_EN (WKUP_ENABLE | WKUP_ON_EDGE) /* Default mux configuration for gpio-ranges to use with pinctrl */ #define PIN_GPIO_RANGE_IOPAD (PIN_INPUT | 7) diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi index 39806f0ae513..9aa7b1872bd6 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi @@ -152,6 +152,7 @@ gic: interrupt-controller@24001000 { compatible = "arm,gic-400"; interrupt-controller; + #address-cells = <0>; #interrupt-cells = <3>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; reg = <0 0x24001000 0 0x1000>, diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile index 7f5a8801cad1..70fac0b276df 100644 --- a/arch/arm64/boot/dts/xilinx/Makefile +++ b/arch/arm64/boot/dts/xilinx/Makefile @@ -30,4 +30,28 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kv-g-revA.dtb zynqmp-smk-k26-revA-sck-kv-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kv-g-revB.dtb +zynqmp-sm-k26-revA-sck-kr-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kr-g-revA.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kr-g-revA.dtb +zynqmp-sm-k26-revA-sck-kr-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kr-g-revB.dtb +zynqmp-smk-k26-revA-sck-kr-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revA.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kr-g-revA.dtb +zynqmp-smk-k26-revA-sck-kr-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kr-g-revB.dtb + +zynqmp-sm-k24-revA-sck-kd-g-revA-dtbs := zynqmp-sm-k24-revA.dtb zynqmp-sck-kd-g-revA.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kd-g-revA.dtb +zynqmp-smk-k24-revA-sck-kd-g-revA-dtbs := zynqmp-smk-k24-revA.dtb zynqmp-sck-kd-g-revA.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kd-g-revA.dtb + +zynqmp-sm-k24-revA-sck-kv-g-revB-dtbs := zynqmp-sm-k24-revA.dtb zynqmp-sck-kv-g-revB.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kv-g-revB.dtb +zynqmp-smk-k24-revA-sck-kv-g-revB-dtbs := zynqmp-smk-k24-revA.dtb zynqmp-sck-kv-g-revB.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kv-g-revB.dtb + +zynqmp-sm-k24-revA-sck-kr-g-revB-dtbs := zynqmp-sm-k24-revA.dtb zynqmp-sck-kr-g-revB.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kr-g-revB.dtb +zynqmp-smk-k24-revA-sck-kr-g-revB-dtbs := zynqmp-smk-k24-revA.dtb zynqmp-sck-kr-g-revB.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kr-g-revB.dtb + dtb-$(CONFIG_ARCH_ZYNQMP) += versal-net-vn-x-b2197-01-revA.dtb diff --git a/arch/arm64/boot/dts/xilinx/versal-net.dtsi b/arch/arm64/boot/dts/xilinx/versal-net.dtsi index fc9f49e57385..412af9a394aa 100644 --- a/arch/arm64/boot/dts/xilinx/versal-net.dtsi +++ b/arch/arm64/boot/dts/xilinx/versal-net.dtsi @@ -104,6 +104,28 @@ reg = <0>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_00>; + l2_00: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_0>; + }; }; cpu100: cpu@100 { compatible = "arm,cortex-a78"; @@ -112,6 +134,28 @@ reg = <0x100>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_01>; + l2_01: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_0>; + }; }; cpu200: cpu@200 { compatible = "arm,cortex-a78"; @@ -120,6 +164,28 @@ reg = <0x200>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_02>; + l2_02: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_0>; + }; }; cpu300: cpu@300 { compatible = "arm,cortex-a78"; @@ -128,6 +194,28 @@ reg = <0x300>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_03>; + l2_03: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_0>; + }; }; cpu10000: cpu@10000 { compatible = "arm,cortex-a78"; @@ -136,6 +224,28 @@ reg = <0x10000>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_10>; + l2_10: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_1>; + }; }; cpu10100: cpu@10100 { compatible = "arm,cortex-a78"; @@ -144,6 +254,28 @@ reg = <0x10100>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_11>; + l2_11: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_1>; + }; }; cpu10200: cpu@10200 { compatible = "arm,cortex-a78"; @@ -152,6 +284,28 @@ reg = <0x10200>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_12>; + l2_12: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_1>; + }; }; cpu10300: cpu@10300 { compatible = "arm,cortex-a78"; @@ -160,6 +314,28 @@ reg = <0x10300>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_13>; + l2_13: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_1>; + }; }; cpu20000: cpu@20000 { compatible = "arm,cortex-a78"; @@ -168,6 +344,28 @@ reg = <0x20000>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_20>; + l2_20: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_2>; + }; }; cpu20100: cpu@20100 { compatible = "arm,cortex-a78"; @@ -176,6 +374,28 @@ reg = <0x20100>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_21>; + l2_21: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_2>; + }; }; cpu20200: cpu@20200 { compatible = "arm,cortex-a78"; @@ -184,6 +404,28 @@ reg = <0x20200>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_22>; + l2_22: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_2>; + }; }; cpu20300: cpu@20300 { compatible = "arm,cortex-a78"; @@ -192,6 +434,28 @@ reg = <0x20300>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_23>; + l2_23: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_2>; + }; }; cpu30000: cpu@30000 { compatible = "arm,cortex-a78"; @@ -200,6 +464,28 @@ reg = <0x30000>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_30>; + l2_30: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_3>; + }; }; cpu30100: cpu@30100 { compatible = "arm,cortex-a78"; @@ -208,6 +494,28 @@ reg = <0x30100>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_31>; + l2_31: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_3>; + }; }; cpu30200: cpu@30200 { compatible = "arm,cortex-a78"; @@ -216,6 +524,28 @@ reg = <0x30200>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_32>; + l2_32: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_3>; + }; }; cpu30300: cpu@30300 { compatible = "arm,cortex-a78"; @@ -224,7 +554,85 @@ reg = <0x30300>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_33>; + l2_33: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_3>; + }; + }; + + l3_0: l3-0-cache { /* cluster private */ + compatible = "cache"; + cache-level = <3>; + cache-size = <0x200000>; /* 2MB */ + cache-line-size = <64>; + /* 16 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <2048>; + cache-unified; + next-level-cache = <&llc>; + }; + + l3_1: l3-1-cache { /* cluster private */ + compatible = "cache"; + cache-level = <3>; + cache-size = <0x200000>; /* 2MB */ + cache-line-size = <64>; + /* 16 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <2048>; + cache-unified; + next-level-cache = <&llc>; + }; + + l3_2: l3-2-cache { /* cluster private */ + compatible = "cache"; + cache-level = <3>; + cache-size = <0x200000>; /* 2MB */ + cache-line-size = <64>; + /* 16 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <2048>; + cache-unified; + next-level-cache = <&llc>; + }; + + l3_3: l3-3-cache { /* cluster private */ + compatible = "cache"; + cache-level = <3>; + cache-size = <0x200000>; /* 2MB */ + cache-line-size = <64>; + /* 16 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <2048>; + cache-unified; + next-level-cache = <&llc>; + }; + + llc: l4-cache { /* LLC inside CMN */ + compatible = "cache"; + cache-level = <4>; + cache-size = <0x1000000>; /* 16MB */ + cache-unified; }; + idle-states { entry-method = "psci"; @@ -556,7 +964,7 @@ reg = <0 0xf12a0000 0 0x100>; interrupts = <0 200 4>, <0 201 4>; interrupt-names = "alarm", "sec"; - calibration = <0x8000>; + calibration = <0x7FFF>; }; sdhci0: mmc@f1040000 { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso new file mode 100644 index 000000000000..02be5e1e8686 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso @@ -0,0 +1,390 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for KD240 revA Carrier Card + * + * Copyright (C) 2021 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "xlnx,zynqmp-sk-kd240-rev1", + "xlnx,zynqmp-sk-kd240-revB", + "xlnx,zynqmp-sk-kd240-revA", + "xlnx,zynqmp-sk-kd240", "xlnx,zynqmp"; + model = "ZynqMP KD240 revA/B/1"; + + aliases { + ethernet0 = "/axi/ethernet@ff0c0000"; /* &gem1 */ + }; + + ina260-u3 { + compatible = "iio-hwmon"; + io-channels = <&u3 0>, <&u3 1>, <&u3 2>; + }; + + clk_26: clock2 { /* u17 - USB */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + clk_25_0: clock4 { /* u92/u91 - GEM2 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + clk_25_1: clock5 { /* u92/u91 - GEM3 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&can0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_default>; +}; + +&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + u3: ina260@40 { /* u3 */ + compatible = "ti,ina260"; + #io-channel-cells = <1>; + label = "ina260-u14"; + reg = <0x40>; + }; + + slg7xl45106: gpio@11 { /* u13 - reset logic */ + compatible = "dlg,slg7xl45106"; + reg = <0x11>; + label = "resetchip"; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "USB0_PHY_RESET_B", "", + "SD_RESET_B", "USB0_HUB_RESET_B", + "", "PS_GEM0_RESET_B", + "", ""; + }; + + hub: usb-hub@2d { /* u36 */ + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; +}; + +/* USB 3.0 */ +&psgtr { + status = "okay"; + /* usb */ + clocks = <&clk_26>; + clock-names = "ref2"; +}; + +&usb0 { /* mio52 - mio63 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; + reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>; + assigned-clock-rates = <250000000>, <20000000>; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub_3_0>; + i2c-bus = <&hub>; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub_2_0>; + i2c-bus = <&hub>; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; +}; + +&gem1 { /* mdio mio50/51 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem1_default>; + assigned-clock-rates = <250000000>; + + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@8 { /* Adin u31 */ + #phy-cells = <1>; + compatible = "ethernet-phy-id0283.bc30"; + reg = <8>; + adi,rx-internal-delay-ps = <2000>; + adi,tx-internal-delay-ps = <2000>; + adi,fifo-depth-bits = <8>; + reset-assert-us = <10>; + reset-deassert-us = <5000>; + reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>; + }; + }; +}; + +/* 2 more ethernet phys u32@2 and u34@3 */ + +&pinctrl0 { /* required by spec */ + status = "okay"; + + pinctrl_can0_default: can0-default { + mux { + function = "can0"; + groups = "can0_16_grp"; + }; + + conf { + groups = "can0_16_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO66"; + bias-pull-up; + }; + + conf-tx { + pins = "MIO67"; + bias-pull-up; + drive-strength = <4>; + }; + }; + + pinctrl_uart0_default: uart0-default { + conf { + groups = "uart0_17_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO70"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO71"; + bias-disable; + }; + + mux { + groups = "uart0_17_grp"; + function = "uart0"; + }; + }; + + pinctrl_uart1_default: uart1-default { + conf { + groups = "uart1_9_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO37"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO36"; + bias-disable; + output-enable; + }; + + mux { + groups = "uart1_9_grp"; + function = "uart1"; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + conf { + groups = "i2c1_6_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "i2c1_6_grp"; + function = "i2c1"; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + conf { + groups = "gpio0_24_grp", "gpio0_25_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "gpio0_24_grp", "gpio0_25_grp"; + function = "gpio0"; + }; + }; + + pinctrl_gem1_default: gem1-default { + conf { + groups = "ethernet1_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO45", "MIO46", "MIO47", "MIO48"; + bias-disable; + low-power-disable; + }; + + conf-bootstrap { + pins = "MIO44", "MIO49"; + bias-disable; + output-enable; + low-power-disable; + }; + + conf-tx { + pins = "MIO38", "MIO39", "MIO40", + "MIO41", "MIO42", "MIO43"; + bias-disable; + output-enable; + low-power-enable; + }; + + conf-mdio { + groups = "mdio1_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + bias-disable; + output-enable; + }; + + mux-mdio { + function = "mdio1"; + groups = "mdio1_0_grp"; + }; + + mux { + function = "ethernet1"; + groups = "ethernet1_0_grp"; + }; + }; + + pinctrl_usb0_default: usb0-default { + conf { + groups = "usb0_0_grp"; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + drive-strength = <12>; + slew-rate = <SLEW_RATE_FAST>; + }; + + conf-tx { + pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + output-enable; + drive-strength = <4>; + slew-rate = <SLEW_RATE_SLOW>; + }; + + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + }; + + pinctrl_usb1_default: usb1-default { + conf { + groups = "usb1_0_grp"; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO64", "MIO65", "MIO67"; + bias-high-impedance; + drive-strength = <12>; + slew-rate = <SLEW_RATE_FAST>; + }; + + conf-tx { + pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", + "MIO72", "MIO73", "MIO74", "MIO75"; + bias-disable; + output-enable; + drive-strength = <4>; + slew-rate = <SLEW_RATE_SLOW>; + }; + + mux { + groups = "usb1_0_grp"; + function = "usb1"; + }; + }; +}; + +&uart0 { + status = "okay"; + rts-gpios = <&gpio 72 GPIO_ACTIVE_HIGH>; + linux,rs485-enabled-at-boot-time; + rs485-rts-delay = <10 10>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0_default>; + assigned-clock-rates = <100000000>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; +}; + +&zynqmp_dpsub { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso new file mode 100644 index 000000000000..b92dcb86e87e --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso @@ -0,0 +1,455 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for KR260 revA Carrier Card + * + * (C) Copyright 2021, Xilinx, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/net/ti-dp83867.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "xlnx,zynqmp-sk-kr260-revA", + "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp"; + model = "ZynqMP KR260 revA"; + + aliases { + ethernet0 = "/axi/ethernet@ff0b0000"; /* &gem0 */ + ethernet1 = "/axi/ethernet@ff0c0000"; /* &gem1 */ + }; + + ina260-u14 { + compatible = "iio-hwmon"; + io-channels = <&u14 0>, <&u14 1>, <&u14 2>; + }; + + clk_27: clock0 { /* u86 - DP */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; + + clk_125: si5332-0 { /* u17 - GEM0/1 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + clk_74: si5332-5 { /* u17 - SLVC-EC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <74250000>; + }; + + clk_26: si5332-2 { /* u17 - USB */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + clk_156: si5332-3 { /* u17 - SFP+ */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <156250000>; + }; + + clk_25_0: si5332-1 { /* u17 - GEM2 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + clk_25_1: si5332-4 { /* u17 - GEM3 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; +}; + +&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + u14: ina260@40 { /* u14 */ + compatible = "ti,ina260"; + #io-channel-cells = <1>; + label = "ina260-u14"; + reg = <0x40>; + }; + + slg7xl45106: gpio@11 { /* u19 - reset logic */ + compatible = "dlg,slg7xl45106"; + reg = <0x11>; + label = "resetchip"; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B", + "SD_RESET_B", "USB0_HUB_RESET_B", + "USB1_HUB_RESET_B", "PS_GEM0_RESET_B", + "PS_GEM1_RESET_B", ""; + }; + + i2c-mux@74 { /* u18 */ + compatible = "nxp,pca9546"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + usbhub_i2c0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + hub_1: usb-hub@2d { + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; + }; + usbhub_i2c1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + hub_2: usb-hub@2d { + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; + }; + /* Bus 2/3 are not connected */ + }; + + /* si5332@6a - u17 - clock-generator */ +}; + +/* GEM SGMII/DP and USB 3.0 */ +&psgtr { + status = "okay"; + /* gem0/1, dp, usb */ + clocks = <&clk_125>, <&clk_27>, <&clk_26>; + clock-names = "ref0", "ref1", "ref2"; +}; + +&zynqmp_dpsub { + status = "okay"; + phy-names = "dp-phy0"; + phys = <&psgtr 1 PHY_TYPE_DP 0 1>; + assigned-clock-rates = <27000000>, <25000000>, <300000000>; +}; + +&out_dp { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; +}; + +&zynqmp_dpdma { + status = "okay"; + assigned-clock-rates = <600000000>; +}; + +&usb0 { /* mio52 - mio63 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; + reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>; + assigned-clock-rates = <250000000>, <20000000>; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub_3_0>; + i2c-bus = <&hub_1>; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub_2_0>; + i2c-bus = <&hub_1>; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; +}; + +&usb1 { /* mio64 - mio75 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 3 PHY_TYPE_USB3 1 2>; + reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>; + assigned-clock-rates = <250000000>, <20000000>; +}; + +&dwc3_1 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub1_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub1_3_0>; + i2c-bus = <&hub_2>; + reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub1_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub1_2_0>; + i2c-bus = <&hub_2>; + reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; +}; + +&gem0 { /* mdio mio50/51 */ + status = "okay"; + phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; + phy-handle = <&phy0>; + phy-mode = "sgmii"; + assigned-clock-rates = <250000000>; +}; + +&gem1 { /* mdio mio50/51, gem mio38 - mio49 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem1_default>; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + assigned-clock-rates = <250000000>; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@4 { /* u81 */ + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <4>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,dp83867-rxctrl-strap-quirk; + reset-assert-us = <300>; + reset-deassert-us = <280>; + reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>; + }; + phy1: ethernet-phy@8 { /* u36 */ + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <8>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,dp83867-rxctrl-strap-quirk; + reset-assert-us = <100>; + reset-deassert-us = <280>; + reset-gpios = <&slg7xl45106 6 GPIO_ACTIVE_LOW>; + }; + }; +}; + +/* gem2/gem3 via PL with phys u79@2 and u80@3 */ + +&pinctrl0 { + status = "okay"; + + pinctrl_uart1_default: uart1-default { + conf { + groups = "uart1_9_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO37"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO36"; + bias-disable; + output-enable; + }; + + mux { + groups = "uart1_9_grp"; + function = "uart1"; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + conf { + groups = "i2c1_6_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "i2c1_6_grp"; + function = "i2c1"; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + conf { + groups = "gpio0_24_grp", "gpio0_25_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "gpio0_24_grp", "gpio0_25_grp"; + function = "gpio0"; + }; + }; + + pinctrl_gem1_default: gem1-default { + conf { + groups = "ethernet1_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO44", "MIO46", "MIO48"; + bias-high-impedance; + low-power-disable; + }; + + conf-bootstrap { + pins = "MIO45", "MIO47", "MIO49"; + bias-disable; + output-enable; + low-power-disable; + }; + + conf-tx { + pins = "MIO38", "MIO39", "MIO40", + "MIO41", "MIO42", "MIO43"; + bias-disable; + output-enable; + low-power-enable; + }; + + conf-mdio { + groups = "mdio1_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + bias-disable; + output-enable; + }; + + mux-mdio { + function = "mdio1"; + groups = "mdio1_0_grp"; + }; + + mux { + function = "ethernet1"; + groups = "ethernet1_0_grp"; + }; + }; + + pinctrl_usb0_default: usb0-default { + conf { + groups = "usb0_0_grp"; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + drive-strength = <12>; + slew-rate = <SLEW_RATE_FAST>; + }; + + conf-tx { + pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + output-enable; + drive-strength = <4>; + slew-rate = <SLEW_RATE_SLOW>; + }; + + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + }; + + pinctrl_usb1_default: usb1-default { + conf { + groups = "usb1_0_grp"; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO64", "MIO65", "MIO67"; + bias-high-impedance; + drive-strength = <12>; + slew-rate = <SLEW_RATE_FAST>; + }; + + conf-tx { + pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", + "MIO72", "MIO73", "MIO74", "MIO75"; + bias-disable; + output-enable; + drive-strength = <4>; + slew-rate = <SLEW_RATE_SLOW>; + }; + + mux { + groups = "usb1_0_grp"; + function = "usb1"; + }; + }; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso new file mode 100644 index 000000000000..99ad220d13d6 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso @@ -0,0 +1,456 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for KR260 revB Carrier Card (A03 revision) + * + * (C) Copyright 2021 - 2022, Xilinx, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/net/ti-dp83867.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "xlnx,zynqmp-sk-kr260-revB", + "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp"; + model = "ZynqMP KR260 revB"; + + aliases { + ethernet0 = "/axi/ethernet@ff0b0000"; /* &gem0 */ + ethernet1 = "/axi/ethernet@ff0c0000"; /* &gem1 */ + }; + + ina260-u14 { + compatible = "iio-hwmon"; + io-channels = <&u14 0>, <&u14 1>, <&u14 2>; + }; + + clk_125: clock0 { /* u87 - GEM0/1 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + clk_27: clock1 { /* u86 - DP */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; + + clk_26: clock2 { /* u89 - USB */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + clk_156: clock3 { /* u90 - SFP+ */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <156250000>; + }; + + clk_25_0: clock4 { /* u92/u91 - GEM2 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + clk_25_1: clock5 { /* u92/u91 - GEM3 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + clk_74: clock6 { /* u88 - SLVC-EC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <74250000>; + }; + + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; +}; + +&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + u14: ina260@40 { /* u14 */ + compatible = "ti,ina260"; + #io-channel-cells = <1>; + label = "ina260-u14"; + reg = <0x40>; + }; + + slg7xl45106: gpio@11 { /* u19 - reset logic */ + compatible = "dlg,slg7xl45106"; + reg = <0x11>; + label = "resetchip"; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B", + "SD_RESET_B", "USB0_HUB_RESET_B", + "USB1_HUB_RESET_B", "PS_GEM0_RESET_B", + "PS_GEM1_RESET_B", ""; + }; + + i2c-mux@74 { /* u18 */ + compatible = "nxp,pca9546"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + usbhub_i2c0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + hub_1: usb-hub@2d { + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; + }; + usbhub_i2c1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + hub_2: usb-hub@2d { + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; + }; + /* Bus 2/3 are not connected */ + }; + + /* si5332@6a - u17 - clock-generator */ +}; + +/* GEM SGMII/DP and USB 3.0 */ +&psgtr { + status = "okay"; + /* gem0/1, dp, usb */ + clocks = <&clk_125>, <&clk_27>, <&clk_26>; + clock-names = "ref0", "ref1", "ref2"; +}; + +&zynqmp_dpsub { + status = "okay"; + phy-names = "dp-phy0"; + phys = <&psgtr 1 PHY_TYPE_DP 0 1>; + assigned-clock-rates = <27000000>, <25000000>, <300000000>; +}; + +&out_dp { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; +}; + +&zynqmp_dpdma { + status = "okay"; + assigned-clock-rates = <600000000>; +}; + +&usb0 { /* mio52 - mio63 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; + reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>; + assigned-clock-rates = <250000000>, <20000000>; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub_3_0>; + i2c-bus = <&hub_1>; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub_2_0>; + i2c-bus = <&hub_1>; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; +}; + +&usb1 { /* mio64 - mio75 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 3 PHY_TYPE_USB3 1 2>; + reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>; + assigned-clock-rates = <250000000>, <20000000>; +}; + +&dwc3_1 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub1_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub1_3_0>; + i2c-bus = <&hub_2>; + reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub1_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub1_2_0>; + i2c-bus = <&hub_2>; + reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; +}; + +&gem0 { /* mdio mio50/51 */ + status = "okay"; + phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; + phy-handle = <&phy0>; + phy-mode = "sgmii"; + assigned-clock-rates = <250000000>; +}; + +&gem1 { /* mdio mio50/51, gem mio38 - mio49 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem1_default>; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + assigned-clock-rates = <250000000>; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@4 { /* u81 */ + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <4>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,dp83867-rxctrl-strap-quirk; + reset-assert-us = <300>; + reset-deassert-us = <280>; + reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>; + }; + phy1: ethernet-phy@8 { /* u36 */ + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <8>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,dp83867-rxctrl-strap-quirk; + reset-assert-us = <100>; + reset-deassert-us = <280>; + reset-gpios = <&slg7xl45106 6 GPIO_ACTIVE_LOW>; + }; + }; +}; + +/* gem2/gem3 via PL with phys u79@2 and u80@3 */ + +&pinctrl0 { + status = "okay"; + + pinctrl_uart1_default: uart1-default { + conf { + groups = "uart1_9_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO37"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO36"; + bias-disable; + output-enable; + }; + + mux { + groups = "uart1_9_grp"; + function = "uart1"; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + conf { + groups = "i2c1_6_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "i2c1_6_grp"; + function = "i2c1"; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + conf { + groups = "gpio0_24_grp", "gpio0_25_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "gpio0_24_grp", "gpio0_25_grp"; + function = "gpio0"; + }; + }; + + pinctrl_gem1_default: gem1-default { + conf { + groups = "ethernet1_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO44", "MIO46", "MIO48"; + bias-high-impedance; + low-power-disable; + }; + + conf-bootstrap { + pins = "MIO45", "MIO47", "MIO49"; + bias-disable; + output-enable; + low-power-disable; + }; + + conf-tx { + pins = "MIO38", "MIO39", "MIO40", + "MIO41", "MIO42", "MIO43"; + bias-disable; + output-enable; + low-power-enable; + }; + + conf-mdio { + groups = "mdio1_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + bias-disable; + output-enable; + }; + + mux-mdio { + function = "mdio1"; + groups = "mdio1_0_grp"; + }; + + mux { + function = "ethernet1"; + groups = "ethernet1_0_grp"; + }; + }; + + pinctrl_usb0_default: usb0-default { + conf { + groups = "usb0_0_grp"; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + drive-strength = <12>; + slew-rate = <SLEW_RATE_FAST>; + }; + + conf-tx { + pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + output-enable; + drive-strength = <4>; + slew-rate = <SLEW_RATE_SLOW>; + }; + + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + }; + + pinctrl_usb1_default: usb1-default { + conf { + groups = "usb1_0_grp"; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO64", "MIO65", "MIO67"; + bias-high-impedance; + drive-strength = <12>; + slew-rate = <SLEW_RATE_FAST>; + }; + + conf-tx { + pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", + "MIO72", "MIO73", "MIO74", "MIO75"; + bias-disable; + output-enable; + drive-strength = <4>; + slew-rate = <SLEW_RATE_SLOW>; + }; + + mux { + groups = "usb1_0_grp"; + function = "usb1"; + }; + }; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index 95d16904d765..d7351a17d3e8 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -28,6 +28,10 @@ "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp"; model = "ZynqMP KV260 revA"; + aliases { + ethernet0 = "/axi/ethernet@ff0e0000"; /* &gem3 */ + }; + ina260-u14 { compatible = "iio-hwmon"; io-channels = <&u14 0>, <&u14 1>, <&u14 2>; @@ -68,6 +72,17 @@ #clock-cells = <0>; clock-frequency = <27000000>; }; + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; }; &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ @@ -118,6 +133,12 @@ assigned-clock-rates = <27000000>, <25000000>, <300000000>; }; +&out_dp { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; +}; + &zynqmp_dpdma { status = "okay"; assigned-clock-rates = <600000000>; @@ -129,7 +150,6 @@ pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; - /* missing usb5744 - u43 */ }; &dwc3_0 { @@ -137,6 +157,24 @@ dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + }; }; &sdhci1 { /* on CC with tuned parameters */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index a74d0ac7e07a..a4ae37ebaccf 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -23,6 +23,10 @@ "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp"; model = "ZynqMP KV260 revB"; + aliases { + ethernet0 = "/axi/ethernet@ff0e0000"; /* &gem3 */ + }; + ina260-u14 { compatible = "iio-hwmon"; io-channels = <&u14 0>, <&u14 1>, <&u14 2>; @@ -92,7 +96,10 @@ label = "ina260-u14"; reg = <0x40>; }; - /* u43 - 0x2d - USB hub */ + hub: usb-hub@2d { + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ }; @@ -109,13 +116,11 @@ phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; assigned-clock-rates = <27000000>, <25000000>, <300000000>; +}; - ports { - port@5 { - dpsub_dp_out: endpoint { - remote-endpoint = <&dpcon_in>; - }; - }; +&out_dp { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; }; }; @@ -138,6 +143,26 @@ dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub_3_0>; + i2c-bus = <&hub>; + reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub_2_0>; + i2c-bus = <&hub>; + reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + }; }; &sdhci1 { /* on CC with tuned parameters */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k24-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k24-revA.dts new file mode 100644 index 000000000000..653bd9362264 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k24-revA.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP SM-K24 RevA + * + * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2022, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include "zynqmp-sm-k26-revA.dts" + +/ { + model = "ZynqMP SM-K24 RevA/B/1"; + compatible = "xlnx,zynqmp-sm-k24-rev1", "xlnx,zynqmp-sm-k24-revB", + "xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24", + "xlnx,zynqmp"; + + memory@0 { + device_type = "memory"; /* 2GB */ + reg = <0 0 0 0x80000000>; + }; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index bfa7ea6b9224..500af1d2232f 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -90,10 +90,10 @@ }; }; - pwm-fan { + pwm_fan: pwm-fan { compatible = "pwm-fan"; status = "okay"; - pwms = <&ttc0 2 40000 0>; + pwms = <&ttc0 2 40000 1>; }; }; @@ -233,6 +233,9 @@ pinctrl-0 = <&pinctrl_sdhci0_default>; non-removable; disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; xlnx,mio-bank = <0>; assigned-clock-rates = <187498123>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-smk-k24-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-smk-k24-revA.dts new file mode 100644 index 000000000000..7308983b15a0 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-smk-k24-revA.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP SMK-K24 RevA + * + * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2022, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include "zynqmp-sm-k24-revA.dts" + +/ { + model = "ZynqMP SMK-K24 RevA"; + compatible = "xlnx,zynqmp-smk-k24-revA", "xlnx,zynqmp-smk-k24", + "xlnx,zynqmp"; +}; + +&sdhci0 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts index 1850325e1d6c..2ad7423c2f05 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts @@ -135,7 +135,6 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand0_default>; - arasan,has-mdma; nand@0 { reg = <0x0>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts index f553b317e6b2..8fbc33562bc4 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts @@ -129,7 +129,6 @@ /* MT29F64G08AECDBJ4-6 */ &nand0 { status = "okay"; - arasan,has-mdma; num-cs = <2>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index 62c2503a502a..4ec8a400494e 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -134,6 +134,18 @@ #clock-cells = <0>; clock-frequency = <27000000>; }; + + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; }; &dcc { @@ -509,6 +521,9 @@ xlnx,mio-bank = <0>; non-removable; disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; @@ -604,3 +619,9 @@ phys = <&psgtr 1 PHY_TYPE_DP 0 1>, <&psgtr 0 PHY_TYPE_DP 1 1>; }; + +&out_dp { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 7e26489a1539..e172a30e7b21 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -151,6 +151,18 @@ #clock-cells = <0>; clock-frequency = <114285000>; }; + + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; }; &can1 { @@ -1045,3 +1057,9 @@ phy-names = "dp-phy0"; phys = <&psgtr 1 PHY_TYPE_DP 0 3>; }; + +&out_dp { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index eb2090673ec1..fe8f151ed706 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -60,6 +60,18 @@ #clock-cells = <0>; clock-frequency = <27000000>; }; + + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; }; &can1 { @@ -529,3 +541,9 @@ phys = <&psgtr 1 PHY_TYPE_DP 0 3>, <&psgtr 0 PHY_TYPE_DP 1 3>; }; + +&out_dp { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts index 4694d0a841f1..3ee8ab224722 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -65,6 +65,18 @@ #clock-cells = <0>; clock-frequency = <27000000>; }; + + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; }; &can1 { @@ -541,3 +553,9 @@ phys = <&psgtr 1 PHY_TYPE_DP 0 3>, <&psgtr 0 PHY_TYPE_DP 1 3>; }; + +&out_dp { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 7beedd730f94..7f6c87d4d77e 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -808,8 +808,8 @@ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; - drive-strength = <4>; - slew-rate = <SLEW_RATE_SLOW>; + drive-strength = <12>; + slew-rate = <SLEW_RATE_FAST>; }; }; @@ -1042,12 +1042,10 @@ phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 3>, <&psgtr 0 PHY_TYPE_DP 1 3>; +}; - ports { - port@5 { - dpsub_dp_out: endpoint { - remote-endpoint = <&dpcon_in>; - }; - }; +&out_dp { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index b67ff7ecf3c3..428b5558fbba 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -129,6 +129,18 @@ #clock-cells = <0>; clock-frequency = <48000000>; }; + + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; }; &dcc { @@ -494,7 +506,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <5>; - sc18is603@2f { /* sc18is602 - u93 */ + sc18is603: spi@2f { /* sc18is602 - u93 */ compatible = "nxp,sc18is603"; reg = <0x2f>; /* 4 gpios for CS not handled by driver */ @@ -864,3 +876,9 @@ phys = <&psgtr 1 PHY_TYPE_DP 0 1>, <&psgtr 0 PHY_TYPE_DP 1 1>; }; + +&out_dp { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index e11d282462bd..938b014ca923 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -187,7 +187,7 @@ }; psci { - compatible = "arm,psci-0.2"; + compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; }; @@ -550,6 +550,7 @@ reg = <0x0 0xfec10000 0x0 0x1000>; clock-names = "apb_pclk"; cpu = <&cpu0>; + status = "disabled"; }; cpu1_debug: debug@fed10000 { @@ -557,6 +558,7 @@ reg = <0x0 0xfed10000 0x0 0x1000>; clock-names = "apb_pclk"; cpu = <&cpu1>; + status = "disabled"; }; cpu2_debug: debug@fee10000 { @@ -564,6 +566,7 @@ reg = <0x0 0xfee10000 0x0 0x1000>; clock-names = "apb_pclk"; cpu = <&cpu2>; + status = "disabled"; }; cpu3_debug: debug@fef10000 { @@ -571,6 +574,7 @@ reg = <0x0 0xfef10000 0x0 0x1000>; clock-names = "apb_pclk"; cpu = <&cpu3>; + status = "disabled"; }; /* GDMA */ @@ -1319,22 +1323,22 @@ #address-cells = <1>; #size-cells = <0>; - port@0 { + live_video: port@0 { reg = <0>; }; - port@1 { + live_gfx: port@1 { reg = <1>; }; - port@2 { + live_audio: port@2 { reg = <2>; }; - port@3 { + out_video: port@3 { reg = <3>; }; - port@4 { + out_audio: port@4 { reg = <4>; }; - port@5 { + out_dp: port@5 { reg = <5>; }; }; diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 58f87d09366c..e3a2d37bd104 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -38,6 +38,7 @@ CONFIG_ARCH_AIROHA=y CONFIG_ARCH_SUNXI=y CONFIG_ARCH_ALPINE=y CONFIG_ARCH_APPLE=y +CONFIG_ARCH_ARTPEC=y CONFIG_ARCH_AXIADO=y CONFIG_ARCH_BCM=y CONFIG_ARCH_BCM2835=y @@ -441,6 +442,7 @@ CONFIG_IWLMVM=m CONFIG_MWIFIEX=m CONFIG_MWIFIEX_SDIO=m CONFIG_MWIFIEX_PCIE=m +CONFIG_MWIFIEX_USB=m CONFIG_MT7921E=m CONFIG_RSI_91X=m CONFIG_WL18XX=m @@ -499,6 +501,7 @@ CONFIG_SERIAL_TEGRA_TCU=y CONFIG_SERIAL_IMX=y CONFIG_SERIAL_IMX_CONSOLE=y CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_RSCI=y CONFIG_SERIAL_MSM=y CONFIG_SERIAL_MSM_CONSOLE=y CONFIG_SERIAL_QCOM_GENI=y @@ -579,6 +582,7 @@ CONFIG_SPI_ROCKCHIP=y CONFIG_SPI_ROCKCHIP_SFC=m CONFIG_SPI_RPCIF=m CONFIG_SPI_RSPI=m +CONFIG_SPI_RZV2H_RSPI=m CONFIG_SPI_RZV2M_CSI=m CONFIG_SPI_QCOM_QSPI=m CONFIG_SPI_QUP=y @@ -592,6 +596,8 @@ CONFIG_SPI_TEGRA114=m CONFIG_SPI_SPIDEV=m CONFIG_SPMI=y CONFIG_SPMI_MTK_PMIF=m +CONFIG_PINCTRL_BRCMSTB=y +CONFIG_PINCTRL_BCM2712=y CONFIG_PINCTRL_DA9062=m CONFIG_PINCTRL_MAX77620=y CONFIG_PINCTRL_RK805=m @@ -607,6 +613,7 @@ CONFIG_PINCTRL_IMX8QM=y CONFIG_PINCTRL_IMX8QXP=y CONFIG_PINCTRL_IMX8DXL=y CONFIG_PINCTRL_IMX8ULP=y +CONFIG_PINCTRL_IMX91=y CONFIG_PINCTRL_IMX93=y CONFIG_PINCTRL_MSM=y CONFIG_PINCTRL_IPQ5018=y @@ -1300,6 +1307,7 @@ CONFIG_RENESAS_USB_DMAC=m CONFIG_RZ_DMAC=y CONFIG_TI_K3_UDMA=y CONFIG_TI_K3_UDMA_GLUE_LAYER=y +CONFIG_STM32_DMA3=m CONFIG_VFIO=y CONFIG_VFIO_PCI=y CONFIG_VIRTIO_PCI=y @@ -1360,6 +1368,7 @@ CONFIG_CLK_X1E80100_DISPCC=m CONFIG_CLK_X1E80100_GCC=y CONFIG_CLK_X1E80100_GPUCC=m CONFIG_CLK_X1E80100_TCSRCC=y +CONFIG_CLK_X1P42100_GPUCC=m CONFIG_CLK_QCM2290_GPUCC=m CONFIG_QCOM_A53PLL=y CONFIG_QCOM_CLK_APCS_MSM8916=y @@ -1385,11 +1394,15 @@ CONFIG_MSM_GCC_8998=y CONFIG_MSM_MMCC_8998=m CONFIG_QCM_GCC_2290=y CONFIG_QCM_DISPCC_2290=m +CONFIG_QCS_DISPCC_615=m +CONFIG_QCS_CAMCC_615=m CONFIG_QCS_GCC_404=y CONFIG_QCS_GCC_615=y CONFIG_QCS_GCC_8300=y CONFIG_SC_CAMCC_7280=m CONFIG_SA_CAMCC_8775P=m +CONFIG_QCS_GPUCC_615=m +CONFIG_QCS_VIDEOCC_615=m CONFIG_QDU_GCC_1000=y CONFIG_SC_CAMCC_8280XP=m CONFIG_SC_DISPCC_7280=m diff --git a/arch/arm64/crypto/Kconfig b/arch/arm64/crypto/Kconfig index 3bb5b513d5ae..91f3093eee6a 100644 --- a/arch/arm64/crypto/Kconfig +++ b/arch/arm64/crypto/Kconfig @@ -71,6 +71,7 @@ config CRYPTO_POLYVAL_ARM64_CE config CRYPTO_AES_ARM64 tristate "Ciphers: AES, modes: ECB, CBC, CTR, CTS, XCTR, XTS" select CRYPTO_AES + select CRYPTO_LIB_SHA256 help Block ciphers: AES cipher algorithms (FIPS-197) Length-preserving ciphers: AES with ECB, CBC, CTR, CTS, diff --git a/arch/arm64/crypto/aes-glue.c b/arch/arm64/crypto/aes-glue.c index 81560f722b9d..5e207ff34482 100644 --- a/arch/arm64/crypto/aes-glue.c +++ b/arch/arm64/crypto/aes-glue.c @@ -122,7 +122,6 @@ struct crypto_aes_xts_ctx { struct crypto_aes_essiv_cbc_ctx { struct crypto_aes_ctx key1; struct crypto_aes_ctx __aligned(8) key2; - struct crypto_shash *hash; }; struct mac_tfm_ctx { @@ -171,7 +170,7 @@ static int __maybe_unused essiv_cbc_set_key(struct crypto_skcipher *tfm, if (ret) return ret; - crypto_shash_tfm_digest(ctx->hash, in_key, key_len, digest); + sha256(in_key, key_len, digest); return aes_expandkey(&ctx->key2, digest, sizeof(digest)); } @@ -388,22 +387,6 @@ static int cts_cbc_decrypt(struct skcipher_request *req) return skcipher_walk_done(&walk, 0); } -static int __maybe_unused essiv_cbc_init_tfm(struct crypto_skcipher *tfm) -{ - struct crypto_aes_essiv_cbc_ctx *ctx = crypto_skcipher_ctx(tfm); - - ctx->hash = crypto_alloc_shash("sha256", 0, 0); - - return PTR_ERR_OR_ZERO(ctx->hash); -} - -static void __maybe_unused essiv_cbc_exit_tfm(struct crypto_skcipher *tfm) -{ - struct crypto_aes_essiv_cbc_ctx *ctx = crypto_skcipher_ctx(tfm); - - crypto_free_shash(ctx->hash); -} - static int __maybe_unused essiv_cbc_encrypt(struct skcipher_request *req) { struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); @@ -793,8 +776,6 @@ static struct skcipher_alg aes_algs[] = { { .setkey = essiv_cbc_set_key, .encrypt = essiv_cbc_encrypt, .decrypt = essiv_cbc_decrypt, - .init = essiv_cbc_init_tfm, - .exit = essiv_cbc_exit_tfm, } }; static int cbcmac_setkey(struct crypto_shash *tfm, const u8 *in_key, diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index bf13d676aae2..e223cbf350e4 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -871,6 +871,8 @@ static inline bool system_supports_pmuv3(void) return cpus_have_final_cap(ARM64_HAS_PMUV3); } +bool cpu_supports_bbml2_noabort(void); + static inline bool system_supports_bbml2_noabort(void) { return alternative_has_cap_unlikely(ARM64_HAS_BBML2_NOABORT); diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 661735616787..9b00b75acbf2 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -81,7 +81,6 @@ #define ARM_CPU_PART_CORTEX_A78AE 0xD42 #define ARM_CPU_PART_CORTEX_X1 0xD44 #define ARM_CPU_PART_CORTEX_A510 0xD46 -#define ARM_CPU_PART_CORTEX_X1C 0xD4C #define ARM_CPU_PART_CORTEX_A520 0xD80 #define ARM_CPU_PART_CORTEX_A710 0xD47 #define ARM_CPU_PART_CORTEX_A715 0xD4D @@ -93,9 +92,11 @@ #define ARM_CPU_PART_NEOVERSE_V2 0xD4F #define ARM_CPU_PART_CORTEX_A720 0xD81 #define ARM_CPU_PART_CORTEX_X4 0xD82 +#define ARM_CPU_PART_NEOVERSE_V3AE 0xD83 #define ARM_CPU_PART_NEOVERSE_V3 0xD84 #define ARM_CPU_PART_CORTEX_X925 0xD85 #define ARM_CPU_PART_CORTEX_A725 0xD87 +#define ARM_CPU_PART_CORTEX_A720AE 0xD89 #define ARM_CPU_PART_NEOVERSE_N3 0xD8E #define APM_CPU_PART_XGENE 0x000 @@ -129,6 +130,7 @@ #define NVIDIA_CPU_PART_DENVER 0x003 #define NVIDIA_CPU_PART_CARMEL 0x004 +#define NVIDIA_CPU_PART_OLYMPUS 0x010 #define FUJITSU_CPU_PART_A64FX 0x001 @@ -170,7 +172,6 @@ #define MIDR_CORTEX_A78AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78AE) #define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1) #define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510) -#define MIDR_CORTEX_X1C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1C) #define MIDR_CORTEX_A520 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520) #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710) #define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A715) @@ -182,9 +183,11 @@ #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) #define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720) #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4) +#define MIDR_NEOVERSE_V3AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3AE) #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3) #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925) #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725) +#define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE) #define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) @@ -220,6 +223,7 @@ #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER) #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL) +#define MIDR_NVIDIA_OLYMPUS MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_OLYMPUS) #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX) #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110) #define MIDR_HISI_HIP09 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP09) diff --git a/arch/arm64/include/asm/daifflags.h b/arch/arm64/include/asm/daifflags.h index fbb5c99eb2f9..5fca48009043 100644 --- a/arch/arm64/include/asm/daifflags.h +++ b/arch/arm64/include/asm/daifflags.h @@ -128,7 +128,7 @@ static inline void local_daif_inherit(struct pt_regs *regs) { unsigned long flags = regs->pstate & DAIF_MASK; - if (interrupts_enabled(regs)) + if (!regs_irqs_disabled(regs)) trace_hardirqs_on(); if (system_uses_irq_prio_masking()) diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h index 46033027510c..b37da3ee8529 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -91,6 +91,14 @@ msr cntvoff_el2, xzr // Clear virtual offset .endm +/* Branch to skip_label if SPE version is less than given version */ +.macro __spe_vers_imp skip_label, version, tmp + mrs \tmp, id_aa64dfr0_el1 + ubfx \tmp, \tmp, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4 + cmp \tmp, \version + b.lt \skip_label +.endm + .macro __init_el2_debug mrs x1, id_aa64dfr0_el1 ubfx x0, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4 @@ -103,8 +111,7 @@ csel x2, xzr, x0, eq // all PMU counters from EL1 /* Statistical profiling */ - ubfx x0, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4 - cbz x0, .Lskip_spe_\@ // Skip if SPE not present + __spe_vers_imp .Lskip_spe_\@, ID_AA64DFR0_EL1_PMSVer_IMP, x0 // Skip if SPE not present mrs_s x0, SYS_PMBIDR_EL1 // If SPE available at EL2, and x0, x0, #(1 << PMBIDR_EL1_P_SHIFT) @@ -263,10 +270,8 @@ mov x0, xzr mov x2, xzr - mrs x1, id_aa64dfr0_el1 - ubfx x1, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4 - cmp x1, #3 - b.lt .Lskip_spe_fgt_\@ + /* If SPEv1p2 is implemented, */ + __spe_vers_imp .Lskip_spe_fgt_\@, #ID_AA64DFR0_EL1_PMSVer_V1P2, x1 /* Disable PMSNEVFR_EL1 read and write traps */ orr x0, x0, #HDFGRTR_EL2_nPMSNEVFR_EL1_MASK orr x2, x2, #HDFGWTR_EL2_nPMSNEVFR_EL1_MASK @@ -387,6 +392,17 @@ orr x0, x0, #HDFGRTR2_EL2_nPMICFILTR_EL0 orr x0, x0, #HDFGRTR2_EL2_nPMUACR_EL1 .Lskip_pmuv3p9_\@: + /* If SPE is implemented, */ + __spe_vers_imp .Lskip_spefds_\@, ID_AA64DFR0_EL1_PMSVer_IMP, x1 + /* we can read PMSIDR and */ + mrs_s x1, SYS_PMSIDR_EL1 + and x1, x1, #PMSIDR_EL1_FDS + /* if FEAT_SPE_FDS is implemented, */ + cbz x1, .Lskip_spefds_\@ + /* disable traps of PMSDSFR to EL2. */ + orr x0, x0, #HDFGRTR2_EL2_nPMSDSFR_EL1 + +.Lskip_spefds_\@: msr_s SYS_HDFGRTR2_EL2, x0 msr_s SYS_HDFGWTR2_EL2, x0 msr_s SYS_HFGRTR2_EL2, xzr diff --git a/arch/arm64/include/asm/entry-common.h b/arch/arm64/include/asm/entry-common.h new file mode 100644 index 000000000000..cab8cd78f693 --- /dev/null +++ b/arch/arm64/include/asm/entry-common.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _ASM_ARM64_ENTRY_COMMON_H +#define _ASM_ARM64_ENTRY_COMMON_H + +#include <linux/thread_info.h> + +#include <asm/cpufeature.h> +#include <asm/daifflags.h> +#include <asm/fpsimd.h> +#include <asm/mte.h> +#include <asm/stacktrace.h> + +#define ARCH_EXIT_TO_USER_MODE_WORK (_TIF_MTE_ASYNC_FAULT | _TIF_FOREIGN_FPSTATE) + +static __always_inline void arch_exit_to_user_mode_work(struct pt_regs *regs, + unsigned long ti_work) +{ + if (ti_work & _TIF_MTE_ASYNC_FAULT) { + clear_thread_flag(TIF_MTE_ASYNC_FAULT); + send_sig_fault(SIGSEGV, SEGV_MTEAERR, (void __user *)NULL, current); + } + + if (ti_work & _TIF_FOREIGN_FPSTATE) + fpsimd_restore_current_state(); +} + +#define arch_exit_to_user_mode_work arch_exit_to_user_mode_work + +static inline bool arch_irqentry_exit_need_resched(void) +{ + /* + * DAIF.DA are cleared at the start of IRQ/FIQ handling, and when GIC + * priority masking is used the GIC irqchip driver will clear DAIF.IF + * using gic_arch_enable_irqs() for normal IRQs. If anything is set in + * DAIF we must have handled an NMI, so skip preemption. + */ + if (system_uses_irq_prio_masking() && read_sysreg(daif)) + return false; + + /* + * Preempting a task from an IRQ means we leave copies of PSTATE + * on the stack. cpufeature's enable calls may modify PSTATE, but + * resuming one of these preempted tasks would undo those changes. + * + * Only allow a task to be preempted once cpufeatures have been + * enabled. + */ + if (!system_capabilities_finalized()) + return false; + + return true; +} + +#define arch_irqentry_exit_need_resched arch_irqentry_exit_need_resched + +#endif /* _ASM_ARM64_ENTRY_COMMON_H */ diff --git a/arch/arm64/include/asm/exception.h b/arch/arm64/include/asm/exception.h index e3874c4fc399..a2da3cb21c24 100644 --- a/arch/arm64/include/asm/exception.h +++ b/arch/arm64/include/asm/exception.h @@ -89,7 +89,6 @@ void do_el1_fpac(struct pt_regs *regs, unsigned long esr); void do_el0_mops(struct pt_regs *regs, unsigned long esr); void do_el1_mops(struct pt_regs *regs, unsigned long esr); void do_serror(struct pt_regs *regs, unsigned long esr); -void do_signal(struct pt_regs *regs); void __noreturn panic_bad_stack(struct pt_regs *regs, unsigned long esr, unsigned long far); #endif /* __ASM_EXCEPTION_H */ diff --git a/arch/arm64/include/asm/gcs.h b/arch/arm64/include/asm/gcs.h index 5bc432234d3a..8fa0707069e8 100644 --- a/arch/arm64/include/asm/gcs.h +++ b/arch/arm64/include/asm/gcs.h @@ -21,7 +21,7 @@ static inline void gcsstr(u64 *addr, u64 val) register u64 *_addr __asm__ ("x0") = addr; register long _val __asm__ ("x1") = val; - /* GCSSTTR x1, x0 */ + /* GCSSTTR x1, [x0] */ asm volatile( ".inst 0xd91f1c01\n" : @@ -81,6 +81,82 @@ static inline int gcs_check_locked(struct task_struct *task, return 0; } +static inline int gcssttr(unsigned long __user *addr, unsigned long val) +{ + register unsigned long __user *_addr __asm__ ("x0") = addr; + register unsigned long _val __asm__ ("x1") = val; + int err = 0; + + /* GCSSTTR x1, [x0] */ + asm volatile( + "1: .inst 0xd91f1c01\n" + "2: \n" + _ASM_EXTABLE_UACCESS_ERR(1b, 2b, %w0) + : "+r" (err) + : "rZ" (_val), "r" (_addr) + : "memory"); + + return err; +} + +static inline void put_user_gcs(unsigned long val, unsigned long __user *addr, + int *err) +{ + int ret; + + if (!access_ok((char __user *)addr, sizeof(u64))) { + *err = -EFAULT; + return; + } + + uaccess_ttbr0_enable(); + ret = gcssttr(addr, val); + if (ret != 0) + *err = ret; + uaccess_ttbr0_disable(); +} + +static inline void push_user_gcs(unsigned long val, int *err) +{ + u64 gcspr = read_sysreg_s(SYS_GCSPR_EL0); + + gcspr -= sizeof(u64); + put_user_gcs(val, (unsigned long __user *)gcspr, err); + if (!*err) + write_sysreg_s(gcspr, SYS_GCSPR_EL0); +} + +/* + * Unlike put/push_user_gcs() above, get/pop_user_gsc() doesn't + * validate the GCS permission is set on the page being read. This + * differs from how the hardware works when it consumes data stored at + * GCSPR. Callers should ensure this is acceptable. + */ +static inline u64 get_user_gcs(unsigned long __user *addr, int *err) +{ + unsigned long ret; + u64 load = 0; + + /* Ensure previous GCS operation are visible before we read the page */ + gcsb_dsync(); + ret = copy_from_user(&load, addr, sizeof(load)); + if (ret != 0) + *err = ret; + return load; +} + +static inline u64 pop_user_gcs(int *err) +{ + u64 gcspr = read_sysreg_s(SYS_GCSPR_EL0); + u64 read_val; + + read_val = get_user_gcs((__force unsigned long __user *)gcspr, err); + if (!*err) + write_sysreg_s(gcspr + sizeof(u64), SYS_GCSPR_EL0); + + return read_val; +} + #else static inline bool task_gcs_el0_enabled(struct task_struct *task) @@ -91,6 +167,10 @@ static inline bool task_gcs_el0_enabled(struct task_struct *task) static inline void gcs_set_el0_mode(struct task_struct *task) { } static inline void gcs_free(struct task_struct *task) { } static inline void gcs_preserve_current_state(void) { } +static inline void put_user_gcs(unsigned long val, unsigned long __user *addr, + int *err) { } +static inline void push_user_gcs(unsigned long val, int *err) { } + static inline unsigned long gcs_alloc_thread_stack(struct task_struct *tsk, const struct kernel_clone_args *args) { @@ -101,6 +181,15 @@ static inline int gcs_check_locked(struct task_struct *task, { return 0; } +static inline u64 get_user_gcs(unsigned long __user *addr, int *err) +{ + *err = -EFAULT; + return 0; +} +static inline u64 pop_user_gcs(int *err) +{ + return 0; +} #endif diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h index 13f94c8ddfc0..6d567265467c 100644 --- a/arch/arm64/include/asm/hwcap.h +++ b/arch/arm64/include/asm/hwcap.h @@ -178,6 +178,7 @@ #define __khwcap3_feature(x) (const_ilog2(HWCAP3_ ## x) + 128) #define KERNEL_HWCAP_MTE_FAR __khwcap3_feature(MTE_FAR) #define KERNEL_HWCAP_MTE_STORE_ONLY __khwcap3_feature(MTE_STORE_ONLY) +#define KERNEL_HWCAP_LSFE __khwcap3_feature(LSFE) /* * This yields a mask that user programs can use to figure out what diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h index 9b96840fb979..83e03abbb2ca 100644 --- a/arch/arm64/include/asm/io.h +++ b/arch/arm64/include/asm/io.h @@ -274,6 +274,10 @@ int arm64_ioremap_prot_hook_register(const ioremap_prot_hook_t hook); #define ioremap_np(addr, size) \ ioremap_prot((addr), (size), __pgprot(PROT_DEVICE_nGnRnE)) + +#define ioremap_encrypted(addr, size) \ + ioremap_prot((addr), (size), PAGE_KERNEL) + /* * io{read,write}{16,32,64}be() macros */ @@ -311,7 +315,7 @@ extern bool arch_memremap_can_ram_remap(resource_size_t offset, size_t size, static inline bool arm64_is_protected_mmio(phys_addr_t phys_addr, size_t size) { if (unlikely(is_realm_world())) - return __arm64_is_protected_mmio(phys_addr, size); + return arm64_rsi_is_protected(phys_addr, size); return false; } diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h index bec227f9500a..9da54d4ee49e 100644 --- a/arch/arm64/include/asm/kvm_asm.h +++ b/arch/arm64/include/asm/kvm_asm.h @@ -81,6 +81,8 @@ enum __kvm_host_smccc_func { __KVM_HOST_SMCCC_FUNC___kvm_timer_set_cntvoff, __KVM_HOST_SMCCC_FUNC___vgic_v3_save_vmcr_aprs, __KVM_HOST_SMCCC_FUNC___vgic_v3_restore_vmcr_aprs, + __KVM_HOST_SMCCC_FUNC___pkvm_reserve_vm, + __KVM_HOST_SMCCC_FUNC___pkvm_unreserve_vm, __KVM_HOST_SMCCC_FUNC___pkvm_init_vm, __KVM_HOST_SMCCC_FUNC___pkvm_init_vcpu, __KVM_HOST_SMCCC_FUNC___pkvm_teardown_vm, diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h index fa8a08a1ccd5..c9eab316398e 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -220,6 +220,20 @@ static inline bool vcpu_el2_tge_is_set(const struct kvm_vcpu *vcpu) static inline bool vcpu_el2_amo_is_set(const struct kvm_vcpu *vcpu) { + /* + * DDI0487L.b Known Issue D22105 + * + * When executing at EL2 and HCR_EL2.{E2H,TGE} = {1, 0} it is + * IMPLEMENTATION DEFINED whether the effective value of HCR_EL2.AMO + * is the value programmed or 1. + * + * Make the implementation choice of treating the effective value as 1 as + * we cannot subsequently catch changes to TGE or AMO that would + * otherwise lead to the SError becoming deliverable. + */ + if (vcpu_is_el2(vcpu) && vcpu_el2_e2h_is_set(vcpu) && !vcpu_el2_tge_is_set(vcpu)) + return true; + return ctxt_sys_reg(&vcpu->arch.ctxt, HCR_EL2) & HCR_AMO; } @@ -511,21 +525,29 @@ static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu) if (vcpu_mode_is_32bit(vcpu)) { *vcpu_cpsr(vcpu) |= PSR_AA32_E_BIT; } else { - u64 sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1); + enum vcpu_sysreg r; + u64 sctlr; + + r = vcpu_has_nv(vcpu) ? SCTLR_EL2 : SCTLR_EL1; + + sctlr = vcpu_read_sys_reg(vcpu, r); sctlr |= SCTLR_ELx_EE; - vcpu_write_sys_reg(vcpu, sctlr, SCTLR_EL1); + vcpu_write_sys_reg(vcpu, sctlr, r); } } static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu) { + enum vcpu_sysreg r; + u64 bit; + if (vcpu_mode_is_32bit(vcpu)) return !!(*vcpu_cpsr(vcpu) & PSR_AA32_E_BIT); - if (vcpu_mode_priv(vcpu)) - return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & SCTLR_ELx_EE); - else - return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & SCTLR_EL1_E0E); + r = is_hyp_ctxt(vcpu) ? SCTLR_EL2 : SCTLR_EL1; + bit = vcpu_mode_priv(vcpu) ? SCTLR_ELx_EE : SCTLR_EL1_E0E; + + return vcpu_read_sys_reg(vcpu, r) & bit; } static inline unsigned long vcpu_data_guest_to_host(struct kvm_vcpu *vcpu, diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 2b07f0a27a7d..b763293281c8 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -252,7 +252,8 @@ struct kvm_protected_vm { pkvm_handle_t handle; struct kvm_hyp_memcache teardown_mc; struct kvm_hyp_memcache stage2_teardown_mc; - bool enabled; + bool is_protected; + bool is_created; }; struct kvm_mpidr_data { @@ -1369,6 +1370,7 @@ static inline bool kvm_system_needs_idmapped_vectors(void) } void kvm_init_host_debug_data(void); +void kvm_debug_init_vhe(void); void kvm_vcpu_load_debug(struct kvm_vcpu *vcpu); void kvm_vcpu_put_debug(struct kvm_vcpu *vcpu); void kvm_debug_set_guest_ownership(struct kvm_vcpu *vcpu); @@ -1441,7 +1443,7 @@ struct kvm *kvm_arch_alloc_vm(void); #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS_RANGE -#define kvm_vm_is_protected(kvm) (is_protected_kvm_enabled() && (kvm)->arch.pkvm.enabled) +#define kvm_vm_is_protected(kvm) (is_protected_kvm_enabled() && (kvm)->arch.pkvm.is_protected) #define vcpu_is_protected(vcpu) kvm_vm_is_protected((vcpu)->kvm) diff --git a/arch/arm64/include/asm/kvm_nested.h b/arch/arm64/include/asm/kvm_nested.h index 7fd76f41c296..f7c06a840963 100644 --- a/arch/arm64/include/asm/kvm_nested.h +++ b/arch/arm64/include/asm/kvm_nested.h @@ -83,6 +83,8 @@ extern void check_nested_vcpu_requests(struct kvm_vcpu *vcpu); extern void kvm_nested_flush_hwstate(struct kvm_vcpu *vcpu); extern void kvm_nested_sync_hwstate(struct kvm_vcpu *vcpu); +extern void kvm_nested_setup_mdcr_el2(struct kvm_vcpu *vcpu); + struct kvm_s2_trans { phys_addr_t output; unsigned long block_size; @@ -265,7 +267,7 @@ static inline u64 decode_range_tlbi(u64 val, u64 *range, u16 *asid) return base; } -static inline unsigned int ps_to_output_size(unsigned int ps) +static inline unsigned int ps_to_output_size(unsigned int ps, bool pa52bit) { switch (ps) { case 0: return 32; @@ -273,7 +275,10 @@ static inline unsigned int ps_to_output_size(unsigned int ps) case 2: return 40; case 3: return 42; case 4: return 44; - case 5: + case 5: return 48; + case 6: if (pa52bit) + return 52; + fallthrough; default: return 48; } @@ -285,13 +290,28 @@ enum trans_regime { TR_EL2, }; +struct s1_walk_info; + +struct s1_walk_context { + struct s1_walk_info *wi; + u64 table_ipa; + int level; +}; + +struct s1_walk_filter { + int (*fn)(struct s1_walk_context *, void *); + void *priv; +}; + struct s1_walk_info { + struct s1_walk_filter *filter; u64 baddr; enum trans_regime regime; unsigned int max_oa_bits; unsigned int pgshift; unsigned int txsz; int sl; + u8 sh; bool as_el0; bool hpd; bool e0poe; @@ -299,6 +319,7 @@ struct s1_walk_info { bool pan; bool be; bool s2; + bool pa52bit; }; struct s1_walk_result { @@ -334,6 +355,8 @@ struct s1_walk_result { int __kvm_translate_va(struct kvm_vcpu *vcpu, struct s1_walk_info *wi, struct s1_walk_result *wr, u64 va); +int __kvm_find_s1_desc_level(struct kvm_vcpu *vcpu, u64 va, u64 ipa, + int *level); /* VNCR management */ int kvm_vcpu_allocate_vncr_tlb(struct kvm_vcpu *vcpu); diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/kvm_pgtable.h index 1246216616b5..2888b5d03757 100644 --- a/arch/arm64/include/asm/kvm_pgtable.h +++ b/arch/arm64/include/asm/kvm_pgtable.h @@ -355,11 +355,6 @@ static inline kvm_pte_t *kvm_dereference_pteref(struct kvm_pgtable_walker *walke return pteref; } -static inline kvm_pte_t *kvm_dereference_pteref_raw(kvm_pteref_t pteref) -{ - return pteref; -} - static inline int kvm_pgtable_walk_begin(struct kvm_pgtable_walker *walker) { /* @@ -389,11 +384,6 @@ static inline kvm_pte_t *kvm_dereference_pteref(struct kvm_pgtable_walker *walke return rcu_dereference_check(pteref, !(walker->flags & KVM_PGTABLE_WALK_SHARED)); } -static inline kvm_pte_t *kvm_dereference_pteref_raw(kvm_pteref_t pteref) -{ - return rcu_dereference_raw(pteref); -} - static inline int kvm_pgtable_walk_begin(struct kvm_pgtable_walker *walker) { if (walker->flags & KVM_PGTABLE_WALK_SHARED) @@ -562,26 +552,6 @@ static inline int kvm_pgtable_stage2_init(struct kvm_pgtable *pgt, struct kvm_s2 void kvm_pgtable_stage2_destroy(struct kvm_pgtable *pgt); /** - * kvm_pgtable_stage2_destroy_range() - Destroy the unlinked range of addresses. - * @pgt: Page-table structure initialised by kvm_pgtable_stage2_init*(). - * @addr: Intermediate physical address at which to place the mapping. - * @size: Size of the mapping. - * - * The page-table is assumed to be unreachable by any hardware walkers prior - * to freeing and therefore no TLB invalidation is performed. - */ -void kvm_pgtable_stage2_destroy_range(struct kvm_pgtable *pgt, - u64 addr, u64 size); - -/** - * kvm_pgtable_stage2_destroy_pgd() - Destroy the PGD of guest stage-2 page-table. - * @pgt: Page-table structure initialised by kvm_pgtable_stage2_init*(). - * - * It is assumed that the rest of the page-table is freed before this operation. - */ -void kvm_pgtable_stage2_destroy_pgd(struct kvm_pgtable *pgt); - -/** * kvm_pgtable_stage2_free_unlinked() - Free an unlinked stage-2 paging structure. * @mm_ops: Memory management callbacks. * @pgtable: Unlinked stage-2 paging structure to be freed. diff --git a/arch/arm64/include/asm/kvm_pkvm.h b/arch/arm64/include/asm/kvm_pkvm.h index 35f9d9478004..08be89c95466 100644 --- a/arch/arm64/include/asm/kvm_pkvm.h +++ b/arch/arm64/include/asm/kvm_pkvm.h @@ -18,6 +18,7 @@ int pkvm_init_host_vm(struct kvm *kvm); int pkvm_create_hyp_vm(struct kvm *kvm); +bool pkvm_hyp_vm_is_created(struct kvm *kvm); void pkvm_destroy_hyp_vm(struct kvm *kvm); int pkvm_create_hyp_vcpu(struct kvm_vcpu *vcpu); @@ -179,9 +180,7 @@ struct pkvm_mapping { int pkvm_pgtable_stage2_init(struct kvm_pgtable *pgt, struct kvm_s2_mmu *mmu, struct kvm_pgtable_mm_ops *mm_ops); -void pkvm_pgtable_stage2_destroy_range(struct kvm_pgtable *pgt, - u64 addr, u64 size); -void pkvm_pgtable_stage2_destroy_pgd(struct kvm_pgtable *pgt); +void pkvm_pgtable_stage2_destroy(struct kvm_pgtable *pgt); int pkvm_pgtable_stage2_map(struct kvm_pgtable *pgt, u64 addr, u64 size, u64 phys, enum kvm_pgtable_prot prot, void *mc, enum kvm_pgtable_walk_flags flags); diff --git a/arch/arm64/include/asm/mmu.h b/arch/arm64/include/asm/mmu.h index 49f1a810df16..ff6fd0bbd7d2 100644 --- a/arch/arm64/include/asm/mmu.h +++ b/arch/arm64/include/asm/mmu.h @@ -78,6 +78,9 @@ extern void create_pgd_mapping(struct mm_struct *mm, phys_addr_t phys, pgprot_t prot, bool page_mappings_only); extern void *fixmap_remap_fdt(phys_addr_t dt_phys, int *size, pgprot_t prot); extern void mark_linear_text_alias_ro(void); +extern int split_kernel_leaf_mapping(unsigned long start, unsigned long end); +extern void init_idmap_kpti_bbml2_flag(void); +extern void linear_map_maybe_split_to_ptes(void); /* * This check is triggered during the early boot before the cpufeature diff --git a/arch/arm64/include/asm/module.h b/arch/arm64/include/asm/module.h index 79550b22ba19..fb9b88eebeb1 100644 --- a/arch/arm64/include/asm/module.h +++ b/arch/arm64/include/asm/module.h @@ -19,6 +19,7 @@ struct mod_arch_specific { /* for CONFIG_DYNAMIC_FTRACE */ struct plt_entry *ftrace_trampolines; + struct plt_entry *init_ftrace_trampolines; }; u64 module_emit_plt_entry(struct module *mod, Elf64_Shdr *sechdrs, diff --git a/arch/arm64/include/asm/module.lds.h b/arch/arm64/include/asm/module.lds.h index b9ae8349e35d..fb944b46846d 100644 --- a/arch/arm64/include/asm/module.lds.h +++ b/arch/arm64/include/asm/module.lds.h @@ -2,6 +2,7 @@ SECTIONS { .plt 0 : { BYTE(0) } .init.plt 0 : { BYTE(0) } .text.ftrace_trampoline 0 : { BYTE(0) } + .init.text.ftrace_trampoline 0 : { BYTE(0) } #ifdef CONFIG_KASAN_SW_TAGS /* diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index abd2dee416b3..aa89c2e67ebc 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -371,6 +371,11 @@ static inline pmd_t pmd_mkcont(pmd_t pmd) return __pmd(pmd_val(pmd) | PMD_SECT_CONT); } +static inline pmd_t pmd_mknoncont(pmd_t pmd) +{ + return __pmd(pmd_val(pmd) & ~PMD_SECT_CONT); +} + #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP static inline int pte_uffd_wp(pte_t pte) { diff --git a/arch/arm64/include/asm/preempt.h b/arch/arm64/include/asm/preempt.h index 0159b625cc7f..932ea4b62042 100644 --- a/arch/arm64/include/asm/preempt.h +++ b/arch/arm64/include/asm/preempt.h @@ -2,7 +2,6 @@ #ifndef __ASM_PREEMPT_H #define __ASM_PREEMPT_H -#include <linux/jump_label.h> #include <linux/thread_info.h> #define PREEMPT_NEED_RESCHED BIT(32) @@ -87,7 +86,6 @@ void preempt_schedule_notrace(void); #ifdef CONFIG_PREEMPT_DYNAMIC -DECLARE_STATIC_KEY_TRUE(sk_dynamic_irqentry_exit_cond_resched); void dynamic_preempt_schedule(void); #define __preempt_schedule() dynamic_preempt_schedule() void dynamic_preempt_schedule_notrace(void); diff --git a/arch/arm64/include/asm/ptdump.h b/arch/arm64/include/asm/ptdump.h index fded5358641f..baff24004459 100644 --- a/arch/arm64/include/asm/ptdump.h +++ b/arch/arm64/include/asm/ptdump.h @@ -7,6 +7,8 @@ #include <linux/ptdump.h> +DECLARE_STATIC_KEY_FALSE(arm64_ptdump_lock_key); + #ifdef CONFIG_PTDUMP #include <linux/mm_types.h> diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h index 47ff8654c5ec..65b053a24d82 100644 --- a/arch/arm64/include/asm/ptrace.h +++ b/arch/arm64/include/asm/ptrace.h @@ -169,10 +169,6 @@ struct pt_regs { u64 sdei_ttbr1; struct frame_record_meta stackframe; - - /* Only valid for some EL1 exceptions. */ - u64 lockdep_hardirqs; - u64 exit_rcu; }; /* For correct stack alignment, pt_regs has to be a multiple of 16 bytes. */ @@ -214,11 +210,12 @@ static inline void forget_syscall(struct pt_regs *regs) (regs)->pmr == GIC_PRIO_IRQON : \ true) -#define interrupts_enabled(regs) \ - (!((regs)->pstate & PSR_I_BIT) && irqs_priority_unmasked(regs)) +static __always_inline bool regs_irqs_disabled(const struct pt_regs *regs) +{ + return (regs->pstate & PSR_I_BIT) || !irqs_priority_unmasked(regs); +} -#define fast_interrupts_enabled(regs) \ - (!((regs)->pstate & PSR_F_BIT)) +#define interrupts_enabled(regs) (!regs_irqs_disabled(regs)) static inline unsigned long user_stack_pointer(struct pt_regs *regs) { diff --git a/arch/arm64/include/asm/rsi.h b/arch/arm64/include/asm/rsi.h index b42aeac05340..88b50d660e85 100644 --- a/arch/arm64/include/asm/rsi.h +++ b/arch/arm64/include/asm/rsi.h @@ -16,7 +16,7 @@ DECLARE_STATIC_KEY_FALSE(rsi_present); void __init arm64_rsi_init(void); -bool __arm64_is_protected_mmio(phys_addr_t base, size_t size); +bool arm64_rsi_is_protected(phys_addr_t base, size_t size); static inline bool is_realm_world(void) { diff --git a/arch/arm64/include/asm/setup.h b/arch/arm64/include/asm/setup.h index ba269a7a3201..3d96dde4d214 100644 --- a/arch/arm64/include/asm/setup.h +++ b/arch/arm64/include/asm/setup.h @@ -21,7 +21,7 @@ static inline bool arch_parse_debug_rodata(char *arg) if (!arg) return false; - if (!strcmp(arg, "full")) { + if (!strcmp(arg, "on")) { rodata_enabled = rodata_full = true; return true; } @@ -31,7 +31,7 @@ static inline bool arch_parse_debug_rodata(char *arg) return true; } - if (!strcmp(arg, "on")) { + if (!strcmp(arg, "noalias")) { rodata_enabled = true; rodata_full = false; return true; diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 6604fd6f33f4..6455db1b54fd 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -281,8 +281,6 @@ #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5) #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) -#define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) - #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0) #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1) #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2) @@ -344,15 +342,6 @@ #define SYS_PAR_EL1_ATTR GENMASK_ULL(63, 56) #define SYS_PAR_EL1_F0_RES0 (GENMASK_ULL(6, 1) | GENMASK_ULL(55, 52)) -/*** Statistical Profiling Extension ***/ -#define PMSEVFR_EL1_RES0_IMP \ - (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\ - BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0)) -#define PMSEVFR_EL1_RES0_V1P1 \ - (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) -#define PMSEVFR_EL1_RES0_V1P2 \ - (PMSEVFR_EL1_RES0_V1P1 & ~BIT_ULL(6)) - /* Buffer error reporting */ #define PMBSR_EL1_FAULT_FSC_SHIFT PMBSR_EL1_MSS_SHIFT #define PMBSR_EL1_FAULT_FSC_MASK PMBSR_EL1_MSS_MASK diff --git a/arch/arm64/include/asm/traps.h b/arch/arm64/include/asm/traps.h index e3e8944a71c3..e92e4a0e48fc 100644 --- a/arch/arm64/include/asm/traps.h +++ b/arch/arm64/include/asm/traps.h @@ -36,6 +36,7 @@ int kasan_brk_handler(struct pt_regs *regs, unsigned long esr); int ubsan_brk_handler(struct pt_regs *regs, unsigned long esr); int early_brk64(unsigned long addr, unsigned long esr, struct pt_regs *regs); +void dump_kernel_instr(unsigned long kaddr); /* * Move regs->pc to next instruction and do necessary setup before it diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index 5b91803201ef..1aa4ecb73429 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -502,44 +502,4 @@ static inline size_t probe_subpage_writeable(const char __user *uaddr, #endif /* CONFIG_ARCH_HAS_SUBPAGE_FAULTS */ -#ifdef CONFIG_ARM64_GCS - -static inline int gcssttr(unsigned long __user *addr, unsigned long val) -{ - register unsigned long __user *_addr __asm__ ("x0") = addr; - register unsigned long _val __asm__ ("x1") = val; - int err = 0; - - /* GCSSTTR x1, x0 */ - asm volatile( - "1: .inst 0xd91f1c01\n" - "2: \n" - _ASM_EXTABLE_UACCESS_ERR(1b, 2b, %w0) - : "+r" (err) - : "rZ" (_val), "r" (_addr) - : "memory"); - - return err; -} - -static inline void put_user_gcs(unsigned long val, unsigned long __user *addr, - int *err) -{ - int ret; - - if (!access_ok((char __user *)addr, sizeof(u64))) { - *err = -EFAULT; - return; - } - - uaccess_ttbr0_enable(); - ret = gcssttr(addr, val); - if (ret != 0) - *err = ret; - uaccess_ttbr0_disable(); -} - - -#endif /* CONFIG_ARM64_GCS */ - #endif /* __ASM_UACCESS_H */ diff --git a/arch/arm64/include/asm/vdso/compat_barrier.h b/arch/arm64/include/asm/vdso/compat_barrier.h index 3ac35f4a667c..6d75e03d3827 100644 --- a/arch/arm64/include/asm/vdso/compat_barrier.h +++ b/arch/arm64/include/asm/vdso/compat_barrier.h @@ -7,11 +7,10 @@ #ifndef __ASSEMBLY__ /* - * Warning: This code is meant to be used with - * ENABLE_COMPAT_VDSO only. + * Warning: This code is meant to be used from the compat vDSO only. */ -#ifndef ENABLE_COMPAT_VDSO -#error This header is meant to be used with ENABLE_COMPAT_VDSO only +#ifdef __arch64__ +#error This header is meant to be used with from the compat vDSO only #endif #ifdef dmb diff --git a/arch/arm64/include/asm/vdso/compat_gettimeofday.h b/arch/arm64/include/asm/vdso/compat_gettimeofday.h index d60ea7a72a9c..7d1a116549b1 100644 --- a/arch/arm64/include/asm/vdso/compat_gettimeofday.h +++ b/arch/arm64/include/asm/vdso/compat_gettimeofday.h @@ -2,8 +2,8 @@ /* * Copyright (C) 2018 ARM Limited */ -#ifndef __ASM_VDSO_GETTIMEOFDAY_H -#define __ASM_VDSO_GETTIMEOFDAY_H +#ifndef __ASM_VDSO_COMPAT_GETTIMEOFDAY_H +#define __ASM_VDSO_COMPAT_GETTIMEOFDAY_H #ifndef __ASSEMBLY__ @@ -163,4 +163,4 @@ static inline bool vdso_clocksource_ok(const struct vdso_clock *vc) #endif /* !__ASSEMBLY__ */ -#endif /* __ASM_VDSO_GETTIMEOFDAY_H */ +#endif /* __ASM_VDSO_COMPAT_GETTIMEOFDAY_H */ diff --git a/arch/arm64/include/asm/vdso/gettimeofday.h b/arch/arm64/include/asm/vdso/gettimeofday.h index da1ab8759592..c59e84105b43 100644 --- a/arch/arm64/include/asm/vdso/gettimeofday.h +++ b/arch/arm64/include/asm/vdso/gettimeofday.h @@ -5,6 +5,8 @@ #ifndef __ASM_VDSO_GETTIMEOFDAY_H #define __ASM_VDSO_GETTIMEOFDAY_H +#ifdef __aarch64__ + #ifndef __ASSEMBLY__ #include <asm/alternative.h> @@ -96,4 +98,10 @@ static __always_inline const struct vdso_time_data *__arch_get_vdso_u_time_data( #endif /* !__ASSEMBLY__ */ +#else /* !__aarch64__ */ + +#include "compat_gettimeofday.h" + +#endif /* __aarch64__ */ + #endif /* __ASM_VDSO_GETTIMEOFDAY_H */ diff --git a/arch/arm64/include/asm/vmalloc.h b/arch/arm64/include/asm/vmalloc.h index 12f534e8f3ed..4ec1acd3c1b3 100644 --- a/arch/arm64/include/asm/vmalloc.h +++ b/arch/arm64/include/asm/vmalloc.h @@ -9,18 +9,13 @@ #define arch_vmap_pud_supported arch_vmap_pud_supported static inline bool arch_vmap_pud_supported(pgprot_t prot) { - /* - * SW table walks can't handle removal of intermediate entries. - */ - return pud_sect_supported() && - !IS_ENABLED(CONFIG_PTDUMP_DEBUGFS); + return pud_sect_supported(); } #define arch_vmap_pmd_supported arch_vmap_pmd_supported static inline bool arch_vmap_pmd_supported(pgprot_t prot) { - /* See arch_vmap_pud_supported() */ - return !IS_ENABLED(CONFIG_PTDUMP_DEBUGFS); + return true; } #define arch_vmap_pte_range_map_size arch_vmap_pte_range_map_size diff --git a/arch/arm64/include/asm/vncr_mapping.h b/arch/arm64/include/asm/vncr_mapping.h index f6ec500ad3fa..c2485a862e69 100644 --- a/arch/arm64/include/asm/vncr_mapping.h +++ b/arch/arm64/include/asm/vncr_mapping.h @@ -94,6 +94,8 @@ #define VNCR_PMSICR_EL1 0x838 #define VNCR_PMSIRR_EL1 0x840 #define VNCR_PMSLATFR_EL1 0x848 +#define VNCR_PMSNEVFR_EL1 0x850 +#define VNCR_PMSDSFR_EL1 0x858 #define VNCR_TRFCR_EL1 0x880 #define VNCR_MPAM1_EL1 0x900 #define VNCR_MPAMHCR_EL2 0x930 diff --git a/arch/arm64/include/asm/xen/events.h b/arch/arm64/include/asm/xen/events.h index 2788e95d0ff0..2977b5fe068d 100644 --- a/arch/arm64/include/asm/xen/events.h +++ b/arch/arm64/include/asm/xen/events.h @@ -14,7 +14,7 @@ enum ipi_vector { static inline int xen_irqs_disabled(struct pt_regs *regs) { - return !interrupts_enabled(regs); + return regs_irqs_disabled(regs); } #define xchg_xen_ulong(ptr, val) xchg((ptr), (val)) diff --git a/arch/arm64/include/uapi/asm/bitsperlong.h b/arch/arm64/include/uapi/asm/bitsperlong.h index 485d60bee26c..d59730975f30 100644 --- a/arch/arm64/include/uapi/asm/bitsperlong.h +++ b/arch/arm64/include/uapi/asm/bitsperlong.h @@ -17,7 +17,12 @@ #ifndef __ASM_BITSPERLONG_H #define __ASM_BITSPERLONG_H +#if defined(__KERNEL__) && !defined(__aarch64__) +/* Used by the compat vDSO */ +#define __BITS_PER_LONG 32 +#else #define __BITS_PER_LONG 64 +#endif #include <asm-generic/bitsperlong.h> diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h index 72c78468b806..575564ecdb0b 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -145,5 +145,6 @@ */ #define HWCAP3_MTE_FAR (1UL << 0) #define HWCAP3_MTE_STORE_ONLY (1UL << 1) +#define HWCAP3_LSFE (1UL << 2) #endif /* _UAPI__ASM_HWCAP_H */ diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c index 4d529ff7ba51..7aca29e1d30b 100644 --- a/arch/arm64/kernel/acpi.c +++ b/arch/arm64/kernel/acpi.c @@ -357,6 +357,16 @@ void __iomem *acpi_os_ioremap(acpi_physical_address phys, acpi_size size) * as long as we take care not to create a writable * mapping for executable code. */ + fallthrough; + + case EFI_ACPI_MEMORY_NVS: + /* + * ACPI NVS marks an area reserved for use by the + * firmware, even after exiting the boot service. + * This may be used by the firmware for sharing dynamic + * tables/data (e.g., ACPI CCEL) with the OS. Map it + * as read-only. + */ prot = PAGE_KERNEL_RO; break; @@ -407,7 +417,7 @@ int apei_claim_sea(struct pt_regs *regs) return_to_irqs_enabled = !irqs_disabled_flags(arch_local_save_flags()); if (regs) - return_to_irqs_enabled = interrupts_enabled(regs); + return_to_irqs_enabled = !regs_irqs_disabled(regs); /* * SEA can interrupt SError, mask it and describe this as an NMI so diff --git a/arch/arm64/kernel/asm-offsets.c b/arch/arm64/kernel/asm-offsets.c index 30d4bbe68661..b6367ff3a49c 100644 --- a/arch/arm64/kernel/asm-offsets.c +++ b/arch/arm64/kernel/asm-offsets.c @@ -6,6 +6,7 @@ * 2001-2002 Keith Owens * Copyright (C) 2012 ARM Ltd. */ +#define COMPILE_OFFSETS #include <linux/arm_sdei.h> #include <linux/sched.h> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 59d723c9ab8f..8cb3b575a031 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -531,6 +531,7 @@ static const struct midr_range erratum_spec_ssbs_list[] = { MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), MIDR_ALL_VERSIONS(MIDR_CORTEX_A715), MIDR_ALL_VERSIONS(MIDR_CORTEX_A720), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE), MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), MIDR_ALL_VERSIONS(MIDR_CORTEX_X1), MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C), @@ -545,6 +546,7 @@ static const struct midr_range erratum_spec_ssbs_list[] = { MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2), MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3AE), {} }; #endif diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 1f6e8c87aae7..3917ad897801 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -279,6 +279,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { static const struct arm64_ftr_bits ftr_id_aa64isar3[] = { ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FPRCVT_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_LSFE_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0), ARM64_FTR_END, }; @@ -2028,6 +2029,7 @@ static void __init kpti_install_ng_mappings(void) if (arm64_use_ng_mappings) return; + init_idmap_kpti_bbml2_flag(); stop_machine(__kpti_install_ng_mappings, NULL, cpu_online_mask); } @@ -2218,7 +2220,7 @@ static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE); } -static bool has_bbml2_noabort(const struct arm64_cpu_capabilities *caps, int scope) +bool cpu_supports_bbml2_noabort(void) { /* * We want to allow usage of BBML2 in as wide a range of kernel contexts @@ -2235,6 +2237,10 @@ static bool has_bbml2_noabort(const struct arm64_cpu_capabilities *caps, int sco static const struct midr_range supports_bbml2_noabort_list[] = { MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf), MIDR_REV_RANGE(MIDR_NEOVERSE_V3, 0, 2, 0xf), + MIDR_REV_RANGE(MIDR_NEOVERSE_V3AE, 0, 2, 0xf), + MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), + MIDR_ALL_VERSIONS(MIDR_AMPERE1), + MIDR_ALL_VERSIONS(MIDR_AMPERE1A), {} }; @@ -2250,6 +2256,11 @@ static bool has_bbml2_noabort(const struct arm64_cpu_capabilities *caps, int sco return true; } +static bool has_bbml2_noabort(const struct arm64_cpu_capabilities *caps, int scope) +{ + return cpu_supports_bbml2_noabort(); +} + #ifdef CONFIG_ARM64_PAN static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) { @@ -2539,6 +2550,15 @@ test_has_mpam_hcr(const struct arm64_cpu_capabilities *entry, int scope) return idr & MPAMIDR_EL1_HAS_HCR; } +static bool +test_has_gicv5_legacy(const struct arm64_cpu_capabilities *entry, int scope) +{ + if (!this_cpu_has_cap(ARM64_HAS_GICV5_CPUIF)) + return false; + + return !!(read_sysreg_s(SYS_ICC_IDR0_EL1) & ICC_IDR0_EL1_GCIE_LEGACY); +} + static const struct arm64_cpu_capabilities arm64_features[] = { { .capability = ARM64_ALWAYS_BOOT, @@ -3156,6 +3176,12 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .matches = has_cpuid_feature, ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, GCIE, IMP) }, + { + .desc = "GICv5 Legacy vCPU interface", + .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, + .capability = ARM64_HAS_GICV5_LEGACY, + .matches = test_has_gicv5_legacy, + }, {}, }; @@ -3277,6 +3303,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT), HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX), + HWCAP_CAP(ID_AA64ISAR3_EL1, LSFE, IMP, CAP_HWCAP, KERNEL_HWCAP_LSFE), HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), #ifdef CONFIG_ARM64_SVE HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), @@ -3948,6 +3975,7 @@ void __init setup_system_features(void) { setup_system_capabilities(); + linear_map_maybe_split_to_ptes(); kpti_install_ng_mappings(); sve_setup(); diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index ba834909a28b..c44e6d94f5de 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -162,6 +162,7 @@ static const char *const hwcap_str[] = { [KERNEL_HWCAP_SME_SMOP4] = "smesmop4", [KERNEL_HWCAP_MTE_FAR] = "mtefar", [KERNEL_HWCAP_MTE_STORE_ONLY] = "mtestoreonly", + [KERNEL_HWCAP_LSFE] = "lsfe", }; #ifdef CONFIG_COMPAT diff --git a/arch/arm64/kernel/debug-monitors.c b/arch/arm64/kernel/debug-monitors.c index 110d9ff54174..29307642f4c9 100644 --- a/arch/arm64/kernel/debug-monitors.c +++ b/arch/arm64/kernel/debug-monitors.c @@ -167,7 +167,7 @@ static void send_user_sigtrap(int si_code) if (WARN_ON(!user_mode(regs))) return; - if (interrupts_enabled(regs)) + if (!regs_irqs_disabled(regs)) local_irq_enable(); arm64_force_sig_fault(SIGTRAP, si_code, instruction_pointer(regs), @@ -212,7 +212,7 @@ static int call_el1_break_hook(struct pt_regs *regs, unsigned long esr) if (esr_brk_comment(esr) == BUG_BRK_IMM) return bug_brk_handler(regs, esr); - if (IS_ENABLED(CONFIG_CFI_CLANG) && esr_is_cfi_brk(esr)) + if (IS_ENABLED(CONFIG_CFI) && esr_is_cfi_brk(esr)) return cfi_brk_handler(regs, esr); if (esr_brk_comment(esr) == FAULT_BRK_IMM) diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-common.c index 2b0c5925502e..f546a914f041 100644 --- a/arch/arm64/kernel/entry-common.c +++ b/arch/arm64/kernel/entry-common.c @@ -6,6 +6,7 @@ */ #include <linux/context_tracking.h> +#include <linux/irq-entry-common.h> #include <linux/kasan.h> #include <linux/linkage.h> #include <linux/livepatch.h> @@ -37,29 +38,20 @@ * This is intended to match the logic in irqentry_enter(), handling the kernel * mode transitions only. */ -static __always_inline void __enter_from_kernel_mode(struct pt_regs *regs) +static __always_inline irqentry_state_t __enter_from_kernel_mode(struct pt_regs *regs) { - regs->exit_rcu = false; - - if (!IS_ENABLED(CONFIG_TINY_RCU) && is_idle_task(current)) { - lockdep_hardirqs_off(CALLER_ADDR0); - ct_irq_enter(); - trace_hardirqs_off_finish(); - - regs->exit_rcu = true; - return; - } - - lockdep_hardirqs_off(CALLER_ADDR0); - rcu_irq_enter_check_tick(); - trace_hardirqs_off_finish(); + return irqentry_enter(regs); } -static void noinstr enter_from_kernel_mode(struct pt_regs *regs) +static noinstr irqentry_state_t enter_from_kernel_mode(struct pt_regs *regs) { - __enter_from_kernel_mode(regs); + irqentry_state_t state; + + state = __enter_from_kernel_mode(regs); mte_check_tfsr_entry(); mte_disable_tco_entry(current); + + return state; } /* @@ -70,30 +62,17 @@ static void noinstr enter_from_kernel_mode(struct pt_regs *regs) * This is intended to match the logic in irqentry_exit(), handling the kernel * mode transitions only, and with preemption handled elsewhere. */ -static __always_inline void __exit_to_kernel_mode(struct pt_regs *regs) -{ - lockdep_assert_irqs_disabled(); - - if (interrupts_enabled(regs)) { - if (regs->exit_rcu) { - trace_hardirqs_on_prepare(); - lockdep_hardirqs_on_prepare(); - ct_irq_exit(); - lockdep_hardirqs_on(CALLER_ADDR0); - return; - } - - trace_hardirqs_on(); - } else { - if (regs->exit_rcu) - ct_irq_exit(); - } +static __always_inline void __exit_to_kernel_mode(struct pt_regs *regs, + irqentry_state_t state) +{ + irqentry_exit(regs, state); } -static void noinstr exit_to_kernel_mode(struct pt_regs *regs) +static void noinstr exit_to_kernel_mode(struct pt_regs *regs, + irqentry_state_t state) { mte_check_tfsr_exit(); - __exit_to_kernel_mode(regs); + __exit_to_kernel_mode(regs, state); } /* @@ -101,18 +80,15 @@ static void noinstr exit_to_kernel_mode(struct pt_regs *regs) * Before this function is called it is not safe to call regular kernel code, * instrumentable code, or any code which may trigger an exception. */ -static __always_inline void __enter_from_user_mode(void) +static __always_inline void __enter_from_user_mode(struct pt_regs *regs) { - lockdep_hardirqs_off(CALLER_ADDR0); - CT_WARN_ON(ct_state() != CT_STATE_USER); - user_exit_irqoff(); - trace_hardirqs_off_finish(); + enter_from_user_mode(regs); mte_disable_tco_entry(current); } -static __always_inline void enter_from_user_mode(struct pt_regs *regs) +static __always_inline void arm64_enter_from_user_mode(struct pt_regs *regs) { - __enter_from_user_mode(); + __enter_from_user_mode(regs); } /* @@ -120,113 +96,19 @@ static __always_inline void enter_from_user_mode(struct pt_regs *regs) * After this function returns it is not safe to call regular kernel code, * instrumentable code, or any code which may trigger an exception. */ -static __always_inline void __exit_to_user_mode(void) -{ - trace_hardirqs_on_prepare(); - lockdep_hardirqs_on_prepare(); - user_enter_irqoff(); - lockdep_hardirqs_on(CALLER_ADDR0); -} - -static void do_notify_resume(struct pt_regs *regs, unsigned long thread_flags) -{ - do { - local_irq_enable(); - - if (thread_flags & (_TIF_NEED_RESCHED | _TIF_NEED_RESCHED_LAZY)) - schedule(); - - if (thread_flags & _TIF_UPROBE) - uprobe_notify_resume(regs); - - if (thread_flags & _TIF_MTE_ASYNC_FAULT) { - clear_thread_flag(TIF_MTE_ASYNC_FAULT); - send_sig_fault(SIGSEGV, SEGV_MTEAERR, - (void __user *)NULL, current); - } - - if (thread_flags & _TIF_PATCH_PENDING) - klp_update_patch_state(current); - if (thread_flags & (_TIF_SIGPENDING | _TIF_NOTIFY_SIGNAL)) - do_signal(regs); - - if (thread_flags & _TIF_NOTIFY_RESUME) - resume_user_mode_work(regs); - - if (thread_flags & _TIF_FOREIGN_FPSTATE) - fpsimd_restore_current_state(); - - local_irq_disable(); - thread_flags = read_thread_flags(); - } while (thread_flags & _TIF_WORK_MASK); -} - -static __always_inline void exit_to_user_mode_prepare(struct pt_regs *regs) +static __always_inline void arm64_exit_to_user_mode(struct pt_regs *regs) { - unsigned long flags; - local_irq_disable(); - - flags = read_thread_flags(); - if (unlikely(flags & _TIF_WORK_MASK)) - do_notify_resume(regs, flags); - - local_daif_mask(); - - lockdep_sys_exit(); -} - -static __always_inline void exit_to_user_mode(struct pt_regs *regs) -{ exit_to_user_mode_prepare(regs); + local_daif_mask(); mte_check_tfsr_exit(); - __exit_to_user_mode(); + exit_to_user_mode(); } asmlinkage void noinstr asm_exit_to_user_mode(struct pt_regs *regs) { - exit_to_user_mode(regs); -} - -/* - * Handle IRQ/context state management when entering an NMI from user/kernel - * mode. Before this function is called it is not safe to call regular kernel - * code, instrumentable code, or any code which may trigger an exception. - */ -static void noinstr arm64_enter_nmi(struct pt_regs *regs) -{ - regs->lockdep_hardirqs = lockdep_hardirqs_enabled(); - - __nmi_enter(); - lockdep_hardirqs_off(CALLER_ADDR0); - lockdep_hardirq_enter(); - ct_nmi_enter(); - - trace_hardirqs_off_finish(); - ftrace_nmi_enter(); -} - -/* - * Handle IRQ/context state management when exiting an NMI from user/kernel - * mode. After this function returns it is not safe to call regular kernel - * code, instrumentable code, or any code which may trigger an exception. - */ -static void noinstr arm64_exit_nmi(struct pt_regs *regs) -{ - bool restore = regs->lockdep_hardirqs; - - ftrace_nmi_exit(); - if (restore) { - trace_hardirqs_on_prepare(); - lockdep_hardirqs_on_prepare(); - } - - ct_nmi_exit(); - lockdep_hardirq_exit(); - if (restore) - lockdep_hardirqs_on(CALLER_ADDR0); - __nmi_exit(); + arm64_exit_to_user_mode(regs); } /* @@ -234,14 +116,18 @@ static void noinstr arm64_exit_nmi(struct pt_regs *regs) * kernel mode. Before this function is called it is not safe to call regular * kernel code, instrumentable code, or any code which may trigger an exception. */ -static void noinstr arm64_enter_el1_dbg(struct pt_regs *regs) +static noinstr irqentry_state_t arm64_enter_el1_dbg(struct pt_regs *regs) { - regs->lockdep_hardirqs = lockdep_hardirqs_enabled(); + irqentry_state_t state; + + state.lockdep = lockdep_hardirqs_enabled(); lockdep_hardirqs_off(CALLER_ADDR0); ct_nmi_enter(); trace_hardirqs_off_finish(); + + return state; } /* @@ -249,62 +135,19 @@ static void noinstr arm64_enter_el1_dbg(struct pt_regs *regs) * kernel mode. After this function returns it is not safe to call regular * kernel code, instrumentable code, or any code which may trigger an exception. */ -static void noinstr arm64_exit_el1_dbg(struct pt_regs *regs) +static void noinstr arm64_exit_el1_dbg(struct pt_regs *regs, + irqentry_state_t state) { - bool restore = regs->lockdep_hardirqs; - - if (restore) { + if (state.lockdep) { trace_hardirqs_on_prepare(); lockdep_hardirqs_on_prepare(); } ct_nmi_exit(); - if (restore) + if (state.lockdep) lockdep_hardirqs_on(CALLER_ADDR0); } -#ifdef CONFIG_PREEMPT_DYNAMIC -DEFINE_STATIC_KEY_TRUE(sk_dynamic_irqentry_exit_cond_resched); -#define need_irq_preemption() \ - (static_branch_unlikely(&sk_dynamic_irqentry_exit_cond_resched)) -#else -#define need_irq_preemption() (IS_ENABLED(CONFIG_PREEMPTION)) -#endif - -static void __sched arm64_preempt_schedule_irq(void) -{ - if (!need_irq_preemption()) - return; - - /* - * Note: thread_info::preempt_count includes both thread_info::count - * and thread_info::need_resched, and is not equivalent to - * preempt_count(). - */ - if (READ_ONCE(current_thread_info()->preempt_count) != 0) - return; - - /* - * DAIF.DA are cleared at the start of IRQ/FIQ handling, and when GIC - * priority masking is used the GIC irqchip driver will clear DAIF.IF - * using gic_arch_enable_irqs() for normal IRQs. If anything is set in - * DAIF we must have handled an NMI, so skip preemption. - */ - if (system_uses_irq_prio_masking() && read_sysreg(daif)) - return; - - /* - * Preempting a task from an IRQ means we leave copies of PSTATE - * on the stack. cpufeature's enable calls may modify PSTATE, but - * resuming one of these preempted tasks would undo those changes. - * - * Only allow a task to be preempted once cpufeatures have been - * enabled. - */ - if (system_capabilities_finalized()) - preempt_schedule_irq(); -} - static void do_interrupt_handler(struct pt_regs *regs, void (*handler)(struct pt_regs *)) { @@ -324,7 +167,7 @@ extern void (*handle_arch_fiq)(struct pt_regs *); static void noinstr __panic_unhandled(struct pt_regs *regs, const char *vector, unsigned long esr) { - arm64_enter_nmi(regs); + irqentry_nmi_enter(regs); console_verbose(); @@ -475,73 +318,87 @@ UNHANDLED(el1t, 64, error) static void noinstr el1_abort(struct pt_regs *regs, unsigned long esr) { unsigned long far = read_sysreg(far_el1); + irqentry_state_t state; - enter_from_kernel_mode(regs); + state = enter_from_kernel_mode(regs); local_daif_inherit(regs); do_mem_abort(far, esr, regs); local_daif_mask(); - exit_to_kernel_mode(regs); + exit_to_kernel_mode(regs, state); } static void noinstr el1_pc(struct pt_regs *regs, unsigned long esr) { unsigned long far = read_sysreg(far_el1); + irqentry_state_t state; - enter_from_kernel_mode(regs); + state = enter_from_kernel_mode(regs); local_daif_inherit(regs); do_sp_pc_abort(far, esr, regs); local_daif_mask(); - exit_to_kernel_mode(regs); + exit_to_kernel_mode(regs, state); } static void noinstr el1_undef(struct pt_regs *regs, unsigned long esr) { - enter_from_kernel_mode(regs); + irqentry_state_t state; + + state = enter_from_kernel_mode(regs); local_daif_inherit(regs); do_el1_undef(regs, esr); local_daif_mask(); - exit_to_kernel_mode(regs); + exit_to_kernel_mode(regs, state); } static void noinstr el1_bti(struct pt_regs *regs, unsigned long esr) { - enter_from_kernel_mode(regs); + irqentry_state_t state; + + state = enter_from_kernel_mode(regs); local_daif_inherit(regs); do_el1_bti(regs, esr); local_daif_mask(); - exit_to_kernel_mode(regs); + exit_to_kernel_mode(regs, state); } static void noinstr el1_gcs(struct pt_regs *regs, unsigned long esr) { - enter_from_kernel_mode(regs); + irqentry_state_t state; + + state = enter_from_kernel_mode(regs); local_daif_inherit(regs); do_el1_gcs(regs, esr); local_daif_mask(); - exit_to_kernel_mode(regs); + exit_to_kernel_mode(regs, state); } static void noinstr el1_mops(struct pt_regs *regs, unsigned long esr) { - enter_from_kernel_mode(regs); + irqentry_state_t state; + + state = enter_from_kernel_mode(regs); local_daif_inherit(regs); do_el1_mops(regs, esr); local_daif_mask(); - exit_to_kernel_mode(regs); + exit_to_kernel_mode(regs, state); } static void noinstr el1_breakpt(struct pt_regs *regs, unsigned long esr) { - arm64_enter_el1_dbg(regs); + irqentry_state_t state; + + state = arm64_enter_el1_dbg(regs); debug_exception_enter(regs); do_breakpoint(esr, regs); debug_exception_exit(regs); - arm64_exit_el1_dbg(regs); + arm64_exit_el1_dbg(regs, state); } static void noinstr el1_softstp(struct pt_regs *regs, unsigned long esr) { - arm64_enter_el1_dbg(regs); + irqentry_state_t state; + + state = arm64_enter_el1_dbg(regs); if (!cortex_a76_erratum_1463225_debug_handler(regs)) { debug_exception_enter(regs); /* @@ -554,37 +411,42 @@ static void noinstr el1_softstp(struct pt_regs *regs, unsigned long esr) do_el1_softstep(esr, regs); debug_exception_exit(regs); } - arm64_exit_el1_dbg(regs); + arm64_exit_el1_dbg(regs, state); } static void noinstr el1_watchpt(struct pt_regs *regs, unsigned long esr) { /* Watchpoints are the only debug exception to write FAR_EL1 */ unsigned long far = read_sysreg(far_el1); + irqentry_state_t state; - arm64_enter_el1_dbg(regs); + state = arm64_enter_el1_dbg(regs); debug_exception_enter(regs); do_watchpoint(far, esr, regs); debug_exception_exit(regs); - arm64_exit_el1_dbg(regs); + arm64_exit_el1_dbg(regs, state); } static void noinstr el1_brk64(struct pt_regs *regs, unsigned long esr) { - arm64_enter_el1_dbg(regs); + irqentry_state_t state; + + state = arm64_enter_el1_dbg(regs); debug_exception_enter(regs); do_el1_brk64(esr, regs); debug_exception_exit(regs); - arm64_exit_el1_dbg(regs); + arm64_exit_el1_dbg(regs, state); } static void noinstr el1_fpac(struct pt_regs *regs, unsigned long esr) { - enter_from_kernel_mode(regs); + irqentry_state_t state; + + state = enter_from_kernel_mode(regs); local_daif_inherit(regs); do_el1_fpac(regs, esr); local_daif_mask(); - exit_to_kernel_mode(regs); + exit_to_kernel_mode(regs, state); } asmlinkage void noinstr el1h_64_sync_handler(struct pt_regs *regs) @@ -639,30 +501,32 @@ asmlinkage void noinstr el1h_64_sync_handler(struct pt_regs *regs) static __always_inline void __el1_pnmi(struct pt_regs *regs, void (*handler)(struct pt_regs *)) { - arm64_enter_nmi(regs); + irqentry_state_t state; + + state = irqentry_nmi_enter(regs); do_interrupt_handler(regs, handler); - arm64_exit_nmi(regs); + irqentry_nmi_exit(regs, state); } static __always_inline void __el1_irq(struct pt_regs *regs, void (*handler)(struct pt_regs *)) { - enter_from_kernel_mode(regs); + irqentry_state_t state; + + state = enter_from_kernel_mode(regs); irq_enter_rcu(); do_interrupt_handler(regs, handler); irq_exit_rcu(); - arm64_preempt_schedule_irq(); - - exit_to_kernel_mode(regs); + exit_to_kernel_mode(regs, state); } static void noinstr el1_interrupt(struct pt_regs *regs, void (*handler)(struct pt_regs *)) { write_sysreg(DAIF_PROCCTX_NOIRQ, daif); - if (IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && !interrupts_enabled(regs)) + if (IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && regs_irqs_disabled(regs)) __el1_pnmi(regs, handler); else __el1_irq(regs, handler); @@ -681,21 +545,22 @@ asmlinkage void noinstr el1h_64_fiq_handler(struct pt_regs *regs) asmlinkage void noinstr el1h_64_error_handler(struct pt_regs *regs) { unsigned long esr = read_sysreg(esr_el1); + irqentry_state_t state; local_daif_restore(DAIF_ERRCTX); - arm64_enter_nmi(regs); + state = irqentry_nmi_enter(regs); do_serror(regs, esr); - arm64_exit_nmi(regs); + irqentry_nmi_exit(regs, state); } static void noinstr el0_da(struct pt_regs *regs, unsigned long esr) { unsigned long far = read_sysreg(far_el1); - enter_from_user_mode(regs); + arm64_enter_from_user_mode(regs); local_daif_restore(DAIF_PROCCTX); do_mem_abort(far, esr, regs); - exit_to_user_mode(regs); + arm64_exit_to_user_mode(regs); } static void noinstr el0_ia(struct pt_regs *regs, unsigned long esr) @@ -710,50 +575,50 @@ static void noinstr el0_ia(struct pt_regs *regs, unsigned long esr) if (!is_ttbr0_addr(far)) arm64_apply_bp_hardening(); - enter_from_user_mode(regs); + arm64_enter_from_user_mode(regs); local_daif_restore(DAIF_PROCCTX); do_mem_abort(far, esr, regs); - exit_to_user_mode(regs); + arm64_exit_to_user_mode(regs); } static void noinstr el0_fpsimd_acc(struct pt_regs *regs, unsigned long esr) { - enter_from_user_mode(regs); + arm64_enter_from_user_mode(regs); local_daif_restore(DAIF_PROCCTX); do_fpsimd_acc(esr, regs); - exit_to_user_mode(regs); + arm64_exit_to_user_mode(regs); } static void noinstr el0_sve_acc(struct pt_regs *regs, unsigned long esr) { - enter_from_user_mode(regs); + arm64_enter_from_user_mode(regs); local_daif_restore(DAIF_PROCCTX); do_sve_acc(esr, regs); - exit_to_user_mode(regs); + arm64_exit_to_user_mode(regs); } static void noinstr el0_sme_acc(struct pt_regs *regs, unsigned long esr) { - enter_from_user_mode(regs); + arm64_enter_from_user_mode(regs); local_daif_restore(DAIF_PROCCTX); do_sme_acc(esr, regs); - exit_to_user_mode(regs); + arm64_exit_to_user_mode(regs); } static void noinstr el0_fpsimd_exc(struct pt_regs *regs, unsigned long esr) { - enter_from_user_mode(regs); + arm64_enter_from_user_mode(regs); local_daif_restore(DAIF_PROCCTX); do_fpsimd_exc(esr, regs); - exit_to_user_mode(regs); + arm64_exit_to_user_mode(regs); } static void noinstr el0_sys(struct pt_regs *regs, unsigned long esr) { - enter_from_user_mode(regs); + arm64_enter_from_user_mode(regs); local_daif_restore(DAIF_PROCCTX); do_el0_sys(esr, regs); - exit_to_user_mode(regs); + arm64_exit_to_user_mode(regs); } static void noinstr el0_pc(struct pt_regs *regs, unsigned long esr) @@ -763,58 +628,58 @@ static void noinstr el0_pc(struct pt_regs *regs, unsigned long esr) if (!is_ttbr0_addr(instruction_pointer(regs))) arm64_apply_bp_hardening(); - enter_from_user_mode(regs); + arm64_enter_from_user_mode(regs); local_daif_restore(DAIF_PROCCTX); do_sp_pc_abort(far, esr, regs); - exit_to_user_mode(regs); + arm64_exit_to_user_mode(regs); } static void noinstr el0_sp(struct pt_regs *regs, unsigned long esr) { - enter_from_user_mode(regs); + arm64_enter_from_user_mode(regs); local_daif_restore(DAIF_PROCCTX); do_sp_pc_abort(regs->sp, esr, regs); - exit_to_user_mode(regs); + arm64_exit_to_user_mode(regs); } static void noinstr el0_undef(struct pt_regs *regs, unsigned long esr) { - enter_from_user_mode(regs); + arm64_enter_from_user_mode(regs); local_daif_restore(DAIF_PROCCTX); do_el0_undef(regs, esr); - exit_to_user_mode(regs); + arm64_exit_to_user_mode(regs); } static void noinstr el0_bti(struct pt_regs *regs) { - enter_from_user_mode(regs); + arm64_enter_from_user_mode(regs); local_daif_restore(DAIF_PROCCTX); do_el0_bti(regs); - exit_to_user_mode(regs); + arm64_exit_to_user_mode(regs); } static void noinstr el0_mops(struct pt_regs *regs, unsigned long esr) { - enter_from_user_mode(regs); + arm64_enter_from_user_mode(regs); local_daif_restore(DAIF_PROCCTX); do_el0_mops(regs, esr); - exit_to_user_mode(regs); + arm64_exit_to_user_mode(regs); } static void noinstr el0_gcs(struct pt_regs *regs, unsigned long esr) { - enter_from_user_mode(regs); + arm64_enter_from_user_mode(regs); local_daif_restore(DAIF_PROCCTX); do_el0_gcs(regs, esr); - exit_to_user_mode(regs); + arm64_exit_to_user_mode(regs); } static void noinstr el0_inv(struct pt_regs *regs, unsigned long esr) { - enter_from_user_mode(regs); + arm64_enter_from_user_mode(regs); local_daif_restore(DAIF_PROCCTX); bad_el0_sync(regs, 0, esr); - exit_to_user_mode(regs); + arm64_exit_to_user_mode(regs); } static void noinstr el0_breakpt(struct pt_regs *regs, unsigned long esr) @@ -822,12 +687,12 @@ static void noinstr el0_breakpt(struct pt_regs *regs, unsigned long esr) if (!is_ttbr0_addr(regs->pc)) arm64_apply_bp_hardening(); - enter_from_user_mode(regs); + arm64_enter_from_user_mode(regs); debug_exception_enter(regs); do_breakpoint(esr, regs); debug_exception_exit(regs); local_daif_restore(DAIF_PROCCTX); - exit_to_user_mode(regs); + arm64_exit_to_user_mode(regs); } static void noinstr el0_softstp(struct pt_regs *regs, unsigned long esr) @@ -835,7 +700,7 @@ static void noinstr el0_softstp(struct pt_regs *regs, unsigned long esr) if (!is_ttbr0_addr(regs->pc)) arm64_apply_bp_hardening(); - enter_from_user_mode(regs); + arm64_enter_from_user_mode(regs); /* * After handling a breakpoint, we suspend the breakpoint * and use single-step to move to the next instruction. @@ -846,7 +711,7 @@ static void noinstr el0_softstp(struct pt_regs *regs, unsigned long esr) local_daif_restore(DAIF_PROCCTX); do_el0_softstep(esr, regs); } - exit_to_user_mode(regs); + arm64_exit_to_user_mode(regs); } static void noinstr el0_watchpt(struct pt_regs *regs, unsigned long esr) @@ -854,39 +719,39 @@ static void noinstr el0_watchpt(struct pt_regs *regs, unsigned long esr) /* Watchpoints are the only debug exception to write FAR_EL1 */ unsigned long far = read_sysreg(far_el1); - enter_from_user_mode(regs); + arm64_enter_from_user_mode(regs); debug_exception_enter(regs); do_watchpoint(far, esr, regs); debug_exception_exit(regs); local_daif_restore(DAIF_PROCCTX); - exit_to_user_mode(regs); + arm64_exit_to_user_mode(regs); } static void noinstr el0_brk64(struct pt_regs *regs, unsigned long esr) { - enter_from_user_mode(regs); + arm64_enter_from_user_mode(regs); local_daif_restore(DAIF_PROCCTX); do_el0_brk64(esr, regs); - exit_to_user_mode(regs); + arm64_exit_to_user_mode(regs); } static void noinstr el0_svc(struct pt_regs *regs) { - enter_from_user_mode(regs); + arm64_enter_from_user_mode(regs); cortex_a76_erratum_1463225_svc_handler(); fpsimd_syscall_enter(); local_daif_restore(DAIF_PROCCTX); do_el0_svc(regs); - exit_to_user_mode(regs); + arm64_exit_to_user_mode(regs); fpsimd_syscall_exit(); } static void noinstr el0_fpac(struct pt_regs *regs, unsigned long esr) { - enter_from_user_mode(regs); + arm64_enter_from_user_mode(regs); local_daif_restore(DAIF_PROCCTX); do_el0_fpac(regs, esr); - exit_to_user_mode(regs); + arm64_exit_to_user_mode(regs); } asmlinkage void noinstr el0t_64_sync_handler(struct pt_regs *regs) @@ -960,7 +825,7 @@ asmlinkage void noinstr el0t_64_sync_handler(struct pt_regs *regs) static void noinstr el0_interrupt(struct pt_regs *regs, void (*handler)(struct pt_regs *)) { - enter_from_user_mode(regs); + arm64_enter_from_user_mode(regs); write_sysreg(DAIF_PROCCTX_NOIRQ, daif); @@ -971,7 +836,7 @@ static void noinstr el0_interrupt(struct pt_regs *regs, do_interrupt_handler(regs, handler); irq_exit_rcu(); - exit_to_user_mode(regs); + arm64_exit_to_user_mode(regs); } static void noinstr __el0_irq_handler_common(struct pt_regs *regs) @@ -997,14 +862,15 @@ asmlinkage void noinstr el0t_64_fiq_handler(struct pt_regs *regs) static void noinstr __el0_error_handler_common(struct pt_regs *regs) { unsigned long esr = read_sysreg(esr_el1); + irqentry_state_t state; - enter_from_user_mode(regs); + arm64_enter_from_user_mode(regs); local_daif_restore(DAIF_ERRCTX); - arm64_enter_nmi(regs); + state = irqentry_nmi_enter(regs); do_serror(regs, esr); - arm64_exit_nmi(regs); + irqentry_nmi_exit(regs, state); local_daif_restore(DAIF_PROCCTX); - exit_to_user_mode(regs); + arm64_exit_to_user_mode(regs); } asmlinkage void noinstr el0t_64_error_handler(struct pt_regs *regs) @@ -1015,27 +881,27 @@ asmlinkage void noinstr el0t_64_error_handler(struct pt_regs *regs) #ifdef CONFIG_COMPAT static void noinstr el0_cp15(struct pt_regs *regs, unsigned long esr) { - enter_from_user_mode(regs); + arm64_enter_from_user_mode(regs); local_daif_restore(DAIF_PROCCTX); do_el0_cp15(esr, regs); - exit_to_user_mode(regs); + arm64_exit_to_user_mode(regs); } static void noinstr el0_svc_compat(struct pt_regs *regs) { - enter_from_user_mode(regs); + arm64_enter_from_user_mode(regs); cortex_a76_erratum_1463225_svc_handler(); local_daif_restore(DAIF_PROCCTX); do_el0_svc_compat(regs); - exit_to_user_mode(regs); + arm64_exit_to_user_mode(regs); } static void noinstr el0_bkpt32(struct pt_regs *regs, unsigned long esr) { - enter_from_user_mode(regs); + arm64_enter_from_user_mode(regs); local_daif_restore(DAIF_PROCCTX); do_bkpt32(esr, regs); - exit_to_user_mode(regs); + arm64_exit_to_user_mode(regs); } asmlinkage void noinstr el0t_32_sync_handler(struct pt_regs *regs) @@ -1114,7 +980,7 @@ asmlinkage void noinstr __noreturn handle_bad_stack(struct pt_regs *regs) unsigned long esr = read_sysreg(esr_el1); unsigned long far = read_sysreg(far_el1); - arm64_enter_nmi(regs); + irqentry_nmi_enter(regs); panic_bad_stack(regs, esr, far); } @@ -1122,6 +988,7 @@ asmlinkage void noinstr __noreturn handle_bad_stack(struct pt_regs *regs) asmlinkage noinstr unsigned long __sdei_handler(struct pt_regs *regs, struct sdei_registered_event *arg) { + irqentry_state_t state; unsigned long ret; /* @@ -1146,9 +1013,9 @@ __sdei_handler(struct pt_regs *regs, struct sdei_registered_event *arg) else if (cpu_has_pan()) set_pstate_pan(0); - arm64_enter_nmi(regs); + state = irqentry_nmi_enter(regs); ret = do_sdei_event(regs, arg); - arm64_exit_nmi(regs); + irqentry_nmi_exit(regs, state); return ret; } diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c index c37f02d7194e..e3f8f51748bc 100644 --- a/arch/arm64/kernel/fpsimd.c +++ b/arch/arm64/kernel/fpsimd.c @@ -1265,6 +1265,8 @@ void __init sme_setup(void) if (!system_supports_sme()) return; + min_bit = find_last_bit(info->vq_map, SVE_VQ_MAX); + /* * SME doesn't require any particular vector length be * supported but it does require at least one. We should have @@ -1272,9 +1274,8 @@ void __init sme_setup(void) * let's double check here. The bitmap is SVE_VQ_MAP sized for * sharing with SVE. */ - WARN_ON(bitmap_empty(info->vq_map, SVE_VQ_MAX)); + WARN_ON(min_bit >= SVE_VQ_MAX); - min_bit = find_last_bit(info->vq_map, SVE_VQ_MAX); info->min_vl = sve_vl_from_vq(__bit_to_vq(min_bit)); max_bit = find_first_bit(info->vq_map, SVE_VQ_MAX); diff --git a/arch/arm64/kernel/ftrace.c b/arch/arm64/kernel/ftrace.c index 5a890714ee2e..5adad37ab4fa 100644 --- a/arch/arm64/kernel/ftrace.c +++ b/arch/arm64/kernel/ftrace.c @@ -258,10 +258,17 @@ int ftrace_update_ftrace_func(ftrace_func_t func) return ftrace_modify_code(pc, 0, new, false); } -static struct plt_entry *get_ftrace_plt(struct module *mod) +static struct plt_entry *get_ftrace_plt(struct module *mod, unsigned long addr) { #ifdef CONFIG_MODULES - struct plt_entry *plt = mod->arch.ftrace_trampolines; + struct plt_entry *plt = NULL; + + if (within_module_mem_type(addr, mod, MOD_INIT_TEXT)) + plt = mod->arch.init_ftrace_trampolines; + else if (within_module_mem_type(addr, mod, MOD_TEXT)) + plt = mod->arch.ftrace_trampolines; + else + return NULL; return &plt[FTRACE_PLT_IDX]; #else @@ -332,7 +339,7 @@ static bool ftrace_find_callable_addr(struct dyn_ftrace *rec, if (WARN_ON(!mod)) return false; - plt = get_ftrace_plt(mod); + plt = get_ftrace_plt(mod, pc); if (!plt) { pr_err("ftrace: no module PLT for %ps\n", (void *)*addr); return false; diff --git a/arch/arm64/kernel/image-vars.h b/arch/arm64/kernel/image-vars.h index 714b0b5ec5ac..5369763606e7 100644 --- a/arch/arm64/kernel/image-vars.h +++ b/arch/arm64/kernel/image-vars.h @@ -105,6 +105,9 @@ KVM_NVHE_ALIAS(__hyp_stub_vectors); KVM_NVHE_ALIAS(vgic_v2_cpuif_trap); KVM_NVHE_ALIAS(vgic_v3_cpuif_trap); +/* Static key indicating whether GICv3 has GICv2 compatibility */ +KVM_NVHE_ALIAS(vgic_v3_has_v2_compat); + /* Static key which is set if CNTVOFF_EL2 is unusable */ KVM_NVHE_ALIAS(broken_cntvoff_key); diff --git a/arch/arm64/kernel/module-plts.c b/arch/arm64/kernel/module-plts.c index bde32979c06a..7afd370da9f4 100644 --- a/arch/arm64/kernel/module-plts.c +++ b/arch/arm64/kernel/module-plts.c @@ -283,7 +283,7 @@ int module_frob_arch_sections(Elf_Ehdr *ehdr, Elf_Shdr *sechdrs, unsigned long core_plts = 0; unsigned long init_plts = 0; Elf64_Sym *syms = NULL; - Elf_Shdr *pltsec, *tramp = NULL; + Elf_Shdr *pltsec, *tramp = NULL, *init_tramp = NULL; int i; /* @@ -298,6 +298,9 @@ int module_frob_arch_sections(Elf_Ehdr *ehdr, Elf_Shdr *sechdrs, else if (!strcmp(secstrings + sechdrs[i].sh_name, ".text.ftrace_trampoline")) tramp = sechdrs + i; + else if (!strcmp(secstrings + sechdrs[i].sh_name, + ".init.text.ftrace_trampoline")) + init_tramp = sechdrs + i; else if (sechdrs[i].sh_type == SHT_SYMTAB) syms = (Elf64_Sym *)sechdrs[i].sh_addr; } @@ -363,5 +366,12 @@ int module_frob_arch_sections(Elf_Ehdr *ehdr, Elf_Shdr *sechdrs, tramp->sh_size = NR_FTRACE_PLTS * sizeof(struct plt_entry); } + if (init_tramp) { + init_tramp->sh_type = SHT_NOBITS; + init_tramp->sh_flags = SHF_EXECINSTR | SHF_ALLOC; + init_tramp->sh_addralign = __alignof__(struct plt_entry); + init_tramp->sh_size = NR_FTRACE_PLTS * sizeof(struct plt_entry); + } + return 0; } diff --git a/arch/arm64/kernel/module.c b/arch/arm64/kernel/module.c index 40148d2725ce..d6d443c4a01a 100644 --- a/arch/arm64/kernel/module.c +++ b/arch/arm64/kernel/module.c @@ -466,6 +466,17 @@ static int module_init_ftrace_plt(const Elf_Ehdr *hdr, __init_plt(&plts[FTRACE_PLT_IDX], FTRACE_ADDR); mod->arch.ftrace_trampolines = plts; + + s = find_section(hdr, sechdrs, ".init.text.ftrace_trampoline"); + if (!s) + return -ENOEXEC; + + plts = (void *)s->sh_addr; + + __init_plt(&plts[FTRACE_PLT_IDX], FTRACE_ADDR); + + mod->arch.init_ftrace_trampolines = plts; + #endif return 0; } diff --git a/arch/arm64/kernel/pi/map_kernel.c b/arch/arm64/kernel/pi/map_kernel.c index 0f4bd7771859..e8ddbde31a83 100644 --- a/arch/arm64/kernel/pi/map_kernel.c +++ b/arch/arm64/kernel/pi/map_kernel.c @@ -18,9 +18,9 @@ extern const u8 __eh_frame_start[], __eh_frame_end[]; -extern void idmap_cpu_replace_ttbr1(void *pgdir); +extern void idmap_cpu_replace_ttbr1(phys_addr_t pgdir); -static void __init map_segment(pgd_t *pg_dir, u64 *pgd, u64 va_offset, +static void __init map_segment(pgd_t *pg_dir, phys_addr_t *pgd, u64 va_offset, void *start, void *end, pgprot_t prot, bool may_use_cont, int root_level) { @@ -40,7 +40,7 @@ static void __init map_kernel(u64 kaslr_offset, u64 va_offset, int root_level) { bool enable_scs = IS_ENABLED(CONFIG_UNWIND_PATCH_PAC_INTO_SCS); bool twopass = IS_ENABLED(CONFIG_RELOCATABLE); - u64 pgdp = (u64)init_pg_dir + PAGE_SIZE; + phys_addr_t pgdp = (phys_addr_t)init_pg_dir + PAGE_SIZE; pgprot_t text_prot = PAGE_KERNEL_ROX; pgprot_t data_prot = PAGE_KERNEL; pgprot_t prot; @@ -78,6 +78,12 @@ static void __init map_kernel(u64 kaslr_offset, u64 va_offset, int root_level) twopass |= enable_scs; prot = twopass ? data_prot : text_prot; + /* + * [_stext, _text) isn't executed after boot and contains some + * non-executable, unpredictable data, so map it non-executable. + */ + map_segment(init_pg_dir, &pgdp, va_offset, _text, _stext, data_prot, + false, root_level); map_segment(init_pg_dir, &pgdp, va_offset, _stext, _etext, prot, !twopass, root_level); map_segment(init_pg_dir, &pgdp, va_offset, __start_rodata, @@ -90,7 +96,7 @@ static void __init map_kernel(u64 kaslr_offset, u64 va_offset, int root_level) true, root_level); dsb(ishst); - idmap_cpu_replace_ttbr1(init_pg_dir); + idmap_cpu_replace_ttbr1((phys_addr_t)init_pg_dir); if (twopass) { if (IS_ENABLED(CONFIG_RELOCATABLE)) @@ -129,10 +135,10 @@ static void __init map_kernel(u64 kaslr_offset, u64 va_offset, int root_level) /* Copy the root page table to its final location */ memcpy((void *)swapper_pg_dir + va_offset, init_pg_dir, PAGE_SIZE); dsb(ishst); - idmap_cpu_replace_ttbr1(swapper_pg_dir); + idmap_cpu_replace_ttbr1((phys_addr_t)swapper_pg_dir); } -static void noinline __section(".idmap.text") set_ttbr0_for_lpa2(u64 ttbr) +static void noinline __section(".idmap.text") set_ttbr0_for_lpa2(phys_addr_t ttbr) { u64 sctlr = read_sysreg(sctlr_el1); u64 tcr = read_sysreg(tcr_el1) | TCR_DS; @@ -172,30 +178,30 @@ static void __init remap_idmap_for_lpa2(void) */ create_init_idmap(init_pg_dir, mask); dsb(ishst); - set_ttbr0_for_lpa2((u64)init_pg_dir); + set_ttbr0_for_lpa2((phys_addr_t)init_pg_dir); /* * Recreate the initial ID map with the same granularity as before. * Don't bother with the FDT, we no longer need it after this. */ memset(init_idmap_pg_dir, 0, - (u64)init_idmap_pg_end - (u64)init_idmap_pg_dir); + (char *)init_idmap_pg_end - (char *)init_idmap_pg_dir); create_init_idmap(init_idmap_pg_dir, mask); dsb(ishst); /* switch back to the updated initial ID map */ - set_ttbr0_for_lpa2((u64)init_idmap_pg_dir); + set_ttbr0_for_lpa2((phys_addr_t)init_idmap_pg_dir); /* wipe the temporary ID map from memory */ - memset(init_pg_dir, 0, (u64)init_pg_end - (u64)init_pg_dir); + memset(init_pg_dir, 0, (char *)init_pg_end - (char *)init_pg_dir); } -static void __init map_fdt(u64 fdt) +static void *__init map_fdt(phys_addr_t fdt) { static u8 ptes[INIT_IDMAP_FDT_SIZE] __initdata __aligned(PAGE_SIZE); - u64 efdt = fdt + MAX_FDT_SIZE; - u64 ptep = (u64)ptes; + phys_addr_t efdt = fdt + MAX_FDT_SIZE; + phys_addr_t ptep = (phys_addr_t)ptes; /* We're idmapped when called */ /* * Map up to MAX_FDT_SIZE bytes, but avoid overlap with @@ -205,6 +211,8 @@ static void __init map_fdt(u64 fdt) fdt, PAGE_KERNEL, IDMAP_ROOT_LEVEL, (pte_t *)init_idmap_pg_dir, false, 0); dsb(ishst); + + return (void *)fdt; } /* @@ -230,7 +238,7 @@ static bool __init ng_mappings_allowed(void) return true; } -asmlinkage void __init early_map_kernel(u64 boot_status, void *fdt) +asmlinkage void __init early_map_kernel(u64 boot_status, phys_addr_t fdt) { static char const chosen_str[] __initconst = "/chosen"; u64 va_base, pa_base = (u64)&_text; @@ -238,15 +246,14 @@ asmlinkage void __init early_map_kernel(u64 boot_status, void *fdt) int root_level = 4 - CONFIG_PGTABLE_LEVELS; int va_bits = VA_BITS; int chosen; - - map_fdt((u64)fdt); + void *fdt_mapped = map_fdt(fdt); /* Clear BSS and the initial page tables */ - memset(__bss_start, 0, (u64)init_pg_end - (u64)__bss_start); + memset(__bss_start, 0, (char *)init_pg_end - (char *)__bss_start); /* Parse the command line for CPU feature overrides */ - chosen = fdt_path_offset(fdt, chosen_str); - init_feature_override(boot_status, fdt, chosen); + chosen = fdt_path_offset(fdt_mapped, chosen_str); + init_feature_override(boot_status, fdt_mapped, chosen); if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && !cpu_has_lva()) { va_bits = VA_BITS_MIN; @@ -266,7 +273,7 @@ asmlinkage void __init early_map_kernel(u64 boot_status, void *fdt) * fill in the high bits from the seed. */ if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) { - u64 kaslr_seed = kaslr_early_init(fdt, chosen); + u64 kaslr_seed = kaslr_early_init(fdt_mapped, chosen); if (kaslr_seed && kaslr_requires_kpti()) arm64_use_ng_mappings = ng_mappings_allowed(); diff --git a/arch/arm64/kernel/pi/map_range.c b/arch/arm64/kernel/pi/map_range.c index 7982788e7b9a..de52cd85c691 100644 --- a/arch/arm64/kernel/pi/map_range.c +++ b/arch/arm64/kernel/pi/map_range.c @@ -26,8 +26,9 @@ * @va_offset: Offset between a physical page and its current mapping * in the VA space */ -void __init map_range(u64 *pte, u64 start, u64 end, u64 pa, pgprot_t prot, - int level, pte_t *tbl, bool may_use_cont, u64 va_offset) +void __init map_range(phys_addr_t *pte, u64 start, u64 end, phys_addr_t pa, + pgprot_t prot, int level, pte_t *tbl, bool may_use_cont, + u64 va_offset) { u64 cmask = (level == 3) ? CONT_PTE_SIZE - 1 : U64_MAX; ptdesc_t protval = pgprot_val(prot) & ~PTE_TYPE_MASK; @@ -87,19 +88,22 @@ void __init map_range(u64 *pte, u64 start, u64 end, u64 pa, pgprot_t prot, } } -asmlinkage u64 __init create_init_idmap(pgd_t *pg_dir, ptdesc_t clrmask) +asmlinkage phys_addr_t __init create_init_idmap(pgd_t *pg_dir, ptdesc_t clrmask) { - u64 ptep = (u64)pg_dir + PAGE_SIZE; + phys_addr_t ptep = (phys_addr_t)pg_dir + PAGE_SIZE; /* MMU is off */ pgprot_t text_prot = PAGE_KERNEL_ROX; pgprot_t data_prot = PAGE_KERNEL; pgprot_val(text_prot) &= ~clrmask; pgprot_val(data_prot) &= ~clrmask; - map_range(&ptep, (u64)_stext, (u64)__initdata_begin, (u64)_stext, - text_prot, IDMAP_ROOT_LEVEL, (pte_t *)pg_dir, false, 0); - map_range(&ptep, (u64)__initdata_begin, (u64)_end, (u64)__initdata_begin, - data_prot, IDMAP_ROOT_LEVEL, (pte_t *)pg_dir, false, 0); + /* MMU is off; pointer casts to phys_addr_t are safe */ + map_range(&ptep, (u64)_stext, (u64)__initdata_begin, + (phys_addr_t)_stext, text_prot, IDMAP_ROOT_LEVEL, + (pte_t *)pg_dir, false, 0); + map_range(&ptep, (u64)__initdata_begin, (u64)_end, + (phys_addr_t)__initdata_begin, data_prot, IDMAP_ROOT_LEVEL, + (pte_t *)pg_dir, false, 0); return ptep; } diff --git a/arch/arm64/kernel/pi/pi.h b/arch/arm64/kernel/pi/pi.h index 46cafee7829f..08ef9f80456b 100644 --- a/arch/arm64/kernel/pi/pi.h +++ b/arch/arm64/kernel/pi/pi.h @@ -29,9 +29,10 @@ u64 kaslr_early_init(void *fdt, int chosen); void relocate_kernel(u64 offset); int scs_patch(const u8 eh_frame[], int size); -void map_range(u64 *pgd, u64 start, u64 end, u64 pa, pgprot_t prot, - int level, pte_t *tbl, bool may_use_cont, u64 va_offset); +void map_range(phys_addr_t *pte, u64 start, u64 end, phys_addr_t pa, + pgprot_t prot, int level, pte_t *tbl, bool may_use_cont, + u64 va_offset); -asmlinkage void early_map_kernel(u64 boot_status, void *fdt); +asmlinkage void early_map_kernel(u64 boot_status, phys_addr_t fdt); -asmlinkage u64 create_init_idmap(pgd_t *pgd, ptdesc_t clrmask); +asmlinkage phys_addr_t create_init_idmap(pgd_t *pgd, ptdesc_t clrmask); diff --git a/arch/arm64/kernel/probes/decode-insn.c b/arch/arm64/kernel/probes/decode-insn.c index 6438bf62e753..4137cc5ef031 100644 --- a/arch/arm64/kernel/probes/decode-insn.c +++ b/arch/arm64/kernel/probes/decode-insn.c @@ -108,9 +108,10 @@ arm_probe_decode_insn(u32 insn, struct arch_probe_insn *api) aarch64_insn_is_bl(insn)) { api->handler = simulate_b_bl; } else if (aarch64_insn_is_br(insn) || - aarch64_insn_is_blr(insn) || - aarch64_insn_is_ret(insn)) { - api->handler = simulate_br_blr_ret; + aarch64_insn_is_blr(insn)) { + api->handler = simulate_br_blr; + } else if (aarch64_insn_is_ret(insn)) { + api->handler = simulate_ret; } else { /* * Instruction cannot be stepped out-of-line and we don't diff --git a/arch/arm64/kernel/probes/simulate-insn.c b/arch/arm64/kernel/probes/simulate-insn.c index 4c6d2d712fbd..89fbeb32107e 100644 --- a/arch/arm64/kernel/probes/simulate-insn.c +++ b/arch/arm64/kernel/probes/simulate-insn.c @@ -13,6 +13,7 @@ #include <asm/traps.h> #include "simulate-insn.h" +#include "asm/gcs.h" #define bbl_displacement(insn) \ sign_extend32(((insn) & 0x3ffffff) << 2, 27) @@ -49,6 +50,21 @@ static inline u32 get_w_reg(struct pt_regs *regs, int reg) return lower_32_bits(pt_regs_read_reg(regs, reg)); } +static inline int update_lr(struct pt_regs *regs, long addr) +{ + int err = 0; + + if (user_mode(regs) && task_gcs_el0_enabled(current)) { + push_user_gcs(addr, &err); + if (err) { + force_sig(SIGSEGV); + return err; + } + } + procedure_link_pointer_set(regs, addr); + return err; +} + static bool __kprobes check_cbz(u32 opcode, struct pt_regs *regs) { int xn = opcode & 0x1f; @@ -107,9 +123,9 @@ simulate_b_bl(u32 opcode, long addr, struct pt_regs *regs) { int disp = bbl_displacement(opcode); - /* Link register is x30 */ if (opcode & (1 << 31)) - set_x_reg(regs, 30, addr + 4); + if (update_lr(regs, addr + 4)) + return; instruction_pointer_set(regs, addr + disp); } @@ -126,16 +142,34 @@ simulate_b_cond(u32 opcode, long addr, struct pt_regs *regs) } void __kprobes -simulate_br_blr_ret(u32 opcode, long addr, struct pt_regs *regs) +simulate_br_blr(u32 opcode, long addr, struct pt_regs *regs) { int xn = (opcode >> 5) & 0x1f; + u64 b_target = get_x_reg(regs, xn); - /* update pc first in case we're doing a "blr lr" */ - instruction_pointer_set(regs, get_x_reg(regs, xn)); - - /* Link register is x30 */ if (((opcode >> 21) & 0x3) == 1) - set_x_reg(regs, 30, addr + 4); + if (update_lr(regs, addr + 4)) + return; + + instruction_pointer_set(regs, b_target); +} + +void __kprobes +simulate_ret(u32 opcode, long addr, struct pt_regs *regs) +{ + u64 ret_addr; + int err = 0; + int xn = (opcode >> 5) & 0x1f; + u64 r_target = get_x_reg(regs, xn); + + if (user_mode(regs) && task_gcs_el0_enabled(current)) { + ret_addr = pop_user_gcs(&err); + if (err || ret_addr != r_target) { + force_sig(SIGSEGV); + return; + } + } + instruction_pointer_set(regs, r_target); } void __kprobes diff --git a/arch/arm64/kernel/probes/simulate-insn.h b/arch/arm64/kernel/probes/simulate-insn.h index efb2803ec943..9e772a292d56 100644 --- a/arch/arm64/kernel/probes/simulate-insn.h +++ b/arch/arm64/kernel/probes/simulate-insn.h @@ -11,7 +11,8 @@ void simulate_adr_adrp(u32 opcode, long addr, struct pt_regs *regs); void simulate_b_bl(u32 opcode, long addr, struct pt_regs *regs); void simulate_b_cond(u32 opcode, long addr, struct pt_regs *regs); -void simulate_br_blr_ret(u32 opcode, long addr, struct pt_regs *regs); +void simulate_br_blr(u32 opcode, long addr, struct pt_regs *regs); +void simulate_ret(u32 opcode, long addr, struct pt_regs *regs); void simulate_cbz_cbnz(u32 opcode, long addr, struct pt_regs *regs); void simulate_tbz_tbnz(u32 opcode, long addr, struct pt_regs *regs); void simulate_ldr_literal(u32 opcode, long addr, struct pt_regs *regs); diff --git a/arch/arm64/kernel/probes/uprobes.c b/arch/arm64/kernel/probes/uprobes.c index 1f91fd2a8187..2799bdb2fb82 100644 --- a/arch/arm64/kernel/probes/uprobes.c +++ b/arch/arm64/kernel/probes/uprobes.c @@ -6,6 +6,7 @@ #include <linux/ptrace.h> #include <linux/uprobes.h> #include <asm/cacheflush.h> +#include <asm/gcs.h> #include "decode-insn.h" @@ -159,11 +160,43 @@ arch_uretprobe_hijack_return_addr(unsigned long trampoline_vaddr, struct pt_regs *regs) { unsigned long orig_ret_vaddr; + unsigned long gcs_ret_vaddr; + int err = 0; + u64 gcspr; orig_ret_vaddr = procedure_link_pointer(regs); + + if (task_gcs_el0_enabled(current)) { + gcspr = read_sysreg_s(SYS_GCSPR_EL0); + gcs_ret_vaddr = get_user_gcs((__force unsigned long __user *)gcspr, &err); + if (err) { + force_sig(SIGSEGV); + goto out; + } + + /* + * If the LR and GCS return addr don't match, then some kind of PAC + * signing or control flow occurred since entering the probed function. + * Likely because the user is attempting to retprobe on an instruction + * that isn't a function boundary or inside a leaf function. Explicitly + * abort this retprobe because it will generate a GCS exception. + */ + if (gcs_ret_vaddr != orig_ret_vaddr) { + orig_ret_vaddr = -1; + goto out; + } + + put_user_gcs(trampoline_vaddr, (__force unsigned long __user *)gcspr, &err); + if (err) { + force_sig(SIGSEGV); + goto out; + } + } + /* Replace the return addr with trampoline addr */ procedure_link_pointer_set(regs, trampoline_vaddr); +out: return orig_ret_vaddr; } diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 96482a1412c6..fba7ca102a8c 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -409,7 +409,7 @@ asmlinkage void ret_from_fork(void) asm("ret_from_fork"); int copy_thread(struct task_struct *p, const struct kernel_clone_args *args) { - unsigned long clone_flags = args->flags; + u64 clone_flags = args->flags; unsigned long stack_start = args->stack; unsigned long tls = args->tls; struct pt_regs *childregs = task_pt_regs(p); diff --git a/arch/arm64/kernel/proton-pack.c b/arch/arm64/kernel/proton-pack.c index edf1783ffc81..f9a32dfde006 100644 --- a/arch/arm64/kernel/proton-pack.c +++ b/arch/arm64/kernel/proton-pack.c @@ -884,6 +884,7 @@ static u8 spectre_bhb_loop_affected(void) static const struct midr_range spectre_bhb_k38_list[] = { MIDR_ALL_VERSIONS(MIDR_CORTEX_A715), MIDR_ALL_VERSIONS(MIDR_CORTEX_A720), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE), {}, }; static const struct midr_range spectre_bhb_k32_list[] = { diff --git a/arch/arm64/kernel/rsi.c b/arch/arm64/kernel/rsi.c index ce4778141ec7..c64a06f58c0b 100644 --- a/arch/arm64/kernel/rsi.c +++ b/arch/arm64/kernel/rsi.c @@ -84,7 +84,25 @@ static void __init arm64_rsi_setup_memory(void) } } -bool __arm64_is_protected_mmio(phys_addr_t base, size_t size) +/* + * Check if a given PA range is Trusted (e.g., Protected memory, a Trusted Device + * mapping, or an MMIO emulated in the Realm world). + * + * We can rely on the RIPAS value of the region to detect if a given region is + * protected. + * + * RIPAS_DEV - A trusted device memory or a trusted emulated MMIO (in the Realm + * world + * RIPAS_RAM - Memory (RAM), protected by the RMM guarantees. (e.g., Firmware + * reserved regions for data sharing). + * + * RIPAS_DESTROYED is a special case of one of the above, where the host did + * something without our permission and as such we can't do anything about it. + * + * The only case where something is emulated by the untrusted hypervisor or is + * backed by shared memory is indicated by RSI_RIPAS_EMPTY. + */ +bool arm64_rsi_is_protected(phys_addr_t base, size_t size) { enum ripas ripas; phys_addr_t end, top; @@ -101,18 +119,18 @@ bool __arm64_is_protected_mmio(phys_addr_t base, size_t size) break; if (WARN_ON(top <= base)) break; - if (ripas != RSI_RIPAS_DEV) + if (ripas == RSI_RIPAS_EMPTY) break; base = top; } return base >= end; } -EXPORT_SYMBOL(__arm64_is_protected_mmio); +EXPORT_SYMBOL(arm64_rsi_is_protected); static int realm_ioremap_hook(phys_addr_t phys, size_t size, pgprot_t *prot) { - if (__arm64_is_protected_mmio(phys, size)) + if (arm64_rsi_is_protected(phys, size)) *prot = pgprot_encrypted(*prot); else *prot = pgprot_decrypted(*prot); diff --git a/arch/arm64/kernel/sdei.c b/arch/arm64/kernel/sdei.c index 6f24a0251e18..95169f7b6531 100644 --- a/arch/arm64/kernel/sdei.c +++ b/arch/arm64/kernel/sdei.c @@ -243,7 +243,7 @@ unsigned long __kprobes do_sdei_event(struct pt_regs *regs, * If we interrupted the kernel with interrupts masked, we always go * back to wherever we came from. */ - if (mode == kernel_mode && !interrupts_enabled(regs)) + if (mode == kernel_mode && regs_irqs_disabled(regs)) return SDEI_EV_HANDLED; /* diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c index 77c7926a4df6..23c05dc7a8f2 100644 --- a/arch/arm64/kernel/setup.c +++ b/arch/arm64/kernel/setup.c @@ -214,7 +214,7 @@ static void __init request_standard_resources(void) unsigned long i = 0; size_t res_size; - kernel_code.start = __pa_symbol(_stext); + kernel_code.start = __pa_symbol(_text); kernel_code.end = __pa_symbol(__init_begin - 1); kernel_data.start = __pa_symbol(_sdata); kernel_data.end = __pa_symbol(_end - 1); @@ -280,7 +280,7 @@ u64 cpu_logical_map(unsigned int cpu) void __init __no_sanitize_address setup_arch(char **cmdline_p) { - setup_initial_init_mm(_stext, _etext, _edata, _end); + setup_initial_init_mm(_text, _etext, _edata, _end); *cmdline_p = boot_command_line; diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c index db3f972f8cd9..1110eeb21f57 100644 --- a/arch/arm64/kernel/signal.c +++ b/arch/arm64/kernel/signal.c @@ -9,6 +9,7 @@ #include <linux/cache.h> #include <linux/compat.h> #include <linux/errno.h> +#include <linux/irq-entry-common.h> #include <linux/kernel.h> #include <linux/signal.h> #include <linux/freezer.h> @@ -1576,7 +1577,7 @@ static void handle_signal(struct ksignal *ksig, struct pt_regs *regs) * the kernel can handle, and then we build all the user-level signal handling * stack-frames in one go after that. */ -void do_signal(struct pt_regs *regs) +void arch_do_signal_or_restart(struct pt_regs *regs) { unsigned long continue_addr = 0, restart_addr = 0; int retval = 0; diff --git a/arch/arm64/kernel/syscall.c b/arch/arm64/kernel/syscall.c index c442fcec6b9e..aba7ca6bca2d 100644 --- a/arch/arm64/kernel/syscall.c +++ b/arch/arm64/kernel/syscall.c @@ -43,7 +43,7 @@ static void invoke_syscall(struct pt_regs *regs, unsigned int scno, add_random_kstack_offset(); - if (scno < sc_nr) { + if (likely(scno < sc_nr)) { syscall_fn_t syscall_fn; syscall_fn = syscall_table[array_index_nospec(scno, sc_nr)]; ret = __invoke_syscall(regs, syscall_fn); diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c index f528b6041f6a..681939ef5d16 100644 --- a/arch/arm64/kernel/traps.c +++ b/arch/arm64/kernel/traps.c @@ -149,19 +149,18 @@ pstate_check_t * const aarch32_opcode_cond_checks[16] = { int show_unhandled_signals = 0; -static void dump_kernel_instr(const char *lvl, struct pt_regs *regs) +void dump_kernel_instr(unsigned long kaddr) { - unsigned long addr = instruction_pointer(regs); char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str; int i; - if (user_mode(regs)) + if (!is_ttbr1_addr(kaddr)) return; for (i = -4; i < 1; i++) { unsigned int val, bad; - bad = aarch64_insn_read(&((u32 *)addr)[i], &val); + bad = aarch64_insn_read(&((u32 *)kaddr)[i], &val); if (!bad) p += sprintf(p, i == 0 ? "(%08x) " : "%08x ", val); @@ -169,7 +168,7 @@ static void dump_kernel_instr(const char *lvl, struct pt_regs *regs) p += sprintf(p, i == 0 ? "(????????) " : "???????? "); } - printk("%sCode: %s\n", lvl, str); + printk(KERN_EMERG "Code: %s\n", str); } #define S_SMP " SMP" @@ -178,6 +177,7 @@ static int __die(const char *str, long err, struct pt_regs *regs) { static int die_counter; int ret; + unsigned long addr = instruction_pointer(regs); pr_emerg("Internal error: %s: %016lx [#%d] " S_SMP "\n", str, err, ++die_counter); @@ -190,7 +190,10 @@ static int __die(const char *str, long err, struct pt_regs *regs) print_modules(); show_regs(regs); - dump_kernel_instr(KERN_EMERG, regs); + if (user_mode(regs)) + return ret; + + dump_kernel_instr(addr); return ret; } @@ -1015,7 +1018,7 @@ int bug_brk_handler(struct pt_regs *regs, unsigned long esr) return DBG_HOOK_HANDLED; } -#ifdef CONFIG_CFI_CLANG +#ifdef CONFIG_CFI int cfi_brk_handler(struct pt_regs *regs, unsigned long esr) { unsigned long target; @@ -1039,7 +1042,7 @@ int cfi_brk_handler(struct pt_regs *regs, unsigned long esr) arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); return DBG_HOOK_HANDLED; } -#endif /* CONFIG_CFI_CLANG */ +#endif /* CONFIG_CFI */ int reserved_fault_brk_handler(struct pt_regs *regs, unsigned long esr) { diff --git a/arch/arm64/kernel/vdso32/Makefile b/arch/arm64/kernel/vdso32/Makefile index f2dfdc7dc818..ffa3536581f6 100644 --- a/arch/arm64/kernel/vdso32/Makefile +++ b/arch/arm64/kernel/vdso32/Makefile @@ -21,8 +21,6 @@ endif cc32-option = $(call try-run,\ $(CC_COMPAT) $(1) -c -x c /dev/null -o "$$TMP",$(1),$(2)) -cc32-disable-warning = $(call try-run,\ - $(CC_COMPAT) -W$(strip $(1)) -c -x c /dev/null -o "$$TMP",-Wno-$(strip $(1))) # We cannot use the global flags to compile the vDSO files, the main reason # being that the 32-bit compiler may be older than the main (64-bit) compiler @@ -59,10 +57,10 @@ VDSO_CAFLAGS += -DDISABLE_BRANCH_PROFILING VDSO_CAFLAGS += -march=armv8-a VDSO_CFLAGS := $(VDSO_CAFLAGS) -VDSO_CFLAGS += -DENABLE_COMPAT_VDSO=1 # KBUILD_CFLAGS from top-level Makefile VDSO_CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \ -fno-strict-aliasing -fno-common \ + $(filter -Werror,$(KBUILD_CPPFLAGS)) \ -Werror-implicit-function-declaration \ -Wno-format-security \ -std=gnu11 @@ -74,16 +72,6 @@ VDSO_CFLAGS += $(call cc32-option,-Werror=strict-prototypes) VDSO_CFLAGS += -Werror=date-time VDSO_CFLAGS += $(call cc32-option,-Werror=incompatible-pointer-types) -# The 32-bit compiler does not provide 128-bit integers, which are used in -# some headers that are indirectly included from the vDSO code. -# This hack makes the compiler happy and should trigger a warning/error if -# variables of such type are referenced. -VDSO_CFLAGS += -D__uint128_t='void*' -# Silence some warnings coming from headers that operate on long's -# (on GCC 4.8 or older, there is unfortunately no way to silence this warning) -VDSO_CFLAGS += $(call cc32-disable-warning,shift-count-overflow) -VDSO_CFLAGS += -Wno-int-to-pointer-cast - # Compile as THUMB2 or ARM. Unwinding via frame-pointers in THUMB2 is # unreliable. ifeq ($(CONFIG_THUMB2_COMPAT_VDSO), y) diff --git a/arch/arm64/kvm/Kconfig b/arch/arm64/kvm/Kconfig index 713248f240e0..bff62e75d681 100644 --- a/arch/arm64/kvm/Kconfig +++ b/arch/arm64/kvm/Kconfig @@ -37,6 +37,7 @@ menuconfig KVM select HAVE_KVM_VCPU_RUN_PID_CHANGE select SCHED_INFO select GUEST_PERF_EVENTS if PERF_EVENTS + select KVM_GUEST_MEMFD help Support hosting virtualized guest machines. diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 5bf101c869c9..fa79744290f3 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -170,10 +170,6 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) if (ret) return ret; - ret = pkvm_init_host_vm(kvm); - if (ret) - goto err_unshare_kvm; - if (!zalloc_cpumask_var(&kvm->arch.supported_cpus, GFP_KERNEL_ACCOUNT)) { ret = -ENOMEM; goto err_unshare_kvm; @@ -184,6 +180,16 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) if (ret) goto err_free_cpumask; + if (is_protected_kvm_enabled()) { + /* + * If any failures occur after this is successful, make sure to + * call __pkvm_unreserve_vm to unreserve the VM in hyp. + */ + ret = pkvm_init_host_vm(kvm); + if (ret) + goto err_free_cpumask; + } + kvm_vgic_early_init(kvm); kvm_timer_init_vm(kvm); @@ -2113,8 +2119,10 @@ static void cpu_hyp_init_features(void) { cpu_set_hyp_vector(); - if (is_kernel_in_hyp_mode()) + if (is_kernel_in_hyp_mode()) { kvm_timer_init_vhe(); + kvm_debug_init_vhe(); + } if (vgic_present) kvm_vgic_init_cpu_hardware(); @@ -2315,8 +2323,9 @@ static int __init init_subsystems(void) } if (kvm_mode == KVM_MODE_NV && - !(vgic_present && kvm_vgic_global_state.type == VGIC_V3)) { - kvm_err("NV support requires GICv3, giving up\n"); + !(vgic_present && (kvm_vgic_global_state.type == VGIC_V3 || + kvm_vgic_global_state.has_gcie_v3_compat))) { + kvm_err("NV support requires GICv3 or GICv5 with legacy support, giving up\n"); err = -EINVAL; goto out; } diff --git a/arch/arm64/kvm/at.c b/arch/arm64/kvm/at.c index d71ca4ddc9d1..20bb9af125b1 100644 --- a/arch/arm64/kvm/at.c +++ b/arch/arm64/kvm/at.c @@ -28,9 +28,57 @@ static int get_ia_size(struct s1_walk_info *wi) /* Return true if the IPA is out of the OA range */ static bool check_output_size(u64 ipa, struct s1_walk_info *wi) { + if (wi->pa52bit) + return wi->max_oa_bits < 52 && (ipa & GENMASK_ULL(51, wi->max_oa_bits)); return wi->max_oa_bits < 48 && (ipa & GENMASK_ULL(47, wi->max_oa_bits)); } +static bool has_52bit_pa(struct kvm_vcpu *vcpu, struct s1_walk_info *wi, u64 tcr) +{ + switch (BIT(wi->pgshift)) { + case SZ_64K: + default: /* IMPDEF: treat any other value as 64k */ + if (!kvm_has_feat_enum(vcpu->kvm, ID_AA64MMFR0_EL1, PARANGE, 52)) + return false; + return ((wi->regime == TR_EL2 ? + FIELD_GET(TCR_EL2_PS_MASK, tcr) : + FIELD_GET(TCR_IPS_MASK, tcr)) == 0b0110); + case SZ_16K: + if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR0_EL1, TGRAN16, 52_BIT)) + return false; + break; + case SZ_4K: + if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR0_EL1, TGRAN4, 52_BIT)) + return false; + break; + } + + return (tcr & (wi->regime == TR_EL2 ? TCR_EL2_DS : TCR_DS)); +} + +static u64 desc_to_oa(struct s1_walk_info *wi, u64 desc) +{ + u64 addr; + + if (!wi->pa52bit) + return desc & GENMASK_ULL(47, wi->pgshift); + + switch (BIT(wi->pgshift)) { + case SZ_4K: + case SZ_16K: + addr = desc & GENMASK_ULL(49, wi->pgshift); + addr |= FIELD_GET(KVM_PTE_ADDR_51_50_LPA2, desc) << 50; + break; + case SZ_64K: + default: /* IMPDEF: treat any other value as 64k */ + addr = desc & GENMASK_ULL(47, wi->pgshift); + addr |= FIELD_GET(KVM_PTE_ADDR_51_48, desc) << 48; + break; + } + + return addr; +} + /* Return the translation regime that applies to an AT instruction */ static enum trans_regime compute_translation_regime(struct kvm_vcpu *vcpu, u32 op) { @@ -50,21 +98,26 @@ static enum trans_regime compute_translation_regime(struct kvm_vcpu *vcpu, u32 o } } +static u64 effective_tcr2(struct kvm_vcpu *vcpu, enum trans_regime regime) +{ + if (regime == TR_EL10) { + if (vcpu_has_nv(vcpu) && + !(__vcpu_sys_reg(vcpu, HCRX_EL2) & HCRX_EL2_TCR2En)) + return 0; + + return vcpu_read_sys_reg(vcpu, TCR2_EL1); + } + + return vcpu_read_sys_reg(vcpu, TCR2_EL2); +} + static bool s1pie_enabled(struct kvm_vcpu *vcpu, enum trans_regime regime) { if (!kvm_has_s1pie(vcpu->kvm)) return false; - switch (regime) { - case TR_EL2: - case TR_EL20: - return vcpu_read_sys_reg(vcpu, TCR2_EL2) & TCR2_EL2_PIE; - case TR_EL10: - return (__vcpu_sys_reg(vcpu, HCRX_EL2) & HCRX_EL2_TCR2En) && - (__vcpu_sys_reg(vcpu, TCR2_EL1) & TCR2_EL1_PIE); - default: - BUG(); - } + /* Abuse TCR2_EL1_PIE and use it for EL2 as well */ + return effective_tcr2(vcpu, regime) & TCR2_EL1_PIE; } static void compute_s1poe(struct kvm_vcpu *vcpu, struct s1_walk_info *wi) @@ -76,23 +129,11 @@ static void compute_s1poe(struct kvm_vcpu *vcpu, struct s1_walk_info *wi) return; } - switch (wi->regime) { - case TR_EL2: - case TR_EL20: - val = vcpu_read_sys_reg(vcpu, TCR2_EL2); - wi->poe = val & TCR2_EL2_POE; - wi->e0poe = (wi->regime == TR_EL20) && (val & TCR2_EL2_E0POE); - break; - case TR_EL10: - if (__vcpu_sys_reg(vcpu, HCRX_EL2) & HCRX_EL2_TCR2En) { - wi->poe = wi->e0poe = false; - return; - } + val = effective_tcr2(vcpu, wi->regime); - val = __vcpu_sys_reg(vcpu, TCR2_EL1); - wi->poe = val & TCR2_EL1_POE; - wi->e0poe = val & TCR2_EL1_E0POE; - } + /* Abuse TCR2_EL1_* for EL2 */ + wi->poe = val & TCR2_EL1_POE; + wi->e0poe = (wi->regime != TR_EL2) && (val & TCR2_EL1_E0POE); } static int setup_s1_walk(struct kvm_vcpu *vcpu, struct s1_walk_info *wi, @@ -102,14 +143,16 @@ static int setup_s1_walk(struct kvm_vcpu *vcpu, struct s1_walk_info *wi, unsigned int stride, x; bool va55, tbi, lva; - hcr = __vcpu_sys_reg(vcpu, HCR_EL2); - va55 = va & BIT(55); - if (wi->regime == TR_EL2 && va55) - goto addrsz; - - wi->s2 = wi->regime == TR_EL10 && (hcr & (HCR_VM | HCR_DC)); + if (vcpu_has_nv(vcpu)) { + hcr = __vcpu_sys_reg(vcpu, HCR_EL2); + wi->s2 = wi->regime == TR_EL10 && (hcr & (HCR_VM | HCR_DC)); + } else { + WARN_ON_ONCE(wi->regime != TR_EL10); + wi->s2 = false; + hcr = 0; + } switch (wi->regime) { case TR_EL10: @@ -131,6 +174,46 @@ static int setup_s1_walk(struct kvm_vcpu *vcpu, struct s1_walk_info *wi, BUG(); } + /* Someone was silly enough to encode TG0/TG1 differently */ + if (va55 && wi->regime != TR_EL2) { + wi->txsz = FIELD_GET(TCR_T1SZ_MASK, tcr); + tg = FIELD_GET(TCR_TG1_MASK, tcr); + + switch (tg << TCR_TG1_SHIFT) { + case TCR_TG1_4K: + wi->pgshift = 12; break; + case TCR_TG1_16K: + wi->pgshift = 14; break; + case TCR_TG1_64K: + default: /* IMPDEF: treat any other value as 64k */ + wi->pgshift = 16; break; + } + } else { + wi->txsz = FIELD_GET(TCR_T0SZ_MASK, tcr); + tg = FIELD_GET(TCR_TG0_MASK, tcr); + + switch (tg << TCR_TG0_SHIFT) { + case TCR_TG0_4K: + wi->pgshift = 12; break; + case TCR_TG0_16K: + wi->pgshift = 14; break; + case TCR_TG0_64K: + default: /* IMPDEF: treat any other value as 64k */ + wi->pgshift = 16; break; + } + } + + wi->pa52bit = has_52bit_pa(vcpu, wi, tcr); + + ia_bits = get_ia_size(wi); + + /* AArch64.S1StartLevel() */ + stride = wi->pgshift - 3; + wi->sl = 3 - (((ia_bits - 1) - wi->pgshift) / stride); + + if (wi->regime == TR_EL2 && va55) + goto addrsz; + tbi = (wi->regime == TR_EL2 ? FIELD_GET(TCR_EL2_TBI, tcr) : (va55 ? @@ -140,6 +223,12 @@ static int setup_s1_walk(struct kvm_vcpu *vcpu, struct s1_walk_info *wi, if (!tbi && (u64)sign_extend64(va, 55) != va) goto addrsz; + wi->sh = (wi->regime == TR_EL2 ? + FIELD_GET(TCR_EL2_SH0_MASK, tcr) : + (va55 ? + FIELD_GET(TCR_SH1_MASK, tcr) : + FIELD_GET(TCR_SH0_MASK, tcr))); + va = (u64)sign_extend64(va, 55); /* Let's put the MMU disabled case aside immediately */ @@ -194,53 +283,20 @@ static int setup_s1_walk(struct kvm_vcpu *vcpu, struct s1_walk_info *wi, /* R_BVXDG */ wi->hpd |= (wi->poe || wi->e0poe); - /* Someone was silly enough to encode TG0/TG1 differently */ - if (va55) { - wi->txsz = FIELD_GET(TCR_T1SZ_MASK, tcr); - tg = FIELD_GET(TCR_TG1_MASK, tcr); - - switch (tg << TCR_TG1_SHIFT) { - case TCR_TG1_4K: - wi->pgshift = 12; break; - case TCR_TG1_16K: - wi->pgshift = 14; break; - case TCR_TG1_64K: - default: /* IMPDEF: treat any other value as 64k */ - wi->pgshift = 16; break; - } - } else { - wi->txsz = FIELD_GET(TCR_T0SZ_MASK, tcr); - tg = FIELD_GET(TCR_TG0_MASK, tcr); - - switch (tg << TCR_TG0_SHIFT) { - case TCR_TG0_4K: - wi->pgshift = 12; break; - case TCR_TG0_16K: - wi->pgshift = 14; break; - case TCR_TG0_64K: - default: /* IMPDEF: treat any other value as 64k */ - wi->pgshift = 16; break; - } - } - /* R_PLCGL, R_YXNYW */ if (!kvm_has_feat_enum(vcpu->kvm, ID_AA64MMFR2_EL1, ST, 48_47)) { if (wi->txsz > 39) - goto transfault_l0; + goto transfault; } else { if (wi->txsz > 48 || (BIT(wi->pgshift) == SZ_64K && wi->txsz > 47)) - goto transfault_l0; + goto transfault; } /* R_GTJBY, R_SXWGM */ switch (BIT(wi->pgshift)) { case SZ_4K: - lva = kvm_has_feat(vcpu->kvm, ID_AA64MMFR0_EL1, TGRAN4, 52_BIT); - lva &= tcr & (wi->regime == TR_EL2 ? TCR_EL2_DS : TCR_DS); - break; case SZ_16K: - lva = kvm_has_feat(vcpu->kvm, ID_AA64MMFR0_EL1, TGRAN16, 52_BIT); - lva &= tcr & (wi->regime == TR_EL2 ? TCR_EL2_DS : TCR_DS); + lva = wi->pa52bit; break; case SZ_64K: lva = kvm_has_feat(vcpu->kvm, ID_AA64MMFR2_EL1, VARange, 52); @@ -248,38 +304,42 @@ static int setup_s1_walk(struct kvm_vcpu *vcpu, struct s1_walk_info *wi, } if ((lva && wi->txsz < 12) || (!lva && wi->txsz < 16)) - goto transfault_l0; - - ia_bits = get_ia_size(wi); + goto transfault; /* R_YYVYV, I_THCZK */ if ((!va55 && va > GENMASK(ia_bits - 1, 0)) || (va55 && va < GENMASK(63, ia_bits))) - goto transfault_l0; + goto transfault; /* I_ZFSYQ */ if (wi->regime != TR_EL2 && (tcr & (va55 ? TCR_EPD1_MASK : TCR_EPD0_MASK))) - goto transfault_l0; + goto transfault; /* R_BNDVG and following statements */ if (kvm_has_feat(vcpu->kvm, ID_AA64MMFR2_EL1, E0PD, IMP) && wi->as_el0 && (tcr & (va55 ? TCR_E0PD1 : TCR_E0PD0))) - goto transfault_l0; - - /* AArch64.S1StartLevel() */ - stride = wi->pgshift - 3; - wi->sl = 3 - (((ia_bits - 1) - wi->pgshift) / stride); + goto transfault; ps = (wi->regime == TR_EL2 ? FIELD_GET(TCR_EL2_PS_MASK, tcr) : FIELD_GET(TCR_IPS_MASK, tcr)); - wi->max_oa_bits = min(get_kvm_ipa_limit(), ps_to_output_size(ps)); + wi->max_oa_bits = min(get_kvm_ipa_limit(), ps_to_output_size(ps, wi->pa52bit)); /* Compute minimal alignment */ x = 3 + ia_bits - ((3 - wi->sl) * stride + wi->pgshift); wi->baddr = ttbr & TTBRx_EL1_BADDR; + if (wi->pa52bit) { + /* + * Force the alignment on 64 bytes for top-level tables + * smaller than 8 entries, since TTBR.BADDR[5:2] are used to + * store bits [51:48] of the first level of lookup. + */ + x = max(x, 6); + + wi->baddr |= FIELD_GET(GENMASK_ULL(5, 2), ttbr) << 48; + } /* R_VPBBF */ if (check_output_size(wi->baddr, wi)) @@ -289,12 +349,17 @@ static int setup_s1_walk(struct kvm_vcpu *vcpu, struct s1_walk_info *wi, return 0; -addrsz: /* Address Size Fault level 0 */ +addrsz: + /* + * Address Size Fault level 0 to indicate it comes from TTBR. + * yes, this is an oddity. + */ fail_s1_walk(wr, ESR_ELx_FSC_ADDRSZ_L(0), false); return -EFAULT; -transfault_l0: /* Translation Fault level 0 */ - fail_s1_walk(wr, ESR_ELx_FSC_FAULT_L(0), false); +transfault: + /* Translation Fault on start level */ + fail_s1_walk(wr, ESR_ELx_FSC_FAULT_L(wi->sl), false); return -EFAULT; } @@ -339,6 +404,17 @@ static int walk_s1(struct kvm_vcpu *vcpu, struct s1_walk_info *wi, ipa = kvm_s2_trans_output(&s2_trans); } + if (wi->filter) { + ret = wi->filter->fn(&(struct s1_walk_context) + { + .wi = wi, + .table_ipa = baddr, + .level = level, + }, wi->filter->priv); + if (ret) + return ret; + } + ret = kvm_read_guest(vcpu->kvm, ipa, &desc, sizeof(desc)); if (ret) { fail_s1_walk(wr, ESR_ELx_FSC_SEA_TTW(level), false); @@ -369,7 +445,7 @@ static int walk_s1(struct kvm_vcpu *vcpu, struct s1_walk_info *wi, wr->PXNTable |= FIELD_GET(PMD_TABLE_PXN, desc); } - baddr = desc & GENMASK_ULL(47, wi->pgshift); + baddr = desc_to_oa(wi, desc); /* Check for out-of-range OA */ if (check_output_size(baddr, wi)) @@ -386,11 +462,11 @@ static int walk_s1(struct kvm_vcpu *vcpu, struct s1_walk_info *wi, switch (BIT(wi->pgshift)) { case SZ_4K: - valid_block = level == 1 || level == 2; + valid_block = level == 1 || level == 2 || (wi->pa52bit && level == 0); break; case SZ_16K: case SZ_64K: - valid_block = level == 2; + valid_block = level == 2 || (wi->pa52bit && level == 1); break; } @@ -398,7 +474,8 @@ static int walk_s1(struct kvm_vcpu *vcpu, struct s1_walk_info *wi, goto transfault; } - if (check_output_size(desc & GENMASK(47, va_bottom), wi)) + baddr = desc_to_oa(wi, desc); + if (check_output_size(baddr & GENMASK(52, va_bottom), wi)) goto addrsz; if (!(desc & PTE_AF)) { @@ -411,7 +488,7 @@ static int walk_s1(struct kvm_vcpu *vcpu, struct s1_walk_info *wi, wr->failed = false; wr->level = level; wr->desc = desc; - wr->pa = desc & GENMASK(47, va_bottom); + wr->pa = baddr & GENMASK(52, va_bottom); wr->pa |= va & GENMASK_ULL(va_bottom - 1, 0); wr->nG = (wi->regime != TR_EL2) && (desc & PTE_NG); @@ -640,21 +717,36 @@ static u8 combine_s1_s2_attr(u8 s1, u8 s2) #define ATTR_OSH 0b10 #define ATTR_ISH 0b11 -static u8 compute_sh(u8 attr, u64 desc) +static u8 compute_final_sh(u8 attr, u8 sh) { - u8 sh; - /* Any form of device, as well as NC has SH[1:0]=0b10 */ if (MEMATTR_IS_DEVICE(attr) || attr == MEMATTR(NC, NC)) return ATTR_OSH; - sh = FIELD_GET(PTE_SHARED, desc); if (sh == ATTR_RSV) /* Reserved, mapped to NSH */ sh = ATTR_NSH; return sh; } +static u8 compute_s1_sh(struct s1_walk_info *wi, struct s1_walk_result *wr, + u8 attr) +{ + u8 sh; + + /* + * non-52bit and LPA have their basic shareability described in the + * descriptor. LPA2 gets it from the corresponding field in TCR, + * conveniently recorded in the walk info. + */ + if (!wi->pa52bit || BIT(wi->pgshift) == SZ_64K) + sh = FIELD_GET(KVM_PTE_LEAF_ATTR_LO_S1_SH, wr->desc); + else + sh = wi->sh; + + return compute_final_sh(attr, sh); +} + static u8 combine_sh(u8 s1_sh, u8 s2_sh) { if (s1_sh == ATTR_OSH || s2_sh == ATTR_OSH) @@ -668,7 +760,7 @@ static u8 combine_sh(u8 s1_sh, u8 s2_sh) static u64 compute_par_s12(struct kvm_vcpu *vcpu, u64 s1_par, struct kvm_s2_trans *tr) { - u8 s1_parattr, s2_memattr, final_attr; + u8 s1_parattr, s2_memattr, final_attr, s2_sh; u64 par; /* If S2 has failed to translate, report the damage */ @@ -741,17 +833,19 @@ static u64 compute_par_s12(struct kvm_vcpu *vcpu, u64 s1_par, !MEMATTR_IS_DEVICE(final_attr)) final_attr = MEMATTR(NC, NC); + s2_sh = FIELD_GET(KVM_PTE_LEAF_ATTR_LO_S2_SH, tr->desc); + par = FIELD_PREP(SYS_PAR_EL1_ATTR, final_attr); par |= tr->output & GENMASK(47, 12); par |= FIELD_PREP(SYS_PAR_EL1_SH, combine_sh(FIELD_GET(SYS_PAR_EL1_SH, s1_par), - compute_sh(final_attr, tr->desc))); + compute_final_sh(final_attr, s2_sh))); return par; } -static u64 compute_par_s1(struct kvm_vcpu *vcpu, struct s1_walk_result *wr, - enum trans_regime regime) +static u64 compute_par_s1(struct kvm_vcpu *vcpu, struct s1_walk_info *wi, + struct s1_walk_result *wr) { u64 par; @@ -764,9 +858,9 @@ static u64 compute_par_s1(struct kvm_vcpu *vcpu, struct s1_walk_result *wr, } else if (wr->level == S1_MMU_DISABLED) { /* MMU off or HCR_EL2.DC == 1 */ par = SYS_PAR_EL1_NSE; - par |= wr->pa & GENMASK_ULL(47, 12); + par |= wr->pa & SYS_PAR_EL1_PA; - if (regime == TR_EL10 && + if (wi->regime == TR_EL10 && vcpu_has_nv(vcpu) && (__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_DC)) { par |= FIELD_PREP(SYS_PAR_EL1_ATTR, MEMATTR(WbRaWa, WbRaWa)); @@ -781,14 +875,14 @@ static u64 compute_par_s1(struct kvm_vcpu *vcpu, struct s1_walk_result *wr, par = SYS_PAR_EL1_NSE; - mair = (regime == TR_EL10 ? + mair = (wi->regime == TR_EL10 ? vcpu_read_sys_reg(vcpu, MAIR_EL1) : vcpu_read_sys_reg(vcpu, MAIR_EL2)); mair >>= FIELD_GET(PTE_ATTRINDX_MASK, wr->desc) * 8; mair &= 0xff; - sctlr = (regime == TR_EL10 ? + sctlr = (wi->regime == TR_EL10 ? vcpu_read_sys_reg(vcpu, SCTLR_EL1) : vcpu_read_sys_reg(vcpu, SCTLR_EL2)); @@ -797,9 +891,9 @@ static u64 compute_par_s1(struct kvm_vcpu *vcpu, struct s1_walk_result *wr, mair = MEMATTR(NC, NC); par |= FIELD_PREP(SYS_PAR_EL1_ATTR, mair); - par |= wr->pa & GENMASK_ULL(47, 12); + par |= wr->pa & SYS_PAR_EL1_PA; - sh = compute_sh(mair, wr->desc); + sh = compute_s1_sh(wi, wr, mair); par |= FIELD_PREP(SYS_PAR_EL1_SH, sh); } @@ -873,7 +967,7 @@ static void compute_s1_direct_permissions(struct kvm_vcpu *vcpu, wxn = (vcpu_read_sys_reg(vcpu, SCTLR_EL2) & SCTLR_ELx_WXN); break; case TR_EL10: - wxn = (__vcpu_sys_reg(vcpu, SCTLR_EL1) & SCTLR_ELx_WXN); + wxn = (vcpu_read_sys_reg(vcpu, SCTLR_EL1) & SCTLR_ELx_WXN); break; } @@ -1186,7 +1280,7 @@ static u64 handle_at_slow(struct kvm_vcpu *vcpu, u32 op, u64 vaddr) fail_s1_walk(&wr, ESR_ELx_FSC_PERM_L(wr.level), false); compute_par: - return compute_par_s1(vcpu, &wr, wi.regime); + return compute_par_s1(vcpu, &wi, &wr); } /* @@ -1202,7 +1296,7 @@ static u64 __kvm_at_s1e01_fast(struct kvm_vcpu *vcpu, u32 op, u64 vaddr) { struct mmu_config config; struct kvm_s2_mmu *mmu; - bool fail; + bool fail, mmu_cs; u64 par; par = SYS_PAR_EL1_F; @@ -1218,8 +1312,13 @@ static u64 __kvm_at_s1e01_fast(struct kvm_vcpu *vcpu, u32 op, u64 vaddr) * If HCR_EL2.{E2H,TGE} == {1,1}, the MMU context is already * the right one (as we trapped from vEL2). If not, save the * full MMU context. + * + * We are also guaranteed to be in the correct context if + * we're not in a nested VM. */ - if (vcpu_el2_e2h_is_set(vcpu) && vcpu_el2_tge_is_set(vcpu)) + mmu_cs = (vcpu_has_nv(vcpu) && + !(vcpu_el2_e2h_is_set(vcpu) && vcpu_el2_tge_is_set(vcpu))); + if (!mmu_cs) goto skip_mmu_switch; /* @@ -1287,7 +1386,7 @@ skip_mmu_switch: write_sysreg_hcr(HCR_HOST_VHE_FLAGS); - if (!(vcpu_el2_e2h_is_set(vcpu) && vcpu_el2_tge_is_set(vcpu))) + if (mmu_cs) __mmu_config_restore(&config); return par; @@ -1470,3 +1569,68 @@ int __kvm_translate_va(struct kvm_vcpu *vcpu, struct s1_walk_info *wi, return 0; } + +struct desc_match { + u64 ipa; + int level; +}; + +static int match_s1_desc(struct s1_walk_context *ctxt, void *priv) +{ + struct desc_match *dm = priv; + u64 ipa = dm->ipa; + + /* Use S1 granule alignment */ + ipa &= GENMASK(51, ctxt->wi->pgshift); + + /* Not the IPA we're looking for? Continue. */ + if (ipa != ctxt->table_ipa) + return 0; + + /* Note the level and interrupt the walk */ + dm->level = ctxt->level; + return -EINTR; +} + +int __kvm_find_s1_desc_level(struct kvm_vcpu *vcpu, u64 va, u64 ipa, int *level) +{ + struct desc_match dm = { + .ipa = ipa, + }; + struct s1_walk_info wi = { + .filter = &(struct s1_walk_filter){ + .fn = match_s1_desc, + .priv = &dm, + }, + .regime = TR_EL10, + .as_el0 = false, + .pan = false, + }; + struct s1_walk_result wr = {}; + int ret; + + ret = setup_s1_walk(vcpu, &wi, &wr, va); + if (ret) + return ret; + + /* We really expect the S1 MMU to be on here... */ + if (WARN_ON_ONCE(wr.level == S1_MMU_DISABLED)) { + *level = 0; + return 0; + } + + /* Walk the guest's PT, looking for a match along the way */ + ret = walk_s1(vcpu, &wi, &wr, va); + switch (ret) { + case -EINTR: + /* We interrupted the walk on a match, return the level */ + *level = dm.level; + return 0; + case 0: + /* The walk completed, we failed to find the entry */ + return -ENOENT; + default: + /* Any other error... */ + return ret; + } +} diff --git a/arch/arm64/kvm/config.c b/arch/arm64/kvm/config.c index da66c4a14775..fbd8944a3dea 100644 --- a/arch/arm64/kvm/config.c +++ b/arch/arm64/kvm/config.c @@ -7,12 +7,22 @@ #include <linux/kvm_host.h> #include <asm/sysreg.h> +/* + * Describes the dependencies between a set of bits (or the negation + * of a set of RES0 bits) and a feature. The flags indicate how the + * data is interpreted. + */ struct reg_bits_to_feat_map { - u64 bits; + union { + u64 bits; + u64 *res0p; + }; #define NEVER_FGU BIT(0) /* Can trap, but never UNDEF */ #define CALL_FUNC BIT(1) /* Needs to evaluate tons of crap */ #define FIXED_VALUE BIT(2) /* RAZ/WI or RAO/WI in KVM */ +#define RES0_POINTER BIT(3) /* Pointer to RES0 value instead of bits */ + unsigned long flags; union { @@ -28,9 +38,27 @@ struct reg_bits_to_feat_map { }; }; -#define __NEEDS_FEAT_3(m, f, id, fld, lim) \ +/* + * Describes the dependencies for a given register: + * + * @feat_map describes the dependency for the whole register. If the + * features the register depends on are not present, the whole + * register is effectively RES0. + * + * @bit_feat_map describes the dependencies for a set of bits in that + * register. If the features these bits depend on are not present, the + * bits are effectively RES0. + */ +struct reg_feat_map_desc { + const char *name; + const struct reg_bits_to_feat_map feat_map; + const struct reg_bits_to_feat_map *bit_feat_map; + const unsigned int bit_feat_map_sz; +}; + +#define __NEEDS_FEAT_3(m, f, w, id, fld, lim) \ { \ - .bits = (m), \ + .w = (m), \ .flags = (f), \ .regidx = IDREG_IDX(SYS_ ## id), \ .shift = id ##_## fld ## _SHIFT, \ @@ -39,28 +67,63 @@ struct reg_bits_to_feat_map { .lo_lim = id ##_## fld ##_## lim \ } -#define __NEEDS_FEAT_2(m, f, fun, dummy) \ +#define __NEEDS_FEAT_2(m, f, w, fun, dummy) \ { \ - .bits = (m), \ + .w = (m), \ .flags = (f) | CALL_FUNC, \ .fval = (fun), \ } -#define __NEEDS_FEAT_1(m, f, fun) \ +#define __NEEDS_FEAT_1(m, f, w, fun) \ { \ - .bits = (m), \ + .w = (m), \ .flags = (f) | CALL_FUNC, \ .match = (fun), \ } +#define __NEEDS_FEAT_FLAG(m, f, w, ...) \ + CONCATENATE(__NEEDS_FEAT_, COUNT_ARGS(__VA_ARGS__))(m, f, w, __VA_ARGS__) + #define NEEDS_FEAT_FLAG(m, f, ...) \ - CONCATENATE(__NEEDS_FEAT_, COUNT_ARGS(__VA_ARGS__))(m, f, __VA_ARGS__) + __NEEDS_FEAT_FLAG(m, f, bits, __VA_ARGS__) #define NEEDS_FEAT_FIXED(m, ...) \ - NEEDS_FEAT_FLAG(m, FIXED_VALUE, __VA_ARGS__, 0) + __NEEDS_FEAT_FLAG(m, FIXED_VALUE, bits, __VA_ARGS__, 0) +#define NEEDS_FEAT_RES0(p, ...) \ + __NEEDS_FEAT_FLAG(p, RES0_POINTER, res0p, __VA_ARGS__) + +/* + * Declare the dependency between a set of bits and a set of features, + * generating a struct reg_bit_to_feat_map. + */ #define NEEDS_FEAT(m, ...) NEEDS_FEAT_FLAG(m, 0, __VA_ARGS__) +/* + * Declare the dependency between a non-FGT register, a set of + * feature, and the set of individual bits it contains. This generates + * a struct reg_feat_map_desc. + */ +#define DECLARE_FEAT_MAP(n, r, m, f) \ + struct reg_feat_map_desc n = { \ + .name = #r, \ + .feat_map = NEEDS_FEAT(~r##_RES0, f), \ + .bit_feat_map = m, \ + .bit_feat_map_sz = ARRAY_SIZE(m), \ + } + +/* + * Specialised version of the above for FGT registers that have their + * RES0 masks described as struct fgt_masks. + */ +#define DECLARE_FEAT_MAP_FGT(n, msk, m, f) \ + struct reg_feat_map_desc n = { \ + .name = #msk, \ + .feat_map = NEEDS_FEAT_RES0(&msk.res0, f),\ + .bit_feat_map = m, \ + .bit_feat_map_sz = ARRAY_SIZE(m), \ + } + #define FEAT_SPE ID_AA64DFR0_EL1, PMSVer, IMP #define FEAT_SPE_FnE ID_AA64DFR0_EL1, PMSVer, V1P2 #define FEAT_BRBE ID_AA64DFR0_EL1, BRBE, IMP @@ -73,6 +136,7 @@ struct reg_bits_to_feat_map { #define FEAT_AA32EL0 ID_AA64PFR0_EL1, EL0, AARCH32 #define FEAT_AA32EL1 ID_AA64PFR0_EL1, EL1, AARCH32 #define FEAT_AA64EL1 ID_AA64PFR0_EL1, EL1, IMP +#define FEAT_AA64EL2 ID_AA64PFR0_EL1, EL2, IMP #define FEAT_AA64EL3 ID_AA64PFR0_EL1, EL3, IMP #define FEAT_AIE ID_AA64MMFR3_EL1, AIE, IMP #define FEAT_S2POE ID_AA64MMFR3_EL1, S2POE, IMP @@ -131,7 +195,6 @@ struct reg_bits_to_feat_map { #define FEAT_SPMU ID_AA64DFR1_EL1, SPMU, IMP #define FEAT_SPE_nVM ID_AA64DFR2_EL1, SPE_nVM, IMP #define FEAT_STEP2 ID_AA64DFR2_EL1, STEP, IMP -#define FEAT_SYSREG128 ID_AA64ISAR2_EL1, SYSREG_128, IMP #define FEAT_CPA2 ID_AA64ISAR3_EL1, CPA, CPA2 #define FEAT_ASID2 ID_AA64MMFR4_EL1, ASID2, IMP #define FEAT_MEC ID_AA64MMFR3_EL1, MEC, IMP @@ -143,7 +206,6 @@ struct reg_bits_to_feat_map { #define FEAT_LSMAOC ID_AA64MMFR2_EL1, LSM, IMP #define FEAT_MixedEnd ID_AA64MMFR0_EL1, BIGEND, IMP #define FEAT_MixedEndEL0 ID_AA64MMFR0_EL1, BIGENDEL0, IMP -#define FEAT_MTE2 ID_AA64PFR1_EL1, MTE, MTE2 #define FEAT_MTE_ASYNC ID_AA64PFR1_EL1, MTE_frac, ASYNC #define FEAT_MTE_STORE_ONLY ID_AA64PFR2_EL1, MTESTOREONLY, IMP #define FEAT_PAN ID_AA64MMFR1_EL1, PAN, IMP @@ -151,7 +213,9 @@ struct reg_bits_to_feat_map { #define FEAT_SSBS ID_AA64PFR1_EL1, SSBS, IMP #define FEAT_TIDCP1 ID_AA64MMFR1_EL1, TIDCP1, IMP #define FEAT_FGT ID_AA64MMFR0_EL1, FGT, IMP +#define FEAT_FGT2 ID_AA64MMFR0_EL1, FGT, FGT2 #define FEAT_MTPMU ID_AA64DFR0_EL1, MTPMU, IMP +#define FEAT_HCX ID_AA64MMFR1_EL1, HCX, IMP static bool not_feat_aa64el3(struct kvm *kvm) { @@ -397,6 +461,10 @@ static const struct reg_bits_to_feat_map hfgrtr_feat_map[] = { NEVER_FGU, FEAT_AA64EL1), }; + +static const DECLARE_FEAT_MAP_FGT(hfgrtr_desc, hfgrtr_masks, + hfgrtr_feat_map, FEAT_FGT); + static const struct reg_bits_to_feat_map hfgwtr_feat_map[] = { NEEDS_FEAT(HFGWTR_EL2_nAMAIR2_EL1 | HFGWTR_EL2_nMAIR2_EL1, @@ -461,6 +529,9 @@ static const struct reg_bits_to_feat_map hfgwtr_feat_map[] = { NEVER_FGU, FEAT_AA64EL1), }; +static const DECLARE_FEAT_MAP_FGT(hfgwtr_desc, hfgwtr_masks, + hfgwtr_feat_map, FEAT_FGT); + static const struct reg_bits_to_feat_map hdfgrtr_feat_map[] = { NEEDS_FEAT(HDFGRTR_EL2_PMBIDR_EL1 | HDFGRTR_EL2_PMSLATFR_EL1 | @@ -528,6 +599,9 @@ static const struct reg_bits_to_feat_map hdfgrtr_feat_map[] = { NEVER_FGU, FEAT_AA64EL1) }; +static const DECLARE_FEAT_MAP_FGT(hdfgrtr_desc, hdfgrtr_masks, + hdfgrtr_feat_map, FEAT_FGT); + static const struct reg_bits_to_feat_map hdfgwtr_feat_map[] = { NEEDS_FEAT(HDFGWTR_EL2_PMSLATFR_EL1 | HDFGWTR_EL2_PMSIRR_EL1 | @@ -588,6 +662,8 @@ static const struct reg_bits_to_feat_map hdfgwtr_feat_map[] = { NEEDS_FEAT(HDFGWTR_EL2_TRFCR_EL1, FEAT_TRF), }; +static const DECLARE_FEAT_MAP_FGT(hdfgwtr_desc, hdfgwtr_masks, + hdfgwtr_feat_map, FEAT_FGT); static const struct reg_bits_to_feat_map hfgitr_feat_map[] = { NEEDS_FEAT(HFGITR_EL2_PSBCSYNC, FEAT_SPEv1p5), @@ -662,6 +738,9 @@ static const struct reg_bits_to_feat_map hfgitr_feat_map[] = { NEVER_FGU, FEAT_AA64EL1), }; +static const DECLARE_FEAT_MAP_FGT(hfgitr_desc, hfgitr_masks, + hfgitr_feat_map, FEAT_FGT); + static const struct reg_bits_to_feat_map hafgrtr_feat_map[] = { NEEDS_FEAT(HAFGRTR_EL2_AMEVTYPER115_EL0 | HAFGRTR_EL2_AMEVTYPER114_EL0 | @@ -704,11 +783,17 @@ static const struct reg_bits_to_feat_map hafgrtr_feat_map[] = { FEAT_AMUv1), }; +static const DECLARE_FEAT_MAP_FGT(hafgrtr_desc, hafgrtr_masks, + hafgrtr_feat_map, FEAT_FGT); + static const struct reg_bits_to_feat_map hfgitr2_feat_map[] = { NEEDS_FEAT(HFGITR2_EL2_nDCCIVAPS, FEAT_PoPS), NEEDS_FEAT(HFGITR2_EL2_TSBCSYNC, FEAT_TRBEv1p1) }; +static const DECLARE_FEAT_MAP_FGT(hfgitr2_desc, hfgitr2_masks, + hfgitr2_feat_map, FEAT_FGT2); + static const struct reg_bits_to_feat_map hfgrtr2_feat_map[] = { NEEDS_FEAT(HFGRTR2_EL2_nPFAR_EL1, FEAT_PFAR), NEEDS_FEAT(HFGRTR2_EL2_nERXGSR_EL1, FEAT_RASv2), @@ -728,6 +813,9 @@ static const struct reg_bits_to_feat_map hfgrtr2_feat_map[] = { NEEDS_FEAT(HFGRTR2_EL2_nRCWSMASK_EL1, FEAT_THE), }; +static const DECLARE_FEAT_MAP_FGT(hfgrtr2_desc, hfgrtr2_masks, + hfgrtr2_feat_map, FEAT_FGT2); + static const struct reg_bits_to_feat_map hfgwtr2_feat_map[] = { NEEDS_FEAT(HFGWTR2_EL2_nPFAR_EL1, FEAT_PFAR), NEEDS_FEAT(HFGWTR2_EL2_nACTLRALIAS_EL1 | @@ -746,6 +834,9 @@ static const struct reg_bits_to_feat_map hfgwtr2_feat_map[] = { NEEDS_FEAT(HFGWTR2_EL2_nRCWSMASK_EL1, FEAT_THE), }; +static const DECLARE_FEAT_MAP_FGT(hfgwtr2_desc, hfgwtr2_masks, + hfgwtr2_feat_map, FEAT_FGT2); + static const struct reg_bits_to_feat_map hdfgrtr2_feat_map[] = { NEEDS_FEAT(HDFGRTR2_EL2_nMDSELR_EL1, FEAT_Debugv8p9), NEEDS_FEAT(HDFGRTR2_EL2_nPMECR_EL1, feat_ebep_pmuv3_ss), @@ -776,6 +867,9 @@ static const struct reg_bits_to_feat_map hdfgrtr2_feat_map[] = { NEEDS_FEAT(HDFGRTR2_EL2_nTRBMPAM_EL1, feat_trbe_mpam), }; +static const DECLARE_FEAT_MAP_FGT(hdfgrtr2_desc, hdfgrtr2_masks, + hdfgrtr2_feat_map, FEAT_FGT2); + static const struct reg_bits_to_feat_map hdfgwtr2_feat_map[] = { NEEDS_FEAT(HDFGWTR2_EL2_nMDSELR_EL1, FEAT_Debugv8p9), NEEDS_FEAT(HDFGWTR2_EL2_nPMECR_EL1, feat_ebep_pmuv3_ss), @@ -804,6 +898,10 @@ static const struct reg_bits_to_feat_map hdfgwtr2_feat_map[] = { NEEDS_FEAT(HDFGWTR2_EL2_nTRBMPAM_EL1, feat_trbe_mpam), }; +static const DECLARE_FEAT_MAP_FGT(hdfgwtr2_desc, hdfgwtr2_masks, + hdfgwtr2_feat_map, FEAT_FGT2); + + static const struct reg_bits_to_feat_map hcrx_feat_map[] = { NEEDS_FEAT(HCRX_EL2_PACMEn, feat_pauth_lr), NEEDS_FEAT(HCRX_EL2_EnFPM, FEAT_FPMR), @@ -833,6 +931,10 @@ static const struct reg_bits_to_feat_map hcrx_feat_map[] = { NEEDS_FEAT(HCRX_EL2_EnAS0, FEAT_LS64_ACCDATA), }; + +static const DECLARE_FEAT_MAP(hcrx_desc, __HCRX_EL2, + hcrx_feat_map, FEAT_HCX); + static const struct reg_bits_to_feat_map hcr_feat_map[] = { NEEDS_FEAT(HCR_EL2_TID0, FEAT_AA32EL0), NEEDS_FEAT_FIXED(HCR_EL2_RW, compute_hcr_rw), @@ -904,6 +1006,9 @@ static const struct reg_bits_to_feat_map hcr_feat_map[] = { NEEDS_FEAT_FIXED(HCR_EL2_E2H, compute_hcr_e2h), }; +static const DECLARE_FEAT_MAP(hcr_desc, HCR_EL2, + hcr_feat_map, FEAT_AA64EL2); + static const struct reg_bits_to_feat_map sctlr2_feat_map[] = { NEEDS_FEAT(SCTLR2_EL1_NMEA | SCTLR2_EL1_EASE, @@ -921,6 +1026,9 @@ static const struct reg_bits_to_feat_map sctlr2_feat_map[] = { FEAT_CPA2), }; +static const DECLARE_FEAT_MAP(sctlr2_desc, SCTLR2_EL1, + sctlr2_feat_map, FEAT_SCTLR2); + static const struct reg_bits_to_feat_map tcr2_el2_feat_map[] = { NEEDS_FEAT(TCR2_EL2_FNG1 | TCR2_EL2_FNG0 | @@ -943,6 +1051,9 @@ static const struct reg_bits_to_feat_map tcr2_el2_feat_map[] = { NEEDS_FEAT(TCR2_EL2_PIE, FEAT_S1PIE), }; +static const DECLARE_FEAT_MAP(tcr2_el2_desc, TCR2_EL2, + tcr2_el2_feat_map, FEAT_TCR2); + static const struct reg_bits_to_feat_map sctlr_el1_feat_map[] = { NEEDS_FEAT(SCTLR_EL1_CP15BEN | SCTLR_EL1_ITD | @@ -1017,6 +1128,9 @@ static const struct reg_bits_to_feat_map sctlr_el1_feat_map[] = { FEAT_AA64EL1), }; +static const DECLARE_FEAT_MAP(sctlr_el1_desc, SCTLR_EL1, + sctlr_el1_feat_map, FEAT_AA64EL1); + static const struct reg_bits_to_feat_map mdcr_el2_feat_map[] = { NEEDS_FEAT(MDCR_EL2_EBWE, FEAT_Debugv8p9), NEEDS_FEAT(MDCR_EL2_TDOSA, FEAT_DoubleLock), @@ -1048,6 +1162,9 @@ static const struct reg_bits_to_feat_map mdcr_el2_feat_map[] = { FEAT_AA64EL1), }; +static const DECLARE_FEAT_MAP(mdcr_el2_desc, MDCR_EL2, + mdcr_el2_feat_map, FEAT_AA64EL2); + static void __init check_feat_map(const struct reg_bits_to_feat_map *map, int map_size, u64 res0, const char *str) { @@ -1061,32 +1178,36 @@ static void __init check_feat_map(const struct reg_bits_to_feat_map *map, str, mask ^ ~res0); } +static u64 reg_feat_map_bits(const struct reg_bits_to_feat_map *map) +{ + return map->flags & RES0_POINTER ? ~(*map->res0p) : map->bits; +} + +static void __init check_reg_desc(const struct reg_feat_map_desc *r) +{ + check_feat_map(r->bit_feat_map, r->bit_feat_map_sz, + ~reg_feat_map_bits(&r->feat_map), r->name); +} + void __init check_feature_map(void) { - check_feat_map(hfgrtr_feat_map, ARRAY_SIZE(hfgrtr_feat_map), - hfgrtr_masks.res0, hfgrtr_masks.str); - check_feat_map(hfgwtr_feat_map, ARRAY_SIZE(hfgwtr_feat_map), - hfgwtr_masks.res0, hfgwtr_masks.str); - check_feat_map(hfgitr_feat_map, ARRAY_SIZE(hfgitr_feat_map), - hfgitr_masks.res0, hfgitr_masks.str); - check_feat_map(hdfgrtr_feat_map, ARRAY_SIZE(hdfgrtr_feat_map), - hdfgrtr_masks.res0, hdfgrtr_masks.str); - check_feat_map(hdfgwtr_feat_map, ARRAY_SIZE(hdfgwtr_feat_map), - hdfgwtr_masks.res0, hdfgwtr_masks.str); - check_feat_map(hafgrtr_feat_map, ARRAY_SIZE(hafgrtr_feat_map), - hafgrtr_masks.res0, hafgrtr_masks.str); - check_feat_map(hcrx_feat_map, ARRAY_SIZE(hcrx_feat_map), - __HCRX_EL2_RES0, "HCRX_EL2"); - check_feat_map(hcr_feat_map, ARRAY_SIZE(hcr_feat_map), - HCR_EL2_RES0, "HCR_EL2"); - check_feat_map(sctlr2_feat_map, ARRAY_SIZE(sctlr2_feat_map), - SCTLR2_EL1_RES0, "SCTLR2_EL1"); - check_feat_map(tcr2_el2_feat_map, ARRAY_SIZE(tcr2_el2_feat_map), - TCR2_EL2_RES0, "TCR2_EL2"); - check_feat_map(sctlr_el1_feat_map, ARRAY_SIZE(sctlr_el1_feat_map), - SCTLR_EL1_RES0, "SCTLR_EL1"); - check_feat_map(mdcr_el2_feat_map, ARRAY_SIZE(mdcr_el2_feat_map), - MDCR_EL2_RES0, "MDCR_EL2"); + check_reg_desc(&hfgrtr_desc); + check_reg_desc(&hfgwtr_desc); + check_reg_desc(&hfgitr_desc); + check_reg_desc(&hdfgrtr_desc); + check_reg_desc(&hdfgwtr_desc); + check_reg_desc(&hafgrtr_desc); + check_reg_desc(&hfgrtr2_desc); + check_reg_desc(&hfgwtr2_desc); + check_reg_desc(&hfgitr2_desc); + check_reg_desc(&hdfgrtr2_desc); + check_reg_desc(&hdfgwtr2_desc); + check_reg_desc(&hcrx_desc); + check_reg_desc(&hcr_desc); + check_reg_desc(&sctlr2_desc); + check_reg_desc(&tcr2_el2_desc); + check_reg_desc(&sctlr_el1_desc); + check_reg_desc(&mdcr_el2_desc); } static bool idreg_feat_match(struct kvm *kvm, const struct reg_bits_to_feat_map *map) @@ -1129,7 +1250,7 @@ static u64 __compute_fixed_bits(struct kvm *kvm, match = idreg_feat_match(kvm, &map[i]); if (!match || (map[i].flags & FIXED_VALUE)) - val |= map[i].bits; + val |= reg_feat_map_bits(&map[i]); } return val; @@ -1145,15 +1266,36 @@ static u64 compute_res0_bits(struct kvm *kvm, require, exclude | FIXED_VALUE); } -static u64 compute_fixed_bits(struct kvm *kvm, - const struct reg_bits_to_feat_map *map, - int map_size, - u64 *fixed_bits, - unsigned long require, - unsigned long exclude) +static u64 compute_reg_res0_bits(struct kvm *kvm, + const struct reg_feat_map_desc *r, + unsigned long require, unsigned long exclude) + +{ + u64 res0; + + res0 = compute_res0_bits(kvm, r->bit_feat_map, r->bit_feat_map_sz, + require, exclude); + + /* + * If computing FGUs, don't take RES0 or register existence + * into account -- we're not computing bits for the register + * itself. + */ + if (!(exclude & NEVER_FGU)) { + res0 |= compute_res0_bits(kvm, &r->feat_map, 1, require, exclude); + res0 |= ~reg_feat_map_bits(&r->feat_map); + } + + return res0; +} + +static u64 compute_reg_fixed_bits(struct kvm *kvm, + const struct reg_feat_map_desc *r, + u64 *fixed_bits, unsigned long require, + unsigned long exclude) { - return __compute_fixed_bits(kvm, map, map_size, fixed_bits, - require | FIXED_VALUE, exclude); + return __compute_fixed_bits(kvm, r->bit_feat_map, r->bit_feat_map_sz, + fixed_bits, require | FIXED_VALUE, exclude); } void compute_fgu(struct kvm *kvm, enum fgt_group_id fgt) @@ -1162,51 +1304,40 @@ void compute_fgu(struct kvm *kvm, enum fgt_group_id fgt) switch (fgt) { case HFGRTR_GROUP: - val |= compute_res0_bits(kvm, hfgrtr_feat_map, - ARRAY_SIZE(hfgrtr_feat_map), - 0, NEVER_FGU); - val |= compute_res0_bits(kvm, hfgwtr_feat_map, - ARRAY_SIZE(hfgwtr_feat_map), - 0, NEVER_FGU); + val |= compute_reg_res0_bits(kvm, &hfgrtr_desc, + 0, NEVER_FGU); + val |= compute_reg_res0_bits(kvm, &hfgwtr_desc, + 0, NEVER_FGU); break; case HFGITR_GROUP: - val |= compute_res0_bits(kvm, hfgitr_feat_map, - ARRAY_SIZE(hfgitr_feat_map), - 0, NEVER_FGU); + val |= compute_reg_res0_bits(kvm, &hfgitr_desc, + 0, NEVER_FGU); break; case HDFGRTR_GROUP: - val |= compute_res0_bits(kvm, hdfgrtr_feat_map, - ARRAY_SIZE(hdfgrtr_feat_map), - 0, NEVER_FGU); - val |= compute_res0_bits(kvm, hdfgwtr_feat_map, - ARRAY_SIZE(hdfgwtr_feat_map), - 0, NEVER_FGU); + val |= compute_reg_res0_bits(kvm, &hdfgrtr_desc, + 0, NEVER_FGU); + val |= compute_reg_res0_bits(kvm, &hdfgwtr_desc, + 0, NEVER_FGU); break; case HAFGRTR_GROUP: - val |= compute_res0_bits(kvm, hafgrtr_feat_map, - ARRAY_SIZE(hafgrtr_feat_map), - 0, NEVER_FGU); + val |= compute_reg_res0_bits(kvm, &hafgrtr_desc, + 0, NEVER_FGU); break; case HFGRTR2_GROUP: - val |= compute_res0_bits(kvm, hfgrtr2_feat_map, - ARRAY_SIZE(hfgrtr2_feat_map), - 0, NEVER_FGU); - val |= compute_res0_bits(kvm, hfgwtr2_feat_map, - ARRAY_SIZE(hfgwtr2_feat_map), - 0, NEVER_FGU); + val |= compute_reg_res0_bits(kvm, &hfgrtr2_desc, + 0, NEVER_FGU); + val |= compute_reg_res0_bits(kvm, &hfgwtr2_desc, + 0, NEVER_FGU); break; case HFGITR2_GROUP: - val |= compute_res0_bits(kvm, hfgitr2_feat_map, - ARRAY_SIZE(hfgitr2_feat_map), - 0, NEVER_FGU); + val |= compute_reg_res0_bits(kvm, &hfgitr2_desc, + 0, NEVER_FGU); break; case HDFGRTR2_GROUP: - val |= compute_res0_bits(kvm, hdfgrtr2_feat_map, - ARRAY_SIZE(hdfgrtr2_feat_map), - 0, NEVER_FGU); - val |= compute_res0_bits(kvm, hdfgwtr2_feat_map, - ARRAY_SIZE(hdfgwtr2_feat_map), - 0, NEVER_FGU); + val |= compute_reg_res0_bits(kvm, &hdfgrtr2_desc, + 0, NEVER_FGU); + val |= compute_reg_res0_bits(kvm, &hdfgwtr2_desc, + 0, NEVER_FGU); break; default: BUG(); @@ -1221,109 +1352,74 @@ void get_reg_fixed_bits(struct kvm *kvm, enum vcpu_sysreg reg, u64 *res0, u64 *r switch (reg) { case HFGRTR_EL2: - *res0 = compute_res0_bits(kvm, hfgrtr_feat_map, - ARRAY_SIZE(hfgrtr_feat_map), 0, 0); - *res0 |= hfgrtr_masks.res0; + *res0 = compute_reg_res0_bits(kvm, &hfgrtr_desc, 0, 0); *res1 = HFGRTR_EL2_RES1; break; case HFGWTR_EL2: - *res0 = compute_res0_bits(kvm, hfgwtr_feat_map, - ARRAY_SIZE(hfgwtr_feat_map), 0, 0); - *res0 |= hfgwtr_masks.res0; + *res0 = compute_reg_res0_bits(kvm, &hfgwtr_desc, 0, 0); *res1 = HFGWTR_EL2_RES1; break; case HFGITR_EL2: - *res0 = compute_res0_bits(kvm, hfgitr_feat_map, - ARRAY_SIZE(hfgitr_feat_map), 0, 0); - *res0 |= hfgitr_masks.res0; + *res0 = compute_reg_res0_bits(kvm, &hfgitr_desc, 0, 0); *res1 = HFGITR_EL2_RES1; break; case HDFGRTR_EL2: - *res0 = compute_res0_bits(kvm, hdfgrtr_feat_map, - ARRAY_SIZE(hdfgrtr_feat_map), 0, 0); - *res0 |= hdfgrtr_masks.res0; + *res0 = compute_reg_res0_bits(kvm, &hdfgrtr_desc, 0, 0); *res1 = HDFGRTR_EL2_RES1; break; case HDFGWTR_EL2: - *res0 = compute_res0_bits(kvm, hdfgwtr_feat_map, - ARRAY_SIZE(hdfgwtr_feat_map), 0, 0); - *res0 |= hdfgwtr_masks.res0; + *res0 = compute_reg_res0_bits(kvm, &hdfgwtr_desc, 0, 0); *res1 = HDFGWTR_EL2_RES1; break; case HAFGRTR_EL2: - *res0 = compute_res0_bits(kvm, hafgrtr_feat_map, - ARRAY_SIZE(hafgrtr_feat_map), 0, 0); - *res0 |= hafgrtr_masks.res0; + *res0 = compute_reg_res0_bits(kvm, &hafgrtr_desc, 0, 0); *res1 = HAFGRTR_EL2_RES1; break; case HFGRTR2_EL2: - *res0 = compute_res0_bits(kvm, hfgrtr2_feat_map, - ARRAY_SIZE(hfgrtr2_feat_map), 0, 0); - *res0 |= hfgrtr2_masks.res0; + *res0 = compute_reg_res0_bits(kvm, &hfgrtr2_desc, 0, 0); *res1 = HFGRTR2_EL2_RES1; break; case HFGWTR2_EL2: - *res0 = compute_res0_bits(kvm, hfgwtr2_feat_map, - ARRAY_SIZE(hfgwtr2_feat_map), 0, 0); - *res0 |= hfgwtr2_masks.res0; + *res0 = compute_reg_res0_bits(kvm, &hfgwtr2_desc, 0, 0); *res1 = HFGWTR2_EL2_RES1; break; case HFGITR2_EL2: - *res0 = compute_res0_bits(kvm, hfgitr2_feat_map, - ARRAY_SIZE(hfgitr2_feat_map), 0, 0); - *res0 |= hfgitr2_masks.res0; + *res0 = compute_reg_res0_bits(kvm, &hfgitr2_desc, 0, 0); *res1 = HFGITR2_EL2_RES1; break; case HDFGRTR2_EL2: - *res0 = compute_res0_bits(kvm, hdfgrtr2_feat_map, - ARRAY_SIZE(hdfgrtr2_feat_map), 0, 0); - *res0 |= hdfgrtr2_masks.res0; + *res0 = compute_reg_res0_bits(kvm, &hdfgrtr2_desc, 0, 0); *res1 = HDFGRTR2_EL2_RES1; break; case HDFGWTR2_EL2: - *res0 = compute_res0_bits(kvm, hdfgwtr2_feat_map, - ARRAY_SIZE(hdfgwtr2_feat_map), 0, 0); - *res0 |= hdfgwtr2_masks.res0; + *res0 = compute_reg_res0_bits(kvm, &hdfgwtr2_desc, 0, 0); *res1 = HDFGWTR2_EL2_RES1; break; case HCRX_EL2: - *res0 = compute_res0_bits(kvm, hcrx_feat_map, - ARRAY_SIZE(hcrx_feat_map), 0, 0); - *res0 |= __HCRX_EL2_RES0; + *res0 = compute_reg_res0_bits(kvm, &hcrx_desc, 0, 0); *res1 = __HCRX_EL2_RES1; break; case HCR_EL2: - mask = compute_fixed_bits(kvm, hcr_feat_map, - ARRAY_SIZE(hcr_feat_map), &fixed, - 0, 0); - *res0 = compute_res0_bits(kvm, hcr_feat_map, - ARRAY_SIZE(hcr_feat_map), 0, 0); - *res0 |= HCR_EL2_RES0 | (mask & ~fixed); + mask = compute_reg_fixed_bits(kvm, &hcr_desc, &fixed, 0, 0); + *res0 = compute_reg_res0_bits(kvm, &hcr_desc, 0, 0); + *res0 |= (mask & ~fixed); *res1 = HCR_EL2_RES1 | (mask & fixed); break; case SCTLR2_EL1: case SCTLR2_EL2: - *res0 = compute_res0_bits(kvm, sctlr2_feat_map, - ARRAY_SIZE(sctlr2_feat_map), 0, 0); - *res0 |= SCTLR2_EL1_RES0; + *res0 = compute_reg_res0_bits(kvm, &sctlr2_desc, 0, 0); *res1 = SCTLR2_EL1_RES1; break; case TCR2_EL2: - *res0 = compute_res0_bits(kvm, tcr2_el2_feat_map, - ARRAY_SIZE(tcr2_el2_feat_map), 0, 0); - *res0 |= TCR2_EL2_RES0; + *res0 = compute_reg_res0_bits(kvm, &tcr2_el2_desc, 0, 0); *res1 = TCR2_EL2_RES1; break; case SCTLR_EL1: - *res0 = compute_res0_bits(kvm, sctlr_el1_feat_map, - ARRAY_SIZE(sctlr_el1_feat_map), 0, 0); - *res0 |= SCTLR_EL1_RES0; + *res0 = compute_reg_res0_bits(kvm, &sctlr_el1_desc, 0, 0); *res1 = SCTLR_EL1_RES1; break; case MDCR_EL2: - *res0 = compute_res0_bits(kvm, mdcr_el2_feat_map, - ARRAY_SIZE(mdcr_el2_feat_map), 0, 0); - *res0 |= MDCR_EL2_RES0; + *res0 = compute_reg_res0_bits(kvm, &mdcr_el2_desc, 0, 0); *res1 = MDCR_EL2_RES1; break; default: diff --git a/arch/arm64/kvm/debug.c b/arch/arm64/kvm/debug.c index 381382c19fe4..3515a273eaa2 100644 --- a/arch/arm64/kvm/debug.c +++ b/arch/arm64/kvm/debug.c @@ -56,6 +56,9 @@ static void kvm_arm_setup_mdcr_el2(struct kvm_vcpu *vcpu) if (!kvm_guest_owns_debug_regs(vcpu)) vcpu->arch.mdcr_el2 |= MDCR_EL2_TDA; + if (vcpu_has_nv(vcpu)) + kvm_nested_setup_mdcr_el2(vcpu); + /* Write MDCR_EL2 directly if we're already at EL2 */ if (has_vhe()) write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2); @@ -96,6 +99,13 @@ void kvm_init_host_debug_data(void) } } +void kvm_debug_init_vhe(void) +{ + /* Clear PMSCR_EL1.E{0,1}SPE which reset to UNKNOWN values. */ + if (SYS_FIELD_GET(ID_AA64DFR0_EL1, PMSVer, read_sysreg(id_aa64dfr0_el1))) + write_sysreg_el1(0, SYS_PMSCR); +} + /* * Configures the 'external' MDSCR_EL1 value for the guest, i.e. when the host * has taken over MDSCR_EL1. @@ -138,6 +148,9 @@ void kvm_vcpu_load_debug(struct kvm_vcpu *vcpu) /* Must be called before kvm_vcpu_load_vhe() */ KVM_BUG_ON(vcpu_get_flag(vcpu, SYSREGS_ON_CPU), vcpu->kvm); + if (has_vhe()) + *host_data_ptr(host_debug_state.mdcr_el2) = read_sysreg(mdcr_el2); + /* * Determine which of the possible debug states we're in: * @@ -184,6 +197,9 @@ void kvm_vcpu_load_debug(struct kvm_vcpu *vcpu) void kvm_vcpu_put_debug(struct kvm_vcpu *vcpu) { + if (has_vhe()) + write_sysreg(*host_data_ptr(host_debug_state.mdcr_el2), mdcr_el2); + if (likely(!(vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) return; @@ -230,29 +246,29 @@ void kvm_debug_handle_oslar(struct kvm_vcpu *vcpu, u64 val) preempt_enable(); } -void kvm_enable_trbe(void) +static bool skip_trbe_access(bool skip_condition) { - if (has_vhe() || is_protected_kvm_enabled() || - WARN_ON_ONCE(preemptible())) - return; + return (WARN_ON_ONCE(preemptible()) || skip_condition || + is_protected_kvm_enabled() || !is_kvm_arm_initialised()); +} - host_data_set_flag(TRBE_ENABLED); +void kvm_enable_trbe(void) +{ + if (!skip_trbe_access(has_vhe())) + host_data_set_flag(TRBE_ENABLED); } EXPORT_SYMBOL_GPL(kvm_enable_trbe); void kvm_disable_trbe(void) { - if (has_vhe() || is_protected_kvm_enabled() || - WARN_ON_ONCE(preemptible())) - return; - - host_data_clear_flag(TRBE_ENABLED); + if (!skip_trbe_access(has_vhe())) + host_data_clear_flag(TRBE_ENABLED); } EXPORT_SYMBOL_GPL(kvm_disable_trbe); void kvm_tracing_set_el1_configuration(u64 trfcr_while_in_guest) { - if (is_protected_kvm_enabled() || WARN_ON_ONCE(preemptible())) + if (skip_trbe_access(false)) return; if (has_vhe()) { diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c index af69c897c2c3..834f13fb1fb7 100644 --- a/arch/arm64/kvm/emulate-nested.c +++ b/arch/arm64/kvm/emulate-nested.c @@ -1185,6 +1185,7 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = { SR_TRAP(SYS_PMSIRR_EL1, CGT_MDCR_TPMS), SR_TRAP(SYS_PMSLATFR_EL1, CGT_MDCR_TPMS), SR_TRAP(SYS_PMSNEVFR_EL1, CGT_MDCR_TPMS), + SR_TRAP(SYS_PMSDSFR_EL1, CGT_MDCR_TPMS), SR_TRAP(SYS_TRFCR_EL1, CGT_MDCR_TTRF), SR_TRAP(SYS_TRBBASER_EL1, CGT_MDCR_E2TB), SR_TRAP(SYS_TRBLIMITR_EL1, CGT_MDCR_E2TB), diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c index a598072f36d2..bca8c80e11da 100644 --- a/arch/arm64/kvm/handle_exit.c +++ b/arch/arm64/kvm/handle_exit.c @@ -545,7 +545,7 @@ void __noreturn __cold nvhe_hyp_panic_handler(u64 esr, u64 spsr, kvm_err("nVHE hyp BUG at: %s:%u!\n", file, line); else print_nvhe_hyp_panic("BUG", panic_addr); - } else if (IS_ENABLED(CONFIG_CFI_CLANG) && esr_is_cfi_brk(esr)) { + } else if (IS_ENABLED(CONFIG_CFI) && esr_is_cfi_brk(esr)) { kvm_nvhe_report_cfi_failure(panic_addr); } else if (IS_ENABLED(CONFIG_UBSAN_KVM_EL2) && ESR_ELx_EC(esr) == ESR_ELx_EC_BRK64 && @@ -559,6 +559,9 @@ void __noreturn __cold nvhe_hyp_panic_handler(u64 esr, u64 spsr, /* Dump the nVHE hypervisor backtrace */ kvm_nvhe_dump_backtrace(hyp_offset); + /* Dump the faulting instruction */ + dump_kernel_instr(panic_addr + kaslr_offset()); + /* * Hyp has panicked and we're going to handle that by panicking the * kernel. The kernel offset will be revealed in the panic so we're diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h index 84ec4e100fbb..b6682202edf3 100644 --- a/arch/arm64/kvm/hyp/include/hyp/switch.h +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h @@ -431,9 +431,6 @@ static inline void __activate_traps_common(struct kvm_vcpu *vcpu) vcpu_set_flag(vcpu, PMUSERENR_ON_CPU); } - *host_data_ptr(host_debug_state.mdcr_el2) = read_sysreg(mdcr_el2); - write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2); - if (cpus_have_final_cap(ARM64_HAS_HCX)) { u64 hcrx = vcpu->arch.hcrx_el2; if (is_nested_ctxt(vcpu)) { @@ -454,8 +451,6 @@ static inline void __deactivate_traps_common(struct kvm_vcpu *vcpu) { struct kvm_cpu_context *hctxt = host_data_ptr(host_ctxt); - write_sysreg(*host_data_ptr(host_debug_state.mdcr_el2), mdcr_el2); - write_sysreg(0, hstr_el2); if (system_supports_pmuv3()) { write_sysreg(ctxt_sys_reg(hctxt, PMUSERENR_EL0), pmuserenr_el0); diff --git a/arch/arm64/kvm/hyp/include/nvhe/pkvm.h b/arch/arm64/kvm/hyp/include/nvhe/pkvm.h index ce31d3b73603..184ad7a39950 100644 --- a/arch/arm64/kvm/hyp/include/nvhe/pkvm.h +++ b/arch/arm64/kvm/hyp/include/nvhe/pkvm.h @@ -29,7 +29,7 @@ struct pkvm_hyp_vcpu { }; /* - * Holds the relevant data for running a protected vm. + * Holds the relevant data for running a vm in protected mode. */ struct pkvm_hyp_vm { struct kvm kvm; @@ -67,6 +67,8 @@ static inline bool pkvm_hyp_vm_is_protected(struct pkvm_hyp_vm *hyp_vm) void pkvm_hyp_vm_table_init(void *tbl); +int __pkvm_reserve_vm(void); +void __pkvm_unreserve_vm(pkvm_handle_t handle); int __pkvm_init_vm(struct kvm *host_kvm, unsigned long vm_hva, unsigned long pgd_hva); int __pkvm_init_vcpu(pkvm_handle_t handle, struct kvm_vcpu *host_vcpu, diff --git a/arch/arm64/kvm/hyp/include/nvhe/trap_handler.h b/arch/arm64/kvm/hyp/include/nvhe/trap_handler.h index 1e6d995968a1..ba5382c12787 100644 --- a/arch/arm64/kvm/hyp/include/nvhe/trap_handler.h +++ b/arch/arm64/kvm/hyp/include/nvhe/trap_handler.h @@ -12,7 +12,8 @@ #include <asm/kvm_host.h> #define cpu_reg(ctxt, r) (ctxt)->regs.regs[r] -#define DECLARE_REG(type, name, ctxt, reg) \ +#define DECLARE_REG(type, name, ctxt, reg) \ + __always_unused int ___check_reg_ ## reg; \ type name = (type)cpu_reg(ctxt, (reg)) #endif /* __ARM64_KVM_NVHE_TRAP_HANDLER_H__ */ diff --git a/arch/arm64/kvm/hyp/nvhe/Makefile b/arch/arm64/kvm/hyp/nvhe/Makefile index 0b0a68b663d4..a244ec25f8c5 100644 --- a/arch/arm64/kvm/hyp/nvhe/Makefile +++ b/arch/arm64/kvm/hyp/nvhe/Makefile @@ -27,6 +27,7 @@ hyp-obj-y := timer-sr.o sysreg-sr.o debug-sr.o switch.o tlb.o hyp-init.o host.o cache.o setup.o mm.o mem_protect.o sys_regs.o pkvm.o stacktrace.o ffa.o hyp-obj-y += ../vgic-v3-sr.o ../aarch32.o ../vgic-v2-cpuif-proxy.o ../entry.o \ ../fpsimd.o ../hyp-entry.o ../exception.o ../pgtable.o +hyp-obj-y += ../../../kernel/smccc-call.o hyp-obj-$(CONFIG_LIST_HARDENED) += list_debug.o hyp-obj-y += $(lib-objs) diff --git a/arch/arm64/kvm/hyp/nvhe/ffa.c b/arch/arm64/kvm/hyp/nvhe/ffa.c index 3369dd0c4009..4e16f9b96f63 100644 --- a/arch/arm64/kvm/hyp/nvhe/ffa.c +++ b/arch/arm64/kvm/hyp/nvhe/ffa.c @@ -71,36 +71,68 @@ static u32 hyp_ffa_version; static bool has_version_negotiated; static hyp_spinlock_t version_lock; -static void ffa_to_smccc_error(struct arm_smccc_res *res, u64 ffa_errno) +static void ffa_to_smccc_error(struct arm_smccc_1_2_regs *res, u64 ffa_errno) { - *res = (struct arm_smccc_res) { + *res = (struct arm_smccc_1_2_regs) { .a0 = FFA_ERROR, .a2 = ffa_errno, }; } -static void ffa_to_smccc_res_prop(struct arm_smccc_res *res, int ret, u64 prop) +static void ffa_to_smccc_res_prop(struct arm_smccc_1_2_regs *res, int ret, u64 prop) { if (ret == FFA_RET_SUCCESS) { - *res = (struct arm_smccc_res) { .a0 = FFA_SUCCESS, - .a2 = prop }; + *res = (struct arm_smccc_1_2_regs) { .a0 = FFA_SUCCESS, + .a2 = prop }; } else { ffa_to_smccc_error(res, ret); } } -static void ffa_to_smccc_res(struct arm_smccc_res *res, int ret) +static void ffa_to_smccc_res(struct arm_smccc_1_2_regs *res, int ret) { ffa_to_smccc_res_prop(res, ret, 0); } static void ffa_set_retval(struct kvm_cpu_context *ctxt, - struct arm_smccc_res *res) + struct arm_smccc_1_2_regs *res) { cpu_reg(ctxt, 0) = res->a0; cpu_reg(ctxt, 1) = res->a1; cpu_reg(ctxt, 2) = res->a2; cpu_reg(ctxt, 3) = res->a3; + cpu_reg(ctxt, 4) = res->a4; + cpu_reg(ctxt, 5) = res->a5; + cpu_reg(ctxt, 6) = res->a6; + cpu_reg(ctxt, 7) = res->a7; + + /* + * DEN0028C 2.6: SMC32/HVC32 call from aarch64 must preserve x8-x30. + * + * In FF-A 1.2, we cannot rely on the function ID sent by the caller to + * detect 32-bit calls because the CPU cycle management interfaces (e.g. + * FFA_MSG_WAIT, FFA_RUN) are 32-bit only but can have 64-bit responses. + * + * FFA-1.3 introduces 64-bit variants of the CPU cycle management + * interfaces. Moreover, FF-A 1.3 clarifies that SMC32 direct requests + * complete with SMC32 direct reponses which *should* allow us use the + * function ID sent by the caller to determine whether to return x8-x17. + * + * Note that we also cannot rely on function IDs in the response. + * + * Given the above, assume SMC64 and send back x0-x17 unconditionally + * as the passthrough code (__kvm_hyp_host_forward_smc) does the same. + */ + cpu_reg(ctxt, 8) = res->a8; + cpu_reg(ctxt, 9) = res->a9; + cpu_reg(ctxt, 10) = res->a10; + cpu_reg(ctxt, 11) = res->a11; + cpu_reg(ctxt, 12) = res->a12; + cpu_reg(ctxt, 13) = res->a13; + cpu_reg(ctxt, 14) = res->a14; + cpu_reg(ctxt, 15) = res->a15; + cpu_reg(ctxt, 16) = res->a16; + cpu_reg(ctxt, 17) = res->a17; } static bool is_ffa_call(u64 func_id) @@ -113,82 +145,92 @@ static bool is_ffa_call(u64 func_id) static int ffa_map_hyp_buffers(u64 ffa_page_count) { - struct arm_smccc_res res; + struct arm_smccc_1_2_regs res; - arm_smccc_1_1_smc(FFA_FN64_RXTX_MAP, - hyp_virt_to_phys(hyp_buffers.tx), - hyp_virt_to_phys(hyp_buffers.rx), - ffa_page_count, - 0, 0, 0, 0, - &res); + arm_smccc_1_2_smc(&(struct arm_smccc_1_2_regs) { + .a0 = FFA_FN64_RXTX_MAP, + .a1 = hyp_virt_to_phys(hyp_buffers.tx), + .a2 = hyp_virt_to_phys(hyp_buffers.rx), + .a3 = ffa_page_count, + }, &res); return res.a0 == FFA_SUCCESS ? FFA_RET_SUCCESS : res.a2; } static int ffa_unmap_hyp_buffers(void) { - struct arm_smccc_res res; + struct arm_smccc_1_2_regs res; - arm_smccc_1_1_smc(FFA_RXTX_UNMAP, - HOST_FFA_ID, - 0, 0, 0, 0, 0, 0, - &res); + arm_smccc_1_2_smc(&(struct arm_smccc_1_2_regs) { + .a0 = FFA_RXTX_UNMAP, + .a1 = HOST_FFA_ID, + }, &res); return res.a0 == FFA_SUCCESS ? FFA_RET_SUCCESS : res.a2; } -static void ffa_mem_frag_tx(struct arm_smccc_res *res, u32 handle_lo, +static void ffa_mem_frag_tx(struct arm_smccc_1_2_regs *res, u32 handle_lo, u32 handle_hi, u32 fraglen, u32 endpoint_id) { - arm_smccc_1_1_smc(FFA_MEM_FRAG_TX, - handle_lo, handle_hi, fraglen, endpoint_id, - 0, 0, 0, - res); + arm_smccc_1_2_smc(&(struct arm_smccc_1_2_regs) { + .a0 = FFA_MEM_FRAG_TX, + .a1 = handle_lo, + .a2 = handle_hi, + .a3 = fraglen, + .a4 = endpoint_id, + }, res); } -static void ffa_mem_frag_rx(struct arm_smccc_res *res, u32 handle_lo, +static void ffa_mem_frag_rx(struct arm_smccc_1_2_regs *res, u32 handle_lo, u32 handle_hi, u32 fragoff) { - arm_smccc_1_1_smc(FFA_MEM_FRAG_RX, - handle_lo, handle_hi, fragoff, HOST_FFA_ID, - 0, 0, 0, - res); + arm_smccc_1_2_smc(&(struct arm_smccc_1_2_regs) { + .a0 = FFA_MEM_FRAG_RX, + .a1 = handle_lo, + .a2 = handle_hi, + .a3 = fragoff, + .a4 = HOST_FFA_ID, + }, res); } -static void ffa_mem_xfer(struct arm_smccc_res *res, u64 func_id, u32 len, +static void ffa_mem_xfer(struct arm_smccc_1_2_regs *res, u64 func_id, u32 len, u32 fraglen) { - arm_smccc_1_1_smc(func_id, len, fraglen, - 0, 0, 0, 0, 0, - res); + arm_smccc_1_2_smc(&(struct arm_smccc_1_2_regs) { + .a0 = func_id, + .a1 = len, + .a2 = fraglen, + }, res); } -static void ffa_mem_reclaim(struct arm_smccc_res *res, u32 handle_lo, +static void ffa_mem_reclaim(struct arm_smccc_1_2_regs *res, u32 handle_lo, u32 handle_hi, u32 flags) { - arm_smccc_1_1_smc(FFA_MEM_RECLAIM, - handle_lo, handle_hi, flags, - 0, 0, 0, 0, - res); + arm_smccc_1_2_smc(&(struct arm_smccc_1_2_regs) { + .a0 = FFA_MEM_RECLAIM, + .a1 = handle_lo, + .a2 = handle_hi, + .a3 = flags, + }, res); } -static void ffa_retrieve_req(struct arm_smccc_res *res, u32 len) +static void ffa_retrieve_req(struct arm_smccc_1_2_regs *res, u32 len) { - arm_smccc_1_1_smc(FFA_FN64_MEM_RETRIEVE_REQ, - len, len, - 0, 0, 0, 0, 0, - res); + arm_smccc_1_2_smc(&(struct arm_smccc_1_2_regs) { + .a0 = FFA_FN64_MEM_RETRIEVE_REQ, + .a1 = len, + .a2 = len, + }, res); } -static void ffa_rx_release(struct arm_smccc_res *res) +static void ffa_rx_release(struct arm_smccc_1_2_regs *res) { - arm_smccc_1_1_smc(FFA_RX_RELEASE, - 0, 0, - 0, 0, 0, 0, 0, - res); + arm_smccc_1_2_smc(&(struct arm_smccc_1_2_regs) { + .a0 = FFA_RX_RELEASE, + }, res); } -static void do_ffa_rxtx_map(struct arm_smccc_res *res, +static void do_ffa_rxtx_map(struct arm_smccc_1_2_regs *res, struct kvm_cpu_context *ctxt) { DECLARE_REG(phys_addr_t, tx, ctxt, 1); @@ -267,7 +309,7 @@ err_unmap: goto out_unlock; } -static void do_ffa_rxtx_unmap(struct arm_smccc_res *res, +static void do_ffa_rxtx_unmap(struct arm_smccc_1_2_regs *res, struct kvm_cpu_context *ctxt) { DECLARE_REG(u32, id, ctxt, 1); @@ -368,7 +410,7 @@ static int ffa_host_unshare_ranges(struct ffa_mem_region_addr_range *ranges, return ret; } -static void do_ffa_mem_frag_tx(struct arm_smccc_res *res, +static void do_ffa_mem_frag_tx(struct arm_smccc_1_2_regs *res, struct kvm_cpu_context *ctxt) { DECLARE_REG(u32, handle_lo, ctxt, 1); @@ -427,7 +469,7 @@ out: } static void __do_ffa_mem_xfer(const u64 func_id, - struct arm_smccc_res *res, + struct arm_smccc_1_2_regs *res, struct kvm_cpu_context *ctxt) { DECLARE_REG(u32, len, ctxt, 1); @@ -521,7 +563,7 @@ err_unshare: __do_ffa_mem_xfer((fid), (res), (ctxt)); \ } while (0); -static void do_ffa_mem_reclaim(struct arm_smccc_res *res, +static void do_ffa_mem_reclaim(struct arm_smccc_1_2_regs *res, struct kvm_cpu_context *ctxt) { DECLARE_REG(u32, handle_lo, ctxt, 1); @@ -628,13 +670,26 @@ static bool ffa_call_supported(u64 func_id) case FFA_RXTX_MAP: case FFA_MEM_DONATE: case FFA_MEM_RETRIEVE_REQ: + /* Optional notification interfaces added in FF-A 1.1 */ + case FFA_NOTIFICATION_BITMAP_CREATE: + case FFA_NOTIFICATION_BITMAP_DESTROY: + case FFA_NOTIFICATION_BIND: + case FFA_NOTIFICATION_UNBIND: + case FFA_NOTIFICATION_SET: + case FFA_NOTIFICATION_GET: + case FFA_NOTIFICATION_INFO_GET: + /* Optional interfaces added in FF-A 1.2 */ + case FFA_MSG_SEND_DIRECT_REQ2: /* Optional per 7.5.1 */ + case FFA_MSG_SEND_DIRECT_RESP2: /* Optional per 7.5.1 */ + case FFA_CONSOLE_LOG: /* Optional per 13.1: not in Table 13.1 */ + case FFA_PARTITION_INFO_GET_REGS: /* Optional for virtual instances per 13.1 */ return false; } return true; } -static bool do_ffa_features(struct arm_smccc_res *res, +static bool do_ffa_features(struct arm_smccc_1_2_regs *res, struct kvm_cpu_context *ctxt) { DECLARE_REG(u32, id, ctxt, 1); @@ -666,21 +721,25 @@ out_handled: static int hyp_ffa_post_init(void) { size_t min_rxtx_sz; - struct arm_smccc_res res; + struct arm_smccc_1_2_regs res; - arm_smccc_1_1_smc(FFA_ID_GET, 0, 0, 0, 0, 0, 0, 0, &res); + arm_smccc_1_2_smc(&(struct arm_smccc_1_2_regs){ + .a0 = FFA_ID_GET, + }, &res); if (res.a0 != FFA_SUCCESS) return -EOPNOTSUPP; if (res.a2 != HOST_FFA_ID) return -EINVAL; - arm_smccc_1_1_smc(FFA_FEATURES, FFA_FN64_RXTX_MAP, - 0, 0, 0, 0, 0, 0, &res); + arm_smccc_1_2_smc(&(struct arm_smccc_1_2_regs){ + .a0 = FFA_FEATURES, + .a1 = FFA_FN64_RXTX_MAP, + }, &res); if (res.a0 != FFA_SUCCESS) return -EOPNOTSUPP; - switch (res.a2) { + switch (res.a2 & FFA_FEAT_RXTX_MIN_SZ_MASK) { case FFA_FEAT_RXTX_MIN_SZ_4K: min_rxtx_sz = SZ_4K; break; @@ -700,7 +759,7 @@ static int hyp_ffa_post_init(void) return 0; } -static void do_ffa_version(struct arm_smccc_res *res, +static void do_ffa_version(struct arm_smccc_1_2_regs *res, struct kvm_cpu_context *ctxt) { DECLARE_REG(u32, ffa_req_version, ctxt, 1); @@ -712,7 +771,10 @@ static void do_ffa_version(struct arm_smccc_res *res, hyp_spin_lock(&version_lock); if (has_version_negotiated) { - res->a0 = hyp_ffa_version; + if (FFA_MINOR_VERSION(ffa_req_version) < FFA_MINOR_VERSION(hyp_ffa_version)) + res->a0 = FFA_RET_NOT_SUPPORTED; + else + res->a0 = hyp_ffa_version; goto unlock; } @@ -721,9 +783,10 @@ static void do_ffa_version(struct arm_smccc_res *res, * first if TEE supports it. */ if (FFA_MINOR_VERSION(ffa_req_version) < FFA_MINOR_VERSION(hyp_ffa_version)) { - arm_smccc_1_1_smc(FFA_VERSION, ffa_req_version, 0, - 0, 0, 0, 0, 0, - res); + arm_smccc_1_2_smc(&(struct arm_smccc_1_2_regs) { + .a0 = FFA_VERSION, + .a1 = ffa_req_version, + }, res); if (res->a0 == FFA_RET_NOT_SUPPORTED) goto unlock; @@ -740,7 +803,7 @@ unlock: hyp_spin_unlock(&version_lock); } -static void do_ffa_part_get(struct arm_smccc_res *res, +static void do_ffa_part_get(struct arm_smccc_1_2_regs *res, struct kvm_cpu_context *ctxt) { DECLARE_REG(u32, uuid0, ctxt, 1); @@ -756,9 +819,14 @@ static void do_ffa_part_get(struct arm_smccc_res *res, goto out_unlock; } - arm_smccc_1_1_smc(FFA_PARTITION_INFO_GET, uuid0, uuid1, - uuid2, uuid3, flags, 0, 0, - res); + arm_smccc_1_2_smc(&(struct arm_smccc_1_2_regs) { + .a0 = FFA_PARTITION_INFO_GET, + .a1 = uuid0, + .a2 = uuid1, + .a3 = uuid2, + .a4 = uuid3, + .a5 = flags, + }, res); if (res->a0 != FFA_SUCCESS) goto out_unlock; @@ -791,7 +859,7 @@ out_unlock: bool kvm_host_ffa_handler(struct kvm_cpu_context *host_ctxt, u32 func_id) { - struct arm_smccc_res res; + struct arm_smccc_1_2_regs res; /* * There's no way we can tell what a non-standard SMC call might @@ -860,13 +928,16 @@ out_handled: int hyp_ffa_init(void *pages) { - struct arm_smccc_res res; + struct arm_smccc_1_2_regs res; void *tx, *rx; if (kvm_host_psci_config.smccc_version < ARM_SMCCC_VERSION_1_2) return 0; - arm_smccc_1_1_smc(FFA_VERSION, FFA_VERSION_1_1, 0, 0, 0, 0, 0, 0, &res); + arm_smccc_1_2_smc(&(struct arm_smccc_1_2_regs) { + .a0 = FFA_VERSION, + .a1 = FFA_VERSION_1_2, + }, &res); if (res.a0 == FFA_RET_NOT_SUPPORTED) return 0; @@ -886,10 +957,10 @@ int hyp_ffa_init(void *pages) if (FFA_MAJOR_VERSION(res.a0) != 1) return -EOPNOTSUPP; - if (FFA_MINOR_VERSION(res.a0) < FFA_MINOR_VERSION(FFA_VERSION_1_1)) + if (FFA_MINOR_VERSION(res.a0) < FFA_MINOR_VERSION(FFA_VERSION_1_2)) hyp_ffa_version = res.a0; else - hyp_ffa_version = FFA_VERSION_1_1; + hyp_ffa_version = FFA_VERSION_1_2; tx = pages; pages += KVM_FFA_MBOX_NR_PAGES * PAGE_SIZE; diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-main.c b/arch/arm64/kvm/hyp/nvhe/hyp-main.c index 3206b2c07f82..29430c031095 100644 --- a/arch/arm64/kvm/hyp/nvhe/hyp-main.c +++ b/arch/arm64/kvm/hyp/nvhe/hyp-main.c @@ -546,6 +546,18 @@ static void handle___pkvm_prot_finalize(struct kvm_cpu_context *host_ctxt) cpu_reg(host_ctxt, 1) = __pkvm_prot_finalize(); } +static void handle___pkvm_reserve_vm(struct kvm_cpu_context *host_ctxt) +{ + cpu_reg(host_ctxt, 1) = __pkvm_reserve_vm(); +} + +static void handle___pkvm_unreserve_vm(struct kvm_cpu_context *host_ctxt) +{ + DECLARE_REG(pkvm_handle_t, handle, host_ctxt, 1); + + __pkvm_unreserve_vm(handle); +} + static void handle___pkvm_init_vm(struct kvm_cpu_context *host_ctxt) { DECLARE_REG(struct kvm *, host_kvm, host_ctxt, 1); @@ -606,6 +618,8 @@ static const hcall_t host_hcall[] = { HANDLE_FUNC(__kvm_timer_set_cntvoff), HANDLE_FUNC(__vgic_v3_save_vmcr_aprs), HANDLE_FUNC(__vgic_v3_restore_vmcr_aprs), + HANDLE_FUNC(__pkvm_reserve_vm), + HANDLE_FUNC(__pkvm_unreserve_vm), HANDLE_FUNC(__pkvm_init_vm), HANDLE_FUNC(__pkvm_init_vcpu), HANDLE_FUNC(__pkvm_teardown_vm), diff --git a/arch/arm64/kvm/hyp/nvhe/mem_protect.c b/arch/arm64/kvm/hyp/nvhe/mem_protect.c index 8957734d6183..ddc8beb55eee 100644 --- a/arch/arm64/kvm/hyp/nvhe/mem_protect.c +++ b/arch/arm64/kvm/hyp/nvhe/mem_protect.c @@ -1010,9 +1010,12 @@ static int __check_host_shared_guest(struct pkvm_hyp_vm *vm, u64 *__phys, u64 ip return ret; if (!kvm_pte_valid(pte)) return -ENOENT; - if (kvm_granule_size(level) != size) + if (size && kvm_granule_size(level) != size) return -E2BIG; + if (!size) + size = kvm_granule_size(level); + state = guest_get_page_state(pte, ipa); if (state != PKVM_PAGE_SHARED_BORROWED) return -EPERM; @@ -1100,7 +1103,7 @@ int __pkvm_host_relax_perms_guest(u64 gfn, struct pkvm_hyp_vcpu *vcpu, enum kvm_ if (prot & ~KVM_PGTABLE_PROT_RWX) return -EINVAL; - assert_host_shared_guest(vm, ipa, PAGE_SIZE); + assert_host_shared_guest(vm, ipa, 0); guest_lock_component(vm); ret = kvm_pgtable_stage2_relax_perms(&vm->pgt, ipa, prot, 0); guest_unlock_component(vm); @@ -1156,7 +1159,7 @@ int __pkvm_host_mkyoung_guest(u64 gfn, struct pkvm_hyp_vcpu *vcpu) if (pkvm_hyp_vm_is_protected(vm)) return -EPERM; - assert_host_shared_guest(vm, ipa, PAGE_SIZE); + assert_host_shared_guest(vm, ipa, 0); guest_lock_component(vm); kvm_pgtable_stage2_mkyoung(&vm->pgt, ipa, 0); guest_unlock_component(vm); diff --git a/arch/arm64/kvm/hyp/nvhe/pkvm.c b/arch/arm64/kvm/hyp/nvhe/pkvm.c index 338505cb0171..05774aed09cb 100644 --- a/arch/arm64/kvm/hyp/nvhe/pkvm.c +++ b/arch/arm64/kvm/hyp/nvhe/pkvm.c @@ -23,8 +23,8 @@ unsigned int kvm_arm_vmid_bits; unsigned int kvm_host_sve_max_vl; /* - * The currently loaded hyp vCPU for each physical CPU. Used only when - * protected KVM is enabled, but for both protected and non-protected VMs. + * The currently loaded hyp vCPU for each physical CPU. Used in protected mode + * for both protected and non-protected VMs. */ static DEFINE_PER_CPU(struct pkvm_hyp_vcpu *, loaded_hyp_vcpu); @@ -135,7 +135,7 @@ static int pkvm_check_pvm_cpu_features(struct kvm_vcpu *vcpu) { struct kvm *kvm = vcpu->kvm; - /* Protected KVM does not support AArch32 guests. */ + /* No AArch32 support for protected guests. */ if (kvm_has_feat(kvm, ID_AA64PFR0_EL1, EL0, AARCH32) || kvm_has_feat(kvm, ID_AA64PFR0_EL1, EL1, AARCH32)) return -EINVAL; @@ -192,6 +192,11 @@ static int pkvm_vcpu_init_traps(struct pkvm_hyp_vcpu *hyp_vcpu) */ #define HANDLE_OFFSET 0x1000 +/* + * Marks a reserved but not yet used entry in the VM table. + */ +#define RESERVED_ENTRY ((void *)0xa110ca7ed) + static unsigned int vm_handle_to_idx(pkvm_handle_t handle) { return handle - HANDLE_OFFSET; @@ -210,8 +215,8 @@ static pkvm_handle_t idx_to_vm_handle(unsigned int idx) DEFINE_HYP_SPINLOCK(vm_table_lock); /* - * The table of VM entries for protected VMs in hyp. - * Allocated at hyp initialization and setup. + * A table that tracks all VMs in protected mode. + * Allocated during hyp initialization and setup. */ static struct pkvm_hyp_vm **vm_table; @@ -231,6 +236,10 @@ static struct pkvm_hyp_vm *get_vm_by_handle(pkvm_handle_t handle) if (unlikely(idx >= KVM_MAX_PVMS)) return NULL; + /* A reserved entry doesn't represent an initialized VM. */ + if (unlikely(vm_table[idx] == RESERVED_ENTRY)) + return NULL; + return vm_table[idx]; } @@ -401,14 +410,26 @@ static void unpin_host_vcpus(struct pkvm_hyp_vcpu *hyp_vcpus[], } static void init_pkvm_hyp_vm(struct kvm *host_kvm, struct pkvm_hyp_vm *hyp_vm, - unsigned int nr_vcpus) + unsigned int nr_vcpus, pkvm_handle_t handle) { + struct kvm_s2_mmu *mmu = &hyp_vm->kvm.arch.mmu; + int idx = vm_handle_to_idx(handle); + + hyp_vm->kvm.arch.pkvm.handle = handle; + hyp_vm->host_kvm = host_kvm; hyp_vm->kvm.created_vcpus = nr_vcpus; - hyp_vm->kvm.arch.mmu.vtcr = host_mmu.arch.mmu.vtcr; - hyp_vm->kvm.arch.pkvm.enabled = READ_ONCE(host_kvm->arch.pkvm.enabled); + hyp_vm->kvm.arch.pkvm.is_protected = READ_ONCE(host_kvm->arch.pkvm.is_protected); + hyp_vm->kvm.arch.pkvm.is_created = true; hyp_vm->kvm.arch.flags = 0; pkvm_init_features_from_host(hyp_vm, host_kvm); + + /* VMID 0 is reserved for the host */ + atomic64_set(&mmu->vmid.id, idx + 1); + + mmu->vtcr = host_mmu.arch.mmu.vtcr; + mmu->arch = &hyp_vm->kvm.arch; + mmu->pgt = &hyp_vm->pgt; } static int pkvm_vcpu_init_sve(struct pkvm_hyp_vcpu *hyp_vcpu, struct kvm_vcpu *host_vcpu) @@ -480,7 +501,7 @@ done: return ret; } -static int find_free_vm_table_entry(struct kvm *host_kvm) +static int find_free_vm_table_entry(void) { int i; @@ -493,15 +514,13 @@ static int find_free_vm_table_entry(struct kvm *host_kvm) } /* - * Allocate a VM table entry and insert a pointer to the new vm. + * Reserve a VM table entry. * - * Return a unique handle to the protected VM on success, + * Return a unique handle to the VM on success, * negative error code on failure. */ -static pkvm_handle_t insert_vm_table_entry(struct kvm *host_kvm, - struct pkvm_hyp_vm *hyp_vm) +static int allocate_vm_table_entry(void) { - struct kvm_s2_mmu *mmu = &hyp_vm->kvm.arch.mmu; int idx; hyp_assert_lock_held(&vm_table_lock); @@ -514,20 +533,57 @@ static pkvm_handle_t insert_vm_table_entry(struct kvm *host_kvm, if (unlikely(!vm_table)) return -EINVAL; - idx = find_free_vm_table_entry(host_kvm); - if (idx < 0) + idx = find_free_vm_table_entry(); + if (unlikely(idx < 0)) return idx; - hyp_vm->kvm.arch.pkvm.handle = idx_to_vm_handle(idx); + vm_table[idx] = RESERVED_ENTRY; - /* VMID 0 is reserved for the host */ - atomic64_set(&mmu->vmid.id, idx + 1); + return idx; +} - mmu->arch = &hyp_vm->kvm.arch; - mmu->pgt = &hyp_vm->pgt; +static int __insert_vm_table_entry(pkvm_handle_t handle, + struct pkvm_hyp_vm *hyp_vm) +{ + unsigned int idx; + + hyp_assert_lock_held(&vm_table_lock); + + /* + * Initializing protected state might have failed, yet a malicious + * host could trigger this function. Thus, ensure that 'vm_table' + * exists. + */ + if (unlikely(!vm_table)) + return -EINVAL; + + idx = vm_handle_to_idx(handle); + if (unlikely(idx >= KVM_MAX_PVMS)) + return -EINVAL; + + if (unlikely(vm_table[idx] != RESERVED_ENTRY)) + return -EINVAL; vm_table[idx] = hyp_vm; - return hyp_vm->kvm.arch.pkvm.handle; + + return 0; +} + +/* + * Insert a pointer to the initialized VM into the VM table. + * + * Return 0 on success, or negative error code on failure. + */ +static int insert_vm_table_entry(pkvm_handle_t handle, + struct pkvm_hyp_vm *hyp_vm) +{ + int ret; + + hyp_spin_lock(&vm_table_lock); + ret = __insert_vm_table_entry(handle, hyp_vm); + hyp_spin_unlock(&vm_table_lock); + + return ret; } /* @@ -594,10 +650,45 @@ static void unmap_donated_memory_noclear(void *va, size_t size) } /* - * Initialize the hypervisor copy of the protected VM state using the - * memory donated by the host. + * Reserves an entry in the hypervisor for a new VM in protected mode. * - * Unmaps the donated memory from the host at stage 2. + * Return a unique handle to the VM on success, negative error code on failure. + */ +int __pkvm_reserve_vm(void) +{ + int ret; + + hyp_spin_lock(&vm_table_lock); + ret = allocate_vm_table_entry(); + hyp_spin_unlock(&vm_table_lock); + + if (ret < 0) + return ret; + + return idx_to_vm_handle(ret); +} + +/* + * Removes a reserved entry, but only if is hasn't been used yet. + * Otherwise, the VM needs to be destroyed. + */ +void __pkvm_unreserve_vm(pkvm_handle_t handle) +{ + unsigned int idx = vm_handle_to_idx(handle); + + if (unlikely(!vm_table)) + return; + + hyp_spin_lock(&vm_table_lock); + if (likely(idx < KVM_MAX_PVMS && vm_table[idx] == RESERVED_ENTRY)) + remove_vm_table_entry(handle); + hyp_spin_unlock(&vm_table_lock); +} + +/* + * Initialize the hypervisor copy of the VM state using host-donated memory. + * + * Unmap the donated memory from the host at stage 2. * * host_kvm: A pointer to the host's struct kvm. * vm_hva: The host va of the area being donated for the VM state. @@ -606,8 +697,7 @@ static void unmap_donated_memory_noclear(void *va, size_t size) * the VM. Must be page aligned. Its size is implied by the VM's * VTCR. * - * Return a unique handle to the protected VM on success, - * negative error code on failure. + * Return 0 success, negative error code on failure. */ int __pkvm_init_vm(struct kvm *host_kvm, unsigned long vm_hva, unsigned long pgd_hva) @@ -615,6 +705,7 @@ int __pkvm_init_vm(struct kvm *host_kvm, unsigned long vm_hva, struct pkvm_hyp_vm *hyp_vm = NULL; size_t vm_size, pgd_size; unsigned int nr_vcpus; + pkvm_handle_t handle; void *pgd = NULL; int ret; @@ -628,6 +719,12 @@ int __pkvm_init_vm(struct kvm *host_kvm, unsigned long vm_hva, goto err_unpin_kvm; } + handle = READ_ONCE(host_kvm->arch.pkvm.handle); + if (unlikely(handle < HANDLE_OFFSET)) { + ret = -EINVAL; + goto err_unpin_kvm; + } + vm_size = pkvm_get_hyp_vm_size(nr_vcpus); pgd_size = kvm_pgtable_stage2_pgd_size(host_mmu.arch.mmu.vtcr); @@ -641,24 +738,19 @@ int __pkvm_init_vm(struct kvm *host_kvm, unsigned long vm_hva, if (!pgd) goto err_remove_mappings; - init_pkvm_hyp_vm(host_kvm, hyp_vm, nr_vcpus); - - hyp_spin_lock(&vm_table_lock); - ret = insert_vm_table_entry(host_kvm, hyp_vm); - if (ret < 0) - goto err_unlock; + init_pkvm_hyp_vm(host_kvm, hyp_vm, nr_vcpus, handle); ret = kvm_guest_prepare_stage2(hyp_vm, pgd); if (ret) - goto err_remove_vm_table_entry; - hyp_spin_unlock(&vm_table_lock); + goto err_remove_mappings; - return hyp_vm->kvm.arch.pkvm.handle; + /* Must be called last since this publishes the VM. */ + ret = insert_vm_table_entry(handle, hyp_vm); + if (ret) + goto err_remove_mappings; + + return 0; -err_remove_vm_table_entry: - remove_vm_table_entry(hyp_vm->kvm.arch.pkvm.handle); -err_unlock: - hyp_spin_unlock(&vm_table_lock); err_remove_mappings: unmap_donated_memory(hyp_vm, vm_size); unmap_donated_memory(pgd, pgd_size); @@ -668,10 +760,9 @@ err_unpin_kvm: } /* - * Initialize the hypervisor copy of the protected vCPU state using the - * memory donated by the host. + * Initialize the hypervisor copy of the vCPU state using host-donated memory. * - * handle: The handle for the protected vm. + * handle: The hypervisor handle for the vm. * host_vcpu: A pointer to the corresponding host vcpu. * vcpu_hva: The host va of the area being donated for the vcpu state. * Must be page aligned. The size of the area must be equal to diff --git a/arch/arm64/kvm/hyp/nvhe/setup.c b/arch/arm64/kvm/hyp/nvhe/setup.c index a48d3f5a5afb..90bd014e952f 100644 --- a/arch/arm64/kvm/hyp/nvhe/setup.c +++ b/arch/arm64/kvm/hyp/nvhe/setup.c @@ -192,6 +192,7 @@ static int fix_host_ownership_walker(const struct kvm_pgtable_visit_ctx *ctx, enum pkvm_page_state state; struct hyp_page *page; phys_addr_t phys; + enum kvm_pgtable_prot prot; if (!kvm_pte_valid(ctx->old)) return 0; @@ -210,11 +211,18 @@ static int fix_host_ownership_walker(const struct kvm_pgtable_visit_ctx *ctx, * configured in the hypervisor stage-1, and make sure to propagate them * to the hyp_vmemmap state. */ - state = pkvm_getstate(kvm_pgtable_hyp_pte_prot(ctx->old)); + prot = kvm_pgtable_hyp_pte_prot(ctx->old); + state = pkvm_getstate(prot); switch (state) { case PKVM_PAGE_OWNED: set_hyp_state(page, PKVM_PAGE_OWNED); - return host_stage2_set_owner_locked(phys, PAGE_SIZE, PKVM_ID_HYP); + /* hyp text is RO in the host stage-2 to be inspected on panic. */ + if (prot == PAGE_HYP_EXEC) { + set_host_state(page, PKVM_NOPAGE); + return host_stage2_idmap_locked(phys, PAGE_SIZE, KVM_PGTABLE_PROT_R); + } else { + return host_stage2_set_owner_locked(phys, PAGE_SIZE, PKVM_ID_HYP); + } case PKVM_PAGE_SHARED_OWNED: set_hyp_state(page, PKVM_PAGE_SHARED_OWNED); set_host_state(page, PKVM_PAGE_SHARED_BORROWED); diff --git a/arch/arm64/kvm/hyp/nvhe/switch.c b/arch/arm64/kvm/hyp/nvhe/switch.c index ccd575d5f6de..d3b9ec8a7c28 100644 --- a/arch/arm64/kvm/hyp/nvhe/switch.c +++ b/arch/arm64/kvm/hyp/nvhe/switch.c @@ -50,6 +50,10 @@ extern void kvm_nvhe_prepare_backtrace(unsigned long fp, unsigned long pc); static void __activate_traps(struct kvm_vcpu *vcpu) { ___activate_traps(vcpu, vcpu->arch.hcr_el2); + + *host_data_ptr(host_debug_state.mdcr_el2) = read_sysreg(mdcr_el2); + write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2); + __activate_traps_common(vcpu); __activate_cptr_traps(vcpu); @@ -93,6 +97,8 @@ static void __deactivate_traps(struct kvm_vcpu *vcpu) isb(); } + write_sysreg(*host_data_ptr(host_debug_state.mdcr_el2), mdcr_el2); + __deactivate_traps_common(vcpu); write_sysreg_hcr(this_cpu_ptr(&kvm_init_params)->hcr_el2); diff --git a/arch/arm64/kvm/hyp/nvhe/sys_regs.c b/arch/arm64/kvm/hyp/nvhe/sys_regs.c index 71d2fc97f004..82da9b03692d 100644 --- a/arch/arm64/kvm/hyp/nvhe/sys_regs.c +++ b/arch/arm64/kvm/hyp/nvhe/sys_regs.c @@ -253,7 +253,7 @@ static void inject_undef64(struct kvm_vcpu *vcpu) *vcpu_pc(vcpu) = read_sysreg_el2(SYS_ELR); *vcpu_cpsr(vcpu) = read_sysreg_el2(SYS_SPSR); - __vcpu_assign_sys_reg(vcpu, read_sysreg_el1(SYS_VBAR), VBAR_EL1); + __vcpu_assign_sys_reg(vcpu, VBAR_EL1, read_sysreg_el1(SYS_VBAR)); kvm_pend_exception(vcpu, EXCEPT_AA64_EL1_SYNC); diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c index c36f282a175d..c351b4abd5db 100644 --- a/arch/arm64/kvm/hyp/pgtable.c +++ b/arch/arm64/kvm/hyp/pgtable.c @@ -1551,38 +1551,21 @@ static int stage2_free_walker(const struct kvm_pgtable_visit_ctx *ctx, return 0; } -void kvm_pgtable_stage2_destroy_range(struct kvm_pgtable *pgt, - u64 addr, u64 size) +void kvm_pgtable_stage2_destroy(struct kvm_pgtable *pgt) { + size_t pgd_sz; struct kvm_pgtable_walker walker = { .cb = stage2_free_walker, .flags = KVM_PGTABLE_WALK_LEAF | KVM_PGTABLE_WALK_TABLE_POST, }; - WARN_ON(kvm_pgtable_walk(pgt, addr, size, &walker)); -} - -void kvm_pgtable_stage2_destroy_pgd(struct kvm_pgtable *pgt) -{ - size_t pgd_sz; - + WARN_ON(kvm_pgtable_walk(pgt, 0, BIT(pgt->ia_bits), &walker)); pgd_sz = kvm_pgd_pages(pgt->ia_bits, pgt->start_level) * PAGE_SIZE; - - /* - * Since the pgtable is unlinked at this point, and not shared with - * other walkers, safely deference pgd with kvm_dereference_pteref_raw() - */ - pgt->mm_ops->free_pages_exact(kvm_dereference_pteref_raw(pgt->pgd), pgd_sz); + pgt->mm_ops->free_pages_exact(kvm_dereference_pteref(&walker, pgt->pgd), pgd_sz); pgt->pgd = NULL; } -void kvm_pgtable_stage2_destroy(struct kvm_pgtable *pgt) -{ - kvm_pgtable_stage2_destroy_range(pgt, 0, BIT(pgt->ia_bits)); - kvm_pgtable_stage2_destroy_pgd(pgt); -} - void kvm_pgtable_stage2_free_unlinked(struct kvm_pgtable_mm_ops *mm_ops, void *pgtable, s8 level) { kvm_pteref_t ptep = (kvm_pteref_t)pgtable; diff --git a/arch/arm64/kvm/hyp/vgic-v3-sr.c b/arch/arm64/kvm/hyp/vgic-v3-sr.c index d81275790e69..acd909b7f225 100644 --- a/arch/arm64/kvm/hyp/vgic-v3-sr.c +++ b/arch/arm64/kvm/hyp/vgic-v3-sr.c @@ -295,12 +295,8 @@ void __vgic_v3_activate_traps(struct vgic_v3_cpu_if *cpu_if) } } - /* - * GICv5 BET0 FEAT_GCIE_LEGACY doesn't include ICC_SRE_EL2. This is due - * to be relaxed in a future spec release, at which point this in - * condition can be dropped. - */ - if (!cpus_have_final_cap(ARM64_HAS_GICV5_CPUIF)) { + /* Only disable SRE if the host implements the GICv2 interface */ + if (static_branch_unlikely(&vgic_v3_has_v2_compat)) { /* * Prevent the guest from touching the ICC_SRE_EL1 system * register. Note that this may not have any effect, as @@ -329,19 +325,16 @@ void __vgic_v3_deactivate_traps(struct vgic_v3_cpu_if *cpu_if) cpu_if->vgic_vmcr = read_gicreg(ICH_VMCR_EL2); } - /* - * Can be dropped in the future when GICv5 spec is relaxed. See comment - * above. - */ - if (!cpus_have_final_cap(ARM64_HAS_GICV5_CPUIF)) { + /* Only restore SRE if the host implements the GICv2 interface */ + if (static_branch_unlikely(&vgic_v3_has_v2_compat)) { val = read_gicreg(ICC_SRE_EL2); write_gicreg(val | ICC_SRE_EL2_ENABLE, ICC_SRE_EL2); - } - if (!cpu_if->vgic_sre) { - /* Make sure ENABLE is set at EL2 before setting SRE at EL1 */ - isb(); - write_gicreg(1, ICC_SRE_EL1); + if (!cpu_if->vgic_sre) { + /* Make sure ENABLE is set at EL2 before setting SRE at EL1 */ + isb(); + write_gicreg(1, ICC_SRE_EL1); + } } /* diff --git a/arch/arm64/kvm/hyp/vhe/switch.c b/arch/arm64/kvm/hyp/vhe/switch.c index 0998ad4a2552..9984c492305a 100644 --- a/arch/arm64/kvm/hyp/vhe/switch.c +++ b/arch/arm64/kvm/hyp/vhe/switch.c @@ -95,6 +95,13 @@ static u64 __compute_hcr(struct kvm_vcpu *vcpu) /* Force NV2 in case the guest is forgetful... */ guest_hcr |= HCR_NV2; } + + /* + * Exclude the guest's TWED configuration if it hasn't set TWE + * to avoid potentially delaying traps for the host. + */ + if (!(guest_hcr & HCR_TWE)) + guest_hcr &= ~(HCR_EL2_TWEDEn | HCR_EL2_TWEDEL); } BUG_ON(host_data_test_flag(VCPU_IN_HYP_CONTEXT) && diff --git a/arch/arm64/kvm/inject_fault.c b/arch/arm64/kvm/inject_fault.c index 6745f38b64f9..dfcd66c65517 100644 --- a/arch/arm64/kvm/inject_fault.c +++ b/arch/arm64/kvm/inject_fault.c @@ -106,7 +106,30 @@ static void inject_abt64(struct kvm_vcpu *vcpu, bool is_iabt, unsigned long addr { unsigned long cpsr = *vcpu_cpsr(vcpu); bool is_aarch32 = vcpu_mode_is_32bit(vcpu); - u64 esr = 0; + u64 esr = 0, fsc; + int level; + + /* + * If injecting an abort from a failed S1PTW, rewalk the S1 PTs to + * find the failing level. If we can't find it, assume the error was + * transient and restart without changing the state. + */ + if (kvm_vcpu_abt_iss1tw(vcpu)) { + u64 hpfar = kvm_vcpu_get_fault_ipa(vcpu); + int ret; + + if (hpfar == INVALID_GPA) + return; + + ret = __kvm_find_s1_desc_level(vcpu, addr, hpfar, &level); + if (ret) + return; + + WARN_ON_ONCE(level < -1 || level > 3); + fsc = ESR_ELx_FSC_SEA_TTW(level); + } else { + fsc = ESR_ELx_FSC_EXTABT; + } /* This delight is brought to you by FEAT_DoubleFault2. */ if (effective_sctlr2_ease(vcpu)) @@ -133,7 +156,7 @@ static void inject_abt64(struct kvm_vcpu *vcpu, bool is_iabt, unsigned long addr if (!is_iabt) esr |= ESR_ELx_EC_DABT_LOW << ESR_ELx_EC_SHIFT; - esr |= ESR_ELx_FSC_EXTABT; + esr |= fsc; vcpu_write_sys_reg(vcpu, addr, exception_far_elx(vcpu)); vcpu_write_sys_reg(vcpu, esr, exception_esr_elx(vcpu)); diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index 86f3d80daf37..7cc964af8d30 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -904,38 +904,6 @@ static int kvm_init_ipa_range(struct kvm_s2_mmu *mmu, unsigned long type) return 0; } -/* - * Assume that @pgt is valid and unlinked from the KVM MMU to free the - * page-table without taking the kvm_mmu_lock and without performing any - * TLB invalidations. - * - * Also, the range of addresses can be large enough to cause need_resched - * warnings, for instance on CONFIG_PREEMPT_NONE kernels. Hence, invoke - * cond_resched() periodically to prevent hogging the CPU for a long time - * and schedule something else, if required. - */ -static void stage2_destroy_range(struct kvm_pgtable *pgt, phys_addr_t addr, - phys_addr_t end) -{ - u64 next; - - do { - next = stage2_range_addr_end(addr, end); - KVM_PGT_FN(kvm_pgtable_stage2_destroy_range)(pgt, addr, - next - addr); - if (next != end) - cond_resched(); - } while (addr = next, addr != end); -} - -static void kvm_stage2_destroy(struct kvm_pgtable *pgt) -{ - unsigned int ia_bits = VTCR_EL2_IPA(pgt->mmu->vtcr); - - stage2_destroy_range(pgt, 0, BIT(ia_bits)); - KVM_PGT_FN(kvm_pgtable_stage2_destroy_pgd)(pgt); -} - /** * kvm_init_stage2_mmu - Initialise a S2 MMU structure * @kvm: The pointer to the KVM structure @@ -1012,7 +980,7 @@ int kvm_init_stage2_mmu(struct kvm *kvm, struct kvm_s2_mmu *mmu, unsigned long t return 0; out_destroy_pgtable: - kvm_stage2_destroy(pgt); + KVM_PGT_FN(kvm_pgtable_stage2_destroy)(pgt); out_free_pgtable: kfree(pgt); return err; @@ -1106,10 +1074,14 @@ void kvm_free_stage2_pgd(struct kvm_s2_mmu *mmu) mmu->pgt = NULL; free_percpu(mmu->last_vcpu_ran); } + + if (kvm_is_nested_s2_mmu(kvm, mmu)) + kvm_init_nested_s2_mmu(mmu); + write_unlock(&kvm->mmu_lock); if (pgt) { - kvm_stage2_destroy(pgt); + KVM_PGT_FN(kvm_pgtable_stage2_destroy)(pgt); kfree(pgt); } } @@ -1459,11 +1431,8 @@ static int get_vma_page_shift(struct vm_area_struct *vma, unsigned long hva) * able to see the page's tags and therefore they must be initialised first. If * PG_mte_tagged is set, tags have already been initialised. * - * The race in the test/set of the PG_mte_tagged flag is handled by: - * - preventing VM_SHARED mappings in a memslot with MTE preventing two VMs - * racing to santise the same page - * - mmap_lock protects between a VM faulting a page in and the VMM performing - * an mprotect() to add VM_MTE + * Must be called with kvm->mmu_lock held to ensure the memory remains mapped + * while the tags are zeroed. */ static void sanitise_mte_tags(struct kvm *kvm, kvm_pfn_t pfn, unsigned long size) @@ -1510,13 +1479,132 @@ static bool kvm_vma_is_cacheable(struct vm_area_struct *vma) } } +static int prepare_mmu_memcache(struct kvm_vcpu *vcpu, bool topup_memcache, + void **memcache) +{ + int min_pages; + + if (!is_protected_kvm_enabled()) + *memcache = &vcpu->arch.mmu_page_cache; + else + *memcache = &vcpu->arch.pkvm_memcache; + + if (!topup_memcache) + return 0; + + min_pages = kvm_mmu_cache_min_pages(vcpu->arch.hw_mmu); + + if (!is_protected_kvm_enabled()) + return kvm_mmu_topup_memory_cache(*memcache, min_pages); + + return topup_hyp_memcache(*memcache, min_pages); +} + +/* + * Potentially reduce shadow S2 permissions to match the guest's own S2. For + * exec faults, we'd only reach this point if the guest actually allowed it (see + * kvm_s2_handle_perm_fault). + * + * Also encode the level of the original translation in the SW bits of the leaf + * entry as a proxy for the span of that translation. This will be retrieved on + * TLB invalidation from the guest and used to limit the invalidation scope if a + * TTL hint or a range isn't provided. + */ +static void adjust_nested_fault_perms(struct kvm_s2_trans *nested, + enum kvm_pgtable_prot *prot, + bool *writable) +{ + *writable &= kvm_s2_trans_writable(nested); + if (!kvm_s2_trans_readable(nested)) + *prot &= ~KVM_PGTABLE_PROT_R; + + *prot |= kvm_encode_nested_level(nested); +} + +#define KVM_PGTABLE_WALK_MEMABORT_FLAGS (KVM_PGTABLE_WALK_HANDLE_FAULT | KVM_PGTABLE_WALK_SHARED) + +static int gmem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, + struct kvm_s2_trans *nested, + struct kvm_memory_slot *memslot, bool is_perm) +{ + bool write_fault, exec_fault, writable; + enum kvm_pgtable_walk_flags flags = KVM_PGTABLE_WALK_MEMABORT_FLAGS; + enum kvm_pgtable_prot prot = KVM_PGTABLE_PROT_R; + struct kvm_pgtable *pgt = vcpu->arch.hw_mmu->pgt; + unsigned long mmu_seq; + struct page *page; + struct kvm *kvm = vcpu->kvm; + void *memcache; + kvm_pfn_t pfn; + gfn_t gfn; + int ret; + + ret = prepare_mmu_memcache(vcpu, true, &memcache); + if (ret) + return ret; + + if (nested) + gfn = kvm_s2_trans_output(nested) >> PAGE_SHIFT; + else + gfn = fault_ipa >> PAGE_SHIFT; + + write_fault = kvm_is_write_fault(vcpu); + exec_fault = kvm_vcpu_trap_is_exec_fault(vcpu); + + VM_WARN_ON_ONCE(write_fault && exec_fault); + + mmu_seq = kvm->mmu_invalidate_seq; + /* Pairs with the smp_wmb() in kvm_mmu_invalidate_end(). */ + smp_rmb(); + + ret = kvm_gmem_get_pfn(kvm, memslot, gfn, &pfn, &page, NULL); + if (ret) { + kvm_prepare_memory_fault_exit(vcpu, fault_ipa, PAGE_SIZE, + write_fault, exec_fault, false); + return ret; + } + + writable = !(memslot->flags & KVM_MEM_READONLY); + + if (nested) + adjust_nested_fault_perms(nested, &prot, &writable); + + if (writable) + prot |= KVM_PGTABLE_PROT_W; + + if (exec_fault || + (cpus_have_final_cap(ARM64_HAS_CACHE_DIC) && + (!nested || kvm_s2_trans_executable(nested)))) + prot |= KVM_PGTABLE_PROT_X; + + kvm_fault_lock(kvm); + if (mmu_invalidate_retry(kvm, mmu_seq)) { + ret = -EAGAIN; + goto out_unlock; + } + + ret = KVM_PGT_FN(kvm_pgtable_stage2_map)(pgt, fault_ipa, PAGE_SIZE, + __pfn_to_phys(pfn), prot, + memcache, flags); + +out_unlock: + kvm_release_faultin_page(kvm, page, !!ret, writable); + kvm_fault_unlock(kvm); + + if (writable && !ret) + mark_page_dirty_in_slot(kvm, memslot, gfn); + + return ret != -EAGAIN ? ret : 0; +} + static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, struct kvm_s2_trans *nested, struct kvm_memory_slot *memslot, unsigned long hva, bool fault_is_perm) { int ret = 0; - bool write_fault, writable, force_pte = false; + bool topup_memcache; + bool write_fault, writable; bool exec_fault, mte_allowed, is_vma_cacheable; bool s2_force_noncacheable = false, vfio_allow_any_uc = false; unsigned long mmu_seq; @@ -1528,28 +1616,19 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, gfn_t gfn; kvm_pfn_t pfn; bool logging_active = memslot_is_logging(memslot); + bool force_pte = logging_active; long vma_pagesize, fault_granule; enum kvm_pgtable_prot prot = KVM_PGTABLE_PROT_R; struct kvm_pgtable *pgt; struct page *page; vm_flags_t vm_flags; - enum kvm_pgtable_walk_flags flags = KVM_PGTABLE_WALK_HANDLE_FAULT | KVM_PGTABLE_WALK_SHARED; + enum kvm_pgtable_walk_flags flags = KVM_PGTABLE_WALK_MEMABORT_FLAGS; if (fault_is_perm) fault_granule = kvm_vcpu_trap_get_perm_fault_granule(vcpu); write_fault = kvm_is_write_fault(vcpu); exec_fault = kvm_vcpu_trap_is_exec_fault(vcpu); - VM_BUG_ON(write_fault && exec_fault); - - if (fault_is_perm && !write_fault && !exec_fault) { - kvm_err("Unexpected L2 read permission error\n"); - return -EFAULT; - } - - if (!is_protected_kvm_enabled()) - memcache = &vcpu->arch.mmu_page_cache; - else - memcache = &vcpu->arch.pkvm_memcache; + VM_WARN_ON_ONCE(write_fault && exec_fault); /* * Permission faults just need to update the existing leaf entry, @@ -1557,17 +1636,10 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, * only exception to this is when dirty logging is enabled at runtime * and a write fault needs to collapse a block entry into a table. */ - if (!fault_is_perm || (logging_active && write_fault)) { - int min_pages = kvm_mmu_cache_min_pages(vcpu->arch.hw_mmu); - - if (!is_protected_kvm_enabled()) - ret = kvm_mmu_topup_memory_cache(memcache, min_pages); - else - ret = topup_hyp_memcache(memcache, min_pages); - - if (ret) - return ret; - } + topup_memcache = !fault_is_perm || (logging_active && write_fault); + ret = prepare_mmu_memcache(vcpu, topup_memcache, &memcache); + if (ret) + return ret; /* * Let's check if we will get back a huge page backed by hugetlbfs, or @@ -1581,16 +1653,10 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, return -EFAULT; } - /* - * logging_active is guaranteed to never be true for VM_PFNMAP - * memslots. - */ - if (logging_active) { - force_pte = true; + if (force_pte) vma_shift = PAGE_SHIFT; - } else { + else vma_shift = get_vma_page_shift(vma, hva); - } switch (vma_shift) { #ifndef __PAGETABLE_PMD_FOLDED @@ -1642,7 +1708,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, max_map_size = PAGE_SIZE; force_pte = (max_map_size == PAGE_SIZE); - vma_pagesize = min(vma_pagesize, (long)max_map_size); + vma_pagesize = min_t(long, vma_pagesize, max_map_size); } /* @@ -1675,7 +1741,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, * Rely on mmap_read_unlock() for an implicit smp_rmb(), which pairs * with the smp_wmb() in kvm_mmu_invalidate_end(). */ - mmu_seq = vcpu->kvm->mmu_invalidate_seq; + mmu_seq = kvm->mmu_invalidate_seq; mmap_read_unlock(current->mm); pfn = __kvm_faultin_pfn(memslot, gfn, write_fault ? FOLL_WRITE : 0, @@ -1706,7 +1772,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, * cache maintenance. */ if (!kvm_supports_cacheable_pfnmap()) - return -EFAULT; + ret = -EFAULT; } else { /* * If the page was identified as device early by looking at @@ -1729,27 +1795,16 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, } if (exec_fault && s2_force_noncacheable) - return -ENOEXEC; - - /* - * Potentially reduce shadow S2 permissions to match the guest's own - * S2. For exec faults, we'd only reach this point if the guest - * actually allowed it (see kvm_s2_handle_perm_fault). - * - * Also encode the level of the original translation in the SW bits - * of the leaf entry as a proxy for the span of that translation. - * This will be retrieved on TLB invalidation from the guest and - * used to limit the invalidation scope if a TTL hint or a range - * isn't provided. - */ - if (nested) { - writable &= kvm_s2_trans_writable(nested); - if (!kvm_s2_trans_readable(nested)) - prot &= ~KVM_PGTABLE_PROT_R; + ret = -ENOEXEC; - prot |= kvm_encode_nested_level(nested); + if (ret) { + kvm_release_page_unused(page); + return ret; } + if (nested) + adjust_nested_fault_perms(nested, &prot, &writable); + kvm_fault_lock(kvm); pgt = vcpu->arch.hw_mmu->pgt; if (mmu_invalidate_retry(kvm, mmu_seq)) { @@ -2018,8 +2073,15 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu) goto out_unlock; } - ret = user_mem_abort(vcpu, fault_ipa, nested, memslot, hva, - esr_fsc_is_permission_fault(esr)); + VM_WARN_ON_ONCE(kvm_vcpu_trap_is_permission_fault(vcpu) && + !write_fault && !kvm_vcpu_trap_is_exec_fault(vcpu)); + + if (kvm_slot_has_gmem(memslot)) + ret = gmem_abort(vcpu, fault_ipa, nested, memslot, + esr_fsc_is_permission_fault(esr)); + else + ret = user_mem_abort(vcpu, fault_ipa, nested, memslot, hva, + esr_fsc_is_permission_fault(esr)); if (ret == 0) ret = 1; out: @@ -2251,6 +2313,13 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm, if ((new->base_gfn + new->npages) > (kvm_phys_size(&kvm->arch.mmu) >> PAGE_SHIFT)) return -EFAULT; + /* + * Only support guest_memfd backed memslots with mappable memory, since + * there aren't any CoCo VMs that support only private memory on arm64. + */ + if (kvm_slot_has_gmem(new) && !kvm_memslot_is_gmem_only(new)) + return -EINVAL; + hva = new->userspace_addr; reg_end = hva + (new->npages << PAGE_SHIFT); diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c index 77db81bae86f..7a045cad6bdf 100644 --- a/arch/arm64/kvm/nested.c +++ b/arch/arm64/kvm/nested.c @@ -349,7 +349,7 @@ static void vtcr_to_walk_info(u64 vtcr, struct s2_walk_info *wi) wi->sl = FIELD_GET(VTCR_EL2_SL0_MASK, vtcr); /* Global limit for now, should eventually be per-VM */ wi->max_oa_bits = min(get_kvm_ipa_limit(), - ps_to_output_size(FIELD_GET(VTCR_EL2_PS_MASK, vtcr))); + ps_to_output_size(FIELD_GET(VTCR_EL2_PS_MASK, vtcr), false)); } int kvm_walk_nested_s2(struct kvm_vcpu *vcpu, phys_addr_t gipa, @@ -847,7 +847,7 @@ static void kvm_invalidate_vncr_ipa(struct kvm *kvm, u64 start, u64 end) ipa_size = ttl_to_size(pgshift_level_to_ttl(vt->wi.pgshift, vt->wr.level)); - ipa_start = vt->wr.pa & (ipa_size - 1); + ipa_start = vt->wr.pa & ~(ipa_size - 1); ipa_end = ipa_start + ipa_size; if (ipa_end <= start || ipa_start >= end) @@ -887,7 +887,7 @@ static void invalidate_vncr_va(struct kvm *kvm, va_size = ttl_to_size(pgshift_level_to_ttl(vt->wi.pgshift, vt->wr.level)); - va_start = vt->gva & (va_size - 1); + va_start = vt->gva & ~(va_size - 1); va_end = va_start + va_size; switch (scope->type) { @@ -1172,8 +1172,9 @@ static u64 read_vncr_el2(struct kvm_vcpu *vcpu) return (u64)sign_extend64(__vcpu_sys_reg(vcpu, VNCR_EL2), 48); } -static int kvm_translate_vncr(struct kvm_vcpu *vcpu) +static int kvm_translate_vncr(struct kvm_vcpu *vcpu, bool *is_gmem) { + struct kvm_memory_slot *memslot; bool write_fault, writable; unsigned long mmu_seq; struct vncr_tlb *vt; @@ -1216,10 +1217,25 @@ static int kvm_translate_vncr(struct kvm_vcpu *vcpu) smp_rmb(); gfn = vt->wr.pa >> PAGE_SHIFT; - pfn = kvm_faultin_pfn(vcpu, gfn, write_fault, &writable, &page); - if (is_error_noslot_pfn(pfn) || (write_fault && !writable)) + memslot = gfn_to_memslot(vcpu->kvm, gfn); + if (!memslot) return -EFAULT; + *is_gmem = kvm_slot_has_gmem(memslot); + if (!*is_gmem) { + pfn = __kvm_faultin_pfn(memslot, gfn, write_fault ? FOLL_WRITE : 0, + &writable, &page); + if (is_error_noslot_pfn(pfn) || (write_fault && !writable)) + return -EFAULT; + } else { + ret = kvm_gmem_get_pfn(vcpu->kvm, memslot, gfn, &pfn, &page, NULL); + if (ret) { + kvm_prepare_memory_fault_exit(vcpu, vt->wr.pa, PAGE_SIZE, + write_fault, false, false); + return ret; + } + } + scoped_guard(write_lock, &vcpu->kvm->mmu_lock) { if (mmu_invalidate_retry(vcpu->kvm, mmu_seq)) return -EAGAIN; @@ -1276,7 +1292,7 @@ static bool kvm_vncr_tlb_lookup(struct kvm_vcpu *vcpu) !(tcr & TCR_ASID16)) asid &= GENMASK(7, 0); - return asid != vt->wr.asid; + return asid == vt->wr.asid; } return true; @@ -1295,23 +1311,36 @@ int kvm_handle_vncr_abort(struct kvm_vcpu *vcpu) if (esr_fsc_is_permission_fault(esr)) { inject_vncr_perm(vcpu); } else if (esr_fsc_is_translation_fault(esr)) { - bool valid; + bool valid, is_gmem = false; int ret; scoped_guard(read_lock, &vcpu->kvm->mmu_lock) valid = kvm_vncr_tlb_lookup(vcpu); if (!valid) - ret = kvm_translate_vncr(vcpu); + ret = kvm_translate_vncr(vcpu, &is_gmem); else ret = -EPERM; switch (ret) { case -EAGAIN: - case -ENOMEM: /* Let's try again... */ break; + case -ENOMEM: + /* + * For guest_memfd, this indicates that it failed to + * create a folio to back the memory. Inform userspace. + */ + if (is_gmem) + return 0; + /* Otherwise, let's try again... */ + break; case -EFAULT: + case -EIO: + case -EHWPOISON: + if (is_gmem) + return 0; + fallthrough; case -EINVAL: case -ENOENT: case -EACCES: @@ -1462,9 +1491,16 @@ u64 limit_nv_id_reg(struct kvm *kvm, u32 reg, u64 val) case SYS_ID_AA64PFR1_EL1: /* Only support BTI, SSBS, CSV2_frac */ - val &= (ID_AA64PFR1_EL1_BT | - ID_AA64PFR1_EL1_SSBS | - ID_AA64PFR1_EL1_CSV2_frac); + val &= ~(ID_AA64PFR1_EL1_PFAR | + ID_AA64PFR1_EL1_MTEX | + ID_AA64PFR1_EL1_THE | + ID_AA64PFR1_EL1_GCS | + ID_AA64PFR1_EL1_MTE_frac | + ID_AA64PFR1_EL1_NMI | + ID_AA64PFR1_EL1_SME | + ID_AA64PFR1_EL1_RES0 | + ID_AA64PFR1_EL1_MPAM_frac | + ID_AA64PFR1_EL1_MTE); break; case SYS_ID_AA64MMFR0_EL1: @@ -1517,12 +1553,11 @@ u64 limit_nv_id_reg(struct kvm *kvm, u32 reg, u64 val) break; case SYS_ID_AA64MMFR1_EL1: - val &= (ID_AA64MMFR1_EL1_HCX | - ID_AA64MMFR1_EL1_PAN | - ID_AA64MMFR1_EL1_LO | - ID_AA64MMFR1_EL1_HPDS | - ID_AA64MMFR1_EL1_VH | - ID_AA64MMFR1_EL1_VMIDBits); + val &= ~(ID_AA64MMFR1_EL1_CMOW | + ID_AA64MMFR1_EL1_nTLBPA | + ID_AA64MMFR1_EL1_ETS | + ID_AA64MMFR1_EL1_XNX | + ID_AA64MMFR1_EL1_HAFDBS); /* FEAT_E2H0 implies no VHE */ if (test_bit(KVM_ARM_VCPU_HAS_EL2_E2H0, kvm->arch.vcpu_features)) val &= ~ID_AA64MMFR1_EL1_VH; @@ -1564,14 +1599,22 @@ u64 limit_nv_id_reg(struct kvm *kvm, u32 reg, u64 val) case SYS_ID_AA64DFR0_EL1: /* Only limited support for PMU, Debug, BPs, WPs, and HPMN0 */ - val &= (ID_AA64DFR0_EL1_PMUVer | - ID_AA64DFR0_EL1_WRPs | - ID_AA64DFR0_EL1_BRPs | - ID_AA64DFR0_EL1_DebugVer| - ID_AA64DFR0_EL1_HPMN0); - - /* Cap Debug to ARMv8.1 */ - val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64DFR0_EL1, DebugVer, VHE); + val &= ~(ID_AA64DFR0_EL1_ExtTrcBuff | + ID_AA64DFR0_EL1_BRBE | + ID_AA64DFR0_EL1_MTPMU | + ID_AA64DFR0_EL1_TraceBuffer | + ID_AA64DFR0_EL1_TraceFilt | + ID_AA64DFR0_EL1_PMSVer | + ID_AA64DFR0_EL1_CTX_CMPs | + ID_AA64DFR0_EL1_SEBEP | + ID_AA64DFR0_EL1_PMSS | + ID_AA64DFR0_EL1_TraceVer); + + /* + * FEAT_Debugv8p9 requires support for extended breakpoints / + * watchpoints. + */ + val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64DFR0_EL1, DebugVer, V8P8); break; } @@ -1796,3 +1839,33 @@ void kvm_nested_sync_hwstate(struct kvm_vcpu *vcpu) if (unlikely(vcpu_test_and_clear_flag(vcpu, NESTED_SERROR_PENDING))) kvm_inject_serror_esr(vcpu, vcpu_get_vsesr(vcpu)); } + +/* + * KVM unconditionally sets most of these traps anyway but use an allowlist + * to document the guest hypervisor traps that may take precedence and guard + * against future changes to the non-nested trap configuration. + */ +#define NV_MDCR_GUEST_INCLUDE (MDCR_EL2_TDE | \ + MDCR_EL2_TDA | \ + MDCR_EL2_TDRA | \ + MDCR_EL2_TTRF | \ + MDCR_EL2_TPMS | \ + MDCR_EL2_TPM | \ + MDCR_EL2_TPMCR | \ + MDCR_EL2_TDCC | \ + MDCR_EL2_TDOSA) + +void kvm_nested_setup_mdcr_el2(struct kvm_vcpu *vcpu) +{ + u64 guest_mdcr = __vcpu_sys_reg(vcpu, MDCR_EL2); + + /* + * In yet another example where FEAT_NV2 is fscking broken, accesses + * to MDSCR_EL1 are redirected to the VNCR despite having an effect + * at EL2. Use a big hammer to apply sanity. + */ + if (is_hyp_ctxt(vcpu)) + vcpu->arch.mdcr_el2 |= MDCR_EL2_TDA; + else + vcpu->arch.mdcr_el2 |= (guest_mdcr & NV_MDCR_GUEST_INCLUDE); +} diff --git a/arch/arm64/kvm/pkvm.c b/arch/arm64/kvm/pkvm.c index 61827cf6fea4..24f0f8a8c943 100644 --- a/arch/arm64/kvm/pkvm.c +++ b/arch/arm64/kvm/pkvm.c @@ -85,16 +85,23 @@ void __init kvm_hyp_reserve(void) hyp_mem_base); } -static void __pkvm_destroy_hyp_vm(struct kvm *host_kvm) +static void __pkvm_destroy_hyp_vm(struct kvm *kvm) { - if (host_kvm->arch.pkvm.handle) { + if (pkvm_hyp_vm_is_created(kvm)) { WARN_ON(kvm_call_hyp_nvhe(__pkvm_teardown_vm, - host_kvm->arch.pkvm.handle)); + kvm->arch.pkvm.handle)); + } else if (kvm->arch.pkvm.handle) { + /* + * The VM could have been reserved but hyp initialization has + * failed. Make sure to unreserve it. + */ + kvm_call_hyp_nvhe(__pkvm_unreserve_vm, kvm->arch.pkvm.handle); } - host_kvm->arch.pkvm.handle = 0; - free_hyp_memcache(&host_kvm->arch.pkvm.teardown_mc); - free_hyp_memcache(&host_kvm->arch.pkvm.stage2_teardown_mc); + kvm->arch.pkvm.handle = 0; + kvm->arch.pkvm.is_created = false; + free_hyp_memcache(&kvm->arch.pkvm.teardown_mc); + free_hyp_memcache(&kvm->arch.pkvm.stage2_teardown_mc); } static int __pkvm_create_hyp_vcpu(struct kvm_vcpu *vcpu) @@ -129,16 +136,16 @@ static int __pkvm_create_hyp_vcpu(struct kvm_vcpu *vcpu) * * Return 0 on success, negative error code on failure. */ -static int __pkvm_create_hyp_vm(struct kvm *host_kvm) +static int __pkvm_create_hyp_vm(struct kvm *kvm) { size_t pgd_sz, hyp_vm_sz; void *pgd, *hyp_vm; int ret; - if (host_kvm->created_vcpus < 1) + if (kvm->created_vcpus < 1) return -EINVAL; - pgd_sz = kvm_pgtable_stage2_pgd_size(host_kvm->arch.mmu.vtcr); + pgd_sz = kvm_pgtable_stage2_pgd_size(kvm->arch.mmu.vtcr); /* * The PGD pages will be reclaimed using a hyp_memcache which implies @@ -152,7 +159,7 @@ static int __pkvm_create_hyp_vm(struct kvm *host_kvm) /* Allocate memory to donate to hyp for vm and vcpu pointers. */ hyp_vm_sz = PAGE_ALIGN(size_add(PKVM_HYP_VM_SIZE, size_mul(sizeof(void *), - host_kvm->created_vcpus))); + kvm->created_vcpus))); hyp_vm = alloc_pages_exact(hyp_vm_sz, GFP_KERNEL_ACCOUNT); if (!hyp_vm) { ret = -ENOMEM; @@ -160,12 +167,12 @@ static int __pkvm_create_hyp_vm(struct kvm *host_kvm) } /* Donate the VM memory to hyp and let hyp initialize it. */ - ret = kvm_call_hyp_nvhe(__pkvm_init_vm, host_kvm, hyp_vm, pgd); - if (ret < 0) + ret = kvm_call_hyp_nvhe(__pkvm_init_vm, kvm, hyp_vm, pgd); + if (ret) goto free_vm; - host_kvm->arch.pkvm.handle = ret; - host_kvm->arch.pkvm.stage2_teardown_mc.flags |= HYP_MEMCACHE_ACCOUNT_STAGE2; + kvm->arch.pkvm.is_created = true; + kvm->arch.pkvm.stage2_teardown_mc.flags |= HYP_MEMCACHE_ACCOUNT_STAGE2; kvm_account_pgtable_pages(pgd, pgd_sz / PAGE_SIZE); return 0; @@ -176,14 +183,19 @@ free_pgd: return ret; } -int pkvm_create_hyp_vm(struct kvm *host_kvm) +bool pkvm_hyp_vm_is_created(struct kvm *kvm) +{ + return READ_ONCE(kvm->arch.pkvm.is_created); +} + +int pkvm_create_hyp_vm(struct kvm *kvm) { int ret = 0; - mutex_lock(&host_kvm->arch.config_lock); - if (!host_kvm->arch.pkvm.handle) - ret = __pkvm_create_hyp_vm(host_kvm); - mutex_unlock(&host_kvm->arch.config_lock); + mutex_lock(&kvm->arch.config_lock); + if (!pkvm_hyp_vm_is_created(kvm)) + ret = __pkvm_create_hyp_vm(kvm); + mutex_unlock(&kvm->arch.config_lock); return ret; } @@ -200,15 +212,31 @@ int pkvm_create_hyp_vcpu(struct kvm_vcpu *vcpu) return ret; } -void pkvm_destroy_hyp_vm(struct kvm *host_kvm) +void pkvm_destroy_hyp_vm(struct kvm *kvm) { - mutex_lock(&host_kvm->arch.config_lock); - __pkvm_destroy_hyp_vm(host_kvm); - mutex_unlock(&host_kvm->arch.config_lock); + mutex_lock(&kvm->arch.config_lock); + __pkvm_destroy_hyp_vm(kvm); + mutex_unlock(&kvm->arch.config_lock); } -int pkvm_init_host_vm(struct kvm *host_kvm) +int pkvm_init_host_vm(struct kvm *kvm) { + int ret; + + if (pkvm_hyp_vm_is_created(kvm)) + return -EINVAL; + + /* VM is already reserved, no need to proceed. */ + if (kvm->arch.pkvm.handle) + return 0; + + /* Reserve the VM in hyp and obtain a hyp handle for the VM. */ + ret = kvm_call_hyp_nvhe(__pkvm_reserve_vm); + if (ret < 0) + return ret; + + kvm->arch.pkvm.handle = ret; + return 0; } @@ -316,16 +344,9 @@ static int __pkvm_pgtable_stage2_unmap(struct kvm_pgtable *pgt, u64 start, u64 e return 0; } -void pkvm_pgtable_stage2_destroy_range(struct kvm_pgtable *pgt, - u64 addr, u64 size) -{ - __pkvm_pgtable_stage2_unmap(pgt, addr, addr + size); -} - -void pkvm_pgtable_stage2_destroy_pgd(struct kvm_pgtable *pgt) +void pkvm_pgtable_stage2_destroy(struct kvm_pgtable *pgt) { - /* Expected to be called after all pKVM mappings have been released. */ - WARN_ON_ONCE(!RB_EMPTY_ROOT(&pgt->pkvm_mappings.rb_root)); + __pkvm_pgtable_stage2_unmap(pgt, 0, ~(0ULL)); } int pkvm_pgtable_stage2_map(struct kvm_pgtable *pgt, u64 addr, u64 size, diff --git a/arch/arm64/kvm/ptdump.c b/arch/arm64/kvm/ptdump.c index 098416d7e5c2..dc5acfb00af9 100644 --- a/arch/arm64/kvm/ptdump.c +++ b/arch/arm64/kvm/ptdump.c @@ -32,23 +32,23 @@ static const struct ptdump_prot_bits stage2_pte_bits[] = { .set = " ", .clear = "F", }, { - .mask = KVM_PTE_LEAF_ATTR_LO_S2_S2AP_R | PTE_VALID, - .val = KVM_PTE_LEAF_ATTR_LO_S2_S2AP_R | PTE_VALID, + .mask = KVM_PTE_LEAF_ATTR_LO_S2_S2AP_R, + .val = KVM_PTE_LEAF_ATTR_LO_S2_S2AP_R, .set = "R", .clear = " ", }, { - .mask = KVM_PTE_LEAF_ATTR_LO_S2_S2AP_W | PTE_VALID, - .val = KVM_PTE_LEAF_ATTR_LO_S2_S2AP_W | PTE_VALID, + .mask = KVM_PTE_LEAF_ATTR_LO_S2_S2AP_W, + .val = KVM_PTE_LEAF_ATTR_LO_S2_S2AP_W, .set = "W", .clear = " ", }, { - .mask = KVM_PTE_LEAF_ATTR_HI_S2_XN | PTE_VALID, - .val = PTE_VALID, - .set = " ", - .clear = "X", + .mask = KVM_PTE_LEAF_ATTR_HI_S2_XN, + .val = KVM_PTE_LEAF_ATTR_HI_S2_XN, + .set = "NX", + .clear = "x ", }, { - .mask = KVM_PTE_LEAF_ATTR_LO_S2_AF | PTE_VALID, - .val = KVM_PTE_LEAF_ATTR_LO_S2_AF | PTE_VALID, + .mask = KVM_PTE_LEAF_ATTR_LO_S2_AF, + .val = KVM_PTE_LEAF_ATTR_LO_S2_AF, .set = "AF", .clear = " ", }, { diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index b29f72478a50..91053aa832d0 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1757,7 +1757,8 @@ static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, val &= ~ID_AA64ISAR2_EL1_WFxT; break; case SYS_ID_AA64ISAR3_EL1: - val &= ID_AA64ISAR3_EL1_FPRCVT | ID_AA64ISAR3_EL1_FAMINMAX; + val &= ID_AA64ISAR3_EL1_FPRCVT | ID_AA64ISAR3_EL1_LSFE | + ID_AA64ISAR3_EL1_FAMINMAX; break; case SYS_ID_AA64MMFR2_EL1: val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; @@ -1997,6 +1998,26 @@ static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val) return val; } +/* + * Older versions of KVM erroneously claim support for FEAT_DoubleLock with + * NV-enabled VMs on unsupporting hardware. Silently ignore the incorrect + * value if it is consistent with the bug. + */ +static bool ignore_feat_doublelock(struct kvm_vcpu *vcpu, u64 val) +{ + u8 host, user; + + if (!vcpu_has_nv(vcpu)) + return false; + + host = SYS_FIELD_GET(ID_AA64DFR0_EL1, DoubleLock, + read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1)); + user = SYS_FIELD_GET(ID_AA64DFR0_EL1, DoubleLock, val); + + return host == ID_AA64DFR0_EL1_DoubleLock_NI && + user == ID_AA64DFR0_EL1_DoubleLock_IMP; +} + static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, u64 val) @@ -2028,6 +2049,11 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, if (debugver < ID_AA64DFR0_EL1_DebugVer_IMP) return -EINVAL; + if (ignore_feat_doublelock(vcpu, val)) { + val &= ~ID_AA64DFR0_EL1_DoubleLock; + val |= SYS_FIELD_PREP_ENUM(ID_AA64DFR0_EL1, DoubleLock, NI); + } + return set_id_reg(vcpu, rd, val); } @@ -2148,16 +2174,29 @@ static int set_id_aa64pfr1_el1(struct kvm_vcpu *vcpu, return set_id_reg(vcpu, rd, user_val); } +/* + * Allow userspace to de-feature a stage-2 translation granule but prevent it + * from claiming the impossible. + */ +#define tgran2_val_allowed(tg, safe, user) \ +({ \ + u8 __s = SYS_FIELD_GET(ID_AA64MMFR0_EL1, tg, safe); \ + u8 __u = SYS_FIELD_GET(ID_AA64MMFR0_EL1, tg, user); \ + \ + __s == __u || __u == ID_AA64MMFR0_EL1_##tg##_NI; \ +}) + static int set_id_aa64mmfr0_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, u64 user_val) { u64 sanitized_val = kvm_read_sanitised_id_reg(vcpu, rd); - u64 tgran2_mask = ID_AA64MMFR0_EL1_TGRAN4_2_MASK | - ID_AA64MMFR0_EL1_TGRAN16_2_MASK | - ID_AA64MMFR0_EL1_TGRAN64_2_MASK; - if (vcpu_has_nv(vcpu) && - ((sanitized_val & tgran2_mask) != (user_val & tgran2_mask))) + if (!vcpu_has_nv(vcpu)) + return set_id_reg(vcpu, rd, user_val); + + if (!tgran2_val_allowed(TGRAN4_2, sanitized_val, user_val) || + !tgran2_val_allowed(TGRAN16_2, sanitized_val, user_val) || + !tgran2_val_allowed(TGRAN64_2, sanitized_val, user_val)) return -EINVAL; return set_id_reg(vcpu, rd, user_val); @@ -3141,6 +3180,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_AA64ISAR2_EL1_APA3 | ID_AA64ISAR2_EL1_GPA3)), ID_WRITABLE(ID_AA64ISAR3_EL1, (ID_AA64ISAR3_EL1_FPRCVT | + ID_AA64ISAR3_EL1_LSFE | ID_AA64ISAR3_EL1_FAMINMAX)), ID_UNALLOCATED(6,4), ID_UNALLOCATED(6,5), @@ -3152,8 +3192,6 @@ static const struct sys_reg_desc sys_reg_descs[] = { ~(ID_AA64MMFR0_EL1_RES0 | ID_AA64MMFR0_EL1_ASIDBITS)), ID_WRITABLE(ID_AA64MMFR1_EL1, ~(ID_AA64MMFR1_EL1_RES0 | - ID_AA64MMFR1_EL1_HCX | - ID_AA64MMFR1_EL1_TWED | ID_AA64MMFR1_EL1_XNX | ID_AA64MMFR1_EL1_VH | ID_AA64MMFR1_EL1_VMIDBits)), @@ -3238,6 +3276,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access }, { SYS_DESC(SYS_PMBPTR_EL1), undef_access }, { SYS_DESC(SYS_PMBSR_EL1), undef_access }, + { SYS_DESC(SYS_PMSDSFR_EL1), undef_access }, /* PMBIDR_EL1 is not trapped */ { PMU_SYS_REG(PMINTENSET_EL1), diff --git a/arch/arm64/kvm/vgic/vgic-debug.c b/arch/arm64/kvm/vgic/vgic-debug.c index 2684f273d9e1..4c1209261b65 100644 --- a/arch/arm64/kvm/vgic/vgic-debug.c +++ b/arch/arm64/kvm/vgic/vgic-debug.c @@ -69,7 +69,7 @@ static int iter_mark_lpis(struct kvm *kvm) int nr_lpis = 0; xa_for_each(&dist->lpi_xa, intid, irq) { - if (!vgic_try_get_irq_kref(irq)) + if (!vgic_try_get_irq_ref(irq)) continue; xa_set_mark(&dist->lpi_xa, intid, LPI_XA_MARK_DEBUG_ITER); diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-init.c index 1e680ad6e863..1796b1a22a72 100644 --- a/arch/arm64/kvm/vgic/vgic-init.c +++ b/arch/arm64/kvm/vgic/vgic-init.c @@ -53,7 +53,7 @@ void kvm_vgic_early_init(struct kvm *kvm) { struct vgic_dist *dist = &kvm->arch.vgic; - xa_init_flags(&dist->lpi_xa, XA_FLAGS_LOCK_IRQ); + xa_init(&dist->lpi_xa); } /* CREATION */ @@ -208,7 +208,7 @@ static int kvm_vgic_dist_init(struct kvm *kvm, unsigned int nr_spis) raw_spin_lock_init(&irq->irq_lock); irq->vcpu = NULL; irq->target_vcpu = vcpu0; - kref_init(&irq->refcount); + refcount_set(&irq->refcount, 0); switch (dist->vgic_model) { case KVM_DEV_TYPE_ARM_VGIC_V2: irq->targets = 0; @@ -277,7 +277,7 @@ static int vgic_allocate_private_irqs_locked(struct kvm_vcpu *vcpu, u32 type) irq->intid = i; irq->vcpu = NULL; irq->target_vcpu = vcpu; - kref_init(&irq->refcount); + refcount_set(&irq->refcount, 0); if (vgic_irq_is_sgi(i)) { /* SGIs */ irq->enabled = 1; @@ -554,7 +554,6 @@ int vgic_lazy_init(struct kvm *kvm) * Also map the virtual CPU interface into the VM. * v2 calls vgic_init() if not already done. * v3 and derivatives return an error if the VGIC is not initialized. - * vgic_ready() returns true if this function has succeeded. */ int kvm_vgic_map_resources(struct kvm *kvm) { @@ -563,12 +562,12 @@ int kvm_vgic_map_resources(struct kvm *kvm) gpa_t dist_base; int ret = 0; - if (likely(vgic_ready(kvm))) + if (likely(smp_load_acquire(&dist->ready))) return 0; mutex_lock(&kvm->slots_lock); mutex_lock(&kvm->arch.config_lock); - if (vgic_ready(kvm)) + if (dist->ready) goto out; if (!irqchip_in_kernel(kvm)) @@ -594,14 +593,7 @@ int kvm_vgic_map_resources(struct kvm *kvm) goto out_slots; } - /* - * kvm_io_bus_register_dev() guarantees all readers see the new MMIO - * registration before returning through synchronize_srcu(), which also - * implies a full memory barrier. As such, marking the distributor as - * 'ready' here is guaranteed to be ordered after all vCPUs having seen - * a completely configured distributor. - */ - dist->ready = true; + smp_store_release(&dist->ready, true); goto out_slots; out: mutex_unlock(&kvm->arch.config_lock); diff --git a/arch/arm64/kvm/vgic/vgic-its.c b/arch/arm64/kvm/vgic/vgic-its.c index 7368c13f16b7..ce3e3ed3f29f 100644 --- a/arch/arm64/kvm/vgic/vgic-its.c +++ b/arch/arm64/kvm/vgic/vgic-its.c @@ -78,7 +78,6 @@ static struct vgic_irq *vgic_add_lpi(struct kvm *kvm, u32 intid, { struct vgic_dist *dist = &kvm->arch.vgic; struct vgic_irq *irq = vgic_get_irq(kvm, intid), *oldirq; - unsigned long flags; int ret; /* In this case there is no put, since we keep the reference. */ @@ -89,7 +88,7 @@ static struct vgic_irq *vgic_add_lpi(struct kvm *kvm, u32 intid, if (!irq) return ERR_PTR(-ENOMEM); - ret = xa_reserve_irq(&dist->lpi_xa, intid, GFP_KERNEL_ACCOUNT); + ret = xa_reserve(&dist->lpi_xa, intid, GFP_KERNEL_ACCOUNT); if (ret) { kfree(irq); return ERR_PTR(ret); @@ -99,19 +98,19 @@ static struct vgic_irq *vgic_add_lpi(struct kvm *kvm, u32 intid, raw_spin_lock_init(&irq->irq_lock); irq->config = VGIC_CONFIG_EDGE; - kref_init(&irq->refcount); + refcount_set(&irq->refcount, 1); irq->intid = intid; irq->target_vcpu = vcpu; irq->group = 1; - xa_lock_irqsave(&dist->lpi_xa, flags); + xa_lock(&dist->lpi_xa); /* * There could be a race with another vgic_add_lpi(), so we need to * check that we don't add a second list entry with the same LPI. */ oldirq = xa_load(&dist->lpi_xa, intid); - if (vgic_try_get_irq_kref(oldirq)) { + if (vgic_try_get_irq_ref(oldirq)) { /* Someone was faster with adding this LPI, lets use that. */ kfree(irq); irq = oldirq; @@ -126,7 +125,7 @@ static struct vgic_irq *vgic_add_lpi(struct kvm *kvm, u32 intid, } out_unlock: - xa_unlock_irqrestore(&dist->lpi_xa, flags); + xa_unlock(&dist->lpi_xa); if (ret) return ERR_PTR(ret); @@ -547,7 +546,7 @@ static struct vgic_irq *vgic_its_check_cache(struct kvm *kvm, phys_addr_t db, rcu_read_lock(); irq = xa_load(&its->translation_cache, cache_key); - if (!vgic_try_get_irq_kref(irq)) + if (!vgic_try_get_irq_ref(irq)) irq = NULL; rcu_read_unlock(); @@ -571,7 +570,7 @@ static void vgic_its_cache_translation(struct kvm *kvm, struct vgic_its *its, * its_lock, as the ITE (and the reference it holds) cannot be freed. */ lockdep_assert_held(&its->its_lock); - vgic_get_irq_kref(irq); + vgic_get_irq_ref(irq); old = xa_store(&its->translation_cache, cache_key, irq, GFP_KERNEL_ACCOUNT); diff --git a/arch/arm64/kvm/vgic/vgic-v3.c b/arch/arm64/kvm/vgic/vgic-v3.c index b9ad7c42c5b0..f1c153106c56 100644 --- a/arch/arm64/kvm/vgic/vgic-v3.c +++ b/arch/arm64/kvm/vgic/vgic-v3.c @@ -588,6 +588,7 @@ int vgic_v3_map_resources(struct kvm *kvm) } DEFINE_STATIC_KEY_FALSE(vgic_v3_cpuif_trap); +DEFINE_STATIC_KEY_FALSE(vgic_v3_has_v2_compat); static int __init early_group0_trap_cfg(char *buf) { @@ -697,6 +698,13 @@ int vgic_v3_probe(const struct gic_kvm_info *info) if (kvm_vgic_global_state.vcpu_base == 0) kvm_info("disabling GICv2 emulation\n"); + /* + * Flip the static branch if the HW supports v2, even if we're + * not using it (such as in protected mode). + */ + if (has_v2) + static_branch_enable(&vgic_v3_has_v2_compat); + if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_30115)) { group0_trap = true; group1_trap = true; diff --git a/arch/arm64/kvm/vgic/vgic-v4.c b/arch/arm64/kvm/vgic/vgic-v4.c index 4d9343d2b0b1..548aec9d5a72 100644 --- a/arch/arm64/kvm/vgic/vgic-v4.c +++ b/arch/arm64/kvm/vgic/vgic-v4.c @@ -518,7 +518,7 @@ static struct vgic_irq *__vgic_host_irq_get_vlpi(struct kvm *kvm, int host_irq) if (!irq->hw || irq->host_irq != host_irq) continue; - if (!vgic_try_get_irq_kref(irq)) + if (!vgic_try_get_irq_ref(irq)) return NULL; return irq; diff --git a/arch/arm64/kvm/vgic/vgic-v5.c b/arch/arm64/kvm/vgic/vgic-v5.c index 6bdbb221bcde..2d3811f4e117 100644 --- a/arch/arm64/kvm/vgic/vgic-v5.c +++ b/arch/arm64/kvm/vgic/vgic-v5.c @@ -15,7 +15,7 @@ int vgic_v5_probe(const struct gic_kvm_info *info) u64 ich_vtr_el2; int ret; - if (!info->has_gcie_v3_compat) + if (!cpus_have_final_cap(ARM64_HAS_GICV5_LEGACY)) return -ENODEV; kvm_vgic_global_state.type = VGIC_V5; diff --git a/arch/arm64/kvm/vgic/vgic.c b/arch/arm64/kvm/vgic/vgic.c index f5148b38120a..6dd5a10081e2 100644 --- a/arch/arm64/kvm/vgic/vgic.c +++ b/arch/arm64/kvm/vgic/vgic.c @@ -28,8 +28,8 @@ struct vgic_global kvm_vgic_global_state __ro_after_init = { * kvm->arch.config_lock (mutex) * its->cmd_lock (mutex) * its->its_lock (mutex) - * vgic_cpu->ap_list_lock must be taken with IRQs disabled - * vgic_dist->lpi_xa.xa_lock must be taken with IRQs disabled + * vgic_dist->lpi_xa.xa_lock + * vgic_cpu->ap_list_lock must be taken with IRQs disabled * vgic_irq->irq_lock must be taken with IRQs disabled * * As the ap_list_lock might be taken from the timer interrupt handler, @@ -71,7 +71,7 @@ static struct vgic_irq *vgic_get_lpi(struct kvm *kvm, u32 intid) rcu_read_lock(); irq = xa_load(&dist->lpi_xa, intid); - if (!vgic_try_get_irq_kref(irq)) + if (!vgic_try_get_irq_ref(irq)) irq = NULL; rcu_read_unlock(); @@ -114,37 +114,66 @@ struct vgic_irq *vgic_get_vcpu_irq(struct kvm_vcpu *vcpu, u32 intid) return vgic_get_irq(vcpu->kvm, intid); } -/* - * We can't do anything in here, because we lack the kvm pointer to - * lock and remove the item from the lpi_list. So we keep this function - * empty and use the return value of kref_put() to trigger the freeing. - */ -static void vgic_irq_release(struct kref *ref) +static void vgic_release_lpi_locked(struct vgic_dist *dist, struct vgic_irq *irq) +{ + lockdep_assert_held(&dist->lpi_xa.xa_lock); + __xa_erase(&dist->lpi_xa, irq->intid); + kfree_rcu(irq, rcu); +} + +static __must_check bool __vgic_put_irq(struct kvm *kvm, struct vgic_irq *irq) +{ + if (irq->intid < VGIC_MIN_LPI) + return false; + + return refcount_dec_and_test(&irq->refcount); +} + +static __must_check bool vgic_put_irq_norelease(struct kvm *kvm, struct vgic_irq *irq) { + if (!__vgic_put_irq(kvm, irq)) + return false; + + irq->pending_release = true; + return true; } void vgic_put_irq(struct kvm *kvm, struct vgic_irq *irq) { struct vgic_dist *dist = &kvm->arch.vgic; - unsigned long flags; - if (irq->intid < VGIC_MIN_LPI) - return; + if (irq->intid >= VGIC_MIN_LPI) + might_lock(&dist->lpi_xa.xa_lock); - if (!kref_put(&irq->refcount, vgic_irq_release)) + if (!__vgic_put_irq(kvm, irq)) return; - xa_lock_irqsave(&dist->lpi_xa, flags); - __xa_erase(&dist->lpi_xa, irq->intid); - xa_unlock_irqrestore(&dist->lpi_xa, flags); + xa_lock(&dist->lpi_xa); + vgic_release_lpi_locked(dist, irq); + xa_unlock(&dist->lpi_xa); +} - kfree_rcu(irq, rcu); +static void vgic_release_deleted_lpis(struct kvm *kvm) +{ + struct vgic_dist *dist = &kvm->arch.vgic; + unsigned long intid; + struct vgic_irq *irq; + + xa_lock(&dist->lpi_xa); + + xa_for_each(&dist->lpi_xa, intid, irq) { + if (irq->pending_release) + vgic_release_lpi_locked(dist, irq); + } + + xa_unlock(&dist->lpi_xa); } void vgic_flush_pending_lpis(struct kvm_vcpu *vcpu) { struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; struct vgic_irq *irq, *tmp; + bool deleted = false; unsigned long flags; raw_spin_lock_irqsave(&vgic_cpu->ap_list_lock, flags); @@ -155,11 +184,14 @@ void vgic_flush_pending_lpis(struct kvm_vcpu *vcpu) list_del(&irq->ap_list); irq->vcpu = NULL; raw_spin_unlock(&irq->irq_lock); - vgic_put_irq(vcpu->kvm, irq); + deleted |= vgic_put_irq_norelease(vcpu->kvm, irq); } } raw_spin_unlock_irqrestore(&vgic_cpu->ap_list_lock, flags); + + if (deleted) + vgic_release_deleted_lpis(vcpu->kvm); } void vgic_irq_set_phys_pending(struct vgic_irq *irq, bool pending) @@ -399,7 +431,7 @@ retry: * now in the ap_list. This is safe as the caller must already hold a * reference on the irq. */ - vgic_get_irq_kref(irq); + vgic_get_irq_ref(irq); list_add_tail(&irq->ap_list, &vcpu->arch.vgic_cpu.ap_list_head); irq->vcpu = vcpu; @@ -630,6 +662,7 @@ static void vgic_prune_ap_list(struct kvm_vcpu *vcpu) { struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; struct vgic_irq *irq, *tmp; + bool deleted_lpis = false; DEBUG_SPINLOCK_BUG_ON(!irqs_disabled()); @@ -657,12 +690,12 @@ retry: /* * This vgic_put_irq call matches the - * vgic_get_irq_kref in vgic_queue_irq_unlock, + * vgic_get_irq_ref in vgic_queue_irq_unlock, * where we added the LPI to the ap_list. As * we remove the irq from the list, we drop * also drop the refcount. */ - vgic_put_irq(vcpu->kvm, irq); + deleted_lpis |= vgic_put_irq_norelease(vcpu->kvm, irq); continue; } @@ -725,6 +758,9 @@ retry: } raw_spin_unlock(&vgic_cpu->ap_list_lock); + + if (unlikely(deleted_lpis)) + vgic_release_deleted_lpis(vcpu->kvm); } static inline void vgic_fold_lr_state(struct kvm_vcpu *vcpu) @@ -818,7 +854,7 @@ static void vgic_flush_lr_state(struct kvm_vcpu *vcpu) * the AP list has been sorted already. */ if (multi_sgi && irq->priority > prio) { - _raw_spin_unlock(&irq->irq_lock); + raw_spin_unlock(&irq->irq_lock); break; } diff --git a/arch/arm64/kvm/vgic/vgic.h b/arch/arm64/kvm/vgic/vgic.h index de1c1d3261c3..ac5f9c5d2b98 100644 --- a/arch/arm64/kvm/vgic/vgic.h +++ b/arch/arm64/kvm/vgic/vgic.h @@ -267,7 +267,7 @@ void vgic_v2_put(struct kvm_vcpu *vcpu); void vgic_v2_save_state(struct kvm_vcpu *vcpu); void vgic_v2_restore_state(struct kvm_vcpu *vcpu); -static inline bool vgic_try_get_irq_kref(struct vgic_irq *irq) +static inline bool vgic_try_get_irq_ref(struct vgic_irq *irq) { if (!irq) return false; @@ -275,12 +275,12 @@ static inline bool vgic_try_get_irq_kref(struct vgic_irq *irq) if (irq->intid < VGIC_MIN_LPI) return true; - return kref_get_unless_zero(&irq->refcount); + return refcount_inc_not_zero(&irq->refcount); } -static inline void vgic_get_irq_kref(struct vgic_irq *irq) +static inline void vgic_get_irq_ref(struct vgic_irq *irq) { - WARN_ON_ONCE(!vgic_try_get_irq_kref(irq)); + WARN_ON_ONCE(!vgic_try_get_irq_ref(irq)); } void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu); diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c index ea84a61ed508..524d34a0e921 100644 --- a/arch/arm64/mm/init.c +++ b/arch/arm64/mm/init.c @@ -243,7 +243,7 @@ void __init arm64_memblock_init(void) */ if (memory_limit != PHYS_ADDR_MAX) { memblock_mem_limit_remove_map(memory_limit); - memblock_add(__pa_symbol(_text), (u64)(_end - _text)); + memblock_add(__pa_symbol(_text), (resource_size_t)(_end - _text)); } if (IS_ENABLED(CONFIG_BLK_DEV_INITRD) && phys_initrd_size) { @@ -252,8 +252,8 @@ void __init arm64_memblock_init(void) * initrd to become inaccessible via the linear mapping. * Otherwise, this is a no-op */ - u64 base = phys_initrd_start & PAGE_MASK; - u64 size = PAGE_ALIGN(phys_initrd_start + phys_initrd_size) - base; + phys_addr_t base = phys_initrd_start & PAGE_MASK; + resource_size_t size = PAGE_ALIGN(phys_initrd_start + phys_initrd_size) - base; /* * We can only add back the initrd memory if we don't end up @@ -279,7 +279,7 @@ void __init arm64_memblock_init(void) * Register the kernel text, kernel data, initrd, and initial * pagetables with memblock. */ - memblock_reserve(__pa_symbol(_stext), _end - _stext); + memblock_reserve(__pa_symbol(_text), _end - _text); if (IS_ENABLED(CONFIG_BLK_DEV_INITRD) && phys_initrd_size) { /* the generic initrd code expects virtual addresses */ initrd_start = __phys_to_virt(phys_initrd_start); diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index 980d7745a549..b3d8c3de4149 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -27,6 +27,8 @@ #include <linux/kfence.h> #include <linux/pkeys.h> #include <linux/mm_inline.h> +#include <linux/pagewalk.h> +#include <linux/stop_machine.h> #include <asm/barrier.h> #include <asm/cputype.h> @@ -47,6 +49,8 @@ #define NO_CONT_MAPPINGS BIT(1) #define NO_EXEC_MAPPINGS BIT(2) /* assumes FEAT_HPDS is not used */ +DEFINE_STATIC_KEY_FALSE(arm64_ptdump_lock_key); + u64 kimage_voffset __ro_after_init; EXPORT_SYMBOL(kimage_voffset); @@ -474,14 +478,18 @@ void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt, int flags); #endif -static phys_addr_t __pgd_pgtable_alloc(struct mm_struct *mm, +#define INVALID_PHYS_ADDR (-1ULL) + +static phys_addr_t __pgd_pgtable_alloc(struct mm_struct *mm, gfp_t gfp, enum pgtable_type pgtable_type) { /* Page is zeroed by init_clear_pgtable() so don't duplicate effort. */ - struct ptdesc *ptdesc = pagetable_alloc(GFP_PGTABLE_KERNEL & ~__GFP_ZERO, 0); + struct ptdesc *ptdesc = pagetable_alloc(gfp & ~__GFP_ZERO, 0); phys_addr_t pa; - BUG_ON(!ptdesc); + if (!ptdesc) + return INVALID_PHYS_ADDR; + pa = page_to_phys(ptdesc_page(ptdesc)); switch (pgtable_type) { @@ -502,16 +510,392 @@ static phys_addr_t __pgd_pgtable_alloc(struct mm_struct *mm, return pa; } +static phys_addr_t +try_pgd_pgtable_alloc_init_mm(enum pgtable_type pgtable_type, gfp_t gfp) +{ + return __pgd_pgtable_alloc(&init_mm, gfp, pgtable_type); +} + static phys_addr_t __maybe_unused pgd_pgtable_alloc_init_mm(enum pgtable_type pgtable_type) { - return __pgd_pgtable_alloc(&init_mm, pgtable_type); + phys_addr_t pa; + + pa = __pgd_pgtable_alloc(&init_mm, GFP_PGTABLE_KERNEL, pgtable_type); + BUG_ON(pa == INVALID_PHYS_ADDR); + return pa; } static phys_addr_t pgd_pgtable_alloc_special_mm(enum pgtable_type pgtable_type) { - return __pgd_pgtable_alloc(NULL, pgtable_type); + phys_addr_t pa; + + pa = __pgd_pgtable_alloc(NULL, GFP_PGTABLE_KERNEL, pgtable_type); + BUG_ON(pa == INVALID_PHYS_ADDR); + return pa; +} + +static void split_contpte(pte_t *ptep) +{ + int i; + + ptep = PTR_ALIGN_DOWN(ptep, sizeof(*ptep) * CONT_PTES); + for (i = 0; i < CONT_PTES; i++, ptep++) + __set_pte(ptep, pte_mknoncont(__ptep_get(ptep))); +} + +static int split_pmd(pmd_t *pmdp, pmd_t pmd, gfp_t gfp, bool to_cont) +{ + pmdval_t tableprot = PMD_TYPE_TABLE | PMD_TABLE_UXN | PMD_TABLE_AF; + unsigned long pfn = pmd_pfn(pmd); + pgprot_t prot = pmd_pgprot(pmd); + phys_addr_t pte_phys; + pte_t *ptep; + int i; + + pte_phys = try_pgd_pgtable_alloc_init_mm(TABLE_PTE, gfp); + if (pte_phys == INVALID_PHYS_ADDR) + return -ENOMEM; + ptep = (pte_t *)phys_to_virt(pte_phys); + + if (pgprot_val(prot) & PMD_SECT_PXN) + tableprot |= PMD_TABLE_PXN; + + prot = __pgprot((pgprot_val(prot) & ~PTE_TYPE_MASK) | PTE_TYPE_PAGE); + prot = __pgprot(pgprot_val(prot) & ~PTE_CONT); + if (to_cont) + prot = __pgprot(pgprot_val(prot) | PTE_CONT); + + for (i = 0; i < PTRS_PER_PTE; i++, ptep++, pfn++) + __set_pte(ptep, pfn_pte(pfn, prot)); + + /* + * Ensure the pte entries are visible to the table walker by the time + * the pmd entry that points to the ptes is visible. + */ + dsb(ishst); + __pmd_populate(pmdp, pte_phys, tableprot); + + return 0; +} + +static void split_contpmd(pmd_t *pmdp) +{ + int i; + + pmdp = PTR_ALIGN_DOWN(pmdp, sizeof(*pmdp) * CONT_PMDS); + for (i = 0; i < CONT_PMDS; i++, pmdp++) + set_pmd(pmdp, pmd_mknoncont(pmdp_get(pmdp))); +} + +static int split_pud(pud_t *pudp, pud_t pud, gfp_t gfp, bool to_cont) +{ + pudval_t tableprot = PUD_TYPE_TABLE | PUD_TABLE_UXN | PUD_TABLE_AF; + unsigned int step = PMD_SIZE >> PAGE_SHIFT; + unsigned long pfn = pud_pfn(pud); + pgprot_t prot = pud_pgprot(pud); + phys_addr_t pmd_phys; + pmd_t *pmdp; + int i; + + pmd_phys = try_pgd_pgtable_alloc_init_mm(TABLE_PMD, gfp); + if (pmd_phys == INVALID_PHYS_ADDR) + return -ENOMEM; + pmdp = (pmd_t *)phys_to_virt(pmd_phys); + + if (pgprot_val(prot) & PMD_SECT_PXN) + tableprot |= PUD_TABLE_PXN; + + prot = __pgprot((pgprot_val(prot) & ~PMD_TYPE_MASK) | PMD_TYPE_SECT); + prot = __pgprot(pgprot_val(prot) & ~PTE_CONT); + if (to_cont) + prot = __pgprot(pgprot_val(prot) | PTE_CONT); + + for (i = 0; i < PTRS_PER_PMD; i++, pmdp++, pfn += step) + set_pmd(pmdp, pfn_pmd(pfn, prot)); + + /* + * Ensure the pmd entries are visible to the table walker by the time + * the pud entry that points to the pmds is visible. + */ + dsb(ishst); + __pud_populate(pudp, pmd_phys, tableprot); + + return 0; +} + +static int split_kernel_leaf_mapping_locked(unsigned long addr) +{ + pgd_t *pgdp, pgd; + p4d_t *p4dp, p4d; + pud_t *pudp, pud; + pmd_t *pmdp, pmd; + pte_t *ptep, pte; + int ret = 0; + + /* + * PGD: If addr is PGD aligned then addr already describes a leaf + * boundary. If not present then there is nothing to split. + */ + if (ALIGN_DOWN(addr, PGDIR_SIZE) == addr) + goto out; + pgdp = pgd_offset_k(addr); + pgd = pgdp_get(pgdp); + if (!pgd_present(pgd)) + goto out; + + /* + * P4D: If addr is P4D aligned then addr already describes a leaf + * boundary. If not present then there is nothing to split. + */ + if (ALIGN_DOWN(addr, P4D_SIZE) == addr) + goto out; + p4dp = p4d_offset(pgdp, addr); + p4d = p4dp_get(p4dp); + if (!p4d_present(p4d)) + goto out; + + /* + * PUD: If addr is PUD aligned then addr already describes a leaf + * boundary. If not present then there is nothing to split. Otherwise, + * if we have a pud leaf, split to contpmd. + */ + if (ALIGN_DOWN(addr, PUD_SIZE) == addr) + goto out; + pudp = pud_offset(p4dp, addr); + pud = pudp_get(pudp); + if (!pud_present(pud)) + goto out; + if (pud_leaf(pud)) { + ret = split_pud(pudp, pud, GFP_PGTABLE_KERNEL, true); + if (ret) + goto out; + } + + /* + * CONTPMD: If addr is CONTPMD aligned then addr already describes a + * leaf boundary. If not present then there is nothing to split. + * Otherwise, if we have a contpmd leaf, split to pmd. + */ + if (ALIGN_DOWN(addr, CONT_PMD_SIZE) == addr) + goto out; + pmdp = pmd_offset(pudp, addr); + pmd = pmdp_get(pmdp); + if (!pmd_present(pmd)) + goto out; + if (pmd_leaf(pmd)) { + if (pmd_cont(pmd)) + split_contpmd(pmdp); + /* + * PMD: If addr is PMD aligned then addr already describes a + * leaf boundary. Otherwise, split to contpte. + */ + if (ALIGN_DOWN(addr, PMD_SIZE) == addr) + goto out; + ret = split_pmd(pmdp, pmd, GFP_PGTABLE_KERNEL, true); + if (ret) + goto out; + } + + /* + * CONTPTE: If addr is CONTPTE aligned then addr already describes a + * leaf boundary. If not present then there is nothing to split. + * Otherwise, if we have a contpte leaf, split to pte. + */ + if (ALIGN_DOWN(addr, CONT_PTE_SIZE) == addr) + goto out; + ptep = pte_offset_kernel(pmdp, addr); + pte = __ptep_get(ptep); + if (!pte_present(pte)) + goto out; + if (pte_cont(pte)) + split_contpte(ptep); + +out: + return ret; +} + +static DEFINE_MUTEX(pgtable_split_lock); + +int split_kernel_leaf_mapping(unsigned long start, unsigned long end) +{ + int ret; + + /* + * !BBML2_NOABORT systems should not be trying to change permissions on + * anything that is not pte-mapped in the first place. Just return early + * and let the permission change code raise a warning if not already + * pte-mapped. + */ + if (!system_supports_bbml2_noabort()) + return 0; + + /* + * Ensure start and end are at least page-aligned since this is the + * finest granularity we can split to. + */ + if (start != PAGE_ALIGN(start) || end != PAGE_ALIGN(end)) + return -EINVAL; + + mutex_lock(&pgtable_split_lock); + arch_enter_lazy_mmu_mode(); + + /* + * The split_kernel_leaf_mapping_locked() may sleep, it is not a + * problem for ARM64 since ARM64's lazy MMU implementation allows + * sleeping. + * + * Optimize for the common case of splitting out a single page from a + * larger mapping. Here we can just split on the "least aligned" of + * start and end and this will guarantee that there must also be a split + * on the more aligned address since the both addresses must be in the + * same contpte block and it must have been split to ptes. + */ + if (end - start == PAGE_SIZE) { + start = __ffs(start) < __ffs(end) ? start : end; + ret = split_kernel_leaf_mapping_locked(start); + } else { + ret = split_kernel_leaf_mapping_locked(start); + if (!ret) + ret = split_kernel_leaf_mapping_locked(end); + } + + arch_leave_lazy_mmu_mode(); + mutex_unlock(&pgtable_split_lock); + return ret; +} + +static int __init split_to_ptes_pud_entry(pud_t *pudp, unsigned long addr, + unsigned long next, + struct mm_walk *walk) +{ + pud_t pud = pudp_get(pudp); + int ret = 0; + + if (pud_leaf(pud)) + ret = split_pud(pudp, pud, GFP_ATOMIC, false); + + return ret; +} + +static int __init split_to_ptes_pmd_entry(pmd_t *pmdp, unsigned long addr, + unsigned long next, + struct mm_walk *walk) +{ + pmd_t pmd = pmdp_get(pmdp); + int ret = 0; + + if (pmd_leaf(pmd)) { + if (pmd_cont(pmd)) + split_contpmd(pmdp); + ret = split_pmd(pmdp, pmd, GFP_ATOMIC, false); + + /* + * We have split the pmd directly to ptes so there is no need to + * visit each pte to check if they are contpte. + */ + walk->action = ACTION_CONTINUE; + } + + return ret; +} + +static int __init split_to_ptes_pte_entry(pte_t *ptep, unsigned long addr, + unsigned long next, + struct mm_walk *walk) +{ + pte_t pte = __ptep_get(ptep); + + if (pte_cont(pte)) + split_contpte(ptep); + + return 0; +} + +static const struct mm_walk_ops split_to_ptes_ops __initconst = { + .pud_entry = split_to_ptes_pud_entry, + .pmd_entry = split_to_ptes_pmd_entry, + .pte_entry = split_to_ptes_pte_entry, +}; + +static bool linear_map_requires_bbml2 __initdata; + +u32 idmap_kpti_bbml2_flag; + +void __init init_idmap_kpti_bbml2_flag(void) +{ + WRITE_ONCE(idmap_kpti_bbml2_flag, 1); + /* Must be visible to other CPUs before stop_machine() is called. */ + smp_mb(); +} + +static int __init linear_map_split_to_ptes(void *__unused) +{ + /* + * Repainting the linear map must be done by CPU0 (the boot CPU) because + * that's the only CPU that we know supports BBML2. The other CPUs will + * be held in a waiting area with the idmap active. + */ + if (!smp_processor_id()) { + unsigned long lstart = _PAGE_OFFSET(vabits_actual); + unsigned long lend = PAGE_END; + unsigned long kstart = (unsigned long)lm_alias(_stext); + unsigned long kend = (unsigned long)lm_alias(__init_begin); + int ret; + + /* + * Wait for all secondary CPUs to be put into the waiting area. + */ + smp_cond_load_acquire(&idmap_kpti_bbml2_flag, VAL == num_online_cpus()); + + /* + * Walk all of the linear map [lstart, lend), except the kernel + * linear map alias [kstart, kend), and split all mappings to + * PTE. The kernel alias remains static throughout runtime so + * can continue to be safely mapped with large mappings. + */ + ret = walk_kernel_page_table_range_lockless(lstart, kstart, + &split_to_ptes_ops, NULL, NULL); + if (!ret) + ret = walk_kernel_page_table_range_lockless(kend, lend, + &split_to_ptes_ops, NULL, NULL); + if (ret) + panic("Failed to split linear map\n"); + flush_tlb_kernel_range(lstart, lend); + + /* + * Relies on dsb in flush_tlb_kernel_range() to avoid reordering + * before any page table split operations. + */ + WRITE_ONCE(idmap_kpti_bbml2_flag, 0); + } else { + typedef void (wait_split_fn)(void); + extern wait_split_fn wait_linear_map_split_to_ptes; + wait_split_fn *wait_fn; + + wait_fn = (void *)__pa_symbol(wait_linear_map_split_to_ptes); + + /* + * At least one secondary CPU doesn't support BBML2 so cannot + * tolerate the size of the live mappings changing. So have the + * secondary CPUs wait for the boot CPU to make the changes + * with the idmap active and init_mm inactive. + */ + cpu_install_idmap(); + wait_fn(); + cpu_uninstall_idmap(); + } + + return 0; +} + +void __init linear_map_maybe_split_to_ptes(void) +{ + if (linear_map_requires_bbml2 && !system_supports_bbml2_noabort()) { + init_idmap_kpti_bbml2_flag(); + stop_machine(linear_map_split_to_ptes, NULL, cpu_online_mask); + } } /* @@ -574,8 +958,8 @@ void __init mark_linear_text_alias_ro(void) /* * Remove the write permissions from the linear alias of .text/.rodata */ - update_mapping_prot(__pa_symbol(_stext), (unsigned long)lm_alias(_stext), - (unsigned long)__init_begin - (unsigned long)_stext, + update_mapping_prot(__pa_symbol(_text), (unsigned long)lm_alias(_text), + (unsigned long)__init_begin - (unsigned long)_text, PAGE_KERNEL_RO); } @@ -633,10 +1017,20 @@ static inline void arm64_kfence_map_pool(phys_addr_t kfence_pool, pgd_t *pgdp) { #endif /* CONFIG_KFENCE */ +static inline bool force_pte_mapping(void) +{ + bool bbml2 = system_capabilities_finalized() ? + system_supports_bbml2_noabort() : cpu_supports_bbml2_noabort(); + + return (!bbml2 && (rodata_full || arm64_kfence_can_set_direct_map() || + is_realm_world())) || + debug_pagealloc_enabled(); +} + static void __init map_mem(pgd_t *pgdp) { static const u64 direct_map_end = _PAGE_END(VA_BITS_MIN); - phys_addr_t kernel_start = __pa_symbol(_stext); + phys_addr_t kernel_start = __pa_symbol(_text); phys_addr_t kernel_end = __pa_symbol(__init_begin); phys_addr_t start, end; phys_addr_t early_kfence_pool; @@ -658,7 +1052,9 @@ static void __init map_mem(pgd_t *pgdp) early_kfence_pool = arm64_kfence_alloc_pool(); - if (can_set_direct_map()) + linear_map_requires_bbml2 = !force_pte_mapping() && can_set_direct_map(); + + if (force_pte_mapping()) flags |= NO_BLOCK_MAPPINGS | NO_CONT_MAPPINGS; /* @@ -683,7 +1079,7 @@ static void __init map_mem(pgd_t *pgdp) } /* - * Map the linear alias of the [_stext, __init_begin) interval + * Map the linear alias of the [_text, __init_begin) interval * as non-executable now, and remove the write permission in * mark_linear_text_alias_ro() below (which will be called after * alternative patching has completed). This makes the contents @@ -710,6 +1106,10 @@ void mark_rodata_ro(void) WRITE_ONCE(rodata_is_rw, false); update_mapping_prot(__pa_symbol(__start_rodata), (unsigned long)__start_rodata, section_size, PAGE_KERNEL_RO); + /* mark the range between _text and _stext as read only. */ + update_mapping_prot(__pa_symbol(_text), (unsigned long)_text, + (unsigned long)_stext - (unsigned long)_text, + PAGE_KERNEL_RO); } static void __init declare_vma(struct vm_struct *vma, @@ -780,38 +1180,41 @@ static void __init declare_kernel_vmas(void) { static struct vm_struct vmlinux_seg[KERNEL_SEGMENT_COUNT]; - declare_vma(&vmlinux_seg[0], _stext, _etext, VM_NO_GUARD); + declare_vma(&vmlinux_seg[0], _text, _etext, VM_NO_GUARD); declare_vma(&vmlinux_seg[1], __start_rodata, __inittext_begin, VM_NO_GUARD); declare_vma(&vmlinux_seg[2], __inittext_begin, __inittext_end, VM_NO_GUARD); declare_vma(&vmlinux_seg[3], __initdata_begin, __initdata_end, VM_NO_GUARD); declare_vma(&vmlinux_seg[4], _data, _end, 0); } -void __pi_map_range(u64 *pgd, u64 start, u64 end, u64 pa, pgprot_t prot, - int level, pte_t *tbl, bool may_use_cont, u64 va_offset); +void __pi_map_range(phys_addr_t *pte, u64 start, u64 end, phys_addr_t pa, + pgprot_t prot, int level, pte_t *tbl, bool may_use_cont, + u64 va_offset); static u8 idmap_ptes[IDMAP_LEVELS - 1][PAGE_SIZE] __aligned(PAGE_SIZE) __ro_after_init, - kpti_ptes[IDMAP_LEVELS - 1][PAGE_SIZE] __aligned(PAGE_SIZE) __ro_after_init; + kpti_bbml2_ptes[IDMAP_LEVELS - 1][PAGE_SIZE] __aligned(PAGE_SIZE) __ro_after_init; static void __init create_idmap(void) { - u64 start = __pa_symbol(__idmap_text_start); - u64 end = __pa_symbol(__idmap_text_end); - u64 ptep = __pa_symbol(idmap_ptes); + phys_addr_t start = __pa_symbol(__idmap_text_start); + phys_addr_t end = __pa_symbol(__idmap_text_end); + phys_addr_t ptep = __pa_symbol(idmap_ptes); __pi_map_range(&ptep, start, end, start, PAGE_KERNEL_ROX, IDMAP_ROOT_LEVEL, (pte_t *)idmap_pg_dir, false, __phys_to_virt(ptep) - ptep); - if (IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0) && !arm64_use_ng_mappings) { - extern u32 __idmap_kpti_flag; - u64 pa = __pa_symbol(&__idmap_kpti_flag); + if (linear_map_requires_bbml2 || + (IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0) && !arm64_use_ng_mappings)) { + phys_addr_t pa = __pa_symbol(&idmap_kpti_bbml2_flag); /* * The KPTI G-to-nG conversion code needs a read-write mapping - * of its synchronization flag in the ID map. + * of its synchronization flag in the ID map. This is also used + * when splitting the linear map to ptes if a secondary CPU + * doesn't support bbml2. */ - ptep = __pa_symbol(kpti_ptes); + ptep = __pa_symbol(kpti_bbml2_ptes); __pi_map_range(&ptep, pa, pa + sizeof(u32), pa, PAGE_KERNEL, IDMAP_ROOT_LEVEL, (pte_t *)idmap_pg_dir, false, __phys_to_virt(ptep) - ptep); @@ -1261,7 +1664,8 @@ int pmd_clear_huge(pmd_t *pmdp) return 1; } -int pmd_free_pte_page(pmd_t *pmdp, unsigned long addr) +static int __pmd_free_pte_page(pmd_t *pmdp, unsigned long addr, + bool acquire_mmap_lock) { pte_t *table; pmd_t pmd; @@ -1273,13 +1677,25 @@ int pmd_free_pte_page(pmd_t *pmdp, unsigned long addr) return 1; } + /* See comment in pud_free_pmd_page for static key logic */ table = pte_offset_kernel(pmdp, addr); pmd_clear(pmdp); __flush_tlb_kernel_pgtable(addr); + if (static_branch_unlikely(&arm64_ptdump_lock_key) && acquire_mmap_lock) { + mmap_read_lock(&init_mm); + mmap_read_unlock(&init_mm); + } + pte_free_kernel(NULL, table); return 1; } +int pmd_free_pte_page(pmd_t *pmdp, unsigned long addr) +{ + /* If ptdump is walking the pagetables, acquire init_mm.mmap_lock */ + return __pmd_free_pte_page(pmdp, addr, /* acquire_mmap_lock = */ true); +} + int pud_free_pmd_page(pud_t *pudp, unsigned long addr) { pmd_t *table; @@ -1295,16 +1711,36 @@ int pud_free_pmd_page(pud_t *pudp, unsigned long addr) } table = pmd_offset(pudp, addr); + + /* + * Our objective is to prevent ptdump from reading a PMD table which has + * been freed. In this race, if pud_free_pmd_page observes the key on + * (which got flipped by ptdump) then the mmap lock sequence here will, + * as a result of the mmap write lock/unlock sequence in ptdump, give + * us the correct synchronization. If not, this means that ptdump has + * yet not started walking the pagetables - the sequence of barriers + * issued by __flush_tlb_kernel_pgtable() guarantees that ptdump will + * observe an empty PUD. + */ + pud_clear(pudp); + __flush_tlb_kernel_pgtable(addr); + if (static_branch_unlikely(&arm64_ptdump_lock_key)) { + mmap_read_lock(&init_mm); + mmap_read_unlock(&init_mm); + } + pmdp = table; next = addr; end = addr + PUD_SIZE; do { if (pmd_present(pmdp_get(pmdp))) - pmd_free_pte_page(pmdp, next); + /* + * PMD has been isolated, so ptdump won't see it. No + * need to acquire init_mm.mmap_lock. + */ + __pmd_free_pte_page(pmdp, next, /* acquire_mmap_lock = */ false); } while (pmdp++, next += PMD_SIZE, next != end); - pud_clear(pudp); - __flush_tlb_kernel_pgtable(addr); pmd_free(NULL, table); return 1; } @@ -1324,8 +1760,8 @@ static void __remove_pgd_mapping(pgd_t *pgdir, unsigned long start, u64 size) struct range arch_get_mappable_range(void) { struct range mhp_range; - u64 start_linear_pa = __pa(_PAGE_OFFSET(vabits_actual)); - u64 end_linear_pa = __pa(PAGE_END - 1); + phys_addr_t start_linear_pa = __pa(_PAGE_OFFSET(vabits_actual)); + phys_addr_t end_linear_pa = __pa(PAGE_END - 1); if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) { /* @@ -1360,7 +1796,7 @@ int arch_add_memory(int nid, u64 start, u64 size, VM_BUG_ON(!mhp_range_allowed(start, size, true)); - if (can_set_direct_map()) + if (force_pte_mapping()) flags |= NO_BLOCK_MAPPINGS | NO_CONT_MAPPINGS; __create_pgd_mapping(swapper_pg_dir, start, __phys_to_virt(start), diff --git a/arch/arm64/mm/pageattr.c b/arch/arm64/mm/pageattr.c index 04d4a8f676db..5135f2d66958 100644 --- a/arch/arm64/mm/pageattr.c +++ b/arch/arm64/mm/pageattr.c @@ -8,6 +8,7 @@ #include <linux/mem_encrypt.h> #include <linux/sched.h> #include <linux/vmalloc.h> +#include <linux/pagewalk.h> #include <asm/cacheflush.h> #include <asm/pgtable-prot.h> @@ -20,7 +21,66 @@ struct page_change_data { pgprot_t clear_mask; }; -bool rodata_full __ro_after_init = IS_ENABLED(CONFIG_RODATA_FULL_DEFAULT_ENABLED); +static ptdesc_t set_pageattr_masks(ptdesc_t val, struct mm_walk *walk) +{ + struct page_change_data *masks = walk->private; + + val &= ~(pgprot_val(masks->clear_mask)); + val |= (pgprot_val(masks->set_mask)); + + return val; +} + +static int pageattr_pud_entry(pud_t *pud, unsigned long addr, + unsigned long next, struct mm_walk *walk) +{ + pud_t val = pudp_get(pud); + + if (pud_sect(val)) { + if (WARN_ON_ONCE((next - addr) != PUD_SIZE)) + return -EINVAL; + val = __pud(set_pageattr_masks(pud_val(val), walk)); + set_pud(pud, val); + walk->action = ACTION_CONTINUE; + } + + return 0; +} + +static int pageattr_pmd_entry(pmd_t *pmd, unsigned long addr, + unsigned long next, struct mm_walk *walk) +{ + pmd_t val = pmdp_get(pmd); + + if (pmd_sect(val)) { + if (WARN_ON_ONCE((next - addr) != PMD_SIZE)) + return -EINVAL; + val = __pmd(set_pageattr_masks(pmd_val(val), walk)); + set_pmd(pmd, val); + walk->action = ACTION_CONTINUE; + } + + return 0; +} + +static int pageattr_pte_entry(pte_t *pte, unsigned long addr, + unsigned long next, struct mm_walk *walk) +{ + pte_t val = __ptep_get(pte); + + val = __pte(set_pageattr_masks(pte_val(val), walk)); + __set_pte(pte, val); + + return 0; +} + +static const struct mm_walk_ops pageattr_ops = { + .pud_entry = pageattr_pud_entry, + .pmd_entry = pageattr_pmd_entry, + .pte_entry = pageattr_pte_entry, +}; + +bool rodata_full __ro_after_init = true; bool can_set_direct_map(void) { @@ -37,32 +97,39 @@ bool can_set_direct_map(void) arm64_kfence_can_set_direct_map() || is_realm_world(); } -static int change_page_range(pte_t *ptep, unsigned long addr, void *data) +static int update_range_prot(unsigned long start, unsigned long size, + pgprot_t set_mask, pgprot_t clear_mask) { - struct page_change_data *cdata = data; - pte_t pte = __ptep_get(ptep); + struct page_change_data data; + int ret; - pte = clear_pte_bit(pte, cdata->clear_mask); - pte = set_pte_bit(pte, cdata->set_mask); + data.set_mask = set_mask; + data.clear_mask = clear_mask; - __set_pte(ptep, pte); - return 0; + ret = split_kernel_leaf_mapping(start, start + size); + if (WARN_ON_ONCE(ret)) + return ret; + + arch_enter_lazy_mmu_mode(); + + /* + * The caller must ensure that the range we are operating on does not + * partially overlap a block mapping, or a cont mapping. Any such case + * must be eliminated by splitting the mapping. + */ + ret = walk_kernel_page_table_range_lockless(start, start + size, + &pageattr_ops, NULL, &data); + arch_leave_lazy_mmu_mode(); + + return ret; } -/* - * This function assumes that the range is mapped with PAGE_SIZE pages. - */ static int __change_memory_common(unsigned long start, unsigned long size, - pgprot_t set_mask, pgprot_t clear_mask) + pgprot_t set_mask, pgprot_t clear_mask) { - struct page_change_data data; int ret; - data.set_mask = set_mask; - data.clear_mask = clear_mask; - - ret = apply_to_page_range(&init_mm, start, size, change_page_range, - &data); + ret = update_range_prot(start, size, set_mask, clear_mask); /* * If the memory is being made valid without changing any other bits @@ -174,32 +241,26 @@ int set_memory_valid(unsigned long addr, int numpages, int enable) int set_direct_map_invalid_noflush(struct page *page) { - struct page_change_data data = { - .set_mask = __pgprot(0), - .clear_mask = __pgprot(PTE_VALID), - }; + pgprot_t clear_mask = __pgprot(PTE_VALID); + pgprot_t set_mask = __pgprot(0); if (!can_set_direct_map()) return 0; - return apply_to_page_range(&init_mm, - (unsigned long)page_address(page), - PAGE_SIZE, change_page_range, &data); + return update_range_prot((unsigned long)page_address(page), + PAGE_SIZE, set_mask, clear_mask); } int set_direct_map_default_noflush(struct page *page) { - struct page_change_data data = { - .set_mask = __pgprot(PTE_VALID | PTE_WRITE), - .clear_mask = __pgprot(PTE_RDONLY), - }; + pgprot_t set_mask = __pgprot(PTE_VALID | PTE_WRITE); + pgprot_t clear_mask = __pgprot(PTE_RDONLY); if (!can_set_direct_map()) return 0; - return apply_to_page_range(&init_mm, - (unsigned long)page_address(page), - PAGE_SIZE, change_page_range, &data); + return update_range_prot((unsigned long)page_address(page), + PAGE_SIZE, set_mask, clear_mask); } static int __set_memory_enc_dec(unsigned long addr, diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 8c75965afc9e..86818511962b 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -245,10 +245,6 @@ SYM_FUNC_ALIAS(__pi_idmap_cpu_replace_ttbr1, idmap_cpu_replace_ttbr1) * * Called exactly once from stop_machine context by each CPU found during boot. */ - .pushsection ".data", "aw", %progbits -SYM_DATA(__idmap_kpti_flag, .long 1) - .popsection - SYM_TYPED_FUNC_START(idmap_kpti_install_ng_mappings) cpu .req w0 temp_pte .req x0 @@ -273,7 +269,7 @@ SYM_TYPED_FUNC_START(idmap_kpti_install_ng_mappings) mov x5, x3 // preserve temp_pte arg mrs swapper_ttb, ttbr1_el1 - adr_l flag_ptr, __idmap_kpti_flag + adr_l flag_ptr, idmap_kpti_bbml2_flag cbnz cpu, __idmap_kpti_secondary @@ -416,7 +412,25 @@ alternative_else_nop_endif __idmap_kpti_secondary: /* Uninstall swapper before surgery begins */ __idmap_cpu_set_reserved_ttbr1 x16, x17 + b scondary_cpu_wait + + .unreq swapper_ttb + .unreq flag_ptr +SYM_FUNC_END(idmap_kpti_install_ng_mappings) + .popsection +#endif + + .pushsection ".idmap.text", "a" +SYM_TYPED_FUNC_START(wait_linear_map_split_to_ptes) + /* Must be same registers as in idmap_kpti_install_ng_mappings */ + swapper_ttb .req x3 + flag_ptr .req x4 + + mrs swapper_ttb, ttbr1_el1 + adr_l flag_ptr, idmap_kpti_bbml2_flag + __idmap_cpu_set_reserved_ttbr1 x16, x17 +scondary_cpu_wait: /* Increment the flag to let the boot CPU we're ready */ 1: ldxr w16, [flag_ptr] add w16, w16, #1 @@ -436,9 +450,8 @@ __idmap_kpti_secondary: .unreq swapper_ttb .unreq flag_ptr -SYM_FUNC_END(idmap_kpti_install_ng_mappings) +SYM_FUNC_END(wait_linear_map_split_to_ptes) .popsection -#endif /* * __cpu_setup diff --git a/arch/arm64/mm/ptdump.c b/arch/arm64/mm/ptdump.c index 421a5de806c6..ab9899ca1e5f 100644 --- a/arch/arm64/mm/ptdump.c +++ b/arch/arm64/mm/ptdump.c @@ -283,6 +283,13 @@ void note_page_flush(struct ptdump_state *pt_st) note_page(pt_st, 0, -1, pte_val(pte_zero)); } +static void arm64_ptdump_walk_pgd(struct ptdump_state *st, struct mm_struct *mm) +{ + static_branch_inc(&arm64_ptdump_lock_key); + ptdump_walk_pgd(st, mm, NULL); + static_branch_dec(&arm64_ptdump_lock_key); +} + void ptdump_walk(struct seq_file *s, struct ptdump_info *info) { unsigned long end = ~0UL; @@ -311,7 +318,7 @@ void ptdump_walk(struct seq_file *s, struct ptdump_info *info) } }; - ptdump_walk_pgd(&st.ptdump, info->mm, NULL); + arm64_ptdump_walk_pgd(&st.ptdump, info->mm); } static void __init ptdump_initialize(void) @@ -353,7 +360,7 @@ bool ptdump_check_wx(void) } }; - ptdump_walk_pgd(&st.ptdump, &init_mm, NULL); + arm64_ptdump_walk_pgd(&st.ptdump, &init_mm); if (st.wx_pages || st.uxn_pages) { pr_warn("Checked W+X mappings: FAILED, %lu W+X pages found, %lu non-UXN pages found\n", diff --git a/arch/arm64/net/Makefile b/arch/arm64/net/Makefile index 5c540efb7d9b..3ae382bfca87 100644 --- a/arch/arm64/net/Makefile +++ b/arch/arm64/net/Makefile @@ -2,4 +2,4 @@ # # ARM64 networking code # -obj-$(CONFIG_BPF_JIT) += bpf_jit_comp.o +obj-$(CONFIG_BPF_JIT) += bpf_jit_comp.o bpf_timed_may_goto.o diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c index 52ffe115a8c4..ab83089c3d8f 100644 --- a/arch/arm64/net/bpf_jit_comp.c +++ b/arch/arm64/net/bpf_jit_comp.c @@ -185,7 +185,7 @@ static inline void emit_bti(u32 insn, struct jit_ctx *ctx) static inline void emit_kcfi(u32 hash, struct jit_ctx *ctx) { - if (IS_ENABLED(CONFIG_CFI_CLANG)) + if (IS_ENABLED(CONFIG_CFI)) emit_u32_data(hash, ctx); } @@ -1066,19 +1066,53 @@ static void build_epilogue(struct jit_ctx *ctx, bool was_classic) emit(A64_RET(A64_LR), ctx); } -#define BPF_FIXUP_OFFSET_MASK GENMASK(26, 0) +/* + * Metadata encoding for exception handling in JITed code. + * + * Format of `fixup` field in `struct exception_table_entry`: + * + * Bit layout of `fixup` (32-bit): + * + * +-----------+--------+-----------+-----------+----------+ + * | 31-27 | 26-22 | 21 | 20-16 | 15-0 | + * | | | | | | + * | FIXUP_REG | Unused | ARENA_ACC | ARENA_REG | OFFSET | + * +-----------+--------+-----------+-----------+----------+ + * + * - OFFSET (16 bits): Offset used to compute address for Load/Store instruction. + * - ARENA_REG (5 bits): Register that is used to calculate the address for load/store when + * accessing the arena region. + * - ARENA_ACCESS (1 bit): This bit is set when the faulting instruction accessed the arena region. + * - FIXUP_REG (5 bits): Destination register for the load instruction (cleared on fault) or set to + * DONT_CLEAR if it is a store instruction. + */ + +#define BPF_FIXUP_OFFSET_MASK GENMASK(15, 0) +#define BPF_FIXUP_ARENA_REG_MASK GENMASK(20, 16) +#define BPF_ARENA_ACCESS BIT(21) #define BPF_FIXUP_REG_MASK GENMASK(31, 27) #define DONT_CLEAR 5 /* Unused ARM64 register from BPF's POV */ bool ex_handler_bpf(const struct exception_table_entry *ex, struct pt_regs *regs) { - off_t offset = FIELD_GET(BPF_FIXUP_OFFSET_MASK, ex->fixup); int dst_reg = FIELD_GET(BPF_FIXUP_REG_MASK, ex->fixup); + s16 off = FIELD_GET(BPF_FIXUP_OFFSET_MASK, ex->fixup); + int arena_reg = FIELD_GET(BPF_FIXUP_ARENA_REG_MASK, ex->fixup); + bool is_arena = !!(ex->fixup & BPF_ARENA_ACCESS); + bool is_write = (dst_reg == DONT_CLEAR); + unsigned long addr; + + if (is_arena) { + addr = regs->regs[arena_reg] + off; + bpf_prog_report_arena_violation(is_write, addr, regs->pc); + } if (dst_reg != DONT_CLEAR) regs->regs[dst_reg] = 0; - regs->pc = (unsigned long)&ex->fixup - offset; + /* Skip the faulting instruction */ + regs->pc += AARCH64_INSN_SIZE; + return true; } @@ -1088,7 +1122,9 @@ static int add_exception_handler(const struct bpf_insn *insn, int dst_reg) { off_t ins_offset; - off_t fixup_offset; + s16 off = insn->off; + bool is_arena; + int arena_reg; unsigned long pc; struct exception_table_entry *ex; @@ -1097,11 +1133,16 @@ static int add_exception_handler(const struct bpf_insn *insn, return 0; if (BPF_MODE(insn->code) != BPF_PROBE_MEM && - BPF_MODE(insn->code) != BPF_PROBE_MEMSX && - BPF_MODE(insn->code) != BPF_PROBE_MEM32 && - BPF_MODE(insn->code) != BPF_PROBE_ATOMIC) + BPF_MODE(insn->code) != BPF_PROBE_MEMSX && + BPF_MODE(insn->code) != BPF_PROBE_MEM32 && + BPF_MODE(insn->code) != BPF_PROBE_MEM32SX && + BPF_MODE(insn->code) != BPF_PROBE_ATOMIC) return 0; + is_arena = (BPF_MODE(insn->code) == BPF_PROBE_MEM32) || + (BPF_MODE(insn->code) == BPF_PROBE_MEM32SX) || + (BPF_MODE(insn->code) == BPF_PROBE_ATOMIC); + if (!ctx->prog->aux->extable || WARN_ON_ONCE(ctx->exentry_idx >= ctx->prog->aux->num_exentries)) return -EINVAL; @@ -1120,22 +1161,6 @@ static int add_exception_handler(const struct bpf_insn *insn, return -ERANGE; /* - * Since the extable follows the program, the fixup offset is always - * negative and limited to BPF_JIT_REGION_SIZE. Store a positive value - * to keep things simple, and put the destination register in the upper - * bits. We don't need to worry about buildtime or runtime sort - * modifying the upper bits because the table is already sorted, and - * isn't part of the main exception table. - * - * The fixup_offset is set to the next instruction from the instruction - * that may fault. The execution will jump to this after handling the - * fault. - */ - fixup_offset = (long)&ex->fixup - (pc + AARCH64_INSN_SIZE); - if (!FIELD_FIT(BPF_FIXUP_OFFSET_MASK, fixup_offset)) - return -ERANGE; - - /* * The offsets above have been calculated using the RO buffer but we * need to use the R/W buffer for writes. * switch ex to rw buffer for writing. @@ -1147,8 +1172,26 @@ static int add_exception_handler(const struct bpf_insn *insn, if (BPF_CLASS(insn->code) != BPF_LDX) dst_reg = DONT_CLEAR; - ex->fixup = FIELD_PREP(BPF_FIXUP_OFFSET_MASK, fixup_offset) | - FIELD_PREP(BPF_FIXUP_REG_MASK, dst_reg); + ex->fixup = FIELD_PREP(BPF_FIXUP_REG_MASK, dst_reg); + + if (is_arena) { + ex->fixup |= BPF_ARENA_ACCESS; + /* + * insn->src_reg/dst_reg holds the address in the arena region with upper 32-bits + * being zero because of a preceding addr_space_cast(r<n>, 0x0, 0x1) instruction. + * This address is adjusted with the addition of arena_vm_start (see the + * implementation of BPF_PROBE_MEM32 and BPF_PROBE_ATOMIC) before being used for the + * memory access. Pass the reg holding the unmodified 32-bit address to + * ex_handler_bpf. + */ + if (BPF_CLASS(insn->code) == BPF_LDX) + arena_reg = bpf2a64[insn->src_reg]; + else + arena_reg = bpf2a64[insn->dst_reg]; + + ex->fixup |= FIELD_PREP(BPF_FIXUP_OFFSET_MASK, off) | + FIELD_PREP(BPF_FIXUP_ARENA_REG_MASK, arena_reg); + } ex->type = EX_TYPE_BPF; @@ -1558,7 +1601,13 @@ emit_cond_jmp: if (ret < 0) return ret; emit_call(func_addr, ctx); - emit(A64_MOV(1, r0, A64_R(0)), ctx); + /* + * Call to arch_bpf_timed_may_goto() is emitted by the + * verifier and called with custom calling convention with + * first argument and return value in BPF_REG_AX (x9). + */ + if (func_addr != (u64)arch_bpf_timed_may_goto) + emit(A64_MOV(1, r0, A64_R(0)), ctx); break; } /* tail call */ @@ -1612,7 +1661,11 @@ emit_cond_jmp: case BPF_LDX | BPF_PROBE_MEM32 | BPF_H: case BPF_LDX | BPF_PROBE_MEM32 | BPF_W: case BPF_LDX | BPF_PROBE_MEM32 | BPF_DW: - if (BPF_MODE(insn->code) == BPF_PROBE_MEM32) { + case BPF_LDX | BPF_PROBE_MEM32SX | BPF_B: + case BPF_LDX | BPF_PROBE_MEM32SX | BPF_H: + case BPF_LDX | BPF_PROBE_MEM32SX | BPF_W: + if (BPF_MODE(insn->code) == BPF_PROBE_MEM32 || + BPF_MODE(insn->code) == BPF_PROBE_MEM32SX) { emit(A64_ADD(1, tmp2, src, arena_vm_base), ctx); src = tmp2; } @@ -1624,7 +1677,8 @@ emit_cond_jmp: off_adj = off; } sign_extend = (BPF_MODE(insn->code) == BPF_MEMSX || - BPF_MODE(insn->code) == BPF_PROBE_MEMSX); + BPF_MODE(insn->code) == BPF_PROBE_MEMSX || + BPF_MODE(insn->code) == BPF_PROBE_MEM32SX); switch (BPF_SIZE(code)) { case BPF_W: if (is_lsi_offset(off_adj, 2)) { @@ -1832,9 +1886,11 @@ emit_cond_jmp: if (ret) return ret; - ret = add_exception_handler(insn, ctx, dst); - if (ret) - return ret; + if (BPF_MODE(insn->code) == BPF_PROBE_ATOMIC) { + ret = add_exception_handler(insn, ctx, dst); + if (ret) + return ret; + } break; default: @@ -2767,7 +2823,6 @@ int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *ro_image, goto out; } - bpf_flush_icache(ro_image, ro_image + size); out: kvfree(image); return ret; @@ -3038,6 +3093,11 @@ bool bpf_jit_bypass_spec_v4(void) return true; } +bool bpf_jit_supports_timed_may_goto(void) +{ + return true; +} + bool bpf_jit_inlines_helper_call(s32 imm) { switch (imm) { @@ -3064,8 +3124,7 @@ void bpf_jit_free(struct bpf_prog *prog) * before freeing it. */ if (jit_data) { - bpf_arch_text_copy(&jit_data->ro_header->size, &jit_data->header->size, - sizeof(jit_data->header->size)); + bpf_jit_binary_pack_finalize(jit_data->ro_header, jit_data->header); kfree(jit_data); } prog->bpf_func -= cfi_get_offset(); diff --git a/arch/arm64/net/bpf_timed_may_goto.S b/arch/arm64/net/bpf_timed_may_goto.S new file mode 100644 index 000000000000..894cfcd7b241 --- /dev/null +++ b/arch/arm64/net/bpf_timed_may_goto.S @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2025 Puranjay Mohan <puranjay@kernel.org> */ + +#include <linux/linkage.h> + +SYM_FUNC_START(arch_bpf_timed_may_goto) + /* Allocate stack space and emit frame record */ + stp x29, x30, [sp, #-64]! + mov x29, sp + + /* Save BPF registers R0 - R5 (x7, x0-x4)*/ + stp x7, x0, [sp, #16] + stp x1, x2, [sp, #32] + stp x3, x4, [sp, #48] + + /* + * Stack depth was passed in BPF_REG_AX (x9), add it to the BPF_FP + * (x25) to get the pointer to count and timestamp and pass it as the + * first argument in x0. + * + * Before generating the call to arch_bpf_timed_may_goto, the verifier + * generates a load instruction using FP, i.e. REG_AX = *(u64 *)(FP - + * stack_off_cnt), so BPF_REG_FP (x25) is always set up by the arm64 + * jit in this case. + */ + add x0, x9, x25 + bl bpf_check_timed_may_goto + /* BPF_REG_AX(x9) will be stored into count, so move return value to it. */ + mov x9, x0 + + /* Restore BPF registers R0 - R5 (x7, x0-x4) */ + ldp x7, x0, [sp, #16] + ldp x1, x2, [sp, #32] + ldp x3, x4, [sp, #48] + + /* Restore FP and LR */ + ldp x29, x30, [sp], #64 + + ret +SYM_FUNC_END(arch_bpf_timed_may_goto) diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index 9ff5cdbd2759..1b32c1232d28 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -37,6 +37,7 @@ HAS_GENERIC_AUTH_ARCH_QARMA5 HAS_GENERIC_AUTH_IMP_DEF HAS_GICV3_CPUIF HAS_GICV5_CPUIF +HAS_GICV5_LEGACY HAS_GIC_PRIO_MASKING HAS_GIC_PRIO_RELAXED_SYNC HAS_HCR_NV1 diff --git a/arch/arm64/tools/gen-sysreg.awk b/arch/arm64/tools/gen-sysreg.awk index f2a1732cb1f6..bbbb812603e8 100755 --- a/arch/arm64/tools/gen-sysreg.awk +++ b/arch/arm64/tools/gen-sysreg.awk @@ -122,6 +122,10 @@ $1 == "SysregFields" && block_current() == "Root" { res1 = "UL(0)" unkn = "UL(0)" + if (reg in defined_fields) + fatal("Duplicate SysregFields definition for " reg) + defined_fields[reg] = 1 + next_bit = 63 next @@ -162,6 +166,10 @@ $1 == "Sysreg" && block_current() == "Root" { res1 = "UL(0)" unkn = "UL(0)" + if (reg in defined_regs) + fatal("Duplicate Sysreg definition for " reg) + defined_regs[reg] = 1 + define("REG_" reg, "S" op0 "_" op1 "_C" crn "_C" crm "_" op2) define("SYS_" reg, "sys_reg(" op0 ", " op1 ", " crn ", " crm ", " op2 ")") @@ -284,6 +292,8 @@ $1 == "SignedEnum" && (block_current() == "Sysreg" || block_current() == "Sysreg define_field(reg, field, msb, lsb) define_field_sign(reg, field, "true") + delete seen_enum_vals + next } @@ -297,6 +307,8 @@ $1 == "UnsignedEnum" && (block_current() == "Sysreg" || block_current() == "Sysr define_field(reg, field, msb, lsb) define_field_sign(reg, field, "false") + delete seen_enum_vals + next } @@ -309,6 +321,8 @@ $1 == "Enum" && (block_current() == "Sysreg" || block_current() == "SysregFields define_field(reg, field, msb, lsb) + delete seen_enum_vals + next } @@ -320,6 +334,8 @@ $1 == "EndEnum" && block_current() == "Enum" { lsb = null print "" + delete seen_enum_vals + block_pop() next } @@ -329,6 +345,10 @@ $1 == "EndEnum" && block_current() == "Enum" { val = $1 name = $2 + if (val in seen_enum_vals) + fatal("Duplicate Enum value " val " for " name) + seen_enum_vals[val] = 1 + define(reg "_" field "_" name, "UL(" val ")") next } diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 696ab1f32a67..1c6cdf9d54bb 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -31,7 +31,7 @@ # Mapping <name_EL1> # EndSysreg -# Where multiple system regsiters are not VHE aliases but share a +# Where multiple system registers are not VHE aliases but share a # common layout, a SysregFields block can be used to describe the # shared layout: @@ -54,7 +54,7 @@ # # In general it is recommended that new enumeration items be named for the # feature that introduces them (eg, FEAT_LS64_ACCDATA introduces enumeration -# item ACCDATA) though it may be more taseful to do something else. +# item ACCDATA) though it may be more tasteful to do something else. Sysreg OSDTRRX_EL1 2 0 0 0 2 Res0 63:32 @@ -474,7 +474,7 @@ EndEnum Enum 7:4 Security 0b0000 NI 0b0001 EL3 - 0b0001 NSACR_RFR + 0b0010 NSACR_RFR EndEnum UnsignedEnum 3:0 ProgMod 0b0000 NI @@ -1693,7 +1693,7 @@ UnsignedEnum 43:40 TraceFilt 0b0000 NI 0b0001 IMP EndEnum -UnsignedEnum 39:36 DoubleLock +SignedEnum 39:36 DoubleLock 0b0000 IMP 0b1111 NI EndEnum @@ -2409,7 +2409,7 @@ UnsignedEnum 11:8 ASID2 0b0000 NI 0b0001 IMP EndEnum -SignedEnum 7:4 EIESB +UnsignedEnum 7:4 EIESB 0b0000 NI 0b0001 ToEL3 0b0010 ToELx @@ -2528,10 +2528,6 @@ Field 17:16 ZEN Res0 15:0 EndSysreg -Sysreg CPACR_EL12 3 5 1 0 2 -Mapping CPACR_EL1 -EndSysreg - Sysreg CPACRALIAS_EL1 3 0 1 4 4 Mapping CPACR_EL1 EndSysreg @@ -2576,10 +2572,6 @@ Sysreg PFAR_EL12 3 5 6 0 5 Mapping PFAR_EL1 EndSysreg -Sysreg RCWSMASK_EL1 3 0 13 0 3 -Field 63:0 RCWSMASK -EndSysreg - Sysreg SCTLR2_EL1 3 0 1 0 3 Res0 63:13 Field 12 CPTM0 @@ -2994,11 +2986,20 @@ Field 0 RND EndSysreg Sysreg PMSFCR_EL1 3 0 9 9 4 -Res0 63:19 +Res0 63:53 +Field 52 SIMDm +Field 51 FPm +Field 50 STm +Field 49 LDm +Field 48 Bm +Res0 47:21 +Field 20 SIMD +Field 19 FP Field 18 ST Field 17 LD Field 16 B -Res0 15:4 +Res0 15:5 +Field 4 FDS Field 3 FnE Field 2 FL Field 1 FT @@ -4756,17 +4757,53 @@ Field 37 TBI0 Field 36 AS Res0 35 Field 34:32 IPS -Field 31:30 TG1 -Field 29:28 SH1 -Field 27:26 ORGN1 -Field 25:24 IRGN1 +Enum 31:30 TG1 + 0b01 16K + 0b10 4K + 0b11 64K +EndEnum +Enum 29:28 SH1 + 0b00 NONE + 0b10 OUTER + 0b11 INNER +EndEnum +Enum 27:26 ORGN1 + 0b00 NC + 0b01 WBWA + 0b10 WT + 0b11 WBnWA +EndEnum +Enum 25:24 IRGN1 + 0b00 NC + 0b01 WBWA + 0b10 WT + 0b11 WBnWA +EndEnum Field 23 EPD1 Field 22 A1 Field 21:16 T1SZ -Field 15:14 TG0 -Field 13:12 SH0 -Field 11:10 ORGN0 -Field 9:8 IRGN0 +Enum 15:14 TG0 + 0b00 4K + 0b01 64K + 0b10 16K +EndEnum +Enum 13:12 SH0 + 0b00 NONE + 0b10 OUTER + 0b11 INNER +EndEnum +Enum 11:10 ORGN0 + 0b00 NC + 0b01 WBWA + 0b10 WT + 0b11 WBnWA +EndEnum +Enum 9:8 IRGN0 + 0b00 NC + 0b01 WBWA + 0b10 WT + 0b11 WBnWA +EndEnum Field 7 EPD0 Res0 6 Field 5:0 T0SZ |