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path: root/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
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Diffstat (limited to 'drivers/gpu/drm/sun4i/sun8i_vi_scaler.c')
-rw-r--r--drivers/gpu/drm/sun4i/sun8i_vi_scaler.c51
1 files changed, 26 insertions, 25 deletions
diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
index 82df6244af88..3dec4eeb1ba2 100644
--- a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
+++ b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
@@ -833,16 +833,17 @@ static const u32 bicubic4coefftab32[480] = {
0x1012110d, 0x1012110d, 0x1013110c, 0x1013110c,
};
-static u32 sun8i_vi_scaler_base(struct sun8i_mixer *mixer, int channel)
+static u32 sun8i_vi_scaler_base(struct sun8i_layer *layer)
{
- if (mixer->cfg->de_type == SUN8I_MIXER_DE33)
- return sun8i_channel_base(mixer, channel) + 0x3000;
- else if (mixer->cfg->de_type == SUN8I_MIXER_DE3)
+ if (layer->cfg->de_type == SUN8I_MIXER_DE33)
+ return DE33_VI_SCALER_UNIT_BASE +
+ DE33_CH_SIZE * layer->channel;
+ else if (layer->cfg->de_type == SUN8I_MIXER_DE3)
return DE3_VI_SCALER_UNIT_BASE +
- DE3_VI_SCALER_UNIT_SIZE * channel;
+ DE3_VI_SCALER_UNIT_SIZE * layer->channel;
else
return DE2_VI_SCALER_UNIT_BASE +
- DE2_VI_SCALER_UNIT_SIZE * channel;
+ DE2_VI_SCALER_UNIT_SIZE * layer->channel;
}
static int sun8i_vi_scaler_coef_index(unsigned int step)
@@ -909,11 +910,11 @@ static void sun8i_vi_scaler_set_coeff(struct regmap *map, u32 base,
}
}
-void sun8i_vi_scaler_enable(struct sun8i_mixer *mixer, int layer, bool enable)
+void sun8i_vi_scaler_enable(struct sun8i_layer *layer, bool enable)
{
u32 val, base;
- base = sun8i_vi_scaler_base(mixer, layer);
+ base = sun8i_vi_scaler_base(layer);
if (enable)
val = SUN8I_SCALER_VSU_CTRL_EN |
@@ -921,11 +922,11 @@ void sun8i_vi_scaler_enable(struct sun8i_mixer *mixer, int layer, bool enable)
else
val = 0;
- regmap_write(mixer->engine.regs,
+ regmap_write(layer->regs,
SUN8I_SCALER_VSU_CTRL(base), val);
}
-void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer,
+void sun8i_vi_scaler_setup(struct sun8i_layer *layer,
u32 src_w, u32 src_h, u32 dst_w, u32 dst_h,
u32 hscale, u32 vscale, u32 hphase, u32 vphase,
const struct drm_format_info *format)
@@ -934,7 +935,7 @@ void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer,
u32 insize, outsize;
u32 base;
- base = sun8i_vi_scaler_base(mixer, layer);
+ base = sun8i_vi_scaler_base(layer);
hphase <<= SUN8I_VI_SCALER_PHASE_FRAC - 16;
vphase <<= SUN8I_VI_SCALER_PHASE_FRAC - 16;
@@ -958,7 +959,7 @@ void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer,
cvphase = vphase;
}
- if (mixer->cfg->de_type >= SUN8I_MIXER_DE3) {
+ if (layer->cfg->de_type >= SUN8I_MIXER_DE3) {
u32 val;
if (format->hsub == 1 && format->vsub == 1)
@@ -966,36 +967,36 @@ void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer,
else
val = SUN50I_SCALER_VSU_SCALE_MODE_NORMAL;
- regmap_write(mixer->engine.regs,
+ regmap_write(layer->regs,
SUN50I_SCALER_VSU_SCALE_MODE(base), val);
}
- regmap_write(mixer->engine.regs,
+ regmap_write(layer->regs,
SUN8I_SCALER_VSU_OUTSIZE(base), outsize);
- regmap_write(mixer->engine.regs,
+ regmap_write(layer->regs,
SUN8I_SCALER_VSU_YINSIZE(base), insize);
- regmap_write(mixer->engine.regs,
+ regmap_write(layer->regs,
SUN8I_SCALER_VSU_YHSTEP(base), hscale);
- regmap_write(mixer->engine.regs,
+ regmap_write(layer->regs,
SUN8I_SCALER_VSU_YVSTEP(base), vscale);
- regmap_write(mixer->engine.regs,
+ regmap_write(layer->regs,
SUN8I_SCALER_VSU_YHPHASE(base), hphase);
- regmap_write(mixer->engine.regs,
+ regmap_write(layer->regs,
SUN8I_SCALER_VSU_YVPHASE(base), vphase);
- regmap_write(mixer->engine.regs,
+ regmap_write(layer->regs,
SUN8I_SCALER_VSU_CINSIZE(base),
SUN8I_VI_SCALER_SIZE(src_w / format->hsub,
src_h / format->vsub));
- regmap_write(mixer->engine.regs,
+ regmap_write(layer->regs,
SUN8I_SCALER_VSU_CHSTEP(base),
hscale / format->hsub);
- regmap_write(mixer->engine.regs,
+ regmap_write(layer->regs,
SUN8I_SCALER_VSU_CVSTEP(base),
vscale / format->vsub);
- regmap_write(mixer->engine.regs,
+ regmap_write(layer->regs,
SUN8I_SCALER_VSU_CHPHASE(base), chphase);
- regmap_write(mixer->engine.regs,
+ regmap_write(layer->regs,
SUN8I_SCALER_VSU_CVPHASE(base), cvphase);
- sun8i_vi_scaler_set_coeff(mixer->engine.regs, base,
+ sun8i_vi_scaler_set_coeff(layer->regs, base,
hscale, vscale, format);
}