diff options
Diffstat (limited to 'drivers/gpu/nova-core/regs.rs')
| -rw-r--r-- | drivers/gpu/nova-core/regs.rs | 91 |
1 files changed, 78 insertions, 13 deletions
diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 206dab2e1335..82cc6c0790e5 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -7,13 +7,28 @@ #[macro_use] pub(crate) mod macros; -use crate::falcon::{ - DmaTrfCmdSize, FalconCoreRev, FalconCoreRevSubversion, FalconFbifMemType, FalconFbifTarget, - FalconModSelAlgo, FalconSecurityModel, PFalcon2Base, PFalconBase, PeregrineCoreSelect, -}; -use crate::gpu::{Architecture, Chipset}; use kernel::prelude::*; +use crate::{ + falcon::{ + DmaTrfCmdSize, + FalconCoreRev, + FalconCoreRevSubversion, + FalconFbifMemType, + FalconFbifTarget, + FalconModSelAlgo, + FalconSecurityModel, + PFalcon2Base, + PFalconBase, + PeregrineCoreSelect, // + }, + gpu::{ + Architecture, + Chipset, // + }, + num::FromSafeCast, +}; + // PMC register!(NV_PMC_BOOT_0 @ 0x00000000, "Basic revision information about the GPU" { @@ -25,13 +40,24 @@ register!(NV_PMC_BOOT_0 @ 0x00000000, "Basic revision information about the GPU" }); impl NV_PMC_BOOT_0 { - /// Combines `architecture_0` and `architecture_1` to obtain the architecture of the chip. - pub(crate) fn architecture(self) -> Result<Architecture> { - Architecture::try_from( - self.architecture_0() | (self.architecture_1() << Self::ARCHITECTURE_0_RANGE.len()), - ) + pub(crate) fn is_older_than_fermi(self) -> bool { + // From https://github.com/NVIDIA/open-gpu-doc/tree/master/manuals : + const NV_PMC_BOOT_0_ARCHITECTURE_GF100: u8 = 0xc; + + // Older chips left arch1 zeroed out. That, combined with an arch0 value that is less than + // GF100, means "older than Fermi". + self.architecture_1() == 0 && self.architecture_0() < NV_PMC_BOOT_0_ARCHITECTURE_GF100 } +} +register!(NV_PMC_BOOT_42 @ 0x00000a00, "Extended architecture information" { + 15:12 minor_revision as u8, "Minor revision of the chip"; + 19:16 major_revision as u8, "Major revision of the chip"; + 23:20 implementation as u8, "Implementation version of the architecture"; + 29:24 architecture as u8 ?=> Architecture, "Architecture value"; +}); + +impl NV_PMC_BOOT_42 { /// Combines `architecture` and `implementation` to obtain a code unique to the chipset. pub(crate) fn chipset(self) -> Result<Chipset> { self.architecture() @@ -41,6 +67,24 @@ impl NV_PMC_BOOT_0 { }) .and_then(Chipset::try_from) } + + /// Returns the raw architecture value from the register. + fn architecture_raw(self) -> u8 { + ((self.0 >> Self::ARCHITECTURE_RANGE.start()) & ((1 << Self::ARCHITECTURE_RANGE.len()) - 1)) + as u8 + } +} + +impl kernel::fmt::Display for NV_PMC_BOOT_42 { + fn fmt(&self, f: &mut kernel::fmt::Formatter<'_>) -> kernel::fmt::Result { + write!( + f, + "boot42 = 0x{:08x} (architecture 0x{:x}, implementation 0x{:x})", + self.0, + self.architecture_raw(), + self.implementation() + ) + } } // PBUS @@ -71,11 +115,15 @@ register!(NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE @ 0x00100ce0 { 30:30 ecc_mode_enabled as bool; }); +register!(NV_PGSP_QUEUE_HEAD @ 0x00110c00 { + 31:0 address as u32; +}); + impl NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE { /// Returns the usable framebuffer size, in bytes. pub(crate) fn usable_fb_size(self) -> u64 { let size = (u64::from(self.lower_mag()) << u64::from(self.lower_scale())) - * kernel::sizes::SZ_1M as u64; + * u64::from_safe_cast(kernel::sizes::SZ_1M); if self.ecc_mode_enabled() { // Remove the amount of memory reserved for ECC (one per 16 units). @@ -119,6 +167,12 @@ impl NV_PFB_PRI_MMU_WPR2_ADDR_HI { // These scratch registers remain powered on even in a low-power state and have a designated group // number. +// Boot Sequence Interface (BSI) register used to determine +// if GSP reload/resume has completed during the boot process. +register!(NV_PGC6_BSI_SECURE_SCRATCH_14 @ 0x001180f8 { + 26:26 boot_stage_3_handoff as bool; +}); + // Privilege level mask register. It dictates whether the host CPU has privilege to access the // `PGC6_AON_SECURE_SCRATCH_GROUP_05` register (which it needs to read GFW_BOOT). register!(NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK @ 0x00118128, @@ -158,7 +212,7 @@ register!( impl NV_USABLE_FB_SIZE_IN_MB { /// Returns the usable framebuffer size, in bytes. pub(crate) fn usable_fb_size(self) -> u64 { - u64::from(self.value()) * kernel::sizes::SZ_1M as u64 + u64::from(self.value()) * u64::from_safe_cast(kernel::sizes::SZ_1M) } } @@ -211,6 +265,12 @@ register!(NV_PFALCON_FALCON_MAILBOX1 @ PFalconBase[0x00000044] { 31:0 value as u32; }); +// Used to store version information about the firmware running +// on the Falcon processor. +register!(NV_PFALCON_FALCON_OS @ PFalconBase[0x00000080] { + 31:0 value as u32; +}); + register!(NV_PFALCON_FALCON_RM @ PFalconBase[0x00000084] { 31:0 value as u32; }); @@ -320,7 +380,12 @@ register!(NV_PFALCON2_FALCON_BROM_PARAADDR @ PFalcon2Base[0x00000210[1]] { // PRISCV -register!(NV_PRISCV_RISCV_BCR_CTRL @ PFalconBase[0x00001668] { +register!(NV_PRISCV_RISCV_CPUCTL @ PFalcon2Base[0x00000388] { + 0:0 halted as bool; + 7:7 active_stat as bool; +}); + +register!(NV_PRISCV_RISCV_BCR_CTRL @ PFalcon2Base[0x00000668] { 0:0 valid as bool; 4:4 core_select as bool => PeregrineCoreSelect; 8:8 br_fetch as bool; |