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path: root/drivers/media/platform/qcom/camss/camss.c
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Diffstat (limited to 'drivers/media/platform/qcom/camss/camss.c')
-rw-r--r--drivers/media/platform/qcom/camss/camss.c483
1 files changed, 482 insertions, 1 deletions
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 2fbcd0e343aa..fcc2b2c3cba0 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -154,6 +154,149 @@ static const struct camss_subdev_resources vfe_res_8x16[] = {
}
};
+static const struct camss_subdev_resources csiphy_res_8x39[] = {
+ /* CSIPHY0 */
+ {
+ .regulators = { "vdda" },
+ .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" },
+ .clock_rate = { { 0 },
+ { 40000000, 80000000 },
+ { 0 },
+ { 100000000, 200000000 } },
+ .reg = { "csiphy0", "csiphy0_clk_mux" },
+ .interrupt = { "csiphy0" },
+ .csiphy = {
+ .id = 0,
+ .hw_ops = &csiphy_ops_2ph_1_0,
+ .formats = &csiphy_formats_8x16
+ }
+ },
+
+ /* CSIPHY1 */
+ {
+ .regulators = { "vdda" },
+ .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer" },
+ .clock_rate = { { 0 },
+ { 40000000, 80000000 },
+ { 0 },
+ { 100000000, 200000000 } },
+ .reg = { "csiphy1", "csiphy1_clk_mux" },
+ .interrupt = { "csiphy1" },
+ .csiphy = {
+ .id = 1,
+ .hw_ops = &csiphy_ops_2ph_1_0,
+ .formats = &csiphy_formats_8x16
+ }
+ }
+};
+
+static const struct camss_subdev_resources csid_res_8x39[] = {
+ /* CSID0 */
+ {
+ .regulators = {},
+ .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb",
+ "csi0", "csi0_phy", "csi0_pix", "csi0_rdi" },
+ .clock_rate = { { 0 },
+ { 40000000, 80000000 },
+ { 0 },
+ { 0 },
+ { 100000000, 200000000 },
+ { 0 },
+ { 0 },
+ { 0 } },
+ .reg = { "csid0" },
+ .interrupt = { "csid0" },
+ .csid = {
+ .hw_ops = &csid_ops_4_1,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_4_1
+ }
+ },
+
+ /* CSID1 */
+ {
+ .regulators = {},
+ .clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb",
+ "csi1", "csi1_phy", "csi1_pix", "csi1_rdi" },
+ .clock_rate = { { 0 },
+ { 40000000, 80000000 },
+ { 0 },
+ { 0 },
+ { 100000000, 200000000 },
+ { 0 },
+ { 0 },
+ { 0 } },
+ .reg = { "csid1" },
+ .interrupt = { "csid1" },
+ .csid = {
+ .hw_ops = &csid_ops_4_1,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_4_1
+ }
+ },
+
+ /* CSID2 */
+ {
+ .regulators = {},
+ .clock = { "top_ahb", "ispif_ahb", "csi2_ahb", "ahb",
+ "csi2", "csi2_phy", "csi2_pix", "csi2_rdi" },
+ .clock_rate = { { 0 },
+ { 40000000, 80000000 },
+ { 0 },
+ { 0 },
+ { 100000000, 200000000 },
+ { 0 },
+ { 0 },
+ { 0 } },
+ .reg = { "csid2" },
+ .interrupt = { "csid2" },
+ .csid = {
+ .hw_ops = &csid_ops_4_1,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_4_1
+ }
+ },
+};
+
+static const struct camss_subdev_resources ispif_res_8x39 = {
+ /* ISPIF */
+ .clock = { "top_ahb", "ispif_ahb", "ahb",
+ "csi0", "csi0_pix", "csi0_rdi",
+ "csi1", "csi1_pix", "csi1_rdi",
+ "csi2", "csi2_pix", "csi2_rdi" },
+ .clock_for_reset = { "vfe0", "csi_vfe0" },
+ .reg = { "ispif", "csi_clk_mux" },
+ .interrupt = { "ispif" },
+};
+
+static const struct camss_subdev_resources vfe_res_8x39[] = {
+ /* VFE0 */
+ {
+ .regulators = {},
+ .clock = { "top_ahb", "ispif_ahb", "vfe0", "csi_vfe0",
+ "vfe_ahb", "vfe_axi", "ahb" },
+ .clock_rate = { { 0 },
+ { 40000000, 80000000 },
+ { 50000000, 80000000, 100000000, 160000000,
+ 177780000, 200000000, 266670000, 320000000,
+ 400000000, 465000000, 480000000, 600000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 0 } },
+ .reg = { "vfe0" },
+ .interrupt = { "vfe0" },
+ .vfe = {
+ .line_num = 3,
+ .has_vbif = true,
+ .vbif_name = "vfe0_vbif",
+ .hw_ops = &vfe_ops_4_1,
+ .formats_rdi = &vfe_formats_rdi_8x16,
+ .formats_pix = &vfe_formats_pix_8x16
+ }
+ }
+};
+
static const struct camss_subdev_resources csid_res_8x53[] = {
/* CSID0 */
{
@@ -2617,6 +2760,317 @@ static const struct resources_icc icc_res_sm8550[] = {
},
};
+static const struct camss_subdev_resources csiphy_res_sm8650[] = {
+ /* CSIPHY0 */
+ {
+ .regulators = { "vdd-csiphy01-0p9", "vdd-csiphy01-1p2", },
+ .clock = { "csiphy0", "csiphy0_timer" },
+ .clock_rate = { { 400000000 },
+ { 400000000 } },
+ .reg = { "csiphy0" },
+ .interrupt = { "csiphy0" },
+ .csiphy = {
+ .id = 0,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845,
+ },
+ },
+ /* CSIPHY1 */
+ {
+ .regulators = { "vdd-csiphy01-0p9", "vdd-csiphy01-1p2", },
+ .clock = { "csiphy1", "csiphy1_timer" },
+ .clock_rate = { { 400000000 },
+ { 400000000 } },
+ .reg = { "csiphy1" },
+ .interrupt = { "csiphy1" },
+ .csiphy = {
+ .id = 1,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845,
+ },
+ },
+ /* CSIPHY2 */
+ {
+ .regulators = { "vdd-csiphy24-0p9", "vdd-csiphy24-1p2", },
+ .clock = { "csiphy2", "csiphy2_timer" },
+ .clock_rate = { { 400000000 },
+ { 400000000 } },
+ .reg = { "csiphy2" },
+ .interrupt = { "csiphy2" },
+ .csiphy = {
+ .id = 2,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845,
+ },
+ },
+ /* CSIPHY3 */
+ {
+ .regulators = { "vdd-csiphy35-0p9", "vdd-csiphy35-1p2", },
+ .clock = { "csiphy3", "csiphy3_timer" },
+ .clock_rate = { { 400000000 },
+ { 400000000 } },
+ .reg = { "csiphy3" },
+ .interrupt = { "csiphy3" },
+ .csiphy = {
+ .id = 3,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845,
+ },
+ },
+ /* CSIPHY4 */
+ {
+ .regulators = { "vdd-csiphy24-0p9", "vdd-csiphy24-1p2", },
+ .clock = { "csiphy4", "csiphy4_timer" },
+ .clock_rate = { { 400000000 },
+ { 400000000 } },
+ .reg = { "csiphy4" },
+ .interrupt = { "csiphy4" },
+ .csiphy = {
+ .id = 4,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845,
+ },
+ },
+ /* CSIPHY5 */
+ {
+ .regulators = { "vdd-csiphy35-0p9", "vdd-csiphy35-1p2", },
+ .clock = { "csiphy5", "csiphy5_timer" },
+ .clock_rate = { { 400000000 },
+ { 400000000 } },
+ .reg = { "csiphy5" },
+ .interrupt = { "csiphy5" },
+ .csiphy = {
+ .id = 5,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845,
+ },
+ },
+};
+
+static const struct camss_subdev_resources csid_res_sm8650[] = {
+ /* CSID0 */
+ {
+ .regulators = { },
+ .clock = { "csid", "csiphy_rx" },
+ .clock_rate = { { 400000000 },
+ { 400000000, 480000000 } },
+ .reg = { "csid0" },
+ .interrupt = { "csid0" },
+ .csid = {
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_gen3,
+ .formats = &csid_formats_gen2,
+ },
+ },
+ /* CSID1 */
+ {
+ .regulators = { },
+ .clock = { "csid", "csiphy_rx" },
+ .clock_rate = { { 400000000 },
+ { 400000000, 480000000 } },
+ .reg = { "csid1" },
+ .interrupt = { "csid1" },
+ .csid = {
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_gen3,
+ .formats = &csid_formats_gen2,
+ },
+ },
+ /* CSID2 */
+ {
+ .regulators = { },
+ .clock = { "csid", "csiphy_rx" },
+ .clock_rate = { { 400000000 },
+ { 400000000, 480000000 } },
+ .reg = { "csid2" },
+ .interrupt = { "csid2" },
+ .csid = {
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_gen3,
+ .formats = &csid_formats_gen2,
+ },
+ },
+ /* CSID3 lite */
+ {
+ .regulators = { },
+ .clock = { "vfe_lite_ahb", "vfe_lite_csid", "vfe_lite_cphy_rx" },
+ .clock_rate = { { 0 },
+ { 400000000, 480000000 },
+ { 0 } },
+ .reg = { "csid_lite0" },
+ .interrupt = { "csid_lite0" },
+ .csid = {
+ .is_lite = true,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_gen3,
+ .formats = &csid_formats_gen2,
+ },
+ },
+ /* CSID4 lite */
+ {
+ .regulators = { },
+ .clock = { "vfe_lite_ahb", "vfe_lite_csid", "vfe_lite_cphy_rx" },
+ .clock_rate = { { 0 },
+ { 400000000, 480000000 },
+ { 0 } },
+ .reg = { "csid_lite1" },
+ .interrupt = { "csid_lite1" },
+ .csid = {
+ .is_lite = true,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_gen3,
+ .formats = &csid_formats_gen2,
+ },
+ },
+};
+
+static const struct camss_subdev_resources vfe_res_sm8650[] = {
+ /* VFE0 */
+ {
+ .regulators = { },
+ .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb",
+ "camnoc_axi", "vfe0_fast_ahb", "vfe0", "cpas_vfe0",
+ "qdss_debug_xo",
+ },
+ .clock_rate = { { 0 },
+ { 80000000 },
+ { 300000000, 400000000 },
+ { 300000000, 400000000 },
+ { 0 },
+ { 466000000, 594000000, 675000000, 785000000 },
+ { 0 },
+ { 0 },
+ },
+ .reg = { "vfe0" },
+ .interrupt = { "vfe0" },
+ .vfe = {
+ .line_num = 3,
+ .has_pd = true,
+ .pd_name = "ife0",
+ .hw_ops = &vfe_ops_gen3,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ },
+ },
+ /* VFE1 */
+ {
+ .regulators = { },
+ .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb",
+ "camnoc_axi", "vfe1_fast_ahb", "vfe1", "cpas_vfe1",
+ "qdss_debug_xo",
+ },
+ .clock_rate = { { 0 },
+ { 80000000 },
+ { 300000000, 400000000 },
+ { 300000000, 400000000 },
+ { 0 },
+ { 466000000, 594000000, 675000000, 785000000 },
+ { 0 },
+ { 0 },
+ },
+ .reg = { "vfe1" },
+ .interrupt = { "vfe1" },
+ .vfe = {
+ .line_num = 3,
+ .has_pd = true,
+ .pd_name = "ife1",
+ .hw_ops = &vfe_ops_gen3,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ },
+ },
+ /* VFE2 */
+ {
+ .regulators = { },
+ .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb",
+ "camnoc_axi", "vfe2_fast_ahb", "vfe2", "cpas_vfe2",
+ "qdss_debug_xo",
+ },
+ .clock_rate = { { 0 },
+ { 80000000 },
+ { 300000000, 400000000 },
+ { 300000000, 400000000 },
+ { 0 },
+ { 466000000, 594000000, 675000000, 785000000 },
+ { 0 },
+ { 0 },
+ },
+ .reg = { "vfe2" },
+ .interrupt = { "vfe2" },
+ .vfe = {
+ .line_num = 3,
+ .has_pd = true,
+ .pd_name = "ife2",
+ .hw_ops = &vfe_ops_gen3,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ },
+ },
+ /* VFE3 lite */
+ {
+ .regulators = { },
+ .clock = { "gcc_axi_hf", "cpas_ahb", "camnoc_axi",
+ "vfe_lite_ahb", "vfe_lite", "cpas_vfe_lite",
+ "qdss_debug_xo",
+ },
+ .clock_rate = { { 0 },
+ { 80000000 },
+ { 300000000, 400000000 },
+ { 0 },
+ { 400000000, 480000000 },
+ { 0 },
+ { 0 },
+ },
+ .reg = { "vfe_lite0" },
+ .interrupt = { "vfe_lite0" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .hw_ops = &vfe_ops_gen3,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ },
+ },
+ /* VFE4 lite */
+ {
+ .regulators = { },
+ .clock = { "gcc_axi_hf", "cpas_ahb", "camnoc_axi",
+ "vfe_lite_ahb", "vfe_lite", "cpas_vfe_lite",
+ "qdss_debug_xo",
+ },
+ .clock_rate = { { 0 },
+ { 80000000 },
+ { 300000000, 400000000 },
+ { 0 },
+ { 400000000, 480000000 },
+ { 0 },
+ { 0 },
+ },
+ .reg = { "vfe_lite1" },
+ .interrupt = { "vfe_lite1" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .hw_ops = &vfe_ops_gen3,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ },
+ },
+};
+
+static const struct resources_icc icc_res_sm8650[] = {
+ {
+ .name = "ahb",
+ .icc_bw_tbl.avg = 38400,
+ .icc_bw_tbl.peak = 76800,
+ },
+ {
+ .name = "hf_mnoc",
+ .icc_bw_tbl.avg = 2097152,
+ .icc_bw_tbl.peak = 2097152,
+ },
+};
+
static const struct camss_subdev_resources csiphy_res_8300[] = {
/* CSIPHY0 */
{
@@ -4171,6 +4625,7 @@ static int camss_probe(struct platform_device *pdev)
return -ENOMEM;
if (camss->res->version == CAMSS_8x16 ||
+ camss->res->version == CAMSS_8x39 ||
camss->res->version == CAMSS_8x53 ||
camss->res->version == CAMSS_8x96) {
camss->ispif = devm_kcalloc(dev, 1, sizeof(*camss->ispif), GFP_KERNEL);
@@ -4302,6 +4757,17 @@ static const struct camss_resources msm8916_resources = {
.vfe_num = ARRAY_SIZE(vfe_res_8x16),
};
+static const struct camss_resources msm8939_resources = {
+ .version = CAMSS_8x39,
+ .csiphy_res = csiphy_res_8x39,
+ .csid_res = csid_res_8x39,
+ .ispif_res = &ispif_res_8x39,
+ .vfe_res = vfe_res_8x39,
+ .csiphy_num = ARRAY_SIZE(csiphy_res_8x39),
+ .csid_num = ARRAY_SIZE(csid_res_8x39),
+ .vfe_num = ARRAY_SIZE(vfe_res_8x39),
+};
+
static const struct camss_resources msm8953_resources = {
.version = CAMSS_8x53,
.icc_res = icc_res_8x53,
@@ -4452,6 +4918,20 @@ static const struct camss_resources sm8550_resources = {
.vfe_num = ARRAY_SIZE(vfe_res_8550),
};
+static const struct camss_resources sm8650_resources = {
+ .version = CAMSS_8650,
+ .pd_name = "top",
+ .csiphy_res = csiphy_res_sm8650,
+ .csid_res = csid_res_sm8650,
+ .csid_wrapper_res = &csid_wrapper_res_sm8550,
+ .vfe_res = vfe_res_sm8650,
+ .icc_res = icc_res_sm8650,
+ .icc_path_num = ARRAY_SIZE(icc_res_sm8650),
+ .csiphy_num = ARRAY_SIZE(csiphy_res_sm8650),
+ .csid_num = ARRAY_SIZE(csid_res_sm8650),
+ .vfe_num = ARRAY_SIZE(vfe_res_sm8650),
+};
+
static const struct camss_resources x1e80100_resources = {
.version = CAMSS_X1E80100,
.pd_name = "top",
@@ -4468,6 +4948,7 @@ static const struct camss_resources x1e80100_resources = {
static const struct of_device_id camss_dt_match[] = {
{ .compatible = "qcom,msm8916-camss", .data = &msm8916_resources },
+ { .compatible = "qcom,msm8939-camss", .data = &msm8939_resources },
{ .compatible = "qcom,msm8953-camss", .data = &msm8953_resources },
{ .compatible = "qcom,msm8996-camss", .data = &msm8996_resources },
{ .compatible = "qcom,qcm2290-camss", .data = &qcm2290_resources },
@@ -4480,6 +4961,7 @@ static const struct of_device_id camss_dt_match[] = {
{ .compatible = "qcom,sdm845-camss", .data = &sdm845_resources },
{ .compatible = "qcom,sm8250-camss", .data = &sm8250_resources },
{ .compatible = "qcom,sm8550-camss", .data = &sm8550_resources },
+ { .compatible = "qcom,sm8650-camss", .data = &sm8650_resources },
{ .compatible = "qcom,x1e80100-camss", .data = &x1e80100_resources },
{ }
};
@@ -4537,7 +5019,6 @@ static struct platform_driver qcom_camss_driver = {
module_platform_driver(qcom_camss_driver);
-MODULE_ALIAS("platform:qcom-camss");
MODULE_DESCRIPTION("Qualcomm Camera Subsystem driver");
MODULE_AUTHOR("Todor Tomov <todor.tomov@linaro.org>");
MODULE_LICENSE("GPL v2");
generated by cgit v1.2.3 (git 2.46.0) at 2025-12-04 22:12:15 +0000