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-rw-r--r--include/asm-ppc/ibm44x.h435
-rw-r--r--include/asm-ppc/ibm4xx.h18
-rw-r--r--include/asm-ppc/io.h13
-rw-r--r--include/asm-ppc/irq.h8
-rw-r--r--include/asm-ppc/mmu.h62
-rw-r--r--include/asm-ppc/page.h28
-rw-r--r--include/asm-ppc/pgalloc.h7
-rw-r--r--include/asm-ppc/pgtable.h96
-rw-r--r--include/asm-ppc/ppc_asm.h6
-rw-r--r--include/asm-ppc/processor.h159
-rw-r--r--include/asm-ppc/serial.h2
-rw-r--r--include/asm-ppc/tlbflush.h12
12 files changed, 812 insertions, 34 deletions
diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h
new file mode 100644
index 000000000000..ff6b72df2c10
--- /dev/null
+++ b/include/asm-ppc/ibm44x.h
@@ -0,0 +1,435 @@
+/*
+ * include/asm-ppc/ibm44x.h
+ *
+ * PPC44x definitions
+ *
+ * Matt Porter <mporter@mvista.com>
+ *
+ * Copyright 2002-2003 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifdef __KERNEL__
+#ifndef __ASM_IBM44x_H__
+#define __ASM_IBM44x_H__
+
+#include <linux/config.h>
+
+#ifndef __ASSEMBLY__
+/*
+ * Data structure defining board information maintained by the boot
+ * ROM on IBM's "Ebony" evaluation board. An effort has been made to
+ * keep the field names consistent with the 8xx 'bd_t' board info
+ * structures.
+ *
+ * Ebony firmware stores MAC addresses in the F/W VPD area. The
+ * firmware must store the other dynamic values in NVRAM like on
+ * the previous 40x systems so they should be accessible if we
+ * really want them.
+ */
+typedef struct board_info {
+ unsigned char bi_enetaddr[2][6]; /* EMAC addresses */
+ unsigned int bi_opb_busfreq; /* OPB clock in Hz */
+ int bi_iic_fast[2]; /* Use fast i2c mode */
+} bd_t;
+#endif /* __ASSEMBLY__ */
+
+#ifndef NR_BOARD_IRQS
+#define NR_BOARD_IRQS 0
+#endif
+
+#define _IO_BASE isa_io_base
+#define _ISA_MEM_BASE isa_mem_base
+#define PCI_DRAM_OFFSET pci_dram_offset
+
+/* TLB entry offset/size used for pinning kernel lowmem */
+#define PPC44x_PIN_SHIFT 28
+#define PPC44x_PIN_SIZE (1 << PPC44x_PIN_SHIFT)
+
+/* Lowest TLB slot consumed by the default pinned TLBs */
+#define PPC44x_LOW_SLOT 62
+
+/*
+ * Standard 4GB "page" definitions
+ */
+#define PPC44x_IO_PAGE 0x0000000100000000ULL
+#define PPC44x_PCICFG_PAGE 0x0000000200000000ULL
+#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
+#define PPC44x_PCIMEM_PAGE 0x0000000300000000ULL
+
+/*
+ * 36-bit trap ranges
+ */
+#define PPC44x_IO_LO 0x40000000
+#define PPC44x_IO_HI 0x40001000
+#define PPC44x_PCICFG_LO 0x0ec00000
+#define PPC44x_PCICFG_HI 0x0ec7ffff
+#define PPC44x_PCIMEM_LO 0x80002000
+#define PPC44x_PCIMEM_HI 0xffffffff
+
+/*
+ * The "residual" board information structure the boot loader passes
+ * into the kernel.
+ */
+#ifndef __ASSEMBLY__
+
+/*
+ * SPRN definitions
+ */
+#define SPRN_CPC0_GPIO 0xe5/BEARLRL
+
+/*
+ * DCRN definitions
+ */
+
+#ifdef CONFIG_440GX
+/* SDRs */
+#define DCRN_SDR_CONFIG_ADDR 0xe
+#define DCRN_SDR_CONFIG_DATA 0xf
+#define DCRN_SDR_PFC0 0x4100
+#define DCRN_SDR_PFC1 0x4101
+#define DCRN_SDR_MFR 0x4300
+#define DCRN_SDR_MFR_TAH0 0x80000000 /* TAHOE0 Enable */
+#define DCRN_SDR_MFR_TAH1 0x40000000 /* TAHOE1 Enable */
+#define DCRN_SDR_MFR_PCM 0x10000000 /* PPC440GP irq compat mode */
+#define DCRN_SDR_MFR_ECS 0x08000000 /* EMAC int clk */
+#define DCRN_SDR_MFR_T0TXFL 0x00080000
+#define DCRN_SDR_MFR_T0TXFH 0x00040000
+#define DCRN_SDR_MFR_T1TXFL 0x00020000
+#define DCRN_SDR_MFR_T1TXFH 0x00010000
+#define DCRN_SDR_MFR_E0TXFL 0x00008000
+#define DCRN_SDR_MFR_E0TXFH 0x00004000
+#define DCRN_SDR_MFR_E0RXFL 0x00002000
+#define DCRN_SDR_MFR_E0RXFH 0x00001000
+#define DCRN_SDR_MFR_E1TXFL 0x00000800
+#define DCRN_SDR_MFR_E1TXFH 0x00000400
+#define DCRN_SDR_MFR_E1RXFL 0x00000200
+#define DCRN_SDR_MFR_E1RXFH 0x00000100
+#define DCRN_SDR_MFR_E2TXFL 0x00000080
+#define DCRN_SDR_MFR_E2TXFH 0x00000040
+#define DCRN_SDR_MFR_E2RXFL 0x00000020
+#define DCRN_SDR_MFR_E2RXFH 0x00000010
+#define DCRN_SDR_MFR_E3TXFL 0x00000008
+#define DCRN_SDR_MFR_E3TXFH 0x00000004
+#define DCRN_SDR_MFR_E3RXFL 0x00000002
+#define DCRN_SDR_MFR_E3RXFH 0x00000001
+
+/* SDR read/write helper macros */
+#define SDR_READ(offset) ({\
+ mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
+ mfdcr(DCRN_SDR_CONFIG_DATA);})
+#define SDR_WRITE(offset, data) ({\
+ mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
+ mtdcr(DCRN_SDR_CONFIG_DATA,data);})
+#endif /* CONFIG_440GX */
+
+/* Base DCRNs */
+#define DCRN_DMA0_BASE 0x100
+#define DCRN_DMA1_BASE 0x108
+#define DCRN_DMA2_BASE 0x110
+#define DCRN_DMA3_BASE 0x118
+#define DCRN_DMASR_BASE 0x120
+#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
+#define DCRN_MAL_BASE 0x180
+
+/* UIC */
+#define DCRN_UIC0_BASE 0xc0
+#define DCRN_UIC1_BASE 0xd0
+#define UIC0 DCRN_UIC0_BASE
+#define UIC1 DCRN_UIC1_BASE
+
+#define DCRN_UIC_SR(base) (base + 0x0)
+#define DCRN_UIC_ER(base) (base + 0x2)
+#define DCRN_UIC_CR(base) (base + 0x3)
+#define DCRN_UIC_PR(base) (base + 0x4)
+#define DCRN_UIC_TR(base) (base + 0x5)
+#define DCRN_UIC_MSR(base) (base + 0x6)
+#define DCRN_UIC_VR(base) (base + 0x7)
+#define DCRN_UIC_VCR(base) (base + 0x8)
+
+#define UIC0_UIC1NC 30 /* UIC1 non-critical interrupt */
+#define UIC0_UIC1CR 31 /* UIC1 critical interrupt */
+
+/* 440GP MAL DCRs */
+#define DCRN_MALCR(base) (base + 0x0) /* Configuration */
+#define DCRN_MALESR(base) (base + 0x1) /* Error Status */
+#define DCRN_MALIER(base) (base + 0x2) /* Interrupt Enable */
+#define DCRN_MALTXCASR(base) (base + 0x4) /* Tx Channel Active Set */
+#define DCRN_MALTXCARR(base) (base + 0x5) /* Tx Channel Active Reset */
+#define DCRN_MALTXEOBISR(base) (base + 0x6) /* Tx End of Buffer Interrupt Status */
+#define DCRN_MALTXDEIR(base) (base + 0x7) /* Tx Descriptor Error Interrupt */
+#define DCRN_MALRXCASR(base) (base + 0x10) /* Rx Channel Active Set */
+#define DCRN_MALRXCARR(base) (base + 0x11) /* Rx Channel Active Reset */
+#define DCRN_MALRXEOBISR(base) (base + 0x12) /* Rx End of Buffer Interrupt Status */
+#define DCRN_MALRXDEIR(base) (base + 0x13) /* Rx Descriptor Error Interrupt */
+#define DCRN_MALTXCTP0R(base) (base + 0x20) /* Channel Tx 0 Channel Table Pointer */
+#define DCRN_MALTXCTP1R(base) (base + 0x21) /* Channel Tx 1 Channel Table Pointer */
+#define DCRN_MALTXCTP2R(base) (base + 0x22) /* Channel Tx 2 Channel Table Pointer */
+#define DCRN_MALTXCTP3R(base) (base + 0x23) /* Channel Tx 3 Channel Table Pointer */
+#define DCRN_MALRXCTP0R(base) (base + 0x40) /* Channel Rx 0 Channel Table Pointer */
+#define DCRN_MALRXCTP1R(base) (base + 0x41) /* Channel Rx 1 Channel Table Pointer */
+#define DCRN_MALRCBS0(base) (base + 0x60) /* Channel Rx 0 Channel Buffer Size */
+#define DCRN_MALRCBS1(base) (base + 0x61) /* Channel Rx 1 Channel Buffer Size */
+
+/* Compatibility DCRN's */
+#define DCRN_MALRXCTP2R(base) ((base) + 0x42) /* Channel Rx 2 Channel Table Pointer */
+#define DCRN_MALRXCTP3R(base) ((base) + 0x43) /* Channel Rx 3 Channel Table Pointer */
+#define DCRN_MALTXCTP4R(base) ((base) + 0x24) /* Channel Tx 4 Channel Table Pointer */
+#define DCRN_MALTXCTP5R(base) ((base) + 0x25) /* Channel Tx 5 Channel Table Pointer */
+#define DCRN_MALTXCTP6R(base) ((base) + 0x26) /* Channel Tx 6 Channel Table Pointer */
+#define DCRN_MALTXCTP7R(base) ((base) + 0x27) /* Channel Tx 7 Channel Table Pointer */
+#define DCRN_MALRCBS2(base) ((base) + 0x62) /* Channel Rx 2 Channel Buffer Size */
+#define DCRN_MALRCBS3(base) ((base) + 0x63) /* Channel Rx 3 Channel Buffer Size */
+
+
+#define MALCR_MMSR 0x80000000 /* MAL Software reset */
+#define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */
+#define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */
+#define MALCR_PLBP_3 0x00C00000 /* highest */
+#define MALCR_GA 0x00200000 /* Guarded Active Bit */
+#define MALCR_OA 0x00100000 /* Ordered Active Bit */
+#define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */
+#define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */
+#define MALCR_PLBLT_2 0x00020000
+#define MALCR_PLBLT_3 0x00010000
+#define MALCR_PLBLT_4 0x00008000
+#ifdef CONFIG_440GP
+#define MALCR_PLBLT_DEFAULT 0x00330000 /* PLB Latency Timer default */
+#else
+#define MALCR_PLBLT_DEFAULT 0x00ff0000 /* PLB Latency Timer default */
+#endif
+#define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */
+#define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */
+#define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */
+#define MALCR_LEA 0x00000002 /* Locked Error Active */
+#define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */
+/* DCRN_MALESR */
+#define MALESR_EVB 0x80000000 /* Error Valid Bit */
+#define MALESR_CIDRX 0x40000000 /* Channel ID Receive */
+#define MALESR_DE 0x00100000 /* Descriptor Error */
+#define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */
+#define MALESR_OTE 0x00040000 /* OPB Timeout Error */
+#define MALESR_OSE 0x00020000 /* OPB Slave Error */
+#define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */
+#define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */
+#define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */
+#define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */
+#define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */
+#define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */
+/* DCRN_MALIER */
+#define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */
+#define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */
+#define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */
+#define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */
+#define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */
+/* DCRN_MALTXEOBISR */
+#define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */
+#define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */
+
+/* 440GP PLB Arbiter DCRs */
+#define DCRN_PLB0_REVID 0x082 /* PLB Arbiter Revision ID */
+#define DCRN_PLB0_ACR 0x083 /* PLB Arbiter Control */
+#define DCRN_PLB0_BESR 0x084 /* PLB Error Status */
+#define DCRN_PLB0_BEARL 0x086 /* PLB Error Address Low */
+#define DCRN_PLB0_BEAR DCRN_PLB0_BEARL /* 40x compatibility */
+#define DCRN_PLB0_BEARH 0x087 /* PLB Error Address High */
+
+/* 440GP Clock, PM, chip control */
+#define DCRN_CPC0_SR 0x0b0
+#define DCRN_CPC0_ER 0x0b1
+#define DCRN_CPC0_FR 0x0b2
+#define DCRN_CPC0_SYS0 0x0e0
+#define DCRN_CPC0_SYS1 0x0e1
+#define DCRN_CPC0_CUST0 0x0e2
+#define DCRN_CPC0_CUST1 0x0e3
+#define DCRN_CPC0_STRP0 0x0e4
+#define DCRN_CPC0_STRP1 0x0e5
+#define DCRN_CPC0_STRP2 0x0e6
+#define DCRN_CPC0_STRP3 0x0e7
+#define DCRN_CPC0_GPIO 0x0e8
+#define DCRN_CPC0_PLB 0x0e9
+#define DCRN_CPC0_CR1 0x0ea
+#define DCRN_CPC0_CR0 0x0eb
+#define DCRN_CPC0_MIRQ0 0x0ec
+#define DCRN_CPC0_MIRQ1 0x0ed
+#define DCRN_CPC0_JTAGID 0x0ef
+
+/* 440GP DMA controller DCRs */
+#define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0) /* DMA Channel Control 0 */
+#define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count 0 */
+#define DCRN_DMASAH0 (DCRN_DMA0_BASE + 0x2) /* DMA Src Addr High 0 */
+#define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3) /* DMA Src Addr Low 0 */
+#define DCRN_DMADAH0 (DCRN_DMA0_BASE + 0x4) /* DMA Dest Addr High 0 */
+#define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x5) /* DMA Dest Addr Low 0 */
+#define DCRN_ASGH0 (DCRN_DMA0_BASE + 0x6) /* DMA SG Desc Addr High 0 */
+#define DCRN_ASG0 (DCRN_DMA0_BASE + 0x7) /* DMA SG Desc Addr Low 0 */
+
+#define DCRN_DMACR1 (DCRN_DMA1_BASE + 0x0) /* DMA Channel Control 1 */
+#define DCRN_DMACT1 (DCRN_DMA1_BASE + 0x1) /* DMA Count 1 */
+#define DCRN_DMASAH1 (DCRN_DMA1_BASE + 0x2) /* DMA Src Addr High 1 */
+#define DCRN_DMASA1 (DCRN_DMA1_BASE + 0x3) /* DMA Src Addr Low 1 */
+#define DCRN_DMADAH1 (DCRN_DMA1_BASE + 0x4) /* DMA Dest Addr High 1 */
+#define DCRN_DMADA1 (DCRN_DMA1_BASE + 0x5) /* DMA Dest Addr Low 1 */
+#define DCRN_ASGH1 (DCRN_DMA1_BASE + 0x6) /* DMA SG Desc Addr High 1 */
+#define DCRN_ASG1 (DCRN_DMA1_BASE + 0x7) /* DMA SG Desc Addr Low 1 */
+
+#define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control 2 */
+#define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count 2 */
+#define DCRN_DMASAH2 (DCRN_DMA2_BASE + 0x2) /* DMA Src Addr High 2 */
+#define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Src Addr Low 2 */
+#define DCRN_DMADAH2 (DCRN_DMA2_BASE + 0x4) /* DMA Dest Addr High 2 */
+#define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x5) /* DMA Dest Addr Low 2 */
+#define DCRN_ASGH2 (DCRN_DMA2_BASE + 0x6) /* DMA SG Desc Addr High 2 */
+#define DCRN_ASG2 (DCRN_DMA2_BASE + 0x7) /* DMA SG Desc Addr Low 2 */
+
+#define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control 3 */
+#define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count 3 */
+#define DCRN_DMASAH3 (DCRN_DMA3_BASE + 0x2) /* DMA Src Addr High 3 */
+#define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Src Addr Low 3 */
+#define DCRN_DMADAH3 (DCRN_DMA3_BASE + 0x4) /* DMA Dest Addr High 3 */
+#define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x5) /* DMA Dest Addr Low 3 */
+#define DCRN_ASGH3 (DCRN_DMA3_BASE + 0x6) /* DMA SG Desc Addr High 3 */
+#define DCRN_ASG3 (DCRN_DMA3_BASE + 0x7) /* DMA SG Desc Addr Low 3 */
+
+#define DCRN_DMASR (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */
+#define DCRN_ASGC (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */
+#define DCRN_SLP (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */
+#define DCRN_POL (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */
+
+/* 440GP DRAM controller DCRs */
+#define DCRN_SDRAM0_CFGADDR 0x010
+#define DCRN_SDRAM0_CFGDATA 0x011
+
+#define SDRAM0_B0CR 0x40
+#define SDRAM0_B1CR 0x44
+#define SDRAM0_B2CR 0x48
+#define SDRAM0_B3CR 0x4c
+
+#define SDRAM_CONFIG_BANK_ENABLE 0x00000001
+#define SDRAM_CONFIG_SIZE_MASK 0x000e0000
+#define SDRAM_CONFIG_BANK_SIZE(reg) ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17)
+#define SDRAM_CONFIG_SIZE_8M 0x00000001
+#define SDRAM_CONFIG_SIZE_16M 0x00000002
+#define SDRAM_CONFIG_SIZE_32M 0x00000003
+#define SDRAM_CONFIG_SIZE_64M 0x00000004
+#define SDRAM_CONFIG_SIZE_128M 0x00000005
+#define SDRAM_CONFIG_SIZE_256M 0x00000006
+#define SDRAM_CONFIG_SIZE_512M 0x00000007
+#define PPC44x_MEM_SIZE_8M 0x00800000
+#define PPC44x_MEM_SIZE_16M 0x01000000
+#define PPC44x_MEM_SIZE_32M 0x02000000
+#define PPC44x_MEM_SIZE_64M 0x04000000
+#define PPC44x_MEM_SIZE_128M 0x08000000
+#define PPC44x_MEM_SIZE_256M 0x10000000
+#define PPC44x_MEM_SIZE_512M 0x20000000
+
+/*
+ * PCI-X definitions
+ */
+#define PCIX0_REG_BASE 0x20ec80000ULL
+#define PCIX0_REG_SIZE 0x200
+
+#define PCIX0_VENDID 0x000
+#define PCIX0_DEVID 0x002
+#define PCIX0_COMMAND 0x004
+#define PCIX0_STATUS 0x006
+#define PCIX0_REVID 0x008
+#define PCIX0_CLS 0x009
+#define PCIX0_CACHELS 0x00c
+#define PCIX0_LATTIM 0x00d
+#define PCIX0_HDTYPE 0x00e
+#define PCIX0_BIST 0x00f
+#define PCIX0_BAR0L 0x010
+#define PCIX0_BAR0H 0x014
+#define PCIX0_BAR1 0x018
+#define PCIX0_BAR2L 0x01c
+#define PCIX0_BAR2H 0x020
+#define PCIX0_BAR3 0x024
+#define PCIX0_CISPTR 0x028
+#define PCIX0_SBSYSVID 0x02c
+#define PCIX0_SBSYSID 0x02e
+#define PCIX0_EROMBA 0x030
+#define PCIX0_CAP 0x034
+#define PCIX0_RES0 0x035
+#define PCIX0_RES1 0x036
+#define PCIX0_RES2 0x038
+#define PCIX0_INTLN 0x03c
+#define PCIX0_INTPN 0x03d
+#define PCIX0_MINGNT 0x03e
+#define PCIX0_MAXLTNCY 0x03f
+#define PCIX0_BRDGOPT1 0x040
+#define PCIX0_BRDGOPT2 0x044
+#define PCIX0_ERREN 0x050
+#define PCIX0_ERRSTS 0x054
+#define PCIX0_PLBBESR 0x058
+#define PCIX0_PLBBEARL 0x05c
+#define PCIX0_PLBBEARH 0x060
+#define PCIX0_POM0LAL 0x068
+#define PCIX0_POM0LAH 0x06c
+#define PCIX0_POM0SA 0x070
+#define PCIX0_POM0PCIAL 0x074
+#define PCIX0_POM0PCIAH 0x078
+#define PCIX0_POM1LAL 0x07c
+#define PCIX0_POM1LAH 0x080
+#define PCIX0_POM1SA 0x084
+#define PCIX0_POM1PCIAL 0x088
+#define PCIX0_POM1PCIAH 0x08c
+#define PCIX0_POM2SA 0x090
+#define PCIX0_PIM0SAL 0x098
+#define PCIX0_PIM0SA PCIX0_PIM0SAL
+#define PCIX0_PIM0LAL 0x09c
+#define PCIX0_PIM0LAH 0x0a0
+#define PCIX0_PIM1SA 0x0a4
+#define PCIX0_PIM1LAL 0x0a8
+#define PCIX0_PIM1LAH 0x0ac
+#define PCIX0_PIM2SAL 0x0b0
+#define PCIX0_PIM2SA PCIX0_PIM2SAL
+#define PCIX0_PIM2LAL 0x0b4
+#define PCIX0_PIM2LAH 0x0b8
+#define PCIX0_OMCAPID 0x0c0
+#define PCIX0_OMNIPTR 0x0c1
+#define PCIX0_OMMC 0x0c2
+#define PCIX0_OMMA 0x0c4
+#define PCIX0_OMMUA 0x0c8
+#define PCIX0_OMMDATA 0x0cc
+#define PCIX0_OMMEOI 0x0ce
+#define PCIX0_PMCAPID 0x0d0
+#define PCIX0_PMNIPTR 0x0d1
+#define PCIX0_PMC 0x0d2
+#define PCIX0_PMCSR 0x0d4
+#define PCIX0_PMCSRBSE 0x0d6
+#define PCIX0_PMDATA 0x0d7
+#define PCIX0_PMSCRR 0x0d8
+#define PCIX0_CAPID 0x0dc
+#define PCIX0_NIPTR 0x0dd
+#define PCIX0_CMD 0x0de
+#define PCIX0_STS 0x0e0
+#define PCIX0_IDR 0x0e4
+#define PCIX0_CID 0x0e8
+#define PCIX0_RID 0x0ec
+#define PCIX0_PIM0SAH 0x0f8
+#define PCIX0_PIM2SAH 0x0fc
+#define PCIX0_MSGIL 0x100
+#define PCIX0_MSGIH 0x104
+#define PCIX0_MSGOL 0x108
+#define PCIX0_MSGOH 0x10c
+#define PCIX0_IM 0x1f8
+
+#define IIC_OWN 0x55
+#define IIC_CLOCK 50
+
+#undef NR_UICS
+#define NR_UICS 2
+#define UIC_CASCADE_MASK 0x0003 /* bits 30 & 31 */
+
+#define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i]
+
+#include <asm/ibm4xx.h>
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_IBM44x_H__ */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/ibm4xx.h b/include/asm-ppc/ibm4xx.h
index 4884067dbcd9..c8da43c8512f 100644
--- a/include/asm-ppc/ibm4xx.h
+++ b/include/asm-ppc/ibm4xx.h
@@ -122,7 +122,25 @@ void ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5,
#define PCI_DRAM_OFFSET 0
#endif
+#elif CONFIG_44x
+
+#if defined(CONFIG_EBONY)
+#include <platforms/4xx/ebony.h>
+#endif
+
+#if defined(CONFIG_OCOTEA)
+#include <platforms/4xx/ocotea.h>
+#endif
#endif /* CONFIG_40x */
+
+#ifndef __ASSEMBLY__
+/*
+ * The "residual" board information structure the boot loader passes
+ * into the kernel.
+ */
+extern bd_t __res;
+#endif
+
#endif /* __ASM_IBM4XX_H__ */
#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h
index b67f27323f46..55e67291c3d2 100644
--- a/include/asm-ppc/io.h
+++ b/include/asm-ppc/io.h
@@ -4,9 +4,11 @@
#include <linux/config.h>
#include <linux/types.h>
+#include <linux/mm.h>
#include <asm/page.h>
#include <asm/byteorder.h>
+#include <asm/mmu.h>
#define SIO_CONFIG_RA 0x398
#define SIO_CONFIG_RD 0x399
@@ -22,7 +24,7 @@
#define PREP_ISA_MEM_BASE 0xc0000000
#define PREP_PCI_DRAM_OFFSET 0x80000000
-#if defined(CONFIG_40x)
+#if defined(CONFIG_4xx)
#include <asm/ibm4xx.h>
#elif defined(CONFIG_8xx)
#include <asm/mpc8xx.h>
@@ -197,14 +199,17 @@ extern void _outsl_ns(volatile u32 *port, const void *buf, int nl);
* Map in an area of physical address space, for accessing
* I/O devices etc.
*/
-extern void *__ioremap(unsigned long address, unsigned long size,
+extern void *__ioremap(phys_addr_t address, unsigned long size,
unsigned long flags);
-extern void *ioremap(unsigned long address, unsigned long size);
+extern void *ioremap(phys_addr_t address, unsigned long size);
+#ifdef CONFIG_44x
+extern void *ioremap64(unsigned long long address, unsigned long size);
+#endif
#define ioremap_nocache(addr, size) ioremap((addr), (size))
extern void iounmap(void *addr);
extern unsigned long iopa(unsigned long addr);
extern unsigned long mm_ptov(unsigned long addr) __attribute__ ((const));
-extern void io_block_mapping(unsigned long virt, unsigned long phys,
+extern void io_block_mapping(unsigned long virt, phys_addr_t phys,
unsigned int size, int flags);
/*
diff --git a/include/asm-ppc/irq.h b/include/asm-ppc/irq.h
index 6ca586ab8f4e..02b993f6c3c7 100644
--- a/include/asm-ppc/irq.h
+++ b/include/asm-ppc/irq.h
@@ -71,11 +71,11 @@ irq_canonicalize(int irq)
return (irq);
}
-#elif defined(CONFIG_440)
-#include <asm/ibm440.h>
+#elif defined(CONFIG_44x)
+#include <asm/ibm44x.h>
-#define NR_UIC_IRQS 64
-#define NR_IRQS (NR_UIC_IRQS + NR_BOARD_IRQS)
+#define NR_UIC_IRQS 32
+#define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
static __inline__ int
irq_canonicalize(int irq)
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index 7b729cdf52f4..b75b24e4c056 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -10,6 +10,18 @@
#ifndef __ASSEMBLY__
+/*
+ * Define physical address type. Machines using split size
+ * virtual/physical addressing like 32-bit virtual / 36-bit
+ * physical need a larger than native word size type. -Matt
+ */
+#ifndef CONFIG_PTE_64BIT
+typedef unsigned long phys_addr_t;
+#else
+typedef unsigned long long phys_addr_t;
+extern phys_addr_t fixup_bigphys_addr(phys_addr_t, phys_addr_t);
+#endif
+
/* Default "unsigned long" context */
typedef unsigned long mm_context_t;
@@ -320,5 +332,55 @@ typedef struct _P601_BAT {
#define TLB_M 0x00000002 /* Memory is coherent */
#define TLB_G 0x00000001 /* Memory is guarded from prefetch */
+/*
+ * PPC440 support
+ */
+#define PPC44x_MMUCR_TID 0x000000ff
+#define PPC44x_MMUCR_STS 0x00010000
+
+#define PPC44x_TLB_PAGEID 0
+#define PPC44x_TLB_XLAT 1
+#define PPC44x_TLB_ATTRIB 2
+
+/* Page identification fields */
+#define PPC44x_TLB_EPN_MASK 0xfffffc00 /* Effective Page Number */
+#define PPC44x_TLB_VALID 0x00000200 /* Valid flag */
+#define PPC44x_TLB_TS 0x00000100 /* Translation address space */
+#define PPC44x_TLB_PAGESZ_MASK 0x000000f0
+#define PPC44x_TLB_PAGESZ(x) (x << 4)
+#define PPC44x_PAGESZ_1K 0
+#define PPC44x_PAGESZ_4K 1
+#define PPC44x_PAGESZ_16K 2
+#define PPC44x_PAGESZ_64K 3
+#define PPC44x_PAGESZ_256K 4
+#define PPC44x_PAGESZ_1M 5
+#define PPC44x_PAGESZ_16M 7
+#define PPC44x_PAGESZ_256M 9
+
+/* Translation fields */
+#define PPC44x_TLB_RPN_MASK 0xfffffc00 /* Real Page Number */
+#define PPC44x_TLB_ERPN_MASK 0x0000000f
+
+/* Storage attribute and access control fields */
+#define PPC44x_TLB_ATTR_MASK 0x0000ff80
+#define PPC44x_TLB_U0 0x00008000 /* User 0 */
+#define PPC44x_TLB_U1 0x00004000 /* User 1 */
+#define PPC44x_TLB_U2 0x00002000 /* User 2 */
+#define PPC44x_TLB_U3 0x00001000 /* User 3 */
+#define PPC44x_TLB_W 0x00000800 /* Caching is write-through */
+#define PPC44x_TLB_I 0x00000400 /* Caching is inhibited */
+#define PPC44x_TLB_M 0x00000200 /* Memory is coherent */
+#define PPC44x_TLB_G 0x00000100 /* Memory is guarded */
+#define PPC44x_TLB_E 0x00000080 /* Memory is guarded */
+
+#define PPC44x_TLB_PERM_MASK 0x0000003f
+#define PPC44x_TLB_UX 0x00000020 /* User execution */
+#define PPC44x_TLB_UW 0x00000010 /* User write */
+#define PPC44x_TLB_UR 0x00000008 /* User read */
+#define PPC44x_TLB_SX 0x00000004 /* Super execution */
+#define PPC44x_TLB_SW 0x00000002 /* Super write */
+#define PPC44x_TLB_SR 0x00000001 /* Super read */
+
+
#endif /* _PPC_MMU_H_ */
#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/page.h b/include/asm-ppc/page.h
index b8f25854778d..6d2a8a40368f 100644
--- a/include/asm-ppc/page.h
+++ b/include/asm-ppc/page.h
@@ -4,7 +4,12 @@
/* PAGE_SHIFT determines the page size */
#define PAGE_SHIFT 12
#define PAGE_SIZE (1UL << PAGE_SHIFT)
-#define PAGE_MASK (~(PAGE_SIZE-1))
+
+/*
+ * Subtle: this is an int (not an unsigned long) and so it
+ * gets extended to 64 bits the way want (i.e. with 1s). -- paulus
+ */
+#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1))
#ifdef __KERNEL__
#include <linux/config.h>
@@ -15,13 +20,27 @@
#ifndef __ASSEMBLY__
-#define STRICT_MM_TYPECHECKS
+/*
+ * The basic type of a PTE - 64 bits for those CPUs with > 32 bit
+ * physical addressing. For now this just the IBM PPC440.
+ */
+#ifdef CONFIG_PTE_64BIT
+typedef unsigned long long pte_basic_t;
+#define PTE_SHIFT (PAGE_SHIFT - 3) /* 512 ptes per page */
+#define PTE_FMT "%16Lx"
+#else
+typedef unsigned long pte_basic_t;
+#define PTE_SHIFT (PAGE_SHIFT - 2) /* 1024 ptes per page */
+#define PTE_FMT "%.8lx"
+#endif
+
+#undef STRICT_MM_TYPECHECKS
#ifdef STRICT_MM_TYPECHECKS
/*
* These are used to make use of C type-checking..
*/
-typedef struct { unsigned long pte; } pte_t;
+typedef struct { pte_basic_t pte; } pte_t;
typedef struct { unsigned long pmd; } pmd_t;
typedef struct { unsigned long pgd; } pgd_t;
typedef struct { unsigned long pgprot; } pgprot_t;
@@ -40,7 +59,7 @@ typedef struct { unsigned long pgprot; } pgprot_t;
/*
* .. while these make it easier on the compiler
*/
-typedef unsigned long pte_t;
+typedef pte_basic_t pte_t;
typedef unsigned long pmd_t;
typedef unsigned long pgd_t;
typedef unsigned long pgprot_t;
@@ -123,6 +142,7 @@ static inline void* ___va(unsigned long p)
#define pfn_to_page(pfn) (mem_map + ((pfn) - PPC_PGSTART))
#define page_to_pfn(page) ((unsigned long)((page) - mem_map) + PPC_PGSTART)
#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
+#define page_to_virt(page) __va(page_to_pfn(page) << PAGE_SHIFT)
#define pfn_valid(pfn) (((pfn) - PPC_PGSTART) < max_mapnr)
#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
diff --git a/include/asm-ppc/pgalloc.h b/include/asm-ppc/pgalloc.h
index 7d5d0455cc00..faf91bc03022 100644
--- a/include/asm-ppc/pgalloc.h
+++ b/include/asm-ppc/pgalloc.h
@@ -20,10 +20,17 @@ extern void pgd_free(pgd_t *pgd);
#define __pmd_free_tlb(tlb,x) do { } while (0)
#define pgd_populate(mm, pmd, pte) BUG()
+#ifndef CONFIG_BOOKE
#define pmd_populate_kernel(mm, pmd, pte) \
(pmd_val(*(pmd)) = __pa(pte) | _PMD_PRESENT)
#define pmd_populate(mm, pmd, pte) \
(pmd_val(*(pmd)) = (page_to_pfn(pte) << PAGE_SHIFT) | _PMD_PRESENT)
+#else
+#define pmd_populate_kernel(mm, pmd, pte) \
+ (pmd_val(*(pmd)) = (unsigned long)pte | _PMD_PRESENT)
+#define pmd_populate(mm, pmd, pte) \
+ (pmd_val(*(pmd)) = (unsigned long)page_to_virt(pte) | _PMD_PRESENT)
+#endif
extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr);
extern struct page *pte_alloc_one(struct mm_struct *mm, unsigned long addr);
diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h
index 73a8f18d22cf..0399c8cfbcab 100644
--- a/include/asm-ppc/pgtable.h
+++ b/include/asm-ppc/pgtable.h
@@ -65,13 +65,23 @@ extern unsigned long ioremap_bot, ioremap_base;
* and ITLB, respectively (see "mmu.h" for definitions).
*/
-/* PMD_SHIFT determines the size of the area mapped by the second-level page tables */
-#define PMD_SHIFT 22
+/*
+ * The normal case is that PTEs are 32-bits and we have a 1-page
+ * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
+ *
+ * For any >32-bit physical address platform, we can use the following
+ * two level page table layout where the pgdir is 8KB and the MS 13 bits
+ * are an index to the second level table. The combined pgdir/pmd first
+ * level has 2048 entries and the second level has 512 64-bit PTE entries.
+ * -Matt
+ */
+/* PMD_SHIFT determines the size of the area mapped by the PTE pages */
+#define PMD_SHIFT (PAGE_SHIFT + PTE_SHIFT)
#define PMD_SIZE (1UL << PMD_SHIFT)
#define PMD_MASK (~(PMD_SIZE-1))
-/* PGDIR_SHIFT determines what a third-level page table entry can map */
-#define PGDIR_SHIFT 22
+/* PGDIR_SHIFT determines what a top-level page table entry can map */
+#define PGDIR_SHIFT PMD_SHIFT
#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
#define PGDIR_MASK (~(PGDIR_SIZE-1))
@@ -79,9 +89,10 @@ extern unsigned long ioremap_bot, ioremap_base;
* entries per page directory level: our page-table tree is two-level, so
* we don't really have any PMD directory.
*/
-#define PTRS_PER_PTE 1024
+#define PTRS_PER_PTE (1 << PTE_SHIFT)
#define PTRS_PER_PMD 1
-#define PTRS_PER_PGD 1024
+#define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT))
+
#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
#define FIRST_USER_PGD_NR 0
@@ -89,7 +100,7 @@ extern unsigned long ioremap_bot, ioremap_base;
#define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
#define pte_ERROR(e) \
- printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
+ printk("%s:%d: bad pte "PTE_FMT".\n", __FILE__, __LINE__, pte_val(e))
#define pmd_ERROR(e) \
printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
#define pgd_ERROR(e) \
@@ -113,7 +124,11 @@ extern unsigned long ioremap_bot, ioremap_base;
* of RAM. -- Cort
*/
#define VMALLOC_OFFSET (0x1000000) /* 16M */
+#ifdef CONFIG_44x
+#define VMALLOC_START (((_ALIGN((long)high_memory, PPC44x_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
+#else
#define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
+#endif
#define VMALLOC_VMADDR(x) ((unsigned long)(x))
#define VMALLOC_END ioremap_bot
@@ -170,6 +185,44 @@ extern unsigned long ioremap_bot, ioremap_base;
#define _PMD_SIZE_16M 0x0e0
#define PMD_PAGE_SIZE(pmdval) (1024 << (((pmdval) & _PMD_SIZE) >> 4))
+#elif defined(CONFIG_44x)
+/*
+ * Definitions for PPC440
+ *
+ * Because of the 3 word TLB entries to support 36-bit addressing,
+ * the attribute are difficult to map in such a fashion that they
+ * are easily loaded during exception processing. I decided to
+ * organize the entry so the ERPN is the only portion in the
+ * upper word of the PTE and the attribute bits below are packed
+ * in as sensibly as they can be in the area below a 4KB page size
+ * oriented RPN. This at least makes it easy to load the RPN and
+ * ERPN fields in the TLB. -Matt
+ *
+ * Note that these bits preclude future use of a page size
+ * less than 4KB.
+ */
+#define _PAGE_PRESENT 0x00000001 /* S: PTE valid */
+#define _PAGE_RW 0x00000002 /* S: Write permission */
+#define _PAGE_DIRTY 0x00000004 /* S: Page dirty */
+#define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */
+#define _PAGE_HWWRITE 0x00000010 /* H: Dirty & RW */
+#define _PAGE_HWEXEC 0x00000020 /* H: Execute permission */
+#define _PAGE_USER 0x00000040 /* S: User page */
+#define _PAGE_ENDIAN 0x00000080 /* H: E bit */
+#define _PAGE_GUARDED 0x00000100 /* H: G bit */
+#define _PAGE_COHERENT 0x00000200 /* H: M bit */
+#define _PAGE_FILE 0x00000400 /* S: nonlinear file mapping */
+#define _PAGE_NO_CACHE 0x00000400 /* H: I bit */
+#define _PAGE_WRITETHRU 0x00000800 /* H: W bit */
+
+/* TODO: Add large page lowmem mapping support */
+#define _PMD_PRESENT 0
+#define _PMD_PRESENT_MASK (PAGE_MASK)
+#define _PMD_BAD (~PAGE_MASK)
+
+/* ERPN in a PTE never gets cleared, ignore it */
+#define _PTE_NONE_MASK 0xffffffff00000000ULL
+
#elif defined(CONFIG_8xx)
/* Definitions for 8xx embedded chips. */
#define _PAGE_PRESENT 0x0001 /* Page is valid */
@@ -270,7 +323,11 @@ extern unsigned long ioremap_bot, ioremap_base;
#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED)
#define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE)
+#ifndef CONFIG_44x
#define _PAGE_KERNEL (_PAGE_BASE | _PAGE_SHARED | _PAGE_WRENABLE)
+#else
+#define _PAGE_KERNEL (_PAGE_BASE | _PAGE_SHARED | _PAGE_WRENABLE | _PAGE_GUARDED)
+#endif
#ifdef CONFIG_PPC_STD_MMU
/* On standard PPC MMU, no user access implies kernel read/write access,
@@ -283,7 +340,7 @@ extern unsigned long ioremap_bot, ioremap_base;
#define _PAGE_IO (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED)
#define _PAGE_RAM (_PAGE_KERNEL | _PAGE_HWEXEC)
-#if defined(CONFIG_KGDB) || defined(CONFIG_XMON)
+#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH)
/* We want the debuggers to be able to set breakpoints anywhere, so
* don't write protect the kernel text */
#define _PAGE_RAM_TEXT _PAGE_RAM
@@ -420,6 +477,8 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
*
* pte_update clears and sets bit atomically, and returns
* the old pte value.
+ * The ((unsigned long)(p+1) - 4) hack is to get to the least-significant
+ * 32 bits of the PTE regardless of whether PTEs are 32 or 64 bits.
*/
static inline unsigned long pte_update(pte_t *p, unsigned long clr,
unsigned long set)
@@ -434,7 +493,7 @@ static inline unsigned long pte_update(pte_t *p, unsigned long clr,
" stwcx. %1,0,%3\n\
bne- 1b"
: "=&r" (old), "=&r" (tmp), "=m" (*p)
- : "r" (p), "r" (clr), "r" (set), "m" (*p)
+ : "r" ((unsigned long)(p+1) - 4), "r" (clr), "r" (set), "m" (*p)
: "cc" );
return old;
}
@@ -485,11 +544,25 @@ static inline void ptep_mkdirty(pte_t *ptep)
#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
+/*
+ * Note that on Book E processors, the pmd contains the kernel virtual
+ * (lowmem) address of the pte page. The physical address is less useful
+ * because everything runs with translation enabled (even the TLB miss
+ * handler). On everything else the pmd contains the physical address
+ * of the pte page. -- paulus
+ */
+#ifndef CONFIG_BOOKE
#define pmd_page_kernel(pmd) \
((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
#define pmd_page(pmd) \
(mem_map + (pmd_val(pmd) >> PAGE_SHIFT))
-
+#else
+#define pmd_page_kernel(pmd) \
+ ((unsigned long) (pmd_val(pmd) & PAGE_MASK))
+#define pmd_page(pmd) \
+ (mem_map + (__pa(pmd_val(pmd)) >> PAGE_SHIFT))
+#endif
+
/* to find an entry in a kernel page-table-directory */
#define pgd_offset_k(address) pgd_offset(&init_mm, address)
@@ -516,7 +589,8 @@ static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
#define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0)
#define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1)
-extern pgd_t swapper_pg_dir[1024];
+extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
+
extern void paging_init(void);
/*
diff --git a/include/asm-ppc/ppc_asm.h b/include/asm-ppc/ppc_asm.h
index 39049bcac7fc..afd99032491c 100644
--- a/include/asm-ppc/ppc_asm.h
+++ b/include/asm-ppc/ppc_asm.h
@@ -107,7 +107,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
bdnz 0b
#endif
-#if !defined(CONFIG_440)
+#if !defined(CONFIG_44x)
/*
* On APUS (Amiga PowerPC cpu upgrade board), we don't know the
* physical base address of RAM at compile time.
@@ -125,7 +125,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
.align 1; \
.long 0b; \
.previous
-#else /* CONFIG_440 */
+#else /* CONFIG_44x */
#define tophys(rd,rs) \
mr rd,rs
@@ -133,7 +133,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
#define tovirt(rd,rs) \
mr rd,rs
-#endif /* CONFIG_440 */
+#endif /* CONFIG_44x */
/*
* On 64-bit cpus, we use the rfid instruction instead of rfi, but
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 21c2c819b98f..e13d0a0b1f45 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -3,6 +3,12 @@
#define __ASM_PPC_PROCESSOR_H
/*
+ * The Book E definitions are hacked into here for 440 right
+ * now. This whole thing needs regorganized (maybe two files)
+ * so that it becomes readable. -Matt
+ */
+
+/*
* Default implementation of macro that returns current
* instruction pointer ("program counter").
*/
@@ -45,6 +51,11 @@
#define MSR_RI (1<<1) /* Recoverable Exception */
#define MSR_LE (1<<0) /* Little Endian */
+#ifdef CONFIG_BOOKE
+#define MSR_IS MSR_IR /* Instruction Space */
+#define MSR_DS MSR_DR /* Data Space */
+#endif
+
#ifdef CONFIG_APUS_FAST_EXCEPT
#define MSR_ (MSR_ME|MSR_IP|MSR_RI)
#else
@@ -93,8 +104,13 @@
#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
#define SPRN_CTR 0x009 /* Count Register */
#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
+#ifndef CONFIG_BOOKE
#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
+#else
+#define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */
+#define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */
+#endif /* CONFIG_BOOKE */
#define SPRN_DAR 0x013 /* Data Address Register */
#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
@@ -146,7 +162,11 @@
#define DBCR_SDA 0x00000004 /* Second DAC Enable */
#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
+#ifndef CONFIG_BOOKE
#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
+#else
+#define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */
+#endif /* CONFIG_BOOKE */
#define DBCR0_EDM 0x80000000 /* External Debug Mode */
#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */
#define DBCR0_RST 0x30000000 /* all the bits in the RST field */
@@ -169,11 +189,18 @@
#define DBCR0_IA12T 0x00008000 /* Instr Addr 1-2 range Toggle */
#define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */
#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
+#ifndef CONFIG_BOOKE
#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
#define SPRN_DBSR 0x3F0 /* Debug Status Register */
#define DBSR_IC 0x80000000 /* Instruction Completion */
#define DBSR_BT 0x40000000 /* Branch taken */
#define DBSR_TIE 0x10000000 /* Trap Instruction debug Event */
+#else
+#define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */
+#define SPRN_DBSR 0x130 /* Book E Debug Status Register */
+#define DBSR_IC 0x08000000 /* Book E Instruction Completion */
+#define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */
+#endif /* CONFIG_BOOKE */
#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
#define DCCR_NOCACHE 0 /* Noncacheable */
#define DCCR_CACHE 1 /* Cacheable */
@@ -181,7 +208,11 @@
#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
#define DCWR_COPY 0 /* Copy-back */
#define DCWR_WRITE 1 /* Write-through */
+#ifndef CONFIG_BOOKE
#define SPRN_DEAR 0x3D5 /* Data Error Address Register */
+#else
+#define SPRN_DEAR 0x03D /* Book E Data Error Address Register */
+#endif /* CONFIG_BOOKE */
#define SPRN_DEC 0x016 /* Decrement Register */
#define SPRN_DER 0x095 /* Debug Enable Regsiter */
#define DER_RSTE 0x40000000 /* Reset Interrupt */
@@ -206,12 +237,16 @@
#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
#define SPRN_EAR 0x11A /* External Address Register */
+#ifndef CONFIG_BOOKE
#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
+#else
+#define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */
+#endif /* CONFIG_BOOKE */
#define ESR_MCI 0x80000000 /* 405 Machine Check - Instruction */
-#define ESR_IMCP 0x80000000 /* 403 Inst. Mach. Check - Protection */
-#define ESR_IMCN 0x40000000 /* 403 Inst. Mach. Check - Non-config */
-#define ESR_IMCB 0x20000000 /* 403 Inst. Mach. Check - Bus error */
-#define ESR_IMCT 0x10000000 /* 403 Inst. Mach. Check - Timeout */
+#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
+#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
+#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
+#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
#define ESR_PIL 0x08000000 /* Program Exception - Illegal */
#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */
#define ESR_PTR 0x02000000 /* Program Exception - Trap */
@@ -266,8 +301,13 @@
#define HID1_SYNCBE (1<<11) /* 7450 ABE for sync, eieio */
#define HID1_ABE (1<<10) /* 7450 Address Broadcast Enable */
#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
+#ifndef CONFIG_BOOKE
#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
+#else
+#define SPRN_IAC1 0x138 /* Book E Instruction Address Compare 1 */
+#define SPRN_IAC2 0x139 /* Book E Instruction Address Compare 2 */
+#endif /* CONFIG_BOOKE */
#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */
#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */
#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */
@@ -358,8 +398,13 @@
#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */
+#ifndef CONFIG_BOOKE
#define SPRN_PID 0x3B1 /* Process ID */
#define SPRN_PIR 0x3FF /* Processor Identification Register */
+#else
+#define SPRN_PID 0x030 /* Book E Process ID */
+#define SPRN_PIR 0x11E /* Book E Processor Identification Register */
+#endif /* CONFIG_BOOKE */
#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
#define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */
#define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */
@@ -375,6 +420,7 @@
#define SGR_NORMAL 0
#define SGR_GUARDED 1
#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
+#define SPRN_SLER 0x3BB /* Little-endian real mode */
#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
@@ -387,6 +433,7 @@
#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
+#define SPRN_SU0R 0x3BC /* "User 0" real mode */
#define SPRN_TBHI 0x3DC /* Time Base High (4xx) */
#define SPRN_TBHU 0x3CC /* Time Base High User-mode (4xx) */
#define SPRN_TBLO 0x3DD /* Time Base Low (4xx) */
@@ -395,7 +442,11 @@
#define SPRN_TBRU 0x10D /* Time Base Read Upper Register (user, R/O) */
#define SPRN_TBWL 0x11C /* Time Base Lower Register (super, R/W) */
#define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */
+#ifndef CONFIG_BOOKE
#define SPRN_TCR 0x3DA /* Timer Control Register */
+#else
+#define SPRN_TCR 0x154 /* Book E Timer Control Register */
+#endif
#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
#define TCR_WP_MASK TCR_WP(3)
#define WP_2_17 0 /* 2^17 clocks */
@@ -410,6 +461,7 @@
#define WRC_SYSTEM 3 /* System reset will occur */
#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
+#define TCR_DIE TCR_PIE /* DEC Interrupt Enable */
#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */
#define TCR_FP_MASK TCR_FP(3)
#define FP_2_9 0 /* 2^9 clocks */
@@ -431,7 +483,11 @@
#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
#define THRM3_E (1<<0)
#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
+#ifndef CONFIG_BOOKE
#define SPRN_TSR 0x3D8 /* Timer Status Register */
+#else
+#define SPRN_TSR 0x150 /* Book E Timer Status Register */
+#endif /* CONFIG_BOOKE */
#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
#define TSR_WIS 0x40000000 /* WDT Interrupt Status */
#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
@@ -440,6 +496,7 @@
#define WRS_CHIP 2 /* WDT forced chip reset */
#define WRS_SYSTEM 3 /* WDT forced system reset */
#define TSR_PIS 0x08000000 /* PIT Interrupt Status */
+#define TSR_DIS TSR_PIS /* DEC Interrupt Status */
#define TSR_FIS 0x04000000 /* FIT Interrupt Status */
#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
@@ -452,6 +509,45 @@
#define SPRN_XER 0x001 /* Fixed Point Exception Register */
#define SPRN_ZPR 0x3B0 /* Zone Protection Register */
+/* Book E definitions */
+#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
+#define SPRN_CSRR0 0x03A /* Critical Save and Restore Register 0 */
+#define SPRN_CSRR1 0x03B /* Critical Save and Restore Register 1 */
+#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
+#define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
+#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
+#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
+#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
+#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
+#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
+#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */
+#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */
+#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */
+#define SPRN_DBCR2 0x136 /* Debug Control Register 2 */
+#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */
+#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */
+#define SPRN_DVC1 0x13E /* */
+#define SPRN_DVC2 0x13F /* */
+#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */
+#define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */
+#define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */
+#define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */
+#define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */
+#define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */
+#define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */
+#define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */
+#define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */
+#define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */
+#define SPRN_IVOR10 0x19a /* Interrupt Vector Offset Register 10 */
+#define SPRN_IVOR11 0x19b /* Interrupt Vector Offset Register 11 */
+#define SPRN_IVOR12 0x19c /* Interrupt Vector Offset Register 12 */
+#define SPRN_IVOR13 0x19d /* Interrupt Vector Offset Register 13 */
+#define SPRN_IVOR14 0x19e /* Interrupt Vector Offset Register 14 */
+#define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */
+#define SPRN_MMUCR 0x3b2 /* MMU Control Register */
+
+#define ESR_ST 0x00800000 /* Store Operation */
+
/* Short-hand versions for a number of the above SPRNs */
#define CTR SPRN_CTR /* Counter Register */
@@ -524,6 +620,16 @@
#define SPRG5 SPRN_SPRG5
#define SPRG6 SPRN_SPRG6
#define SPRG7 SPRN_SPRG7
+#define SPRG4R SPRN_SPRG4R /* Book E Supervisor Private Registers */
+#define SPRG5R SPRN_SPRG5R
+#define SPRG6R SPRN_SPRG6R
+#define SPRG7R SPRN_SPRG7R
+#define SPRG4W SPRN_SPRG4W
+#define SPRG5W SPRN_SPRG5W
+#define SPRG6W SPRN_SPRG6W
+#define SPRG7W SPRN_SPRG7W
+#define CSRR0 SPRN_CSRR0 /* Critical Save and Restore Register 0 */
+#define CSRR1 SPRN_CSRR1 /* Critical Save and Restore Register 1 */
#define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */
#define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */
#define SRR2 SPRN_SRR2 /* Save and Restore Register 2 */
@@ -557,6 +663,51 @@
#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
+/* Processor Version Numbers */
+
+#define PVR_403GA 0x00200000
+#define PVR_403GB 0x00200100
+#define PVR_403GC 0x00200200
+#define PVR_403GCX 0x00201400
+#define PVR_405GP 0x40110000
+#define PVR_STB03XXX 0x40310000
+#define PVR_NP405H 0x41410000
+#define PVR_NP405L 0x41610000
+#define PVR_440GP_RB 0x40120440
+#define PVR_440GP_RC1 0x40120481
+#define PVR_440GP_RC2 0x40200481
+#define PVR_440GX_RC1 0x51b21850
+#define PVR_601 0x00010000
+#define PVR_602 0x00050000
+#define PVR_603 0x00030000
+#define PVR_603e 0x00060000
+#define PVR_603ev 0x00070000
+#define PVR_603r 0x00071000
+#define PVR_604 0x00040000
+#define PVR_604e 0x00090000
+#define PVR_604r 0x000A0000
+#define PVR_620 0x00140000
+#define PVR_740 0x00080000
+#define PVR_750 PVR_740
+#define PVR_740P 0x10080000
+#define PVR_750P PVR_740P
+#define PVR_7400 0x000C0000
+#define PVR_7410 0x800C0000
+#define PVR_7450 0x80000000
+/*
+ * For the 8xx processors, all of them report the same PVR family for
+ * the PowerPC core. The various versions of these processors must be
+ * differentiated by the version number in the Communication Processor
+ * Module (CPM).
+ */
+#define PVR_821 0x00500000
+#define PVR_823 PVR_821
+#define PVR_850 PVR_821
+#define PVR_860 PVR_821
+#define PVR_8240 0x00810100
+#define PVR_8245 0x80811014
+#define PVR_8260 PVR_8240
+
/* We only need to define a new _MACH_xxx for machines which are part of
* a configuration which supports more than one type of different machine.
* This is currently limited to CONFIG_PPC_MULTIPLATFORM and CHRP/PReP/PMac. -- Tom
diff --git a/include/asm-ppc/serial.h b/include/asm-ppc/serial.h
index 5d121448d3c1..2d9e8642cc87 100644
--- a/include/asm-ppc/serial.h
+++ b/include/asm-ppc/serial.h
@@ -28,7 +28,7 @@
#include <platforms/sandpoint.h>
#elif defined(CONFIG_SPRUCE)
#include <platforms/spruce_serial.h>
-#elif defined(CONFIG_40x)
+#elif defined(CONFIG_4xx)
#include <asm/ibm4xx.h>
#else
diff --git a/include/asm-ppc/tlbflush.h b/include/asm-ppc/tlbflush.h
index 2ccb0b20d2af..a441eb07e0e5 100644
--- a/include/asm-ppc/tlbflush.h
+++ b/include/asm-ppc/tlbflush.h
@@ -19,17 +19,23 @@ extern void _tlbia(void);
#if defined(CONFIG_4xx)
+#ifndef CONFIG_44x
+#define __tlbia() asm volatile ("sync; tlbia; isync" : : : "memory")
+#else
+#define __tlbia _tlbia
+#endif
+
static inline void flush_tlb_mm(struct mm_struct *mm)
- { _tlbia(); }
+ { __tlbia(); }
static inline void flush_tlb_page(struct vm_area_struct *vma,
unsigned long vmaddr)
{ _tlbie(vmaddr); }
static inline void flush_tlb_range(struct vm_area_struct *vma,
unsigned long start, unsigned long end)
- { _tlbia(); }
+ { __tlbia(); }
static inline void flush_tlb_kernel_range(unsigned long start,
unsigned long end)
- { _tlbia(); }
+ { __tlbia(); }
#elif defined(CONFIG_8xx)
#define __tlbia() asm volatile ("tlbia; sync" : : : "memory")
generated by cgit v1.2.3 (git 2.46.0) at 2026-02-10 10:39:36 +0000