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-rw-r--r--include/linux/device.h1
-rw-r--r--include/linux/dmapool.h27
-rw-r--r--include/linux/pci.h16
-rw-r--r--include/linux/pci_msi.h193
4 files changed, 36 insertions, 201 deletions
diff --git a/include/linux/device.h b/include/linux/device.h
index 6da63dac06b0..aef6b2f8836e 100644
--- a/include/linux/device.h
+++ b/include/linux/device.h
@@ -285,6 +285,7 @@ struct device {
detached from its driver. */
u64 *dma_mask; /* dma mask (if dma'able device) */
+ struct list_head dma_pools; /* dma pools (if dma'ble) */
void (*release)(struct device * dev);
};
diff --git a/include/linux/dmapool.h b/include/linux/dmapool.h
new file mode 100644
index 000000000000..e60bfdac348d
--- /dev/null
+++ b/include/linux/dmapool.h
@@ -0,0 +1,27 @@
+/*
+ * include/linux/dmapool.h
+ *
+ * Allocation pools for DMAable (coherent) memory.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef LINUX_DMAPOOL_H
+#define LINUX_DMAPOOL_H
+
+#include <asm/io.h>
+#include <asm/scatterlist.h>
+
+struct dma_pool *dma_pool_create(const char *name, struct device *dev,
+ size_t size, size_t align, size_t allocation);
+
+void dma_pool_destroy(struct dma_pool *pool);
+
+void *dma_pool_alloc(struct dma_pool *pool, int mem_flags, dma_addr_t *handle);
+
+void dma_pool_free(struct dma_pool *pool, void *vaddr, dma_addr_t addr);
+
+#endif
+
diff --git a/include/linux/pci.h b/include/linux/pci.h
index bc51ca9edef1..bde9c5e8dbf8 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -393,7 +393,6 @@ struct pci_dev {
0xffffffff. You only need to change
this if your device has broken DMA
or supports 64-bit transfers. */
- struct list_head pools; /* pci_pools tied to this device */
u64 consistent_dma_mask;/* Like dma_mask, but for
pci_alloc_consistent mappings as
@@ -416,8 +415,6 @@ struct pci_dev {
*/
unsigned int irq;
struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
- struct resource dma_resource[DEVICE_COUNT_DMA];
- struct resource irq_resource[DEVICE_COUNT_IRQ];
char * slot_name; /* pointer to dev.bus_id */
@@ -694,12 +691,15 @@ const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, co
int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass);
/* kmem_cache style wrapper around pci_alloc_consistent() */
-struct pci_pool *pci_pool_create (const char *name, struct pci_dev *dev,
- size_t size, size_t align, size_t allocation);
-void pci_pool_destroy (struct pci_pool *pool);
-void *pci_pool_alloc (struct pci_pool *pool, int flags, dma_addr_t *handle);
-void pci_pool_free (struct pci_pool *pool, void *vaddr, dma_addr_t addr);
+#include <linux/dmapool.h>
+
+#define pci_pool dma_pool
+#define pci_pool_create(name, pdev, size, align, allocation) \
+ dma_pool_create(name, &pdev->dev, size, align, allocation)
+#define pci_pool_destroy(pool) dma_pool_destroy(pool)
+#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
+#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
extern struct pci_dev *isa_bridge;
diff --git a/include/linux/pci_msi.h b/include/linux/pci_msi.h
deleted file mode 100644
index 0e42e65bc3e1..000000000000
--- a/include/linux/pci_msi.h
+++ /dev/null
@@ -1,193 +0,0 @@
-/*
- * ../include/linux/pci_msi.h
- *
- */
-
-#ifndef _ASM_PCI_MSI_H
-#define _ASM_PCI_MSI_H
-
-#include <linux/pci.h>
-
-#define MSI_AUTO -1
-#define NR_REPEATS 23
-#define NR_RESERVED_VECTORS 3 /*FIRST_DEVICE_VECTOR,FIRST_SYSTEM_VECTOR,0x80 */
-
-/*
- * Assume the maximum number of hot plug slots supported by the system is about
- * ten. The worstcase is that each of these slots is hot-added with a device,
- * which has two MSI/MSI-X capable functions. To avoid any MSI-X driver, which
- * attempts to request all available vectors, NR_HP_RESERVED_VECTORS is defined
- * as below to ensure at least one message is assigned to each detected MSI/
- * MSI-X device function.
- */
-#define NR_HP_RESERVED_VECTORS 20
-
-extern int vector_irq[NR_IRQS];
-extern cpumask_t pending_irq_balance_cpumask[NR_IRQS];
-extern void (*interrupt[NR_IRQS])(void);
-
-#ifdef CONFIG_SMP
-#define set_msi_irq_affinity set_msi_affinity
-#else
-#define set_msi_irq_affinity NULL
-static inline void move_msi(int vector) {}
-#endif
-
-#ifndef CONFIG_X86_IO_APIC
-static inline int get_ioapic_vector(struct pci_dev *dev) { return -1;}
-static inline void restore_ioapic_irq_handler(int irq) {}
-#else
-extern void restore_ioapic_irq_handler(int irq);
-#endif
-
-/*
- * MSI-X Address Register
- */
-#define PCI_MSIX_FLAGS_QSIZE 0x7FF
-#define PCI_MSIX_FLAGS_ENABLE (1 << 15)
-#define PCI_MSIX_FLAGS_BIRMASK (7 << 0)
-#define PCI_MSIX_FLAGS_BITMASK (1 << 0)
-
-#define PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET 0
-#define PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET 4
-#define PCI_MSIX_ENTRY_DATA_OFFSET 8
-#define PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET 12
-#define PCI_MSIX_ENTRY_SIZE 16
-
-#define msi_control_reg(base) (base + PCI_MSI_FLAGS)
-#define msi_lower_address_reg(base) (base + PCI_MSI_ADDRESS_LO)
-#define msi_upper_address_reg(base) (base + PCI_MSI_ADDRESS_HI)
-#define msi_data_reg(base, is64bit) \
- ( (is64bit == 1) ? base+PCI_MSI_DATA_64 : base+PCI_MSI_DATA_32 )
-#define msi_mask_bits_reg(base, is64bit) \
- ( (is64bit == 1) ? base+PCI_MSI_MASK_BIT : base+PCI_MSI_MASK_BIT-4)
-#define msi_disable(control) control &= ~PCI_MSI_FLAGS_ENABLE
-#define multi_msi_capable(control) \
- (1 << ((control & PCI_MSI_FLAGS_QMASK) >> 1))
-#define multi_msi_enable(control, num) \
- control |= (((num >> 1) << 4) & PCI_MSI_FLAGS_QSIZE);
-#define is_64bit_address(control) (control & PCI_MSI_FLAGS_64BIT)
-#define is_mask_bit_support(control) (control & PCI_MSI_FLAGS_MASKBIT)
-#define msi_enable(control, num) multi_msi_enable(control, num); \
- control |= PCI_MSI_FLAGS_ENABLE
-
-#define msix_control_reg msi_control_reg
-#define msix_table_offset_reg(base) (base + 0x04)
-#define msix_pba_offset_reg(base) (base + 0x08)
-#define msix_enable(control) control |= PCI_MSIX_FLAGS_ENABLE
-#define msix_disable(control) control &= ~PCI_MSIX_FLAGS_ENABLE
-#define msix_table_size(control) ((control & PCI_MSIX_FLAGS_QSIZE)+1)
-#define multi_msix_capable msix_table_size
-#define msix_unmask(address) (address & ~PCI_MSIX_FLAGS_BITMASK)
-#define msix_mask(address) (address | PCI_MSIX_FLAGS_BITMASK)
-#define msix_is_pending(address) (address & PCI_MSIX_FLAGS_PENDMASK)
-
-extern char __dbg_str_buf[256];
-#define _DEFINE_DBG_BUFFER char __dbg_str_buf[256];
-#define _DBG_K_TRACE_ENTRY ((unsigned int)0x00000001)
-#define _DBG_K_TRACE_EXIT ((unsigned int)0x00000002)
-#define _DBG_K_INFO ((unsigned int)0x00000004)
-#define _DBG_K_ERROR ((unsigned int)0x00000008)
-#define _DBG_K_TRACE (_DBG_K_TRACE_ENTRY | _DBG_K_TRACE_EXIT)
-
-#define _DEBUG_LEVEL (_DBG_K_INFO | _DBG_K_ERROR | _DBG_K_TRACE)
-#define _DBG_PRINT( dbg_flags, args... ) \
-if ( _DEBUG_LEVEL & (dbg_flags) ) \
-{ \
- int len; \
- len = sprintf(__dbg_str_buf, "%s:%d: %s ", \
- __FILE__, __LINE__, __FUNCTION__ ); \
- sprintf(__dbg_str_buf + len, args); \
- printk(KERN_INFO "%s\n", __dbg_str_buf); \
-}
-
-#define MSI_FUNCTION_TRACE_ENTER \
- _DBG_PRINT (_DBG_K_TRACE_ENTRY, "%s", "[Entry]");
-#define MSI_FUNCTION_TRACE_EXIT \
- _DBG_PRINT (_DBG_K_TRACE_EXIT, "%s", "[Entry]");
-
-/*
- * MSI Defined Data Structures
- */
-#define MSI_ADDRESS_HEADER 0xfee
-#define MSI_ADDRESS_HEADER_SHIFT 12
-#define MSI_ADDRESS_HEADER_MASK 0xfff000
-#define MSI_TARGET_CPU_SHIFT 4
-#define MSI_TARGET_CPU_MASK 0xff
-#define MSI_DELIVERY_MODE 0
-#define MSI_LEVEL_MODE 1 /* Edge always assert */
-#define MSI_TRIGGER_MODE 0 /* MSI is edge sensitive */
-#define MSI_LOGICAL_MODE 1
-#define MSI_REDIRECTION_HINT_MODE 0
-#ifdef CONFIG_SMP
-#define MSI_TARGET_CPU logical_smp_processor_id()
-#else
-#define MSI_TARGET_CPU TARGET_CPUS
-#endif
-
-struct msg_data {
-#if defined(__LITTLE_ENDIAN_BITFIELD)
- __u32 vector : 8;
- __u32 delivery_mode : 3; /* 000b: FIXED | 001b: lowest prior */
- __u32 reserved_1 : 3;
- __u32 level : 1; /* 0: deassert | 1: assert */
- __u32 trigger : 1; /* 0: edge | 1: level */
- __u32 reserved_2 : 16;
-#elif defined(__BIG_ENDIAN_BITFIELD)
- __u32 reserved_2 : 16;
- __u32 trigger : 1; /* 0: edge | 1: level */
- __u32 level : 1; /* 0: deassert | 1: assert */
- __u32 reserved_1 : 3;
- __u32 delivery_mode : 3; /* 000b: FIXED | 001b: lowest prior */
- __u32 vector : 8;
-#else
-#error "Bitfield endianness not defined! Check your byteorder.h"
-#endif
-} __attribute__ ((packed));
-
-struct msg_address {
- union {
- struct {
-#if defined(__LITTLE_ENDIAN_BITFIELD)
- __u32 reserved_1 : 2;
- __u32 dest_mode : 1; /*0:physic | 1:logic */
- __u32 redirection_hint: 1; /*0: dedicated CPU
- 1: lowest priority */
- __u32 reserved_2 : 4;
- __u32 dest_id : 24; /* Destination ID */
-#elif defined(__BIG_ENDIAN_BITFIELD)
- __u32 dest_id : 24; /* Destination ID */
- __u32 reserved_2 : 4;
- __u32 redirection_hint: 1; /*0: dedicated CPU
- 1: lowest priority */
- __u32 dest_mode : 1; /*0:physic | 1:logic */
- __u32 reserved_1 : 2;
-#else
-#error "Bitfield endianness not defined! Check your byteorder.h"
-#endif
- }u;
- __u32 value;
- }lo_address;
- __u32 hi_address;
-} __attribute__ ((packed));
-
-struct msi_desc {
- struct {
- __u8 type : 5; /* {0: unused, 5h:MSI, 11h:MSI-X} */
- __u8 maskbit : 1; /* mask-pending bit supported ? */
- __u8 reserved: 2; /* reserved */
- __u8 entry_nr; /* specific enabled entry */
- __u8 default_vector; /* default pre-assigned vector */
- __u8 current_cpu; /* current destination cpu */
- }msi_attrib;
-
- struct {
- __u16 head;
- __u16 tail;
- }link;
-
- unsigned long mask_base;
- struct pci_dev *dev;
-};
-
-#endif /* _ASM_PCI_MSI_H */
generated by cgit v1.2.3 (git 2.46.0) at 2026-01-27 12:56:53 +0000