diff options
Diffstat (limited to 'include')
119 files changed, 2495 insertions, 783 deletions
diff --git a/include/acpi/processor.h b/include/acpi/processor.h index 985cc0616dd1..dab7521d8ac6 100644 --- a/include/acpi/processor.h +++ b/include/acpi/processor.h @@ -9,8 +9,6 @@ #define ACPI_PROCESSOR_MAX_C2_LATENCY 100 #define ACPI_PROCESSOR_MAX_C3_LATENCY 1000 -#define ACPI_PROCESSOR_MAX_PERFORMANCE 8 - #define ACPI_PROCESSOR_MAX_THROTTLING 16 #define ACPI_PROCESSOR_MAX_THROTTLE 250 /* 25% */ #define ACPI_PROCESSOR_MAX_DUTY_WIDTH 4 @@ -67,20 +65,22 @@ struct acpi_processor_px { acpi_integer status; /* success indicator */ }; +#define ACPI_PDC_REVISION_ID 0x1 + struct acpi_processor_performance { - int state; - int platform_limit; - u16 control_register; - u16 status_register; - u8 control_register_bit_width; - u8 status_register_bit_width; - int state_count; - struct acpi_processor_px states[ACPI_PROCESSOR_MAX_PERFORMANCE]; - struct cpufreq_frequency_table freq_table[ACPI_PROCESSOR_MAX_PERFORMANCE]; - struct acpi_processor *pr; + unsigned int state; + unsigned int platform_limit; + struct acpi_pct_register control_register; + struct acpi_pct_register status_register; + unsigned int state_count; + struct acpi_processor_px *states; + + /* the _PDC objects passed by the driver, if any */ + struct acpi_object_list *pdc; }; + /* Throttling Control */ struct acpi_processor_tx { @@ -133,11 +133,11 @@ struct acpi_processor { struct acpi_processor_limit limit; }; -extern int acpi_processor_get_platform_limit ( - struct acpi_processor* pr); extern int acpi_processor_register_performance ( struct acpi_processor_performance * performance, - struct acpi_processor ** pr, + unsigned int cpu); +extern void acpi_processor_unregister_performance ( + struct acpi_processor_performance * performance, unsigned int cpu); #endif diff --git a/include/asm-alpha/byteorder.h b/include/asm-alpha/byteorder.h index e5179c55920c..7af2b8d25486 100644 --- a/include/asm-alpha/byteorder.h +++ b/include/asm-alpha/byteorder.h @@ -2,11 +2,12 @@ #define _ALPHA_BYTEORDER_H #include <asm/types.h> +#include <linux/compiler.h> #include <asm/compiler.h> #ifdef __GNUC__ -static __inline __u32 __attribute_const__ __arch__swab32(__u32 x) +static __inline __attribute_const__ __u32 __arch__swab32(__u32 x) { /* * Unfortunately, we can't use the 6 instruction sequence diff --git a/include/asm-alpha/pci.h b/include/asm-alpha/pci.h index faeee0303518..8eba57310ad2 100644 --- a/include/asm-alpha/pci.h +++ b/include/asm-alpha/pci.h @@ -208,6 +208,10 @@ static inline int pci_name_bus(char *name, struct pci_bus *bus) return 0; } +static inline void pcibios_add_platform_entries(struct pci_dev *dev) +{ +} + #endif /* __KERNEL__ */ /* Values for the `which' argument to sys_pciconfig_iobase. */ diff --git a/include/asm-arm/pci.h b/include/asm-arm/pci.h index 5280c8fa574d..6456092a5ab8 100644 --- a/include/asm-arm/pci.h +++ b/include/asm-arm/pci.h @@ -186,6 +186,10 @@ extern void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, struct resource *res); +static inline void pcibios_add_platform_entries(struct pci_dev *dev) +{ +} + #endif /* __KERNEL__ */ #endif diff --git a/include/asm-arm/setup.h b/include/asm-arm/setup.h index 9d92daa4173e..4680c39be96f 100644 --- a/include/asm-arm/setup.h +++ b/include/asm-arm/setup.h @@ -171,7 +171,7 @@ struct tagtable { int (*parse)(const struct tag *); }; -#define __tag __attribute__((unused, __section__(".taglist"))) +#define __tag __attribute_used__ __attribute__((__section__(".taglist"))) #define __tagtable(tag, fn) \ static struct tagtable __tagtable_##fn __tag = { tag, fn } @@ -210,9 +210,8 @@ struct early_params { void (*fn)(char **p); }; -#define __early_param(name,fn) \ -static struct early_params __early_##fn \ -__attribute__((section("__early_param"), unused)) = \ - { name, fn } +#define __early_param(name,fn) \ +static struct early_params __early_##fn __attribute_used__ \ +__attribute__((__section__("__early_param"))) = { name, fn } #endif diff --git a/include/asm-generic/local.h b/include/asm-generic/local.h index 45c07dbc0a59..c814b2f840ba 100644 --- a/include/asm-generic/local.h +++ b/include/asm-generic/local.h @@ -9,7 +9,7 @@ /* An unsigned long type for operations which are atomic for a single * CPU. Usually used in combination with per-cpu variables. */ -#if BITS_PER_LONG == 32 && !defined(CONFIG_SPARC32) +#if BITS_PER_LONG == 32 /* Implement in terms of atomics. */ /* Don't use typedef: don't want them to be mixed with atomic_t's. */ diff --git a/include/asm-h8300/pci.h b/include/asm-h8300/pci.h index f4813f0a9021..d032729b19df 100644 --- a/include/asm-h8300/pci.h +++ b/include/asm-h8300/pci.h @@ -22,4 +22,8 @@ extern inline void pcibios_penalize_isa_irq(int irq) #define PCI_DMA_BUS_IS_PHYS (1) +static inline void pcibios_add_platform_entries(struct pci_dev *dev) +{ +} + #endif /* _ASM_H8300_PCI_H */ diff --git a/include/asm-i386/atomic.h b/include/asm-i386/atomic.h index 61a1aece830b..4df45c5e4b16 100644 --- a/include/asm-i386/atomic.h +++ b/include/asm-i386/atomic.h @@ -27,8 +27,7 @@ typedef struct { volatile int counter; } atomic_t; * atomic_read - read atomic variable * @v: pointer of type atomic_t * - * Atomically reads the value of @v. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. + * Atomically reads the value of @v. */ #define atomic_read(v) ((v)->counter) @@ -37,8 +36,7 @@ typedef struct { volatile int counter; } atomic_t; * @v: pointer of type atomic_t * @i: required value * - * Atomically sets the value of @v to @i. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. + * Atomically sets the value of @v to @i. */ #define atomic_set(v,i) (((v)->counter) = (i)) @@ -47,8 +45,7 @@ typedef struct { volatile int counter; } atomic_t; * @i: integer value to add * @v: pointer of type atomic_t * - * Atomically adds @i to @v. Note that the guaranteed useful range - * of an atomic_t is only 24 bits. + * Atomically adds @i to @v. */ static __inline__ void atomic_add(int i, atomic_t *v) { @@ -63,8 +60,7 @@ static __inline__ void atomic_add(int i, atomic_t *v) * @i: integer value to subtract * @v: pointer of type atomic_t * - * Atomically subtracts @i from @v. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. + * Atomically subtracts @i from @v. */ static __inline__ void atomic_sub(int i, atomic_t *v) { @@ -81,8 +77,7 @@ static __inline__ void atomic_sub(int i, atomic_t *v) * * Atomically subtracts @i from @v and returns * true if the result is zero, or false for all - * other cases. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. + * other cases. */ static __inline__ int atomic_sub_and_test(int i, atomic_t *v) { @@ -99,8 +94,7 @@ static __inline__ int atomic_sub_and_test(int i, atomic_t *v) * atomic_inc - increment atomic variable * @v: pointer of type atomic_t * - * Atomically increments @v by 1. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. + * Atomically increments @v by 1. */ static __inline__ void atomic_inc(atomic_t *v) { @@ -114,8 +108,7 @@ static __inline__ void atomic_inc(atomic_t *v) * atomic_dec - decrement atomic variable * @v: pointer of type atomic_t * - * Atomically decrements @v by 1. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. + * Atomically decrements @v by 1. */ static __inline__ void atomic_dec(atomic_t *v) { @@ -131,8 +124,7 @@ static __inline__ void atomic_dec(atomic_t *v) * * Atomically decrements @v by 1 and * returns true if the result is 0, or false for all other - * cases. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. + * cases. */ static __inline__ int atomic_dec_and_test(atomic_t *v) { @@ -151,8 +143,7 @@ static __inline__ int atomic_dec_and_test(atomic_t *v) * * Atomically increments @v by 1 * and returns true if the result is zero, or false for all - * other cases. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. + * other cases. */ static __inline__ int atomic_inc_and_test(atomic_t *v) { @@ -172,8 +163,7 @@ static __inline__ int atomic_inc_and_test(atomic_t *v) * * Atomically adds @i to @v and returns true * if the result is negative, or false when - * result is greater than or equal to zero. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. + * result is greater than or equal to zero. */ static __inline__ int atomic_add_negative(int i, atomic_t *v) { diff --git a/include/asm-i386/pci.h b/include/asm-i386/pci.h index 83aede6ce595..909a2c152862 100644 --- a/include/asm-i386/pci.h +++ b/include/asm-i386/pci.h @@ -89,6 +89,11 @@ pci_dac_dma_sync_single(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, enum pci_mmap_state mmap_state, int write_combine); + +static inline void pcibios_add_platform_entries(struct pci_dev *dev) +{ +} + #endif /* __KERNEL__ */ /* implement the pci_ DMA API in terms of the generic device dma_ one */ diff --git a/include/asm-ia64/fpswa.h b/include/asm-ia64/fpswa.h index 8986f033c815..62edfceadaa6 100644 --- a/include/asm-ia64/fpswa.h +++ b/include/asm-ia64/fpswa.h @@ -68,4 +68,6 @@ typedef struct { efi_fpswa_t fpswa; } fpswa_interface_t; +extern fpswa_interface_t *fpswa_interface; + #endif /* _ASM_IA64_FPSWA_H */ diff --git a/include/asm-ia64/iosapic.h b/include/asm-ia64/iosapic.h index 68fa169e7a5b..ba8a35f418a2 100644 --- a/include/asm-ia64/iosapic.h +++ b/include/asm-ia64/iosapic.h @@ -52,6 +52,9 @@ #ifndef __ASSEMBLY__ #ifdef CONFIG_IOSAPIC + +#define NR_IOSAPICS 256 + extern void __init iosapic_system_init (int pcat_compat); extern void __init iosapic_init (unsigned long address, unsigned int gsi_base); diff --git a/include/asm-ia64/mca.h b/include/asm-ia64/mca.h index f6439e7dd68e..0957e2ab689d 100644 --- a/include/asm-ia64/mca.h +++ b/include/asm-ia64/mca.h @@ -2,7 +2,7 @@ * File: mca.h * Purpose: Machine check handling specific defines * - * Copyright (C) 1999 Silicon Graphics, Inc. + * Copyright (C) 1999, 2004 Silicon Graphics, Inc. * Copyright (C) Vijay Chander (vijay@engr.sgi.com) * Copyright (C) Srinivasa Thirumalachar (sprasad@engr.sgi.com) */ @@ -20,23 +20,8 @@ #include <asm/processor.h> #include <asm/mca_asm.h> -/* These are the return codes from all the IA64_MCA specific interfaces */ -typedef int ia64_mca_return_code_t; - -enum { - IA64_MCA_SUCCESS = 0, - IA64_MCA_FAILURE = 1 -}; - #define IA64_MCA_RENDEZ_TIMEOUT (20 * 1000) /* value in milliseconds - 20 seconds */ -#define IA64_CMC_INT_DISABLE 0 -#define IA64_CMC_INT_ENABLE 1 - - -typedef u32 int_vector_t; -typedef u64 millisec_t; - typedef union cmcv_reg_u { u64 cmcv_regval; struct { @@ -53,10 +38,6 @@ typedef union cmcv_reg_u { #define cmcv_mask cmcv_reg_s.cmcr_mask #define cmcv_vector cmcv_reg_s.cmcr_vector - -#define IA64_MCA_UCMC_HANDLER_SIZE 0x10 -#define IA64_INIT_HANDLER_SIZE 0x10 - enum { IA64_MCA_RENDEZ_CHECKIN_NOTDONE = 0x0, IA64_MCA_RENDEZ_CHECKIN_DONE = 0x1 @@ -85,16 +66,6 @@ typedef struct ia64_mc_info_s { } ia64_mc_info_t; -/* Possible rendez states passed from SAL to OS during MCA - * handoff - */ -enum { - IA64_MCA_RENDEZ_NOT_RQD = 0x0, - IA64_MCA_RENDEZ_DONE_WITHOUT_INIT = 0x1, - IA64_MCA_RENDEZ_DONE_WITH_INIT = 0x2, - IA64_MCA_RENDEZ_FAILURE = -1 -}; - typedef struct ia64_mca_sal_to_os_state_s { u64 imsto_os_gp; /* GP of the os registered with the SAL */ u64 imsto_pal_proc; /* PAL_PROC entry point - physical addr */ @@ -136,41 +107,13 @@ typedef struct ia64_mca_os_to_sal_state_s { */ } ia64_mca_os_to_sal_state_t; -typedef int (*prfunc_t)(const char * fmt, ...); - extern void ia64_mca_init(void); extern void ia64_os_mca_dispatch(void); extern void ia64_os_mca_dispatch_end(void); extern void ia64_mca_ucmc_handler(void); extern void ia64_monarch_init_handler(void); extern void ia64_slave_init_handler(void); -extern irqreturn_t ia64_mca_rendez_int_handler(int,void *,struct pt_regs *); -extern irqreturn_t ia64_mca_wakeup_int_handler(int,void *,struct pt_regs *); -extern irqreturn_t ia64_mca_cmc_int_handler(int,void *,struct pt_regs *); -extern irqreturn_t ia64_mca_cmc_int_caller(int,void *,struct pt_regs *); -extern irqreturn_t ia64_mca_cpe_int_handler(int,void *,struct pt_regs *); -extern irqreturn_t ia64_mca_cpe_int_caller(int,void *,struct pt_regs *); -extern int ia64_log_print(int,prfunc_t); extern void ia64_mca_cmc_vector_setup(void); -extern int ia64_mca_check_errors(void); - -#define PLATFORM_CALL(fn, args) printk("Platform call TBD\n") - -#define platform_mem_dev_err_print ia64_log_prt_oem_data -#define platform_pci_bus_err_print ia64_log_prt_oem_data -#define platform_pci_comp_err_print ia64_log_prt_oem_data -#define platform_plat_specific_err_print ia64_log_prt_oem_data -#define platform_host_ctlr_err_print ia64_log_prt_oem_data -#define platform_plat_bus_err_print ia64_log_prt_oem_data - -#undef MCA_TEST - -#undef IA64_MCA_DEBUG_INFO -#if defined(IA64_MCA_DEBUG_INFO) -# define IA64_MCA_DEBUG(fmt...) printk(fmt) -#else -# define IA64_MCA_DEBUG(fmt...) -#endif #endif /* !__ASSEMBLY__ */ #endif /* _ASM_IA64_MCA_H */ diff --git a/include/asm-ia64/mmu_context.h b/include/asm-ia64/mmu_context.h index 3a3ea55e9ab3..41d65da53e85 100644 --- a/include/asm-ia64/mmu_context.h +++ b/include/asm-ia64/mmu_context.h @@ -106,6 +106,7 @@ get_mmu_context (struct mm_struct *mm) /* re-check, now that we've got the lock: */ context = mm->context; if (context == 0) { + cpus_clear(mm->cpu_vm_mask); if (ia64_ctx.next >= ia64_ctx.limit) wrap_mmu_context(mm); mm->context = context = ia64_ctx.next++; @@ -170,6 +171,8 @@ activate_context (struct mm_struct *mm) do { context = get_mmu_context(mm); MMU_TRACE('A', smp_processor_id(), mm, context); + if (!cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) + cpu_set(smp_processor_id(), mm->cpu_vm_mask); reload_context(context); MMU_TRACE('a', smp_processor_id(), mm, context); /* in the unlikely event of a TLB-flush by another thread, redo the load: */ diff --git a/include/asm-ia64/pci.h b/include/asm-ia64/pci.h index 42f66dda432b..cbf5c0d9529c 100644 --- a/include/asm-ia64/pci.h +++ b/include/asm-ia64/pci.h @@ -112,6 +112,10 @@ static inline int pci_name_bus(char *name, struct pci_bus *bus) return 0; } +static inline void pcibios_add_platform_entries(struct pci_dev *dev) +{ +} + /* generic pci stuff */ #include <asm-generic/pci.h> diff --git a/include/asm-ia64/percpu.h b/include/asm-ia64/percpu.h index a44ee78e999f..1e87f19dad56 100644 --- a/include/asm-ia64/percpu.h +++ b/include/asm-ia64/percpu.h @@ -50,7 +50,7 @@ extern void *per_cpu_init(void); #else /* ! SMP */ -#define per_cpu(var, cpu) ((void)cpu, per_cpu__##var) +#define per_cpu(var, cpu) (*((void)cpu, &per_cpu__##var)) #define __get_cpu_var(var) per_cpu__##var #define per_cpu_init() (__phys_per_cpu_start) diff --git a/include/asm-ia64/processor.h b/include/asm-ia64/processor.h index 5641a23f990c..4b1870a784cb 100644 --- a/include/asm-ia64/processor.h +++ b/include/asm-ia64/processor.h @@ -289,19 +289,19 @@ struct thread_struct { struct ia64_fpreg fph[96]; /* saved/loaded on demand */ }; -#define INIT_THREAD { \ - .flags = 0, \ - .on_ustack = 0, \ - .ksp = 0, \ - .map_base = DEFAULT_MAP_BASE, \ - .rbs_bot = DEFAULT_USER_STACK_SIZE, \ - .task_size = DEFAULT_TASK_SIZE, \ - .last_fph_cpu = -1, \ - INIT_THREAD_IA32 \ - INIT_THREAD_PM \ - .dbr = {0, }, \ - .ibr = {0, }, \ - .fph = {{{{0}}}, } \ +#define INIT_THREAD { \ + .flags = 0, \ + .on_ustack = 0, \ + .ksp = 0, \ + .map_base = DEFAULT_MAP_BASE, \ + .rbs_bot = STACK_TOP - DEFAULT_USER_STACK_SIZE, \ + .task_size = DEFAULT_TASK_SIZE, \ + .last_fph_cpu = -1, \ + INIT_THREAD_IA32 \ + INIT_THREAD_PM \ + .dbr = {0, }, \ + .ibr = {0, }, \ + .fph = {{{{0}}}, } \ } #define start_thread(regs,new_ip,new_sp) do { \ diff --git a/include/asm-m68k/pci.h b/include/asm-m68k/pci.h index 57e1487bac3f..9e7d79ab5d13 100644 --- a/include/asm-m68k/pci.h +++ b/include/asm-m68k/pci.h @@ -54,4 +54,8 @@ static inline void pcibios_penalize_isa_irq(int irq) */ #define PCI_DMA_BUS_IS_PHYS (1) +static inline void pcibios_add_platform_entries(struct pci_dev *dev) +{ +} + #endif /* _ASM_M68K_PCI_H */ diff --git a/include/asm-m68knommu/pci.h b/include/asm-m68knommu/pci.h index a99ce768f4a6..e04c77e1184d 100644 --- a/include/asm-m68knommu/pci.h +++ b/include/asm-m68knommu/pci.h @@ -30,6 +30,10 @@ static inline int pci_dma_supported(struct pci_dev *hwdev, u64 mask) */ #define pci_dac_dma_supported(pci_dev, mask) (0) +static inline void pcibios_add_platform_entries(struct pci_dev *dev) +{ +} + #endif /* CONFIG_COMEMPCI */ #endif /* M68KNOMMU_PCI_H */ diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h index ccecd9767cb0..69d676ddb1ab 100644 --- a/include/asm-mips/atomic.h +++ b/include/asm-mips/atomic.h @@ -29,8 +29,7 @@ typedef struct { volatile __s64 counter; } atomic64_t; * atomic_read - read atomic variable * @v: pointer of type atomic_t * - * Atomically reads the value of @v. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. + * Atomically reads the value of @v. */ #define atomic_read(v) ((v)->counter) @@ -46,8 +45,7 @@ typedef struct { volatile __s64 counter; } atomic64_t; * @v: pointer of type atomic_t * @i: required value * - * Atomically sets the value of @v to @i. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. + * Atomically sets the value of @v to @i. */ #define atomic_set(v,i) ((v)->counter = (i)) @@ -68,8 +66,7 @@ typedef struct { volatile __s64 counter; } atomic64_t; * @i: integer value to add * @v: pointer of type atomic_t * - * Atomically adds @i to @v. Note that the guaranteed useful range - * of an atomic_t is only 24 bits. + * Atomically adds @i to @v. */ static __inline__ void atomic_add(int i, atomic_t * v) { @@ -85,8 +82,7 @@ static __inline__ void atomic_add(int i, atomic_t * v) * @i: integer value to subtract * @v: pointer of type atomic_t * - * Atomically subtracts @i from @v. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. + * Atomically subtracts @i from @v. */ static __inline__ void atomic_sub(int i, atomic_t * v) { @@ -137,8 +133,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v) * @i: integer value to add * @v: pointer of type atomic_t * - * Atomically adds @i to @v. Note that the guaranteed useful range - * of an atomic_t is only 24 bits. + * Atomically adds @i to @v. */ static __inline__ void atomic_add(int i, atomic_t * v) { @@ -158,8 +153,7 @@ static __inline__ void atomic_add(int i, atomic_t * v) * @i: integer value to subtract * @v: pointer of type atomic_t * - * Atomically subtracts @i from @v. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. + * Atomically subtracts @i from @v. */ static __inline__ void atomic_sub(int i, atomic_t * v) { @@ -390,8 +384,7 @@ static __inline__ int atomic64_sub_return(int i, atomic64_t * v) * * Atomically subtracts @i from @v and returns * true if the result is zero, or false for all - * other cases. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. + * other cases. */ #define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0) @@ -412,8 +405,7 @@ static __inline__ int atomic64_sub_return(int i, atomic64_t * v) * * Atomically increments @v by 1 * and returns true if the result is zero, or false for all - * other cases. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. + * other cases. */ #define atomic_inc_and_test(v) (atomic_inc_return(v) == 0) @@ -433,8 +425,7 @@ static __inline__ int atomic64_sub_return(int i, atomic64_t * v) * * Atomically decrements @v by 1 and * returns true if the result is 0, or false for all other - * cases. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. + * cases. */ #define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0) @@ -452,8 +443,7 @@ static __inline__ int atomic64_sub_return(int i, atomic64_t * v) * atomic_inc - increment atomic variable * @v: pointer of type atomic_t * - * Atomically increments @v by 1. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. + * Atomically increments @v by 1. */ #define atomic_inc(v) atomic_add(1,(v)) @@ -469,8 +459,7 @@ static __inline__ int atomic64_sub_return(int i, atomic64_t * v) * atomic_dec - decrement and test * @v: pointer of type atomic_t * - * Atomically decrements @v by 1. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. + * Atomically decrements @v by 1. */ #define atomic_dec(v) atomic_sub(1,(v)) @@ -489,8 +478,7 @@ static __inline__ int atomic64_sub_return(int i, atomic64_t * v) * * Atomically adds @i to @v and returns true * if the result is negative, or false when - * result is greater than or equal to zero. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. + * result is greater than or equal to zero. */ #define atomic_add_negative(i,v) (atomic_add_return(i, (v)) < 0) diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h index 3943c111647e..75a2b5536bb0 100644 --- a/include/asm-mips/pci.h +++ b/include/asm-mips/pci.h @@ -120,6 +120,10 @@ static inline void pci_dac_dma_sync_single(struct pci_dev *pdev, dma_cache_wback_inv(addr, len); } +static inline void pcibios_add_platform_entries(struct pci_dev *dev) +{ +} + #endif /* __KERNEL__ */ /* implement the pci_ DMA API in terms of the generic device dma_ one */ diff --git a/include/asm-parisc/pci.h b/include/asm-parisc/pci.h index d5dca01282f0..6d803a9e8967 100644 --- a/include/asm-parisc/pci.h +++ b/include/asm-parisc/pci.h @@ -196,4 +196,8 @@ extern void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, struct resource *res); +static inline void pcibios_add_platform_entries(struct pci_dev *dev) +{ +} + #endif /* __ASM_PARISC_PCI_H */ diff --git a/include/asm-ppc/bootinfo.h b/include/asm-ppc/bootinfo.h index 213bab4f1481..93d955c70d65 100644 --- a/include/asm-ppc/bootinfo.h +++ b/include/asm-ppc/bootinfo.h @@ -10,6 +10,7 @@ #define _PPC_BOOTINFO_H #include <linux/config.h> +#include <asm/page.h> #if defined(CONFIG_APUS) && !defined(__BOOTER__) #include <asm-m68k/bootinfo.h> @@ -29,11 +30,21 @@ struct bi_record { #define BI_SYSMAP 0x1015 #define BI_MACHTYPE 0x1016 #define BI_MEMSIZE 0x1017 +#define BI_BOARD_INFO 0x1018 extern struct bi_record *find_bootinfo(void); +extern void bootinfo_init(struct bi_record *rec); +extern void bootinfo_append(unsigned long tag, unsigned long size, void * data); extern void parse_bootinfo(struct bi_record *rec); extern unsigned long boot_mem_size; +static inline struct bi_record * +bootinfo_addr(unsigned long offset) +{ + + return (struct bi_record *)_ALIGN((offset) + (1 << 20) - 1, + (1 << 20)); +} #endif /* CONFIG_APUS */ diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h index e5d2df3d765b..2bfdad685d95 100644 --- a/include/asm-ppc/ibm44x.h +++ b/include/asm-ppc/ibm44x.h @@ -51,7 +51,7 @@ typedef struct board_info { #define PPC44x_PIN_SIZE (1 << PPC44x_PIN_SHIFT) /* Lowest TLB slot consumed by the default pinned TLBs */ -#define PPC44x_LOW_SLOT 62 +#define PPC44x_LOW_SLOT 63 /* * Standard 4GB "page" definitions diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 0b231e3c0fb1..5797fd1cf232 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -346,16 +346,14 @@ typedef struct _P601_BAT { #define PPC44x_TLB_EPN_MASK 0xfffffc00 /* Effective Page Number */ #define PPC44x_TLB_VALID 0x00000200 /* Valid flag */ #define PPC44x_TLB_TS 0x00000100 /* Translation address space */ -#define PPC44x_TLB_PAGESZ_MASK 0x000000f0 -#define PPC44x_TLB_PAGESZ(x) (x << 4) -#define PPC44x_PAGESZ_1K 0 -#define PPC44x_PAGESZ_4K 1 -#define PPC44x_PAGESZ_16K 2 -#define PPC44x_PAGESZ_64K 3 -#define PPC44x_PAGESZ_256K 4 -#define PPC44x_PAGESZ_1M 5 -#define PPC44x_PAGESZ_16M 7 -#define PPC44x_PAGESZ_256M 9 +#define PPC44x_TLB_1K 0x00000000 /* Page sizes */ +#define PPC44x_TLB_4K 0x00000010 +#define PPC44x_TLB_16K 0x00000020 +#define PPC44x_TLB_64K 0x00000030 +#define PPC44x_TLB_256K 0x00000040 +#define PPC44x_TLB_1M 0x00000050 +#define PPC44x_TLB_16M 0x00000070 +#define PPC44x_TLB_256M 0x00000090 /* Translation fields */ #define PPC44x_TLB_RPN_MASK 0xfffffc00 /* Real Page Number */ diff --git a/include/asm-ppc/pci.h b/include/asm-ppc/pci.h index 16d617508242..0228e6e40e05 100644 --- a/include/asm-ppc/pci.h +++ b/include/asm-ppc/pci.h @@ -282,6 +282,8 @@ extern void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, struct resource *res); +extern void pcibios_add_platform_entries(struct pci_dev *dev); + #endif /* __KERNEL__ */ #endif /* __PPC_PCI_H */ diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h index 8ac2de22eadd..98e9bb20e36e 100644 --- a/include/asm-ppc/pgtable.h +++ b/include/asm-ppc/pgtable.h @@ -320,13 +320,13 @@ extern unsigned long ioremap_bot, ioremap_base; * another purpose. -- paulus. */ +#ifdef CONFIG_44x +#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_GUARDED) +#else #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED) +#endif #define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE) -#ifndef CONFIG_44x #define _PAGE_KERNEL (_PAGE_BASE | _PAGE_SHARED | _PAGE_WRENABLE) -#else -#define _PAGE_KERNEL (_PAGE_BASE | _PAGE_SHARED | _PAGE_WRENABLE | _PAGE_GUARDED) -#endif #ifdef CONFIG_PPC_STD_MMU /* On standard PPC MMU, no user access implies kernel read/write access, diff --git a/include/asm-ppc/pmac_feature.h b/include/asm-ppc/pmac_feature.h index 83cc2ea442c4..11065e368382 100644 --- a/include/asm-ppc/pmac_feature.h +++ b/include/asm-ppc/pmac_feature.h @@ -115,6 +115,7 @@ /* MacRISC4 / G5 machines */ #define PMAC_TYPE_POWERMAC_G5 0x150 /* First tower */ +#define PMAC_TYPE_UNKNOWN_K2 0x19f /* Any other K2 based */ /* * Motherboard flags diff --git a/include/asm-ppc/reg_booke.h b/include/asm-ppc/reg_booke.h index b008212e584d..1aa6322f82f6 100644 --- a/include/asm-ppc/reg_booke.h +++ b/include/asm-ppc/reg_booke.h @@ -47,7 +47,11 @@ do { \ #define MSR_DS MSR_DR /* Data Space */ /* Default MSR for kernel mode. */ +#if defined (CONFIG_40x) #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE|MSR_DE) +#elif defined(CONFIG_BOOKE) +#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE|MSR_DE) +#endif /* Special Purpose Registers (SPRNs)*/ #define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */ @@ -130,6 +134,8 @@ do { \ #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ #define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ #define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ +#define SPRN_CSRR0 SPRN_SRR2 /* Critical Save and Restore Register 0 */ +#define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */ #endif /* Bit definitions for the DBSR. */ @@ -237,8 +243,13 @@ do { \ #define SGR_GUARDED 1 /* Speculative fetching disallowed. */ /* Short-hand for various SPRs. */ +#ifdef CONFIG_BOOKE #define CSRR0 SPRN_CSRR0 /* Critical Save and Restore Register 0 */ #define CSRR1 SPRN_CSRR1 /* Critical Save and Restore Register 1 */ +#else +#define CSRR0 SPRN_SRR2 /* Logically and functionally equivalent. */ +#define CSRR1 SPRN_SRR3 /* Logically and functionally equivalent. */ +#endif #define DCMP SPRN_DCMP /* Data TLB Compare Register */ #define SPRG4R SPRN_SPRG4R /* Supervisor Private Registers */ #define SPRG5R SPRN_SPRG5R diff --git a/include/asm-ppc64/bootx.h b/include/asm-ppc64/bootx.h new file mode 100644 index 000000000000..b0c51b45d7a2 --- /dev/null +++ b/include/asm-ppc64/bootx.h @@ -0,0 +1,135 @@ +/* + * This file describes the structure passed from the BootX application + * (for MacOS) when it is used to boot Linux. + * + * Written by Benjamin Herrenschmidt. + */ + + +#ifndef __ASM_BOOTX_H__ +#define __ASM_BOOTX_H__ + +#ifdef macintosh +#include <Types.h> +#include "linux_type_defs.h" +#endif + +#ifdef macintosh +/* All this requires PowerPC alignment */ +#pragma options align=power +#endif + +/* On kernel entry: + * + * r3 = 0x426f6f58 ('BooX') + * r4 = pointer to boot_infos + * r5 = NULL + * + * Data and instruction translation disabled, interrupts + * disabled, kernel loaded at physical 0x00000000 on PCI + * machines (will be different on NuBus). + */ + +#define BOOT_INFO_VERSION 5 +#define BOOT_INFO_COMPATIBLE_VERSION 1 + +/* Bit in the architecture flag mask. More to be defined in + future versions. Note that either BOOT_ARCH_PCI or + BOOT_ARCH_NUBUS is set. The other BOOT_ARCH_NUBUS_xxx are + set additionally when BOOT_ARCH_NUBUS is set. + */ +#define BOOT_ARCH_PCI 0x00000001UL +#define BOOT_ARCH_NUBUS 0x00000002UL +#define BOOT_ARCH_NUBUS_PDM 0x00000010UL +#define BOOT_ARCH_NUBUS_PERFORMA 0x00000020UL +#define BOOT_ARCH_NUBUS_POWERBOOK 0x00000040UL + +/* Maximum number of ranges in phys memory map */ +#define MAX_MEM_MAP_SIZE 26 + +/* This is the format of an element in the physical memory map. Note that + the map is optional and current BootX will only build it for pre-PCI + machines */ +typedef struct boot_info_map_entry +{ + __u32 physAddr; /* Physical starting address */ + __u32 size; /* Size in bytes */ +} boot_info_map_entry_t; + + +/* Here are the boot informations that are passed to the bootstrap + * Note that the kernel arguments and the device tree are appended + * at the end of this structure. */ +typedef struct boot_infos +{ + /* Version of this structure */ + __u32 version; + /* backward compatible down to version: */ + __u32 compatible_version; + + /* NEW (vers. 2) this holds the current _logical_ base addr of + the frame buffer (for use by early boot message) */ + __u8* logicalDisplayBase; + + /* NEW (vers. 4) Apple's machine identification */ + __u32 machineID; + + /* NEW (vers. 4) Detected hw architecture */ + __u32 architecture; + + /* The device tree (internal addresses relative to the beginning of the tree, + * device tree offset relative to the beginning of this structure). + * On pre-PCI macintosh (BOOT_ARCH_PCI bit set to 0 in architecture), this + * field is 0. + */ + __u32 deviceTreeOffset; /* Device tree offset */ + __u32 deviceTreeSize; /* Size of the device tree */ + + /* Some infos about the current MacOS display */ + __u32 dispDeviceRect[4]; /* left,top,right,bottom */ + __u32 dispDeviceDepth; /* (8, 16 or 32) */ + __u8* dispDeviceBase; /* base address (physical) */ + __u32 dispDeviceRowBytes; /* rowbytes (in bytes) */ + __u32 dispDeviceColorsOffset; /* Colormap (8 bits only) or 0 (*) */ + /* Optional offset in the registry to the current + * MacOS display. (Can be 0 when not detected) */ + __u32 dispDeviceRegEntryOffset; + + /* Optional pointer to boot ramdisk (offset from this structure) */ + __u32 ramDisk; + __u32 ramDiskSize; /* size of ramdisk image */ + + /* Kernel command line arguments (offset from this structure) */ + __u32 kernelParamsOffset; + + /* ALL BELOW NEW (vers. 4) */ + + /* This defines the physical memory. Valid with BOOT_ARCH_NUBUS flag + (non-PCI) only. On PCI, memory is contiguous and it's size is in the + device-tree. */ + boot_info_map_entry_t + physMemoryMap[MAX_MEM_MAP_SIZE]; /* Where the phys memory is */ + __u32 physMemoryMapSize; /* How many entries in map */ + + + /* The framebuffer size (optional, currently 0) */ + __u32 frameBufferSize; /* Represents a max size, can be 0. */ + + /* NEW (vers. 5) */ + + /* Total params size (args + colormap + device tree + ramdisk) */ + __u32 totalParamsSize; + +} boot_infos_t; + +/* (*) The format of the colormap is 256 * 3 * 2 bytes. Each color index is represented + * by 3 short words containing a 16 bits (unsigned) color component. + * Later versions may contain the gamma table for direct-color devices here. + */ +#define BOOTX_COLORTABLE_SIZE (256UL*3UL*2UL) + +#ifdef macintosh +#pragma options align=reset +#endif + +#endif diff --git a/include/asm-ppc64/btext.h b/include/asm-ppc64/btext.h new file mode 100644 index 000000000000..ba6b5b3ae98a --- /dev/null +++ b/include/asm-ppc64/btext.h @@ -0,0 +1,29 @@ +/* + * Definitions for using the procedures in btext.c. + * + * Benjamin Herrenschmidt <benh@kernel.crashing.org> + */ +#ifndef __PPC_BTEXT_H +#define __PPC_BTEXT_H +#ifdef __KERNEL__ + +#include <asm/bootx.h> + +extern void btext_clearscreen(void); +extern void btext_flushscreen(void); + +extern boot_infos_t disp_bi; +extern int boot_text_mapped; + +void btext_setup_display(int width, int height, int depth, int pitch, + unsigned long address); +void map_boot_text(void); +void btext_update_display(unsigned long phys, int width, int height, + int depth, int pitch); + +void btext_drawchar(char c); +void btext_drawstring(const char *str); +void btext_drawhex(unsigned long v); + +#endif /* __KERNEL__ */ +#endif /* __PPC_BTEXT_H */ diff --git a/include/asm-ppc64/dbdma.h b/include/asm-ppc64/dbdma.h new file mode 100644 index 000000000000..f2d5d5dc3377 --- /dev/null +++ b/include/asm-ppc64/dbdma.h @@ -0,0 +1,2 @@ +#include <asm-ppc/dbdma.h> + diff --git a/include/asm-ppc64/keylargo.h b/include/asm-ppc64/keylargo.h new file mode 100644 index 000000000000..4d78e3d0314c --- /dev/null +++ b/include/asm-ppc64/keylargo.h @@ -0,0 +1,2 @@ +#include <asm-ppc/keylargo.h> + diff --git a/include/asm-ppc64/lmb.h b/include/asm-ppc64/lmb.h index af8edcacd3c9..aecc2f36c6b4 100644 --- a/include/asm-ppc64/lmb.h +++ b/include/asm-ppc64/lmb.h @@ -21,8 +21,9 @@ extern unsigned long reloc_offset(void); #define MAX_LMB_REGIONS 64 union lmb_reg_property { - struct reg_property32 addr32[MAX_LMB_REGIONS]; - struct reg_property64 addr64[MAX_LMB_REGIONS]; + struct reg_property32 addr32[MAX_LMB_REGIONS]; + struct reg_property64 addr64[MAX_LMB_REGIONS]; + struct reg_property_pmac addrPM[MAX_LMB_REGIONS]; }; #define LMB_MEMORY_AREA 1 diff --git a/include/asm-ppc64/machdep.h b/include/asm-ppc64/machdep.h index f34d3a824546..513ea51cd358 100644 --- a/include/asm-ppc64/machdep.h +++ b/include/asm-ppc64/machdep.h @@ -69,6 +69,9 @@ struct machdep_calls { void (*init_IRQ)(void); int (*get_irq)(struct pt_regs *); + /* PCI stuff */ + void (*pcibios_fixup)(void); + /* Optional, may be NULL. */ void (*init)(void); @@ -94,11 +97,15 @@ struct machdep_calls { ssize_t (*nvram_write)(char *buf, size_t count, loff_t *index); ssize_t (*nvram_read)(char *buf, size_t count, loff_t *index); + ssize_t (*nvram_size)(void); + int (*nvram_sync)(void); + + /* Motherboard/chipset features. This is a kind of general purpose + * hook used to control some machine specific features (like reset + * lines, chip power control, etc...). + */ + long (*feature_call)(unsigned int feature, ...); -#ifdef CONFIG_SMP - /* functions for dealing with other cpus */ - struct smp_ops_t smp_ops; -#endif /* CONFIG_SMP */ }; extern struct machdep_calls ppc_md; diff --git a/include/asm-ppc64/macio.h b/include/asm-ppc64/macio.h new file mode 100644 index 000000000000..a3028b364f70 --- /dev/null +++ b/include/asm-ppc64/macio.h @@ -0,0 +1,2 @@ +#include <asm-ppc/macio.h> + diff --git a/include/asm-ppc64/mmzone.h b/include/asm-ppc64/mmzone.h index 7503c373f55e..e2b3d7792142 100644 --- a/include/asm-ppc64/mmzone.h +++ b/include/asm-ppc64/mmzone.h @@ -72,9 +72,6 @@ static inline int pa_to_nid(unsigned long pa) #define local_mapnr(kvaddr) \ ( (__pa(kvaddr) >> PAGE_SHIFT) - node_start_pfn(kvaddr_to_nid(kvaddr)) -/* XXX fix - Anton - and wli */ -#define kern_addr_valid(kaddr) (0) - /* Written this way to avoid evaluating arguments twice */ #define discontigmem_pfn_to_page(pfn) \ ({ \ diff --git a/include/asm-ppc64/nvram.h b/include/asm-ppc64/nvram.h index 93b1686a1116..4e6dd370d936 100644 --- a/include/asm-ppc64/nvram.h +++ b/include/asm-ppc64/nvram.h @@ -38,12 +38,15 @@ #define NVRAM_SIG_OF 0x50 /* open firmware config */ #define NVRAM_SIG_FW 0x51 /* general firmware */ #define NVRAM_SIG_HW 0x52 /* hardware (VPD) */ +#define NVRAM_SIG_FLIP 0x5a /* Apple flip/flop header */ +#define NVRAM_SIG_APPL 0x5f /* Apple "system" (???) */ #define NVRAM_SIG_SYS 0x70 /* system env vars */ #define NVRAM_SIG_CFG 0x71 /* config data */ #define NVRAM_SIG_ELOG 0x72 /* error log */ #define NVRAM_SIG_VEND 0x7e /* vendor defined */ #define NVRAM_SIG_FREE 0x7f /* Free space */ #define NVRAM_SIG_OS 0xa0 /* OS defined */ +#define NVRAM_SIG_PANIC 0xa1 /* Apple OSX "panic" */ /* If change this size, then change the size of NVNAME_LEN */ struct nvram_header { @@ -60,11 +63,53 @@ struct nvram_partition { }; -ssize_t pSeries_nvram_read(char *buf, size_t count, loff_t *index); -ssize_t pSeries_nvram_write(char *buf, size_t count, loff_t *index); -int nvram_write_error_log(char * buff, int length, unsigned int err_type); -int nvram_read_error_log(char * buff, int length, unsigned int * err_type); -int nvram_clear_error_log(void); -void nvram_print_partitions(char * label); +extern int nvram_write_error_log(char * buff, int length, unsigned int err_type); +extern int nvram_read_error_log(char * buff, int length, unsigned int * err_type); +extern int nvram_clear_error_log(void); +extern struct nvram_partition *nvram_find_partition(int sig, const char *name); + +extern int pSeries_nvram_init(void); +extern int pmac_nvram_init(void); + +/* PowerMac specific nvram stuffs */ + +enum { + pmac_nvram_OF, /* Open Firmware partition */ + pmac_nvram_XPRAM, /* MacOS XPRAM partition */ + pmac_nvram_NR /* MacOS Name Registry partition */ +}; + +/* Return partition offset in nvram */ +extern int pmac_get_partition(int partition); + +/* Direct access to XPRAM on PowerMacs */ +extern u8 pmac_xpram_read(int xpaddr); +extern void pmac_xpram_write(int xpaddr, u8 data); + +/* Synchronize NVRAM */ +extern int nvram_sync(void); + +/* Some offsets in XPRAM */ +#define PMAC_XPRAM_MACHINE_LOC 0xe4 +#define PMAC_XPRAM_SOUND_VOLUME 0x08 + +/* Machine location structure in PowerMac XPRAM */ +struct pmac_machine_location { + unsigned int latitude; /* 2+30 bit Fractional number */ + unsigned int longitude; /* 2+30 bit Fractional number */ + unsigned int delta; /* mix of GMT delta and DLS */ +}; + +/* + * /dev/nvram ioctls + * + * Note that PMAC_NVRAM_GET_OFFSET is still supported, but is + * definitely obsolete. Do not use it if you can avoid it + */ + +#define OBSOLETE_PMAC_NVRAM_GET_OFFSET \ + _IOWR('p', 0x40, int) + +#define IOC_NVRAM_GET_OFFSET _IOWR('p', 0x42, int) /* Get NVRAM partition offset */ #endif /* _PPC64_NVRAM_H */ diff --git a/include/asm-ppc64/of_device.h b/include/asm-ppc64/of_device.h new file mode 100644 index 000000000000..7bc136e22590 --- /dev/null +++ b/include/asm-ppc64/of_device.h @@ -0,0 +1,2 @@ +#include <asm-ppc/of_device.h> + diff --git a/include/asm-ppc64/pci-bridge.h b/include/asm-ppc64/pci-bridge.h index 33933158cc51..a092b9cae621 100644 --- a/include/asm-ppc64/pci-bridge.h +++ b/include/asm-ppc64/pci-bridge.h @@ -21,7 +21,8 @@ enum phb_types { phb_type_hypervisor = 0x1, phb_type_python = 0x10, phb_type_speedwagon = 0x11, - phb_type_winnipeg = 0x12 + phb_type_winnipeg = 0x12, + phb_type_apple = 0xff }; /* @@ -47,6 +48,8 @@ struct pci_controller { unsigned long pci_io_offset; struct pci_ops *ops; + volatile unsigned int *cfg_addr; + volatile unsigned char *cfg_data; /* Currently, we limit ourselves to 1 IO range and 3 mem * ranges since the common pci_bus structure can't handle more diff --git a/include/asm-ppc64/pci.h b/include/asm-ppc64/pci.h index 60d3832dd934..f2e5f70a4002 100644 --- a/include/asm-ppc64/pci.h +++ b/include/asm-ppc64/pci.h @@ -55,19 +55,62 @@ static inline int pcibios_prep_mwi(struct pci_dev *dev) extern unsigned int pcibios_assign_all_busses(void); -extern void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size, - dma_addr_t *dma_handle); -extern void pci_free_consistent(struct pci_dev *hwdev, size_t size, - void *vaddr, dma_addr_t dma_handle); - -extern dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr, - size_t size, int direction); -extern void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, - size_t size, int direction); -extern int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, - int nents, int direction); -extern void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg, - int nents, int direction); +/* + * PCI DMA operations are abstracted for G5 vs. i/pSeries + */ +struct pci_dma_ops { + void * (*pci_alloc_consistent)(struct pci_dev *hwdev, size_t size, + dma_addr_t *dma_handle); + void (*pci_free_consistent)(struct pci_dev *hwdev, size_t size, + void *vaddr, dma_addr_t dma_handle); + + dma_addr_t (*pci_map_single)(struct pci_dev *hwdev, void *ptr, + size_t size, int direction); + void (*pci_unmap_single)(struct pci_dev *hwdev, dma_addr_t dma_addr, + size_t size, int direction); + int (*pci_map_sg)(struct pci_dev *hwdev, struct scatterlist *sg, + int nents, int direction); + void (*pci_unmap_sg)(struct pci_dev *hwdev, struct scatterlist *sg, + int nents, int direction); +}; + +extern struct pci_dma_ops pci_dma_ops; + +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size, + dma_addr_t *dma_handle) +{ + return pci_dma_ops.pci_alloc_consistent(hwdev, size, dma_handle); +} + +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size, + void *vaddr, dma_addr_t dma_handle) +{ + pci_dma_ops.pci_free_consistent(hwdev, size, vaddr, dma_handle); +} + +static inline dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr, + size_t size, int direction) +{ + return pci_dma_ops.pci_map_single(hwdev, ptr, size, direction); +} + +static inline void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, + size_t size, int direction) +{ + pci_dma_ops.pci_unmap_single(hwdev, dma_addr, size, direction); +} + +static inline int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, + int nents, int direction) +{ + return pci_dma_ops.pci_map_sg(hwdev, sg, nents, direction); +} + +static inline void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg, + int nents, int direction) +{ + pci_dma_ops.pci_unmap_sg(hwdev, sg, nents, direction); +} static inline void pci_dma_sync_single(struct pci_dev *hwdev, dma_addr_t dma_handle, @@ -152,6 +195,8 @@ pcibios_fixup_device_resources(struct pci_dev *dev, struct pci_bus *bus); extern int pci_read_irq_line(struct pci_dev *dev); +extern void pcibios_add_platform_entries(struct pci_dev *dev); + #endif /* __KERNEL__ */ #endif /* __PPC64_PCI_H */ diff --git a/include/asm-ppc64/pci_dma.h b/include/asm-ppc64/pci_dma.h index 7b88d2c35838..bee2fc242da6 100644 --- a/include/asm-ppc64/pci_dma.h +++ b/include/asm-ppc64/pci_dma.h @@ -94,7 +94,9 @@ extern struct TceTable virtBusTceTable; /* Tce table for virtual bus */ extern void create_tce_tables(void); extern void create_pci_bus_tce_table(unsigned long); -void tce_init_pSeries(void); -void tce_init_iSeries(void); +extern void tce_init_pSeries(void); +extern void tce_init_iSeries(void); + +extern void pci_dma_init_direct(void); #endif diff --git a/include/asm-ppc64/pmac_feature.h b/include/asm-ppc64/pmac_feature.h new file mode 100644 index 000000000000..e07e36c4cbb2 --- /dev/null +++ b/include/asm-ppc64/pmac_feature.h @@ -0,0 +1,2 @@ +#include <asm-ppc/pmac_feature.h> + diff --git a/include/asm-ppc64/pmac_low_i2c.h b/include/asm-ppc64/pmac_low_i2c.h new file mode 100644 index 000000000000..7bcfc72c5c8a --- /dev/null +++ b/include/asm-ppc64/pmac_low_i2c.h @@ -0,0 +1,2 @@ +#include <asm-ppc/pmac_low_i2c.h> + diff --git a/include/asm-ppc64/ppcdebug.h b/include/asm-ppc64/ppcdebug.h index 91c31d5284ee..862ae6df6b0b 100644 --- a/include/asm-ppc64/ppcdebug.h +++ b/include/asm-ppc64/ppcdebug.h @@ -95,11 +95,6 @@ extern char *trace_names[64]; #define ppcdebugset(FLAGS) (udbg_ifdebug(FLAGS)) #define PPCDBG_BINFMT (test_thread_flag(TIF_32BIT) ? PPCDBG_BINFMT32 : PPCDBG_BINFMT64) -#ifdef CONFIG_XMON -#define PPCDBG_ENTER_DEBUGGER() xmon(0) -#define PPCDBG_ENTER_DEBUGGER_REGS(X) xmon(X) -#endif - #else #define PPCDBG(...) do {;} while (0) #define PPCDBGCALL(FLAGS,FUNCTION) do {;} while (0) @@ -107,12 +102,4 @@ extern char *trace_names[64]; #define ppcdebugset(FLAGS) (0) #endif /* CONFIG_PPCDBG */ -#ifndef PPCDBG_ENTER_DEBUGGER -#define PPCDBG_ENTER_DEBUGGER() do {;} while(0) -#endif - -#ifndef PPCDBG_ENTER_DEBUGGER_REGS -#define PPCDBG_ENTER_DEBUGGER_REGS(A) do {;} while(0) -#endif - #endif /*__PPCDEBUG_H */ diff --git a/include/asm-ppc64/processor.h b/include/asm-ppc64/processor.h index ffb684f7ab71..1bde268f4d85 100644 --- a/include/asm-ppc64/processor.h +++ b/include/asm-ppc64/processor.h @@ -216,8 +216,11 @@ #define HID0_BHTE (1<<2) /* Branch History Table Enable */ #define HID0_BTCD (1<<1) /* Branch target cache disable */ #define SPRN_MSRDORM 0x3F1 /* Hardware Implementation Register 1 */ +#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ #define SPRN_NIADORM 0x3F3 /* Hardware Implementation Register 2 */ +#define SPRN_HID4 0x3F4 /* 970 HID4 */ +#define SPRN_HID5 0x3F6 /* 970 HID5 */ #define SPRN_TSC 0x3FD /* Thread switch control */ #define SPRN_TST 0x3FC /* Thread switch timeout */ #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ @@ -263,6 +266,7 @@ #define SPRN_TBRU 0x10D /* Time Base Read Upper Register (user, R/O) */ #define SPRN_TBWL 0x11C /* Time Base Lower Register (super, W/O) */ #define SPRN_TBWU 0x11D /* Time Base Write Upper Register (super, W/O) */ +#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */ #define SPRN_TCR 0x3DA /* Timer Control Register */ #define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ #define WP_2_17 0 /* 2^17 clocks */ @@ -373,6 +377,7 @@ #define PV_ICESTAR 0x0036 #define PV_SSTAR 0x0037 #define PV_POWER4p 0x0038 +#define PV_GPUL 0x0039 #define PV_POWER5 0x003A #define PV_630 0x0040 #define PV_630p 0x0041 @@ -382,7 +387,12 @@ #define PLATFORM_PSERIES_LPAR 0x0101 #define PLATFORM_ISERIES_LPAR 0x0201 #define PLATFORM_LPAR 0x0001 - +#define PLATFORM_POWERMAC 0x0400 + +/* Compatibility with drivers coming from PPC32 world */ +#define _machine (systemcfg->platform) +#define _MACH_Pmac PLATFORM_POWERMAC + /* * List of interrupt controllers. */ @@ -457,6 +467,14 @@ GLUE(.,name): asm volatile("mfasr %0" : "=r" (rval)); rval;}) #ifndef __ASSEMBLY__ + +static inline void set_tb(unsigned int upper, unsigned int lower) +{ + mttbl(0); + mttbu(upper); + mttbl(lower); +} + extern unsigned long *_get_SP(void); extern int have_of; diff --git a/include/asm-ppc64/prom.h b/include/asm-ppc64/prom.h index 988f5a272be4..f54c47efde42 100644 --- a/include/asm-ppc64/prom.h +++ b/include/asm-ppc64/prom.h @@ -108,6 +108,12 @@ struct reg_property64 { unsigned long size; }; +struct reg_property_pmac { + unsigned int address_hi; + unsigned int address_lo; + unsigned int size; +}; + struct translation_property { unsigned long virt; unsigned long size; @@ -207,6 +213,7 @@ struct prom_args { struct prom_t { unsigned long entry; + ihandle root; ihandle chosen; int cpu; ihandle stdout; diff --git a/include/asm-ppc64/sections.h b/include/asm-ppc64/sections.h index b74722491931..95bac41d79b8 100644 --- a/include/asm-ppc64/sections.h +++ b/include/asm-ppc64/sections.h @@ -5,4 +5,16 @@ extern char _end[]; #include <asm-generic/sections.h> +#define __pmac +#define __pmacdata + +#define __prep +#define __prepdata + +#define __chrp +#define __chrpdata + +#define __openfirmware +#define __openfirmwaredata + #endif diff --git a/include/asm-ppc64/smp.h b/include/asm-ppc64/smp.h index c54f858b3b85..7c8fae309721 100644 --- a/include/asm-ppc64/smp.h +++ b/include/asm-ppc64/smp.h @@ -29,8 +29,7 @@ #ifdef CONFIG_SMP extern void smp_message_pass(int target, int msg, unsigned long data, int wait); -extern void smp_send_tlb_invalidate(int); -extern void smp_send_xmon_break(int cpu); +extern void smp_send_debugger_break(int cpu); struct pt_regs; extern void smp_message_recv(int, struct pt_regs *); @@ -63,17 +62,22 @@ extern cpumask_t cpu_available_map; * in /proc/interrupts will be wrong!!! --Troy */ #define PPC_MSG_CALL_FUNCTION 0 #define PPC_MSG_RESCHEDULE 1 +/* This is unused now */ +#if 0 #define PPC_MSG_MIGRATE_TASK 2 -#define PPC_MSG_XMON_BREAK 3 +#endif +#define PPC_MSG_DEBUGGER_BREAK 3 void smp_init_iSeries(void); void smp_init_pSeries(void); #endif /* !(CONFIG_SMP) */ -#endif /* __ASSEMBLY__ */ #define get_hard_smp_processor_id(CPU) (paca[(CPU)].xHwProcNum) -#define set_hard_smp_processor_id(CPU, VAL) do { (paca[(CPU)].xHwProcNum = VAL); } while (0) +#define set_hard_smp_processor_id(CPU, VAL) \ + do { (paca[(CPU)].xHwProcNum = VAL); } while (0) + +#endif /* __ASSEMBLY__ */ #endif /* !(_PPC64_SMP_H) */ #endif /* __KERNEL__ */ diff --git a/include/asm-ppc64/system.h b/include/asm-ppc64/system.h index 2a88765fd600..7080a2c3cb23 100644 --- a/include/asm-ppc64/system.h +++ b/include/asm-ppc64/system.h @@ -9,6 +9,7 @@ */ #include <linux/config.h> +#include <linux/compiler.h> #include <asm/page.h> #include <asm/processor.h> #include <asm/hw_irq.h> @@ -52,31 +53,41 @@ #define smp_read_barrier_depends() do { } while(0) #endif /* CONFIG_SMP */ -#ifdef CONFIG_DEBUG_KERNEL -extern void (*debugger)(struct pt_regs *regs); -extern int (*debugger_bpt)(struct pt_regs *regs); -extern int (*debugger_sstep)(struct pt_regs *regs); -extern int (*debugger_iabr_match)(struct pt_regs *regs); -extern int (*debugger_dabr_match)(struct pt_regs *regs); -extern void (*debugger_fault_handler)(struct pt_regs *regs); +#ifdef CONFIG_DEBUGGER + +extern int (*__debugger)(struct pt_regs *regs); +extern int (*__debugger_bpt)(struct pt_regs *regs); +extern int (*__debugger_sstep)(struct pt_regs *regs); +extern int (*__debugger_iabr_match)(struct pt_regs *regs); +extern int (*__debugger_dabr_match)(struct pt_regs *regs); +extern int (*__debugger_fault_handler)(struct pt_regs *regs); + +#define DEBUGGER_BOILERPLATE(__NAME) \ +static inline int __NAME(struct pt_regs *regs) \ +{ \ + if (unlikely(__ ## __NAME)) \ + return __ ## __NAME(regs); \ + return 0; \ +} + +DEBUGGER_BOILERPLATE(debugger) +DEBUGGER_BOILERPLATE(debugger_bpt) +DEBUGGER_BOILERPLATE(debugger_sstep) +DEBUGGER_BOILERPLATE(debugger_iabr_match) +DEBUGGER_BOILERPLATE(debugger_dabr_match) +DEBUGGER_BOILERPLATE(debugger_fault_handler) + +#ifdef CONFIG_XMON +extern void xmon_init(void); +#endif + #else -#define debugger(regs) do { } while (0) +#define debugger(regs) 0 #define debugger_bpt(regs) 0 #define debugger_sstep(regs) 0 #define debugger_iabr_match(regs) 0 #define debugger_dabr_match(regs) 0 -#define debugger_fault_handler ((void (*)(struct pt_regs *))0) -#endif - -#ifdef CONFIG_XMON -extern void xmon_irq(int, void *, struct pt_regs *); - -extern void xmon(struct pt_regs *regs); -extern int xmon_bpt(struct pt_regs *regs); -extern int xmon_sstep(struct pt_regs *regs); -extern int xmon_iabr_match(struct pt_regs *regs); -extern int xmon_dabr_match(struct pt_regs *regs); -extern void (*xmon_fault_handler)(struct pt_regs *regs); +#define debugger_fault_handler(regs) 0 #endif extern void show_regs(struct pt_regs * regs); diff --git a/include/asm-ppc64/systemcfg.h b/include/asm-ppc64/systemcfg.h index b78c5a2828ca..72b5adba9325 100644 --- a/include/asm-ppc64/systemcfg.h +++ b/include/asm-ppc64/systemcfg.h @@ -72,6 +72,7 @@ extern struct systemcfg *systemcfg; #define PV_ICESTAR 0x0036 #define PV_SSTAR 0x0037 #define PV_POWER4p 0x0038 +#define PV_GPUL 0x0039 #define PV_630 0x0040 #define PV_630p 0x0041 @@ -79,6 +80,11 @@ extern struct systemcfg *systemcfg; #define PLATFORM_PSERIES 0x0100 #define PLATFORM_PSERIES_LPAR 0x0101 #define PLATFORM_ISERIES_LPAR 0x0201 +#define PLATFORM_POWERMAC 0x0400 + +/* Compatibility with drivers coming from PPC32 world */ +#define _machine (systemcfg->platform) +#define _MACH_Pmac PLATFORM_POWERMAC static inline volatile struct systemcfg *systemcfg_init(void) diff --git a/include/asm-ppc64/uninorth.h b/include/asm-ppc64/uninorth.h new file mode 100644 index 000000000000..7ad7059f2c80 --- /dev/null +++ b/include/asm-ppc64/uninorth.h @@ -0,0 +1,2 @@ +#include <asm-ppc/uninorth.h> + diff --git a/include/asm-sh/hd64461/hd64461.h b/include/asm-sh/hd64461/hd64461.h index 4badb6e0c58b..306541673860 100644 --- a/include/asm-sh/hd64461/hd64461.h +++ b/include/asm-sh/hd64461/hd64461.h @@ -1,20 +1,40 @@ #ifndef __ASM_SH_HD64461 #define __ASM_SH_HD64461 /* - * $Id: hd64461.h,v 1.3 2003/05/04 19:30:14 lethal Exp $ + * $Id: hd64461.h,v 1.4 2004/02/01 19:46:04 lethal Exp $ * Copyright (C) 2000 YAEGASHI Takeshi * Hitachi HD64461 companion chip support */ #include <linux/config.h> #define HD64461_STBCR 0x10000 +#define HD64461_STBCR_CKIO_STBY 0x2000 +#define HD64461_STBCR_SAFECKE_IST 0x1000 +#define HD64461_STBCR_SLCKE_IST 0x0800 +#define HD64461_STBCR_SAFECKE_OST 0x0400 +#define HD64461_STBCR_SLCKE_OST 0x0200 +#define HD64461_STBCR_SMIAST 0x0100 +#define HD64461_STBCR_SLCDST 0x0080 +#define HD64461_STBCR_SPC0ST 0x0040 +#define HD64461_STBCR_SPC1ST 0x0020 +#define HD64461_STBCR_SAFEST 0x0010 +#define HD64461_STBCR_STM0ST 0x0008 +#define HD64461_STBCR_STM1ST 0x0004 +#define HD64461_STBCR_SIRST 0x0002 +#define HD64461_STBCR_SURTSD 0x0001 + #define HD64461_SYSCR 0x10002 #define HD64461_SCPUCR 0x10004 #define HD64461_LCDCBAR 0x11000 #define HD64461_LCDCLOR 0x11002 -#define HD64461_LCDCCRR 0x11004 +#define HD64461_LCDCCR 0x11004 +#define HD64461_LCDCCR_MOFF 0x80 + #define HD64461_LDR1 0x11010 +#define HD64461_LDR1_DON 0x01 +#define HD64461_LDR1_DINV 0x80 + #define HD64461_LDR2 0x11012 #define HD64461_LDHNCR 0x11014 #define HD64461_LDHNSR 0x11016 @@ -28,6 +48,35 @@ #define HD64461_CPTRAR 0x11034 #define HD64461_CPTRDR 0x11036 +#define HD64461_GRDOR 0x11040 +#define HD64461_GRSCR 0x11042 +#define HD64461_GRCFGR 0x11044 +#define HD64461_GRCFGR_ACCSTATUS 0x10 +#define HD64461_GRCFGR_ACCRESET 0x08 +#define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 +#define HD64461_GRCFGR_ACCSTART_LINE 0x04 +#define HD64461_GRCFGR_COLORDEPTH16 0x01 + +#define HD64461_LNSARH 0x11046 +#define HD64461_LNSARL 0x11048 +#define HD64461_LNAXLR 0x1104a +#define HD64461_LNDGR 0x1104c +#define HD64461_LNAXR 0x1104e +#define HD64461_LNERTR 0x11050 +#define HD64461_LNMDR 0x11052 +#define HD64461_BBTSSARH 0x11054 +#define HD64461_BBTSSARL 0x11056 +#define HD64461_BBTDSARH 0x11058 +#define HD64461_BBTDSARL 0x1105a +#define HD64461_BBTDWR 0x1105c +#define HD64461_BBTDHR 0x1105e +#define HD64461_BBTPARH 0x11060 +#define HD64461_BBTPARL 0x11062 +#define HD64461_BBTMARH 0x11064 +#define HD64461_BBTMARL 0x11066 +#define HD64461_BBTROPR 0x11068 +#define HD64461_BBTMDR 0x1106a + #define HD64461_PCC0ISR 0x12000 #define HD64461_PCC0GCR 0x12002 #define HD64461_PCC0CSCR 0x12004 diff --git a/include/asm-sh/hd64461/io.h b/include/asm-sh/hd64461/io.h index 03753b6d458a..a4c22eb98689 100644 --- a/include/asm-sh/hd64461/io.h +++ b/include/asm-sh/hd64461/io.h @@ -23,6 +23,15 @@ extern void hd64461_outl(unsigned int value, unsigned long port); extern unsigned char hd64461_inb_p(unsigned long port); extern void hd64461_outb_p(unsigned char value, unsigned long port); +extern void hd64461_insb(unsigned long port, const void *buffer, unsigned long count); +extern void hd64461_insw(unsigned long port, const void *buffer, unsigned long count); +extern void hd64461_insl(unsigned long port, const void *buffer, unsigned long count); + +extern void hd64461_outsb(unsigned long port, const void *buffer, unsigned long count); +extern void hd64461_outsw(unsigned long port, const void *buffer, unsigned long count); +extern void hd64461_outsl(unsigned long port, const void *buffer, unsigned long count); + + extern int hd64461_irq_demux(int irq); #endif /* _ASM_SH_IO_HD64461_H */ diff --git a/include/asm-sh/io_generic.h b/include/asm-sh/io_generic.h new file mode 100644 index 000000000000..be14587342f7 --- /dev/null +++ b/include/asm-sh/io_generic.h @@ -0,0 +1,51 @@ +/* + * include/asm-sh/io_generic.h + * + * Copyright 2000 Stuart Menefy (stuart.menefy@st.com) + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + * + * Generic IO functions + */ + +#ifndef _ASM_SH_IO_GENERIC_H +#define _ASM_SH_IO_GENERIC_H + +extern unsigned long generic_io_base; + +extern unsigned char generic_inb(unsigned long port); +extern unsigned short generic_inw(unsigned long port); +extern unsigned int generic_inl(unsigned long port); + +extern void generic_outb(unsigned char value, unsigned long port); +extern void generic_outw(unsigned short value, unsigned long port); +extern void generic_outl(unsigned int value, unsigned long port); + +extern unsigned char generic_inb_p(unsigned long port); +extern unsigned short generic_inw_p(unsigned long port); +extern unsigned int generic_inl_p(unsigned long port); +extern void generic_outb_p(unsigned char value, unsigned long port); +extern void generic_outw_p(unsigned short value, unsigned long port); +extern void generic_outl_p(unsigned int value, unsigned long port); + +extern void generic_insb(unsigned long port, void *addr, unsigned long count); +extern void generic_insw(unsigned long port, void *addr, unsigned long count); +extern void generic_insl(unsigned long port, void *addr, unsigned long count); +extern void generic_outsb(unsigned long port, const void *addr, unsigned long count); +extern void generic_outsw(unsigned long port, const void *addr, unsigned long count); +extern void generic_outsl(unsigned long port, const void *addr, unsigned long count); + +extern unsigned char generic_readb(unsigned long addr); +extern unsigned short generic_readw(unsigned long addr); +extern unsigned int generic_readl(unsigned long addr); +extern void generic_writeb(unsigned char b, unsigned long addr); +extern void generic_writew(unsigned short b, unsigned long addr); +extern void generic_writel(unsigned int b, unsigned long addr); + +extern void *generic_ioremap(unsigned long offset, unsigned long size); +extern void generic_iounmap(void *addr); + +extern unsigned long generic_isa_port2addr(unsigned long offset); + +#endif /* _ASM_SH_IO_GENERIC_H */ diff --git a/include/asm-sh/pci.h b/include/asm-sh/pci.h index fe2c08b2e7cd..b16a62e61771 100644 --- a/include/asm-sh/pci.h +++ b/include/asm-sh/pci.h @@ -256,6 +256,10 @@ extern void pcibios_fixup_irqs(void); extern int pciauto_assign_resources(int busno, struct pci_channel *hose); #endif +static inline void pcibios_add_platform_entries(struct pci_dev *dev) +{ +} + #endif /* __KERNEL__ */ /* generic pci stuff */ diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h index e570e71cbeb5..215b7e12e6ca 100644 --- a/include/asm-sh/processor.h +++ b/include/asm-sh/processor.h @@ -12,6 +12,7 @@ #include <asm/types.h> #include <asm/cache.h> #include <linux/threads.h> +#include <asm/ptrace.h> /* * Default implementation of macro that returns current @@ -167,7 +168,7 @@ extern int ubc_usercnt; #define start_thread(regs, new_pc, new_sp) \ set_fs(USER_DS); \ regs->pr = 0; \ - regs->sr = 0; /* User mode. */ \ + regs->sr = SR_FD; /* User mode. */ \ regs->pc = new_pc; \ regs->regs[15] = new_sp @@ -200,7 +201,7 @@ extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); * FPU lazy state save handling. */ -static __inline__ void release_fpu(void) +static __inline__ void disable_fpu(void) { unsigned long __dummy; @@ -212,7 +213,7 @@ static __inline__ void release_fpu(void) : "r" (SR_FD)); } -static __inline__ void grab_fpu(void) +static __inline__ void enable_fpu(void) { unsigned long __dummy; @@ -224,22 +225,32 @@ static __inline__ void grab_fpu(void) : "r" (~SR_FD)); } +static __inline__ void release_fpu(struct pt_regs *regs) +{ + regs->sr |= SR_FD; +} + +static __inline__ void grab_fpu(struct pt_regs *regs) +{ + regs->sr &= ~SR_FD; +} + #ifdef CONFIG_CPU_SH4 -extern void save_fpu(struct task_struct *__tsk); +extern void save_fpu(struct task_struct *__tsk, struct pt_regs *regs); #else #define save_fpu(tsk) do { } while (0) #endif -#define unlazy_fpu(tsk) do { \ +#define unlazy_fpu(tsk, regs) do { \ if (test_tsk_thread_flag(tsk, TIF_USEDFPU)) { \ - save_fpu(tsk); \ + save_fpu(tsk, regs); \ } \ } while (0) -#define clear_fpu(tsk) do { \ +#define clear_fpu(tsk, regs) do { \ if (test_tsk_thread_flag(tsk, TIF_USEDFPU)) { \ clear_tsk_thread_flag(tsk, TIF_USEDFPU); \ - release_fpu(); \ + release_fpu(regs); \ } \ } while (0) diff --git a/include/asm-sh/ptrace.h b/include/asm-sh/ptrace.h index 7931ef8f859b..d0ca02c926bf 100644 --- a/include/asm-sh/ptrace.h +++ b/include/asm-sh/ptrace.h @@ -1,7 +1,6 @@ #ifndef __ASM_SH_PTRACE_H #define __ASM_SH_PTRACE_H -#include <asm/processor.h> #include <asm/ubc.h> /* diff --git a/include/asm-sparc/atomic.h b/include/asm-sparc/atomic.h index f42ba9526265..873f806fc678 100644 --- a/include/asm-sparc/atomic.h +++ b/include/asm-sparc/atomic.h @@ -2,21 +2,82 @@ * * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) * Copyright (C) 2000 Anton Blanchard (anton@linuxcare.com.au) + * + * Additions by Keith M Wesolowski (wesolows@foobazco.org) based + * on asm-parisc/atomic.h Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>. */ #ifndef __ARCH_SPARC_ATOMIC__ #define __ARCH_SPARC_ATOMIC__ #include <linux/config.h> +#include <linux/spinlock.h> typedef struct { volatile int counter; } atomic_t; #ifdef __KERNEL__ -#ifndef CONFIG_SMP + +#ifdef CONFIG_SMP + +#define ATOMIC_HASH_SIZE 4 +#define ATOMIC_HASH(a) (&__atomic_hash[(((unsigned long)a)>>8) & (ATOMIC_HASH_SIZE-1)]) +extern spinlock_t __atomic_hash[ATOMIC_HASH_SIZE]; + +#else /* SMP */ + +#define ATOMIC_HASH_SIZE 1 +#define ATOMIC_HASH(a) 0 + +#endif /* SMP */ + +static inline int __atomic_add_return(int i, atomic_t *v) +{ + int ret; + unsigned long flags; + spin_lock_irqsave(ATOMIC_HASH(v), flags); + + ret = (v->counter += i); + + spin_unlock_irqrestore(ATOMIC_HASH(v), flags); + return ret; +} + +static inline void atomic_set(atomic_t *v, int i) +{ + unsigned long flags; + spin_lock_irqsave(ATOMIC_HASH(v), flags); + + v->counter = i; + + spin_unlock_irqrestore(ATOMIC_HASH(v), flags); +} #define ATOMIC_INIT(i) { (i) } + #define atomic_read(v) ((v)->counter) -#define atomic_set(v, i) (((v)->counter) = i) + +#define atomic_add(i, v) ((void)__atomic_add_return( (int)(i), (v))) +#define atomic_sub(i, v) ((void)__atomic_add_return(-(int)(i), (v))) +#define atomic_inc(v) ((void)__atomic_add_return( 1, (v))) +#define atomic_dec(v) ((void)__atomic_add_return( -1, (v))) + +#define atomic_add_return(i, v) (__atomic_add_return( (int)(i), (v))) +#define atomic_sub_return(i, v) (__atomic_add_return(-(int)(i), (v))) +#define atomic_inc_return(v) (__atomic_add_return( 1, (v))) +#define atomic_dec_return(v) (__atomic_add_return( -1, (v))) + +#define atomic_dec_and_test(v) (atomic_dec_return(v) == 0) + +/* This is the old 24-bit implementation. It's still used internally + * by some sparc-specific code, notably the semaphore implementation. + */ +typedef struct { volatile int counter; } atomic24_t; + +#ifndef CONFIG_SMP + +#define ATOMIC24_INIT(i) { (i) } +#define atomic24_read(v) ((v)->counter) +#define atomic24_set(v, i) (((v)->counter) = i) #else /* We do the bulk of the actual work out of line in two common @@ -33,9 +94,9 @@ typedef struct { volatile int counter; } atomic_t; * 31 8 7 0 */ -#define ATOMIC_INIT(i) { ((i) << 8) } +#define ATOMIC24_INIT(i) { ((i) << 8) } -static __inline__ int atomic_read(const atomic_t *v) +static inline int atomic24_read(const atomic24_t *v) { int ret = v->counter; @@ -45,10 +106,10 @@ static __inline__ int atomic_read(const atomic_t *v) return ret >> 8; } -#define atomic_set(v, i) (((v)->counter) = ((i) << 8)) +#define atomic24_set(v, i) (((v)->counter) = ((i) << 8)) #endif -static inline int __atomic_add(int i, atomic_t *v) +static inline int __atomic24_add(int i, atomic24_t *v) { register volatile int *ptr asm("g1"); register int increment asm("g2"); @@ -61,7 +122,7 @@ static inline int __atomic_add(int i, atomic_t *v) __asm__ __volatile__( "mov %%o7, %%g4\n\t" - "call ___atomic_add\n\t" + "call ___atomic24_add\n\t" " add %%o7, 8, %%o7\n" : "=&r" (increment), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3) : "0" (increment), "r" (ptr) @@ -70,7 +131,7 @@ static inline int __atomic_add(int i, atomic_t *v) return increment; } -static inline int __atomic_sub(int i, atomic_t *v) +static inline int __atomic24_sub(int i, atomic24_t *v) { register volatile int *ptr asm("g1"); register int increment asm("g2"); @@ -83,7 +144,7 @@ static inline int __atomic_sub(int i, atomic_t *v) __asm__ __volatile__( "mov %%o7, %%g4\n\t" - "call ___atomic_sub\n\t" + "call ___atomic24_sub\n\t" " add %%o7, 8, %%o7\n" : "=&r" (increment), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3) : "0" (increment), "r" (ptr) @@ -92,19 +153,19 @@ static inline int __atomic_sub(int i, atomic_t *v) return increment; } -#define atomic_add(i, v) ((void)__atomic_add((i), (v))) -#define atomic_sub(i, v) ((void)__atomic_sub((i), (v))) +#define atomic24_add(i, v) ((void)__atomic24_add((i), (v))) +#define atomic24_sub(i, v) ((void)__atomic24_sub((i), (v))) -#define atomic_dec_return(v) __atomic_sub(1, (v)) -#define atomic_inc_return(v) __atomic_add(1, (v)) +#define atomic24_dec_return(v) __atomic24_sub(1, (v)) +#define atomic24_inc_return(v) __atomic24_add(1, (v)) -#define atomic_sub_and_test(i, v) (__atomic_sub((i), (v)) == 0) -#define atomic_dec_and_test(v) (__atomic_sub(1, (v)) == 0) +#define atomic24_sub_and_test(i, v) (__atomic24_sub((i), (v)) == 0) +#define atomic24_dec_and_test(v) (__atomic24_sub(1, (v)) == 0) -#define atomic_inc(v) ((void)__atomic_add(1, (v))) -#define atomic_dec(v) ((void)__atomic_sub(1, (v))) +#define atomic24_inc(v) ((void)__atomic24_add(1, (v))) +#define atomic24_dec(v) ((void)__atomic24_sub(1, (v))) -#define atomic_add_negative(i, v) (__atomic_add((i), (v)) < 0) +#define atomic24_add_negative(i, v) (__atomic24_add((i), (v)) < 0) /* Atomic operations are already serializing */ #define smp_mb__before_atomic_dec() barrier() diff --git a/include/asm-sparc/dma-mapping.h b/include/asm-sparc/dma-mapping.h index 779cfef77d00..2dc5bb8effa6 100644 --- a/include/asm-sparc/dma-mapping.h +++ b/include/asm-sparc/dma-mapping.h @@ -1,5 +1,25 @@ +#ifndef _ASM_SPARC_DMA_MAPPING_H +#define _ASM_SPARC_DMA_MAPPING_H + #include <linux/config.h> #ifdef CONFIG_PCI #include <asm-generic/dma-mapping.h> -#endif +#else + +static inline void *dma_alloc_coherent(struct device *dev, size_t size, + dma_addr_t *dma_handle, int flag) +{ + BUG(); + return NULL; +} + +static inline void dma_free_coherent(struct device *dev, size_t size, + void *vaddr, dma_addr_t dma_handle) +{ + BUG(); +} + +#endif /* PCI */ + +#endif /* _ASM_SPARC_DMA_MAPPING_H */ diff --git a/include/asm-sparc/pci.h b/include/asm-sparc/pci.h index e97afc5a44db..e78d2cbf0426 100644 --- a/include/asm-sparc/pci.h +++ b/include/asm-sparc/pci.h @@ -141,6 +141,10 @@ extern inline int pci_dma_supported(struct pci_dev *hwdev, u64 mask) #define pci_dac_dma_supported(dev, mask) (0) +static inline void pcibios_add_platform_entries(struct pci_dev *dev) +{ +} + #endif /* __KERNEL__ */ /* generic pci stuff */ diff --git a/include/asm-sparc/processor.h b/include/asm-sparc/processor.h index b0c5a0d09204..0a9a4f5bc585 100644 --- a/include/asm-sparc/processor.h +++ b/include/asm-sparc/processor.h @@ -22,7 +22,6 @@ #include <asm/segment.h> #include <asm/btfixup.h> #include <asm/page.h> -#include <asm/atomic.h> /* * Bus types diff --git a/include/asm-sparc/semaphore.h b/include/asm-sparc/semaphore.h index 0e6122ae3058..b3b16d121ace 100644 --- a/include/asm-sparc/semaphore.h +++ b/include/asm-sparc/semaphore.h @@ -10,7 +10,7 @@ #include <linux/rwsem.h> struct semaphore { - atomic_t count; + atomic24_t count; int sleepers; wait_queue_head_t wait; #if WAITQUEUE_DEBUG @@ -40,7 +40,7 @@ struct semaphore { static inline void sema_init (struct semaphore *sem, int val) { - atomic_set(&sem->count, val); + atomic24_set(&sem->count, val); sem->sleepers = 0; init_waitqueue_head(&sem->wait); #if WAITQUEUE_DEBUG @@ -78,7 +78,7 @@ static inline void down(struct semaphore * sem) __asm__ __volatile__( "mov %%o7, %%g4\n\t" - "call ___atomic_sub\n\t" + "call ___atomic24_sub\n\t" " add %%o7, 8, %%o7\n\t" "tst %%g2\n\t" "bl 2f\n\t" @@ -115,7 +115,7 @@ static inline int down_interruptible(struct semaphore * sem) __asm__ __volatile__( "mov %%o7, %%g4\n\t" - "call ___atomic_sub\n\t" + "call ___atomic24_sub\n\t" " add %%o7, 8, %%o7\n\t" "tst %%g2\n\t" "bl 2f\n\t" @@ -154,7 +154,7 @@ static inline int down_trylock(struct semaphore * sem) __asm__ __volatile__( "mov %%o7, %%g4\n\t" - "call ___atomic_sub\n\t" + "call ___atomic24_sub\n\t" " add %%o7, 8, %%o7\n\t" "tst %%g2\n\t" "bl 2f\n\t" @@ -193,7 +193,7 @@ static inline void up(struct semaphore * sem) __asm__ __volatile__( "mov %%o7, %%g4\n\t" - "call ___atomic_add\n\t" + "call ___atomic24_add\n\t" " add %%o7, 8, %%o7\n\t" "tst %%g2\n\t" "ble 2f\n\t" diff --git a/include/asm-sparc/system.h b/include/asm-sparc/system.h index b53cf2c6897e..a4c7d566e075 100644 --- a/include/asm-sparc/system.h +++ b/include/asm-sparc/system.h @@ -171,32 +171,11 @@ extern void fpsave(unsigned long *fpregs, unsigned long *fsr, /* * Changing the IRQ level on the Sparc. */ -extern __inline__ void setipl(unsigned long __orig_psr) -{ - __asm__ __volatile__( - "wr %0, 0x0, %%psr\n\t" - "nop; nop; nop\n" - : /* no outputs */ - : "r" (__orig_psr) - : "memory", "cc"); -} +extern void local_irq_restore(unsigned long); +extern unsigned long __local_irq_save(void); +extern void local_irq_enable(void); -extern __inline__ void local_irq_enable(void) -{ - unsigned long tmp; - - __asm__ __volatile__( - "rd %%psr, %0\n\t" - "nop; nop; nop;\n\t" /* Sun4m + Cypress + SMP bug */ - "andn %0, %1, %0\n\t" - "wr %0, 0x0, %%psr\n\t" - "nop; nop; nop\n" - : "=r" (tmp) - : "i" (PSR_PIL) - : "memory"); -} - -extern __inline__ unsigned long getipl(void) +static inline unsigned long getipl(void) { unsigned long retval; @@ -204,76 +183,11 @@ extern __inline__ unsigned long getipl(void) return retval; } -#if 0 /* not used */ -extern __inline__ unsigned long swap_pil(unsigned long __new_psr) -{ - unsigned long retval; - - __asm__ __volatile__( - "rd %%psr, %0\n\t" - "nop; nop; nop;\n\t" /* Sun4m + Cypress + SMP bug */ - "and %0, %2, %%g1\n\t" - "and %1, %2, %%g2\n\t" - "xorcc %%g1, %%g2, %%g0\n\t" - "be 1f\n\t" - " nop\n\t" - "wr %0, %2, %%psr\n\t" - "nop; nop; nop;\n" - "1:\n" - : "=&r" (retval) - : "r" (__new_psr), "i" (PSR_PIL) - : "g1", "g2", "memory", "cc"); - - return retval; -} -#endif - -extern __inline__ unsigned long read_psr_and_cli(void) -{ - unsigned long retval; - - __asm__ __volatile__( - "rd %%psr, %0\n\t" - "nop; nop; nop;\n\t" /* Sun4m + Cypress + SMP bug */ - "or %0, %1, %%g1\n\t" - "wr %%g1, 0x0, %%psr\n\t" - "nop; nop; nop\n\t" - : "=r" (retval) - : "i" (PSR_PIL) - : "g1", "memory"); - - return retval; -} - #define local_save_flags(flags) ((flags) = getipl()) -#define local_irq_save(flags) ((flags) = read_psr_and_cli()) -#define local_irq_restore(flags) setipl((flags)) -#define local_irq_disable() ((void) read_psr_and_cli()) - +#define local_irq_save(flags) ((flags) = __local_irq_save()) +#define local_irq_disable() ((void) __local_irq_save()) #define irqs_disabled() ((getipl() & PSR_PIL) != 0) -#ifdef CONFIG_SMP - -extern unsigned char global_irq_holder; - -#define save_and_cli(flags) do { save_flags(flags); cli(); } while(0) - -extern void __global_cli(void); -extern void __global_sti(void); -extern unsigned long __global_save_flags(void); -extern void __global_restore_flags(unsigned long flags); -#define cli() __global_cli() -#define sti() __global_sti() -#define save_flags(flags) ((flags)=__global_save_flags()) -#define restore_flags(flags) __global_restore_flags(flags) - -#else - -#define cli() local_irq_disable() -#define sti() local_irq_enable() - -#endif - /* XXX Change this if we ever use a PSO mode kernel. */ #define mb() __asm__ __volatile__ ("" : : : "memory") #define rmb() mb() diff --git a/include/asm-sparc/unistd.h b/include/asm-sparc/unistd.h index 044ab5ab5747..695768130a4c 100644 --- a/include/asm-sparc/unistd.h +++ b/include/asm-sparc/unistd.h @@ -285,14 +285,14 @@ #define __NR_timer_create 266 /* #define __NR_vserver 267 Reserved for VSERVER */ #define __NR_io_setup 268 -#define __NR_io_destroy 268 -#define __NR_io_submit 269 -#define __NR_io_cancel 270 -#define __NR_io_getevents 271 -/* WARNING: You MAY NOT add syscall numbers larger than 271, since +#define __NR_io_destroy 269 +#define __NR_io_submit 270 +#define __NR_io_cancel 271 +#define __NR_io_getevents 272 +/* WARNING: You MAY NOT add syscall numbers larger than 272, since * all of the syscall tables in the Sparc kernel are - * sized to have 272 entries (starting at zero). Therefore - * find a free slot in the 0-271 range. + * sized to have 273 entries (starting at zero). Therefore + * find a free slot in the 0-272 range. */ #define _syscall0(type,name) \ diff --git a/include/asm-sparc64/dma-mapping.h b/include/asm-sparc64/dma-mapping.h index 779cfef77d00..1c5da41653a4 100644 --- a/include/asm-sparc64/dma-mapping.h +++ b/include/asm-sparc64/dma-mapping.h @@ -1,5 +1,27 @@ +#ifndef _ASM_SPARC64_DMA_MAPPING_H +#define _ASM_SPARC64_DMA_MAPPING_H + #include <linux/config.h> #ifdef CONFIG_PCI #include <asm-generic/dma-mapping.h> -#endif +#else + +struct device; + +static inline void *dma_alloc_coherent(struct device *dev, size_t size, + dma_addr_t *dma_handle, int flag) +{ + BUG(); + return NULL; +} + +static inline void dma_free_coherent(struct device *dev, size_t size, + void *vaddr, dma_addr_t dma_handle) +{ + BUG(); +} + +#endif /* PCI */ + +#endif /* _ASM_SPARC64_DMA_MAPPING_H */ diff --git a/include/asm-sparc64/pci.h b/include/asm-sparc64/pci.h index ea722dcb49d8..e64c30c45b10 100644 --- a/include/asm-sparc64/pci.h +++ b/include/asm-sparc64/pci.h @@ -215,6 +215,10 @@ extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, struct pci_bus_region *region); +static inline void pcibios_add_platform_entries(struct pci_dev *dev) +{ +} + #endif /* __KERNEL__ */ #endif /* __SPARC64_PCI_H */ diff --git a/include/asm-sparc64/unistd.h b/include/asm-sparc64/unistd.h index defdb109015b..109d44cfabfe 100644 --- a/include/asm-sparc64/unistd.h +++ b/include/asm-sparc64/unistd.h @@ -287,14 +287,14 @@ #define __NR_timer_create 266 /* #define __NR_vserver 267 Reserved for VSERVER */ #define __NR_io_setup 268 -#define __NR_io_destroy 268 -#define __NR_io_submit 269 -#define __NR_io_cancel 270 -#define __NR_io_getevents 271 -/* WARNING: You MAY NOT add syscall numbers larger than 271, since +#define __NR_io_destroy 269 +#define __NR_io_submit 270 +#define __NR_io_cancel 271 +#define __NR_io_getevents 272 +/* WARNING: You MAY NOT add syscall numbers larger than 272, since * all of the syscall tables in the Sparc kernel are - * sized to have 272 entries (starting at zero). Therefore - * find a free slot in the 0-271 range. + * sized to have 273 entries (starting at zero). Therefore + * find a free slot in the 0-272 range. */ #define _syscall0(type,name) \ diff --git a/include/asm-v850/delay.h b/include/asm-v850/delay.h index bad311ba44b5..1ce65d48a7c5 100644 --- a/include/asm-v850/delay.h +++ b/include/asm-v850/delay.h @@ -2,8 +2,8 @@ * include/asm-v850/delay.h -- Delay routines, using a pre-computed * "loops_per_second" value * - * Copyright (C) 2001 NEC Corporation - * Copyright (C) 2001 Miles Bader <miles@gnu.org> + * Copyright (C) 2001,03 NEC Corporation + * Copyright (C) 2001,03 Miles Bader <miles@gnu.org> * Copyright (C) 1994 Hamish Macdonald * * This file is subject to the terms and conditions of the GNU General @@ -18,8 +18,9 @@ extern __inline__ void __delay(unsigned long loops) { - __asm__ __volatile__ ("1: add -1, %0; bnz 1b" - : "=r" (loops) : "0" (loops)); + if (loops) + __asm__ __volatile__ ("1: add -1, %0; bnz 1b" + : "=r" (loops) : "0" (loops)); } /* diff --git a/include/asm-v850/module.h b/include/asm-v850/module.h index 9b2e1e30033a..2c2f4944f09f 100644 --- a/include/asm-v850/module.h +++ b/include/asm-v850/module.h @@ -1,8 +1,8 @@ /* * include/asm-v850/module.h -- Architecture-specific module hooks * - * Copyright (C) 2001,02,03 NEC Corporation - * Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org> + * Copyright (C) 2001,02,03,04 NEC Corporation + * Copyright (C) 2001,02,03,04 Miles Bader <miles@gnu.org> * Copyright (C) 2001,03 Rusty Russell * * This file is subject to the terms and conditions of the GNU General @@ -50,5 +50,13 @@ search_extable(const struct exception_table_entry *first, { return 0; } +#define ARCH_HAS_SEARCH_EXTABLE +static inline void +sort_extable(struct exception_table_entry *start, + struct exception_table_entry *finish) +{ + /* nada */ +} +#define ARCH_HAS_SORT_EXTABLE #endif /* __V850_MODULE_H__ */ diff --git a/include/asm-v850/pci.h b/include/asm-v850/pci.h index 81addb7df017..e3a33920e693 100644 --- a/include/asm-v850/pci.h +++ b/include/asm-v850/pci.h @@ -76,4 +76,8 @@ extern void pci_free_consistent (struct pci_dev *pdev, size_t size, void *cpu_addr, dma_addr_t dma_addr); +static inline void pcibios_add_platform_entries(struct pci_dev *dev) +{ +} + #endif /* __V850_PCI_H__ */ diff --git a/include/asm-x86_64/atomic.h b/include/asm-x86_64/atomic.h index fb8d4f54d3d0..baf472fb50f2 100644 --- a/include/asm-x86_64/atomic.h +++ b/include/asm-x86_64/atomic.h @@ -29,8 +29,7 @@ typedef struct { volatile int counter; } atomic_t; * atomic_read - read atomic variable * @v: pointer of type atomic_t * - * Atomically reads the value of @v. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. + * Atomically reads the value of @v. */ #define atomic_read(v) ((v)->counter) @@ -39,8 +38,7 @@ typedef struct { volatile int counter; } atomic_t; * @v: pointer of type atomic_t * @i: required value * - * Atomically sets the value of @v to @i. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. + * Atomically sets the value of @v to @i. */ #define atomic_set(v,i) (((v)->counter) = (i)) @@ -49,8 +47,7 @@ typedef struct { volatile int counter; } atomic_t; * @i: integer value to add * @v: pointer of type atomic_t * - * Atomically adds @i to @v. Note that the guaranteed useful range - * of an atomic_t is only 24 bits. + * Atomically adds @i to @v. */ static __inline__ void atomic_add(int i, atomic_t *v) { @@ -65,8 +62,7 @@ static __inline__ void atomic_add(int i, atomic_t *v) * @i: integer value to subtract * @v: pointer of type atomic_t * - * Atomically subtracts @i from @v. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. + * Atomically subtracts @i from @v. */ static __inline__ void atomic_sub(int i, atomic_t *v) { @@ -83,8 +79,7 @@ static __inline__ void atomic_sub(int i, atomic_t *v) * * Atomically subtracts @i from @v and returns * true if the result is zero, or false for all - * other cases. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. + * other cases. */ static __inline__ int atomic_sub_and_test(int i, atomic_t *v) { @@ -101,8 +96,7 @@ static __inline__ int atomic_sub_and_test(int i, atomic_t *v) * atomic_inc - increment atomic variable * @v: pointer of type atomic_t * - * Atomically increments @v by 1. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. + * Atomically increments @v by 1. */ static __inline__ void atomic_inc(atomic_t *v) { @@ -116,8 +110,7 @@ static __inline__ void atomic_inc(atomic_t *v) * atomic_dec - decrement atomic variable * @v: pointer of type atomic_t * - * Atomically decrements @v by 1. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. + * Atomically decrements @v by 1. */ static __inline__ void atomic_dec(atomic_t *v) { @@ -133,8 +126,7 @@ static __inline__ void atomic_dec(atomic_t *v) * * Atomically decrements @v by 1 and * returns true if the result is 0, or false for all other - * cases. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. + * cases. */ static __inline__ int atomic_dec_and_test(atomic_t *v) { @@ -153,8 +145,7 @@ static __inline__ int atomic_dec_and_test(atomic_t *v) * * Atomically increments @v by 1 * and returns true if the result is zero, or false for all - * other cases. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. + * other cases. */ static __inline__ int atomic_inc_and_test(atomic_t *v) { @@ -174,8 +165,7 @@ static __inline__ int atomic_inc_and_test(atomic_t *v) * * Atomically adds @i to @v and returns true * if the result is negative, or false when - * result is greater than or equal to zero. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. + * result is greater than or equal to zero. */ static __inline__ int atomic_add_negative(int i, atomic_t *v) { diff --git a/include/asm-x86_64/pci.h b/include/asm-x86_64/pci.h index 6feb36107d64..1ba95e06f32f 100644 --- a/include/asm-x86_64/pci.h +++ b/include/asm-x86_64/pci.h @@ -263,6 +263,10 @@ pci_dac_dma_sync_single(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, enum pci_mmap_state mmap_state, int write_combine); +static inline void pcibios_add_platform_entries(struct pci_dev *dev) +{ +} + #endif /* __KERNEL__ */ /* generic pci stuff */ diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 8e4eba21e7ea..f851b34903e3 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -355,8 +355,8 @@ int acpi_numa_init (void); int acpi_table_init (void); int acpi_table_parse (enum acpi_table_id id, acpi_table_handler handler); int acpi_get_table_header_early (enum acpi_table_id id, struct acpi_table_header **header); -int acpi_table_parse_madt (enum acpi_madt_entry_id id, acpi_madt_entry_handler handler); -int acpi_table_parse_srat (enum acpi_srat_entry_id id, acpi_madt_entry_handler handler); +int acpi_table_parse_madt (enum acpi_madt_entry_id id, acpi_madt_entry_handler handler, unsigned int max_entries); +int acpi_table_parse_srat (enum acpi_srat_entry_id id, acpi_madt_entry_handler handler, unsigned int max_entries); void acpi_table_print (struct acpi_table_header *header, unsigned long phys_addr); void acpi_table_print_madt_entry (acpi_table_entry_header *madt); void acpi_table_print_srat_entry (acpi_table_entry_header *srat); diff --git a/include/linux/ata.h b/include/linux/ata.h index b4b4543bee53..968d54214248 100644 --- a/include/linux/ata.h +++ b/include/linux/ata.h @@ -1,7 +1,7 @@ /* - Copyright 2003 Red Hat, Inc. All rights reserved. - Copyright 2003 Jeff Garzik + Copyright 2003-2004 Red Hat, Inc. All rights reserved. + Copyright 2003-2004 Jeff Garzik The contents of this file are subject to the Open Software License version 1.1 that can be found at diff --git a/include/linux/atmdev.h b/include/linux/atmdev.h index 0b371eb0e69d..81f37e55c510 100644 --- a/include/linux/atmdev.h +++ b/include/linux/atmdev.h @@ -200,9 +200,7 @@ struct atm_cirange { "SESSION", "HASSAP", "BOUND", "CLOSE" -#ifndef __KERNEL__ -#undef __AAL_STAT_ITEMS -#else +#ifdef __KERNEL__ #include <linux/wait.h> /* wait_queue_head_t */ #include <linux/time.h> /* struct timeval */ diff --git a/include/linux/cdev.h b/include/linux/cdev.h index 191c800fa127..f1996ec09e96 100644 --- a/include/linux/cdev.h +++ b/include/linux/cdev.h @@ -7,6 +7,8 @@ struct cdev { struct module *owner; struct file_operations *ops; struct list_head list; + dev_t dev; + unsigned int count; }; void cdev_init(struct cdev *, struct file_operations *); @@ -21,8 +23,6 @@ int cdev_add(struct cdev *, dev_t, unsigned); void cdev_del(struct cdev *); -void cdev_unmap(dev_t, unsigned); - void cd_forget(struct inode *); #endif diff --git a/include/linux/compiler.h b/include/linux/compiler.h index ba3ef774bc17..cc46aa0584f9 100644 --- a/include/linux/compiler.h +++ b/include/linux/compiler.h @@ -9,6 +9,8 @@ # define __kernel #endif +#ifdef __KERNEL__ + #ifndef __ASSEMBLY__ #if __GNUC__ > 3 # include <linux/compiler-gcc+.h> /* catch-all for GCC 4, 5, etc. */ @@ -106,4 +108,6 @@ (typeof(ptr)) (__ptr + (off)); }) #endif +#endif /* __KERNEL__ */ + #endif /* __LINUX_COMPILER_H */ diff --git a/include/linux/device.h b/include/linux/device.h index 367b21888ad4..aef6b2f8836e 100644 --- a/include/linux/device.h +++ b/include/linux/device.h @@ -253,6 +253,8 @@ extern struct class_simple *class_simple_create(struct module *owner, char *name extern void class_simple_destroy(struct class_simple *cs); extern struct class_device *class_simple_device_add(struct class_simple *cs, dev_t dev, struct device *device, const char *fmt, ...) __attribute__((format(printf,4,5))); +extern int class_simple_set_hotplug(struct class_simple *, + int (*hotplug)(struct class_device *dev, char **envp, int num_envp, char *buffer, int buffer_size)); extern void class_simple_device_remove(dev_t dev); @@ -263,7 +265,6 @@ struct device { struct list_head children; struct device * parent; - struct completion * complete; /* Notification for freeing device. */ struct kobject kobj; char bus_id[BUS_ID_SIZE]; /* position on parent bus */ @@ -284,6 +285,7 @@ struct device { detached from its driver. */ u64 *dma_mask; /* dma mask (if dma'able device) */ + struct list_head dma_pools; /* dma pools (if dma'ble) */ void (*release)(struct device * dev); }; @@ -311,7 +313,6 @@ dev_set_drvdata (struct device *dev, void *data) */ extern int device_register(struct device * dev); extern void device_unregister(struct device * dev); -extern void device_unregister_wait(struct device * dev); extern void device_initialize(struct device * dev); extern int device_add(struct device * dev); extern void device_del(struct device * dev); diff --git a/include/linux/dmapool.h b/include/linux/dmapool.h new file mode 100644 index 000000000000..e60bfdac348d --- /dev/null +++ b/include/linux/dmapool.h @@ -0,0 +1,27 @@ +/* + * include/linux/dmapool.h + * + * Allocation pools for DMAable (coherent) memory. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef LINUX_DMAPOOL_H +#define LINUX_DMAPOOL_H + +#include <asm/io.h> +#include <asm/scatterlist.h> + +struct dma_pool *dma_pool_create(const char *name, struct device *dev, + size_t size, size_t align, size_t allocation); + +void dma_pool_destroy(struct dma_pool *pool); + +void *dma_pool_alloc(struct dma_pool *pool, int mem_flags, dma_addr_t *handle); + +void dma_pool_free(struct dma_pool *pool, void *vaddr, dma_addr_t addr); + +#endif + diff --git a/include/linux/fb.h b/include/linux/fb.h index e6a2053fbd51..574808f1450d 100644 --- a/include/linux/fb.h +++ b/include/linux/fb.h @@ -340,6 +340,24 @@ struct device; struct file; /* + * Register/unregister for framebuffer events + */ + +/* The resolution of the passed in fb_info about to change */ +#define FB_EVENT_MODE_CHANGE 0x01 +/* The display on this fb_info is beeing suspended, no access to the + * framebuffer is allowed any more after that call returns + */ +#define FB_EVENT_SUSPEND 0x02 +/* The display on this fb_info was resumed, you can restore the display + * if you own it + */ +#define FB_EVENT_RESUME 0x03 + +extern int fb_register_client(struct notifier_block *nb); +extern int fb_unregister_client(struct notifier_block *nb); + +/* * Pixmap structure definition * * The purpose of this structure is to translate data @@ -363,8 +381,6 @@ struct fb_pixmap { /* access methods */ void (*outbuf)(u8 *dst, u8 *addr, unsigned int size); u8 (*inbuf) (u8 *addr); - spinlock_t lock; /* spinlock */ - atomic_t count; }; /* @@ -448,8 +464,10 @@ struct fb_info { char *screen_base; /* Virtual address */ struct vc_data *display_fg; /* Console visible on this display */ int currcon; /* Current VC. */ - struct class_device class_dev; /* Sysfs data */ void *pseudo_palette; /* Fake palette of 16 colors */ +#define FBINFO_STATE_RUNNING 0 +#define FBINFO_STATE_SUSPENDED 1 + u32 state; /* Hardware state i.e suspend */ /* From here on everything is device dependent */ void *par; }; @@ -476,7 +494,7 @@ struct fb_info { #define fb_writeq sbus_writeq #define fb_memset sbus_memset_io -#elif defined(__i386__) || defined(__alpha__) || defined(__x86_64__) || defined(__hppa__) +#elif defined(__i386__) || defined(__alpha__) || defined(__x86_64__) || defined(__hppa__) || defined(__sh__) #define fb_readb __raw_readb #define fb_readw __raw_readw @@ -526,15 +544,13 @@ extern void move_buf_unaligned(struct fb_info *info, u8 * dst, u8 * src, u32 idx); extern void move_buf_aligned(struct fb_info *info, u8 * dst, u8 * src, u32 d_pitch, u32 s_pitch, u32 height); +extern void fb_set_suspend(struct fb_info *info, int state); extern struct fb_info *registered_fb[FB_MAX]; extern int num_registered_fb; /* drivers/video/fbsysfs.c */ extern struct fb_info *framebuffer_alloc(size_t size, struct device *dev); extern void framebuffer_release(struct fb_info *info); -extern int fb_add_class_device(struct fb_info *info); - -extern struct class fb_class; /* drivers/video/fbmon.c */ #define FB_MAXTIMINGS 0 diff --git a/include/linux/fs.h b/include/linux/fs.h index 7d9154665d9b..fb2306154b75 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -1421,5 +1421,25 @@ static inline ino_t parent_ino(struct dentry *dentry) /* kernel/fork.c */ extern int unshare_files(void); +#ifdef CONFIG_SECURITY +static inline char *alloc_secdata(void) +{ + return (char *)get_zeroed_page(GFP_KERNEL); +} + +static inline void free_secdata(void *secdata) +{ + free_page((unsigned long)secdata); +} +#else +static inline char *alloc_secdata(void) +{ + return (char *)1; +} + +static inline void free_secdata(void *secdata) +{ } +#endif /* CONFIG_SECURITY */ + #endif /* __KERNEL__ */ #endif /* _LINUX_FS_H */ diff --git a/include/linux/i2c-id.h b/include/linux/i2c-id.h index d4dcd2126ce1..e988edbcb5b8 100644 --- a/include/linux/i2c-id.h +++ b/include/linux/i2c-id.h @@ -156,6 +156,7 @@ #define I2C_DRIVERID_LM83 1040 #define I2C_DRIVERID_LM90 1042 #define I2C_DRIVERID_ASB100 1043 +#define I2C_DRIVERID_FSCHER 1046 #define I2C_DRIVERID_W83L785TS 1047 /* diff --git a/include/linux/ide.h b/include/linux/ide.h index f5ee5b62adee..f7c97c9b0b8f 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -790,14 +790,10 @@ typedef struct ide_dma_ops_s { int (*ide_dma_end)(ide_drive_t *drive); int (*ide_dma_check)(ide_drive_t *drive); int (*ide_dma_on)(ide_drive_t *drive); - int (*ide_dma_off)(ide_drive_t *drive); int (*ide_dma_off_quietly)(ide_drive_t *drive); int (*ide_dma_test_irq)(ide_drive_t *drive); int (*ide_dma_host_on)(ide_drive_t *drive); int (*ide_dma_host_off)(ide_drive_t *drive); - int (*ide_dma_bad_drive)(ide_drive_t *drive); - int (*ide_dma_good_drive)(ide_drive_t *drive); - int (*ide_dma_count)(ide_drive_t *drive); int (*ide_dma_verbose)(ide_drive_t *drive); int (*ide_dma_lostirq)(ide_drive_t *drive); int (*ide_dma_timeout)(ide_drive_t *drive); @@ -929,14 +925,10 @@ typedef struct hwif_s { int (*ide_dma_end)(ide_drive_t *drive); int (*ide_dma_check)(ide_drive_t *drive); int (*ide_dma_on)(ide_drive_t *drive); - int (*ide_dma_off)(ide_drive_t *drive); int (*ide_dma_off_quietly)(ide_drive_t *drive); int (*ide_dma_test_irq)(ide_drive_t *drive); int (*ide_dma_host_on)(ide_drive_t *drive); int (*ide_dma_host_off)(ide_drive_t *drive); - int (*ide_dma_bad_drive)(ide_drive_t *drive); - int (*ide_dma_good_drive)(ide_drive_t *drive); - int (*ide_dma_count)(ide_drive_t *drive); int (*ide_dma_verbose)(ide_drive_t *drive); int (*ide_dma_lostirq)(ide_drive_t *drive); int (*ide_dma_timeout)(ide_drive_t *drive); @@ -1597,6 +1589,11 @@ extern void ide_setup_pci_devices(struct pci_dev *, struct pci_dev *, ide_pci_de #define BAD_DMA_DRIVE 0 #define GOOD_DMA_DRIVE 1 +#ifdef CONFIG_BLK_DEV_IDEDMA +int __ide_dma_bad_drive(ide_drive_t *); +int __ide_dma_good_drive(ide_drive_t *); +int __ide_dma_off(ide_drive_t *); + #ifdef CONFIG_BLK_DEV_IDEDMA_PCI extern int ide_build_sglist(ide_drive_t *, struct request *); extern int ide_raw_build_sglist(ide_drive_t *, struct request *); @@ -1609,7 +1606,6 @@ extern int ide_start_dma(ide_hwif_t *, ide_drive_t *, int); extern int __ide_dma_host_off(ide_drive_t *); extern int __ide_dma_off_quietly(ide_drive_t *); -extern int __ide_dma_off(ide_drive_t *); extern int __ide_dma_host_on(ide_drive_t *); extern int __ide_dma_on(ide_drive_t *); extern int __ide_dma_check(ide_drive_t *); @@ -1618,12 +1614,10 @@ extern int __ide_dma_write(ide_drive_t *); extern int __ide_dma_begin(ide_drive_t *); extern int __ide_dma_end(ide_drive_t *); extern int __ide_dma_test_irq(ide_drive_t *); -extern int __ide_dma_bad_drive(ide_drive_t *); -extern int __ide_dma_good_drive(ide_drive_t *); -extern int __ide_dma_count(ide_drive_t *); extern int __ide_dma_verbose(ide_drive_t *); extern int __ide_dma_lostirq(ide_drive_t *); extern int __ide_dma_timeout(ide_drive_t *); +#endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ #ifdef CONFIG_BLK_DEV_IDE_TCQ extern int __ide_dma_queued_on(ide_drive_t *drive); @@ -1634,6 +1628,10 @@ extern ide_startstop_t __ide_dma_queued_start(ide_drive_t *drive); #endif #else +static inline int __ide_dma_off(ide_drive_t *drive) { return 0; } +#endif /* CONFIG_BLK_DEV_IDEDMA */ + +#ifndef CONFIG_BLK_DEV_IDEDMA_PCI static inline void ide_release_dma(ide_hwif_t *drive) {;} #endif diff --git a/include/linux/input.h b/include/linux/input.h index 59afa63abbb3..77ba731cfb3a 100644 --- a/include/linux/input.h +++ b/include/linux/input.h @@ -752,25 +752,28 @@ struct ff_effect { #define init_input_dev(dev) do { INIT_LIST_HEAD(&((dev)->h_list)); INIT_LIST_HEAD(&((dev)->node)); } while (0) #define SET_INPUT_KEYCODE(dev, scancode, val) \ - do { \ + ({ unsigned __old; \ switch (dev->keycodesize) { \ case 1: { \ u8 *k = (u8 *)dev->keycode; \ + __old = k[scancode]; \ k[scancode] = val; \ break; \ } \ case 2: { \ u16 *k = (u16 *)dev->keycode; \ + __old = k[scancode]; \ k[scancode] = val; \ break; \ } \ - case 4: { \ + default: { \ u32 *k = (u32 *)dev->keycode; \ + __old = k[scancode]; \ k[scancode] = val; \ break; \ } \ } \ - } while (0) + __old; }) struct input_dev { diff --git a/include/linux/ipv6.h b/include/linux/ipv6.h index ab97fc520921..29911bf4218e 100644 --- a/include/linux/ipv6.h +++ b/include/linux/ipv6.h @@ -185,7 +185,6 @@ struct inet6_skb_parm int iif; __u16 ra; __u16 hop; - __u16 auth; __u16 dst0; __u16 srcrt; __u16 dst1; @@ -211,7 +210,6 @@ struct ipv6_pinfo { rxhlim:1, hopopts:1, dstopts:1, - authhdr:1, rxflow:1; } bits; __u8 all; diff --git a/include/linux/libata.h b/include/linux/libata.h index 53ce430954da..deddc267392c 100644 --- a/include/linux/libata.h +++ b/include/linux/libata.h @@ -1,6 +1,6 @@ /* - Copyright 2003 Red Hat, Inc. All rights reserved. - Copyright 2003 Jeff Garzik + Copyright 2003-2004 Red Hat, Inc. All rights reserved. + Copyright 2003-2004 Jeff Garzik The contents of this file are subject to the Open Software License version 1.1 that can be found at diff --git a/include/linux/list.h b/include/linux/list.h index 9a5df31af22e..5388098449cc 100644 --- a/include/linux/list.h +++ b/include/linux/list.h @@ -344,6 +344,16 @@ static inline void list_splice_init(struct list_head *list, prefetch(pos->member.prev)) /** + * list_prepare_entry - prepare a pos entry for use as a start point in + * list_for_each_entry_continue + * @pos: the type * to use as a start point + * @head: the head of the list + * @member: the name of the list_struct within the struct. + */ +#define list_prepare_entry(pos, head, member) \ + ((pos) ? : list_entry(head, typeof(*pos), member)) + +/** * list_for_each_entry_continue - iterate over list of given type * continuing after existing point * @pos: the type * to use as a loop counter. diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h index 67cce1744c86..c0d7ce138d99 100644 --- a/include/linux/mod_devicetable.h +++ b/include/linux/mod_devicetable.h @@ -148,4 +148,21 @@ struct ccw_device_id { #define CCW_DEVICE_ID_MATCH_DEVICE_MODEL 0x08 +#define PNP_ID_LEN 8 +#define PNP_MAX_DEVICES 8 + +struct pnp_device_id { + __u8 id[PNP_ID_LEN]; + kernel_ulong_t driver_data; +}; + +struct pnp_card_device_id { + __u8 id[PNP_ID_LEN]; + kernel_ulong_t driver_data; + struct { + __u8 id[PNP_ID_LEN]; + } devs[PNP_MAX_DEVICES]; +}; + + #endif /* LINUX_MOD_DEVICETABLE_H */ diff --git a/include/linux/nfs4.h b/include/linux/nfs4.h index 8bb512eb2b43..35baf20a5b5c 100644 --- a/include/linux/nfs4.h +++ b/include/linux/nfs4.h @@ -88,6 +88,76 @@ enum nfs_opnum4 { OP_WRITE = 38, }; +enum nfsstat4 { + NFS4_OK = 0, + NFS4ERR_PERM = 1, + NFS4ERR_NOENT = 2, + NFS4ERR_IO = 5, + NFS4ERR_NXIO = 6, + NFS4ERR_ACCESS = 13, + NFS4ERR_EXIST = 17, + NFS4ERR_XDEV = 18, + /* Unused/reserved 19 */ + NFS4ERR_NOTDIR = 20, + NFS4ERR_ISDIR = 21, + NFS4ERR_INVAL = 22, + NFS4ERR_FBIG = 27, + NFS4ERR_NOSPC = 28, + NFS4ERR_ROFS = 30, + NFS4ERR_MLINK = 31, + NFS4ERR_NAMETOOLONG = 63, + NFS4ERR_NOTEMPTY = 66, + NFS4ERR_DQUOT = 69, + NFS4ERR_STALE = 70, + NFS4ERR_BADHANDLE = 10001, + NFS4ERR_BAD_COOKIE = 10003, + NFS4ERR_NOTSUPP = 10004, + NFS4ERR_TOOSMALL = 10005, + NFS4ERR_SERVERFAULT = 10006, + NFS4ERR_BADTYPE = 10007, + NFS4ERR_DELAY = 10008, + NFS4ERR_SAME = 10009, + NFS4ERR_DENIED = 10010, + NFS4ERR_EXPIRED = 10011, + NFS4ERR_LOCKED = 10012, + NFS4ERR_GRACE = 10013, + NFS4ERR_FHEXPIRED = 10014, + NFS4ERR_SHARE_DENIED = 10015, + NFS4ERR_WRONGSEC = 10016, + NFS4ERR_CLID_INUSE = 10017, + NFS4ERR_RESOURCE = 10018, + NFS4ERR_MOVED = 10019, + NFS4ERR_NOFILEHANDLE = 10020, + NFS4ERR_MINOR_VERS_MISMATCH = 10021, + NFS4ERR_STALE_CLIENTID = 10022, + NFS4ERR_STALE_STATEID = 10023, + NFS4ERR_OLD_STATEID = 10024, + NFS4ERR_BAD_STATEID = 10025, + NFS4ERR_BAD_SEQID = 10026, + NFS4ERR_NOT_SAME = 10027, + NFS4ERR_LOCK_RANGE = 10028, + NFS4ERR_SYMLINK = 10029, + NFS4ERR_RESTOREFH = 10030, + NFS4ERR_LEASE_MOVED = 10031, + NFS4ERR_ATTRNOTSUPP = 10032, + NFS4ERR_NO_GRACE = 10033, + NFS4ERR_RECLAIM_BAD = 10034, + NFS4ERR_RECLAIM_CONFLICT = 10035, + NFS4ERR_BADXDR = 10036, + NFS4ERR_LOCKS_HELD = 10037, + NFS4ERR_OPENMODE = 10038, + NFS4ERR_BADOWNER = 10039, + NFS4ERR_BADCHAR = 10040, + NFS4ERR_BADNAME = 10041, + NFS4ERR_BAD_RANGE = 10042, + NFS4ERR_LOCK_NOTSUPP = 10043, + NFS4ERR_OP_ILLEGAL = 10044, + NFS4ERR_DEADLOCK = 10045, + NFS4ERR_FILE_OPEN = 10046, + NFS4ERR_ADMIN_REVOKED = 10047, + NFS4ERR_CB_PATH_DOWN = 10048 +}; + /* * Note: NF4BAD is not actually part of the protocol; it is just used * internally by nfsd. @@ -219,8 +289,17 @@ enum { NFSPROC4_CLNT_COMMIT, NFSPROC4_CLNT_OPEN, NFSPROC4_CLNT_OPEN_CONFIRM, + NFSPROC4_CLNT_OPEN_RECLAIM, + NFSPROC4_CLNT_OPEN_DOWNGRADE, NFSPROC4_CLNT_CLOSE, NFSPROC4_CLNT_SETATTR, + NFSPROC4_CLNT_FSINFO, + NFSPROC4_CLNT_RENEW, + NFSPROC4_CLNT_SETCLIENTID, + NFSPROC4_CLNT_SETCLIENTID_CONFIRM, + NFSPROC4_CLNT_LOCK, + NFSPROC4_CLNT_LOCKT, + NFSPROC4_CLNT_LOCKU, }; #endif diff --git a/include/linux/nfs_fs.h b/include/linux/nfs_fs.h index 5ae592b26d63..524eb6d04d7b 100644 --- a/include/linux/nfs_fs.h +++ b/include/linux/nfs_fs.h @@ -28,6 +28,7 @@ #include <linux/nfs3.h> #include <linux/nfs4.h> #include <linux/nfs_xdr.h> +#include <linux/workqueue.h> /* * Enable debugging support for nfs client. @@ -437,6 +438,8 @@ extern void * nfs_root_data(void); #ifdef CONFIG_NFS_V4 +struct idmap; + /* * In a seqid-mutating op, this macro controls which error return * values trigger incrementation of the seqid. @@ -464,6 +467,7 @@ extern void * nfs_root_data(void); enum nfs4_client_state { NFS4CLNT_OK = 0, NFS4CLNT_NEW, + NFS4CLNT_SETUP_STATE, }; /* @@ -474,7 +478,8 @@ struct nfs4_client { struct in_addr cl_addr; /* Server identifier */ u64 cl_clientid; /* constant */ nfs4_verifier cl_confirm; - enum nfs4_client_state cl_state; + unsigned long cl_state; + long cl_generation; u32 cl_lockowner_id; @@ -489,6 +494,27 @@ struct nfs4_client { int cl_nunused; spinlock_t cl_lock; atomic_t cl_count; + + struct rpc_clnt * cl_rpcclient; + struct rpc_cred * cl_cred; + + struct list_head cl_superblocks; /* List of nfs_server structs */ + + unsigned long cl_lease_time; + unsigned long cl_last_renewal; + struct work_struct cl_renewd; + struct work_struct cl_recoverd; + + wait_queue_head_t cl_waitq; + struct rpc_wait_queue cl_rpcwaitq; + + /* idmapper */ + struct idmap * cl_idmap; + + /* Our own IP address, as a null-terminated string. + * This is used to generate the clientid, and the callback address. + */ + char cl_ipaddr[16]; }; /* @@ -508,6 +534,7 @@ struct nfs4_state_owner { u32 so_seqid; /* protected by so_sema */ unsigned int so_flags; /* protected by so_sema */ atomic_t so_count; + long so_generation; struct rpc_cred *so_cred; /* Associated cred */ struct list_head so_states; @@ -515,73 +542,105 @@ struct nfs4_state_owner { /* * struct nfs4_state maintains the client-side state for a given - * (state_owner,inode) tuple. + * (state_owner,inode) tuple (OPEN) or state_owner (LOCK). * + * OPEN: * In order to know when to OPEN_DOWNGRADE or CLOSE the state on the server, * we need to know how many files are open for reading or writing on a * given inode. This information too is stored here. + * + * LOCK: one nfs4_state (LOCK) to hold the lock stateid nfs4_state(OPEN) */ + +struct nfs4_lock_state { + struct list_head ls_locks; /* Other lock stateids */ + fl_owner_t ls_owner; /* POSIX lock owner */ + struct nfs4_state * ls_parent; /* Parent nfs4_state */ + u32 ls_seqid; + u32 ls_id; + nfs4_stateid ls_stateid; + atomic_t ls_count; +}; + +/* bits for nfs4_state->flags */ +enum { + LK_STATE_IN_USE, +}; + struct nfs4_state { struct list_head open_states; /* List of states for the same state_owner */ struct list_head inode_states; /* List of states for the same inode */ + struct list_head lock_states; /* List of subservient lock stateids */ struct nfs4_state_owner *owner; /* Pointer to the open owner */ struct inode *inode; /* Pointer to the inode */ - pid_t pid; /* Thread that called OPEN */ + + unsigned long flags; /* Do we hold any locks? */ + struct semaphore lock_sema; /* Serializes file locking operations */ + rwlock_t state_lock; /* Protects the lock_states list */ nfs4_stateid stateid; + unsigned int nreaders; + unsigned int nwriters; int state; /* State on the server (R,W, or RW) */ atomic_t count; }; +extern struct dentry_operations nfs4_dentry_operations; +extern struct inode_operations nfs4_dir_inode_operations; + /* nfs4proc.c */ -extern int nfs4_proc_renew(struct nfs_server *server); +extern int nfs4_proc_setclientid(struct nfs4_client *, u32, unsigned short); +extern int nfs4_proc_setclientid_confirm(struct nfs4_client *); +extern int nfs4_open_reclaim(struct nfs4_state_owner *, struct nfs4_state *); +extern int nfs4_proc_async_renew(struct nfs4_client *); +extern int nfs4_proc_renew(struct nfs4_client *); extern int nfs4_do_close(struct inode *, struct nfs4_state *); +int nfs4_do_downgrade(struct inode *inode, struct nfs4_state *state, mode_t mode); +extern int nfs4_wait_clnt_recover(struct rpc_clnt *, struct nfs4_client *); +extern struct inode *nfs4_atomic_open(struct inode *, struct dentry *, struct nameidata *); +extern int nfs4_open_revalidate(struct inode *, struct dentry *, int); /* nfs4renewd.c */ -extern int nfs4_init_renewd(struct nfs_server *server); +extern void nfs4_schedule_state_renewal(struct nfs4_client *); +extern void nfs4_renewd_prepare_shutdown(struct nfs_server *); +extern void nfs4_kill_renewd(struct nfs4_client *); /* nfs4state.c */ +extern void init_nfsv4_state(struct nfs_server *); +extern void destroy_nfsv4_state(struct nfs_server *); extern struct nfs4_client *nfs4_get_client(struct in_addr *); extern void nfs4_put_client(struct nfs4_client *clp); +extern u32 nfs4_alloc_lockowner_id(struct nfs4_client *); + extern struct nfs4_state_owner * nfs4_get_state_owner(struct nfs_server *, struct rpc_cred *); extern void nfs4_put_state_owner(struct nfs4_state_owner *); extern struct nfs4_state * nfs4_get_open_state(struct inode *, struct nfs4_state_owner *); extern void nfs4_put_open_state(struct nfs4_state *); -extern void nfs4_increment_seqid(u32 status, struct nfs4_state_owner *sp); - - - +extern void nfs4_close_state(struct nfs4_state *, mode_t); +extern struct nfs4_state *nfs4_find_state(struct inode *, struct rpc_cred *, mode_t mode); +extern void nfs4_increment_seqid(int status, struct nfs4_state_owner *sp); +extern int nfs4_handle_error(struct nfs_server *, int); +extern void nfs4_schedule_state_recovery(struct nfs4_client *); +extern struct nfs4_lock_state *nfs4_find_lock_state(struct nfs4_state *state, fl_owner_t); +extern struct nfs4_lock_state *nfs4_alloc_lock_state(struct nfs4_state *state, fl_owner_t); +extern void nfs4_put_lock_state(struct nfs4_lock_state *state); +extern void nfs4_increment_lock_seqid(int status, struct nfs4_lock_state *ls); +extern void nfs4_notify_setlk(struct inode *, struct file_lock *, struct nfs4_lock_state *); +extern void nfs4_notify_unlck(struct inode *, struct file_lock *, struct nfs4_lock_state *); +extern void nfs4_copy_stateid(nfs4_stateid *, struct nfs4_state *, fl_owner_t); struct nfs4_mount_data; -static inline int -create_nfsv4_state(struct nfs_server *server, struct nfs4_mount_data *data) -{ - server->nfs4_state = NULL; - return 0; -} - -static inline void -destroy_nfsv4_state(struct nfs_server *server) -{ - if (server->mnt_path) { - kfree(server->mnt_path); - server->mnt_path = NULL; - } - if (server->nfs4_state) { - nfs4_put_client(server->nfs4_state); - server->nfs4_state = NULL; - } -} #else -#define create_nfsv4_state(server, data) 0 +#define init_nfsv4_state(server) do { } while (0) #define destroy_nfsv4_state(server) do { } while (0) #define nfs4_put_state_owner(inode, owner) do { } while (0) #define nfs4_put_open_state(state) do { } while (0) +#define nfs4_renewd_prepare_shutdown(server) do { } while (0) #endif #endif /* __KERNEL__ */ diff --git a/include/linux/nfs_fs_sb.h b/include/linux/nfs_fs_sb.h index 20ceb626cb3b..1b5f7e130502 100644 --- a/include/linux/nfs_fs_sb.h +++ b/include/linux/nfs_fs_sb.h @@ -35,9 +35,9 @@ struct nfs_server { char ip_addr[16]; char * mnt_path; struct nfs4_client * nfs4_state; /* all NFSv4 state starts here */ - unsigned long lease_time; /* in jiffies */ - unsigned long last_renewal; /* in jiffies */ - void *idmap; + struct list_head nfs4_siblings; /* List of other nfs_server structs + * that share the same clientid + */ #endif }; diff --git a/include/linux/nfs_idmap.h b/include/linux/nfs_idmap.h index 248adf707071..a0f1f25e0ead 100644 --- a/include/linux/nfs_idmap.h +++ b/include/linux/nfs_idmap.h @@ -52,18 +52,25 @@ #define IDMAP_STATUS_SUCCESS 0x08 struct idmap_msg { - u_int8_t im_type; - u_int8_t im_conv; - char im_name[IDMAP_NAMESZ]; - u_int32_t im_id; - u_int8_t im_status; + __u8 im_type; + __u8 im_conv; + char im_name[IDMAP_NAMESZ]; + __u32 im_id; + __u8 im_status; }; #ifdef __KERNEL__ -void *nfs_idmap_new(struct nfs_server *); -void nfs_idmap_delete(struct nfs_server *); -int nfs_idmap_id(struct nfs_server *, u_int8_t, char *, u_int, uid_t *); -int nfs_idmap_name(struct nfs_server *, u_int8_t, uid_t, char *, u_int *); + +/* Forward declaration to make this header independent of others */ +struct nfs4_client; + +void nfs_idmap_new(struct nfs4_client *); +void nfs_idmap_delete(struct nfs4_client *); + +int nfs_map_name_to_uid(struct nfs4_client *, const char *, size_t, __u32 *); +int nfs_map_group_to_gid(struct nfs4_client *, const char *, size_t, __u32 *); +int nfs_map_uid_to_name(struct nfs4_client *, __u32, char *); +int nfs_map_gid_to_group(struct nfs4_client *, __u32, char *); #endif /* __KERNEL__ */ #endif /* NFS_IDMAP_H */ diff --git a/include/linux/nfs_mount.h b/include/linux/nfs_mount.h index 23a9ff52537f..0071428231f9 100644 --- a/include/linux/nfs_mount.h +++ b/include/linux/nfs_mount.h @@ -20,7 +20,8 @@ * mount-to-kernel version compatibility. Some of these aren't used yet * but here they are anyway. */ -#define NFS_MOUNT_VERSION 5 +#define NFS_MOUNT_VERSION 6 +#define NFS_MAX_CONTEXT_LEN 256 struct nfs_mount_data { int version; /* 1 */ @@ -41,6 +42,7 @@ struct nfs_mount_data { unsigned int bsize; /* 3 */ struct nfs3_fh root; /* 4 */ int pseudoflavor; /* 5 */ + char context[NFS_MAX_CONTEXT_LEN + 1]; /* 6 */ }; /* bits in the flags field */ diff --git a/include/linux/nfs_page.h b/include/linux/nfs_page.h index 42677b62e92b..c41a4e75555e 100644 --- a/include/linux/nfs_page.h +++ b/include/linux/nfs_page.h @@ -26,6 +26,7 @@ struct nfs_page { struct list_head wb_list, /* Defines state of page: */ *wb_list_head; /* read/write/commit */ struct file *wb_file; + fl_owner_t wb_lockowner; struct inode *wb_inode; struct rpc_cred *wb_cred; struct nfs4_state *wb_state; diff --git a/include/linux/nfs_xdr.h b/include/linux/nfs_xdr.h index 5bc59e4db5e3..a3ecfab78bc6 100644 --- a/include/linux/nfs_xdr.h +++ b/include/linux/nfs_xdr.h @@ -109,7 +109,6 @@ struct nfs_openargs { }; struct nfs_openres { - __u32 status; nfs4_stateid stateid; struct nfs_fh fh; struct nfs4_change_info * cinfo; @@ -129,24 +128,95 @@ struct nfs_open_confirmargs { }; struct nfs_open_confirmres { - __u32 status; nfs4_stateid stateid; }; /* + * Arguments to the open_reclaim call. + */ +struct nfs_open_reclaimargs { + struct nfs_fh * fh; + __u64 clientid; + __u32 seqid; + __u32 id; + __u32 share_access; + __u32 claim; + struct nfs4_getattr * f_getattr; +}; + +/* * Arguments to the close call. */ struct nfs_closeargs { struct nfs_fh * fh; nfs4_stateid stateid; __u32 seqid; + __u32 share_access; }; struct nfs_closeres { - __u32 status; nfs4_stateid stateid; }; +/* + * * Arguments to the lock,lockt, and locku call. + * */ +struct nfs_lowner { + __u64 clientid; + u32 id; +}; +struct nfs_open_to_lock { + __u32 open_seqid; + nfs4_stateid open_stateid; + __u32 lock_seqid; + struct nfs_lowner lock_owner; +}; + +struct nfs_exist_lock { + nfs4_stateid stateid; + __u32 seqid; +}; + +struct nfs_lock_opargs { + __u32 reclaim; + __u32 new_lock_owner; + union { + struct nfs_open_to_lock *open_lock; + struct nfs_exist_lock *exist_lock; + } u; +}; + +struct nfs_locku_opargs { + __u32 seqid; + nfs4_stateid stateid; +}; + +struct nfs_lockargs { + struct nfs_fh * fh; + __u32 type; + __u64 offset; + __u64 length; + union { + struct nfs_lock_opargs *lock; /* LOCK */ + struct nfs_lowner *lockt; /* LOCKT */ + struct nfs_locku_opargs *locku; /* LOCKU */ + } u; +}; + +struct nfs_lock_denied { + __u64 offset; + __u64 length; + __u32 type; + struct nfs_lowner owner; +}; + +struct nfs_lockres { + union { + nfs4_stateid stateid;/* LOCK success, LOCKU */ + struct nfs_lock_denied denied; /* LOCK failed, LOCKT success */ + } u; + struct nfs_server * server; +}; /* * Arguments to the read call. @@ -449,7 +519,6 @@ struct nfs4_getattr { u32 * gt_bmval; /* request */ struct nfs_fattr * gt_attrs; /* response */ struct nfs_fsstat * gt_fsstat; /* response */ - struct nfs_fsinfo * gt_fsinfo; /* response */ struct nfs_pathconf * gt_pathconf; /* response */ }; @@ -556,8 +625,6 @@ struct nfs4_op { struct nfs4_rename rename; struct nfs4_client * renew; struct nfs4_setattr setattr; - struct nfs4_setclientid setclientid; - struct nfs4_client * setclientid_confirm; } u; }; @@ -594,6 +661,7 @@ struct nfs_read_data { struct rpc_task task; struct inode *inode; struct rpc_cred *cred; + fl_owner_t lockowner; struct nfs_fattr fattr; /* fattr storage */ struct list_head pages; /* Coalesced read requests */ struct page *pagevec[NFS_READ_MAXIOV]; @@ -609,6 +677,7 @@ struct nfs_write_data { struct rpc_task task; struct inode *inode; struct rpc_cred *cred; + fl_owner_t lockowner; struct nfs_fattr fattr; struct nfs_writeverf verf; struct list_head pages; /* Coalesced requests we wish to flush */ @@ -627,6 +696,8 @@ struct nfs_page; */ struct nfs_rpc_ops { int version; /* Protocol version */ + struct dentry_operations *dentry_ops; + struct inode_operations *dir_inode_ops; int (*getroot) (struct nfs_server *, struct nfs_fh *, struct nfs_fattr *); @@ -673,6 +744,7 @@ struct nfs_rpc_ops { int (*file_release) (struct inode *, struct file *); void (*request_init)(struct nfs_page *, struct file *); int (*request_compatible)(struct nfs_page *, struct file *, struct page *); + int (*lock)(struct file *, int, struct file_lock *); }; /* diff --git a/include/linux/pci.h b/include/linux/pci.h index bc51ca9edef1..bde9c5e8dbf8 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -393,7 +393,6 @@ struct pci_dev { 0xffffffff. You only need to change this if your device has broken DMA or supports 64-bit transfers. */ - struct list_head pools; /* pci_pools tied to this device */ u64 consistent_dma_mask;/* Like dma_mask, but for pci_alloc_consistent mappings as @@ -416,8 +415,6 @@ struct pci_dev { */ unsigned int irq; struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ - struct resource dma_resource[DEVICE_COUNT_DMA]; - struct resource irq_resource[DEVICE_COUNT_IRQ]; char * slot_name; /* pointer to dev.bus_id */ @@ -694,12 +691,15 @@ const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, co int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass); /* kmem_cache style wrapper around pci_alloc_consistent() */ -struct pci_pool *pci_pool_create (const char *name, struct pci_dev *dev, - size_t size, size_t align, size_t allocation); -void pci_pool_destroy (struct pci_pool *pool); -void *pci_pool_alloc (struct pci_pool *pool, int flags, dma_addr_t *handle); -void pci_pool_free (struct pci_pool *pool, void *vaddr, dma_addr_t addr); +#include <linux/dmapool.h> + +#define pci_pool dma_pool +#define pci_pool_create(name, pdev, size, align, allocation) \ + dma_pool_create(name, &pdev->dev, size, align, allocation) +#define pci_pool_destroy(pool) dma_pool_destroy(pool) +#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) +#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) #if defined(CONFIG_ISA) || defined(CONFIG_EISA) extern struct pci_dev *isa_bridge; diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index c21bb5925bd1..a96b2fbdc511 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -216,28 +216,37 @@ /* Rage128 GL */ #define PCI_DEVICE_ID_ATI_RAGE128_RE 0x5245 #define PCI_DEVICE_ID_ATI_RAGE128_RF 0x5246 -#define PCI_DEVICE_ID_ATI_RAGE128_RG 0x534b -#define PCI_DEVICE_ID_ATI_RAGE128_RH 0x534c -#define PCI_DEVICE_ID_ATI_RAGE128_RI 0x534d +#define PCI_DEVICE_ID_ATI_RAGE128_RG 0x5247 /* Rage128 VR */ #define PCI_DEVICE_ID_ATI_RAGE128_RK 0x524b #define PCI_DEVICE_ID_ATI_RAGE128_RL 0x524c -#define PCI_DEVICE_ID_ATI_RAGE128_RM 0x5345 -#define PCI_DEVICE_ID_ATI_RAGE128_RN 0x5346 -#define PCI_DEVICE_ID_ATI_RAGE128_RO 0x5347 +#define PCI_DEVICE_ID_ATI_RAGE128_SE 0x5345 +#define PCI_DEVICE_ID_ATI_RAGE128_SF 0x5346 +#define PCI_DEVICE_ID_ATI_RAGE128_SG 0x5347 +#define PCI_DEVICE_ID_ATI_RAGE128_SH 0x5348 +#define PCI_DEVICE_ID_ATI_RAGE128_SK 0x534b +#define PCI_DEVICE_ID_ATI_RAGE128_SL 0x534c +#define PCI_DEVICE_ID_ATI_RAGE128_SM 0x534d +#define PCI_DEVICE_ID_ATI_RAGE128_SN 0x534e +/* Rage128 Ultra */ +#define PCI_DEVICE_ID_ATI_RAGE128_TF 0x5446 +#define PCI_DEVICE_ID_ATI_RAGE128_TL 0x544c +#define PCI_DEVICE_ID_ATI_RAGE128_TR 0x5452 +#define PCI_DEVICE_ID_ATI_RAGE128_TS 0x5453 +#define PCI_DEVICE_ID_ATI_RAGE128_TT 0x5454 +#define PCI_DEVICE_ID_ATI_RAGE128_TU 0x5455 /* Rage128 M3 */ #define PCI_DEVICE_ID_ATI_RAGE128_LE 0x4c45 #define PCI_DEVICE_ID_ATI_RAGE128_LF 0x4c46 -/* Rage128 Pro Ultra */ -#define PCI_DEVICE_ID_ATI_RAGE128_U1 0x5446 -#define PCI_DEVICE_ID_ATI_RAGE128_U2 0x544C -#define PCI_DEVICE_ID_ATI_RAGE128_U3 0x5452 +/* Rage128 M4 */ +#define PCI_DEVICE_ID_ATI_RAGE128_MF 0x4d46 +#define PCI_DEVICE_ID_ATI_RAGE128_ML 0x4d4c /* Rage128 Pro GL */ -#define PCI_DEVICE_ID_ATI_Rage128_PA 0x5041 -#define PCI_DEVICE_ID_ATI_Rage128_PB 0x5042 -#define PCI_DEVICE_ID_ATI_Rage128_PC 0x5043 -#define PCI_DEVICE_ID_ATI_Rage128_PD 0x5044 -#define PCI_DEVICE_ID_ATI_Rage128_PE 0x5045 +#define PCI_DEVICE_ID_ATI_RAGE128_PA 0x5041 +#define PCI_DEVICE_ID_ATI_RAGE128_PB 0x5042 +#define PCI_DEVICE_ID_ATI_RAGE128_PC 0x5043 +#define PCI_DEVICE_ID_ATI_RAGE128_PD 0x5044 +#define PCI_DEVICE_ID_ATI_RAGE128_PE 0x5045 #define PCI_DEVICE_ID_ATI_RAGE128_PF 0x5046 /* Rage128 Pro VR */ #define PCI_DEVICE_ID_ATI_RAGE128_PG 0x5047 @@ -291,6 +300,7 @@ #define PCI_DEVICE_ID_ATI_RADEON_Ig 0x4967 /* Radeon RV280 (9200) */ #define PCI_DEVICE_ID_ATI_RADEON_Y_ 0x5960 +#define PCI_DEVICE_ID_ATI_RADEON_Ya 0x5961 #define PCI_DEVICE_ID_ATI_RADEON_Yd 0x5964 /* Radeon R300 (9500) */ #define PCI_DEVICE_ID_ATI_RADEON_AD 0x4144 diff --git a/include/linux/pci_msi.h b/include/linux/pci_msi.h deleted file mode 100644 index 0e42e65bc3e1..000000000000 --- a/include/linux/pci_msi.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * ../include/linux/pci_msi.h - * - */ - -#ifndef _ASM_PCI_MSI_H -#define _ASM_PCI_MSI_H - -#include <linux/pci.h> - -#define MSI_AUTO -1 -#define NR_REPEATS 23 -#define NR_RESERVED_VECTORS 3 /*FIRST_DEVICE_VECTOR,FIRST_SYSTEM_VECTOR,0x80 */ - -/* - * Assume the maximum number of hot plug slots supported by the system is about - * ten. The worstcase is that each of these slots is hot-added with a device, - * which has two MSI/MSI-X capable functions. To avoid any MSI-X driver, which - * attempts to request all available vectors, NR_HP_RESERVED_VECTORS is defined - * as below to ensure at least one message is assigned to each detected MSI/ - * MSI-X device function. - */ -#define NR_HP_RESERVED_VECTORS 20 - -extern int vector_irq[NR_IRQS]; -extern cpumask_t pending_irq_balance_cpumask[NR_IRQS]; -extern void (*interrupt[NR_IRQS])(void); - -#ifdef CONFIG_SMP -#define set_msi_irq_affinity set_msi_affinity -#else -#define set_msi_irq_affinity NULL -static inline void move_msi(int vector) {} -#endif - -#ifndef CONFIG_X86_IO_APIC -static inline int get_ioapic_vector(struct pci_dev *dev) { return -1;} -static inline void restore_ioapic_irq_handler(int irq) {} -#else -extern void restore_ioapic_irq_handler(int irq); -#endif - -/* - * MSI-X Address Register - */ -#define PCI_MSIX_FLAGS_QSIZE 0x7FF -#define PCI_MSIX_FLAGS_ENABLE (1 << 15) -#define PCI_MSIX_FLAGS_BIRMASK (7 << 0) -#define PCI_MSIX_FLAGS_BITMASK (1 << 0) - -#define PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET 0 -#define PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET 4 -#define PCI_MSIX_ENTRY_DATA_OFFSET 8 -#define PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET 12 -#define PCI_MSIX_ENTRY_SIZE 16 - -#define msi_control_reg(base) (base + PCI_MSI_FLAGS) -#define msi_lower_address_reg(base) (base + PCI_MSI_ADDRESS_LO) -#define msi_upper_address_reg(base) (base + PCI_MSI_ADDRESS_HI) -#define msi_data_reg(base, is64bit) \ - ( (is64bit == 1) ? base+PCI_MSI_DATA_64 : base+PCI_MSI_DATA_32 ) -#define msi_mask_bits_reg(base, is64bit) \ - ( (is64bit == 1) ? base+PCI_MSI_MASK_BIT : base+PCI_MSI_MASK_BIT-4) -#define msi_disable(control) control &= ~PCI_MSI_FLAGS_ENABLE -#define multi_msi_capable(control) \ - (1 << ((control & PCI_MSI_FLAGS_QMASK) >> 1)) -#define multi_msi_enable(control, num) \ - control |= (((num >> 1) << 4) & PCI_MSI_FLAGS_QSIZE); -#define is_64bit_address(control) (control & PCI_MSI_FLAGS_64BIT) -#define is_mask_bit_support(control) (control & PCI_MSI_FLAGS_MASKBIT) -#define msi_enable(control, num) multi_msi_enable(control, num); \ - control |= PCI_MSI_FLAGS_ENABLE - -#define msix_control_reg msi_control_reg -#define msix_table_offset_reg(base) (base + 0x04) -#define msix_pba_offset_reg(base) (base + 0x08) -#define msix_enable(control) control |= PCI_MSIX_FLAGS_ENABLE -#define msix_disable(control) control &= ~PCI_MSIX_FLAGS_ENABLE -#define msix_table_size(control) ((control & PCI_MSIX_FLAGS_QSIZE)+1) -#define multi_msix_capable msix_table_size -#define msix_unmask(address) (address & ~PCI_MSIX_FLAGS_BITMASK) -#define msix_mask(address) (address | PCI_MSIX_FLAGS_BITMASK) -#define msix_is_pending(address) (address & PCI_MSIX_FLAGS_PENDMASK) - -extern char __dbg_str_buf[256]; -#define _DEFINE_DBG_BUFFER char __dbg_str_buf[256]; -#define _DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) -#define _DBG_K_TRACE_EXIT ((unsigned int)0x00000002) -#define _DBG_K_INFO ((unsigned int)0x00000004) -#define _DBG_K_ERROR ((unsigned int)0x00000008) -#define _DBG_K_TRACE (_DBG_K_TRACE_ENTRY | _DBG_K_TRACE_EXIT) - -#define _DEBUG_LEVEL (_DBG_K_INFO | _DBG_K_ERROR | _DBG_K_TRACE) -#define _DBG_PRINT( dbg_flags, args... ) \ -if ( _DEBUG_LEVEL & (dbg_flags) ) \ -{ \ - int len; \ - len = sprintf(__dbg_str_buf, "%s:%d: %s ", \ - __FILE__, __LINE__, __FUNCTION__ ); \ - sprintf(__dbg_str_buf + len, args); \ - printk(KERN_INFO "%s\n", __dbg_str_buf); \ -} - -#define MSI_FUNCTION_TRACE_ENTER \ - _DBG_PRINT (_DBG_K_TRACE_ENTRY, "%s", "[Entry]"); -#define MSI_FUNCTION_TRACE_EXIT \ - _DBG_PRINT (_DBG_K_TRACE_EXIT, "%s", "[Entry]"); - -/* - * MSI Defined Data Structures - */ -#define MSI_ADDRESS_HEADER 0xfee -#define MSI_ADDRESS_HEADER_SHIFT 12 -#define MSI_ADDRESS_HEADER_MASK 0xfff000 -#define MSI_TARGET_CPU_SHIFT 4 -#define MSI_TARGET_CPU_MASK 0xff -#define MSI_DELIVERY_MODE 0 -#define MSI_LEVEL_MODE 1 /* Edge always assert */ -#define MSI_TRIGGER_MODE 0 /* MSI is edge sensitive */ -#define MSI_LOGICAL_MODE 1 -#define MSI_REDIRECTION_HINT_MODE 0 -#ifdef CONFIG_SMP -#define MSI_TARGET_CPU logical_smp_processor_id() -#else -#define MSI_TARGET_CPU TARGET_CPUS -#endif - -struct msg_data { -#if defined(__LITTLE_ENDIAN_BITFIELD) - __u32 vector : 8; - __u32 delivery_mode : 3; /* 000b: FIXED | 001b: lowest prior */ - __u32 reserved_1 : 3; - __u32 level : 1; /* 0: deassert | 1: assert */ - __u32 trigger : 1; /* 0: edge | 1: level */ - __u32 reserved_2 : 16; -#elif defined(__BIG_ENDIAN_BITFIELD) - __u32 reserved_2 : 16; - __u32 trigger : 1; /* 0: edge | 1: level */ - __u32 level : 1; /* 0: deassert | 1: assert */ - __u32 reserved_1 : 3; - __u32 delivery_mode : 3; /* 000b: FIXED | 001b: lowest prior */ - __u32 vector : 8; -#else -#error "Bitfield endianness not defined! Check your byteorder.h" -#endif -} __attribute__ ((packed)); - -struct msg_address { - union { - struct { -#if defined(__LITTLE_ENDIAN_BITFIELD) - __u32 reserved_1 : 2; - __u32 dest_mode : 1; /*0:physic | 1:logic */ - __u32 redirection_hint: 1; /*0: dedicated CPU - 1: lowest priority */ - __u32 reserved_2 : 4; - __u32 dest_id : 24; /* Destination ID */ -#elif defined(__BIG_ENDIAN_BITFIELD) - __u32 dest_id : 24; /* Destination ID */ - __u32 reserved_2 : 4; - __u32 redirection_hint: 1; /*0: dedicated CPU - 1: lowest priority */ - __u32 dest_mode : 1; /*0:physic | 1:logic */ - __u32 reserved_1 : 2; -#else -#error "Bitfield endianness not defined! Check your byteorder.h" -#endif - }u; - __u32 value; - }lo_address; - __u32 hi_address; -} __attribute__ ((packed)); - -struct msi_desc { - struct { - __u8 type : 5; /* {0: unused, 5h:MSI, 11h:MSI-X} */ - __u8 maskbit : 1; /* mask-pending bit supported ? */ - __u8 reserved: 2; /* reserved */ - __u8 entry_nr; /* specific enabled entry */ - __u8 default_vector; /* default pre-assigned vector */ - __u8 current_cpu; /* current destination cpu */ - }msi_attrib; - - struct { - __u16 head; - __u16 tail; - }link; - - unsigned long mask_base; - struct pci_dev *dev; -}; - -#endif /* _ASM_PCI_MSI_H */ diff --git a/include/linux/pnp.h b/include/linux/pnp.h index 1dcef561a280..d728e2f5cf71 100644 --- a/include/linux/pnp.h +++ b/include/linux/pnp.h @@ -12,13 +12,12 @@ #include <linux/device.h> #include <linux/list.h> #include <linux/errno.h> +#include <linux/mod_devicetable.h> #define PNP_MAX_PORT 8 #define PNP_MAX_MEM 4 #define PNP_MAX_IRQ 2 #define PNP_MAX_DMA 2 -#define PNP_MAX_DEVICES 8 -#define PNP_ID_LEN 8 #define PNP_NAME_LEN 50 struct pnp_protocol; @@ -33,7 +32,9 @@ struct pnp_dev; #define pnp_port_start(dev,bar) ((dev)->res.port_resource[(bar)].start) #define pnp_port_end(dev,bar) ((dev)->res.port_resource[(bar)].end) #define pnp_port_flags(dev,bar) ((dev)->res.port_resource[(bar)].flags) -#define pnp_port_valid(dev,bar) (pnp_port_flags((dev),(bar)) & IORESOURCE_IO) +#define pnp_port_valid(dev,bar) \ + ((pnp_port_flags((dev),(bar)) & (IORESOURCE_IO | IORESOURCE_UNSET)) \ + == IORESOURCE_IO) #define pnp_port_len(dev,bar) \ ((pnp_port_start((dev),(bar)) == 0 && \ pnp_port_end((dev),(bar)) == \ @@ -45,7 +46,9 @@ struct pnp_dev; #define pnp_mem_start(dev,bar) ((dev)->res.mem_resource[(bar)].start) #define pnp_mem_end(dev,bar) ((dev)->res.mem_resource[(bar)].end) #define pnp_mem_flags(dev,bar) ((dev)->res.mem_resource[(bar)].flags) -#define pnp_mem_valid(dev,bar) (pnp_mem_flags((dev),(bar)) & IORESOURCE_MEM) +#define pnp_mem_valid(dev,bar) \ + ((pnp_mem_flags((dev),(bar)) & (IORESOURCE_MEM | IORESOURCE_UNSET)) \ + == IORESOURCE_MEM) #define pnp_mem_len(dev,bar) \ ((pnp_mem_start((dev),(bar)) == 0 && \ pnp_mem_end((dev),(bar)) == \ @@ -56,11 +59,15 @@ struct pnp_dev; #define pnp_irq(dev,bar) ((dev)->res.irq_resource[(bar)].start) #define pnp_irq_flags(dev,bar) ((dev)->res.irq_resource[(bar)].flags) -#define pnp_irq_valid(dev,bar) (pnp_irq_flags((dev),(bar)) & IORESOURCE_IRQ) +#define pnp_irq_valid(dev,bar) \ + ((pnp_irq_flags((dev),(bar)) & (IORESOURCE_IRQ | IORESOURCE_UNSET)) \ + == IORESOURCE_IRQ) #define pnp_dma(dev,bar) ((dev)->res.dma_resource[(bar)].start) #define pnp_dma_flags(dev,bar) ((dev)->res.dma_resource[(bar)].flags) -#define pnp_dma_valid(dev,bar) (pnp_dma_flags((dev),(bar)) & IORESOURCE_DMA) +#define pnp_dma_valid(dev,bar) \ + ((pnp_dma_flags((dev),(bar)) & (IORESOURCE_DMA | IORESOURCE_UNSET)) \ + == IORESOURCE_DMA) #define PNP_PORT_FLAG_16BITADDR (1<<0) #define PNP_PORT_FLAG_FIXED (1<<1) @@ -279,19 +286,6 @@ struct pnp_id { struct pnp_id * next; }; -struct pnp_device_id { - char id[PNP_ID_LEN]; - unsigned long driver_data; /* data private to the driver */ -}; - -struct pnp_card_device_id { - char id[PNP_ID_LEN]; - unsigned long driver_data; /* data private to the driver */ - struct { - char id[PNP_ID_LEN]; - } devs[PNP_MAX_DEVICES]; /* logical devices */ -}; - struct pnp_driver { char * name; const struct pnp_device_id *id_table; diff --git a/include/linux/security.h b/include/linux/security.h index 92786e0700c3..10789232ff05 100644 --- a/include/linux/security.h +++ b/include/linux/security.h @@ -171,6 +171,16 @@ struct swap_info_struct; * @flags contains the mount flags. * @data contains the filesystem-specific data. * Return 0 if permission is granted. + * @sb_copy_data: + * Allow mount option data to be copied prior to parsing by the filesystem, + * so that the security module can extract security-specific mount + * options cleanly (a filesystem may modify the data e.g. with strsep()). + * This also allows the original mount data to be stripped of security- + * specific options to avoid having to make filesystems aware of them. + * @fstype the type of filesystem being mounted. + * @orig the original mount data copied from userspace. + * @copy copied data which will be passed to the security module. + * Returns 0 if the copy was successful. * @sb_check_sb: * Check permission before the device with superblock @mnt->sb is mounted * on the mount point named by @nd. @@ -1024,7 +1034,8 @@ struct security_operations { int (*sb_alloc_security) (struct super_block * sb); void (*sb_free_security) (struct super_block * sb); - int (*sb_kern_mount) (struct super_block *sb); + int (*sb_copy_data)(const char *fstype, void *orig, void *copy); + int (*sb_kern_mount) (struct super_block *sb, void *data); int (*sb_statfs) (struct super_block * sb); int (*sb_mount) (char *dev_name, struct nameidata * nd, char *type, unsigned long flags, void *data); @@ -1308,9 +1319,14 @@ static inline void security_sb_free (struct super_block *sb) security_ops->sb_free_security (sb); } -static inline int security_sb_kern_mount (struct super_block *sb) +static inline int security_sb_copy_data (const char *fstype, void *orig, void *copy) { - return security_ops->sb_kern_mount (sb); + return security_ops->sb_copy_data (fstype, orig, copy); +} + +static inline int security_sb_kern_mount (struct super_block *sb, void *data) +{ + return security_ops->sb_kern_mount (sb, data); } static inline int security_sb_statfs (struct super_block *sb) @@ -1973,7 +1989,12 @@ static inline int security_sb_alloc (struct super_block *sb) static inline void security_sb_free (struct super_block *sb) { } -static inline int security_sb_kern_mount (struct super_block *sb) +static inline int security_sb_copy_data (const char *fstype, void *orig, void *copy) +{ + return 0; +} + +static inline int security_sb_kern_mount (struct super_block *sb, void *data) { return 0; } diff --git a/include/linux/slab.h b/include/linux/slab.h index d797c981f37e..69be5b308a11 100644 --- a/include/linux/slab.h +++ b/include/linux/slab.h @@ -101,6 +101,7 @@ extern void kfree(const void *); extern unsigned int ksize(const void *); extern int FASTCALL(kmem_cache_reap(int)); +extern int FASTCALL(kmem_ptr_validate(kmem_cache_t *cachep, void *ptr)); /* System wide caches */ extern kmem_cache_t *vm_area_cachep; diff --git a/include/linux/sonet.h b/include/linux/sonet.h index 30c45ec59e2e..753680296e17 100644 --- a/include/linux/sonet.h +++ b/include/linux/sonet.h @@ -56,9 +56,7 @@ struct sonet_stats { #define SONET_FRSENSE_SIZE 6 /* C1[3],H1[3] (0xff for unknown) */ -#ifndef __KERNEL__ -#undef __SONET_ITEMS -#else +#ifdef __KERNEL__ #include <asm/atomic.h> diff --git a/include/linux/sunrpc/auth.h b/include/linux/sunrpc/auth.h index 70cc3360e608..1f83e0f5b9d3 100644 --- a/include/linux/sunrpc/auth.h +++ b/include/linux/sunrpc/auth.h @@ -73,6 +73,7 @@ struct rpc_auth { * differ from the flavor in * au_ops->au_flavor in gss * case) */ + atomic_t au_count; /* Reference counter */ /* per-flavor data */ }; @@ -102,6 +103,10 @@ struct rpc_credops { u32 * (*crmarshal)(struct rpc_task *, u32 *, int); int (*crrefresh)(struct rpc_task *); u32 * (*crvalidate)(struct rpc_task *, u32 *); + int (*crwrap_req)(struct rpc_task *, kxdrproc_t, + void *, u32 *, void *); + int (*crunwrap_resp)(struct rpc_task *, kxdrproc_t, + void *, u32 *, void *); }; extern struct rpc_authops authunix_ops; @@ -124,6 +129,8 @@ void put_rpccred(struct rpc_cred *); void rpcauth_unbindcred(struct rpc_task *); u32 * rpcauth_marshcred(struct rpc_task *, u32 *); u32 * rpcauth_checkverf(struct rpc_task *, u32 *); +int rpcauth_wrap_req(struct rpc_task *task, kxdrproc_t encode, void *rqstp, u32 *data, void *obj); +int rpcauth_unwrap_resp(struct rpc_task *task, kxdrproc_t decode, void *rqstp, u32 *data, void *obj); int rpcauth_refreshcred(struct rpc_task *); void rpcauth_invalcred(struct rpc_task *); int rpcauth_uptodatecred(struct rpc_task *); diff --git a/include/linux/sunrpc/clnt.h b/include/linux/sunrpc/clnt.h index 99d57fec03a9..917ec29d789b 100644 --- a/include/linux/sunrpc/clnt.h +++ b/include/linux/sunrpc/clnt.h @@ -26,6 +26,8 @@ struct rpc_portmap { __u32 pm_vers; __u32 pm_prot; __u16 pm_port; + unsigned char pm_binding : 1; /* doing a getport() */ + struct rpc_wait_queue pm_bindwait; /* waiting on getport() */ }; struct rpc_inode; @@ -34,6 +36,7 @@ struct rpc_inode; * The high-level client handle */ struct rpc_clnt { + atomic_t cl_count; /* Number of clones */ atomic_t cl_users; /* number of references */ struct rpc_xprt * cl_xprt; /* transport */ struct rpc_procinfo * cl_procinfo; /* procedure info */ @@ -48,26 +51,27 @@ struct rpc_clnt { cl_intr : 1,/* interruptible */ cl_chatty : 1,/* be verbose */ cl_autobind : 1,/* use getport() */ - cl_binding : 1,/* doing a getport() */ cl_droppriv : 1,/* enable NFS suid hack */ cl_oneshot : 1,/* dispose after use */ cl_dead : 1;/* abandoned */ - struct rpc_rtt cl_rtt; /* RTO estimator data */ - - struct rpc_portmap cl_pmap; /* port mapping */ - struct rpc_wait_queue cl_bindwait; /* waiting on getport() */ + struct rpc_rtt * cl_rtt; /* RTO estimator data */ + struct rpc_portmap * cl_pmap; /* port mapping */ int cl_nodelen; /* nodename length */ char cl_nodename[UNX_MAXNODENAME]; char cl_pathname[30];/* Path in rpc_pipe_fs */ struct dentry * cl_dentry; /* inode */ + struct rpc_clnt * cl_parent; /* Points to parent of clones */ + struct rpc_rtt cl_rtt_default; + struct rpc_portmap cl_pmap_default; + char cl_inline_name[32]; }; #define cl_timeout cl_xprt->timeout -#define cl_prog cl_pmap.pm_prog -#define cl_vers cl_pmap.pm_vers -#define cl_port cl_pmap.pm_port -#define cl_prot cl_pmap.pm_prot +#define cl_prog cl_pmap->pm_prog +#define cl_vers cl_pmap->pm_vers +#define cl_port cl_pmap->pm_port +#define cl_prot cl_pmap->pm_prot /* * General RPC program info @@ -108,6 +112,7 @@ struct rpc_procinfo { struct rpc_clnt *rpc_create_client(struct rpc_xprt *xprt, char *servname, struct rpc_program *info, u32 version, rpc_authflavor_t authflavor); +struct rpc_clnt *rpc_clone_client(struct rpc_clnt *); int rpc_shutdown_client(struct rpc_clnt *); int rpc_destroy_client(struct rpc_clnt *); void rpc_release_client(struct rpc_clnt *); diff --git a/include/linux/sunrpc/gss_api.h b/include/linux/sunrpc/gss_api.h index 35988e7bfb77..cbb60ac22fd4 100644 --- a/include/linux/sunrpc/gss_api.h +++ b/include/linux/sunrpc/gss_api.h @@ -16,6 +16,7 @@ #ifdef __KERNEL__ #include <linux/sunrpc/xdr.h> +#include <linux/uio.h> /* The mechanism-independent gss-api context: */ struct gss_ctx { @@ -39,11 +40,11 @@ u32 gss_import_sec_context( u32 gss_get_mic( struct gss_ctx *ctx_id, u32 qop, - struct xdr_netobj *message, + struct xdr_buf *message, struct xdr_netobj *mic_token); u32 gss_verify_mic( struct gss_ctx *ctx_id, - struct xdr_netobj *message, + struct xdr_buf *message, struct xdr_netobj *mic_token, u32 *qstate); u32 gss_delete_sec_context( @@ -95,11 +96,11 @@ struct gss_api_ops { u32 (*gss_get_mic)( struct gss_ctx *ctx_id, u32 qop, - struct xdr_netobj *message, + struct xdr_buf *message, struct xdr_netobj *mic_token); u32 (*gss_verify_mic)( struct gss_ctx *ctx_id, - struct xdr_netobj *message, + struct xdr_buf *message, struct xdr_netobj *mic_token, u32 *qstate); void (*gss_delete_sec_context)( diff --git a/include/linux/sunrpc/gss_krb5.h b/include/linux/sunrpc/gss_krb5.h index 8db6d1e13a69..9616746407f3 100644 --- a/include/linux/sunrpc/gss_krb5.h +++ b/include/linux/sunrpc/gss_krb5.h @@ -50,7 +50,6 @@ struct krb5_ctx { struct crypto_tfm *seq; s32 endtime; u32 seq_send; - u32 seq_recv; struct xdr_netobj mech_used; }; @@ -73,7 +72,7 @@ enum seal_alg { SEAL_ALG_DES3KD = 0x0002 }; -#define RSA_MD5_CKSUM_LENGTH 16 +#define KRB5_CKSUM_LENGTH 8 #define CKSUMTYPE_CRC32 0x0001 #define CKSUMTYPE_RSA_MD4 0x0002 @@ -100,16 +99,6 @@ enum seal_alg { #define KG_EMPTY_CCACHE (39756044L) #define KG_NO_CTYPES (39756045L) -#define KV5M_PRINCIPAL (-1760647423L) -#define KV5M_KEYBLOCK (-1760647421L) -#define KV5M_CHECKSUM (-1760647420L) -#define KV5M_ADDRESS (-1760647390L) -#define KV5M_AUTHENTICATOR (-1760647410L) -#define KV5M_AUTH_CONTEXT (-1760647383L) -#define KV5M_AUTHDATA (-1760647414L) -#define KV5M_GSS_OID (-1760647372L) -#define KV5M_GSS_QUEUE (-1760647371L) - /* per Kerberos v5 protocol spec crypto types from the wire. * these get mapped to linux kernel crypto routines. */ @@ -126,19 +115,18 @@ enum seal_alg { #define ENCTYPE_UNKNOWN 0x01ff s32 -krb5_make_checksum(s32 cksumtype, - struct xdr_netobj *input, +krb5_make_checksum(s32 cksumtype, char *header, struct xdr_buf *body, struct xdr_netobj *cksum); u32 krb5_make_token(struct krb5_ctx *context_handle, int qop_req, - struct xdr_netobj * input_message_buffer, - struct xdr_netobj * output_message_buffer, int toktype); + struct xdr_buf *input_message_buffer, + struct xdr_netobj *output_message_buffer, int toktype); u32 krb5_read_token(struct krb5_ctx *context_handle, struct xdr_netobj *input_token_buffer, - struct xdr_netobj *message_buffer, + struct xdr_buf *message_buffer, int *qop_state, int toktype); u32 diff --git a/include/linux/sunrpc/rpc_pipe_fs.h b/include/linux/sunrpc/rpc_pipe_fs.h index eabb2ebf2289..63929349571f 100644 --- a/include/linux/sunrpc/rpc_pipe_fs.h +++ b/include/linux/sunrpc/rpc_pipe_fs.h @@ -14,6 +14,7 @@ struct rpc_pipe_msg { struct rpc_pipe_ops { ssize_t (*upcall)(struct file *, struct rpc_pipe_msg *, char __user *, size_t); ssize_t (*downcall)(struct file *, const char __user *, size_t); + void (*release_pipe)(struct inode *); void (*destroy_msg)(struct rpc_pipe_msg *); }; @@ -21,12 +22,15 @@ struct rpc_inode { struct inode vfs_inode; void *private; struct list_head pipe; + struct list_head in_upcall; int pipelen; int nreaders; + int nwriters; wait_queue_head_t waitq; #define RPC_PIPE_WAIT_FOR_OPEN 1 int flags; struct rpc_pipe_ops *ops; + struct work_struct queue_timeout; }; static inline struct rpc_inode * @@ -35,7 +39,6 @@ RPC_I(struct inode *inode) return container_of(inode, struct rpc_inode, vfs_inode); } -extern void rpc_inode_setowner(struct inode *, void *); extern int rpc_queue_upcall(struct inode *, struct rpc_pipe_msg *); extern struct dentry *rpc_mkdir(char *, struct rpc_clnt *); diff --git a/include/linux/sunrpc/sched.h b/include/linux/sunrpc/sched.h index 5e2d23e0ce6c..6b8e3eb91513 100644 --- a/include/linux/sunrpc/sched.h +++ b/include/linux/sunrpc/sched.h @@ -48,8 +48,6 @@ struct rpc_task { __u8 tk_garb_retry, tk_cred_retry, tk_suid_retry; - u32 tk_gss_seqno; /* rpcsec_gss sequence number - used on this request */ /* * timeout_fn to be executed by timer bottom half @@ -110,6 +108,7 @@ typedef void (*rpc_action)(struct rpc_task *); #define RPC_TASK_ROOTCREDS 0x0040 /* force root creds */ #define RPC_TASK_DYNAMIC 0x0080 /* task was kmalloc'ed */ #define RPC_TASK_KILLED 0x0100 /* task was killed */ +#define RPC_TASK_SOFT 0x0200 /* Use soft timeouts */ #define RPC_IS_ASYNC(t) ((t)->tk_flags & RPC_TASK_ASYNC) #define RPC_IS_SETUID(t) ((t)->tk_flags & RPC_TASK_SETUID) @@ -119,6 +118,7 @@ typedef void (*rpc_action)(struct rpc_task *); #define RPC_ASSASSINATED(t) ((t)->tk_flags & RPC_TASK_KILLED) #define RPC_IS_ACTIVATED(t) ((t)->tk_active) #define RPC_DO_CALLBACK(t) ((t)->tk_callback != NULL) +#define RPC_IS_SOFT(t) ((t)->tk_flags & RPC_TASK_SOFT) #define RPC_TASK_SLEEPING 0 #define RPC_TASK_RUNNING 1 diff --git a/include/linux/sunrpc/xdr.h b/include/linux/sunrpc/xdr.h index 2c6f76d1cc14..8082a0029100 100644 --- a/include/linux/sunrpc/xdr.h +++ b/include/linux/sunrpc/xdr.h @@ -141,6 +141,10 @@ void xdr_shift_iovec(struct iovec *, int, size_t); extern int xdr_kmap(struct iovec *, struct xdr_buf *, size_t); extern void xdr_kunmap(struct xdr_buf *, size_t); extern void xdr_shift_buf(struct xdr_buf *, size_t); +extern void _copy_from_pages(char *, struct page **, size_t, size_t); +extern void xdr_buf_from_iov(struct iovec *, struct xdr_buf *); +extern int xdr_buf_subsegment(struct xdr_buf *, struct xdr_buf *, int, int); +extern int xdr_buf_read_netobj(struct xdr_buf *, struct xdr_netobj *, int); /* * Helper structure for copying from an sk_buff. diff --git a/include/linux/sunrpc/xprt.h b/include/linux/sunrpc/xprt.h index e29381edeaea..393e6dc6a268 100644 --- a/include/linux/sunrpc/xprt.h +++ b/include/linux/sunrpc/xprt.h @@ -95,6 +95,7 @@ struct rpc_rqst { struct rpc_rqst * rq_next; /* free list */ int rq_cong; /* has incremented xprt->cong */ int rq_received; /* receive completed */ + u32 rq_seqno; /* gss seq no. used on req. */ struct list_head rq_list; @@ -162,6 +163,12 @@ struct rpc_xprt { tcp_offset; /* fragment offset */ unsigned long tcp_copied, /* copied to request */ tcp_flags; + /* + * Disconnection of idle sockets + */ + struct work_struct task_cleanup; + struct timer_list timer; + unsigned long last_used; /* * Send stuff @@ -201,6 +208,7 @@ int xprt_clear_backlog(struct rpc_xprt *); void xprt_sock_setbufsize(struct rpc_xprt *); #define XPRT_CONNECT 0 +#define XPRT_LOCKED 1 #define xprt_connected(xp) (test_bit(XPRT_CONNECT, &(xp)->sockstate)) #define xprt_set_connected(xp) (set_bit(XPRT_CONNECT, &(xp)->sockstate)) diff --git a/include/linux/sysctl.h b/include/linux/sysctl.h index 935be9d21b69..dc4167a0dbf2 100644 --- a/include/linux/sysctl.h +++ b/include/linux/sysctl.h @@ -583,6 +583,8 @@ enum { NET_SCTP_PRESERVE_ENABLE = 11, NET_SCTP_MAX_BURST = 12, NET_SCTP_ADDIP_ENABLE = 13, + NET_SCTP_RMEM = 14, + NET_SCTP_WMEM = 15, }; /* /proc/sys/net/bridge */ diff --git a/include/linux/usb.h b/include/linux/usb.h index c405f81be765..45caca344ca3 100644 --- a/include/linux/usb.h +++ b/include/linux/usb.h @@ -274,7 +274,6 @@ struct usb_device { }; #define to_usb_device(d) container_of(d, struct usb_device, dev) -extern struct usb_device *usb_alloc_dev(struct usb_device *parent, struct usb_bus *); extern struct usb_device *usb_get_dev(struct usb_device *dev); extern void usb_put_dev(struct usb_device *dev); @@ -1016,16 +1015,6 @@ static inline unsigned int __create_pipe(struct usb_device *dev, unsigned int en /* -------------------------------------------------------------------------- */ -/* - * Debugging and troubleshooting/diagnostic helpers. - */ -void usb_show_device_descriptor(struct usb_device_descriptor *); -void usb_show_config_descriptor(struct usb_config_descriptor *); -void usb_show_interface_descriptor(struct usb_interface_descriptor *); -void usb_show_endpoint_descriptor(struct usb_endpoint_descriptor *); -void usb_show_device(struct usb_device *); -void usb_show_string(struct usb_device *dev, char *id, int index); - #ifdef DEBUG #define dbg(format, arg...) printk(KERN_DEBUG "%s: " format "\n" , __FILE__ , ## arg) #else diff --git a/include/net/bluetooth/hci.h b/include/net/bluetooth/hci.h index 59523c39d6fb..39bce6f7bd5d 100644 --- a/include/net/bluetooth/hci.h +++ b/include/net/bluetooth/hci.h @@ -253,6 +253,17 @@ struct hci_cp_write_dev_class { __u8 dev_class[3]; } __attribute__ ((packed)); +#define OCF_READ_VOICE_SETTING 0x0025 +struct hci_rp_read_voice_setting { + __u8 status; + __u16 voice_setting; +} __attribute__ ((packed)); + +#define OCF_WRITE_VOICE_SETTING 0x0026 +struct hci_cp_write_voice_setting { + __u16 voice_setting; +} __attribute__ ((packed)); + #define OCF_HOST_BUFFER_SIZE 0x0033 struct hci_cp_host_buffer_size { __u16 acl_mtu; diff --git a/include/net/bluetooth/hci_core.h b/include/net/bluetooth/hci_core.h index 6a429873df9c..03c51bba58a3 100644 --- a/include/net/bluetooth/hci_core.h +++ b/include/net/bluetooth/hci_core.h @@ -71,11 +71,12 @@ struct hci_dev { __u8 type; bdaddr_t bdaddr; __u8 features[8]; + __u16 voice_setting; __u16 pkt_type; __u16 link_policy; __u16 link_mode; - + atomic_t cmd_cnt; unsigned int acl_cnt; unsigned int sco_cnt; @@ -88,7 +89,7 @@ struct hci_dev { unsigned long cmd_last_tx; unsigned long acl_last_tx; unsigned long sco_last_tx; - + struct tasklet_struct cmd_task; struct tasklet_struct rx_task; struct tasklet_struct tx_task; @@ -119,7 +120,7 @@ struct hci_dev { #endif struct module *owner; - + int (*open)(struct hci_dev *hdev); int (*close)(struct hci_dev *hdev); int (*flush)(struct hci_dev *hdev); diff --git a/include/net/irda/irlap.h b/include/net/irda/irlap.h index 9385cffa836c..c7c2aecaf637 100644 --- a/include/net/irda/irlap.h +++ b/include/net/irda/irlap.h @@ -283,4 +283,10 @@ static inline int irlap_is_primary(struct irlap_cb *self) return(ret); } +/* Clear a pending IrLAP disconnect. - Jean II */ +static inline void irlap_clear_disconnect(struct irlap_cb *self) +{ + self->disconnect_pending = FALSE; +} + #endif diff --git a/include/net/irda/irlmp.h b/include/net/irda/irlmp.h index 32bf8ea47d14..d92b02561993 100644 --- a/include/net/irda/irlmp.h +++ b/include/net/irda/irlmp.h @@ -237,7 +237,7 @@ int irlmp_udata_request(struct lsap_cb *, struct sk_buff *); void irlmp_udata_indication(struct lsap_cb *, struct sk_buff *); #ifdef CONFIG_IRDA_ULTRA -int irlmp_connless_data_request(struct lsap_cb *, struct sk_buff *); +int irlmp_connless_data_request(struct lsap_cb *, struct sk_buff *, __u8); void irlmp_connless_data_indication(struct lsap_cb *, struct sk_buff *); #endif /* CONFIG_IRDA_ULTRA */ diff --git a/include/net/sctp/constants.h b/include/net/sctp/constants.h index f031313bb3ef..6112e85f7a9c 100644 --- a/include/net/sctp/constants.h +++ b/include/net/sctp/constants.h @@ -323,7 +323,7 @@ typedef enum { #define SCTP_DEFAULT_COOKIE_LIFE_USEC 0 /* microseconds */ #define SCTP_DEFAULT_MINWINDOW 1500 /* default minimum rwnd size */ -#define SCTP_DEFAULT_MAXWINDOW 32768 /* default rwnd size */ +#define SCTP_DEFAULT_MAXWINDOW 65535 /* default rwnd size */ #define SCTP_DEFAULT_MAXSEGMENT 1500 /* MTU size, this is the limit * to which we will raise the P-MTU. */ diff --git a/include/video/aty128.h b/include/video/aty128.h index 7892a02665ff..7079beb005e8 100644 --- a/include/video/aty128.h +++ b/include/video/aty128.h @@ -415,5 +415,8 @@ #define PWR_MGT_SLOWDOWN_MCLK 0x00002000 #define PMI_PMSCR_REG 0x60 + +/* used by ATI bug fix for hardware ROM */ +#define RAGE128_MPP_TB_CONFIG 0x01c0 #endif /* REG_RAGE128_H */ diff --git a/include/video/radeon.h b/include/video/radeon.h index 8730694e968a..c8b7042aaadd 100644 --- a/include/video/radeon.h +++ b/include/video/radeon.h @@ -365,6 +365,9 @@ #define DSTCACHE_CTLSTAT 0x1714 #define DEFAULT_PITCH_OFFSET 0x16E0 #define DEFAULT_SC_BOTTOM_RIGHT 0x16E8 +#define DEFAULT_SC_TOP_LEFT 0x16EC +#define SRC_PITCH_OFFSET 0x1428 +#define DST_PITCH_OFFSET 0x142C #define DP_GUI_MASTER_CNTL 0x146C #define SC_TOP_LEFT 0x16EC #define SC_BOTTOM_RIGHT 0x16F0 @@ -373,18 +376,23 @@ #define RB2D_DSTCACHE_CTLSTAT 0x342C #define LVDS_GEN_CNTL 0x02d0 #define LVDS_PLL_CNTL 0x02d4 +#define FP2_GEN_CNTL 0x0288 +#define TMDS_CNTL 0x0294 #define TMDS_CRC 0x02a0 #define TMDS_TRANSMITTER_CNTL 0x02a4 +#define MPP_TB_CONFIG 0x01c0 + +//#define BASE_CODE 0x0f0b +#define BIOS_0_SCRATCH 0x0010 +#define BIOS_1_SCRATCH 0x0014 +#define BIOS_2_SCRATCH 0x0018 +#define BIOS_3_SCRATCH 0x001c +#define BIOS_4_SCRATCH 0x0020 +#define BIOS_5_SCRATCH 0x0024 +#define BIOS_6_SCRATCH 0x0028 +#define BIOS_7_SCRATCH 0x002c -#define RADEON_BASE_CODE 0x0f0b -#define RADEON_BIOS_0_SCRATCH 0x0010 -#define RADEON_BIOS_1_SCRATCH 0x0014 -#define RADEON_BIOS_2_SCRATCH 0x0018 -#define RADEON_BIOS_3_SCRATCH 0x001c -#define RADEON_BIOS_4_SCRATCH 0x0020 -#define RADEON_BIOS_5_SCRATCH 0x0024 -#define RADEON_BIOS_6_SCRATCH 0x0028 -#define RADEON_BIOS_7_SCRATCH 0x002c +#define HDP_SOFT_RESET (1 << 26) #define TV_DAC_CNTL 0x088c #define GPIOPAD_MASK 0x0198 @@ -406,7 +414,7 @@ #define PPLL_DIV_3 0x0007 #define VCLK_ECP_CNTL 0x0008 #define HTOTAL_CNTL 0x0009 -#define M_SPLL_REF_FB_DIV 0x000a +#define X_MPLL_REF_FB_DIV 0x000a #define AGP_PLL_CNTL 0x000b #define SPLL_CNTL 0x000c #define SCLK_CNTL 0x000d @@ -422,6 +430,7 @@ #define P2PLL_CNTL 0x002a #define P2PLL_REF_DIV 0x002b #define PIXCLKS_CNTL 0x002d +#define SCLK_MORE_CNTL 0x0035 /* MCLK_CNTL bit constants */ #define FORCEON_MCLKA (1 << 16) @@ -431,6 +440,13 @@ #define FORCEON_MC (1 << 20) #define FORCEON_AIC (1 << 21) +/* SCLK_CNTL bit constants */ +#define DYN_STOP_LAT_MASK 0x00007ff8 +#define CP_MAX_DYN_STOP_LAT 0x0008 +#define SCLK_FORCEON_MASK 0xffff8000 + +/* SCLK_MORE_CNTL bit constants */ +#define SCLK_MORE_FORCEON 0x0700 /* BUS_CNTL bit constants */ #define BUS_DBL_RESYNC 0x00000001 @@ -457,12 +473,26 @@ #define BUS_READ_BURST 0x40000000 #define BUS_RDY_READ_DLY 0x80000000 +/* PIXCLKS_CNTL */ +#define PIX2CLK_SRC_SEL_MASK 0x03 +#define PIX2CLK_SRC_SEL_CPUCLK 0x00 +#define PIX2CLK_SRC_SEL_PSCANCLK 0x01 +#define PIX2CLK_SRC_SEL_BYTECLK 0x02 +#define PIX2CLK_SRC_SEL_P2PLLCLK 0x03 +#define PIX2CLK_ALWAYS_ONb (1<<6) +#define PIX2CLK_DAC_ALWAYS_ONb (1<<7) +#define PIXCLK_TV_SRC_SEL (1 << 8) +#define PIXCLK_LVDS_ALWAYS_ONb (1 << 14) +#define PIXCLK_TMDS_ALWAYS_ONb (1 << 15) + /* CLOCK_CNTL_INDEX bit constants */ #define PLL_WR_EN 0x00000080 /* CONFIG_CNTL bit constants */ #define CFG_VGA_RAM_EN 0x00000100 +#define CFG_ATI_REV_ID_MASK (0xf << 16) +#define CFG_ATI_REV_A11 (0 << 16) /* CRTC_EXT_CNTL bit constants */ #define VGA_ATI_LINEAR 0x00000008 @@ -484,6 +514,7 @@ #define CRTC_DBL_SCAN_EN 0x00000001 #define CRTC_CUR_EN 0x00010000 #define CRTC_INTERLACE_EN (1 << 1) +#define CRTC_BYPASS_LUT_EN (1 << 14) #define CRTC_EXT_DISP_EN (1 << 24) #define CRTC_EN (1 << 25) #define CRTC_DISP_REQ_EN_B (1 << 26) @@ -500,6 +531,22 @@ /* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */ #define CUR_LOCK 0x80000000 +/* GPIO bit constants */ +#define GPIO_A_0 (1 << 0) +#define GPIO_A_1 (1 << 1) +#define GPIO_Y_0 (1 << 8) +#define GPIO_Y_1 (1 << 9) +#define GPIO_EN_0 (1 << 16) +#define GPIO_EN_1 (1 << 17) +#define GPIO_MASK_0 (1 << 24) +#define GPIO_MASK_1 (1 << 25) +#define VGA_DDC_DATA_OUTPUT GPIO_A_0 +#define VGA_DDC_CLK_OUTPUT GPIO_A_1 +#define VGA_DDC_DATA_INPUT GPIO_Y_0 +#define VGA_DDC_CLK_INPUT GPIO_Y_1 +#define VGA_DDC_DATA_OUT_EN GPIO_EN_0 +#define VGA_DDC_CLK_OUT_EN GPIO_EN_1 + /* FP bit constants */ #define FP_CRTC_H_TOTAL_MASK 0x000003ff @@ -536,6 +583,25 @@ #define FP_USE_SHADOW_EN (1 << 24) #define FP_CRT_SYNC_ALT (1 << 26) +/* FP2_GEN_CNTL bit constants */ +#define FP2_BLANK_EN (1 << 1) +#define FP2_ON (1 << 2) +#define FP2_PANEL_FORMAT (1 << 3) +#define FP2_SOURCE_SEL_MASK (3 << 10) +#define FP2_SOURCE_SEL_CRTC2 (1 << 10) +#define FP2_SRC_SEL_MASK (3 << 13) +#define FP2_SRC_SEL_CRTC2 (1 << 13) +#define FP2_FP_POL (1 << 16) +#define FP2_LP_POL (1 << 17) +#define FP2_SCK_POL (1 << 18) +#define FP2_LCD_CNTL_MASK (7 << 19) +#define FP2_PAD_FLOP_EN (1 << 22) +#define FP2_CRC_EN (1 << 23) +#define FP2_CRC_READ_EN (1 << 24) +#define FP2_DV0_EN (1 << 25) +#define FP2_DV0_RATE_SEL_SDR (1 << 26) + + /* LVDS_GEN_CNTL bit constants */ #define LVDS_ON (1 << 0) #define LVDS_DISPLAY_DIS (1 << 1) @@ -560,7 +626,7 @@ #define TMDS_PLL_EN (1 << 0) #define TMDS_PLLRST (1 << 1) #define TMDS_RAN_PAT_RST (1 << 7) -#define ICHCSEL (1 << 28) +#define TMDS_ICHCSEL (1 << 28) /* FP_HORZ_STRETCH bit constants */ #define HORZ_STRETCH_RATIO_MASK 0xffff @@ -592,14 +658,25 @@ #define DAC_4BPP_PIX_ORDER 0x00000200 #define DAC_CRC_EN 0x00080000 #define DAC_MASK_ALL (0xff << 24) +#define DAC_PDWN (1 << 15) #define DAC_EXPAND_MODE (1 << 14) #define DAC_VGA_ADR_EN (1 << 13) -#define DAC_RANGE_CNTL (3 << 0) -#define DAC_BLANKING (1 << 2) -#define DAC_CMP_EN (1 << 3) +#define DAC_RANGE_CNTL (3 << 0) +#define DAC_RANGE_CNTL_MASK 0x03 +#define DAC_BLANKING (1 << 2) +#define DAC_CMP_EN (1 << 3) +#define DAC_CMP_OUTPUT (1 << 7) /* DAC_CNTL2 bit constants */ #define DAC2_CMP_EN (1 << 7) +#define DAC2_PALETTE_ACCESS_CNTL (1 << 5) + +/* DAC_EXT_CNTL bit constants */ +#define DAC_FORCE_BLANK_OFF_EN (1 << 4) +#define DAC_FORCE_DATA_EN (1 << 5) +#define DAC_FORCE_DATA_SEL_MASK (3 << 6) +#define DAC_FORCE_DATA_MASK 0x0003ff00 +#define DAC_FORCE_DATA_SHIFT 8 /* GEN_RESET_CNTL bit constants */ #define SOFT_RESET_GUI 0x00000001 @@ -796,6 +873,11 @@ #define MRDCKA1_RESET 0x00020000 /* VCLK_ECP_CNTL constants */ +#define VCLK_SRC_SEL_MASK 0x03 +#define VCLK_SRC_SEL_CPUCLK 0x00 +#define VCLK_SRC_SEL_PSCANCLK 0x01 +#define VCLK_SRC_SEL_BYTECLK 0x02 +#define VCLK_SRC_SEL_PPLLCLK 0x03 #define PIXCLK_ALWAYS_ONb 0x00000040 #define PIXCLK_DAC_ALWAYS_ONb 0x00000080 @@ -862,6 +944,7 @@ #define DEFAULT_TILE_MASK 0xc0000000 #define PPLL_DIV_SEL_MASK 0x00000300 #define PPLL_RESET 0x00000001 +#define PPLL_SLEEP 0x00000002 #define PPLL_ATOMIC_UPDATE_EN 0x00010000 #define PPLL_REF_DIV_MASK 0x000003ff #define PPLL_FB3_DIV_MASK 0x000007ff @@ -869,8 +952,999 @@ #define PPLL_ATOMIC_UPDATE_R 0x00008000 #define PPLL_ATOMIC_UPDATE_W 0x00008000 #define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000 +#define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18) +#define R300_PPLL_REF_DIV_ACC_SHIFT 18 #define GUI_ACTIVE 0x80000000 + +#define MC_IND_INDEX 0x01F8 +#define MC_IND_DATA 0x01FC +#define MEM_REFRESH_CNTL 0x0178 + +// CLK_PIN_CNTL +#define CLK_PIN_CNTL__OSC_EN_MASK 0x00000001L +#define CLK_PIN_CNTL__OSC_EN 0x00000001L +#define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK 0x00000004L +#define CLK_PIN_CNTL__XTL_LOW_GAIN 0x00000004L +#define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK 0x00000010L +#define CLK_PIN_CNTL__DONT_USE_XTALIN 0x00000010L +#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK 0x00000020L +#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE 0x00000020L +#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK 0x00000800L +#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN 0x00000800L +#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK 0x00001000L +#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN 0x00001000L +#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK 0x00002000L +#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND 0x00002000L +#define CLK_PIN_CNTL__CG_SPARE_MASK 0x00004000L +#define CLK_PIN_CNTL__CG_SPARE 0x00004000L +#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK 0x00008000L +#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL 0x00008000L +#define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK 0x00010000L +#define CLK_PIN_CNTL__CP_CLK_RUNNING 0x00010000L +#define CLK_PIN_CNTL__CG_SPARE_RD_MASK 0x00060000L +#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK 0x00080000L +#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb 0x00080000L +#define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK 0xff000000L + +// CLK_PWRMGT_CNTL_M6 +#define CLK_PWRMGT_CNTL_M6__MPLL_PWRMGT_OFF__SHIFT 0x00000000 +#define CLK_PWRMGT_CNTL_M6__SPLL_PWRMGT_OFF__SHIFT 0x00000001 +#define CLK_PWRMGT_CNTL_M6__PPLL_PWRMGT_OFF__SHIFT 0x00000002 +#define CLK_PWRMGT_CNTL_M6__P2PLL_PWRMGT_OFF__SHIFT 0x00000003 +#define CLK_PWRMGT_CNTL_M6__MCLK_TURNOFF__SHIFT 0x00000004 +#define CLK_PWRMGT_CNTL_M6__SCLK_TURNOFF__SHIFT 0x00000005 +#define CLK_PWRMGT_CNTL_M6__PCLK_TURNOFF__SHIFT 0x00000006 +#define CLK_PWRMGT_CNTL_M6__P2CLK_TURNOFF__SHIFT 0x00000007 +#define CLK_PWRMGT_CNTL_M6__MC_CH_MODE__SHIFT 0x00000008 +#define CLK_PWRMGT_CNTL_M6__TEST_MODE__SHIFT 0x00000009 +#define CLK_PWRMGT_CNTL_M6__GLOBAL_PMAN_EN__SHIFT 0x0000000a +#define CLK_PWRMGT_CNTL_M6__ENGINE_DYNCLK_MODE__SHIFT 0x0000000c +#define CLK_PWRMGT_CNTL_M6__ACTIVE_HILO_LAT__SHIFT 0x0000000d +#define CLK_PWRMGT_CNTL_M6__DISP_DYN_STOP_LAT__SHIFT 0x0000000f +#define CLK_PWRMGT_CNTL_M6__MC_BUSY__SHIFT 0x00000010 +#define CLK_PWRMGT_CNTL_M6__MC_INT_CNTL__SHIFT 0x00000011 +#define CLK_PWRMGT_CNTL_M6__MC_SWITCH__SHIFT 0x00000012 +#define CLK_PWRMGT_CNTL_M6__DLL_READY__SHIFT 0x00000013 +#define CLK_PWRMGT_CNTL_M6__DISP_PM__SHIFT 0x00000014 +#define CLK_PWRMGT_CNTL_M6__DYN_STOP_MODE__SHIFT 0x00000015 +#define CLK_PWRMGT_CNTL_M6__CG_NO1_DEBUG__SHIFT 0x00000018 +#define CLK_PWRMGT_CNTL_M6__TVPLL_PWRMGT_OFF__SHIFT 0x0000001e +#define CLK_PWRMGT_CNTL_M6__TVCLK_TURNOFF__SHIFT 0x0000001f + +// P2PLL_CNTL +#define P2PLL_CNTL__P2PLL_RESET_MASK 0x00000001L +#define P2PLL_CNTL__P2PLL_RESET 0x00000001L +#define P2PLL_CNTL__P2PLL_SLEEP_MASK 0x00000002L +#define P2PLL_CNTL__P2PLL_SLEEP 0x00000002L +#define P2PLL_CNTL__P2PLL_TST_EN_MASK 0x00000004L +#define P2PLL_CNTL__P2PLL_TST_EN 0x00000004L +#define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK 0x00000010L +#define P2PLL_CNTL__P2PLL_REFCLK_SEL 0x00000010L +#define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK 0x00000020L +#define P2PLL_CNTL__P2PLL_FBCLK_SEL 0x00000020L +#define P2PLL_CNTL__P2PLL_TCPOFF_MASK 0x00000040L +#define P2PLL_CNTL__P2PLL_TCPOFF 0x00000040L +#define P2PLL_CNTL__P2PLL_TVCOMAX_MASK 0x00000080L +#define P2PLL_CNTL__P2PLL_TVCOMAX 0x00000080L +#define P2PLL_CNTL__P2PLL_PCP_MASK 0x00000700L +#define P2PLL_CNTL__P2PLL_PVG_MASK 0x00003800L +#define P2PLL_CNTL__P2PLL_PDC_MASK 0x0000c000L +#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK 0x00010000L +#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN 0x00010000L +#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK 0x00040000L +#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC 0x00040000L +#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK 0x00080000L +#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET 0x00080000L + +// PIXCLKS_CNTL +#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT 0x00000000 +#define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT 0x00000004 +#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT 0x00000005 +#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT 0x00000006 +#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT 0x00000007 +#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT 0x00000008 +#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT 0x0000000b +#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT 0x0000000c +#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT 0x0000000d +#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT 0x0000000e +#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT 0x0000000f + + +// PIXCLKS_CNTL +#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK 0x00000003L +#define PIXCLKS_CNTL__PIX2CLK_INVERT_MASK 0x00000010L +#define PIXCLKS_CNTL__PIX2CLK_INVERT 0x00000010L +#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT_MASK 0x00000020L +#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT 0x00000020L +#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb_MASK 0x00000040L +#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb 0x00000040L +#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb_MASK 0x00000080L +#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb 0x00000080L +#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL_MASK 0x00000100L +#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL 0x00000100L +#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb_MASK 0x00000800L +#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb 0x00000800L +#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb_MASK 0x00001000L +#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb 0x00001000L +#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb_MASK 0x00002000L +#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb 0x00002000L +#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb_MASK 0x00004000L +#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb 0x00004000L +#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb_MASK 0x00008000L +#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb 0x00008000L + + +// P2PLL_DIV_0 +#define P2PLL_DIV_0__P2PLL_FB_DIV_MASK 0x000007ffL +#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK 0x00008000L +#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W 0x00008000L +#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK 0x00008000L +#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R 0x00008000L +#define P2PLL_DIV_0__P2PLL_POST_DIV_MASK 0x00070000L + +// SCLK_CNTL_M6 +#define SCLK_CNTL_M6__SCLK_SRC_SEL_MASK 0x00000007L +#define SCLK_CNTL_M6__CP_MAX_DYN_STOP_LAT_MASK 0x00000008L +#define SCLK_CNTL_M6__CP_MAX_DYN_STOP_LAT 0x00000008L +#define SCLK_CNTL_M6__HDP_MAX_DYN_STOP_LAT_MASK 0x00000010L +#define SCLK_CNTL_M6__HDP_MAX_DYN_STOP_LAT 0x00000010L +#define SCLK_CNTL_M6__TV_MAX_DYN_STOP_LAT_MASK 0x00000020L +#define SCLK_CNTL_M6__TV_MAX_DYN_STOP_LAT 0x00000020L +#define SCLK_CNTL_M6__E2_MAX_DYN_STOP_LAT_MASK 0x00000040L +#define SCLK_CNTL_M6__E2_MAX_DYN_STOP_LAT 0x00000040L +#define SCLK_CNTL_M6__SE_MAX_DYN_STOP_LAT_MASK 0x00000080L +#define SCLK_CNTL_M6__SE_MAX_DYN_STOP_LAT 0x00000080L +#define SCLK_CNTL_M6__IDCT_MAX_DYN_STOP_LAT_MASK 0x00000100L +#define SCLK_CNTL_M6__IDCT_MAX_DYN_STOP_LAT 0x00000100L +#define SCLK_CNTL_M6__VIP_MAX_DYN_STOP_LAT_MASK 0x00000200L +#define SCLK_CNTL_M6__VIP_MAX_DYN_STOP_LAT 0x00000200L +#define SCLK_CNTL_M6__RE_MAX_DYN_STOP_LAT_MASK 0x00000400L +#define SCLK_CNTL_M6__RE_MAX_DYN_STOP_LAT 0x00000400L +#define SCLK_CNTL_M6__PB_MAX_DYN_STOP_LAT_MASK 0x00000800L +#define SCLK_CNTL_M6__PB_MAX_DYN_STOP_LAT 0x00000800L +#define SCLK_CNTL_M6__TAM_MAX_DYN_STOP_LAT_MASK 0x00001000L +#define SCLK_CNTL_M6__TAM_MAX_DYN_STOP_LAT 0x00001000L +#define SCLK_CNTL_M6__TDM_MAX_DYN_STOP_LAT_MASK 0x00002000L +#define SCLK_CNTL_M6__TDM_MAX_DYN_STOP_LAT 0x00002000L +#define SCLK_CNTL_M6__RB_MAX_DYN_STOP_LAT_MASK 0x00004000L +#define SCLK_CNTL_M6__RB_MAX_DYN_STOP_LAT 0x00004000L +#define SCLK_CNTL_M6__FORCE_DISP2_MASK 0x00008000L +#define SCLK_CNTL_M6__FORCE_DISP2 0x00008000L +#define SCLK_CNTL_M6__FORCE_CP_MASK 0x00010000L +#define SCLK_CNTL_M6__FORCE_CP 0x00010000L +#define SCLK_CNTL_M6__FORCE_HDP_MASK 0x00020000L +#define SCLK_CNTL_M6__FORCE_HDP 0x00020000L +#define SCLK_CNTL_M6__FORCE_DISP1_MASK 0x00040000L +#define SCLK_CNTL_M6__FORCE_DISP1 0x00040000L +#define SCLK_CNTL_M6__FORCE_TOP_MASK 0x00080000L +#define SCLK_CNTL_M6__FORCE_TOP 0x00080000L +#define SCLK_CNTL_M6__FORCE_E2_MASK 0x00100000L +#define SCLK_CNTL_M6__FORCE_E2 0x00100000L +#define SCLK_CNTL_M6__FORCE_SE_MASK 0x00200000L +#define SCLK_CNTL_M6__FORCE_SE 0x00200000L +#define SCLK_CNTL_M6__FORCE_IDCT_MASK 0x00400000L +#define SCLK_CNTL_M6__FORCE_IDCT 0x00400000L +#define SCLK_CNTL_M6__FORCE_VIP_MASK 0x00800000L +#define SCLK_CNTL_M6__FORCE_VIP 0x00800000L +#define SCLK_CNTL_M6__FORCE_RE_MASK 0x01000000L +#define SCLK_CNTL_M6__FORCE_RE 0x01000000L +#define SCLK_CNTL_M6__FORCE_PB_MASK 0x02000000L +#define SCLK_CNTL_M6__FORCE_PB 0x02000000L +#define SCLK_CNTL_M6__FORCE_TAM_MASK 0x04000000L +#define SCLK_CNTL_M6__FORCE_TAM 0x04000000L +#define SCLK_CNTL_M6__FORCE_TDM_MASK 0x08000000L +#define SCLK_CNTL_M6__FORCE_TDM 0x08000000L +#define SCLK_CNTL_M6__FORCE_RB_MASK 0x10000000L +#define SCLK_CNTL_M6__FORCE_RB 0x10000000L +#define SCLK_CNTL_M6__FORCE_TV_SCLK_MASK 0x20000000L +#define SCLK_CNTL_M6__FORCE_TV_SCLK 0x20000000L +#define SCLK_CNTL_M6__FORCE_SUBPIC_MASK 0x40000000L +#define SCLK_CNTL_M6__FORCE_SUBPIC 0x40000000L +#define SCLK_CNTL_M6__FORCE_OV0_MASK 0x80000000L +#define SCLK_CNTL_M6__FORCE_OV0 0x80000000L + +// SCLK_MORE_CNTL +#define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT_MASK 0x00000001L +#define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT 0x00000001L +#define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT_MASK 0x00000002L +#define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT 0x00000002L +#define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT_MASK 0x00000004L +#define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT 0x00000004L +#define SCLK_MORE_CNTL__FORCE_DISPREGS_MASK 0x00000100L +#define SCLK_MORE_CNTL__FORCE_DISPREGS 0x00000100L +#define SCLK_MORE_CNTL__FORCE_MC_GUI_MASK 0x00000200L +#define SCLK_MORE_CNTL__FORCE_MC_GUI 0x00000200L +#define SCLK_MORE_CNTL__FORCE_MC_HOST_MASK 0x00000400L +#define SCLK_MORE_CNTL__FORCE_MC_HOST 0x00000400L +#define SCLK_MORE_CNTL__STOP_SCLK_EN_MASK 0x00001000L +#define SCLK_MORE_CNTL__STOP_SCLK_EN 0x00001000L +#define SCLK_MORE_CNTL__STOP_SCLK_A_MASK 0x00002000L +#define SCLK_MORE_CNTL__STOP_SCLK_A 0x00002000L +#define SCLK_MORE_CNTL__STOP_SCLK_B_MASK 0x00004000L +#define SCLK_MORE_CNTL__STOP_SCLK_B 0x00004000L +#define SCLK_MORE_CNTL__STOP_SCLK_C_MASK 0x00008000L +#define SCLK_MORE_CNTL__STOP_SCLK_C 0x00008000L +#define SCLK_MORE_CNTL__HALF_SPEED_SCLK_MASK 0x00010000L +#define SCLK_MORE_CNTL__HALF_SPEED_SCLK 0x00010000L +#define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP_MASK 0x00020000L +#define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP 0x00020000L +#define SCLK_MORE_CNTL__TVFB_SOFT_RESET_MASK 0x00040000L +#define SCLK_MORE_CNTL__TVFB_SOFT_RESET 0x00040000L +#define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC_MASK 0x00080000L +#define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC 0x00080000L +#define SCLK_MORE_CNTL__VOLTAGE_DELAY_SEL_MASK 0x00300000L +#define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK_MASK 0x00400000L +#define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK 0x00400000L +#define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK_MASK 0x00800000L +#define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK 0x00800000L +#define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK 0xff000000L + +// MCLK_CNTL_M6 +#define MCLK_CNTL_M6__MCLKA_SRC_SEL_MASK 0x00000007L +#define MCLK_CNTL_M6__YCLKA_SRC_SEL_MASK 0x00000070L +#define MCLK_CNTL_M6__MCLKB_SRC_SEL_MASK 0x00000700L +#define MCLK_CNTL_M6__YCLKB_SRC_SEL_MASK 0x00007000L +#define MCLK_CNTL_M6__FORCE_MCLKA_MASK 0x00010000L +#define MCLK_CNTL_M6__FORCE_MCLKA 0x00010000L +#define MCLK_CNTL_M6__FORCE_MCLKB_MASK 0x00020000L +#define MCLK_CNTL_M6__FORCE_MCLKB 0x00020000L +#define MCLK_CNTL_M6__FORCE_YCLKA_MASK 0x00040000L +#define MCLK_CNTL_M6__FORCE_YCLKA 0x00040000L +#define MCLK_CNTL_M6__FORCE_YCLKB_MASK 0x00080000L +#define MCLK_CNTL_M6__FORCE_YCLKB 0x00080000L +#define MCLK_CNTL_M6__FORCE_MC_MASK 0x00100000L +#define MCLK_CNTL_M6__FORCE_MC 0x00100000L +#define MCLK_CNTL_M6__FORCE_AIC_MASK 0x00200000L +#define MCLK_CNTL_M6__FORCE_AIC 0x00200000L +#define MCLK_CNTL_M6__MRDCKA0_SOUTSEL_MASK 0x03000000L +#define MCLK_CNTL_M6__MRDCKA1_SOUTSEL_MASK 0x0c000000L +#define MCLK_CNTL_M6__MRDCKB0_SOUTSEL_MASK 0x30000000L +#define MCLK_CNTL_M6__MRDCKB1_SOUTSEL_MASK 0xc0000000L + +// MCLK_MISC +#define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK 0x00000003L +#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK 0x00000004L +#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL 0x00000004L +#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK 0x00000008L +#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL 0x00000008L +#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK 0x00000010L +#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN 0x00000010L +#define MCLK_MISC__DLL_READY_LAT_MASK 0x00000100L +#define MCLK_MISC__DLL_READY_LAT 0x00000100L +#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK 0x00001000L +#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT 0x00001000L +#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK 0x00002000L +#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT 0x00002000L +#define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK 0x00004000L +#define MCLK_MISC__MC_MCLK_DYN_ENABLE 0x00004000L +#define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK 0x00008000L +#define MCLK_MISC__IO_MCLK_DYN_ENABLE 0x00008000L +#define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK 0x00010000L +#define MCLK_MISC__CGM_CLK_TO_OUTPIN 0x00010000L +#define MCLK_MISC__CLK_OR_COUNT_SEL_MASK 0x00020000L +#define MCLK_MISC__CLK_OR_COUNT_SEL 0x00020000L +#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK 0x00040000L +#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND 0x00040000L +#define MCLK_MISC__CGM_SPARE_RD_MASK 0x00300000L +#define MCLK_MISC__CGM_SPARE_A_RD_MASK 0x00c00000L +#define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK 0x01000000L +#define MCLK_MISC__TCLK_TO_YCLKB_EN 0x01000000L +#define MCLK_MISC__CGM_SPARE_A_MASK 0x0e000000L + +// VCLK_ECP_CNTL +#define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK 0x00000003L +#define VCLK_ECP_CNTL__VCLK_INVERT_MASK 0x00000010L +#define VCLK_ECP_CNTL__VCLK_INVERT 0x00000010L +#define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT_MASK 0x00000020L +#define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT 0x00000020L +#define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb_MASK 0x00000040L +#define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb 0x00000040L +#define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb_MASK 0x00000080L +#define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb 0x00000080L +#define VCLK_ECP_CNTL__ECP_DIV_MASK 0x00000300L +#define VCLK_ECP_CNTL__ECP_FORCE_ON_MASK 0x00040000L +#define VCLK_ECP_CNTL__ECP_FORCE_ON 0x00040000L +#define VCLK_ECP_CNTL__SUBCLK_FORCE_ON_MASK 0x00080000L +#define VCLK_ECP_CNTL__SUBCLK_FORCE_ON 0x00080000L + +// PLL_PWRMGT_CNTL +#define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK 0x00000001L +#define PLL_PWRMGT_CNTL__MPLL_TURNOFF 0x00000001L +#define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK 0x00000002L +#define PLL_PWRMGT_CNTL__SPLL_TURNOFF 0x00000002L +#define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK 0x00000004L +#define PLL_PWRMGT_CNTL__PPLL_TURNOFF 0x00000004L +#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK 0x00000008L +#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF 0x00000008L +#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK 0x00000010L +#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF 0x00000010L +#define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK 0x000001e0L +#define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK 0x00000600L +#define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK 0x00001800L +#define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK 0x00002000L +#define PLL_PWRMGT_CNTL__PM_MODE_SEL 0x00002000L +#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK 0x00004000L +#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND 0x00004000L +#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK 0x00008000L +#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND 0x00008000L +#define PLL_PWRMGT_CNTL__MOBILE_SU_MASK 0x00010000L +#define PLL_PWRMGT_CNTL__MOBILE_SU 0x00010000L +#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK 0x00020000L +#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK 0x00020000L +#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK 0x00040000L +#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK 0x00040000L +#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK 0x00080000L +#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE 0x00080000L +#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK 0x00100000L +#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE 0x00100000L +#define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD_MASK 0x00200000L +#define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD 0x00200000L +#define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK 0xff000000L + +// CLK_PWRMGT_CNTL_M6 +#define CLK_PWRMGT_CNTL_M6__MPLL_PWRMGT_OFF_MASK 0x00000001L +#define CLK_PWRMGT_CNTL_M6__MPLL_PWRMGT_OFF 0x00000001L +#define CLK_PWRMGT_CNTL_M6__SPLL_PWRMGT_OFF_MASK 0x00000002L +#define CLK_PWRMGT_CNTL_M6__SPLL_PWRMGT_OFF 0x00000002L +#define CLK_PWRMGT_CNTL_M6__PPLL_PWRMGT_OFF_MASK 0x00000004L +#define CLK_PWRMGT_CNTL_M6__PPLL_PWRMGT_OFF 0x00000004L +#define CLK_PWRMGT_CNTL_M6__P2PLL_PWRMGT_OFF_MASK 0x00000008L +#define CLK_PWRMGT_CNTL_M6__P2PLL_PWRMGT_OFF 0x00000008L +#define CLK_PWRMGT_CNTL_M6__MCLK_TURNOFF_MASK 0x00000010L +#define CLK_PWRMGT_CNTL_M6__MCLK_TURNOFF 0x00000010L +#define CLK_PWRMGT_CNTL_M6__SCLK_TURNOFF_MASK 0x00000020L +#define CLK_PWRMGT_CNTL_M6__SCLK_TURNOFF 0x00000020L +#define CLK_PWRMGT_CNTL_M6__PCLK_TURNOFF_MASK 0x00000040L +#define CLK_PWRMGT_CNTL_M6__PCLK_TURNOFF 0x00000040L +#define CLK_PWRMGT_CNTL_M6__P2CLK_TURNOFF_MASK 0x00000080L +#define CLK_PWRMGT_CNTL_M6__P2CLK_TURNOFF 0x00000080L +#define CLK_PWRMGT_CNTL_M6__MC_CH_MODE_MASK 0x00000100L +#define CLK_PWRMGT_CNTL_M6__MC_CH_MODE 0x00000100L +#define CLK_PWRMGT_CNTL_M6__TEST_MODE_MASK 0x00000200L +#define CLK_PWRMGT_CNTL_M6__TEST_MODE 0x00000200L +#define CLK_PWRMGT_CNTL_M6__GLOBAL_PMAN_EN_MASK 0x00000400L +#define CLK_PWRMGT_CNTL_M6__GLOBAL_PMAN_EN 0x00000400L +#define CLK_PWRMGT_CNTL_M6__ENGINE_DYNCLK_MODE_MASK 0x00001000L +#define CLK_PWRMGT_CNTL_M6__ENGINE_DYNCLK_MODE 0x00001000L +#define CLK_PWRMGT_CNTL_M6__ACTIVE_HILO_LAT_MASK 0x00006000L +#define CLK_PWRMGT_CNTL_M6__DISP_DYN_STOP_LAT_MASK 0x00008000L +#define CLK_PWRMGT_CNTL_M6__DISP_DYN_STOP_LAT 0x00008000L +#define CLK_PWRMGT_CNTL_M6__MC_BUSY_MASK 0x00010000L +#define CLK_PWRMGT_CNTL_M6__MC_BUSY 0x00010000L +#define CLK_PWRMGT_CNTL_M6__MC_INT_CNTL_MASK 0x00020000L +#define CLK_PWRMGT_CNTL_M6__MC_INT_CNTL 0x00020000L +#define CLK_PWRMGT_CNTL_M6__MC_SWITCH_MASK 0x00040000L +#define CLK_PWRMGT_CNTL_M6__MC_SWITCH 0x00040000L +#define CLK_PWRMGT_CNTL_M6__DLL_READY_MASK 0x00080000L +#define CLK_PWRMGT_CNTL_M6__DLL_READY 0x00080000L +#define CLK_PWRMGT_CNTL_M6__DISP_PM_MASK 0x00100000L +#define CLK_PWRMGT_CNTL_M6__DISP_PM 0x00100000L +#define CLK_PWRMGT_CNTL_M6__DYN_STOP_MODE_MASK 0x00e00000L +#define CLK_PWRMGT_CNTL_M6__CG_NO1_DEBUG_MASK 0x3f000000L +#define CLK_PWRMGT_CNTL_M6__TVPLL_PWRMGT_OFF_MASK 0x40000000L +#define CLK_PWRMGT_CNTL_M6__TVPLL_PWRMGT_OFF 0x40000000L +#define CLK_PWRMGT_CNTL_M6__TVCLK_TURNOFF_MASK 0x80000000L +#define CLK_PWRMGT_CNTL_M6__TVCLK_TURNOFF 0x80000000L + +// BUS_CNTL1 +#define BUS_CNTL1__PMI_IO_DISABLE_MASK 0x00000001L +#define BUS_CNTL1__PMI_IO_DISABLE 0x00000001L +#define BUS_CNTL1__PMI_MEM_DISABLE_MASK 0x00000002L +#define BUS_CNTL1__PMI_MEM_DISABLE 0x00000002L +#define BUS_CNTL1__PMI_BM_DISABLE_MASK 0x00000004L +#define BUS_CNTL1__PMI_BM_DISABLE 0x00000004L +#define BUS_CNTL1__PMI_INT_DISABLE_MASK 0x00000008L +#define BUS_CNTL1__PMI_INT_DISABLE 0x00000008L +#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK 0x00000020L +#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE 0x00000020L +#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK 0x00000100L +#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS 0x00000100L +#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK 0x00000200L +#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS 0x00000200L +#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK 0x00000400L +#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS 0x00000400L +#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK 0x00000800L +#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS 0x00000800L +#define BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK 0x0c000000L +#define BUS_CNTL1__SEND_SBA_LATENCY_MASK 0x70000000L +#define BUS_CNTL1__AGPCLK_VALID_MASK 0x80000000L +#define BUS_CNTL1__AGPCLK_VALID 0x80000000L + +// BUS_CNTL1 +#define BUS_CNTL1__PMI_IO_DISABLE__SHIFT 0x00000000 +#define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT 0x00000001 +#define BUS_CNTL1__PMI_BM_DISABLE__SHIFT 0x00000002 +#define BUS_CNTL1__PMI_INT_DISABLE__SHIFT 0x00000003 +#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT 0x00000005 +#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT 0x00000008 +#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT 0x00000009 +#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT 0x0000000a +#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT 0x0000000b +#define BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT 0x0000001a +#define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT 0x0000001c +#define BUS_CNTL1__AGPCLK_VALID__SHIFT 0x0000001f + +// CRTC_OFFSET_CNTL +#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK 0x0000000fL +#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK 0x000000f0L +#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK 0x00004000L +#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT 0x00004000L +#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_MASK 0x00008000L +#define CRTC_OFFSET_CNTL__CRTC_TILE_EN 0x00008000L +#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL_MASK 0x00010000L +#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL 0x00010000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN_MASK 0x00020000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN 0x00020000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN_MASK 0x000c0000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN_MASK 0x00100000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN 0x00100000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_MASK 0x00200000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC 0x00200000L +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN_MASK 0x10000000L +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN 0x10000000L +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN_MASK 0x20000000L +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000L +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK 0x40000000L +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET 0x40000000L +#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK 0x80000000L +#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK 0x80000000L + +// CRTC_GEN_CNTL +#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK 0x00000001L +#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001L +#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK 0x00000002L +#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN 0x00000002L +#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK 0x00000010L +#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN 0x00000010L +#define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK 0x00000f00L +#define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK 0x00008000L +#define CRTC_GEN_CNTL__CRTC_ICON_EN 0x00008000L +#define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK 0x00010000L +#define CRTC_GEN_CNTL__CRTC_CUR_EN 0x00010000L +#define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK 0x00060000L +#define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK 0x00700000L +#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK 0x01000000L +#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN 0x01000000L +#define CRTC_GEN_CNTL__CRTC_EN_MASK 0x02000000L +#define CRTC_GEN_CNTL__CRTC_EN 0x02000000L +#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK 0x04000000L +#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000L + +// CRTC2_GEN_CNTL +#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK 0x00000001L +#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN 0x00000001L +#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK 0x00000002L +#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN 0x00000002L +#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK 0x00000010L +#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE 0x00000010L +#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK 0x00000020L +#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE 0x00000020L +#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK 0x00000040L +#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE 0x00000040L +#define CRTC2_GEN_CNTL__CRT2_ON_MASK 0x00000080L +#define CRTC2_GEN_CNTL__CRT2_ON 0x00000080L +#define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK 0x00000f00L +#define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK 0x00008000L +#define CRTC2_GEN_CNTL__CRTC2_ICON_EN 0x00008000L +#define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK 0x00010000L +#define CRTC2_GEN_CNTL__CRTC2_CUR_EN 0x00010000L +#define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK 0x00700000L +#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK 0x00800000L +#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS 0x00800000L +#define CRTC2_GEN_CNTL__CRTC2_EN_MASK 0x02000000L +#define CRTC2_GEN_CNTL__CRTC2_EN 0x02000000L +#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK 0x04000000L +#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B 0x04000000L +#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK 0x08000000L +#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN 0x08000000L +#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK 0x10000000L +#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS 0x10000000L +#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK 0x20000000L +#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS 0x20000000L + +// AGP_CNTL +#define AGP_CNTL__MAX_IDLE_CLK_MASK 0x000000ffL +#define AGP_CNTL__HOLD_RD_FIFO_MASK 0x00000100L +#define AGP_CNTL__HOLD_RD_FIFO 0x00000100L +#define AGP_CNTL__HOLD_RQ_FIFO_MASK 0x00000200L +#define AGP_CNTL__HOLD_RQ_FIFO 0x00000200L +#define AGP_CNTL__EN_2X_STBB_MASK 0x00000400L +#define AGP_CNTL__EN_2X_STBB 0x00000400L +#define AGP_CNTL__FORCE_FULL_SBA_MASK 0x00000800L +#define AGP_CNTL__FORCE_FULL_SBA 0x00000800L +#define AGP_CNTL__SBA_DIS_MASK 0x00001000L +#define AGP_CNTL__SBA_DIS 0x00001000L +#define AGP_CNTL__AGP_REV_ID_MASK 0x00002000L +#define AGP_CNTL__AGP_REV_ID 0x00002000L +#define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK 0x00004000L +#define AGP_CNTL__REG_CRIPPLE_AGP4X 0x00004000L +#define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK 0x00008000L +#define AGP_CNTL__REG_CRIPPLE_AGP2X4X 0x00008000L +#define AGP_CNTL__FORCE_INT_VREF_MASK 0x00010000L +#define AGP_CNTL__FORCE_INT_VREF 0x00010000L +#define AGP_CNTL__PENDING_SLOTS_VAL_MASK 0x00060000L +#define AGP_CNTL__PENDING_SLOTS_SEL_MASK 0x00080000L +#define AGP_CNTL__PENDING_SLOTS_SEL 0x00080000L +#define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK 0x00100000L +#define AGP_CNTL__EN_EXTENDED_AD_STB_2X 0x00100000L +#define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK 0x00200000L +#define AGP_CNTL__DIS_QUEUED_GNT_FIX 0x00200000L +#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK 0x00400000L +#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET 0x00400000L +#define AGP_CNTL__EN_RBFCALM_MASK 0x00800000L +#define AGP_CNTL__EN_RBFCALM 0x00800000L +#define AGP_CNTL__FORCE_EXT_VREF_MASK 0x01000000L +#define AGP_CNTL__FORCE_EXT_VREF 0x01000000L +#define AGP_CNTL__DIS_RBF_MASK 0x02000000L +#define AGP_CNTL__DIS_RBF 0x02000000L +#define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK 0x04000000L +#define AGP_CNTL__DELAY_FIRST_SBA_EN 0x04000000L +#define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK 0x38000000L +#define AGP_CNTL__AGP_MISC_MASK 0xc0000000L + +// AGP_CNTL +#define AGP_CNTL__MAX_IDLE_CLK__SHIFT 0x00000000 +#define AGP_CNTL__HOLD_RD_FIFO__SHIFT 0x00000008 +#define AGP_CNTL__HOLD_RQ_FIFO__SHIFT 0x00000009 +#define AGP_CNTL__EN_2X_STBB__SHIFT 0x0000000a +#define AGP_CNTL__FORCE_FULL_SBA__SHIFT 0x0000000b +#define AGP_CNTL__SBA_DIS__SHIFT 0x0000000c +#define AGP_CNTL__AGP_REV_ID__SHIFT 0x0000000d +#define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT 0x0000000e +#define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT 0x0000000f +#define AGP_CNTL__FORCE_INT_VREF__SHIFT 0x00000010 +#define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT 0x00000011 +#define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT 0x00000013 +#define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT 0x00000014 +#define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT 0x00000015 +#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT 0x00000016 +#define AGP_CNTL__EN_RBFCALM__SHIFT 0x00000017 +#define AGP_CNTL__FORCE_EXT_VREF__SHIFT 0x00000018 +#define AGP_CNTL__DIS_RBF__SHIFT 0x00000019 +#define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT 0x0000001a +#define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT 0x0000001b +#define AGP_CNTL__AGP_MISC__SHIFT 0x0000001e + +// DISP_MISC_CNTL +#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK 0x00000001L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP 0x00000001L +#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK 0x00000002L +#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP 0x00000002L +#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK 0x00000004L +#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP 0x00000004L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK 0x00000010L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK 0x00000010L +#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK 0x00000020L +#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK 0x00000020L +#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK 0x00000040L +#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK 0x00000040L +#define DISP_MISC_CNTL__SYNC_STRENGTH_MASK 0x00000300L +#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK 0x00000400L +#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN 0x00000400L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK 0x00001000L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP 0x00001000L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK 0x00008000L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK 0x00008000L +#define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK 0x00010000L +#define DISP_MISC_CNTL__SOFT_RESET_LVDS 0x00010000L +#define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK 0x00020000L +#define DISP_MISC_CNTL__SOFT_RESET_TMDS 0x00020000L +#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK 0x00040000L +#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS 0x00040000L +#define DISP_MISC_CNTL__SOFT_RESET_TV_MASK 0x00080000L +#define DISP_MISC_CNTL__SOFT_RESET_TV 0x00080000L +#define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK 0x00f00000L +#define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK 0x0f000000L +#define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK 0xf0000000L + +// DISP_PWR_MAN +#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK 0x00000001L +#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN 0x00000001L +#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK 0x00000010L +#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN 0x00000010L +#define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK 0x00000300L +#define DISP_PWR_MAN__DISP_D3_RST_MASK 0x00010000L +#define DISP_PWR_MAN__DISP_D3_RST 0x00010000L +#define DISP_PWR_MAN__DISP_D3_REG_RST_MASK 0x00020000L +#define DISP_PWR_MAN__DISP_D3_REG_RST 0x00020000L +#define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK 0x00040000L +#define DISP_PWR_MAN__DISP_D3_GRPH_RST 0x00040000L +#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK 0x00080000L +#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST 0x00080000L +#define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK 0x00100000L +#define DISP_PWR_MAN__DISP_D3_OV0_RST 0x00100000L +#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK 0x00200000L +#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST 0x00200000L +#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK 0x00400000L +#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST 0x00400000L +#define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK 0x00800000L +#define DISP_PWR_MAN__DISP_D1D2_OV0_RST 0x00800000L +#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK 0x01000000L +#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST 0x01000000L +#define DISP_PWR_MAN__TV_ENABLE_RST_MASK 0x02000000L +#define DISP_PWR_MAN__TV_ENABLE_RST 0x02000000L +#define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK 0x04000000L +#define DISP_PWR_MAN__AUTO_PWRUP_EN 0x04000000L + +// MC_IND_INDEX +#define MC_IND_INDEX__MC_IND_ADDR_MASK 0x0000001fL +#define MC_IND_INDEX__MC_IND_WR_EN_MASK 0x00000100L +#define MC_IND_INDEX__MC_IND_WR_EN 0x00000100L + +// MC_IND_DATA +#define MC_IND_DATA__MC_IND_DATA_MASK 0xffffffffL + +// MC_CHP_IO_CNTL_A1 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT 0x00000000 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT 0x00000001 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT 0x00000002 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT 0x00000003 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT 0x00000004 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT 0x00000005 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT 0x00000006 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT 0x00000007 +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT 0x00000008 +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT 0x00000009 +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT 0x0000000a +#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT 0x0000000c +#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT 0x0000000e +#define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT 0x00000010 +#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT 0x00000012 +#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT 0x00000014 +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT 0x00000016 +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT 0x00000017 +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT 0x00000018 +#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT 0x0000001a +#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT 0x0000001c +#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT 0x0000001e +#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT 0x0000001f + +// MC_CHP_IO_CNTL_B1 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT 0x00000000 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT 0x00000001 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT 0x00000002 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT 0x00000003 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT 0x00000004 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT 0x00000005 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT 0x00000006 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT 0x00000007 +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT 0x00000008 +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT 0x00000009 +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT 0x0000000a +#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT 0x0000000c +#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT 0x0000000e +#define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT 0x00000010 +#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT 0x00000012 +#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT 0x00000014 +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT 0x00000016 +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT 0x00000017 +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT 0x00000018 +#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT 0x0000001a +#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT 0x0000001c +#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT 0x0000001e +#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT 0x0000001f + +// MC_CHP_IO_CNTL_A1 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK 0x00000001L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA 0x00000001L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK 0x00000002L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA 0x00000002L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK 0x00000004L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA 0x00000004L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK 0x00000008L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA 0x00000008L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK 0x00000010L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA 0x00000010L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK 0x00000020L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA 0x00000020L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK 0x00000040L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA 0x00000040L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK 0x00000080L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA 0x00000080L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK 0x00000100L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA 0x00000100L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK 0x00000200L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA 0x00000200L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK 0x00000400L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA 0x00000400L +#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK 0x00003000L +#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK 0x0000c000L +#define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK 0x00030000L +#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK 0x000c0000L +#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK 0x00300000L +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK 0x00400000L +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA 0x00400000L +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK 0x00800000L +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA 0x00800000L +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK 0x03000000L +#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK 0x0c000000L +#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK 0x10000000L +#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA 0x10000000L +#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK 0x40000000L +#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A 0x40000000L +#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK 0x80000000L +#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A 0x80000000L + +// MC_CHP_IO_CNTL_B1 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK 0x00000001L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB 0x00000001L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK 0x00000002L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB 0x00000002L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK 0x00000004L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB 0x00000004L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK 0x00000008L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB 0x00000008L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK 0x00000010L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB 0x00000010L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK 0x00000020L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB 0x00000020L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK 0x00000040L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB 0x00000040L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK 0x00000080L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB 0x00000080L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK 0x00000100L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB 0x00000100L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK 0x00000200L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB 0x00000200L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK 0x00000400L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB 0x00000400L +#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK 0x00003000L +#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK 0x0000c000L +#define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK 0x00030000L +#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK 0x000c0000L +#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK 0x00300000L +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK 0x00400000L +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB 0x00400000L +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK 0x00800000L +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB 0x00800000L +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK 0x03000000L +#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK 0x0c000000L +#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK 0x10000000L +#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB 0x10000000L +#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK 0x40000000L +#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B 0x40000000L +#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK 0x80000000L +#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B 0x80000000L + +// MEM_SDRAM_MODE_REG +#define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK 0x00007fffL +#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK 0x000f0000L +#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK 0x00700000L +#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK 0x00800000L +#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY 0x00800000L +#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK 0x01000000L +#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY 0x01000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK 0x02000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD 0x02000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK 0x04000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA 0x04000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK 0x08000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR 0x08000000L +#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK 0x10000000L +#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE 0x10000000L +#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK 0x20000000L +#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL 0x20000000L +#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK 0x40000000L +#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE 0x40000000L +#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK 0x80000000L +#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET 0x80000000L + +// MEM_SDRAM_MODE_REG +#define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT 0x00000000 +#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT 0x00000010 +#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT 0x00000014 +#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT 0x00000017 +#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT 0x00000018 +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT 0x00000019 +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT 0x0000001a +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT 0x0000001b +#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT 0x0000001c +#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT 0x0000001d +#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT 0x0000001e +#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT 0x0000001f + +// MEM_REFRESH_CNTL +#define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK 0x000000ffL +#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK 0x00000100L +#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS 0x00000100L +#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK 0x00000200L +#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE 0x00000200L +#define MEM_REFRESH_CNTL__MEM_TRFC_MASK 0x0000f000L +#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK 0x00010000L +#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE 0x00010000L +#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK 0x00020000L +#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE 0x00020000L +#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK 0x00040000L +#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE 0x00040000L +#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK 0x00080000L +#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE 0x00080000L +#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK 0x00100000L +#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE 0x00100000L +#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK 0x00c00000L +#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK 0x01000000L +#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE 0x01000000L +#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK 0x02000000L +#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE 0x02000000L +#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK 0x04000000L +#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE 0x04000000L +#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK 0x08000000L +#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE 0x08000000L +#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK 0x10000000L +#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE 0x10000000L +#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK 0xc0000000L + +// MC_STATUS +#define MC_STATUS__MEM_PWRUP_COMPL_A_MASK 0x00000001L +#define MC_STATUS__MEM_PWRUP_COMPL_A 0x00000001L +#define MC_STATUS__MEM_PWRUP_COMPL_B_MASK 0x00000002L +#define MC_STATUS__MEM_PWRUP_COMPL_B 0x00000002L +#define MC_STATUS__MC_IDLE_MASK 0x00000004L +#define MC_STATUS__MC_IDLE 0x00000004L +#define MC_STATUS__IMP_N_VALUE_R_BACK_MASK 0x00000078L +#define MC_STATUS__IMP_P_VALUE_R_BACK_MASK 0x00000780L +#define MC_STATUS__TEST_OUT_R_BACK_MASK 0x00000800L +#define MC_STATUS__TEST_OUT_R_BACK 0x00000800L +#define MC_STATUS__DUMMY_OUT_R_BACK_MASK 0x00001000L +#define MC_STATUS__DUMMY_OUT_R_BACK 0x00001000L +#define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK 0x0001e000L +#define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK 0x001e0000L +#define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK 0x01e00000L +#define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK 0x1e000000L + +// MDLL_CKO +#define MDLL_CKO__MCKOA_SLEEP_MASK 0x00000001L +#define MDLL_CKO__MCKOA_SLEEP 0x00000001L +#define MDLL_CKO__MCKOA_RESET_MASK 0x00000002L +#define MDLL_CKO__MCKOA_RESET 0x00000002L +#define MDLL_CKO__MCKOA_RANGE_MASK 0x0000000cL +#define MDLL_CKO__ERSTA_SOUTSEL_MASK 0x00000030L +#define MDLL_CKO__MCKOA_FB_SEL_MASK 0x000000c0L +#define MDLL_CKO__MCKOA_REF_SKEW_MASK 0x00000700L +#define MDLL_CKO__MCKOA_FB_SKEW_MASK 0x00007000L +#define MDLL_CKO__MCKOA_BP_SEL_MASK 0x00008000L +#define MDLL_CKO__MCKOA_BP_SEL 0x00008000L +#define MDLL_CKO__MCKOB_SLEEP_MASK 0x00010000L +#define MDLL_CKO__MCKOB_SLEEP 0x00010000L +#define MDLL_CKO__MCKOB_RESET_MASK 0x00020000L +#define MDLL_CKO__MCKOB_RESET 0x00020000L +#define MDLL_CKO__MCKOB_RANGE_MASK 0x000c0000L +#define MDLL_CKO__ERSTB_SOUTSEL_MASK 0x00300000L +#define MDLL_CKO__MCKOB_FB_SEL_MASK 0x00c00000L +#define MDLL_CKO__MCKOB_REF_SKEW_MASK 0x07000000L +#define MDLL_CKO__MCKOB_FB_SKEW_MASK 0x70000000L +#define MDLL_CKO__MCKOB_BP_SEL_MASK 0x80000000L +#define MDLL_CKO__MCKOB_BP_SEL 0x80000000L + +// MDLL_RDCKA +#define MDLL_RDCKA__MRDCKA0_SLEEP_MASK 0x00000001L +#define MDLL_RDCKA__MRDCKA0_SLEEP 0x00000001L +#define MDLL_RDCKA__MRDCKA0_RESET_MASK 0x00000002L +#define MDLL_RDCKA__MRDCKA0_RESET 0x00000002L +#define MDLL_RDCKA__MRDCKA0_RANGE_MASK 0x0000000cL +#define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK 0x00000030L +#define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK 0x000000c0L +#define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK 0x00000700L +#define MDLL_RDCKA__MRDCKA0_SINSEL_MASK 0x00000800L +#define MDLL_RDCKA__MRDCKA0_SINSEL 0x00000800L +#define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK 0x00007000L +#define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK 0x00008000L +#define MDLL_RDCKA__MRDCKA0_BP_SEL 0x00008000L +#define MDLL_RDCKA__MRDCKA1_SLEEP_MASK 0x00010000L +#define MDLL_RDCKA__MRDCKA1_SLEEP 0x00010000L +#define MDLL_RDCKA__MRDCKA1_RESET_MASK 0x00020000L +#define MDLL_RDCKA__MRDCKA1_RESET 0x00020000L +#define MDLL_RDCKA__MRDCKA1_RANGE_MASK 0x000c0000L +#define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK 0x00300000L +#define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK 0x00c00000L +#define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK 0x07000000L +#define MDLL_RDCKA__MRDCKA1_SINSEL_MASK 0x08000000L +#define MDLL_RDCKA__MRDCKA1_SINSEL 0x08000000L +#define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK 0x70000000L +#define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK 0x80000000L +#define MDLL_RDCKA__MRDCKA1_BP_SEL 0x80000000L + +// MDLL_RDCKB +#define MDLL_RDCKB__MRDCKB0_SLEEP_MASK 0x00000001L +#define MDLL_RDCKB__MRDCKB0_SLEEP 0x00000001L +#define MDLL_RDCKB__MRDCKB0_RESET_MASK 0x00000002L +#define MDLL_RDCKB__MRDCKB0_RESET 0x00000002L +#define MDLL_RDCKB__MRDCKB0_RANGE_MASK 0x0000000cL +#define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK 0x00000030L +#define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK 0x000000c0L +#define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK 0x00000700L +#define MDLL_RDCKB__MRDCKB0_SINSEL_MASK 0x00000800L +#define MDLL_RDCKB__MRDCKB0_SINSEL 0x00000800L +#define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK 0x00007000L +#define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK 0x00008000L +#define MDLL_RDCKB__MRDCKB0_BP_SEL 0x00008000L +#define MDLL_RDCKB__MRDCKB1_SLEEP_MASK 0x00010000L +#define MDLL_RDCKB__MRDCKB1_SLEEP 0x00010000L +#define MDLL_RDCKB__MRDCKB1_RESET_MASK 0x00020000L +#define MDLL_RDCKB__MRDCKB1_RESET 0x00020000L +#define MDLL_RDCKB__MRDCKB1_RANGE_MASK 0x000c0000L +#define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK 0x00300000L +#define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK 0x00c00000L +#define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK 0x07000000L +#define MDLL_RDCKB__MRDCKB1_SINSEL_MASK 0x08000000L +#define MDLL_RDCKB__MRDCKB1_SINSEL 0x08000000L +#define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK 0x70000000L +#define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK 0x80000000L +#define MDLL_RDCKB__MRDCKB1_BP_SEL 0x80000000L + +#define pllVCLK_ECP_CNTL 0x0008 +#define pllDISP_TEST_MACRO_RW_WRITE 0x001A +#define pllDISP_TEST_MACRO_RW_READ 0x001B +#define pllDISP_TEST_MACRO_RW_DATA 0x001C +#define pllDISP_TEST_MACRO_RW_CNTL 0x001D +#define pllPIXCLKS_CNTL 0x002D +#define pllPPLL_DIV_0 0x0004 +#define pllPPLL_DIV_1 0x0005 +#define pllPPLL_DIV_2 0x0006 +#define pllPPLL_DIV_3 0x0007 +#define pllHTOTAL_CNTL 0x0009 +#define pllPLL_TEST_CNTL_M6 0x0013 +#define pllP2PLL_DIV_0 0x002C +#define pllHTOTAL2_CNTL 0x002E +#define pllCLK_PIN_CNTL 0x0001 +#define pllPPLL_CNTL 0x0002 +#define pllPPLL_REF_DIV 0x0003 +#define pllSPLL_CNTL 0x000C +#define pllSPLL_AUX_CNTL 0x0024 +#define pllSCLK_CNTL_M6 0x000D +#define pllAGP_PLL_CNTL 0x000B +#define pllTV_PLL_FINE_CNTL 0x0020 +#define pllTV_PLL_CNTL 0x0021 +#define pllTV_PLL_CNTL1 0x0022 +#define pllTV_DTO_INCREMENTS 0x0023 +#define pllP2PLL_CNTL 0x002A +#define pllP2PLL_REF_DIV 0x002B +#define pllSSPLL_CNTL 0x0030 +#define pllSSPLL_REF_DIV 0x0031 +#define pllSSPLL_DIV_0 0x0032 +#define pllSS_INT_CNTL 0x0033 +#define pllSS_TST_CNTL 0x0034 +#define pllSCLK_MORE_CNTL 0x0035 +#define pllCLK_PWRMGT_CNTL_M6 0x0014 +#define pllPLL_PWRMGT_CNTL 0x0015 +#define pllM_SPLL_REF_FB_DIV 0x000A +#define pllMPLL_CNTL 0x000E +#define pllMPLL_AUX_CNTL 0x0025 +#define pllMDLL_CKO 0x000F +#define pllMDLL_RDCKA 0x0010 +#define pllMDLL_RDCKB 0x0011 +#define pllMCLK_CNTL_M6 0x0012 +#define pllMCLK_MISC 0x001F +#define pllCG_TEST_MACRO_RW_WRITE 0x0016 +#define pllCG_TEST_MACRO_RW_READ 0x0017 +#define pllCG_TEST_MACRO_RW_DATA 0x0018 +#define pllCG_TEST_MACRO_RW_CNTL 0x0019 + +#define ixMC_PERF_CNTL 0x0000 +#define ixMC_PERF_SEL 0x0001 +#define ixMC_PERF_REGION_0 0x0002 +#define ixMC_PERF_REGION_1 0x0003 +#define ixMC_PERF_COUNT_0 0x0004 +#define ixMC_PERF_COUNT_1 0x0005 +#define ixMC_PERF_COUNT_2 0x0006 +#define ixMC_PERF_COUNT_3 0x0007 +#define ixMC_PERF_COUNT_MEMCH_A 0x0008 +#define ixMC_PERF_COUNT_MEMCH_B 0x0009 +#define ixMC_IMP_CNTL 0x000A +#define ixMC_CHP_IO_CNTL_A0 0x000B +#define ixMC_CHP_IO_CNTL_A1 0x000C +#define ixMC_CHP_IO_CNTL_B0 0x000D +#define ixMC_CHP_IO_CNTL_B1 0x000E +#define ixMC_IMP_CNTL_0 0x000F +#define ixTC_MISMATCH_1 0x0010 +#define ixTC_MISMATCH_2 0x0011 +#define ixMC_BIST_CTRL 0x0012 +#define ixREG_COLLAR_WRITE 0x0013 +#define ixREG_COLLAR_READ 0x0014 + + + + #endif /* _RADEON_H */ |