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-rw-r--r--include/asm-arm/arch-ebsa110/param.h1
-rw-r--r--include/asm-arm/arch-ebsa110/time.h86
-rw-r--r--include/asm-arm/arch-rpc/hardware.h11
-rw-r--r--include/asm-arm/arch-rpc/io.h5
-rw-r--r--include/asm-arm/arch-sa1100/ide.h24
-rw-r--r--include/asm-arm/arch-sa1100/mftb2.h210
-rw-r--r--include/asm-arm/arch-sa1100/trizeps.h20
-rw-r--r--include/asm-arm/bug.h1
-rw-r--r--include/asm-arm/ecard.h17
-rw-r--r--include/asm-arm/io.h8
-rw-r--r--include/asm-arm/mach/irq.h5
-rw-r--r--include/asm-arm/module.h5
-rw-r--r--include/asm-arm/proc-armv/processor.h6
13 files changed, 381 insertions, 18 deletions
diff --git a/include/asm-arm/arch-ebsa110/param.h b/include/asm-arm/arch-ebsa110/param.h
index f077b717193d..13a9fc1b7a25 100644
--- a/include/asm-arm/arch-ebsa110/param.h
+++ b/include/asm-arm/arch-ebsa110/param.h
@@ -1,3 +1,4 @@
/*
* linux/include/asm-arm/arch-ebsa110/param.h
*/
+#define __KERNEL_HZ 200
diff --git a/include/asm-arm/arch-ebsa110/time.h b/include/asm-arm/arch-ebsa110/time.h
index 278c8e3632a1..30c90e607546 100644
--- a/include/asm-arm/arch-ebsa110/time.h
+++ b/include/asm-arm/arch-ebsa110/time.h
@@ -17,17 +17,80 @@
*/
#include <asm/leds.h>
+#include <asm/io.h>
-extern int ebsa110_reset_timer(void);
-extern void ebsa110_setup_timer(void);
+extern unsigned long (*gettimeoffset)(void);
+
+#define PIT_CTRL (PIT_BASE + 0x0d)
+#define PIT_T2 (PIT_BASE + 0x09)
+#define PIT_T1 (PIT_BASE + 0x05)
+#define PIT_T0 (PIT_BASE + 0x01)
+
+/*
+ * This is the rate at which your MCLK signal toggles (in Hz)
+ * This was measured on a 10 digit frequency counter sampling
+ * over 1 second.
+ */
+#define MCLK 47894000
+
+/*
+ * This is the rate at which the PIT timers get clocked
+ */
+#define CLKBY7 (MCLK / 7)
+
+/*
+ * This is the counter value. We tick at 200Hz on this platform.
+ */
+#define COUNT ((CLKBY7 + (HZ / 2)) / HZ)
+
+/*
+ * Get the time offset from the system PIT. Note that if we have missed an
+ * interrupt, then the PIT counter will roll over (ie, be negative).
+ * This actually works out to be convenient.
+ */
+static unsigned long ebsa110_gettimeoffset(void)
+{
+ unsigned long offset, count;
+
+ __raw_writeb(0x40, PIT_CTRL);
+ count = __raw_readb(PIT_T1);
+ count |= __raw_readb(PIT_T1) << 8;
+
+ /*
+ * If count > COUNT, make the number negative.
+ */
+ if (count > COUNT)
+ count |= 0xffff0000;
+
+ offset = COUNT;
+ offset -= count;
+
+ /*
+ * `offset' is in units of timer counts. Convert
+ * offset to units of microseconds.
+ */
+ offset = offset * (1000000 / HZ) / COUNT;
+
+ return offset;
+}
static void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
- if (ebsa110_reset_timer()) {
- do_leds();
- do_timer(regs);
- do_profile(regs);
- }
+ u32 count;
+
+ /* latch and read timer 1 */
+ __raw_writeb(0x40, PIT_CTRL);
+ count = __raw_readb(PIT_T1);
+ count |= __raw_readb(PIT_T1) << 8;
+
+ count += COUNT;
+
+ __raw_writeb(count & 0xff, PIT_T1);
+ __raw_writeb(count >> 8, PIT_T1);
+
+ do_leds();
+ do_timer(regs);
+ do_profile(regs);
}
/*
@@ -35,7 +98,14 @@ static void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
*/
void __init time_init(void)
{
- ebsa110_setup_timer();
+ /*
+ * Timer 1, mode 2, LSB/MSB
+ */
+ __raw_writeb(0x70, PIT_CTRL);
+ __raw_writeb(COUNT & 0xff, PIT_T1);
+ __raw_writeb(COUNT >> 8, PIT_T1);
+
+ gettimeoffset = ebsa110_gettimeoffset;
timer_irq.handler = timer_interrupt;
diff --git a/include/asm-arm/arch-rpc/hardware.h b/include/asm-arm/arch-rpc/hardware.h
index a25d8394ffc5..9dc5f5d4b912 100644
--- a/include/asm-arm/arch-rpc/hardware.h
+++ b/include/asm-arm/arch-rpc/hardware.h
@@ -63,6 +63,17 @@
#define IO_EC_MEMC8_BASE 0x8000ac00
#define IO_EC_MEMC_BASE 0x80000000
+#define NETSLOT_BASE 0x0302b000
+#define NETSLOT_SIZE 0x00001000
+
+#define PODSLOT_IOC0_BASE 0x03240000
+#define PODSLOT_IOC4_BASE 0x03270000
+#define PODSLOT_IOC_SIZE (1 << 14)
+#define PODSLOT_MEMC_BASE 0x03000000
+#define PODSLOT_MEMC_SIZE (1 << 14)
+#define PODSLOT_EASI_BASE 0x08000000
+#define PODSLOT_EASI_SIZE (1 << 24)
+
#define EXPMASK_STATUS (EXPMASK_BASE + 0x00)
#define EXPMASK_ENABLE (EXPMASK_BASE + 0x04)
diff --git a/include/asm-arm/arch-rpc/io.h b/include/asm-arm/arch-rpc/io.h
index 3a1c18ad63bb..3f7a2366cad3 100644
--- a/include/asm-arm/arch-rpc/io.h
+++ b/include/asm-arm/arch-rpc/io.h
@@ -247,4 +247,9 @@ DECLARE_IO(int,l,"")
#define outsb(p,d,l) __raw_writesb(__ioaddr(p),d,l)
#define outsw(p,d,l) __raw_writesw(__ioaddr(p),d,l)
+/*
+ * 1:1 mapping for ioremapped regions.
+ */
+#define __mem_pci(x) (x)
+
#endif
diff --git a/include/asm-arm/arch-sa1100/ide.h b/include/asm-arm/arch-sa1100/ide.h
index a5f392d1dd8d..9c8e1c7644aa 100644
--- a/include/asm-arm/arch-sa1100/ide.h
+++ b/include/asm-arm/arch-sa1100/ide.h
@@ -49,8 +49,9 @@ ide_init_hwif_ports(hw_regs_t *hw, int data_port, int ctrl_port, int *irq)
*irq = 0;
}
-
-
+#ifdef CONFIG_SA1100_TRIZEPS
+#include <asm/arch/trizeps.h>
+#endif
/*
* This registers the standard ports for this architecture with the IDE
@@ -124,6 +125,23 @@ ide_init_default_hwifs(void)
ide_register_hw(&hw);
#endif
}
-}
+ else if( machine_is_trizeps() ){
+#ifdef CONFIG_SA1100_TRIZEPS
+ hw_regs_t hw;
+ /* Enable appropriate GPIOs as interrupt lines */
+ GPDR &= ~GPIO_GPIO(TRIZEPS_IRQ_IDE);
+ set_irq_type( TRIZEPS_IRQ_IDE, IRQT_RISING );
+ /* set the pcmcia interface timing */
+ //MECR = 0x00060006; // Done on trizeps init
+
+ /* Take hard drives out of reset */
+ GPSR = GPIO_GPIO(TRIZEPS_IRQ_IDE);
+
+ ide_init_hwif_ports(&hw, TRIZEPS_IDE_CS0 + 0, TRIZEPS_IDE_CS1 + 6, NULL);
+ hw.irq = TRIZEPS_IRQ_IDE;
+ ide_register_hw(&hw, NULL);
+#endif
+ }
+}
diff --git a/include/asm-arm/arch-sa1100/mftb2.h b/include/asm-arm/arch-sa1100/mftb2.h
new file mode 100644
index 000000000000..1d4c9f7dcdf0
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/mftb2.h
@@ -0,0 +1,210 @@
+#ifndef _ARCH_ARM_MFTB2_h_
+#define _ARCH_ARM_MFTB2_h_
+
+// Defines for arch/arm/mm/mm-sa1100.h
+#define TRIZEPS_PHYS_VIRT_MAP_SIZE 0x00800000l
+
+// physical address (only for mm-sa1100.h)
+#define TRIZEPS_PHYS_IO_BASE 0x30000000l
+#define TRIZEPS_PHYS_MEM_BASE 0x38000000l
+
+// virtual
+#define TRIZEPS_IO_BASE 0xF0000000l
+#define TRIZEPS_MEM_BASE 0xF2000000l
+
+// Offsets for phys and virtual
+#define TRIZEPS_OFFSET_REG0 0x00300000l
+#define TRIZEPS_OFFSET_REG1 0x00380000l
+#define TRIZEPS_OFFSET_IDE_CS0 0x00000000l
+#define TRIZEPS_OFFSET_IDE_CS1 0x00080000l
+#define TRIZEPS_OFFSET_UART5 0x00100000l
+#define TRIZEPS_OFFSET_UART6 0x00180000l
+#define TRIZEPS_PHYS_REG0 (TRIZEPS_PHYS_IO_BASE + TRIZEPS_OFFSET_REG0)
+#define TRIZEPS_PHYS_REG1 (TRIZEPS_PHYS_IO_BASE + TRIZEPS_OFFSET_REG1)
+#define TRIZEPS_PHYS_IDE_CS0 (TRIZEPS_PHYS_IO_BASE + TRIZEPS_OFFSET_IDE_CS0)
+#define TRIZEPS_PHYS_IDE_CS1 (TRIZEPS_PHYS_IO_BASE + TRIZEPS_OFFSET_IDE_CS1)
+#define TRIZEPS_PHYS_UART5 (TRIZEPS_PHYS_IO_BASE + TRIZEPS_OFFSET_UART5)
+#define TRIZEPS_PHYS_UART6 (TRIZEPS_PHYS_IO_BASE + TRIZEPS_OFFSET_UART6)
+
+// Use follow defines in devices
+// virtual address
+#define TRIZEPS_REG0 (TRIZEPS_IO_BASE + TRIZEPS_OFFSET_REG0)
+#define TRIZEPS_REG1 (TRIZEPS_IO_BASE + TRIZEPS_OFFSET_REG1)
+#define TRIZEPS_IDE_CS0 (TRIZEPS_IO_BASE + TRIZEPS_OFFSET_IDE_CS0)
+#define TRIZEPS_IDE_CS1 (TRIZEPS_IO_BASE + TRIZEPS_OFFSET_IDE_CS1)
+#define TRIZEPS_UART5 (TRIZEPS_IO_BASE + TRIZEPS_OFFSET_UART5)
+#define TRIZEPS_UART6 (TRIZEPS_IO_BASE + TRIZEPS_OFFSET_UART6)
+
+#define TRIZEPS_BAUD_BASE 1500000
+
+//#if 0 //temporarily disabled
+#ifndef __ASSEMBLY__
+struct tri_uart_cts_data_t {
+ int cts_gpio;
+ int cts_prev_state;
+ struct uart_info *info;
+ struct uart_port *port;
+ const char *name;
+};
+#endif /* __ASSEMBLY__ */
+
+/* Defines for MFTB2 serial_sa1100.c hardware handshaking lines */
+#define SERIAL_FULL
+#define NOT_CONNECTED 0
+#ifdef SERIAL_FULL
+#define TRIZEPS_GPIO_UART1_RTS GPIO_GPIO14
+#define TRIZEPS_GPIO_UART1_DTR NOT_CONNECTED //GPIO_GPIO9
+#define TRIZEPS_GPIO_UART1_CTS GPIO_GPIO15
+#define TRIZEPS_GPIO_UART1_DCD NOT_CONNECTED //GPIO_GPIO2
+#define TRIZEPS_GPIO_UART1_DSR NOT_CONNECTED //GPIO_GPIO3
+#define TRIZEPS_GPIO_UART3_RTS NOT_CONNECTED //GPIO_GPIO7
+#define TRIZEPS_GPIO_UART3_DTR NOT_CONNECTED //GPIO_GPIO8
+#define TRIZEPS_GPIO_UART3_CTS NOT_CONNECTED //GPIO_GPIO4
+#define TRIZEPS_GPIO_UART3_DCD NOT_CONNECTED //GPIO_GPIO5
+#define TRIZEPS_GPIO_UART3_DSR NOT_CONNECTED //GPIO_GPIO6
+
+#define TRIZEPS_GPIO_UART2_RTS NOT_CONNECTED //GPIO_GPIO7
+#define TRIZEPS_GPIO_UART2_DTR NOT_CONNECTED //GPIO_GPIO8
+#define TRIZEPS_GPIO_UART2_CTS NOT_CONNECTED //GPIO_GPIO4
+#define TRIZEPS_GPIO_UART2_DCD NOT_CONNECTED //GPIO_GPIO5
+#define TRIZEPS_GPIO_UART2_DSR NOT_CONNECTED //GPIO_GPIO6
+
+#define TRIZEPS_IRQ_UART1_CTS IRQ_GPIO15
+#define TRIZEPS_IRQ_UART1_DCD NO_IRQ //IRQ_GPIO2
+#define TRIZEPS_IRQ_UART1_DSR NO_IRQ //IRQ_GPIO3
+#define TRIZEPS_IRQ_UART3_CTS NO_IRQ //IRQ_GPIO4
+#define TRIZEPS_IRQ_UART3_DCD NO_IRQ //IRQ_GPIO5
+#define TRIZEPS_IRQ_UART3_DSR NO_IRQ //IRQ_GPIO6
+
+#define TRIZEPS_IRQ_UART2_CTS NO_IRQ //IRQ_GPIO4
+#define TRIZEPS_IRQ_UART2_DCD NO_IRQ //IRQ_GPIO5
+#define TRIZEPS_IRQ_UART2_DSR NO_IRQ //IRQ_GPIO6
+
+#endif /* SERIAL_FULL */
+//#endif //0
+
+/*
+ * This section contains the defines for the MFTB2 implementation
+ * of drivers/ide/hd.c. HD_IOBASE_0 and HD_IOBASE_1 have to be
+ * adjusted if hardware changes.
+ */
+#define TRIZEPS_IRQ_IDE 10 /* MFTB2 specific */
+
+/*--- ROOT ---*/
+#define TRIZEPS_GPIO_ROOT_NFS 0
+#define TRIZEPS_GPIO_ROOT_HD 21
+/*--- PCMCIA ---*/
+#define TRIZEPS_GPIO_PCMCIA_IRQ0 1
+#define TRIZEPS_GPIO_PCMCIA_CD0 24
+#define TRIZEPS_IRQ_PCMCIA_IRQ0 TRIZEPS_GPIO_PCMCIA_IRQ0
+#define TRIZEPS_IRQ_PCMCIA_CD0 TRIZEPS_GPIO_PCMCIA_CD0 + 32 - 11
+
+// REGISTER 0 -> 0x0XXXX (16bit access)
+// read only
+#define TRIZEPS_A_STAT 0x8000l
+#define TRIZEPS_F_STAT 0x4000l
+#define TRIZEPS_BATT_FAULT_EN 0x2000l
+#define TRIZEPS_nDQ 0x1000l
+#define TRIZEPS_MFT_OFF 0x0800l
+#define TRIZEPS_D_APWOFF 0x0400l
+#define TRIZEPS_F_CTRL 0x0200l
+#define TRIZEPS_F_STOP 0x0100l
+
+// read / write
+#define TRIZEPS_KP_IR_EN 0x0080l
+#define TRIZEPS_FIR 0x0040l
+#define TRIZEPS_BAR_ON 0x0020l
+#define TRIZEPS_VCI_ON 0x0010l
+#define TRIZEPS_LED4 0x0008l
+#define TRIZEPS_LED3 0x0004l
+#define TRIZEPS_LED2 0x0002l
+#define TRIZEPS_LED1 0x0001l
+
+// REGISTER 1 -> 0x1XXXX (16bit access)
+// read only
+#define TRIZEPS_nVCI2 0x8000l
+#define TRIZEPS_nAB_LOW 0x4000l
+#define TRIZEPS_nMB_DEAD 0x2000l
+#define TRIZEPS_nMB_LOW 0x1000l
+#define TRIZEPS_nPCM_VS2 0x0800l
+#define TRIZEPS_nPCM_VS1 0x0400l
+#define TRIZEPS_PCM_BVD2 0x0200l
+#define TRIZEPS_PCM_BVD1 0x0100l
+
+// read / write
+#define TRIZEPS_nROOT_NFS 0x0080l
+#define TRIZEPS_nROOT_HD 0x0040l
+#define TRIZEPS_nPCM_ENA_REG 0x0020l
+#define TRIZEPS_nPCM_RESET_DISABLE 0x0010l
+#define TRIZEPS_PCM_EN0_REG 0x0008l
+#define TRIZEPS_PCM_EN1_REG 0x0004l
+#define TRIZEPS_PCM_V3_EN_REG 0x0002l
+#define TRIZEPS_PCM_V5_EN_REG 0x0001l
+
+/* Access to Board Control Register */
+#define TRIZEPS_BCR0 (*(volatile unsigned short *)(TRIZEPS_REG0))
+#define TRIZEPS_BCR1 (*(volatile unsigned short *)(TRIZEPS_REG1))
+
+#define TRIZEPS_BCR_set( reg, x ) do { \
+ unsigned long flags; \
+ local_irq_save(flags); \
+ (reg) |= (x); \
+ local_irq_restore(flags); \
+} while (0)
+
+#define TRIZEPS_BCR_clear( reg, x ) do { \
+ unsigned long flags; \
+ local_irq_save(flags); \
+ (reg) &= ~(x); \
+ local_irq_restore(flags); \
+} while (0)
+
+#define TRIZEPS_OFFSET_KP_REG 0x00200000l
+#define TRIZEPS_OFFSET_VCI2 0x00280000l
+#define TRIZEPS_OFFSET_VCI4 0x00400000l
+
+#define TRIZEPS_OFFSET_VCI2_1_DPR (TRIZEPS_OFFSET_VCI2 + 0x00010000l)
+#define TRIZEPS_OFFSET_VCI2_2_DPR (TRIZEPS_OFFSET_VCI2 + 0x00018000l)
+#define TRIZEPS_OFFSET_VCI2_1_SEMA (TRIZEPS_OFFSET_VCI2 + 0x00020000l)
+#define TRIZEPS_OFFSET_VCI2_2_SEMA (TRIZEPS_OFFSET_VCI2 + 0x00028000l)
+
+#define TRIZEPS_OFFSET_VCI4_1_DPR (TRIZEPS_OFFSET_VCI4 + 0x00000000l)
+#define TRIZEPS_OFFSET_VCI4_2_DPR (TRIZEPS_OFFSET_VCI4 + 0x00008000l)
+#define TRIZEPS_OFFSET_VCI4_1_SEMA (TRIZEPS_OFFSET_VCI4 + 0x00000380l)
+#define TRIZEPS_OFFSET_VCI4_2_SEMA (TRIZEPS_OFFSET_VCI4 + 0x00000388l)
+#define TRIZEPS_OFFSET_VCI4_1_CNTR (TRIZEPS_OFFSET_VCI4 + 0x00000390l)
+#define TRIZEPS_OFFSET_VCI4_2_CNTR (TRIZEPS_OFFSET_VCI4 + 0x00000392l)
+
+#define TRIZEPS_PHYS_KP_REG (PHYS_TRIZEPS_IO_BASE + TRIZEPS_OFFSET_KP_REG)
+
+// VCI address
+#define TRIZEPS_PHYS_VCI2_1_DPR (TRIZEPS_PHYS_MEM_BASE + TRIZEPS_OFFSET_VCI2_1_DPR)
+#define TRIZEPS_PHYS_VCI2_2_DPR (TRIZEPS_PHYS_MEM_BASE + TRIZEPS_OFFSET_VCI2_2_DPR)
+#define TRIZEPS_PHYS_VCI2_1_SEMA (TRIZEPS_PHYS_MEM_BASE + TRIZEPS_OFFSET_VCI2_1_SEMA)
+#define TRIZEPS_PHYS_VCI2_2_SEMA (TRIZEPS_PHYS_MEM_BASE + TRIZEPS_OFFSET_VCI2_2_SEMA)
+
+// VCI4 address
+#define TRIZEPS_PHYS_VCI4_1_DPR (TRIZEPS_PHYS_MEM_BASE + TRIZEPS_OFFSET_VCI4_1_DPR)
+#define TRIZEPS_PHYS_VCI4_2_DPR (TRIZEPS_PHYS_MEM_BASE + TRIZEPS_OFFSET_VCI4_2_DPR)
+#define TRIZEPS_PHYS_VCI4_1_SEMA (TRIZEPS_PHYS_IO_BASE + TRIZEPS_OFFSET_VCI4_1_SEMA)
+#define TRIZEPS_PHYS_VCI4_2_SEMA (TRIZEPS_PHYS_IO_BASE + TRIZEPS_OFFSET_VCI4_2_SEMA)
+#define TRIZEPS_PHYS_VCI4_1_CNTR (TRIZEPS_PHYS_IO_BASE + TRIZEPS_OFFSET_VCI4_1_CNTR)
+#define TRIZEPS_PHYS_VCI4_2_CNTR (TRIZEPS_PHYS_IO_BASE + TRIZEPS_OFFSET_VCI4_2_CNTR)
+
+#define TRIZEPS_KP_REG (TRIZEPS_IO_BASE + TRIZEPS_OFFSET_KP_REG)
+
+// VCI address
+#define TRIZEPS_VCI2_1_DPR (TRIZEPS_MEM_BASE + TRIZEPS_OFFSET_VCI2_1_DPR)
+#define TRIZEPS_VCI2_2_DPR (TRIZEPS_MEM_BASE + TRIZEPS_OFFSET_VCI2_2_DPR)
+#define TRIZEPS_VCI2_1_SEMA (TRIZEPS_MEM_BASE + TRIZEPS_OFFSET_VCI2_1_SEMA)
+#define TRIZEPS_VCI2_2_SEMA (TRIZEPS_MEM_BASE + TRIZEPS_OFFSET_VCI2_2_SEMA)
+
+// VCI4 address
+#define TRIZEPS_VCI4_1_DPR (TRIZEPS_MEM_BASE + TRIZEPS_OFFSET_VCI4_1_DPR)
+#define TRIZEPS_VCI4_2_DPR (TRIZEPS_MEM_BASE + TRIZEPS_OFFSET_VCI4_2_DPR)
+#define TRIZEPS_VCI4_1_SEMA (TRIZEPS_IO_BASE + TRIZEPS_OFFSET_VCI4_1_SEMA)
+#define TRIZEPS_VCI4_2_SEMA (TRIZEPS_IO_BASE + TRIZEPS_OFFSET_VCI4_2_SEMA)
+#define TRIZEPS_VCI4_1_CNTR (TRIZEPS_IO_BASE + TRIZEPS_OFFSET_VCI4_1_CNTR)
+#define TRIZEPS_VCI4_2_CNTR (TRIZEPS_IO_BASE + TRIZEPS_OFFSET_VCI4_2_CNTR)
+
+#endif
diff --git a/include/asm-arm/arch-sa1100/trizeps.h b/include/asm-arm/arch-sa1100/trizeps.h
new file mode 100644
index 000000000000..b9cc02bac5d9
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/trizeps.h
@@ -0,0 +1,20 @@
+/*
+ * linux/include/asm-arm/arch-sa1100/trizeps.h
+ *
+ * This file contains the hardware specific definitions for Trizeps
+ *
+ * Authors:
+ * Andreas Hofer <ho@dsa-ac.de>,
+ * Peter Lueg <pl@dsa-ac.de>,
+ * Guennadi Liakhovetski <gl@dsa-ac.de>
+ *
+ */
+
+#ifndef _ASM_ARCH_TRIZEPS_H_
+#define _ASM_ARCH_TRIZEPS_H_
+
+#ifdef CONFIG_TRIZEPS_MFTB2
+#include "mftb2.h"
+#endif
+
+#endif // _INCLUDE_TRIZEPS_
diff --git a/include/asm-arm/bug.h b/include/asm-arm/bug.h
index c9b6e7f6b317..326400b2b83f 100644
--- a/include/asm-arm/bug.h
+++ b/include/asm-arm/bug.h
@@ -18,3 +18,4 @@ extern volatile void __bug(const char *file, int line, void *data);
#endif
+#endif
diff --git a/include/asm-arm/ecard.h b/include/asm-arm/ecard.h
index 602dc63b9dfa..89c1d1db4b7b 100644
--- a/include/asm-arm/ecard.h
+++ b/include/asm-arm/ecard.h
@@ -130,6 +130,20 @@ typedef struct { /* Card handler routines */
int (*fiqpending)(ecard_t *ec);
} expansioncard_ops_t;
+#define ECARD_NUM_RESOURCES (6)
+
+#define ECARD_RES_IOCSLOW (0)
+#define ECARD_RES_IOCMEDIUM (1)
+#define ECARD_RES_IOCFAST (2)
+#define ECARD_RES_IOCSYNC (3)
+#define ECARD_RES_MEMC (4)
+#define ECARD_RES_EASI (5)
+
+#define ecard_resource_start(ec,nr) ((ec)->resource[nr].start)
+#define ecard_resource_end(ec,nr) ((ec)->resource[nr].end)
+#define ecard_resource_len(ec,nr) ((ec)->resource[nr].end - \
+ (ec)->resource[nr].start + 1)
+
/*
* This contains all the info needed on an expansion card
*/
@@ -137,6 +151,7 @@ struct expansion_card {
struct expansion_card *next;
struct device dev;
+ struct resource resource[ECARD_NUM_RESOURCES];
/* Public data */
volatile unsigned char *irqaddr; /* address of IRQ register */
@@ -147,7 +162,7 @@ struct expansion_card {
void *irq_data; /* Data for use for IRQ by card */
void *fiq_data; /* Data for use for FIQ by card */
- expansioncard_ops_t *ops; /* Enable/Disable Ops for card */
+ const expansioncard_ops_t *ops; /* Enable/Disable Ops for card */
CONST unsigned int slot_no; /* Slot number */
CONST unsigned int dma; /* DMA number (for request_dma) */
diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h
index 1dc1dd5d611a..8bb0d5e1cc9a 100644
--- a/include/asm-arm/io.h
+++ b/include/asm-arm/io.h
@@ -150,10 +150,18 @@ extern void _memset_io(unsigned long, int, size_t);
#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
+#define readsb(p,d,l) __raw_readsb((unsigned int)__mem_pci(p),d,l)
+#define readsw(p,d,l) __raw_readsw((unsigned int)__mem_pci(p),d,l)
+#define readsl(p,d,l) __raw_readsl((unsigned int)__mem_pci(p),d,l)
+
#define writeb(v,c) __raw_writeb(v,__mem_pci(c))
#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c))
#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c))
+#define writesb(p,d,l) __raw_writesb((unsigned int)__mem_pci(p),d,l)
+#define writesw(p,d,l) __raw_writesw((unsigned int)__mem_pci(p),d,l)
+#define writesl(p,d,l) __raw_writesl((unsigned int)__mem_pci(p),d,l)
+
#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l))
#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l))
#define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l))
diff --git a/include/asm-arm/mach/irq.h b/include/asm-arm/mach/irq.h
index 60ce4643c027..5a3007b97324 100644
--- a/include/asm-arm/mach/irq.h
+++ b/include/asm-arm/mach/irq.h
@@ -50,8 +50,8 @@ struct irqdesc {
irq_handler_t handle;
struct irqchip *chip;
struct irqaction *action;
+ unsigned int disable_depth;
- unsigned int enabled : 1; /* IRQ is currently enabled */
unsigned int triggered: 1; /* IRQ has occurred */
unsigned int running : 1; /* IRQ is running */
unsigned int pending : 1; /* IRQ is pending */
@@ -59,8 +59,7 @@ struct irqdesc {
unsigned int probe_ok : 1; /* IRQ can be used for probe */
unsigned int valid : 1; /* IRQ claimable */
unsigned int noautoenable : 1; /* don't automatically enable IRQ */
- unsigned int unused :23;
- unsigned int depth; /* disable depth */
+ unsigned int unused :25;
/*
* IRQ lock detection
diff --git a/include/asm-arm/module.h b/include/asm-arm/module.h
index 5b4d1a3f3679..24b168dc31a3 100644
--- a/include/asm-arm/module.h
+++ b/include/asm-arm/module.h
@@ -10,4 +10,9 @@ struct mod_arch_specific
#define Elf_Sym Elf32_Sym
#define Elf_Ehdr Elf32_Ehdr
+/*
+ * Include the ARM architecture version.
+ */
+#define MODULE_ARCH_VERMAGIC "ARMv" __stringify(__LINUX_ARM_ARCH__) " "
+
#endif /* _ASM_ARM_MODULE_H */
diff --git a/include/asm-arm/proc-armv/processor.h b/include/asm-arm/proc-armv/processor.h
index 853f411083db..390e887d2037 100644
--- a/include/asm-arm/proc-armv/processor.h
+++ b/include/asm-arm/proc-armv/processor.h
@@ -23,7 +23,7 @@
#define KERNEL_STACK_SIZE PAGE_SIZE
#define INIT_EXTRA_THREAD_INFO \
- cpu_domain: domain_val(DOMAIN_USER, DOMAIN_CLIENT) | \
+ .cpu_domain = domain_val(DOMAIN_USER, DOMAIN_CLIENT) | \
domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
domain_val(DOMAIN_IO, DOMAIN_CLIENT)
@@ -45,7 +45,7 @@
regs->ARM_r0 = stack[0]; /* r0 (argc) */ \
})
-#define KSTK_EIP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1019])
-#define KSTK_ESP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1017])
+#define KSTK_EIP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)->thread_info))[1019])
+#define KSTK_ESP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)->thread_info))[1017])
#endif
generated by cgit v1.2.3 (git 2.46.0) at 2026-01-28 20:06:36 +0000