diff options
Diffstat (limited to 'include')
116 files changed, 783 insertions, 13267 deletions
diff --git a/include/asm-alpha/processor.h b/include/asm-alpha/processor.h index 830d6f73bea1..fe03e7309686 100644 --- a/include/asm-alpha/processor.h +++ b/include/asm-alpha/processor.h @@ -29,7 +29,6 @@ /* * Bus types */ -#define EISA_bus 1 #define MCA_bus 0 #define MCA_bus__is_a_macro /* for versions in ksyms.c */ diff --git a/include/asm-alpha/signal.h b/include/asm-alpha/signal.h index 27282f335de4..e24248f01340 100644 --- a/include/asm-alpha/signal.h +++ b/include/asm-alpha/signal.h @@ -71,7 +71,7 @@ typedef unsigned long sigset_t; /* These should not be considered constants from userland. */ #define SIGRTMIN 32 -#define SIGRTMAX (_NSIG-1) +#define SIGRTMAX _NSIG /* * SA_FLAGS values: diff --git a/include/asm-arm/arch-iop3xx/iop321-irqs.h b/include/asm-arm/arch-iop3xx/iop321-irqs.h index 6e757b819105..9d5518da56fc 100644 --- a/include/asm-arm/arch-iop3xx/iop321-irqs.h +++ b/include/asm-arm/arch-iop3xx/iop321-irqs.h @@ -10,6 +10,7 @@ * */ +#include <linux/config.h> /* * IOP80321 chipset interrupts diff --git a/include/asm-arm/arch-iop3xx/irqs.h b/include/asm-arm/arch-iop3xx/irqs.h index 7468fab71d94..1df33024c8ea 100644 --- a/include/asm-arm/arch-iop3xx/irqs.h +++ b/include/asm-arm/arch-iop3xx/irqs.h @@ -10,6 +10,8 @@ * */ +#include <linux/config.h> + /* * Whic iop3xx implementation is this? */ diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h index 9faf4e77b305..638bd35d7964 100644 --- a/include/asm-arm/arch-pxa/hardware.h +++ b/include/asm-arm/arch-pxa/hardware.h @@ -13,7 +13,6 @@ #ifndef __ASM_ARCH_HARDWARE_H #define __ASM_ARCH_HARDWARE_H -#include <linux/config.h> #include <asm/mach-types.h> diff --git a/include/asm-arm/arch-pxa/ide.h b/include/asm-arm/arch-pxa/ide.h index 926797e14a06..71a2e11b0206 100644 --- a/include/asm-arm/arch-pxa/ide.h +++ b/include/asm-arm/arch-pxa/ide.h @@ -14,7 +14,6 @@ * */ -#include <linux/config.h> #include <asm/irq.h> #include <asm/hardware.h> #include <asm/mach-types.h> diff --git a/include/asm-arm/arch-pxa/idp.h b/include/asm-arm/arch-pxa/idp.h index 63932060242e..e496ed7f496a 100644 --- a/include/asm-arm/arch-pxa/idp.h +++ b/include/asm-arm/arch-pxa/idp.h @@ -12,6 +12,7 @@ * */ +#include <linux/config.h> /* * Note: this file must be safe to include in assembly files diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h index 6d452434eabc..ba16af5ee41a 100644 --- a/include/asm-arm/arch-pxa/irqs.h +++ b/include/asm-arm/arch-pxa/irqs.h @@ -10,6 +10,8 @@ * published by the Free Software Foundation. */ +#include <linux/config.h> + #define PXA_IRQ_SKIP 7 /* The first 7 IRQs are not yet used */ #define PXA_IRQ(x) ((x) - PXA_IRQ_SKIP) diff --git a/include/asm-arm/arch-pxa/keyboard.h b/include/asm-arm/arch-pxa/keyboard.h index 8cd10f1aa231..7bec3179b189 100644 --- a/include/asm-arm/arch-pxa/keyboard.h +++ b/include/asm-arm/arch-pxa/keyboard.h @@ -7,7 +7,6 @@ #ifndef _PXA_KEYBOARD_H #define _PXA_KEYBOARD_H -#include <linux/config.h> #include <asm/mach-types.h> #include <asm/hardware.h> diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index 1823479b1057..15b8ddd50065 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -10,6 +10,7 @@ * published by the Free Software Foundation. */ +#include <linux/config.h> // FIXME hack so that SA-1111.h will work [cb] diff --git a/include/asm-arm/arch-sa1100/serial.h b/include/asm-arm/arch-sa1100/serial.h index 74ebcd5c669c..a6a2267a2dfa 100644 --- a/include/asm-arm/arch-sa1100/serial.h +++ b/include/asm-arm/arch-sa1100/serial.h @@ -7,6 +7,8 @@ * This is included by serial.c -- serial_sa1100.c makes no use of it. */ +#include <linux/config.h> + /* Standard COM flags */ #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) diff --git a/include/asm-arm/arch-sa1100/trizeps.h b/include/asm-arm/arch-sa1100/trizeps.h index b9cc02bac5d9..1802947011be 100644 --- a/include/asm-arm/arch-sa1100/trizeps.h +++ b/include/asm-arm/arch-sa1100/trizeps.h @@ -13,6 +13,8 @@ #ifndef _ASM_ARCH_TRIZEPS_H_ #define _ASM_ARCH_TRIZEPS_H_ +#include <linux/config.h> + #ifdef CONFIG_TRIZEPS_MFTB2 #include "mftb2.h" #endif diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h index 30a47cba4d4b..cff6d6f05913 100644 --- a/include/asm-arm/cacheflush.h +++ b/include/asm-arm/cacheflush.h @@ -10,6 +10,7 @@ #ifndef _ASMARM_CACHEFLUSH_H #define _ASMARM_CACHEFLUSH_H +#include <linux/config.h> #include <linux/sched.h> #include <linux/mm.h> diff --git a/include/asm-arm/glue.h b/include/asm-arm/glue.h index 932f523d92dd..d211a21213ce 100644 --- a/include/asm-arm/glue.h +++ b/include/asm-arm/glue.h @@ -90,7 +90,7 @@ # endif #endif -#ifdef CONFIG_CPU_ABORT_EV5T +#ifdef CONFIG_CPU_ABRT_EV5T # ifdef CPU_ABORT_HANDLER # define MULTI_ABORT 1 # else diff --git a/include/asm-arm/mmu.h b/include/asm-arm/mmu.h index c33797d6cc7b..a457cb71984f 100644 --- a/include/asm-arm/mmu.h +++ b/include/asm-arm/mmu.h @@ -1,8 +1,6 @@ #ifndef __ARM_MMU_H #define __ARM_MMU_H -#include <linux/config.h> - typedef struct { #if __LINUX_ARM_ARCH__ >= 6 unsigned int id; diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h index 5b23a0a59778..9a09fb19258b 100644 --- a/include/asm-arm/pgtable.h +++ b/include/asm-arm/pgtable.h @@ -10,7 +10,6 @@ #ifndef _ASMARM_PGTABLE_H #define _ASMARM_PGTABLE_H -#include <linux/config.h> #include <asm/memory.h> #include <asm/proc-fns.h> #include <asm/arch/vmalloc.h> diff --git a/include/asm-arm/processor.h b/include/asm-arm/processor.h index 31c888ba601c..3890d6038355 100644 --- a/include/asm-arm/processor.h +++ b/include/asm-arm/processor.h @@ -19,7 +19,6 @@ #ifdef __KERNEL__ -#define EISA_bus 0 #define MCA_bus 0 #define MCA_bus__is_a_macro diff --git a/include/asm-arm/signal.h b/include/asm-arm/signal.h index eb59aa539b9c..6d623e24c0fb 100644 --- a/include/asm-arm/signal.h +++ b/include/asm-arm/signal.h @@ -68,7 +68,7 @@ typedef unsigned long sigset_t; /* These should not be considered constants from userland. */ #define SIGRTMIN 32 -#define SIGRTMAX (_NSIG-1) +#define SIGRTMAX _NSIG #define SIGSWI 32 diff --git a/include/asm-arm26/processor.h b/include/asm-arm26/processor.h index 8f9f6ad53474..9e0d90433795 100644 --- a/include/asm-arm26/processor.h +++ b/include/asm-arm26/processor.h @@ -20,7 +20,6 @@ #ifdef __KERNEL__ -#define EISA_bus 0 #define MCA_bus 0 #define MCA_bus__is_a_macro diff --git a/include/asm-arm26/signal.h b/include/asm-arm26/signal.h index e166988dbd5c..6f62e51a2e5a 100644 --- a/include/asm-arm26/signal.h +++ b/include/asm-arm26/signal.h @@ -68,7 +68,7 @@ typedef unsigned long sigset_t; /* These should not be considered constants from userland. */ #define SIGRTMIN 32 -#define SIGRTMAX (_NSIG-1) +#define SIGRTMAX _NSIG #define SIGSWI 32 diff --git a/include/asm-cris/signal.h b/include/asm-cris/signal.h index 1335bf27d8e2..3f187ec4800a 100644 --- a/include/asm-cris/signal.h +++ b/include/asm-cris/signal.h @@ -68,7 +68,7 @@ typedef unsigned long sigset_t; /* These should not be considered constants from userland. */ #define SIGRTMIN 32 -#define SIGRTMAX (_NSIG-1) +#define SIGRTMAX _NSIG /* * SA_FLAGS values: diff --git a/include/asm-generic/cpumask_arith.h b/include/asm-generic/cpumask_arith.h index bd8712d38fee..c19a0a6e45f0 100644 --- a/include/asm-generic/cpumask_arith.h +++ b/include/asm-generic/cpumask_arith.h @@ -27,7 +27,12 @@ #define cpus_shift_right(dst, src, n) do { dst = (src) >> (n); } while (0) #define cpus_shift_left(dst, src, n) do { dst = (src) << (n); } while (0) -#define any_online_cpu(map) ({ (map) ? first_cpu(map) : NR_CPUS; }) +#define any_online_cpu(map) \ +({ \ + cpumask_t __tmp__; \ + cpus_and(__tmp__, map, cpu_online_map); \ + __tmp__ ? first_cpu(__tmp__) : NR_CPUS; \ +}) #define CPU_MASK_ALL (~((cpumask_t)0) >> (8*sizeof(cpumask_t) - NR_CPUS)) #define CPU_MASK_NONE ((cpumask_t)0) diff --git a/include/asm-generic/cpumask_array.h b/include/asm-generic/cpumask_array.h index 991a04bf7062..60c955d823b7 100644 --- a/include/asm-generic/cpumask_array.h +++ b/include/asm-generic/cpumask_array.h @@ -36,7 +36,13 @@ cpu_set(cpu, __cpu_mask); \ __cpu_mask; \ }) -#define any_online_cpu(map) find_first_bit((map).mask, NR_CPUS) +#define any_online_cpu(map) \ +({ \ + cpumask_t __tmp__; \ + cpus_and(__tmp__, map, cpu_online_map); \ + find_first_bit(__tmp__.mask, NR_CPUS); \ +}) + /* * um, these need to be usable as static initializers diff --git a/include/asm-h8300/processor.h b/include/asm-h8300/processor.h index 819c9b34e152..a0bc63dd8b2b 100644 --- a/include/asm-h8300/processor.h +++ b/include/asm-h8300/processor.h @@ -48,7 +48,6 @@ extern inline void wrusp(unsigned long usp) { /* * Bus types */ -#define EISA_bus 0 #define MCA_bus 0 struct thread_struct { diff --git a/include/asm-h8300/signal.h b/include/asm-h8300/signal.h index 460d8a6f69f4..6612725c2297 100644 --- a/include/asm-h8300/signal.h +++ b/include/asm-h8300/signal.h @@ -68,7 +68,7 @@ typedef unsigned long sigset_t; /* These should not be considered constants from userland. */ #define SIGRTMIN 32 -#define SIGRTMAX (_NSIG-1) +#define SIGRTMAX _NSIG /* * SA_FLAGS values: diff --git a/include/asm-i386/genapic.h b/include/asm-i386/genapic.h index cd4b708133c3..76465ccbbdf8 100644 --- a/include/asm-i386/genapic.h +++ b/include/asm-i386/genapic.h @@ -30,6 +30,7 @@ struct genapic { unsigned long (*check_apicid_used)(physid_mask_t bitmap, int apicid); unsigned long (*check_apicid_present)(int apicid); int no_balance_irq; + int no_ioapic_check; void (*init_apic_ldr)(void); physid_mask_t (*ioapic_phys_id_map)(physid_mask_t map); @@ -77,6 +78,7 @@ struct genapic { .int_dest_mode = INT_DEST_MODE, \ .apic_broadcast_id = APIC_BROADCAST_ID, \ .no_balance_irq = NO_BALANCE_IRQ, \ + .no_ioapic_check = NO_IOAPIC_CHECK, \ APICFUNC(apic_id_registered), \ APICFUNC(target_cpus), \ APICFUNC(check_apicid_used), \ diff --git a/include/asm-i386/mach-bigsmp/mach_apic.h b/include/asm-i386/mach-bigsmp/mach_apic.h index dab6aa34c6fa..0e9855144660 100644 --- a/include/asm-i386/mach-bigsmp/mach_apic.h +++ b/include/asm-i386/mach-bigsmp/mach_apic.h @@ -14,6 +14,8 @@ #define NO_BALANCE_IRQ (1) #define esr_disable (1) +#define NO_IOAPIC_CHECK (0) + static inline int apic_id_registered(void) { return (1); diff --git a/include/asm-i386/mach-default/mach_apic.h b/include/asm-i386/mach-default/mach_apic.h index a96477cf10a0..8875f34285bd 100644 --- a/include/asm-i386/mach-default/mach_apic.h +++ b/include/asm-i386/mach-default/mach_apic.h @@ -18,6 +18,8 @@ static inline cpumask_t target_cpus(void) #define NO_BALANCE_IRQ (0) #define esr_disable (0) +#define NO_IOAPIC_CHECK (0) + #define INT_DELIVERY_MODE dest_LowestPrio #define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */ diff --git a/include/asm-i386/mach-generic/mach_apic.h b/include/asm-i386/mach-generic/mach_apic.h index 71b4849614bc..21f0e75f1b25 100644 --- a/include/asm-i386/mach-generic/mach_apic.h +++ b/include/asm-i386/mach-generic/mach_apic.h @@ -5,6 +5,7 @@ #define esr_disable (genapic->esr_disable) #define NO_BALANCE_IRQ (genapic->no_balance_irq) +#define NO_IOAPIC_CHECK (genapic->no_ioapic_check) #define APIC_BROADCAST_ID (genapic->apic_broadcast_id) #define INT_DELIVERY_MODE (genapic->int_delivery_mode) #define INT_DEST_MODE (genapic->int_dest_mode) diff --git a/include/asm-i386/mach-numaq/mach_apic.h b/include/asm-i386/mach-numaq/mach_apic.h index 98b4e5921aa8..814ee9aa2521 100644 --- a/include/asm-i386/mach-numaq/mach_apic.h +++ b/include/asm-i386/mach-numaq/mach_apic.h @@ -17,6 +17,8 @@ static inline cpumask_t target_cpus(void) #define NO_BALANCE_IRQ (1) #define esr_disable (1) +#define NO_IOAPIC_CHECK (0) + #define INT_DELIVERY_MODE dest_LowestPrio #define INT_DEST_MODE 0 /* physical delivery on LOCAL quad */ diff --git a/include/asm-i386/mach-summit/mach_apic.h b/include/asm-i386/mach-summit/mach_apic.h index 73a4a1077e85..a10b4591737e 100644 --- a/include/asm-i386/mach-summit/mach_apic.h +++ b/include/asm-i386/mach-summit/mach_apic.h @@ -7,14 +7,13 @@ #define esr_disable (1) #define NO_BALANCE_IRQ (0) -#define XAPIC_DEST_CPUS_MASK 0x0Fu -#define XAPIC_DEST_CLUSTER_MASK 0xF0u +#define NO_IOAPIC_CHECK (1) /* Don't check I/O APIC ID for xAPIC */ -static inline unsigned long xapic_phys_to_log_apicid(int phys_apic) -{ - return ( (1ul << ((phys_apic) & 0x3)) | - ((phys_apic) & XAPIC_DEST_CLUSTER_MASK) ); -} +/* In clustered mode, the high nibble of APIC ID is a cluster number. + * The low nibble is a 4-bit bitmap. */ +#define XAPIC_DEST_CPUS_SHIFT 4 +#define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1) +#define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT) #define APIC_DFR_VALUE (APIC_DFR_CLUSTER) @@ -40,15 +39,29 @@ static inline unsigned long check_apicid_present(int bit) return 1; } -#define apicid_cluster(apicid) (apicid & 0xF0) +#define apicid_cluster(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK) extern u8 bios_cpu_apicid[]; +extern u8 cpu_2_logical_apicid[]; static inline void init_apic_ldr(void) { unsigned long val, id; - - id = xapic_phys_to_log_apicid(hard_smp_processor_id()); + int i, count; + u8 lid; + u8 my_id = (u8)hard_smp_processor_id(); + u8 my_cluster = (u8)apicid_cluster(my_id); + + /* Create logical APIC IDs by counting CPUs already in cluster. */ + for (count = 0, i = NR_CPUS; --i >= 0; ) { + lid = cpu_2_logical_apicid[i]; + if (lid != BAD_APICID && apicid_cluster(lid) == my_cluster) + ++count; + } + /* We only have a 4 wide bitmap in cluster mode. If a deranged + * BIOS puts 5 CPUs in one APIC cluster, we're hosed. */ + BUG_ON(count >= XAPIC_DEST_CPUS_SHIFT); + id = my_cluster | (1UL << count); apic_write_around(APIC_DFR, APIC_DFR_VALUE); val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; val |= SET_APIC_LOGICAL_ID(id); @@ -77,7 +90,6 @@ static inline int apicid_to_node(int logical_apicid) } /* Mapping from cpu number to logical apicid */ -extern u8 cpu_2_logical_apicid[]; static inline int cpu_to_logical_apicid(int cpu) { if (cpu >= NR_CPUS) diff --git a/include/asm-i386/mach-visws/mach_apic.h b/include/asm-i386/mach-visws/mach_apic.h index ab40e5c0f3e5..9a0208496458 100644 --- a/include/asm-i386/mach-visws/mach_apic.h +++ b/include/asm-i386/mach-visws/mach_apic.h @@ -8,6 +8,8 @@ #define no_balance_irq (0) #define esr_disable (0) +#define NO_IOAPIC_CHECK (0) + #define INT_DELIVERY_MODE dest_LowestPrio #define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */ diff --git a/include/asm-i386/mmzone.h b/include/asm-i386/mmzone.h index cdae0e44df92..8587d7e3a2ae 100644 --- a/include/asm-i386/mmzone.h +++ b/include/asm-i386/mmzone.h @@ -122,11 +122,29 @@ static inline struct pglist_data *pfn_to_pgdat(unsigned long pfn) #elif CONFIG_ACPI_SRAT #include <asm/srat.h> #elif CONFIG_X86_PC -#define get_memcfg_numa get_memcfg_numa_flat #define get_zholes_size(n) (0) #else #define pfn_to_nid(pfn) (0) #endif /* CONFIG_X86_NUMAQ */ +extern int get_memcfg_numa_flat(void ); +/* + * This allows any one NUMA architecture to be compiled + * for, and still fall back to the flat function if it + * fails. + */ +static inline void get_memcfg_numa(void) +{ +#ifdef CONFIG_X86_NUMAQ + if (get_memcfg_numaq()) + return; +#elif CONFIG_ACPI_SRAT + if (get_memcfg_from_srat()) + return; +#endif + + get_memcfg_numa_flat(); +} + #endif /* CONFIG_DISCONTIGMEM */ #endif /* _ASM_MMZONE_H_ */ diff --git a/include/asm-i386/numaq.h b/include/asm-i386/numaq.h index de52624c6e0b..13eb04501378 100644 --- a/include/asm-i386/numaq.h +++ b/include/asm-i386/numaq.h @@ -29,8 +29,7 @@ #ifdef CONFIG_X86_NUMAQ #define MAX_NUMNODES 16 -extern void get_memcfg_numaq(void); -#define get_memcfg_numa() get_memcfg_numaq() +extern int get_memcfg_numaq(void); /* * SYS_CFG_DATA_PRIV_ADDR, struct eachquadmem, and struct sys_cfg_data are the diff --git a/include/asm-i386/processor.h b/include/asm-i386/processor.h index 9eb3f78ffd51..7a65d14b1dca 100644 --- a/include/asm-i386/processor.h +++ b/include/asm-i386/processor.h @@ -260,11 +260,6 @@ static inline void clear_in_cr4 (unsigned long mask) * Bus types (default is ISA, but people can check others with these..) * pc98 indicates PC98 systems (CBUS) */ -#ifdef CONFIG_EISA -extern int EISA_bus; -#else -#define EISA_bus (0) -#endif extern int MCA_bus; #ifdef CONFIG_X86_PC9800 #define pc98 1 diff --git a/include/asm-i386/signal.h b/include/asm-i386/signal.h index 80b7d5fdef9b..e3397cd6f77b 100644 --- a/include/asm-i386/signal.h +++ b/include/asm-i386/signal.h @@ -70,7 +70,7 @@ typedef unsigned long sigset_t; /* These should not be considered constants from userland. */ #define SIGRTMIN 32 -#define SIGRTMAX (_NSIG-1) +#define SIGRTMAX _NSIG /* * SA_FLAGS values: diff --git a/include/asm-i386/srat.h b/include/asm-i386/srat.h index b71cca0553c3..13563f45870e 100644 --- a/include/asm-i386/srat.h +++ b/include/asm-i386/srat.h @@ -32,8 +32,7 @@ #endif #define MAX_NUMNODES 8 -extern void get_memcfg_from_srat(void); +extern int get_memcfg_from_srat(void); extern unsigned long *get_zholes_size(int); -#define get_memcfg_numa() get_memcfg_from_srat() #endif /* _ASM_SRAT_H_ */ diff --git a/include/asm-i386/uaccess.h b/include/asm-i386/uaccess.h index d3eabf5b95c7..8042de63aa55 100644 --- a/include/asm-i386/uaccess.h +++ b/include/asm-i386/uaccess.h @@ -80,7 +80,7 @@ extern struct movsl_mask { * checks that the pointer is in the user space range - after calling * this function, memory access functions may still return -EFAULT. */ -#define access_ok(type,addr,size) (__range_ok(addr,size) == 0) +#define access_ok(type,addr,size) (likely(__range_ok(addr,size) == 0)) /** * verify_area: - Obsolete, use access_ok() diff --git a/include/asm-ia64/acpi.h b/include/asm-ia64/acpi.h index 51d587edf419..66d1a35f2de0 100644 --- a/include/asm-ia64/acpi.h +++ b/include/asm-ia64/acpi.h @@ -30,6 +30,8 @@ #ifdef __KERNEL__ +#include <asm/system.h> + #define COMPILER_DEPENDENT_INT64 long #define COMPILER_DEPENDENT_UINT64 unsigned long diff --git a/include/asm-ia64/numa.h b/include/asm-ia64/numa.h index a6a87c92689f..c3a26e12cd07 100644 --- a/include/asm-ia64/numa.h +++ b/include/asm-ia64/numa.h @@ -23,7 +23,7 @@ #include <linux/cache.h> extern volatile char cpu_to_node_map[NR_CPUS] __cacheline_aligned; -extern volatile unsigned long node_to_cpu_mask[NR_NODES] __cacheline_aligned; +extern volatile cpumask_t node_to_cpu_mask[NR_NODES] __cacheline_aligned; /* Stuff below this line could be architecture independent */ diff --git a/include/asm-ia64/param.h b/include/asm-ia64/param.h index eaee5da9a787..f39d939ebb80 100644 --- a/include/asm-ia64/param.h +++ b/include/asm-ia64/param.h @@ -4,22 +4,10 @@ /* * Fundamental kernel parameters. * - * Copyright (C) 1998, 1999, 2002 Hewlett-Packard Co + * Copyright (C) 1998, 1999, 2002-2003 Hewlett-Packard Co * David Mosberger-Tang <davidm@hpl.hp.com> */ -#include <linux/config.h> - -#ifdef CONFIG_IA64_HP_SIM -/* - * Yeah, simulating stuff is slow, so let us catch some breath between - * timer interrupts... - */ -# define HZ 32 -#else -# define HZ 1024 -#endif - #define EXEC_PAGESIZE 65536 #ifndef NGROUPS @@ -33,8 +21,24 @@ #define MAXHOSTNAMELEN 64 /* max length of hostname */ #ifdef __KERNEL__ +# include <linux/config.h> /* mustn't include <linux/config.h> outside of #ifdef __KERNEL__ */ +# ifdef CONFIG_IA64_HP_SIM + /* + * Yeah, simulating stuff is slow, so let us catch some breath between + * timer interrupts... + */ +# define HZ 32 +# else +# define HZ 1024 +# endif # define USER_HZ HZ # define CLOCKS_PER_SEC HZ /* frequency at which times() counts */ +#else + /* + * Technically, this is wrong, but some old apps still refer to it. The proper way to + * get the HZ value is via sysconf(_SC_CLK_TCK). + */ +# define HZ 1024 #endif #endif /* _ASM_IA64_PARAM_H */ diff --git a/include/asm-ia64/processor.h b/include/asm-ia64/processor.h index c6b4af2b3643..ed83487c5dc1 100644 --- a/include/asm-ia64/processor.h +++ b/include/asm-ia64/processor.h @@ -56,7 +56,6 @@ /* * Bus types */ -#define EISA_bus 0 #define MCA_bus 0 #define MCA_bus__is_a_macro /* for versions in ksyms.c */ diff --git a/include/asm-ia64/signal.h b/include/asm-ia64/signal.h index f98d3bb65a92..5744b56571ba 100644 --- a/include/asm-ia64/signal.h +++ b/include/asm-ia64/signal.h @@ -50,7 +50,7 @@ /* These should not be considered constants from userland. */ #define SIGRTMIN 32 -#define SIGRTMAX (_NSIG-1) +#define SIGRTMAX _NSIG /* * SA_FLAGS values: diff --git a/include/asm-ia64/sn/ksys/elsc.h b/include/asm-ia64/sn/ksys/elsc.h index aa8272ad8580..987cc1b17e7e 100644 --- a/include/asm-ia64/sn/ksys/elsc.h +++ b/include/asm-ia64/sn/ksys/elsc.h @@ -9,9 +9,6 @@ #ifndef _ASM_SN_KSYS_ELSC_H #define _ASM_SN_KSYS_ELSC_H -#include <linux/config.h> -#include <asm/sn/ksys/l1.h> - /* * Error codes * diff --git a/include/asm-ia64/sn/ksys/l1.h b/include/asm-ia64/sn/ksys/l1.h index beb89ad4cd1a..b7386fdbe50f 100644 --- a/include/asm-ia64/sn/ksys/l1.h +++ b/include/asm-ia64/sn/ksys/l1.h @@ -10,10 +10,7 @@ #ifndef _ASM_SN_KSYS_L1_H #define _ASM_SN_KSYS_L1_H -#include <linux/config.h> -#include <asm/sn/vector.h> -#include <asm/sn/addrs.h> -#include <asm/atomic.h> +#include <asm/sn/types.h> /* L1 Target Addresses */ /* @@ -39,18 +36,6 @@ #define L1_ADDR_TASK_BEDROCK 0x05 /* bedrock */ #define L1_ADDR_TASK_GENERAL 0x06 /* general requests */ -#define L1_ADDR_LOCAL \ - (L1_ADDR_TYPE_L1 << L1_ADDR_TYPE_SHFT) | \ - (L1_ADDR_RACK_LOCAL << L1_ADDR_RACK_SHFT) | \ - (L1_ADDR_BAY_LOCAL << L1_ADDR_BAY_SHFT) - -#define L1_ADDR_LOCALIO \ - (L1_ADDR_TYPE_IOBRICK << L1_ADDR_TYPE_SHFT) | \ - (L1_ADDR_RACK_LOCAL << L1_ADDR_RACK_SHFT) | \ - (L1_ADDR_BAY_LOCAL << L1_ADDR_BAY_SHFT) - -#define L1_ADDR_LOCAL_SHFT L1_ADDR_BAY_SHFT - /* response argument types */ #define L1_ARG_INT 0x00 /* 4-byte integer (big-endian) */ #define L1_ARG_ASCII 0x01 /* null-terminated ASCII string */ @@ -133,18 +118,6 @@ #define L1_EEP_IUSE 3 /* internal use area */ #define L1_EEP_SPD 4 /* serial presence detect record */ -typedef uint32_t l1addr_t; - -#define L1_BUILD_ADDR(addr,at,r,s,t) \ - (*(l1addr_t *)(addr) = ((l1addr_t)(at) << L1_ADDR_TYPE_SHFT) | \ - ((l1addr_t)(r) << L1_ADDR_RACK_SHFT) | \ - ((l1addr_t)(s) << L1_ADDR_BAY_SHFT) | \ - ((l1addr_t)(t) << L1_ADDR_TASK_SHFT)) - -#define L1_ADDRESS_TO_TASK(addr,trb,tsk) \ - (*(l1addr_t *)(addr) = (l1addr_t)(trb) | \ - ((l1addr_t)(tsk) << L1_ADDR_TASK_SHFT)) - #define L1_DISPLAY_LINE_LENGTH 12 /* L1 display characters/line */ #ifdef L1_DISP_2LINES @@ -154,11 +127,9 @@ typedef uint32_t l1addr_t; * to system software */ #endif -#define bzero(d, n) memset((d), 0, (n)) - int elsc_display_line(nasid_t nasid, char *line, int lnum); -int iobrick_rack_bay_type_get( nasid_t nasid, uint *rack, - uint *bay, uint *brick_type ); +int iobrick_rack_bay_type_get( nasid_t nasid, unsigned int *rack, + unsigned int *bay, unsigned int *brick_type ); int iobrick_module_get( nasid_t nasid ); diff --git a/include/asm-ia64/sn/nodepda.h b/include/asm-ia64/sn/nodepda.h index b2ed848afa38..edf269398884 100644 --- a/include/asm-ia64/sn/nodepda.h +++ b/include/asm-ia64/sn/nodepda.h @@ -128,7 +128,7 @@ typedef struct irqpda_s irqpda_t; * Check if given a compact node id the corresponding node has all the * cpus disabled. */ -#define is_headless_node(cnode) (!node_to_cpumask(cnode)) +#define is_headless_node(cnode) (!any_online_cpu(node_to_cpumask(cnode))) /* * Check if given a node vertex handle the corresponding node has all the diff --git a/include/asm-ia64/sn/pci/pcibr_private.h b/include/asm-ia64/sn/pci/pcibr_private.h index 6e1cfde2c993..6c120927249c 100644 --- a/include/asm-ia64/sn/pci/pcibr_private.h +++ b/include/asm-ia64/sn/pci/pcibr_private.h @@ -15,11 +15,9 @@ * should ever peek into this file. */ -#include <linux/config.h> #include <linux/pci.h> #include <asm/sn/pci/pcibr.h> #include <asm/sn/pci/pciio_private.h> -#include <asm/sn/ksys/l1.h> /* * convenience typedefs diff --git a/include/asm-ia64/sn/router.h b/include/asm-ia64/sn/router.h index 1c280988539f..bbd7ba62a733 100644 --- a/include/asm-ia64/sn/router.h +++ b/include/asm-ia64/sn/router.h @@ -1,5 +1,4 @@ - -/* $Id$ +/* $id$ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -19,7 +18,6 @@ #ifndef __ASSEMBLY__ -#include <linux/devfs_fs_kernel.h> #include <asm/sn/vector.h> #include <asm/sn/slotnum.h> #include <asm/sn/arch.h> @@ -31,23 +29,19 @@ typedef uint64_t router_reg_t; #define MAX_ROUTER_PATH 80 #define ROUTER_REG_CAST (volatile router_reg_t *) -#define PS_UINT_CAST (__psunsigned_t) -#define UINT64_CAST (uint64_t) typedef signed char port_no_t; /* Type for router port number */ #else #define ROUTERREG_CAST -#define PS_UINT_CAST -#define UINT64_CAST #endif /* __ASSEMBLY__ */ -#define MAX_ROUTER_PORTS (8) /* Max. number of ports on a router */ +#define MAX_ROUTER_PORTS 8 /* Max. number of ports on a router */ #define ALL_PORTS ((1 << MAX_ROUTER_PORTS) - 1) /* for 0 based references */ -#define PORT_INVALID (-1) /* Invalid port number */ +#define PORT_INVALID -1 /* Invalid port number */ #define IS_META(_rp) ((_rp)->flags & PCFG_ROUTER_META) @@ -126,24 +120,24 @@ typedef signed char port_no_t; /* Type for router port number */ */ #define RSRI_INPORT_SHFT 52 -#define RSRI_INPORT_MASK (UINT64_CAST 0xf << 52) +#define RSRI_INPORT_MASK (0xfUL << 52) #define RSRI_LINKWORKING_BIT(_L) (35 + 2 * (_L)) -#define RSRI_LINKWORKING(_L) (UINT64_CAST 1 << (35 + 2 * (_L))) -#define RSRI_LINKRESETFAIL(_L) (UINT64_CAST 1 << (34 + 2 * (_L))) +#define RSRI_LINKWORKING(_L) (1UL << (35 + 2 * (_L))) +#define RSRI_LINKRESETFAIL(_L) (1UL << (34 + 2 * (_L))) #define RSRI_LSTAT_SHFT(_L) (34 + 2 * (_L)) -#define RSRI_LSTAT_MASK(_L) (UINT64_CAST 0x3 << 34 + 2 * (_L)) -#define RSRI_LOCALSBERROR (UINT64_CAST 1 << 35) -#define RSRI_LOCALSTUCK (UINT64_CAST 1 << 34) -#define RSRI_LOCALBADVEC (UINT64_CAST 1 << 33) -#define RSRI_LOCALTAILERR (UINT64_CAST 1 << 32) +#define RSRI_LSTAT_MASK(_L) (0x3UL << 34 + 2 * (_L)) +#define RSRI_LOCALSBERROR (1UL << 35) +#define RSRI_LOCALSTUCK (1UL << 34) +#define RSRI_LOCALBADVEC (1UL << 33) +#define RSRI_LOCALTAILERR (1UL << 32) #define RSRI_LOCAL_SHFT 32 -#define RSRI_LOCAL_MASK (UINT64_CAST 0xf << 32) +#define RSRI_LOCAL_MASK (0xfUL << 32) #define RSRI_CHIPREV_SHFT 28 -#define RSRI_CHIPREV_MASK (UINT64_CAST 0xf << 28) +#define RSRI_CHIPREV_MASK (0xfUL << 28) #define RSRI_CHIPID_SHFT 12 -#define RSRI_CHIPID_MASK (UINT64_CAST 0xffff << 12) +#define RSRI_CHIPID_MASK (0xffffUL << 12) #define RSRI_MFGID_SHFT 1 -#define RSRI_MFGID_MASK (UINT64_CAST 0x7ff << 1) +#define RSRI_MFGID_MASK (0x7ffUL << 1) #define RSRI_LSTAT_WENTDOWN 0 #define RSRI_LSTAT_RESETFAIL 1 @@ -154,38 +148,38 @@ typedef signed char port_no_t; /* Type for router port number */ * RR_PORT_RESET mask definitions */ -#define RPRESET_WARM (UINT64_CAST 1 << 9) -#define RPRESET_LINK(_L) (UINT64_CAST 1 << (_L)) -#define RPRESET_LOCAL (UINT64_CAST 1) +#define RPRESET_WARM (1UL << 9) +#define RPRESET_LINK(_L) (1UL << (_L)) +#define RPRESET_LOCAL 1UL /* * RR_PROT_CONF mask and shift definitions */ #define RPCONF_DIRCMPDIS_SHFT 13 -#define RPCONF_DIRCMPDIS_MASK (UINT64_CAST 1 << 13) -#define RPCONF_FORCELOCAL (UINT64_CAST 1 << 12) +#define RPCONF_DIRCMPDIS_MASK (1UL << 13) +#define RPCONF_FORCELOCAL (1UL << 12) #define RPCONF_FLOCAL_SHFT 12 #define RPCONF_METAID_SHFT 8 -#define RPCONF_METAID_MASK (UINT64_CAST 0xf << 8) -#define RPCONF_RESETOK(_L) (UINT64_CAST 1 << ((_L) - 1)) +#define RPCONF_METAID_MASK (0xfUL << 8) +#define RPCONF_RESETOK(_L) (1UL << ((_L) - 1)) /* * RR_GLOBAL_PORT_DEF mask and shift definitions */ #define RGPD_MGLBLNHBR_ID_SHFT 12 /* -global neighbor ID */ -#define RGPD_MGLBLNHBR_ID_MASK (UINT64_CAST 0xf << 12) +#define RGPD_MGLBLNHBR_ID_MASK (0xfUL << 12) #define RGPD_MGLBLNHBR_VLD_SHFT 11 /* -global neighbor Valid */ -#define RGPD_MGLBLNHBR_VLD_MASK (UINT64_CAST 0x1 << 11) +#define RGPD_MGLBLNHBR_VLD_MASK (0x1UL << 11) #define RGPD_MGLBLPORT_SHFT 8 /* -global neighbor Port */ -#define RGPD_MGLBLPORT_MASK (UINT64_CAST 0x7 << 8) +#define RGPD_MGLBLPORT_MASK (0x7UL << 8) #define RGPD_PGLBLNHBR_ID_SHFT 4 /* +global neighbor ID */ -#define RGPD_PGLBLNHBR_ID_MASK (UINT64_CAST 0xf << 4) +#define RGPD_PGLBLNHBR_ID_MASK (0xfUL << 4) #define RGPD_PGLBLNHBR_VLD_SHFT 3 /* +global neighbor Valid */ -#define RGPD_PGLBLNHBR_VLD_MASK (UINT64_CAST 0x1 << 3) +#define RGPD_PGLBLNHBR_VLD_MASK (0x1UL << 3) #define RGPD_PGLBLPORT_SHFT 0 /* +global neighbor Port */ -#define RGPD_PGLBLPORT_MASK (UINT64_CAST 0x7 << 0) +#define RGPD_PGLBLPORT_MASK (0x7UL << 0) #define GLBL_PARMS_REGS 2 /* Two Global Parms registers */ @@ -194,95 +188,95 @@ typedef signed char port_no_t; /* Type for router port number */ */ #define RGPARM0_ARB_VALUE_SHFT 54 /* Local Block Arbitration State */ -#define RGPARM0_ARB_VALUE_MASK (UINT64_CAST 0x7 << 54) +#define RGPARM0_ARB_VALUE_MASK (0x7UL << 54) #define RGPARM0_ROTATEARB_SHFT 53 /* Rotate Local Block Arbitration */ -#define RGPARM0_ROTATEARB_MASK (UINT64_CAST 0x1 << 53) +#define RGPARM0_ROTATEARB_MASK (1UL << 53) #define RGPARM0_FAIREN_SHFT 52 /* Fairness logic Enable */ -#define RGPARM0_FAIREN_MASK (UINT64_CAST 0x1 << 52) +#define RGPARM0_FAIREN_MASK (1UL << 52) #define RGPARM0_LOCGNTTO_SHFT 40 /* Local grant timeout */ -#define RGPARM0_LOCGNTTO_MASK (UINT64_CAST 0xfff << 40) +#define RGPARM0_LOCGNTTO_MASK (0xfffUL << 40) #define RGPARM0_DATELINE_SHFT 38 /* Dateline crossing router */ -#define RGPARM0_DATELINE_MASK (UINT64_CAST 0x1 << 38) +#define RGPARM0_DATELINE_MASK (1UL << 38) #define RGPARM0_MAXRETRY_SHFT 28 /* Max retry count */ -#define RGPARM0_MAXRETRY_MASK (UINT64_CAST 0x3ff << 28) +#define RGPARM0_MAXRETRY_MASK (0x3ffUL << 28) #define RGPARM0_URGWRAP_SHFT 20 /* Urgent wrap */ -#define RGPARM0_URGWRAP_MASK (UINT64_CAST 0xff << 20) +#define RGPARM0_URGWRAP_MASK (0xffUL << 20) #define RGPARM0_DEADLKTO_SHFT 16 /* Deadlock timeout */ -#define RGPARM0_DEADLKTO_MASK (UINT64_CAST 0xf << 16) +#define RGPARM0_DEADLKTO_MASK (0xfUL << 16) #define RGPARM0_URGVAL_SHFT 12 /* Urgent value */ -#define RGPARM0_URGVAL_MASK (UINT64_CAST 0xf << 12) +#define RGPARM0_URGVAL_MASK (0xfUL << 12) #define RGPARM0_VCHSELEN_SHFT 11 /* VCH_SEL_EN */ -#define RGPARM0_VCHSELEN_MASK (UINT64_CAST 0x1 << 11) +#define RGPARM0_VCHSELEN_MASK (1UL << 11) #define RGPARM0_LOCURGTO_SHFT 9 /* Local urgent timeout */ -#define RGPARM0_LOCURGTO_MASK (UINT64_CAST 0x3 << 9) +#define RGPARM0_LOCURGTO_MASK (0x3UL << 9) #define RGPARM0_TAILVAL_SHFT 5 /* Tail value */ -#define RGPARM0_TAILVAL_MASK (UINT64_CAST 0xf << 5) +#define RGPARM0_TAILVAL_MASK (0xfUL << 5) #define RGPARM0_CLOCK_SHFT 1 /* Global clock select */ -#define RGPARM0_CLOCK_MASK (UINT64_CAST 0xf << 1) +#define RGPARM0_CLOCK_MASK (0xfUL << 1) #define RGPARM0_BYPEN_SHFT 0 -#define RGPARM0_BYPEN_MASK (UINT64_CAST 1) /* Bypass enable */ +#define RGPARM0_BYPEN_MASK 1UL /* Bypass enable */ /* * RR_GLOBAL_PARMS1 shift and mask definitions */ #define RGPARM1_TTOWRAP_SHFT 12 /* Tail timeout wrap */ -#define RGPARM1_TTOWRAP_MASK (UINT64_CAST 0xfffff << 12) +#define RGPARM1_TTOWRAP_MASK (0xfffffUL << 12) #define RGPARM1_AGERATE_SHFT 8 /* Age rate */ -#define RGPARM1_AGERATE_MASK (UINT64_CAST 0xf << 8) +#define RGPARM1_AGERATE_MASK (0xfUL << 8) #define RGPARM1_JSWSTAT_SHFT 0 /* JTAG Sw Register bits */ -#define RGPARM1_JSWSTAT_MASK (UINT64_CAST 0xff << 0) +#define RGPARM1_JSWSTAT_MASK (0xffUL << 0) /* * RR_DIAG_PARMS mask and shift definitions */ -#define RDPARM_ABSHISTOGRAM (UINT64_CAST 1 << 17) /* Absolute histgrm */ -#define RDPARM_DEADLOCKRESET (UINT64_CAST 1 << 16) /* Reset on deadlck */ -#define RDPARM_DISABLE(_L) (UINT64_CAST 1 << ((_L) + 7)) -#define RDPARM_SENDERROR(_L) (UINT64_CAST 1 << ((_L) - 1)) +#define RDPARM_ABSHISTOGRAM (1UL << 17) /* Absolute histgrm */ +#define RDPARM_DEADLOCKRESET (1UL << 16) /* Reset on deadlck */ +#define RDPARM_DISABLE(_L) (1UL << ((_L) + 7)) +#define RDPARM_SENDERROR(_L) (1UL << ((_L) - 1)) /* * RR_DEBUG_ADDR mask and shift definitions */ #define RDA_DATA_SHFT 10 /* Observed debug data */ -#define RDA_DATA_MASK (UINT64_CAST 0xffff << 10) +#define RDA_DATA_MASK (0xffffUL << 10) #define RDA_ADDR_SHFT 0 /* debug address for data */ -#define RDA_ADDR_MASK (UINT64_CAST 0x3ff << 0) +#define RDA_ADDR_MASK (0x3ffUL << 0) /* * RR_LB_TO_L2 mask and shift definitions */ #define RLBTOL2_DATA_VLD_SHFT 32 /* data is valid for JTAG controller */ -#define RLBTOL2_DATA_VLD_MASK (UINT64_CAST 0x1 << 32) +#define RLBTOL2_DATA_VLD_MASK (1UL << 32) #define RLBTOL2_DATA_SHFT 0 /* data bits for JTAG controller */ -#define RLBTOL2_DATA_MASK (UINT64_CAST 0xffffffff) +#define RLBTOL2_DATA_MASK 0xffffffffUL /* * RR_L2_TO_LB mask and shift definitions */ #define RL2TOLB_DATA_VLD_SHFT 33 /* data is valid from JTAG controller */ -#define RL2TOLB_DATA_VLD_MASK (UINT64_CAST 0x1 << 33) +#define RL2TOLB_DATA_VLD_MASK (1UL << 33) #define RL2TOLB_PARITY_SHFT 32 /* sw implemented parity for data */ -#define RL2TOLB_PARITY_MASK (UINT64_CAST 0x1 << 32) +#define RL2TOLB_PARITY_MASK (1UL << 32) #define RL2TOLB_DATA_SHFT 0 /* data bits from JTAG controller */ -#define RL2TOLB_DATA_MASK (UINT64_CAST 0xffffffff) +#define RL2TOLB_DATA_MASK 0xffffffffUL /* * RR_JBUS_CONTROL mask and shift definitions */ #define RJC_POS_BITS_SHFT 20 /* Router position bits */ -#define RJC_POS_BITS_MASK (UINT64_CAST 0xf << 20) +#define RJC_POS_BITS_MASK (0xfUL << 20) #define RJC_RD_DATA_STROBE_SHFT 16 /* count when read data is strobed in */ -#define RJC_RD_DATA_STROBE_MASK (UINT64_CAST 0xf << 16) +#define RJC_RD_DATA_STROBE_MASK (0xfUL << 16) #define RJC_WE_OE_HOLD_SHFT 8 /* time OE or WE is held */ -#define RJC_WE_OE_HOLD_MASK (UINT64_CAST 0xff << 8) +#define RJC_WE_OE_HOLD_MASK (0xffUL << 8) #define RJC_ADDR_SET_HLD_SHFT 0 /* time address driven around OE/WE */ -#define RJC_ADDR_SET_HLD_MASK (UINT64_CAST 0xff) +#define RJC_ADDR_SET_HLD_MASK 0xffUL /* * RR_SCRATCH_REGx mask and shift definitions @@ -291,58 +285,58 @@ typedef signed char port_no_t; /* Type for router port number */ */ #define RSCR0_BOOTED_SHFT 63 -#define RSCR0_BOOTED_MASK (UINT64_CAST 0x1 << RSCR0_BOOTED_SHFT) +#define RSCR0_BOOTED_MASK (0x1UL << RSCR0_BOOTED_SHFT) #define RSCR0_LOCALID_SHFT 56 -#define RSCR0_LOCALID_MASK (UINT64_CAST 0x7f << RSCR0_LOCALID_SHFT) +#define RSCR0_LOCALID_MASK (0x7fUL << RSCR0_LOCALID_SHFT) #define RSCR0_UNUSED_SHFT 48 -#define RSCR0_UNUSED_MASK (UINT64_CAST 0xff << RSCR0_UNUSED_SHFT) +#define RSCR0_UNUSED_MASK (0xffUL << RSCR0_UNUSED_SHFT) #define RSCR0_NIC_SHFT 0 -#define RSCR0_NIC_MASK (UINT64_CAST 0xffffffffffff) +#define RSCR0_NIC_MASK 0xffffffffffffUL #define RSCR1_MODID_SHFT 0 -#define RSCR1_MODID_MASK (UINT64_CAST 0xffff) +#define RSCR1_MODID_MASK 0xffffUL /* * RR_VECTOR_HW_BAR mask and shift definitions */ #define BAR_TX_SHFT 27 /* Barrier in trans(m)it when read */ -#define BAR_TX_MASK (UINT64_CAST 1 << BAR_TX_SHFT) +#define BAR_TX_MASK (1UL << BAR_TX_SHFT) #define BAR_VLD_SHFT 26 /* Valid Configuration */ -#define BAR_VLD_MASK (UINT64_CAST 1 << BAR_VLD_SHFT) +#define BAR_VLD_MASK (1UL << BAR_VLD_SHFT) #define BAR_SEQ_SHFT 24 /* Sequence number */ -#define BAR_SEQ_MASK (UINT64_CAST 3 << BAR_SEQ_SHFT) +#define BAR_SEQ_MASK (3UL << BAR_SEQ_SHFT) #define BAR_LEAFSTATE_SHFT 18 /* Leaf State */ -#define BAR_LEAFSTATE_MASK (UINT64_CAST 0x3f << BAR_LEAFSTATE_SHFT) +#define BAR_LEAFSTATE_MASK (0x3fUL << BAR_LEAFSTATE_SHFT) #define BAR_PARENT_SHFT 14 /* Parent Port */ -#define BAR_PARENT_MASK (UINT64_CAST 0xf << BAR_PARENT_SHFT) +#define BAR_PARENT_MASK (0xfUL << BAR_PARENT_SHFT) #define BAR_CHILDREN_SHFT 6 /* Child Select port bits */ -#define BAR_CHILDREN_MASK (UINT64_CAST 0xff << BAR_CHILDREN_SHFT) +#define BAR_CHILDREN_MASK (0xffUL << BAR_CHILDREN_SHFT) #define BAR_LEAFCOUNT_SHFT 0 /* Leaf Count to trigger parent */ -#define BAR_LEAFCOUNT_MASK (UINT64_CAST 0x3f) +#define BAR_LEAFCOUNT_MASK 0x3fUL /* * RR_PORT_PARMS(_L) mask and shift definitions */ #define RPPARM_MIPRESETEN_SHFT 29 /* Message In Progress reset enable */ -#define RPPARM_MIPRESETEN_MASK (UINT64_CAST 0x1 << 29) +#define RPPARM_MIPRESETEN_MASK (0x1UL << 29) #define RPPARM_UBAREN_SHFT 28 /* Enable user barrier requests */ -#define RPPARM_UBAREN_MASK (UINT64_CAST 0x1 << 28) +#define RPPARM_UBAREN_MASK (0x1UL << 28) #define RPPARM_OUTPDTO_SHFT 24 /* Output Port Deadlock TO value */ -#define RPPARM_OUTPDTO_MASK (UINT64_CAST 0xf << 24) +#define RPPARM_OUTPDTO_MASK (0xfUL << 24) #define RPPARM_PORTMATE_SHFT 21 /* Port Mate for the port */ -#define RPPARM_PORTMATE_MASK (UINT64_CAST 0x7 << 21) +#define RPPARM_PORTMATE_MASK (0x7UL << 21) #define RPPARM_HISTEN_SHFT 20 /* Histogram counter enable */ -#define RPPARM_HISTEN_MASK (UINT64_CAST 0x1 << 20) +#define RPPARM_HISTEN_MASK (0x1UL << 20) #define RPPARM_HISTSEL_SHFT 18 -#define RPPARM_HISTSEL_MASK (UINT64_CAST 0x3 << 18) +#define RPPARM_HISTSEL_MASK (0x3UL << 18) #define RPPARM_DAMQHS_SHFT 16 -#define RPPARM_DAMQHS_MASK (UINT64_CAST 0x3 << 16) +#define RPPARM_DAMQHS_MASK (0x3UL << 16) #define RPPARM_NULLTO_SHFT 10 -#define RPPARM_NULLTO_MASK (UINT64_CAST 0x3f << 10) +#define RPPARM_NULLTO_MASK (0x3fUL << 10) #define RPPARM_MAXBURST_SHFT 0 -#define RPPARM_MAXBURST_MASK (UINT64_CAST 0x3ff) +#define RPPARM_MAXBURST_MASK 0x3ffUL /* * NOTE: Normally the kernel tracks only UTILIZATION statistics. @@ -356,23 +350,23 @@ typedef signed char port_no_t; /* Type for router port number */ /* * RR_STATUS_ERROR(_L) and RR_ERROR_CLEAR(_L) mask and shift definitions */ -#define RSERR_POWERNOK (UINT64_CAST 1 << 38) -#define RSERR_PORT_DEADLOCK (UINT64_CAST 1 << 37) -#define RSERR_WARMRESET (UINT64_CAST 1 << 36) -#define RSERR_LINKRESET (UINT64_CAST 1 << 35) -#define RSERR_RETRYTIMEOUT (UINT64_CAST 1 << 34) -#define RSERR_FIFOOVERFLOW (UINT64_CAST 1 << 33) -#define RSERR_ILLEGALPORT (UINT64_CAST 1 << 32) +#define RSERR_POWERNOK (1UL << 38) +#define RSERR_PORT_DEADLOCK (1UL << 37) +#define RSERR_WARMRESET (1UL << 36) +#define RSERR_LINKRESET (1UL << 35) +#define RSERR_RETRYTIMEOUT (1UL << 34) +#define RSERR_FIFOOVERFLOW (1UL << 33) +#define RSERR_ILLEGALPORT (1UL << 32) #define RSERR_DEADLOCKTO_SHFT 28 -#define RSERR_DEADLOCKTO_MASK (UINT64_CAST 0xf << 28) +#define RSERR_DEADLOCKTO_MASK (0xfUL << 28) #define RSERR_RECVTAILTO_SHFT 24 -#define RSERR_RECVTAILTO_MASK (UINT64_CAST 0xf << 24) +#define RSERR_RECVTAILTO_MASK (0xfUL << 24) #define RSERR_RETRYCNT_SHFT 16 -#define RSERR_RETRYCNT_MASK (UINT64_CAST 0xff << 16) +#define RSERR_RETRYCNT_MASK (0xffUL << 16) #define RSERR_CBERRCNT_SHFT 8 -#define RSERR_CBERRCNT_MASK (UINT64_CAST 0xff << 8) +#define RSERR_CBERRCNT_MASK (0xffUL << 8) #define RSERR_SNERRCNT_SHFT 0 -#define RSERR_SNERRCNT_MASK (UINT64_CAST 0xff << 0) +#define RSERR_SNERRCNT_MASK (0xffUL << 0) #define PORT_STATUS_UP (1 << 0) /* Router link up */ @@ -393,10 +387,10 @@ typedef signed char port_no_t; /* Type for router port number */ * why the router link * went down */ -#define PROBE_RESULT_BAD (-1) /* Set if any of the router +#define PROBE_RESULT_BAD -1 /* Set if any of the router * links failed after reset */ -#define PROBE_RESULT_GOOD (0) /* Set if all the router links +#define PROBE_RESULT_GOOD 0 /* Set if all the router links * which came out of reset * are up */ @@ -528,23 +522,6 @@ typedef struct router_info_s { #define RIP_PROMLOG 2 /* Router info in promlog */ #define RIP_CONSOLE 4 /* Router info on console */ -#define ROUTER_INFO_PRINT(_rip,_where) (_rip->ri_print |= _where) - /* Set the field used to check if a - * router info can be printed - */ -#define IS_ROUTER_INFO_PRINTED(_rip,_where) \ - (_rip->ri_print & _where) - /* Was the router info printed to - * the given location (_where) ? - * Mainly used to prevent duplicate - * router error states. - */ -#define ROUTER_INFO_LOCK(_rip,_s) _s = mutex_spinlock(&(_rip->ri_lock)) - /* Take the lock on router info - * to gain exclusive access - */ -#define ROUTER_INFO_UNLOCK(_rip,_s) mutex_spinunlock(&(_rip->ri_lock),_s) - /* Release the lock on router info */ /* * Router info hanging in the nodepda */ @@ -623,7 +600,7 @@ typedef struct router_queue_s { */ #define RHIST_BUCKET_SHFT(_x) (32 * ((_x) & 0x1)) -#define RHIST_BUCKET_MASK(_x) (UINT64_CAST 0xffffffff << RHIST_BUCKET_SHFT((_x) & 0x1)) +#define RHIST_BUCKET_MASK(_x) (0xffffffffUL << RHIST_BUCKET_SHFT((_x) & 0x1)) #define RHIST_GET_BUCKET(_x, _reg) \ ((RHIST_BUCKET_MASK(_x) & ((_reg)[(_x) >> 1])) >> RHIST_BUCKET_SHFT(_x)) @@ -631,7 +608,7 @@ typedef struct router_queue_s { * RR_RESET_MASK(_L) mask and shift definitions */ -#define RRM_RESETOK(_L) (UINT64_CAST 1 << ((_L) - 1)) +#define RRM_RESETOK(_L) (1UL << ((_L) - 1)) #define RRM_RESETOK_ALL ALL_PORTS /* @@ -639,7 +616,7 @@ typedef struct router_queue_s { */ #define RTABLE_SHFT(_L) (4 * ((_L) - 1)) -#define RTABLE_MASK(_L) (UINT64_CAST 0x7 << RTABLE_SHFT(_L)) +#define RTABLE_MASK(_L) (0x7UL << RTABLE_SHFT(_L)) #define ROUTERINFO_STKSZ 4096 diff --git a/include/asm-ia64/sn/sn2/shub.h b/include/asm-ia64/sn/sn2/shub.h index 4547ff440550..7b094da0e2a0 100644 --- a/include/asm-ia64/sn/sn2/shub.h +++ b/include/asm-ia64/sn/sn2/shub.h @@ -11,13 +11,6 @@ #ifndef _ASM_IA64_SN_SN2_SHUB_H #define _ASM_IA64_SN_SN2_SHUB_H -#include <asm/sn/sn2/shub_mmr.h> /* shub mmr addresses and formats */ -#include <asm/sn/sn2/shub_md.h> -#include <asm/sn/sn2/shubio.h> -#ifndef __ASSEMBLY__ -#include <asm/sn/sn2/shub_mmr_t.h> /* shub mmr struct defines */ -#endif - /* * Junk Bus Address Space * The junk bus is used to access the PROM, LED's, and UART. It's diff --git a/include/asm-ia64/sn/sn2/shub_mmr_t.h b/include/asm-ia64/sn/sn2/shub_mmr_t.h index f0397c400750..5e74a7e1c8b5 100644 --- a/include/asm-ia64/sn/sn2/shub_mmr_t.h +++ b/include/asm-ia64/sn/sn2/shub_mmr_t.h @@ -7,8 +7,6 @@ * Copyright (c) 2001-2003 Silicon Graphics, Inc. All rights reserved. */ - - #ifndef _ASM_IA64_SN_SN2_SHUB_MMR_T_H #define _ASM_IA64_SN_SN2_SHUB_MMR_T_H @@ -19,7 +17,6 @@ /* FSB BINIT# Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_fsb_binit_control_u { mmr_t sh_fsb_binit_control_regval; struct { @@ -27,22 +24,12 @@ typedef union sh_fsb_binit_control_u { mmr_t reserved_0 : 63; } sh_fsb_binit_control_s; } sh_fsb_binit_control_u_t; -#else -typedef union sh_fsb_binit_control_u { - mmr_t sh_fsb_binit_control_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t binit : 1; - } sh_fsb_binit_control_s; -} sh_fsb_binit_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_FSB_RESET_CONTROL" */ /* FSB Reset Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_fsb_reset_control_u { mmr_t sh_fsb_reset_control_regval; struct { @@ -50,22 +37,12 @@ typedef union sh_fsb_reset_control_u { mmr_t reserved_0 : 63; } sh_fsb_reset_control_s; } sh_fsb_reset_control_u_t; -#else -typedef union sh_fsb_reset_control_u { - mmr_t sh_fsb_reset_control_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t reset : 1; - } sh_fsb_reset_control_s; -} sh_fsb_reset_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_FSB_SYSTEM_AGENT_CONFIG" */ /* FSB System Agent Configuration */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_fsb_system_agent_config_u { mmr_t sh_fsb_system_agent_config_regval; struct { @@ -88,37 +65,12 @@ typedef union sh_fsb_system_agent_config_u { mmr_t reserved_3 : 18; } sh_fsb_system_agent_config_s; } sh_fsb_system_agent_config_u_t; -#else -typedef union sh_fsb_system_agent_config_u { - mmr_t sh_fsb_system_agent_config_regval; - struct { - mmr_t reserved_3 : 18; - mmr_t binit_event_enables : 14; - mmr_t reserved_2 : 7; - mmr_t serialize_fsb_en : 1; - mmr_t tdot : 1; - mmr_t reserved_1 : 4; - mmr_t inta_trans_rsp : 1; - mmr_t xtpr_trans_rsp : 1; - mmr_t io_trans_rsp : 1; - mmr_t inta_rsp_data : 8; - mmr_t short_hang_en : 1; - mmr_t bnr_throttling_en : 1; - mmr_t binit_assert_en : 1; - mmr_t berr_sampling_en : 1; - mmr_t berr_assert_en : 1; - mmr_t reserved_0 : 2; - mmr_t rcnt_scnt_en : 1; - } sh_fsb_system_agent_config_s; -} sh_fsb_system_agent_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_FSB_VGA_REMAP" */ /* FSB VGA Address Space Remap */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_fsb_vga_remap_u { mmr_t sh_fsb_vga_remap_regval; struct { @@ -131,27 +83,12 @@ typedef union sh_fsb_vga_remap_u { mmr_t reserved_2 : 1; } sh_fsb_vga_remap_s; } sh_fsb_vga_remap_u_t; -#else -typedef union sh_fsb_vga_remap_u { - mmr_t sh_fsb_vga_remap_regval; - struct { - mmr_t reserved_2 : 1; - mmr_t vga_remapping_enabled : 1; - mmr_t reserved_1 : 13; - mmr_t nid : 11; - mmr_t asid : 2; - mmr_t offset : 19; - mmr_t reserved_0 : 17; - } sh_fsb_vga_remap_s; -} sh_fsb_vga_remap_u_t; -#endif /* ==================================================================== */ /* Register "SH_FSB_RESET_STATUS" */ /* FSB Reset Status */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_fsb_reset_status_u { mmr_t sh_fsb_reset_status_regval; struct { @@ -159,22 +96,12 @@ typedef union sh_fsb_reset_status_u { mmr_t reserved_0 : 63; } sh_fsb_reset_status_s; } sh_fsb_reset_status_u_t; -#else -typedef union sh_fsb_reset_status_u { - mmr_t sh_fsb_reset_status_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t reset_in_progress : 1; - } sh_fsb_reset_status_s; -} sh_fsb_reset_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_FSB_SYMMETRIC_AGENT_STATUS" */ /* FSB Symmetric Agent Status */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_fsb_symmetric_agent_status_u { mmr_t sh_fsb_symmetric_agent_status_regval; struct { @@ -184,24 +111,12 @@ typedef union sh_fsb_symmetric_agent_status_u { mmr_t reserved_0 : 61; } sh_fsb_symmetric_agent_status_s; } sh_fsb_symmetric_agent_status_u_t; -#else -typedef union sh_fsb_symmetric_agent_status_u { - mmr_t sh_fsb_symmetric_agent_status_regval; - struct { - mmr_t reserved_0 : 61; - mmr_t cpus_ready : 1; - mmr_t cpu_1_active : 1; - mmr_t cpu_0_active : 1; - } sh_fsb_symmetric_agent_status_s; -} sh_fsb_symmetric_agent_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_CREDIT_COUNT_0" */ /* Graphics-write Credit Count for CPU 0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_credit_count_0_u { mmr_t sh_gfx_credit_count_0_regval; struct { @@ -210,23 +125,12 @@ typedef union sh_gfx_credit_count_0_u { mmr_t reset_gfx_state : 1; } sh_gfx_credit_count_0_s; } sh_gfx_credit_count_0_u_t; -#else -typedef union sh_gfx_credit_count_0_u { - mmr_t sh_gfx_credit_count_0_regval; - struct { - mmr_t reset_gfx_state : 1; - mmr_t reserved_0 : 43; - mmr_t count : 20; - } sh_gfx_credit_count_0_s; -} sh_gfx_credit_count_0_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_CREDIT_COUNT_1" */ /* Graphics-write Credit Count for CPU 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_credit_count_1_u { mmr_t sh_gfx_credit_count_1_regval; struct { @@ -235,23 +139,12 @@ typedef union sh_gfx_credit_count_1_u { mmr_t reset_gfx_state : 1; } sh_gfx_credit_count_1_s; } sh_gfx_credit_count_1_u_t; -#else -typedef union sh_gfx_credit_count_1_u { - mmr_t sh_gfx_credit_count_1_regval; - struct { - mmr_t reset_gfx_state : 1; - mmr_t reserved_0 : 43; - mmr_t count : 20; - } sh_gfx_credit_count_1_s; -} sh_gfx_credit_count_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_MODE_CNTRL_0" */ /* Graphics credit mode amd message ordering for CPU 0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_mode_cntrl_0_u { mmr_t sh_gfx_mode_cntrl_0_regval; struct { @@ -261,24 +154,12 @@ typedef union sh_gfx_mode_cntrl_0_u { mmr_t reserved_0 : 61; } sh_gfx_mode_cntrl_0_s; } sh_gfx_mode_cntrl_0_u_t; -#else -typedef union sh_gfx_mode_cntrl_0_u { - mmr_t sh_gfx_mode_cntrl_0_regval; - struct { - mmr_t reserved_0 : 61; - mmr_t relaxed_ordering : 1; - mmr_t mixed_mode_credits : 1; - mmr_t dword_credits : 1; - } sh_gfx_mode_cntrl_0_s; -} sh_gfx_mode_cntrl_0_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_MODE_CNTRL_1" */ /* Graphics credit mode amd message ordering for CPU 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_mode_cntrl_1_u { mmr_t sh_gfx_mode_cntrl_1_regval; struct { @@ -288,24 +169,12 @@ typedef union sh_gfx_mode_cntrl_1_u { mmr_t reserved_0 : 61; } sh_gfx_mode_cntrl_1_s; } sh_gfx_mode_cntrl_1_u_t; -#else -typedef union sh_gfx_mode_cntrl_1_u { - mmr_t sh_gfx_mode_cntrl_1_regval; - struct { - mmr_t reserved_0 : 61; - mmr_t relaxed_ordering : 1; - mmr_t mixed_mode_credits : 1; - mmr_t dword_credits : 1; - } sh_gfx_mode_cntrl_1_s; -} sh_gfx_mode_cntrl_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_SKID_CREDIT_COUNT_0" */ /* Graphics-write Skid Credit Count for CPU 0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_skid_credit_count_0_u { mmr_t sh_gfx_skid_credit_count_0_regval; struct { @@ -313,22 +182,12 @@ typedef union sh_gfx_skid_credit_count_0_u { mmr_t reserved_0 : 44; } sh_gfx_skid_credit_count_0_s; } sh_gfx_skid_credit_count_0_u_t; -#else -typedef union sh_gfx_skid_credit_count_0_u { - mmr_t sh_gfx_skid_credit_count_0_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t skid : 20; - } sh_gfx_skid_credit_count_0_s; -} sh_gfx_skid_credit_count_0_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_SKID_CREDIT_COUNT_1" */ /* Graphics-write Skid Credit Count for CPU 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_skid_credit_count_1_u { mmr_t sh_gfx_skid_credit_count_1_regval; struct { @@ -336,22 +195,12 @@ typedef union sh_gfx_skid_credit_count_1_u { mmr_t reserved_0 : 44; } sh_gfx_skid_credit_count_1_s; } sh_gfx_skid_credit_count_1_u_t; -#else -typedef union sh_gfx_skid_credit_count_1_u { - mmr_t sh_gfx_skid_credit_count_1_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t skid : 20; - } sh_gfx_skid_credit_count_1_s; -} sh_gfx_skid_credit_count_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_STALL_LIMIT_0" */ /* Graphics-write Stall Limit for CPU 0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_stall_limit_0_u { mmr_t sh_gfx_stall_limit_0_regval; struct { @@ -359,22 +208,12 @@ typedef union sh_gfx_stall_limit_0_u { mmr_t reserved_0 : 38; } sh_gfx_stall_limit_0_s; } sh_gfx_stall_limit_0_u_t; -#else -typedef union sh_gfx_stall_limit_0_u { - mmr_t sh_gfx_stall_limit_0_regval; - struct { - mmr_t reserved_0 : 38; - mmr_t limit : 26; - } sh_gfx_stall_limit_0_s; -} sh_gfx_stall_limit_0_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_STALL_LIMIT_1" */ /* Graphics-write Stall Limit for CPU 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_stall_limit_1_u { mmr_t sh_gfx_stall_limit_1_regval; struct { @@ -382,22 +221,12 @@ typedef union sh_gfx_stall_limit_1_u { mmr_t reserved_0 : 38; } sh_gfx_stall_limit_1_s; } sh_gfx_stall_limit_1_u_t; -#else -typedef union sh_gfx_stall_limit_1_u { - mmr_t sh_gfx_stall_limit_1_regval; - struct { - mmr_t reserved_0 : 38; - mmr_t limit : 26; - } sh_gfx_stall_limit_1_s; -} sh_gfx_stall_limit_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_STALL_TIMER_0" */ /* Graphics-write Stall Timer for CPU 0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_stall_timer_0_u { mmr_t sh_gfx_stall_timer_0_regval; struct { @@ -405,22 +234,12 @@ typedef union sh_gfx_stall_timer_0_u { mmr_t reserved_0 : 38; } sh_gfx_stall_timer_0_s; } sh_gfx_stall_timer_0_u_t; -#else -typedef union sh_gfx_stall_timer_0_u { - mmr_t sh_gfx_stall_timer_0_regval; - struct { - mmr_t reserved_0 : 38; - mmr_t timer_value : 26; - } sh_gfx_stall_timer_0_s; -} sh_gfx_stall_timer_0_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_STALL_TIMER_1" */ /* Graphics-write Stall Timer for CPU 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_stall_timer_1_u { mmr_t sh_gfx_stall_timer_1_regval; struct { @@ -428,22 +247,12 @@ typedef union sh_gfx_stall_timer_1_u { mmr_t reserved_0 : 38; } sh_gfx_stall_timer_1_s; } sh_gfx_stall_timer_1_u_t; -#else -typedef union sh_gfx_stall_timer_1_u { - mmr_t sh_gfx_stall_timer_1_regval; - struct { - mmr_t reserved_0 : 38; - mmr_t timer_value : 26; - } sh_gfx_stall_timer_1_s; -} sh_gfx_stall_timer_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_WINDOW_0" */ /* Graphics-write Window for CPU 0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_window_0_u { mmr_t sh_gfx_window_0_regval; struct { @@ -453,24 +262,12 @@ typedef union sh_gfx_window_0_u { mmr_t gfx_window_en : 1; } sh_gfx_window_0_s; } sh_gfx_window_0_u_t; -#else -typedef union sh_gfx_window_0_u { - mmr_t sh_gfx_window_0_regval; - struct { - mmr_t gfx_window_en : 1; - mmr_t reserved_1 : 27; - mmr_t base_addr : 12; - mmr_t reserved_0 : 24; - } sh_gfx_window_0_s; -} sh_gfx_window_0_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_WINDOW_1" */ /* Graphics-write Window for CPU 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_window_1_u { mmr_t sh_gfx_window_1_regval; struct { @@ -480,24 +277,12 @@ typedef union sh_gfx_window_1_u { mmr_t gfx_window_en : 1; } sh_gfx_window_1_s; } sh_gfx_window_1_u_t; -#else -typedef union sh_gfx_window_1_u { - mmr_t sh_gfx_window_1_regval; - struct { - mmr_t gfx_window_en : 1; - mmr_t reserved_1 : 27; - mmr_t base_addr : 12; - mmr_t reserved_0 : 24; - } sh_gfx_window_1_s; -} sh_gfx_window_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_INTERRUPT_TIMER_LIMIT_0" */ /* Graphics-write Interrupt Limit for CPU 0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_interrupt_timer_limit_0_u { mmr_t sh_gfx_interrupt_timer_limit_0_regval; struct { @@ -505,22 +290,12 @@ typedef union sh_gfx_interrupt_timer_limit_0_u { mmr_t reserved_0 : 56; } sh_gfx_interrupt_timer_limit_0_s; } sh_gfx_interrupt_timer_limit_0_u_t; -#else -typedef union sh_gfx_interrupt_timer_limit_0_u { - mmr_t sh_gfx_interrupt_timer_limit_0_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t interrupt_timer_limit : 8; - } sh_gfx_interrupt_timer_limit_0_s; -} sh_gfx_interrupt_timer_limit_0_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_INTERRUPT_TIMER_LIMIT_1" */ /* Graphics-write Interrupt Limit for CPU 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_interrupt_timer_limit_1_u { mmr_t sh_gfx_interrupt_timer_limit_1_regval; struct { @@ -528,22 +303,12 @@ typedef union sh_gfx_interrupt_timer_limit_1_u { mmr_t reserved_0 : 56; } sh_gfx_interrupt_timer_limit_1_s; } sh_gfx_interrupt_timer_limit_1_u_t; -#else -typedef union sh_gfx_interrupt_timer_limit_1_u { - mmr_t sh_gfx_interrupt_timer_limit_1_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t interrupt_timer_limit : 8; - } sh_gfx_interrupt_timer_limit_1_s; -} sh_gfx_interrupt_timer_limit_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_WRITE_STATUS_0" */ /* Graphics Write Status for CPU 0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_write_status_0_u { mmr_t sh_gfx_write_status_0_regval; struct { @@ -552,23 +317,12 @@ typedef union sh_gfx_write_status_0_u { mmr_t re_enable_gfx_stall : 1; } sh_gfx_write_status_0_s; } sh_gfx_write_status_0_u_t; -#else -typedef union sh_gfx_write_status_0_u { - mmr_t sh_gfx_write_status_0_regval; - struct { - mmr_t re_enable_gfx_stall : 1; - mmr_t reserved_0 : 62; - mmr_t busy : 1; - } sh_gfx_write_status_0_s; -} sh_gfx_write_status_0_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_WRITE_STATUS_1" */ /* Graphics Write Status for CPU 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_write_status_1_u { mmr_t sh_gfx_write_status_1_regval; struct { @@ -577,23 +331,12 @@ typedef union sh_gfx_write_status_1_u { mmr_t re_enable_gfx_stall : 1; } sh_gfx_write_status_1_s; } sh_gfx_write_status_1_u_t; -#else -typedef union sh_gfx_write_status_1_u { - mmr_t sh_gfx_write_status_1_regval; - struct { - mmr_t re_enable_gfx_stall : 1; - mmr_t reserved_0 : 62; - mmr_t busy : 1; - } sh_gfx_write_status_1_s; -} sh_gfx_write_status_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_II_INT0" */ /* SHub II Interrupt 0 Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ii_int0_u { mmr_t sh_ii_int0_regval; struct { @@ -602,23 +345,12 @@ typedef union sh_ii_int0_u { mmr_t reserved_0 : 55; } sh_ii_int0_s; } sh_ii_int0_u_t; -#else -typedef union sh_ii_int0_u { - mmr_t sh_ii_int0_regval; - struct { - mmr_t reserved_0 : 55; - mmr_t send : 1; - mmr_t idx : 8; - } sh_ii_int0_s; -} sh_ii_int0_u_t; -#endif /* ==================================================================== */ /* Register "SH_II_INT0_CONFIG" */ /* SHub II Interrupt 0 Config Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ii_int0_config_u { mmr_t sh_ii_int0_config_regval; struct { @@ -630,26 +362,12 @@ typedef union sh_ii_int0_config_u { mmr_t reserved_1 : 14; } sh_ii_int0_config_s; } sh_ii_int0_config_u_t; -#else -typedef union sh_ii_int0_config_u { - mmr_t sh_ii_int0_config_regval; - struct { - mmr_t reserved_1 : 14; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_ii_int0_config_s; -} sh_ii_int0_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_II_INT0_ENABLE" */ /* SHub II Interrupt 0 Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ii_int0_enable_u { mmr_t sh_ii_int0_enable_regval; struct { @@ -657,22 +375,12 @@ typedef union sh_ii_int0_enable_u { mmr_t reserved_0 : 63; } sh_ii_int0_enable_s; } sh_ii_int0_enable_u_t; -#else -typedef union sh_ii_int0_enable_u { - mmr_t sh_ii_int0_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t ii_enable : 1; - } sh_ii_int0_enable_s; -} sh_ii_int0_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_II_INT1" */ /* SHub II Interrupt 1 Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ii_int1_u { mmr_t sh_ii_int1_regval; struct { @@ -681,23 +389,12 @@ typedef union sh_ii_int1_u { mmr_t reserved_0 : 55; } sh_ii_int1_s; } sh_ii_int1_u_t; -#else -typedef union sh_ii_int1_u { - mmr_t sh_ii_int1_regval; - struct { - mmr_t reserved_0 : 55; - mmr_t send : 1; - mmr_t idx : 8; - } sh_ii_int1_s; -} sh_ii_int1_u_t; -#endif /* ==================================================================== */ /* Register "SH_II_INT1_CONFIG" */ /* SHub II Interrupt 1 Config Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ii_int1_config_u { mmr_t sh_ii_int1_config_regval; struct { @@ -709,26 +406,12 @@ typedef union sh_ii_int1_config_u { mmr_t reserved_1 : 14; } sh_ii_int1_config_s; } sh_ii_int1_config_u_t; -#else -typedef union sh_ii_int1_config_u { - mmr_t sh_ii_int1_config_regval; - struct { - mmr_t reserved_1 : 14; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_ii_int1_config_s; -} sh_ii_int1_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_II_INT1_ENABLE" */ /* SHub II Interrupt 1 Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ii_int1_enable_u { mmr_t sh_ii_int1_enable_regval; struct { @@ -736,22 +419,12 @@ typedef union sh_ii_int1_enable_u { mmr_t reserved_0 : 63; } sh_ii_int1_enable_s; } sh_ii_int1_enable_u_t; -#else -typedef union sh_ii_int1_enable_u { - mmr_t sh_ii_int1_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t ii_enable : 1; - } sh_ii_int1_enable_s; -} sh_ii_int1_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_INT_NODE_ID_CONFIG" */ /* SHub Interrupt Node ID Configuration */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_int_node_id_config_u { mmr_t sh_int_node_id_config_regval; struct { @@ -760,23 +433,12 @@ typedef union sh_int_node_id_config_u { mmr_t reserved_0 : 52; } sh_int_node_id_config_s; } sh_int_node_id_config_u_t; -#else -typedef union sh_int_node_id_config_u { - mmr_t sh_int_node_id_config_regval; - struct { - mmr_t reserved_0 : 52; - mmr_t id_sel : 1; - mmr_t node_id : 11; - } sh_int_node_id_config_s; -} sh_int_node_id_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_IPI_INT" */ /* SHub Inter-Processor Interrupt Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ipi_int_u { mmr_t sh_ipi_int_regval; struct { @@ -791,29 +453,12 @@ typedef union sh_ipi_int_u { mmr_t send : 1; } sh_ipi_int_s; } sh_ipi_int_u_t; -#else -typedef union sh_ipi_int_u { - mmr_t sh_ipi_int_regval; - struct { - mmr_t send : 1; - mmr_t reserved_2 : 3; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_ipi_int_s; -} sh_ipi_int_u_t; -#endif /* ==================================================================== */ /* Register "SH_IPI_INT_ENABLE" */ /* SHub Inter-Processor Interrupt Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ipi_int_enable_u { mmr_t sh_ipi_int_enable_regval; struct { @@ -821,22 +466,12 @@ typedef union sh_ipi_int_enable_u { mmr_t reserved_0 : 63; } sh_ipi_int_enable_s; } sh_ipi_int_enable_u_t; -#else -typedef union sh_ipi_int_enable_u { - mmr_t sh_ipi_int_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t pio_enable : 1; - } sh_ipi_int_enable_s; -} sh_ipi_int_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_LOCAL_INT0_CONFIG" */ /* SHub Local Interrupt 0 Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_local_int0_config_u { mmr_t sh_local_int0_config_regval; struct { @@ -850,28 +485,12 @@ typedef union sh_local_int0_config_u { mmr_t reserved_2 : 4; } sh_local_int0_config_s; } sh_local_int0_config_u_t; -#else -typedef union sh_local_int0_config_u { - mmr_t sh_local_int0_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_local_int0_config_s; -} sh_local_int0_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_LOCAL_INT0_ENABLE" */ /* SHub Local Interrupt 0 Enable */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_local_int0_enable_u { mmr_t sh_local_int0_enable_regval; struct { @@ -894,37 +513,12 @@ typedef union sh_local_int0_enable_u { mmr_t reserved_1 : 48; } sh_local_int0_enable_s; } sh_local_int0_enable_u_t; -#else -typedef union sh_local_int0_enable_u { - mmr_t sh_local_int0_enable_regval; - struct { - mmr_t reserved_1 : 48; - mmr_t stop_clock : 1; - mmr_t l1_nmi_int : 1; - mmr_t uart_int : 1; - mmr_t system_shutdown_int : 1; - mmr_t reserved_0 : 1; - mmr_t xn_uce_int : 1; - mmr_t md_uce_int : 1; - mmr_t pi_uce_int : 1; - mmr_t xn_ce_int : 1; - mmr_t md_ce_int : 1; - mmr_t pi_ce_int : 1; - mmr_t ii_hw_int : 1; - mmr_t lb_hw_int : 1; - mmr_t xn_hw_int : 1; - mmr_t md_hw_int : 1; - mmr_t pi_hw_int : 1; - } sh_local_int0_enable_s; -} sh_local_int0_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_LOCAL_INT1_CONFIG" */ /* SHub Local Interrupt 1 Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_local_int1_config_u { mmr_t sh_local_int1_config_regval; struct { @@ -938,28 +532,12 @@ typedef union sh_local_int1_config_u { mmr_t reserved_2 : 4; } sh_local_int1_config_s; } sh_local_int1_config_u_t; -#else -typedef union sh_local_int1_config_u { - mmr_t sh_local_int1_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_local_int1_config_s; -} sh_local_int1_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_LOCAL_INT1_ENABLE" */ /* SHub Local Interrupt 1 Enable */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_local_int1_enable_u { mmr_t sh_local_int1_enable_regval; struct { @@ -982,37 +560,12 @@ typedef union sh_local_int1_enable_u { mmr_t reserved_1 : 48; } sh_local_int1_enable_s; } sh_local_int1_enable_u_t; -#else -typedef union sh_local_int1_enable_u { - mmr_t sh_local_int1_enable_regval; - struct { - mmr_t reserved_1 : 48; - mmr_t stop_clock : 1; - mmr_t l1_nmi_int : 1; - mmr_t uart_int : 1; - mmr_t system_shutdown_int : 1; - mmr_t reserved_0 : 1; - mmr_t xn_uce_int : 1; - mmr_t md_uce_int : 1; - mmr_t pi_uce_int : 1; - mmr_t xn_ce_int : 1; - mmr_t md_ce_int : 1; - mmr_t pi_ce_int : 1; - mmr_t ii_hw_int : 1; - mmr_t lb_hw_int : 1; - mmr_t xn_hw_int : 1; - mmr_t md_hw_int : 1; - mmr_t pi_hw_int : 1; - } sh_local_int1_enable_s; -} sh_local_int1_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_LOCAL_INT2_CONFIG" */ /* SHub Local Interrupt 2 Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_local_int2_config_u { mmr_t sh_local_int2_config_regval; struct { @@ -1026,28 +579,12 @@ typedef union sh_local_int2_config_u { mmr_t reserved_2 : 4; } sh_local_int2_config_s; } sh_local_int2_config_u_t; -#else -typedef union sh_local_int2_config_u { - mmr_t sh_local_int2_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_local_int2_config_s; -} sh_local_int2_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_LOCAL_INT2_ENABLE" */ /* SHub Local Interrupt 2 Enable */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_local_int2_enable_u { mmr_t sh_local_int2_enable_regval; struct { @@ -1070,37 +607,12 @@ typedef union sh_local_int2_enable_u { mmr_t reserved_1 : 48; } sh_local_int2_enable_s; } sh_local_int2_enable_u_t; -#else -typedef union sh_local_int2_enable_u { - mmr_t sh_local_int2_enable_regval; - struct { - mmr_t reserved_1 : 48; - mmr_t stop_clock : 1; - mmr_t l1_nmi_int : 1; - mmr_t uart_int : 1; - mmr_t system_shutdown_int : 1; - mmr_t reserved_0 : 1; - mmr_t xn_uce_int : 1; - mmr_t md_uce_int : 1; - mmr_t pi_uce_int : 1; - mmr_t xn_ce_int : 1; - mmr_t md_ce_int : 1; - mmr_t pi_ce_int : 1; - mmr_t ii_hw_int : 1; - mmr_t lb_hw_int : 1; - mmr_t xn_hw_int : 1; - mmr_t md_hw_int : 1; - mmr_t pi_hw_int : 1; - } sh_local_int2_enable_s; -} sh_local_int2_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_LOCAL_INT3_CONFIG" */ /* SHub Local Interrupt 3 Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_local_int3_config_u { mmr_t sh_local_int3_config_regval; struct { @@ -1114,28 +626,12 @@ typedef union sh_local_int3_config_u { mmr_t reserved_2 : 4; } sh_local_int3_config_s; } sh_local_int3_config_u_t; -#else -typedef union sh_local_int3_config_u { - mmr_t sh_local_int3_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_local_int3_config_s; -} sh_local_int3_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_LOCAL_INT3_ENABLE" */ /* SHub Local Interrupt 3 Enable */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_local_int3_enable_u { mmr_t sh_local_int3_enable_regval; struct { @@ -1158,37 +654,12 @@ typedef union sh_local_int3_enable_u { mmr_t reserved_1 : 48; } sh_local_int3_enable_s; } sh_local_int3_enable_u_t; -#else -typedef union sh_local_int3_enable_u { - mmr_t sh_local_int3_enable_regval; - struct { - mmr_t reserved_1 : 48; - mmr_t stop_clock : 1; - mmr_t l1_nmi_int : 1; - mmr_t uart_int : 1; - mmr_t system_shutdown_int : 1; - mmr_t reserved_0 : 1; - mmr_t xn_uce_int : 1; - mmr_t md_uce_int : 1; - mmr_t pi_uce_int : 1; - mmr_t xn_ce_int : 1; - mmr_t md_ce_int : 1; - mmr_t pi_ce_int : 1; - mmr_t ii_hw_int : 1; - mmr_t lb_hw_int : 1; - mmr_t xn_hw_int : 1; - mmr_t md_hw_int : 1; - mmr_t pi_hw_int : 1; - } sh_local_int3_enable_s; -} sh_local_int3_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_LOCAL_INT4_CONFIG" */ /* SHub Local Interrupt 4 Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_local_int4_config_u { mmr_t sh_local_int4_config_regval; struct { @@ -1202,28 +673,12 @@ typedef union sh_local_int4_config_u { mmr_t reserved_2 : 4; } sh_local_int4_config_s; } sh_local_int4_config_u_t; -#else -typedef union sh_local_int4_config_u { - mmr_t sh_local_int4_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_local_int4_config_s; -} sh_local_int4_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_LOCAL_INT4_ENABLE" */ /* SHub Local Interrupt 4 Enable */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_local_int4_enable_u { mmr_t sh_local_int4_enable_regval; struct { @@ -1246,37 +701,12 @@ typedef union sh_local_int4_enable_u { mmr_t reserved_1 : 48; } sh_local_int4_enable_s; } sh_local_int4_enable_u_t; -#else -typedef union sh_local_int4_enable_u { - mmr_t sh_local_int4_enable_regval; - struct { - mmr_t reserved_1 : 48; - mmr_t stop_clock : 1; - mmr_t l1_nmi_int : 1; - mmr_t uart_int : 1; - mmr_t system_shutdown_int : 1; - mmr_t reserved_0 : 1; - mmr_t xn_uce_int : 1; - mmr_t md_uce_int : 1; - mmr_t pi_uce_int : 1; - mmr_t xn_ce_int : 1; - mmr_t md_ce_int : 1; - mmr_t pi_ce_int : 1; - mmr_t ii_hw_int : 1; - mmr_t lb_hw_int : 1; - mmr_t xn_hw_int : 1; - mmr_t md_hw_int : 1; - mmr_t pi_hw_int : 1; - } sh_local_int4_enable_s; -} sh_local_int4_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_LOCAL_INT5_CONFIG" */ /* SHub Local Interrupt 5 Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_local_int5_config_u { mmr_t sh_local_int5_config_regval; struct { @@ -1290,28 +720,12 @@ typedef union sh_local_int5_config_u { mmr_t reserved_2 : 4; } sh_local_int5_config_s; } sh_local_int5_config_u_t; -#else -typedef union sh_local_int5_config_u { - mmr_t sh_local_int5_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_local_int5_config_s; -} sh_local_int5_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_LOCAL_INT5_ENABLE" */ /* SHub Local Interrupt 5 Enable */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_local_int5_enable_u { mmr_t sh_local_int5_enable_regval; struct { @@ -1334,37 +748,12 @@ typedef union sh_local_int5_enable_u { mmr_t reserved_1 : 48; } sh_local_int5_enable_s; } sh_local_int5_enable_u_t; -#else -typedef union sh_local_int5_enable_u { - mmr_t sh_local_int5_enable_regval; - struct { - mmr_t reserved_1 : 48; - mmr_t stop_clock : 1; - mmr_t l1_nmi_int : 1; - mmr_t uart_int : 1; - mmr_t system_shutdown_int : 1; - mmr_t reserved_0 : 1; - mmr_t xn_uce_int : 1; - mmr_t md_uce_int : 1; - mmr_t pi_uce_int : 1; - mmr_t xn_ce_int : 1; - mmr_t md_ce_int : 1; - mmr_t pi_ce_int : 1; - mmr_t ii_hw_int : 1; - mmr_t lb_hw_int : 1; - mmr_t xn_hw_int : 1; - mmr_t md_hw_int : 1; - mmr_t pi_hw_int : 1; - } sh_local_int5_enable_s; -} sh_local_int5_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC0_ERR_INT_CONFIG" */ /* SHub Processor 0 Error Interrupt Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc0_err_int_config_u { mmr_t sh_proc0_err_int_config_regval; struct { @@ -1378,28 +767,12 @@ typedef union sh_proc0_err_int_config_u { mmr_t reserved_2 : 4; } sh_proc0_err_int_config_s; } sh_proc0_err_int_config_u_t; -#else -typedef union sh_proc0_err_int_config_u { - mmr_t sh_proc0_err_int_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_proc0_err_int_config_s; -} sh_proc0_err_int_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC1_ERR_INT_CONFIG" */ /* SHub Processor 1 Error Interrupt Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc1_err_int_config_u { mmr_t sh_proc1_err_int_config_regval; struct { @@ -1413,28 +786,12 @@ typedef union sh_proc1_err_int_config_u { mmr_t reserved_2 : 4; } sh_proc1_err_int_config_s; } sh_proc1_err_int_config_u_t; -#else -typedef union sh_proc1_err_int_config_u { - mmr_t sh_proc1_err_int_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_proc1_err_int_config_s; -} sh_proc1_err_int_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC2_ERR_INT_CONFIG" */ /* SHub Processor 2 Error Interrupt Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc2_err_int_config_u { mmr_t sh_proc2_err_int_config_regval; struct { @@ -1448,28 +805,12 @@ typedef union sh_proc2_err_int_config_u { mmr_t reserved_2 : 4; } sh_proc2_err_int_config_s; } sh_proc2_err_int_config_u_t; -#else -typedef union sh_proc2_err_int_config_u { - mmr_t sh_proc2_err_int_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_proc2_err_int_config_s; -} sh_proc2_err_int_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC3_ERR_INT_CONFIG" */ /* SHub Processor 3 Error Interrupt Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc3_err_int_config_u { mmr_t sh_proc3_err_int_config_regval; struct { @@ -1483,28 +824,12 @@ typedef union sh_proc3_err_int_config_u { mmr_t reserved_2 : 4; } sh_proc3_err_int_config_s; } sh_proc3_err_int_config_u_t; -#else -typedef union sh_proc3_err_int_config_u { - mmr_t sh_proc3_err_int_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_proc3_err_int_config_s; -} sh_proc3_err_int_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC0_ADV_INT_CONFIG" */ /* SHub Processor 0 Advisory Interrupt Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc0_adv_int_config_u { mmr_t sh_proc0_adv_int_config_regval; struct { @@ -1518,28 +843,12 @@ typedef union sh_proc0_adv_int_config_u { mmr_t reserved_2 : 4; } sh_proc0_adv_int_config_s; } sh_proc0_adv_int_config_u_t; -#else -typedef union sh_proc0_adv_int_config_u { - mmr_t sh_proc0_adv_int_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_proc0_adv_int_config_s; -} sh_proc0_adv_int_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC1_ADV_INT_CONFIG" */ /* SHub Processor 1 Advisory Interrupt Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc1_adv_int_config_u { mmr_t sh_proc1_adv_int_config_regval; struct { @@ -1553,28 +862,12 @@ typedef union sh_proc1_adv_int_config_u { mmr_t reserved_2 : 4; } sh_proc1_adv_int_config_s; } sh_proc1_adv_int_config_u_t; -#else -typedef union sh_proc1_adv_int_config_u { - mmr_t sh_proc1_adv_int_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_proc1_adv_int_config_s; -} sh_proc1_adv_int_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC2_ADV_INT_CONFIG" */ /* SHub Processor 2 Advisory Interrupt Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc2_adv_int_config_u { mmr_t sh_proc2_adv_int_config_regval; struct { @@ -1588,28 +881,12 @@ typedef union sh_proc2_adv_int_config_u { mmr_t reserved_2 : 4; } sh_proc2_adv_int_config_s; } sh_proc2_adv_int_config_u_t; -#else -typedef union sh_proc2_adv_int_config_u { - mmr_t sh_proc2_adv_int_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_proc2_adv_int_config_s; -} sh_proc2_adv_int_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC3_ADV_INT_CONFIG" */ /* SHub Processor 3 Advisory Interrupt Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc3_adv_int_config_u { mmr_t sh_proc3_adv_int_config_regval; struct { @@ -1623,28 +900,12 @@ typedef union sh_proc3_adv_int_config_u { mmr_t reserved_2 : 4; } sh_proc3_adv_int_config_s; } sh_proc3_adv_int_config_u_t; -#else -typedef union sh_proc3_adv_int_config_u { - mmr_t sh_proc3_adv_int_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_proc3_adv_int_config_s; -} sh_proc3_adv_int_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC0_ERR_INT_ENABLE" */ /* SHub Processor 0 Error Interrupt Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc0_err_int_enable_u { mmr_t sh_proc0_err_int_enable_regval; struct { @@ -1652,22 +913,12 @@ typedef union sh_proc0_err_int_enable_u { mmr_t reserved_0 : 63; } sh_proc0_err_int_enable_s; } sh_proc0_err_int_enable_u_t; -#else -typedef union sh_proc0_err_int_enable_u { - mmr_t sh_proc0_err_int_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t proc0_err_enable : 1; - } sh_proc0_err_int_enable_s; -} sh_proc0_err_int_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC1_ERR_INT_ENABLE" */ /* SHub Processor 1 Error Interrupt Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc1_err_int_enable_u { mmr_t sh_proc1_err_int_enable_regval; struct { @@ -1675,22 +926,12 @@ typedef union sh_proc1_err_int_enable_u { mmr_t reserved_0 : 63; } sh_proc1_err_int_enable_s; } sh_proc1_err_int_enable_u_t; -#else -typedef union sh_proc1_err_int_enable_u { - mmr_t sh_proc1_err_int_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t proc1_err_enable : 1; - } sh_proc1_err_int_enable_s; -} sh_proc1_err_int_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC2_ERR_INT_ENABLE" */ /* SHub Processor 2 Error Interrupt Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc2_err_int_enable_u { mmr_t sh_proc2_err_int_enable_regval; struct { @@ -1698,22 +939,12 @@ typedef union sh_proc2_err_int_enable_u { mmr_t reserved_0 : 63; } sh_proc2_err_int_enable_s; } sh_proc2_err_int_enable_u_t; -#else -typedef union sh_proc2_err_int_enable_u { - mmr_t sh_proc2_err_int_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t proc2_err_enable : 1; - } sh_proc2_err_int_enable_s; -} sh_proc2_err_int_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC3_ERR_INT_ENABLE" */ /* SHub Processor 3 Error Interrupt Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc3_err_int_enable_u { mmr_t sh_proc3_err_int_enable_regval; struct { @@ -1721,22 +952,12 @@ typedef union sh_proc3_err_int_enable_u { mmr_t reserved_0 : 63; } sh_proc3_err_int_enable_s; } sh_proc3_err_int_enable_u_t; -#else -typedef union sh_proc3_err_int_enable_u { - mmr_t sh_proc3_err_int_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t proc3_err_enable : 1; - } sh_proc3_err_int_enable_s; -} sh_proc3_err_int_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC0_ADV_INT_ENABLE" */ /* SHub Processor 0 Advisory Interrupt Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc0_adv_int_enable_u { mmr_t sh_proc0_adv_int_enable_regval; struct { @@ -1744,22 +965,12 @@ typedef union sh_proc0_adv_int_enable_u { mmr_t reserved_0 : 63; } sh_proc0_adv_int_enable_s; } sh_proc0_adv_int_enable_u_t; -#else -typedef union sh_proc0_adv_int_enable_u { - mmr_t sh_proc0_adv_int_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t proc0_adv_enable : 1; - } sh_proc0_adv_int_enable_s; -} sh_proc0_adv_int_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC1_ADV_INT_ENABLE" */ /* SHub Processor 1 Advisory Interrupt Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc1_adv_int_enable_u { mmr_t sh_proc1_adv_int_enable_regval; struct { @@ -1767,22 +978,12 @@ typedef union sh_proc1_adv_int_enable_u { mmr_t reserved_0 : 63; } sh_proc1_adv_int_enable_s; } sh_proc1_adv_int_enable_u_t; -#else -typedef union sh_proc1_adv_int_enable_u { - mmr_t sh_proc1_adv_int_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t proc1_adv_enable : 1; - } sh_proc1_adv_int_enable_s; -} sh_proc1_adv_int_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC2_ADV_INT_ENABLE" */ /* SHub Processor 2 Advisory Interrupt Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc2_adv_int_enable_u { mmr_t sh_proc2_adv_int_enable_regval; struct { @@ -1790,22 +991,12 @@ typedef union sh_proc2_adv_int_enable_u { mmr_t reserved_0 : 63; } sh_proc2_adv_int_enable_s; } sh_proc2_adv_int_enable_u_t; -#else -typedef union sh_proc2_adv_int_enable_u { - mmr_t sh_proc2_adv_int_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t proc2_adv_enable : 1; - } sh_proc2_adv_int_enable_s; -} sh_proc2_adv_int_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC3_ADV_INT_ENABLE" */ /* SHub Processor 3 Advisory Interrupt Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc3_adv_int_enable_u { mmr_t sh_proc3_adv_int_enable_regval; struct { @@ -1813,22 +1004,12 @@ typedef union sh_proc3_adv_int_enable_u { mmr_t reserved_0 : 63; } sh_proc3_adv_int_enable_s; } sh_proc3_adv_int_enable_u_t; -#else -typedef union sh_proc3_adv_int_enable_u { - mmr_t sh_proc3_adv_int_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t proc3_adv_enable : 1; - } sh_proc3_adv_int_enable_s; -} sh_proc3_adv_int_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROFILE_INT_CONFIG" */ /* SHub Profile Interrupt Configuration Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_profile_int_config_u { mmr_t sh_profile_int_config_regval; struct { @@ -1842,28 +1023,12 @@ typedef union sh_profile_int_config_u { mmr_t reserved_2 : 4; } sh_profile_int_config_s; } sh_profile_int_config_u_t; -#else -typedef union sh_profile_int_config_u { - mmr_t sh_profile_int_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_profile_int_config_s; -} sh_profile_int_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROFILE_INT_ENABLE" */ /* SHub Profile Interrupt Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_profile_int_enable_u { mmr_t sh_profile_int_enable_regval; struct { @@ -1871,22 +1036,12 @@ typedef union sh_profile_int_enable_u { mmr_t reserved_0 : 63; } sh_profile_int_enable_s; } sh_profile_int_enable_u_t; -#else -typedef union sh_profile_int_enable_u { - mmr_t sh_profile_int_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t profile_enable : 1; - } sh_profile_int_enable_s; -} sh_profile_int_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_RTC0_INT_CONFIG" */ /* SHub RTC 0 Interrupt Config Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_rtc0_int_config_u { mmr_t sh_rtc0_int_config_regval; struct { @@ -1900,28 +1055,12 @@ typedef union sh_rtc0_int_config_u { mmr_t reserved_2 : 4; } sh_rtc0_int_config_s; } sh_rtc0_int_config_u_t; -#else -typedef union sh_rtc0_int_config_u { - mmr_t sh_rtc0_int_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_rtc0_int_config_s; -} sh_rtc0_int_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_RTC0_INT_ENABLE" */ /* SHub RTC 0 Interrupt Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_rtc0_int_enable_u { mmr_t sh_rtc0_int_enable_regval; struct { @@ -1929,22 +1068,12 @@ typedef union sh_rtc0_int_enable_u { mmr_t reserved_0 : 63; } sh_rtc0_int_enable_s; } sh_rtc0_int_enable_u_t; -#else -typedef union sh_rtc0_int_enable_u { - mmr_t sh_rtc0_int_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t rtc0_enable : 1; - } sh_rtc0_int_enable_s; -} sh_rtc0_int_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_RTC1_INT_CONFIG" */ /* SHub RTC 1 Interrupt Config Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_rtc1_int_config_u { mmr_t sh_rtc1_int_config_regval; struct { @@ -1958,28 +1087,12 @@ typedef union sh_rtc1_int_config_u { mmr_t reserved_2 : 4; } sh_rtc1_int_config_s; } sh_rtc1_int_config_u_t; -#else -typedef union sh_rtc1_int_config_u { - mmr_t sh_rtc1_int_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_rtc1_int_config_s; -} sh_rtc1_int_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_RTC1_INT_ENABLE" */ /* SHub RTC 1 Interrupt Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_rtc1_int_enable_u { mmr_t sh_rtc1_int_enable_regval; struct { @@ -1987,22 +1100,12 @@ typedef union sh_rtc1_int_enable_u { mmr_t reserved_0 : 63; } sh_rtc1_int_enable_s; } sh_rtc1_int_enable_u_t; -#else -typedef union sh_rtc1_int_enable_u { - mmr_t sh_rtc1_int_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t rtc1_enable : 1; - } sh_rtc1_int_enable_s; -} sh_rtc1_int_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_RTC2_INT_CONFIG" */ /* SHub RTC 2 Interrupt Config Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_rtc2_int_config_u { mmr_t sh_rtc2_int_config_regval; struct { @@ -2016,28 +1119,12 @@ typedef union sh_rtc2_int_config_u { mmr_t reserved_2 : 4; } sh_rtc2_int_config_s; } sh_rtc2_int_config_u_t; -#else -typedef union sh_rtc2_int_config_u { - mmr_t sh_rtc2_int_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_rtc2_int_config_s; -} sh_rtc2_int_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_RTC2_INT_ENABLE" */ /* SHub RTC 2 Interrupt Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_rtc2_int_enable_u { mmr_t sh_rtc2_int_enable_regval; struct { @@ -2045,22 +1132,12 @@ typedef union sh_rtc2_int_enable_u { mmr_t reserved_0 : 63; } sh_rtc2_int_enable_s; } sh_rtc2_int_enable_u_t; -#else -typedef union sh_rtc2_int_enable_u { - mmr_t sh_rtc2_int_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t rtc2_enable : 1; - } sh_rtc2_int_enable_s; -} sh_rtc2_int_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_RTC3_INT_CONFIG" */ /* SHub RTC 3 Interrupt Config Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_rtc3_int_config_u { mmr_t sh_rtc3_int_config_regval; struct { @@ -2074,28 +1151,12 @@ typedef union sh_rtc3_int_config_u { mmr_t reserved_2 : 4; } sh_rtc3_int_config_s; } sh_rtc3_int_config_u_t; -#else -typedef union sh_rtc3_int_config_u { - mmr_t sh_rtc3_int_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_rtc3_int_config_s; -} sh_rtc3_int_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_RTC3_INT_ENABLE" */ /* SHub RTC 3 Interrupt Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_rtc3_int_enable_u { mmr_t sh_rtc3_int_enable_regval; struct { @@ -2103,22 +1164,12 @@ typedef union sh_rtc3_int_enable_u { mmr_t reserved_0 : 63; } sh_rtc3_int_enable_s; } sh_rtc3_int_enable_u_t; -#else -typedef union sh_rtc3_int_enable_u { - mmr_t sh_rtc3_int_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t rtc3_enable : 1; - } sh_rtc3_int_enable_s; -} sh_rtc3_int_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_EVENT_OCCURRED" */ /* SHub Interrupt Event Occurred */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_event_occurred_u { mmr_t sh_event_occurred_regval; struct { @@ -2156,52 +1207,12 @@ typedef union sh_event_occurred_u { mmr_t reserved_0 : 33; } sh_event_occurred_s; } sh_event_occurred_u_t; -#else -typedef union sh_event_occurred_u { - mmr_t sh_event_occurred_regval; - struct { - mmr_t reserved_0 : 33; - mmr_t ii_int1 : 1; - mmr_t ii_int0 : 1; - mmr_t ipi_int : 1; - mmr_t profile_int : 1; - mmr_t rtc3_int : 1; - mmr_t rtc2_int : 1; - mmr_t rtc1_int : 1; - mmr_t rtc0_int : 1; - mmr_t stop_clock : 1; - mmr_t l1_nmi_int : 1; - mmr_t uart_int : 1; - mmr_t system_shutdown_int : 1; - mmr_t proc3_err_int : 1; - mmr_t proc2_err_int : 1; - mmr_t proc1_err_int : 1; - mmr_t proc0_err_int : 1; - mmr_t proc3_adv_int : 1; - mmr_t proc2_adv_int : 1; - mmr_t proc1_adv_int : 1; - mmr_t proc0_adv_int : 1; - mmr_t xn_uce_int : 1; - mmr_t md_uce_int : 1; - mmr_t pi_uce_int : 1; - mmr_t xn_ce_int : 1; - mmr_t md_ce_int : 1; - mmr_t pi_ce_int : 1; - mmr_t ii_hw_int : 1; - mmr_t lb_hw_int : 1; - mmr_t xn_hw_int : 1; - mmr_t md_hw_int : 1; - mmr_t pi_hw_int : 1; - } sh_event_occurred_s; -} sh_event_occurred_u_t; -#endif /* ==================================================================== */ /* Register "SH_EVENT_OVERFLOW" */ /* SHub Interrupt Event Occurred Overflow */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_event_overflow_u { mmr_t sh_event_overflow_regval; struct { @@ -2236,49 +1247,12 @@ typedef union sh_event_overflow_u { mmr_t reserved_0 : 36; } sh_event_overflow_s; } sh_event_overflow_u_t; -#else -typedef union sh_event_overflow_u { - mmr_t sh_event_overflow_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t profile_int : 1; - mmr_t rtc3_int : 1; - mmr_t rtc2_int : 1; - mmr_t rtc1_int : 1; - mmr_t rtc0_int : 1; - mmr_t stop_clock : 1; - mmr_t l1_nmi_int : 1; - mmr_t uart_int : 1; - mmr_t system_shutdown_int : 1; - mmr_t proc3_err_int : 1; - mmr_t proc2_err_int : 1; - mmr_t proc1_err_int : 1; - mmr_t proc0_err_int : 1; - mmr_t proc3_adv_int : 1; - mmr_t proc2_adv_int : 1; - mmr_t proc1_adv_int : 1; - mmr_t proc0_adv_int : 1; - mmr_t xn_uce_int : 1; - mmr_t md_uce_int : 1; - mmr_t pi_uce_int : 1; - mmr_t xn_ce_int : 1; - mmr_t md_ce_int : 1; - mmr_t pi_ce_int : 1; - mmr_t ii_hw_int : 1; - mmr_t lb_hw_int : 1; - mmr_t xn_hw_int : 1; - mmr_t md_hw_int : 1; - mmr_t pi_hw_int : 1; - } sh_event_overflow_s; -} sh_event_overflow_u_t; -#endif /* ==================================================================== */ /* Register "SH_JUNK_BUS_TIME" */ /* Junk Bus Timing */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_junk_bus_time_u { mmr_t sh_junk_bus_time_regval; struct { @@ -2289,25 +1263,12 @@ typedef union sh_junk_bus_time_u { mmr_t reserved_0 : 32; } sh_junk_bus_time_s; } sh_junk_bus_time_u_t; -#else -typedef union sh_junk_bus_time_u { - mmr_t sh_junk_bus_time_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t uart_enable : 8; - mmr_t uart_setup_hold : 8; - mmr_t fprom_enable : 8; - mmr_t fprom_setup_hold : 8; - } sh_junk_bus_time_s; -} sh_junk_bus_time_u_t; -#endif /* ==================================================================== */ /* Register "SH_JUNK_LATCH_TIME" */ /* Junk Bus Latch Timing */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_junk_latch_time_u { mmr_t sh_junk_latch_time_regval; struct { @@ -2315,22 +1276,12 @@ typedef union sh_junk_latch_time_u { mmr_t reserved_0 : 61; } sh_junk_latch_time_s; } sh_junk_latch_time_u_t; -#else -typedef union sh_junk_latch_time_u { - mmr_t sh_junk_latch_time_regval; - struct { - mmr_t reserved_0 : 61; - mmr_t setup_hold : 3; - } sh_junk_latch_time_s; -} sh_junk_latch_time_u_t; -#endif /* ==================================================================== */ /* Register "SH_JUNK_NACK_RESET" */ /* Junk Bus Nack Counter Reset */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_junk_nack_reset_u { mmr_t sh_junk_nack_reset_regval; struct { @@ -2338,22 +1289,12 @@ typedef union sh_junk_nack_reset_u { mmr_t reserved_0 : 63; } sh_junk_nack_reset_s; } sh_junk_nack_reset_u_t; -#else -typedef union sh_junk_nack_reset_u { - mmr_t sh_junk_nack_reset_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t pulse : 1; - } sh_junk_nack_reset_s; -} sh_junk_nack_reset_u_t; -#endif /* ==================================================================== */ /* Register "SH_JUNK_BUS_LED0" */ /* Junk Bus LED0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_junk_bus_led0_u { mmr_t sh_junk_bus_led0_regval; struct { @@ -2361,22 +1302,12 @@ typedef union sh_junk_bus_led0_u { mmr_t reserved_0 : 56; } sh_junk_bus_led0_s; } sh_junk_bus_led0_u_t; -#else -typedef union sh_junk_bus_led0_u { - mmr_t sh_junk_bus_led0_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t led0_data : 8; - } sh_junk_bus_led0_s; -} sh_junk_bus_led0_u_t; -#endif /* ==================================================================== */ /* Register "SH_JUNK_BUS_LED1" */ /* Junk Bus LED1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_junk_bus_led1_u { mmr_t sh_junk_bus_led1_regval; struct { @@ -2384,22 +1315,12 @@ typedef union sh_junk_bus_led1_u { mmr_t reserved_0 : 56; } sh_junk_bus_led1_s; } sh_junk_bus_led1_u_t; -#else -typedef union sh_junk_bus_led1_u { - mmr_t sh_junk_bus_led1_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t led1_data : 8; - } sh_junk_bus_led1_s; -} sh_junk_bus_led1_u_t; -#endif /* ==================================================================== */ /* Register "SH_JUNK_BUS_LED2" */ /* Junk Bus LED2 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_junk_bus_led2_u { mmr_t sh_junk_bus_led2_regval; struct { @@ -2407,22 +1328,12 @@ typedef union sh_junk_bus_led2_u { mmr_t reserved_0 : 56; } sh_junk_bus_led2_s; } sh_junk_bus_led2_u_t; -#else -typedef union sh_junk_bus_led2_u { - mmr_t sh_junk_bus_led2_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t led2_data : 8; - } sh_junk_bus_led2_s; -} sh_junk_bus_led2_u_t; -#endif /* ==================================================================== */ /* Register "SH_JUNK_BUS_LED3" */ /* Junk Bus LED3 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_junk_bus_led3_u { mmr_t sh_junk_bus_led3_regval; struct { @@ -2430,22 +1341,12 @@ typedef union sh_junk_bus_led3_u { mmr_t reserved_0 : 56; } sh_junk_bus_led3_s; } sh_junk_bus_led3_u_t; -#else -typedef union sh_junk_bus_led3_u { - mmr_t sh_junk_bus_led3_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t led3_data : 8; - } sh_junk_bus_led3_s; -} sh_junk_bus_led3_u_t; -#endif /* ==================================================================== */ /* Register "SH_JUNK_ERROR_STATUS" */ /* Junk Bus Error Status */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_junk_error_status_u { mmr_t sh_junk_error_status_regval; struct { @@ -2457,26 +1358,12 @@ typedef union sh_junk_error_status_u { mmr_t reserved_1 : 3; } sh_junk_error_status_s; } sh_junk_error_status_u_t; -#else -typedef union sh_junk_error_status_u { - mmr_t sh_junk_error_status_regval; - struct { - mmr_t reserved_1 : 3; - mmr_t status : 4; - mmr_t mode : 1; - mmr_t cmd : 8; - mmr_t reserved_0 : 1; - mmr_t address : 47; - } sh_junk_error_status_s; -} sh_junk_error_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_LLP_STAT" */ /* This register describes the LLP status. */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_llp_stat_u { mmr_t sh_ni0_llp_stat_regval; struct { @@ -2484,22 +1371,12 @@ typedef union sh_ni0_llp_stat_u { mmr_t reserved_0 : 60; } sh_ni0_llp_stat_s; } sh_ni0_llp_stat_u_t; -#else -typedef union sh_ni0_llp_stat_u { - mmr_t sh_ni0_llp_stat_regval; - struct { - mmr_t reserved_0 : 60; - mmr_t link_reset_state : 4; - } sh_ni0_llp_stat_s; -} sh_ni0_llp_stat_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_LLP_RESET" */ /* Writing issues a reset to the network interface */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_llp_reset_u { mmr_t sh_ni0_llp_reset_regval; struct { @@ -2508,23 +1385,12 @@ typedef union sh_ni0_llp_reset_u { mmr_t reserved_0 : 62; } sh_ni0_llp_reset_s; } sh_ni0_llp_reset_u_t; -#else -typedef union sh_ni0_llp_reset_u { - mmr_t sh_ni0_llp_reset_regval; - struct { - mmr_t reserved_0 : 62; - mmr_t warm : 1; - mmr_t link : 1; - } sh_ni0_llp_reset_s; -} sh_ni0_llp_reset_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_LLP_RESET_EN" */ /* Controls LLP warm reset propagation */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_llp_reset_en_u { mmr_t sh_ni0_llp_reset_en_regval; struct { @@ -2532,22 +1398,12 @@ typedef union sh_ni0_llp_reset_en_u { mmr_t reserved_0 : 63; } sh_ni0_llp_reset_en_s; } sh_ni0_llp_reset_en_u_t; -#else -typedef union sh_ni0_llp_reset_en_u { - mmr_t sh_ni0_llp_reset_en_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t ok : 1; - } sh_ni0_llp_reset_en_s; -} sh_ni0_llp_reset_en_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_LLP_CHAN_MODE" */ /* Sets the signaling mode of LLP and channel */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_llp_chan_mode_u { mmr_t sh_ni0_llp_chan_mode_regval; struct { @@ -2559,26 +1415,12 @@ typedef union sh_ni0_llp_chan_mode_u { mmr_t reserved_0 : 59; } sh_ni0_llp_chan_mode_s; } sh_ni0_llp_chan_mode_u_t; -#else -typedef union sh_ni0_llp_chan_mode_u { - mmr_t sh_ni0_llp_chan_mode_regval; - struct { - mmr_t reserved_0 : 59; - mmr_t enable_clkquad : 1; - mmr_t enable_rmt_ft_upd : 1; - mmr_t enable_tuning : 1; - mmr_t ac_encode : 1; - mmr_t bitmode32 : 1; - } sh_ni0_llp_chan_mode_s; -} sh_ni0_llp_chan_mode_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_LLP_CONFIG" */ /* Sets the configuration of LLP and channel */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_llp_config_u { mmr_t sh_ni0_llp_config_regval; struct { @@ -2589,24 +1431,11 @@ typedef union sh_ni0_llp_config_u { mmr_t reserved_0 : 26; } sh_ni0_llp_config_s; } sh_ni0_llp_config_u_t; -#else -typedef union sh_ni0_llp_config_u { - mmr_t sh_ni0_llp_config_regval; - struct { - mmr_t reserved_0 : 26; - mmr_t ftu_time : 12; - mmr_t nulltimeout : 6; - mmr_t maxretry : 10; - mmr_t maxburst : 10; - } sh_ni0_llp_config_s; -} sh_ni0_llp_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_LLP_TEST_CTL" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_llp_test_ctl_u { mmr_t sh_ni0_llp_test_ctl_regval; struct { @@ -2627,77 +1456,36 @@ typedef union sh_ni0_llp_test_ctl_u { mmr_t reserved_2 : 1; } sh_ni0_llp_test_ctl_s; } sh_ni0_llp_test_ctl_u_t; -#else -typedef union sh_ni0_llp_test_ctl_u { - mmr_t sh_ni0_llp_test_ctl_regval; - struct { - mmr_t reserved_2 : 1; - mmr_t cberror : 1; - mmr_t captured : 1; - mmr_t fakesnerror : 1; - mmr_t sendsnerror : 1; - mmr_t sendcberror : 1; - mmr_t capturecbonly : 1; - mmr_t armcapture : 1; - mmr_t noise_mode : 2; - mmr_t lfsr_mode : 2; - mmr_t reserved_1 : 2; - mmr_t wire_sel : 6; - mmr_t reserved_0 : 2; - mmr_t send_test_mode : 2; - mmr_t pattern : 40; - } sh_ni0_llp_test_ctl_s; -} sh_ni0_llp_test_ctl_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_LLP_CAPT_WD1" */ /* low order 64-bit captured word */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_ni0_llp_capt_wd1_u { - mmr_t sh_ni0_llp_capt_wd1_regval; - struct { - mmr_t data : 64; - } sh_ni0_llp_capt_wd1_s; -} sh_ni0_llp_capt_wd1_u_t; -#else typedef union sh_ni0_llp_capt_wd1_u { mmr_t sh_ni0_llp_capt_wd1_regval; struct { mmr_t data : 64; } sh_ni0_llp_capt_wd1_s; } sh_ni0_llp_capt_wd1_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_LLP_CAPT_WD2" */ /* high order 64-bit captured word */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_llp_capt_wd2_u { mmr_t sh_ni0_llp_capt_wd2_regval; struct { mmr_t data : 64; } sh_ni0_llp_capt_wd2_s; } sh_ni0_llp_capt_wd2_u_t; -#else -typedef union sh_ni0_llp_capt_wd2_u { - mmr_t sh_ni0_llp_capt_wd2_regval; - struct { - mmr_t data : 64; - } sh_ni0_llp_capt_wd2_s; -} sh_ni0_llp_capt_wd2_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_LLP_CAPT_SBCB" */ /* captured sideband, sequence, and CRC */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_llp_capt_sbcb_u { mmr_t sh_ni0_llp_capt_sbcb_regval; struct { @@ -2711,27 +1499,11 @@ typedef union sh_ni0_llp_capt_sbcb_u { mmr_t reserved_0 : 27; } sh_ni0_llp_capt_sbcb_s; } sh_ni0_llp_capt_sbcb_u_t; -#else -typedef union sh_ni0_llp_capt_sbcb_u { - mmr_t sh_ni0_llp_capt_sbcb_regval; - struct { - mmr_t reserved_0 : 27; - mmr_t chargeunderflow : 1; - mmr_t chargeoverflow : 1; - mmr_t fakedallsnerrors : 1; - mmr_t sentallsnerrors : 1; - mmr_t sentallcberrors : 1; - mmr_t capturedrcvcrc : 16; - mmr_t capturedrcvsbsn : 16; - } sh_ni0_llp_capt_sbcb_s; -} sh_ni0_llp_capt_sbcb_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_LLP_ERR" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_llp_err_u { mmr_t sh_ni0_llp_err_regval; struct { @@ -2747,30 +1519,12 @@ typedef union sh_ni0_llp_err_u { mmr_t reserved_0 : 11; } sh_ni0_llp_err_s; } sh_ni0_llp_err_u_t; -#else -typedef union sh_ni0_llp_err_u { - mmr_t sh_ni0_llp_err_regval; - struct { - mmr_t reserved_0 : 11; - mmr_t wire_overflow : 1; - mmr_t wire_cnt : 24; - mmr_t power_not_ok : 1; - mmr_t squash : 1; - mmr_t rcv_link_reset : 1; - mmr_t retry_timeout : 1; - mmr_t retry_count : 8; - mmr_t rx_cb_err_count : 8; - mmr_t rx_sn_err_count : 8; - } sh_ni0_llp_err_s; -} sh_ni0_llp_err_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_LLP_STAT" */ /* This register describes the LLP status. */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_llp_stat_u { mmr_t sh_ni1_llp_stat_regval; struct { @@ -2778,22 +1532,12 @@ typedef union sh_ni1_llp_stat_u { mmr_t reserved_0 : 60; } sh_ni1_llp_stat_s; } sh_ni1_llp_stat_u_t; -#else -typedef union sh_ni1_llp_stat_u { - mmr_t sh_ni1_llp_stat_regval; - struct { - mmr_t reserved_0 : 60; - mmr_t link_reset_state : 4; - } sh_ni1_llp_stat_s; -} sh_ni1_llp_stat_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_LLP_RESET" */ /* Writing issues a reset to the network interface */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_llp_reset_u { mmr_t sh_ni1_llp_reset_regval; struct { @@ -2802,23 +1546,12 @@ typedef union sh_ni1_llp_reset_u { mmr_t reserved_0 : 62; } sh_ni1_llp_reset_s; } sh_ni1_llp_reset_u_t; -#else -typedef union sh_ni1_llp_reset_u { - mmr_t sh_ni1_llp_reset_regval; - struct { - mmr_t reserved_0 : 62; - mmr_t warm : 1; - mmr_t link : 1; - } sh_ni1_llp_reset_s; -} sh_ni1_llp_reset_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_LLP_RESET_EN" */ /* Controls LLP warm reset propagation */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_llp_reset_en_u { mmr_t sh_ni1_llp_reset_en_regval; struct { @@ -2826,22 +1559,12 @@ typedef union sh_ni1_llp_reset_en_u { mmr_t reserved_0 : 63; } sh_ni1_llp_reset_en_s; } sh_ni1_llp_reset_en_u_t; -#else -typedef union sh_ni1_llp_reset_en_u { - mmr_t sh_ni1_llp_reset_en_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t ok : 1; - } sh_ni1_llp_reset_en_s; -} sh_ni1_llp_reset_en_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_LLP_CHAN_MODE" */ /* Sets the signaling mode of LLP and channel */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_llp_chan_mode_u { mmr_t sh_ni1_llp_chan_mode_regval; struct { @@ -2853,26 +1576,12 @@ typedef union sh_ni1_llp_chan_mode_u { mmr_t reserved_0 : 59; } sh_ni1_llp_chan_mode_s; } sh_ni1_llp_chan_mode_u_t; -#else -typedef union sh_ni1_llp_chan_mode_u { - mmr_t sh_ni1_llp_chan_mode_regval; - struct { - mmr_t reserved_0 : 59; - mmr_t enable_clkquad : 1; - mmr_t enable_rmt_ft_upd : 1; - mmr_t enable_tuning : 1; - mmr_t ac_encode : 1; - mmr_t bitmode32 : 1; - } sh_ni1_llp_chan_mode_s; -} sh_ni1_llp_chan_mode_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_LLP_CONFIG" */ /* Sets the configuration of LLP and channel */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_llp_config_u { mmr_t sh_ni1_llp_config_regval; struct { @@ -2883,24 +1592,11 @@ typedef union sh_ni1_llp_config_u { mmr_t reserved_0 : 26; } sh_ni1_llp_config_s; } sh_ni1_llp_config_u_t; -#else -typedef union sh_ni1_llp_config_u { - mmr_t sh_ni1_llp_config_regval; - struct { - mmr_t reserved_0 : 26; - mmr_t ftu_time : 12; - mmr_t nulltimeout : 6; - mmr_t maxretry : 10; - mmr_t maxburst : 10; - } sh_ni1_llp_config_s; -} sh_ni1_llp_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_LLP_TEST_CTL" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_llp_test_ctl_u { mmr_t sh_ni1_llp_test_ctl_regval; struct { @@ -2921,77 +1617,36 @@ typedef union sh_ni1_llp_test_ctl_u { mmr_t reserved_2 : 1; } sh_ni1_llp_test_ctl_s; } sh_ni1_llp_test_ctl_u_t; -#else -typedef union sh_ni1_llp_test_ctl_u { - mmr_t sh_ni1_llp_test_ctl_regval; - struct { - mmr_t reserved_2 : 1; - mmr_t cberror : 1; - mmr_t captured : 1; - mmr_t fakesnerror : 1; - mmr_t sendsnerror : 1; - mmr_t sendcberror : 1; - mmr_t capturecbonly : 1; - mmr_t armcapture : 1; - mmr_t noise_mode : 2; - mmr_t lfsr_mode : 2; - mmr_t reserved_1 : 2; - mmr_t wire_sel : 6; - mmr_t reserved_0 : 2; - mmr_t send_test_mode : 2; - mmr_t pattern : 40; - } sh_ni1_llp_test_ctl_s; -} sh_ni1_llp_test_ctl_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_LLP_CAPT_WD1" */ /* low order 64-bit captured word */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_ni1_llp_capt_wd1_u { - mmr_t sh_ni1_llp_capt_wd1_regval; - struct { - mmr_t data : 64; - } sh_ni1_llp_capt_wd1_s; -} sh_ni1_llp_capt_wd1_u_t; -#else typedef union sh_ni1_llp_capt_wd1_u { mmr_t sh_ni1_llp_capt_wd1_regval; struct { mmr_t data : 64; } sh_ni1_llp_capt_wd1_s; } sh_ni1_llp_capt_wd1_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_LLP_CAPT_WD2" */ /* high order 64-bit captured word */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_ni1_llp_capt_wd2_u { - mmr_t sh_ni1_llp_capt_wd2_regval; - struct { - mmr_t data : 64; - } sh_ni1_llp_capt_wd2_s; -} sh_ni1_llp_capt_wd2_u_t; -#else typedef union sh_ni1_llp_capt_wd2_u { mmr_t sh_ni1_llp_capt_wd2_regval; struct { mmr_t data : 64; } sh_ni1_llp_capt_wd2_s; } sh_ni1_llp_capt_wd2_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_LLP_CAPT_SBCB" */ /* captured sideband, sequence, and CRC */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_llp_capt_sbcb_u { mmr_t sh_ni1_llp_capt_sbcb_regval; struct { @@ -3005,27 +1660,11 @@ typedef union sh_ni1_llp_capt_sbcb_u { mmr_t reserved_0 : 27; } sh_ni1_llp_capt_sbcb_s; } sh_ni1_llp_capt_sbcb_u_t; -#else -typedef union sh_ni1_llp_capt_sbcb_u { - mmr_t sh_ni1_llp_capt_sbcb_regval; - struct { - mmr_t reserved_0 : 27; - mmr_t chargeunderflow : 1; - mmr_t chargeoverflow : 1; - mmr_t fakedallsnerrors : 1; - mmr_t sentallsnerrors : 1; - mmr_t sentallcberrors : 1; - mmr_t capturedrcvcrc : 16; - mmr_t capturedrcvsbsn : 16; - } sh_ni1_llp_capt_sbcb_s; -} sh_ni1_llp_capt_sbcb_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_LLP_ERR" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_llp_err_u { mmr_t sh_ni1_llp_err_regval; struct { @@ -3041,29 +1680,11 @@ typedef union sh_ni1_llp_err_u { mmr_t reserved_0 : 11; } sh_ni1_llp_err_s; } sh_ni1_llp_err_u_t; -#else -typedef union sh_ni1_llp_err_u { - mmr_t sh_ni1_llp_err_regval; - struct { - mmr_t reserved_0 : 11; - mmr_t wire_overflow : 1; - mmr_t wire_cnt : 24; - mmr_t power_not_ok : 1; - mmr_t squash : 1; - mmr_t rcv_link_reset : 1; - mmr_t retry_timeout : 1; - mmr_t retry_count : 8; - mmr_t rx_cb_err_count : 8; - mmr_t rx_sn_err_count : 8; - } sh_ni1_llp_err_s; -} sh_ni1_llp_err_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_LLP_TO_FIFO02_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_llp_to_fifo02_flow_u { mmr_t sh_xnni0_llp_to_fifo02_flow_regval; struct { @@ -3084,34 +1705,11 @@ typedef union sh_xnni0_llp_to_fifo02_flow_u { mmr_t reserved_6 : 2; } sh_xnni0_llp_to_fifo02_flow_s; } sh_xnni0_llp_to_fifo02_flow_u_t; -#else -typedef union sh_xnni0_llp_to_fifo02_flow_u { - mmr_t sh_xnni0_llp_to_fifo02_flow_regval; - struct { - mmr_t reserved_6 : 2; - mmr_t credit_vc2_cap : 6; - mmr_t reserved_5 : 2; - mmr_t credit_vc2_dyn : 6; - mmr_t reserved_4 : 10; - mmr_t credit_vc0_cap : 6; - mmr_t reserved_3 : 2; - mmr_t credit_vc0_dyn : 6; - mmr_t reserved_2 : 8; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnni0_llp_to_fifo02_flow_s; -} sh_xnni0_llp_to_fifo02_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_LLP_TO_FIFO13_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_llp_to_fifo13_flow_u { mmr_t sh_xnni0_llp_to_fifo13_flow_regval; struct { @@ -3132,34 +1730,11 @@ typedef union sh_xnni0_llp_to_fifo13_flow_u { mmr_t reserved_6 : 2; } sh_xnni0_llp_to_fifo13_flow_s; } sh_xnni0_llp_to_fifo13_flow_u_t; -#else -typedef union sh_xnni0_llp_to_fifo13_flow_u { - mmr_t sh_xnni0_llp_to_fifo13_flow_regval; - struct { - mmr_t reserved_6 : 2; - mmr_t credit_vc2_cap : 6; - mmr_t reserved_5 : 2; - mmr_t credit_vc2_dyn : 6; - mmr_t reserved_4 : 10; - mmr_t credit_vc0_cap : 6; - mmr_t reserved_3 : 2; - mmr_t credit_vc0_dyn : 6; - mmr_t reserved_2 : 8; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnni0_llp_to_fifo13_flow_s; -} sh_xnni0_llp_to_fifo13_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_LLP_DEBIT_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_llp_debit_flow_u { mmr_t sh_xnni0_llp_debit_flow_regval; struct { @@ -3181,35 +1756,11 @@ typedef union sh_xnni0_llp_debit_flow_u { mmr_t reserved_7 : 3; } sh_xnni0_llp_debit_flow_s; } sh_xnni0_llp_debit_flow_u_t; -#else -typedef union sh_xnni0_llp_debit_flow_u { - mmr_t sh_xnni0_llp_debit_flow_regval; - struct { - mmr_t reserved_7 : 3; - mmr_t debit_vc3_cap : 5; - mmr_t reserved_6 : 3; - mmr_t debit_vc3_dyn : 5; - mmr_t reserved_5 : 3; - mmr_t debit_vc2_cap : 5; - mmr_t reserved_4 : 3; - mmr_t debit_vc2_dyn : 5; - mmr_t reserved_3 : 3; - mmr_t debit_vc1_cap : 5; - mmr_t reserved_2 : 3; - mmr_t debit_vc1_dyn : 5; - mmr_t reserved_1 : 3; - mmr_t debit_vc0_cap : 5; - mmr_t reserved_0 : 3; - mmr_t debit_vc0_dyn : 5; - } sh_xnni0_llp_debit_flow_s; -} sh_xnni0_llp_debit_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_LINK_0_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_link_0_flow_u { mmr_t sh_xnni0_link_0_flow_regval; struct { @@ -3224,28 +1775,11 @@ typedef union sh_xnni0_link_0_flow_u { mmr_t reserved_3 : 33; } sh_xnni0_link_0_flow_s; } sh_xnni0_link_0_flow_u_t; -#else -typedef union sh_xnni0_link_0_flow_u { - mmr_t sh_xnni0_link_0_flow_regval; - struct { - mmr_t reserved_3 : 33; - mmr_t credit_vc0_cap : 7; - mmr_t reserved_2 : 1; - mmr_t credit_vc0_dyn : 7; - mmr_t reserved_1 : 1; - mmr_t credit_vc0_test : 7; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnni0_link_0_flow_s; -} sh_xnni0_link_0_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_LINK_1_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_link_1_flow_u { mmr_t sh_xnni0_link_1_flow_regval; struct { @@ -3260,28 +1794,11 @@ typedef union sh_xnni0_link_1_flow_u { mmr_t reserved_3 : 33; } sh_xnni0_link_1_flow_s; } sh_xnni0_link_1_flow_u_t; -#else -typedef union sh_xnni0_link_1_flow_u { - mmr_t sh_xnni0_link_1_flow_regval; - struct { - mmr_t reserved_3 : 33; - mmr_t credit_vc1_cap : 7; - mmr_t reserved_2 : 1; - mmr_t credit_vc1_dyn : 7; - mmr_t reserved_1 : 1; - mmr_t credit_vc1_test : 7; - mmr_t debit_vc1_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc1_withhold : 6; - } sh_xnni0_link_1_flow_s; -} sh_xnni0_link_1_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_LINK_2_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_link_2_flow_u { mmr_t sh_xnni0_link_2_flow_regval; struct { @@ -3296,28 +1813,11 @@ typedef union sh_xnni0_link_2_flow_u { mmr_t reserved_3 : 33; } sh_xnni0_link_2_flow_s; } sh_xnni0_link_2_flow_u_t; -#else -typedef union sh_xnni0_link_2_flow_u { - mmr_t sh_xnni0_link_2_flow_regval; - struct { - mmr_t reserved_3 : 33; - mmr_t credit_vc2_cap : 7; - mmr_t reserved_2 : 1; - mmr_t credit_vc2_dyn : 7; - mmr_t reserved_1 : 1; - mmr_t credit_vc2_test : 7; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc2_withhold : 6; - } sh_xnni0_link_2_flow_s; -} sh_xnni0_link_2_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_LINK_3_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_link_3_flow_u { mmr_t sh_xnni0_link_3_flow_regval; struct { @@ -3332,28 +1832,11 @@ typedef union sh_xnni0_link_3_flow_u { mmr_t reserved_3 : 33; } sh_xnni0_link_3_flow_s; } sh_xnni0_link_3_flow_u_t; -#else -typedef union sh_xnni0_link_3_flow_u { - mmr_t sh_xnni0_link_3_flow_regval; - struct { - mmr_t reserved_3 : 33; - mmr_t credit_vc3_cap : 7; - mmr_t reserved_2 : 1; - mmr_t credit_vc3_dyn : 7; - mmr_t reserved_1 : 1; - mmr_t credit_vc3_test : 7; - mmr_t debit_vc3_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc3_withhold : 6; - } sh_xnni0_link_3_flow_s; -} sh_xnni0_link_3_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_LLP_TO_FIFO02_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_llp_to_fifo02_flow_u { mmr_t sh_xnni1_llp_to_fifo02_flow_regval; struct { @@ -3374,34 +1857,11 @@ typedef union sh_xnni1_llp_to_fifo02_flow_u { mmr_t reserved_6 : 2; } sh_xnni1_llp_to_fifo02_flow_s; } sh_xnni1_llp_to_fifo02_flow_u_t; -#else -typedef union sh_xnni1_llp_to_fifo02_flow_u { - mmr_t sh_xnni1_llp_to_fifo02_flow_regval; - struct { - mmr_t reserved_6 : 2; - mmr_t credit_vc2_cap : 6; - mmr_t reserved_5 : 2; - mmr_t credit_vc2_dyn : 6; - mmr_t reserved_4 : 10; - mmr_t credit_vc0_cap : 6; - mmr_t reserved_3 : 2; - mmr_t credit_vc0_dyn : 6; - mmr_t reserved_2 : 8; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnni1_llp_to_fifo02_flow_s; -} sh_xnni1_llp_to_fifo02_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_LLP_TO_FIFO13_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_llp_to_fifo13_flow_u { mmr_t sh_xnni1_llp_to_fifo13_flow_regval; struct { @@ -3422,34 +1882,11 @@ typedef union sh_xnni1_llp_to_fifo13_flow_u { mmr_t reserved_6 : 2; } sh_xnni1_llp_to_fifo13_flow_s; } sh_xnni1_llp_to_fifo13_flow_u_t; -#else -typedef union sh_xnni1_llp_to_fifo13_flow_u { - mmr_t sh_xnni1_llp_to_fifo13_flow_regval; - struct { - mmr_t reserved_6 : 2; - mmr_t credit_vc2_cap : 6; - mmr_t reserved_5 : 2; - mmr_t credit_vc2_dyn : 6; - mmr_t reserved_4 : 10; - mmr_t credit_vc0_cap : 6; - mmr_t reserved_3 : 2; - mmr_t credit_vc0_dyn : 6; - mmr_t reserved_2 : 8; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnni1_llp_to_fifo13_flow_s; -} sh_xnni1_llp_to_fifo13_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_LLP_DEBIT_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_llp_debit_flow_u { mmr_t sh_xnni1_llp_debit_flow_regval; struct { @@ -3471,35 +1908,11 @@ typedef union sh_xnni1_llp_debit_flow_u { mmr_t reserved_7 : 3; } sh_xnni1_llp_debit_flow_s; } sh_xnni1_llp_debit_flow_u_t; -#else -typedef union sh_xnni1_llp_debit_flow_u { - mmr_t sh_xnni1_llp_debit_flow_regval; - struct { - mmr_t reserved_7 : 3; - mmr_t debit_vc3_cap : 5; - mmr_t reserved_6 : 3; - mmr_t debit_vc3_dyn : 5; - mmr_t reserved_5 : 3; - mmr_t debit_vc2_cap : 5; - mmr_t reserved_4 : 3; - mmr_t debit_vc2_dyn : 5; - mmr_t reserved_3 : 3; - mmr_t debit_vc1_cap : 5; - mmr_t reserved_2 : 3; - mmr_t debit_vc1_dyn : 5; - mmr_t reserved_1 : 3; - mmr_t debit_vc0_cap : 5; - mmr_t reserved_0 : 3; - mmr_t debit_vc0_dyn : 5; - } sh_xnni1_llp_debit_flow_s; -} sh_xnni1_llp_debit_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_LINK_0_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_link_0_flow_u { mmr_t sh_xnni1_link_0_flow_regval; struct { @@ -3514,28 +1927,11 @@ typedef union sh_xnni1_link_0_flow_u { mmr_t reserved_3 : 33; } sh_xnni1_link_0_flow_s; } sh_xnni1_link_0_flow_u_t; -#else -typedef union sh_xnni1_link_0_flow_u { - mmr_t sh_xnni1_link_0_flow_regval; - struct { - mmr_t reserved_3 : 33; - mmr_t credit_vc0_cap : 7; - mmr_t reserved_2 : 1; - mmr_t credit_vc0_dyn : 7; - mmr_t reserved_1 : 1; - mmr_t credit_vc0_test : 7; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnni1_link_0_flow_s; -} sh_xnni1_link_0_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_LINK_1_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_link_1_flow_u { mmr_t sh_xnni1_link_1_flow_regval; struct { @@ -3550,28 +1946,11 @@ typedef union sh_xnni1_link_1_flow_u { mmr_t reserved_3 : 33; } sh_xnni1_link_1_flow_s; } sh_xnni1_link_1_flow_u_t; -#else -typedef union sh_xnni1_link_1_flow_u { - mmr_t sh_xnni1_link_1_flow_regval; - struct { - mmr_t reserved_3 : 33; - mmr_t credit_vc1_cap : 7; - mmr_t reserved_2 : 1; - mmr_t credit_vc1_dyn : 7; - mmr_t reserved_1 : 1; - mmr_t credit_vc1_test : 7; - mmr_t debit_vc1_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc1_withhold : 6; - } sh_xnni1_link_1_flow_s; -} sh_xnni1_link_1_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_LINK_2_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_link_2_flow_u { mmr_t sh_xnni1_link_2_flow_regval; struct { @@ -3586,28 +1965,11 @@ typedef union sh_xnni1_link_2_flow_u { mmr_t reserved_3 : 33; } sh_xnni1_link_2_flow_s; } sh_xnni1_link_2_flow_u_t; -#else -typedef union sh_xnni1_link_2_flow_u { - mmr_t sh_xnni1_link_2_flow_regval; - struct { - mmr_t reserved_3 : 33; - mmr_t credit_vc2_cap : 7; - mmr_t reserved_2 : 1; - mmr_t credit_vc2_dyn : 7; - mmr_t reserved_1 : 1; - mmr_t credit_vc2_test : 7; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc2_withhold : 6; - } sh_xnni1_link_2_flow_s; -} sh_xnni1_link_2_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_LINK_3_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_link_3_flow_u { mmr_t sh_xnni1_link_3_flow_regval; struct { @@ -3622,29 +1984,12 @@ typedef union sh_xnni1_link_3_flow_u { mmr_t reserved_3 : 33; } sh_xnni1_link_3_flow_s; } sh_xnni1_link_3_flow_u_t; -#else -typedef union sh_xnni1_link_3_flow_u { - mmr_t sh_xnni1_link_3_flow_regval; - struct { - mmr_t reserved_3 : 33; - mmr_t credit_vc3_cap : 7; - mmr_t reserved_2 : 1; - mmr_t credit_vc3_dyn : 7; - mmr_t reserved_1 : 1; - mmr_t credit_vc3_test : 7; - mmr_t debit_vc3_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc3_withhold : 6; - } sh_xnni1_link_3_flow_s; -} sh_xnni1_link_3_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_IILB_LOCAL_TABLE" */ /* local lookup table */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_iilb_local_table_u { mmr_t sh_iilb_local_table_regval; struct { @@ -3655,25 +2000,12 @@ typedef union sh_iilb_local_table_u { mmr_t valid : 1; } sh_iilb_local_table_s; } sh_iilb_local_table_u_t; -#else -typedef union sh_iilb_local_table_u { - mmr_t sh_iilb_local_table_regval; - struct { - mmr_t valid : 1; - mmr_t reserved_0 : 57; - mmr_t ni_sel0 : 1; - mmr_t v0 : 1; - mmr_t dir0 : 4; - } sh_iilb_local_table_s; -} sh_iilb_local_table_u_t; -#endif /* ==================================================================== */ /* Register "SH_IILB_GLOBAL_TABLE" */ /* global lookup table */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_iilb_global_table_u { mmr_t sh_iilb_global_table_regval; struct { @@ -3684,25 +2016,12 @@ typedef union sh_iilb_global_table_u { mmr_t valid : 1; } sh_iilb_global_table_s; } sh_iilb_global_table_u_t; -#else -typedef union sh_iilb_global_table_u { - mmr_t sh_iilb_global_table_regval; - struct { - mmr_t valid : 1; - mmr_t reserved_0 : 57; - mmr_t ni_sel0 : 1; - mmr_t v0 : 1; - mmr_t dir0 : 4; - } sh_iilb_global_table_s; -} sh_iilb_global_table_u_t; -#endif /* ==================================================================== */ /* Register "SH_IILB_OVER_RIDE_TABLE" */ /* If enabled, bypass the Global/Local tables */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_iilb_over_ride_table_u { mmr_t sh_iilb_over_ride_table_regval; struct { @@ -3713,46 +2032,24 @@ typedef union sh_iilb_over_ride_table_u { mmr_t enable : 1; } sh_iilb_over_ride_table_s; } sh_iilb_over_ride_table_u_t; -#else -typedef union sh_iilb_over_ride_table_u { - mmr_t sh_iilb_over_ride_table_regval; - struct { - mmr_t enable : 1; - mmr_t reserved_0 : 57; - mmr_t ni_sel0 : 1; - mmr_t v0 : 1; - mmr_t dir0 : 4; - } sh_iilb_over_ride_table_s; -} sh_iilb_over_ride_table_u_t; -#endif /* ==================================================================== */ /* Register "SH_IILB_RSP_PLANE_HINT" */ /* If enabled, invert incoming response only plane hint bit before lo */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_iilb_rsp_plane_hint_u { - mmr_t sh_iilb_rsp_plane_hint_regval; - struct { - mmr_t reserved_0 : 64; - } sh_iilb_rsp_plane_hint_s; -} sh_iilb_rsp_plane_hint_u_t; -#else typedef union sh_iilb_rsp_plane_hint_u { mmr_t sh_iilb_rsp_plane_hint_regval; struct { mmr_t reserved_0 : 64; } sh_iilb_rsp_plane_hint_s; } sh_iilb_rsp_plane_hint_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_LOCAL_TABLE" */ /* local lookup table */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_local_table_u { mmr_t sh_pi_local_table_regval; struct { @@ -3767,29 +2064,12 @@ typedef union sh_pi_local_table_u { mmr_t valid : 1; } sh_pi_local_table_s; } sh_pi_local_table_u_t; -#else -typedef union sh_pi_local_table_u { - mmr_t sh_pi_local_table_regval; - struct { - mmr_t valid : 1; - mmr_t reserved_1 : 49; - mmr_t ni_sel1 : 1; - mmr_t v1 : 1; - mmr_t dir1 : 4; - mmr_t reserved_0 : 2; - mmr_t ni_sel0 : 1; - mmr_t v0 : 1; - mmr_t dir0 : 4; - } sh_pi_local_table_s; -} sh_pi_local_table_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_GLOBAL_TABLE" */ /* global lookup table */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_global_table_u { mmr_t sh_pi_global_table_regval; struct { @@ -3804,29 +2084,12 @@ typedef union sh_pi_global_table_u { mmr_t valid : 1; } sh_pi_global_table_s; } sh_pi_global_table_u_t; -#else -typedef union sh_pi_global_table_u { - mmr_t sh_pi_global_table_regval; - struct { - mmr_t valid : 1; - mmr_t reserved_1 : 49; - mmr_t ni_sel1 : 1; - mmr_t v1 : 1; - mmr_t dir1 : 4; - mmr_t reserved_0 : 2; - mmr_t ni_sel0 : 1; - mmr_t v0 : 1; - mmr_t dir0 : 4; - } sh_pi_global_table_s; -} sh_pi_global_table_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_OVER_RIDE_TABLE" */ /* If enabled, bypass the Global/Local tables */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_over_ride_table_u { mmr_t sh_pi_over_ride_table_regval; struct { @@ -3841,29 +2104,12 @@ typedef union sh_pi_over_ride_table_u { mmr_t enable : 1; } sh_pi_over_ride_table_s; } sh_pi_over_ride_table_u_t; -#else -typedef union sh_pi_over_ride_table_u { - mmr_t sh_pi_over_ride_table_regval; - struct { - mmr_t enable : 1; - mmr_t reserved_1 : 49; - mmr_t ni_sel1 : 1; - mmr_t v1 : 1; - mmr_t dir1 : 4; - mmr_t reserved_0 : 2; - mmr_t ni_sel0 : 1; - mmr_t v0 : 1; - mmr_t dir0 : 4; - } sh_pi_over_ride_table_s; -} sh_pi_over_ride_table_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_RSP_PLANE_HINT" */ /* If enabled, invert incoming response only plane hint bit before lo */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_rsp_plane_hint_u { mmr_t sh_pi_rsp_plane_hint_regval; struct { @@ -3871,22 +2117,12 @@ typedef union sh_pi_rsp_plane_hint_u { mmr_t reserved_0 : 63; } sh_pi_rsp_plane_hint_s; } sh_pi_rsp_plane_hint_u_t; -#else -typedef union sh_pi_rsp_plane_hint_u { - mmr_t sh_pi_rsp_plane_hint_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t invert : 1; - } sh_pi_rsp_plane_hint_s; -} sh_pi_rsp_plane_hint_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_LOCAL_TABLE" */ /* local lookup table */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_local_table_u { mmr_t sh_ni0_local_table_regval; struct { @@ -3896,24 +2132,12 @@ typedef union sh_ni0_local_table_u { mmr_t valid : 1; } sh_ni0_local_table_s; } sh_ni0_local_table_u_t; -#else -typedef union sh_ni0_local_table_u { - mmr_t sh_ni0_local_table_regval; - struct { - mmr_t valid : 1; - mmr_t reserved_0 : 58; - mmr_t v0 : 1; - mmr_t dir0 : 4; - } sh_ni0_local_table_s; -} sh_ni0_local_table_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_GLOBAL_TABLE" */ /* global lookup table */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_global_table_u { mmr_t sh_ni0_global_table_regval; struct { @@ -3923,24 +2147,12 @@ typedef union sh_ni0_global_table_u { mmr_t valid : 1; } sh_ni0_global_table_s; } sh_ni0_global_table_u_t; -#else -typedef union sh_ni0_global_table_u { - mmr_t sh_ni0_global_table_regval; - struct { - mmr_t valid : 1; - mmr_t reserved_0 : 58; - mmr_t v0 : 1; - mmr_t dir0 : 4; - } sh_ni0_global_table_s; -} sh_ni0_global_table_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_OVER_RIDE_TABLE" */ /* If enabled, bypass the Global/Local tables */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_over_ride_table_u { mmr_t sh_ni0_over_ride_table_regval; struct { @@ -3950,45 +2162,24 @@ typedef union sh_ni0_over_ride_table_u { mmr_t enable : 1; } sh_ni0_over_ride_table_s; } sh_ni0_over_ride_table_u_t; -#else -typedef union sh_ni0_over_ride_table_u { - mmr_t sh_ni0_over_ride_table_regval; - struct { - mmr_t enable : 1; - mmr_t reserved_0 : 58; - mmr_t v0 : 1; - mmr_t dir0 : 4; - } sh_ni0_over_ride_table_s; -} sh_ni0_over_ride_table_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_RSP_PLANE_HINT" */ /* If enabled, invert incoming response only plane hint bit before lo */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_ni0_rsp_plane_hint_u { - mmr_t sh_ni0_rsp_plane_hint_regval; - struct { - mmr_t reserved_0 : 64; - } sh_ni0_rsp_plane_hint_s; -} sh_ni0_rsp_plane_hint_u_t; -#else typedef union sh_ni0_rsp_plane_hint_u { mmr_t sh_ni0_rsp_plane_hint_regval; struct { mmr_t reserved_0 : 64; } sh_ni0_rsp_plane_hint_s; } sh_ni0_rsp_plane_hint_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_LOCAL_TABLE" */ /* local lookup table */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_local_table_u { mmr_t sh_ni1_local_table_regval; struct { @@ -3998,24 +2189,12 @@ typedef union sh_ni1_local_table_u { mmr_t valid : 1; } sh_ni1_local_table_s; } sh_ni1_local_table_u_t; -#else -typedef union sh_ni1_local_table_u { - mmr_t sh_ni1_local_table_regval; - struct { - mmr_t valid : 1; - mmr_t reserved_0 : 58; - mmr_t v0 : 1; - mmr_t dir0 : 4; - } sh_ni1_local_table_s; -} sh_ni1_local_table_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_GLOBAL_TABLE" */ /* global lookup table */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_global_table_u { mmr_t sh_ni1_global_table_regval; struct { @@ -4025,24 +2204,12 @@ typedef union sh_ni1_global_table_u { mmr_t valid : 1; } sh_ni1_global_table_s; } sh_ni1_global_table_u_t; -#else -typedef union sh_ni1_global_table_u { - mmr_t sh_ni1_global_table_regval; - struct { - mmr_t valid : 1; - mmr_t reserved_0 : 58; - mmr_t v0 : 1; - mmr_t dir0 : 4; - } sh_ni1_global_table_s; -} sh_ni1_global_table_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_OVER_RIDE_TABLE" */ /* If enabled, bypass the Global/Local tables */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_over_ride_table_u { mmr_t sh_ni1_over_ride_table_regval; struct { @@ -4052,45 +2219,24 @@ typedef union sh_ni1_over_ride_table_u { mmr_t enable : 1; } sh_ni1_over_ride_table_s; } sh_ni1_over_ride_table_u_t; -#else -typedef union sh_ni1_over_ride_table_u { - mmr_t sh_ni1_over_ride_table_regval; - struct { - mmr_t enable : 1; - mmr_t reserved_0 : 58; - mmr_t v0 : 1; - mmr_t dir0 : 4; - } sh_ni1_over_ride_table_s; -} sh_ni1_over_ride_table_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_RSP_PLANE_HINT" */ /* If enabled, invert incoming response only plane hint bit before lo */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_ni1_rsp_plane_hint_u { - mmr_t sh_ni1_rsp_plane_hint_regval; - struct { - mmr_t reserved_0 : 64; - } sh_ni1_rsp_plane_hint_s; -} sh_ni1_rsp_plane_hint_u_t; -#else typedef union sh_ni1_rsp_plane_hint_u { mmr_t sh_ni1_rsp_plane_hint_regval; struct { mmr_t reserved_0 : 64; } sh_ni1_rsp_plane_hint_s; } sh_ni1_rsp_plane_hint_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_LOCAL_TABLE" */ /* local lookup table */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_local_table_u { mmr_t sh_md_local_table_regval; struct { @@ -4105,29 +2251,12 @@ typedef union sh_md_local_table_u { mmr_t valid : 1; } sh_md_local_table_s; } sh_md_local_table_u_t; -#else -typedef union sh_md_local_table_u { - mmr_t sh_md_local_table_regval; - struct { - mmr_t valid : 1; - mmr_t reserved_1 : 49; - mmr_t ni_sel1 : 1; - mmr_t v1 : 1; - mmr_t dir1 : 4; - mmr_t reserved_0 : 2; - mmr_t ni_sel0 : 1; - mmr_t v0 : 1; - mmr_t dir0 : 4; - } sh_md_local_table_s; -} sh_md_local_table_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_GLOBAL_TABLE" */ /* global lookup table */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_global_table_u { mmr_t sh_md_global_table_regval; struct { @@ -4142,29 +2271,12 @@ typedef union sh_md_global_table_u { mmr_t valid : 1; } sh_md_global_table_s; } sh_md_global_table_u_t; -#else -typedef union sh_md_global_table_u { - mmr_t sh_md_global_table_regval; - struct { - mmr_t valid : 1; - mmr_t reserved_1 : 49; - mmr_t ni_sel1 : 1; - mmr_t v1 : 1; - mmr_t dir1 : 4; - mmr_t reserved_0 : 2; - mmr_t ni_sel0 : 1; - mmr_t v0 : 1; - mmr_t dir0 : 4; - } sh_md_global_table_s; -} sh_md_global_table_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_OVER_RIDE_TABLE" */ /* If enabled, bypass the Global/Local tables */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_over_ride_table_u { mmr_t sh_md_over_ride_table_regval; struct { @@ -4179,29 +2291,12 @@ typedef union sh_md_over_ride_table_u { mmr_t enable : 1; } sh_md_over_ride_table_s; } sh_md_over_ride_table_u_t; -#else -typedef union sh_md_over_ride_table_u { - mmr_t sh_md_over_ride_table_regval; - struct { - mmr_t enable : 1; - mmr_t reserved_1 : 49; - mmr_t ni_sel1 : 1; - mmr_t v1 : 1; - mmr_t dir1 : 4; - mmr_t reserved_0 : 2; - mmr_t ni_sel0 : 1; - mmr_t v0 : 1; - mmr_t dir0 : 4; - } sh_md_over_ride_table_s; -} sh_md_over_ride_table_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_RSP_PLANE_HINT" */ /* If enabled, invert incoming response only plane hint bit before lo */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_rsp_plane_hint_u { mmr_t sh_md_rsp_plane_hint_regval; struct { @@ -4209,22 +2304,12 @@ typedef union sh_md_rsp_plane_hint_u { mmr_t reserved_0 : 63; } sh_md_rsp_plane_hint_s; } sh_md_rsp_plane_hint_u_t; -#else -typedef union sh_md_rsp_plane_hint_u { - mmr_t sh_md_rsp_plane_hint_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t invert : 1; - } sh_md_rsp_plane_hint_s; -} sh_md_rsp_plane_hint_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_LIQ_CTL" */ /* Local Block LIQ Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_liq_ctl_u { mmr_t sh_lb_liq_ctl_regval; struct { @@ -4238,28 +2323,12 @@ typedef union sh_lb_liq_ctl_u { mmr_t reserved_2 : 45; } sh_lb_liq_ctl_s; } sh_lb_liq_ctl_u_t; -#else -typedef union sh_lb_liq_ctl_u { - mmr_t sh_lb_liq_ctl_regval; - struct { - mmr_t reserved_2 : 45; - mmr_t force_linvv_credit : 1; - mmr_t force_rp_credit : 1; - mmr_t force_rq_credit : 1; - mmr_t reserved_1 : 4; - mmr_t liq_rpl_ctl : 4; - mmr_t reserved_0 : 3; - mmr_t liq_req_ctl : 5; - } sh_lb_liq_ctl_s; -} sh_lb_liq_ctl_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_LOQ_CTL" */ /* Local Block LOQ Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_loq_ctl_u { mmr_t sh_lb_loq_ctl_regval; struct { @@ -4268,23 +2337,12 @@ typedef union sh_lb_loq_ctl_u { mmr_t reserved_0 : 62; } sh_lb_loq_ctl_s; } sh_lb_loq_ctl_u_t; -#else -typedef union sh_lb_loq_ctl_u { - mmr_t sh_lb_loq_ctl_regval; - struct { - mmr_t reserved_0 : 62; - mmr_t loq_rpl_ctl : 1; - mmr_t loq_req_ctl : 1; - } sh_lb_loq_ctl_s; -} sh_lb_loq_ctl_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_MAX_REP_CREDIT_CNT" */ /* Maximum number of reply credits from XN */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_max_rep_credit_cnt_u { mmr_t sh_lb_max_rep_credit_cnt_regval; struct { @@ -4292,22 +2350,12 @@ typedef union sh_lb_max_rep_credit_cnt_u { mmr_t reserved_0 : 59; } sh_lb_max_rep_credit_cnt_s; } sh_lb_max_rep_credit_cnt_u_t; -#else -typedef union sh_lb_max_rep_credit_cnt_u { - mmr_t sh_lb_max_rep_credit_cnt_regval; - struct { - mmr_t reserved_0 : 59; - mmr_t max_cnt : 5; - } sh_lb_max_rep_credit_cnt_s; -} sh_lb_max_rep_credit_cnt_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_MAX_REQ_CREDIT_CNT" */ /* Maximum number of request credits from XN */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_max_req_credit_cnt_u { mmr_t sh_lb_max_req_credit_cnt_regval; struct { @@ -4315,22 +2363,12 @@ typedef union sh_lb_max_req_credit_cnt_u { mmr_t reserved_0 : 59; } sh_lb_max_req_credit_cnt_s; } sh_lb_max_req_credit_cnt_u_t; -#else -typedef union sh_lb_max_req_credit_cnt_u { - mmr_t sh_lb_max_req_credit_cnt_regval; - struct { - mmr_t reserved_0 : 59; - mmr_t max_cnt : 5; - } sh_lb_max_req_credit_cnt_s; -} sh_lb_max_req_credit_cnt_u_t; -#endif /* ==================================================================== */ /* Register "SH_PIO_TIME_OUT" */ /* Local Block PIO time out value */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pio_time_out_u { mmr_t sh_pio_time_out_regval; struct { @@ -4338,22 +2376,12 @@ typedef union sh_pio_time_out_u { mmr_t reserved_0 : 48; } sh_pio_time_out_s; } sh_pio_time_out_u_t; -#else -typedef union sh_pio_time_out_u { - mmr_t sh_pio_time_out_regval; - struct { - mmr_t reserved_0 : 48; - mmr_t value : 16; - } sh_pio_time_out_s; -} sh_pio_time_out_u_t; -#endif /* ==================================================================== */ /* Register "SH_PIO_NACK_RESET" */ /* Local Block PIO Reset for nack counters */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pio_nack_reset_u { mmr_t sh_pio_nack_reset_regval; struct { @@ -4361,22 +2389,12 @@ typedef union sh_pio_nack_reset_u { mmr_t reserved_0 : 63; } sh_pio_nack_reset_s; } sh_pio_nack_reset_u_t; -#else -typedef union sh_pio_nack_reset_u { - mmr_t sh_pio_nack_reset_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t pulse : 1; - } sh_pio_nack_reset_s; -} sh_pio_nack_reset_u_t; -#endif /* ==================================================================== */ /* Register "SH_CONVEYOR_BELT_TIME_OUT" */ /* Local Block conveyor belt time out value */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_conveyor_belt_time_out_u { mmr_t sh_conveyor_belt_time_out_regval; struct { @@ -4384,22 +2402,12 @@ typedef union sh_conveyor_belt_time_out_u { mmr_t reserved_0 : 52; } sh_conveyor_belt_time_out_s; } sh_conveyor_belt_time_out_u_t; -#else -typedef union sh_conveyor_belt_time_out_u { - mmr_t sh_conveyor_belt_time_out_regval; - struct { - mmr_t reserved_0 : 52; - mmr_t value : 12; - } sh_conveyor_belt_time_out_s; -} sh_conveyor_belt_time_out_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_CREDIT_STATUS" */ /* Credit Counter Status Register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_credit_status_u { mmr_t sh_lb_credit_status_regval; struct { @@ -4413,28 +2421,12 @@ typedef union sh_lb_credit_status_u { mmr_t reserved_2 : 36; } sh_lb_credit_status_s; } sh_lb_credit_status_u_t; -#else -typedef union sh_lb_credit_status_u { - mmr_t sh_lb_credit_status_regval; - struct { - mmr_t reserved_2 : 36; - mmr_t loq_rp_credit : 5; - mmr_t loq_rq_credit : 5; - mmr_t linvv_credit : 6; - mmr_t reserved_1 : 2; - mmr_t liq_rp_credit : 4; - mmr_t reserved_0 : 1; - mmr_t liq_rq_credit : 5; - } sh_lb_credit_status_s; -} sh_lb_credit_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_DEBUG_LOCAL_SEL" */ /* LB Debug Port Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_debug_local_sel_u { mmr_t sh_lb_debug_local_sel_regval; struct { @@ -4472,52 +2464,12 @@ typedef union sh_lb_debug_local_sel_u { mmr_t trigger_enable : 1; } sh_lb_debug_local_sel_s; } sh_lb_debug_local_sel_u_t; -#else -typedef union sh_lb_debug_local_sel_u { - mmr_t sh_lb_debug_local_sel_regval; - struct { - mmr_t trigger_enable : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_chiplet_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_chiplet_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_chiplet_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_chiplet_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_chiplet_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_chiplet_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_chiplet_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_chiplet_sel : 3; - } sh_lb_debug_local_sel_s; -} sh_lb_debug_local_sel_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_DEBUG_PERF_SEL" */ /* LB Debug Port Performance Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_debug_perf_sel_u { mmr_t sh_lb_debug_perf_sel_regval; struct { @@ -4555,52 +2507,12 @@ typedef union sh_lb_debug_perf_sel_u { mmr_t reserved_15 : 1; } sh_lb_debug_perf_sel_s; } sh_lb_debug_perf_sel_u_t; -#else -typedef union sh_lb_debug_perf_sel_u { - mmr_t sh_lb_debug_perf_sel_regval; - struct { - mmr_t reserved_15 : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_chiplet_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_chiplet_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_chiplet_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_chiplet_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_chiplet_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_chiplet_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_chiplet_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_chiplet_sel : 3; - } sh_lb_debug_perf_sel_s; -} sh_lb_debug_perf_sel_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_DEBUG_TRIG_SEL" */ /* LB Debug Trigger Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_debug_trig_sel_u { mmr_t sh_lb_debug_trig_sel_regval; struct { @@ -4638,52 +2550,12 @@ typedef union sh_lb_debug_trig_sel_u { mmr_t reserved_15 : 1; } sh_lb_debug_trig_sel_s; } sh_lb_debug_trig_sel_u_t; -#else -typedef union sh_lb_debug_trig_sel_u { - mmr_t sh_lb_debug_trig_sel_regval; - struct { - mmr_t reserved_15 : 1; - mmr_t trigger7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t trigger7_chiplet_sel : 3; - mmr_t reserved_13 : 1; - mmr_t trigger6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t trigger6_chiplet_sel : 3; - mmr_t reserved_11 : 1; - mmr_t trigger5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t trigger5_chiplet_sel : 3; - mmr_t reserved_9 : 1; - mmr_t trigger4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t trigger4_chiplet_sel : 3; - mmr_t reserved_7 : 1; - mmr_t trigger3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t trigger3_chiplet_sel : 3; - mmr_t reserved_5 : 1; - mmr_t trigger2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t trigger2_chiplet_sel : 3; - mmr_t reserved_3 : 1; - mmr_t trigger1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t trigger1_chiplet_sel : 3; - mmr_t reserved_1 : 1; - mmr_t trigger0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t trigger0_chiplet_sel : 3; - } sh_lb_debug_trig_sel_s; -} sh_lb_debug_trig_sel_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_ERROR_DETAIL_1" */ /* LB Error capture information: HDR1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_error_detail_1_u { mmr_t sh_lb_error_detail_1_regval; struct { @@ -4700,31 +2572,12 @@ typedef union sh_lb_error_detail_1_u { mmr_t valid : 1; } sh_lb_error_detail_1_s; } sh_lb_error_detail_1_u_t; -#else -typedef union sh_lb_error_detail_1_u { - mmr_t sh_lb_error_detail_1_regval; - struct { - mmr_t valid : 1; - mmr_t reserved_3 : 13; - mmr_t data_err : 1; - mmr_t hdr_err : 1; - mmr_t reserved_2 : 5; - mmr_t dest : 3; - mmr_t reserved_1 : 2; - mmr_t source : 14; - mmr_t reserved_0 : 2; - mmr_t suppl : 14; - mmr_t command : 8; - } sh_lb_error_detail_1_s; -} sh_lb_error_detail_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_ERROR_DETAIL_2" */ /* LB Error Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_error_detail_2_u { mmr_t sh_lb_error_detail_2_regval; struct { @@ -4732,64 +2585,36 @@ typedef union sh_lb_error_detail_2_u { mmr_t reserved_0 : 17; } sh_lb_error_detail_2_s; } sh_lb_error_detail_2_u_t; -#else -typedef union sh_lb_error_detail_2_u { - mmr_t sh_lb_error_detail_2_regval; - struct { - mmr_t reserved_0 : 17; - mmr_t address : 47; - } sh_lb_error_detail_2_s; -} sh_lb_error_detail_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_ERROR_DETAIL_3" */ /* LB Error Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_lb_error_detail_3_u { - mmr_t sh_lb_error_detail_3_regval; - struct { - mmr_t data : 64; - } sh_lb_error_detail_3_s; -} sh_lb_error_detail_3_u_t; -#else typedef union sh_lb_error_detail_3_u { mmr_t sh_lb_error_detail_3_regval; struct { mmr_t data : 64; } sh_lb_error_detail_3_s; } sh_lb_error_detail_3_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_ERROR_DETAIL_4" */ /* LB Error Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_lb_error_detail_4_u { - mmr_t sh_lb_error_detail_4_regval; - struct { - mmr_t route : 64; - } sh_lb_error_detail_4_s; -} sh_lb_error_detail_4_u_t; -#else typedef union sh_lb_error_detail_4_u { mmr_t sh_lb_error_detail_4_regval; struct { mmr_t route : 64; } sh_lb_error_detail_4_s; } sh_lb_error_detail_4_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_ERROR_DETAIL_5" */ /* LB Error Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_error_detail_5_u { mmr_t sh_lb_error_detail_5_regval; struct { @@ -4803,28 +2628,12 @@ typedef union sh_lb_error_detail_5_u { mmr_t reserved_0 : 57; } sh_lb_error_detail_5_s; } sh_lb_error_detail_5_u_t; -#else -typedef union sh_lb_error_detail_5_u { - mmr_t sh_lb_error_detail_5_regval; - struct { - mmr_t reserved_0 : 57; - mmr_t nack_b_timeout : 1; - mmr_t nack_a_timeout : 1; - mmr_t count_b_overflow : 1; - mmr_t count_a_overflow : 1; - mmr_t write_retry : 1; - mmr_t ptc1_write : 1; - mmr_t read_retry : 1; - } sh_lb_error_detail_5_s; -} sh_lb_error_detail_5_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_ERROR_MASK" */ /* LB Error Mask */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_error_mask_u { mmr_t sh_lb_error_mask_regval; struct { @@ -4854,44 +2663,12 @@ typedef union sh_lb_error_mask_u { mmr_t reserved_0 : 41; } sh_lb_error_mask_s; } sh_lb_error_mask_u_t; -#else -typedef union sh_lb_error_mask_u { - mmr_t sh_lb_error_mask_regval; - struct { - mmr_t reserved_0 : 41; - mmr_t rp_credit_overflow : 1; - mmr_t rq_credit_overflow : 1; - mmr_t unexp_valid : 1; - mmr_t rp_fifo_error : 1; - mmr_t rq_fifo_error : 1; - mmr_t gclk_drop : 1; - mmr_t vector_rp_route_error : 1; - mmr_t vector_rq_route_error : 1; - mmr_t pio_cb_err : 1; - mmr_t junk_bus_err : 1; - mmr_t ptc_1_timeout : 1; - mmr_t unexpected_linv : 1; - mmr_t linvv_overflow : 1; - mmr_t rq_time_out : 1; - mmr_t rq_bad_addr : 1; - mmr_t rp_bad_data : 1; - mmr_t rq_bad_data : 1; - mmr_t rp_long : 1; - mmr_t rq_long : 1; - mmr_t rp_short : 1; - mmr_t rq_short : 1; - mmr_t rp_bad_cmd : 1; - mmr_t rq_bad_cmd : 1; - } sh_lb_error_mask_s; -} sh_lb_error_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_ERROR_OVERFLOW" */ /* LB Error Overflow */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_error_overflow_u { mmr_t sh_lb_error_overflow_regval; struct { @@ -4921,44 +2698,12 @@ typedef union sh_lb_error_overflow_u { mmr_t reserved_0 : 41; } sh_lb_error_overflow_s; } sh_lb_error_overflow_u_t; -#else -typedef union sh_lb_error_overflow_u { - mmr_t sh_lb_error_overflow_regval; - struct { - mmr_t reserved_0 : 41; - mmr_t rp_credit_overflow_ovrfl : 1; - mmr_t rq_credit_overflow_ovrfl : 1; - mmr_t unexp_valid_ovrfl : 1; - mmr_t rp_fifo_error_ovrfl : 1; - mmr_t rq_fifo_error_ovrfl : 1; - mmr_t gclk_drop_ovrfl : 1; - mmr_t vector_rp_route_error_ovrfl : 1; - mmr_t vector_rq_route_error_ovrfl : 1; - mmr_t pio_cb_err_ovrfl : 1; - mmr_t junk_bus_err_ovrfl : 1; - mmr_t ptc_1_timeout_ovrfl : 1; - mmr_t unexpected_linv_ovrfl : 1; - mmr_t linvv_overflow_ovrfl : 1; - mmr_t rq_time_out_ovrfl : 1; - mmr_t rq_bad_addr_ovrfl : 1; - mmr_t rp_bad_data_ovrfl : 1; - mmr_t rq_bad_data_ovrfl : 1; - mmr_t rp_long_ovrfl : 1; - mmr_t rq_long_ovrfl : 1; - mmr_t rp_short_ovrfl : 1; - mmr_t rq_short_ovrfl : 1; - mmr_t rp_bad_cmd_ovrfl : 1; - mmr_t rq_bad_cmd_ovrfl : 1; - } sh_lb_error_overflow_s; -} sh_lb_error_overflow_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_ERROR_SUMMARY" */ /* LB Error Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_error_summary_u { mmr_t sh_lb_error_summary_regval; struct { @@ -4988,44 +2733,12 @@ typedef union sh_lb_error_summary_u { mmr_t reserved_0 : 41; } sh_lb_error_summary_s; } sh_lb_error_summary_u_t; -#else -typedef union sh_lb_error_summary_u { - mmr_t sh_lb_error_summary_regval; - struct { - mmr_t reserved_0 : 41; - mmr_t rp_credit_overflow : 1; - mmr_t rq_credit_overflow : 1; - mmr_t unexp_valid : 1; - mmr_t rp_fifo_error : 1; - mmr_t rq_fifo_error : 1; - mmr_t gclk_drop : 1; - mmr_t vector_rp_route_error : 1; - mmr_t vector_rq_route_error : 1; - mmr_t pio_cb_err : 1; - mmr_t junk_bus_err : 1; - mmr_t ptc_1_timeout : 1; - mmr_t unexpected_linv : 1; - mmr_t linvv_overflow : 1; - mmr_t rq_time_out : 1; - mmr_t rq_bad_addr : 1; - mmr_t rp_bad_data : 1; - mmr_t rq_bad_data : 1; - mmr_t rp_long : 1; - mmr_t rq_long : 1; - mmr_t rp_short : 1; - mmr_t rq_short : 1; - mmr_t rp_bad_cmd : 1; - mmr_t rq_bad_cmd : 1; - } sh_lb_error_summary_s; -} sh_lb_error_summary_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_FIRST_ERROR" */ /* LB First Error */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_first_error_u { mmr_t sh_lb_first_error_regval; struct { @@ -5055,44 +2768,12 @@ typedef union sh_lb_first_error_u { mmr_t reserved_0 : 41; } sh_lb_first_error_s; } sh_lb_first_error_u_t; -#else -typedef union sh_lb_first_error_u { - mmr_t sh_lb_first_error_regval; - struct { - mmr_t reserved_0 : 41; - mmr_t rp_credit_overflow : 1; - mmr_t rq_credit_overflow : 1; - mmr_t unexp_valid : 1; - mmr_t rp_fifo_error : 1; - mmr_t rq_fifo_error : 1; - mmr_t gclk_drop : 1; - mmr_t vector_rp_route_error : 1; - mmr_t vector_rq_route_error : 1; - mmr_t pio_cb_err : 1; - mmr_t junk_bus_err : 1; - mmr_t ptc_1_timeout : 1; - mmr_t unexpected_linv : 1; - mmr_t linvv_overflow : 1; - mmr_t rq_time_out : 1; - mmr_t rq_bad_addr : 1; - mmr_t rp_bad_data : 1; - mmr_t rq_bad_data : 1; - mmr_t rp_long : 1; - mmr_t rq_long : 1; - mmr_t rp_short : 1; - mmr_t rq_short : 1; - mmr_t rp_bad_cmd : 1; - mmr_t rq_bad_cmd : 1; - } sh_lb_first_error_s; -} sh_lb_first_error_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_LAST_CREDIT" */ /* Credit counter status register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_last_credit_u { mmr_t sh_lb_last_credit_regval; struct { @@ -5106,28 +2787,12 @@ typedef union sh_lb_last_credit_u { mmr_t reserved_2 : 36; } sh_lb_last_credit_s; } sh_lb_last_credit_u_t; -#else -typedef union sh_lb_last_credit_u { - mmr_t sh_lb_last_credit_regval; - struct { - mmr_t reserved_2 : 36; - mmr_t loq_rp_credit : 5; - mmr_t loq_rq_credit : 5; - mmr_t linvv_credit : 6; - mmr_t reserved_1 : 2; - mmr_t liq_rp_credit : 4; - mmr_t reserved_0 : 1; - mmr_t liq_rq_credit : 5; - } sh_lb_last_credit_s; -} sh_lb_last_credit_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_NACK_STATUS" */ /* Nack Counter Status Register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_nack_status_u { mmr_t sh_lb_nack_status_regval; struct { @@ -5141,28 +2806,12 @@ typedef union sh_lb_nack_status_u { mmr_t reserved_2 : 2; } sh_lb_nack_status_s; } sh_lb_nack_status_u_t; -#else -typedef union sh_lb_nack_status_u { - mmr_t sh_lb_nack_status_regval; - struct { - mmr_t reserved_2 : 2; - mmr_t cb_state : 2; - mmr_t cb_timeout_count : 12; - mmr_t junk_nack : 16; - mmr_t reserved_1 : 4; - mmr_t pio_nack_b : 12; - mmr_t reserved_0 : 4; - mmr_t pio_nack_a : 12; - } sh_lb_nack_status_s; -} sh_lb_nack_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_TRIGGER_COMPARE" */ /* LB Test-point Trigger Compare */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_trigger_compare_u { mmr_t sh_lb_trigger_compare_regval; struct { @@ -5170,22 +2819,12 @@ typedef union sh_lb_trigger_compare_u { mmr_t reserved_0 : 32; } sh_lb_trigger_compare_s; } sh_lb_trigger_compare_u_t; -#else -typedef union sh_lb_trigger_compare_u { - mmr_t sh_lb_trigger_compare_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t mask : 32; - } sh_lb_trigger_compare_s; -} sh_lb_trigger_compare_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_TRIGGER_DATA" */ /* LB Test-point Trigger Compare Data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_trigger_data_u { mmr_t sh_lb_trigger_data_regval; struct { @@ -5193,22 +2832,12 @@ typedef union sh_lb_trigger_data_u { mmr_t reserved_0 : 32; } sh_lb_trigger_data_s; } sh_lb_trigger_data_u_t; -#else -typedef union sh_lb_trigger_data_u { - mmr_t sh_lb_trigger_data_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t compare_pattern : 32; - } sh_lb_trigger_data_s; -} sh_lb_trigger_data_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_AEC_CONFIG" */ /* PI Adaptive Error Correction Configuration */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_aec_config_u { mmr_t sh_pi_aec_config_regval; struct { @@ -5216,22 +2845,12 @@ typedef union sh_pi_aec_config_u { mmr_t reserved_0 : 61; } sh_pi_aec_config_s; } sh_pi_aec_config_u_t; -#else -typedef union sh_pi_aec_config_u { - mmr_t sh_pi_aec_config_regval; - struct { - mmr_t reserved_0 : 61; - mmr_t mode : 3; - } sh_pi_aec_config_s; -} sh_pi_aec_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_AFI_ERROR_MASK" */ /* PI AFI Error Mask */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_afi_error_mask_u { mmr_t sh_pi_afi_error_mask_regval; struct { @@ -5253,36 +2872,12 @@ typedef union sh_pi_afi_error_mask_u { mmr_t reserved_1 : 29; } sh_pi_afi_error_mask_s; } sh_pi_afi_error_mask_u_t; -#else -typedef union sh_pi_afi_error_mask_u { - mmr_t sh_pi_afi_error_mask_regval; - struct { - mmr_t reserved_1 : 29; - mmr_t msg_len : 1; - mmr_t fsb_tbl_miss : 1; - mmr_t bad_snoop : 1; - mmr_t livelock : 1; - mmr_t shub_fsb_ce : 1; - mmr_t shub_fsb_uce : 1; - mmr_t shub_fsb_dqe : 1; - mmr_t addr_parity : 1; - mmr_t req_parity : 1; - mmr_t addr_access : 1; - mmr_t req_format : 1; - mmr_t ioq_overrun : 1; - mmr_t rsp_parity : 1; - mmr_t hung_bus : 1; - mmr_t reserved_0 : 21; - } sh_pi_afi_error_mask_s; -} sh_pi_afi_error_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_AFI_TEST_POINT_COMPARE" */ /* PI AFI Test Point Compare */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_afi_test_point_compare_u { mmr_t sh_pi_afi_test_point_compare_regval; struct { @@ -5290,22 +2885,12 @@ typedef union sh_pi_afi_test_point_compare_u { mmr_t compare_pattern : 32; } sh_pi_afi_test_point_compare_s; } sh_pi_afi_test_point_compare_u_t; -#else -typedef union sh_pi_afi_test_point_compare_u { - mmr_t sh_pi_afi_test_point_compare_regval; - struct { - mmr_t compare_pattern : 32; - mmr_t compare_mask : 32; - } sh_pi_afi_test_point_compare_s; -} sh_pi_afi_test_point_compare_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_AFI_TEST_POINT_SELECT" */ /* PI AFI Test Point Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_afi_test_point_select_u { mmr_t sh_pi_afi_test_point_select_regval; struct { @@ -5335,44 +2920,12 @@ typedef union sh_pi_afi_test_point_select_u { mmr_t trigger_enable : 1; } sh_pi_afi_test_point_select_s; } sh_pi_afi_test_point_select_u_t; -#else -typedef union sh_pi_afi_test_point_select_u { - mmr_t sh_pi_afi_test_point_select_regval; - struct { - mmr_t trigger_enable : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t nibble7_chiplet_sel : 4; - mmr_t reserved_6 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t nibble6_chiplet_sel : 4; - mmr_t reserved_5 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t nibble5_chiplet_sel : 4; - mmr_t reserved_4 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t nibble4_chiplet_sel : 4; - mmr_t reserved_3 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t nibble3_chiplet_sel : 4; - mmr_t reserved_2 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t nibble2_chiplet_sel : 4; - mmr_t reserved_1 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t nibble1_chiplet_sel : 4; - mmr_t reserved_0 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t nibble0_chiplet_sel : 4; - } sh_pi_afi_test_point_select_s; -} sh_pi_afi_test_point_select_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_AFI_TEST_POINT_TRIGGER_SELECT" */ /* PI CRBC Test Point Trigger Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_afi_test_point_trigger_select_u { mmr_t sh_pi_afi_test_point_trigger_select_regval; struct { @@ -5402,44 +2955,12 @@ typedef union sh_pi_afi_test_point_trigger_select_u { mmr_t reserved_7 : 1; } sh_pi_afi_test_point_trigger_select_s; } sh_pi_afi_test_point_trigger_select_u_t; -#else -typedef union sh_pi_afi_test_point_trigger_select_u { - mmr_t sh_pi_afi_test_point_trigger_select_regval; - struct { - mmr_t reserved_7 : 1; - mmr_t trigger7_nibble_sel : 3; - mmr_t trigger7_chiplet_sel : 4; - mmr_t reserved_6 : 1; - mmr_t trigger6_nibble_sel : 3; - mmr_t trigger6_chiplet_sel : 4; - mmr_t reserved_5 : 1; - mmr_t trigger5_nibble_sel : 3; - mmr_t trigger5_chiplet_sel : 4; - mmr_t reserved_4 : 1; - mmr_t trigger4_nibble_sel : 3; - mmr_t trigger4_chiplet_sel : 4; - mmr_t reserved_3 : 1; - mmr_t trigger3_nibble_sel : 3; - mmr_t trigger3_chiplet_sel : 4; - mmr_t reserved_2 : 1; - mmr_t trigger2_nibble_sel : 3; - mmr_t trigger2_chiplet_sel : 4; - mmr_t reserved_1 : 1; - mmr_t trigger1_nibble_sel : 3; - mmr_t trigger1_chiplet_sel : 4; - mmr_t reserved_0 : 1; - mmr_t trigger0_nibble_sel : 3; - mmr_t trigger0_chiplet_sel : 4; - } sh_pi_afi_test_point_trigger_select_s; -} sh_pi_afi_test_point_trigger_select_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_AUTO_REPLY_ENABLE" */ /* PI Auto Reply Enable */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_auto_reply_enable_u { mmr_t sh_pi_auto_reply_enable_regval; struct { @@ -5447,22 +2968,12 @@ typedef union sh_pi_auto_reply_enable_u { mmr_t reserved_0 : 63; } sh_pi_auto_reply_enable_s; } sh_pi_auto_reply_enable_u_t; -#else -typedef union sh_pi_auto_reply_enable_u { - mmr_t sh_pi_auto_reply_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t auto_reply_enable : 1; - } sh_pi_auto_reply_enable_s; -} sh_pi_auto_reply_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CAM_CONTROL" */ /* CRB CAM MMR Access Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_cam_control_u { mmr_t sh_pi_cam_control_regval; struct { @@ -5474,26 +2985,12 @@ typedef union sh_pi_cam_control_u { mmr_t start : 1; } sh_pi_cam_control_s; } sh_pi_cam_control_u_t; -#else -typedef union sh_pi_cam_control_u { - mmr_t sh_pi_cam_control_regval; - struct { - mmr_t start : 1; - mmr_t reserved_1 : 53; - mmr_t rrb_rd_xfer_clear : 1; - mmr_t cam_write : 1; - mmr_t reserved_0 : 1; - mmr_t cam_indx : 7; - } sh_pi_cam_control_s; -} sh_pi_cam_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CRBC_TEST_POINT_COMPARE" */ /* PI CRBC Test Point Compare */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_crbc_test_point_compare_u { mmr_t sh_pi_crbc_test_point_compare_regval; struct { @@ -5501,22 +2998,12 @@ typedef union sh_pi_crbc_test_point_compare_u { mmr_t compare_pattern : 32; } sh_pi_crbc_test_point_compare_s; } sh_pi_crbc_test_point_compare_u_t; -#else -typedef union sh_pi_crbc_test_point_compare_u { - mmr_t sh_pi_crbc_test_point_compare_regval; - struct { - mmr_t compare_pattern : 32; - mmr_t compare_mask : 32; - } sh_pi_crbc_test_point_compare_s; -} sh_pi_crbc_test_point_compare_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CRBC_TEST_POINT_SELECT" */ /* PI CRBC Test Point Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_crbc_test_point_select_u { mmr_t sh_pi_crbc_test_point_select_regval; struct { @@ -5554,52 +3041,12 @@ typedef union sh_pi_crbc_test_point_select_u { mmr_t trigger_enable : 1; } sh_pi_crbc_test_point_select_s; } sh_pi_crbc_test_point_select_u_t; -#else -typedef union sh_pi_crbc_test_point_select_u { - mmr_t sh_pi_crbc_test_point_select_regval; - struct { - mmr_t trigger_enable : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_chiplet_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_chiplet_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_chiplet_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_chiplet_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_chiplet_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_chiplet_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_chiplet_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_chiplet_sel : 3; - } sh_pi_crbc_test_point_select_s; -} sh_pi_crbc_test_point_select_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT" */ /* PI CRBC Test Point Trigger Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_crbc_test_point_trigger_select_u { mmr_t sh_pi_crbc_test_point_trigger_select_regval; struct { @@ -5637,52 +3084,12 @@ typedef union sh_pi_crbc_test_point_trigger_select_u { mmr_t reserved_15 : 1; } sh_pi_crbc_test_point_trigger_select_s; } sh_pi_crbc_test_point_trigger_select_u_t; -#else -typedef union sh_pi_crbc_test_point_trigger_select_u { - mmr_t sh_pi_crbc_test_point_trigger_select_regval; - struct { - mmr_t reserved_15 : 1; - mmr_t trigger7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t trigger7_chiplet_sel : 3; - mmr_t reserved_13 : 1; - mmr_t trigger6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t trigger6_chiplet_sel : 3; - mmr_t reserved_11 : 1; - mmr_t trigger5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t trigger5_chiplet_sel : 3; - mmr_t reserved_9 : 1; - mmr_t trigger4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t trigger4_chiplet_sel : 3; - mmr_t reserved_7 : 1; - mmr_t trigger3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t trigger3_chiplet_sel : 3; - mmr_t reserved_5 : 1; - mmr_t trigger2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t trigger2_chiplet_sel : 3; - mmr_t reserved_3 : 1; - mmr_t trigger1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t trigger1_chiplet_sel : 3; - mmr_t reserved_1 : 1; - mmr_t trigger0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t trigger0_chiplet_sel : 3; - } sh_pi_crbc_test_point_trigger_select_s; -} sh_pi_crbc_test_point_trigger_select_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CRBP_ERROR_MASK" */ /* PI CRBP Error Mask */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_crbp_error_mask_u { mmr_t sh_pi_crbp_error_mask_regval; struct { @@ -5710,42 +3117,12 @@ typedef union sh_pi_crbp_error_mask_u { mmr_t reserved_0 : 43; } sh_pi_crbp_error_mask_s; } sh_pi_crbp_error_mask_u_t; -#else -typedef union sh_pi_crbp_error_mask_u { - mmr_t sh_pi_crbp_error_mask_regval; - struct { - mmr_t reserved_0 : 43; - mmr_t xn_rp_crd_oflow : 1; - mmr_t xn_rq_crd_oflow : 1; - mmr_t md_rp_crd_oflow : 1; - mmr_t md_rq_crd_oflow : 1; - mmr_t gfx_int_1 : 1; - mmr_t gfx_int_0 : 1; - mmr_t nack_oflow : 1; - mmr_t xn_rp_q_oflow : 1; - mmr_t xn_rq_q_oflow : 1; - mmr_t md_rp_q_oflow : 1; - mmr_t md_rq_q_oflow : 1; - mmr_t msg_color_err : 1; - mmr_t fsb_shub_ce : 1; - mmr_t fsb_shub_uce : 1; - mmr_t pio_to_err : 1; - mmr_t mem_to_err : 1; - mmr_t pio_rp_err : 1; - mmr_t mem_rp_err : 1; - mmr_t xb_proto_err : 1; - mmr_t gfx_rp_err : 1; - mmr_t fsb_proto_err : 1; - } sh_pi_crbp_error_mask_s; -} sh_pi_crbp_error_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CRBP_FSB_PIPE_COMPARE" */ /* CRBP FSB Pipe Compare */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_crbp_fsb_pipe_compare_u { mmr_t sh_pi_crbp_fsb_pipe_compare_regval; struct { @@ -5754,23 +3131,12 @@ typedef union sh_pi_crbp_fsb_pipe_compare_u { mmr_t reserved_0 : 11; } sh_pi_crbp_fsb_pipe_compare_s; } sh_pi_crbp_fsb_pipe_compare_u_t; -#else -typedef union sh_pi_crbp_fsb_pipe_compare_u { - mmr_t sh_pi_crbp_fsb_pipe_compare_regval; - struct { - mmr_t reserved_0 : 11; - mmr_t compare_req : 6; - mmr_t compare_address : 47; - } sh_pi_crbp_fsb_pipe_compare_s; -} sh_pi_crbp_fsb_pipe_compare_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CRBP_FSB_PIPE_MASK" */ /* CRBP Compare Mask */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_crbp_fsb_pipe_mask_u { mmr_t sh_pi_crbp_fsb_pipe_mask_regval; struct { @@ -5779,23 +3145,12 @@ typedef union sh_pi_crbp_fsb_pipe_mask_u { mmr_t reserved_0 : 11; } sh_pi_crbp_fsb_pipe_mask_s; } sh_pi_crbp_fsb_pipe_mask_u_t; -#else -typedef union sh_pi_crbp_fsb_pipe_mask_u { - mmr_t sh_pi_crbp_fsb_pipe_mask_regval; - struct { - mmr_t reserved_0 : 11; - mmr_t compare_req_mask : 6; - mmr_t compare_address_mask : 47; - } sh_pi_crbp_fsb_pipe_mask_s; -} sh_pi_crbp_fsb_pipe_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CRBP_TEST_POINT_COMPARE" */ /* PI CRBP Test Point Compare */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_crbp_test_point_compare_u { mmr_t sh_pi_crbp_test_point_compare_regval; struct { @@ -5803,22 +3158,12 @@ typedef union sh_pi_crbp_test_point_compare_u { mmr_t compare_pattern : 32; } sh_pi_crbp_test_point_compare_s; } sh_pi_crbp_test_point_compare_u_t; -#else -typedef union sh_pi_crbp_test_point_compare_u { - mmr_t sh_pi_crbp_test_point_compare_regval; - struct { - mmr_t compare_pattern : 32; - mmr_t compare_mask : 32; - } sh_pi_crbp_test_point_compare_s; -} sh_pi_crbp_test_point_compare_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CRBP_TEST_POINT_SELECT" */ /* PI CRBP Test Point Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_crbp_test_point_select_u { mmr_t sh_pi_crbp_test_point_select_regval; struct { @@ -5856,52 +3201,12 @@ typedef union sh_pi_crbp_test_point_select_u { mmr_t trigger_enable : 1; } sh_pi_crbp_test_point_select_s; } sh_pi_crbp_test_point_select_u_t; -#else -typedef union sh_pi_crbp_test_point_select_u { - mmr_t sh_pi_crbp_test_point_select_regval; - struct { - mmr_t trigger_enable : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_chiplet_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_chiplet_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_chiplet_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_chiplet_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_chiplet_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_chiplet_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_chiplet_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_chiplet_sel : 3; - } sh_pi_crbp_test_point_select_s; -} sh_pi_crbp_test_point_select_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT" */ /* PI CRBP Test Point Trigger Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_crbp_test_point_trigger_select_u { mmr_t sh_pi_crbp_test_point_trigger_select_regval; struct { @@ -5939,52 +3244,12 @@ typedef union sh_pi_crbp_test_point_trigger_select_u { mmr_t reserved_15 : 1; } sh_pi_crbp_test_point_trigger_select_s; } sh_pi_crbp_test_point_trigger_select_u_t; -#else -typedef union sh_pi_crbp_test_point_trigger_select_u { - mmr_t sh_pi_crbp_test_point_trigger_select_regval; - struct { - mmr_t reserved_15 : 1; - mmr_t trigger7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t trigger7_chiplet_sel : 3; - mmr_t reserved_13 : 1; - mmr_t trigger6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t trigger6_chiplet_sel : 3; - mmr_t reserved_11 : 1; - mmr_t trigger5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t trigger5_chiplet_sel : 3; - mmr_t reserved_9 : 1; - mmr_t trigger4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t trigger4_chiplet_sel : 3; - mmr_t reserved_7 : 1; - mmr_t trigger3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t trigger3_chiplet_sel : 3; - mmr_t reserved_5 : 1; - mmr_t trigger2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t trigger2_chiplet_sel : 3; - mmr_t reserved_3 : 1; - mmr_t trigger1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t trigger1_chiplet_sel : 3; - mmr_t reserved_1 : 1; - mmr_t trigger0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t trigger0_chiplet_sel : 3; - } sh_pi_crbp_test_point_trigger_select_s; -} sh_pi_crbp_test_point_trigger_select_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CRBP_XB_PIPE_COMPARE_0" */ /* CRBP XB Pipe Compare */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_crbp_xb_pipe_compare_0_u { mmr_t sh_pi_crbp_xb_pipe_compare_0_regval; struct { @@ -5993,23 +3258,12 @@ typedef union sh_pi_crbp_xb_pipe_compare_0_u { mmr_t reserved_0 : 9; } sh_pi_crbp_xb_pipe_compare_0_s; } sh_pi_crbp_xb_pipe_compare_0_u_t; -#else -typedef union sh_pi_crbp_xb_pipe_compare_0_u { - mmr_t sh_pi_crbp_xb_pipe_compare_0_regval; - struct { - mmr_t reserved_0 : 9; - mmr_t compare_command : 8; - mmr_t compare_address : 47; - } sh_pi_crbp_xb_pipe_compare_0_s; -} sh_pi_crbp_xb_pipe_compare_0_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CRBP_XB_PIPE_COMPARE_1" */ /* CRBP XB Pipe Compare */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_crbp_xb_pipe_compare_1_u { mmr_t sh_pi_crbp_xb_pipe_compare_1_regval; struct { @@ -6021,26 +3275,12 @@ typedef union sh_pi_crbp_xb_pipe_compare_1_u { mmr_t reserved_2 : 23; } sh_pi_crbp_xb_pipe_compare_1_s; } sh_pi_crbp_xb_pipe_compare_1_u_t; -#else -typedef union sh_pi_crbp_xb_pipe_compare_1_u { - mmr_t sh_pi_crbp_xb_pipe_compare_1_regval; - struct { - mmr_t reserved_2 : 23; - mmr_t compare_echo : 9; - mmr_t reserved_1 : 2; - mmr_t compare_supplemental : 14; - mmr_t reserved_0 : 2; - mmr_t compare_source : 14; - } sh_pi_crbp_xb_pipe_compare_1_s; -} sh_pi_crbp_xb_pipe_compare_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CRBP_XB_PIPE_MASK_0" */ /* CRBP Compare Mask Register 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_crbp_xb_pipe_mask_0_u { mmr_t sh_pi_crbp_xb_pipe_mask_0_regval; struct { @@ -6049,23 +3289,12 @@ typedef union sh_pi_crbp_xb_pipe_mask_0_u { mmr_t reserved_0 : 9; } sh_pi_crbp_xb_pipe_mask_0_s; } sh_pi_crbp_xb_pipe_mask_0_u_t; -#else -typedef union sh_pi_crbp_xb_pipe_mask_0_u { - mmr_t sh_pi_crbp_xb_pipe_mask_0_regval; - struct { - mmr_t reserved_0 : 9; - mmr_t compare_command_mask : 8; - mmr_t compare_address_mask : 47; - } sh_pi_crbp_xb_pipe_mask_0_s; -} sh_pi_crbp_xb_pipe_mask_0_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CRBP_XB_PIPE_MASK_1" */ /* CRBP XB Pipe Compare Mask Register 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_crbp_xb_pipe_mask_1_u { mmr_t sh_pi_crbp_xb_pipe_mask_1_regval; struct { @@ -6077,26 +3306,12 @@ typedef union sh_pi_crbp_xb_pipe_mask_1_u { mmr_t reserved_2 : 23; } sh_pi_crbp_xb_pipe_mask_1_s; } sh_pi_crbp_xb_pipe_mask_1_u_t; -#else -typedef union sh_pi_crbp_xb_pipe_mask_1_u { - mmr_t sh_pi_crbp_xb_pipe_mask_1_regval; - struct { - mmr_t reserved_2 : 23; - mmr_t compare_echo_mask : 9; - mmr_t reserved_1 : 2; - mmr_t compare_supplemental_mask : 14; - mmr_t reserved_0 : 2; - mmr_t compare_source_mask : 14; - } sh_pi_crbp_xb_pipe_mask_1_s; -} sh_pi_crbp_xb_pipe_mask_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_DPC_QUEUE_CONFIG" */ /* DPC Queue Configuration */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_dpc_queue_config_u { mmr_t sh_pi_dpc_queue_config_regval; struct { @@ -6110,28 +3325,12 @@ typedef union sh_pi_dpc_queue_config_u { mmr_t reserved_3 : 35; } sh_pi_dpc_queue_config_s; } sh_pi_dpc_queue_config_u_t; -#else -typedef union sh_pi_dpc_queue_config_u { - mmr_t sh_pi_dpc_queue_config_regval; - struct { - mmr_t reserved_3 : 35; - mmr_t fwcq_af_thresh : 5; - mmr_t reserved_2 : 3; - mmr_t fwcq_ae_level : 5; - mmr_t reserved_1 : 3; - mmr_t dwcq_af_thresh : 5; - mmr_t reserved_0 : 3; - mmr_t dwcq_ae_level : 5; - } sh_pi_dpc_queue_config_s; -} sh_pi_dpc_queue_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_ERROR_MASK" */ /* PI Error Mask */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_error_mask_u { mmr_t sh_pi_error_mask_regval; struct { @@ -6173,56 +3372,12 @@ typedef union sh_pi_error_mask_u { mmr_t reserved_0 : 29; } sh_pi_error_mask_s; } sh_pi_error_mask_u_t; -#else -typedef union sh_pi_error_mask_u { - mmr_t sh_pi_error_mask_regval; - struct { - mmr_t reserved_0 : 29; - mmr_t msg_length : 1; - mmr_t fsb_tbl_miss : 1; - mmr_t bad_snoop : 1; - mmr_t livelock : 1; - mmr_t shub_fsb_ce : 1; - mmr_t shub_fsb_uce : 1; - mmr_t shub_fsb_dqe : 1; - mmr_t addr_parity : 1; - mmr_t req_parity : 1; - mmr_t addr_access : 1; - mmr_t req_format : 1; - mmr_t ioq_overrun : 1; - mmr_t rsp_parity : 1; - mmr_t hung_bus : 1; - mmr_t xn_rp_crd_oflow : 1; - mmr_t xn_rq_crd_oflow : 1; - mmr_t md_rp_crd_oflow : 1; - mmr_t md_rq_crd_oflow : 1; - mmr_t gfx_int_1 : 1; - mmr_t gfx_int_0 : 1; - mmr_t nack_oflow : 1; - mmr_t xn_rp_q_oflow : 1; - mmr_t xn_rq_q_oflow : 1; - mmr_t md_rp_q_oflow : 1; - mmr_t md_rq_q_oflow : 1; - mmr_t msg_color_err : 1; - mmr_t fsb_shub_ce : 1; - mmr_t fsb_shub_uce : 1; - mmr_t pio_to_err : 1; - mmr_t mem_to_err : 1; - mmr_t pio_rp_err : 1; - mmr_t mem_rp_err : 1; - mmr_t xb_proto_err : 1; - mmr_t gfx_rp_err : 1; - mmr_t fsb_proto_err : 1; - } sh_pi_error_mask_s; -} sh_pi_error_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_EXPRESS_REPLY_CONFIG" */ /* PI Express Reply Configuration */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_express_reply_config_u { mmr_t sh_pi_express_reply_config_regval; struct { @@ -6230,64 +3385,36 @@ typedef union sh_pi_express_reply_config_u { mmr_t reserved_0 : 61; } sh_pi_express_reply_config_s; } sh_pi_express_reply_config_u_t; -#else -typedef union sh_pi_express_reply_config_u { - mmr_t sh_pi_express_reply_config_regval; - struct { - mmr_t reserved_0 : 61; - mmr_t mode : 3; - } sh_pi_express_reply_config_s; -} sh_pi_express_reply_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_FSB_COMPARE_VALUE" */ /* FSB Compare Value */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_pi_fsb_compare_value_u { - mmr_t sh_pi_fsb_compare_value_regval; - struct { - mmr_t compare_value : 64; - } sh_pi_fsb_compare_value_s; -} sh_pi_fsb_compare_value_u_t; -#else typedef union sh_pi_fsb_compare_value_u { mmr_t sh_pi_fsb_compare_value_regval; struct { mmr_t compare_value : 64; } sh_pi_fsb_compare_value_s; } sh_pi_fsb_compare_value_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_FSB_COMPARE_MASK" */ /* FSB Compare Mask */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_fsb_compare_mask_u { mmr_t sh_pi_fsb_compare_mask_regval; struct { mmr_t mask_value : 64; } sh_pi_fsb_compare_mask_s; } sh_pi_fsb_compare_mask_u_t; -#else -typedef union sh_pi_fsb_compare_mask_u { - mmr_t sh_pi_fsb_compare_mask_regval; - struct { - mmr_t mask_value : 64; - } sh_pi_fsb_compare_mask_s; -} sh_pi_fsb_compare_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_FSB_ERROR_INJECTION" */ /* Inject an Error onto the FSB */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_fsb_error_injection_u { mmr_t sh_pi_fsb_error_injection_regval; struct { @@ -6321,48 +3448,12 @@ typedef union sh_pi_fsb_error_injection_u { mmr_t reserved_2 : 29; } sh_pi_fsb_error_injection_s; } sh_pi_fsb_error_injection_u_t; -#else -typedef union sh_pi_fsb_error_injection_u { - mmr_t sh_pi_fsb_error_injection_regval; - struct { - mmr_t reserved_2 : 29; - mmr_t bus_hang : 1; - mmr_t livelock : 1; - mmr_t ioq_overrun : 1; - mmr_t reserved_1 : 4; - mmr_t dw3_uce_from_fsb : 1; - mmr_t dw3_ce_from_fsb : 1; - mmr_t dw2_uce_from_fsb : 1; - mmr_t dw2_ce_from_fsb : 1; - mmr_t dw1_uce_from_fsb : 1; - mmr_t dw1_ce_from_fsb : 1; - mmr_t dw0_uce_from_fsb : 1; - mmr_t dw0_ce_from_fsb : 1; - mmr_t rsp_pe_from_fsb : 1; - mmr_t ap1_pe_from_fsb : 1; - mmr_t ap0_pe_from_fsb : 1; - mmr_t rp_pe_from_fsb : 1; - mmr_t reserved_0 : 6; - mmr_t ip1_pe_to_fsb : 1; - mmr_t ip0_pe_to_fsb : 1; - mmr_t dw1_uce_to_fsb : 1; - mmr_t dw1_ce_to_fsb : 1; - mmr_t dw0_uce_to_fsb : 1; - mmr_t dw0_ce_to_fsb : 1; - mmr_t rsp_pe_to_fsb : 1; - mmr_t ap1_pe_to_fsb : 1; - mmr_t ap0_pe_to_fsb : 1; - mmr_t rp_pe_to_fsb : 1; - } sh_pi_fsb_error_injection_s; -} sh_pi_fsb_error_injection_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_MD2PI_REPLY_VC_CONFIG" */ /* MD-to-PI Reply Virtual Channel Configuration */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_md2pi_reply_vc_config_u { mmr_t sh_pi_md2pi_reply_vc_config_regval; struct { @@ -6374,26 +3465,12 @@ typedef union sh_pi_md2pi_reply_vc_config_u { mmr_t capture_credit_status : 1; } sh_pi_md2pi_reply_vc_config_s; } sh_pi_md2pi_reply_vc_config_u_t; -#else -typedef union sh_pi_md2pi_reply_vc_config_u { - mmr_t sh_pi_md2pi_reply_vc_config_regval; - struct { - mmr_t capture_credit_status : 1; - mmr_t force_credit : 1; - mmr_t reserved_0 : 48; - mmr_t max_credits : 6; - mmr_t data_depth : 4; - mmr_t hdr_depth : 4; - } sh_pi_md2pi_reply_vc_config_s; -} sh_pi_md2pi_reply_vc_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_MD2PI_REQUEST_VC_CONFIG" */ /* MD-to-PI Request Virtual Channel Configuration */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_md2pi_request_vc_config_u { mmr_t sh_pi_md2pi_request_vc_config_regval; struct { @@ -6405,26 +3482,12 @@ typedef union sh_pi_md2pi_request_vc_config_u { mmr_t capture_credit_status : 1; } sh_pi_md2pi_request_vc_config_s; } sh_pi_md2pi_request_vc_config_u_t; -#else -typedef union sh_pi_md2pi_request_vc_config_u { - mmr_t sh_pi_md2pi_request_vc_config_regval; - struct { - mmr_t capture_credit_status : 1; - mmr_t force_credit : 1; - mmr_t reserved_0 : 48; - mmr_t max_credits : 6; - mmr_t data_depth : 4; - mmr_t hdr_depth : 4; - } sh_pi_md2pi_request_vc_config_s; -} sh_pi_md2pi_request_vc_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_QUEUE_ERROR_INJECTION" */ /* PI Queue Error Injection */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_queue_error_injection_u { mmr_t sh_pi_queue_error_injection_regval; struct { @@ -6439,29 +3502,12 @@ typedef union sh_pi_queue_error_injection_u { mmr_t reserved_0 : 56; } sh_pi_queue_error_injection_s; } sh_pi_queue_error_injection_u_t; -#else -typedef union sh_pi_queue_error_injection_u { - mmr_t sh_pi_queue_error_injection_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t xnpi_rpy_bfr : 1; - mmr_t rxl_rdy_q : 1; - mmr_t rxl_kill_q : 1; - mmr_t ptc_intr : 1; - mmr_t mdpi_rpy_bfr : 1; - mmr_t fsb_wtl_cmnd_q : 1; - mmr_t dxb_wtl_cmnd_q : 1; - mmr_t dat_dfr_q : 1; - } sh_pi_queue_error_injection_s; -} sh_pi_queue_error_injection_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_TEST_POINT_COMPARE" */ /* PI Test Point Compare */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_test_point_compare_u { mmr_t sh_pi_test_point_compare_regval; struct { @@ -6469,22 +3515,12 @@ typedef union sh_pi_test_point_compare_u { mmr_t compare_pattern : 32; } sh_pi_test_point_compare_s; } sh_pi_test_point_compare_u_t; -#else -typedef union sh_pi_test_point_compare_u { - mmr_t sh_pi_test_point_compare_regval; - struct { - mmr_t compare_pattern : 32; - mmr_t compare_mask : 32; - } sh_pi_test_point_compare_s; -} sh_pi_test_point_compare_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_TEST_POINT_SELECT" */ /* PI Test Point Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_test_point_select_u { mmr_t sh_pi_test_point_select_regval; struct { @@ -6522,52 +3558,12 @@ typedef union sh_pi_test_point_select_u { mmr_t trigger_enable : 1; } sh_pi_test_point_select_s; } sh_pi_test_point_select_u_t; -#else -typedef union sh_pi_test_point_select_u { - mmr_t sh_pi_test_point_select_regval; - struct { - mmr_t trigger_enable : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_chiplet_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_chiplet_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_chiplet_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_chiplet_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_chiplet_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_chiplet_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_chiplet_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_chiplet_sel : 3; - } sh_pi_test_point_select_s; -} sh_pi_test_point_select_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_TEST_POINT_TRIGGER_SELECT" */ /* PI Test Point Trigger Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_test_point_trigger_select_u { mmr_t sh_pi_test_point_trigger_select_regval; struct { @@ -6605,52 +3601,12 @@ typedef union sh_pi_test_point_trigger_select_u { mmr_t reserved_15 : 1; } sh_pi_test_point_trigger_select_s; } sh_pi_test_point_trigger_select_u_t; -#else -typedef union sh_pi_test_point_trigger_select_u { - mmr_t sh_pi_test_point_trigger_select_regval; - struct { - mmr_t reserved_15 : 1; - mmr_t trigger7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t trigger7_chiplet_sel : 3; - mmr_t reserved_13 : 1; - mmr_t trigger6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t trigger6_chiplet_sel : 3; - mmr_t reserved_11 : 1; - mmr_t trigger5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t trigger5_chiplet_sel : 3; - mmr_t reserved_9 : 1; - mmr_t trigger4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t trigger4_chiplet_sel : 3; - mmr_t reserved_7 : 1; - mmr_t trigger3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t trigger3_chiplet_sel : 3; - mmr_t reserved_5 : 1; - mmr_t trigger2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t trigger2_chiplet_sel : 3; - mmr_t reserved_3 : 1; - mmr_t trigger1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t trigger1_chiplet_sel : 3; - mmr_t reserved_1 : 1; - mmr_t trigger0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t trigger0_chiplet_sel : 3; - } sh_pi_test_point_trigger_select_s; -} sh_pi_test_point_trigger_select_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_XN2PI_REPLY_VC_CONFIG" */ /* XN-to-PI Reply Virtual Channel Configuration */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_xn2pi_reply_vc_config_u { mmr_t sh_pi_xn2pi_reply_vc_config_regval; struct { @@ -6662,26 +3618,12 @@ typedef union sh_pi_xn2pi_reply_vc_config_u { mmr_t capture_credit_status : 1; } sh_pi_xn2pi_reply_vc_config_s; } sh_pi_xn2pi_reply_vc_config_u_t; -#else -typedef union sh_pi_xn2pi_reply_vc_config_u { - mmr_t sh_pi_xn2pi_reply_vc_config_regval; - struct { - mmr_t capture_credit_status : 1; - mmr_t force_credit : 1; - mmr_t reserved_0 : 48; - mmr_t max_credits : 6; - mmr_t data_depth : 4; - mmr_t hdr_depth : 4; - } sh_pi_xn2pi_reply_vc_config_s; -} sh_pi_xn2pi_reply_vc_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_XN2PI_REQUEST_VC_CONFIG" */ /* XN-to-PI Request Virtual Channel Configuration */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_xn2pi_request_vc_config_u { mmr_t sh_pi_xn2pi_request_vc_config_regval; struct { @@ -6693,26 +3635,12 @@ typedef union sh_pi_xn2pi_request_vc_config_u { mmr_t capture_credit_status : 1; } sh_pi_xn2pi_request_vc_config_s; } sh_pi_xn2pi_request_vc_config_u_t; -#else -typedef union sh_pi_xn2pi_request_vc_config_u { - mmr_t sh_pi_xn2pi_request_vc_config_regval; - struct { - mmr_t capture_credit_status : 1; - mmr_t force_credit : 1; - mmr_t reserved_0 : 48; - mmr_t max_credits : 6; - mmr_t data_depth : 4; - mmr_t hdr_depth : 4; - } sh_pi_xn2pi_request_vc_config_s; -} sh_pi_xn2pi_request_vc_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_AEC_STATUS" */ /* PI Adaptive Error Correction Status */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_aec_status_u { mmr_t sh_pi_aec_status_regval; struct { @@ -6720,22 +3648,12 @@ typedef union sh_pi_aec_status_u { mmr_t reserved_0 : 61; } sh_pi_aec_status_s; } sh_pi_aec_status_u_t; -#else -typedef union sh_pi_aec_status_u { - mmr_t sh_pi_aec_status_regval; - struct { - mmr_t reserved_0 : 61; - mmr_t state : 3; - } sh_pi_aec_status_s; -} sh_pi_aec_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_AFI_FIRST_ERROR" */ /* PI AFI First Error */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_afi_first_error_u { mmr_t sh_pi_afi_first_error_regval; struct { @@ -6760,39 +3678,12 @@ typedef union sh_pi_afi_first_error_u { mmr_t reserved_2 : 29; } sh_pi_afi_first_error_s; } sh_pi_afi_first_error_u_t; -#else -typedef union sh_pi_afi_first_error_u { - mmr_t sh_pi_afi_first_error_regval; - struct { - mmr_t reserved_2 : 29; - mmr_t msg_len : 1; - mmr_t fsb_tbl_miss : 1; - mmr_t bad_snoop : 1; - mmr_t livelock : 1; - mmr_t shub_fsb_ce : 1; - mmr_t shub_fsb_uce : 1; - mmr_t shub_fsb_dqe : 1; - mmr_t addr_parity : 1; - mmr_t req_parity : 1; - mmr_t addr_access : 1; - mmr_t req_format : 1; - mmr_t ioq_overrun : 1; - mmr_t rsp_parity : 1; - mmr_t hung_bus : 1; - mmr_t reserved_1 : 12; - mmr_t fsb_shub_ce : 1; - mmr_t fsb_shub_uce : 1; - mmr_t reserved_0 : 7; - } sh_pi_afi_first_error_s; -} sh_pi_afi_first_error_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CAM_ADDRESS_READ_DATA" */ /* CRB CAM MMR Address Read Data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_cam_address_read_data_u { mmr_t sh_pi_cam_address_read_data_regval; struct { @@ -6801,44 +3692,24 @@ typedef union sh_pi_cam_address_read_data_u { mmr_t cam_addr_val : 1; } sh_pi_cam_address_read_data_s; } sh_pi_cam_address_read_data_u_t; -#else -typedef union sh_pi_cam_address_read_data_u { - mmr_t sh_pi_cam_address_read_data_regval; - struct { - mmr_t cam_addr_val : 1; - mmr_t reserved_0 : 15; - mmr_t cam_addr : 48; - } sh_pi_cam_address_read_data_s; -} sh_pi_cam_address_read_data_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CAM_LPRA_READ_DATA" */ /* CRB CAM MMR LPRA Read Data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_cam_lpra_read_data_u { mmr_t sh_pi_cam_lpra_read_data_regval; struct { mmr_t cam_lpra : 64; } sh_pi_cam_lpra_read_data_s; } sh_pi_cam_lpra_read_data_u_t; -#else -typedef union sh_pi_cam_lpra_read_data_u { - mmr_t sh_pi_cam_lpra_read_data_regval; - struct { - mmr_t cam_lpra : 64; - } sh_pi_cam_lpra_read_data_s; -} sh_pi_cam_lpra_read_data_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CAM_STATE_READ_DATA" */ /* CRB CAM MMR State Read Data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_cam_state_read_data_u { mmr_t sh_pi_cam_state_read_data_regval; struct { @@ -6851,27 +3722,12 @@ typedef union sh_pi_cam_state_read_data_u { mmr_t cam_rd_data_val : 1; } sh_pi_cam_state_read_data_s; } sh_pi_cam_state_read_data_u_t; -#else -typedef union sh_pi_cam_state_read_data_u { - mmr_t sh_pi_cam_state_read_data_regval; - struct { - mmr_t cam_rd_data_val : 1; - mmr_t reserved_1 : 13; - mmr_t cam_lpra : 18; - mmr_t reserved_0 : 26; - mmr_t cam_state_rd_pend : 1; - mmr_t cam_to : 1; - mmr_t cam_state : 4; - } sh_pi_cam_state_read_data_s; -} sh_pi_cam_state_read_data_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CORRECTED_DETAIL_1" */ /* PI Corrected Error Detail */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_corrected_detail_1_u { mmr_t sh_pi_corrected_detail_1_regval; struct { @@ -6880,44 +3736,24 @@ typedef union sh_pi_corrected_detail_1_u { mmr_t dep : 8; } sh_pi_corrected_detail_1_s; } sh_pi_corrected_detail_1_u_t; -#else -typedef union sh_pi_corrected_detail_1_u { - mmr_t sh_pi_corrected_detail_1_regval; - struct { - mmr_t dep : 8; - mmr_t syndrome : 8; - mmr_t address : 48; - } sh_pi_corrected_detail_1_s; -} sh_pi_corrected_detail_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CORRECTED_DETAIL_2" */ /* PI Corrected Error Detail 2 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_pi_corrected_detail_2_u { - mmr_t sh_pi_corrected_detail_2_regval; - struct { - mmr_t data : 64; - } sh_pi_corrected_detail_2_s; -} sh_pi_corrected_detail_2_u_t; -#else typedef union sh_pi_corrected_detail_2_u { mmr_t sh_pi_corrected_detail_2_regval; struct { mmr_t data : 64; } sh_pi_corrected_detail_2_s; } sh_pi_corrected_detail_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CORRECTED_DETAIL_3" */ /* PI Corrected Error Detail 3 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_corrected_detail_3_u { mmr_t sh_pi_corrected_detail_3_regval; struct { @@ -6926,44 +3762,24 @@ typedef union sh_pi_corrected_detail_3_u { mmr_t dep : 8; } sh_pi_corrected_detail_3_s; } sh_pi_corrected_detail_3_u_t; -#else -typedef union sh_pi_corrected_detail_3_u { - mmr_t sh_pi_corrected_detail_3_regval; - struct { - mmr_t dep : 8; - mmr_t syndrome : 8; - mmr_t address : 48; - } sh_pi_corrected_detail_3_s; -} sh_pi_corrected_detail_3_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CORRECTED_DETAIL_4" */ /* PI Corrected Error Detail 4 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_pi_corrected_detail_4_u { - mmr_t sh_pi_corrected_detail_4_regval; - struct { - mmr_t data : 64; - } sh_pi_corrected_detail_4_s; -} sh_pi_corrected_detail_4_u_t; -#else typedef union sh_pi_corrected_detail_4_u { mmr_t sh_pi_corrected_detail_4_regval; struct { mmr_t data : 64; } sh_pi_corrected_detail_4_s; } sh_pi_corrected_detail_4_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CRBP_FIRST_ERROR" */ /* PI CRBP First Error */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_crbp_first_error_u { mmr_t sh_pi_crbp_first_error_regval; struct { @@ -6991,84 +3807,36 @@ typedef union sh_pi_crbp_first_error_u { mmr_t reserved_0 : 43; } sh_pi_crbp_first_error_s; } sh_pi_crbp_first_error_u_t; -#else -typedef union sh_pi_crbp_first_error_u { - mmr_t sh_pi_crbp_first_error_regval; - struct { - mmr_t reserved_0 : 43; - mmr_t xn_rp_crd_oflow : 1; - mmr_t xn_rq_crd_oflow : 1; - mmr_t md_rp_crd_oflow : 1; - mmr_t md_rq_crd_oflow : 1; - mmr_t gfx_int_1 : 1; - mmr_t gfx_int_0 : 1; - mmr_t nack_oflow : 1; - mmr_t xn_rp_q_oflow : 1; - mmr_t xn_rq_q_oflow : 1; - mmr_t md_rp_q_oflow : 1; - mmr_t md_rq_q_oflow : 1; - mmr_t msg_color_err : 1; - mmr_t fsb_shub_ce : 1; - mmr_t fsb_shub_uce : 1; - mmr_t pio_to_err : 1; - mmr_t mem_to_err : 1; - mmr_t pio_rp_err : 1; - mmr_t mem_rp_err : 1; - mmr_t xb_proto_err : 1; - mmr_t gfx_rp_err : 1; - mmr_t fsb_proto_err : 1; - } sh_pi_crbp_first_error_s; -} sh_pi_crbp_first_error_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_ERROR_DETAIL_1" */ /* PI Error Detail 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_pi_error_detail_1_u { - mmr_t sh_pi_error_detail_1_regval; - struct { - mmr_t status : 64; - } sh_pi_error_detail_1_s; -} sh_pi_error_detail_1_u_t; -#else typedef union sh_pi_error_detail_1_u { mmr_t sh_pi_error_detail_1_regval; struct { mmr_t status : 64; } sh_pi_error_detail_1_s; } sh_pi_error_detail_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_ERROR_DETAIL_2" */ /* PI Error Detail 2 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_pi_error_detail_2_u { - mmr_t sh_pi_error_detail_2_regval; - struct { - mmr_t status : 64; - } sh_pi_error_detail_2_s; -} sh_pi_error_detail_2_u_t; -#else typedef union sh_pi_error_detail_2_u { mmr_t sh_pi_error_detail_2_regval; struct { mmr_t status : 64; } sh_pi_error_detail_2_s; } sh_pi_error_detail_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_ERROR_OVERFLOW" */ /* PI Error Overflow */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_error_overflow_u { mmr_t sh_pi_error_overflow_regval; struct { @@ -7110,56 +3878,12 @@ typedef union sh_pi_error_overflow_u { mmr_t reserved_0 : 29; } sh_pi_error_overflow_s; } sh_pi_error_overflow_u_t; -#else -typedef union sh_pi_error_overflow_u { - mmr_t sh_pi_error_overflow_regval; - struct { - mmr_t reserved_0 : 29; - mmr_t msg_length : 1; - mmr_t fsb_tbl_miss : 1; - mmr_t bad_snoop : 1; - mmr_t livelock : 1; - mmr_t shub_fsb_ce : 1; - mmr_t shub_fsb_uce : 1; - mmr_t shub_fsb_dqe : 1; - mmr_t addr_parity : 1; - mmr_t req_parity : 1; - mmr_t addr_access : 1; - mmr_t req_format : 1; - mmr_t ioq_overrun : 1; - mmr_t rsp_parity : 1; - mmr_t hung_bus : 1; - mmr_t xn_rp_crd_oflow : 1; - mmr_t xn_rq_crd_oflow : 1; - mmr_t md_rp_crd_oflow : 1; - mmr_t md_rq_crd_oflow : 1; - mmr_t gfx_int_1 : 1; - mmr_t gfx_int_0 : 1; - mmr_t nack_oflow : 1; - mmr_t xn_rp_q_oflow : 1; - mmr_t xn_rq_q_oflow : 1; - mmr_t md_rp_q_oflow : 1; - mmr_t md_rq_q_oflow : 1; - mmr_t msg_color_err : 1; - mmr_t fsb_shub_ce : 1; - mmr_t fsb_shub_uce : 1; - mmr_t pio_to_err : 1; - mmr_t mem_to_err : 1; - mmr_t pio_rp_err : 1; - mmr_t mem_rp_err : 1; - mmr_t xb_proto_err : 1; - mmr_t gfx_rp_err : 1; - mmr_t fsb_proto_err : 1; - } sh_pi_error_overflow_s; -} sh_pi_error_overflow_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_ERROR_SUMMARY" */ /* PI Error Summary */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_error_summary_u { mmr_t sh_pi_error_summary_regval; struct { @@ -7201,56 +3925,12 @@ typedef union sh_pi_error_summary_u { mmr_t reserved_0 : 29; } sh_pi_error_summary_s; } sh_pi_error_summary_u_t; -#else -typedef union sh_pi_error_summary_u { - mmr_t sh_pi_error_summary_regval; - struct { - mmr_t reserved_0 : 29; - mmr_t msg_length : 1; - mmr_t fsb_tbl_miss : 1; - mmr_t bad_snoop : 1; - mmr_t livelock : 1; - mmr_t shub_fsb_ce : 1; - mmr_t shub_fsb_uce : 1; - mmr_t shub_fsb_dqe : 1; - mmr_t addr_parity : 1; - mmr_t req_parity : 1; - mmr_t addr_access : 1; - mmr_t req_format : 1; - mmr_t ioq_overrun : 1; - mmr_t rsp_parity : 1; - mmr_t hung_bus : 1; - mmr_t xn_rp_crd_oflow : 1; - mmr_t xn_rq_crd_oflow : 1; - mmr_t md_rp_crd_oflow : 1; - mmr_t md_rq_crd_oflow : 1; - mmr_t gfx_int_1 : 1; - mmr_t gfx_int_0 : 1; - mmr_t nack_oflow : 1; - mmr_t xn_rp_q_oflow : 1; - mmr_t xn_rq_q_oflow : 1; - mmr_t md_rp_q_oflow : 1; - mmr_t md_rq_q_oflow : 1; - mmr_t msg_color_err : 1; - mmr_t fsb_shub_ce : 1; - mmr_t fsb_shub_uce : 1; - mmr_t pio_to_err : 1; - mmr_t mem_to_err : 1; - mmr_t pio_rp_err : 1; - mmr_t mem_rp_err : 1; - mmr_t xb_proto_err : 1; - mmr_t gfx_rp_err : 1; - mmr_t fsb_proto_err : 1; - } sh_pi_error_summary_s; -} sh_pi_error_summary_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_EXPRESS_REPLY_STATUS" */ /* PI Express Reply Status */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_express_reply_status_u { mmr_t sh_pi_express_reply_status_regval; struct { @@ -7258,22 +3938,12 @@ typedef union sh_pi_express_reply_status_u { mmr_t reserved_0 : 61; } sh_pi_express_reply_status_s; } sh_pi_express_reply_status_u_t; -#else -typedef union sh_pi_express_reply_status_u { - mmr_t sh_pi_express_reply_status_regval; - struct { - mmr_t reserved_0 : 61; - mmr_t state : 3; - } sh_pi_express_reply_status_s; -} sh_pi_express_reply_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_FIRST_ERROR" */ /* PI First Error */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_first_error_u { mmr_t sh_pi_first_error_regval; struct { @@ -7315,56 +3985,12 @@ typedef union sh_pi_first_error_u { mmr_t reserved_0 : 29; } sh_pi_first_error_s; } sh_pi_first_error_u_t; -#else -typedef union sh_pi_first_error_u { - mmr_t sh_pi_first_error_regval; - struct { - mmr_t reserved_0 : 29; - mmr_t msg_length : 1; - mmr_t fsb_tbl_miss : 1; - mmr_t bad_snoop : 1; - mmr_t livelock : 1; - mmr_t shub_fsb_ce : 1; - mmr_t shub_fsb_uce : 1; - mmr_t shub_fsb_dqe : 1; - mmr_t addr_parity : 1; - mmr_t req_parity : 1; - mmr_t addr_access : 1; - mmr_t req_format : 1; - mmr_t ioq_overrun : 1; - mmr_t rsp_parity : 1; - mmr_t hung_bus : 1; - mmr_t xn_rp_crd_oflow : 1; - mmr_t xn_rq_crd_oflow : 1; - mmr_t md_rp_crd_oflow : 1; - mmr_t md_rq_crd_oflow : 1; - mmr_t gfx_int_1 : 1; - mmr_t gfx_int_0 : 1; - mmr_t nack_oflow : 1; - mmr_t xn_rp_q_oflow : 1; - mmr_t xn_rq_q_oflow : 1; - mmr_t md_rp_q_oflow : 1; - mmr_t md_rq_q_oflow : 1; - mmr_t msg_color_err : 1; - mmr_t fsb_shub_ce : 1; - mmr_t fsb_shub_uce : 1; - mmr_t pio_to_err : 1; - mmr_t mem_to_err : 1; - mmr_t pio_rp_err : 1; - mmr_t mem_rp_err : 1; - mmr_t xb_proto_err : 1; - mmr_t gfx_rp_err : 1; - mmr_t fsb_proto_err : 1; - } sh_pi_first_error_s; -} sh_pi_first_error_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_PI2MD_REPLY_VC_STATUS" */ /* PI-to-MD Reply Virtual Channel Status */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_pi2md_reply_vc_status_u { mmr_t sh_pi_pi2md_reply_vc_status_regval; struct { @@ -7372,22 +3998,12 @@ typedef union sh_pi_pi2md_reply_vc_status_u { mmr_t reserved_0 : 58; } sh_pi_pi2md_reply_vc_status_s; } sh_pi_pi2md_reply_vc_status_u_t; -#else -typedef union sh_pi_pi2md_reply_vc_status_u { - mmr_t sh_pi_pi2md_reply_vc_status_regval; - struct { - mmr_t reserved_0 : 58; - mmr_t output_crd_stat : 6; - } sh_pi_pi2md_reply_vc_status_s; -} sh_pi_pi2md_reply_vc_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_PI2MD_REQUEST_VC_STATUS" */ /* PI-to-MD Request Virtual Channel Status */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_pi2md_request_vc_status_u { mmr_t sh_pi_pi2md_request_vc_status_regval; struct { @@ -7395,22 +4011,12 @@ typedef union sh_pi_pi2md_request_vc_status_u { mmr_t reserved_0 : 58; } sh_pi_pi2md_request_vc_status_s; } sh_pi_pi2md_request_vc_status_u_t; -#else -typedef union sh_pi_pi2md_request_vc_status_u { - mmr_t sh_pi_pi2md_request_vc_status_regval; - struct { - mmr_t reserved_0 : 58; - mmr_t output_crd_stat : 6; - } sh_pi_pi2md_request_vc_status_s; -} sh_pi_pi2md_request_vc_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_PI2XN_REPLY_VC_STATUS" */ /* PI-to-XN Reply Virtual Channel Status */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_pi2xn_reply_vc_status_u { mmr_t sh_pi_pi2xn_reply_vc_status_regval; struct { @@ -7418,22 +4024,12 @@ typedef union sh_pi_pi2xn_reply_vc_status_u { mmr_t reserved_0 : 58; } sh_pi_pi2xn_reply_vc_status_s; } sh_pi_pi2xn_reply_vc_status_u_t; -#else -typedef union sh_pi_pi2xn_reply_vc_status_u { - mmr_t sh_pi_pi2xn_reply_vc_status_regval; - struct { - mmr_t reserved_0 : 58; - mmr_t output_crd_stat : 6; - } sh_pi_pi2xn_reply_vc_status_s; -} sh_pi_pi2xn_reply_vc_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_PI2XN_REQUEST_VC_STATUS" */ /* PI-to-XN Request Virtual Channel Status */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_pi2xn_request_vc_status_u { mmr_t sh_pi_pi2xn_request_vc_status_regval; struct { @@ -7441,22 +4037,12 @@ typedef union sh_pi_pi2xn_request_vc_status_u { mmr_t reserved_0 : 58; } sh_pi_pi2xn_request_vc_status_s; } sh_pi_pi2xn_request_vc_status_u_t; -#else -typedef union sh_pi_pi2xn_request_vc_status_u { - mmr_t sh_pi_pi2xn_request_vc_status_regval; - struct { - mmr_t reserved_0 : 58; - mmr_t output_crd_stat : 6; - } sh_pi_pi2xn_request_vc_status_s; -} sh_pi_pi2xn_request_vc_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_UNCORRECTED_DETAIL_1" */ /* PI Uncorrected Error Detail 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_uncorrected_detail_1_u { mmr_t sh_pi_uncorrected_detail_1_regval; struct { @@ -7465,44 +4051,24 @@ typedef union sh_pi_uncorrected_detail_1_u { mmr_t dep : 8; } sh_pi_uncorrected_detail_1_s; } sh_pi_uncorrected_detail_1_u_t; -#else -typedef union sh_pi_uncorrected_detail_1_u { - mmr_t sh_pi_uncorrected_detail_1_regval; - struct { - mmr_t dep : 8; - mmr_t syndrome : 8; - mmr_t address : 48; - } sh_pi_uncorrected_detail_1_s; -} sh_pi_uncorrected_detail_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_UNCORRECTED_DETAIL_2" */ /* PI Uncorrected Error Detail 2 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_uncorrected_detail_2_u { mmr_t sh_pi_uncorrected_detail_2_regval; struct { mmr_t data : 64; } sh_pi_uncorrected_detail_2_s; } sh_pi_uncorrected_detail_2_u_t; -#else -typedef union sh_pi_uncorrected_detail_2_u { - mmr_t sh_pi_uncorrected_detail_2_regval; - struct { - mmr_t data : 64; - } sh_pi_uncorrected_detail_2_s; -} sh_pi_uncorrected_detail_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_UNCORRECTED_DETAIL_3" */ /* PI Uncorrected Error Detail 3 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_uncorrected_detail_3_u { mmr_t sh_pi_uncorrected_detail_3_regval; struct { @@ -7511,44 +4077,24 @@ typedef union sh_pi_uncorrected_detail_3_u { mmr_t dep : 8; } sh_pi_uncorrected_detail_3_s; } sh_pi_uncorrected_detail_3_u_t; -#else -typedef union sh_pi_uncorrected_detail_3_u { - mmr_t sh_pi_uncorrected_detail_3_regval; - struct { - mmr_t dep : 8; - mmr_t syndrome : 8; - mmr_t address : 48; - } sh_pi_uncorrected_detail_3_s; -} sh_pi_uncorrected_detail_3_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_UNCORRECTED_DETAIL_4" */ /* PI Uncorrected Error Detail 4 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_pi_uncorrected_detail_4_u { - mmr_t sh_pi_uncorrected_detail_4_regval; - struct { - mmr_t data : 64; - } sh_pi_uncorrected_detail_4_s; -} sh_pi_uncorrected_detail_4_u_t; -#else typedef union sh_pi_uncorrected_detail_4_u { mmr_t sh_pi_uncorrected_detail_4_regval; struct { mmr_t data : 64; } sh_pi_uncorrected_detail_4_s; } sh_pi_uncorrected_detail_4_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_MD2PI_REPLY_VC_STATUS" */ /* MD-to-PI Reply Virtual Channel Status */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_md2pi_reply_vc_status_u { mmr_t sh_pi_md2pi_reply_vc_status_regval; struct { @@ -7558,24 +4104,12 @@ typedef union sh_pi_md2pi_reply_vc_status_u { mmr_t reserved_0 : 52; } sh_pi_md2pi_reply_vc_status_s; } sh_pi_md2pi_reply_vc_status_u_t; -#else -typedef union sh_pi_md2pi_reply_vc_status_u { - mmr_t sh_pi_md2pi_reply_vc_status_regval; - struct { - mmr_t reserved_0 : 52; - mmr_t input_queue_stat : 4; - mmr_t input_dat_crd_stat : 4; - mmr_t input_hdr_crd_stat : 4; - } sh_pi_md2pi_reply_vc_status_s; -} sh_pi_md2pi_reply_vc_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_MD2PI_REQUEST_VC_STATUS" */ /* MD-to-PI Request Virtual Channel Status */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_md2pi_request_vc_status_u { mmr_t sh_pi_md2pi_request_vc_status_regval; struct { @@ -7585,24 +4119,12 @@ typedef union sh_pi_md2pi_request_vc_status_u { mmr_t reserved_0 : 52; } sh_pi_md2pi_request_vc_status_s; } sh_pi_md2pi_request_vc_status_u_t; -#else -typedef union sh_pi_md2pi_request_vc_status_u { - mmr_t sh_pi_md2pi_request_vc_status_regval; - struct { - mmr_t reserved_0 : 52; - mmr_t input_queue_stat : 4; - mmr_t input_dat_crd_stat : 4; - mmr_t input_hdr_crd_stat : 4; - } sh_pi_md2pi_request_vc_status_s; -} sh_pi_md2pi_request_vc_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_XN2PI_REPLY_VC_STATUS" */ /* XN-to-PI Reply Virtual Channel Status */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_xn2pi_reply_vc_status_u { mmr_t sh_pi_xn2pi_reply_vc_status_regval; struct { @@ -7612,24 +4134,12 @@ typedef union sh_pi_xn2pi_reply_vc_status_u { mmr_t reserved_0 : 52; } sh_pi_xn2pi_reply_vc_status_s; } sh_pi_xn2pi_reply_vc_status_u_t; -#else -typedef union sh_pi_xn2pi_reply_vc_status_u { - mmr_t sh_pi_xn2pi_reply_vc_status_regval; - struct { - mmr_t reserved_0 : 52; - mmr_t input_queue_stat : 4; - mmr_t input_dat_crd_stat : 4; - mmr_t input_hdr_crd_stat : 4; - } sh_pi_xn2pi_reply_vc_status_s; -} sh_pi_xn2pi_reply_vc_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_XN2PI_REQUEST_VC_STATUS" */ /* XN-to-PI Request Virtual Channel Status */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_xn2pi_request_vc_status_u { mmr_t sh_pi_xn2pi_request_vc_status_regval; struct { @@ -7639,23 +4149,11 @@ typedef union sh_pi_xn2pi_request_vc_status_u { mmr_t reserved_0 : 52; } sh_pi_xn2pi_request_vc_status_s; } sh_pi_xn2pi_request_vc_status_u_t; -#else -typedef union sh_pi_xn2pi_request_vc_status_u { - mmr_t sh_pi_xn2pi_request_vc_status_regval; - struct { - mmr_t reserved_0 : 52; - mmr_t input_queue_stat : 4; - mmr_t input_dat_crd_stat : 4; - mmr_t input_hdr_crd_stat : 4; - } sh_pi_xn2pi_request_vc_status_s; -} sh_pi_xn2pi_request_vc_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_SIC_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnpi_sic_flow_u { mmr_t sh_xnpi_sic_flow_regval; struct { @@ -7680,38 +4178,11 @@ typedef union sh_xnpi_sic_flow_u { mmr_t disable_bypass_out : 1; } sh_xnpi_sic_flow_s; } sh_xnpi_sic_flow_u_t; -#else -typedef union sh_xnpi_sic_flow_u { - mmr_t sh_xnpi_sic_flow_regval; - struct { - mmr_t disable_bypass_out : 1; - mmr_t reserved_7 : 2; - mmr_t credit_vc2_cap : 5; - mmr_t reserved_6 : 3; - mmr_t credit_vc2_dyn : 5; - mmr_t reserved_5 : 3; - mmr_t credit_vc2_test : 5; - mmr_t reserved_4 : 3; - mmr_t credit_vc0_cap : 5; - mmr_t reserved_3 : 3; - mmr_t credit_vc0_dyn : 5; - mmr_t reserved_2 : 3; - mmr_t credit_vc0_test : 5; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_1 : 2; - mmr_t debit_vc2_withhold : 5; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 2; - mmr_t debit_vc0_withhold : 5; - } sh_xnpi_sic_flow_s; -} sh_xnpi_sic_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_TO_NI0_PORT_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnpi_to_ni0_port_flow_u { mmr_t sh_xnpi_to_ni0_port_flow_regval; struct { @@ -7732,34 +4203,11 @@ typedef union sh_xnpi_to_ni0_port_flow_u { mmr_t reserved_6 : 2; } sh_xnpi_to_ni0_port_flow_s; } sh_xnpi_to_ni0_port_flow_u_t; -#else -typedef union sh_xnpi_to_ni0_port_flow_u { - mmr_t sh_xnpi_to_ni0_port_flow_regval; - struct { - mmr_t reserved_6 : 2; - mmr_t credit_vc2_cap : 6; - mmr_t reserved_5 : 2; - mmr_t credit_vc2_dyn : 6; - mmr_t reserved_4 : 10; - mmr_t credit_vc0_cap : 6; - mmr_t reserved_3 : 2; - mmr_t credit_vc0_dyn : 6; - mmr_t reserved_2 : 8; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnpi_to_ni0_port_flow_s; -} sh_xnpi_to_ni0_port_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_TO_NI1_PORT_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnpi_to_ni1_port_flow_u { mmr_t sh_xnpi_to_ni1_port_flow_regval; struct { @@ -7780,34 +4228,11 @@ typedef union sh_xnpi_to_ni1_port_flow_u { mmr_t reserved_6 : 2; } sh_xnpi_to_ni1_port_flow_s; } sh_xnpi_to_ni1_port_flow_u_t; -#else -typedef union sh_xnpi_to_ni1_port_flow_u { - mmr_t sh_xnpi_to_ni1_port_flow_regval; - struct { - mmr_t reserved_6 : 2; - mmr_t credit_vc2_cap : 6; - mmr_t reserved_5 : 2; - mmr_t credit_vc2_dyn : 6; - mmr_t reserved_4 : 10; - mmr_t credit_vc0_cap : 6; - mmr_t reserved_3 : 2; - mmr_t credit_vc0_dyn : 6; - mmr_t reserved_2 : 8; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnpi_to_ni1_port_flow_s; -} sh_xnpi_to_ni1_port_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_TO_IILB_PORT_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnpi_to_iilb_port_flow_u { mmr_t sh_xnpi_to_iilb_port_flow_regval; struct { @@ -7828,34 +4253,11 @@ typedef union sh_xnpi_to_iilb_port_flow_u { mmr_t reserved_6 : 2; } sh_xnpi_to_iilb_port_flow_s; } sh_xnpi_to_iilb_port_flow_u_t; -#else -typedef union sh_xnpi_to_iilb_port_flow_u { - mmr_t sh_xnpi_to_iilb_port_flow_regval; - struct { - mmr_t reserved_6 : 2; - mmr_t credit_vc2_cap : 6; - mmr_t reserved_5 : 2; - mmr_t credit_vc2_dyn : 6; - mmr_t reserved_4 : 10; - mmr_t credit_vc0_cap : 6; - mmr_t reserved_3 : 2; - mmr_t credit_vc0_dyn : 6; - mmr_t reserved_2 : 8; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnpi_to_iilb_port_flow_s; -} sh_xnpi_to_iilb_port_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_FR_NI0_PORT_FLOW_FIFO" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnpi_fr_ni0_port_flow_fifo_u { mmr_t sh_xnpi_fr_ni0_port_flow_fifo_regval; struct { @@ -7873,31 +4275,11 @@ typedef union sh_xnpi_fr_ni0_port_flow_fifo_u { mmr_t reserved_5 : 19; } sh_xnpi_fr_ni0_port_flow_fifo_s; } sh_xnpi_fr_ni0_port_flow_fifo_u_t; -#else -typedef union sh_xnpi_fr_ni0_port_flow_fifo_u { - mmr_t sh_xnpi_fr_ni0_port_flow_fifo_regval; - struct { - mmr_t reserved_5 : 19; - mmr_t entry_vc2_test : 5; - mmr_t reserved_4 : 3; - mmr_t entry_vc0_test : 5; - mmr_t reserved_3 : 2; - mmr_t entry_vc2_cap : 6; - mmr_t reserved_2 : 2; - mmr_t entry_vc2_dyn : 6; - mmr_t reserved_1 : 2; - mmr_t entry_vc0_cap : 6; - mmr_t reserved_0 : 2; - mmr_t entry_vc0_dyn : 6; - } sh_xnpi_fr_ni0_port_flow_fifo_s; -} sh_xnpi_fr_ni0_port_flow_fifo_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_FR_NI1_PORT_FLOW_FIFO" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnpi_fr_ni1_port_flow_fifo_u { mmr_t sh_xnpi_fr_ni1_port_flow_fifo_regval; struct { @@ -7915,31 +4297,11 @@ typedef union sh_xnpi_fr_ni1_port_flow_fifo_u { mmr_t reserved_5 : 19; } sh_xnpi_fr_ni1_port_flow_fifo_s; } sh_xnpi_fr_ni1_port_flow_fifo_u_t; -#else -typedef union sh_xnpi_fr_ni1_port_flow_fifo_u { - mmr_t sh_xnpi_fr_ni1_port_flow_fifo_regval; - struct { - mmr_t reserved_5 : 19; - mmr_t entry_vc2_test : 5; - mmr_t reserved_4 : 3; - mmr_t entry_vc0_test : 5; - mmr_t reserved_3 : 2; - mmr_t entry_vc2_cap : 6; - mmr_t reserved_2 : 2; - mmr_t entry_vc2_dyn : 6; - mmr_t reserved_1 : 2; - mmr_t entry_vc0_cap : 6; - mmr_t reserved_0 : 2; - mmr_t entry_vc0_dyn : 6; - } sh_xnpi_fr_ni1_port_flow_fifo_s; -} sh_xnpi_fr_ni1_port_flow_fifo_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_FR_IILB_PORT_FLOW_FIFO" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnpi_fr_iilb_port_flow_fifo_u { mmr_t sh_xnpi_fr_iilb_port_flow_fifo_regval; struct { @@ -7957,31 +4319,11 @@ typedef union sh_xnpi_fr_iilb_port_flow_fifo_u { mmr_t reserved_5 : 19; } sh_xnpi_fr_iilb_port_flow_fifo_s; } sh_xnpi_fr_iilb_port_flow_fifo_u_t; -#else -typedef union sh_xnpi_fr_iilb_port_flow_fifo_u { - mmr_t sh_xnpi_fr_iilb_port_flow_fifo_regval; - struct { - mmr_t reserved_5 : 19; - mmr_t entry_vc2_test : 5; - mmr_t reserved_4 : 3; - mmr_t entry_vc0_test : 5; - mmr_t reserved_3 : 2; - mmr_t entry_vc2_cap : 6; - mmr_t reserved_2 : 2; - mmr_t entry_vc2_dyn : 6; - mmr_t reserved_1 : 2; - mmr_t entry_vc0_cap : 6; - mmr_t reserved_0 : 2; - mmr_t entry_vc0_dyn : 6; - } sh_xnpi_fr_iilb_port_flow_fifo_s; -} sh_xnpi_fr_iilb_port_flow_fifo_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_SIC_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnmd_sic_flow_u { mmr_t sh_xnmd_sic_flow_regval; struct { @@ -8006,38 +4348,11 @@ typedef union sh_xnmd_sic_flow_u { mmr_t disable_bypass_out : 1; } sh_xnmd_sic_flow_s; } sh_xnmd_sic_flow_u_t; -#else -typedef union sh_xnmd_sic_flow_u { - mmr_t sh_xnmd_sic_flow_regval; - struct { - mmr_t disable_bypass_out : 1; - mmr_t reserved_7 : 2; - mmr_t credit_vc2_cap : 5; - mmr_t reserved_6 : 3; - mmr_t credit_vc2_dyn : 5; - mmr_t reserved_5 : 3; - mmr_t credit_vc2_test : 5; - mmr_t reserved_4 : 3; - mmr_t credit_vc0_cap : 5; - mmr_t reserved_3 : 3; - mmr_t credit_vc0_dyn : 5; - mmr_t reserved_2 : 3; - mmr_t credit_vc0_test : 5; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_1 : 2; - mmr_t debit_vc2_withhold : 5; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 2; - mmr_t debit_vc0_withhold : 5; - } sh_xnmd_sic_flow_s; -} sh_xnmd_sic_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_TO_NI0_PORT_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnmd_to_ni0_port_flow_u { mmr_t sh_xnmd_to_ni0_port_flow_regval; struct { @@ -8058,34 +4373,11 @@ typedef union sh_xnmd_to_ni0_port_flow_u { mmr_t reserved_6 : 2; } sh_xnmd_to_ni0_port_flow_s; } sh_xnmd_to_ni0_port_flow_u_t; -#else -typedef union sh_xnmd_to_ni0_port_flow_u { - mmr_t sh_xnmd_to_ni0_port_flow_regval; - struct { - mmr_t reserved_6 : 2; - mmr_t credit_vc2_cap : 6; - mmr_t reserved_5 : 2; - mmr_t credit_vc2_dyn : 6; - mmr_t reserved_4 : 10; - mmr_t credit_vc0_cap : 6; - mmr_t reserved_3 : 2; - mmr_t credit_vc0_dyn : 6; - mmr_t reserved_2 : 8; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnmd_to_ni0_port_flow_s; -} sh_xnmd_to_ni0_port_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_TO_NI1_PORT_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnmd_to_ni1_port_flow_u { mmr_t sh_xnmd_to_ni1_port_flow_regval; struct { @@ -8106,34 +4398,11 @@ typedef union sh_xnmd_to_ni1_port_flow_u { mmr_t reserved_6 : 2; } sh_xnmd_to_ni1_port_flow_s; } sh_xnmd_to_ni1_port_flow_u_t; -#else -typedef union sh_xnmd_to_ni1_port_flow_u { - mmr_t sh_xnmd_to_ni1_port_flow_regval; - struct { - mmr_t reserved_6 : 2; - mmr_t credit_vc2_cap : 6; - mmr_t reserved_5 : 2; - mmr_t credit_vc2_dyn : 6; - mmr_t reserved_4 : 10; - mmr_t credit_vc0_cap : 6; - mmr_t reserved_3 : 2; - mmr_t credit_vc0_dyn : 6; - mmr_t reserved_2 : 8; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnmd_to_ni1_port_flow_s; -} sh_xnmd_to_ni1_port_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_TO_IILB_PORT_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnmd_to_iilb_port_flow_u { mmr_t sh_xnmd_to_iilb_port_flow_regval; struct { @@ -8154,34 +4423,11 @@ typedef union sh_xnmd_to_iilb_port_flow_u { mmr_t reserved_6 : 2; } sh_xnmd_to_iilb_port_flow_s; } sh_xnmd_to_iilb_port_flow_u_t; -#else -typedef union sh_xnmd_to_iilb_port_flow_u { - mmr_t sh_xnmd_to_iilb_port_flow_regval; - struct { - mmr_t reserved_6 : 2; - mmr_t credit_vc2_cap : 6; - mmr_t reserved_5 : 2; - mmr_t credit_vc2_dyn : 6; - mmr_t reserved_4 : 10; - mmr_t credit_vc0_cap : 6; - mmr_t reserved_3 : 2; - mmr_t credit_vc0_dyn : 6; - mmr_t reserved_2 : 8; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnmd_to_iilb_port_flow_s; -} sh_xnmd_to_iilb_port_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_FR_NI0_PORT_FLOW_FIFO" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnmd_fr_ni0_port_flow_fifo_u { mmr_t sh_xnmd_fr_ni0_port_flow_fifo_regval; struct { @@ -8199,31 +4445,11 @@ typedef union sh_xnmd_fr_ni0_port_flow_fifo_u { mmr_t reserved_5 : 19; } sh_xnmd_fr_ni0_port_flow_fifo_s; } sh_xnmd_fr_ni0_port_flow_fifo_u_t; -#else -typedef union sh_xnmd_fr_ni0_port_flow_fifo_u { - mmr_t sh_xnmd_fr_ni0_port_flow_fifo_regval; - struct { - mmr_t reserved_5 : 19; - mmr_t entry_vc2_test : 5; - mmr_t reserved_4 : 3; - mmr_t entry_vc0_test : 5; - mmr_t reserved_3 : 2; - mmr_t entry_vc2_cap : 6; - mmr_t reserved_2 : 2; - mmr_t entry_vc2_dyn : 6; - mmr_t reserved_1 : 2; - mmr_t entry_vc0_cap : 6; - mmr_t reserved_0 : 2; - mmr_t entry_vc0_dyn : 6; - } sh_xnmd_fr_ni0_port_flow_fifo_s; -} sh_xnmd_fr_ni0_port_flow_fifo_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_FR_NI1_PORT_FLOW_FIFO" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnmd_fr_ni1_port_flow_fifo_u { mmr_t sh_xnmd_fr_ni1_port_flow_fifo_regval; struct { @@ -8241,31 +4467,11 @@ typedef union sh_xnmd_fr_ni1_port_flow_fifo_u { mmr_t reserved_5 : 19; } sh_xnmd_fr_ni1_port_flow_fifo_s; } sh_xnmd_fr_ni1_port_flow_fifo_u_t; -#else -typedef union sh_xnmd_fr_ni1_port_flow_fifo_u { - mmr_t sh_xnmd_fr_ni1_port_flow_fifo_regval; - struct { - mmr_t reserved_5 : 19; - mmr_t entry_vc2_test : 5; - mmr_t reserved_4 : 3; - mmr_t entry_vc0_test : 5; - mmr_t reserved_3 : 2; - mmr_t entry_vc2_cap : 6; - mmr_t reserved_2 : 2; - mmr_t entry_vc2_dyn : 6; - mmr_t reserved_1 : 2; - mmr_t entry_vc0_cap : 6; - mmr_t reserved_0 : 2; - mmr_t entry_vc0_dyn : 6; - } sh_xnmd_fr_ni1_port_flow_fifo_s; -} sh_xnmd_fr_ni1_port_flow_fifo_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_FR_IILB_PORT_FLOW_FIFO" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnmd_fr_iilb_port_flow_fifo_u { mmr_t sh_xnmd_fr_iilb_port_flow_fifo_regval; struct { @@ -8283,31 +4489,11 @@ typedef union sh_xnmd_fr_iilb_port_flow_fifo_u { mmr_t reserved_5 : 19; } sh_xnmd_fr_iilb_port_flow_fifo_s; } sh_xnmd_fr_iilb_port_flow_fifo_u_t; -#else -typedef union sh_xnmd_fr_iilb_port_flow_fifo_u { - mmr_t sh_xnmd_fr_iilb_port_flow_fifo_regval; - struct { - mmr_t reserved_5 : 19; - mmr_t entry_vc2_test : 5; - mmr_t reserved_4 : 3; - mmr_t entry_vc0_test : 5; - mmr_t reserved_3 : 2; - mmr_t entry_vc2_cap : 6; - mmr_t reserved_2 : 2; - mmr_t entry_vc2_dyn : 6; - mmr_t reserved_1 : 2; - mmr_t entry_vc0_cap : 6; - mmr_t reserved_0 : 2; - mmr_t entry_vc0_dyn : 6; - } sh_xnmd_fr_iilb_port_flow_fifo_s; -} sh_xnmd_fr_iilb_port_flow_fifo_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNII_INTRA_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnii_intra_flow_u { mmr_t sh_xnii_intra_flow_regval; struct { @@ -8331,37 +4517,11 @@ typedef union sh_xnii_intra_flow_u { mmr_t reserved_7 : 1; } sh_xnii_intra_flow_s; } sh_xnii_intra_flow_u_t; -#else -typedef union sh_xnii_intra_flow_u { - mmr_t sh_xnii_intra_flow_regval; - struct { - mmr_t reserved_7 : 1; - mmr_t credit_vc2_cap : 7; - mmr_t reserved_6 : 1; - mmr_t credit_vc2_dyn : 7; - mmr_t reserved_5 : 1; - mmr_t credit_vc2_test : 7; - mmr_t reserved_4 : 1; - mmr_t credit_vc0_cap : 7; - mmr_t reserved_3 : 1; - mmr_t credit_vc0_dyn : 7; - mmr_t reserved_2 : 1; - mmr_t credit_vc0_test : 7; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnii_intra_flow_s; -} sh_xnii_intra_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNLB_INTRA_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnlb_intra_flow_u { mmr_t sh_xnlb_intra_flow_regval; struct { @@ -8385,37 +4545,11 @@ typedef union sh_xnlb_intra_flow_u { mmr_t disable_bypass_in : 1; } sh_xnlb_intra_flow_s; } sh_xnlb_intra_flow_u_t; -#else -typedef union sh_xnlb_intra_flow_u { - mmr_t sh_xnlb_intra_flow_regval; - struct { - mmr_t disable_bypass_in : 1; - mmr_t credit_vc2_cap : 7; - mmr_t reserved_6 : 1; - mmr_t credit_vc2_dyn : 7; - mmr_t reserved_5 : 1; - mmr_t credit_vc2_test : 7; - mmr_t reserved_4 : 1; - mmr_t credit_vc0_cap : 7; - mmr_t reserved_3 : 1; - mmr_t credit_vc0_dyn : 7; - mmr_t reserved_2 : 1; - mmr_t credit_vc0_test : 7; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnlb_intra_flow_s; -} sh_xnlb_intra_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xniilb_to_ni0_intra_flow_debit_u { mmr_t sh_xniilb_to_ni0_intra_flow_debit_regval; struct { @@ -8436,34 +4570,11 @@ typedef union sh_xniilb_to_ni0_intra_flow_debit_u { mmr_t reserved_6 : 1; } sh_xniilb_to_ni0_intra_flow_debit_s; } sh_xniilb_to_ni0_intra_flow_debit_u_t; -#else -typedef union sh_xniilb_to_ni0_intra_flow_debit_u { - mmr_t sh_xniilb_to_ni0_intra_flow_debit_regval; - struct { - mmr_t reserved_6 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 9; - mmr_t vc0_cap : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_2 : 8; - mmr_t vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t vc2_withhold : 6; - mmr_t vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t vc0_withhold : 6; - } sh_xniilb_to_ni0_intra_flow_debit_s; -} sh_xniilb_to_ni0_intra_flow_debit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xniilb_to_ni1_intra_flow_debit_u { mmr_t sh_xniilb_to_ni1_intra_flow_debit_regval; struct { @@ -8484,34 +4595,11 @@ typedef union sh_xniilb_to_ni1_intra_flow_debit_u { mmr_t reserved_6 : 1; } sh_xniilb_to_ni1_intra_flow_debit_s; } sh_xniilb_to_ni1_intra_flow_debit_u_t; -#else -typedef union sh_xniilb_to_ni1_intra_flow_debit_u { - mmr_t sh_xniilb_to_ni1_intra_flow_debit_regval; - struct { - mmr_t reserved_6 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 9; - mmr_t vc0_cap : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_2 : 8; - mmr_t vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t vc2_withhold : 6; - mmr_t vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t vc0_withhold : 6; - } sh_xniilb_to_ni1_intra_flow_debit_s; -} sh_xniilb_to_ni1_intra_flow_debit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xniilb_to_md_intra_flow_debit_u { mmr_t sh_xniilb_to_md_intra_flow_debit_regval; struct { @@ -8532,34 +4620,11 @@ typedef union sh_xniilb_to_md_intra_flow_debit_u { mmr_t reserved_6 : 1; } sh_xniilb_to_md_intra_flow_debit_s; } sh_xniilb_to_md_intra_flow_debit_u_t; -#else -typedef union sh_xniilb_to_md_intra_flow_debit_u { - mmr_t sh_xniilb_to_md_intra_flow_debit_regval; - struct { - mmr_t reserved_6 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 9; - mmr_t vc0_cap : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_2 : 8; - mmr_t vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t vc2_withhold : 6; - mmr_t vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t vc0_withhold : 6; - } sh_xniilb_to_md_intra_flow_debit_s; -} sh_xniilb_to_md_intra_flow_debit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xniilb_to_iilb_intra_flow_debit_u { mmr_t sh_xniilb_to_iilb_intra_flow_debit_regval; struct { @@ -8580,34 +4645,11 @@ typedef union sh_xniilb_to_iilb_intra_flow_debit_u { mmr_t reserved_6 : 1; } sh_xniilb_to_iilb_intra_flow_debit_s; } sh_xniilb_to_iilb_intra_flow_debit_u_t; -#else -typedef union sh_xniilb_to_iilb_intra_flow_debit_u { - mmr_t sh_xniilb_to_iilb_intra_flow_debit_regval; - struct { - mmr_t reserved_6 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 9; - mmr_t vc0_cap : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_2 : 8; - mmr_t vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t vc2_withhold : 6; - mmr_t vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t vc0_withhold : 6; - } sh_xniilb_to_iilb_intra_flow_debit_s; -} sh_xniilb_to_iilb_intra_flow_debit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xniilb_to_pi_intra_flow_debit_u { mmr_t sh_xniilb_to_pi_intra_flow_debit_regval; struct { @@ -8628,34 +4670,11 @@ typedef union sh_xniilb_to_pi_intra_flow_debit_u { mmr_t reserved_6 : 1; } sh_xniilb_to_pi_intra_flow_debit_s; } sh_xniilb_to_pi_intra_flow_debit_u_t; -#else -typedef union sh_xniilb_to_pi_intra_flow_debit_u { - mmr_t sh_xniilb_to_pi_intra_flow_debit_regval; - struct { - mmr_t reserved_6 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 9; - mmr_t vc0_cap : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_2 : 8; - mmr_t vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t vc2_withhold : 6; - mmr_t vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t vc0_withhold : 6; - } sh_xniilb_to_pi_intra_flow_debit_s; -} sh_xniilb_to_pi_intra_flow_debit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xniilb_fr_ni0_intra_flow_credit_u { mmr_t sh_xniilb_fr_ni0_intra_flow_credit_regval; struct { @@ -8673,31 +4692,11 @@ typedef union sh_xniilb_fr_ni0_intra_flow_credit_u { mmr_t reserved_5 : 17; } sh_xniilb_fr_ni0_intra_flow_credit_s; } sh_xniilb_fr_ni0_intra_flow_credit_u_t; -#else -typedef union sh_xniilb_fr_ni0_intra_flow_credit_u { - mmr_t sh_xniilb_fr_ni0_intra_flow_credit_regval; - struct { - mmr_t reserved_5 : 17; - mmr_t vc2_cap : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_2 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_test : 7; - } sh_xniilb_fr_ni0_intra_flow_credit_s; -} sh_xniilb_fr_ni0_intra_flow_credit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xniilb_fr_ni1_intra_flow_credit_u { mmr_t sh_xniilb_fr_ni1_intra_flow_credit_regval; struct { @@ -8715,31 +4714,11 @@ typedef union sh_xniilb_fr_ni1_intra_flow_credit_u { mmr_t reserved_5 : 17; } sh_xniilb_fr_ni1_intra_flow_credit_s; } sh_xniilb_fr_ni1_intra_flow_credit_u_t; -#else -typedef union sh_xniilb_fr_ni1_intra_flow_credit_u { - mmr_t sh_xniilb_fr_ni1_intra_flow_credit_regval; - struct { - mmr_t reserved_5 : 17; - mmr_t vc2_cap : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_2 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_test : 7; - } sh_xniilb_fr_ni1_intra_flow_credit_s; -} sh_xniilb_fr_ni1_intra_flow_credit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xniilb_fr_md_intra_flow_credit_u { mmr_t sh_xniilb_fr_md_intra_flow_credit_regval; struct { @@ -8757,31 +4736,11 @@ typedef union sh_xniilb_fr_md_intra_flow_credit_u { mmr_t reserved_5 : 17; } sh_xniilb_fr_md_intra_flow_credit_s; } sh_xniilb_fr_md_intra_flow_credit_u_t; -#else -typedef union sh_xniilb_fr_md_intra_flow_credit_u { - mmr_t sh_xniilb_fr_md_intra_flow_credit_regval; - struct { - mmr_t reserved_5 : 17; - mmr_t vc2_cap : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_2 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_test : 7; - } sh_xniilb_fr_md_intra_flow_credit_s; -} sh_xniilb_fr_md_intra_flow_credit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xniilb_fr_iilb_intra_flow_credit_u { mmr_t sh_xniilb_fr_iilb_intra_flow_credit_regval; struct { @@ -8799,31 +4758,11 @@ typedef union sh_xniilb_fr_iilb_intra_flow_credit_u { mmr_t reserved_5 : 17; } sh_xniilb_fr_iilb_intra_flow_credit_s; } sh_xniilb_fr_iilb_intra_flow_credit_u_t; -#else -typedef union sh_xniilb_fr_iilb_intra_flow_credit_u { - mmr_t sh_xniilb_fr_iilb_intra_flow_credit_regval; - struct { - mmr_t reserved_5 : 17; - mmr_t vc2_cap : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_2 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_test : 7; - } sh_xniilb_fr_iilb_intra_flow_credit_s; -} sh_xniilb_fr_iilb_intra_flow_credit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xniilb_fr_pi_intra_flow_credit_u { mmr_t sh_xniilb_fr_pi_intra_flow_credit_regval; struct { @@ -8841,31 +4780,11 @@ typedef union sh_xniilb_fr_pi_intra_flow_credit_u { mmr_t reserved_5 : 17; } sh_xniilb_fr_pi_intra_flow_credit_s; } sh_xniilb_fr_pi_intra_flow_credit_u_t; -#else -typedef union sh_xniilb_fr_pi_intra_flow_credit_u { - mmr_t sh_xniilb_fr_pi_intra_flow_credit_regval; - struct { - mmr_t reserved_5 : 17; - mmr_t vc2_cap : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_2 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_test : 7; - } sh_xniilb_fr_pi_intra_flow_credit_s; -} sh_xniilb_fr_pi_intra_flow_credit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_to_pi_intra_flow_debit_u { mmr_t sh_xnni0_to_pi_intra_flow_debit_regval; struct { @@ -8886,34 +4805,11 @@ typedef union sh_xnni0_to_pi_intra_flow_debit_u { mmr_t reserved_6 : 1; } sh_xnni0_to_pi_intra_flow_debit_s; } sh_xnni0_to_pi_intra_flow_debit_u_t; -#else -typedef union sh_xnni0_to_pi_intra_flow_debit_u { - mmr_t sh_xnni0_to_pi_intra_flow_debit_regval; - struct { - mmr_t reserved_6 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 9; - mmr_t vc0_cap : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_2 : 8; - mmr_t vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t vc2_withhold : 6; - mmr_t vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t vc0_withhold : 6; - } sh_xnni0_to_pi_intra_flow_debit_s; -} sh_xnni0_to_pi_intra_flow_debit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_to_md_intra_flow_debit_u { mmr_t sh_xnni0_to_md_intra_flow_debit_regval; struct { @@ -8934,34 +4830,11 @@ typedef union sh_xnni0_to_md_intra_flow_debit_u { mmr_t reserved_6 : 1; } sh_xnni0_to_md_intra_flow_debit_s; } sh_xnni0_to_md_intra_flow_debit_u_t; -#else -typedef union sh_xnni0_to_md_intra_flow_debit_u { - mmr_t sh_xnni0_to_md_intra_flow_debit_regval; - struct { - mmr_t reserved_6 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 9; - mmr_t vc0_cap : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_2 : 8; - mmr_t vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t vc2_withhold : 6; - mmr_t vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t vc0_withhold : 6; - } sh_xnni0_to_md_intra_flow_debit_s; -} sh_xnni0_to_md_intra_flow_debit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_to_iilb_intra_flow_debit_u { mmr_t sh_xnni0_to_iilb_intra_flow_debit_regval; struct { @@ -8982,34 +4855,11 @@ typedef union sh_xnni0_to_iilb_intra_flow_debit_u { mmr_t reserved_6 : 1; } sh_xnni0_to_iilb_intra_flow_debit_s; } sh_xnni0_to_iilb_intra_flow_debit_u_t; -#else -typedef union sh_xnni0_to_iilb_intra_flow_debit_u { - mmr_t sh_xnni0_to_iilb_intra_flow_debit_regval; - struct { - mmr_t reserved_6 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 9; - mmr_t vc0_cap : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_2 : 8; - mmr_t vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t vc2_withhold : 6; - mmr_t vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t vc0_withhold : 6; - } sh_xnni0_to_iilb_intra_flow_debit_s; -} sh_xnni0_to_iilb_intra_flow_debit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_fr_pi_intra_flow_credit_u { mmr_t sh_xnni0_fr_pi_intra_flow_credit_regval; struct { @@ -9027,31 +4877,11 @@ typedef union sh_xnni0_fr_pi_intra_flow_credit_u { mmr_t reserved_5 : 17; } sh_xnni0_fr_pi_intra_flow_credit_s; } sh_xnni0_fr_pi_intra_flow_credit_u_t; -#else -typedef union sh_xnni0_fr_pi_intra_flow_credit_u { - mmr_t sh_xnni0_fr_pi_intra_flow_credit_regval; - struct { - mmr_t reserved_5 : 17; - mmr_t vc2_cap : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_2 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_test : 7; - } sh_xnni0_fr_pi_intra_flow_credit_s; -} sh_xnni0_fr_pi_intra_flow_credit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_fr_md_intra_flow_credit_u { mmr_t sh_xnni0_fr_md_intra_flow_credit_regval; struct { @@ -9069,31 +4899,11 @@ typedef union sh_xnni0_fr_md_intra_flow_credit_u { mmr_t reserved_5 : 17; } sh_xnni0_fr_md_intra_flow_credit_s; } sh_xnni0_fr_md_intra_flow_credit_u_t; -#else -typedef union sh_xnni0_fr_md_intra_flow_credit_u { - mmr_t sh_xnni0_fr_md_intra_flow_credit_regval; - struct { - mmr_t reserved_5 : 17; - mmr_t vc2_cap : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_2 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_test : 7; - } sh_xnni0_fr_md_intra_flow_credit_s; -} sh_xnni0_fr_md_intra_flow_credit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_fr_iilb_intra_flow_credit_u { mmr_t sh_xnni0_fr_iilb_intra_flow_credit_regval; struct { @@ -9111,31 +4921,11 @@ typedef union sh_xnni0_fr_iilb_intra_flow_credit_u { mmr_t reserved_5 : 17; } sh_xnni0_fr_iilb_intra_flow_credit_s; } sh_xnni0_fr_iilb_intra_flow_credit_u_t; -#else -typedef union sh_xnni0_fr_iilb_intra_flow_credit_u { - mmr_t sh_xnni0_fr_iilb_intra_flow_credit_regval; - struct { - mmr_t reserved_5 : 17; - mmr_t vc2_cap : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_2 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_test : 7; - } sh_xnni0_fr_iilb_intra_flow_credit_s; -} sh_xnni0_fr_iilb_intra_flow_credit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_0_INTRANI_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_0_intrani_flow_u { mmr_t sh_xnni0_0_intrani_flow_regval; struct { @@ -9145,23 +4935,11 @@ typedef union sh_xnni0_0_intrani_flow_u { mmr_t reserved_1 : 56; } sh_xnni0_0_intrani_flow_s; } sh_xnni0_0_intrani_flow_u_t; -#else -typedef union sh_xnni0_0_intrani_flow_u { - mmr_t sh_xnni0_0_intrani_flow_regval; - struct { - mmr_t reserved_1 : 56; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnni0_0_intrani_flow_s; -} sh_xnni0_0_intrani_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_1_INTRANI_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_1_intrani_flow_u { mmr_t sh_xnni0_1_intrani_flow_regval; struct { @@ -9171,23 +4949,11 @@ typedef union sh_xnni0_1_intrani_flow_u { mmr_t reserved_1 : 56; } sh_xnni0_1_intrani_flow_s; } sh_xnni0_1_intrani_flow_u_t; -#else -typedef union sh_xnni0_1_intrani_flow_u { - mmr_t sh_xnni0_1_intrani_flow_regval; - struct { - mmr_t reserved_1 : 56; - mmr_t debit_vc1_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc1_withhold : 6; - } sh_xnni0_1_intrani_flow_s; -} sh_xnni0_1_intrani_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_2_INTRANI_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_2_intrani_flow_u { mmr_t sh_xnni0_2_intrani_flow_regval; struct { @@ -9197,23 +4963,11 @@ typedef union sh_xnni0_2_intrani_flow_u { mmr_t reserved_1 : 56; } sh_xnni0_2_intrani_flow_s; } sh_xnni0_2_intrani_flow_u_t; -#else -typedef union sh_xnni0_2_intrani_flow_u { - mmr_t sh_xnni0_2_intrani_flow_regval; - struct { - mmr_t reserved_1 : 56; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc2_withhold : 6; - } sh_xnni0_2_intrani_flow_s; -} sh_xnni0_2_intrani_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_3_INTRANI_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_3_intrani_flow_u { mmr_t sh_xnni0_3_intrani_flow_regval; struct { @@ -9223,23 +4977,11 @@ typedef union sh_xnni0_3_intrani_flow_u { mmr_t reserved_1 : 56; } sh_xnni0_3_intrani_flow_s; } sh_xnni0_3_intrani_flow_u_t; -#else -typedef union sh_xnni0_3_intrani_flow_u { - mmr_t sh_xnni0_3_intrani_flow_regval; - struct { - mmr_t reserved_1 : 56; - mmr_t debit_vc3_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc3_withhold : 6; - } sh_xnni0_3_intrani_flow_s; -} sh_xnni0_3_intrani_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_VCSWITCH_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_vcswitch_flow_u { mmr_t sh_xnni0_vcswitch_flow_regval; struct { @@ -9257,31 +4999,11 @@ typedef union sh_xnni0_vcswitch_flow_u { mmr_t reserved_4 : 29; } sh_xnni0_vcswitch_flow_s; } sh_xnni0_vcswitch_flow_u_t; -#else -typedef union sh_xnni0_vcswitch_flow_u { - mmr_t sh_xnni0_vcswitch_flow_regval; - struct { - mmr_t reserved_4 : 29; - mmr_t async_fifoes : 1; - mmr_t disable_sync_bypass_out : 1; - mmr_t disable_sync_bypass_in : 1; - mmr_t reserved_3 : 7; - mmr_t iilb_vcfifo_switch : 1; - mmr_t reserved_2 : 7; - mmr_t md_vcfifo_switch : 1; - mmr_t reserved_1 : 7; - mmr_t pi_vcfifo_switch : 1; - mmr_t reserved_0 : 7; - mmr_t ni_vcfifo_dateline_switch : 1; - } sh_xnni0_vcswitch_flow_s; -} sh_xnni0_vcswitch_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_TIMER_REG" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_timer_reg_u { mmr_t sh_xnni0_timer_reg_regval; struct { @@ -9291,23 +5013,11 @@ typedef union sh_xnni0_timer_reg_u { mmr_t reserved_1 : 31; } sh_xnni0_timer_reg_s; } sh_xnni0_timer_reg_u_t; -#else -typedef union sh_xnni0_timer_reg_u { - mmr_t sh_xnni0_timer_reg_regval; - struct { - mmr_t reserved_1 : 31; - mmr_t linkcleanup_reg : 1; - mmr_t reserved_0 : 8; - mmr_t timeout_reg : 24; - } sh_xnni0_timer_reg_s; -} sh_xnni0_timer_reg_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_FIFO02_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_fifo02_flow_u { mmr_t sh_xnni0_fifo02_flow_regval; struct { @@ -9325,31 +5035,11 @@ typedef union sh_xnni0_fifo02_flow_u { mmr_t reserved_5 : 20; } sh_xnni0_fifo02_flow_s; } sh_xnni0_fifo02_flow_u_t; -#else -typedef union sh_xnni0_fifo02_flow_u { - mmr_t sh_xnni0_fifo02_flow_regval; - struct { - mmr_t reserved_5 : 20; - mmr_t count_vc2_cap : 4; - mmr_t reserved_4 : 4; - mmr_t count_vc2_dyn : 4; - mmr_t reserved_3 : 4; - mmr_t count_vc2_limit : 4; - mmr_t reserved_2 : 4; - mmr_t count_vc0_cap : 4; - mmr_t reserved_1 : 4; - mmr_t count_vc0_dyn : 4; - mmr_t reserved_0 : 4; - mmr_t count_vc0_limit : 4; - } sh_xnni0_fifo02_flow_s; -} sh_xnni0_fifo02_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_FIFO13_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_fifo13_flow_u { mmr_t sh_xnni0_fifo13_flow_regval; struct { @@ -9367,31 +5057,11 @@ typedef union sh_xnni0_fifo13_flow_u { mmr_t reserved_5 : 20; } sh_xnni0_fifo13_flow_s; } sh_xnni0_fifo13_flow_u_t; -#else -typedef union sh_xnni0_fifo13_flow_u { - mmr_t sh_xnni0_fifo13_flow_regval; - struct { - mmr_t reserved_5 : 20; - mmr_t count_vc3_cap : 4; - mmr_t reserved_4 : 4; - mmr_t count_vc3_dyn : 4; - mmr_t reserved_3 : 4; - mmr_t count_vc3_limit : 4; - mmr_t reserved_2 : 4; - mmr_t count_vc1_cap : 4; - mmr_t reserved_1 : 4; - mmr_t count_vc1_dyn : 4; - mmr_t reserved_0 : 4; - mmr_t count_vc1_limit : 4; - } sh_xnni0_fifo13_flow_s; -} sh_xnni0_fifo13_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_NI_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_ni_flow_u { mmr_t sh_xnni0_ni_flow_regval; struct { @@ -9413,35 +5083,11 @@ typedef union sh_xnni0_ni_flow_u { mmr_t vc3_cap : 4; } sh_xnni0_ni_flow_s; } sh_xnni0_ni_flow_u_t; -#else -typedef union sh_xnni0_ni_flow_u { - mmr_t sh_xnni0_ni_flow_regval; - struct { - mmr_t vc3_cap : 4; - mmr_t vc3_dyn : 4; - mmr_t reserved_3 : 4; - mmr_t vc3_limit : 4; - mmr_t vc2_cap : 4; - mmr_t vc2_dyn : 4; - mmr_t reserved_2 : 4; - mmr_t vc2_limit : 4; - mmr_t vc1_cap : 4; - mmr_t vc1_dyn : 4; - mmr_t reserved_1 : 4; - mmr_t vc1_limit : 4; - mmr_t vc0_cap : 4; - mmr_t vc0_dyn : 4; - mmr_t reserved_0 : 4; - mmr_t vc0_limit : 4; - } sh_xnni0_ni_flow_s; -} sh_xnni0_ni_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_DEAD_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_dead_flow_u { mmr_t sh_xnni0_dead_flow_regval; struct { @@ -9463,35 +5109,11 @@ typedef union sh_xnni0_dead_flow_u { mmr_t vc3_cap : 4; } sh_xnni0_dead_flow_s; } sh_xnni0_dead_flow_u_t; -#else -typedef union sh_xnni0_dead_flow_u { - mmr_t sh_xnni0_dead_flow_regval; - struct { - mmr_t vc3_cap : 4; - mmr_t vc3_dyn : 4; - mmr_t reserved_3 : 4; - mmr_t vc3_limit : 4; - mmr_t vc2_cap : 4; - mmr_t vc2_dyn : 4; - mmr_t reserved_2 : 4; - mmr_t vc2_limit : 4; - mmr_t vc1_cap : 4; - mmr_t vc1_dyn : 4; - mmr_t reserved_1 : 4; - mmr_t vc1_limit : 4; - mmr_t vc0_cap : 4; - mmr_t vc0_dyn : 4; - mmr_t reserved_0 : 4; - mmr_t vc0_limit : 4; - } sh_xnni0_dead_flow_s; -} sh_xnni0_dead_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_INJECT_AGE" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_inject_age_u { mmr_t sh_xnni0_inject_age_regval; struct { @@ -9500,22 +5122,11 @@ typedef union sh_xnni0_inject_age_u { mmr_t reserved_0 : 48; } sh_xnni0_inject_age_s; } sh_xnni0_inject_age_u_t; -#else -typedef union sh_xnni0_inject_age_u { - mmr_t sh_xnni0_inject_age_regval; - struct { - mmr_t reserved_0 : 48; - mmr_t reply_inject : 8; - mmr_t request_inject : 8; - } sh_xnni0_inject_age_s; -} sh_xnni0_inject_age_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_to_pi_intra_flow_debit_u { mmr_t sh_xnni1_to_pi_intra_flow_debit_regval; struct { @@ -9536,34 +5147,11 @@ typedef union sh_xnni1_to_pi_intra_flow_debit_u { mmr_t reserved_6 : 1; } sh_xnni1_to_pi_intra_flow_debit_s; } sh_xnni1_to_pi_intra_flow_debit_u_t; -#else -typedef union sh_xnni1_to_pi_intra_flow_debit_u { - mmr_t sh_xnni1_to_pi_intra_flow_debit_regval; - struct { - mmr_t reserved_6 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 9; - mmr_t vc0_cap : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_2 : 8; - mmr_t vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t vc2_withhold : 6; - mmr_t vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t vc0_withhold : 6; - } sh_xnni1_to_pi_intra_flow_debit_s; -} sh_xnni1_to_pi_intra_flow_debit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_to_md_intra_flow_debit_u { mmr_t sh_xnni1_to_md_intra_flow_debit_regval; struct { @@ -9584,34 +5172,11 @@ typedef union sh_xnni1_to_md_intra_flow_debit_u { mmr_t reserved_6 : 1; } sh_xnni1_to_md_intra_flow_debit_s; } sh_xnni1_to_md_intra_flow_debit_u_t; -#else -typedef union sh_xnni1_to_md_intra_flow_debit_u { - mmr_t sh_xnni1_to_md_intra_flow_debit_regval; - struct { - mmr_t reserved_6 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 9; - mmr_t vc0_cap : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_2 : 8; - mmr_t vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t vc2_withhold : 6; - mmr_t vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t vc0_withhold : 6; - } sh_xnni1_to_md_intra_flow_debit_s; -} sh_xnni1_to_md_intra_flow_debit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_to_iilb_intra_flow_debit_u { mmr_t sh_xnni1_to_iilb_intra_flow_debit_regval; struct { @@ -9632,34 +5197,11 @@ typedef union sh_xnni1_to_iilb_intra_flow_debit_u { mmr_t reserved_6 : 1; } sh_xnni1_to_iilb_intra_flow_debit_s; } sh_xnni1_to_iilb_intra_flow_debit_u_t; -#else -typedef union sh_xnni1_to_iilb_intra_flow_debit_u { - mmr_t sh_xnni1_to_iilb_intra_flow_debit_regval; - struct { - mmr_t reserved_6 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 9; - mmr_t vc0_cap : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_2 : 8; - mmr_t vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t vc2_withhold : 6; - mmr_t vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t vc0_withhold : 6; - } sh_xnni1_to_iilb_intra_flow_debit_s; -} sh_xnni1_to_iilb_intra_flow_debit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_fr_pi_intra_flow_credit_u { mmr_t sh_xnni1_fr_pi_intra_flow_credit_regval; struct { @@ -9677,31 +5219,11 @@ typedef union sh_xnni1_fr_pi_intra_flow_credit_u { mmr_t reserved_5 : 17; } sh_xnni1_fr_pi_intra_flow_credit_s; } sh_xnni1_fr_pi_intra_flow_credit_u_t; -#else -typedef union sh_xnni1_fr_pi_intra_flow_credit_u { - mmr_t sh_xnni1_fr_pi_intra_flow_credit_regval; - struct { - mmr_t reserved_5 : 17; - mmr_t vc2_cap : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_2 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_test : 7; - } sh_xnni1_fr_pi_intra_flow_credit_s; -} sh_xnni1_fr_pi_intra_flow_credit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_fr_md_intra_flow_credit_u { mmr_t sh_xnni1_fr_md_intra_flow_credit_regval; struct { @@ -9719,31 +5241,11 @@ typedef union sh_xnni1_fr_md_intra_flow_credit_u { mmr_t reserved_5 : 17; } sh_xnni1_fr_md_intra_flow_credit_s; } sh_xnni1_fr_md_intra_flow_credit_u_t; -#else -typedef union sh_xnni1_fr_md_intra_flow_credit_u { - mmr_t sh_xnni1_fr_md_intra_flow_credit_regval; - struct { - mmr_t reserved_5 : 17; - mmr_t vc2_cap : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_2 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_test : 7; - } sh_xnni1_fr_md_intra_flow_credit_s; -} sh_xnni1_fr_md_intra_flow_credit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_fr_iilb_intra_flow_credit_u { mmr_t sh_xnni1_fr_iilb_intra_flow_credit_regval; struct { @@ -9761,31 +5263,11 @@ typedef union sh_xnni1_fr_iilb_intra_flow_credit_u { mmr_t reserved_5 : 17; } sh_xnni1_fr_iilb_intra_flow_credit_s; } sh_xnni1_fr_iilb_intra_flow_credit_u_t; -#else -typedef union sh_xnni1_fr_iilb_intra_flow_credit_u { - mmr_t sh_xnni1_fr_iilb_intra_flow_credit_regval; - struct { - mmr_t reserved_5 : 17; - mmr_t vc2_cap : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_2 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_test : 7; - } sh_xnni1_fr_iilb_intra_flow_credit_s; -} sh_xnni1_fr_iilb_intra_flow_credit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_0_INTRANI_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_0_intrani_flow_u { mmr_t sh_xnni1_0_intrani_flow_regval; struct { @@ -9795,23 +5277,11 @@ typedef union sh_xnni1_0_intrani_flow_u { mmr_t reserved_1 : 56; } sh_xnni1_0_intrani_flow_s; } sh_xnni1_0_intrani_flow_u_t; -#else -typedef union sh_xnni1_0_intrani_flow_u { - mmr_t sh_xnni1_0_intrani_flow_regval; - struct { - mmr_t reserved_1 : 56; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnni1_0_intrani_flow_s; -} sh_xnni1_0_intrani_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_1_INTRANI_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_1_intrani_flow_u { mmr_t sh_xnni1_1_intrani_flow_regval; struct { @@ -9821,23 +5291,11 @@ typedef union sh_xnni1_1_intrani_flow_u { mmr_t reserved_1 : 56; } sh_xnni1_1_intrani_flow_s; } sh_xnni1_1_intrani_flow_u_t; -#else -typedef union sh_xnni1_1_intrani_flow_u { - mmr_t sh_xnni1_1_intrani_flow_regval; - struct { - mmr_t reserved_1 : 56; - mmr_t debit_vc1_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc1_withhold : 6; - } sh_xnni1_1_intrani_flow_s; -} sh_xnni1_1_intrani_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_2_INTRANI_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_2_intrani_flow_u { mmr_t sh_xnni1_2_intrani_flow_regval; struct { @@ -9847,23 +5305,11 @@ typedef union sh_xnni1_2_intrani_flow_u { mmr_t reserved_1 : 56; } sh_xnni1_2_intrani_flow_s; } sh_xnni1_2_intrani_flow_u_t; -#else -typedef union sh_xnni1_2_intrani_flow_u { - mmr_t sh_xnni1_2_intrani_flow_regval; - struct { - mmr_t reserved_1 : 56; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc2_withhold : 6; - } sh_xnni1_2_intrani_flow_s; -} sh_xnni1_2_intrani_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_3_INTRANI_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_3_intrani_flow_u { mmr_t sh_xnni1_3_intrani_flow_regval; struct { @@ -9873,23 +5319,11 @@ typedef union sh_xnni1_3_intrani_flow_u { mmr_t reserved_1 : 56; } sh_xnni1_3_intrani_flow_s; } sh_xnni1_3_intrani_flow_u_t; -#else -typedef union sh_xnni1_3_intrani_flow_u { - mmr_t sh_xnni1_3_intrani_flow_regval; - struct { - mmr_t reserved_1 : 56; - mmr_t debit_vc3_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc3_withhold : 6; - } sh_xnni1_3_intrani_flow_s; -} sh_xnni1_3_intrani_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_VCSWITCH_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_vcswitch_flow_u { mmr_t sh_xnni1_vcswitch_flow_regval; struct { @@ -9907,31 +5341,11 @@ typedef union sh_xnni1_vcswitch_flow_u { mmr_t reserved_4 : 29; } sh_xnni1_vcswitch_flow_s; } sh_xnni1_vcswitch_flow_u_t; -#else -typedef union sh_xnni1_vcswitch_flow_u { - mmr_t sh_xnni1_vcswitch_flow_regval; - struct { - mmr_t reserved_4 : 29; - mmr_t async_fifoes : 1; - mmr_t disable_sync_bypass_out : 1; - mmr_t disable_sync_bypass_in : 1; - mmr_t reserved_3 : 7; - mmr_t iilb_vcfifo_switch : 1; - mmr_t reserved_2 : 7; - mmr_t md_vcfifo_switch : 1; - mmr_t reserved_1 : 7; - mmr_t pi_vcfifo_switch : 1; - mmr_t reserved_0 : 7; - mmr_t ni_vcfifo_dateline_switch : 1; - } sh_xnni1_vcswitch_flow_s; -} sh_xnni1_vcswitch_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_TIMER_REG" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_timer_reg_u { mmr_t sh_xnni1_timer_reg_regval; struct { @@ -9941,23 +5355,11 @@ typedef union sh_xnni1_timer_reg_u { mmr_t reserved_1 : 31; } sh_xnni1_timer_reg_s; } sh_xnni1_timer_reg_u_t; -#else -typedef union sh_xnni1_timer_reg_u { - mmr_t sh_xnni1_timer_reg_regval; - struct { - mmr_t reserved_1 : 31; - mmr_t linkcleanup_reg : 1; - mmr_t reserved_0 : 8; - mmr_t timeout_reg : 24; - } sh_xnni1_timer_reg_s; -} sh_xnni1_timer_reg_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_FIFO02_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_fifo02_flow_u { mmr_t sh_xnni1_fifo02_flow_regval; struct { @@ -9975,31 +5377,11 @@ typedef union sh_xnni1_fifo02_flow_u { mmr_t reserved_5 : 20; } sh_xnni1_fifo02_flow_s; } sh_xnni1_fifo02_flow_u_t; -#else -typedef union sh_xnni1_fifo02_flow_u { - mmr_t sh_xnni1_fifo02_flow_regval; - struct { - mmr_t reserved_5 : 20; - mmr_t count_vc2_cap : 4; - mmr_t reserved_4 : 4; - mmr_t count_vc2_dyn : 4; - mmr_t reserved_3 : 4; - mmr_t count_vc2_limit : 4; - mmr_t reserved_2 : 4; - mmr_t count_vc0_cap : 4; - mmr_t reserved_1 : 4; - mmr_t count_vc0_dyn : 4; - mmr_t reserved_0 : 4; - mmr_t count_vc0_limit : 4; - } sh_xnni1_fifo02_flow_s; -} sh_xnni1_fifo02_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_FIFO13_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_fifo13_flow_u { mmr_t sh_xnni1_fifo13_flow_regval; struct { @@ -10017,31 +5399,11 @@ typedef union sh_xnni1_fifo13_flow_u { mmr_t reserved_5 : 20; } sh_xnni1_fifo13_flow_s; } sh_xnni1_fifo13_flow_u_t; -#else -typedef union sh_xnni1_fifo13_flow_u { - mmr_t sh_xnni1_fifo13_flow_regval; - struct { - mmr_t reserved_5 : 20; - mmr_t count_vc3_cap : 4; - mmr_t reserved_4 : 4; - mmr_t count_vc3_dyn : 4; - mmr_t reserved_3 : 4; - mmr_t count_vc3_limit : 4; - mmr_t reserved_2 : 4; - mmr_t count_vc1_cap : 4; - mmr_t reserved_1 : 4; - mmr_t count_vc1_dyn : 4; - mmr_t reserved_0 : 4; - mmr_t count_vc1_limit : 4; - } sh_xnni1_fifo13_flow_s; -} sh_xnni1_fifo13_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_NI_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_ni_flow_u { mmr_t sh_xnni1_ni_flow_regval; struct { @@ -10063,35 +5425,11 @@ typedef union sh_xnni1_ni_flow_u { mmr_t vc3_cap : 4; } sh_xnni1_ni_flow_s; } sh_xnni1_ni_flow_u_t; -#else -typedef union sh_xnni1_ni_flow_u { - mmr_t sh_xnni1_ni_flow_regval; - struct { - mmr_t vc3_cap : 4; - mmr_t vc3_dyn : 4; - mmr_t reserved_3 : 4; - mmr_t vc3_limit : 4; - mmr_t vc2_cap : 4; - mmr_t vc2_dyn : 4; - mmr_t reserved_2 : 4; - mmr_t vc2_limit : 4; - mmr_t vc1_cap : 4; - mmr_t vc1_dyn : 4; - mmr_t reserved_1 : 4; - mmr_t vc1_limit : 4; - mmr_t vc0_cap : 4; - mmr_t vc0_dyn : 4; - mmr_t reserved_0 : 4; - mmr_t vc0_limit : 4; - } sh_xnni1_ni_flow_s; -} sh_xnni1_ni_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_DEAD_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_dead_flow_u { mmr_t sh_xnni1_dead_flow_regval; struct { @@ -10113,35 +5451,11 @@ typedef union sh_xnni1_dead_flow_u { mmr_t vc3_cap : 4; } sh_xnni1_dead_flow_s; } sh_xnni1_dead_flow_u_t; -#else -typedef union sh_xnni1_dead_flow_u { - mmr_t sh_xnni1_dead_flow_regval; - struct { - mmr_t vc3_cap : 4; - mmr_t vc3_dyn : 4; - mmr_t reserved_3 : 4; - mmr_t vc3_limit : 4; - mmr_t vc2_cap : 4; - mmr_t vc2_dyn : 4; - mmr_t reserved_2 : 4; - mmr_t vc2_limit : 4; - mmr_t vc1_cap : 4; - mmr_t vc1_dyn : 4; - mmr_t reserved_1 : 4; - mmr_t vc1_limit : 4; - mmr_t vc0_cap : 4; - mmr_t vc0_dyn : 4; - mmr_t reserved_0 : 4; - mmr_t vc0_limit : 4; - } sh_xnni1_dead_flow_s; -} sh_xnni1_dead_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_INJECT_AGE" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_inject_age_u { mmr_t sh_xnni1_inject_age_regval; struct { @@ -10150,23 +5464,12 @@ typedef union sh_xnni1_inject_age_u { mmr_t reserved_0 : 48; } sh_xnni1_inject_age_s; } sh_xnni1_inject_age_u_t; -#else -typedef union sh_xnni1_inject_age_u { - mmr_t sh_xnni1_inject_age_regval; - struct { - mmr_t reserved_0 : 48; - mmr_t reply_inject : 8; - mmr_t request_inject : 8; - } sh_xnni1_inject_age_s; -} sh_xnni1_inject_age_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_DEBUG_SEL" */ /* XN Debug Port Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_debug_sel_u { mmr_t sh_xn_debug_sel_regval; struct { @@ -10204,52 +5507,12 @@ typedef union sh_xn_debug_sel_u { mmr_t trigger_enable : 1; } sh_xn_debug_sel_s; } sh_xn_debug_sel_u_t; -#else -typedef union sh_xn_debug_sel_u { - mmr_t sh_xn_debug_sel_regval; - struct { - mmr_t trigger_enable : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_rlm_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_rlm_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_rlm_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_rlm_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_rlm_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_rlm_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_rlm_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_rlm_sel : 3; - } sh_xn_debug_sel_s; -} sh_xn_debug_sel_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_DEBUG_TRIG_SEL" */ /* XN Debug trigger Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_debug_trig_sel_u { mmr_t sh_xn_debug_trig_sel_regval; struct { @@ -10287,52 +5550,12 @@ typedef union sh_xn_debug_trig_sel_u { mmr_t reserved_15 : 1; } sh_xn_debug_trig_sel_s; } sh_xn_debug_trig_sel_u_t; -#else -typedef union sh_xn_debug_trig_sel_u { - mmr_t sh_xn_debug_trig_sel_regval; - struct { - mmr_t reserved_15 : 1; - mmr_t trigger7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t trigger7_rlm_sel : 3; - mmr_t reserved_13 : 1; - mmr_t trigger6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t trigger6_rlm_sel : 3; - mmr_t reserved_11 : 1; - mmr_t trigger5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t trigger5_rlm_sel : 3; - mmr_t reserved_9 : 1; - mmr_t trigger4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t trigger4_rlm_sel : 3; - mmr_t reserved_7 : 1; - mmr_t trigger3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t trigger3_rlm_sel : 3; - mmr_t reserved_5 : 1; - mmr_t trigger2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t trigger2_rlm_sel : 3; - mmr_t reserved_3 : 1; - mmr_t trigger1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t trigger1_rlm_sel : 3; - mmr_t reserved_1 : 1; - mmr_t trigger0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t trigger0_rlm_sel : 3; - } sh_xn_debug_trig_sel_s; -} sh_xn_debug_trig_sel_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_TRIGGER_COMPARE" */ /* XN Debug Compare */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_trigger_compare_u { mmr_t sh_xn_trigger_compare_regval; struct { @@ -10340,22 +5563,12 @@ typedef union sh_xn_trigger_compare_u { mmr_t reserved_0 : 32; } sh_xn_trigger_compare_s; } sh_xn_trigger_compare_u_t; -#else -typedef union sh_xn_trigger_compare_u { - mmr_t sh_xn_trigger_compare_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t mask : 32; - } sh_xn_trigger_compare_s; -} sh_xn_trigger_compare_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_TRIGGER_DATA" */ /* XN Debug Compare Data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_trigger_data_u { mmr_t sh_xn_trigger_data_regval; struct { @@ -10363,22 +5576,12 @@ typedef union sh_xn_trigger_data_u { mmr_t reserved_0 : 32; } sh_xn_trigger_data_s; } sh_xn_trigger_data_u_t; -#else -typedef union sh_xn_trigger_data_u { - mmr_t sh_xn_trigger_data_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t compare_pattern : 32; - } sh_xn_trigger_data_s; -} sh_xn_trigger_data_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_DEBUG_SEL" */ /* XN IILB Debug Port Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_iilb_debug_sel_u { mmr_t sh_xn_iilb_debug_sel_regval; struct { @@ -10416,52 +5619,12 @@ typedef union sh_xn_iilb_debug_sel_u { mmr_t reserved_15 : 1; } sh_xn_iilb_debug_sel_s; } sh_xn_iilb_debug_sel_u_t; -#else -typedef union sh_xn_iilb_debug_sel_u { - mmr_t sh_xn_iilb_debug_sel_regval; - struct { - mmr_t reserved_15 : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_input_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_input_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_input_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_input_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_input_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_input_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_input_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_input_sel : 3; - } sh_xn_iilb_debug_sel_s; -} sh_xn_iilb_debug_sel_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_DEBUG_SEL" */ /* XN PI Debug Port Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_pi_debug_sel_u { mmr_t sh_xn_pi_debug_sel_regval; struct { @@ -10499,52 +5662,12 @@ typedef union sh_xn_pi_debug_sel_u { mmr_t reserved_15 : 1; } sh_xn_pi_debug_sel_s; } sh_xn_pi_debug_sel_u_t; -#else -typedef union sh_xn_pi_debug_sel_u { - mmr_t sh_xn_pi_debug_sel_regval; - struct { - mmr_t reserved_15 : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_input_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_input_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_input_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_input_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_input_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_input_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_input_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_input_sel : 3; - } sh_xn_pi_debug_sel_s; -} sh_xn_pi_debug_sel_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_DEBUG_SEL" */ /* XN MD Debug Port Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_md_debug_sel_u { mmr_t sh_xn_md_debug_sel_regval; struct { @@ -10582,52 +5705,12 @@ typedef union sh_xn_md_debug_sel_u { mmr_t reserved_15 : 1; } sh_xn_md_debug_sel_s; } sh_xn_md_debug_sel_u_t; -#else -typedef union sh_xn_md_debug_sel_u { - mmr_t sh_xn_md_debug_sel_regval; - struct { - mmr_t reserved_15 : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_input_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_input_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_input_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_input_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_input_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_input_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_input_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_input_sel : 3; - } sh_xn_md_debug_sel_s; -} sh_xn_md_debug_sel_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_DEBUG_SEL" */ /* XN NI0 Debug Port Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_ni0_debug_sel_u { mmr_t sh_xn_ni0_debug_sel_regval; struct { @@ -10665,52 +5748,12 @@ typedef union sh_xn_ni0_debug_sel_u { mmr_t reserved_15 : 1; } sh_xn_ni0_debug_sel_s; } sh_xn_ni0_debug_sel_u_t; -#else -typedef union sh_xn_ni0_debug_sel_u { - mmr_t sh_xn_ni0_debug_sel_regval; - struct { - mmr_t reserved_15 : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_input_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_input_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_input_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_input_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_input_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_input_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_input_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_input_sel : 3; - } sh_xn_ni0_debug_sel_s; -} sh_xn_ni0_debug_sel_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_DEBUG_SEL" */ /* XN NI1 Debug Port Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_ni1_debug_sel_u { mmr_t sh_xn_ni1_debug_sel_regval; struct { @@ -10748,829 +5791,456 @@ typedef union sh_xn_ni1_debug_sel_u { mmr_t reserved_15 : 1; } sh_xn_ni1_debug_sel_s; } sh_xn_ni1_debug_sel_u_t; -#else -typedef union sh_xn_ni1_debug_sel_u { - mmr_t sh_xn_ni1_debug_sel_regval; - struct { - mmr_t reserved_15 : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_input_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_input_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_input_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_input_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_input_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_input_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_input_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_input_sel : 3; - } sh_xn_ni1_debug_sel_s; -} sh_xn_ni1_debug_sel_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_LB_CMP_EXP_DATA0" */ /* IILB compare LB input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_iilb_lb_cmp_exp_data0_u { mmr_t sh_xn_iilb_lb_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_iilb_lb_cmp_exp_data0_s; } sh_xn_iilb_lb_cmp_exp_data0_u_t; -#else -typedef union sh_xn_iilb_lb_cmp_exp_data0_u { - mmr_t sh_xn_iilb_lb_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_lb_cmp_exp_data0_s; -} sh_xn_iilb_lb_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_LB_CMP_EXP_DATA1" */ /* IILB compare LB input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_iilb_lb_cmp_exp_data1_u { mmr_t sh_xn_iilb_lb_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_iilb_lb_cmp_exp_data1_s; } sh_xn_iilb_lb_cmp_exp_data1_u_t; -#else -typedef union sh_xn_iilb_lb_cmp_exp_data1_u { - mmr_t sh_xn_iilb_lb_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_lb_cmp_exp_data1_s; -} sh_xn_iilb_lb_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_LB_CMP_ENABLE0" */ /* IILB compare LB input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_lb_cmp_enable0_u { - mmr_t sh_xn_iilb_lb_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_lb_cmp_enable0_s; -} sh_xn_iilb_lb_cmp_enable0_u_t; -#else typedef union sh_xn_iilb_lb_cmp_enable0_u { mmr_t sh_xn_iilb_lb_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_iilb_lb_cmp_enable0_s; } sh_xn_iilb_lb_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_LB_CMP_ENABLE1" */ /* IILB compare LB input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_lb_cmp_enable1_u { - mmr_t sh_xn_iilb_lb_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_lb_cmp_enable1_s; -} sh_xn_iilb_lb_cmp_enable1_u_t; -#else typedef union sh_xn_iilb_lb_cmp_enable1_u { mmr_t sh_xn_iilb_lb_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_iilb_lb_cmp_enable1_s; } sh_xn_iilb_lb_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_II_CMP_EXP_DATA0" */ /* IILB compare II input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_ii_cmp_exp_data0_u { - mmr_t sh_xn_iilb_ii_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_ii_cmp_exp_data0_s; -} sh_xn_iilb_ii_cmp_exp_data0_u_t; -#else typedef union sh_xn_iilb_ii_cmp_exp_data0_u { mmr_t sh_xn_iilb_ii_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_iilb_ii_cmp_exp_data0_s; } sh_xn_iilb_ii_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_II_CMP_EXP_DATA1" */ /* IILB compare II input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_ii_cmp_exp_data1_u { - mmr_t sh_xn_iilb_ii_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_ii_cmp_exp_data1_s; -} sh_xn_iilb_ii_cmp_exp_data1_u_t; -#else typedef union sh_xn_iilb_ii_cmp_exp_data1_u { mmr_t sh_xn_iilb_ii_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_iilb_ii_cmp_exp_data1_s; } sh_xn_iilb_ii_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_II_CMP_ENABLE0" */ /* IILB compare II input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_ii_cmp_enable0_u { - mmr_t sh_xn_iilb_ii_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_ii_cmp_enable0_s; -} sh_xn_iilb_ii_cmp_enable0_u_t; -#else typedef union sh_xn_iilb_ii_cmp_enable0_u { mmr_t sh_xn_iilb_ii_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_iilb_ii_cmp_enable0_s; } sh_xn_iilb_ii_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_II_CMP_ENABLE1" */ /* IILB compare II input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_ii_cmp_enable1_u { - mmr_t sh_xn_iilb_ii_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_ii_cmp_enable1_s; -} sh_xn_iilb_ii_cmp_enable1_u_t; -#else typedef union sh_xn_iilb_ii_cmp_enable1_u { mmr_t sh_xn_iilb_ii_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_iilb_ii_cmp_enable1_s; } sh_xn_iilb_ii_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_MD_CMP_EXP_DATA0" */ /* IILB compare MD input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_md_cmp_exp_data0_u { - mmr_t sh_xn_iilb_md_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_md_cmp_exp_data0_s; -} sh_xn_iilb_md_cmp_exp_data0_u_t; -#else typedef union sh_xn_iilb_md_cmp_exp_data0_u { mmr_t sh_xn_iilb_md_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_iilb_md_cmp_exp_data0_s; } sh_xn_iilb_md_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_MD_CMP_EXP_DATA1" */ /* IILB compare MD input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_md_cmp_exp_data1_u { - mmr_t sh_xn_iilb_md_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_md_cmp_exp_data1_s; -} sh_xn_iilb_md_cmp_exp_data1_u_t; -#else typedef union sh_xn_iilb_md_cmp_exp_data1_u { mmr_t sh_xn_iilb_md_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_iilb_md_cmp_exp_data1_s; } sh_xn_iilb_md_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_MD_CMP_ENABLE0" */ /* IILB compare MD input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_md_cmp_enable0_u { - mmr_t sh_xn_iilb_md_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_md_cmp_enable0_s; -} sh_xn_iilb_md_cmp_enable0_u_t; -#else typedef union sh_xn_iilb_md_cmp_enable0_u { mmr_t sh_xn_iilb_md_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_iilb_md_cmp_enable0_s; } sh_xn_iilb_md_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_MD_CMP_ENABLE1" */ /* IILB compare MD input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_md_cmp_enable1_u { - mmr_t sh_xn_iilb_md_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_md_cmp_enable1_s; -} sh_xn_iilb_md_cmp_enable1_u_t; -#else typedef union sh_xn_iilb_md_cmp_enable1_u { mmr_t sh_xn_iilb_md_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_iilb_md_cmp_enable1_s; } sh_xn_iilb_md_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_PI_CMP_EXP_DATA0" */ /* IILB compare PI input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_pi_cmp_exp_data0_u { - mmr_t sh_xn_iilb_pi_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_pi_cmp_exp_data0_s; -} sh_xn_iilb_pi_cmp_exp_data0_u_t; -#else typedef union sh_xn_iilb_pi_cmp_exp_data0_u { mmr_t sh_xn_iilb_pi_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_iilb_pi_cmp_exp_data0_s; } sh_xn_iilb_pi_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_PI_CMP_EXP_DATA1" */ /* IILB compare PI input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_pi_cmp_exp_data1_u { - mmr_t sh_xn_iilb_pi_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_pi_cmp_exp_data1_s; -} sh_xn_iilb_pi_cmp_exp_data1_u_t; -#else typedef union sh_xn_iilb_pi_cmp_exp_data1_u { mmr_t sh_xn_iilb_pi_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_iilb_pi_cmp_exp_data1_s; } sh_xn_iilb_pi_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_PI_CMP_ENABLE0" */ /* IILB compare PI input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_iilb_pi_cmp_enable0_u { mmr_t sh_xn_iilb_pi_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_iilb_pi_cmp_enable0_s; } sh_xn_iilb_pi_cmp_enable0_u_t; -#else -typedef union sh_xn_iilb_pi_cmp_enable0_u { - mmr_t sh_xn_iilb_pi_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_pi_cmp_enable0_s; -} sh_xn_iilb_pi_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_PI_CMP_ENABLE1" */ /* IILB compare PI input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_pi_cmp_enable1_u { - mmr_t sh_xn_iilb_pi_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_pi_cmp_enable1_s; -} sh_xn_iilb_pi_cmp_enable1_u_t; -#else typedef union sh_xn_iilb_pi_cmp_enable1_u { mmr_t sh_xn_iilb_pi_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_iilb_pi_cmp_enable1_s; } sh_xn_iilb_pi_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_NI0_CMP_EXP_DATA0" */ /* IILB compare NI0 input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_ni0_cmp_exp_data0_u { - mmr_t sh_xn_iilb_ni0_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_ni0_cmp_exp_data0_s; -} sh_xn_iilb_ni0_cmp_exp_data0_u_t; -#else typedef union sh_xn_iilb_ni0_cmp_exp_data0_u { mmr_t sh_xn_iilb_ni0_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_iilb_ni0_cmp_exp_data0_s; } sh_xn_iilb_ni0_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_NI0_CMP_EXP_DATA1" */ /* IILB compare NI0 input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_ni0_cmp_exp_data1_u { - mmr_t sh_xn_iilb_ni0_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_ni0_cmp_exp_data1_s; -} sh_xn_iilb_ni0_cmp_exp_data1_u_t; -#else typedef union sh_xn_iilb_ni0_cmp_exp_data1_u { mmr_t sh_xn_iilb_ni0_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_iilb_ni0_cmp_exp_data1_s; } sh_xn_iilb_ni0_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_NI0_CMP_ENABLE0" */ /* IILB compare NI0 input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_ni0_cmp_enable0_u { - mmr_t sh_xn_iilb_ni0_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_ni0_cmp_enable0_s; -} sh_xn_iilb_ni0_cmp_enable0_u_t; -#else typedef union sh_xn_iilb_ni0_cmp_enable0_u { mmr_t sh_xn_iilb_ni0_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_iilb_ni0_cmp_enable0_s; } sh_xn_iilb_ni0_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_NI0_CMP_ENABLE1" */ /* IILB compare NI0 input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_ni0_cmp_enable1_u { - mmr_t sh_xn_iilb_ni0_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_ni0_cmp_enable1_s; -} sh_xn_iilb_ni0_cmp_enable1_u_t; -#else typedef union sh_xn_iilb_ni0_cmp_enable1_u { mmr_t sh_xn_iilb_ni0_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_iilb_ni0_cmp_enable1_s; } sh_xn_iilb_ni0_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_NI1_CMP_EXP_DATA0" */ /* IILB compare NI1 input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_ni1_cmp_exp_data0_u { - mmr_t sh_xn_iilb_ni1_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_ni1_cmp_exp_data0_s; -} sh_xn_iilb_ni1_cmp_exp_data0_u_t; -#else typedef union sh_xn_iilb_ni1_cmp_exp_data0_u { mmr_t sh_xn_iilb_ni1_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_iilb_ni1_cmp_exp_data0_s; } sh_xn_iilb_ni1_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_NI1_CMP_EXP_DATA1" */ /* IILB compare NI1 input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_iilb_ni1_cmp_exp_data1_u { mmr_t sh_xn_iilb_ni1_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_iilb_ni1_cmp_exp_data1_s; } sh_xn_iilb_ni1_cmp_exp_data1_u_t; -#else -typedef union sh_xn_iilb_ni1_cmp_exp_data1_u { - mmr_t sh_xn_iilb_ni1_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_ni1_cmp_exp_data1_s; -} sh_xn_iilb_ni1_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_NI1_CMP_ENABLE0" */ /* IILB compare NI1 input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_ni1_cmp_enable0_u { - mmr_t sh_xn_iilb_ni1_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_ni1_cmp_enable0_s; -} sh_xn_iilb_ni1_cmp_enable0_u_t; -#else typedef union sh_xn_iilb_ni1_cmp_enable0_u { mmr_t sh_xn_iilb_ni1_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_iilb_ni1_cmp_enable0_s; } sh_xn_iilb_ni1_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_NI1_CMP_ENABLE1" */ /* IILB compare NI1 input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_ni1_cmp_enable1_u { - mmr_t sh_xn_iilb_ni1_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_ni1_cmp_enable1_s; -} sh_xn_iilb_ni1_cmp_enable1_u_t; -#else typedef union sh_xn_iilb_ni1_cmp_enable1_u { mmr_t sh_xn_iilb_ni1_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_iilb_ni1_cmp_enable1_s; } sh_xn_iilb_ni1_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_IILB_CMP_EXP_DATA0" */ /* MD compare IILB input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_md_iilb_cmp_exp_data0_u { mmr_t sh_xn_md_iilb_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_md_iilb_cmp_exp_data0_s; } sh_xn_md_iilb_cmp_exp_data0_u_t; -#else -typedef union sh_xn_md_iilb_cmp_exp_data0_u { - mmr_t sh_xn_md_iilb_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_md_iilb_cmp_exp_data0_s; -} sh_xn_md_iilb_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_IILB_CMP_EXP_DATA1" */ /* MD compare IILB input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_md_iilb_cmp_exp_data1_u { - mmr_t sh_xn_md_iilb_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_md_iilb_cmp_exp_data1_s; -} sh_xn_md_iilb_cmp_exp_data1_u_t; -#else typedef union sh_xn_md_iilb_cmp_exp_data1_u { mmr_t sh_xn_md_iilb_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_md_iilb_cmp_exp_data1_s; } sh_xn_md_iilb_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_IILB_CMP_ENABLE0" */ /* MD compare IILB input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_md_iilb_cmp_enable0_u { mmr_t sh_xn_md_iilb_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_md_iilb_cmp_enable0_s; } sh_xn_md_iilb_cmp_enable0_u_t; -#else -typedef union sh_xn_md_iilb_cmp_enable0_u { - mmr_t sh_xn_md_iilb_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_md_iilb_cmp_enable0_s; -} sh_xn_md_iilb_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_IILB_CMP_ENABLE1" */ /* MD compare IILB input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_md_iilb_cmp_enable1_u { - mmr_t sh_xn_md_iilb_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_md_iilb_cmp_enable1_s; -} sh_xn_md_iilb_cmp_enable1_u_t; -#else typedef union sh_xn_md_iilb_cmp_enable1_u { mmr_t sh_xn_md_iilb_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_md_iilb_cmp_enable1_s; } sh_xn_md_iilb_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_NI0_CMP_EXP_DATA0" */ /* MD compare NI0 input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_md_ni0_cmp_exp_data0_u { mmr_t sh_xn_md_ni0_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_md_ni0_cmp_exp_data0_s; } sh_xn_md_ni0_cmp_exp_data0_u_t; -#else -typedef union sh_xn_md_ni0_cmp_exp_data0_u { - mmr_t sh_xn_md_ni0_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_md_ni0_cmp_exp_data0_s; -} sh_xn_md_ni0_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_NI0_CMP_EXP_DATA1" */ /* MD compare NI0 input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_md_ni0_cmp_exp_data1_u { - mmr_t sh_xn_md_ni0_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_md_ni0_cmp_exp_data1_s; -} sh_xn_md_ni0_cmp_exp_data1_u_t; -#else typedef union sh_xn_md_ni0_cmp_exp_data1_u { mmr_t sh_xn_md_ni0_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_md_ni0_cmp_exp_data1_s; } sh_xn_md_ni0_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_NI0_CMP_ENABLE0" */ /* MD compare NI0 input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_md_ni0_cmp_enable0_u { - mmr_t sh_xn_md_ni0_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_md_ni0_cmp_enable0_s; -} sh_xn_md_ni0_cmp_enable0_u_t; -#else typedef union sh_xn_md_ni0_cmp_enable0_u { mmr_t sh_xn_md_ni0_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_md_ni0_cmp_enable0_s; } sh_xn_md_ni0_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_NI0_CMP_ENABLE1" */ /* MD compare NI0 input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_md_ni0_cmp_enable1_u { - mmr_t sh_xn_md_ni0_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_md_ni0_cmp_enable1_s; -} sh_xn_md_ni0_cmp_enable1_u_t; -#else typedef union sh_xn_md_ni0_cmp_enable1_u { mmr_t sh_xn_md_ni0_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_md_ni0_cmp_enable1_s; } sh_xn_md_ni0_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_NI1_CMP_EXP_DATA0" */ /* MD compare NI1 input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_md_ni1_cmp_exp_data0_u { - mmr_t sh_xn_md_ni1_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_md_ni1_cmp_exp_data0_s; -} sh_xn_md_ni1_cmp_exp_data0_u_t; -#else typedef union sh_xn_md_ni1_cmp_exp_data0_u { mmr_t sh_xn_md_ni1_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_md_ni1_cmp_exp_data0_s; } sh_xn_md_ni1_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_NI1_CMP_EXP_DATA1" */ /* MD compare NI1 input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_md_ni1_cmp_exp_data1_u { mmr_t sh_xn_md_ni1_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_md_ni1_cmp_exp_data1_s; } sh_xn_md_ni1_cmp_exp_data1_u_t; -#else -typedef union sh_xn_md_ni1_cmp_exp_data1_u { - mmr_t sh_xn_md_ni1_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_md_ni1_cmp_exp_data1_s; -} sh_xn_md_ni1_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_NI1_CMP_ENABLE0" */ /* MD compare NI1 input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_md_ni1_cmp_enable0_u { - mmr_t sh_xn_md_ni1_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_md_ni1_cmp_enable0_s; -} sh_xn_md_ni1_cmp_enable0_u_t; -#else typedef union sh_xn_md_ni1_cmp_enable0_u { mmr_t sh_xn_md_ni1_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_md_ni1_cmp_enable0_s; } sh_xn_md_ni1_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_NI1_CMP_ENABLE1" */ /* MD compare NI1 input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_md_ni1_cmp_enable1_u { - mmr_t sh_xn_md_ni1_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_md_ni1_cmp_enable1_s; -} sh_xn_md_ni1_cmp_enable1_u_t; -#else typedef union sh_xn_md_ni1_cmp_enable1_u { mmr_t sh_xn_md_ni1_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_md_ni1_cmp_enable1_s; } sh_xn_md_ni1_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_SIC_CMP_EXP_HDR0" */ /* MD compare SIC input expected header0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_md_sic_cmp_exp_hdr0_u { - mmr_t sh_xn_md_sic_cmp_exp_hdr0_regval; - struct { - mmr_t data : 64; - } sh_xn_md_sic_cmp_exp_hdr0_s; -} sh_xn_md_sic_cmp_exp_hdr0_u_t; -#else typedef union sh_xn_md_sic_cmp_exp_hdr0_u { mmr_t sh_xn_md_sic_cmp_exp_hdr0_regval; struct { mmr_t data : 64; } sh_xn_md_sic_cmp_exp_hdr0_s; } sh_xn_md_sic_cmp_exp_hdr0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_SIC_CMP_EXP_HDR1" */ /* MD compare SIC input expected header1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_md_sic_cmp_exp_hdr1_u { mmr_t sh_xn_md_sic_cmp_exp_hdr1_regval; struct { @@ -11578,43 +6248,24 @@ typedef union sh_xn_md_sic_cmp_exp_hdr1_u { mmr_t reserved_0 : 22; } sh_xn_md_sic_cmp_exp_hdr1_s; } sh_xn_md_sic_cmp_exp_hdr1_u_t; -#else -typedef union sh_xn_md_sic_cmp_exp_hdr1_u { - mmr_t sh_xn_md_sic_cmp_exp_hdr1_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t data : 42; - } sh_xn_md_sic_cmp_exp_hdr1_s; -} sh_xn_md_sic_cmp_exp_hdr1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_SIC_CMP_HDR_ENABLE0" */ /* MD compare SIC header enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_md_sic_cmp_hdr_enable0_u { - mmr_t sh_xn_md_sic_cmp_hdr_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_md_sic_cmp_hdr_enable0_s; -} sh_xn_md_sic_cmp_hdr_enable0_u_t; -#else typedef union sh_xn_md_sic_cmp_hdr_enable0_u { mmr_t sh_xn_md_sic_cmp_hdr_enable0_regval; struct { mmr_t enable : 64; } sh_xn_md_sic_cmp_hdr_enable0_s; } sh_xn_md_sic_cmp_hdr_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_SIC_CMP_HDR_ENABLE1" */ /* MD compare SIC header enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_md_sic_cmp_hdr_enable1_u { mmr_t sh_xn_md_sic_cmp_hdr_enable1_regval; struct { @@ -11622,463 +6273,264 @@ typedef union sh_xn_md_sic_cmp_hdr_enable1_u { mmr_t reserved_0 : 22; } sh_xn_md_sic_cmp_hdr_enable1_s; } sh_xn_md_sic_cmp_hdr_enable1_u_t; -#else -typedef union sh_xn_md_sic_cmp_hdr_enable1_u { - mmr_t sh_xn_md_sic_cmp_hdr_enable1_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t enable : 42; - } sh_xn_md_sic_cmp_hdr_enable1_s; -} sh_xn_md_sic_cmp_hdr_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_SIC_CMP_DATA0" */ /* MD compare SIC data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_md_sic_cmp_data0_u { - mmr_t sh_xn_md_sic_cmp_data0_regval; - struct { - mmr_t data0 : 64; - } sh_xn_md_sic_cmp_data0_s; -} sh_xn_md_sic_cmp_data0_u_t; -#else typedef union sh_xn_md_sic_cmp_data0_u { mmr_t sh_xn_md_sic_cmp_data0_regval; struct { mmr_t data0 : 64; } sh_xn_md_sic_cmp_data0_s; } sh_xn_md_sic_cmp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_SIC_CMP_DATA1" */ /* MD compare SIC data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_md_sic_cmp_data1_u { mmr_t sh_xn_md_sic_cmp_data1_regval; struct { mmr_t data1 : 64; } sh_xn_md_sic_cmp_data1_s; } sh_xn_md_sic_cmp_data1_u_t; -#else -typedef union sh_xn_md_sic_cmp_data1_u { - mmr_t sh_xn_md_sic_cmp_data1_regval; - struct { - mmr_t data1 : 64; - } sh_xn_md_sic_cmp_data1_s; -} sh_xn_md_sic_cmp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_SIC_CMP_DATA2" */ /* MD compare SIC data2 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_md_sic_cmp_data2_u { - mmr_t sh_xn_md_sic_cmp_data2_regval; - struct { - mmr_t data2 : 64; - } sh_xn_md_sic_cmp_data2_s; -} sh_xn_md_sic_cmp_data2_u_t; -#else typedef union sh_xn_md_sic_cmp_data2_u { mmr_t sh_xn_md_sic_cmp_data2_regval; struct { mmr_t data2 : 64; } sh_xn_md_sic_cmp_data2_s; } sh_xn_md_sic_cmp_data2_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_SIC_CMP_DATA3" */ /* MD compare SIC data3 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_md_sic_cmp_data3_u { - mmr_t sh_xn_md_sic_cmp_data3_regval; - struct { - mmr_t data3 : 64; - } sh_xn_md_sic_cmp_data3_s; -} sh_xn_md_sic_cmp_data3_u_t; -#else typedef union sh_xn_md_sic_cmp_data3_u { mmr_t sh_xn_md_sic_cmp_data3_regval; struct { mmr_t data3 : 64; } sh_xn_md_sic_cmp_data3_s; } sh_xn_md_sic_cmp_data3_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE0" */ /* MD enable compare SIC data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_md_sic_cmp_data_enable0_u { - mmr_t sh_xn_md_sic_cmp_data_enable0_regval; - struct { - mmr_t data_enable0 : 64; - } sh_xn_md_sic_cmp_data_enable0_s; -} sh_xn_md_sic_cmp_data_enable0_u_t; -#else typedef union sh_xn_md_sic_cmp_data_enable0_u { mmr_t sh_xn_md_sic_cmp_data_enable0_regval; struct { mmr_t data_enable0 : 64; } sh_xn_md_sic_cmp_data_enable0_s; } sh_xn_md_sic_cmp_data_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE1" */ /* MD enable compare SIC data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_md_sic_cmp_data_enable1_u { - mmr_t sh_xn_md_sic_cmp_data_enable1_regval; - struct { - mmr_t data_enable1 : 64; - } sh_xn_md_sic_cmp_data_enable1_s; -} sh_xn_md_sic_cmp_data_enable1_u_t; -#else typedef union sh_xn_md_sic_cmp_data_enable1_u { mmr_t sh_xn_md_sic_cmp_data_enable1_regval; struct { mmr_t data_enable1 : 64; } sh_xn_md_sic_cmp_data_enable1_s; } sh_xn_md_sic_cmp_data_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE2" */ /* MD enable compare SIC data2 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_md_sic_cmp_data_enable2_u { mmr_t sh_xn_md_sic_cmp_data_enable2_regval; struct { mmr_t data_enable2 : 64; } sh_xn_md_sic_cmp_data_enable2_s; } sh_xn_md_sic_cmp_data_enable2_u_t; -#else -typedef union sh_xn_md_sic_cmp_data_enable2_u { - mmr_t sh_xn_md_sic_cmp_data_enable2_regval; - struct { - mmr_t data_enable2 : 64; - } sh_xn_md_sic_cmp_data_enable2_s; -} sh_xn_md_sic_cmp_data_enable2_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE3" */ /* MD enable compare SIC data3 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_md_sic_cmp_data_enable3_u { mmr_t sh_xn_md_sic_cmp_data_enable3_regval; struct { mmr_t data_enable3 : 64; } sh_xn_md_sic_cmp_data_enable3_s; } sh_xn_md_sic_cmp_data_enable3_u_t; -#else -typedef union sh_xn_md_sic_cmp_data_enable3_u { - mmr_t sh_xn_md_sic_cmp_data_enable3_regval; - struct { - mmr_t data_enable3 : 64; - } sh_xn_md_sic_cmp_data_enable3_s; -} sh_xn_md_sic_cmp_data_enable3_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_IILB_CMP_EXP_DATA0" */ /* PI compare IILB input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_iilb_cmp_exp_data0_u { - mmr_t sh_xn_pi_iilb_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_pi_iilb_cmp_exp_data0_s; -} sh_xn_pi_iilb_cmp_exp_data0_u_t; -#else typedef union sh_xn_pi_iilb_cmp_exp_data0_u { mmr_t sh_xn_pi_iilb_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_pi_iilb_cmp_exp_data0_s; } sh_xn_pi_iilb_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_IILB_CMP_EXP_DATA1" */ /* PI compare IILB input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_iilb_cmp_exp_data1_u { - mmr_t sh_xn_pi_iilb_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_pi_iilb_cmp_exp_data1_s; -} sh_xn_pi_iilb_cmp_exp_data1_u_t; -#else typedef union sh_xn_pi_iilb_cmp_exp_data1_u { mmr_t sh_xn_pi_iilb_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_pi_iilb_cmp_exp_data1_s; } sh_xn_pi_iilb_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_IILB_CMP_ENABLE0" */ /* PI compare IILB input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_iilb_cmp_enable0_u { - mmr_t sh_xn_pi_iilb_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_pi_iilb_cmp_enable0_s; -} sh_xn_pi_iilb_cmp_enable0_u_t; -#else typedef union sh_xn_pi_iilb_cmp_enable0_u { mmr_t sh_xn_pi_iilb_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_pi_iilb_cmp_enable0_s; } sh_xn_pi_iilb_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_IILB_CMP_ENABLE1" */ /* PI compare IILB input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_pi_iilb_cmp_enable1_u { mmr_t sh_xn_pi_iilb_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_pi_iilb_cmp_enable1_s; } sh_xn_pi_iilb_cmp_enable1_u_t; -#else -typedef union sh_xn_pi_iilb_cmp_enable1_u { - mmr_t sh_xn_pi_iilb_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_pi_iilb_cmp_enable1_s; -} sh_xn_pi_iilb_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_NI0_CMP_EXP_DATA0" */ /* PI compare NI0 input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_pi_ni0_cmp_exp_data0_u { mmr_t sh_xn_pi_ni0_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_pi_ni0_cmp_exp_data0_s; } sh_xn_pi_ni0_cmp_exp_data0_u_t; -#else -typedef union sh_xn_pi_ni0_cmp_exp_data0_u { - mmr_t sh_xn_pi_ni0_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_pi_ni0_cmp_exp_data0_s; -} sh_xn_pi_ni0_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_NI0_CMP_EXP_DATA1" */ /* PI compare NI0 input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_pi_ni0_cmp_exp_data1_u { mmr_t sh_xn_pi_ni0_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_pi_ni0_cmp_exp_data1_s; } sh_xn_pi_ni0_cmp_exp_data1_u_t; -#else -typedef union sh_xn_pi_ni0_cmp_exp_data1_u { - mmr_t sh_xn_pi_ni0_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_pi_ni0_cmp_exp_data1_s; -} sh_xn_pi_ni0_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_NI0_CMP_ENABLE0" */ /* PI compare NI0 input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_pi_ni0_cmp_enable0_u { mmr_t sh_xn_pi_ni0_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_pi_ni0_cmp_enable0_s; } sh_xn_pi_ni0_cmp_enable0_u_t; -#else -typedef union sh_xn_pi_ni0_cmp_enable0_u { - mmr_t sh_xn_pi_ni0_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_pi_ni0_cmp_enable0_s; -} sh_xn_pi_ni0_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_NI0_CMP_ENABLE1" */ /* PI compare NI0 input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_ni0_cmp_enable1_u { - mmr_t sh_xn_pi_ni0_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_pi_ni0_cmp_enable1_s; -} sh_xn_pi_ni0_cmp_enable1_u_t; -#else typedef union sh_xn_pi_ni0_cmp_enable1_u { mmr_t sh_xn_pi_ni0_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_pi_ni0_cmp_enable1_s; } sh_xn_pi_ni0_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_NI1_CMP_EXP_DATA0" */ /* PI compare NI1 input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_ni1_cmp_exp_data0_u { - mmr_t sh_xn_pi_ni1_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_pi_ni1_cmp_exp_data0_s; -} sh_xn_pi_ni1_cmp_exp_data0_u_t; -#else typedef union sh_xn_pi_ni1_cmp_exp_data0_u { mmr_t sh_xn_pi_ni1_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_pi_ni1_cmp_exp_data0_s; } sh_xn_pi_ni1_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_NI1_CMP_EXP_DATA1" */ /* PI compare NI1 input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_ni1_cmp_exp_data1_u { - mmr_t sh_xn_pi_ni1_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_pi_ni1_cmp_exp_data1_s; -} sh_xn_pi_ni1_cmp_exp_data1_u_t; -#else typedef union sh_xn_pi_ni1_cmp_exp_data1_u { mmr_t sh_xn_pi_ni1_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_pi_ni1_cmp_exp_data1_s; } sh_xn_pi_ni1_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_NI1_CMP_ENABLE0" */ /* PI compare NI1 input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_ni1_cmp_enable0_u { - mmr_t sh_xn_pi_ni1_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_pi_ni1_cmp_enable0_s; -} sh_xn_pi_ni1_cmp_enable0_u_t; -#else typedef union sh_xn_pi_ni1_cmp_enable0_u { mmr_t sh_xn_pi_ni1_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_pi_ni1_cmp_enable0_s; } sh_xn_pi_ni1_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_NI1_CMP_ENABLE1" */ /* PI compare NI1 input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_ni1_cmp_enable1_u { - mmr_t sh_xn_pi_ni1_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_pi_ni1_cmp_enable1_s; -} sh_xn_pi_ni1_cmp_enable1_u_t; -#else typedef union sh_xn_pi_ni1_cmp_enable1_u { mmr_t sh_xn_pi_ni1_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_pi_ni1_cmp_enable1_s; } sh_xn_pi_ni1_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_SIC_CMP_EXP_HDR0" */ /* PI compare SIC input expected header0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_sic_cmp_exp_hdr0_u { - mmr_t sh_xn_pi_sic_cmp_exp_hdr0_regval; - struct { - mmr_t data : 64; - } sh_xn_pi_sic_cmp_exp_hdr0_s; -} sh_xn_pi_sic_cmp_exp_hdr0_u_t; -#else typedef union sh_xn_pi_sic_cmp_exp_hdr0_u { mmr_t sh_xn_pi_sic_cmp_exp_hdr0_regval; struct { mmr_t data : 64; } sh_xn_pi_sic_cmp_exp_hdr0_s; } sh_xn_pi_sic_cmp_exp_hdr0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_SIC_CMP_EXP_HDR1" */ /* PI compare SIC input expected header1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_pi_sic_cmp_exp_hdr1_u { mmr_t sh_xn_pi_sic_cmp_exp_hdr1_regval; struct { @@ -12086,43 +6538,24 @@ typedef union sh_xn_pi_sic_cmp_exp_hdr1_u { mmr_t reserved_0 : 22; } sh_xn_pi_sic_cmp_exp_hdr1_s; } sh_xn_pi_sic_cmp_exp_hdr1_u_t; -#else -typedef union sh_xn_pi_sic_cmp_exp_hdr1_u { - mmr_t sh_xn_pi_sic_cmp_exp_hdr1_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t data : 42; - } sh_xn_pi_sic_cmp_exp_hdr1_s; -} sh_xn_pi_sic_cmp_exp_hdr1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_SIC_CMP_HDR_ENABLE0" */ /* PI compare SIC header enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_sic_cmp_hdr_enable0_u { - mmr_t sh_xn_pi_sic_cmp_hdr_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_pi_sic_cmp_hdr_enable0_s; -} sh_xn_pi_sic_cmp_hdr_enable0_u_t; -#else typedef union sh_xn_pi_sic_cmp_hdr_enable0_u { mmr_t sh_xn_pi_sic_cmp_hdr_enable0_regval; struct { mmr_t enable : 64; } sh_xn_pi_sic_cmp_hdr_enable0_s; } sh_xn_pi_sic_cmp_hdr_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_SIC_CMP_HDR_ENABLE1" */ /* PI compare SIC header enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_pi_sic_cmp_hdr_enable1_u { mmr_t sh_xn_pi_sic_cmp_hdr_enable1_regval; struct { @@ -12130,1029 +6563,587 @@ typedef union sh_xn_pi_sic_cmp_hdr_enable1_u { mmr_t reserved_0 : 22; } sh_xn_pi_sic_cmp_hdr_enable1_s; } sh_xn_pi_sic_cmp_hdr_enable1_u_t; -#else -typedef union sh_xn_pi_sic_cmp_hdr_enable1_u { - mmr_t sh_xn_pi_sic_cmp_hdr_enable1_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t enable : 42; - } sh_xn_pi_sic_cmp_hdr_enable1_s; -} sh_xn_pi_sic_cmp_hdr_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_SIC_CMP_DATA0" */ /* PI compare SIC data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_sic_cmp_data0_u { - mmr_t sh_xn_pi_sic_cmp_data0_regval; - struct { - mmr_t data0 : 64; - } sh_xn_pi_sic_cmp_data0_s; -} sh_xn_pi_sic_cmp_data0_u_t; -#else typedef union sh_xn_pi_sic_cmp_data0_u { mmr_t sh_xn_pi_sic_cmp_data0_regval; struct { mmr_t data0 : 64; } sh_xn_pi_sic_cmp_data0_s; } sh_xn_pi_sic_cmp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_SIC_CMP_DATA1" */ /* PI compare SIC data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_sic_cmp_data1_u { - mmr_t sh_xn_pi_sic_cmp_data1_regval; - struct { - mmr_t data1 : 64; - } sh_xn_pi_sic_cmp_data1_s; -} sh_xn_pi_sic_cmp_data1_u_t; -#else typedef union sh_xn_pi_sic_cmp_data1_u { mmr_t sh_xn_pi_sic_cmp_data1_regval; struct { mmr_t data1 : 64; } sh_xn_pi_sic_cmp_data1_s; } sh_xn_pi_sic_cmp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_SIC_CMP_DATA2" */ /* PI compare SIC data2 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_sic_cmp_data2_u { - mmr_t sh_xn_pi_sic_cmp_data2_regval; - struct { - mmr_t data2 : 64; - } sh_xn_pi_sic_cmp_data2_s; -} sh_xn_pi_sic_cmp_data2_u_t; -#else typedef union sh_xn_pi_sic_cmp_data2_u { mmr_t sh_xn_pi_sic_cmp_data2_regval; struct { mmr_t data2 : 64; } sh_xn_pi_sic_cmp_data2_s; } sh_xn_pi_sic_cmp_data2_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_SIC_CMP_DATA3" */ /* PI compare SIC data3 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_pi_sic_cmp_data3_u { mmr_t sh_xn_pi_sic_cmp_data3_regval; struct { mmr_t data3 : 64; } sh_xn_pi_sic_cmp_data3_s; } sh_xn_pi_sic_cmp_data3_u_t; -#else -typedef union sh_xn_pi_sic_cmp_data3_u { - mmr_t sh_xn_pi_sic_cmp_data3_regval; - struct { - mmr_t data3 : 64; - } sh_xn_pi_sic_cmp_data3_s; -} sh_xn_pi_sic_cmp_data3_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE0" */ /* PI enable compare SIC data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_sic_cmp_data_enable0_u { - mmr_t sh_xn_pi_sic_cmp_data_enable0_regval; - struct { - mmr_t data_enable0 : 64; - } sh_xn_pi_sic_cmp_data_enable0_s; -} sh_xn_pi_sic_cmp_data_enable0_u_t; -#else typedef union sh_xn_pi_sic_cmp_data_enable0_u { mmr_t sh_xn_pi_sic_cmp_data_enable0_regval; struct { mmr_t data_enable0 : 64; } sh_xn_pi_sic_cmp_data_enable0_s; } sh_xn_pi_sic_cmp_data_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE1" */ /* PI enable compare SIC data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_sic_cmp_data_enable1_u { - mmr_t sh_xn_pi_sic_cmp_data_enable1_regval; - struct { - mmr_t data_enable1 : 64; - } sh_xn_pi_sic_cmp_data_enable1_s; -} sh_xn_pi_sic_cmp_data_enable1_u_t; -#else typedef union sh_xn_pi_sic_cmp_data_enable1_u { mmr_t sh_xn_pi_sic_cmp_data_enable1_regval; struct { mmr_t data_enable1 : 64; } sh_xn_pi_sic_cmp_data_enable1_s; } sh_xn_pi_sic_cmp_data_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE2" */ /* PI enable compare SIC data2 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_sic_cmp_data_enable2_u { - mmr_t sh_xn_pi_sic_cmp_data_enable2_regval; - struct { - mmr_t data_enable2 : 64; - } sh_xn_pi_sic_cmp_data_enable2_s; -} sh_xn_pi_sic_cmp_data_enable2_u_t; -#else typedef union sh_xn_pi_sic_cmp_data_enable2_u { mmr_t sh_xn_pi_sic_cmp_data_enable2_regval; struct { mmr_t data_enable2 : 64; } sh_xn_pi_sic_cmp_data_enable2_s; } sh_xn_pi_sic_cmp_data_enable2_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE3" */ /* PI enable compare SIC data3 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_sic_cmp_data_enable3_u { - mmr_t sh_xn_pi_sic_cmp_data_enable3_regval; - struct { - mmr_t data_enable3 : 64; - } sh_xn_pi_sic_cmp_data_enable3_s; -} sh_xn_pi_sic_cmp_data_enable3_u_t; -#else typedef union sh_xn_pi_sic_cmp_data_enable3_u { mmr_t sh_xn_pi_sic_cmp_data_enable3_regval; struct { mmr_t data_enable3 : 64; } sh_xn_pi_sic_cmp_data_enable3_s; } sh_xn_pi_sic_cmp_data_enable3_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_IILB_CMP_EXP_DATA0" */ /* NI0 compare IILB input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni0_iilb_cmp_exp_data0_u { - mmr_t sh_xn_ni0_iilb_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_ni0_iilb_cmp_exp_data0_s; -} sh_xn_ni0_iilb_cmp_exp_data0_u_t; -#else typedef union sh_xn_ni0_iilb_cmp_exp_data0_u { mmr_t sh_xn_ni0_iilb_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_ni0_iilb_cmp_exp_data0_s; } sh_xn_ni0_iilb_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_IILB_CMP_EXP_DATA1" */ /* NI0 compare IILB input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_ni0_iilb_cmp_exp_data1_u { mmr_t sh_xn_ni0_iilb_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_ni0_iilb_cmp_exp_data1_s; } sh_xn_ni0_iilb_cmp_exp_data1_u_t; -#else -typedef union sh_xn_ni0_iilb_cmp_exp_data1_u { - mmr_t sh_xn_ni0_iilb_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_ni0_iilb_cmp_exp_data1_s; -} sh_xn_ni0_iilb_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_IILB_CMP_ENABLE0" */ /* NI0 compare IILB input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni0_iilb_cmp_enable0_u { - mmr_t sh_xn_ni0_iilb_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni0_iilb_cmp_enable0_s; -} sh_xn_ni0_iilb_cmp_enable0_u_t; -#else typedef union sh_xn_ni0_iilb_cmp_enable0_u { mmr_t sh_xn_ni0_iilb_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_ni0_iilb_cmp_enable0_s; } sh_xn_ni0_iilb_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_IILB_CMP_ENABLE1" */ /* NI0 compare IILB input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni0_iilb_cmp_enable1_u { - mmr_t sh_xn_ni0_iilb_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni0_iilb_cmp_enable1_s; -} sh_xn_ni0_iilb_cmp_enable1_u_t; -#else typedef union sh_xn_ni0_iilb_cmp_enable1_u { mmr_t sh_xn_ni0_iilb_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_ni0_iilb_cmp_enable1_s; } sh_xn_ni0_iilb_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_PI_CMP_EXP_DATA0" */ /* NI0 compare PI input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni0_pi_cmp_exp_data0_u { - mmr_t sh_xn_ni0_pi_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_ni0_pi_cmp_exp_data0_s; -} sh_xn_ni0_pi_cmp_exp_data0_u_t; -#else typedef union sh_xn_ni0_pi_cmp_exp_data0_u { mmr_t sh_xn_ni0_pi_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_ni0_pi_cmp_exp_data0_s; } sh_xn_ni0_pi_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_PI_CMP_EXP_DATA1" */ /* NI0 compare PI input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_ni0_pi_cmp_exp_data1_u { mmr_t sh_xn_ni0_pi_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_ni0_pi_cmp_exp_data1_s; } sh_xn_ni0_pi_cmp_exp_data1_u_t; -#else -typedef union sh_xn_ni0_pi_cmp_exp_data1_u { - mmr_t sh_xn_ni0_pi_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_ni0_pi_cmp_exp_data1_s; -} sh_xn_ni0_pi_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_PI_CMP_ENABLE0" */ /* NI0 compare PI input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_ni0_pi_cmp_enable0_u { mmr_t sh_xn_ni0_pi_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_ni0_pi_cmp_enable0_s; } sh_xn_ni0_pi_cmp_enable0_u_t; -#else -typedef union sh_xn_ni0_pi_cmp_enable0_u { - mmr_t sh_xn_ni0_pi_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni0_pi_cmp_enable0_s; -} sh_xn_ni0_pi_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_PI_CMP_ENABLE1" */ /* NI0 compare PI input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_ni0_pi_cmp_enable1_u { mmr_t sh_xn_ni0_pi_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_ni0_pi_cmp_enable1_s; } sh_xn_ni0_pi_cmp_enable1_u_t; -#else -typedef union sh_xn_ni0_pi_cmp_enable1_u { - mmr_t sh_xn_ni0_pi_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni0_pi_cmp_enable1_s; -} sh_xn_ni0_pi_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_MD_CMP_EXP_DATA0" */ /* NI0 compare MD input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni0_md_cmp_exp_data0_u { - mmr_t sh_xn_ni0_md_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_ni0_md_cmp_exp_data0_s; -} sh_xn_ni0_md_cmp_exp_data0_u_t; -#else typedef union sh_xn_ni0_md_cmp_exp_data0_u { mmr_t sh_xn_ni0_md_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_ni0_md_cmp_exp_data0_s; } sh_xn_ni0_md_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_MD_CMP_EXP_DATA1" */ /* NI0 compare MD input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni0_md_cmp_exp_data1_u { - mmr_t sh_xn_ni0_md_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_ni0_md_cmp_exp_data1_s; -} sh_xn_ni0_md_cmp_exp_data1_u_t; -#else typedef union sh_xn_ni0_md_cmp_exp_data1_u { mmr_t sh_xn_ni0_md_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_ni0_md_cmp_exp_data1_s; } sh_xn_ni0_md_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_MD_CMP_ENABLE0" */ /* NI0 compare MD input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_ni0_md_cmp_enable0_u { mmr_t sh_xn_ni0_md_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_ni0_md_cmp_enable0_s; } sh_xn_ni0_md_cmp_enable0_u_t; -#else -typedef union sh_xn_ni0_md_cmp_enable0_u { - mmr_t sh_xn_ni0_md_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni0_md_cmp_enable0_s; -} sh_xn_ni0_md_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_MD_CMP_ENABLE1" */ /* NI0 compare MD input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni0_md_cmp_enable1_u { - mmr_t sh_xn_ni0_md_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni0_md_cmp_enable1_s; -} sh_xn_ni0_md_cmp_enable1_u_t; -#else typedef union sh_xn_ni0_md_cmp_enable1_u { mmr_t sh_xn_ni0_md_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_ni0_md_cmp_enable1_s; } sh_xn_ni0_md_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_NI_CMP_EXP_DATA0" */ /* NI0 compare NI input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni0_ni_cmp_exp_data0_u { - mmr_t sh_xn_ni0_ni_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_ni0_ni_cmp_exp_data0_s; -} sh_xn_ni0_ni_cmp_exp_data0_u_t; -#else typedef union sh_xn_ni0_ni_cmp_exp_data0_u { mmr_t sh_xn_ni0_ni_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_ni0_ni_cmp_exp_data0_s; } sh_xn_ni0_ni_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_NI_CMP_EXP_DATA1" */ /* NI0 compare NI input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni0_ni_cmp_exp_data1_u { - mmr_t sh_xn_ni0_ni_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_ni0_ni_cmp_exp_data1_s; -} sh_xn_ni0_ni_cmp_exp_data1_u_t; -#else typedef union sh_xn_ni0_ni_cmp_exp_data1_u { mmr_t sh_xn_ni0_ni_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_ni0_ni_cmp_exp_data1_s; } sh_xn_ni0_ni_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_NI_CMP_ENABLE0" */ /* NI0 compare NI input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni0_ni_cmp_enable0_u { - mmr_t sh_xn_ni0_ni_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni0_ni_cmp_enable0_s; -} sh_xn_ni0_ni_cmp_enable0_u_t; -#else typedef union sh_xn_ni0_ni_cmp_enable0_u { mmr_t sh_xn_ni0_ni_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_ni0_ni_cmp_enable0_s; } sh_xn_ni0_ni_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_NI_CMP_ENABLE1" */ /* NI0 compare NI input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_ni0_ni_cmp_enable1_u { mmr_t sh_xn_ni0_ni_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_ni0_ni_cmp_enable1_s; } sh_xn_ni0_ni_cmp_enable1_u_t; -#else -typedef union sh_xn_ni0_ni_cmp_enable1_u { - mmr_t sh_xn_ni0_ni_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni0_ni_cmp_enable1_s; -} sh_xn_ni0_ni_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_LLP_CMP_EXP_DATA0" */ /* NI0 compare LLP input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni0_llp_cmp_exp_data0_u { - mmr_t sh_xn_ni0_llp_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_ni0_llp_cmp_exp_data0_s; -} sh_xn_ni0_llp_cmp_exp_data0_u_t; -#else typedef union sh_xn_ni0_llp_cmp_exp_data0_u { mmr_t sh_xn_ni0_llp_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_ni0_llp_cmp_exp_data0_s; } sh_xn_ni0_llp_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_LLP_CMP_EXP_DATA1" */ /* NI0 compare LLP input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni0_llp_cmp_exp_data1_u { - mmr_t sh_xn_ni0_llp_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_ni0_llp_cmp_exp_data1_s; -} sh_xn_ni0_llp_cmp_exp_data1_u_t; -#else typedef union sh_xn_ni0_llp_cmp_exp_data1_u { mmr_t sh_xn_ni0_llp_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_ni0_llp_cmp_exp_data1_s; } sh_xn_ni0_llp_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_LLP_CMP_ENABLE0" */ /* NI0 compare LLP input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni0_llp_cmp_enable0_u { - mmr_t sh_xn_ni0_llp_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni0_llp_cmp_enable0_s; -} sh_xn_ni0_llp_cmp_enable0_u_t; -#else typedef union sh_xn_ni0_llp_cmp_enable0_u { mmr_t sh_xn_ni0_llp_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_ni0_llp_cmp_enable0_s; } sh_xn_ni0_llp_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_LLP_CMP_ENABLE1" */ /* NI0 compare LLP input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni0_llp_cmp_enable1_u { - mmr_t sh_xn_ni0_llp_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni0_llp_cmp_enable1_s; -} sh_xn_ni0_llp_cmp_enable1_u_t; -#else typedef union sh_xn_ni0_llp_cmp_enable1_u { mmr_t sh_xn_ni0_llp_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_ni0_llp_cmp_enable1_s; } sh_xn_ni0_llp_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_IILB_CMP_EXP_DATA0" */ /* NI1 compare IILB input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_ni1_iilb_cmp_exp_data0_u { mmr_t sh_xn_ni1_iilb_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_ni1_iilb_cmp_exp_data0_s; } sh_xn_ni1_iilb_cmp_exp_data0_u_t; -#else -typedef union sh_xn_ni1_iilb_cmp_exp_data0_u { - mmr_t sh_xn_ni1_iilb_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_ni1_iilb_cmp_exp_data0_s; -} sh_xn_ni1_iilb_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_IILB_CMP_EXP_DATA1" */ /* NI1 compare IILB input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_ni1_iilb_cmp_exp_data1_u { mmr_t sh_xn_ni1_iilb_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_ni1_iilb_cmp_exp_data1_s; } sh_xn_ni1_iilb_cmp_exp_data1_u_t; -#else -typedef union sh_xn_ni1_iilb_cmp_exp_data1_u { - mmr_t sh_xn_ni1_iilb_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_ni1_iilb_cmp_exp_data1_s; -} sh_xn_ni1_iilb_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_IILB_CMP_ENABLE0" */ /* NI1 compare IILB input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni1_iilb_cmp_enable0_u { - mmr_t sh_xn_ni1_iilb_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni1_iilb_cmp_enable0_s; -} sh_xn_ni1_iilb_cmp_enable0_u_t; -#else typedef union sh_xn_ni1_iilb_cmp_enable0_u { mmr_t sh_xn_ni1_iilb_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_ni1_iilb_cmp_enable0_s; } sh_xn_ni1_iilb_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_IILB_CMP_ENABLE1" */ /* NI1 compare IILB input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni1_iilb_cmp_enable1_u { - mmr_t sh_xn_ni1_iilb_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni1_iilb_cmp_enable1_s; -} sh_xn_ni1_iilb_cmp_enable1_u_t; -#else typedef union sh_xn_ni1_iilb_cmp_enable1_u { mmr_t sh_xn_ni1_iilb_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_ni1_iilb_cmp_enable1_s; } sh_xn_ni1_iilb_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_PI_CMP_EXP_DATA0" */ /* NI1 compare PI input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni1_pi_cmp_exp_data0_u { - mmr_t sh_xn_ni1_pi_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_ni1_pi_cmp_exp_data0_s; -} sh_xn_ni1_pi_cmp_exp_data0_u_t; -#else typedef union sh_xn_ni1_pi_cmp_exp_data0_u { mmr_t sh_xn_ni1_pi_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_ni1_pi_cmp_exp_data0_s; } sh_xn_ni1_pi_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_PI_CMP_EXP_DATA1" */ /* NI1 compare PI input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_ni1_pi_cmp_exp_data1_u { mmr_t sh_xn_ni1_pi_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_ni1_pi_cmp_exp_data1_s; } sh_xn_ni1_pi_cmp_exp_data1_u_t; -#else -typedef union sh_xn_ni1_pi_cmp_exp_data1_u { - mmr_t sh_xn_ni1_pi_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_ni1_pi_cmp_exp_data1_s; -} sh_xn_ni1_pi_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_PI_CMP_ENABLE0" */ /* NI1 compare PI input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni1_pi_cmp_enable0_u { - mmr_t sh_xn_ni1_pi_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni1_pi_cmp_enable0_s; -} sh_xn_ni1_pi_cmp_enable0_u_t; -#else typedef union sh_xn_ni1_pi_cmp_enable0_u { mmr_t sh_xn_ni1_pi_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_ni1_pi_cmp_enable0_s; } sh_xn_ni1_pi_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_PI_CMP_ENABLE1" */ /* NI1 compare PI input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni1_pi_cmp_enable1_u { - mmr_t sh_xn_ni1_pi_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni1_pi_cmp_enable1_s; -} sh_xn_ni1_pi_cmp_enable1_u_t; -#else typedef union sh_xn_ni1_pi_cmp_enable1_u { mmr_t sh_xn_ni1_pi_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_ni1_pi_cmp_enable1_s; } sh_xn_ni1_pi_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_MD_CMP_EXP_DATA0" */ /* NI1 compare MD input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_ni1_md_cmp_exp_data0_u { mmr_t sh_xn_ni1_md_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_ni1_md_cmp_exp_data0_s; } sh_xn_ni1_md_cmp_exp_data0_u_t; -#else -typedef union sh_xn_ni1_md_cmp_exp_data0_u { - mmr_t sh_xn_ni1_md_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_ni1_md_cmp_exp_data0_s; -} sh_xn_ni1_md_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_MD_CMP_EXP_DATA1" */ /* NI1 compare MD input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni1_md_cmp_exp_data1_u { - mmr_t sh_xn_ni1_md_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_ni1_md_cmp_exp_data1_s; -} sh_xn_ni1_md_cmp_exp_data1_u_t; -#else typedef union sh_xn_ni1_md_cmp_exp_data1_u { mmr_t sh_xn_ni1_md_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_ni1_md_cmp_exp_data1_s; } sh_xn_ni1_md_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_MD_CMP_ENABLE0" */ /* NI1 compare MD input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_ni1_md_cmp_enable0_u { mmr_t sh_xn_ni1_md_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_ni1_md_cmp_enable0_s; } sh_xn_ni1_md_cmp_enable0_u_t; -#else -typedef union sh_xn_ni1_md_cmp_enable0_u { - mmr_t sh_xn_ni1_md_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni1_md_cmp_enable0_s; -} sh_xn_ni1_md_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_MD_CMP_ENABLE1" */ /* NI1 compare MD input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_ni1_md_cmp_enable1_u { mmr_t sh_xn_ni1_md_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_ni1_md_cmp_enable1_s; } sh_xn_ni1_md_cmp_enable1_u_t; -#else -typedef union sh_xn_ni1_md_cmp_enable1_u { - mmr_t sh_xn_ni1_md_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni1_md_cmp_enable1_s; -} sh_xn_ni1_md_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_NI_CMP_EXP_DATA0" */ /* NI1 compare NI input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni1_ni_cmp_exp_data0_u { - mmr_t sh_xn_ni1_ni_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_ni1_ni_cmp_exp_data0_s; -} sh_xn_ni1_ni_cmp_exp_data0_u_t; -#else typedef union sh_xn_ni1_ni_cmp_exp_data0_u { mmr_t sh_xn_ni1_ni_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_ni1_ni_cmp_exp_data0_s; } sh_xn_ni1_ni_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_NI_CMP_EXP_DATA1" */ /* NI1 compare NI input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_ni1_ni_cmp_exp_data1_u { mmr_t sh_xn_ni1_ni_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_ni1_ni_cmp_exp_data1_s; } sh_xn_ni1_ni_cmp_exp_data1_u_t; -#else -typedef union sh_xn_ni1_ni_cmp_exp_data1_u { - mmr_t sh_xn_ni1_ni_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_ni1_ni_cmp_exp_data1_s; -} sh_xn_ni1_ni_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_NI_CMP_ENABLE0" */ /* NI1 compare NI input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni1_ni_cmp_enable0_u { - mmr_t sh_xn_ni1_ni_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni1_ni_cmp_enable0_s; -} sh_xn_ni1_ni_cmp_enable0_u_t; -#else typedef union sh_xn_ni1_ni_cmp_enable0_u { mmr_t sh_xn_ni1_ni_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_ni1_ni_cmp_enable0_s; } sh_xn_ni1_ni_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_NI_CMP_ENABLE1" */ /* NI1 compare NI input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni1_ni_cmp_enable1_u { - mmr_t sh_xn_ni1_ni_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni1_ni_cmp_enable1_s; -} sh_xn_ni1_ni_cmp_enable1_u_t; -#else typedef union sh_xn_ni1_ni_cmp_enable1_u { mmr_t sh_xn_ni1_ni_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_ni1_ni_cmp_enable1_s; } sh_xn_ni1_ni_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_LLP_CMP_EXP_DATA0" */ /* NI1 compare LLP input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni1_llp_cmp_exp_data0_u { - mmr_t sh_xn_ni1_llp_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_ni1_llp_cmp_exp_data0_s; -} sh_xn_ni1_llp_cmp_exp_data0_u_t; -#else typedef union sh_xn_ni1_llp_cmp_exp_data0_u { mmr_t sh_xn_ni1_llp_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_ni1_llp_cmp_exp_data0_s; } sh_xn_ni1_llp_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_LLP_CMP_EXP_DATA1" */ /* NI1 compare LLP input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni1_llp_cmp_exp_data1_u { - mmr_t sh_xn_ni1_llp_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_ni1_llp_cmp_exp_data1_s; -} sh_xn_ni1_llp_cmp_exp_data1_u_t; -#else typedef union sh_xn_ni1_llp_cmp_exp_data1_u { mmr_t sh_xn_ni1_llp_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_ni1_llp_cmp_exp_data1_s; } sh_xn_ni1_llp_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_LLP_CMP_ENABLE0" */ /* NI1 compare LLP input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni1_llp_cmp_enable0_u { - mmr_t sh_xn_ni1_llp_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni1_llp_cmp_enable0_s; -} sh_xn_ni1_llp_cmp_enable0_u_t; -#else typedef union sh_xn_ni1_llp_cmp_enable0_u { mmr_t sh_xn_ni1_llp_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_ni1_llp_cmp_enable0_s; } sh_xn_ni1_llp_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_LLP_CMP_ENABLE1" */ /* NI1 compare LLP input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni1_llp_cmp_enable1_u { - mmr_t sh_xn_ni1_llp_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni1_llp_cmp_enable1_s; -} sh_xn_ni1_llp_cmp_enable1_u_t; -#else typedef union sh_xn_ni1_llp_cmp_enable1_u { mmr_t sh_xn_ni1_llp_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_ni1_llp_cmp_enable1_s; } sh_xn_ni1_llp_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_ECC_INJ_REG" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnpi_ecc_inj_reg_u { mmr_t sh_xnpi_ecc_inj_reg_regval; struct { @@ -13182,123 +7173,55 @@ typedef union sh_xnpi_ecc_inj_reg_u { mmr_t data_cb_cont3 : 1; } sh_xnpi_ecc_inj_reg_s; } sh_xnpi_ecc_inj_reg_u_t; -#else -typedef union sh_xnpi_ecc_inj_reg_u { - mmr_t sh_xnpi_ecc_inj_reg_regval; - struct { - mmr_t data_cb_cont3 : 1; - mmr_t data_cb_1shot3 : 1; - mmr_t data_cont3 : 1; - mmr_t data_1shot3 : 1; - mmr_t reserved_3 : 4; - mmr_t byte3 : 8; - mmr_t data_cb_cont2 : 1; - mmr_t data_cb_1shot2 : 1; - mmr_t data_cont2 : 1; - mmr_t data_1shot2 : 1; - mmr_t reserved_2 : 4; - mmr_t byte2 : 8; - mmr_t data_cb_cont1 : 1; - mmr_t data_cb_1shot1 : 1; - mmr_t data_cont1 : 1; - mmr_t data_1shot1 : 1; - mmr_t reserved_1 : 4; - mmr_t byte1 : 8; - mmr_t data_cb_cont0 : 1; - mmr_t data_cb_1shot0 : 1; - mmr_t data_cont0 : 1; - mmr_t data_1shot0 : 1; - mmr_t reserved_0 : 4; - mmr_t byte0 : 8; - } sh_xnpi_ecc_inj_reg_s; -} sh_xnpi_ecc_inj_reg_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_ECC0_INJ_MASK_REG" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnpi_ecc0_inj_mask_reg_u { mmr_t sh_xnpi_ecc0_inj_mask_reg_regval; struct { mmr_t mask_ecc0 : 64; } sh_xnpi_ecc0_inj_mask_reg_s; } sh_xnpi_ecc0_inj_mask_reg_u_t; -#else -typedef union sh_xnpi_ecc0_inj_mask_reg_u { - mmr_t sh_xnpi_ecc0_inj_mask_reg_regval; - struct { - mmr_t mask_ecc0 : 64; - } sh_xnpi_ecc0_inj_mask_reg_s; -} sh_xnpi_ecc0_inj_mask_reg_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_ECC1_INJ_MASK_REG" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xnpi_ecc1_inj_mask_reg_u { - mmr_t sh_xnpi_ecc1_inj_mask_reg_regval; - struct { - mmr_t mask_ecc1 : 64; - } sh_xnpi_ecc1_inj_mask_reg_s; -} sh_xnpi_ecc1_inj_mask_reg_u_t; -#else typedef union sh_xnpi_ecc1_inj_mask_reg_u { mmr_t sh_xnpi_ecc1_inj_mask_reg_regval; struct { mmr_t mask_ecc1 : 64; } sh_xnpi_ecc1_inj_mask_reg_s; } sh_xnpi_ecc1_inj_mask_reg_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_ECC2_INJ_MASK_REG" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xnpi_ecc2_inj_mask_reg_u { - mmr_t sh_xnpi_ecc2_inj_mask_reg_regval; - struct { - mmr_t mask_ecc2 : 64; - } sh_xnpi_ecc2_inj_mask_reg_s; -} sh_xnpi_ecc2_inj_mask_reg_u_t; -#else typedef union sh_xnpi_ecc2_inj_mask_reg_u { mmr_t sh_xnpi_ecc2_inj_mask_reg_regval; struct { mmr_t mask_ecc2 : 64; } sh_xnpi_ecc2_inj_mask_reg_s; } sh_xnpi_ecc2_inj_mask_reg_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_ECC3_INJ_MASK_REG" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnpi_ecc3_inj_mask_reg_u { mmr_t sh_xnpi_ecc3_inj_mask_reg_regval; struct { mmr_t mask_ecc3 : 64; } sh_xnpi_ecc3_inj_mask_reg_s; } sh_xnpi_ecc3_inj_mask_reg_u_t; -#else -typedef union sh_xnpi_ecc3_inj_mask_reg_u { - mmr_t sh_xnpi_ecc3_inj_mask_reg_regval; - struct { - mmr_t mask_ecc3 : 64; - } sh_xnpi_ecc3_inj_mask_reg_s; -} sh_xnpi_ecc3_inj_mask_reg_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_ECC_INJ_REG" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnmd_ecc_inj_reg_u { mmr_t sh_xnmd_ecc_inj_reg_regval; struct { @@ -13328,123 +7251,55 @@ typedef union sh_xnmd_ecc_inj_reg_u { mmr_t data_cb_cont3 : 1; } sh_xnmd_ecc_inj_reg_s; } sh_xnmd_ecc_inj_reg_u_t; -#else -typedef union sh_xnmd_ecc_inj_reg_u { - mmr_t sh_xnmd_ecc_inj_reg_regval; - struct { - mmr_t data_cb_cont3 : 1; - mmr_t data_cb_1shot3 : 1; - mmr_t data_cont3 : 1; - mmr_t data_1shot3 : 1; - mmr_t reserved_3 : 4; - mmr_t byte3 : 8; - mmr_t data_cb_cont2 : 1; - mmr_t data_cb_1shot2 : 1; - mmr_t data_cont2 : 1; - mmr_t data_1shot2 : 1; - mmr_t reserved_2 : 4; - mmr_t byte2 : 8; - mmr_t data_cb_cont1 : 1; - mmr_t data_cb_1shot1 : 1; - mmr_t data_cont1 : 1; - mmr_t data_1shot1 : 1; - mmr_t reserved_1 : 4; - mmr_t byte1 : 8; - mmr_t data_cb_cont0 : 1; - mmr_t data_cb_1shot0 : 1; - mmr_t data_cont0 : 1; - mmr_t data_1shot0 : 1; - mmr_t reserved_0 : 4; - mmr_t byte0 : 8; - } sh_xnmd_ecc_inj_reg_s; -} sh_xnmd_ecc_inj_reg_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_ECC0_INJ_MASK_REG" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xnmd_ecc0_inj_mask_reg_u { - mmr_t sh_xnmd_ecc0_inj_mask_reg_regval; - struct { - mmr_t mask_ecc0 : 64; - } sh_xnmd_ecc0_inj_mask_reg_s; -} sh_xnmd_ecc0_inj_mask_reg_u_t; -#else typedef union sh_xnmd_ecc0_inj_mask_reg_u { mmr_t sh_xnmd_ecc0_inj_mask_reg_regval; struct { mmr_t mask_ecc0 : 64; } sh_xnmd_ecc0_inj_mask_reg_s; } sh_xnmd_ecc0_inj_mask_reg_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_ECC1_INJ_MASK_REG" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnmd_ecc1_inj_mask_reg_u { mmr_t sh_xnmd_ecc1_inj_mask_reg_regval; struct { mmr_t mask_ecc1 : 64; } sh_xnmd_ecc1_inj_mask_reg_s; } sh_xnmd_ecc1_inj_mask_reg_u_t; -#else -typedef union sh_xnmd_ecc1_inj_mask_reg_u { - mmr_t sh_xnmd_ecc1_inj_mask_reg_regval; - struct { - mmr_t mask_ecc1 : 64; - } sh_xnmd_ecc1_inj_mask_reg_s; -} sh_xnmd_ecc1_inj_mask_reg_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_ECC2_INJ_MASK_REG" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xnmd_ecc2_inj_mask_reg_u { - mmr_t sh_xnmd_ecc2_inj_mask_reg_regval; - struct { - mmr_t mask_ecc2 : 64; - } sh_xnmd_ecc2_inj_mask_reg_s; -} sh_xnmd_ecc2_inj_mask_reg_u_t; -#else typedef union sh_xnmd_ecc2_inj_mask_reg_u { mmr_t sh_xnmd_ecc2_inj_mask_reg_regval; struct { mmr_t mask_ecc2 : 64; } sh_xnmd_ecc2_inj_mask_reg_s; } sh_xnmd_ecc2_inj_mask_reg_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_ECC3_INJ_MASK_REG" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xnmd_ecc3_inj_mask_reg_u { - mmr_t sh_xnmd_ecc3_inj_mask_reg_regval; - struct { - mmr_t mask_ecc3 : 64; - } sh_xnmd_ecc3_inj_mask_reg_s; -} sh_xnmd_ecc3_inj_mask_reg_u_t; -#else typedef union sh_xnmd_ecc3_inj_mask_reg_u { mmr_t sh_xnmd_ecc3_inj_mask_reg_regval; struct { mmr_t mask_ecc3 : 64; } sh_xnmd_ecc3_inj_mask_reg_s; } sh_xnmd_ecc3_inj_mask_reg_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_ECC_ERR_REPORT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnmd_ecc_err_report_u { mmr_t sh_xnmd_ecc_err_report_regval; struct { @@ -13458,28 +7313,12 @@ typedef union sh_xnmd_ecc_err_report_u { mmr_t reserved_3 : 15; } sh_xnmd_ecc_err_report_s; } sh_xnmd_ecc_err_report_u_t; -#else -typedef union sh_xnmd_ecc_err_report_u { - mmr_t sh_xnmd_ecc_err_report_regval; - struct { - mmr_t reserved_3 : 15; - mmr_t ecc_disable3 : 1; - mmr_t reserved_2 : 15; - mmr_t ecc_disable2 : 1; - mmr_t reserved_1 : 15; - mmr_t ecc_disable1 : 1; - mmr_t reserved_0 : 15; - mmr_t ecc_disable0 : 1; - } sh_xnmd_ecc_err_report_s; -} sh_xnmd_ecc_err_report_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_ERROR_SUMMARY_1" */ /* ni0 Error Summary Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_error_summary_1_u { mmr_t sh_ni0_error_summary_1_regval; struct { @@ -13549,84 +7388,12 @@ typedef union sh_ni0_error_summary_1_u { mmr_t tail_timeout_ni_vc3 : 1; } sh_ni0_error_summary_1_s; } sh_ni0_error_summary_1_u_t; -#else -typedef union sh_ni0_error_summary_1_u { - mmr_t sh_ni0_error_summary_1_regval; - struct { - mmr_t tail_timeout_ni_vc3 : 1; - mmr_t tail_timeout_ni_vc2 : 1; - mmr_t tail_timeout_ni_vc1 : 1; - mmr_t tail_timeout_ni_vc0 : 1; - mmr_t tail_timeout_fifo13_vc3 : 1; - mmr_t tail_timeout_fifo13_vc1 : 1; - mmr_t tail_timeout_fifo02_vc2 : 1; - mmr_t tail_timeout_fifo02_vc0 : 1; - mmr_t overflow_ni_fifo_vc3_credit : 1; - mmr_t overflow_ni_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc1_credit : 1; - mmr_t overflow_ni_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_credit : 1; - mmr_t overflow_md_fifo_vc0_credit : 1; - mmr_t overflow_iilb_fifo_vc2_credit : 1; - mmr_t overflow_iilb_fifo_vc0_credit : 1; - mmr_t overflow_pi_fifo_vc2_credit : 1; - mmr_t overflow_pi_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_push : 1; - mmr_t overflow_md_fifo_vc0_push : 1; - mmr_t overflow_iilb_fifo_vc2_push : 1; - mmr_t overflow_iilb_fifo_vc0_push : 1; - mmr_t overflow_pi_fifo_vc2_push : 1; - mmr_t overflow_pi_fifo_vc0_push : 1; - mmr_t overflow_ni_fifo_vc2_pop : 1; - mmr_t overflow_ni_fifo_vc0_pop : 1; - mmr_t overflow_md_fifo_vc2_pop : 1; - mmr_t overflow_md_fifo_vc0_pop : 1; - mmr_t overflow_iilb_fifo_vc2_pop : 1; - mmr_t overflow_iilb_fifo_vc0_pop : 1; - mmr_t overflow_pi_fifo_vc2_pop : 1; - mmr_t overflow_pi_fifo_vc0_pop : 1; - mmr_t overflow_ni_fifo_debit3 : 1; - mmr_t overflow_ni_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit1 : 1; - mmr_t overflow_ni_fifo_debit0 : 1; - mmr_t overflow_md_fifo_debit2 : 1; - mmr_t overflow_md_fifo_debit0 : 1; - mmr_t overflow_iilb_fifo_debit2 : 1; - mmr_t overflow_iilb_fifo_debit0 : 1; - mmr_t overflow_pi_fifo_debit2 : 1; - mmr_t overflow_pi_fifo_debit0 : 1; - mmr_t overflow2_vc2_credit : 1; - mmr_t overflow1_vc2_credit : 1; - mmr_t overflow0_vc2_credit : 1; - mmr_t overflow2_vc0_credit : 1; - mmr_t overflow1_vc0_credit : 1; - mmr_t overflow0_vc0_credit : 1; - mmr_t overflow_fifo13_vc2_credit : 1; - mmr_t overflow_fifo13_vc0_credit : 1; - mmr_t overflow_fifo02_vc2_credit : 1; - mmr_t overflow_fifo02_vc0_credit : 1; - mmr_t overflow_fifo13_vc3_push : 1; - mmr_t overflow_fifo13_vc1_push : 1; - mmr_t overflow_fifo02_vc2_push : 1; - mmr_t overflow_fifo02_vc0_push : 1; - mmr_t overflow_fifo13_vc3_pop : 1; - mmr_t overflow_fifo13_vc1_pop : 1; - mmr_t overflow_fifo02_vc2_pop : 1; - mmr_t overflow_fifo02_vc0_pop : 1; - mmr_t overflow_fifo13_debit2 : 1; - mmr_t overflow_fifo13_debit0 : 1; - mmr_t overflow_fifo02_debit2 : 1; - mmr_t overflow_fifo02_debit0 : 1; - } sh_ni0_error_summary_1_s; -} sh_ni0_error_summary_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_ERROR_SUMMARY_2" */ /* ni0 Error Summary Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_error_summary_2_u { mmr_t sh_ni0_error_summary_2_regval; struct { @@ -13687,75 +7454,12 @@ typedef union sh_ni0_error_summary_2_u { mmr_t reserved_1 : 1; } sh_ni0_error_summary_2_s; } sh_ni0_error_summary_2_u_t; -#else -typedef union sh_ni0_error_summary_2_u { - mmr_t sh_ni0_error_summary_2_regval; - struct { - mmr_t reserved_1 : 1; - mmr_t retry_timeout_error : 1; - mmr_t lut_read_error : 1; - mmr_t chiplet_nomatch : 1; - mmr_t llp_deadlock_vc3 : 1; - mmr_t llp_deadlock_vc2 : 1; - mmr_t llp_deadlock_vc1 : 1; - mmr_t llp_deadlock_vc0 : 1; - mmr_t underflow_ni_fifo_vc3_credit : 1; - mmr_t underflow_ni_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc1_credit : 1; - mmr_t underflow_ni_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_credit : 1; - mmr_t underflow_md_fifo_vc0_credit : 1; - mmr_t underflow_iilb_fifo_vc2_credit : 1; - mmr_t underflow_iilb_fifo_vc0_credit : 1; - mmr_t underflow_pi_fifo_vc2_credit : 1; - mmr_t underflow_pi_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_push : 1; - mmr_t underflow_md_fifo_vc0_push : 1; - mmr_t underflow_iilb_fifo_vc2_push : 1; - mmr_t underflow_iilb_fifo_vc0_push : 1; - mmr_t underflow_pi_fifo_vc2_push : 1; - mmr_t underflow_pi_fifo_vc0_push : 1; - mmr_t underflow_ni_fifo_vc2_pop : 1; - mmr_t underflow_ni_fifo_vc0_pop : 1; - mmr_t underflow_md_fifo_vc2_pop : 1; - mmr_t underflow_md_fifo_vc0_pop : 1; - mmr_t underflow_iilb_fifo_vc2_pop : 1; - mmr_t underflow_iilb_fifo_vc0_pop : 1; - mmr_t underflow_pi_fifo_vc2_pop : 1; - mmr_t underflow_pi_fifo_vc0_pop : 1; - mmr_t reserved_0 : 10; - mmr_t underflow2_vc2_credit : 1; - mmr_t underflow1_vc2_credit : 1; - mmr_t underflow0_vc2_credit : 1; - mmr_t underflow2_vc0_credit : 1; - mmr_t underflow1_vc0_credit : 1; - mmr_t underflow0_vc0_credit : 1; - mmr_t underflow_fifo13_vc2_credit : 1; - mmr_t underflow_fifo13_vc0_credit : 1; - mmr_t underflow_fifo02_vc2_credit : 1; - mmr_t underflow_fifo02_vc0_credit : 1; - mmr_t underflow_fifo13_vc3_push : 1; - mmr_t underflow_fifo13_vc1_push : 1; - mmr_t underflow_fifo02_vc2_push : 1; - mmr_t underflow_fifo02_vc0_push : 1; - mmr_t underflow_fifo13_vc3_pop : 1; - mmr_t underflow_fifo13_vc1_pop : 1; - mmr_t underflow_fifo02_vc2_pop : 1; - mmr_t underflow_fifo02_vc0_pop : 1; - mmr_t illegal_vciilb : 1; - mmr_t illegal_vcmd : 1; - mmr_t illegal_vcpi : 1; - mmr_t illegal_vcni : 1; - } sh_ni0_error_summary_2_s; -} sh_ni0_error_summary_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_ERROR_OVERFLOW_1" */ /* ni0 Error Overflow Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_error_overflow_1_u { mmr_t sh_ni0_error_overflow_1_regval; struct { @@ -13825,84 +7529,12 @@ typedef union sh_ni0_error_overflow_1_u { mmr_t tail_timeout_ni_vc3 : 1; } sh_ni0_error_overflow_1_s; } sh_ni0_error_overflow_1_u_t; -#else -typedef union sh_ni0_error_overflow_1_u { - mmr_t sh_ni0_error_overflow_1_regval; - struct { - mmr_t tail_timeout_ni_vc3 : 1; - mmr_t tail_timeout_ni_vc2 : 1; - mmr_t tail_timeout_ni_vc1 : 1; - mmr_t tail_timeout_ni_vc0 : 1; - mmr_t tail_timeout_fifo13_vc3 : 1; - mmr_t tail_timeout_fifo13_vc1 : 1; - mmr_t tail_timeout_fifo02_vc2 : 1; - mmr_t tail_timeout_fifo02_vc0 : 1; - mmr_t overflow_ni_fifo_vc3_credit : 1; - mmr_t overflow_ni_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc1_credit : 1; - mmr_t overflow_ni_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_credit : 1; - mmr_t overflow_md_fifo_vc0_credit : 1; - mmr_t overflow_iilb_fifo_vc2_credit : 1; - mmr_t overflow_iilb_fifo_vc0_credit : 1; - mmr_t overflow_pi_fifo_vc2_credit : 1; - mmr_t overflow_pi_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_push : 1; - mmr_t overflow_md_fifo_vc0_push : 1; - mmr_t overflow_iilb_fifo_vc2_push : 1; - mmr_t overflow_iilb_fifo_vc0_push : 1; - mmr_t overflow_pi_fifo_vc2_push : 1; - mmr_t overflow_pi_fifo_vc0_push : 1; - mmr_t overflow_ni_fifo_vc2_pop : 1; - mmr_t overflow_ni_fifo_vc0_pop : 1; - mmr_t overflow_md_fifo_vc2_pop : 1; - mmr_t overflow_md_fifo_vc0_pop : 1; - mmr_t overflow_iilb_fifo_vc2_pop : 1; - mmr_t overflow_iilb_fifo_vc0_pop : 1; - mmr_t overflow_pi_fifo_vc2_pop : 1; - mmr_t overflow_pi_fifo_vc0_pop : 1; - mmr_t overflow_ni_fifo_debit3 : 1; - mmr_t overflow_ni_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit1 : 1; - mmr_t overflow_ni_fifo_debit0 : 1; - mmr_t overflow_md_fifo_debit2 : 1; - mmr_t overflow_md_fifo_debit0 : 1; - mmr_t overflow_iilb_fifo_debit2 : 1; - mmr_t overflow_iilb_fifo_debit0 : 1; - mmr_t overflow_pi_fifo_debit2 : 1; - mmr_t overflow_pi_fifo_debit0 : 1; - mmr_t overflow2_vc2_credit : 1; - mmr_t overflow1_vc2_credit : 1; - mmr_t overflow0_vc2_credit : 1; - mmr_t overflow2_vc0_credit : 1; - mmr_t overflow1_vc0_credit : 1; - mmr_t overflow0_vc0_credit : 1; - mmr_t overflow_fifo13_vc2_credit : 1; - mmr_t overflow_fifo13_vc0_credit : 1; - mmr_t overflow_fifo02_vc2_credit : 1; - mmr_t overflow_fifo02_vc0_credit : 1; - mmr_t overflow_fifo13_vc3_push : 1; - mmr_t overflow_fifo13_vc1_push : 1; - mmr_t overflow_fifo02_vc2_push : 1; - mmr_t overflow_fifo02_vc0_push : 1; - mmr_t overflow_fifo13_vc3_pop : 1; - mmr_t overflow_fifo13_vc1_pop : 1; - mmr_t overflow_fifo02_vc2_pop : 1; - mmr_t overflow_fifo02_vc0_pop : 1; - mmr_t overflow_fifo13_debit2 : 1; - mmr_t overflow_fifo13_debit0 : 1; - mmr_t overflow_fifo02_debit2 : 1; - mmr_t overflow_fifo02_debit0 : 1; - } sh_ni0_error_overflow_1_s; -} sh_ni0_error_overflow_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_ERROR_OVERFLOW_2" */ /* ni0 Error Overflow Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_error_overflow_2_u { mmr_t sh_ni0_error_overflow_2_regval; struct { @@ -13963,75 +7595,12 @@ typedef union sh_ni0_error_overflow_2_u { mmr_t reserved_1 : 1; } sh_ni0_error_overflow_2_s; } sh_ni0_error_overflow_2_u_t; -#else -typedef union sh_ni0_error_overflow_2_u { - mmr_t sh_ni0_error_overflow_2_regval; - struct { - mmr_t reserved_1 : 1; - mmr_t retry_timeout_error : 1; - mmr_t lut_read_error : 1; - mmr_t chiplet_nomatch : 1; - mmr_t llp_deadlock_vc3 : 1; - mmr_t llp_deadlock_vc2 : 1; - mmr_t llp_deadlock_vc1 : 1; - mmr_t llp_deadlock_vc0 : 1; - mmr_t underflow_ni_fifo_vc3_credit : 1; - mmr_t underflow_ni_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc1_credit : 1; - mmr_t underflow_ni_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_credit : 1; - mmr_t underflow_md_fifo_vc0_credit : 1; - mmr_t underflow_iilb_fifo_vc2_credit : 1; - mmr_t underflow_iilb_fifo_vc0_credit : 1; - mmr_t underflow_pi_fifo_vc2_credit : 1; - mmr_t underflow_pi_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_push : 1; - mmr_t underflow_md_fifo_vc0_push : 1; - mmr_t underflow_iilb_fifo_vc2_push : 1; - mmr_t underflow_iilb_fifo_vc0_push : 1; - mmr_t underflow_pi_fifo_vc2_push : 1; - mmr_t underflow_pi_fifo_vc0_push : 1; - mmr_t underflow_ni_fifo_vc2_pop : 1; - mmr_t underflow_ni_fifo_vc0_pop : 1; - mmr_t underflow_md_fifo_vc2_pop : 1; - mmr_t underflow_md_fifo_vc0_pop : 1; - mmr_t underflow_iilb_fifo_vc2_pop : 1; - mmr_t underflow_iilb_fifo_vc0_pop : 1; - mmr_t underflow_pi_fifo_vc2_pop : 1; - mmr_t underflow_pi_fifo_vc0_pop : 1; - mmr_t reserved_0 : 10; - mmr_t underflow2_vc2_credit : 1; - mmr_t underflow1_vc2_credit : 1; - mmr_t underflow0_vc2_credit : 1; - mmr_t underflow2_vc0_credit : 1; - mmr_t underflow1_vc0_credit : 1; - mmr_t underflow0_vc0_credit : 1; - mmr_t underflow_fifo13_vc2_credit : 1; - mmr_t underflow_fifo13_vc0_credit : 1; - mmr_t underflow_fifo02_vc2_credit : 1; - mmr_t underflow_fifo02_vc0_credit : 1; - mmr_t underflow_fifo13_vc3_push : 1; - mmr_t underflow_fifo13_vc1_push : 1; - mmr_t underflow_fifo02_vc2_push : 1; - mmr_t underflow_fifo02_vc0_push : 1; - mmr_t underflow_fifo13_vc3_pop : 1; - mmr_t underflow_fifo13_vc1_pop : 1; - mmr_t underflow_fifo02_vc2_pop : 1; - mmr_t underflow_fifo02_vc0_pop : 1; - mmr_t illegal_vciilb : 1; - mmr_t illegal_vcmd : 1; - mmr_t illegal_vcpi : 1; - mmr_t illegal_vcni : 1; - } sh_ni0_error_overflow_2_s; -} sh_ni0_error_overflow_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_ERROR_MASK_1" */ /* ni0 Error Mask Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_error_mask_1_u { mmr_t sh_ni0_error_mask_1_regval; struct { @@ -14101,84 +7670,12 @@ typedef union sh_ni0_error_mask_1_u { mmr_t tail_timeout_ni_vc3 : 1; } sh_ni0_error_mask_1_s; } sh_ni0_error_mask_1_u_t; -#else -typedef union sh_ni0_error_mask_1_u { - mmr_t sh_ni0_error_mask_1_regval; - struct { - mmr_t tail_timeout_ni_vc3 : 1; - mmr_t tail_timeout_ni_vc2 : 1; - mmr_t tail_timeout_ni_vc1 : 1; - mmr_t tail_timeout_ni_vc0 : 1; - mmr_t tail_timeout_fifo13_vc3 : 1; - mmr_t tail_timeout_fifo13_vc1 : 1; - mmr_t tail_timeout_fifo02_vc2 : 1; - mmr_t tail_timeout_fifo02_vc0 : 1; - mmr_t overflow_ni_fifo_vc3_credit : 1; - mmr_t overflow_ni_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc1_credit : 1; - mmr_t overflow_ni_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_credit : 1; - mmr_t overflow_md_fifo_vc0_credit : 1; - mmr_t overflow_iilb_fifo_vc2_credit : 1; - mmr_t overflow_iilb_fifo_vc0_credit : 1; - mmr_t overflow_pi_fifo_vc2_credit : 1; - mmr_t overflow_pi_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_push : 1; - mmr_t overflow_md_fifo_vc0_push : 1; - mmr_t overflow_iilb_fifo_vc2_push : 1; - mmr_t overflow_iilb_fifo_vc0_push : 1; - mmr_t overflow_pi_fifo_vc2_push : 1; - mmr_t overflow_pi_fifo_vc0_push : 1; - mmr_t overflow_ni_fifo_vc2_pop : 1; - mmr_t overflow_ni_fifo_vc0_pop : 1; - mmr_t overflow_md_fifo_vc2_pop : 1; - mmr_t overflow_md_fifo_vc0_pop : 1; - mmr_t overflow_iilb_fifo_vc2_pop : 1; - mmr_t overflow_iilb_fifo_vc0_pop : 1; - mmr_t overflow_pi_fifo_vc2_pop : 1; - mmr_t overflow_pi_fifo_vc0_pop : 1; - mmr_t overflow_ni_fifo_debit3 : 1; - mmr_t overflow_ni_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit1 : 1; - mmr_t overflow_ni_fifo_debit0 : 1; - mmr_t overflow_md_fifo_debit2 : 1; - mmr_t overflow_md_fifo_debit0 : 1; - mmr_t overflow_iilb_fifo_debit2 : 1; - mmr_t overflow_iilb_fifo_debit0 : 1; - mmr_t overflow_pi_fifo_debit2 : 1; - mmr_t overflow_pi_fifo_debit0 : 1; - mmr_t overflow2_vc2_credit : 1; - mmr_t overflow1_vc2_credit : 1; - mmr_t overflow0_vc2_credit : 1; - mmr_t overflow2_vc0_credit : 1; - mmr_t overflow1_vc0_credit : 1; - mmr_t overflow0_vc0_credit : 1; - mmr_t overflow_fifo13_vc2_credit : 1; - mmr_t overflow_fifo13_vc0_credit : 1; - mmr_t overflow_fifo02_vc2_credit : 1; - mmr_t overflow_fifo02_vc0_credit : 1; - mmr_t overflow_fifo13_vc3_push : 1; - mmr_t overflow_fifo13_vc1_push : 1; - mmr_t overflow_fifo02_vc2_push : 1; - mmr_t overflow_fifo02_vc0_push : 1; - mmr_t overflow_fifo13_vc3_pop : 1; - mmr_t overflow_fifo13_vc1_pop : 1; - mmr_t overflow_fifo02_vc2_pop : 1; - mmr_t overflow_fifo02_vc0_pop : 1; - mmr_t overflow_fifo13_debit2 : 1; - mmr_t overflow_fifo13_debit0 : 1; - mmr_t overflow_fifo02_debit2 : 1; - mmr_t overflow_fifo02_debit0 : 1; - } sh_ni0_error_mask_1_s; -} sh_ni0_error_mask_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_ERROR_MASK_2" */ /* ni0 Error Mask Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_error_mask_2_u { mmr_t sh_ni0_error_mask_2_regval; struct { @@ -14239,75 +7736,12 @@ typedef union sh_ni0_error_mask_2_u { mmr_t reserved_1 : 1; } sh_ni0_error_mask_2_s; } sh_ni0_error_mask_2_u_t; -#else -typedef union sh_ni0_error_mask_2_u { - mmr_t sh_ni0_error_mask_2_regval; - struct { - mmr_t reserved_1 : 1; - mmr_t retry_timeout_error : 1; - mmr_t lut_read_error : 1; - mmr_t chiplet_nomatch : 1; - mmr_t llp_deadlock_vc3 : 1; - mmr_t llp_deadlock_vc2 : 1; - mmr_t llp_deadlock_vc1 : 1; - mmr_t llp_deadlock_vc0 : 1; - mmr_t underflow_ni_fifo_vc3_credit : 1; - mmr_t underflow_ni_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc1_credit : 1; - mmr_t underflow_ni_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_credit : 1; - mmr_t underflow_md_fifo_vc0_credit : 1; - mmr_t underflow_iilb_fifo_vc2_credit : 1; - mmr_t underflow_iilb_fifo_vc0_credit : 1; - mmr_t underflow_pi_fifo_vc2_credit : 1; - mmr_t underflow_pi_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_push : 1; - mmr_t underflow_md_fifo_vc0_push : 1; - mmr_t underflow_iilb_fifo_vc2_push : 1; - mmr_t underflow_iilb_fifo_vc0_push : 1; - mmr_t underflow_pi_fifo_vc2_push : 1; - mmr_t underflow_pi_fifo_vc0_push : 1; - mmr_t underflow_ni_fifo_vc2_pop : 1; - mmr_t underflow_ni_fifo_vc0_pop : 1; - mmr_t underflow_md_fifo_vc2_pop : 1; - mmr_t underflow_md_fifo_vc0_pop : 1; - mmr_t underflow_iilb_fifo_vc2_pop : 1; - mmr_t underflow_iilb_fifo_vc0_pop : 1; - mmr_t underflow_pi_fifo_vc2_pop : 1; - mmr_t underflow_pi_fifo_vc0_pop : 1; - mmr_t reserved_0 : 10; - mmr_t underflow2_vc2_credit : 1; - mmr_t underflow1_vc2_credit : 1; - mmr_t underflow0_vc2_credit : 1; - mmr_t underflow2_vc0_credit : 1; - mmr_t underflow1_vc0_credit : 1; - mmr_t underflow0_vc0_credit : 1; - mmr_t underflow_fifo13_vc2_credit : 1; - mmr_t underflow_fifo13_vc0_credit : 1; - mmr_t underflow_fifo02_vc2_credit : 1; - mmr_t underflow_fifo02_vc0_credit : 1; - mmr_t underflow_fifo13_vc3_push : 1; - mmr_t underflow_fifo13_vc1_push : 1; - mmr_t underflow_fifo02_vc2_push : 1; - mmr_t underflow_fifo02_vc0_push : 1; - mmr_t underflow_fifo13_vc3_pop : 1; - mmr_t underflow_fifo13_vc1_pop : 1; - mmr_t underflow_fifo02_vc2_pop : 1; - mmr_t underflow_fifo02_vc0_pop : 1; - mmr_t illegal_vciilb : 1; - mmr_t illegal_vcmd : 1; - mmr_t illegal_vcpi : 1; - mmr_t illegal_vcni : 1; - } sh_ni0_error_mask_2_s; -} sh_ni0_error_mask_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_FIRST_ERROR_1" */ /* ni0 First Error Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_first_error_1_u { mmr_t sh_ni0_first_error_1_regval; struct { @@ -14377,84 +7811,12 @@ typedef union sh_ni0_first_error_1_u { mmr_t tail_timeout_ni_vc3 : 1; } sh_ni0_first_error_1_s; } sh_ni0_first_error_1_u_t; -#else -typedef union sh_ni0_first_error_1_u { - mmr_t sh_ni0_first_error_1_regval; - struct { - mmr_t tail_timeout_ni_vc3 : 1; - mmr_t tail_timeout_ni_vc2 : 1; - mmr_t tail_timeout_ni_vc1 : 1; - mmr_t tail_timeout_ni_vc0 : 1; - mmr_t tail_timeout_fifo13_vc3 : 1; - mmr_t tail_timeout_fifo13_vc1 : 1; - mmr_t tail_timeout_fifo02_vc2 : 1; - mmr_t tail_timeout_fifo02_vc0 : 1; - mmr_t overflow_ni_fifo_vc3_credit : 1; - mmr_t overflow_ni_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc1_credit : 1; - mmr_t overflow_ni_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_credit : 1; - mmr_t overflow_md_fifo_vc0_credit : 1; - mmr_t overflow_iilb_fifo_vc2_credit : 1; - mmr_t overflow_iilb_fifo_vc0_credit : 1; - mmr_t overflow_pi_fifo_vc2_credit : 1; - mmr_t overflow_pi_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_push : 1; - mmr_t overflow_md_fifo_vc0_push : 1; - mmr_t overflow_iilb_fifo_vc2_push : 1; - mmr_t overflow_iilb_fifo_vc0_push : 1; - mmr_t overflow_pi_fifo_vc2_push : 1; - mmr_t overflow_pi_fifo_vc0_push : 1; - mmr_t overflow_ni_fifo_vc2_pop : 1; - mmr_t overflow_ni_fifo_vc0_pop : 1; - mmr_t overflow_md_fifo_vc2_pop : 1; - mmr_t overflow_md_fifo_vc0_pop : 1; - mmr_t overflow_iilb_fifo_vc2_pop : 1; - mmr_t overflow_iilb_fifo_vc0_pop : 1; - mmr_t overflow_pi_fifo_vc2_pop : 1; - mmr_t overflow_pi_fifo_vc0_pop : 1; - mmr_t overflow_ni_fifo_debit3 : 1; - mmr_t overflow_ni_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit1 : 1; - mmr_t overflow_ni_fifo_debit0 : 1; - mmr_t overflow_md_fifo_debit2 : 1; - mmr_t overflow_md_fifo_debit0 : 1; - mmr_t overflow_iilb_fifo_debit2 : 1; - mmr_t overflow_iilb_fifo_debit0 : 1; - mmr_t overflow_pi_fifo_debit2 : 1; - mmr_t overflow_pi_fifo_debit0 : 1; - mmr_t overflow2_vc2_credit : 1; - mmr_t overflow1_vc2_credit : 1; - mmr_t overflow0_vc2_credit : 1; - mmr_t overflow2_vc0_credit : 1; - mmr_t overflow1_vc0_credit : 1; - mmr_t overflow0_vc0_credit : 1; - mmr_t overflow_fifo13_vc2_credit : 1; - mmr_t overflow_fifo13_vc0_credit : 1; - mmr_t overflow_fifo02_vc2_credit : 1; - mmr_t overflow_fifo02_vc0_credit : 1; - mmr_t overflow_fifo13_vc3_push : 1; - mmr_t overflow_fifo13_vc1_push : 1; - mmr_t overflow_fifo02_vc2_push : 1; - mmr_t overflow_fifo02_vc0_push : 1; - mmr_t overflow_fifo13_vc3_pop : 1; - mmr_t overflow_fifo13_vc1_pop : 1; - mmr_t overflow_fifo02_vc2_pop : 1; - mmr_t overflow_fifo02_vc0_pop : 1; - mmr_t overflow_fifo13_debit2 : 1; - mmr_t overflow_fifo13_debit0 : 1; - mmr_t overflow_fifo02_debit2 : 1; - mmr_t overflow_fifo02_debit0 : 1; - } sh_ni0_first_error_1_s; -} sh_ni0_first_error_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_FIRST_ERROR_2" */ /* ni0 First Error Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_first_error_2_u { mmr_t sh_ni0_first_error_2_regval; struct { @@ -14515,117 +7877,36 @@ typedef union sh_ni0_first_error_2_u { mmr_t reserved_1 : 1; } sh_ni0_first_error_2_s; } sh_ni0_first_error_2_u_t; -#else -typedef union sh_ni0_first_error_2_u { - mmr_t sh_ni0_first_error_2_regval; - struct { - mmr_t reserved_1 : 1; - mmr_t retry_timeout_error : 1; - mmr_t lut_read_error : 1; - mmr_t chiplet_nomatch : 1; - mmr_t llp_deadlock_vc3 : 1; - mmr_t llp_deadlock_vc2 : 1; - mmr_t llp_deadlock_vc1 : 1; - mmr_t llp_deadlock_vc0 : 1; - mmr_t underflow_ni_fifo_vc3_credit : 1; - mmr_t underflow_ni_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc1_credit : 1; - mmr_t underflow_ni_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_credit : 1; - mmr_t underflow_md_fifo_vc0_credit : 1; - mmr_t underflow_iilb_fifo_vc2_credit : 1; - mmr_t underflow_iilb_fifo_vc0_credit : 1; - mmr_t underflow_pi_fifo_vc2_credit : 1; - mmr_t underflow_pi_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_push : 1; - mmr_t underflow_md_fifo_vc0_push : 1; - mmr_t underflow_iilb_fifo_vc2_push : 1; - mmr_t underflow_iilb_fifo_vc0_push : 1; - mmr_t underflow_pi_fifo_vc2_push : 1; - mmr_t underflow_pi_fifo_vc0_push : 1; - mmr_t underflow_ni_fifo_vc2_pop : 1; - mmr_t underflow_ni_fifo_vc0_pop : 1; - mmr_t underflow_md_fifo_vc2_pop : 1; - mmr_t underflow_md_fifo_vc0_pop : 1; - mmr_t underflow_iilb_fifo_vc2_pop : 1; - mmr_t underflow_iilb_fifo_vc0_pop : 1; - mmr_t underflow_pi_fifo_vc2_pop : 1; - mmr_t underflow_pi_fifo_vc0_pop : 1; - mmr_t reserved_0 : 10; - mmr_t underflow2_vc2_credit : 1; - mmr_t underflow1_vc2_credit : 1; - mmr_t underflow0_vc2_credit : 1; - mmr_t underflow2_vc0_credit : 1; - mmr_t underflow1_vc0_credit : 1; - mmr_t underflow0_vc0_credit : 1; - mmr_t underflow_fifo13_vc2_credit : 1; - mmr_t underflow_fifo13_vc0_credit : 1; - mmr_t underflow_fifo02_vc2_credit : 1; - mmr_t underflow_fifo02_vc0_credit : 1; - mmr_t underflow_fifo13_vc3_push : 1; - mmr_t underflow_fifo13_vc1_push : 1; - mmr_t underflow_fifo02_vc2_push : 1; - mmr_t underflow_fifo02_vc0_push : 1; - mmr_t underflow_fifo13_vc3_pop : 1; - mmr_t underflow_fifo13_vc1_pop : 1; - mmr_t underflow_fifo02_vc2_pop : 1; - mmr_t underflow_fifo02_vc0_pop : 1; - mmr_t illegal_vciilb : 1; - mmr_t illegal_vcmd : 1; - mmr_t illegal_vcpi : 1; - mmr_t illegal_vcni : 1; - } sh_ni0_first_error_2_s; -} sh_ni0_first_error_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_ERROR_DETAIL_1" */ /* ni0 Chiplet no match header bits 63:0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_ni0_error_detail_1_u { - mmr_t sh_ni0_error_detail_1_regval; - struct { - mmr_t header : 64; - } sh_ni0_error_detail_1_s; -} sh_ni0_error_detail_1_u_t; -#else typedef union sh_ni0_error_detail_1_u { mmr_t sh_ni0_error_detail_1_regval; struct { mmr_t header : 64; } sh_ni0_error_detail_1_s; } sh_ni0_error_detail_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_ERROR_DETAIL_2" */ /* ni0 Chiplet no match header bits 127:64 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_ni0_error_detail_2_u { - mmr_t sh_ni0_error_detail_2_regval; - struct { - mmr_t header : 64; - } sh_ni0_error_detail_2_s; -} sh_ni0_error_detail_2_u_t; -#else typedef union sh_ni0_error_detail_2_u { mmr_t sh_ni0_error_detail_2_regval; struct { mmr_t header : 64; } sh_ni0_error_detail_2_s; } sh_ni0_error_detail_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_ERROR_SUMMARY_1" */ /* ni1 Error Summary Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_error_summary_1_u { mmr_t sh_ni1_error_summary_1_regval; struct { @@ -14695,84 +7976,12 @@ typedef union sh_ni1_error_summary_1_u { mmr_t tail_timeout_ni_vc3 : 1; } sh_ni1_error_summary_1_s; } sh_ni1_error_summary_1_u_t; -#else -typedef union sh_ni1_error_summary_1_u { - mmr_t sh_ni1_error_summary_1_regval; - struct { - mmr_t tail_timeout_ni_vc3 : 1; - mmr_t tail_timeout_ni_vc2 : 1; - mmr_t tail_timeout_ni_vc1 : 1; - mmr_t tail_timeout_ni_vc0 : 1; - mmr_t tail_timeout_fifo13_vc3 : 1; - mmr_t tail_timeout_fifo13_vc1 : 1; - mmr_t tail_timeout_fifo02_vc2 : 1; - mmr_t tail_timeout_fifo02_vc0 : 1; - mmr_t overflow_ni_fifo_vc3_credit : 1; - mmr_t overflow_ni_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc1_credit : 1; - mmr_t overflow_ni_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_credit : 1; - mmr_t overflow_md_fifo_vc0_credit : 1; - mmr_t overflow_iilb_fifo_vc2_credit : 1; - mmr_t overflow_iilb_fifo_vc0_credit : 1; - mmr_t overflow_pi_fifo_vc2_credit : 1; - mmr_t overflow_pi_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_push : 1; - mmr_t overflow_md_fifo_vc0_push : 1; - mmr_t overflow_iilb_fifo_vc2_push : 1; - mmr_t overflow_iilb_fifo_vc0_push : 1; - mmr_t overflow_pi_fifo_vc2_push : 1; - mmr_t overflow_pi_fifo_vc0_push : 1; - mmr_t overflow_ni_fifo_vc2_pop : 1; - mmr_t overflow_ni_fifo_vc0_pop : 1; - mmr_t overflow_md_fifo_vc2_pop : 1; - mmr_t overflow_md_fifo_vc0_pop : 1; - mmr_t overflow_iilb_fifo_vc2_pop : 1; - mmr_t overflow_iilb_fifo_vc0_pop : 1; - mmr_t overflow_pi_fifo_vc2_pop : 1; - mmr_t overflow_pi_fifo_vc0_pop : 1; - mmr_t overflow_ni_fifo_debit3 : 1; - mmr_t overflow_ni_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit1 : 1; - mmr_t overflow_ni_fifo_debit0 : 1; - mmr_t overflow_md_fifo_debit2 : 1; - mmr_t overflow_md_fifo_debit0 : 1; - mmr_t overflow_iilb_fifo_debit2 : 1; - mmr_t overflow_iilb_fifo_debit0 : 1; - mmr_t overflow_pi_fifo_debit2 : 1; - mmr_t overflow_pi_fifo_debit0 : 1; - mmr_t overflow2_vc2_credit : 1; - mmr_t overflow1_vc2_credit : 1; - mmr_t overflow0_vc2_credit : 1; - mmr_t overflow2_vc0_credit : 1; - mmr_t overflow1_vc0_credit : 1; - mmr_t overflow0_vc0_credit : 1; - mmr_t overflow_fifo13_vc2_credit : 1; - mmr_t overflow_fifo13_vc0_credit : 1; - mmr_t overflow_fifo02_vc2_credit : 1; - mmr_t overflow_fifo02_vc0_credit : 1; - mmr_t overflow_fifo13_vc3_push : 1; - mmr_t overflow_fifo13_vc1_push : 1; - mmr_t overflow_fifo02_vc2_push : 1; - mmr_t overflow_fifo02_vc0_push : 1; - mmr_t overflow_fifo13_vc3_pop : 1; - mmr_t overflow_fifo13_vc1_pop : 1; - mmr_t overflow_fifo02_vc2_pop : 1; - mmr_t overflow_fifo02_vc0_pop : 1; - mmr_t overflow_fifo13_debit2 : 1; - mmr_t overflow_fifo13_debit0 : 1; - mmr_t overflow_fifo02_debit2 : 1; - mmr_t overflow_fifo02_debit0 : 1; - } sh_ni1_error_summary_1_s; -} sh_ni1_error_summary_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_ERROR_SUMMARY_2" */ /* ni1 Error Summary Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_error_summary_2_u { mmr_t sh_ni1_error_summary_2_regval; struct { @@ -14833,75 +8042,12 @@ typedef union sh_ni1_error_summary_2_u { mmr_t reserved_1 : 1; } sh_ni1_error_summary_2_s; } sh_ni1_error_summary_2_u_t; -#else -typedef union sh_ni1_error_summary_2_u { - mmr_t sh_ni1_error_summary_2_regval; - struct { - mmr_t reserved_1 : 1; - mmr_t retry_timeout_error : 1; - mmr_t lut_read_error : 1; - mmr_t chiplet_nomatch : 1; - mmr_t llp_deadlock_vc3 : 1; - mmr_t llp_deadlock_vc2 : 1; - mmr_t llp_deadlock_vc1 : 1; - mmr_t llp_deadlock_vc0 : 1; - mmr_t underflow_ni_fifo_vc3_credit : 1; - mmr_t underflow_ni_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc1_credit : 1; - mmr_t underflow_ni_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_credit : 1; - mmr_t underflow_md_fifo_vc0_credit : 1; - mmr_t underflow_iilb_fifo_vc2_credit : 1; - mmr_t underflow_iilb_fifo_vc0_credit : 1; - mmr_t underflow_pi_fifo_vc2_credit : 1; - mmr_t underflow_pi_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_push : 1; - mmr_t underflow_md_fifo_vc0_push : 1; - mmr_t underflow_iilb_fifo_vc2_push : 1; - mmr_t underflow_iilb_fifo_vc0_push : 1; - mmr_t underflow_pi_fifo_vc2_push : 1; - mmr_t underflow_pi_fifo_vc0_push : 1; - mmr_t underflow_ni_fifo_vc2_pop : 1; - mmr_t underflow_ni_fifo_vc0_pop : 1; - mmr_t underflow_md_fifo_vc2_pop : 1; - mmr_t underflow_md_fifo_vc0_pop : 1; - mmr_t underflow_iilb_fifo_vc2_pop : 1; - mmr_t underflow_iilb_fifo_vc0_pop : 1; - mmr_t underflow_pi_fifo_vc2_pop : 1; - mmr_t underflow_pi_fifo_vc0_pop : 1; - mmr_t reserved_0 : 10; - mmr_t underflow2_vc2_credit : 1; - mmr_t underflow1_vc2_credit : 1; - mmr_t underflow0_vc2_credit : 1; - mmr_t underflow2_vc0_credit : 1; - mmr_t underflow1_vc0_credit : 1; - mmr_t underflow0_vc0_credit : 1; - mmr_t underflow_fifo13_vc2_credit : 1; - mmr_t underflow_fifo13_vc0_credit : 1; - mmr_t underflow_fifo02_vc2_credit : 1; - mmr_t underflow_fifo02_vc0_credit : 1; - mmr_t underflow_fifo13_vc3_push : 1; - mmr_t underflow_fifo13_vc1_push : 1; - mmr_t underflow_fifo02_vc2_push : 1; - mmr_t underflow_fifo02_vc0_push : 1; - mmr_t underflow_fifo13_vc3_pop : 1; - mmr_t underflow_fifo13_vc1_pop : 1; - mmr_t underflow_fifo02_vc2_pop : 1; - mmr_t underflow_fifo02_vc0_pop : 1; - mmr_t illegal_vciilb : 1; - mmr_t illegal_vcmd : 1; - mmr_t illegal_vcpi : 1; - mmr_t illegal_vcni : 1; - } sh_ni1_error_summary_2_s; -} sh_ni1_error_summary_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_ERROR_OVERFLOW_1" */ /* ni1 Error Overflow Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_error_overflow_1_u { mmr_t sh_ni1_error_overflow_1_regval; struct { @@ -14971,84 +8117,12 @@ typedef union sh_ni1_error_overflow_1_u { mmr_t tail_timeout_ni_vc3 : 1; } sh_ni1_error_overflow_1_s; } sh_ni1_error_overflow_1_u_t; -#else -typedef union sh_ni1_error_overflow_1_u { - mmr_t sh_ni1_error_overflow_1_regval; - struct { - mmr_t tail_timeout_ni_vc3 : 1; - mmr_t tail_timeout_ni_vc2 : 1; - mmr_t tail_timeout_ni_vc1 : 1; - mmr_t tail_timeout_ni_vc0 : 1; - mmr_t tail_timeout_fifo13_vc3 : 1; - mmr_t tail_timeout_fifo13_vc1 : 1; - mmr_t tail_timeout_fifo02_vc2 : 1; - mmr_t tail_timeout_fifo02_vc0 : 1; - mmr_t overflow_ni_fifo_vc3_credit : 1; - mmr_t overflow_ni_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc1_credit : 1; - mmr_t overflow_ni_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_credit : 1; - mmr_t overflow_md_fifo_vc0_credit : 1; - mmr_t overflow_iilb_fifo_vc2_credit : 1; - mmr_t overflow_iilb_fifo_vc0_credit : 1; - mmr_t overflow_pi_fifo_vc2_credit : 1; - mmr_t overflow_pi_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_push : 1; - mmr_t overflow_md_fifo_vc0_push : 1; - mmr_t overflow_iilb_fifo_vc2_push : 1; - mmr_t overflow_iilb_fifo_vc0_push : 1; - mmr_t overflow_pi_fifo_vc2_push : 1; - mmr_t overflow_pi_fifo_vc0_push : 1; - mmr_t overflow_ni_fifo_vc2_pop : 1; - mmr_t overflow_ni_fifo_vc0_pop : 1; - mmr_t overflow_md_fifo_vc2_pop : 1; - mmr_t overflow_md_fifo_vc0_pop : 1; - mmr_t overflow_iilb_fifo_vc2_pop : 1; - mmr_t overflow_iilb_fifo_vc0_pop : 1; - mmr_t overflow_pi_fifo_vc2_pop : 1; - mmr_t overflow_pi_fifo_vc0_pop : 1; - mmr_t overflow_ni_fifo_debit3 : 1; - mmr_t overflow_ni_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit1 : 1; - mmr_t overflow_ni_fifo_debit0 : 1; - mmr_t overflow_md_fifo_debit2 : 1; - mmr_t overflow_md_fifo_debit0 : 1; - mmr_t overflow_iilb_fifo_debit2 : 1; - mmr_t overflow_iilb_fifo_debit0 : 1; - mmr_t overflow_pi_fifo_debit2 : 1; - mmr_t overflow_pi_fifo_debit0 : 1; - mmr_t overflow2_vc2_credit : 1; - mmr_t overflow1_vc2_credit : 1; - mmr_t overflow0_vc2_credit : 1; - mmr_t overflow2_vc0_credit : 1; - mmr_t overflow1_vc0_credit : 1; - mmr_t overflow0_vc0_credit : 1; - mmr_t overflow_fifo13_vc2_credit : 1; - mmr_t overflow_fifo13_vc0_credit : 1; - mmr_t overflow_fifo02_vc2_credit : 1; - mmr_t overflow_fifo02_vc0_credit : 1; - mmr_t overflow_fifo13_vc3_push : 1; - mmr_t overflow_fifo13_vc1_push : 1; - mmr_t overflow_fifo02_vc2_push : 1; - mmr_t overflow_fifo02_vc0_push : 1; - mmr_t overflow_fifo13_vc3_pop : 1; - mmr_t overflow_fifo13_vc1_pop : 1; - mmr_t overflow_fifo02_vc2_pop : 1; - mmr_t overflow_fifo02_vc0_pop : 1; - mmr_t overflow_fifo13_debit2 : 1; - mmr_t overflow_fifo13_debit0 : 1; - mmr_t overflow_fifo02_debit2 : 1; - mmr_t overflow_fifo02_debit0 : 1; - } sh_ni1_error_overflow_1_s; -} sh_ni1_error_overflow_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_ERROR_OVERFLOW_2" */ /* ni1 Error Overflow Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_error_overflow_2_u { mmr_t sh_ni1_error_overflow_2_regval; struct { @@ -15109,75 +8183,12 @@ typedef union sh_ni1_error_overflow_2_u { mmr_t reserved_1 : 1; } sh_ni1_error_overflow_2_s; } sh_ni1_error_overflow_2_u_t; -#else -typedef union sh_ni1_error_overflow_2_u { - mmr_t sh_ni1_error_overflow_2_regval; - struct { - mmr_t reserved_1 : 1; - mmr_t retry_timeout_error : 1; - mmr_t lut_read_error : 1; - mmr_t chiplet_nomatch : 1; - mmr_t llp_deadlock_vc3 : 1; - mmr_t llp_deadlock_vc2 : 1; - mmr_t llp_deadlock_vc1 : 1; - mmr_t llp_deadlock_vc0 : 1; - mmr_t underflow_ni_fifo_vc3_credit : 1; - mmr_t underflow_ni_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc1_credit : 1; - mmr_t underflow_ni_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_credit : 1; - mmr_t underflow_md_fifo_vc0_credit : 1; - mmr_t underflow_iilb_fifo_vc2_credit : 1; - mmr_t underflow_iilb_fifo_vc0_credit : 1; - mmr_t underflow_pi_fifo_vc2_credit : 1; - mmr_t underflow_pi_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_push : 1; - mmr_t underflow_md_fifo_vc0_push : 1; - mmr_t underflow_iilb_fifo_vc2_push : 1; - mmr_t underflow_iilb_fifo_vc0_push : 1; - mmr_t underflow_pi_fifo_vc2_push : 1; - mmr_t underflow_pi_fifo_vc0_push : 1; - mmr_t underflow_ni_fifo_vc2_pop : 1; - mmr_t underflow_ni_fifo_vc0_pop : 1; - mmr_t underflow_md_fifo_vc2_pop : 1; - mmr_t underflow_md_fifo_vc0_pop : 1; - mmr_t underflow_iilb_fifo_vc2_pop : 1; - mmr_t underflow_iilb_fifo_vc0_pop : 1; - mmr_t underflow_pi_fifo_vc2_pop : 1; - mmr_t underflow_pi_fifo_vc0_pop : 1; - mmr_t reserved_0 : 10; - mmr_t underflow2_vc2_credit : 1; - mmr_t underflow1_vc2_credit : 1; - mmr_t underflow0_vc2_credit : 1; - mmr_t underflow2_vc0_credit : 1; - mmr_t underflow1_vc0_credit : 1; - mmr_t underflow0_vc0_credit : 1; - mmr_t underflow_fifo13_vc2_credit : 1; - mmr_t underflow_fifo13_vc0_credit : 1; - mmr_t underflow_fifo02_vc2_credit : 1; - mmr_t underflow_fifo02_vc0_credit : 1; - mmr_t underflow_fifo13_vc3_push : 1; - mmr_t underflow_fifo13_vc1_push : 1; - mmr_t underflow_fifo02_vc2_push : 1; - mmr_t underflow_fifo02_vc0_push : 1; - mmr_t underflow_fifo13_vc3_pop : 1; - mmr_t underflow_fifo13_vc1_pop : 1; - mmr_t underflow_fifo02_vc2_pop : 1; - mmr_t underflow_fifo02_vc0_pop : 1; - mmr_t illegal_vciilb : 1; - mmr_t illegal_vcmd : 1; - mmr_t illegal_vcpi : 1; - mmr_t illegal_vcni : 1; - } sh_ni1_error_overflow_2_s; -} sh_ni1_error_overflow_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_ERROR_MASK_1" */ /* ni1 Error Mask Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_error_mask_1_u { mmr_t sh_ni1_error_mask_1_regval; struct { @@ -15247,84 +8258,12 @@ typedef union sh_ni1_error_mask_1_u { mmr_t tail_timeout_ni_vc3 : 1; } sh_ni1_error_mask_1_s; } sh_ni1_error_mask_1_u_t; -#else -typedef union sh_ni1_error_mask_1_u { - mmr_t sh_ni1_error_mask_1_regval; - struct { - mmr_t tail_timeout_ni_vc3 : 1; - mmr_t tail_timeout_ni_vc2 : 1; - mmr_t tail_timeout_ni_vc1 : 1; - mmr_t tail_timeout_ni_vc0 : 1; - mmr_t tail_timeout_fifo13_vc3 : 1; - mmr_t tail_timeout_fifo13_vc1 : 1; - mmr_t tail_timeout_fifo02_vc2 : 1; - mmr_t tail_timeout_fifo02_vc0 : 1; - mmr_t overflow_ni_fifo_vc3_credit : 1; - mmr_t overflow_ni_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc1_credit : 1; - mmr_t overflow_ni_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_credit : 1; - mmr_t overflow_md_fifo_vc0_credit : 1; - mmr_t overflow_iilb_fifo_vc2_credit : 1; - mmr_t overflow_iilb_fifo_vc0_credit : 1; - mmr_t overflow_pi_fifo_vc2_credit : 1; - mmr_t overflow_pi_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_push : 1; - mmr_t overflow_md_fifo_vc0_push : 1; - mmr_t overflow_iilb_fifo_vc2_push : 1; - mmr_t overflow_iilb_fifo_vc0_push : 1; - mmr_t overflow_pi_fifo_vc2_push : 1; - mmr_t overflow_pi_fifo_vc0_push : 1; - mmr_t overflow_ni_fifo_vc2_pop : 1; - mmr_t overflow_ni_fifo_vc0_pop : 1; - mmr_t overflow_md_fifo_vc2_pop : 1; - mmr_t overflow_md_fifo_vc0_pop : 1; - mmr_t overflow_iilb_fifo_vc2_pop : 1; - mmr_t overflow_iilb_fifo_vc0_pop : 1; - mmr_t overflow_pi_fifo_vc2_pop : 1; - mmr_t overflow_pi_fifo_vc0_pop : 1; - mmr_t overflow_ni_fifo_debit3 : 1; - mmr_t overflow_ni_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit1 : 1; - mmr_t overflow_ni_fifo_debit0 : 1; - mmr_t overflow_md_fifo_debit2 : 1; - mmr_t overflow_md_fifo_debit0 : 1; - mmr_t overflow_iilb_fifo_debit2 : 1; - mmr_t overflow_iilb_fifo_debit0 : 1; - mmr_t overflow_pi_fifo_debit2 : 1; - mmr_t overflow_pi_fifo_debit0 : 1; - mmr_t overflow2_vc2_credit : 1; - mmr_t overflow1_vc2_credit : 1; - mmr_t overflow0_vc2_credit : 1; - mmr_t overflow2_vc0_credit : 1; - mmr_t overflow1_vc0_credit : 1; - mmr_t overflow0_vc0_credit : 1; - mmr_t overflow_fifo13_vc2_credit : 1; - mmr_t overflow_fifo13_vc0_credit : 1; - mmr_t overflow_fifo02_vc2_credit : 1; - mmr_t overflow_fifo02_vc0_credit : 1; - mmr_t overflow_fifo13_vc3_push : 1; - mmr_t overflow_fifo13_vc1_push : 1; - mmr_t overflow_fifo02_vc2_push : 1; - mmr_t overflow_fifo02_vc0_push : 1; - mmr_t overflow_fifo13_vc3_pop : 1; - mmr_t overflow_fifo13_vc1_pop : 1; - mmr_t overflow_fifo02_vc2_pop : 1; - mmr_t overflow_fifo02_vc0_pop : 1; - mmr_t overflow_fifo13_debit2 : 1; - mmr_t overflow_fifo13_debit0 : 1; - mmr_t overflow_fifo02_debit2 : 1; - mmr_t overflow_fifo02_debit0 : 1; - } sh_ni1_error_mask_1_s; -} sh_ni1_error_mask_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_ERROR_MASK_2" */ /* ni1 Error Mask Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_error_mask_2_u { mmr_t sh_ni1_error_mask_2_regval; struct { @@ -15385,75 +8324,12 @@ typedef union sh_ni1_error_mask_2_u { mmr_t reserved_1 : 1; } sh_ni1_error_mask_2_s; } sh_ni1_error_mask_2_u_t; -#else -typedef union sh_ni1_error_mask_2_u { - mmr_t sh_ni1_error_mask_2_regval; - struct { - mmr_t reserved_1 : 1; - mmr_t retry_timeout_error : 1; - mmr_t lut_read_error : 1; - mmr_t chiplet_nomatch : 1; - mmr_t llp_deadlock_vc3 : 1; - mmr_t llp_deadlock_vc2 : 1; - mmr_t llp_deadlock_vc1 : 1; - mmr_t llp_deadlock_vc0 : 1; - mmr_t underflow_ni_fifo_vc3_credit : 1; - mmr_t underflow_ni_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc1_credit : 1; - mmr_t underflow_ni_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_credit : 1; - mmr_t underflow_md_fifo_vc0_credit : 1; - mmr_t underflow_iilb_fifo_vc2_credit : 1; - mmr_t underflow_iilb_fifo_vc0_credit : 1; - mmr_t underflow_pi_fifo_vc2_credit : 1; - mmr_t underflow_pi_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_push : 1; - mmr_t underflow_md_fifo_vc0_push : 1; - mmr_t underflow_iilb_fifo_vc2_push : 1; - mmr_t underflow_iilb_fifo_vc0_push : 1; - mmr_t underflow_pi_fifo_vc2_push : 1; - mmr_t underflow_pi_fifo_vc0_push : 1; - mmr_t underflow_ni_fifo_vc2_pop : 1; - mmr_t underflow_ni_fifo_vc0_pop : 1; - mmr_t underflow_md_fifo_vc2_pop : 1; - mmr_t underflow_md_fifo_vc0_pop : 1; - mmr_t underflow_iilb_fifo_vc2_pop : 1; - mmr_t underflow_iilb_fifo_vc0_pop : 1; - mmr_t underflow_pi_fifo_vc2_pop : 1; - mmr_t underflow_pi_fifo_vc0_pop : 1; - mmr_t reserved_0 : 10; - mmr_t underflow2_vc2_credit : 1; - mmr_t underflow1_vc2_credit : 1; - mmr_t underflow0_vc2_credit : 1; - mmr_t underflow2_vc0_credit : 1; - mmr_t underflow1_vc0_credit : 1; - mmr_t underflow0_vc0_credit : 1; - mmr_t underflow_fifo13_vc2_credit : 1; - mmr_t underflow_fifo13_vc0_credit : 1; - mmr_t underflow_fifo02_vc2_credit : 1; - mmr_t underflow_fifo02_vc0_credit : 1; - mmr_t underflow_fifo13_vc3_push : 1; - mmr_t underflow_fifo13_vc1_push : 1; - mmr_t underflow_fifo02_vc2_push : 1; - mmr_t underflow_fifo02_vc0_push : 1; - mmr_t underflow_fifo13_vc3_pop : 1; - mmr_t underflow_fifo13_vc1_pop : 1; - mmr_t underflow_fifo02_vc2_pop : 1; - mmr_t underflow_fifo02_vc0_pop : 1; - mmr_t illegal_vciilb : 1; - mmr_t illegal_vcmd : 1; - mmr_t illegal_vcpi : 1; - mmr_t illegal_vcni : 1; - } sh_ni1_error_mask_2_s; -} sh_ni1_error_mask_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_FIRST_ERROR_1" */ /* ni1 First Error Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_first_error_1_u { mmr_t sh_ni1_first_error_1_regval; struct { @@ -15523,84 +8399,12 @@ typedef union sh_ni1_first_error_1_u { mmr_t tail_timeout_ni_vc3 : 1; } sh_ni1_first_error_1_s; } sh_ni1_first_error_1_u_t; -#else -typedef union sh_ni1_first_error_1_u { - mmr_t sh_ni1_first_error_1_regval; - struct { - mmr_t tail_timeout_ni_vc3 : 1; - mmr_t tail_timeout_ni_vc2 : 1; - mmr_t tail_timeout_ni_vc1 : 1; - mmr_t tail_timeout_ni_vc0 : 1; - mmr_t tail_timeout_fifo13_vc3 : 1; - mmr_t tail_timeout_fifo13_vc1 : 1; - mmr_t tail_timeout_fifo02_vc2 : 1; - mmr_t tail_timeout_fifo02_vc0 : 1; - mmr_t overflow_ni_fifo_vc3_credit : 1; - mmr_t overflow_ni_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc1_credit : 1; - mmr_t overflow_ni_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_credit : 1; - mmr_t overflow_md_fifo_vc0_credit : 1; - mmr_t overflow_iilb_fifo_vc2_credit : 1; - mmr_t overflow_iilb_fifo_vc0_credit : 1; - mmr_t overflow_pi_fifo_vc2_credit : 1; - mmr_t overflow_pi_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_push : 1; - mmr_t overflow_md_fifo_vc0_push : 1; - mmr_t overflow_iilb_fifo_vc2_push : 1; - mmr_t overflow_iilb_fifo_vc0_push : 1; - mmr_t overflow_pi_fifo_vc2_push : 1; - mmr_t overflow_pi_fifo_vc0_push : 1; - mmr_t overflow_ni_fifo_vc2_pop : 1; - mmr_t overflow_ni_fifo_vc0_pop : 1; - mmr_t overflow_md_fifo_vc2_pop : 1; - mmr_t overflow_md_fifo_vc0_pop : 1; - mmr_t overflow_iilb_fifo_vc2_pop : 1; - mmr_t overflow_iilb_fifo_vc0_pop : 1; - mmr_t overflow_pi_fifo_vc2_pop : 1; - mmr_t overflow_pi_fifo_vc0_pop : 1; - mmr_t overflow_ni_fifo_debit3 : 1; - mmr_t overflow_ni_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit1 : 1; - mmr_t overflow_ni_fifo_debit0 : 1; - mmr_t overflow_md_fifo_debit2 : 1; - mmr_t overflow_md_fifo_debit0 : 1; - mmr_t overflow_iilb_fifo_debit2 : 1; - mmr_t overflow_iilb_fifo_debit0 : 1; - mmr_t overflow_pi_fifo_debit2 : 1; - mmr_t overflow_pi_fifo_debit0 : 1; - mmr_t overflow2_vc2_credit : 1; - mmr_t overflow1_vc2_credit : 1; - mmr_t overflow0_vc2_credit : 1; - mmr_t overflow2_vc0_credit : 1; - mmr_t overflow1_vc0_credit : 1; - mmr_t overflow0_vc0_credit : 1; - mmr_t overflow_fifo13_vc2_credit : 1; - mmr_t overflow_fifo13_vc0_credit : 1; - mmr_t overflow_fifo02_vc2_credit : 1; - mmr_t overflow_fifo02_vc0_credit : 1; - mmr_t overflow_fifo13_vc3_push : 1; - mmr_t overflow_fifo13_vc1_push : 1; - mmr_t overflow_fifo02_vc2_push : 1; - mmr_t overflow_fifo02_vc0_push : 1; - mmr_t overflow_fifo13_vc3_pop : 1; - mmr_t overflow_fifo13_vc1_pop : 1; - mmr_t overflow_fifo02_vc2_pop : 1; - mmr_t overflow_fifo02_vc0_pop : 1; - mmr_t overflow_fifo13_debit2 : 1; - mmr_t overflow_fifo13_debit0 : 1; - mmr_t overflow_fifo02_debit2 : 1; - mmr_t overflow_fifo02_debit0 : 1; - } sh_ni1_first_error_1_s; -} sh_ni1_first_error_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_FIRST_ERROR_2" */ /* ni1 First Error Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_first_error_2_u { mmr_t sh_ni1_first_error_2_regval; struct { @@ -15661,117 +8465,36 @@ typedef union sh_ni1_first_error_2_u { mmr_t reserved_1 : 1; } sh_ni1_first_error_2_s; } sh_ni1_first_error_2_u_t; -#else -typedef union sh_ni1_first_error_2_u { - mmr_t sh_ni1_first_error_2_regval; - struct { - mmr_t reserved_1 : 1; - mmr_t retry_timeout_error : 1; - mmr_t lut_read_error : 1; - mmr_t chiplet_nomatch : 1; - mmr_t llp_deadlock_vc3 : 1; - mmr_t llp_deadlock_vc2 : 1; - mmr_t llp_deadlock_vc1 : 1; - mmr_t llp_deadlock_vc0 : 1; - mmr_t underflow_ni_fifo_vc3_credit : 1; - mmr_t underflow_ni_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc1_credit : 1; - mmr_t underflow_ni_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_credit : 1; - mmr_t underflow_md_fifo_vc0_credit : 1; - mmr_t underflow_iilb_fifo_vc2_credit : 1; - mmr_t underflow_iilb_fifo_vc0_credit : 1; - mmr_t underflow_pi_fifo_vc2_credit : 1; - mmr_t underflow_pi_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_push : 1; - mmr_t underflow_md_fifo_vc0_push : 1; - mmr_t underflow_iilb_fifo_vc2_push : 1; - mmr_t underflow_iilb_fifo_vc0_push : 1; - mmr_t underflow_pi_fifo_vc2_push : 1; - mmr_t underflow_pi_fifo_vc0_push : 1; - mmr_t underflow_ni_fifo_vc2_pop : 1; - mmr_t underflow_ni_fifo_vc0_pop : 1; - mmr_t underflow_md_fifo_vc2_pop : 1; - mmr_t underflow_md_fifo_vc0_pop : 1; - mmr_t underflow_iilb_fifo_vc2_pop : 1; - mmr_t underflow_iilb_fifo_vc0_pop : 1; - mmr_t underflow_pi_fifo_vc2_pop : 1; - mmr_t underflow_pi_fifo_vc0_pop : 1; - mmr_t reserved_0 : 10; - mmr_t underflow2_vc2_credit : 1; - mmr_t underflow1_vc2_credit : 1; - mmr_t underflow0_vc2_credit : 1; - mmr_t underflow2_vc0_credit : 1; - mmr_t underflow1_vc0_credit : 1; - mmr_t underflow0_vc0_credit : 1; - mmr_t underflow_fifo13_vc2_credit : 1; - mmr_t underflow_fifo13_vc0_credit : 1; - mmr_t underflow_fifo02_vc2_credit : 1; - mmr_t underflow_fifo02_vc0_credit : 1; - mmr_t underflow_fifo13_vc3_push : 1; - mmr_t underflow_fifo13_vc1_push : 1; - mmr_t underflow_fifo02_vc2_push : 1; - mmr_t underflow_fifo02_vc0_push : 1; - mmr_t underflow_fifo13_vc3_pop : 1; - mmr_t underflow_fifo13_vc1_pop : 1; - mmr_t underflow_fifo02_vc2_pop : 1; - mmr_t underflow_fifo02_vc0_pop : 1; - mmr_t illegal_vciilb : 1; - mmr_t illegal_vcmd : 1; - mmr_t illegal_vcpi : 1; - mmr_t illegal_vcni : 1; - } sh_ni1_first_error_2_s; -} sh_ni1_first_error_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_ERROR_DETAIL_1" */ /* ni1 Chiplet no match header bits 63:0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_error_detail_1_u { mmr_t sh_ni1_error_detail_1_regval; struct { mmr_t header : 64; } sh_ni1_error_detail_1_s; } sh_ni1_error_detail_1_u_t; -#else -typedef union sh_ni1_error_detail_1_u { - mmr_t sh_ni1_error_detail_1_regval; - struct { - mmr_t header : 64; - } sh_ni1_error_detail_1_s; -} sh_ni1_error_detail_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_ERROR_DETAIL_2" */ /* ni1 Chiplet no match header bits 127:64 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_ni1_error_detail_2_u { - mmr_t sh_ni1_error_detail_2_regval; - struct { - mmr_t header : 64; - } sh_ni1_error_detail_2_s; -} sh_ni1_error_detail_2_u_t; -#else typedef union sh_ni1_error_detail_2_u { mmr_t sh_ni1_error_detail_2_regval; struct { mmr_t header : 64; } sh_ni1_error_detail_2_s; } sh_ni1_error_detail_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_CORRECTED_DETAIL_1" */ /* Corrected error details */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_corrected_detail_1_u { mmr_t sh_xn_corrected_detail_1_regval; struct { @@ -15793,78 +8516,36 @@ typedef union sh_xn_corrected_detail_1_u { mmr_t reserved_3 : 4; } sh_xn_corrected_detail_1_s; } sh_xn_corrected_detail_1_u_t; -#else -typedef union sh_xn_corrected_detail_1_u { - mmr_t sh_xn_corrected_detail_1_regval; - struct { - mmr_t reserved_3 : 4; - mmr_t ecc3_vc : 2; - mmr_t ecc3_wc : 2; - mmr_t ecc3_syndrome : 8; - mmr_t reserved_2 : 4; - mmr_t ecc2_vc : 2; - mmr_t ecc2_wc : 2; - mmr_t ecc2_syndrome : 8; - mmr_t reserved_1 : 4; - mmr_t ecc1_vc : 2; - mmr_t ecc1_wc : 2; - mmr_t ecc1_syndrome : 8; - mmr_t reserved_0 : 4; - mmr_t ecc0_vc : 2; - mmr_t ecc0_wc : 2; - mmr_t ecc0_syndrome : 8; - } sh_xn_corrected_detail_1_s; -} sh_xn_corrected_detail_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_CORRECTED_DETAIL_2" */ /* Corrected error data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_corrected_detail_2_u { - mmr_t sh_xn_corrected_detail_2_regval; - struct { - mmr_t data : 64; - } sh_xn_corrected_detail_2_s; -} sh_xn_corrected_detail_2_u_t; -#else typedef union sh_xn_corrected_detail_2_u { mmr_t sh_xn_corrected_detail_2_regval; struct { mmr_t data : 64; } sh_xn_corrected_detail_2_s; } sh_xn_corrected_detail_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_CORRECTED_DETAIL_3" */ /* Corrected error header0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_corrected_detail_3_u { mmr_t sh_xn_corrected_detail_3_regval; struct { mmr_t header0 : 64; } sh_xn_corrected_detail_3_s; } sh_xn_corrected_detail_3_u_t; -#else -typedef union sh_xn_corrected_detail_3_u { - mmr_t sh_xn_corrected_detail_3_regval; - struct { - mmr_t header0 : 64; - } sh_xn_corrected_detail_3_s; -} sh_xn_corrected_detail_3_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_CORRECTED_DETAIL_4" */ /* Corrected error header1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_corrected_detail_4_u { mmr_t sh_xn_corrected_detail_4_regval; struct { @@ -15873,23 +8554,12 @@ typedef union sh_xn_corrected_detail_4_u { mmr_t err_group : 2; } sh_xn_corrected_detail_4_s; } sh_xn_corrected_detail_4_u_t; -#else -typedef union sh_xn_corrected_detail_4_u { - mmr_t sh_xn_corrected_detail_4_regval; - struct { - mmr_t err_group : 2; - mmr_t reserved_0 : 20; - mmr_t header1 : 42; - } sh_xn_corrected_detail_4_s; -} sh_xn_corrected_detail_4_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_UNCORRECTED_DETAIL_1" */ /* Uncorrected error details */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_uncorrected_detail_1_u { mmr_t sh_xn_uncorrected_detail_1_regval; struct { @@ -15911,78 +8581,36 @@ typedef union sh_xn_uncorrected_detail_1_u { mmr_t reserved_3 : 4; } sh_xn_uncorrected_detail_1_s; } sh_xn_uncorrected_detail_1_u_t; -#else -typedef union sh_xn_uncorrected_detail_1_u { - mmr_t sh_xn_uncorrected_detail_1_regval; - struct { - mmr_t reserved_3 : 4; - mmr_t ecc3_vc : 2; - mmr_t ecc3_wc : 2; - mmr_t ecc3_syndrome : 8; - mmr_t reserved_2 : 4; - mmr_t ecc2_vc : 2; - mmr_t ecc2_wc : 2; - mmr_t ecc2_syndrome : 8; - mmr_t reserved_1 : 4; - mmr_t ecc1_vc : 2; - mmr_t ecc1_wc : 2; - mmr_t ecc1_syndrome : 8; - mmr_t reserved_0 : 4; - mmr_t ecc0_vc : 2; - mmr_t ecc0_wc : 2; - mmr_t ecc0_syndrome : 8; - } sh_xn_uncorrected_detail_1_s; -} sh_xn_uncorrected_detail_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_UNCORRECTED_DETAIL_2" */ /* Uncorrected error data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_uncorrected_detail_2_u { - mmr_t sh_xn_uncorrected_detail_2_regval; - struct { - mmr_t data : 64; - } sh_xn_uncorrected_detail_2_s; -} sh_xn_uncorrected_detail_2_u_t; -#else typedef union sh_xn_uncorrected_detail_2_u { mmr_t sh_xn_uncorrected_detail_2_regval; struct { mmr_t data : 64; } sh_xn_uncorrected_detail_2_s; } sh_xn_uncorrected_detail_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_UNCORRECTED_DETAIL_3" */ /* Uncorrected error header0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_uncorrected_detail_3_u { mmr_t sh_xn_uncorrected_detail_3_regval; struct { mmr_t header0 : 64; } sh_xn_uncorrected_detail_3_s; } sh_xn_uncorrected_detail_3_u_t; -#else -typedef union sh_xn_uncorrected_detail_3_u { - mmr_t sh_xn_uncorrected_detail_3_regval; - struct { - mmr_t header0 : 64; - } sh_xn_uncorrected_detail_3_s; -} sh_xn_uncorrected_detail_3_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_UNCORRECTED_DETAIL_4" */ /* Uncorrected error header1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_uncorrected_detail_4_u { mmr_t sh_xn_uncorrected_detail_4_regval; struct { @@ -15991,23 +8619,12 @@ typedef union sh_xn_uncorrected_detail_4_u { mmr_t err_group : 2; } sh_xn_uncorrected_detail_4_s; } sh_xn_uncorrected_detail_4_u_t; -#else -typedef union sh_xn_uncorrected_detail_4_u { - mmr_t sh_xn_uncorrected_detail_4_regval; - struct { - mmr_t err_group : 2; - mmr_t reserved_0 : 20; - mmr_t header1 : 42; - } sh_xn_uncorrected_detail_4_s; -} sh_xn_uncorrected_detail_4_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_ERROR_DETAIL_1" */ /* Look Up Table Address (md) */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnmd_error_detail_1_u { mmr_t sh_xnmd_error_detail_1_regval; struct { @@ -16015,22 +8632,12 @@ typedef union sh_xnmd_error_detail_1_u { mmr_t reserved_0 : 53; } sh_xnmd_error_detail_1_s; } sh_xnmd_error_detail_1_u_t; -#else -typedef union sh_xnmd_error_detail_1_u { - mmr_t sh_xnmd_error_detail_1_regval; - struct { - mmr_t reserved_0 : 53; - mmr_t lut_addr : 11; - } sh_xnmd_error_detail_1_s; -} sh_xnmd_error_detail_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_ERROR_DETAIL_1" */ /* Look Up Table Address (pi) */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnpi_error_detail_1_u { mmr_t sh_xnpi_error_detail_1_regval; struct { @@ -16038,64 +8645,36 @@ typedef union sh_xnpi_error_detail_1_u { mmr_t reserved_0 : 53; } sh_xnpi_error_detail_1_s; } sh_xnpi_error_detail_1_u_t; -#else -typedef union sh_xnpi_error_detail_1_u { - mmr_t sh_xnpi_error_detail_1_regval; - struct { - mmr_t reserved_0 : 53; - mmr_t lut_addr : 11; - } sh_xnpi_error_detail_1_s; -} sh_xnpi_error_detail_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_ERROR_DETAIL_1" */ /* Chiplet NoMatch header [63:0] */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xniilb_error_detail_1_u { - mmr_t sh_xniilb_error_detail_1_regval; - struct { - mmr_t header : 64; - } sh_xniilb_error_detail_1_s; -} sh_xniilb_error_detail_1_u_t; -#else typedef union sh_xniilb_error_detail_1_u { mmr_t sh_xniilb_error_detail_1_regval; struct { mmr_t header : 64; } sh_xniilb_error_detail_1_s; } sh_xniilb_error_detail_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_ERROR_DETAIL_2" */ /* Chiplet NoMatch header [127:64] */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xniilb_error_detail_2_u { - mmr_t sh_xniilb_error_detail_2_regval; - struct { - mmr_t header : 64; - } sh_xniilb_error_detail_2_s; -} sh_xniilb_error_detail_2_u_t; -#else typedef union sh_xniilb_error_detail_2_u { mmr_t sh_xniilb_error_detail_2_regval; struct { mmr_t header : 64; } sh_xniilb_error_detail_2_s; } sh_xniilb_error_detail_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_ERROR_DETAIL_3" */ /* Look Up Table Address (iilb) */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xniilb_error_detail_3_u { mmr_t sh_xniilb_error_detail_3_regval; struct { @@ -16103,22 +8682,12 @@ typedef union sh_xniilb_error_detail_3_u { mmr_t reserved_0 : 53; } sh_xniilb_error_detail_3_s; } sh_xniilb_error_detail_3_u_t; -#else -typedef union sh_xniilb_error_detail_3_u { - mmr_t sh_xniilb_error_detail_3_regval; - struct { - mmr_t reserved_0 : 53; - mmr_t lut_addr : 11; - } sh_xniilb_error_detail_3_s; -} sh_xniilb_error_detail_3_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_ERROR_DETAIL_3" */ /* Look Up Table Address (ni0) */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_error_detail_3_u { mmr_t sh_ni0_error_detail_3_regval; struct { @@ -16126,22 +8695,12 @@ typedef union sh_ni0_error_detail_3_u { mmr_t reserved_0 : 53; } sh_ni0_error_detail_3_s; } sh_ni0_error_detail_3_u_t; -#else -typedef union sh_ni0_error_detail_3_u { - mmr_t sh_ni0_error_detail_3_regval; - struct { - mmr_t reserved_0 : 53; - mmr_t lut_addr : 11; - } sh_ni0_error_detail_3_s; -} sh_ni0_error_detail_3_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_ERROR_DETAIL_3" */ /* Look Up Table Address (ni1) */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_error_detail_3_u { mmr_t sh_ni1_error_detail_3_regval; struct { @@ -16149,21 +8708,11 @@ typedef union sh_ni1_error_detail_3_u { mmr_t reserved_0 : 53; } sh_ni1_error_detail_3_s; } sh_ni1_error_detail_3_u_t; -#else -typedef union sh_ni1_error_detail_3_u { - mmr_t sh_ni1_error_detail_3_regval; - struct { - mmr_t reserved_0 : 53; - mmr_t lut_addr : 11; - } sh_ni1_error_detail_3_s; -} sh_ni1_error_detail_3_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_ERROR_SUMMARY" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_error_summary_u { mmr_t sh_xn_error_summary_regval; struct { @@ -16208,58 +8757,11 @@ typedef union sh_xn_error_summary_u { mmr_t reserved_0 : 26; } sh_xn_error_summary_s; } sh_xn_error_summary_u_t; -#else -typedef union sh_xn_error_summary_u { - mmr_t sh_xn_error_summary_regval; - struct { - mmr_t reserved_0 : 26; - mmr_t iilb_chiplet_or_lut : 1; - mmr_t iilb_fifo_underflow : 1; - mmr_t iilb_credit_underflow : 1; - mmr_t iilb_fifo_overflow : 1; - mmr_t iilb_credit_overflow : 1; - mmr_t iilb_debit_overflow : 1; - mmr_t xnpi_lut_error : 1; - mmr_t xnpi_uce_error : 1; - mmr_t xnpi_sbe_error : 1; - mmr_t xnpi_credit_underflow : 1; - mmr_t xnpi_data_buff_overflow : 1; - mmr_t xnpi_debit_overflow : 1; - mmr_t xnpi_credit_overflow : 1; - mmr_t xnmd_lut_error : 1; - mmr_t xnmd_uce_error : 1; - mmr_t xnmd_sbe_error : 1; - mmr_t xnmd_credit_underflow : 1; - mmr_t xnmd_data_buff_overflow : 1; - mmr_t xnmd_debit_overflow : 1; - mmr_t xnmd_credit_overflow : 1; - mmr_t ni1_pipe_error : 1; - mmr_t ni1_llp_error : 1; - mmr_t ni1_credit_underflow : 1; - mmr_t ni1_push_underflow : 1; - mmr_t ni1_pop_underflow : 1; - mmr_t ni1_debit_overflow : 1; - mmr_t ni1_credit_overflow : 1; - mmr_t ni1_push_overflow : 1; - mmr_t ni1_pop_overflow : 1; - mmr_t ni0_pipe_error : 1; - mmr_t ni0_llp_error : 1; - mmr_t ni0_credit_underflow : 1; - mmr_t ni0_push_underflow : 1; - mmr_t ni0_pop_underflow : 1; - mmr_t ni0_debit_overflow : 1; - mmr_t ni0_credit_overflow : 1; - mmr_t ni0_push_overflow : 1; - mmr_t ni0_pop_overflow : 1; - } sh_xn_error_summary_s; -} sh_xn_error_summary_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_ERROR_OVERFLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_error_overflow_u { mmr_t sh_xn_error_overflow_regval; struct { @@ -16304,58 +8806,11 @@ typedef union sh_xn_error_overflow_u { mmr_t reserved_0 : 26; } sh_xn_error_overflow_s; } sh_xn_error_overflow_u_t; -#else -typedef union sh_xn_error_overflow_u { - mmr_t sh_xn_error_overflow_regval; - struct { - mmr_t reserved_0 : 26; - mmr_t iilb_chiplet_or_lut : 1; - mmr_t iilb_fifo_underflow : 1; - mmr_t iilb_credit_underflow : 1; - mmr_t iilb_fifo_overflow : 1; - mmr_t iilb_credit_overflow : 1; - mmr_t iilb_debit_overflow : 1; - mmr_t xnpi_lut_error : 1; - mmr_t xnpi_uce_error : 1; - mmr_t xnpi_sbe_error : 1; - mmr_t xnpi_credit_underflow : 1; - mmr_t xnpi_data_buff_overflow : 1; - mmr_t xnpi_debit_overflow : 1; - mmr_t xnpi_credit_overflow : 1; - mmr_t xnmd_lut_error : 1; - mmr_t xnmd_uce_error : 1; - mmr_t xnmd_sbe_error : 1; - mmr_t xnmd_credit_underflow : 1; - mmr_t xnmd_data_buff_overflow : 1; - mmr_t xnmd_debit_overflow : 1; - mmr_t xnmd_credit_overflow : 1; - mmr_t ni1_pipe_error : 1; - mmr_t ni1_llp_error : 1; - mmr_t ni1_credit_underflow : 1; - mmr_t ni1_push_underflow : 1; - mmr_t ni1_pop_underflow : 1; - mmr_t ni1_debit_overflow : 1; - mmr_t ni1_credit_overflow : 1; - mmr_t ni1_push_overflow : 1; - mmr_t ni1_pop_overflow : 1; - mmr_t ni0_pipe_error : 1; - mmr_t ni0_llp_error : 1; - mmr_t ni0_credit_underflow : 1; - mmr_t ni0_push_underflow : 1; - mmr_t ni0_pop_underflow : 1; - mmr_t ni0_debit_overflow : 1; - mmr_t ni0_credit_overflow : 1; - mmr_t ni0_push_overflow : 1; - mmr_t ni0_pop_overflow : 1; - } sh_xn_error_overflow_s; -} sh_xn_error_overflow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_ERROR_MASK" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_error_mask_u { mmr_t sh_xn_error_mask_regval; struct { @@ -16400,58 +8855,11 @@ typedef union sh_xn_error_mask_u { mmr_t reserved_0 : 26; } sh_xn_error_mask_s; } sh_xn_error_mask_u_t; -#else -typedef union sh_xn_error_mask_u { - mmr_t sh_xn_error_mask_regval; - struct { - mmr_t reserved_0 : 26; - mmr_t iilb_chiplet_or_lut : 1; - mmr_t iilb_fifo_underflow : 1; - mmr_t iilb_credit_underflow : 1; - mmr_t iilb_fifo_overflow : 1; - mmr_t iilb_credit_overflow : 1; - mmr_t iilb_debit_overflow : 1; - mmr_t xnpi_lut_error : 1; - mmr_t xnpi_uce_error : 1; - mmr_t xnpi_sbe_error : 1; - mmr_t xnpi_credit_underflow : 1; - mmr_t xnpi_data_buff_overflow : 1; - mmr_t xnpi_debit_overflow : 1; - mmr_t xnpi_credit_overflow : 1; - mmr_t xnmd_lut_error : 1; - mmr_t xnmd_uce_error : 1; - mmr_t xnmd_sbe_error : 1; - mmr_t xnmd_credit_underflow : 1; - mmr_t xnmd_data_buff_overflow : 1; - mmr_t xnmd_debit_overflow : 1; - mmr_t xnmd_credit_overflow : 1; - mmr_t ni1_pipe_error : 1; - mmr_t ni1_llp_error : 1; - mmr_t ni1_credit_underflow : 1; - mmr_t ni1_push_underflow : 1; - mmr_t ni1_pop_underflow : 1; - mmr_t ni1_debit_overflow : 1; - mmr_t ni1_credit_overflow : 1; - mmr_t ni1_push_overflow : 1; - mmr_t ni1_pop_overflow : 1; - mmr_t ni0_pipe_error : 1; - mmr_t ni0_llp_error : 1; - mmr_t ni0_credit_underflow : 1; - mmr_t ni0_push_underflow : 1; - mmr_t ni0_pop_underflow : 1; - mmr_t ni0_debit_overflow : 1; - mmr_t ni0_credit_overflow : 1; - mmr_t ni0_push_overflow : 1; - mmr_t ni0_pop_overflow : 1; - } sh_xn_error_mask_s; -} sh_xn_error_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_FIRST_ERROR" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_first_error_u { mmr_t sh_xn_first_error_regval; struct { @@ -16496,58 +8904,11 @@ typedef union sh_xn_first_error_u { mmr_t reserved_0 : 26; } sh_xn_first_error_s; } sh_xn_first_error_u_t; -#else -typedef union sh_xn_first_error_u { - mmr_t sh_xn_first_error_regval; - struct { - mmr_t reserved_0 : 26; - mmr_t iilb_chiplet_or_lut : 1; - mmr_t iilb_fifo_underflow : 1; - mmr_t iilb_credit_underflow : 1; - mmr_t iilb_fifo_overflow : 1; - mmr_t iilb_credit_overflow : 1; - mmr_t iilb_debit_overflow : 1; - mmr_t xnpi_lut_error : 1; - mmr_t xnpi_uce_error : 1; - mmr_t xnpi_sbe_error : 1; - mmr_t xnpi_credit_underflow : 1; - mmr_t xnpi_data_buff_overflow : 1; - mmr_t xnpi_debit_overflow : 1; - mmr_t xnpi_credit_overflow : 1; - mmr_t xnmd_lut_error : 1; - mmr_t xnmd_uce_error : 1; - mmr_t xnmd_sbe_error : 1; - mmr_t xnmd_credit_underflow : 1; - mmr_t xnmd_data_buff_overflow : 1; - mmr_t xnmd_debit_overflow : 1; - mmr_t xnmd_credit_overflow : 1; - mmr_t ni1_pipe_error : 1; - mmr_t ni1_llp_error : 1; - mmr_t ni1_credit_underflow : 1; - mmr_t ni1_push_underflow : 1; - mmr_t ni1_pop_underflow : 1; - mmr_t ni1_debit_overflow : 1; - mmr_t ni1_credit_overflow : 1; - mmr_t ni1_push_overflow : 1; - mmr_t ni1_pop_overflow : 1; - mmr_t ni0_pipe_error : 1; - mmr_t ni0_llp_error : 1; - mmr_t ni0_credit_underflow : 1; - mmr_t ni0_push_underflow : 1; - mmr_t ni0_pop_underflow : 1; - mmr_t ni0_debit_overflow : 1; - mmr_t ni0_credit_overflow : 1; - mmr_t ni0_push_overflow : 1; - mmr_t ni0_pop_overflow : 1; - } sh_xn_first_error_s; -} sh_xn_first_error_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_ERROR_SUMMARY" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xniilb_error_summary_u { mmr_t sh_xniilb_error_summary_regval; struct { @@ -16617,83 +8978,11 @@ typedef union sh_xniilb_error_summary_u { mmr_t lut_read_error : 1; } sh_xniilb_error_summary_s; } sh_xniilb_error_summary_u_t; -#else -typedef union sh_xniilb_error_summary_u { - mmr_t sh_xniilb_error_summary_regval; - struct { - mmr_t lut_read_error : 1; - mmr_t chiplet_nomatch : 1; - mmr_t underflow_ni1_vc2_credit_out : 1; - mmr_t underflow_ni1_vc0_credit_out : 1; - mmr_t underflow_ni0_vc2_credit_out : 1; - mmr_t underflow_ni0_vc0_credit_out : 1; - mmr_t underflow_iilb_vc2_credit_out : 1; - mmr_t underflow_iilb_vc0_credit_out : 1; - mmr_t underflow_md_vc2_credit_out : 1; - mmr_t underflow_md_vc0_credit_out : 1; - mmr_t underflow_pi_vc2_credit_out : 1; - mmr_t underflow_pi_vc0_credit_out : 1; - mmr_t overflow_ni1_vc2_credit_out : 1; - mmr_t overflow_ni1_vc0_credit_out : 1; - mmr_t overflow_ni0_vc2_credit_out : 1; - mmr_t overflow_ni0_vc0_credit_out : 1; - mmr_t overflow_iilb_vc2_credit_out : 1; - mmr_t overflow_iilb_vc0_credit_out : 1; - mmr_t overflow_md_vc2_credit_out : 1; - mmr_t overflow_md_vc0_credit_out : 1; - mmr_t overflow_pi_vc2_credit_out : 1; - mmr_t overflow_pi_vc0_credit_out : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_md_debit2 : 1; - mmr_t overflow_md_debit0 : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_pi_debit2 : 1; - mmr_t overflow_pi_debit0 : 1; - mmr_t underflow_ni1_vc2_credit_in : 1; - mmr_t underflow_ni0_vc2_credit_in : 1; - mmr_t underflow_md_vc2_credit_in : 1; - mmr_t underflow_iilb_vc2_credit_in : 1; - mmr_t underflow_pi_vc2_credit_in : 1; - mmr_t underflow_ni1_vc0_credit_in : 1; - mmr_t underflow_ni0_vc0_credit_in : 1; - mmr_t underflow_md_vc0_credit_in : 1; - mmr_t underflow_iilb_vc0_credit_in : 1; - mmr_t underflow_pi_vc0_credit_in : 1; - mmr_t overflow_ni1_vc2_credit_in : 1; - mmr_t overflow_ni0_vc2_credit_in : 1; - mmr_t overflow_md_vc2_credit_in : 1; - mmr_t overflow_iilb_vc2_credit_in : 1; - mmr_t overflow_pi_vc2_credit_in : 1; - mmr_t overflow_ni1_vc0_credit_in : 1; - mmr_t overflow_ni0_vc0_credit_in : 1; - mmr_t overflow_md_vc0_credit_in : 1; - mmr_t overflow_iilb_vc0_credit_in : 1; - mmr_t overflow_pi_vc0_credit_in : 1; - mmr_t underflow_lb_vc2 : 1; - mmr_t underflow_lb_vc0 : 1; - mmr_t overflow_lb_vc2 : 1; - mmr_t overflow_lb_vc0 : 1; - mmr_t underflow_ii_vc2 : 1; - mmr_t underflow_ii_vc0 : 1; - mmr_t overflow_ii_vc2 : 1; - mmr_t overflow_ii_vc0 : 1; - mmr_t overflow_lb_debit2 : 1; - mmr_t overflow_lb_debit0 : 1; - mmr_t overflow_ii_debit2 : 1; - mmr_t overflow_ii_debit0 : 1; - } sh_xniilb_error_summary_s; -} sh_xniilb_error_summary_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_ERROR_OVERFLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xniilb_error_overflow_u { mmr_t sh_xniilb_error_overflow_regval; struct { @@ -16763,83 +9052,11 @@ typedef union sh_xniilb_error_overflow_u { mmr_t lut_read_error : 1; } sh_xniilb_error_overflow_s; } sh_xniilb_error_overflow_u_t; -#else -typedef union sh_xniilb_error_overflow_u { - mmr_t sh_xniilb_error_overflow_regval; - struct { - mmr_t lut_read_error : 1; - mmr_t chiplet_nomatch : 1; - mmr_t underflow_ni1_vc2_credit_out : 1; - mmr_t underflow_ni1_vc0_credit_out : 1; - mmr_t underflow_ni0_vc2_credit_out : 1; - mmr_t underflow_ni0_vc0_credit_out : 1; - mmr_t underflow_iilb_vc2_credit_out : 1; - mmr_t underflow_iilb_vc0_credit_out : 1; - mmr_t underflow_md_vc2_credit_out : 1; - mmr_t underflow_md_vc0_credit_out : 1; - mmr_t underflow_pi_vc2_credit_out : 1; - mmr_t underflow_pi_vc0_credit_out : 1; - mmr_t overflow_ni1_vc2_credit_out : 1; - mmr_t overflow_ni1_vc0_credit_out : 1; - mmr_t overflow_ni0_vc2_credit_out : 1; - mmr_t overflow_ni0_vc0_credit_out : 1; - mmr_t overflow_iilb_vc2_credit_out : 1; - mmr_t overflow_iilb_vc0_credit_out : 1; - mmr_t overflow_md_vc2_credit_out : 1; - mmr_t overflow_md_vc0_credit_out : 1; - mmr_t overflow_pi_vc2_credit_out : 1; - mmr_t overflow_pi_vc0_credit_out : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_md_debit2 : 1; - mmr_t overflow_md_debit0 : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_pi_debit2 : 1; - mmr_t overflow_pi_debit0 : 1; - mmr_t underflow_ni1_vc2_credit_in : 1; - mmr_t underflow_ni0_vc2_credit_in : 1; - mmr_t underflow_md_vc2_credit_in : 1; - mmr_t underflow_iilb_vc2_credit_in : 1; - mmr_t underflow_pi_vc2_credit_in : 1; - mmr_t underflow_ni1_vc0_credit_in : 1; - mmr_t underflow_ni0_vc0_credit_in : 1; - mmr_t underflow_md_vc0_credit_in : 1; - mmr_t underflow_iilb_vc0_credit_in : 1; - mmr_t underflow_pi_vc0_credit_in : 1; - mmr_t overflow_ni1_vc2_credit_in : 1; - mmr_t overflow_ni0_vc2_credit_in : 1; - mmr_t overflow_md_vc2_credit_in : 1; - mmr_t overflow_iilb_vc2_credit_in : 1; - mmr_t overflow_pi_vc2_credit_in : 1; - mmr_t overflow_ni1_vc0_credit_in : 1; - mmr_t overflow_ni0_vc0_credit_in : 1; - mmr_t overflow_md_vc0_credit_in : 1; - mmr_t overflow_iilb_vc0_credit_in : 1; - mmr_t overflow_pi_vc0_credit_in : 1; - mmr_t underflow_lb_vc2 : 1; - mmr_t underflow_lb_vc0 : 1; - mmr_t overflow_lb_vc2 : 1; - mmr_t overflow_lb_vc0 : 1; - mmr_t underflow_ii_vc2 : 1; - mmr_t underflow_ii_vc0 : 1; - mmr_t overflow_ii_vc2 : 1; - mmr_t overflow_ii_vc0 : 1; - mmr_t overflow_lb_debit2 : 1; - mmr_t overflow_lb_debit0 : 1; - mmr_t overflow_ii_debit2 : 1; - mmr_t overflow_ii_debit0 : 1; - } sh_xniilb_error_overflow_s; -} sh_xniilb_error_overflow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_ERROR_MASK" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xniilb_error_mask_u { mmr_t sh_xniilb_error_mask_regval; struct { @@ -16909,83 +9126,11 @@ typedef union sh_xniilb_error_mask_u { mmr_t lut_read_error : 1; } sh_xniilb_error_mask_s; } sh_xniilb_error_mask_u_t; -#else -typedef union sh_xniilb_error_mask_u { - mmr_t sh_xniilb_error_mask_regval; - struct { - mmr_t lut_read_error : 1; - mmr_t chiplet_nomatch : 1; - mmr_t underflow_ni1_vc2_credit_out : 1; - mmr_t underflow_ni1_vc0_credit_out : 1; - mmr_t underflow_ni0_vc2_credit_out : 1; - mmr_t underflow_ni0_vc0_credit_out : 1; - mmr_t underflow_iilb_vc2_credit_out : 1; - mmr_t underflow_iilb_vc0_credit_out : 1; - mmr_t underflow_md_vc2_credit_out : 1; - mmr_t underflow_md_vc0_credit_out : 1; - mmr_t underflow_pi_vc2_credit_out : 1; - mmr_t underflow_pi_vc0_credit_out : 1; - mmr_t overflow_ni1_vc2_credit_out : 1; - mmr_t overflow_ni1_vc0_credit_out : 1; - mmr_t overflow_ni0_vc2_credit_out : 1; - mmr_t overflow_ni0_vc0_credit_out : 1; - mmr_t overflow_iilb_vc2_credit_out : 1; - mmr_t overflow_iilb_vc0_credit_out : 1; - mmr_t overflow_md_vc2_credit_out : 1; - mmr_t overflow_md_vc0_credit_out : 1; - mmr_t overflow_pi_vc2_credit_out : 1; - mmr_t overflow_pi_vc0_credit_out : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_md_debit2 : 1; - mmr_t overflow_md_debit0 : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_pi_debit2 : 1; - mmr_t overflow_pi_debit0 : 1; - mmr_t underflow_ni1_vc2_credit_in : 1; - mmr_t underflow_ni0_vc2_credit_in : 1; - mmr_t underflow_md_vc2_credit_in : 1; - mmr_t underflow_iilb_vc2_credit_in : 1; - mmr_t underflow_pi_vc2_credit_in : 1; - mmr_t underflow_ni1_vc0_credit_in : 1; - mmr_t underflow_ni0_vc0_credit_in : 1; - mmr_t underflow_md_vc0_credit_in : 1; - mmr_t underflow_iilb_vc0_credit_in : 1; - mmr_t underflow_pi_vc0_credit_in : 1; - mmr_t overflow_ni1_vc2_credit_in : 1; - mmr_t overflow_ni0_vc2_credit_in : 1; - mmr_t overflow_md_vc2_credit_in : 1; - mmr_t overflow_iilb_vc2_credit_in : 1; - mmr_t overflow_pi_vc2_credit_in : 1; - mmr_t overflow_ni1_vc0_credit_in : 1; - mmr_t overflow_ni0_vc0_credit_in : 1; - mmr_t overflow_md_vc0_credit_in : 1; - mmr_t overflow_iilb_vc0_credit_in : 1; - mmr_t overflow_pi_vc0_credit_in : 1; - mmr_t underflow_lb_vc2 : 1; - mmr_t underflow_lb_vc0 : 1; - mmr_t overflow_lb_vc2 : 1; - mmr_t overflow_lb_vc0 : 1; - mmr_t underflow_ii_vc2 : 1; - mmr_t underflow_ii_vc0 : 1; - mmr_t overflow_ii_vc2 : 1; - mmr_t overflow_ii_vc0 : 1; - mmr_t overflow_lb_debit2 : 1; - mmr_t overflow_lb_debit0 : 1; - mmr_t overflow_ii_debit2 : 1; - mmr_t overflow_ii_debit0 : 1; - } sh_xniilb_error_mask_s; -} sh_xniilb_error_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_FIRST_ERROR" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xniilb_first_error_u { mmr_t sh_xniilb_first_error_regval; struct { @@ -17055,83 +9200,11 @@ typedef union sh_xniilb_first_error_u { mmr_t lut_read_error : 1; } sh_xniilb_first_error_s; } sh_xniilb_first_error_u_t; -#else -typedef union sh_xniilb_first_error_u { - mmr_t sh_xniilb_first_error_regval; - struct { - mmr_t lut_read_error : 1; - mmr_t chiplet_nomatch : 1; - mmr_t underflow_ni1_vc2_credit_out : 1; - mmr_t underflow_ni1_vc0_credit_out : 1; - mmr_t underflow_ni0_vc2_credit_out : 1; - mmr_t underflow_ni0_vc0_credit_out : 1; - mmr_t underflow_iilb_vc2_credit_out : 1; - mmr_t underflow_iilb_vc0_credit_out : 1; - mmr_t underflow_md_vc2_credit_out : 1; - mmr_t underflow_md_vc0_credit_out : 1; - mmr_t underflow_pi_vc2_credit_out : 1; - mmr_t underflow_pi_vc0_credit_out : 1; - mmr_t overflow_ni1_vc2_credit_out : 1; - mmr_t overflow_ni1_vc0_credit_out : 1; - mmr_t overflow_ni0_vc2_credit_out : 1; - mmr_t overflow_ni0_vc0_credit_out : 1; - mmr_t overflow_iilb_vc2_credit_out : 1; - mmr_t overflow_iilb_vc0_credit_out : 1; - mmr_t overflow_md_vc2_credit_out : 1; - mmr_t overflow_md_vc0_credit_out : 1; - mmr_t overflow_pi_vc2_credit_out : 1; - mmr_t overflow_pi_vc0_credit_out : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_md_debit2 : 1; - mmr_t overflow_md_debit0 : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_pi_debit2 : 1; - mmr_t overflow_pi_debit0 : 1; - mmr_t underflow_ni1_vc2_credit_in : 1; - mmr_t underflow_ni0_vc2_credit_in : 1; - mmr_t underflow_md_vc2_credit_in : 1; - mmr_t underflow_iilb_vc2_credit_in : 1; - mmr_t underflow_pi_vc2_credit_in : 1; - mmr_t underflow_ni1_vc0_credit_in : 1; - mmr_t underflow_ni0_vc0_credit_in : 1; - mmr_t underflow_md_vc0_credit_in : 1; - mmr_t underflow_iilb_vc0_credit_in : 1; - mmr_t underflow_pi_vc0_credit_in : 1; - mmr_t overflow_ni1_vc2_credit_in : 1; - mmr_t overflow_ni0_vc2_credit_in : 1; - mmr_t overflow_md_vc2_credit_in : 1; - mmr_t overflow_iilb_vc2_credit_in : 1; - mmr_t overflow_pi_vc2_credit_in : 1; - mmr_t overflow_ni1_vc0_credit_in : 1; - mmr_t overflow_ni0_vc0_credit_in : 1; - mmr_t overflow_md_vc0_credit_in : 1; - mmr_t overflow_iilb_vc0_credit_in : 1; - mmr_t overflow_pi_vc0_credit_in : 1; - mmr_t underflow_lb_vc2 : 1; - mmr_t underflow_lb_vc0 : 1; - mmr_t overflow_lb_vc2 : 1; - mmr_t overflow_lb_vc0 : 1; - mmr_t underflow_ii_vc2 : 1; - mmr_t underflow_ii_vc0 : 1; - mmr_t overflow_ii_vc2 : 1; - mmr_t overflow_ii_vc0 : 1; - mmr_t overflow_lb_debit2 : 1; - mmr_t overflow_lb_debit0 : 1; - mmr_t overflow_ii_debit2 : 1; - mmr_t overflow_ii_debit0 : 1; - } sh_xniilb_first_error_s; -} sh_xniilb_first_error_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_ERROR_SUMMARY" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnpi_error_summary_u { mmr_t sh_xnpi_error_summary_regval; struct { @@ -17188,70 +9261,11 @@ typedef union sh_xnpi_error_summary_u { mmr_t reserved_0 : 14; } sh_xnpi_error_summary_s; } sh_xnpi_error_summary_u_t; -#else -typedef union sh_xnpi_error_summary_u { - mmr_t sh_xnpi_error_summary_regval; - struct { - mmr_t reserved_0 : 14; - mmr_t overflow_header_cancel_fifo : 1; - mmr_t overflow_iilb_vc2_credit : 1; - mmr_t underflow_iilb_vc2_credit : 1; - mmr_t overflow_iilb_vc0_credit : 1; - mmr_t underflow_iilb_vc0_credit : 1; - mmr_t overflow_ni1_vc2_credit : 1; - mmr_t underflow_ni1_vc2_credit : 1; - mmr_t overflow_ni1_vc0_credit : 1; - mmr_t underflow_ni1_vc0_credit : 1; - mmr_t overflow_ni0_vc2_credit : 1; - mmr_t underflow_ni0_vc2_credit : 1; - mmr_t overflow_ni0_vc0_credit : 1; - mmr_t underflow_ni0_vc0_credit : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_sic_cntr2 : 1; - mmr_t underflow_sic_cntr2 : 1; - mmr_t overflow_sic_cntr0 : 1; - mmr_t underflow_sic_cntr0 : 1; - mmr_t uncor_error3 : 1; - mmr_t uncor_error2 : 1; - mmr_t uncor_error1 : 1; - mmr_t uncor_error0 : 1; - mmr_t single_bit_error3 : 1; - mmr_t single_bit_error2 : 1; - mmr_t single_bit_error1 : 1; - mmr_t single_bit_error0 : 1; - mmr_t lut_read_error : 1; - mmr_t overflow_databuff_vc2 : 1; - mmr_t overflow_databuff_vc0 : 1; - mmr_t overflow_vc2_credit : 1; - mmr_t underflow_vc2_credit : 1; - mmr_t overflow_vc0_credit : 1; - mmr_t underflow_vc0_credit : 1; - mmr_t overflow_iilb_vc2 : 1; - mmr_t underflow_iilb_vc2 : 1; - mmr_t overflow_iilb_vc0 : 1; - mmr_t underflow_iilb_vc0 : 1; - mmr_t overflow_ni1_vc2 : 1; - mmr_t underflow_ni1_vc2 : 1; - mmr_t overflow_ni1_vc0 : 1; - mmr_t underflow_ni1_vc0 : 1; - mmr_t overflow_ni0_vc2 : 1; - mmr_t underflow_ni0_vc2 : 1; - mmr_t overflow_ni0_vc0 : 1; - mmr_t underflow_ni0_vc0 : 1; - } sh_xnpi_error_summary_s; -} sh_xnpi_error_summary_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_ERROR_OVERFLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnpi_error_overflow_u { mmr_t sh_xnpi_error_overflow_regval; struct { @@ -17308,70 +9322,11 @@ typedef union sh_xnpi_error_overflow_u { mmr_t reserved_0 : 14; } sh_xnpi_error_overflow_s; } sh_xnpi_error_overflow_u_t; -#else -typedef union sh_xnpi_error_overflow_u { - mmr_t sh_xnpi_error_overflow_regval; - struct { - mmr_t reserved_0 : 14; - mmr_t overflow_header_cancel_fifo : 1; - mmr_t overflow_iilb_vc2_credit : 1; - mmr_t underflow_iilb_vc2_credit : 1; - mmr_t overflow_iilb_vc0_credit : 1; - mmr_t underflow_iilb_vc0_credit : 1; - mmr_t overflow_ni1_vc2_credit : 1; - mmr_t underflow_ni1_vc2_credit : 1; - mmr_t overflow_ni1_vc0_credit : 1; - mmr_t underflow_ni1_vc0_credit : 1; - mmr_t overflow_ni0_vc2_credit : 1; - mmr_t underflow_ni0_vc2_credit : 1; - mmr_t overflow_ni0_vc0_credit : 1; - mmr_t underflow_ni0_vc0_credit : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_sic_cntr2 : 1; - mmr_t underflow_sic_cntr2 : 1; - mmr_t overflow_sic_cntr0 : 1; - mmr_t underflow_sic_cntr0 : 1; - mmr_t uncor_error3 : 1; - mmr_t uncor_error2 : 1; - mmr_t uncor_error1 : 1; - mmr_t uncor_error0 : 1; - mmr_t single_bit_error3 : 1; - mmr_t single_bit_error2 : 1; - mmr_t single_bit_error1 : 1; - mmr_t single_bit_error0 : 1; - mmr_t lut_read_error : 1; - mmr_t overflow_databuff_vc2 : 1; - mmr_t overflow_databuff_vc0 : 1; - mmr_t overflow_vc2_credit : 1; - mmr_t underflow_vc2_credit : 1; - mmr_t overflow_vc0_credit : 1; - mmr_t underflow_vc0_credit : 1; - mmr_t overflow_iilb_vc2 : 1; - mmr_t underflow_iilb_vc2 : 1; - mmr_t overflow_iilb_vc0 : 1; - mmr_t underflow_iilb_vc0 : 1; - mmr_t overflow_ni1_vc2 : 1; - mmr_t underflow_ni1_vc2 : 1; - mmr_t overflow_ni1_vc0 : 1; - mmr_t underflow_ni1_vc0 : 1; - mmr_t overflow_ni0_vc2 : 1; - mmr_t underflow_ni0_vc2 : 1; - mmr_t overflow_ni0_vc0 : 1; - mmr_t underflow_ni0_vc0 : 1; - } sh_xnpi_error_overflow_s; -} sh_xnpi_error_overflow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_ERROR_MASK" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnpi_error_mask_u { mmr_t sh_xnpi_error_mask_regval; struct { @@ -17428,70 +9383,11 @@ typedef union sh_xnpi_error_mask_u { mmr_t reserved_0 : 14; } sh_xnpi_error_mask_s; } sh_xnpi_error_mask_u_t; -#else -typedef union sh_xnpi_error_mask_u { - mmr_t sh_xnpi_error_mask_regval; - struct { - mmr_t reserved_0 : 14; - mmr_t overflow_header_cancel_fifo : 1; - mmr_t overflow_iilb_vc2_credit : 1; - mmr_t underflow_iilb_vc2_credit : 1; - mmr_t overflow_iilb_vc0_credit : 1; - mmr_t underflow_iilb_vc0_credit : 1; - mmr_t overflow_ni1_vc2_credit : 1; - mmr_t underflow_ni1_vc2_credit : 1; - mmr_t overflow_ni1_vc0_credit : 1; - mmr_t underflow_ni1_vc0_credit : 1; - mmr_t overflow_ni0_vc2_credit : 1; - mmr_t underflow_ni0_vc2_credit : 1; - mmr_t overflow_ni0_vc0_credit : 1; - mmr_t underflow_ni0_vc0_credit : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_sic_cntr2 : 1; - mmr_t underflow_sic_cntr2 : 1; - mmr_t overflow_sic_cntr0 : 1; - mmr_t underflow_sic_cntr0 : 1; - mmr_t uncor_error3 : 1; - mmr_t uncor_error2 : 1; - mmr_t uncor_error1 : 1; - mmr_t uncor_error0 : 1; - mmr_t single_bit_error3 : 1; - mmr_t single_bit_error2 : 1; - mmr_t single_bit_error1 : 1; - mmr_t single_bit_error0 : 1; - mmr_t lut_read_error : 1; - mmr_t overflow_databuff_vc2 : 1; - mmr_t overflow_databuff_vc0 : 1; - mmr_t overflow_vc2_credit : 1; - mmr_t underflow_vc2_credit : 1; - mmr_t overflow_vc0_credit : 1; - mmr_t underflow_vc0_credit : 1; - mmr_t overflow_iilb_vc2 : 1; - mmr_t underflow_iilb_vc2 : 1; - mmr_t overflow_iilb_vc0 : 1; - mmr_t underflow_iilb_vc0 : 1; - mmr_t overflow_ni1_vc2 : 1; - mmr_t underflow_ni1_vc2 : 1; - mmr_t overflow_ni1_vc0 : 1; - mmr_t underflow_ni1_vc0 : 1; - mmr_t overflow_ni0_vc2 : 1; - mmr_t underflow_ni0_vc2 : 1; - mmr_t overflow_ni0_vc0 : 1; - mmr_t underflow_ni0_vc0 : 1; - } sh_xnpi_error_mask_s; -} sh_xnpi_error_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_FIRST_ERROR" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnpi_first_error_u { mmr_t sh_xnpi_first_error_regval; struct { @@ -17548,70 +9444,11 @@ typedef union sh_xnpi_first_error_u { mmr_t reserved_0 : 14; } sh_xnpi_first_error_s; } sh_xnpi_first_error_u_t; -#else -typedef union sh_xnpi_first_error_u { - mmr_t sh_xnpi_first_error_regval; - struct { - mmr_t reserved_0 : 14; - mmr_t overflow_header_cancel_fifo : 1; - mmr_t overflow_iilb_vc2_credit : 1; - mmr_t underflow_iilb_vc2_credit : 1; - mmr_t overflow_iilb_vc0_credit : 1; - mmr_t underflow_iilb_vc0_credit : 1; - mmr_t overflow_ni1_vc2_credit : 1; - mmr_t underflow_ni1_vc2_credit : 1; - mmr_t overflow_ni1_vc0_credit : 1; - mmr_t underflow_ni1_vc0_credit : 1; - mmr_t overflow_ni0_vc2_credit : 1; - mmr_t underflow_ni0_vc2_credit : 1; - mmr_t overflow_ni0_vc0_credit : 1; - mmr_t underflow_ni0_vc0_credit : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_sic_cntr2 : 1; - mmr_t underflow_sic_cntr2 : 1; - mmr_t overflow_sic_cntr0 : 1; - mmr_t underflow_sic_cntr0 : 1; - mmr_t uncor_error3 : 1; - mmr_t uncor_error2 : 1; - mmr_t uncor_error1 : 1; - mmr_t uncor_error0 : 1; - mmr_t single_bit_error3 : 1; - mmr_t single_bit_error2 : 1; - mmr_t single_bit_error1 : 1; - mmr_t single_bit_error0 : 1; - mmr_t lut_read_error : 1; - mmr_t overflow_databuff_vc2 : 1; - mmr_t overflow_databuff_vc0 : 1; - mmr_t overflow_vc2_credit : 1; - mmr_t underflow_vc2_credit : 1; - mmr_t overflow_vc0_credit : 1; - mmr_t underflow_vc0_credit : 1; - mmr_t overflow_iilb_vc2 : 1; - mmr_t underflow_iilb_vc2 : 1; - mmr_t overflow_iilb_vc0 : 1; - mmr_t underflow_iilb_vc0 : 1; - mmr_t overflow_ni1_vc2 : 1; - mmr_t underflow_ni1_vc2 : 1; - mmr_t overflow_ni1_vc0 : 1; - mmr_t underflow_ni1_vc0 : 1; - mmr_t overflow_ni0_vc2 : 1; - mmr_t underflow_ni0_vc2 : 1; - mmr_t overflow_ni0_vc0 : 1; - mmr_t underflow_ni0_vc0 : 1; - } sh_xnpi_first_error_s; -} sh_xnpi_first_error_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_ERROR_SUMMARY" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnmd_error_summary_u { mmr_t sh_xnmd_error_summary_regval; struct { @@ -17668,70 +9505,11 @@ typedef union sh_xnmd_error_summary_u { mmr_t reserved_0 : 14; } sh_xnmd_error_summary_s; } sh_xnmd_error_summary_u_t; -#else -typedef union sh_xnmd_error_summary_u { - mmr_t sh_xnmd_error_summary_regval; - struct { - mmr_t reserved_0 : 14; - mmr_t overflow_header_cancel_fifo : 1; - mmr_t overflow_iilb_vc2_credit : 1; - mmr_t underflow_iilb_vc2_credit : 1; - mmr_t overflow_iilb_vc0_credit : 1; - mmr_t underflow_iilb_vc0_credit : 1; - mmr_t overflow_ni1_vc2_credit : 1; - mmr_t underflow_ni1_vc2_credit : 1; - mmr_t overflow_ni1_vc0_credit : 1; - mmr_t underflow_ni1_vc0_credit : 1; - mmr_t overflow_ni0_vc2_credit : 1; - mmr_t underflow_ni0_vc2_credit : 1; - mmr_t overflow_ni0_vc0_credit : 1; - mmr_t underflow_ni0_vc0_credit : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_sic_cntr2 : 1; - mmr_t underflow_sic_cntr2 : 1; - mmr_t overflow_sic_cntr0 : 1; - mmr_t underflow_sic_cntr0 : 1; - mmr_t uncor_error3 : 1; - mmr_t uncor_error2 : 1; - mmr_t uncor_error1 : 1; - mmr_t uncor_error0 : 1; - mmr_t single_bit_error3 : 1; - mmr_t single_bit_error2 : 1; - mmr_t single_bit_error1 : 1; - mmr_t single_bit_error0 : 1; - mmr_t lut_read_error : 1; - mmr_t overflow_databuff_vc2 : 1; - mmr_t overflow_databuff_vc0 : 1; - mmr_t overflow_vc2_credit : 1; - mmr_t underflow_vc2_credit : 1; - mmr_t overflow_vc0_credit : 1; - mmr_t underflow_vc0_credit : 1; - mmr_t overflow_iilb_vc2 : 1; - mmr_t underflow_iilb_vc2 : 1; - mmr_t overflow_iilb_vc0 : 1; - mmr_t underflow_iilb_vc0 : 1; - mmr_t overflow_ni1_vc2 : 1; - mmr_t underflow_ni1_vc2 : 1; - mmr_t overflow_ni1_vc0 : 1; - mmr_t underflow_ni1_vc0 : 1; - mmr_t overflow_ni0_vc2 : 1; - mmr_t underflow_ni0_vc2 : 1; - mmr_t overflow_ni0_vc0 : 1; - mmr_t underflow_ni0_vc0 : 1; - } sh_xnmd_error_summary_s; -} sh_xnmd_error_summary_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_ERROR_OVERFLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnmd_error_overflow_u { mmr_t sh_xnmd_error_overflow_regval; struct { @@ -17788,70 +9566,11 @@ typedef union sh_xnmd_error_overflow_u { mmr_t reserved_0 : 14; } sh_xnmd_error_overflow_s; } sh_xnmd_error_overflow_u_t; -#else -typedef union sh_xnmd_error_overflow_u { - mmr_t sh_xnmd_error_overflow_regval; - struct { - mmr_t reserved_0 : 14; - mmr_t overflow_header_cancel_fifo : 1; - mmr_t overflow_iilb_vc2_credit : 1; - mmr_t underflow_iilb_vc2_credit : 1; - mmr_t overflow_iilb_vc0_credit : 1; - mmr_t underflow_iilb_vc0_credit : 1; - mmr_t overflow_ni1_vc2_credit : 1; - mmr_t underflow_ni1_vc2_credit : 1; - mmr_t overflow_ni1_vc0_credit : 1; - mmr_t underflow_ni1_vc0_credit : 1; - mmr_t overflow_ni0_vc2_credit : 1; - mmr_t underflow_ni0_vc2_credit : 1; - mmr_t overflow_ni0_vc0_credit : 1; - mmr_t underflow_ni0_vc0_credit : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_sic_cntr2 : 1; - mmr_t underflow_sic_cntr2 : 1; - mmr_t overflow_sic_cntr0 : 1; - mmr_t underflow_sic_cntr0 : 1; - mmr_t uncor_error3 : 1; - mmr_t uncor_error2 : 1; - mmr_t uncor_error1 : 1; - mmr_t uncor_error0 : 1; - mmr_t single_bit_error3 : 1; - mmr_t single_bit_error2 : 1; - mmr_t single_bit_error1 : 1; - mmr_t single_bit_error0 : 1; - mmr_t lut_read_error : 1; - mmr_t overflow_databuff_vc2 : 1; - mmr_t overflow_databuff_vc0 : 1; - mmr_t overflow_vc2_credit : 1; - mmr_t underflow_vc2_credit : 1; - mmr_t overflow_vc0_credit : 1; - mmr_t underflow_vc0_credit : 1; - mmr_t overflow_iilb_vc2 : 1; - mmr_t underflow_iilb_vc2 : 1; - mmr_t overflow_iilb_vc0 : 1; - mmr_t underflow_iilb_vc0 : 1; - mmr_t overflow_ni1_vc2 : 1; - mmr_t underflow_ni1_vc2 : 1; - mmr_t overflow_ni1_vc0 : 1; - mmr_t underflow_ni1_vc0 : 1; - mmr_t overflow_ni0_vc2 : 1; - mmr_t underflow_ni0_vc2 : 1; - mmr_t overflow_ni0_vc0 : 1; - mmr_t underflow_ni0_vc0 : 1; - } sh_xnmd_error_overflow_s; -} sh_xnmd_error_overflow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_ERROR_MASK" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnmd_error_mask_u { mmr_t sh_xnmd_error_mask_regval; struct { @@ -17908,70 +9627,11 @@ typedef union sh_xnmd_error_mask_u { mmr_t reserved_0 : 14; } sh_xnmd_error_mask_s; } sh_xnmd_error_mask_u_t; -#else -typedef union sh_xnmd_error_mask_u { - mmr_t sh_xnmd_error_mask_regval; - struct { - mmr_t reserved_0 : 14; - mmr_t overflow_header_cancel_fifo : 1; - mmr_t overflow_iilb_vc2_credit : 1; - mmr_t underflow_iilb_vc2_credit : 1; - mmr_t overflow_iilb_vc0_credit : 1; - mmr_t underflow_iilb_vc0_credit : 1; - mmr_t overflow_ni1_vc2_credit : 1; - mmr_t underflow_ni1_vc2_credit : 1; - mmr_t overflow_ni1_vc0_credit : 1; - mmr_t underflow_ni1_vc0_credit : 1; - mmr_t overflow_ni0_vc2_credit : 1; - mmr_t underflow_ni0_vc2_credit : 1; - mmr_t overflow_ni0_vc0_credit : 1; - mmr_t underflow_ni0_vc0_credit : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_sic_cntr2 : 1; - mmr_t underflow_sic_cntr2 : 1; - mmr_t overflow_sic_cntr0 : 1; - mmr_t underflow_sic_cntr0 : 1; - mmr_t uncor_error3 : 1; - mmr_t uncor_error2 : 1; - mmr_t uncor_error1 : 1; - mmr_t uncor_error0 : 1; - mmr_t single_bit_error3 : 1; - mmr_t single_bit_error2 : 1; - mmr_t single_bit_error1 : 1; - mmr_t single_bit_error0 : 1; - mmr_t lut_read_error : 1; - mmr_t overflow_databuff_vc2 : 1; - mmr_t overflow_databuff_vc0 : 1; - mmr_t overflow_vc2_credit : 1; - mmr_t underflow_vc2_credit : 1; - mmr_t overflow_vc0_credit : 1; - mmr_t underflow_vc0_credit : 1; - mmr_t overflow_iilb_vc2 : 1; - mmr_t underflow_iilb_vc2 : 1; - mmr_t overflow_iilb_vc0 : 1; - mmr_t underflow_iilb_vc0 : 1; - mmr_t overflow_ni1_vc2 : 1; - mmr_t underflow_ni1_vc2 : 1; - mmr_t overflow_ni1_vc0 : 1; - mmr_t underflow_ni1_vc0 : 1; - mmr_t overflow_ni0_vc2 : 1; - mmr_t underflow_ni0_vc2 : 1; - mmr_t overflow_ni0_vc0 : 1; - mmr_t underflow_ni0_vc0 : 1; - } sh_xnmd_error_mask_s; -} sh_xnmd_error_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_FIRST_ERROR" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnmd_first_error_u { mmr_t sh_xnmd_first_error_regval; struct { @@ -18028,155 +9688,60 @@ typedef union sh_xnmd_first_error_u { mmr_t reserved_0 : 14; } sh_xnmd_first_error_s; } sh_xnmd_first_error_u_t; -#else -typedef union sh_xnmd_first_error_u { - mmr_t sh_xnmd_first_error_regval; - struct { - mmr_t reserved_0 : 14; - mmr_t overflow_header_cancel_fifo : 1; - mmr_t overflow_iilb_vc2_credit : 1; - mmr_t underflow_iilb_vc2_credit : 1; - mmr_t overflow_iilb_vc0_credit : 1; - mmr_t underflow_iilb_vc0_credit : 1; - mmr_t overflow_ni1_vc2_credit : 1; - mmr_t underflow_ni1_vc2_credit : 1; - mmr_t overflow_ni1_vc0_credit : 1; - mmr_t underflow_ni1_vc0_credit : 1; - mmr_t overflow_ni0_vc2_credit : 1; - mmr_t underflow_ni0_vc2_credit : 1; - mmr_t overflow_ni0_vc0_credit : 1; - mmr_t underflow_ni0_vc0_credit : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_sic_cntr2 : 1; - mmr_t underflow_sic_cntr2 : 1; - mmr_t overflow_sic_cntr0 : 1; - mmr_t underflow_sic_cntr0 : 1; - mmr_t uncor_error3 : 1; - mmr_t uncor_error2 : 1; - mmr_t uncor_error1 : 1; - mmr_t uncor_error0 : 1; - mmr_t single_bit_error3 : 1; - mmr_t single_bit_error2 : 1; - mmr_t single_bit_error1 : 1; - mmr_t single_bit_error0 : 1; - mmr_t lut_read_error : 1; - mmr_t overflow_databuff_vc2 : 1; - mmr_t overflow_databuff_vc0 : 1; - mmr_t overflow_vc2_credit : 1; - mmr_t underflow_vc2_credit : 1; - mmr_t overflow_vc0_credit : 1; - mmr_t underflow_vc0_credit : 1; - mmr_t overflow_iilb_vc2 : 1; - mmr_t underflow_iilb_vc2 : 1; - mmr_t overflow_iilb_vc0 : 1; - mmr_t underflow_iilb_vc0 : 1; - mmr_t overflow_ni1_vc2 : 1; - mmr_t underflow_ni1_vc2 : 1; - mmr_t overflow_ni1_vc0 : 1; - mmr_t underflow_ni1_vc0 : 1; - mmr_t overflow_ni0_vc2 : 1; - mmr_t underflow_ni0_vc2 : 1; - mmr_t overflow_ni0_vc0 : 1; - mmr_t underflow_ni0_vc0 : 1; - } sh_xnmd_first_error_s; -} sh_xnmd_first_error_u_t; -#endif /* ==================================================================== */ /* Register "SH_AUTO_REPLY_ENABLE0" */ /* Automatic Maintenance Reply Enable 0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_auto_reply_enable0_u { - mmr_t sh_auto_reply_enable0_regval; - struct { - mmr_t enable0 : 64; - } sh_auto_reply_enable0_s; -} sh_auto_reply_enable0_u_t; -#else typedef union sh_auto_reply_enable0_u { mmr_t sh_auto_reply_enable0_regval; struct { mmr_t enable0 : 64; } sh_auto_reply_enable0_s; } sh_auto_reply_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_AUTO_REPLY_ENABLE1" */ /* Automatic Maintenance Reply Enable 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_auto_reply_enable1_u { - mmr_t sh_auto_reply_enable1_regval; - struct { - mmr_t enable1 : 64; - } sh_auto_reply_enable1_s; -} sh_auto_reply_enable1_u_t; -#else typedef union sh_auto_reply_enable1_u { mmr_t sh_auto_reply_enable1_regval; struct { mmr_t enable1 : 64; } sh_auto_reply_enable1_s; } sh_auto_reply_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_AUTO_REPLY_HEADER0" */ /* Automatic Maintenance Reply Header 0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_auto_reply_header0_u { - mmr_t sh_auto_reply_header0_regval; - struct { - mmr_t header0 : 64; - } sh_auto_reply_header0_s; -} sh_auto_reply_header0_u_t; -#else typedef union sh_auto_reply_header0_u { mmr_t sh_auto_reply_header0_regval; struct { mmr_t header0 : 64; } sh_auto_reply_header0_s; } sh_auto_reply_header0_u_t; -#endif /* ==================================================================== */ /* Register "SH_AUTO_REPLY_HEADER1" */ /* Automatic Maintenance Reply Header 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_auto_reply_header1_u { - mmr_t sh_auto_reply_header1_regval; - struct { - mmr_t header1 : 64; - } sh_auto_reply_header1_s; -} sh_auto_reply_header1_u_t; -#else typedef union sh_auto_reply_header1_u { mmr_t sh_auto_reply_header1_regval; struct { mmr_t header1 : 64; } sh_auto_reply_header1_s; } sh_auto_reply_header1_u_t; -#endif /* ==================================================================== */ /* Register "SH_ENABLE_RP_AUTO_REPLY" */ /* Enable Automatic Maintenance Reply From Reply Queue */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_enable_rp_auto_reply_u { mmr_t sh_enable_rp_auto_reply_regval; struct { @@ -18184,22 +9749,12 @@ typedef union sh_enable_rp_auto_reply_u { mmr_t reserved_0 : 63; } sh_enable_rp_auto_reply_s; } sh_enable_rp_auto_reply_u_t; -#else -typedef union sh_enable_rp_auto_reply_u { - mmr_t sh_enable_rp_auto_reply_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t enable : 1; - } sh_enable_rp_auto_reply_s; -} sh_enable_rp_auto_reply_u_t; -#endif /* ==================================================================== */ /* Register "SH_ENABLE_RQ_AUTO_REPLY" */ /* Enable Automatic Maintenance Reply From Request Queue */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_enable_rq_auto_reply_u { mmr_t sh_enable_rq_auto_reply_regval; struct { @@ -18207,22 +9762,12 @@ typedef union sh_enable_rq_auto_reply_u { mmr_t reserved_0 : 63; } sh_enable_rq_auto_reply_s; } sh_enable_rq_auto_reply_u_t; -#else -typedef union sh_enable_rq_auto_reply_u { - mmr_t sh_enable_rq_auto_reply_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t enable : 1; - } sh_enable_rq_auto_reply_s; -} sh_enable_rq_auto_reply_u_t; -#endif /* ==================================================================== */ /* Register "SH_REDIRECT_INVAL" */ /* Redirect invalidate to LB instead of PI */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_redirect_inval_u { mmr_t sh_redirect_inval_regval; struct { @@ -18230,22 +9775,12 @@ typedef union sh_redirect_inval_u { mmr_t reserved_0 : 63; } sh_redirect_inval_s; } sh_redirect_inval_u_t; -#else -typedef union sh_redirect_inval_u { - mmr_t sh_redirect_inval_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t redirect : 1; - } sh_redirect_inval_s; -} sh_redirect_inval_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_CNTRL" */ /* Diagnostic Message Control Register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_diag_msg_cntrl_u { mmr_t sh_diag_msg_cntrl_regval; struct { @@ -18258,447 +9793,252 @@ typedef union sh_diag_msg_cntrl_u { mmr_t busy : 1; } sh_diag_msg_cntrl_s; } sh_diag_msg_cntrl_u_t; -#else -typedef union sh_diag_msg_cntrl_u { - mmr_t sh_diag_msg_cntrl_regval; - struct { - mmr_t busy : 1; - mmr_t start : 1; - mmr_t reserved_0 : 48; - mmr_t port : 1; - mmr_t error_inject_enable : 1; - mmr_t error_inject_point : 6; - mmr_t msg_length : 6; - } sh_diag_msg_cntrl_s; -} sh_diag_msg_cntrl_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA0L" */ /* Diagnostic Data, lower 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_diag_msg_data0l_u { - mmr_t sh_diag_msg_data0l_regval; - struct { - mmr_t data_lower : 64; - } sh_diag_msg_data0l_s; -} sh_diag_msg_data0l_u_t; -#else typedef union sh_diag_msg_data0l_u { mmr_t sh_diag_msg_data0l_regval; struct { mmr_t data_lower : 64; } sh_diag_msg_data0l_s; } sh_diag_msg_data0l_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA0U" */ /* Diagnostice Data, upper 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_diag_msg_data0u_u { - mmr_t sh_diag_msg_data0u_regval; - struct { - mmr_t data_upper : 64; - } sh_diag_msg_data0u_s; -} sh_diag_msg_data0u_u_t; -#else typedef union sh_diag_msg_data0u_u { mmr_t sh_diag_msg_data0u_regval; struct { mmr_t data_upper : 64; } sh_diag_msg_data0u_s; } sh_diag_msg_data0u_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA1L" */ /* Diagnostic Data, lower 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_diag_msg_data1l_u { mmr_t sh_diag_msg_data1l_regval; struct { mmr_t data_lower : 64; } sh_diag_msg_data1l_s; } sh_diag_msg_data1l_u_t; -#else -typedef union sh_diag_msg_data1l_u { - mmr_t sh_diag_msg_data1l_regval; - struct { - mmr_t data_lower : 64; - } sh_diag_msg_data1l_s; -} sh_diag_msg_data1l_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA1U" */ /* Diagnostice Data, upper 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_diag_msg_data1u_u { - mmr_t sh_diag_msg_data1u_regval; - struct { - mmr_t data_upper : 64; - } sh_diag_msg_data1u_s; -} sh_diag_msg_data1u_u_t; -#else typedef union sh_diag_msg_data1u_u { mmr_t sh_diag_msg_data1u_regval; struct { mmr_t data_upper : 64; } sh_diag_msg_data1u_s; } sh_diag_msg_data1u_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA2L" */ /* Diagnostic Data, lower 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_diag_msg_data2l_u { - mmr_t sh_diag_msg_data2l_regval; - struct { - mmr_t data_lower : 64; - } sh_diag_msg_data2l_s; -} sh_diag_msg_data2l_u_t; -#else typedef union sh_diag_msg_data2l_u { mmr_t sh_diag_msg_data2l_regval; struct { mmr_t data_lower : 64; } sh_diag_msg_data2l_s; } sh_diag_msg_data2l_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA2U" */ /* Diagnostice Data, upper 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_diag_msg_data2u_u { - mmr_t sh_diag_msg_data2u_regval; - struct { - mmr_t data_upper : 64; - } sh_diag_msg_data2u_s; -} sh_diag_msg_data2u_u_t; -#else typedef union sh_diag_msg_data2u_u { mmr_t sh_diag_msg_data2u_regval; struct { mmr_t data_upper : 64; } sh_diag_msg_data2u_s; } sh_diag_msg_data2u_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA3L" */ /* Diagnostic Data, lower 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_diag_msg_data3l_u { - mmr_t sh_diag_msg_data3l_regval; - struct { - mmr_t data_lower : 64; - } sh_diag_msg_data3l_s; -} sh_diag_msg_data3l_u_t; -#else typedef union sh_diag_msg_data3l_u { mmr_t sh_diag_msg_data3l_regval; struct { mmr_t data_lower : 64; } sh_diag_msg_data3l_s; } sh_diag_msg_data3l_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA3U" */ /* Diagnostice Data, upper 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_diag_msg_data3u_u { - mmr_t sh_diag_msg_data3u_regval; - struct { - mmr_t data_upper : 64; - } sh_diag_msg_data3u_s; -} sh_diag_msg_data3u_u_t; -#else typedef union sh_diag_msg_data3u_u { mmr_t sh_diag_msg_data3u_regval; struct { mmr_t data_upper : 64; } sh_diag_msg_data3u_s; } sh_diag_msg_data3u_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA4L" */ /* Diagnostic Data, lower 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_diag_msg_data4l_u { - mmr_t sh_diag_msg_data4l_regval; - struct { - mmr_t data_lower : 64; - } sh_diag_msg_data4l_s; -} sh_diag_msg_data4l_u_t; -#else typedef union sh_diag_msg_data4l_u { mmr_t sh_diag_msg_data4l_regval; struct { mmr_t data_lower : 64; } sh_diag_msg_data4l_s; } sh_diag_msg_data4l_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA4U" */ /* Diagnostice Data, upper 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_diag_msg_data4u_u { mmr_t sh_diag_msg_data4u_regval; struct { mmr_t data_upper : 64; } sh_diag_msg_data4u_s; } sh_diag_msg_data4u_u_t; -#else -typedef union sh_diag_msg_data4u_u { - mmr_t sh_diag_msg_data4u_regval; - struct { - mmr_t data_upper : 64; - } sh_diag_msg_data4u_s; -} sh_diag_msg_data4u_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA5L" */ /* Diagnostic Data, lower 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_diag_msg_data5l_u { - mmr_t sh_diag_msg_data5l_regval; - struct { - mmr_t data_lower : 64; - } sh_diag_msg_data5l_s; -} sh_diag_msg_data5l_u_t; -#else typedef union sh_diag_msg_data5l_u { mmr_t sh_diag_msg_data5l_regval; struct { mmr_t data_lower : 64; } sh_diag_msg_data5l_s; } sh_diag_msg_data5l_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA5U" */ /* Diagnostice Data, upper 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_diag_msg_data5u_u { - mmr_t sh_diag_msg_data5u_regval; - struct { - mmr_t data_upper : 64; - } sh_diag_msg_data5u_s; -} sh_diag_msg_data5u_u_t; -#else typedef union sh_diag_msg_data5u_u { mmr_t sh_diag_msg_data5u_regval; struct { mmr_t data_upper : 64; } sh_diag_msg_data5u_s; } sh_diag_msg_data5u_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA6L" */ /* Diagnostic Data, lower 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_diag_msg_data6l_u { mmr_t sh_diag_msg_data6l_regval; struct { mmr_t data_lower : 64; } sh_diag_msg_data6l_s; } sh_diag_msg_data6l_u_t; -#else -typedef union sh_diag_msg_data6l_u { - mmr_t sh_diag_msg_data6l_regval; - struct { - mmr_t data_lower : 64; - } sh_diag_msg_data6l_s; -} sh_diag_msg_data6l_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA6U" */ /* Diagnostice Data, upper 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_diag_msg_data6u_u { - mmr_t sh_diag_msg_data6u_regval; - struct { - mmr_t data_upper : 64; - } sh_diag_msg_data6u_s; -} sh_diag_msg_data6u_u_t; -#else typedef union sh_diag_msg_data6u_u { mmr_t sh_diag_msg_data6u_regval; struct { mmr_t data_upper : 64; } sh_diag_msg_data6u_s; } sh_diag_msg_data6u_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA7L" */ /* Diagnostic Data, lower 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_diag_msg_data7l_u { mmr_t sh_diag_msg_data7l_regval; struct { mmr_t data_lower : 64; } sh_diag_msg_data7l_s; } sh_diag_msg_data7l_u_t; -#else -typedef union sh_diag_msg_data7l_u { - mmr_t sh_diag_msg_data7l_regval; - struct { - mmr_t data_lower : 64; - } sh_diag_msg_data7l_s; -} sh_diag_msg_data7l_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA7U" */ /* Diagnostice Data, upper 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_diag_msg_data7u_u { - mmr_t sh_diag_msg_data7u_regval; - struct { - mmr_t data_upper : 64; - } sh_diag_msg_data7u_s; -} sh_diag_msg_data7u_u_t; -#else typedef union sh_diag_msg_data7u_u { mmr_t sh_diag_msg_data7u_regval; struct { mmr_t data_upper : 64; } sh_diag_msg_data7u_s; } sh_diag_msg_data7u_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA8L" */ /* Diagnostic Data, lower 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_diag_msg_data8l_u { mmr_t sh_diag_msg_data8l_regval; struct { mmr_t data_lower : 64; } sh_diag_msg_data8l_s; } sh_diag_msg_data8l_u_t; -#else -typedef union sh_diag_msg_data8l_u { - mmr_t sh_diag_msg_data8l_regval; - struct { - mmr_t data_lower : 64; - } sh_diag_msg_data8l_s; -} sh_diag_msg_data8l_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA8U" */ /* Diagnostice Data, upper 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_diag_msg_data8u_u { - mmr_t sh_diag_msg_data8u_regval; - struct { - mmr_t data_upper : 64; - } sh_diag_msg_data8u_s; -} sh_diag_msg_data8u_u_t; -#else typedef union sh_diag_msg_data8u_u { mmr_t sh_diag_msg_data8u_regval; struct { mmr_t data_upper : 64; } sh_diag_msg_data8u_s; } sh_diag_msg_data8u_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_HDR0" */ /* Diagnostice Data, lower 64 bits of header */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_diag_msg_hdr0_u { - mmr_t sh_diag_msg_hdr0_regval; - struct { - mmr_t header0 : 64; - } sh_diag_msg_hdr0_s; -} sh_diag_msg_hdr0_u_t; -#else typedef union sh_diag_msg_hdr0_u { mmr_t sh_diag_msg_hdr0_regval; struct { mmr_t header0 : 64; } sh_diag_msg_hdr0_s; } sh_diag_msg_hdr0_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_HDR1" */ /* Diagnostice Data, upper 64 bits of header */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_diag_msg_hdr1_u { - mmr_t sh_diag_msg_hdr1_regval; - struct { - mmr_t header1 : 64; - } sh_diag_msg_hdr1_s; -} sh_diag_msg_hdr1_u_t; -#else typedef union sh_diag_msg_hdr1_u { mmr_t sh_diag_msg_hdr1_regval; struct { mmr_t header1 : 64; } sh_diag_msg_hdr1_s; } sh_diag_msg_hdr1_u_t; -#endif /* ==================================================================== */ /* Register "SH_DEBUG_SELECT" */ /* SHub Debug Port Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_debug_select_u { mmr_t sh_debug_select_regval; struct { @@ -18724,40 +10064,12 @@ typedef union sh_debug_select_u { mmr_t trigger_enable : 1; } sh_debug_select_s; } sh_debug_select_u_t; -#else -typedef union sh_debug_select_u { - mmr_t sh_debug_select_regval; - struct { - mmr_t trigger_enable : 1; - mmr_t reserved_0 : 3; - mmr_t sel_ii : 9; - mmr_t debug_ii_sel : 3; - mmr_t nibble7_chiplet_sel : 3; - mmr_t nibble7_nibble_sel : 3; - mmr_t nibble6_chiplet_sel : 3; - mmr_t nibble6_nibble_sel : 3; - mmr_t nibble5_chiplet_sel : 3; - mmr_t nibble5_nibble_sel : 3; - mmr_t nibble4_chiplet_sel : 3; - mmr_t nibble4_nibble_sel : 3; - mmr_t nibble3_chiplet_sel : 3; - mmr_t nibble3_nibble_sel : 3; - mmr_t nibble2_chiplet_sel : 3; - mmr_t nibble2_nibble_sel : 3; - mmr_t nibble1_chiplet_sel : 3; - mmr_t nibble1_nibble_sel : 3; - mmr_t nibble0_chiplet_sel : 3; - mmr_t nibble0_nibble_sel : 3; - } sh_debug_select_s; -} sh_debug_select_u_t; -#endif /* ==================================================================== */ /* Register "SH_TRIGGER_COMPARE_MASK" */ /* SHub Trigger Compare Mask */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_trigger_compare_mask_u { mmr_t sh_trigger_compare_mask_regval; struct { @@ -18765,22 +10077,12 @@ typedef union sh_trigger_compare_mask_u { mmr_t reserved_0 : 32; } sh_trigger_compare_mask_s; } sh_trigger_compare_mask_u_t; -#else -typedef union sh_trigger_compare_mask_u { - mmr_t sh_trigger_compare_mask_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t mask : 32; - } sh_trigger_compare_mask_s; -} sh_trigger_compare_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_TRIGGER_COMPARE_PATTERN" */ /* SHub Trigger Compare Pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_trigger_compare_pattern_u { mmr_t sh_trigger_compare_pattern_regval; struct { @@ -18788,22 +10090,12 @@ typedef union sh_trigger_compare_pattern_u { mmr_t reserved_0 : 32; } sh_trigger_compare_pattern_s; } sh_trigger_compare_pattern_u_t; -#else -typedef union sh_trigger_compare_pattern_u { - mmr_t sh_trigger_compare_pattern_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t data : 32; - } sh_trigger_compare_pattern_s; -} sh_trigger_compare_pattern_u_t; -#endif /* ==================================================================== */ /* Register "SH_TRIGGER_SEL" */ /* Trigger select for SHUB debug port */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_trigger_sel_u { mmr_t sh_trigger_sel_regval; struct { @@ -18841,52 +10133,12 @@ typedef union sh_trigger_sel_u { mmr_t reserved_15 : 1; } sh_trigger_sel_s; } sh_trigger_sel_u_t; -#else -typedef union sh_trigger_sel_u { - mmr_t sh_trigger_sel_regval; - struct { - mmr_t reserved_15 : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_input_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_input_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_input_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_input_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_input_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_input_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_input_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_input_sel : 3; - } sh_trigger_sel_s; -} sh_trigger_sel_u_t; -#endif /* ==================================================================== */ /* Register "SH_STOP_CLK_CONTROL" */ /* Stop Clock Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_stop_clk_control_u { mmr_t sh_stop_clk_control_regval; struct { @@ -18897,25 +10149,12 @@ typedef union sh_stop_clk_control_u { mmr_t reserved_0 : 56; } sh_stop_clk_control_s; } sh_stop_clk_control_u_t; -#else -typedef union sh_stop_clk_control_u { - mmr_t sh_stop_clk_control_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t mode : 1; - mmr_t polarity : 1; - mmr_t event : 1; - mmr_t stimulus : 5; - } sh_stop_clk_control_s; -} sh_stop_clk_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_STOP_CLK_DELAY_PHASE" */ /* Stop Clock Delay Phase */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_stop_clk_delay_phase_u { mmr_t sh_stop_clk_delay_phase_regval; struct { @@ -18923,43 +10162,24 @@ typedef union sh_stop_clk_delay_phase_u { mmr_t reserved_0 : 56; } sh_stop_clk_delay_phase_s; } sh_stop_clk_delay_phase_u_t; -#else -typedef union sh_stop_clk_delay_phase_u { - mmr_t sh_stop_clk_delay_phase_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t delay : 8; - } sh_stop_clk_delay_phase_s; -} sh_stop_clk_delay_phase_u_t; -#endif /* ==================================================================== */ /* Register "SH_TSF_ARM_MASK" */ /* Trigger sequencing facility arm mask */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_tsf_arm_mask_u { mmr_t sh_tsf_arm_mask_regval; struct { mmr_t mask : 64; } sh_tsf_arm_mask_s; } sh_tsf_arm_mask_u_t; -#else -typedef union sh_tsf_arm_mask_u { - mmr_t sh_tsf_arm_mask_regval; - struct { - mmr_t mask : 64; - } sh_tsf_arm_mask_s; -} sh_tsf_arm_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_TSF_COUNTER_PRESETS" */ /* Trigger sequencing facility counter presets */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_tsf_counter_presets_u { mmr_t sh_tsf_counter_presets_regval; struct { @@ -18969,24 +10189,12 @@ typedef union sh_tsf_counter_presets_u { mmr_t count_8a : 8; } sh_tsf_counter_presets_s; } sh_tsf_counter_presets_u_t; -#else -typedef union sh_tsf_counter_presets_u { - mmr_t sh_tsf_counter_presets_regval; - struct { - mmr_t count_8a : 8; - mmr_t count_8b : 8; - mmr_t count_16 : 16; - mmr_t count_32 : 32; - } sh_tsf_counter_presets_s; -} sh_tsf_counter_presets_u_t; -#endif /* ==================================================================== */ /* Register "SH_TSF_DECREMENT_CTL" */ /* Trigger sequencing facility counter decrement control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_tsf_decrement_ctl_u { mmr_t sh_tsf_decrement_ctl_regval; struct { @@ -18994,22 +10202,12 @@ typedef union sh_tsf_decrement_ctl_u { mmr_t reserved_0 : 48; } sh_tsf_decrement_ctl_s; } sh_tsf_decrement_ctl_u_t; -#else -typedef union sh_tsf_decrement_ctl_u { - mmr_t sh_tsf_decrement_ctl_regval; - struct { - mmr_t reserved_0 : 48; - mmr_t ctl : 16; - } sh_tsf_decrement_ctl_s; -} sh_tsf_decrement_ctl_u_t; -#endif /* ==================================================================== */ /* Register "SH_TSF_DIAG_MSG_CTL" */ /* Trigger sequencing facility diagnostic message control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_tsf_diag_msg_ctl_u { mmr_t sh_tsf_diag_msg_ctl_regval; struct { @@ -19017,43 +10215,24 @@ typedef union sh_tsf_diag_msg_ctl_u { mmr_t reserved_0 : 56; } sh_tsf_diag_msg_ctl_s; } sh_tsf_diag_msg_ctl_u_t; -#else -typedef union sh_tsf_diag_msg_ctl_u { - mmr_t sh_tsf_diag_msg_ctl_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t enable : 8; - } sh_tsf_diag_msg_ctl_s; -} sh_tsf_diag_msg_ctl_u_t; -#endif /* ==================================================================== */ /* Register "SH_TSF_DISARM_MASK" */ /* Trigger sequencing facility disarm mask */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_tsf_disarm_mask_u { mmr_t sh_tsf_disarm_mask_regval; struct { mmr_t mask : 64; } sh_tsf_disarm_mask_s; } sh_tsf_disarm_mask_u_t; -#else -typedef union sh_tsf_disarm_mask_u { - mmr_t sh_tsf_disarm_mask_regval; - struct { - mmr_t mask : 64; - } sh_tsf_disarm_mask_s; -} sh_tsf_disarm_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_TSF_ENABLE_CTL" */ /* Trigger sequencing facility counter enable control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_tsf_enable_ctl_u { mmr_t sh_tsf_enable_ctl_regval; struct { @@ -19061,22 +10240,12 @@ typedef union sh_tsf_enable_ctl_u { mmr_t reserved_0 : 48; } sh_tsf_enable_ctl_s; } sh_tsf_enable_ctl_u_t; -#else -typedef union sh_tsf_enable_ctl_u { - mmr_t sh_tsf_enable_ctl_regval; - struct { - mmr_t reserved_0 : 48; - mmr_t ctl : 16; - } sh_tsf_enable_ctl_s; -} sh_tsf_enable_ctl_u_t; -#endif /* ==================================================================== */ /* Register "SH_TSF_SOFTWARE_ARM" */ /* Trigger sequencing facility software arm */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_tsf_software_arm_u { mmr_t sh_tsf_software_arm_regval; struct { @@ -19091,29 +10260,12 @@ typedef union sh_tsf_software_arm_u { mmr_t reserved_0 : 56; } sh_tsf_software_arm_s; } sh_tsf_software_arm_u_t; -#else -typedef union sh_tsf_software_arm_u { - mmr_t sh_tsf_software_arm_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t bit7 : 1; - mmr_t bit6 : 1; - mmr_t bit5 : 1; - mmr_t bit4 : 1; - mmr_t bit3 : 1; - mmr_t bit2 : 1; - mmr_t bit1 : 1; - mmr_t bit0 : 1; - } sh_tsf_software_arm_s; -} sh_tsf_software_arm_u_t; -#endif /* ==================================================================== */ /* Register "SH_TSF_SOFTWARE_DISARM" */ /* Trigger sequencing facility software disarm */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_tsf_software_disarm_u { mmr_t sh_tsf_software_disarm_regval; struct { @@ -19128,29 +10280,12 @@ typedef union sh_tsf_software_disarm_u { mmr_t reserved_0 : 56; } sh_tsf_software_disarm_s; } sh_tsf_software_disarm_u_t; -#else -typedef union sh_tsf_software_disarm_u { - mmr_t sh_tsf_software_disarm_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t bit7 : 1; - mmr_t bit6 : 1; - mmr_t bit5 : 1; - mmr_t bit4 : 1; - mmr_t bit3 : 1; - mmr_t bit2 : 1; - mmr_t bit1 : 1; - mmr_t bit0 : 1; - } sh_tsf_software_disarm_s; -} sh_tsf_software_disarm_u_t; -#endif /* ==================================================================== */ /* Register "SH_TSF_SOFTWARE_TRIGGERED" */ /* Trigger sequencing facility software triggered */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_tsf_software_triggered_u { mmr_t sh_tsf_software_triggered_regval; struct { @@ -19165,71 +10300,36 @@ typedef union sh_tsf_software_triggered_u { mmr_t reserved_0 : 56; } sh_tsf_software_triggered_s; } sh_tsf_software_triggered_u_t; -#else -typedef union sh_tsf_software_triggered_u { - mmr_t sh_tsf_software_triggered_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t bit7 : 1; - mmr_t bit6 : 1; - mmr_t bit5 : 1; - mmr_t bit4 : 1; - mmr_t bit3 : 1; - mmr_t bit2 : 1; - mmr_t bit1 : 1; - mmr_t bit0 : 1; - } sh_tsf_software_triggered_s; -} sh_tsf_software_triggered_u_t; -#endif /* ==================================================================== */ /* Register "SH_TSF_TRIGGER_MASK" */ /* Trigger sequencing facility trigger mask */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_tsf_trigger_mask_u { - mmr_t sh_tsf_trigger_mask_regval; - struct { - mmr_t mask : 64; - } sh_tsf_trigger_mask_s; -} sh_tsf_trigger_mask_u_t; -#else typedef union sh_tsf_trigger_mask_u { mmr_t sh_tsf_trigger_mask_regval; struct { mmr_t mask : 64; } sh_tsf_trigger_mask_s; } sh_tsf_trigger_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_VEC_DATA" */ /* Vector Write Request Message Data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_vec_data_u { - mmr_t sh_vec_data_regval; - struct { - mmr_t data : 64; - } sh_vec_data_s; -} sh_vec_data_u_t; -#else typedef union sh_vec_data_u { mmr_t sh_vec_data_regval; struct { mmr_t data : 64; } sh_vec_data_s; } sh_vec_data_u_t; -#endif /* ==================================================================== */ /* Register "SH_VEC_PARMS" */ /* Vector Message Parameters Register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_vec_parms_u { mmr_t sh_vec_parms_regval; struct { @@ -19243,133 +10343,72 @@ typedef union sh_vec_parms_u { mmr_t busy : 1; } sh_vec_parms_s; } sh_vec_parms_u_t; -#else -typedef union sh_vec_parms_u { - mmr_t sh_vec_parms_regval; - struct { - mmr_t busy : 1; - mmr_t start : 1; - mmr_t reserved_1 : 16; - mmr_t pio_id : 11; - mmr_t address : 32; - mmr_t reserved_0 : 1; - mmr_t ni_port : 1; - mmr_t type : 1; - } sh_vec_parms_s; -} sh_vec_parms_u_t; -#endif /* ==================================================================== */ /* Register "SH_VEC_ROUTE" */ /* Vector Request Message Route */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_vec_route_u { - mmr_t sh_vec_route_regval; - struct { - mmr_t route : 64; - } sh_vec_route_s; -} sh_vec_route_u_t; -#else typedef union sh_vec_route_u { mmr_t sh_vec_route_regval; struct { mmr_t route : 64; } sh_vec_route_s; } sh_vec_route_u_t; -#endif /* ==================================================================== */ /* Register "SH_CPU_PERM" */ /* CPU MMR Access Permission Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_cpu_perm_u { - mmr_t sh_cpu_perm_regval; - struct { - mmr_t access_bits : 64; - } sh_cpu_perm_s; -} sh_cpu_perm_u_t; -#else typedef union sh_cpu_perm_u { mmr_t sh_cpu_perm_regval; struct { mmr_t access_bits : 64; } sh_cpu_perm_s; } sh_cpu_perm_u_t; -#endif /* ==================================================================== */ /* Register "SH_CPU_PERM_OVR" */ /* CPU MMR Access Permission Override */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_cpu_perm_ovr_u { mmr_t sh_cpu_perm_ovr_regval; struct { mmr_t override : 64; } sh_cpu_perm_ovr_s; } sh_cpu_perm_ovr_u_t; -#else -typedef union sh_cpu_perm_ovr_u { - mmr_t sh_cpu_perm_ovr_regval; - struct { - mmr_t override : 64; - } sh_cpu_perm_ovr_s; -} sh_cpu_perm_ovr_u_t; -#endif /* ==================================================================== */ /* Register "SH_EXT_IO_PERM" */ /* External IO MMR Access Permission Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_ext_io_perm_u { - mmr_t sh_ext_io_perm_regval; - struct { - mmr_t access_bits : 64; - } sh_ext_io_perm_s; -} sh_ext_io_perm_u_t; -#else typedef union sh_ext_io_perm_u { mmr_t sh_ext_io_perm_regval; struct { mmr_t access_bits : 64; } sh_ext_io_perm_s; } sh_ext_io_perm_u_t; -#endif /* ==================================================================== */ /* Register "SH_EXT_IOI_ACCESS" */ /* External IO Interrupt Access Permission Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_ext_ioi_access_u { - mmr_t sh_ext_ioi_access_regval; - struct { - mmr_t access_bits : 64; - } sh_ext_ioi_access_s; -} sh_ext_ioi_access_u_t; -#else typedef union sh_ext_ioi_access_u { mmr_t sh_ext_ioi_access_regval; struct { mmr_t access_bits : 64; } sh_ext_ioi_access_s; } sh_ext_ioi_access_u_t; -#endif /* ==================================================================== */ /* Register "SH_GC_FIL_CTRL" */ /* SHub Global Clock Filter Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gc_fil_ctrl_u { mmr_t sh_gc_fil_ctrl_regval; struct { @@ -19386,31 +10425,12 @@ typedef union sh_gc_fil_ctrl_u { mmr_t reserved_4 : 6; } sh_gc_fil_ctrl_s; } sh_gc_fil_ctrl_u_t; -#else -typedef union sh_gc_fil_ctrl_u { - mmr_t sh_gc_fil_ctrl_regval; - struct { - mmr_t reserved_4 : 6; - mmr_t error_counter : 10; - mmr_t reserved_3 : 2; - mmr_t dropout_thresh : 10; - mmr_t reserved_2 : 2; - mmr_t dropout_counter : 10; - mmr_t reserved_1 : 3; - mmr_t mask_enable : 1; - mmr_t mask_counter : 12; - mmr_t reserved_0 : 3; - mmr_t offset : 5; - } sh_gc_fil_ctrl_s; -} sh_gc_fil_ctrl_u_t; -#endif /* ==================================================================== */ /* Register "SH_GC_SRC_CTRL" */ /* SHub Global Clock Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gc_src_ctrl_u { mmr_t sh_gc_src_ctrl_regval; struct { @@ -19426,30 +10446,12 @@ typedef union sh_gc_src_ctrl_u { mmr_t reserved_4 : 30; } sh_gc_src_ctrl_s; } sh_gc_src_ctrl_u_t; -#else -typedef union sh_gc_src_ctrl_u { - mmr_t sh_gc_src_ctrl_regval; - struct { - mmr_t reserved_4 : 30; - mmr_t source_sel : 2; - mmr_t reserved_3 : 3; - mmr_t toggle_bit : 1; - mmr_t reserved_2 : 2; - mmr_t counter : 10; - mmr_t reserved_1 : 2; - mmr_t max_count : 10; - mmr_t reserved_0 : 3; - mmr_t enable_counter : 1; - } sh_gc_src_ctrl_s; -} sh_gc_src_ctrl_u_t; -#endif /* ==================================================================== */ /* Register "SH_HARD_RESET" */ /* SHub Hard Reset */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_hard_reset_u { mmr_t sh_hard_reset_regval; struct { @@ -19457,85 +10459,48 @@ typedef union sh_hard_reset_u { mmr_t reserved_0 : 63; } sh_hard_reset_s; } sh_hard_reset_u_t; -#else -typedef union sh_hard_reset_u { - mmr_t sh_hard_reset_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t hard_reset : 1; - } sh_hard_reset_s; -} sh_hard_reset_u_t; -#endif /* ==================================================================== */ /* Register "SH_IO_PERM" */ /* II MMR Access Permission Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_io_perm_u { mmr_t sh_io_perm_regval; struct { mmr_t access_bits : 64; } sh_io_perm_s; } sh_io_perm_u_t; -#else -typedef union sh_io_perm_u { - mmr_t sh_io_perm_regval; - struct { - mmr_t access_bits : 64; - } sh_io_perm_s; -} sh_io_perm_u_t; -#endif /* ==================================================================== */ /* Register "SH_IOI_ACCESS" */ /* II Interrupt Access Permission Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_ioi_access_u { - mmr_t sh_ioi_access_regval; - struct { - mmr_t access_bits : 64; - } sh_ioi_access_s; -} sh_ioi_access_u_t; -#else typedef union sh_ioi_access_u { mmr_t sh_ioi_access_regval; struct { mmr_t access_bits : 64; } sh_ioi_access_s; } sh_ioi_access_u_t; -#endif /* ==================================================================== */ /* Register "SH_IPI_ACCESS" */ /* CPU interrupt Access Permission Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ipi_access_u { mmr_t sh_ipi_access_regval; struct { mmr_t access_bits : 64; } sh_ipi_access_s; } sh_ipi_access_u_t; -#else -typedef union sh_ipi_access_u { - mmr_t sh_ipi_access_regval; - struct { - mmr_t access_bits : 64; - } sh_ipi_access_s; -} sh_ipi_access_u_t; -#endif /* ==================================================================== */ /* Register "SH_JTAG_CONFIG" */ /* SHub JTAG configuration */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_jtag_config_u { mmr_t sh_jtag_config_regval; struct { @@ -19559,38 +10524,12 @@ typedef union sh_jtag_config_u { mmr_t reserved_0 : 8; } sh_jtag_config_s; } sh_jtag_config_u_t; -#else -typedef union sh_jtag_config_u { - mmr_t sh_jtag_config_regval; - struct { - mmr_t reserved_0 : 8; - mmr_t gtl_config_re : 1; - mmr_t fsb_config_aux : 2; - mmr_t fsb_config_enable_bist : 1; - mmr_t fsb_config_output_tristate : 4; - mmr_t fsb_config_clock_ratio : 5; - mmr_t fsb_config_enable_bus_parking : 1; - mmr_t fsb_config_sample_binit : 1; - mmr_t fsb_config_ioq_depth : 1; - mmr_t jtag_mci_override : 1; - mmr_t jtag_mci_target : 14; - mmr_t jtag_mci_reset_delay : 4; - mmr_t wrt90_override : 1; - mmr_t wrt90_overrider : 1; - mmr_t wrt90_target : 14; - mmr_t ii_clk_sel : 2; - mmr_t ni_clk_sel : 1; - mmr_t md_clk_sel : 2; - } sh_jtag_config_s; -} sh_jtag_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_SHUB_ID" */ /* SHub ID Number */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_shub_id_u { mmr_t sh_shub_id_regval; struct { @@ -19608,116 +10547,60 @@ typedef union sh_shub_id_u { mmr_t reserved_3 : 7; } sh_shub_id_s; } sh_shub_id_u_t; -#else -typedef union sh_shub_id_u { - mmr_t sh_shub_id_regval; - struct { - mmr_t reserved_3 : 7; - mmr_t ni_port : 1; - mmr_t reserved_2 : 3; - mmr_t nodes_per_bit : 5; - mmr_t reserved_1 : 2; - mmr_t sharing_mode : 2; - mmr_t reserved_0 : 1; - mmr_t node_id : 11; - mmr_t revision : 4; - mmr_t part_number : 16; - mmr_t manufacturer : 11; - mmr_t force1 : 1; - } sh_shub_id_s; -} sh_shub_id_u_t; -#endif /* ==================================================================== */ /* Register "SH_SHUBS_PRESENT0" */ /* Shubs 0 - 63 Present. Used for invalidate generation */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_shubs_present0_u { - mmr_t sh_shubs_present0_regval; - struct { - mmr_t shubs_present0 : 64; - } sh_shubs_present0_s; -} sh_shubs_present0_u_t; -#else typedef union sh_shubs_present0_u { mmr_t sh_shubs_present0_regval; struct { mmr_t shubs_present0 : 64; } sh_shubs_present0_s; } sh_shubs_present0_u_t; -#endif /* ==================================================================== */ /* Register "SH_SHUBS_PRESENT1" */ /* Shubs 64 - 127 Present. Used for invalidate generation */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_shubs_present1_u { mmr_t sh_shubs_present1_regval; struct { mmr_t shubs_present1 : 64; } sh_shubs_present1_s; } sh_shubs_present1_u_t; -#else -typedef union sh_shubs_present1_u { - mmr_t sh_shubs_present1_regval; - struct { - mmr_t shubs_present1 : 64; - } sh_shubs_present1_s; -} sh_shubs_present1_u_t; -#endif /* ==================================================================== */ /* Register "SH_SHUBS_PRESENT2" */ /* Shubs 128 - 191 Present. Used for invalidate generation */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_shubs_present2_u { - mmr_t sh_shubs_present2_regval; - struct { - mmr_t shubs_present2 : 64; - } sh_shubs_present2_s; -} sh_shubs_present2_u_t; -#else typedef union sh_shubs_present2_u { mmr_t sh_shubs_present2_regval; struct { mmr_t shubs_present2 : 64; } sh_shubs_present2_s; } sh_shubs_present2_u_t; -#endif /* ==================================================================== */ /* Register "SH_SHUBS_PRESENT3" */ /* Shubs 192 - 255 Present. Used for invalidate generation */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_shubs_present3_u { - mmr_t sh_shubs_present3_regval; - struct { - mmr_t shubs_present3 : 64; - } sh_shubs_present3_s; -} sh_shubs_present3_u_t; -#else typedef union sh_shubs_present3_u { mmr_t sh_shubs_present3_regval; struct { mmr_t shubs_present3 : 64; } sh_shubs_present3_s; } sh_shubs_present3_u_t; -#endif /* ==================================================================== */ /* Register "SH_SOFT_RESET" */ /* SHub Soft Reset */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_soft_reset_u { mmr_t sh_soft_reset_regval; struct { @@ -19725,22 +10608,12 @@ typedef union sh_soft_reset_u { mmr_t reserved_0 : 63; } sh_soft_reset_s; } sh_soft_reset_u_t; -#else -typedef union sh_soft_reset_u { - mmr_t sh_soft_reset_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t soft_reset : 1; - } sh_soft_reset_s; -} sh_soft_reset_u_t; -#endif /* ==================================================================== */ /* Register "SH_FIRST_ERROR" */ /* Shub Global First Error Flags */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_first_error_u { mmr_t sh_first_error_regval; struct { @@ -19748,22 +10621,12 @@ typedef union sh_first_error_u { mmr_t reserved_0 : 45; } sh_first_error_s; } sh_first_error_u_t; -#else -typedef union sh_first_error_u { - mmr_t sh_first_error_regval; - struct { - mmr_t reserved_0 : 45; - mmr_t first_error : 19; - } sh_first_error_s; -} sh_first_error_u_t; -#endif /* ==================================================================== */ /* Register "SH_II_HW_TIME_STAMP" */ /* II hardware error time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ii_hw_time_stamp_u { mmr_t sh_ii_hw_time_stamp_regval; struct { @@ -19771,22 +10634,12 @@ typedef union sh_ii_hw_time_stamp_u { mmr_t valid : 1; } sh_ii_hw_time_stamp_s; } sh_ii_hw_time_stamp_u_t; -#else -typedef union sh_ii_hw_time_stamp_u { - mmr_t sh_ii_hw_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_ii_hw_time_stamp_s; -} sh_ii_hw_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_HW_TIME_STAMP" */ /* LB hardware error time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_hw_time_stamp_u { mmr_t sh_lb_hw_time_stamp_regval; struct { @@ -19794,22 +10647,12 @@ typedef union sh_lb_hw_time_stamp_u { mmr_t valid : 1; } sh_lb_hw_time_stamp_s; } sh_lb_hw_time_stamp_u_t; -#else -typedef union sh_lb_hw_time_stamp_u { - mmr_t sh_lb_hw_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_lb_hw_time_stamp_s; -} sh_lb_hw_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_COR_TIME_STAMP" */ /* MD correctable error time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_cor_time_stamp_u { mmr_t sh_md_cor_time_stamp_regval; struct { @@ -19817,22 +10660,12 @@ typedef union sh_md_cor_time_stamp_u { mmr_t valid : 1; } sh_md_cor_time_stamp_s; } sh_md_cor_time_stamp_u_t; -#else -typedef union sh_md_cor_time_stamp_u { - mmr_t sh_md_cor_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_md_cor_time_stamp_s; -} sh_md_cor_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_HW_TIME_STAMP" */ /* MD hardware error time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_hw_time_stamp_u { mmr_t sh_md_hw_time_stamp_regval; struct { @@ -19840,22 +10673,12 @@ typedef union sh_md_hw_time_stamp_u { mmr_t valid : 1; } sh_md_hw_time_stamp_s; } sh_md_hw_time_stamp_u_t; -#else -typedef union sh_md_hw_time_stamp_u { - mmr_t sh_md_hw_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_md_hw_time_stamp_s; -} sh_md_hw_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_UNCOR_TIME_STAMP" */ /* MD uncorrectable error time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_uncor_time_stamp_u { mmr_t sh_md_uncor_time_stamp_regval; struct { @@ -19863,22 +10686,12 @@ typedef union sh_md_uncor_time_stamp_u { mmr_t valid : 1; } sh_md_uncor_time_stamp_s; } sh_md_uncor_time_stamp_u_t; -#else -typedef union sh_md_uncor_time_stamp_u { - mmr_t sh_md_uncor_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_md_uncor_time_stamp_s; -} sh_md_uncor_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_COR_TIME_STAMP" */ /* PI correctable error time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_cor_time_stamp_u { mmr_t sh_pi_cor_time_stamp_regval; struct { @@ -19886,22 +10699,12 @@ typedef union sh_pi_cor_time_stamp_u { mmr_t valid : 1; } sh_pi_cor_time_stamp_s; } sh_pi_cor_time_stamp_u_t; -#else -typedef union sh_pi_cor_time_stamp_u { - mmr_t sh_pi_cor_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_pi_cor_time_stamp_s; -} sh_pi_cor_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_HW_TIME_STAMP" */ /* PI hardware error time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_hw_time_stamp_u { mmr_t sh_pi_hw_time_stamp_regval; struct { @@ -19909,22 +10712,12 @@ typedef union sh_pi_hw_time_stamp_u { mmr_t valid : 1; } sh_pi_hw_time_stamp_s; } sh_pi_hw_time_stamp_u_t; -#else -typedef union sh_pi_hw_time_stamp_u { - mmr_t sh_pi_hw_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_pi_hw_time_stamp_s; -} sh_pi_hw_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_UNCOR_TIME_STAMP" */ /* PI uncorrectable error time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_uncor_time_stamp_u { mmr_t sh_pi_uncor_time_stamp_regval; struct { @@ -19932,22 +10725,12 @@ typedef union sh_pi_uncor_time_stamp_u { mmr_t valid : 1; } sh_pi_uncor_time_stamp_s; } sh_pi_uncor_time_stamp_u_t; -#else -typedef union sh_pi_uncor_time_stamp_u { - mmr_t sh_pi_uncor_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_pi_uncor_time_stamp_s; -} sh_pi_uncor_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC0_ADV_TIME_STAMP" */ /* Proc 0 advisory time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc0_adv_time_stamp_u { mmr_t sh_proc0_adv_time_stamp_regval; struct { @@ -19955,22 +10738,12 @@ typedef union sh_proc0_adv_time_stamp_u { mmr_t valid : 1; } sh_proc0_adv_time_stamp_s; } sh_proc0_adv_time_stamp_u_t; -#else -typedef union sh_proc0_adv_time_stamp_u { - mmr_t sh_proc0_adv_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_proc0_adv_time_stamp_s; -} sh_proc0_adv_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC0_ERR_TIME_STAMP" */ /* Proc 0 error time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc0_err_time_stamp_u { mmr_t sh_proc0_err_time_stamp_regval; struct { @@ -19978,22 +10751,12 @@ typedef union sh_proc0_err_time_stamp_u { mmr_t valid : 1; } sh_proc0_err_time_stamp_s; } sh_proc0_err_time_stamp_u_t; -#else -typedef union sh_proc0_err_time_stamp_u { - mmr_t sh_proc0_err_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_proc0_err_time_stamp_s; -} sh_proc0_err_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC1_ADV_TIME_STAMP" */ /* Proc 1 advisory time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc1_adv_time_stamp_u { mmr_t sh_proc1_adv_time_stamp_regval; struct { @@ -20001,22 +10764,12 @@ typedef union sh_proc1_adv_time_stamp_u { mmr_t valid : 1; } sh_proc1_adv_time_stamp_s; } sh_proc1_adv_time_stamp_u_t; -#else -typedef union sh_proc1_adv_time_stamp_u { - mmr_t sh_proc1_adv_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_proc1_adv_time_stamp_s; -} sh_proc1_adv_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC1_ERR_TIME_STAMP" */ /* Proc 1 error time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc1_err_time_stamp_u { mmr_t sh_proc1_err_time_stamp_regval; struct { @@ -20024,22 +10777,12 @@ typedef union sh_proc1_err_time_stamp_u { mmr_t valid : 1; } sh_proc1_err_time_stamp_s; } sh_proc1_err_time_stamp_u_t; -#else -typedef union sh_proc1_err_time_stamp_u { - mmr_t sh_proc1_err_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_proc1_err_time_stamp_s; -} sh_proc1_err_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC2_ADV_TIME_STAMP" */ /* Proc 2 advisory time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc2_adv_time_stamp_u { mmr_t sh_proc2_adv_time_stamp_regval; struct { @@ -20047,22 +10790,12 @@ typedef union sh_proc2_adv_time_stamp_u { mmr_t valid : 1; } sh_proc2_adv_time_stamp_s; } sh_proc2_adv_time_stamp_u_t; -#else -typedef union sh_proc2_adv_time_stamp_u { - mmr_t sh_proc2_adv_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_proc2_adv_time_stamp_s; -} sh_proc2_adv_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC2_ERR_TIME_STAMP" */ /* Proc 2 error time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc2_err_time_stamp_u { mmr_t sh_proc2_err_time_stamp_regval; struct { @@ -20070,22 +10803,12 @@ typedef union sh_proc2_err_time_stamp_u { mmr_t valid : 1; } sh_proc2_err_time_stamp_s; } sh_proc2_err_time_stamp_u_t; -#else -typedef union sh_proc2_err_time_stamp_u { - mmr_t sh_proc2_err_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_proc2_err_time_stamp_s; -} sh_proc2_err_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC3_ADV_TIME_STAMP" */ /* Proc 3 advisory time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc3_adv_time_stamp_u { mmr_t sh_proc3_adv_time_stamp_regval; struct { @@ -20093,22 +10816,12 @@ typedef union sh_proc3_adv_time_stamp_u { mmr_t valid : 1; } sh_proc3_adv_time_stamp_s; } sh_proc3_adv_time_stamp_u_t; -#else -typedef union sh_proc3_adv_time_stamp_u { - mmr_t sh_proc3_adv_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_proc3_adv_time_stamp_s; -} sh_proc3_adv_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC3_ERR_TIME_STAMP" */ /* Proc 3 error time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc3_err_time_stamp_u { mmr_t sh_proc3_err_time_stamp_regval; struct { @@ -20116,22 +10829,12 @@ typedef union sh_proc3_err_time_stamp_u { mmr_t valid : 1; } sh_proc3_err_time_stamp_s; } sh_proc3_err_time_stamp_u_t; -#else -typedef union sh_proc3_err_time_stamp_u { - mmr_t sh_proc3_err_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_proc3_err_time_stamp_s; -} sh_proc3_err_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_COR_TIME_STAMP" */ /* XN correctable error time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_cor_time_stamp_u { mmr_t sh_xn_cor_time_stamp_regval; struct { @@ -20139,22 +10842,12 @@ typedef union sh_xn_cor_time_stamp_u { mmr_t valid : 1; } sh_xn_cor_time_stamp_s; } sh_xn_cor_time_stamp_u_t; -#else -typedef union sh_xn_cor_time_stamp_u { - mmr_t sh_xn_cor_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_xn_cor_time_stamp_s; -} sh_xn_cor_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_HW_TIME_STAMP" */ /* XN hardware error time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_hw_time_stamp_u { mmr_t sh_xn_hw_time_stamp_regval; struct { @@ -20162,22 +10855,12 @@ typedef union sh_xn_hw_time_stamp_u { mmr_t valid : 1; } sh_xn_hw_time_stamp_s; } sh_xn_hw_time_stamp_u_t; -#else -typedef union sh_xn_hw_time_stamp_u { - mmr_t sh_xn_hw_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_xn_hw_time_stamp_s; -} sh_xn_hw_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_UNCOR_TIME_STAMP" */ /* XN uncorrectable error time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_uncor_time_stamp_u { mmr_t sh_xn_uncor_time_stamp_regval; struct { @@ -20185,22 +10868,12 @@ typedef union sh_xn_uncor_time_stamp_u { mmr_t valid : 1; } sh_xn_uncor_time_stamp_s; } sh_xn_uncor_time_stamp_u_t; -#else -typedef union sh_xn_uncor_time_stamp_u { - mmr_t sh_xn_uncor_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_xn_uncor_time_stamp_s; -} sh_xn_uncor_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_DEBUG_PORT" */ /* SHub Debug Port */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_debug_port_u { mmr_t sh_debug_port_regval; struct { @@ -20215,29 +10888,12 @@ typedef union sh_debug_port_u { mmr_t reserved_0 : 32; } sh_debug_port_s; } sh_debug_port_u_t; -#else -typedef union sh_debug_port_u { - mmr_t sh_debug_port_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t debug_nibble7 : 4; - mmr_t debug_nibble6 : 4; - mmr_t debug_nibble5 : 4; - mmr_t debug_nibble4 : 4; - mmr_t debug_nibble3 : 4; - mmr_t debug_nibble2 : 4; - mmr_t debug_nibble1 : 4; - mmr_t debug_nibble0 : 4; - } sh_debug_port_s; -} sh_debug_port_u_t; -#endif /* ==================================================================== */ /* Register "SH_II_DEBUG_DATA" */ /* II Debug Data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ii_debug_data_u { mmr_t sh_ii_debug_data_regval; struct { @@ -20245,22 +10901,12 @@ typedef union sh_ii_debug_data_u { mmr_t reserved_0 : 32; } sh_ii_debug_data_s; } sh_ii_debug_data_u_t; -#else -typedef union sh_ii_debug_data_u { - mmr_t sh_ii_debug_data_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t ii_data : 32; - } sh_ii_debug_data_s; -} sh_ii_debug_data_u_t; -#endif /* ==================================================================== */ /* Register "SH_II_WRAP_DEBUG_DATA" */ /* SHub II Wrapper Debug Data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ii_wrap_debug_data_u { mmr_t sh_ii_wrap_debug_data_regval; struct { @@ -20268,22 +10914,12 @@ typedef union sh_ii_wrap_debug_data_u { mmr_t reserved_0 : 32; } sh_ii_wrap_debug_data_s; } sh_ii_wrap_debug_data_u_t; -#else -typedef union sh_ii_wrap_debug_data_u { - mmr_t sh_ii_wrap_debug_data_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t ii_wrap_data : 32; - } sh_ii_wrap_debug_data_s; -} sh_ii_wrap_debug_data_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_DEBUG_DATA" */ /* SHub LB Debug Data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_debug_data_u { mmr_t sh_lb_debug_data_regval; struct { @@ -20291,22 +10927,12 @@ typedef union sh_lb_debug_data_u { mmr_t reserved_0 : 32; } sh_lb_debug_data_s; } sh_lb_debug_data_u_t; -#else -typedef union sh_lb_debug_data_u { - mmr_t sh_lb_debug_data_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t lb_data : 32; - } sh_lb_debug_data_s; -} sh_lb_debug_data_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DEBUG_DATA" */ /* SHub MD Debug Data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_debug_data_u { mmr_t sh_md_debug_data_regval; struct { @@ -20314,22 +10940,12 @@ typedef union sh_md_debug_data_u { mmr_t reserved_0 : 32; } sh_md_debug_data_s; } sh_md_debug_data_u_t; -#else -typedef union sh_md_debug_data_u { - mmr_t sh_md_debug_data_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t md_data : 32; - } sh_md_debug_data_s; -} sh_md_debug_data_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_DEBUG_DATA" */ /* SHub PI Debug Data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_debug_data_u { mmr_t sh_pi_debug_data_regval; struct { @@ -20337,22 +10953,12 @@ typedef union sh_pi_debug_data_u { mmr_t reserved_0 : 32; } sh_pi_debug_data_s; } sh_pi_debug_data_u_t; -#else -typedef union sh_pi_debug_data_u { - mmr_t sh_pi_debug_data_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t pi_data : 32; - } sh_pi_debug_data_s; -} sh_pi_debug_data_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_DEBUG_DATA" */ /* SHub XN Debug Data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_debug_data_u { mmr_t sh_xn_debug_data_regval; struct { @@ -20360,22 +10966,12 @@ typedef union sh_xn_debug_data_u { mmr_t reserved_0 : 32; } sh_xn_debug_data_s; } sh_xn_debug_data_u_t; -#else -typedef union sh_xn_debug_data_u { - mmr_t sh_xn_debug_data_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t xn_data : 32; - } sh_xn_debug_data_s; -} sh_xn_debug_data_u_t; -#endif /* ==================================================================== */ /* Register "SH_TSF_ARMED_STATE" */ /* Trigger sequencing facility arm state */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_tsf_armed_state_u { mmr_t sh_tsf_armed_state_regval; struct { @@ -20383,22 +10979,12 @@ typedef union sh_tsf_armed_state_u { mmr_t reserved_0 : 56; } sh_tsf_armed_state_s; } sh_tsf_armed_state_u_t; -#else -typedef union sh_tsf_armed_state_u { - mmr_t sh_tsf_armed_state_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t state : 8; - } sh_tsf_armed_state_s; -} sh_tsf_armed_state_u_t; -#endif /* ==================================================================== */ /* Register "SH_TSF_COUNTER_VALUE" */ /* Trigger sequencing facility counter value */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_tsf_counter_value_u { mmr_t sh_tsf_counter_value_regval; struct { @@ -20408,24 +10994,12 @@ typedef union sh_tsf_counter_value_u { mmr_t count_8a : 8; } sh_tsf_counter_value_s; } sh_tsf_counter_value_u_t; -#else -typedef union sh_tsf_counter_value_u { - mmr_t sh_tsf_counter_value_regval; - struct { - mmr_t count_8a : 8; - mmr_t count_8b : 8; - mmr_t count_16 : 16; - mmr_t count_32 : 32; - } sh_tsf_counter_value_s; -} sh_tsf_counter_value_u_t; -#endif /* ==================================================================== */ /* Register "SH_TSF_TRIGGERED_STATE" */ /* Trigger sequencing facility triggered state */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_tsf_triggered_state_u { mmr_t sh_tsf_triggered_state_regval; struct { @@ -20433,64 +11007,36 @@ typedef union sh_tsf_triggered_state_u { mmr_t reserved_0 : 56; } sh_tsf_triggered_state_s; } sh_tsf_triggered_state_u_t; -#else -typedef union sh_tsf_triggered_state_u { - mmr_t sh_tsf_triggered_state_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t state : 8; - } sh_tsf_triggered_state_s; -} sh_tsf_triggered_state_u_t; -#endif /* ==================================================================== */ /* Register "SH_VEC_RDDATA" */ /* Vector Reply Message Data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_vec_rddata_u { - mmr_t sh_vec_rddata_regval; - struct { - mmr_t data : 64; - } sh_vec_rddata_s; -} sh_vec_rddata_u_t; -#else typedef union sh_vec_rddata_u { mmr_t sh_vec_rddata_regval; struct { mmr_t data : 64; } sh_vec_rddata_s; } sh_vec_rddata_u_t; -#endif /* ==================================================================== */ /* Register "SH_VEC_RETURN" */ /* Vector Reply Message Return Route */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_vec_return_u { - mmr_t sh_vec_return_regval; - struct { - mmr_t route : 64; - } sh_vec_return_s; -} sh_vec_return_u_t; -#else typedef union sh_vec_return_u { mmr_t sh_vec_return_regval; struct { mmr_t route : 64; } sh_vec_return_s; } sh_vec_return_u_t; -#endif /* ==================================================================== */ /* Register "SH_VEC_STATUS" */ /* Vector Reply Message Status */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_vec_status_u { mmr_t sh_vec_status_regval; struct { @@ -20503,27 +11049,12 @@ typedef union sh_vec_status_u { mmr_t status_valid : 1; } sh_vec_status_s; } sh_vec_status_u_t; -#else -typedef union sh_vec_status_u { - mmr_t sh_vec_status_regval; - struct { - mmr_t status_valid : 1; - mmr_t overrun : 1; - mmr_t reserved_0 : 2; - mmr_t source : 14; - mmr_t pio_id : 11; - mmr_t address : 32; - mmr_t type : 3; - } sh_vec_status_s; -} sh_vec_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNT0_CONTROL" */ /* Performance Counter 0 Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_count0_control_u { mmr_t sh_performance_count0_control_regval; struct { @@ -20541,32 +11072,12 @@ typedef union sh_performance_count0_control_u { mmr_t reserved_0 : 45; } sh_performance_count0_control_s; } sh_performance_count0_control_u_t; -#else -typedef union sh_performance_count0_control_u { - mmr_t sh_performance_count0_control_regval; - struct { - mmr_t reserved_0 : 45; - mmr_t peak_det_enable : 1; - mmr_t dec_enable : 1; - mmr_t inc_enable : 1; - mmr_t dn_mode : 1; - mmr_t dn_polarity : 1; - mmr_t dn_event : 1; - mmr_t dn_stimulus : 5; - mmr_t up_mode : 1; - mmr_t up_polarity : 1; - mmr_t up_event : 1; - mmr_t up_stimulus : 5; - } sh_performance_count0_control_s; -} sh_performance_count0_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNT1_CONTROL" */ /* Performance Counter 1 Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_count1_control_u { mmr_t sh_performance_count1_control_regval; struct { @@ -20584,32 +11095,12 @@ typedef union sh_performance_count1_control_u { mmr_t reserved_0 : 45; } sh_performance_count1_control_s; } sh_performance_count1_control_u_t; -#else -typedef union sh_performance_count1_control_u { - mmr_t sh_performance_count1_control_regval; - struct { - mmr_t reserved_0 : 45; - mmr_t peak_det_enable : 1; - mmr_t dec_enable : 1; - mmr_t inc_enable : 1; - mmr_t dn_mode : 1; - mmr_t dn_polarity : 1; - mmr_t dn_event : 1; - mmr_t dn_stimulus : 5; - mmr_t up_mode : 1; - mmr_t up_polarity : 1; - mmr_t up_event : 1; - mmr_t up_stimulus : 5; - } sh_performance_count1_control_s; -} sh_performance_count1_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNT2_CONTROL" */ /* Performance Counter 2 Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_count2_control_u { mmr_t sh_performance_count2_control_regval; struct { @@ -20627,32 +11118,12 @@ typedef union sh_performance_count2_control_u { mmr_t reserved_0 : 45; } sh_performance_count2_control_s; } sh_performance_count2_control_u_t; -#else -typedef union sh_performance_count2_control_u { - mmr_t sh_performance_count2_control_regval; - struct { - mmr_t reserved_0 : 45; - mmr_t peak_det_enable : 1; - mmr_t dec_enable : 1; - mmr_t inc_enable : 1; - mmr_t dn_mode : 1; - mmr_t dn_polarity : 1; - mmr_t dn_event : 1; - mmr_t dn_stimulus : 5; - mmr_t up_mode : 1; - mmr_t up_polarity : 1; - mmr_t up_event : 1; - mmr_t up_stimulus : 5; - } sh_performance_count2_control_s; -} sh_performance_count2_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNT3_CONTROL" */ /* Performance Counter 3 Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_count3_control_u { mmr_t sh_performance_count3_control_regval; struct { @@ -20670,32 +11141,12 @@ typedef union sh_performance_count3_control_u { mmr_t reserved_0 : 45; } sh_performance_count3_control_s; } sh_performance_count3_control_u_t; -#else -typedef union sh_performance_count3_control_u { - mmr_t sh_performance_count3_control_regval; - struct { - mmr_t reserved_0 : 45; - mmr_t peak_det_enable : 1; - mmr_t dec_enable : 1; - mmr_t inc_enable : 1; - mmr_t dn_mode : 1; - mmr_t dn_polarity : 1; - mmr_t dn_event : 1; - mmr_t dn_stimulus : 5; - mmr_t up_mode : 1; - mmr_t up_polarity : 1; - mmr_t up_event : 1; - mmr_t up_stimulus : 5; - } sh_performance_count3_control_s; -} sh_performance_count3_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNT4_CONTROL" */ /* Performance Counter 4 Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_count4_control_u { mmr_t sh_performance_count4_control_regval; struct { @@ -20713,32 +11164,12 @@ typedef union sh_performance_count4_control_u { mmr_t reserved_0 : 45; } sh_performance_count4_control_s; } sh_performance_count4_control_u_t; -#else -typedef union sh_performance_count4_control_u { - mmr_t sh_performance_count4_control_regval; - struct { - mmr_t reserved_0 : 45; - mmr_t peak_det_enable : 1; - mmr_t dec_enable : 1; - mmr_t inc_enable : 1; - mmr_t dn_mode : 1; - mmr_t dn_polarity : 1; - mmr_t dn_event : 1; - mmr_t dn_stimulus : 5; - mmr_t up_mode : 1; - mmr_t up_polarity : 1; - mmr_t up_event : 1; - mmr_t up_stimulus : 5; - } sh_performance_count4_control_s; -} sh_performance_count4_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNT5_CONTROL" */ /* Performance Counter 5 Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_count5_control_u { mmr_t sh_performance_count5_control_regval; struct { @@ -20756,32 +11187,12 @@ typedef union sh_performance_count5_control_u { mmr_t reserved_0 : 45; } sh_performance_count5_control_s; } sh_performance_count5_control_u_t; -#else -typedef union sh_performance_count5_control_u { - mmr_t sh_performance_count5_control_regval; - struct { - mmr_t reserved_0 : 45; - mmr_t peak_det_enable : 1; - mmr_t dec_enable : 1; - mmr_t inc_enable : 1; - mmr_t dn_mode : 1; - mmr_t dn_polarity : 1; - mmr_t dn_event : 1; - mmr_t dn_stimulus : 5; - mmr_t up_mode : 1; - mmr_t up_polarity : 1; - mmr_t up_event : 1; - mmr_t up_stimulus : 5; - } sh_performance_count5_control_s; -} sh_performance_count5_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNT6_CONTROL" */ /* Performance Counter 6 Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_count6_control_u { mmr_t sh_performance_count6_control_regval; struct { @@ -20799,32 +11210,12 @@ typedef union sh_performance_count6_control_u { mmr_t reserved_0 : 45; } sh_performance_count6_control_s; } sh_performance_count6_control_u_t; -#else -typedef union sh_performance_count6_control_u { - mmr_t sh_performance_count6_control_regval; - struct { - mmr_t reserved_0 : 45; - mmr_t peak_det_enable : 1; - mmr_t dec_enable : 1; - mmr_t inc_enable : 1; - mmr_t dn_mode : 1; - mmr_t dn_polarity : 1; - mmr_t dn_event : 1; - mmr_t dn_stimulus : 5; - mmr_t up_mode : 1; - mmr_t up_polarity : 1; - mmr_t up_event : 1; - mmr_t up_stimulus : 5; - } sh_performance_count6_control_s; -} sh_performance_count6_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNT7_CONTROL" */ /* Performance Counter 7 Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_count7_control_u { mmr_t sh_performance_count7_control_regval; struct { @@ -20842,32 +11233,12 @@ typedef union sh_performance_count7_control_u { mmr_t reserved_0 : 45; } sh_performance_count7_control_s; } sh_performance_count7_control_u_t; -#else -typedef union sh_performance_count7_control_u { - mmr_t sh_performance_count7_control_regval; - struct { - mmr_t reserved_0 : 45; - mmr_t peak_det_enable : 1; - mmr_t dec_enable : 1; - mmr_t inc_enable : 1; - mmr_t dn_mode : 1; - mmr_t dn_polarity : 1; - mmr_t dn_event : 1; - mmr_t dn_stimulus : 5; - mmr_t up_mode : 1; - mmr_t up_polarity : 1; - mmr_t up_event : 1; - mmr_t up_stimulus : 5; - } sh_performance_count7_control_s; -} sh_performance_count7_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROFILE_DN_CONTROL" */ /* Profile Counter Down Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_profile_dn_control_u { mmr_t sh_profile_dn_control_regval; struct { @@ -20878,25 +11249,12 @@ typedef union sh_profile_dn_control_u { mmr_t reserved_0 : 56; } sh_profile_dn_control_s; } sh_profile_dn_control_u_t; -#else -typedef union sh_profile_dn_control_u { - mmr_t sh_profile_dn_control_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t mode : 1; - mmr_t polarity : 1; - mmr_t event : 1; - mmr_t stimulus : 5; - } sh_profile_dn_control_s; -} sh_profile_dn_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROFILE_PEAK_CONTROL" */ /* Profile Counter Peak Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_profile_peak_control_u { mmr_t sh_profile_peak_control_regval; struct { @@ -20908,26 +11266,12 @@ typedef union sh_profile_peak_control_u { mmr_t reserved_2 : 57; } sh_profile_peak_control_s; } sh_profile_peak_control_u_t; -#else -typedef union sh_profile_peak_control_u { - mmr_t sh_profile_peak_control_regval; - struct { - mmr_t reserved_2 : 57; - mmr_t polarity : 1; - mmr_t event : 1; - mmr_t reserved_1 : 1; - mmr_t stimulus : 1; - mmr_t reserved_0 : 3; - } sh_profile_peak_control_s; -} sh_profile_peak_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROFILE_RANGE" */ /* Profile Counter Range */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_profile_range_u { mmr_t sh_profile_range_regval; struct { @@ -20941,28 +11285,12 @@ typedef union sh_profile_range_u { mmr_t range7 : 8; } sh_profile_range_s; } sh_profile_range_u_t; -#else -typedef union sh_profile_range_u { - mmr_t sh_profile_range_regval; - struct { - mmr_t range7 : 8; - mmr_t range6 : 8; - mmr_t range5 : 8; - mmr_t range4 : 8; - mmr_t range3 : 8; - mmr_t range2 : 8; - mmr_t range1 : 8; - mmr_t range0 : 8; - } sh_profile_range_s; -} sh_profile_range_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROFILE_UP_CONTROL" */ /* Profile Counter Up Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_profile_up_control_u { mmr_t sh_profile_up_control_regval; struct { @@ -20973,25 +11301,12 @@ typedef union sh_profile_up_control_u { mmr_t reserved_0 : 56; } sh_profile_up_control_s; } sh_profile_up_control_u_t; -#else -typedef union sh_profile_up_control_u { - mmr_t sh_profile_up_control_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t mode : 1; - mmr_t polarity : 1; - mmr_t event : 1; - mmr_t stimulus : 5; - } sh_profile_up_control_s; -} sh_profile_up_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNTER0" */ /* Performance Counter 0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_counter0_u { mmr_t sh_performance_counter0_regval; struct { @@ -20999,22 +11314,12 @@ typedef union sh_performance_counter0_u { mmr_t reserved_0 : 32; } sh_performance_counter0_s; } sh_performance_counter0_u_t; -#else -typedef union sh_performance_counter0_u { - mmr_t sh_performance_counter0_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t count : 32; - } sh_performance_counter0_s; -} sh_performance_counter0_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNTER1" */ /* Performance Counter 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_counter1_u { mmr_t sh_performance_counter1_regval; struct { @@ -21022,22 +11327,12 @@ typedef union sh_performance_counter1_u { mmr_t reserved_0 : 32; } sh_performance_counter1_s; } sh_performance_counter1_u_t; -#else -typedef union sh_performance_counter1_u { - mmr_t sh_performance_counter1_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t count : 32; - } sh_performance_counter1_s; -} sh_performance_counter1_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNTER2" */ /* Performance Counter 2 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_counter2_u { mmr_t sh_performance_counter2_regval; struct { @@ -21045,22 +11340,12 @@ typedef union sh_performance_counter2_u { mmr_t reserved_0 : 32; } sh_performance_counter2_s; } sh_performance_counter2_u_t; -#else -typedef union sh_performance_counter2_u { - mmr_t sh_performance_counter2_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t count : 32; - } sh_performance_counter2_s; -} sh_performance_counter2_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNTER3" */ /* Performance Counter 3 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_counter3_u { mmr_t sh_performance_counter3_regval; struct { @@ -21068,22 +11353,12 @@ typedef union sh_performance_counter3_u { mmr_t reserved_0 : 32; } sh_performance_counter3_s; } sh_performance_counter3_u_t; -#else -typedef union sh_performance_counter3_u { - mmr_t sh_performance_counter3_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t count : 32; - } sh_performance_counter3_s; -} sh_performance_counter3_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNTER4" */ /* Performance Counter 4 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_counter4_u { mmr_t sh_performance_counter4_regval; struct { @@ -21091,22 +11366,12 @@ typedef union sh_performance_counter4_u { mmr_t reserved_0 : 32; } sh_performance_counter4_s; } sh_performance_counter4_u_t; -#else -typedef union sh_performance_counter4_u { - mmr_t sh_performance_counter4_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t count : 32; - } sh_performance_counter4_s; -} sh_performance_counter4_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNTER5" */ /* Performance Counter 5 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_counter5_u { mmr_t sh_performance_counter5_regval; struct { @@ -21114,22 +11379,12 @@ typedef union sh_performance_counter5_u { mmr_t reserved_0 : 32; } sh_performance_counter5_s; } sh_performance_counter5_u_t; -#else -typedef union sh_performance_counter5_u { - mmr_t sh_performance_counter5_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t count : 32; - } sh_performance_counter5_s; -} sh_performance_counter5_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNTER6" */ /* Performance Counter 6 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_counter6_u { mmr_t sh_performance_counter6_regval; struct { @@ -21137,22 +11392,12 @@ typedef union sh_performance_counter6_u { mmr_t reserved_0 : 32; } sh_performance_counter6_s; } sh_performance_counter6_u_t; -#else -typedef union sh_performance_counter6_u { - mmr_t sh_performance_counter6_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t count : 32; - } sh_performance_counter6_s; -} sh_performance_counter6_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNTER7" */ /* Performance Counter 7 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_counter7_u { mmr_t sh_performance_counter7_regval; struct { @@ -21160,22 +11405,12 @@ typedef union sh_performance_counter7_u { mmr_t reserved_0 : 32; } sh_performance_counter7_s; } sh_performance_counter7_u_t; -#else -typedef union sh_performance_counter7_u { - mmr_t sh_performance_counter7_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t count : 32; - } sh_performance_counter7_s; -} sh_performance_counter7_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROFILE_COUNTER" */ /* Profile Counter */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_profile_counter_u { mmr_t sh_profile_counter_regval; struct { @@ -21183,22 +11418,12 @@ typedef union sh_profile_counter_u { mmr_t reserved_0 : 56; } sh_profile_counter_s; } sh_profile_counter_u_t; -#else -typedef union sh_profile_counter_u { - mmr_t sh_profile_counter_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t counter : 8; - } sh_profile_counter_s; -} sh_profile_counter_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROFILE_PEAK" */ /* Profile Peak Counter */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_profile_peak_u { mmr_t sh_profile_peak_regval; struct { @@ -21206,22 +11431,12 @@ typedef union sh_profile_peak_u { mmr_t reserved_0 : 56; } sh_profile_peak_s; } sh_profile_peak_u_t; -#else -typedef union sh_profile_peak_u { - mmr_t sh_profile_peak_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t counter : 8; - } sh_profile_peak_s; -} sh_profile_peak_u_t; -#endif /* ==================================================================== */ /* Register "SH_PTC_0" */ /* Puge Translation Cache Message Configuration Information */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ptc_0_u { mmr_t sh_ptc_0_regval; struct { @@ -21233,26 +11448,12 @@ typedef union sh_ptc_0_u { mmr_t start : 1; } sh_ptc_0_s; } sh_ptc_0_u_t; -#else -typedef union sh_ptc_0_u { - mmr_t sh_ptc_0_regval; - struct { - mmr_t start : 1; - mmr_t reserved_1 : 31; - mmr_t rid : 24; - mmr_t ps : 6; - mmr_t reserved_0 : 1; - mmr_t a : 1; - } sh_ptc_0_s; -} sh_ptc_0_u_t; -#endif /* ==================================================================== */ /* Register "SH_PTC_1" */ /* Puge Translation Cache Message Configuration Information */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ptc_1_u { mmr_t sh_ptc_1_regval; struct { @@ -21262,24 +11463,12 @@ typedef union sh_ptc_1_u { mmr_t start : 1; } sh_ptc_1_s; } sh_ptc_1_u_t; -#else -typedef union sh_ptc_1_u { - mmr_t sh_ptc_1_regval; - struct { - mmr_t start : 1; - mmr_t reserved_1 : 2; - mmr_t vpn : 49; - mmr_t reserved_0 : 12; - } sh_ptc_1_s; -} sh_ptc_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_PTC_PARMS" */ /* PTC Time-out parmaeters */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ptc_parms_u { mmr_t sh_ptc_parms_regval; struct { @@ -21288,23 +11477,12 @@ typedef union sh_ptc_parms_u { mmr_t reserved_0 : 28; } sh_ptc_parms_s; } sh_ptc_parms_u_t; -#else -typedef union sh_ptc_parms_u { - mmr_t sh_ptc_parms_regval; - struct { - mmr_t reserved_0 : 28; - mmr_t ptc_to_val : 12; - mmr_t ptc_to_wrap : 24; - } sh_ptc_parms_s; -} sh_ptc_parms_u_t; -#endif /* ==================================================================== */ /* Register "SH_INT_CMPA" */ /* RTC Compare Value for Processor A */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_int_cmpa_u { mmr_t sh_int_cmpa_regval; struct { @@ -21312,22 +11490,12 @@ typedef union sh_int_cmpa_u { mmr_t reserved_0 : 9; } sh_int_cmpa_s; } sh_int_cmpa_u_t; -#else -typedef union sh_int_cmpa_u { - mmr_t sh_int_cmpa_regval; - struct { - mmr_t reserved_0 : 9; - mmr_t real_time_cmpa : 55; - } sh_int_cmpa_s; -} sh_int_cmpa_u_t; -#endif /* ==================================================================== */ /* Register "SH_INT_CMPB" */ /* RTC Compare Value for Processor B */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_int_cmpb_u { mmr_t sh_int_cmpb_regval; struct { @@ -21335,22 +11503,12 @@ typedef union sh_int_cmpb_u { mmr_t reserved_0 : 9; } sh_int_cmpb_s; } sh_int_cmpb_u_t; -#else -typedef union sh_int_cmpb_u { - mmr_t sh_int_cmpb_regval; - struct { - mmr_t reserved_0 : 9; - mmr_t real_time_cmpb : 55; - } sh_int_cmpb_s; -} sh_int_cmpb_u_t; -#endif /* ==================================================================== */ /* Register "SH_INT_CMPC" */ /* RTC Compare Value for Processor C */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_int_cmpc_u { mmr_t sh_int_cmpc_regval; struct { @@ -21358,22 +11516,12 @@ typedef union sh_int_cmpc_u { mmr_t reserved_0 : 9; } sh_int_cmpc_s; } sh_int_cmpc_u_t; -#else -typedef union sh_int_cmpc_u { - mmr_t sh_int_cmpc_regval; - struct { - mmr_t reserved_0 : 9; - mmr_t real_time_cmpc : 55; - } sh_int_cmpc_s; -} sh_int_cmpc_u_t; -#endif /* ==================================================================== */ /* Register "SH_INT_CMPD" */ /* RTC Compare Value for Processor D */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_int_cmpd_u { mmr_t sh_int_cmpd_regval; struct { @@ -21381,22 +11529,12 @@ typedef union sh_int_cmpd_u { mmr_t reserved_0 : 9; } sh_int_cmpd_s; } sh_int_cmpd_u_t; -#else -typedef union sh_int_cmpd_u { - mmr_t sh_int_cmpd_regval; - struct { - mmr_t reserved_0 : 9; - mmr_t real_time_cmpd : 55; - } sh_int_cmpd_s; -} sh_int_cmpd_u_t; -#endif /* ==================================================================== */ /* Register "SH_INT_PROF" */ /* Profile Compare Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_int_prof_u { mmr_t sh_int_prof_regval; struct { @@ -21404,22 +11542,12 @@ typedef union sh_int_prof_u { mmr_t reserved_0 : 32; } sh_int_prof_s; } sh_int_prof_u_t; -#else -typedef union sh_int_prof_u { - mmr_t sh_int_prof_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t profile_compare : 32; - } sh_int_prof_s; -} sh_int_prof_u_t; -#endif /* ==================================================================== */ /* Register "SH_RTC" */ /* Real-time Clock */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_rtc_u { mmr_t sh_rtc_regval; struct { @@ -21427,85 +11555,48 @@ typedef union sh_rtc_u { mmr_t reserved_0 : 9; } sh_rtc_s; } sh_rtc_u_t; -#else -typedef union sh_rtc_u { - mmr_t sh_rtc_regval; - struct { - mmr_t reserved_0 : 9; - mmr_t real_time_clock : 55; - } sh_rtc_s; -} sh_rtc_u_t; -#endif /* ==================================================================== */ /* Register "SH_SCRATCH0" */ /* Scratch Register 0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_scratch0_u { mmr_t sh_scratch0_regval; struct { mmr_t scratch0 : 64; } sh_scratch0_s; } sh_scratch0_u_t; -#else -typedef union sh_scratch0_u { - mmr_t sh_scratch0_regval; - struct { - mmr_t scratch0 : 64; - } sh_scratch0_s; -} sh_scratch0_u_t; -#endif /* ==================================================================== */ /* Register "SH_SCRATCH1" */ /* Scratch Register 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_scratch1_u { - mmr_t sh_scratch1_regval; - struct { - mmr_t scratch1 : 64; - } sh_scratch1_s; -} sh_scratch1_u_t; -#else typedef union sh_scratch1_u { mmr_t sh_scratch1_regval; struct { mmr_t scratch1 : 64; } sh_scratch1_s; } sh_scratch1_u_t; -#endif /* ==================================================================== */ /* Register "SH_SCRATCH2" */ /* Scratch Register 2 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_scratch2_u { - mmr_t sh_scratch2_regval; - struct { - mmr_t scratch2 : 64; - } sh_scratch2_s; -} sh_scratch2_u_t; -#else typedef union sh_scratch2_u { mmr_t sh_scratch2_regval; struct { mmr_t scratch2 : 64; } sh_scratch2_s; } sh_scratch2_u_t; -#endif /* ==================================================================== */ /* Register "SH_SCRATCH3" */ /* Scratch Register 3 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_scratch3_u { mmr_t sh_scratch3_regval; struct { @@ -21513,22 +11604,12 @@ typedef union sh_scratch3_u { mmr_t reserved_0 : 63; } sh_scratch3_s; } sh_scratch3_u_t; -#else -typedef union sh_scratch3_u { - mmr_t sh_scratch3_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t scratch3 : 1; - } sh_scratch3_s; -} sh_scratch3_u_t; -#endif /* ==================================================================== */ /* Register "SH_SCRATCH4" */ /* Scratch Register 4 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_scratch4_u { mmr_t sh_scratch4_regval; struct { @@ -21536,22 +11617,12 @@ typedef union sh_scratch4_u { mmr_t reserved_0 : 63; } sh_scratch4_s; } sh_scratch4_u_t; -#else -typedef union sh_scratch4_u { - mmr_t sh_scratch4_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t scratch4 : 1; - } sh_scratch4_s; -} sh_scratch4_u_t; -#endif /* ==================================================================== */ /* Register "SH_CRB_MESSAGE_CONTROL" */ /* Coherent Request Buffer Message Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_crb_message_control_u { mmr_t sh_crb_message_control_regval; struct { @@ -21572,35 +11643,12 @@ typedef union sh_crb_message_control_u { mmr_t ivack_throttle_control : 16; } sh_crb_message_control_s; } sh_crb_message_control_u_t; -#else -typedef union sh_crb_message_control_u { - mmr_t sh_crb_message_control_regval; - struct { - mmr_t ivack_throttle_control : 16; - mmr_t ivack_stall_count : 16; - mmr_t reserved_0 : 20; - mmr_t enable_ivack_consolidation : 1; - mmr_t suppress_bogus_writes : 1; - mmr_t wrb_attribute_mismatch_xb_enable : 1; - mmr_t rrb_attribute_mismatch_xb_enable : 1; - mmr_t irb_attribute_mismatch_fsb_enable : 1; - mmr_t wrb_attribute_mismatch_fsb_enable : 1; - mmr_t rrb_attribute_mismatch_fsb_enable : 1; - mmr_t message_color_enable : 1; - mmr_t message_color : 1; - mmr_t remote_speculative_message_enable : 1; - mmr_t local_speculative_message_enable : 1; - mmr_t system_coherence_enable : 1; - } sh_crb_message_control_s; -} sh_crb_message_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_CRB_NACK_LIMIT" */ /* CRB Nack Limit */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_crb_nack_limit_u { mmr_t sh_crb_nack_limit_regval; struct { @@ -21610,24 +11658,12 @@ typedef union sh_crb_nack_limit_u { mmr_t enable : 1; } sh_crb_nack_limit_s; } sh_crb_nack_limit_u_t; -#else -typedef union sh_crb_nack_limit_u { - mmr_t sh_crb_nack_limit_regval; - struct { - mmr_t enable : 1; - mmr_t reserved_0 : 47; - mmr_t pri_freq : 4; - mmr_t limit : 12; - } sh_crb_nack_limit_s; -} sh_crb_nack_limit_u_t; -#endif /* ==================================================================== */ /* Register "SH_CRB_TIMEOUT_PRESCALE" */ /* Coherent Request Buffer Timeout Prescale */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_crb_timeout_prescale_u { mmr_t sh_crb_timeout_prescale_regval; struct { @@ -21635,22 +11671,12 @@ typedef union sh_crb_timeout_prescale_u { mmr_t reserved_0 : 32; } sh_crb_timeout_prescale_s; } sh_crb_timeout_prescale_u_t; -#else -typedef union sh_crb_timeout_prescale_u { - mmr_t sh_crb_timeout_prescale_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t scaling_factor : 32; - } sh_crb_timeout_prescale_s; -} sh_crb_timeout_prescale_u_t; -#endif /* ==================================================================== */ /* Register "SH_CRB_TIMEOUT_SKID" */ /* Coherent Request Buffer Timeout Skid Limit */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_crb_timeout_skid_u { mmr_t sh_crb_timeout_skid_regval; struct { @@ -21659,23 +11685,12 @@ typedef union sh_crb_timeout_skid_u { mmr_t reset_skid_count : 1; } sh_crb_timeout_skid_s; } sh_crb_timeout_skid_u_t; -#else -typedef union sh_crb_timeout_skid_u { - mmr_t sh_crb_timeout_skid_regval; - struct { - mmr_t reset_skid_count : 1; - mmr_t reserved_0 : 57; - mmr_t skid : 6; - } sh_crb_timeout_skid_s; -} sh_crb_timeout_skid_u_t; -#endif /* ==================================================================== */ /* Register "SH_MEMORY_WRITE_STATUS_0" */ /* Memory Write Status for CPU 0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_memory_write_status_0_u { mmr_t sh_memory_write_status_0_regval; struct { @@ -21683,22 +11698,12 @@ typedef union sh_memory_write_status_0_u { mmr_t reserved_0 : 58; } sh_memory_write_status_0_s; } sh_memory_write_status_0_u_t; -#else -typedef union sh_memory_write_status_0_u { - mmr_t sh_memory_write_status_0_regval; - struct { - mmr_t reserved_0 : 58; - mmr_t pending_write_count : 6; - } sh_memory_write_status_0_s; -} sh_memory_write_status_0_u_t; -#endif /* ==================================================================== */ /* Register "SH_MEMORY_WRITE_STATUS_1" */ /* Memory Write Status for CPU 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_memory_write_status_1_u { mmr_t sh_memory_write_status_1_regval; struct { @@ -21706,22 +11711,12 @@ typedef union sh_memory_write_status_1_u { mmr_t reserved_0 : 58; } sh_memory_write_status_1_s; } sh_memory_write_status_1_u_t; -#else -typedef union sh_memory_write_status_1_u { - mmr_t sh_memory_write_status_1_regval; - struct { - mmr_t reserved_0 : 58; - mmr_t pending_write_count : 6; - } sh_memory_write_status_1_s; -} sh_memory_write_status_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_PIO_WRITE_STATUS_0" */ /* PIO Write Status for CPU 0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pio_write_status_0_u { mmr_t sh_pio_write_status_0_regval; struct { @@ -21735,28 +11730,12 @@ typedef union sh_pio_write_status_0_u { mmr_t writes_ok : 1; } sh_pio_write_status_0_s; } sh_pio_write_status_0_u_t; -#else -typedef union sh_pio_write_status_0_u { - mmr_t sh_pio_write_status_0_regval; - struct { - mmr_t writes_ok : 1; - mmr_t reserved_1 : 1; - mmr_t pending_write_count : 6; - mmr_t reserved_0 : 6; - mmr_t write_error_address : 47; - mmr_t write_error : 1; - mmr_t write_deadlock : 1; - mmr_t multi_write_error : 1; - } sh_pio_write_status_0_s; -} sh_pio_write_status_0_u_t; -#endif /* ==================================================================== */ /* Register "SH_PIO_WRITE_STATUS_1" */ /* PIO Write Status for CPU 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pio_write_status_1_u { mmr_t sh_pio_write_status_1_regval; struct { @@ -21770,28 +11749,12 @@ typedef union sh_pio_write_status_1_u { mmr_t writes_ok : 1; } sh_pio_write_status_1_s; } sh_pio_write_status_1_u_t; -#else -typedef union sh_pio_write_status_1_u { - mmr_t sh_pio_write_status_1_regval; - struct { - mmr_t writes_ok : 1; - mmr_t reserved_1 : 1; - mmr_t pending_write_count : 6; - mmr_t reserved_0 : 6; - mmr_t write_error_address : 47; - mmr_t write_error : 1; - mmr_t write_deadlock : 1; - mmr_t multi_write_error : 1; - } sh_pio_write_status_1_s; -} sh_pio_write_status_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MEMORY_WRITE_STATUS_NON_USER_0" */ /* Memory Write Status for CPU 0. OS access only */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_memory_write_status_non_user_0_u { mmr_t sh_memory_write_status_non_user_0_regval; struct { @@ -21800,23 +11763,12 @@ typedef union sh_memory_write_status_non_user_0_u { mmr_t clear : 1; } sh_memory_write_status_non_user_0_s; } sh_memory_write_status_non_user_0_u_t; -#else -typedef union sh_memory_write_status_non_user_0_u { - mmr_t sh_memory_write_status_non_user_0_regval; - struct { - mmr_t clear : 1; - mmr_t reserved_0 : 57; - mmr_t pending_write_count : 6; - } sh_memory_write_status_non_user_0_s; -} sh_memory_write_status_non_user_0_u_t; -#endif /* ==================================================================== */ /* Register "SH_MEMORY_WRITE_STATUS_NON_USER_1" */ /* Memory Write Status for CPU 1. OS access only */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_memory_write_status_non_user_1_u { mmr_t sh_memory_write_status_non_user_1_regval; struct { @@ -21825,23 +11777,12 @@ typedef union sh_memory_write_status_non_user_1_u { mmr_t clear : 1; } sh_memory_write_status_non_user_1_s; } sh_memory_write_status_non_user_1_u_t; -#else -typedef union sh_memory_write_status_non_user_1_u { - mmr_t sh_memory_write_status_non_user_1_regval; - struct { - mmr_t clear : 1; - mmr_t reserved_0 : 57; - mmr_t pending_write_count : 6; - } sh_memory_write_status_non_user_1_s; -} sh_memory_write_status_non_user_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MMRBIST_ERR" */ /* Error capture for bist read errors */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_mmrbist_err_u { mmr_t sh_mmrbist_err_regval; struct { @@ -21853,26 +11794,12 @@ typedef union sh_mmrbist_err_u { mmr_t reserved_1 : 25; } sh_mmrbist_err_s; } sh_mmrbist_err_u_t; -#else -typedef union sh_mmrbist_err_u { - mmr_t sh_mmrbist_err_regval; - struct { - mmr_t reserved_1 : 25; - mmr_t cancelled : 1; - mmr_t multiple_detected : 1; - mmr_t detected : 1; - mmr_t reserved_0 : 3; - mmr_t addr : 33; - } sh_mmrbist_err_s; -} sh_mmrbist_err_u_t; -#endif /* ==================================================================== */ /* Register "SH_MISC_ERR_HDR_LOWER" */ /* Header capture register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_misc_err_hdr_lower_u { mmr_t sh_misc_err_hdr_lower_regval; struct { @@ -21886,28 +11813,12 @@ typedef union sh_misc_err_hdr_lower_u { mmr_t valid : 1; } sh_misc_err_hdr_lower_s; } sh_misc_err_hdr_lower_u_t; -#else -typedef union sh_misc_err_hdr_lower_u { - mmr_t sh_misc_err_hdr_lower_regval; - struct { - mmr_t valid : 1; - mmr_t reserved_2 : 2; - mmr_t write : 1; - mmr_t reserved_1 : 2; - mmr_t src : 14; - mmr_t cmd : 8; - mmr_t addr : 33; - mmr_t reserved_0 : 3; - } sh_misc_err_hdr_lower_s; -} sh_misc_err_hdr_lower_u_t; -#endif /* ==================================================================== */ /* Register "SH_MISC_ERR_HDR_UPPER" */ /* Error header capture packet and protocol errors */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_misc_err_hdr_upper_u { mmr_t sh_misc_err_hdr_upper_regval; struct { @@ -21924,31 +11835,12 @@ typedef union sh_misc_err_hdr_upper_u { mmr_t reserved_1 : 35; } sh_misc_err_hdr_upper_s; } sh_misc_err_hdr_upper_u_t; -#else -typedef union sh_misc_err_hdr_upper_u { - mmr_t sh_misc_err_hdr_upper_regval; - struct { - mmr_t reserved_1 : 35; - mmr_t echo : 9; - mmr_t reserved_0 : 12; - mmr_t xn_pkt_size : 1; - mmr_t pi_pkt_size : 1; - mmr_t dir_acc : 1; - mmr_t rmw_cor : 1; - mmr_t rmw_uc : 1; - mmr_t nonexist_addr : 1; - mmr_t illegal_cmd : 1; - mmr_t dir_protocol : 1; - } sh_misc_err_hdr_upper_s; -} sh_misc_err_hdr_upper_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIR_UC_ERR_HDR_LOWER" */ /* Header capture register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_dir_uc_err_hdr_lower_u { mmr_t sh_dir_uc_err_hdr_lower_regval; struct { @@ -21962,28 +11854,12 @@ typedef union sh_dir_uc_err_hdr_lower_u { mmr_t valid : 1; } sh_dir_uc_err_hdr_lower_s; } sh_dir_uc_err_hdr_lower_u_t; -#else -typedef union sh_dir_uc_err_hdr_lower_u { - mmr_t sh_dir_uc_err_hdr_lower_regval; - struct { - mmr_t valid : 1; - mmr_t reserved_2 : 2; - mmr_t write : 1; - mmr_t reserved_1 : 2; - mmr_t src : 14; - mmr_t cmd : 8; - mmr_t addr : 33; - mmr_t reserved_0 : 3; - } sh_dir_uc_err_hdr_lower_s; -} sh_dir_uc_err_hdr_lower_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIR_UC_ERR_HDR_UPPER" */ /* Error header capture packet and protocol errors */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_dir_uc_err_hdr_upper_u { mmr_t sh_dir_uc_err_hdr_upper_regval; struct { @@ -21994,25 +11870,12 @@ typedef union sh_dir_uc_err_hdr_upper_u { mmr_t reserved_2 : 35; } sh_dir_uc_err_hdr_upper_s; } sh_dir_uc_err_hdr_upper_u_t; -#else -typedef union sh_dir_uc_err_hdr_upper_u { - mmr_t sh_dir_uc_err_hdr_upper_regval; - struct { - mmr_t reserved_2 : 35; - mmr_t echo : 9; - mmr_t reserved_1 : 16; - mmr_t dir_uc : 1; - mmr_t reserved_0 : 3; - } sh_dir_uc_err_hdr_upper_s; -} sh_dir_uc_err_hdr_upper_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIR_COR_ERR_HDR_LOWER" */ /* Header capture register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_dir_cor_err_hdr_lower_u { mmr_t sh_dir_cor_err_hdr_lower_regval; struct { @@ -22026,28 +11889,12 @@ typedef union sh_dir_cor_err_hdr_lower_u { mmr_t valid : 1; } sh_dir_cor_err_hdr_lower_s; } sh_dir_cor_err_hdr_lower_u_t; -#else -typedef union sh_dir_cor_err_hdr_lower_u { - mmr_t sh_dir_cor_err_hdr_lower_regval; - struct { - mmr_t valid : 1; - mmr_t reserved_2 : 2; - mmr_t write : 1; - mmr_t reserved_1 : 2; - mmr_t src : 14; - mmr_t cmd : 8; - mmr_t addr : 33; - mmr_t reserved_0 : 3; - } sh_dir_cor_err_hdr_lower_s; -} sh_dir_cor_err_hdr_lower_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIR_COR_ERR_HDR_UPPER" */ /* Error header capture packet and protocol errors */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_dir_cor_err_hdr_upper_u { mmr_t sh_dir_cor_err_hdr_upper_regval; struct { @@ -22058,25 +11905,12 @@ typedef union sh_dir_cor_err_hdr_upper_u { mmr_t reserved_2 : 35; } sh_dir_cor_err_hdr_upper_s; } sh_dir_cor_err_hdr_upper_u_t; -#else -typedef union sh_dir_cor_err_hdr_upper_u { - mmr_t sh_dir_cor_err_hdr_upper_regval; - struct { - mmr_t reserved_2 : 35; - mmr_t echo : 9; - mmr_t reserved_1 : 11; - mmr_t dir_cor : 1; - mmr_t reserved_0 : 8; - } sh_dir_cor_err_hdr_upper_s; -} sh_dir_cor_err_hdr_upper_u_t; -#endif /* ==================================================================== */ /* Register "SH_MEM_ERROR_SUMMARY" */ /* Memory error flags */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_mem_error_summary_u { mmr_t sh_mem_error_summary_regval; struct { @@ -22118,56 +11952,12 @@ typedef union sh_mem_error_summary_u { mmr_t reserved_5 : 29; } sh_mem_error_summary_s; } sh_mem_error_summary_u_t; -#else -typedef union sh_mem_error_summary_u { - mmr_t sh_mem_error_summary_regval; - struct { - mmr_t reserved_5 : 29; - mmr_t xn_pkt_size : 1; - mmr_t pi_pkt_size : 1; - mmr_t red_black_err_timeout : 1; - mmr_t xn_request_overflow : 1; - mmr_t pi_request_overflow : 1; - mmr_t xn_reply_overflow : 1; - mmr_t pi_reply_overflow : 1; - mmr_t reserved_4 : 1; - mmr_t dqrs_int_hw : 1; - mmr_t dqrs_int_cor : 1; - mmr_t dqrs_int_uc : 1; - mmr_t reserved_3 : 1; - mmr_t dqrp_int_hw : 1; - mmr_t dqrp_int_cor : 1; - mmr_t dqrp_int_uc : 1; - mmr_t reserved_2 : 1; - mmr_t dqls_int_hw : 1; - mmr_t dqls_int_cor : 1; - mmr_t dqls_int_uc : 1; - mmr_t reserved_1 : 1; - mmr_t dqlp_int_hw : 1; - mmr_t dqlp_int_cor : 1; - mmr_t dqlp_int_uc : 1; - mmr_t reserved_0 : 1; - mmr_t dir_acc : 1; - mmr_t acy_int_hw : 1; - mmr_t acx_int_hw : 1; - mmr_t dqrp_dir_cor : 1; - mmr_t dqrp_dir_uc : 1; - mmr_t dqlp_dir_cor : 1; - mmr_t dqlp_dir_uc : 1; - mmr_t dqrp_dir_perr : 1; - mmr_t dqlp_dir_perr : 1; - mmr_t nonexist_addr : 1; - mmr_t illegal_cmd : 1; - } sh_mem_error_summary_s; -} sh_mem_error_summary_u_t; -#endif /* ==================================================================== */ /* Register "SH_MEM_ERROR_OVERFLOW" */ /* Memory error flags */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_mem_error_overflow_u { mmr_t sh_mem_error_overflow_regval; struct { @@ -22209,56 +11999,12 @@ typedef union sh_mem_error_overflow_u { mmr_t reserved_5 : 29; } sh_mem_error_overflow_s; } sh_mem_error_overflow_u_t; -#else -typedef union sh_mem_error_overflow_u { - mmr_t sh_mem_error_overflow_regval; - struct { - mmr_t reserved_5 : 29; - mmr_t xn_pkt_size : 1; - mmr_t pi_pkt_size : 1; - mmr_t red_black_err_timeout : 1; - mmr_t xn_request_overflow : 1; - mmr_t pi_request_overflow : 1; - mmr_t xn_reply_overflow : 1; - mmr_t pi_reply_overflow : 1; - mmr_t reserved_4 : 1; - mmr_t dqrs_int_hw : 1; - mmr_t dqrs_int_cor : 1; - mmr_t dqrs_int_uc : 1; - mmr_t reserved_3 : 1; - mmr_t dqrp_int_hw : 1; - mmr_t dqrp_int_cor : 1; - mmr_t dqrp_int_uc : 1; - mmr_t reserved_2 : 1; - mmr_t dqls_int_hw : 1; - mmr_t dqls_int_cor : 1; - mmr_t dqls_int_uc : 1; - mmr_t reserved_1 : 1; - mmr_t dqlp_int_hw : 1; - mmr_t dqlp_int_cor : 1; - mmr_t dqlp_int_uc : 1; - mmr_t reserved_0 : 1; - mmr_t dir_acc : 1; - mmr_t acy_int_hw : 1; - mmr_t acx_int_hw : 1; - mmr_t dqrp_dir_cor : 1; - mmr_t dqrp_dir_uc : 1; - mmr_t dqlp_dir_cor : 1; - mmr_t dqlp_dir_uc : 1; - mmr_t dqrp_dir_perr : 1; - mmr_t dqlp_dir_perr : 1; - mmr_t nonexist_addr : 1; - mmr_t illegal_cmd : 1; - } sh_mem_error_overflow_s; -} sh_mem_error_overflow_u_t; -#endif /* ==================================================================== */ /* Register "SH_MEM_ERROR_MASK" */ /* Memory error flags */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_mem_error_mask_u { mmr_t sh_mem_error_mask_regval; struct { @@ -22300,56 +12046,12 @@ typedef union sh_mem_error_mask_u { mmr_t reserved_5 : 29; } sh_mem_error_mask_s; } sh_mem_error_mask_u_t; -#else -typedef union sh_mem_error_mask_u { - mmr_t sh_mem_error_mask_regval; - struct { - mmr_t reserved_5 : 29; - mmr_t xn_pkt_size : 1; - mmr_t pi_pkt_size : 1; - mmr_t red_black_err_timeout : 1; - mmr_t xn_request_overflow : 1; - mmr_t pi_request_overflow : 1; - mmr_t xn_reply_overflow : 1; - mmr_t pi_reply_overflow : 1; - mmr_t reserved_4 : 1; - mmr_t dqrs_int_hw : 1; - mmr_t dqrs_int_cor : 1; - mmr_t dqrs_int_uc : 1; - mmr_t reserved_3 : 1; - mmr_t dqrp_int_hw : 1; - mmr_t dqrp_int_cor : 1; - mmr_t dqrp_int_uc : 1; - mmr_t reserved_2 : 1; - mmr_t dqls_int_hw : 1; - mmr_t dqls_int_cor : 1; - mmr_t dqls_int_uc : 1; - mmr_t reserved_1 : 1; - mmr_t dqlp_int_hw : 1; - mmr_t dqlp_int_cor : 1; - mmr_t dqlp_int_uc : 1; - mmr_t reserved_0 : 1; - mmr_t dir_acc : 1; - mmr_t acy_int_hw : 1; - mmr_t acx_int_hw : 1; - mmr_t dqrp_dir_cor : 1; - mmr_t dqrp_dir_uc : 1; - mmr_t dqlp_dir_cor : 1; - mmr_t dqlp_dir_uc : 1; - mmr_t dqrp_dir_perr : 1; - mmr_t dqlp_dir_perr : 1; - mmr_t nonexist_addr : 1; - mmr_t illegal_cmd : 1; - } sh_mem_error_mask_s; -} sh_mem_error_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_DIMM_CFG" */ /* AC Mem Config Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_dimm_cfg_u { mmr_t sh_x_dimm_cfg_regval; struct { @@ -22377,42 +12079,12 @@ typedef union sh_x_dimm_cfg_u { mmr_t reserved_4 : 28; } sh_x_dimm_cfg_s; } sh_x_dimm_cfg_u_t; -#else -typedef union sh_x_dimm_cfg_u { - mmr_t sh_x_dimm_cfg_regval; - struct { - mmr_t reserved_4 : 28; - mmr_t freq : 4; - mmr_t reserved_3 : 1; - mmr_t dimm3_cs : 2; - mmr_t dimm3_rev : 1; - mmr_t dimm3_2bk : 1; - mmr_t dimm3_size : 3; - mmr_t reserved_2 : 1; - mmr_t dimm2_cs : 2; - mmr_t dimm2_rev : 1; - mmr_t dimm2_2bk : 1; - mmr_t dimm2_size : 3; - mmr_t reserved_1 : 1; - mmr_t dimm1_cs : 2; - mmr_t dimm1_rev : 1; - mmr_t dimm1_2bk : 1; - mmr_t dimm1_size : 3; - mmr_t reserved_0 : 1; - mmr_t dimm0_cs : 2; - mmr_t dimm0_rev : 1; - mmr_t dimm0_2bk : 1; - mmr_t dimm0_size : 3; - } sh_x_dimm_cfg_s; -} sh_x_dimm_cfg_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_DIMM_CFG" */ /* AC Mem Config Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_dimm_cfg_u { mmr_t sh_y_dimm_cfg_regval; struct { @@ -22440,42 +12112,12 @@ typedef union sh_y_dimm_cfg_u { mmr_t reserved_4 : 28; } sh_y_dimm_cfg_s; } sh_y_dimm_cfg_u_t; -#else -typedef union sh_y_dimm_cfg_u { - mmr_t sh_y_dimm_cfg_regval; - struct { - mmr_t reserved_4 : 28; - mmr_t freq : 4; - mmr_t reserved_3 : 1; - mmr_t dimm3_cs : 2; - mmr_t dimm3_rev : 1; - mmr_t dimm3_2bk : 1; - mmr_t dimm3_size : 3; - mmr_t reserved_2 : 1; - mmr_t dimm2_cs : 2; - mmr_t dimm2_rev : 1; - mmr_t dimm2_2bk : 1; - mmr_t dimm2_size : 3; - mmr_t reserved_1 : 1; - mmr_t dimm1_cs : 2; - mmr_t dimm1_rev : 1; - mmr_t dimm1_2bk : 1; - mmr_t dimm1_size : 3; - mmr_t reserved_0 : 1; - mmr_t dimm0_cs : 2; - mmr_t dimm0_rev : 1; - mmr_t dimm0_2bk : 1; - mmr_t dimm0_size : 3; - } sh_y_dimm_cfg_s; -} sh_y_dimm_cfg_u_t; -#endif /* ==================================================================== */ /* Register "SH_JNR_DIMM_CFG" */ /* AC Mem Config Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_jnr_dimm_cfg_u { mmr_t sh_jnr_dimm_cfg_regval; struct { @@ -22503,42 +12145,12 @@ typedef union sh_jnr_dimm_cfg_u { mmr_t reserved_4 : 28; } sh_jnr_dimm_cfg_s; } sh_jnr_dimm_cfg_u_t; -#else -typedef union sh_jnr_dimm_cfg_u { - mmr_t sh_jnr_dimm_cfg_regval; - struct { - mmr_t reserved_4 : 28; - mmr_t freq : 4; - mmr_t reserved_3 : 1; - mmr_t dimm3_cs : 2; - mmr_t dimm3_rev : 1; - mmr_t dimm3_2bk : 1; - mmr_t dimm3_size : 3; - mmr_t reserved_2 : 1; - mmr_t dimm2_cs : 2; - mmr_t dimm2_rev : 1; - mmr_t dimm2_2bk : 1; - mmr_t dimm2_size : 3; - mmr_t reserved_1 : 1; - mmr_t dimm1_cs : 2; - mmr_t dimm1_rev : 1; - mmr_t dimm1_2bk : 1; - mmr_t dimm1_size : 3; - mmr_t reserved_0 : 1; - mmr_t dimm0_cs : 2; - mmr_t dimm0_rev : 1; - mmr_t dimm0_2bk : 1; - mmr_t dimm0_size : 3; - } sh_jnr_dimm_cfg_s; -} sh_jnr_dimm_cfg_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_PHASE_CFG" */ /* AC Phase Config Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_phase_cfg_u { mmr_t sh_x_phase_cfg_regval; struct { @@ -22560,36 +12172,12 @@ typedef union sh_x_phase_cfg_u { mmr_t reserved_0 : 1; } sh_x_phase_cfg_s; } sh_x_phase_cfg_u_t; -#else -typedef union sh_x_phase_cfg_u { - mmr_t sh_x_phase_cfg_regval; - struct { - mmr_t reserved_0 : 1; - mmr_t dq_sel_a : 4; - mmr_t sel_a : 4; - mmr_t phe_bubble : 3; - mmr_t phd_bubble : 3; - mmr_t phc_bubble : 3; - mmr_t phb_bubble : 3; - mmr_t pha_bubble : 3; - mmr_t bubble_en : 5; - mmr_t add_cp : 5; - mmr_t hold_req : 5; - mmr_t hold : 5; - mmr_t dq_ld_b : 5; - mmr_t dq_ld_a : 5; - mmr_t ld_b : 5; - mmr_t ld_a : 5; - } sh_x_phase_cfg_s; -} sh_x_phase_cfg_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_CFG" */ /* AC Config Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_cfg_u { mmr_t sh_x_cfg_regval; struct { @@ -22609,34 +12197,12 @@ typedef union sh_x_cfg_u { mmr_t clr_dir_cache : 1; } sh_x_cfg_s; } sh_x_cfg_u_t; -#else -typedef union sh_x_cfg_u { - mmr_t sh_x_cfg_regval; - struct { - mmr_t clr_dir_cache : 1; - mmr_t inv_cas_addr : 1; - mmr_t req_cntr_val : 6; - mmr_t req_cntr_dis : 1; - mmr_t trcd4_en : 1; - mmr_t trcd2_en : 1; - mmr_t sso_wt_en : 1; - mmr_t wt_bb_clr : 4; - mmr_t dc_bb_clr : 4; - mmr_t da_bb_clr : 4; - mmr_t ta_dlys : 32; - mmr_t dir_counter_init : 6; - mmr_t dirc_random_replacement : 1; - mmr_t mode_serial : 1; - } sh_x_cfg_s; -} sh_x_cfg_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_DQCT_CFG" */ /* AC Config Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_dqct_cfg_u { mmr_t sh_x_dqct_cfg_regval; struct { @@ -22649,27 +12215,12 @@ typedef union sh_x_dqct_cfg_u { mmr_t reserved_0 : 40; } sh_x_dqct_cfg_s; } sh_x_dqct_cfg_u_t; -#else -typedef union sh_x_dqct_cfg_u { - mmr_t sh_x_dqct_cfg_regval; - struct { - mmr_t reserved_0 : 40; - mmr_t mdir_rd_sel : 4; - mmr_t dir_rd_sel : 4; - mmr_t dta_wt_sel : 4; - mmr_t dta_rd_sel : 4; - mmr_t wt_sel : 4; - mmr_t rd_sel : 4; - } sh_x_dqct_cfg_s; -} sh_x_dqct_cfg_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_REFRESH_CONTROL" */ /* Refresh Control Register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_refresh_control_u { mmr_t sh_x_refresh_control_regval; struct { @@ -22681,26 +12232,12 @@ typedef union sh_x_refresh_control_u { mmr_t reserved_0 : 36; } sh_x_refresh_control_s; } sh_x_refresh_control_u_t; -#else -typedef union sh_x_refresh_control_u { - mmr_t sh_x_refresh_control_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t half_rate : 4; - mmr_t interleave : 1; - mmr_t hold : 6; - mmr_t interval : 9; - mmr_t enable : 8; - } sh_x_refresh_control_s; -} sh_x_refresh_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_PHASE_CFG" */ /* AC Phase Config Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_phase_cfg_u { mmr_t sh_y_phase_cfg_regval; struct { @@ -22722,36 +12259,12 @@ typedef union sh_y_phase_cfg_u { mmr_t reserved_0 : 1; } sh_y_phase_cfg_s; } sh_y_phase_cfg_u_t; -#else -typedef union sh_y_phase_cfg_u { - mmr_t sh_y_phase_cfg_regval; - struct { - mmr_t reserved_0 : 1; - mmr_t dq_sel_a : 4; - mmr_t sel_a : 4; - mmr_t phe_bubble : 3; - mmr_t phd_bubble : 3; - mmr_t phc_bubble : 3; - mmr_t phb_bubble : 3; - mmr_t pha_bubble : 3; - mmr_t bubble_en : 5; - mmr_t add_cp : 5; - mmr_t hold_req : 5; - mmr_t hold : 5; - mmr_t dq_ld_b : 5; - mmr_t dq_ld_a : 5; - mmr_t ld_b : 5; - mmr_t ld_a : 5; - } sh_y_phase_cfg_s; -} sh_y_phase_cfg_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_CFG" */ /* AC Config Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_cfg_u { mmr_t sh_y_cfg_regval; struct { @@ -22771,34 +12284,12 @@ typedef union sh_y_cfg_u { mmr_t clr_dir_cache : 1; } sh_y_cfg_s; } sh_y_cfg_u_t; -#else -typedef union sh_y_cfg_u { - mmr_t sh_y_cfg_regval; - struct { - mmr_t clr_dir_cache : 1; - mmr_t inv_cas_addr : 1; - mmr_t req_cntr_val : 6; - mmr_t req_cntr_dis : 1; - mmr_t trcd4_en : 1; - mmr_t trcd2_en : 1; - mmr_t sso_wt_en : 1; - mmr_t wt_bb_clr : 4; - mmr_t dc_bb_clr : 4; - mmr_t da_bb_clr : 4; - mmr_t ta_dlys : 32; - mmr_t dir_counter_init : 6; - mmr_t dirc_random_replacement : 1; - mmr_t mode_serial : 1; - } sh_y_cfg_s; -} sh_y_cfg_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_DQCT_CFG" */ /* AC Config Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_dqct_cfg_u { mmr_t sh_y_dqct_cfg_regval; struct { @@ -22811,27 +12302,12 @@ typedef union sh_y_dqct_cfg_u { mmr_t reserved_0 : 40; } sh_y_dqct_cfg_s; } sh_y_dqct_cfg_u_t; -#else -typedef union sh_y_dqct_cfg_u { - mmr_t sh_y_dqct_cfg_regval; - struct { - mmr_t reserved_0 : 40; - mmr_t mdir_rd_sel : 4; - mmr_t dir_rd_sel : 4; - mmr_t dta_wt_sel : 4; - mmr_t dta_rd_sel : 4; - mmr_t wt_sel : 4; - mmr_t rd_sel : 4; - } sh_y_dqct_cfg_s; -} sh_y_dqct_cfg_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_REFRESH_CONTROL" */ /* Refresh Control Register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_refresh_control_u { mmr_t sh_y_refresh_control_regval; struct { @@ -22843,26 +12319,12 @@ typedef union sh_y_refresh_control_u { mmr_t reserved_0 : 36; } sh_y_refresh_control_s; } sh_y_refresh_control_u_t; -#else -typedef union sh_y_refresh_control_u { - mmr_t sh_y_refresh_control_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t half_rate : 4; - mmr_t interleave : 1; - mmr_t hold : 6; - mmr_t interval : 9; - mmr_t enable : 8; - } sh_y_refresh_control_s; -} sh_y_refresh_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_MEM_RED_BLACK" */ /* MD fairness watchdog timers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_mem_red_black_u { mmr_t sh_mem_red_black_regval; struct { @@ -22871,22 +12333,11 @@ typedef union sh_mem_red_black_u { mmr_t reserved_0 : 12; } sh_mem_red_black_s; } sh_mem_red_black_u_t; -#else -typedef union sh_mem_red_black_u { - mmr_t sh_mem_red_black_regval; - struct { - mmr_t reserved_0 : 12; - mmr_t err_time : 36; - mmr_t time : 16; - } sh_mem_red_black_s; -} sh_mem_red_black_u_t; -#endif /* ==================================================================== */ /* Register "SH_MISC_MEM_CFG" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_misc_mem_cfg_u { mmr_t sh_misc_mem_cfg_regval; struct { @@ -22909,37 +12360,12 @@ typedef union sh_misc_mem_cfg_u { mmr_t reserved_5 : 11; } sh_misc_mem_cfg_s; } sh_misc_mem_cfg_u_t; -#else -typedef union sh_misc_mem_cfg_u { - mmr_t sh_misc_mem_cfg_regval; - struct { - mmr_t reserved_5 : 11; - mmr_t alternate_xn_rp_plane : 1; - mmr_t reserved_4 : 2; - mmr_t disabled_victims : 6; - mmr_t reserved_3 : 3; - mmr_t disabled_write_tnums : 5; - mmr_t reserved_2 : 3; - mmr_t disabled_read_tnums : 5; - mmr_t throttle_cnt : 8; - mmr_t reserved_1 : 2; - mmr_t low_victim_buffer_threshold : 6; - mmr_t reserved_0 : 2; - mmr_t low_write_buffer_threshold : 6; - mmr_t xn_rd_same_as_pi : 1; - mmr_t jnr_bypass_enable : 1; - mmr_t spec_header_enable : 1; - mmr_t express_header_enable : 1; - } sh_misc_mem_cfg_s; -} sh_misc_mem_cfg_u_t; -#endif /* ==================================================================== */ /* Register "SH_PIO_RQ_CRD_CTL" */ /* pio_rq Credit Circulation Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pio_rq_crd_ctl_u { mmr_t sh_pio_rq_crd_ctl_regval; struct { @@ -22947,22 +12373,12 @@ typedef union sh_pio_rq_crd_ctl_u { mmr_t reserved_0 : 58; } sh_pio_rq_crd_ctl_s; } sh_pio_rq_crd_ctl_u_t; -#else -typedef union sh_pio_rq_crd_ctl_u { - mmr_t sh_pio_rq_crd_ctl_regval; - struct { - mmr_t reserved_0 : 58; - mmr_t depth : 6; - } sh_pio_rq_crd_ctl_s; -} sh_pio_rq_crd_ctl_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_MD_RQ_CRD_CTL" */ /* pi_md_rq Credit Circulation Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_md_rq_crd_ctl_u { mmr_t sh_pi_md_rq_crd_ctl_regval; struct { @@ -22970,22 +12386,12 @@ typedef union sh_pi_md_rq_crd_ctl_u { mmr_t reserved_0 : 58; } sh_pi_md_rq_crd_ctl_s; } sh_pi_md_rq_crd_ctl_u_t; -#else -typedef union sh_pi_md_rq_crd_ctl_u { - mmr_t sh_pi_md_rq_crd_ctl_regval; - struct { - mmr_t reserved_0 : 58; - mmr_t depth : 6; - } sh_pi_md_rq_crd_ctl_s; -} sh_pi_md_rq_crd_ctl_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_MD_RP_CRD_CTL" */ /* pi_md_rp Credit Circulation Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_md_rp_crd_ctl_u { mmr_t sh_pi_md_rp_crd_ctl_regval; struct { @@ -22993,22 +12399,12 @@ typedef union sh_pi_md_rp_crd_ctl_u { mmr_t reserved_0 : 58; } sh_pi_md_rp_crd_ctl_s; } sh_pi_md_rp_crd_ctl_u_t; -#else -typedef union sh_pi_md_rp_crd_ctl_u { - mmr_t sh_pi_md_rp_crd_ctl_regval; - struct { - mmr_t reserved_0 : 58; - mmr_t depth : 6; - } sh_pi_md_rp_crd_ctl_s; -} sh_pi_md_rp_crd_ctl_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_RQ_CRD_CTL" */ /* xn_md_rq Credit Circulation Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_md_rq_crd_ctl_u { mmr_t sh_xn_md_rq_crd_ctl_regval; struct { @@ -23016,22 +12412,12 @@ typedef union sh_xn_md_rq_crd_ctl_u { mmr_t reserved_0 : 58; } sh_xn_md_rq_crd_ctl_s; } sh_xn_md_rq_crd_ctl_u_t; -#else -typedef union sh_xn_md_rq_crd_ctl_u { - mmr_t sh_xn_md_rq_crd_ctl_regval; - struct { - mmr_t reserved_0 : 58; - mmr_t depth : 6; - } sh_xn_md_rq_crd_ctl_s; -} sh_xn_md_rq_crd_ctl_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_RP_CRD_CTL" */ /* xn_md_rp Credit Circulation Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_md_rp_crd_ctl_u { mmr_t sh_xn_md_rp_crd_ctl_regval; struct { @@ -23039,22 +12425,12 @@ typedef union sh_xn_md_rp_crd_ctl_u { mmr_t reserved_0 : 58; } sh_xn_md_rp_crd_ctl_s; } sh_xn_md_rp_crd_ctl_u_t; -#else -typedef union sh_xn_md_rp_crd_ctl_u { - mmr_t sh_xn_md_rp_crd_ctl_regval; - struct { - mmr_t reserved_0 : 58; - mmr_t depth : 6; - } sh_xn_md_rp_crd_ctl_s; -} sh_xn_md_rp_crd_ctl_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_TAG0" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_tag0_u { mmr_t sh_x_tag0_regval; struct { @@ -23062,22 +12438,12 @@ typedef union sh_x_tag0_u { mmr_t reserved_0 : 44; } sh_x_tag0_s; } sh_x_tag0_u_t; -#else -typedef union sh_x_tag0_u { - mmr_t sh_x_tag0_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_x_tag0_s; -} sh_x_tag0_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_TAG1" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_tag1_u { mmr_t sh_x_tag1_regval; struct { @@ -23085,22 +12451,12 @@ typedef union sh_x_tag1_u { mmr_t reserved_0 : 44; } sh_x_tag1_s; } sh_x_tag1_u_t; -#else -typedef union sh_x_tag1_u { - mmr_t sh_x_tag1_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_x_tag1_s; -} sh_x_tag1_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_TAG2" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_tag2_u { mmr_t sh_x_tag2_regval; struct { @@ -23108,22 +12464,12 @@ typedef union sh_x_tag2_u { mmr_t reserved_0 : 44; } sh_x_tag2_s; } sh_x_tag2_u_t; -#else -typedef union sh_x_tag2_u { - mmr_t sh_x_tag2_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_x_tag2_s; -} sh_x_tag2_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_TAG3" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_tag3_u { mmr_t sh_x_tag3_regval; struct { @@ -23131,22 +12477,12 @@ typedef union sh_x_tag3_u { mmr_t reserved_0 : 44; } sh_x_tag3_s; } sh_x_tag3_u_t; -#else -typedef union sh_x_tag3_u { - mmr_t sh_x_tag3_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_x_tag3_s; -} sh_x_tag3_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_TAG4" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_tag4_u { mmr_t sh_x_tag4_regval; struct { @@ -23154,22 +12490,12 @@ typedef union sh_x_tag4_u { mmr_t reserved_0 : 44; } sh_x_tag4_s; } sh_x_tag4_u_t; -#else -typedef union sh_x_tag4_u { - mmr_t sh_x_tag4_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_x_tag4_s; -} sh_x_tag4_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_TAG5" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_tag5_u { mmr_t sh_x_tag5_regval; struct { @@ -23177,22 +12503,12 @@ typedef union sh_x_tag5_u { mmr_t reserved_0 : 44; } sh_x_tag5_s; } sh_x_tag5_u_t; -#else -typedef union sh_x_tag5_u { - mmr_t sh_x_tag5_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_x_tag5_s; -} sh_x_tag5_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_TAG6" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_tag6_u { mmr_t sh_x_tag6_regval; struct { @@ -23200,22 +12516,12 @@ typedef union sh_x_tag6_u { mmr_t reserved_0 : 44; } sh_x_tag6_s; } sh_x_tag6_u_t; -#else -typedef union sh_x_tag6_u { - mmr_t sh_x_tag6_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_x_tag6_s; -} sh_x_tag6_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_TAG7" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_tag7_u { mmr_t sh_x_tag7_regval; struct { @@ -23223,22 +12529,12 @@ typedef union sh_x_tag7_u { mmr_t reserved_0 : 44; } sh_x_tag7_s; } sh_x_tag7_u_t; -#else -typedef union sh_x_tag7_u { - mmr_t sh_x_tag7_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_x_tag7_s; -} sh_x_tag7_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_TAG0" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_tag0_u { mmr_t sh_y_tag0_regval; struct { @@ -23246,22 +12542,12 @@ typedef union sh_y_tag0_u { mmr_t reserved_0 : 44; } sh_y_tag0_s; } sh_y_tag0_u_t; -#else -typedef union sh_y_tag0_u { - mmr_t sh_y_tag0_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_y_tag0_s; -} sh_y_tag0_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_TAG1" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_tag1_u { mmr_t sh_y_tag1_regval; struct { @@ -23269,22 +12555,12 @@ typedef union sh_y_tag1_u { mmr_t reserved_0 : 44; } sh_y_tag1_s; } sh_y_tag1_u_t; -#else -typedef union sh_y_tag1_u { - mmr_t sh_y_tag1_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_y_tag1_s; -} sh_y_tag1_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_TAG2" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_tag2_u { mmr_t sh_y_tag2_regval; struct { @@ -23292,22 +12568,12 @@ typedef union sh_y_tag2_u { mmr_t reserved_0 : 44; } sh_y_tag2_s; } sh_y_tag2_u_t; -#else -typedef union sh_y_tag2_u { - mmr_t sh_y_tag2_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_y_tag2_s; -} sh_y_tag2_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_TAG3" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_tag3_u { mmr_t sh_y_tag3_regval; struct { @@ -23315,22 +12581,12 @@ typedef union sh_y_tag3_u { mmr_t reserved_0 : 44; } sh_y_tag3_s; } sh_y_tag3_u_t; -#else -typedef union sh_y_tag3_u { - mmr_t sh_y_tag3_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_y_tag3_s; -} sh_y_tag3_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_TAG4" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_tag4_u { mmr_t sh_y_tag4_regval; struct { @@ -23338,22 +12594,12 @@ typedef union sh_y_tag4_u { mmr_t reserved_0 : 44; } sh_y_tag4_s; } sh_y_tag4_u_t; -#else -typedef union sh_y_tag4_u { - mmr_t sh_y_tag4_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_y_tag4_s; -} sh_y_tag4_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_TAG5" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_tag5_u { mmr_t sh_y_tag5_regval; struct { @@ -23361,22 +12607,12 @@ typedef union sh_y_tag5_u { mmr_t reserved_0 : 44; } sh_y_tag5_s; } sh_y_tag5_u_t; -#else -typedef union sh_y_tag5_u { - mmr_t sh_y_tag5_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_y_tag5_s; -} sh_y_tag5_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_TAG6" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_tag6_u { mmr_t sh_y_tag6_regval; struct { @@ -23384,22 +12620,12 @@ typedef union sh_y_tag6_u { mmr_t reserved_0 : 44; } sh_y_tag6_s; } sh_y_tag6_u_t; -#else -typedef union sh_y_tag6_u { - mmr_t sh_y_tag6_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_y_tag6_s; -} sh_y_tag6_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_TAG7" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_tag7_u { mmr_t sh_y_tag7_regval; struct { @@ -23407,22 +12633,12 @@ typedef union sh_y_tag7_u { mmr_t reserved_0 : 44; } sh_y_tag7_s; } sh_y_tag7_u_t; -#else -typedef union sh_y_tag7_u { - mmr_t sh_y_tag7_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_y_tag7_s; -} sh_y_tag7_u_t; -#endif /* ==================================================================== */ /* Register "SH_MMRBIST_BASE" */ /* mmr/bist base address */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_mmrbist_base_u { mmr_t sh_mmrbist_base_regval; struct { @@ -23431,23 +12647,12 @@ typedef union sh_mmrbist_base_u { mmr_t reserved_1 : 14; } sh_mmrbist_base_s; } sh_mmrbist_base_u_t; -#else -typedef union sh_mmrbist_base_u { - mmr_t sh_mmrbist_base_regval; - struct { - mmr_t reserved_1 : 14; - mmr_t dword_addr : 47; - mmr_t reserved_0 : 3; - } sh_mmrbist_base_s; -} sh_mmrbist_base_u_t; -#endif /* ==================================================================== */ /* Register "SH_MMRBIST_CTL" */ /* Bist base address */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_mmrbist_ctl_u { mmr_t sh_mmrbist_ctl_regval; struct { @@ -23463,30 +12668,12 @@ typedef union sh_mmrbist_ctl_u { mmr_t reserved_3 : 19; } sh_mmrbist_ctl_s; } sh_mmrbist_ctl_u_t; -#else -typedef union sh_mmrbist_ctl_u { - mmr_t sh_mmrbist_ctl_regval; - struct { - mmr_t reserved_3 : 19; - mmr_t reset_state : 1; - mmr_t reserved_2 : 1; - mmr_t mem_idle : 1; - mmr_t fail : 1; - mmr_t in_progress : 1; - mmr_t reserved_1 : 1; - mmr_t cmd : 7; - mmr_t reserved_0 : 1; - mmr_t block_length : 31; - } sh_mmrbist_ctl_s; -} sh_mmrbist_ctl_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DBUG_DATA_CFG" */ /* configuration for md debug data muxes */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dbug_data_cfg_u { mmr_t sh_md_dbug_data_cfg_regval; struct { @@ -23524,52 +12711,12 @@ typedef union sh_md_dbug_data_cfg_u { mmr_t reserved_15 : 1; } sh_md_dbug_data_cfg_s; } sh_md_dbug_data_cfg_u_t; -#else -typedef union sh_md_dbug_data_cfg_u { - mmr_t sh_md_dbug_data_cfg_regval; - struct { - mmr_t reserved_15 : 1; - mmr_t nibble7_nibble : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_chiplet : 3; - mmr_t reserved_13 : 1; - mmr_t nibble6_nibble : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_chiplet : 3; - mmr_t reserved_11 : 1; - mmr_t nibble5_nibble : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_chiplet : 3; - mmr_t reserved_9 : 1; - mmr_t nibble4_nibble : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_chiplet : 3; - mmr_t reserved_7 : 1; - mmr_t nibble3_nibble : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_chiplet : 3; - mmr_t reserved_5 : 1; - mmr_t nibble2_nibble : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_chiplet : 3; - mmr_t reserved_3 : 1; - mmr_t nibble1_nibble : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_chiplet : 3; - mmr_t reserved_1 : 1; - mmr_t nibble0_nibble : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_chiplet : 3; - } sh_md_dbug_data_cfg_s; -} sh_md_dbug_data_cfg_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DBUG_TRIGGER_CFG" */ /* configuration for md debug triggers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dbug_trigger_cfg_u { mmr_t sh_md_dbug_trigger_cfg_regval; struct { @@ -23607,52 +12754,12 @@ typedef union sh_md_dbug_trigger_cfg_u { mmr_t enable : 1; } sh_md_dbug_trigger_cfg_s; } sh_md_dbug_trigger_cfg_u_t; -#else -typedef union sh_md_dbug_trigger_cfg_u { - mmr_t sh_md_dbug_trigger_cfg_regval; - struct { - mmr_t enable : 1; - mmr_t nibble7_nibble : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_chiplet : 3; - mmr_t reserved_13 : 1; - mmr_t nibble6_nibble : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_chiplet : 3; - mmr_t reserved_11 : 1; - mmr_t nibble5_nibble : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_chiplet : 3; - mmr_t reserved_9 : 1; - mmr_t nibble4_nibble : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_chiplet : 3; - mmr_t reserved_7 : 1; - mmr_t nibble3_nibble : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_chiplet : 3; - mmr_t reserved_5 : 1; - mmr_t nibble2_nibble : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_chiplet : 3; - mmr_t reserved_3 : 1; - mmr_t nibble1_nibble : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_chiplet : 3; - mmr_t reserved_1 : 1; - mmr_t nibble0_nibble : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_chiplet : 3; - } sh_md_dbug_trigger_cfg_s; -} sh_md_dbug_trigger_cfg_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DBUG_COMPARE" */ /* md debug compare pattern and mask */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dbug_compare_u { mmr_t sh_md_dbug_compare_regval; struct { @@ -23660,22 +12767,12 @@ typedef union sh_md_dbug_compare_u { mmr_t mask : 32; } sh_md_dbug_compare_s; } sh_md_dbug_compare_u_t; -#else -typedef union sh_md_dbug_compare_u { - mmr_t sh_md_dbug_compare_regval; - struct { - mmr_t mask : 32; - mmr_t pattern : 32; - } sh_md_dbug_compare_s; -} sh_md_dbug_compare_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_MOD_DBUG_SEL" */ /* MD acx debug select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_mod_dbug_sel_u { mmr_t sh_x_mod_dbug_sel_regval; struct { @@ -23689,28 +12786,12 @@ typedef union sh_x_mod_dbug_sel_u { mmr_t reserved_0 : 6; } sh_x_mod_dbug_sel_s; } sh_x_mod_dbug_sel_u_t; -#else -typedef union sh_x_mod_dbug_sel_u { - mmr_t sh_x_mod_dbug_sel_regval; - struct { - mmr_t reserved_0 : 6; - mmr_t dqr_sel : 6; - mmr_t dql_sel : 6; - mmr_t atr_sel : 11; - mmr_t atl_sel : 11; - mmr_t arb_sel : 8; - mmr_t wbq_sel : 8; - mmr_t tag_sel : 8; - } sh_x_mod_dbug_sel_s; -} sh_x_mod_dbug_sel_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_DBUG_SEL" */ /* MD acx debug select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_dbug_sel_u { mmr_t sh_x_dbug_sel_regval; struct { @@ -23718,22 +12799,12 @@ typedef union sh_x_dbug_sel_u { mmr_t reserved_0 : 40; } sh_x_dbug_sel_s; } sh_x_dbug_sel_u_t; -#else -typedef union sh_x_dbug_sel_u { - mmr_t sh_x_dbug_sel_regval; - struct { - mmr_t reserved_0 : 40; - mmr_t dbg_sel : 24; - } sh_x_dbug_sel_s; -} sh_x_dbug_sel_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_LADDR_CMP" */ /* MD acx address compare */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_laddr_cmp_u { mmr_t sh_x_laddr_cmp_regval; struct { @@ -23743,24 +12814,12 @@ typedef union sh_x_laddr_cmp_u { mmr_t reserved_1 : 4; } sh_x_laddr_cmp_s; } sh_x_laddr_cmp_u_t; -#else -typedef union sh_x_laddr_cmp_u { - mmr_t sh_x_laddr_cmp_regval; - struct { - mmr_t reserved_1 : 4; - mmr_t mask_val : 28; - mmr_t reserved_0 : 4; - mmr_t cmp_val : 28; - } sh_x_laddr_cmp_s; -} sh_x_laddr_cmp_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_RADDR_CMP" */ /* MD acx address compare */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_raddr_cmp_u { mmr_t sh_x_raddr_cmp_regval; struct { @@ -23770,24 +12829,12 @@ typedef union sh_x_raddr_cmp_u { mmr_t reserved_1 : 4; } sh_x_raddr_cmp_s; } sh_x_raddr_cmp_u_t; -#else -typedef union sh_x_raddr_cmp_u { - mmr_t sh_x_raddr_cmp_regval; - struct { - mmr_t reserved_1 : 4; - mmr_t mask_val : 28; - mmr_t reserved_0 : 4; - mmr_t cmp_val : 28; - } sh_x_raddr_cmp_s; -} sh_x_raddr_cmp_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_TAG_CMP" */ /* MD acx tagmgr compare */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_tag_cmp_u { mmr_t sh_x_tag_cmp_regval; struct { @@ -23797,24 +12844,12 @@ typedef union sh_x_tag_cmp_u { mmr_t reserved_0 : 9; } sh_x_tag_cmp_s; } sh_x_tag_cmp_u_t; -#else -typedef union sh_x_tag_cmp_u { - mmr_t sh_x_tag_cmp_regval; - struct { - mmr_t reserved_0 : 9; - mmr_t src : 14; - mmr_t addr : 33; - mmr_t cmd : 8; - } sh_x_tag_cmp_s; -} sh_x_tag_cmp_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_TAG_MASK" */ /* MD acx tagmgr mask */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_tag_mask_u { mmr_t sh_x_tag_mask_regval; struct { @@ -23824,24 +12859,12 @@ typedef union sh_x_tag_mask_u { mmr_t reserved_0 : 9; } sh_x_tag_mask_s; } sh_x_tag_mask_u_t; -#else -typedef union sh_x_tag_mask_u { - mmr_t sh_x_tag_mask_regval; - struct { - mmr_t reserved_0 : 9; - mmr_t src : 14; - mmr_t addr : 33; - mmr_t cmd : 8; - } sh_x_tag_mask_s; -} sh_x_tag_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_MOD_DBUG_SEL" */ /* MD acy debug select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_mod_dbug_sel_u { mmr_t sh_y_mod_dbug_sel_regval; struct { @@ -23855,28 +12878,12 @@ typedef union sh_y_mod_dbug_sel_u { mmr_t reserved_0 : 6; } sh_y_mod_dbug_sel_s; } sh_y_mod_dbug_sel_u_t; -#else -typedef union sh_y_mod_dbug_sel_u { - mmr_t sh_y_mod_dbug_sel_regval; - struct { - mmr_t reserved_0 : 6; - mmr_t dqr_sel : 6; - mmr_t dql_sel : 6; - mmr_t atr_sel : 11; - mmr_t atl_sel : 11; - mmr_t arb_sel : 8; - mmr_t wbq_sel : 8; - mmr_t tag_sel : 8; - } sh_y_mod_dbug_sel_s; -} sh_y_mod_dbug_sel_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_DBUG_SEL" */ /* MD acy debug select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_dbug_sel_u { mmr_t sh_y_dbug_sel_regval; struct { @@ -23884,22 +12891,12 @@ typedef union sh_y_dbug_sel_u { mmr_t reserved_0 : 40; } sh_y_dbug_sel_s; } sh_y_dbug_sel_u_t; -#else -typedef union sh_y_dbug_sel_u { - mmr_t sh_y_dbug_sel_regval; - struct { - mmr_t reserved_0 : 40; - mmr_t dbg_sel : 24; - } sh_y_dbug_sel_s; -} sh_y_dbug_sel_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_LADDR_CMP" */ /* MD acy address compare */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_laddr_cmp_u { mmr_t sh_y_laddr_cmp_regval; struct { @@ -23909,24 +12906,12 @@ typedef union sh_y_laddr_cmp_u { mmr_t reserved_1 : 4; } sh_y_laddr_cmp_s; } sh_y_laddr_cmp_u_t; -#else -typedef union sh_y_laddr_cmp_u { - mmr_t sh_y_laddr_cmp_regval; - struct { - mmr_t reserved_1 : 4; - mmr_t mask_val : 28; - mmr_t reserved_0 : 4; - mmr_t cmp_val : 28; - } sh_y_laddr_cmp_s; -} sh_y_laddr_cmp_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_RADDR_CMP" */ /* MD acy address compare */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_raddr_cmp_u { mmr_t sh_y_raddr_cmp_regval; struct { @@ -23936,24 +12921,12 @@ typedef union sh_y_raddr_cmp_u { mmr_t reserved_1 : 4; } sh_y_raddr_cmp_s; } sh_y_raddr_cmp_u_t; -#else -typedef union sh_y_raddr_cmp_u { - mmr_t sh_y_raddr_cmp_regval; - struct { - mmr_t reserved_1 : 4; - mmr_t mask_val : 28; - mmr_t reserved_0 : 4; - mmr_t cmp_val : 28; - } sh_y_raddr_cmp_s; -} sh_y_raddr_cmp_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_TAG_CMP" */ /* MD acy tagmgr compare */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_tag_cmp_u { mmr_t sh_y_tag_cmp_regval; struct { @@ -23963,24 +12936,12 @@ typedef union sh_y_tag_cmp_u { mmr_t reserved_0 : 9; } sh_y_tag_cmp_s; } sh_y_tag_cmp_u_t; -#else -typedef union sh_y_tag_cmp_u { - mmr_t sh_y_tag_cmp_regval; - struct { - mmr_t reserved_0 : 9; - mmr_t src : 14; - mmr_t addr : 33; - mmr_t cmd : 8; - } sh_y_tag_cmp_s; -} sh_y_tag_cmp_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_TAG_MASK" */ /* MD acy tagmgr mask */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_tag_mask_u { mmr_t sh_y_tag_mask_regval; struct { @@ -23990,24 +12951,12 @@ typedef union sh_y_tag_mask_u { mmr_t reserved_0 : 9; } sh_y_tag_mask_s; } sh_y_tag_mask_u_t; -#else -typedef union sh_y_tag_mask_u { - mmr_t sh_y_tag_mask_regval; - struct { - mmr_t reserved_0 : 9; - mmr_t src : 14; - mmr_t addr : 33; - mmr_t cmd : 8; - } sh_y_tag_mask_s; -} sh_y_tag_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_JNR_DBUG_DATA_CFG" */ /* configuration for md jnr debug data muxes */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_jnr_dbug_data_cfg_u { mmr_t sh_md_jnr_dbug_data_cfg_regval; struct { @@ -24029,36 +12978,12 @@ typedef union sh_md_jnr_dbug_data_cfg_u { mmr_t reserved_7 : 33; } sh_md_jnr_dbug_data_cfg_s; } sh_md_jnr_dbug_data_cfg_u_t; -#else -typedef union sh_md_jnr_dbug_data_cfg_u { - mmr_t sh_md_jnr_dbug_data_cfg_regval; - struct { - mmr_t reserved_7 : 33; - mmr_t nibble7_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble6_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble5_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble4_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble3_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble2_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble1_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_sel : 3; - } sh_md_jnr_dbug_data_cfg_s; -} sh_md_jnr_dbug_data_cfg_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_LAST_CREDIT" */ /* captures last credit values on reset */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_last_credit_u { mmr_t sh_md_last_credit_regval; struct { @@ -24074,30 +12999,12 @@ typedef union sh_md_last_credit_u { mmr_t reserved_4 : 26; } sh_md_last_credit_s; } sh_md_last_credit_u_t; -#else -typedef union sh_md_last_credit_u { - mmr_t sh_md_last_credit_regval; - struct { - mmr_t reserved_4 : 26; - mmr_t to_lb : 6; - mmr_t reserved_3 : 2; - mmr_t rp_to_xn : 6; - mmr_t reserved_2 : 2; - mmr_t rq_to_xn : 6; - mmr_t reserved_1 : 2; - mmr_t rp_to_pi : 6; - mmr_t reserved_0 : 2; - mmr_t rq_to_pi : 6; - } sh_md_last_credit_s; -} sh_md_last_credit_u_t; -#endif /* ==================================================================== */ /* Register "SH_MEM_CAPTURE_ADDR" */ /* Address capture address register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_mem_capture_addr_u { mmr_t sh_mem_capture_addr_regval; struct { @@ -24107,24 +13014,12 @@ typedef union sh_mem_capture_addr_u { mmr_t reserved_1 : 20; } sh_mem_capture_addr_s; } sh_mem_capture_addr_u_t; -#else -typedef union sh_mem_capture_addr_u { - mmr_t sh_mem_capture_addr_regval; - struct { - mmr_t reserved_1 : 20; - mmr_t cmd : 8; - mmr_t addr : 33; - mmr_t reserved_0 : 3; - } sh_mem_capture_addr_s; -} sh_mem_capture_addr_u_t; -#endif /* ==================================================================== */ /* Register "SH_MEM_CAPTURE_MASK" */ /* Address capture mask register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_mem_capture_mask_u { mmr_t sh_mem_capture_mask_regval; struct { @@ -24136,26 +13031,12 @@ typedef union sh_mem_capture_mask_u { mmr_t reserved_1 : 18; } sh_mem_capture_mask_s; } sh_mem_capture_mask_u_t; -#else -typedef union sh_mem_capture_mask_u { - mmr_t sh_mem_capture_mask_regval; - struct { - mmr_t reserved_1 : 18; - mmr_t enable_remote : 1; - mmr_t enable_local : 1; - mmr_t cmd : 8; - mmr_t addr : 33; - mmr_t reserved_0 : 3; - } sh_mem_capture_mask_s; -} sh_mem_capture_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_MEM_CAPTURE_HDR" */ /* Address capture header register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_mem_capture_hdr_u { mmr_t sh_mem_capture_hdr_regval; struct { @@ -24166,25 +13047,12 @@ typedef union sh_mem_capture_hdr_u { mmr_t cntr : 6; } sh_mem_capture_hdr_s; } sh_mem_capture_hdr_u_t; -#else -typedef union sh_mem_capture_hdr_u { - mmr_t sh_mem_capture_hdr_regval; - struct { - mmr_t cntr : 6; - mmr_t src : 14; - mmr_t cmd : 8; - mmr_t addr : 33; - mmr_t reserved_0 : 3; - } sh_mem_capture_hdr_s; -} sh_mem_capture_hdr_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_CONFIG" */ /* DQ directory config register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_dir_config_u { mmr_t sh_md_dqlp_mmr_dir_config_regval; struct { @@ -24194,276 +13062,156 @@ typedef union sh_md_dqlp_mmr_dir_config_u { mmr_t reserved_0 : 59; } sh_md_dqlp_mmr_dir_config_s; } sh_md_dqlp_mmr_dir_config_u_t; -#else -typedef union sh_md_dqlp_mmr_dir_config_u { - mmr_t sh_md_dqlp_mmr_dir_config_regval; - struct { - mmr_t reserved_0 : 59; - mmr_t en_dirpois : 1; - mmr_t en_direcc : 1; - mmr_t sys_size : 3; - } sh_md_dqlp_mmr_dir_config_s; -} sh_md_dqlp_mmr_dir_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_PRESVEC0" */ /* node [63:0] presence bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqlp_mmr_dir_presvec0_u { - mmr_t sh_md_dqlp_mmr_dir_presvec0_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_presvec0_s; -} sh_md_dqlp_mmr_dir_presvec0_u_t; -#else typedef union sh_md_dqlp_mmr_dir_presvec0_u { mmr_t sh_md_dqlp_mmr_dir_presvec0_regval; struct { mmr_t vec : 64; } sh_md_dqlp_mmr_dir_presvec0_s; } sh_md_dqlp_mmr_dir_presvec0_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_PRESVEC1" */ /* node [127:64] presence bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqlp_mmr_dir_presvec1_u { - mmr_t sh_md_dqlp_mmr_dir_presvec1_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_presvec1_s; -} sh_md_dqlp_mmr_dir_presvec1_u_t; -#else typedef union sh_md_dqlp_mmr_dir_presvec1_u { mmr_t sh_md_dqlp_mmr_dir_presvec1_regval; struct { mmr_t vec : 64; } sh_md_dqlp_mmr_dir_presvec1_s; } sh_md_dqlp_mmr_dir_presvec1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_PRESVEC2" */ /* node [191:128] presence bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqlp_mmr_dir_presvec2_u { - mmr_t sh_md_dqlp_mmr_dir_presvec2_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_presvec2_s; -} sh_md_dqlp_mmr_dir_presvec2_u_t; -#else typedef union sh_md_dqlp_mmr_dir_presvec2_u { mmr_t sh_md_dqlp_mmr_dir_presvec2_regval; struct { mmr_t vec : 64; } sh_md_dqlp_mmr_dir_presvec2_s; } sh_md_dqlp_mmr_dir_presvec2_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_PRESVEC3" */ /* node [255:192] presence bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqlp_mmr_dir_presvec3_u { - mmr_t sh_md_dqlp_mmr_dir_presvec3_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_presvec3_s; -} sh_md_dqlp_mmr_dir_presvec3_u_t; -#else typedef union sh_md_dqlp_mmr_dir_presvec3_u { mmr_t sh_md_dqlp_mmr_dir_presvec3_regval; struct { mmr_t vec : 64; } sh_md_dqlp_mmr_dir_presvec3_s; } sh_md_dqlp_mmr_dir_presvec3_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC0" */ /* local vector for acc=0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_dir_locvec0_u { mmr_t sh_md_dqlp_mmr_dir_locvec0_regval; struct { mmr_t vec : 64; } sh_md_dqlp_mmr_dir_locvec0_s; } sh_md_dqlp_mmr_dir_locvec0_u_t; -#else -typedef union sh_md_dqlp_mmr_dir_locvec0_u { - mmr_t sh_md_dqlp_mmr_dir_locvec0_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_locvec0_s; -} sh_md_dqlp_mmr_dir_locvec0_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC1" */ /* local vector for acc=1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqlp_mmr_dir_locvec1_u { - mmr_t sh_md_dqlp_mmr_dir_locvec1_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_locvec1_s; -} sh_md_dqlp_mmr_dir_locvec1_u_t; -#else typedef union sh_md_dqlp_mmr_dir_locvec1_u { mmr_t sh_md_dqlp_mmr_dir_locvec1_regval; struct { mmr_t vec : 64; } sh_md_dqlp_mmr_dir_locvec1_s; } sh_md_dqlp_mmr_dir_locvec1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC2" */ /* local vector for acc=2 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqlp_mmr_dir_locvec2_u { - mmr_t sh_md_dqlp_mmr_dir_locvec2_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_locvec2_s; -} sh_md_dqlp_mmr_dir_locvec2_u_t; -#else typedef union sh_md_dqlp_mmr_dir_locvec2_u { mmr_t sh_md_dqlp_mmr_dir_locvec2_regval; struct { mmr_t vec : 64; } sh_md_dqlp_mmr_dir_locvec2_s; } sh_md_dqlp_mmr_dir_locvec2_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC3" */ /* local vector for acc=3 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqlp_mmr_dir_locvec3_u { - mmr_t sh_md_dqlp_mmr_dir_locvec3_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_locvec3_s; -} sh_md_dqlp_mmr_dir_locvec3_u_t; -#else typedef union sh_md_dqlp_mmr_dir_locvec3_u { mmr_t sh_md_dqlp_mmr_dir_locvec3_regval; struct { mmr_t vec : 64; } sh_md_dqlp_mmr_dir_locvec3_s; } sh_md_dqlp_mmr_dir_locvec3_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC4" */ /* local vector for acc=4 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqlp_mmr_dir_locvec4_u { - mmr_t sh_md_dqlp_mmr_dir_locvec4_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_locvec4_s; -} sh_md_dqlp_mmr_dir_locvec4_u_t; -#else typedef union sh_md_dqlp_mmr_dir_locvec4_u { mmr_t sh_md_dqlp_mmr_dir_locvec4_regval; struct { mmr_t vec : 64; } sh_md_dqlp_mmr_dir_locvec4_s; } sh_md_dqlp_mmr_dir_locvec4_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC5" */ /* local vector for acc=5 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqlp_mmr_dir_locvec5_u { - mmr_t sh_md_dqlp_mmr_dir_locvec5_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_locvec5_s; -} sh_md_dqlp_mmr_dir_locvec5_u_t; -#else typedef union sh_md_dqlp_mmr_dir_locvec5_u { mmr_t sh_md_dqlp_mmr_dir_locvec5_regval; struct { mmr_t vec : 64; } sh_md_dqlp_mmr_dir_locvec5_s; } sh_md_dqlp_mmr_dir_locvec5_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC6" */ /* local vector for acc=6 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqlp_mmr_dir_locvec6_u { - mmr_t sh_md_dqlp_mmr_dir_locvec6_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_locvec6_s; -} sh_md_dqlp_mmr_dir_locvec6_u_t; -#else typedef union sh_md_dqlp_mmr_dir_locvec6_u { mmr_t sh_md_dqlp_mmr_dir_locvec6_regval; struct { mmr_t vec : 64; } sh_md_dqlp_mmr_dir_locvec6_s; } sh_md_dqlp_mmr_dir_locvec6_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC7" */ /* local vector for acc=7 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_dir_locvec7_u { mmr_t sh_md_dqlp_mmr_dir_locvec7_regval; struct { mmr_t vec : 64; } sh_md_dqlp_mmr_dir_locvec7_s; } sh_md_dqlp_mmr_dir_locvec7_u_t; -#else -typedef union sh_md_dqlp_mmr_dir_locvec7_u { - mmr_t sh_md_dqlp_mmr_dir_locvec7_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_locvec7_s; -} sh_md_dqlp_mmr_dir_locvec7_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC0" */ /* privilege vector for acc=0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_dir_privec0_u { mmr_t sh_md_dqlp_mmr_dir_privec0_regval; struct { @@ -24472,23 +13220,12 @@ typedef union sh_md_dqlp_mmr_dir_privec0_u { mmr_t reserved_0 : 36; } sh_md_dqlp_mmr_dir_privec0_s; } sh_md_dqlp_mmr_dir_privec0_u_t; -#else -typedef union sh_md_dqlp_mmr_dir_privec0_u { - mmr_t sh_md_dqlp_mmr_dir_privec0_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqlp_mmr_dir_privec0_s; -} sh_md_dqlp_mmr_dir_privec0_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC1" */ /* privilege vector for acc=1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_dir_privec1_u { mmr_t sh_md_dqlp_mmr_dir_privec1_regval; struct { @@ -24497,23 +13234,12 @@ typedef union sh_md_dqlp_mmr_dir_privec1_u { mmr_t reserved_0 : 36; } sh_md_dqlp_mmr_dir_privec1_s; } sh_md_dqlp_mmr_dir_privec1_u_t; -#else -typedef union sh_md_dqlp_mmr_dir_privec1_u { - mmr_t sh_md_dqlp_mmr_dir_privec1_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqlp_mmr_dir_privec1_s; -} sh_md_dqlp_mmr_dir_privec1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC2" */ /* privilege vector for acc=2 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_dir_privec2_u { mmr_t sh_md_dqlp_mmr_dir_privec2_regval; struct { @@ -24522,23 +13248,12 @@ typedef union sh_md_dqlp_mmr_dir_privec2_u { mmr_t reserved_0 : 36; } sh_md_dqlp_mmr_dir_privec2_s; } sh_md_dqlp_mmr_dir_privec2_u_t; -#else -typedef union sh_md_dqlp_mmr_dir_privec2_u { - mmr_t sh_md_dqlp_mmr_dir_privec2_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqlp_mmr_dir_privec2_s; -} sh_md_dqlp_mmr_dir_privec2_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC3" */ /* privilege vector for acc=3 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_dir_privec3_u { mmr_t sh_md_dqlp_mmr_dir_privec3_regval; struct { @@ -24547,23 +13262,12 @@ typedef union sh_md_dqlp_mmr_dir_privec3_u { mmr_t reserved_0 : 36; } sh_md_dqlp_mmr_dir_privec3_s; } sh_md_dqlp_mmr_dir_privec3_u_t; -#else -typedef union sh_md_dqlp_mmr_dir_privec3_u { - mmr_t sh_md_dqlp_mmr_dir_privec3_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqlp_mmr_dir_privec3_s; -} sh_md_dqlp_mmr_dir_privec3_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC4" */ /* privilege vector for acc=4 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_dir_privec4_u { mmr_t sh_md_dqlp_mmr_dir_privec4_regval; struct { @@ -24572,23 +13276,12 @@ typedef union sh_md_dqlp_mmr_dir_privec4_u { mmr_t reserved_0 : 36; } sh_md_dqlp_mmr_dir_privec4_s; } sh_md_dqlp_mmr_dir_privec4_u_t; -#else -typedef union sh_md_dqlp_mmr_dir_privec4_u { - mmr_t sh_md_dqlp_mmr_dir_privec4_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqlp_mmr_dir_privec4_s; -} sh_md_dqlp_mmr_dir_privec4_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC5" */ /* privilege vector for acc=5 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_dir_privec5_u { mmr_t sh_md_dqlp_mmr_dir_privec5_regval; struct { @@ -24597,23 +13290,12 @@ typedef union sh_md_dqlp_mmr_dir_privec5_u { mmr_t reserved_0 : 36; } sh_md_dqlp_mmr_dir_privec5_s; } sh_md_dqlp_mmr_dir_privec5_u_t; -#else -typedef union sh_md_dqlp_mmr_dir_privec5_u { - mmr_t sh_md_dqlp_mmr_dir_privec5_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqlp_mmr_dir_privec5_s; -} sh_md_dqlp_mmr_dir_privec5_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC6" */ /* privilege vector for acc=6 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_dir_privec6_u { mmr_t sh_md_dqlp_mmr_dir_privec6_regval; struct { @@ -24622,23 +13304,12 @@ typedef union sh_md_dqlp_mmr_dir_privec6_u { mmr_t reserved_0 : 36; } sh_md_dqlp_mmr_dir_privec6_s; } sh_md_dqlp_mmr_dir_privec6_u_t; -#else -typedef union sh_md_dqlp_mmr_dir_privec6_u { - mmr_t sh_md_dqlp_mmr_dir_privec6_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqlp_mmr_dir_privec6_s; -} sh_md_dqlp_mmr_dir_privec6_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC7" */ /* privilege vector for acc=7 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_dir_privec7_u { mmr_t sh_md_dqlp_mmr_dir_privec7_regval; struct { @@ -24647,23 +13318,12 @@ typedef union sh_md_dqlp_mmr_dir_privec7_u { mmr_t reserved_0 : 36; } sh_md_dqlp_mmr_dir_privec7_s; } sh_md_dqlp_mmr_dir_privec7_u_t; -#else -typedef union sh_md_dqlp_mmr_dir_privec7_u { - mmr_t sh_md_dqlp_mmr_dir_privec7_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqlp_mmr_dir_privec7_s; -} sh_md_dqlp_mmr_dir_privec7_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_TIMER" */ /* MD SXRO timer */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_dir_timer_u { mmr_t sh_md_dqlp_mmr_dir_timer_regval; struct { @@ -24673,24 +13333,12 @@ typedef union sh_md_dqlp_mmr_dir_timer_u { mmr_t reserved_0 : 42; } sh_md_dqlp_mmr_dir_timer_s; } sh_md_dqlp_mmr_dir_timer_u_t; -#else -typedef union sh_md_dqlp_mmr_dir_timer_u { - mmr_t sh_md_dqlp_mmr_dir_timer_regval; - struct { - mmr_t reserved_0 : 42; - mmr_t timer_cur : 9; - mmr_t timer_en : 1; - mmr_t timer_div : 12; - } sh_md_dqlp_mmr_dir_timer_s; -} sh_md_dqlp_mmr_dir_timer_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY" */ /* directory pio write data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_piowd_dir_entry_u { mmr_t sh_md_dqlp_mmr_piowd_dir_entry_regval; struct { @@ -24701,25 +13349,12 @@ typedef union sh_md_dqlp_mmr_piowd_dir_entry_u { mmr_t reserved_0 : 6; } sh_md_dqlp_mmr_piowd_dir_entry_s; } sh_md_dqlp_mmr_piowd_dir_entry_u_t; -#else -typedef union sh_md_dqlp_mmr_piowd_dir_entry_u { - mmr_t sh_md_dqlp_mmr_piowd_dir_entry_regval; - struct { - mmr_t reserved_0 : 6; - mmr_t acc : 3; - mmr_t pri : 3; - mmr_t dirb : 26; - mmr_t dira : 26; - } sh_md_dqlp_mmr_piowd_dir_entry_s; -} sh_md_dqlp_mmr_piowd_dir_entry_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_PIOWD_DIR_ECC" */ /* directory ecc register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_piowd_dir_ecc_u { mmr_t sh_md_dqlp_mmr_piowd_dir_ecc_regval; struct { @@ -24728,23 +13363,12 @@ typedef union sh_md_dqlp_mmr_piowd_dir_ecc_u { mmr_t reserved_0 : 50; } sh_md_dqlp_mmr_piowd_dir_ecc_s; } sh_md_dqlp_mmr_piowd_dir_ecc_u_t; -#else -typedef union sh_md_dqlp_mmr_piowd_dir_ecc_u { - mmr_t sh_md_dqlp_mmr_piowd_dir_ecc_regval; - struct { - mmr_t reserved_0 : 50; - mmr_t eccb : 7; - mmr_t ecca : 7; - } sh_md_dqlp_mmr_piowd_dir_ecc_s; -} sh_md_dqlp_mmr_piowd_dir_ecc_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY" */ /* x directory pio read data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_xpiord_xdir_entry_u { mmr_t sh_md_dqlp_mmr_xpiord_xdir_entry_regval; struct { @@ -24757,27 +13381,12 @@ typedef union sh_md_dqlp_mmr_xpiord_xdir_entry_u { mmr_t reserved_0 : 4; } sh_md_dqlp_mmr_xpiord_xdir_entry_s; } sh_md_dqlp_mmr_xpiord_xdir_entry_u_t; -#else -typedef union sh_md_dqlp_mmr_xpiord_xdir_entry_u { - mmr_t sh_md_dqlp_mmr_xpiord_xdir_entry_regval; - struct { - mmr_t reserved_0 : 4; - mmr_t unc : 1; - mmr_t cor : 1; - mmr_t acc : 3; - mmr_t pri : 3; - mmr_t dirb : 26; - mmr_t dira : 26; - } sh_md_dqlp_mmr_xpiord_xdir_entry_s; -} sh_md_dqlp_mmr_xpiord_xdir_entry_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_XPIORD_XDIR_ECC" */ /* x directory ecc */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_xpiord_xdir_ecc_u { mmr_t sh_md_dqlp_mmr_xpiord_xdir_ecc_regval; struct { @@ -24786,23 +13395,12 @@ typedef union sh_md_dqlp_mmr_xpiord_xdir_ecc_u { mmr_t reserved_0 : 50; } sh_md_dqlp_mmr_xpiord_xdir_ecc_s; } sh_md_dqlp_mmr_xpiord_xdir_ecc_u_t; -#else -typedef union sh_md_dqlp_mmr_xpiord_xdir_ecc_u { - mmr_t sh_md_dqlp_mmr_xpiord_xdir_ecc_regval; - struct { - mmr_t reserved_0 : 50; - mmr_t eccb : 7; - mmr_t ecca : 7; - } sh_md_dqlp_mmr_xpiord_xdir_ecc_s; -} sh_md_dqlp_mmr_xpiord_xdir_ecc_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY" */ /* y directory pio read data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_ypiord_ydir_entry_u { mmr_t sh_md_dqlp_mmr_ypiord_ydir_entry_regval; struct { @@ -24815,27 +13413,12 @@ typedef union sh_md_dqlp_mmr_ypiord_ydir_entry_u { mmr_t reserved_0 : 4; } sh_md_dqlp_mmr_ypiord_ydir_entry_s; } sh_md_dqlp_mmr_ypiord_ydir_entry_u_t; -#else -typedef union sh_md_dqlp_mmr_ypiord_ydir_entry_u { - mmr_t sh_md_dqlp_mmr_ypiord_ydir_entry_regval; - struct { - mmr_t reserved_0 : 4; - mmr_t unc : 1; - mmr_t cor : 1; - mmr_t acc : 3; - mmr_t pri : 3; - mmr_t dirb : 26; - mmr_t dira : 26; - } sh_md_dqlp_mmr_ypiord_ydir_entry_s; -} sh_md_dqlp_mmr_ypiord_ydir_entry_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_YPIORD_YDIR_ECC" */ /* y directory ecc */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_ypiord_ydir_ecc_u { mmr_t sh_md_dqlp_mmr_ypiord_ydir_ecc_regval; struct { @@ -24844,23 +13427,12 @@ typedef union sh_md_dqlp_mmr_ypiord_ydir_ecc_u { mmr_t reserved_0 : 50; } sh_md_dqlp_mmr_ypiord_ydir_ecc_s; } sh_md_dqlp_mmr_ypiord_ydir_ecc_u_t; -#else -typedef union sh_md_dqlp_mmr_ypiord_ydir_ecc_u { - mmr_t sh_md_dqlp_mmr_ypiord_ydir_ecc_regval; - struct { - mmr_t reserved_0 : 50; - mmr_t eccb : 7; - mmr_t ecca : 7; - } sh_md_dqlp_mmr_ypiord_ydir_ecc_s; -} sh_md_dqlp_mmr_ypiord_ydir_ecc_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_XCERR1" */ /* correctable dir ecc group 1 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_xcerr1_u { mmr_t sh_md_dqlp_mmr_xcerr1_regval; struct { @@ -24871,25 +13443,12 @@ typedef union sh_md_dqlp_mmr_xcerr1_u { mmr_t reserved_0 : 25; } sh_md_dqlp_mmr_xcerr1_s; } sh_md_dqlp_mmr_xcerr1_u_t; -#else -typedef union sh_md_dqlp_mmr_xcerr1_u { - mmr_t sh_md_dqlp_mmr_xcerr1_regval; - struct { - mmr_t reserved_0 : 25; - mmr_t arm : 1; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp1 : 36; - } sh_md_dqlp_mmr_xcerr1_s; -} sh_md_dqlp_mmr_xcerr1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_XCERR2" */ /* correctable dir ecc group 2 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_xcerr2_u { mmr_t sh_md_dqlp_mmr_xcerr2_regval; struct { @@ -24899,24 +13458,12 @@ typedef union sh_md_dqlp_mmr_xcerr2_u { mmr_t reserved_0 : 26; } sh_md_dqlp_mmr_xcerr2_s; } sh_md_dqlp_mmr_xcerr2_u_t; -#else -typedef union sh_md_dqlp_mmr_xcerr2_u { - mmr_t sh_md_dqlp_mmr_xcerr2_regval; - struct { - mmr_t reserved_0 : 26; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp2 : 36; - } sh_md_dqlp_mmr_xcerr2_s; -} sh_md_dqlp_mmr_xcerr2_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_XUERR1" */ /* uncorrectable dir ecc group 1 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_xuerr1_u { mmr_t sh_md_dqlp_mmr_xuerr1_regval; struct { @@ -24927,25 +13474,12 @@ typedef union sh_md_dqlp_mmr_xuerr1_u { mmr_t reserved_0 : 25; } sh_md_dqlp_mmr_xuerr1_s; } sh_md_dqlp_mmr_xuerr1_u_t; -#else -typedef union sh_md_dqlp_mmr_xuerr1_u { - mmr_t sh_md_dqlp_mmr_xuerr1_regval; - struct { - mmr_t reserved_0 : 25; - mmr_t arm : 1; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp1 : 36; - } sh_md_dqlp_mmr_xuerr1_s; -} sh_md_dqlp_mmr_xuerr1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_XUERR2" */ /* uncorrectable dir ecc group 2 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_xuerr2_u { mmr_t sh_md_dqlp_mmr_xuerr2_regval; struct { @@ -24955,24 +13489,12 @@ typedef union sh_md_dqlp_mmr_xuerr2_u { mmr_t reserved_0 : 26; } sh_md_dqlp_mmr_xuerr2_s; } sh_md_dqlp_mmr_xuerr2_u_t; -#else -typedef union sh_md_dqlp_mmr_xuerr2_u { - mmr_t sh_md_dqlp_mmr_xuerr2_regval; - struct { - mmr_t reserved_0 : 26; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp2 : 36; - } sh_md_dqlp_mmr_xuerr2_s; -} sh_md_dqlp_mmr_xuerr2_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_XPERR" */ /* protocol error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_xperr_u { mmr_t sh_md_dqlp_mmr_xperr_regval; struct { @@ -24990,32 +13512,12 @@ typedef union sh_md_dqlp_mmr_xperr_u { mmr_t reserved_0 : 1; } sh_md_dqlp_mmr_xperr_s; } sh_md_dqlp_mmr_xperr_u_t; -#else -typedef union sh_md_dqlp_mmr_xperr_u { - mmr_t sh_md_dqlp_mmr_xperr_regval; - struct { - mmr_t reserved_0 : 1; - mmr_t arm : 1; - mmr_t more : 1; - mmr_t val : 1; - mmr_t mybit : 8; - mmr_t unc : 1; - mmr_t cor : 1; - mmr_t priv : 1; - mmr_t prige : 1; - mmr_t src : 14; - mmr_t cmd : 8; - mmr_t dir : 26; - } sh_md_dqlp_mmr_xperr_s; -} sh_md_dqlp_mmr_xperr_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_YCERR1" */ /* correctable dir ecc group 1 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_ycerr1_u { mmr_t sh_md_dqlp_mmr_ycerr1_regval; struct { @@ -25026,25 +13528,12 @@ typedef union sh_md_dqlp_mmr_ycerr1_u { mmr_t reserved_0 : 25; } sh_md_dqlp_mmr_ycerr1_s; } sh_md_dqlp_mmr_ycerr1_u_t; -#else -typedef union sh_md_dqlp_mmr_ycerr1_u { - mmr_t sh_md_dqlp_mmr_ycerr1_regval; - struct { - mmr_t reserved_0 : 25; - mmr_t arm : 1; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp1 : 36; - } sh_md_dqlp_mmr_ycerr1_s; -} sh_md_dqlp_mmr_ycerr1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_YCERR2" */ /* correctable dir ecc group 2 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_ycerr2_u { mmr_t sh_md_dqlp_mmr_ycerr2_regval; struct { @@ -25054,24 +13543,12 @@ typedef union sh_md_dqlp_mmr_ycerr2_u { mmr_t reserved_0 : 26; } sh_md_dqlp_mmr_ycerr2_s; } sh_md_dqlp_mmr_ycerr2_u_t; -#else -typedef union sh_md_dqlp_mmr_ycerr2_u { - mmr_t sh_md_dqlp_mmr_ycerr2_regval; - struct { - mmr_t reserved_0 : 26; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp2 : 36; - } sh_md_dqlp_mmr_ycerr2_s; -} sh_md_dqlp_mmr_ycerr2_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_YUERR1" */ /* uncorrectable dir ecc group 1 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_yuerr1_u { mmr_t sh_md_dqlp_mmr_yuerr1_regval; struct { @@ -25082,25 +13559,12 @@ typedef union sh_md_dqlp_mmr_yuerr1_u { mmr_t reserved_0 : 25; } sh_md_dqlp_mmr_yuerr1_s; } sh_md_dqlp_mmr_yuerr1_u_t; -#else -typedef union sh_md_dqlp_mmr_yuerr1_u { - mmr_t sh_md_dqlp_mmr_yuerr1_regval; - struct { - mmr_t reserved_0 : 25; - mmr_t arm : 1; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp1 : 36; - } sh_md_dqlp_mmr_yuerr1_s; -} sh_md_dqlp_mmr_yuerr1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_YUERR2" */ /* uncorrectable dir ecc group 2 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_yuerr2_u { mmr_t sh_md_dqlp_mmr_yuerr2_regval; struct { @@ -25110,24 +13574,12 @@ typedef union sh_md_dqlp_mmr_yuerr2_u { mmr_t reserved_0 : 26; } sh_md_dqlp_mmr_yuerr2_s; } sh_md_dqlp_mmr_yuerr2_u_t; -#else -typedef union sh_md_dqlp_mmr_yuerr2_u { - mmr_t sh_md_dqlp_mmr_yuerr2_regval; - struct { - mmr_t reserved_0 : 26; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp2 : 36; - } sh_md_dqlp_mmr_yuerr2_s; -} sh_md_dqlp_mmr_yuerr2_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_YPERR" */ /* protocol error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_yperr_u { mmr_t sh_md_dqlp_mmr_yperr_regval; struct { @@ -25145,32 +13597,12 @@ typedef union sh_md_dqlp_mmr_yperr_u { mmr_t reserved_0 : 1; } sh_md_dqlp_mmr_yperr_s; } sh_md_dqlp_mmr_yperr_u_t; -#else -typedef union sh_md_dqlp_mmr_yperr_u { - mmr_t sh_md_dqlp_mmr_yperr_regval; - struct { - mmr_t reserved_0 : 1; - mmr_t arm : 1; - mmr_t more : 1; - mmr_t val : 1; - mmr_t mybit : 8; - mmr_t unc : 1; - mmr_t cor : 1; - mmr_t priv : 1; - mmr_t prige : 1; - mmr_t src : 14; - mmr_t cmd : 8; - mmr_t dir : 26; - } sh_md_dqlp_mmr_yperr_s; -} sh_md_dqlp_mmr_yperr_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_CMDTRIG" */ /* cmd triggers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_dir_cmdtrig_u { mmr_t sh_md_dqlp_mmr_dir_cmdtrig_regval; struct { @@ -25181,25 +13613,12 @@ typedef union sh_md_dqlp_mmr_dir_cmdtrig_u { mmr_t reserved_0 : 32; } sh_md_dqlp_mmr_dir_cmdtrig_s; } sh_md_dqlp_mmr_dir_cmdtrig_u_t; -#else -typedef union sh_md_dqlp_mmr_dir_cmdtrig_u { - mmr_t sh_md_dqlp_mmr_dir_cmdtrig_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t cmd3 : 8; - mmr_t cmd2 : 8; - mmr_t cmd1 : 8; - mmr_t cmd0 : 8; - } sh_md_dqlp_mmr_dir_cmdtrig_s; -} sh_md_dqlp_mmr_dir_cmdtrig_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_TBLTRIG" */ /* dir table trigger */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_dir_tbltrig_u { mmr_t sh_md_dqlp_mmr_dir_tbltrig_regval; struct { @@ -25212,27 +13631,12 @@ typedef union sh_md_dqlp_mmr_dir_tbltrig_u { mmr_t reserved_0 : 22; } sh_md_dqlp_mmr_dir_tbltrig_s; } sh_md_dqlp_mmr_dir_tbltrig_u_t; -#else -typedef union sh_md_dqlp_mmr_dir_tbltrig_u { - mmr_t sh_md_dqlp_mmr_dir_tbltrig_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t mybit : 8; - mmr_t dirst : 9; - mmr_t prige : 1; - mmr_t acc : 2; - mmr_t cmd : 8; - mmr_t src : 14; - } sh_md_dqlp_mmr_dir_tbltrig_s; -} sh_md_dqlp_mmr_dir_tbltrig_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_TBLMASK" */ /* dir table trigger mask */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_dir_tblmask_u { mmr_t sh_md_dqlp_mmr_dir_tblmask_regval; struct { @@ -25245,27 +13649,12 @@ typedef union sh_md_dqlp_mmr_dir_tblmask_u { mmr_t reserved_0 : 22; } sh_md_dqlp_mmr_dir_tblmask_s; } sh_md_dqlp_mmr_dir_tblmask_u_t; -#else -typedef union sh_md_dqlp_mmr_dir_tblmask_u { - mmr_t sh_md_dqlp_mmr_dir_tblmask_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t mybit : 8; - mmr_t dirst : 9; - mmr_t prige : 1; - mmr_t acc : 2; - mmr_t cmd : 8; - mmr_t src : 14; - } sh_md_dqlp_mmr_dir_tblmask_s; -} sh_md_dqlp_mmr_dir_tblmask_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_XBIST_H" */ /* rising edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_xbist_h_u { mmr_t sh_md_dqlp_mmr_xbist_h_regval; struct { @@ -25277,26 +13666,12 @@ typedef union sh_md_dqlp_mmr_xbist_h_u { mmr_t reserved_1 : 21; } sh_md_dqlp_mmr_xbist_h_s; } sh_md_dqlp_mmr_xbist_h_u_t; -#else -typedef union sh_md_dqlp_mmr_xbist_h_u { - mmr_t sh_md_dqlp_mmr_xbist_h_regval; - struct { - mmr_t reserved_1 : 21; - mmr_t arm : 1; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqlp_mmr_xbist_h_s; -} sh_md_dqlp_mmr_xbist_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_XBIST_L" */ /* falling edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_xbist_l_u { mmr_t sh_md_dqlp_mmr_xbist_l_regval; struct { @@ -25307,25 +13682,12 @@ typedef union sh_md_dqlp_mmr_xbist_l_u { mmr_t reserved_1 : 22; } sh_md_dqlp_mmr_xbist_l_s; } sh_md_dqlp_mmr_xbist_l_u_t; -#else -typedef union sh_md_dqlp_mmr_xbist_l_u { - mmr_t sh_md_dqlp_mmr_xbist_l_regval; - struct { - mmr_t reserved_1 : 22; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqlp_mmr_xbist_l_s; -} sh_md_dqlp_mmr_xbist_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_XBIST_ERR_H" */ /* rising edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_xbist_err_h_u { mmr_t sh_md_dqlp_mmr_xbist_err_h_regval; struct { @@ -25336,25 +13698,12 @@ typedef union sh_md_dqlp_mmr_xbist_err_h_u { mmr_t reserved_1 : 22; } sh_md_dqlp_mmr_xbist_err_h_s; } sh_md_dqlp_mmr_xbist_err_h_u_t; -#else -typedef union sh_md_dqlp_mmr_xbist_err_h_u { - mmr_t sh_md_dqlp_mmr_xbist_err_h_regval; - struct { - mmr_t reserved_1 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqlp_mmr_xbist_err_h_s; -} sh_md_dqlp_mmr_xbist_err_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_XBIST_ERR_L" */ /* falling edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_xbist_err_l_u { mmr_t sh_md_dqlp_mmr_xbist_err_l_regval; struct { @@ -25365,25 +13714,12 @@ typedef union sh_md_dqlp_mmr_xbist_err_l_u { mmr_t reserved_1 : 22; } sh_md_dqlp_mmr_xbist_err_l_s; } sh_md_dqlp_mmr_xbist_err_l_u_t; -#else -typedef union sh_md_dqlp_mmr_xbist_err_l_u { - mmr_t sh_md_dqlp_mmr_xbist_err_l_regval; - struct { - mmr_t reserved_1 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqlp_mmr_xbist_err_l_s; -} sh_md_dqlp_mmr_xbist_err_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_YBIST_H" */ /* rising edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_ybist_h_u { mmr_t sh_md_dqlp_mmr_ybist_h_regval; struct { @@ -25395,26 +13731,12 @@ typedef union sh_md_dqlp_mmr_ybist_h_u { mmr_t reserved_1 : 21; } sh_md_dqlp_mmr_ybist_h_s; } sh_md_dqlp_mmr_ybist_h_u_t; -#else -typedef union sh_md_dqlp_mmr_ybist_h_u { - mmr_t sh_md_dqlp_mmr_ybist_h_regval; - struct { - mmr_t reserved_1 : 21; - mmr_t arm : 1; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqlp_mmr_ybist_h_s; -} sh_md_dqlp_mmr_ybist_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_YBIST_L" */ /* falling edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_ybist_l_u { mmr_t sh_md_dqlp_mmr_ybist_l_regval; struct { @@ -25425,25 +13747,12 @@ typedef union sh_md_dqlp_mmr_ybist_l_u { mmr_t reserved_1 : 22; } sh_md_dqlp_mmr_ybist_l_s; } sh_md_dqlp_mmr_ybist_l_u_t; -#else -typedef union sh_md_dqlp_mmr_ybist_l_u { - mmr_t sh_md_dqlp_mmr_ybist_l_regval; - struct { - mmr_t reserved_1 : 22; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqlp_mmr_ybist_l_s; -} sh_md_dqlp_mmr_ybist_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_YBIST_ERR_H" */ /* rising edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_ybist_err_h_u { mmr_t sh_md_dqlp_mmr_ybist_err_h_regval; struct { @@ -25454,25 +13763,12 @@ typedef union sh_md_dqlp_mmr_ybist_err_h_u { mmr_t reserved_1 : 22; } sh_md_dqlp_mmr_ybist_err_h_s; } sh_md_dqlp_mmr_ybist_err_h_u_t; -#else -typedef union sh_md_dqlp_mmr_ybist_err_h_u { - mmr_t sh_md_dqlp_mmr_ybist_err_h_regval; - struct { - mmr_t reserved_1 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqlp_mmr_ybist_err_h_s; -} sh_md_dqlp_mmr_ybist_err_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_YBIST_ERR_L" */ /* falling edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_ybist_err_l_u { mmr_t sh_md_dqlp_mmr_ybist_err_l_regval; struct { @@ -25483,25 +13779,12 @@ typedef union sh_md_dqlp_mmr_ybist_err_l_u { mmr_t reserved_1 : 22; } sh_md_dqlp_mmr_ybist_err_l_s; } sh_md_dqlp_mmr_ybist_err_l_u_t; -#else -typedef union sh_md_dqlp_mmr_ybist_err_l_u { - mmr_t sh_md_dqlp_mmr_ybist_err_l_regval; - struct { - mmr_t reserved_1 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqlp_mmr_ybist_err_l_s; -} sh_md_dqlp_mmr_ybist_err_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLS_MMR_XBIST_H" */ /* rising edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqls_mmr_xbist_h_u { mmr_t sh_md_dqls_mmr_xbist_h_regval; struct { @@ -25512,25 +13795,12 @@ typedef union sh_md_dqls_mmr_xbist_h_u { mmr_t reserved_0 : 21; } sh_md_dqls_mmr_xbist_h_s; } sh_md_dqls_mmr_xbist_h_u_t; -#else -typedef union sh_md_dqls_mmr_xbist_h_u { - mmr_t sh_md_dqls_mmr_xbist_h_regval; - struct { - mmr_t reserved_0 : 21; - mmr_t arm : 1; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t pat : 40; - } sh_md_dqls_mmr_xbist_h_s; -} sh_md_dqls_mmr_xbist_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLS_MMR_XBIST_L" */ /* falling edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqls_mmr_xbist_l_u { mmr_t sh_md_dqls_mmr_xbist_l_regval; struct { @@ -25540,24 +13810,12 @@ typedef union sh_md_dqls_mmr_xbist_l_u { mmr_t reserved_0 : 22; } sh_md_dqls_mmr_xbist_l_s; } sh_md_dqls_mmr_xbist_l_u_t; -#else -typedef union sh_md_dqls_mmr_xbist_l_u { - mmr_t sh_md_dqls_mmr_xbist_l_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t pat : 40; - } sh_md_dqls_mmr_xbist_l_s; -} sh_md_dqls_mmr_xbist_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLS_MMR_XBIST_ERR_H" */ /* rising edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqls_mmr_xbist_err_h_u { mmr_t sh_md_dqls_mmr_xbist_err_h_regval; struct { @@ -25567,24 +13825,12 @@ typedef union sh_md_dqls_mmr_xbist_err_h_u { mmr_t reserved_0 : 22; } sh_md_dqls_mmr_xbist_err_h_s; } sh_md_dqls_mmr_xbist_err_h_u_t; -#else -typedef union sh_md_dqls_mmr_xbist_err_h_u { - mmr_t sh_md_dqls_mmr_xbist_err_h_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t pat : 40; - } sh_md_dqls_mmr_xbist_err_h_s; -} sh_md_dqls_mmr_xbist_err_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLS_MMR_XBIST_ERR_L" */ /* falling edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqls_mmr_xbist_err_l_u { mmr_t sh_md_dqls_mmr_xbist_err_l_regval; struct { @@ -25594,24 +13840,12 @@ typedef union sh_md_dqls_mmr_xbist_err_l_u { mmr_t reserved_0 : 22; } sh_md_dqls_mmr_xbist_err_l_s; } sh_md_dqls_mmr_xbist_err_l_u_t; -#else -typedef union sh_md_dqls_mmr_xbist_err_l_u { - mmr_t sh_md_dqls_mmr_xbist_err_l_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t pat : 40; - } sh_md_dqls_mmr_xbist_err_l_s; -} sh_md_dqls_mmr_xbist_err_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLS_MMR_YBIST_H" */ /* rising edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqls_mmr_ybist_h_u { mmr_t sh_md_dqls_mmr_ybist_h_regval; struct { @@ -25622,25 +13856,12 @@ typedef union sh_md_dqls_mmr_ybist_h_u { mmr_t reserved_0 : 21; } sh_md_dqls_mmr_ybist_h_s; } sh_md_dqls_mmr_ybist_h_u_t; -#else -typedef union sh_md_dqls_mmr_ybist_h_u { - mmr_t sh_md_dqls_mmr_ybist_h_regval; - struct { - mmr_t reserved_0 : 21; - mmr_t arm : 1; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t pat : 40; - } sh_md_dqls_mmr_ybist_h_s; -} sh_md_dqls_mmr_ybist_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLS_MMR_YBIST_L" */ /* falling edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqls_mmr_ybist_l_u { mmr_t sh_md_dqls_mmr_ybist_l_regval; struct { @@ -25650,24 +13871,12 @@ typedef union sh_md_dqls_mmr_ybist_l_u { mmr_t reserved_0 : 22; } sh_md_dqls_mmr_ybist_l_s; } sh_md_dqls_mmr_ybist_l_u_t; -#else -typedef union sh_md_dqls_mmr_ybist_l_u { - mmr_t sh_md_dqls_mmr_ybist_l_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t pat : 40; - } sh_md_dqls_mmr_ybist_l_s; -} sh_md_dqls_mmr_ybist_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLS_MMR_YBIST_ERR_H" */ /* rising edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqls_mmr_ybist_err_h_u { mmr_t sh_md_dqls_mmr_ybist_err_h_regval; struct { @@ -25677,24 +13886,12 @@ typedef union sh_md_dqls_mmr_ybist_err_h_u { mmr_t reserved_0 : 22; } sh_md_dqls_mmr_ybist_err_h_s; } sh_md_dqls_mmr_ybist_err_h_u_t; -#else -typedef union sh_md_dqls_mmr_ybist_err_h_u { - mmr_t sh_md_dqls_mmr_ybist_err_h_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t pat : 40; - } sh_md_dqls_mmr_ybist_err_h_s; -} sh_md_dqls_mmr_ybist_err_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLS_MMR_YBIST_ERR_L" */ /* falling edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqls_mmr_ybist_err_l_u { mmr_t sh_md_dqls_mmr_ybist_err_l_regval; struct { @@ -25704,24 +13901,12 @@ typedef union sh_md_dqls_mmr_ybist_err_l_u { mmr_t reserved_0 : 22; } sh_md_dqls_mmr_ybist_err_l_s; } sh_md_dqls_mmr_ybist_err_l_u_t; -#else -typedef union sh_md_dqls_mmr_ybist_err_l_u { - mmr_t sh_md_dqls_mmr_ybist_err_l_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t pat : 40; - } sh_md_dqls_mmr_ybist_err_l_s; -} sh_md_dqls_mmr_ybist_err_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLS_MMR_JNR_DEBUG" */ /* joiner/fct debug configuration */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqls_mmr_jnr_debug_u { mmr_t sh_md_dqls_mmr_jnr_debug_regval; struct { @@ -25730,23 +13915,12 @@ typedef union sh_md_dqls_mmr_jnr_debug_u { mmr_t reserved_0 : 62; } sh_md_dqls_mmr_jnr_debug_s; } sh_md_dqls_mmr_jnr_debug_u_t; -#else -typedef union sh_md_dqls_mmr_jnr_debug_u { - mmr_t sh_md_dqls_mmr_jnr_debug_regval; - struct { - mmr_t reserved_0 : 62; - mmr_t rw : 1; - mmr_t px : 1; - } sh_md_dqls_mmr_jnr_debug_s; -} sh_md_dqls_mmr_jnr_debug_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLS_MMR_XAMOPW_ERR" */ /* amo/partial rmw ecc error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqls_mmr_xamopw_err_u { mmr_t sh_md_dqls_mmr_xamopw_err_regval; struct { @@ -25762,30 +13936,12 @@ typedef union sh_md_dqls_mmr_xamopw_err_u { mmr_t reserved_2 : 31; } sh_md_dqls_mmr_xamopw_err_s; } sh_md_dqls_mmr_xamopw_err_u_t; -#else -typedef union sh_md_dqls_mmr_xamopw_err_u { - mmr_t sh_md_dqls_mmr_xamopw_err_regval; - struct { - mmr_t reserved_2 : 31; - mmr_t arm : 1; - mmr_t reserved_1 : 6; - mmr_t runc : 1; - mmr_t rcor : 1; - mmr_t rsyn : 8; - mmr_t reserved_0 : 6; - mmr_t sunc : 1; - mmr_t scor : 1; - mmr_t ssyn : 8; - } sh_md_dqls_mmr_xamopw_err_s; -} sh_md_dqls_mmr_xamopw_err_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_CONFIG" */ /* DQ directory config register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_config_u { mmr_t sh_md_dqrp_mmr_dir_config_regval; struct { @@ -25795,276 +13951,156 @@ typedef union sh_md_dqrp_mmr_dir_config_u { mmr_t reserved_0 : 59; } sh_md_dqrp_mmr_dir_config_s; } sh_md_dqrp_mmr_dir_config_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_config_u { - mmr_t sh_md_dqrp_mmr_dir_config_regval; - struct { - mmr_t reserved_0 : 59; - mmr_t en_dirpois : 1; - mmr_t en_direcc : 1; - mmr_t sys_size : 3; - } sh_md_dqrp_mmr_dir_config_s; -} sh_md_dqrp_mmr_dir_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_PRESVEC0" */ /* node [63:0] presence bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqrp_mmr_dir_presvec0_u { - mmr_t sh_md_dqrp_mmr_dir_presvec0_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_presvec0_s; -} sh_md_dqrp_mmr_dir_presvec0_u_t; -#else typedef union sh_md_dqrp_mmr_dir_presvec0_u { mmr_t sh_md_dqrp_mmr_dir_presvec0_regval; struct { mmr_t vec : 64; } sh_md_dqrp_mmr_dir_presvec0_s; } sh_md_dqrp_mmr_dir_presvec0_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_PRESVEC1" */ /* node [127:64] presence bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_presvec1_u { mmr_t sh_md_dqrp_mmr_dir_presvec1_regval; struct { mmr_t vec : 64; } sh_md_dqrp_mmr_dir_presvec1_s; } sh_md_dqrp_mmr_dir_presvec1_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_presvec1_u { - mmr_t sh_md_dqrp_mmr_dir_presvec1_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_presvec1_s; -} sh_md_dqrp_mmr_dir_presvec1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_PRESVEC2" */ /* node [191:128] presence bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqrp_mmr_dir_presvec2_u { - mmr_t sh_md_dqrp_mmr_dir_presvec2_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_presvec2_s; -} sh_md_dqrp_mmr_dir_presvec2_u_t; -#else typedef union sh_md_dqrp_mmr_dir_presvec2_u { mmr_t sh_md_dqrp_mmr_dir_presvec2_regval; struct { mmr_t vec : 64; } sh_md_dqrp_mmr_dir_presvec2_s; } sh_md_dqrp_mmr_dir_presvec2_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_PRESVEC3" */ /* node [255:192] presence bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqrp_mmr_dir_presvec3_u { - mmr_t sh_md_dqrp_mmr_dir_presvec3_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_presvec3_s; -} sh_md_dqrp_mmr_dir_presvec3_u_t; -#else typedef union sh_md_dqrp_mmr_dir_presvec3_u { mmr_t sh_md_dqrp_mmr_dir_presvec3_regval; struct { mmr_t vec : 64; } sh_md_dqrp_mmr_dir_presvec3_s; } sh_md_dqrp_mmr_dir_presvec3_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC0" */ /* local vector for acc=0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqrp_mmr_dir_locvec0_u { - mmr_t sh_md_dqrp_mmr_dir_locvec0_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_locvec0_s; -} sh_md_dqrp_mmr_dir_locvec0_u_t; -#else typedef union sh_md_dqrp_mmr_dir_locvec0_u { mmr_t sh_md_dqrp_mmr_dir_locvec0_regval; struct { mmr_t vec : 64; } sh_md_dqrp_mmr_dir_locvec0_s; } sh_md_dqrp_mmr_dir_locvec0_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC1" */ /* local vector for acc=1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_locvec1_u { mmr_t sh_md_dqrp_mmr_dir_locvec1_regval; struct { mmr_t vec : 64; } sh_md_dqrp_mmr_dir_locvec1_s; } sh_md_dqrp_mmr_dir_locvec1_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_locvec1_u { - mmr_t sh_md_dqrp_mmr_dir_locvec1_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_locvec1_s; -} sh_md_dqrp_mmr_dir_locvec1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC2" */ /* local vector for acc=2 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_locvec2_u { mmr_t sh_md_dqrp_mmr_dir_locvec2_regval; struct { mmr_t vec : 64; } sh_md_dqrp_mmr_dir_locvec2_s; } sh_md_dqrp_mmr_dir_locvec2_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_locvec2_u { - mmr_t sh_md_dqrp_mmr_dir_locvec2_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_locvec2_s; -} sh_md_dqrp_mmr_dir_locvec2_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC3" */ /* local vector for acc=3 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_locvec3_u { mmr_t sh_md_dqrp_mmr_dir_locvec3_regval; struct { mmr_t vec : 64; } sh_md_dqrp_mmr_dir_locvec3_s; } sh_md_dqrp_mmr_dir_locvec3_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_locvec3_u { - mmr_t sh_md_dqrp_mmr_dir_locvec3_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_locvec3_s; -} sh_md_dqrp_mmr_dir_locvec3_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC4" */ /* local vector for acc=4 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqrp_mmr_dir_locvec4_u { - mmr_t sh_md_dqrp_mmr_dir_locvec4_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_locvec4_s; -} sh_md_dqrp_mmr_dir_locvec4_u_t; -#else typedef union sh_md_dqrp_mmr_dir_locvec4_u { mmr_t sh_md_dqrp_mmr_dir_locvec4_regval; struct { mmr_t vec : 64; } sh_md_dqrp_mmr_dir_locvec4_s; } sh_md_dqrp_mmr_dir_locvec4_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC5" */ /* local vector for acc=5 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqrp_mmr_dir_locvec5_u { - mmr_t sh_md_dqrp_mmr_dir_locvec5_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_locvec5_s; -} sh_md_dqrp_mmr_dir_locvec5_u_t; -#else typedef union sh_md_dqrp_mmr_dir_locvec5_u { mmr_t sh_md_dqrp_mmr_dir_locvec5_regval; struct { mmr_t vec : 64; } sh_md_dqrp_mmr_dir_locvec5_s; } sh_md_dqrp_mmr_dir_locvec5_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC6" */ /* local vector for acc=6 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_locvec6_u { mmr_t sh_md_dqrp_mmr_dir_locvec6_regval; struct { mmr_t vec : 64; } sh_md_dqrp_mmr_dir_locvec6_s; } sh_md_dqrp_mmr_dir_locvec6_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_locvec6_u { - mmr_t sh_md_dqrp_mmr_dir_locvec6_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_locvec6_s; -} sh_md_dqrp_mmr_dir_locvec6_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC7" */ /* local vector for acc=7 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqrp_mmr_dir_locvec7_u { - mmr_t sh_md_dqrp_mmr_dir_locvec7_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_locvec7_s; -} sh_md_dqrp_mmr_dir_locvec7_u_t; -#else typedef union sh_md_dqrp_mmr_dir_locvec7_u { mmr_t sh_md_dqrp_mmr_dir_locvec7_regval; struct { mmr_t vec : 64; } sh_md_dqrp_mmr_dir_locvec7_s; } sh_md_dqrp_mmr_dir_locvec7_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC0" */ /* privilege vector for acc=0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_privec0_u { mmr_t sh_md_dqrp_mmr_dir_privec0_regval; struct { @@ -26073,23 +14109,12 @@ typedef union sh_md_dqrp_mmr_dir_privec0_u { mmr_t reserved_0 : 36; } sh_md_dqrp_mmr_dir_privec0_s; } sh_md_dqrp_mmr_dir_privec0_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_privec0_u { - mmr_t sh_md_dqrp_mmr_dir_privec0_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqrp_mmr_dir_privec0_s; -} sh_md_dqrp_mmr_dir_privec0_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC1" */ /* privilege vector for acc=1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_privec1_u { mmr_t sh_md_dqrp_mmr_dir_privec1_regval; struct { @@ -26098,23 +14123,12 @@ typedef union sh_md_dqrp_mmr_dir_privec1_u { mmr_t reserved_0 : 36; } sh_md_dqrp_mmr_dir_privec1_s; } sh_md_dqrp_mmr_dir_privec1_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_privec1_u { - mmr_t sh_md_dqrp_mmr_dir_privec1_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqrp_mmr_dir_privec1_s; -} sh_md_dqrp_mmr_dir_privec1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC2" */ /* privilege vector for acc=2 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_privec2_u { mmr_t sh_md_dqrp_mmr_dir_privec2_regval; struct { @@ -26123,23 +14137,12 @@ typedef union sh_md_dqrp_mmr_dir_privec2_u { mmr_t reserved_0 : 36; } sh_md_dqrp_mmr_dir_privec2_s; } sh_md_dqrp_mmr_dir_privec2_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_privec2_u { - mmr_t sh_md_dqrp_mmr_dir_privec2_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqrp_mmr_dir_privec2_s; -} sh_md_dqrp_mmr_dir_privec2_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC3" */ /* privilege vector for acc=3 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_privec3_u { mmr_t sh_md_dqrp_mmr_dir_privec3_regval; struct { @@ -26148,23 +14151,12 @@ typedef union sh_md_dqrp_mmr_dir_privec3_u { mmr_t reserved_0 : 36; } sh_md_dqrp_mmr_dir_privec3_s; } sh_md_dqrp_mmr_dir_privec3_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_privec3_u { - mmr_t sh_md_dqrp_mmr_dir_privec3_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqrp_mmr_dir_privec3_s; -} sh_md_dqrp_mmr_dir_privec3_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC4" */ /* privilege vector for acc=4 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_privec4_u { mmr_t sh_md_dqrp_mmr_dir_privec4_regval; struct { @@ -26173,23 +14165,12 @@ typedef union sh_md_dqrp_mmr_dir_privec4_u { mmr_t reserved_0 : 36; } sh_md_dqrp_mmr_dir_privec4_s; } sh_md_dqrp_mmr_dir_privec4_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_privec4_u { - mmr_t sh_md_dqrp_mmr_dir_privec4_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqrp_mmr_dir_privec4_s; -} sh_md_dqrp_mmr_dir_privec4_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC5" */ /* privilege vector for acc=5 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_privec5_u { mmr_t sh_md_dqrp_mmr_dir_privec5_regval; struct { @@ -26198,23 +14179,12 @@ typedef union sh_md_dqrp_mmr_dir_privec5_u { mmr_t reserved_0 : 36; } sh_md_dqrp_mmr_dir_privec5_s; } sh_md_dqrp_mmr_dir_privec5_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_privec5_u { - mmr_t sh_md_dqrp_mmr_dir_privec5_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqrp_mmr_dir_privec5_s; -} sh_md_dqrp_mmr_dir_privec5_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC6" */ /* privilege vector for acc=6 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_privec6_u { mmr_t sh_md_dqrp_mmr_dir_privec6_regval; struct { @@ -26223,23 +14193,12 @@ typedef union sh_md_dqrp_mmr_dir_privec6_u { mmr_t reserved_0 : 36; } sh_md_dqrp_mmr_dir_privec6_s; } sh_md_dqrp_mmr_dir_privec6_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_privec6_u { - mmr_t sh_md_dqrp_mmr_dir_privec6_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqrp_mmr_dir_privec6_s; -} sh_md_dqrp_mmr_dir_privec6_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC7" */ /* privilege vector for acc=7 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_privec7_u { mmr_t sh_md_dqrp_mmr_dir_privec7_regval; struct { @@ -26248,23 +14207,12 @@ typedef union sh_md_dqrp_mmr_dir_privec7_u { mmr_t reserved_0 : 36; } sh_md_dqrp_mmr_dir_privec7_s; } sh_md_dqrp_mmr_dir_privec7_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_privec7_u { - mmr_t sh_md_dqrp_mmr_dir_privec7_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqrp_mmr_dir_privec7_s; -} sh_md_dqrp_mmr_dir_privec7_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_TIMER" */ /* MD SXRO timer */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_timer_u { mmr_t sh_md_dqrp_mmr_dir_timer_regval; struct { @@ -26274,24 +14222,12 @@ typedef union sh_md_dqrp_mmr_dir_timer_u { mmr_t reserved_0 : 42; } sh_md_dqrp_mmr_dir_timer_s; } sh_md_dqrp_mmr_dir_timer_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_timer_u { - mmr_t sh_md_dqrp_mmr_dir_timer_regval; - struct { - mmr_t reserved_0 : 42; - mmr_t timer_cur : 9; - mmr_t timer_en : 1; - mmr_t timer_div : 12; - } sh_md_dqrp_mmr_dir_timer_s; -} sh_md_dqrp_mmr_dir_timer_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY" */ /* directory pio write data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_piowd_dir_entry_u { mmr_t sh_md_dqrp_mmr_piowd_dir_entry_regval; struct { @@ -26302,25 +14238,12 @@ typedef union sh_md_dqrp_mmr_piowd_dir_entry_u { mmr_t reserved_0 : 6; } sh_md_dqrp_mmr_piowd_dir_entry_s; } sh_md_dqrp_mmr_piowd_dir_entry_u_t; -#else -typedef union sh_md_dqrp_mmr_piowd_dir_entry_u { - mmr_t sh_md_dqrp_mmr_piowd_dir_entry_regval; - struct { - mmr_t reserved_0 : 6; - mmr_t acc : 3; - mmr_t pri : 3; - mmr_t dirb : 26; - mmr_t dira : 26; - } sh_md_dqrp_mmr_piowd_dir_entry_s; -} sh_md_dqrp_mmr_piowd_dir_entry_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_PIOWD_DIR_ECC" */ /* directory ecc register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_piowd_dir_ecc_u { mmr_t sh_md_dqrp_mmr_piowd_dir_ecc_regval; struct { @@ -26329,23 +14252,12 @@ typedef union sh_md_dqrp_mmr_piowd_dir_ecc_u { mmr_t reserved_0 : 50; } sh_md_dqrp_mmr_piowd_dir_ecc_s; } sh_md_dqrp_mmr_piowd_dir_ecc_u_t; -#else -typedef union sh_md_dqrp_mmr_piowd_dir_ecc_u { - mmr_t sh_md_dqrp_mmr_piowd_dir_ecc_regval; - struct { - mmr_t reserved_0 : 50; - mmr_t eccb : 7; - mmr_t ecca : 7; - } sh_md_dqrp_mmr_piowd_dir_ecc_s; -} sh_md_dqrp_mmr_piowd_dir_ecc_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY" */ /* x directory pio read data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_xpiord_xdir_entry_u { mmr_t sh_md_dqrp_mmr_xpiord_xdir_entry_regval; struct { @@ -26358,27 +14270,12 @@ typedef union sh_md_dqrp_mmr_xpiord_xdir_entry_u { mmr_t reserved_0 : 4; } sh_md_dqrp_mmr_xpiord_xdir_entry_s; } sh_md_dqrp_mmr_xpiord_xdir_entry_u_t; -#else -typedef union sh_md_dqrp_mmr_xpiord_xdir_entry_u { - mmr_t sh_md_dqrp_mmr_xpiord_xdir_entry_regval; - struct { - mmr_t reserved_0 : 4; - mmr_t unc : 1; - mmr_t cor : 1; - mmr_t acc : 3; - mmr_t pri : 3; - mmr_t dirb : 26; - mmr_t dira : 26; - } sh_md_dqrp_mmr_xpiord_xdir_entry_s; -} sh_md_dqrp_mmr_xpiord_xdir_entry_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_XPIORD_XDIR_ECC" */ /* x directory ecc */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_xpiord_xdir_ecc_u { mmr_t sh_md_dqrp_mmr_xpiord_xdir_ecc_regval; struct { @@ -26387,23 +14284,12 @@ typedef union sh_md_dqrp_mmr_xpiord_xdir_ecc_u { mmr_t reserved_0 : 50; } sh_md_dqrp_mmr_xpiord_xdir_ecc_s; } sh_md_dqrp_mmr_xpiord_xdir_ecc_u_t; -#else -typedef union sh_md_dqrp_mmr_xpiord_xdir_ecc_u { - mmr_t sh_md_dqrp_mmr_xpiord_xdir_ecc_regval; - struct { - mmr_t reserved_0 : 50; - mmr_t eccb : 7; - mmr_t ecca : 7; - } sh_md_dqrp_mmr_xpiord_xdir_ecc_s; -} sh_md_dqrp_mmr_xpiord_xdir_ecc_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY" */ /* y directory pio read data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_ypiord_ydir_entry_u { mmr_t sh_md_dqrp_mmr_ypiord_ydir_entry_regval; struct { @@ -26416,27 +14302,12 @@ typedef union sh_md_dqrp_mmr_ypiord_ydir_entry_u { mmr_t reserved_0 : 4; } sh_md_dqrp_mmr_ypiord_ydir_entry_s; } sh_md_dqrp_mmr_ypiord_ydir_entry_u_t; -#else -typedef union sh_md_dqrp_mmr_ypiord_ydir_entry_u { - mmr_t sh_md_dqrp_mmr_ypiord_ydir_entry_regval; - struct { - mmr_t reserved_0 : 4; - mmr_t unc : 1; - mmr_t cor : 1; - mmr_t acc : 3; - mmr_t pri : 3; - mmr_t dirb : 26; - mmr_t dira : 26; - } sh_md_dqrp_mmr_ypiord_ydir_entry_s; -} sh_md_dqrp_mmr_ypiord_ydir_entry_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_YPIORD_YDIR_ECC" */ /* y directory ecc */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_ypiord_ydir_ecc_u { mmr_t sh_md_dqrp_mmr_ypiord_ydir_ecc_regval; struct { @@ -26445,23 +14316,12 @@ typedef union sh_md_dqrp_mmr_ypiord_ydir_ecc_u { mmr_t reserved_0 : 50; } sh_md_dqrp_mmr_ypiord_ydir_ecc_s; } sh_md_dqrp_mmr_ypiord_ydir_ecc_u_t; -#else -typedef union sh_md_dqrp_mmr_ypiord_ydir_ecc_u { - mmr_t sh_md_dqrp_mmr_ypiord_ydir_ecc_regval; - struct { - mmr_t reserved_0 : 50; - mmr_t eccb : 7; - mmr_t ecca : 7; - } sh_md_dqrp_mmr_ypiord_ydir_ecc_s; -} sh_md_dqrp_mmr_ypiord_ydir_ecc_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_XCERR1" */ /* correctable dir ecc group 1 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_xcerr1_u { mmr_t sh_md_dqrp_mmr_xcerr1_regval; struct { @@ -26472,25 +14332,12 @@ typedef union sh_md_dqrp_mmr_xcerr1_u { mmr_t reserved_0 : 25; } sh_md_dqrp_mmr_xcerr1_s; } sh_md_dqrp_mmr_xcerr1_u_t; -#else -typedef union sh_md_dqrp_mmr_xcerr1_u { - mmr_t sh_md_dqrp_mmr_xcerr1_regval; - struct { - mmr_t reserved_0 : 25; - mmr_t arm : 1; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp1 : 36; - } sh_md_dqrp_mmr_xcerr1_s; -} sh_md_dqrp_mmr_xcerr1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_XCERR2" */ /* correctable dir ecc group 2 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_xcerr2_u { mmr_t sh_md_dqrp_mmr_xcerr2_regval; struct { @@ -26500,24 +14347,12 @@ typedef union sh_md_dqrp_mmr_xcerr2_u { mmr_t reserved_0 : 26; } sh_md_dqrp_mmr_xcerr2_s; } sh_md_dqrp_mmr_xcerr2_u_t; -#else -typedef union sh_md_dqrp_mmr_xcerr2_u { - mmr_t sh_md_dqrp_mmr_xcerr2_regval; - struct { - mmr_t reserved_0 : 26; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp2 : 36; - } sh_md_dqrp_mmr_xcerr2_s; -} sh_md_dqrp_mmr_xcerr2_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_XUERR1" */ /* uncorrectable dir ecc group 1 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_xuerr1_u { mmr_t sh_md_dqrp_mmr_xuerr1_regval; struct { @@ -26528,25 +14363,12 @@ typedef union sh_md_dqrp_mmr_xuerr1_u { mmr_t reserved_0 : 25; } sh_md_dqrp_mmr_xuerr1_s; } sh_md_dqrp_mmr_xuerr1_u_t; -#else -typedef union sh_md_dqrp_mmr_xuerr1_u { - mmr_t sh_md_dqrp_mmr_xuerr1_regval; - struct { - mmr_t reserved_0 : 25; - mmr_t arm : 1; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp1 : 36; - } sh_md_dqrp_mmr_xuerr1_s; -} sh_md_dqrp_mmr_xuerr1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_XUERR2" */ /* uncorrectable dir ecc group 2 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_xuerr2_u { mmr_t sh_md_dqrp_mmr_xuerr2_regval; struct { @@ -26556,24 +14378,12 @@ typedef union sh_md_dqrp_mmr_xuerr2_u { mmr_t reserved_0 : 26; } sh_md_dqrp_mmr_xuerr2_s; } sh_md_dqrp_mmr_xuerr2_u_t; -#else -typedef union sh_md_dqrp_mmr_xuerr2_u { - mmr_t sh_md_dqrp_mmr_xuerr2_regval; - struct { - mmr_t reserved_0 : 26; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp2 : 36; - } sh_md_dqrp_mmr_xuerr2_s; -} sh_md_dqrp_mmr_xuerr2_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_XPERR" */ /* protocol error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_xperr_u { mmr_t sh_md_dqrp_mmr_xperr_regval; struct { @@ -26591,32 +14401,12 @@ typedef union sh_md_dqrp_mmr_xperr_u { mmr_t reserved_0 : 1; } sh_md_dqrp_mmr_xperr_s; } sh_md_dqrp_mmr_xperr_u_t; -#else -typedef union sh_md_dqrp_mmr_xperr_u { - mmr_t sh_md_dqrp_mmr_xperr_regval; - struct { - mmr_t reserved_0 : 1; - mmr_t arm : 1; - mmr_t more : 1; - mmr_t val : 1; - mmr_t mybit : 8; - mmr_t unc : 1; - mmr_t cor : 1; - mmr_t priv : 1; - mmr_t prige : 1; - mmr_t src : 14; - mmr_t cmd : 8; - mmr_t dir : 26; - } sh_md_dqrp_mmr_xperr_s; -} sh_md_dqrp_mmr_xperr_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_YCERR1" */ /* correctable dir ecc group 1 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_ycerr1_u { mmr_t sh_md_dqrp_mmr_ycerr1_regval; struct { @@ -26627,25 +14417,12 @@ typedef union sh_md_dqrp_mmr_ycerr1_u { mmr_t reserved_0 : 25; } sh_md_dqrp_mmr_ycerr1_s; } sh_md_dqrp_mmr_ycerr1_u_t; -#else -typedef union sh_md_dqrp_mmr_ycerr1_u { - mmr_t sh_md_dqrp_mmr_ycerr1_regval; - struct { - mmr_t reserved_0 : 25; - mmr_t arm : 1; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp1 : 36; - } sh_md_dqrp_mmr_ycerr1_s; -} sh_md_dqrp_mmr_ycerr1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_YCERR2" */ /* correctable dir ecc group 2 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_ycerr2_u { mmr_t sh_md_dqrp_mmr_ycerr2_regval; struct { @@ -26655,24 +14432,12 @@ typedef union sh_md_dqrp_mmr_ycerr2_u { mmr_t reserved_0 : 26; } sh_md_dqrp_mmr_ycerr2_s; } sh_md_dqrp_mmr_ycerr2_u_t; -#else -typedef union sh_md_dqrp_mmr_ycerr2_u { - mmr_t sh_md_dqrp_mmr_ycerr2_regval; - struct { - mmr_t reserved_0 : 26; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp2 : 36; - } sh_md_dqrp_mmr_ycerr2_s; -} sh_md_dqrp_mmr_ycerr2_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_YUERR1" */ /* uncorrectable dir ecc group 1 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_yuerr1_u { mmr_t sh_md_dqrp_mmr_yuerr1_regval; struct { @@ -26683,25 +14448,12 @@ typedef union sh_md_dqrp_mmr_yuerr1_u { mmr_t reserved_0 : 25; } sh_md_dqrp_mmr_yuerr1_s; } sh_md_dqrp_mmr_yuerr1_u_t; -#else -typedef union sh_md_dqrp_mmr_yuerr1_u { - mmr_t sh_md_dqrp_mmr_yuerr1_regval; - struct { - mmr_t reserved_0 : 25; - mmr_t arm : 1; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp1 : 36; - } sh_md_dqrp_mmr_yuerr1_s; -} sh_md_dqrp_mmr_yuerr1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_YUERR2" */ /* uncorrectable dir ecc group 2 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_yuerr2_u { mmr_t sh_md_dqrp_mmr_yuerr2_regval; struct { @@ -26711,24 +14463,12 @@ typedef union sh_md_dqrp_mmr_yuerr2_u { mmr_t reserved_0 : 26; } sh_md_dqrp_mmr_yuerr2_s; } sh_md_dqrp_mmr_yuerr2_u_t; -#else -typedef union sh_md_dqrp_mmr_yuerr2_u { - mmr_t sh_md_dqrp_mmr_yuerr2_regval; - struct { - mmr_t reserved_0 : 26; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp2 : 36; - } sh_md_dqrp_mmr_yuerr2_s; -} sh_md_dqrp_mmr_yuerr2_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_YPERR" */ /* protocol error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_yperr_u { mmr_t sh_md_dqrp_mmr_yperr_regval; struct { @@ -26746,32 +14486,12 @@ typedef union sh_md_dqrp_mmr_yperr_u { mmr_t reserved_0 : 1; } sh_md_dqrp_mmr_yperr_s; } sh_md_dqrp_mmr_yperr_u_t; -#else -typedef union sh_md_dqrp_mmr_yperr_u { - mmr_t sh_md_dqrp_mmr_yperr_regval; - struct { - mmr_t reserved_0 : 1; - mmr_t arm : 1; - mmr_t more : 1; - mmr_t val : 1; - mmr_t mybit : 8; - mmr_t unc : 1; - mmr_t cor : 1; - mmr_t priv : 1; - mmr_t prige : 1; - mmr_t src : 14; - mmr_t cmd : 8; - mmr_t dir : 26; - } sh_md_dqrp_mmr_yperr_s; -} sh_md_dqrp_mmr_yperr_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_CMDTRIG" */ /* cmd triggers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_cmdtrig_u { mmr_t sh_md_dqrp_mmr_dir_cmdtrig_regval; struct { @@ -26782,25 +14502,12 @@ typedef union sh_md_dqrp_mmr_dir_cmdtrig_u { mmr_t reserved_0 : 32; } sh_md_dqrp_mmr_dir_cmdtrig_s; } sh_md_dqrp_mmr_dir_cmdtrig_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_cmdtrig_u { - mmr_t sh_md_dqrp_mmr_dir_cmdtrig_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t cmd3 : 8; - mmr_t cmd2 : 8; - mmr_t cmd1 : 8; - mmr_t cmd0 : 8; - } sh_md_dqrp_mmr_dir_cmdtrig_s; -} sh_md_dqrp_mmr_dir_cmdtrig_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_TBLTRIG" */ /* dir table trigger */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_tbltrig_u { mmr_t sh_md_dqrp_mmr_dir_tbltrig_regval; struct { @@ -26813,27 +14520,12 @@ typedef union sh_md_dqrp_mmr_dir_tbltrig_u { mmr_t reserved_0 : 22; } sh_md_dqrp_mmr_dir_tbltrig_s; } sh_md_dqrp_mmr_dir_tbltrig_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_tbltrig_u { - mmr_t sh_md_dqrp_mmr_dir_tbltrig_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t mybit : 8; - mmr_t dirst : 9; - mmr_t prige : 1; - mmr_t acc : 2; - mmr_t cmd : 8; - mmr_t src : 14; - } sh_md_dqrp_mmr_dir_tbltrig_s; -} sh_md_dqrp_mmr_dir_tbltrig_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_TBLMASK" */ /* dir table trigger mask */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_tblmask_u { mmr_t sh_md_dqrp_mmr_dir_tblmask_regval; struct { @@ -26846,27 +14538,12 @@ typedef union sh_md_dqrp_mmr_dir_tblmask_u { mmr_t reserved_0 : 22; } sh_md_dqrp_mmr_dir_tblmask_s; } sh_md_dqrp_mmr_dir_tblmask_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_tblmask_u { - mmr_t sh_md_dqrp_mmr_dir_tblmask_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t mybit : 8; - mmr_t dirst : 9; - mmr_t prige : 1; - mmr_t acc : 2; - mmr_t cmd : 8; - mmr_t src : 14; - } sh_md_dqrp_mmr_dir_tblmask_s; -} sh_md_dqrp_mmr_dir_tblmask_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_XBIST_H" */ /* rising edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_xbist_h_u { mmr_t sh_md_dqrp_mmr_xbist_h_regval; struct { @@ -26878,26 +14555,12 @@ typedef union sh_md_dqrp_mmr_xbist_h_u { mmr_t reserved_1 : 21; } sh_md_dqrp_mmr_xbist_h_s; } sh_md_dqrp_mmr_xbist_h_u_t; -#else -typedef union sh_md_dqrp_mmr_xbist_h_u { - mmr_t sh_md_dqrp_mmr_xbist_h_regval; - struct { - mmr_t reserved_1 : 21; - mmr_t arm : 1; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqrp_mmr_xbist_h_s; -} sh_md_dqrp_mmr_xbist_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_XBIST_L" */ /* falling edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_xbist_l_u { mmr_t sh_md_dqrp_mmr_xbist_l_regval; struct { @@ -26908,25 +14571,12 @@ typedef union sh_md_dqrp_mmr_xbist_l_u { mmr_t reserved_1 : 22; } sh_md_dqrp_mmr_xbist_l_s; } sh_md_dqrp_mmr_xbist_l_u_t; -#else -typedef union sh_md_dqrp_mmr_xbist_l_u { - mmr_t sh_md_dqrp_mmr_xbist_l_regval; - struct { - mmr_t reserved_1 : 22; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqrp_mmr_xbist_l_s; -} sh_md_dqrp_mmr_xbist_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_XBIST_ERR_H" */ /* rising edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_xbist_err_h_u { mmr_t sh_md_dqrp_mmr_xbist_err_h_regval; struct { @@ -26937,25 +14587,12 @@ typedef union sh_md_dqrp_mmr_xbist_err_h_u { mmr_t reserved_1 : 22; } sh_md_dqrp_mmr_xbist_err_h_s; } sh_md_dqrp_mmr_xbist_err_h_u_t; -#else -typedef union sh_md_dqrp_mmr_xbist_err_h_u { - mmr_t sh_md_dqrp_mmr_xbist_err_h_regval; - struct { - mmr_t reserved_1 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqrp_mmr_xbist_err_h_s; -} sh_md_dqrp_mmr_xbist_err_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_XBIST_ERR_L" */ /* falling edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_xbist_err_l_u { mmr_t sh_md_dqrp_mmr_xbist_err_l_regval; struct { @@ -26966,25 +14603,12 @@ typedef union sh_md_dqrp_mmr_xbist_err_l_u { mmr_t reserved_1 : 22; } sh_md_dqrp_mmr_xbist_err_l_s; } sh_md_dqrp_mmr_xbist_err_l_u_t; -#else -typedef union sh_md_dqrp_mmr_xbist_err_l_u { - mmr_t sh_md_dqrp_mmr_xbist_err_l_regval; - struct { - mmr_t reserved_1 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqrp_mmr_xbist_err_l_s; -} sh_md_dqrp_mmr_xbist_err_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_YBIST_H" */ /* rising edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_ybist_h_u { mmr_t sh_md_dqrp_mmr_ybist_h_regval; struct { @@ -26996,26 +14620,12 @@ typedef union sh_md_dqrp_mmr_ybist_h_u { mmr_t reserved_1 : 21; } sh_md_dqrp_mmr_ybist_h_s; } sh_md_dqrp_mmr_ybist_h_u_t; -#else -typedef union sh_md_dqrp_mmr_ybist_h_u { - mmr_t sh_md_dqrp_mmr_ybist_h_regval; - struct { - mmr_t reserved_1 : 21; - mmr_t arm : 1; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqrp_mmr_ybist_h_s; -} sh_md_dqrp_mmr_ybist_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_YBIST_L" */ /* falling edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_ybist_l_u { mmr_t sh_md_dqrp_mmr_ybist_l_regval; struct { @@ -27026,25 +14636,12 @@ typedef union sh_md_dqrp_mmr_ybist_l_u { mmr_t reserved_1 : 22; } sh_md_dqrp_mmr_ybist_l_s; } sh_md_dqrp_mmr_ybist_l_u_t; -#else -typedef union sh_md_dqrp_mmr_ybist_l_u { - mmr_t sh_md_dqrp_mmr_ybist_l_regval; - struct { - mmr_t reserved_1 : 22; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqrp_mmr_ybist_l_s; -} sh_md_dqrp_mmr_ybist_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_YBIST_ERR_H" */ /* rising edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_ybist_err_h_u { mmr_t sh_md_dqrp_mmr_ybist_err_h_regval; struct { @@ -27055,25 +14652,12 @@ typedef union sh_md_dqrp_mmr_ybist_err_h_u { mmr_t reserved_1 : 22; } sh_md_dqrp_mmr_ybist_err_h_s; } sh_md_dqrp_mmr_ybist_err_h_u_t; -#else -typedef union sh_md_dqrp_mmr_ybist_err_h_u { - mmr_t sh_md_dqrp_mmr_ybist_err_h_regval; - struct { - mmr_t reserved_1 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqrp_mmr_ybist_err_h_s; -} sh_md_dqrp_mmr_ybist_err_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_YBIST_ERR_L" */ /* falling edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_ybist_err_l_u { mmr_t sh_md_dqrp_mmr_ybist_err_l_regval; struct { @@ -27084,25 +14668,12 @@ typedef union sh_md_dqrp_mmr_ybist_err_l_u { mmr_t reserved_1 : 22; } sh_md_dqrp_mmr_ybist_err_l_s; } sh_md_dqrp_mmr_ybist_err_l_u_t; -#else -typedef union sh_md_dqrp_mmr_ybist_err_l_u { - mmr_t sh_md_dqrp_mmr_ybist_err_l_regval; - struct { - mmr_t reserved_1 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqrp_mmr_ybist_err_l_s; -} sh_md_dqrp_mmr_ybist_err_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRS_MMR_XBIST_H" */ /* rising edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrs_mmr_xbist_h_u { mmr_t sh_md_dqrs_mmr_xbist_h_regval; struct { @@ -27113,25 +14684,12 @@ typedef union sh_md_dqrs_mmr_xbist_h_u { mmr_t reserved_0 : 21; } sh_md_dqrs_mmr_xbist_h_s; } sh_md_dqrs_mmr_xbist_h_u_t; -#else -typedef union sh_md_dqrs_mmr_xbist_h_u { - mmr_t sh_md_dqrs_mmr_xbist_h_regval; - struct { - mmr_t reserved_0 : 21; - mmr_t arm : 1; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t pat : 40; - } sh_md_dqrs_mmr_xbist_h_s; -} sh_md_dqrs_mmr_xbist_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRS_MMR_XBIST_L" */ /* falling edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrs_mmr_xbist_l_u { mmr_t sh_md_dqrs_mmr_xbist_l_regval; struct { @@ -27141,24 +14699,12 @@ typedef union sh_md_dqrs_mmr_xbist_l_u { mmr_t reserved_0 : 22; } sh_md_dqrs_mmr_xbist_l_s; } sh_md_dqrs_mmr_xbist_l_u_t; -#else -typedef union sh_md_dqrs_mmr_xbist_l_u { - mmr_t sh_md_dqrs_mmr_xbist_l_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t pat : 40; - } sh_md_dqrs_mmr_xbist_l_s; -} sh_md_dqrs_mmr_xbist_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRS_MMR_XBIST_ERR_H" */ /* rising edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrs_mmr_xbist_err_h_u { mmr_t sh_md_dqrs_mmr_xbist_err_h_regval; struct { @@ -27168,24 +14714,12 @@ typedef union sh_md_dqrs_mmr_xbist_err_h_u { mmr_t reserved_0 : 22; } sh_md_dqrs_mmr_xbist_err_h_s; } sh_md_dqrs_mmr_xbist_err_h_u_t; -#else -typedef union sh_md_dqrs_mmr_xbist_err_h_u { - mmr_t sh_md_dqrs_mmr_xbist_err_h_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t pat : 40; - } sh_md_dqrs_mmr_xbist_err_h_s; -} sh_md_dqrs_mmr_xbist_err_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRS_MMR_XBIST_ERR_L" */ /* falling edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrs_mmr_xbist_err_l_u { mmr_t sh_md_dqrs_mmr_xbist_err_l_regval; struct { @@ -27195,24 +14729,12 @@ typedef union sh_md_dqrs_mmr_xbist_err_l_u { mmr_t reserved_0 : 22; } sh_md_dqrs_mmr_xbist_err_l_s; } sh_md_dqrs_mmr_xbist_err_l_u_t; -#else -typedef union sh_md_dqrs_mmr_xbist_err_l_u { - mmr_t sh_md_dqrs_mmr_xbist_err_l_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t pat : 40; - } sh_md_dqrs_mmr_xbist_err_l_s; -} sh_md_dqrs_mmr_xbist_err_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRS_MMR_YBIST_H" */ /* rising edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrs_mmr_ybist_h_u { mmr_t sh_md_dqrs_mmr_ybist_h_regval; struct { @@ -27223,25 +14745,12 @@ typedef union sh_md_dqrs_mmr_ybist_h_u { mmr_t reserved_0 : 21; } sh_md_dqrs_mmr_ybist_h_s; } sh_md_dqrs_mmr_ybist_h_u_t; -#else -typedef union sh_md_dqrs_mmr_ybist_h_u { - mmr_t sh_md_dqrs_mmr_ybist_h_regval; - struct { - mmr_t reserved_0 : 21; - mmr_t arm : 1; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t pat : 40; - } sh_md_dqrs_mmr_ybist_h_s; -} sh_md_dqrs_mmr_ybist_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRS_MMR_YBIST_L" */ /* falling edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrs_mmr_ybist_l_u { mmr_t sh_md_dqrs_mmr_ybist_l_regval; struct { @@ -27251,24 +14760,12 @@ typedef union sh_md_dqrs_mmr_ybist_l_u { mmr_t reserved_0 : 22; } sh_md_dqrs_mmr_ybist_l_s; } sh_md_dqrs_mmr_ybist_l_u_t; -#else -typedef union sh_md_dqrs_mmr_ybist_l_u { - mmr_t sh_md_dqrs_mmr_ybist_l_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t pat : 40; - } sh_md_dqrs_mmr_ybist_l_s; -} sh_md_dqrs_mmr_ybist_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRS_MMR_YBIST_ERR_H" */ /* rising edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrs_mmr_ybist_err_h_u { mmr_t sh_md_dqrs_mmr_ybist_err_h_regval; struct { @@ -27278,24 +14775,12 @@ typedef union sh_md_dqrs_mmr_ybist_err_h_u { mmr_t reserved_0 : 22; } sh_md_dqrs_mmr_ybist_err_h_s; } sh_md_dqrs_mmr_ybist_err_h_u_t; -#else -typedef union sh_md_dqrs_mmr_ybist_err_h_u { - mmr_t sh_md_dqrs_mmr_ybist_err_h_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t pat : 40; - } sh_md_dqrs_mmr_ybist_err_h_s; -} sh_md_dqrs_mmr_ybist_err_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRS_MMR_YBIST_ERR_L" */ /* falling edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrs_mmr_ybist_err_l_u { mmr_t sh_md_dqrs_mmr_ybist_err_l_regval; struct { @@ -27305,24 +14790,12 @@ typedef union sh_md_dqrs_mmr_ybist_err_l_u { mmr_t reserved_0 : 22; } sh_md_dqrs_mmr_ybist_err_l_s; } sh_md_dqrs_mmr_ybist_err_l_u_t; -#else -typedef union sh_md_dqrs_mmr_ybist_err_l_u { - mmr_t sh_md_dqrs_mmr_ybist_err_l_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t pat : 40; - } sh_md_dqrs_mmr_ybist_err_l_s; -} sh_md_dqrs_mmr_ybist_err_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRS_MMR_JNR_DEBUG" */ /* joiner/fct debug configuration */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrs_mmr_jnr_debug_u { mmr_t sh_md_dqrs_mmr_jnr_debug_regval; struct { @@ -27331,23 +14804,12 @@ typedef union sh_md_dqrs_mmr_jnr_debug_u { mmr_t reserved_0 : 62; } sh_md_dqrs_mmr_jnr_debug_s; } sh_md_dqrs_mmr_jnr_debug_u_t; -#else -typedef union sh_md_dqrs_mmr_jnr_debug_u { - mmr_t sh_md_dqrs_mmr_jnr_debug_regval; - struct { - mmr_t reserved_0 : 62; - mmr_t rw : 1; - mmr_t px : 1; - } sh_md_dqrs_mmr_jnr_debug_s; -} sh_md_dqrs_mmr_jnr_debug_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRS_MMR_YAMOPW_ERR" */ /* amo/partial rmw ecc error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrs_mmr_yamopw_err_u { mmr_t sh_md_dqrs_mmr_yamopw_err_regval; struct { @@ -27363,23 +14825,5 @@ typedef union sh_md_dqrs_mmr_yamopw_err_u { mmr_t reserved_2 : 31; } sh_md_dqrs_mmr_yamopw_err_s; } sh_md_dqrs_mmr_yamopw_err_u_t; -#else -typedef union sh_md_dqrs_mmr_yamopw_err_u { - mmr_t sh_md_dqrs_mmr_yamopw_err_regval; - struct { - mmr_t reserved_2 : 31; - mmr_t arm : 1; - mmr_t reserved_1 : 6; - mmr_t runc : 1; - mmr_t rcor : 1; - mmr_t rsyn : 8; - mmr_t reserved_0 : 6; - mmr_t sunc : 1; - mmr_t scor : 1; - mmr_t ssyn : 8; - } sh_md_dqrs_mmr_yamopw_err_s; -} sh_md_dqrs_mmr_yamopw_err_u_t; -#endif - #endif /* _ASM_IA64_SN_SN2_SHUB_MMR_T_H */ diff --git a/include/asm-ia64/spinlock.h b/include/asm-ia64/spinlock.h index 6ab675570740..d2bcd9b20784 100644 --- a/include/asm-ia64/spinlock.h +++ b/include/asm-ia64/spinlock.h @@ -166,7 +166,7 @@ do { \ #define _raw_write_lock(l) \ ({ \ __u64 ia64_val, ia64_set_val = ia64_dep_mi(-1, 0, 31, 1); \ - __u32 ia64_write_lock_ptr = (__u32 *) (l); \ + __u32 *ia64_write_lock_ptr = (__u32 *) (l); \ do { \ while (*ia64_write_lock_ptr) \ ia64_barrier(); \ diff --git a/include/asm-m68k/processor.h b/include/asm-m68k/processor.h index fb463bda10de..7516e2945ecd 100644 --- a/include/asm-m68k/processor.h +++ b/include/asm-m68k/processor.h @@ -56,7 +56,6 @@ extern inline void wrusp(unsigned long usp) { /* * Bus types */ -#define EISA_bus 0 #define MCA_bus 0 struct task_work { diff --git a/include/asm-m68k/signal.h b/include/asm-m68k/signal.h index dfb43563e1cc..8d9c02cafc01 100644 --- a/include/asm-m68k/signal.h +++ b/include/asm-m68k/signal.h @@ -68,7 +68,7 @@ typedef unsigned long sigset_t; /* These should not be considered constants from userland. */ #define SIGRTMIN 32 -#define SIGRTMAX (_NSIG-1) +#define SIGRTMAX _NSIG /* * SA_FLAGS values: diff --git a/include/asm-m68knommu/processor.h b/include/asm-m68knommu/processor.h index 547a96604b46..736e3192f464 100644 --- a/include/asm-m68knommu/processor.h +++ b/include/asm-m68knommu/processor.h @@ -58,7 +58,6 @@ extern inline void wrusp(unsigned long usp) /* * Bus types */ -#define EISA_bus 0 #define MCA_bus 0 /* diff --git a/include/asm-m68knommu/signal.h b/include/asm-m68knommu/signal.h index 4b4f4b4058f1..486cbb0dc088 100644 --- a/include/asm-m68knommu/signal.h +++ b/include/asm-m68knommu/signal.h @@ -68,7 +68,7 @@ typedef unsigned long sigset_t; /* These should not be considered constants from userland. */ #define SIGRTMIN 32 -#define SIGRTMAX (_NSIG-1) +#define SIGRTMAX _NSIG /* * SA_FLAGS values: diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h index c08e0bf6e76c..33e8cc7c721d 100644 --- a/include/asm-mips/processor.h +++ b/include/asm-mips/processor.h @@ -135,12 +135,6 @@ extern unsigned int vced_count, vcei_count; /* * Bus types (default is ISA, but people can check others with these..) */ -#ifdef CONFIG_EISA -extern int EISA_bus; -#else -#define EISA_bus (0) -#endif - #define MCA_bus 0 #define MCA_bus__is_a_macro /* for versions in ksyms.c */ diff --git a/include/asm-mips/signal.h b/include/asm-mips/signal.h index 40d73cc2a1e0..994987db61be 100644 --- a/include/asm-mips/signal.h +++ b/include/asm-mips/signal.h @@ -59,7 +59,7 @@ typedef unsigned long old_sigset_t; /* at least 32 bits */ /* These should not be considered constants from userland. */ #define SIGRTMIN 32 -#define SIGRTMAX (_NSIG-1) +#define SIGRTMAX _NSIG /* * SA_FLAGS values: diff --git a/include/asm-parisc/processor.h b/include/asm-parisc/processor.h index ded1c4904510..4779a6efeb91 100644 --- a/include/asm-parisc/processor.h +++ b/include/asm-parisc/processor.h @@ -101,12 +101,6 @@ extern struct cpuinfo_parisc cpu_data[NR_CPUS]; #define CPU_HVERSION ((boot_cpu_data.hversion >> 4) & 0x0FFF) -#ifdef CONFIG_EISA -extern int EISA_bus; -#else -#define EISA_bus 0 -#endif - #define MCA_bus 0 #define MCA_bus__is_a_macro /* for versions in ksyms.c */ diff --git a/include/asm-parisc/signal.h b/include/asm-parisc/signal.h index 5ab02aef6dea..cd4beefef333 100644 --- a/include/asm-parisc/signal.h +++ b/include/asm-parisc/signal.h @@ -42,7 +42,7 @@ /* These should not be considered constants from userland. */ #define SIGRTMIN 37 -#define SIGRTMAX (_NSIG-1) /* it's 44 under HP/UX */ +#define SIGRTMAX _NSIG /* it's 44 under HP/UX */ /* * SA_FLAGS values: diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 3a893e9d6b47..2a5437042ad8 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -803,7 +803,6 @@ extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); /* * Bus types */ -#define EISA_bus 0 #define MCA_bus 0 #define MCA_bus__is_a_macro diff --git a/include/asm-ppc/signal.h b/include/asm-ppc/signal.h index f692baff3a44..b0528fcbe985 100644 --- a/include/asm-ppc/signal.h +++ b/include/asm-ppc/signal.h @@ -61,7 +61,7 @@ typedef struct { /* These should not be considered constants from userland. */ #define SIGRTMIN 32 -#define SIGRTMAX (_NSIG-1) +#define SIGRTMAX _NSIG /* * SA_FLAGS values: diff --git a/include/asm-ppc/time.h b/include/asm-ppc/time.h index ff2939bcbcf9..67188ec06a7a 100644 --- a/include/asm-ppc/time.h +++ b/include/asm-ppc/time.h @@ -97,6 +97,13 @@ extern __inline__ unsigned long get_rtcl(void) { return rtcl; } +extern __inline__ unsigned long get_rtcu(void) +{ + unsigned long rtcu; + asm volatile("mfrtcu %0" : "=r" (rtcu)); + return rtcu; +} + extern __inline__ unsigned get_native_tbl(void) { if (__USE_RTC()) return get_rtcl(); @@ -140,6 +147,7 @@ extern __inline__ unsigned binary_tbl(void) { #endif /* Use mulhwu to scale processor timebase to timeval */ +/* Specifically, this computes (x * y) / 2^32. -- paulus */ #define mulhwu(x,y) \ ({unsigned z; asm ("mulhwu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;}) diff --git a/include/asm-ppc64/processor.h b/include/asm-ppc64/processor.h index 7d0246bd87cb..f878c5b05d42 100644 --- a/include/asm-ppc64/processor.h +++ b/include/asm-ppc64/processor.h @@ -612,8 +612,6 @@ extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); /* * Bus types */ -#define EISA_bus 0 -#define EISA_bus__is_a_macro /* for versions in ksyms.c */ #define MCA_bus 0 #define MCA_bus__is_a_macro /* for versions in ksyms.c */ diff --git a/include/asm-ppc64/signal.h b/include/asm-ppc64/signal.h index 97ed18c9bb60..d0baf44cc89a 100644 --- a/include/asm-ppc64/signal.h +++ b/include/asm-ppc64/signal.h @@ -57,7 +57,7 @@ typedef struct { /* These should not be considered constants from userland. */ #define SIGRTMIN 32 -#define SIGRTMAX (_NSIG-1) +#define SIGRTMAX _NSIG /* * SA_FLAGS values: diff --git a/include/asm-s390/signal.h b/include/asm-s390/signal.h index fe2263b3ee0d..f273cdcd1cf6 100644 --- a/include/asm-s390/signal.h +++ b/include/asm-s390/signal.h @@ -78,7 +78,7 @@ typedef unsigned long sigset_t; /* These should not be considered constants from userland. */ #define SIGRTMIN 32 -#define SIGRTMAX (_NSIG-1) +#define SIGRTMAX _NSIG /* * SA_FLAGS values: diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h index 99661c8d8cb0..1308d81838fd 100644 --- a/include/asm-sh/processor.h +++ b/include/asm-sh/processor.h @@ -169,8 +169,6 @@ extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); /* * Bus types */ -#define EISA_bus 0 -#define EISA_bus__is_a_macro /* for versions in ksyms.c */ #define MCA_bus 0 #define MCA_bus__is_a_macro /* for versions in ksyms.c */ diff --git a/include/asm-sh/signal.h b/include/asm-sh/signal.h index 2f8118eb0cb5..51a5f0691ee5 100644 --- a/include/asm-sh/signal.h +++ b/include/asm-sh/signal.h @@ -57,7 +57,7 @@ typedef struct { /* These should not be considered constants from userland. */ #define SIGRTMIN 32 -#define SIGRTMAX (_NSIG-1) +#define SIGRTMAX _NSIG /* * SA_FLAGS values: diff --git a/include/asm-sparc/processor.h b/include/asm-sparc/processor.h index c2b7125aa005..3f3bf3ca874c 100644 --- a/include/asm-sparc/processor.h +++ b/include/asm-sparc/processor.h @@ -27,7 +27,6 @@ /* * Bus types */ -#define EISA_bus 0 #define MCA_bus 0 #define MCA_bus__is_a_macro /* for versions in ksyms.c */ diff --git a/include/asm-sparc/signal.h b/include/asm-sparc/signal.h index 4e455b7add4a..6813baae27c6 100644 --- a/include/asm-sparc/signal.h +++ b/include/asm-sparc/signal.h @@ -89,7 +89,7 @@ #define _NSIG_WORDS (__NEW_NSIG / _NSIG_BPW) #define SIGRTMIN 32 -#define SIGRTMAX (__NEW_NSIG - 1) +#define SIGRTMAX __NEW_NSIG #if defined(__KERNEL__) || defined(__WANT_POSIX1B_SIGNALS__) #define _NSIG __NEW_NSIG diff --git a/include/asm-sparc64/processor.h b/include/asm-sparc64/processor.h index bec2ef59d771..416fad2ef1b1 100644 --- a/include/asm-sparc64/processor.h +++ b/include/asm-sparc64/processor.h @@ -22,7 +22,6 @@ #include <asm/page.h> /* Bus types */ -#define EISA_bus 0 #define MCA_bus 0 #define MCA_bus__is_a_macro /* for versions in ksyms.c */ diff --git a/include/asm-sparc64/signal.h b/include/asm-sparc64/signal.h index 63ac2e389367..f2101925bb74 100644 --- a/include/asm-sparc64/signal.h +++ b/include/asm-sparc64/signal.h @@ -89,7 +89,7 @@ #define _NSIG_WORDS (__NEW_NSIG / _NSIG_BPW) #define SIGRTMIN 32 -#define SIGRTMAX (__NEW_NSIG - 1) +#define SIGRTMAX __NEW_NSIG #if defined(__KERNEL__) || defined(__WANT_POSIX1B_SIGNALS__) #define _NSIG __NEW_NSIG diff --git a/include/asm-v850/processor.h b/include/asm-v850/processor.h index 025202b4df7e..b28582ecce02 100644 --- a/include/asm-v850/processor.h +++ b/include/asm-v850/processor.h @@ -52,8 +52,6 @@ /* * Bus types */ -#define EISA_bus 0 -#define EISA_bus__is_a_macro /* for versions in ksyms.c */ #define MCA_bus 0 #define MCA_bus__is_a_macro /* for versions in ksyms.c */ diff --git a/include/asm-v850/signal.h b/include/asm-v850/signal.h index c33b1db71749..407db875899c 100644 --- a/include/asm-v850/signal.h +++ b/include/asm-v850/signal.h @@ -71,7 +71,7 @@ typedef unsigned long sigset_t; /* These should not be considered constants from userland. */ #define SIGRTMIN 32 -#define SIGRTMAX (_NSIG-1) +#define SIGRTMAX _NSIG /* * SA_FLAGS values: diff --git a/include/asm-x86_64/processor.h b/include/asm-x86_64/processor.h index 7b4430ce23a0..805b7c03dbbc 100644 --- a/include/asm-x86_64/processor.h +++ b/include/asm-x86_64/processor.h @@ -160,7 +160,6 @@ static inline void clear_in_cr4 (unsigned long mask) /* * Bus types */ -#define EISA_bus 0 #define MCA_bus 0 #define MCA_bus__is_a_macro diff --git a/include/asm-x86_64/signal.h b/include/asm-x86_64/signal.h index bd1f350f1ba6..21c4bf716666 100644 --- a/include/asm-x86_64/signal.h +++ b/include/asm-x86_64/signal.h @@ -77,7 +77,7 @@ typedef unsigned long sigset_t; /* These should not be considered constants from userland. */ #define SIGRTMIN 32 -#define SIGRTMAX (_NSIG-1) +#define SIGRTMAX _NSIG /* * SA_FLAGS values: diff --git a/include/linux/bio.h b/include/linux/bio.h index 6ad6d20d3778..0ac6a27ea0db 100644 --- a/include/linux/bio.h +++ b/include/linux/bio.h @@ -20,7 +20,6 @@ #ifndef __LINUX_BIO_H #define __LINUX_BIO_H -#include <linux/kdev_t.h> #include <linux/highmem.h> #include <linux/mempool.h> diff --git a/include/linux/compiler-gcc+.h b/include/linux/compiler-gcc+.h new file mode 100644 index 000000000000..f6ae9e76b825 --- /dev/null +++ b/include/linux/compiler-gcc+.h @@ -0,0 +1,14 @@ +/* Never include this file directly. Include <linux/compiler.h> instead. */ + +/* + * These definitions are for Ueber-GCC: always newer than the latest + * version and hence sporting everything plus a kitchen-sink. + */ +#include <linux/compiler-gcc.h> + +#define inline __inline__ __attribute__((always_inline)) +#define __inline__ __inline__ __attribute__((always_inline)) +#define __inline __inline__ __attribute__((always_inline)) +#define __deprecated __attribute__((deprecated)) +#define __attribute_used__ __attribute__((__used__)) +#define __attribute_pure__ __attribute__((pure)) diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h new file mode 100644 index 000000000000..152734055403 --- /dev/null +++ b/include/linux/compiler-gcc.h @@ -0,0 +1,17 @@ +/* Never include this file directly. Include <linux/compiler.h> instead. */ + +/* + * Common definitions for all gcc versions go here. + */ + + +/* Optimization barrier */ +/* The "volatile" is due to gcc bugs */ +#define barrier() __asm__ __volatile__("": : :"memory") + +/* This macro obfuscates arithmetic on a variable address so that gcc + shouldn't recognize the original var, and make assumptions about it */ +#define RELOC_HIDE(ptr, off) \ + ({ unsigned long __ptr; \ + __asm__ ("" : "=g"(__ptr) : "0"(ptr)); \ + (typeof(ptr)) (__ptr + (off)); }) diff --git a/include/linux/compiler-gcc2.h b/include/linux/compiler-gcc2.h new file mode 100644 index 000000000000..6f4f9d526abe --- /dev/null +++ b/include/linux/compiler-gcc2.h @@ -0,0 +1,23 @@ +/* Never include this file directly. Include <linux/compiler.h> instead. */ + +/* These definitions are for GCC v2.x. */ + +/* Somewhere in the middle of the GCC 2.96 development cycle, we implemented + a mechanism by which the user can annotate likely branch directions and + expect the blocks to be reordered appropriately. Define __builtin_expect + to nothing for earlier compilers. */ +#include <linux/compiler-gcc.h> + +#if __GNUC_MINOR__ < 96 +# define __builtin_expect(x, expected_value) (x) +#endif + +#define __attribute_used__ __attribute__((__unused__)) + +/* + * The attribute `pure' is not implemented in GCC versions earlier + * than 2.96. + */ +#if __GNUC_MINOR__ >= 96 +# define __attribute_pure__ __attribute__((pure)) +#endif diff --git a/include/linux/compiler-gcc3.h b/include/linux/compiler-gcc3.h new file mode 100644 index 000000000000..4eac3db89fda --- /dev/null +++ b/include/linux/compiler-gcc3.h @@ -0,0 +1,22 @@ +/* Never include this file directly. Include <linux/compiler.h> instead. */ + +/* These definitions are for GCC v3.x. */ +#include <linux/compiler-gcc.h> + +#if __GNUC_MINOR__ >= 1 +# define inline __inline__ __attribute__((always_inline)) +# define __inline__ __inline__ __attribute__((always_inline)) +# define __inline __inline__ __attribute__((always_inline)) +#endif + +#if __GNUC_MINOR__ > 0 +# define __deprecated __attribute__((deprecated)) +#endif + +#if __GNUC_MINOR__ >= 3 +# define __attribute_used__ __attribute__((__used__)) +#else +# define __attribute_used__ __attribute__((__unused__)) +#endif + +#define __attribute_pure__ __attribute__((pure)) diff --git a/include/linux/compiler-intel.h b/include/linux/compiler-intel.h new file mode 100644 index 000000000000..1d1c3ceaff4e --- /dev/null +++ b/include/linux/compiler-intel.h @@ -0,0 +1,24 @@ +/* Never include this file directly. Include <linux/compiler.h> instead. */ + +#ifdef __ECC + +/* Some compiler specific definitions are overwritten here + * for Intel ECC compiler + */ + +#include <asm/intrinsics.h> + +/* Intel ECC compiler doesn't support gcc specific asm stmts. + * It uses intrinsics to do the equivalent things. + */ +#undef barrier +#undef RELOC_HIDE + +#define barrier() __memory_barrier() + +#define RELOC_HIDE(ptr, off) \ + ({ unsigned long __ptr; \ + __ptr = (unsigned long) (ptr); \ + (typeof(ptr)) (__ptr + (off)); }) + +#endif diff --git a/include/linux/compiler.h b/include/linux/compiler.h index 356428f649fc..528641f69043 100644 --- a/include/linux/compiler.h +++ b/include/linux/compiler.h @@ -2,28 +2,36 @@ #define __LINUX_COMPILER_H #ifdef __CHECKER__ - #define __user __attribute__((noderef, address_space(1))) - #define __kernel /* default address space */ +# define __user __attribute__((noderef, address_space(1))) +# define __kernel /* default address space */ #else - #define __user - #define __kernel +# define __user +# define __kernel #endif -#if (__GNUC__ > 3) || (__GNUC__ == 3 && __GNUC_MINOR__ >= 1) -#define inline __inline__ __attribute__((always_inline)) -#define __inline__ __inline__ __attribute__((always_inline)) -#define __inline __inline__ __attribute__((always_inline)) +#if __GNUC__ > 3 +# include <linux/compiler-gcc+.h> /* catch-all for GCC 4, 5, etc. */ +#elif __GNUC__ == 3 +# include <linux/compiler-gcc3.h> +#elif __GNUC__ == 2 +# include <linux/compiler-gcc2.h> +#else +# error Sorry, your compiler is too old/not recognized. #endif -/* Somewhere in the middle of the GCC 2.96 development cycle, we implemented - a mechanism by which the user can annotate likely branch directions and - expect the blocks to be reordered appropriately. Define __builtin_expect - to nothing for earlier compilers. */ - -#if __GNUC__ == 2 && __GNUC_MINOR__ < 96 -#define __builtin_expect(x, expected_value) (x) +/* Intel compiler defines __GNUC__. So we will overwrite implementations + * coming from above header files here + */ +#ifdef __INTEL_COMPILER +# include <linux/compiler-intel.h> #endif +/* + * Generic compiler-dependent macros required for kernel + * build go below this comment. Actual compiler/compiler version + * specific implementations come from the above header files + */ + #define likely(x) __builtin_expect(!!(x), 1) #define unlikely(x) __builtin_expect(!!(x), 0) @@ -33,10 +41,8 @@ * Usage is: * int __deprecated foo(void) */ -#if ( __GNUC__ == 3 && __GNUC_MINOR__ > 0 ) || __GNUC__ > 3 -#define __deprecated __attribute__((deprecated)) -#else -#define __deprecated +#ifndef __deprecated +# define __deprecated /* unimplemented */ #endif /* @@ -50,10 +56,8 @@ * In prior versions of gcc, such functions and data would be emitted, but * would be warned about except with attribute((unused)). */ -#if __GNUC__ == 3 && __GNUC_MINOR__ >= 3 || __GNUC__ > 3 -#define __attribute_used__ __attribute__((__used__)) -#else -#define __attribute_used__ __attribute__((__unused__)) +#ifndef __attribute_used__ +# define __attribute_used__ /* unimplemented */ #endif /* @@ -65,19 +69,21 @@ * elimination and loop optimization just as an arithmetic operator * would be. * [...] - * The attribute `pure' is not implemented in GCC versions earlier - * than 2.96. */ -#if (__GNUC__ == 2 && __GNUC_MINOR__ >= 96) || __GNUC__ > 2 -#define __attribute_pure__ __attribute__((pure)) -#else -#define __attribute_pure__ /* unimplemented */ +#ifndef __attribute_pure__ +# define __attribute_pure__ /* unimplemented */ +#endif + +/* Optimization barrier */ +#ifndef barrier +# define barrier() __memory_barrier() #endif -/* This macro obfuscates arithmetic on a variable address so that gcc - shouldn't recognize the original var, and make assumptions about it */ -#define RELOC_HIDE(ptr, off) \ +#ifndef RELOC_HIDE +# define RELOC_HIDE(ptr, off) \ ({ unsigned long __ptr; \ - __asm__ ("" : "=g"(__ptr) : "0"(ptr)); \ + __ptr = (unsigned long) (ptr); \ (typeof(ptr)) (__ptr + (off)); }) +#endif + #endif /* __LINUX_COMPILER_H */ diff --git a/include/linux/console.h b/include/linux/console.h index 414ebe159d67..cdff9de7ee71 100644 --- a/include/linux/console.h +++ b/include/linux/console.h @@ -15,7 +15,6 @@ #define _LINUX_CONSOLE_H_ 1 #include <linux/types.h> -#include <linux/kdev_t.h> #include <linux/spinlock.h> struct vc_data; diff --git a/include/linux/devfs_fs_kernel.h b/include/linux/devfs_fs_kernel.h index f12addd1daeb..16c78f54f427 100644 --- a/include/linux/devfs_fs_kernel.h +++ b/include/linux/devfs_fs_kernel.h @@ -4,7 +4,6 @@ #include <linux/fs.h> #include <linux/config.h> #include <linux/spinlock.h> -#include <linux/kdev_t.h> #include <linux/types.h> #include <asm/semaphore.h> diff --git a/include/linux/eisa.h b/include/linux/eisa.h index 2ef648847879..dc76d57b10d0 100644 --- a/include/linux/eisa.h +++ b/include/linux/eisa.h @@ -1,6 +1,19 @@ #ifndef _LINUX_EISA_H #define _LINUX_EISA_H +#include <linux/ioport.h> +#include <linux/device.h> + +#ifdef CONFIG_EISA +# ifdef CONFIG_EISA_ALWAYS +# define EISA_bus 1 +# else + extern int EISA_bus; +# endif +#else +# define EISA_bus 0 +#endif + #define EISA_SIG_LEN 8 #define EISA_MAX_SLOTS 8 diff --git a/include/linux/elevator.h b/include/linux/elevator.h index e43d670c1371..cbd038b665e8 100644 --- a/include/linux/elevator.h +++ b/include/linux/elevator.h @@ -15,7 +15,6 @@ typedef int (elevator_queue_empty_fn) (request_queue_t *); typedef void (elevator_remove_req_fn) (request_queue_t *, struct request *); typedef void (elevator_requeue_req_fn) (request_queue_t *, struct request *); typedef struct request *(elevator_request_list_fn) (request_queue_t *, struct request *); -typedef struct list_head *(elevator_get_sort_head_fn) (request_queue_t *, struct request *); typedef void (elevator_completed_req_fn) (request_queue_t *, struct request *); typedef int (elevator_may_queue_fn) (request_queue_t *, int); diff --git a/include/linux/ftape.h b/include/linux/ftape.h index 99b3535a4e20..e21d4b442843 100644 --- a/include/linux/ftape.h +++ b/include/linux/ftape.h @@ -199,8 +199,6 @@ typedef union { #define ABS(a) ((a) < 0 ? -(a) : (a)) #define NR_ITEMS(x) (int)(sizeof(x)/ sizeof(*x)) -extern int ftape_init(void); - #endif /* __KERNEL__ */ #endif diff --git a/include/linux/input.h b/include/linux/input.h index da49f7ee0f18..c98e6fc575fe 100644 --- a/include/linux/input.h +++ b/include/linux/input.h @@ -751,7 +751,7 @@ struct ff_effect { #define LONG(x) ((x)/BITS_PER_LONG) #define INPUT_KEYCODE(dev, scancode) ((dev->keycodesize == 1) ? ((u8*)dev->keycode)[scancode] : \ - ((dev->keycodesize == 1) ? ((u16*)dev->keycode)[scancode] : (((u32*)dev->keycode)[scancode]))) + ((dev->keycodesize == 2) ? ((u16*)dev->keycode)[scancode] : (((u32*)dev->keycode)[scancode]))) #define init_input_dev(dev) do { INIT_LIST_HEAD(&((dev)->h_list)); INIT_LIST_HEAD(&((dev)->node)); } while (0) diff --git a/include/linux/kernel.h b/include/linux/kernel.h index b2d17ea0dac0..6403c9ef2210 100644 --- a/include/linux/kernel.h +++ b/include/linux/kernel.h @@ -15,10 +15,6 @@ #include <asm/byteorder.h> #include <asm/bug.h> -/* Optimization barrier */ -/* The "volatile" is due to gcc bugs */ -#define barrier() __asm__ __volatile__("": : :"memory") - #define INT_MAX ((int)(~0U>>1)) #define INT_MIN (-INT_MAX - 1) #define UINT_MAX (~0U) diff --git a/include/linux/llc.h b/include/linux/llc.h index 77ac5d9df544..c9085baaf74d 100644 --- a/include/linux/llc.h +++ b/include/linux/llc.h @@ -79,13 +79,5 @@ enum llc_sockopts { #define LLC_SAP_DYN_TRIES 4 #define llc_ui_skb_cb(__skb) ((struct sockaddr_llc *)&((__skb)->cb[0])) - -#ifdef CONFIG_LLC_UI -extern int llc_ui_init(void); -extern void llc_ui_exit(void); -#else -#define llc_ui_init() -#define llc_ui_exit() -#endif #endif /* __KERNEL__ */ #endif /* __LINUX_LLC_H */ diff --git a/include/linux/miscdevice.h b/include/linux/miscdevice.h index d3af91351521..6b7f9c1fa5cd 100644 --- a/include/linux/miscdevice.h +++ b/include/linux/miscdevice.h @@ -36,8 +36,6 @@ #define TUN_MINOR 200 -extern int misc_init(void); - struct miscdevice { int minor; diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index 0175e588f33b..a69f0c920d20 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -502,7 +502,11 @@ extern struct net_device *dev_getbyhwaddr(unsigned short type, char *hwaddr); extern void dev_add_pack(struct packet_type *pt); extern void dev_remove_pack(struct packet_type *pt); extern void __dev_remove_pack(struct packet_type *pt); -extern int dev_get(const char *name); +extern int __dev_get(const char *name); +static inline int __deprecated dev_get(const char *name) +{ + return __dev_get(name); +} extern struct net_device *dev_get_by_flags(unsigned short flags, unsigned short mask); extern struct net_device *__dev_get_by_flags(unsigned short flags, diff --git a/include/linux/netfilter_ipv4/ipt_physdev.h b/include/linux/netfilter_ipv4/ipt_physdev.h index 01684a12d672..7538c8655ec0 100644 --- a/include/linux/netfilter_ipv4/ipt_physdev.h +++ b/include/linux/netfilter_ipv4/ipt_physdev.h @@ -13,12 +13,12 @@ #define IPT_PHYSDEV_OP_MASK (0x20 - 1) struct ipt_physdev_info { - u_int8_t invert; - u_int8_t bitmask; char physindev[IFNAMSIZ]; char in_mask[IFNAMSIZ]; char physoutdev[IFNAMSIZ]; char out_mask[IFNAMSIZ]; + u_int8_t invert; + u_int8_t bitmask; }; #endif /*_IPT_PHYSDEV_H*/ diff --git a/include/linux/nls.h b/include/linux/nls.h index 2ab6466f8043..1c657d4f0cf3 100644 --- a/include/linux/nls.h +++ b/include/linux/nls.h @@ -8,6 +8,7 @@ typedef __u16 wchar_t; struct nls_table { char *charset; + char *alias; int (*uni2char) (wchar_t uni, unsigned char *out, int boundlen); int (*char2uni) (const unsigned char *rawstring, int boundlen, wchar_t *uni); @@ -32,5 +33,7 @@ extern int utf8_mbstowcs(wchar_t *, const __u8 *, int); extern int utf8_wctomb(__u8 *, wchar_t, int); extern int utf8_wcstombs(__u8 *, const wchar_t *, int); +#define MODULE_ALIAS_NLS(name) MODULE_ALIAS("nls_" __stringify(name)) + #endif /* _LINUX_NLS_H */ diff --git a/include/linux/pnpbios.h b/include/linux/pnpbios.h index 5b0e599dd5e2..0720cd72d63a 100644 --- a/include/linux/pnpbios.h +++ b/include/linux/pnpbios.h @@ -26,7 +26,7 @@ #ifdef __KERNEL__ #include <linux/types.h> -#include <linux/pci.h> +#include <linux/pnp.h> /* * Return codes @@ -131,13 +131,7 @@ struct pnp_bios_node { #ifdef CONFIG_PNPBIOS /* non-exported */ -extern int pnpbios_dont_use_current_config; extern struct pnp_dev_node_info node_info; -extern void *pnpbios_kmalloc(size_t size, int f); -extern int pnpbios_init (void); -extern int pnpbios_interface_attach_device(struct pnp_bios_node * node); -extern int pnpbios_proc_init (void); -extern void pnpbios_proc_exit (void); extern int pnp_bios_dev_node_info (struct pnp_dev_node_info *data); extern int pnp_bios_get_dev_node (u8 *nodenum, char config, struct pnp_bios_node *data); diff --git a/include/linux/random.h b/include/linux/random.h index ca0e460941a5..9ccb52fa0a01 100644 --- a/include/linux/random.h +++ b/include/linux/random.h @@ -42,7 +42,6 @@ struct rand_pool_info { #ifdef __KERNEL__ -extern void rand_initialize(void); extern void rand_initialize_irq(int irq); extern void batch_entropy_store(u32 a, u32 b, int num); diff --git a/include/linux/sched.h b/include/linux/sched.h index 3c6e3129144d..1618ae7f42d4 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -281,7 +281,9 @@ struct signal_struct { #define MAX_RT_PRIO MAX_USER_RT_PRIO #define MAX_PRIO (MAX_RT_PRIO + 40) - + +#define rt_task(p) ((p)->prio < MAX_RT_PRIO) + /* * Some day this will be a full-fledged user tracking system.. */ @@ -340,7 +342,9 @@ struct task_struct { prio_array_t *array; unsigned long sleep_avg; - unsigned long last_run; + long interactive_credit; + unsigned long long timestamp; + int activated; unsigned long policy; cpumask_t cpus_allowed; @@ -360,7 +364,7 @@ struct task_struct { unsigned long personality; int did_exec:1; pid_t pid; - pid_t pgrp; + pid_t __pgrp; /* Accessed via process_group() */ pid_t tty_old_pgrp; pid_t session; pid_t tgid; @@ -375,7 +379,7 @@ struct task_struct { struct task_struct *parent; /* parent process */ struct list_head children; /* list of my children */ struct list_head sibling; /* linkage in my parent's children list */ - struct task_struct *group_leader; + struct task_struct *group_leader; /* threadgroup leader */ /* PID/PID hash table linkage. */ struct pid_link pids[PIDTYPE_MAX]; @@ -461,6 +465,11 @@ struct task_struct { siginfo_t *last_siginfo; /* For ptrace use. */ }; +static inline pid_t process_group(struct task_struct *tsk) +{ + return tsk->group_leader->__pgrp; +} + extern void __put_task_struct(struct task_struct *tsk); #define get_task_struct(tsk) do { atomic_inc(&(tsk)->usage); } while(0) #define put_task_struct(tsk) \ @@ -499,6 +508,8 @@ static inline int set_cpus_allowed(task_t *p, cpumask_t new_mask) } #endif +extern unsigned long long sched_clock(void); + #ifdef CONFIG_NUMA extern void sched_balance_exec(void); extern void node_nr_running_init(void); diff --git a/include/linux/serio.h b/include/linux/serio.h index f1c67ff70f2a..66fdaf9b1be5 100644 --- a/include/linux/serio.h +++ b/include/linux/serio.h @@ -65,7 +65,9 @@ void serio_rescan(struct serio *serio); irqreturn_t serio_interrupt(struct serio *serio, unsigned char data, unsigned int flags, struct pt_regs *regs); void serio_register_port(struct serio *serio); +void serio_register_slave_port(struct serio *serio); void serio_unregister_port(struct serio *serio); +void serio_unregister_slave_port(struct serio *serio); void serio_register_device(struct serio_dev *dev); void serio_unregister_device(struct serio_dev *dev); @@ -104,6 +106,7 @@ static __inline__ void serio_cleanup(struct serio *serio) #define SERIO_RS232 0x02000000UL #define SERIO_HIL_MLC 0x03000000UL #define SERIO_PC9800 0x04000000UL +#define SERIO_PS_PSTHRU 0x05000000UL #define SERIO_PROTO 0xFFUL #define SERIO_MSC 0x01 diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h index 4b5f057f8bfb..de8758a5e709 100644 --- a/include/linux/skbuff.h +++ b/include/linux/skbuff.h @@ -306,7 +306,7 @@ extern void skb_under_panic(struct sk_buff *skb, int len, * * Returns true if the queue is empty, false otherwise. */ -static inline int skb_queue_empty(struct sk_buff_head *list) +static inline int skb_queue_empty(const struct sk_buff_head *list) { return list->next == (struct sk_buff *)list; } @@ -357,7 +357,7 @@ static inline void kfree_skb_fast(struct sk_buff *skb) * one of multiple shared copies of the buffer. Cloned buffers are * shared data so must not be written to under normal circumstances. */ -static inline int skb_cloned(struct sk_buff *skb) +static inline int skb_cloned(const struct sk_buff *skb) { return skb->cloned && atomic_read(&skb_shinfo(skb)->dataref) != 1; } @@ -369,7 +369,7 @@ static inline int skb_cloned(struct sk_buff *skb) * Returns true if more than one person has a reference to this * buffer. */ -static inline int skb_shared(struct sk_buff *skb) +static inline int skb_shared(const struct sk_buff *skb) { return atomic_read(&skb->users) != 1; } @@ -477,7 +477,7 @@ static inline struct sk_buff *skb_peek_tail(struct sk_buff_head *list_) * * Return the length of an &sk_buff queue. */ -static inline __u32 skb_queue_len(struct sk_buff_head *list_) +static inline __u32 skb_queue_len(const struct sk_buff_head *list_) { return list_->qlen; } diff --git a/include/linux/swap.h b/include/linux/swap.h index 147e5bf40cbf..1f3517e965f3 100644 --- a/include/linux/swap.h +++ b/include/linux/swap.h @@ -3,7 +3,6 @@ #include <linux/config.h> #include <linux/spinlock.h> -#include <linux/kdev_t.h> #include <linux/linkage.h> #include <linux/mmzone.h> #include <linux/list.h> diff --git a/include/linux/tty.h b/include/linux/tty.h index 205e27af55a2..c575197f00b3 100644 --- a/include/linux/tty.h +++ b/include/linux/tty.h @@ -351,7 +351,6 @@ extern void console_init(void); extern int lp_init(void); extern int pty_init(void); -extern void tty_init(void); extern int mxser_init(void); extern int moxa_init(void); extern int ip2_init(void); diff --git a/include/linux/usb.h b/include/linux/usb.h index a20b33d953aa..5575ebfb276d 100644 --- a/include/linux/usb.h +++ b/include/linux/usb.h @@ -80,7 +80,6 @@ struct usb_host_interface { * @act_altsetting: index of current altsetting. this number is always * less than num_altsetting. after the device is configured, each * interface uses its default setting of zero. - * @max_altsetting: the max number of altsettings for this interface. * @driver: the USB driver that is bound to this interface. * @minor: the minor number assigned to this interface, if this * interface is bound to a driver that uses the USB major number. @@ -118,7 +117,6 @@ struct usb_interface { unsigned act_altsetting; /* active alternate setting */ unsigned num_altsetting; /* number of alternate settings */ - unsigned max_altsetting; /* total memory allocated */ struct usb_driver *driver; /* driver */ int minor; /* minor number this interface is bound to */ diff --git a/include/linux/usb_gadget.h b/include/linux/usb_gadget.h index c98a95dbe250..da2d9749baf6 100644 --- a/include/linux/usb_gadget.h +++ b/include/linux/usb_gadget.h @@ -72,9 +72,9 @@ struct usb_request { unsigned length; dma_addr_t dma; - unsigned no_interrupt : 1, - zero : 1, - short_not_ok : 1; + unsigned no_interrupt:1; + unsigned zero:1; + unsigned short_not_ok:1; void (*complete)(struct usb_ep *ep, struct usb_request *req); @@ -122,9 +122,11 @@ struct usb_ep_ops { /** * struct usb_ep - device side representation of USB endpoint * @name:identifier for the endpoint, such as "ep-a" or "ep9in-bulk" + * @ops: Function pointers used to access hardware-specific operations. * @ep_list:the gadget's ep_list holds all of its endpoints - * @maxpacket:the maximum packet size used on this endpoint, as - * configured when the endpoint was enabled. + * @maxpacket:The maximum packet size used on this endpoint. The initial + * value can sometimes be reduced (hardware allowing), according to + * the endpoint descriptor used to configure the endpoint. * @driver_data:for use by the gadget driver. all other fields are * read-only to gadget drivers. * @@ -138,7 +140,7 @@ struct usb_ep { const char *name; const struct usb_ep_ops *ops; struct list_head ep_list; - unsigned maxpacket : 16; + unsigned maxpacket:16; }; /*-------------------------------------------------------------------------*/ @@ -443,18 +445,21 @@ struct usb_gadget_ops { /** * struct usb_gadget - represents a usb slave device + * @ops: Function pointers used to access hardware-specific operations. * @ep0: Endpoint zero, used when reading or writing responses to * driver setup() requests * @ep_list: List of other endpoints supported by the device. * @speed: Speed of current connection to USB host. * @name: Identifies the controller hardware type. Used in diagnostics * and sometimes configuration. + * @dev: Driver model state for this abstract device. * * Gadgets have a mostly-portable "gadget driver" implementing device - * functions, handling all usb configurations and interfaces. They - * also have a hardware-specific driver (accessed through ops vectors), - * which insulates the gadget driver from hardware details and packages - * the hardware endpoints through generic i/o queues. + * functions, handling all usb configurations and interfaces. Gadget + * drivers talk to hardware-specific code indirectly, through ops vectors. + * That insulates the gadget driver from hardware details, and packages + * the hardware endpoints through generic i/o queues. The "usb_gadget" + * and "usb_ep" interfaces provide that insulation from the hardware. * * Except for the driver data, all fields in this structure are * read-only to the gadget driver. That driver data is part of the @@ -469,10 +474,6 @@ struct usb_gadget { struct list_head ep_list; /* of usb_ep */ enum usb_device_speed speed; const char *name; - - /* use this to allocate dma-coherent buffers or set up - * dma mappings. or print diagnostics, etc. - */ struct device dev; }; @@ -576,6 +577,7 @@ usb_gadget_clear_selfpowered (struct usb_gadget *gadget) * Called in a context that permits sleeping. * @suspend: Invoked on USB suspend. May be called in_interrupt. * @resume: Invoked on USB resume. May be called in_interrupt. + * @driver: Driver model state for this driver. * * Devices are disabled till a gadget driver successfully bind()s, which * means the driver will handle setup() requests needed to enumerate (and diff --git a/include/linux/writeback.h b/include/linux/writeback.h index 373e58fee2d4..1424811e1eab 100644 --- a/include/linux/writeback.h +++ b/include/linux/writeback.h @@ -84,7 +84,6 @@ int dirty_writeback_centisecs_handler(struct ctl_table *, int, struct file *, void __user *, size_t *); void page_writeback_init(void); -void balance_dirty_pages(struct address_space *mapping); void balance_dirty_pages_ratelimited(struct address_space *mapping); int pdflush_operation(void (*fn)(unsigned long), unsigned long arg0); int do_writepages(struct address_space *mapping, struct writeback_control *wbc); diff --git a/include/net/llc.h b/include/net/llc.h new file mode 100644 index 000000000000..bf3882be3529 --- /dev/null +++ b/include/net/llc.h @@ -0,0 +1,91 @@ +#ifndef LLC_H +#define LLC_H +/* + * Copyright (c) 1997 by Procom Technology, Inc. + * 2001-2003 by Arnaldo Carvalho de Melo <acme@conectiva.com.br> + * + * This program can be redistributed or modified under the terms of the + * GNU General Public License as published by the Free Software Foundation. + * This program is distributed without any warranty or implied warranty + * of merchantability or fitness for a particular purpose. + * + * See the GNU General Public License for more details. + */ + +#include <linux/if.h> +#include <linux/if_ether.h> +#include <linux/list.h> +#include <linux/spinlock.h> + +struct net_device; +struct packet_type; +struct sk_buff; + +struct llc_addr { + unsigned char lsap; + unsigned char mac[IFHWADDRLEN]; +}; + +#define LLC_SAP_STATE_INACTIVE 1 +#define LLC_SAP_STATE_ACTIVE 2 + +/** + * struct llc_sap - Defines the SAP component + * + * @station - station this sap belongs to + * @state - sap state + * @p_bit - only lowest-order bit used + * @f_bit - only lowest-order bit used + * @laddr - SAP value in this 'lsap' + * @node - entry in station sap_list + * @sk_list - LLC sockets this one manages + */ +struct llc_sap { + unsigned char state; + unsigned char p_bit; + unsigned char f_bit; + int (*rcv_func)(struct sk_buff *skb, + struct net_device *dev, + struct packet_type *pt); + struct llc_addr laddr; + struct list_head node; + struct { + rwlock_t lock; + struct hlist_head list; + } sk_list; +}; + +#define LLC_DEST_INVALID 0 /* Invalid LLC PDU type */ +#define LLC_DEST_SAP 1 /* Type 1 goes here */ +#define LLC_DEST_CONN 2 /* Type 2 goes here */ + +extern struct list_head llc_sap_list; +extern rwlock_t llc_sap_list_lock; +extern unsigned char llc_station_mac_sa[ETH_ALEN]; + +extern int llc_rcv(struct sk_buff *skb, struct net_device *dev, + struct packet_type *pt); + +extern int llc_mac_hdr_init(struct sk_buff *skb, + unsigned char *sa, unsigned char *da); + +extern void llc_add_pack(int type, void (*handler)(struct llc_sap *sap, + struct sk_buff *skb)); +extern void llc_remove_pack(int type); + +extern void llc_set_station_handler(void (*handler)(struct sk_buff *skb)); + +extern struct llc_sap *llc_sap_open(unsigned char lsap, + int (*rcv)(struct sk_buff *skb, + struct net_device *dev, + struct packet_type *pt)); +extern void llc_sap_close(struct llc_sap *sap); + +extern struct llc_sap *llc_sap_find(unsigned char sap_value); + +extern int llc_build_and_send_ui_pkt(struct llc_sap *sap, struct sk_buff *skb, + unsigned char *dmac, unsigned char dsap); + +extern int llc_station_init(void); +extern void llc_station_exit(void); +#endif /* LLC_H */ diff --git a/include/net/llc_actn.h b/include/net/llc_actn.h deleted file mode 100644 index 3619601c4c81..000000000000 --- a/include/net/llc_actn.h +++ /dev/null @@ -1,49 +0,0 @@ -#ifndef LLC_ACTN_H -#define LLC_ACTN_H -/* - * Copyright (c) 1997 by Procom Technology,Inc. - * 2001 by Arnaldo Carvalho de Melo <acme@conectiva.com.br> - * - * This program can be redistributed or modified under the terms of the - * GNU General Public License as published by the Free Software Foundation. - * This program is distributed without any warranty or implied warranty - * of merchantability or fitness for a particular purpose. - * - * See the GNU General Public License for more details. - */ -/* Station component state transition actions */ -#define LLC_STATION_AC_START_ACK_TMR 1 -#define LLC_STATION_AC_SET_RETRY_CNT_0 2 -#define LLC_STATION_AC_INC_RETRY_CNT_BY_1 3 -#define LLC_STATION_AC_SET_XID_R_CNT_0 4 -#define LLC_STATION_AC_INC_XID_R_CNT_BY_1 5 -#define LLC_STATION_AC_SEND_NULL_DSAP_XID_C 6 -#define LLC_STATION_AC_SEND_XID_R 7 -#define LLC_STATION_AC_SEND_TEST_R 8 -#define LLC_STATION_AC_REPORT_STATUS 9 - -/* All station state event action functions look like this */ -typedef int (*llc_station_action_t)(struct llc_station *station, - struct sk_buff *skb); -extern int llc_station_ac_start_ack_timer(struct llc_station *station, - struct sk_buff *skb); -extern int llc_station_ac_set_retry_cnt_0(struct llc_station *station, - struct sk_buff *skb); -extern int llc_station_ac_inc_retry_cnt_by_1(struct llc_station *station, - struct sk_buff *skb); -extern int llc_station_ac_set_xid_r_cnt_0(struct llc_station *station, - struct sk_buff *skb); -extern int llc_station_ac_inc_xid_r_cnt_by_1(struct llc_station *station, - struct sk_buff *skb); -extern int llc_station_ac_send_null_dsap_xid_c(struct llc_station *station, - struct sk_buff *skb); -extern int llc_station_ac_send_xid_r(struct llc_station *station, - struct sk_buff *skb); -extern int llc_station_ac_send_test_r(struct llc_station *station, - struct sk_buff *skb); -extern int llc_station_ac_report_status(struct llc_station *station, - struct sk_buff *skb); -extern int llc_station_ac_report_status(struct llc_station *station, - struct sk_buff *skb); -extern void llc_station_ack_tmr_cb(unsigned long timeout_data); -#endif /* LLC_ACTN_H */ diff --git a/include/net/llc_conn.h b/include/net/llc_conn.h index 3cefd5ce2642..06fb01bccdbf 100644 --- a/include/net/llc_conn.h +++ b/include/net/llc_conn.h @@ -15,6 +15,14 @@ #include <net/llc_if.h> #include <linux/llc.h> +#define LLC_EVENT 1 +#define LLC_PACKET 2 + +#define LLC_P_TIME 2 +#define LLC_ACK_TIME 1 +#define LLC_REJ_TIME 3 +#define LLC_BUSY_TIME 3 + struct llc_timer { struct timer_list timer; u16 expire; /* timer expire time */ @@ -69,6 +77,16 @@ struct llc_opt { #define llc_sk(__sk) ((struct llc_opt *)(__sk)->sk_protinfo) +static __inline__ void llc_set_backlog_type(struct sk_buff *skb, char type) +{ + skb->cb[sizeof(skb->cb) - 1] = type; +} + +static __inline__ char llc_backlog_type(struct sk_buff *skb) +{ + return skb->cb[sizeof(skb->cb) - 1]; +} + extern struct sock *llc_sk_alloc(int family, int priority); extern void llc_sk_free(struct sock *sk); @@ -90,9 +108,10 @@ extern struct sock *llc_lookup_established(struct llc_sap *sap, struct llc_addr *laddr); extern struct sock *llc_lookup_listener(struct llc_sap *sap, struct llc_addr *laddr); -extern struct sock *llc_lookup_dgram(struct llc_sap *sap, - struct llc_addr *laddr); -extern void llc_save_primitive(struct sk_buff* skb, u8 prim); +extern void llc_sap_add_socket(struct llc_sap *sap, struct sock *sk); +extern void llc_sap_remove_socket(struct llc_sap *sap, struct sock *sk); + extern u8 llc_data_accept_state(u8 state); extern void llc_build_offset_table(void); +extern int llc_release_sockets(struct llc_sap *sap); #endif /* LLC_CONN_H */ diff --git a/include/net/llc_evnt.h b/include/net/llc_evnt.h deleted file mode 100644 index 429adcb480e3..000000000000 --- a/include/net/llc_evnt.h +++ /dev/null @@ -1,70 +0,0 @@ -#ifndef LLC_EVNT_H -#define LLC_EVNT_H -/* - * Copyright (c) 1997 by Procom Technology,Inc. - * 2001 by Arnaldo Carvalho de Melo <acme@conectiva.com.br> - * - * This program can be redistributed or modified under the terms of the - * GNU General Public License as published by the Free Software Foundation. - * This program is distributed without any warranty or implied warranty - * of merchantability or fitness for a particular purpose. - * - * See the GNU General Public License for more details. - */ -/* Station component state transition events */ -/* Types of events (possible values in 'ev->type') */ -#define LLC_STATION_EV_TYPE_SIMPLE 1 -#define LLC_STATION_EV_TYPE_CONDITION 2 -#define LLC_STATION_EV_TYPE_PRIM 3 -#define LLC_STATION_EV_TYPE_PDU 4 /* command/response PDU */ -#define LLC_STATION_EV_TYPE_ACK_TMR 5 -#define LLC_STATION_EV_TYPE_RPT_STATUS 6 - -/* Events */ -#define LLC_STATION_EV_ENABLE_WITH_DUP_ADDR_CHECK 1 -#define LLC_STATION_EV_ENABLE_WITHOUT_DUP_ADDR_CHECK 2 -#define LLC_STATION_EV_ACK_TMR_EXP_LT_RETRY_CNT_MAX_RETRY 3 -#define LLC_STATION_EV_ACK_TMR_EXP_EQ_RETRY_CNT_MAX_RETRY 4 -#define LLC_STATION_EV_RX_NULL_DSAP_XID_C 5 -#define LLC_STATION_EV_RX_NULL_DSAP_0_XID_R_XID_R_CNT_EQ 6 -#define LLC_STATION_EV_RX_NULL_DSAP_1_XID_R_XID_R_CNT_EQ 7 -#define LLC_STATION_EV_RX_NULL_DSAP_TEST_C 8 -#define LLC_STATION_EV_DISABLE_REQ 9 - -struct llc_station_state_ev { - u8 type; - u8 prim; - u8 prim_type; - u8 reason; - struct list_head node; /* node in station->ev_q.list */ -}; - -static __inline__ struct llc_station_state_ev * - llc_station_ev(struct sk_buff *skb) -{ - return (struct llc_station_state_ev *)skb->cb; -} - -typedef int (*llc_station_ev_t)(struct llc_station *station, - struct sk_buff *skb); - -extern int llc_stat_ev_enable_with_dup_addr_check(struct llc_station *station, - struct sk_buff *skb); -extern int llc_stat_ev_enable_without_dup_addr_check(struct llc_station *station, - struct sk_buff *skb); -extern int llc_stat_ev_ack_tmr_exp_lt_retry_cnt_max_retry(struct llc_station * - station, - struct sk_buff *skb); -extern int llc_stat_ev_ack_tmr_exp_eq_retry_cnt_max_retry(struct llc_station *station, - struct sk_buff *skb); -extern int llc_stat_ev_rx_null_dsap_xid_c(struct llc_station *station, - struct sk_buff *skb); -extern int llc_stat_ev_rx_null_dsap_0_xid_r_xid_r_cnt_eq(struct llc_station *station, - struct sk_buff *skb); -extern int llc_stat_ev_rx_null_dsap_1_xid_r_xid_r_cnt_eq(struct llc_station *station, - struct sk_buff *skb); -extern int llc_stat_ev_rx_null_dsap_test_c(struct llc_station *station, - struct sk_buff *skb); -extern int llc_stat_ev_disable_req(struct llc_station *station, - struct sk_buff *skb); -#endif /* LLC_EVNT_H */ diff --git a/include/net/llc_if.h b/include/net/llc_if.h index a72591707e20..090eaa0d71f9 100644 --- a/include/net/llc_if.h +++ b/include/net/llc_if.h @@ -16,6 +16,7 @@ #include <linux/if.h> #include <linux/if_arp.h> #include <linux/llc.h> +#include <net/llc.h> #define LLC_DATAUNIT_PRIM 1 #define LLC_CONN_PRIM 2 @@ -60,29 +61,41 @@ #define LLC_STATUS_CONFLICT 7 /* disconnect conn */ #define LLC_STATUS_RESET_DONE 8 /* */ -/* Structures and types */ -/* SAP/MAC Address pair */ -struct llc_addr { - u8 lsap; - u8 mac[IFHWADDRLEN]; -}; +extern u8 llc_mac_null_var[IFHWADDRLEN]; -struct llc_sap; +/** + * llc_mac_null - determines if a address is a null mac address + * @mac: Mac address to test if null. + * + * Determines if a given address is a null mac address. Returns 0 if the + * address is not a null mac, 1 if the address is a null mac. + */ +static __inline__ int llc_mac_null(u8 *mac) +{ + return !memcmp(mac, llc_mac_null_var, IFHWADDRLEN); +} + +static __inline__ int llc_addrany(struct llc_addr *addr) +{ + return llc_mac_null(addr->mac) && !addr->lsap; +} -extern struct llc_sap *llc_sap_open(u8 lsap, - int (*func)(struct sk_buff *skb, - struct net_device *dev, - struct packet_type *pt)); -extern void llc_sap_close(struct llc_sap *sap); +/** + * llc_mac_match - determines if two mac addresses are the same + * @mac1: First mac address to compare. + * @mac2: Second mac address to compare. + * + * Determines if two given mac address are the same. Returns 0 if there + * is not a complete match up to len, 1 if a complete match up to len is + * found. + */ +static __inline__ int llc_mac_match(u8 *mac1, u8 *mac2) +{ + return !memcmp(mac1, mac2, IFHWADDRLEN); +} extern int llc_establish_connection(struct sock *sk, u8 *lmac, u8 *dmac, u8 dsap); extern int llc_build_and_send_pkt(struct sock *sk, struct sk_buff *skb); -extern void llc_build_and_send_ui_pkt(struct llc_sap *sap, struct sk_buff *skb, - u8 *dmac, u8 dsap); -extern void llc_build_and_send_xid_pkt(struct llc_sap *sap, struct sk_buff *skb, - u8 *dmac, u8 dsap); -extern void llc_build_and_send_test_pkt(struct llc_sap *sap, struct sk_buff *skb, - u8 *dmac, u8 dsap); extern int llc_send_disc(struct sock *sk); #endif /* LLC_IF_H */ diff --git a/include/net/llc_mac.h b/include/net/llc_mac.h deleted file mode 100644 index ded7c830b8a8..000000000000 --- a/include/net/llc_mac.h +++ /dev/null @@ -1,61 +0,0 @@ -#ifndef LLC_MAC_H -#define LLC_MAC_H -/* - * Copyright (c) 1997 by Procom Technology, Inc. - * 2001, 2002 by Arnaldo Carvalho de Melo <acme@conectiva.com.br> - * - * This program can be redistributed or modified under the terms of the - * GNU General Public License as published by the Free Software Foundation. - * This program is distributed without any warranty or implied warranty - * of merchantability or fitness for a particular purpose. - * - * See the GNU General Public License for more details. - */ -extern int llc_rcv(struct sk_buff *skb, struct net_device *dev, - struct packet_type *pt); -extern u16 lan_hdrs_init(struct sk_buff *skb, u8 *sa, u8 *da); -extern int llc_conn_rcv(struct sock *sk, struct sk_buff *skb); - -static __inline__ void llc_set_backlog_type(struct sk_buff *skb, char type) -{ - skb->cb[sizeof(skb->cb) - 1] = type; -} - -static __inline__ char llc_backlog_type(struct sk_buff *skb) -{ - return skb->cb[sizeof(skb->cb) - 1]; -} - -extern u8 llc_mac_null_var[IFHWADDRLEN]; - -/** - * llc_mac_null - determines if a address is a null mac address - * @mac: Mac address to test if null. - * - * Determines if a given address is a null mac address. Returns 0 if the - * address is not a null mac, 1 if the address is a null mac. - */ -static __inline__ int llc_mac_null(u8 *mac) -{ - return !memcmp(mac, llc_mac_null_var, IFHWADDRLEN); -} - -static __inline__ int llc_addrany(struct llc_addr *addr) -{ - return llc_mac_null(addr->mac) && !addr->lsap; -} - -/** - * llc_mac_match - determines if two mac addresses are the same - * @mac1: First mac address to compare. - * @mac2: Second mac address to compare. - * - * Determines if two given mac address are the same. Returns 0 if there - * is not a complete match up to len, 1 if a complete match up to len is - * found. - */ -static __inline__ int llc_mac_match(u8 *mac1, u8 *mac2) -{ - return !memcmp(mac1, mac2, IFHWADDRLEN); -} -#endif /* LLC_MAC_H */ diff --git a/include/net/llc_main.h b/include/net/llc_main.h deleted file mode 100644 index 0e0d39742a2e..000000000000 --- a/include/net/llc_main.h +++ /dev/null @@ -1,67 +0,0 @@ -#ifndef LLC_MAIN_H -#define LLC_MAIN_H -/* - * Copyright (c) 1997 by Procom Technology, Inc. - * 2001 by Arnaldo Carvalho de Melo <acme@conectiva.com.br> - * - * This program can be redistributed or modified under the terms of the - * GNU General Public License as published by the Free Software Foundation. - * This program is distributed without any warranty or implied warranty - * of merchantability or fitness for a particular purpose. - * - * See the GNU General Public License for more details. - */ -#define LLC_EVENT 1 -#define LLC_PACKET 2 -#define LLC_TYPE_1 1 -#define LLC_TYPE_2 2 -#define LLC_P_TIME 2 -#define LLC_ACK_TIME 1 -#define LLC_REJ_TIME 3 -#define LLC_BUSY_TIME 3 -#define LLC_DEST_INVALID 0 /* Invalid LLC PDU type */ -#define LLC_DEST_SAP 1 /* Type 1 goes here */ -#define LLC_DEST_CONN 2 /* Type 2 goes here */ - -/** - * struct llc_station - LLC station component - * - * SAP and connection resource manager, one per adapter. - * - * @state - state of station - * @xid_r_count - XID response PDU counter - * @mac_sa - MAC source address - * @sap_list - list of related SAPs - * @ev_q - events entering state mach. - * @mac_pdu_q - PDUs ready to send to MAC - */ -struct llc_station { - u8 state; - u8 xid_r_count; - struct timer_list ack_timer; - u8 retry_count; - u8 maximum_retry; - u8 mac_sa[6]; - struct { - rwlock_t lock; - struct list_head list; - } sap_list; - struct { - struct sk_buff_head list; - spinlock_t lock; - } ev_q; - struct sk_buff_head mac_pdu_q; -}; - -extern struct llc_sap *llc_sap_alloc(void); -extern void llc_sap_save(struct llc_sap *sap); -extern void llc_free_sap(struct llc_sap *sap); -extern struct llc_sap *llc_sap_find(u8 lsap); -extern void llc_station_state_process(struct llc_station *station, - struct sk_buff *skb); -extern void llc_station_send_pdu(struct llc_station *station, - struct sk_buff *skb); -extern struct sk_buff *llc_alloc_frame(void); - -extern struct llc_station llc_main_station; -#endif /* LLC_MAIN_H */ diff --git a/include/net/llc_pdu.h b/include/net/llc_pdu.h index 235e6c0bc17e..644f9edc2bae 100644 --- a/include/net/llc_pdu.h +++ b/include/net/llc_pdu.h @@ -2,7 +2,7 @@ #define LLC_PDU_H /* * Copyright (c) 1997 by Procom Technology,Inc. - * 2001 by Arnaldo Carvalho de Melo <acme@conectiva.com.br> + * 2001-2003 by Arnaldo Carvalho de Melo <acme@conectiva.com.br> * * This program can be redistributed or modified under the terms of the * GNU General Public License as published by the Free Software Foundation. @@ -11,7 +11,10 @@ * * See the GNU General Public License for more details. */ -/* LLC PDU structure */ + +#include <linux/if_ether.h> +#include <linux/if_tr.h> + /* Lengths of frame formats */ #define LLC_PDU_LEN_I 4 /* header and 2 control bytes */ #define LLC_PDU_LEN_S 4 @@ -198,7 +201,7 @@ struct llc_pdu_sn { u8 ctrl_2; }; -static __inline__ struct llc_pdu_sn *llc_pdu_sn_hdr(struct sk_buff *skb) +static inline struct llc_pdu_sn *llc_pdu_sn_hdr(struct sk_buff *skb) { return (struct llc_pdu_sn *)skb->nh.raw; } @@ -210,16 +213,146 @@ struct llc_pdu_un { u8 ctrl_1; }; -static __inline__ struct llc_pdu_un *llc_pdu_un_hdr(struct sk_buff *skb) +static inline struct llc_pdu_un *llc_pdu_un_hdr(struct sk_buff *skb) { return (struct llc_pdu_un *)skb->nh.raw; } -static __inline__ void *llc_set_pdu_hdr(struct sk_buff *skb, void *ptr) +static inline void *llc_set_pdu_hdr(struct sk_buff *skb, void *ptr) { return skb->nh.raw = ptr; } +/** + * llc_pdu_header_init - initializes pdu header + * @skb: input skb that header must be set into it. + * @type: type of PDU (U, I or S). + * @ssap: source sap. + * @dsap: destination sap. + * @cr: command/response bit (0 or 1). + * + * This function sets DSAP, SSAP and command/Response bit in LLC header. + */ +static inline void llc_pdu_header_init(struct sk_buff *skb, u8 type, + u8 ssap, u8 dsap, u8 cr) +{ + const int hlen = type == LLC_PDU_TYPE_U ? 3 : 4; + struct llc_pdu_un *pdu = llc_set_pdu_hdr(skb, skb_push(skb, hlen)); + pdu->dsap = dsap; + pdu->ssap = ssap; + pdu->ssap |= cr; +} + +/** + * llc_pdu_decode_sa - extracs source address (MAC) of input frame + * @skb: input skb that source address must be extracted from it. + * @sa: pointer to source address (6 byte array). + * + * This function extracts source address(MAC) of input frame. + */ +static inline void llc_pdu_decode_sa(struct sk_buff *skb, u8 *sa) +{ + if (skb->protocol == ntohs(ETH_P_802_2)) + memcpy(sa, ((struct ethhdr *)skb->mac.raw)->h_source, ETH_ALEN); + else if (skb->protocol == ntohs(ETH_P_TR_802_2)) + memcpy(sa, ((struct trh_hdr *)skb->mac.raw)->saddr, ETH_ALEN); +} + +/** + * llc_pdu_decode_da - extracts dest address of input frame + * @skb: input skb that destination address must be extracted from it + * @sa: pointer to destination address (6 byte array). + * + * This function extracts destination address(MAC) of input frame. + */ +static inline void llc_pdu_decode_da(struct sk_buff *skb, u8 *da) +{ + if (skb->protocol == ntohs(ETH_P_802_2)) + memcpy(da, ((struct ethhdr *)skb->mac.raw)->h_dest, ETH_ALEN); + else if (skb->protocol == ntohs(ETH_P_TR_802_2)) + memcpy(da, ((struct trh_hdr *)skb->mac.raw)->daddr, ETH_ALEN); +} + +/** + * llc_pdu_decode_ssap - extracts source SAP of input frame + * @skb: input skb that source SAP must be extracted from it. + * @ssap: source SAP (output argument). + * + * This function extracts source SAP of input frame. Right bit of SSAP is + * command/response bit. + */ +static inline void llc_pdu_decode_ssap(struct sk_buff *skb, u8 *ssap) +{ + *ssap = llc_pdu_un_hdr(skb)->ssap & 0xFE; +} + +/** + * llc_pdu_decode_dsap - extracts dest SAP of input frame + * @skb: input skb that destination SAP must be extracted from it. + * @dsap: destination SAP (output argument). + * + * This function extracts destination SAP of input frame. right bit of + * DSAP designates individual/group SAP. + */ +static inline void llc_pdu_decode_dsap(struct sk_buff *skb, u8 *dsap) +{ + *dsap = llc_pdu_un_hdr(skb)->dsap & 0xFE; +} + +/** + * llc_pdu_init_as_ui_cmd - sets LLC header as UI PDU + * @skb: input skb that header must be set into it. + * + * This function sets third byte of LLC header as a UI PDU. + */ +static inline void llc_pdu_init_as_ui_cmd(struct sk_buff *skb) +{ + struct llc_pdu_un *pdu = llc_pdu_un_hdr(skb); + + pdu->ctrl_1 = LLC_PDU_TYPE_U; + pdu->ctrl_1 |= LLC_1_PDU_CMD_UI; +} + +/** + * llc_pdu_init_as_test_cmd - sets PDU as TEST + * @skb - Address of the skb to build + * + * Sets a PDU as TEST + */ +static inline void llc_pdu_init_as_test_cmd(struct sk_buff *skb) +{ + struct llc_pdu_un *pdu = llc_pdu_un_hdr(skb); + + pdu->ctrl_1 = LLC_PDU_TYPE_U; + pdu->ctrl_1 |= LLC_1_PDU_CMD_TEST; + pdu->ctrl_1 |= LLC_U_PF_BIT_MASK; +} + +/** + * llc_pdu_init_as_test_rsp - build TEST response PDU + * @skb: Address of the skb to build + * @ev_skb: The received TEST command PDU frame + * + * Builds a pdu frame as a TEST response. + */ +static inline void llc_pdu_init_as_test_rsp(struct sk_buff *skb, + struct sk_buff *ev_skb) +{ + struct llc_pdu_un *pdu = llc_pdu_un_hdr(skb); + + pdu->ctrl_1 = LLC_PDU_TYPE_U; + pdu->ctrl_1 |= LLC_1_PDU_CMD_TEST; + pdu->ctrl_1 |= LLC_U_PF_BIT_MASK; + if (ev_skb->protocol == ntohs(ETH_P_802_2)) { + struct llc_pdu_un *ev_pdu = llc_pdu_un_hdr(ev_skb); + int dsize; + + dsize = ntohs(((struct ethhdr *)ev_skb->mac.raw)->h_proto) - 3; + memcpy(((u8 *)pdu) + 3, ((u8 *)ev_pdu) + 3, dsize); + skb_put(skb, dsize); + } +} + /* LLC Type 1 XID command/response information fields format */ struct llc_xid_info { u8 fmt_id; /* always 0x18 for LLC */ @@ -227,6 +360,54 @@ struct llc_xid_info { u8 rw; /* sender receive window */ }; +/** + * llc_pdu_init_as_xid_cmd - sets bytes 3, 4 & 5 of LLC header as XID + * @skb: input skb that header must be set into it. + * + * This function sets third,fourth,fifth and sixth bytes of LLC header as + * a XID PDU. + */ +static inline void llc_pdu_init_as_xid_cmd(struct sk_buff *skb, + u8 svcs_supported, u8 rx_window) +{ + struct llc_xid_info *xid_info; + struct llc_pdu_un *pdu = llc_pdu_un_hdr(skb); + + pdu->ctrl_1 = LLC_PDU_TYPE_U; + pdu->ctrl_1 |= LLC_1_PDU_CMD_XID; + pdu->ctrl_1 |= LLC_U_PF_BIT_MASK; + xid_info = (struct llc_xid_info *)(((u8 *)&pdu->ctrl_1) + 1); + xid_info->fmt_id = LLC_XID_FMT_ID; /* 0x81 */ + xid_info->type = svcs_supported; + xid_info->rw = rx_window << 1; /* size of receive window */ + skb_put(skb, 3); +} + +/** + * llc_pdu_init_as_xid_rsp - builds XID response PDU + * @skb: Address of the skb to build + * @svcs_supported: The class of the LLC (I or II) + * @rx_window: The size of the receive window of the LLC + * + * Builds a pdu frame as an XID response. + */ +static inline void llc_pdu_init_as_xid_rsp(struct sk_buff *skb, + u8 svcs_supported, u8 rx_window) +{ + struct llc_xid_info *xid_info; + struct llc_pdu_un *pdu = llc_pdu_un_hdr(skb); + + pdu->ctrl_1 = LLC_PDU_TYPE_U; + pdu->ctrl_1 |= LLC_1_PDU_CMD_XID; + pdu->ctrl_1 |= LLC_U_PF_BIT_MASK; + + xid_info = (struct llc_xid_info *)(((u8 *)&pdu->ctrl_1) + 1); + xid_info->fmt_id = LLC_XID_FMT_ID; + xid_info->type = svcs_supported; + xid_info->rw = rx_window << 1; + skb_put(skb, 3); +} + /* LLC Type 2 FRMR response information field format */ struct llc_frmr_info { u16 rej_pdu_ctrl; /* bits 1-8 if U-PDU */ @@ -239,17 +420,6 @@ extern void llc_pdu_set_cmd_rsp(struct sk_buff *skb, u8 type); extern void llc_pdu_set_pf_bit(struct sk_buff *skb, u8 bit_value); extern void llc_pdu_decode_pf_bit(struct sk_buff *skb, u8 *pf_bit); extern void llc_pdu_decode_cr_bit(struct sk_buff *skb, u8 *cr_bit); -extern void llc_pdu_decode_sa(struct sk_buff *skb, u8 *sa); -extern void llc_pdu_decode_da(struct sk_buff *skb, u8 *ds); -extern void llc_pdu_decode_dsap(struct sk_buff *skb, u8 *dsap); -extern void llc_pdu_decode_ssap(struct sk_buff *skb, u8 *ssap); -extern void llc_decode_pdu_type(struct sk_buff *skb, u8 *destination); -extern void llc_pdu_header_init(struct sk_buff *skb, u8 pdu_type, u8 ssap, - u8 dsap, u8 cr); -extern void llc_pdu_init_as_ui_cmd(struct sk_buff *skb); -extern void llc_pdu_init_as_xid_cmd(struct sk_buff *skb, u8 svcs_supported, - u8 rx_window); -extern void llc_pdu_init_as_test_cmd(struct sk_buff *skb); extern void llc_pdu_init_as_disc_cmd(struct sk_buff *skb, u8 p_bit); extern void llc_pdu_init_as_i_cmd(struct sk_buff *skb, u8 p_bit, u8 ns, u8 nr); extern void llc_pdu_init_as_rej_cmd(struct sk_buff *skb, u8 p_bit, u8 nr); @@ -257,10 +427,6 @@ extern void llc_pdu_init_as_rnr_cmd(struct sk_buff *skb, u8 p_bit, u8 nr); extern void llc_pdu_init_as_rr_cmd(struct sk_buff *skb, u8 p_bit, u8 nr); extern void llc_pdu_init_as_sabme_cmd(struct sk_buff *skb, u8 p_bit); extern void llc_pdu_init_as_dm_rsp(struct sk_buff *skb, u8 f_bit); -extern void llc_pdu_init_as_xid_rsp(struct sk_buff *skb, u8 svcs_supported, - u8 rx_window); -extern void llc_pdu_init_as_test_rsp(struct sk_buff *skb, - struct sk_buff *ev_skb); extern void llc_pdu_init_as_frmr_rsp(struct sk_buff *skb, struct llc_pdu_sn *prev_pdu, u8 f_bit, u8 vs, u8 vr, u8 vzyxw); diff --git a/include/net/llc_s_st.h b/include/net/llc_s_st.h index 525415ebae92..567c681f1f3e 100644 --- a/include/net/llc_s_st.h +++ b/include/net/llc_s_st.h @@ -11,10 +11,7 @@ * * See the GNU General Public License for more details. */ -/* Defines SAP component states */ -#define LLC_SAP_STATE_INACTIVE 1 -#define LLC_SAP_STATE_ACTIVE 2 #define LLC_NR_SAP_STATES 2 /* size of state table */ /* structures and types */ diff --git a/include/net/llc_sap.h b/include/net/llc_sap.h index b46c85389388..dc60acce8e55 100644 --- a/include/net/llc_sap.h +++ b/include/net/llc_sap.h @@ -2,7 +2,7 @@ #define LLC_SAP_H /* * Copyright (c) 1997 by Procom Technology,Inc. - * 2001 by Arnaldo Carvalho de Melo <acme@conectiva.com.br> + * 2001-2003 by Arnaldo Carvalho de Melo <acme@conectiva.com.br> * * This program can be redistributed or modified under the terms of the * GNU General Public License as published by the Free Software Foundation. @@ -11,37 +11,20 @@ * * See the GNU General Public License for more details. */ -#include <linux/skbuff.h> -#include <net/llc_if.h> -/** - * struct llc_sap - Defines the SAP component - * - * @station - station this sap belongs to - * @state - sap state - * @p_bit - only lowest-order bit used - * @f_bit - only lowest-order bit used - * @laddr - SAP value in this 'lsap' - * @node - entry in station sap_list - * @sk_list - LLC sockets this one manages - */ -struct llc_sap { - struct llc_station *station; - u8 state; - u8 p_bit; - u8 f_bit; - int (*rcv_func)(struct sk_buff *skb, - struct net_device *dev, - struct packet_type *pt); - struct llc_addr laddr; - struct list_head node; - struct { - rwlock_t lock; - struct hlist_head list; - } sk_list; -}; +struct llc_sap; +struct sk_buff; -extern void llc_sap_assign_sock(struct llc_sap *sap, struct sock *sk); -extern void llc_sap_unassign_sock(struct llc_sap *sap, struct sock *sk); extern void llc_sap_state_process(struct llc_sap *sap, struct sk_buff *skb); extern void llc_sap_rtn_pdu(struct llc_sap *sap, struct sk_buff *skb); +extern void llc_save_primitive(struct sk_buff* skb, unsigned char prim); +extern struct sk_buff *llc_alloc_frame(void); + +extern void llc_build_and_send_test_pkt(struct llc_sap *sap, + struct sk_buff *skb, + unsigned char *dmac, + unsigned char dsap); +extern void llc_build_and_send_xid_pkt(struct llc_sap *sap, + struct sk_buff *skb, + unsigned char *dmac, + unsigned char dsap); #endif /* LLC_SAP_H */ diff --git a/include/net/llc_stat.h b/include/net/llc_stat.h deleted file mode 100644 index f8d0bb0a9c75..000000000000 --- a/include/net/llc_stat.h +++ /dev/null @@ -1,35 +0,0 @@ -#ifndef LLC_STAT_H -#define LLC_STAT_H -/* - * Copyright (c) 1997 by Procom Technology,Inc. - * 2001 by Arnaldo Carvalho de Melo <acme@conectiva.com.br> - * - * This program can be redistributed or modified under the terms of the - * GNU General Public License as published by the Free Software Foundation. - * This program is distributed without any warranty or implied warranty - * of merchantability or fitness for a particular purpose. - * - * See the GNU General Public License for more details. - */ -/* Station component state table */ -/* Station component states */ -#define LLC_STATION_STATE_DOWN 1 /* initial state */ -#define LLC_STATION_STATE_DUP_ADDR_CHK 2 -#define LLC_STATION_STATE_UP 3 - -#define LLC_NBR_STATION_STATES 3 /* size of state table */ - -/* Station component state table structure */ -struct llc_station_state_trans { - llc_station_ev_t ev; - u8 next_state; - llc_station_action_t *ev_actions; -}; - -struct llc_station_state { - u8 curr_state; - struct llc_station_state_trans **transitions; -}; - -extern struct llc_station_state llc_station_state_table[LLC_NBR_STATION_STATES]; -#endif /* LLC_STAT_H */ diff --git a/include/net/syncppp.h b/include/net/syncppp.h index 07214226b4e3..f2032606419e 100644 --- a/include/net/syncppp.h +++ b/include/net/syncppp.h @@ -57,8 +57,11 @@ struct ppp_device struct sppp sppp; /* Synchronous PPP */ }; -#define sppp_of(dev) \ - (&((struct ppp_device *)(*(unsigned long *)((dev)->priv)))->sppp) +static inline struct sppp *sppp_of(struct net_device *dev) +{ + struct ppp_device *ppp = dev->priv; + return &ppp->sppp; +} #define PP_KEEPALIVE 0x01 /* use keepalive protocol */ #define PP_CISCO 0x02 /* use Cisco protocol instead of PPP */ |