diff options
Diffstat (limited to 'include')
123 files changed, 3464 insertions, 1184 deletions
diff --git a/include/asm-alpha/cacheflush.h b/include/asm-alpha/cacheflush.h new file mode 100644 index 000000000000..f04d7579fde7 --- /dev/null +++ b/include/asm-alpha/cacheflush.h @@ -0,0 +1,64 @@ +#ifndef _ALPHA_CACHEFLUSH_H +#define _ALPHA_CACHEFLUSH_H + +#include <linux/config.h> +#include <linux/mm.h> + +/* Caches aren't brain-dead on the Alpha. */ +#define flush_cache_all() do { } while (0) +#define flush_cache_mm(mm) do { } while (0) +#define flush_cache_range(vma, start, end) do { } while (0) +#define flush_cache_page(vma, vmaddr) do { } while (0) +#define flush_page_to_ram(page) do { } while (0) +#define flush_dcache_page(page) do { } while (0) + +/* Note that the following two definitions are _highly_ dependent + on the contexts in which they are used in the kernel. I personally + think it is criminal how loosely defined these macros are. */ + +/* We need to flush the kernel's icache after loading modules. The + only other use of this macro is in load_aout_interp which is not + used on Alpha. + + Note that this definition should *not* be used for userspace + icache flushing. While functional, it is _way_ overkill. The + icache is tagged with ASNs and it suffices to allocate a new ASN + for the process. */ +#ifndef CONFIG_SMP +#define flush_icache_range(start, end) imb() +#else +#define flush_icache_range(start, end) smp_imb() +extern void smp_imb(void); +#endif + +/* We need to flush the userspace icache after setting breakpoints in + ptrace. + + Instead of indiscriminately using imb, take advantage of the fact + that icache entries are tagged with the ASN and load a new mm context. */ +/* ??? Ought to use this in arch/alpha/kernel/signal.c too. */ + +#ifndef CONFIG_SMP +extern void __load_new_mm_context(struct mm_struct *); +static inline void +flush_icache_user_range(struct vm_area_struct *vma, struct page *page, + unsigned long addr, int len) +{ + if (vma->vm_flags & VM_EXEC) { + struct mm_struct *mm = vma->vm_mm; + if (current->active_mm == mm) + __load_new_mm_context(mm); + else + mm->context[smp_processor_id()] = 0; + } +} +#else +extern void flush_icache_user_range(struct vm_area_struct *vma, + struct page *page, unsigned long addr, int len); +#endif + +/* This is used only in do_no_page and do_swap_page. */ +#define flush_icache_page(vma, page) \ + flush_icache_user_range((vma), (page), 0, 0) + +#endif /* _ALPHA_CACHEFLUSH_H */ diff --git a/include/asm-alpha/pgalloc.h b/include/asm-alpha/pgalloc.h index 0fbeaa56610d..445dc28b827a 100644 --- a/include/asm-alpha/pgalloc.h +++ b/include/asm-alpha/pgalloc.h @@ -3,228 +3,6 @@ #include <linux/config.h> -#ifndef __EXTERN_INLINE -#define __EXTERN_INLINE extern inline -#define __MMU_EXTERN_INLINE -#endif - -extern void __load_new_mm_context(struct mm_struct *); - - -/* Caches aren't brain-dead on the Alpha. */ -#define flush_cache_all() do { } while (0) -#define flush_cache_mm(mm) do { } while (0) -#define flush_cache_range(vma, start, end) do { } while (0) -#define flush_cache_page(vma, vmaddr) do { } while (0) -#define flush_page_to_ram(page) do { } while (0) -#define flush_dcache_page(page) do { } while (0) - -/* Note that the following two definitions are _highly_ dependent - on the contexts in which they are used in the kernel. I personally - think it is criminal how loosely defined these macros are. */ - -/* We need to flush the kernel's icache after loading modules. The - only other use of this macro is in load_aout_interp which is not - used on Alpha. - - Note that this definition should *not* be used for userspace - icache flushing. While functional, it is _way_ overkill. The - icache is tagged with ASNs and it suffices to allocate a new ASN - for the process. */ -#ifndef CONFIG_SMP -#define flush_icache_range(start, end) imb() -#else -#define flush_icache_range(start, end) smp_imb() -extern void smp_imb(void); -#endif - - -/* - * Use a few helper functions to hide the ugly broken ASN - * numbers on early Alphas (ev4 and ev45) - */ - -__EXTERN_INLINE void -ev4_flush_tlb_current(struct mm_struct *mm) -{ - __load_new_mm_context(mm); - tbiap(); -} - -__EXTERN_INLINE void -ev5_flush_tlb_current(struct mm_struct *mm) -{ - __load_new_mm_context(mm); -} - -static inline void -flush_tlb_other(struct mm_struct *mm) -{ - long * mmc = &mm->context[smp_processor_id()]; - /* - * Check it's not zero first to avoid cacheline ping pong when - * possible. - */ - if (*mmc) - *mmc = 0; -} - -/* We need to flush the userspace icache after setting breakpoints in - ptrace. - - Instead of indiscriminately using imb, take advantage of the fact - that icache entries are tagged with the ASN and load a new mm context. */ -/* ??? Ought to use this in arch/alpha/kernel/signal.c too. */ - -#ifndef CONFIG_SMP -static inline void -flush_icache_user_range(struct vm_area_struct *vma, struct page *page, - unsigned long addr, int len) -{ - if (vma->vm_flags & VM_EXEC) { - struct mm_struct *mm = vma->vm_mm; - if (current->active_mm == mm) - __load_new_mm_context(mm); - else - mm->context[smp_processor_id()] = 0; - } -} -#else -extern void flush_icache_user_range(struct vm_area_struct *vma, - struct page *page, unsigned long addr, int len); -#endif - -/* this is used only in do_no_page and do_swap_page */ -#define flush_icache_page(vma, page) flush_icache_user_range((vma), (page), 0, 0) - -/* - * Flush just one page in the current TLB set. - * We need to be very careful about the icache here, there - * is no way to invalidate a specific icache page.. - */ - -__EXTERN_INLINE void -ev4_flush_tlb_current_page(struct mm_struct * mm, - struct vm_area_struct *vma, - unsigned long addr) -{ - int tbi_flag = 2; - if (vma->vm_flags & VM_EXEC) { - __load_new_mm_context(mm); - tbi_flag = 3; - } - tbi(tbi_flag, addr); -} - -__EXTERN_INLINE void -ev5_flush_tlb_current_page(struct mm_struct * mm, - struct vm_area_struct *vma, - unsigned long addr) -{ - if (vma->vm_flags & VM_EXEC) - __load_new_mm_context(mm); - else - tbi(2, addr); -} - - -#ifdef CONFIG_ALPHA_GENERIC -# define flush_tlb_current alpha_mv.mv_flush_tlb_current -# define flush_tlb_current_page alpha_mv.mv_flush_tlb_current_page -#else -# ifdef CONFIG_ALPHA_EV4 -# define flush_tlb_current ev4_flush_tlb_current -# define flush_tlb_current_page ev4_flush_tlb_current_page -# else -# define flush_tlb_current ev5_flush_tlb_current -# define flush_tlb_current_page ev5_flush_tlb_current_page -# endif -#endif - -#ifdef __MMU_EXTERN_INLINE -#undef __EXTERN_INLINE -#undef __MMU_EXTERN_INLINE -#endif - -/* - * Flush current user mapping. - */ -static inline void flush_tlb(void) -{ - flush_tlb_current(current->active_mm); -} - -/* - * Flush a specified range of user mapping page tables - * from TLB. - * Although Alpha uses VPTE caches, this can be a nop, as Alpha does - * not have finegrained tlb flushing, so it will flush VPTE stuff - * during next flush_tlb_range. - */ -static inline void flush_tlb_pgtables(struct mm_struct *mm, - unsigned long start, unsigned long end) -{ -} - -#ifndef CONFIG_SMP -/* - * Flush everything (kernel mapping may also have - * changed due to vmalloc/vfree) - */ -static inline void flush_tlb_all(void) -{ - tbia(); -} - -/* - * Flush a specified user mapping - */ -static inline void flush_tlb_mm(struct mm_struct *mm) -{ - if (mm == current->active_mm) - flush_tlb_current(mm); - else - flush_tlb_other(mm); -} - -/* - * Page-granular tlb flush. - * - * do a tbisd (type = 2) normally, and a tbis (type = 3) - * if it is an executable mapping. We want to avoid the - * itlb flush, because that potentially also does a - * icache flush. - */ -static inline void flush_tlb_page(struct vm_area_struct *vma, - unsigned long addr) -{ - struct mm_struct * mm = vma->vm_mm; - - if (mm == current->active_mm) - flush_tlb_current_page(mm, vma, addr); - else - flush_tlb_other(mm); -} - -/* - * Flush a specified range of user mapping: on the - * Alpha we flush the whole user tlb. - */ -static inline void flush_tlb_range(struct vm_area_struct *vma, - unsigned long start, unsigned long end) -{ - flush_tlb_mm(vma->vm_mm); -} - -#else /* CONFIG_SMP */ - -extern void flush_tlb_all(void); -extern void flush_tlb_mm(struct mm_struct *); -extern void flush_tlb_page(struct vm_area_struct *, unsigned long); -extern void flush_tlb_range(struct vm_area_struct *, unsigned long, unsigned long); - -#endif /* CONFIG_SMP */ - /* * Allocate and free page tables. The xxx_kernel() versions are * used to allocate a kernel page table - this turns on ASN bits @@ -292,4 +70,6 @@ pte_free(struct page *page) __free_page(page); } +#define check_pgt_cache() do { } while (0) + #endif /* _ALPHA_PGALLOC_H */ diff --git a/include/asm-alpha/tlbflush.h b/include/asm-alpha/tlbflush.h new file mode 100644 index 000000000000..a8b6748c25ce --- /dev/null +++ b/include/asm-alpha/tlbflush.h @@ -0,0 +1,155 @@ +#ifndef _ALPHA_TLBFLUSH_H +#define _ALPHA_TLBFLUSH_H + +#include <linux/config.h> +#include <linux/mm.h> + +#ifndef __EXTERN_INLINE +#define __EXTERN_INLINE extern inline +#define __MMU_EXTERN_INLINE +#endif + +extern void __load_new_mm_context(struct mm_struct *); + + +/* Use a few helper functions to hide the ugly broken ASN + numbers on early Alphas (ev4 and ev45). */ + +__EXTERN_INLINE void +ev4_flush_tlb_current(struct mm_struct *mm) +{ + __load_new_mm_context(mm); + tbiap(); +} + +__EXTERN_INLINE void +ev5_flush_tlb_current(struct mm_struct *mm) +{ + __load_new_mm_context(mm); +} + +/* Flush just one page in the current TLB set. We need to be very + careful about the icache here, there is no way to invalidate a + specific icache page. */ + +__EXTERN_INLINE void +ev4_flush_tlb_current_page(struct mm_struct * mm, + struct vm_area_struct *vma, + unsigned long addr) +{ + int tbi_flag = 2; + if (vma->vm_flags & VM_EXEC) { + __load_new_mm_context(mm); + tbi_flag = 3; + } + tbi(tbi_flag, addr); +} + +__EXTERN_INLINE void +ev5_flush_tlb_current_page(struct mm_struct * mm, + struct vm_area_struct *vma, + unsigned long addr) +{ + if (vma->vm_flags & VM_EXEC) + __load_new_mm_context(mm); + else + tbi(2, addr); +} + + +#ifdef CONFIG_ALPHA_GENERIC +# define flush_tlb_current alpha_mv.mv_flush_tlb_current +# define flush_tlb_current_page alpha_mv.mv_flush_tlb_current_page +#else +# ifdef CONFIG_ALPHA_EV4 +# define flush_tlb_current ev4_flush_tlb_current +# define flush_tlb_current_page ev4_flush_tlb_current_page +# else +# define flush_tlb_current ev5_flush_tlb_current +# define flush_tlb_current_page ev5_flush_tlb_current_page +# endif +#endif + +#ifdef __MMU_EXTERN_INLINE +#undef __EXTERN_INLINE +#undef __MMU_EXTERN_INLINE +#endif + +/* Flush current user mapping. */ +static inline void +flush_tlb(void) +{ + flush_tlb_current(current->active_mm); +} + +/* Flush someone else's user mapping. */ +static inline void +flush_tlb_other(struct mm_struct *mm) +{ + long *mmc = &mm->context[smp_processor_id()]; + /* Check it's not zero first to avoid cacheline ping pong + when possible. */ + if (*mmc) *mmc = 0; +} + +/* Flush a specified range of user mapping page tables from TLB. + Although Alpha uses VPTE caches, this can be a nop, as Alpha does + not have finegrained tlb flushing, so it will flush VPTE stuff + during next flush_tlb_range. */ + +static inline void +flush_tlb_pgtables(struct mm_struct *mm, unsigned long start, + unsigned long end) +{ +} + +#ifndef CONFIG_SMP +/* Flush everything (kernel mapping may also have changed + due to vmalloc/vfree). */ +static inline void flush_tlb_all(void) +{ + tbia(); +} + +/* Flush a specified user mapping. */ +static inline void +flush_tlb_mm(struct mm_struct *mm) +{ + if (mm == current->active_mm) + flush_tlb_current(mm); + else + flush_tlb_other(mm); +} + +/* Page-granular tlb flush. */ +static inline void +flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) +{ + struct mm_struct *mm = vma->vm_mm; + + if (mm == current->active_mm) + flush_tlb_current_page(mm, vma, addr); + else + flush_tlb_other(mm); +} + +/* Flush a specified range of user mapping. On the Alpha we flush + the whole user tlb. */ +static inline void +flush_tlb_range(struct vm_area_struct *vma, unsigned long start, + unsigned long end) +{ + flush_tlb_mm(vma->vm_mm); +} + +#else /* CONFIG_SMP */ + +extern void flush_tlb_all(void); +extern void flush_tlb_mm(struct mm_struct *); +extern void flush_tlb_page(struct vm_area_struct *, unsigned long); +extern void flush_tlb_range(struct vm_area_struct *, unsigned long, + unsigned long); + +#endif /* CONFIG_SMP */ + +#endif /* _ALPHA_TLBFLUSH_H */ diff --git a/include/asm-arm/arch-cl7500/system.h b/include/asm-arm/arch-cl7500/system.h index 6cb002194834..fee569dd0303 100644 --- a/include/asm-arm/arch-cl7500/system.h +++ b/include/asm-arm/arch-cl7500/system.h @@ -18,6 +18,6 @@ static void arch_idle(void) do { \ iomd_writeb(0, IOMD_ROMCR0); \ cpu_reset(0); \ - } while (0); + } while (0) #endif diff --git a/include/asm-arm/arch-pxa/dma.h b/include/asm-arm/arch-pxa/dma.h new file mode 100644 index 000000000000..edc4804a66c0 --- /dev/null +++ b/include/asm-arm/arch-pxa/dma.h @@ -0,0 +1,49 @@ +/* + * linux/include/asm-arm/arch-pxa/dma.h + * + * Author: Nicolas Pitre + * Created: Jun 15, 2001 + * Copyright: MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_ARCH_DMA_H +#define __ASM_ARCH_DMA_H + +#define MAX_DMA_ADDRESS 0xffffffff + +/* No DMA as the rest of the world see it */ +#define MAX_DMA_CHANNELS 0 + +/* + * Descriptor structure for PXA's DMA engine + * Note: this structure must always be aligned to a 16-byte boundary. + */ + +typedef struct { + volatile u32 ddadr; /* Points to the next descriptor + flags */ + volatile u32 dsadr; /* DSADR value for the current transfer */ + volatile u32 dtadr; /* DTADR value for the current transfer */ + volatile u32 dcmd; /* DCMD value for the current transfer */ +} pxa_dma_desc; + +/* + * DMA registration + */ + +typedef enum { + DMA_PRIO_HIGH = 0, + DMA_PRIO_MEDIUM = 4, + DMA_PRIO_LOW = 8 +} pxa_dma_prio; + +int pxa_request_dma (char *name, + pxa_dma_prio prio, + void (*irq_handler)(int, void *, struct pt_regs *), + void *data); + +void pxa_free_dma (int dma_ch); + +#endif /* _ASM_ARCH_DMA_H */ diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h new file mode 100644 index 000000000000..e3aaa49ab3c5 --- /dev/null +++ b/include/asm-arm/arch-pxa/hardware.h @@ -0,0 +1,97 @@ +/* + * linux/include/asm-arm/arch-pxa/hardware.h + * + * Author: Nicolas Pitre + * Created: Jun 15, 2001 + * Copyright: MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include <linux/config.h> +#include <asm/mach-types.h> + + +/* + * These are statically mapped PCMCIA IO space for designs using it as a + * generic IO bus, typically with ISA parts, hardwired IDE interfaces, etc. + * The actual PCMCIA code is mapping required IO region at run time. + */ +#define PCMCIA_IO_0_BASE 0xf6000000 +#define PCMCIA_IO_1_BASE 0xf7000000 + + +/* + * Intel PXA internal I/O mappings + */ + +#define io_p2v(x) \ + (((x) < 0x44000000) ? ((x) - 0x40000000 + 0xfc000000) : \ + ((x) < 0x48000000) ? ((x) - 0x44000000 + 0xfe000000) : \ + ((x) - 0x48000000 + 0xff000000)) +#define io_v2p( x ) \ + (((x) < 0xfe000000) ? ((x) - 0xfc000000 + 0x40000000) : \ + ((x) < 0xff000000) ? ((x) - 0xfe000000 + 0x44000000) : \ + ((x) - 0xff000000 + 0x48000000)) + +#ifndef __ASSEMBLY__ + +#if 0 +# define __REG(x) (*((volatile u32 *)io_p2v(x))) +#else +/* + * This __REG() version gives the same results as the one above, except + * that we are fooling gcc somehow so it generates far better and smaller + * assembly code for access to contigous registers. It's a shame that gcc + * doesn't guess this by itself. + */ +#include <asm/types.h> +typedef struct { volatile u32 offset[1024]; } __regbase; +# define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2] +# define __REG(x) __REGP(io_p2v(x)) +#endif + +/* Let's kick gcc's ass again... */ +# define __REG2(x,y) \ + ( __builtin_constant_p(y) ? (__REG((x) + (y))) \ + : (*(volatile u32 *)((u32)&__REG(x) + (y))) ) + +# define __PREG(x) (io_v2p((u32)&(x))) + +#else + +# define __REG(x) io_p2v(x) +# define __PREG(x) io_v2p(x) + +#endif + +#include "pxa-regs.h" + +#ifndef __ASSEMBLY__ + +/* + * Handy routine to set GPIO alternate functions + */ +extern void pxa_gpio_mode( int gpio_mode ); + +/* + * return current lclk frequency in units of 10kHz + */ +extern unsigned int get_lclk_frequency_10khz(void); + +#endif + + +/* + * Implementation specifics + */ + +#include "lubbock.h" +#include "idp.h" + +#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-pxa/ide.h b/include/asm-arm/arch-pxa/ide.h new file mode 100644 index 000000000000..926797e14a06 --- /dev/null +++ b/include/asm-arm/arch-pxa/ide.h @@ -0,0 +1,57 @@ +/* + * linux/include/asm-arm/arch-pxa/ide.h + * + * Author: George Davis + * Created: Jan 10, 2002 + * Copyright: MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * + * Originally based upon linux/include/asm-arm/arch-sa1100/ide.h + * + */ + +#include <linux/config.h> +#include <asm/irq.h> +#include <asm/hardware.h> +#include <asm/mach-types.h> + + +/* + * Set up a hw structure for a specified data port, control port and IRQ. + * This should follow whatever the default interface uses. + */ +static __inline__ void +ide_init_hwif_ports(hw_regs_t *hw, int data_port, int ctrl_port, int *irq) +{ + ide_ioreg_t reg; + int i; + int regincr = 1; + + memset(hw, 0, sizeof(*hw)); + + reg = (ide_ioreg_t)data_port; + + for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) { + hw->io_ports[i] = reg; + reg += regincr; + } + + hw->io_ports[IDE_CONTROL_OFFSET] = (ide_ioreg_t) ctrl_port; + + if (irq) + *irq = 0; +} + + +/* + * Register the standard ports for this architecture with the IDE driver. + */ +static __inline__ void +ide_init_default_hwifs(void) +{ + /* Nothing to declare... */ +} diff --git a/include/asm-arm/arch-pxa/idp.h b/include/asm-arm/arch-pxa/idp.h new file mode 100644 index 000000000000..4fbcc3b9b84c --- /dev/null +++ b/include/asm-arm/arch-pxa/idp.h @@ -0,0 +1,418 @@ +/* + * linux/include/asm-arm/arch-pxa/idp.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Copyright (c) 2001 Cliff Brake, Accelent Systems Inc. + * + * 2001-09-13: Cliff Brake <cbrake@accelent.com> + * Initial code + * + */ + + +/* + * Note: this file must be safe to include in assembly files + */ + +/* comment out following if you have a rev01 board */ +#define PXA_IDP_REV02 1 +//#undef PXA_IDP_REV02 + +#ifdef PXA_IDP_REV02 + +#define IDP_FLASH_PHYS (PXA_CS0_PHYS) +#define IDP_ALT_FLASH_PHYS (PXA_CS1_PHYS) +#define IDP_MEDIAQ_PHYS (PXA_CS3_PHYS) +#define IDP_IDE_PHYS (PXA_CS5_PHYS + 0x03000000) +#define IDP_ETH_PHYS (PXA_CS5_PHYS + 0x03400000) +#define IDP_COREVOLT_PHYS (PXA_CS5_PHYS + 0x03800000) +#define IDP_CPLD_PHYS (PXA_CS5_PHYS + 0x03C00000) + + +/* + * virtual memory map + */ + +#define IDP_IDE_BASE (0xf0000000) +#define IDP_IDE_SIZE (1*1024*1024) + +#define IDP_ETH_BASE (IDP_IDE_BASE + IDP_IDE_SIZE) +#define IDP_ETH_SIZE (1*1024*1024) +#define ETH_BASE IDP_ETH_BASE //smc9194 driver compatibility issue + +#define IDP_COREVOLT_BASE (IDP_ETH_BASE + IDP_ETH_SIZE) +#define IDP_COREVOLT_SIZE (1*1024*1024) + +#define IDP_CPLD_BASE (IDP_COREVOLT_BASE + IDP_COREVOLT_SIZE) +#define IDP_CPLD_SIZE (1*1024*1024) + +#if (IDP_CPLD_BASE + IDP_CPLD_SIZE) > 0xfc000000 +#error Your custom IO space is getting a bit large !! +#endif + +#define CPLD_P2V(x) ((x) - IDP_CPLD_PHYS + IDP_CPLD_BASE) +#define CPLD_V2P(x) ((x) - IDP_CPLD_BASE + IDP_CPLD_PHYS) + +#ifndef __ASSEMBLY__ +# define __CPLD_REG(x) (*((volatile unsigned long *)CPLD_P2V(x))) +#else +# define __CPLD_REG(x) CPLD_P2V(x) +#endif + +/* board level registers in the CPLD: (offsets from CPLD_BASE) */ + +#define _IDP_CPLD_REV (IDP_CPLD_PHYS + 0x00) +#define _IDP_CPLD_PERIPH_PWR (IDP_CPLD_PHYS + 0x04) +#define _IDP_CPLD_LED_CONTROL (IDP_CPLD_PHYS + 0x08) +#define _IDP_CPLD_KB_COL_HIGH (IDP_CPLD_PHYS + 0x0C) +#define _IDP_CPLD_KB_COL_LOW (IDP_CPLD_PHYS + 0x10) +#define _IDP_CPLD_PCCARD_EN (IDP_CPLD_PHYS + 0x14) +#define _IDP_CPLD_GPIOH_DIR (IDP_CPLD_PHYS + 0x18) +#define _IDP_CPLD_GPIOH_VALUE (IDP_CPLD_PHYS + 0x1C) +#define _IDP_CPLD_GPIOL_DIR (IDP_CPLD_PHYS + 0x20) +#define _IDP_CPLD_GPIOL_VALUE (IDP_CPLD_PHYS + 0x24) +#define _IDP_CPLD_PCCARD_PWR (IDP_CPLD_PHYS + 0x28) +#define _IDP_CPLD_MISC_CTRL (IDP_CPLD_PHYS + 0x2C) +#define _IDP_CPLD_LCD (IDP_CPLD_PHYS + 0x30) +#define _IDP_CPLD_FLASH_WE (IDP_CPLD_PHYS + 0x34) + +#define _IDP_CPLD_KB_ROW (IDP_CPLD_PHYS + 0x50) +#define _IDP_CPLD_PCCARD0_STATUS (IDP_CPLD_PHYS + 0x54) +#define _IDP_CPLD_PCCARD1_STATUS (IDP_CPLD_PHYS + 0x58) +#define _IDP_CPLD_MISC_STATUS (IDP_CPLD_PHYS + 0x5C) + +/* FPGA register virtual addresses */ + +#define IDP_CPLD_REV __CPLD_REG(_IDP_CPLD_REV) +#define IDP_CPLD_PERIPH_PWR __CPLD_REG(_IDP_CPLD_PERIPH_PWR) +#define IDP_CPLD_LED_CONTROL __CPLD_REG(_IDP_CPLD_LED_CONTROL) +#define IDP_CPLD_KB_COL_HIGH __CPLD_REG(_IDP_CPLD_KB_COL_HIGH) +#define IDP_CPLD_KB_COL_LOW __CPLD_REG(_IDP_CPLD_KB_COL_LOW) +#define IDP_CPLD_PCCARD_EN __CPLD_REG(_IDP_CPLD_PCCARD_EN) +#define IDP_CPLD_GPIOH_DIR __CPLD_REG(_IDP_CPLD_GPIOH_DIR) +#define IDP_CPLD_GPIOH_VALUE __CPLD_REG(_IDP_CPLD_GPIOH_VALUE) +#define IDP_CPLD_GPIOL_DIR __CPLD_REG(_IDP_CPLD_GPIOL_DIR) +#define IDP_CPLD_GPIOL_VALUE __CPLD_REG(_IDP_CPLD_GPIOL_VALUE) +#define IDP_CPLD_PCCARD_PWR __CPLD_REG(_IDP_CPLD_PCCARD_PWR) +#define IDP_CPLD_MISC_CTRL __CPLD_REG(_IDP_CPLD_MISC_CTRL) +#define IDP_CPLD_LCD __CPLD_REG(_IDP_CPLD_LCD) +#define IDP_CPLD_FLASH_WE __CPLD_REG(_IDP_CPLD_FLASH_WE) + +#define IDP_CPLD_KB_ROW __CPLD_REG(_IDP_CPLD_KB_ROW) +#define IDP_CPLD_PCCARD0_STATUS __CPLD_REG(_IDP_CPLD_PCCARD0_STATUS) +#define IDP_CPLD_PCCARD1_STATUS __CPLD_REG(_IDP_CPLD_PCCARD1_STATUS) +#define IDP_CPLD_MISC_STATUS __CPLD_REG(_IDP_CPLD_MISC_STATUS) + + +/* + * Bit masks for various registers + */ + + +/* + * Macros for LCD Driver + */ + +#ifdef CONFIG_FB_PXA + +#define FB_BACKLIGHT_ON() (IDP_CPLD_LCD |= (1<<1)) +#define FB_BACKLIGHT_OFF() (IDP_CPLD_LCD &= ~(1<<1)) + +#define FB_PWR_ON() (IDP_CPLD_LCD |= (1<< 0)) +#define FB_PWR_OFF() (IDP_CPLD_LCD &= ~(1<<0)) + +#define FB_VLCD_ON() (IDP_CPLD_LCD |= (1<<2)) +#define FB_VLCD_OFF() (IDP_CPLD_LCD &= ~(1<<2)) + +#endif + + +/* + * Macros for LED Driver + */ + +/* leds 0 = ON */ +#define IDP_HB_LED (1<<5) +#define IDP_BUSY_LED (1<<6) + +#define IDP_LEDS_MASK (IDP_HB_LED | IDP_BUSY_LED) + +#define IDP_WRITE_LEDS(value) (IDP_CPLD_LED_CONTROL = (IDP_CPLD_LED_CONTROL & (~(IDP_LEDS_MASK)) | value)) + +/* + * macros for MTD driver + */ + +#define FLASH_WRITE_PROTECT_DISABLE() ((IDP_CPLD_FLASH_WE) &= ~(0x1)) +#define FLASH_WRITE_PROTECT_ENABLE() ((IDP_CPLD_FLASH_WE) |= (0x1)) + +/* + * macros for matrix keyboard driver + */ + +#define KEYBD_MATRIX_NUMBER_INPUTS 7 +#define KEYBD_MATRIX_NUMBER_OUTPUTS 14 + +#define KEYBD_MATRIX_INVERT_OUTPUT_LOGIC FALSE +#define KEYBD_MATRIX_INVERT_INPUT_LOGIC FALSE + +#define KEYBD_MATRIX_SETTLING_TIME_US 100 +#define KEYBD_MATRIX_KEYSTATE_DEBOUNCE_CONSTANT 2 + +#define KEYBD_MATRIX_SET_OUTPUTS(outputs) \ +{\ + IDP_CPLD_KB_COL_LOW = outputs;\ + IDP_CPLD_KB_COL_HIGH = outputs >> 7;\ +} + +#define KEYBD_MATRIX_GET_INPUTS(inputs) \ +{\ + inputs = (IDP_CPLD_KB_ROW & 0x7f);\ +} + +/* A listing of interrupts used by external hardware devices */ + +#define TOUCH_PANEL_IRQ IRQ_GPIO(21) +#define TOUCH_PANEL_IRQ_EGDE GPIO_FALLING_EDGE + +#define ETHERNET_IRQ IRQ_GPIO(4) +#define ETHERNET_IRQ_EDGE GPIO_RISING_EDGE + +#else + +/* + * following is for rev01 boards only + */ + +#define IDP_FLASH_PHYS (PXA_CS0_PHYS) +#define IDP_ALT_FLASH_PHYS (PXA_CS1_PHYS) +#define IDP_MEDIAQ_PHYS (PXA_CS3_PHYS) +#define IDP_CTRL_PORT_PHYS (PXA_CS5_PHYS + 0x02C00000) +#define IDP_IDE_PHYS (PXA_CS5_PHYS + 0x03000000) +#define IDP_ETH_PHYS (PXA_CS5_PHYS + 0x03400000) +#define IDP_COREVOLT_PHYS (PXA_CS5_PHYS + 0x03800000) +#define IDP_CPLD_PHYS (PXA_CS5_PHYS + 0x03C00000) + + +/* + * virtual memory map + */ + +#define IDP_CTRL_PORT_BASE (0xf0000000) +#define IDP_CTRL_PORT_SIZE (1*1024*1024) + +#define IDP_IDE_BASE (IDP_CTRL_PORT_BASE + IDP_CTRL_PORT_SIZE) +#define IDP_IDE_SIZE (1*1024*1024) + +#define IDP_ETH_BASE (IDP_IDE_BASE + IDP_IDE_SIZE) +#define IDP_ETH_SIZE (1*1024*1024) + +#define IDP_COREVOLT_BASE (IDP_ETH_BASE + IDP_ETH_SIZE) +#define IDP_COREVOLT_SIZE (1*1024*1024) + +#define IDP_CPLD_BASE (IDP_COREVOLT_BASE + IDP_COREVOLT_SIZE) +#define IDP_CPLD_SIZE (1*1024*1024) + +#if (IDP_CPLD_BASE + IDP_CPLD_SIZE) > 0xfc000000 +#error Your custom IO space is getting a bit large !! +#endif + +#define CPLD_P2V(x) ((x) - IDP_CPLD_PHYS + IDP_CPLD_BASE) +#define CPLD_V2P(x) ((x) - IDP_CPLD_BASE + IDP_CPLD_PHYS) + +#ifndef __ASSEMBLY__ +# define __CPLD_REG(x) (*((volatile unsigned long *)CPLD_P2V(x))) +#else +# define __CPLD_REG(x) CPLD_P2V(x) +#endif + +/* board level registers in the CPLD: (offsets from CPLD_BASE) */ + +#define _IDP_CPLD_LED_CONTROL (IDP_CPLD_PHYS + 0x00) +#define _IDP_CPLD_PERIPH_PWR (IDP_CPLD_PHYS + 0x04) +#define _IDP_CPLD_CIR (IDP_CPLD_PHYS + 0x08) +#define _IDP_CPLD_KB_COL_HIGH (IDP_CPLD_PHYS + 0x0C) +#define _IDP_CPLD_KB_COL_LOW (IDP_CPLD_PHYS + 0x10) +#define _IDP_CPLD_PCCARD_EN (IDP_CPLD_PHYS + 0x14) +#define _IDP_CPLD_GPIOH_DIR (IDP_CPLD_PHYS + 0x18) +#define _IDP_CPLD_GPIOH_VALUE (IDP_CPLD_PHYS + 0x1C) +#define _IDP_CPLD_GPIOL_DIR (IDP_CPLD_PHYS + 0x20) +#define _IDP_CPLD_GPIOL_VALUE (IDP_CPLD_PHYS + 0x24) +#define _IDP_CPLD_MISC (IDP_CPLD_PHYS + 0x28) +#define _IDP_CPLD_PCCARD0_STATUS (IDP_CPLD_PHYS + 0x2C) +#define _IDP_CPLD_PCCARD1_STATUS (IDP_CPLD_PHYS + 0x30) + +/* FPGA register virtual addresses */ +#define IDP_CPLD_LED_CONTROL __CPLD_REG(_IDP_CPLD_LED_CONTROL) /* write only */ +#define IDP_CPLD_PERIPH_PWR __CPLD_REG(_IDP_CPLD_PERIPH_PWR) /* write only */ +#define IDP_CPLD_CIR __CPLD_REG(_IDP_CPLD_CIR) /* write only */ +#define IDP_CPLD_KB_COL_HIGH __CPLD_REG(_IDP_CPLD_KB_COL_HIGH) /* write only */ +#define IDP_CPLD_KB_COL_LOW __CPLD_REG(_IDP_CPLD_KB_COL_LOW) /* write only */ +#define IDP_CPLD_PCCARD_EN __CPLD_REG(_IDP_CPLD_PCCARD_EN) /* write only */ +#define IDP_CPLD_GPIOH_DIR __CPLD_REG(_IDP_CPLD_GPIOH_DIR) /* write only */ +#define IDP_CPLD_GPIOH_VALUE __CPLD_REG(_IDP_CPLD_GPIOH_VALUE) /* write only */ +#define IDP_CPLD_GPIOL_DIR __CPLD_REG(_IDP_CPLD_GPIOL_DIR) /* write only */ +#define IDP_CPLD_GPIOL_VALUE __CPLD_REG(_IDP_CPLD_GPIOL_VALUE) /* write only */ +#define IDP_CPLD_MISC __CPLD_REG(_IDP_CPLD_MISC) /* read only */ +#define IDP_CPLD_PCCARD0_STATUS __CPLD_REG(_IDP_CPLD_PCCARD0_STATUS) /* read only */ +#define IDP_CPLD_PCCARD1_STATUS __CPLD_REG(_IDP_CPLD_PCCARD1_STATUS) /* read only */ + + +#ifndef __ASSEMBLY__ + +/* shadow registers for write only registers */ +extern unsigned int idp_cpld_led_control_shadow; +extern unsigned int idp_cpld_periph_pwr_shadow; +extern unsigned int idp_cpld_cir_shadow; +extern unsigned int idp_cpld_kb_col_high_shadow; +extern unsigned int idp_cpld_kb_col_low_shadow; +extern unsigned int idp_cpld_pccard_en_shadow; +extern unsigned int idp_cpld_gpioh_dir_shadow; +extern unsigned int idp_cpld_gpioh_value_shadow; +extern unsigned int idp_cpld_gpiol_dir_shadow; +extern unsigned int idp_cpld_gpiol_value_shadow; + +extern unsigned int idp_control_port_shadow; + +/* + * macros to write to write only register + * + * none of these macros are protected from + * multiple drivers using them in interrupt context. + */ + +#define WRITE_IDP_CPLD_LED_CONTROL(value, mask) \ +{\ + idp_cpld_led_control_shadow = ((value & mask) | (idp_cpld_led_control_shadow & ~mask));\ + IDP_CPLD_LED_CONTROL = idp_cpld_led_control_shadow;\ +} +#define WRITE_IDP_CPLD_PERIPH_PWR(value, mask) \ +{\ + idp_cpld_periph_pwr_shadow = ((value & mask) | (idp_cpld_periph_pwr_shadow & ~mask));\ + IDP_CPLD_PERIPH_PWR = idp_cpld_periph_pwr_shadow;\ +} +#define WRITE_IDP_CPLD_CIR(value, mask) \ +{\ + idp_cpld_cir_shadow = ((value & mask) | (idp_cpld_cir_shadow & ~mask));\ + IDP_CPLD_CIR = idp_cpld_cir_shadow;\ +} +#define WRITE_IDP_CPLD_KB_COL_HIGH(value, mask) \ +{\ + idp_cpld_kb_col_high_shadow = ((value & mask) | (idp_cpld_kb_col_high_shadow & ~mask));\ + IDP_CPLD_KB_COL_HIGH = idp_cpld_kb_col_high_shadow;\ +} +#define WRITE_IDP_CPLD_KB_COL_LOW(value, mask) \ +{\ + idp_cpld_kb_col_low_shadow = ((value & mask) | (idp_cpld_kb_col_low_shadow & ~mask));\ + IDP_CPLD_KB_COL_LOW = idp_cpld_kb_col_low_shadow;\ +} +#define WRITE_IDP_CPLD_PCCARD_EN(value, mask) \ +{\ + idp_cpld_ = ((value & mask) | (idp_cpld_led_control_shadow & ~mask));\ + IDP_CPLD_LED_CONTROL = idp_cpld_led_control_shadow;\ +} +#define WRITE_IDP_CPLD_GPIOH_DIR(value, mask) \ +{\ + idp_cpld_gpioh_dir_shadow = ((value & mask) | (idp_cpld_gpioh_dir_shadow & ~mask));\ + IDP_CPLD_GPIOH_DIR = idp_cpld_gpioh_dir_shadow;\ +} +#define WRITE_IDP_CPLD_GPIOH_VALUE(value, mask) \ +{\ + idp_cpld_gpioh_value_shadow = ((value & mask) | (idp_cpld_gpioh_value_shadow & ~mask));\ + IDP_CPLD_GPIOH_VALUE = idp_cpld_gpioh_value_shadow;\ +} +#define WRITE_IDP_CPLD_GPIOL_DIR(value, mask) \ +{\ + idp_cpld_gpiol_dir_shadow = ((value & mask) | (idp_cpld_gpiol_dir_shadow & ~mask));\ + IDP_CPLD_GPIOL_DIR = idp_cpld_gpiol_dir_shadow;\ +} +#define WRITE_IDP_CPLD_GPIOL_VALUE(value, mask) \ +{\ + idp_cpld_gpiol_value_shadow = ((value & mask) | (idp_cpld_gpiol_value_shadow & ~mask));\ + IDP_CPLD_GPIOL_VALUE = idp_cpld_gpiol_value_shadow;\ +} + +#define WRITE_IDP_CONTROL_PORT(value, mask) \ +{\ + idp_control_port_shadow = ((value & mask) | (idp_control_port_shadow & ~mask));\ + (*((volatile unsigned long *)IDP_CTRL_PORT_BASE)) = idp_control_port_shadow;\ +} + +#endif + +/* A listing of interrupts used by external hardware devices */ + +#define TOUCH_PANEL_IRQ IRQ_GPIO(21) +#define TOUCH_PANEL_IRQ_EGDE GPIO_FALLING_EDGE + +#define ETHERNET_IRQ IRQ_GPIO(4) +#define ETHERNET_IRQ_EDGE GPIO_RISING_EDGE + +/* + * Bit masks for various registers + */ + + +/* control port */ +#define IDP_CONTROL_PORT_PCSLOT0_0 (1 << 0) +#define IDP_CONTROL_PORT_PCSLOT0_1 (1 << 1) +#define IDP_CONTROL_PORT_PCSLOT0_2 (1 << 2) +#define IDP_CONTROL_PORT_PCSLOT0_3 (1 << 3) +#define IDP_CONTROL_PORT_PCSLOT1_1 (1 << 4) +#define IDP_CONTROL_PORT_PCSLOT1_2 (1 << 5) +#define IDP_CONTROL_PORT_PCSLOT1_3 (1 << 6) +#define IDP_CONTROL_PORT_PCSLOT1_4 (1 << 7) +#define IDP_CONTROL_PORT_SERIAL1_EN (1 << 9) +#define IDP_CONTROL_PORT_SERIAL2_EN (1 << 10) +#define IDP_CONTROL_PORT_SERIAL3_EN (1 << 11) +#define IDP_CONTROL_PORT_IRDA_FIR (1 << 12) +#define IDP_CONTROL_PORT_IRDA_M0 (1 << 13) +#define IDP_CONTROL_PORT_IRDA_M1 (1 << 14) +#define IDP_CONTROL_PORT_I2S_PWR (1 << 15) +#define IDP_CONTROL_PORT_FLASH_WP (1 << 19) +#define IDP_CONTROL_PORT_MILL_EN (1 << 20) +#define IDP_CONTROL_PORT_LCD_PWR (1 << 21) +#define IDP_CONTROL_PORT_LCD_BKLEN (1 << 22) +#define IDP_CONTROL_PORT_LCD_ENAVLCD (1 << 23) + +/* + * Macros for LCD Driver + */ + +#ifdef CONFIG_FB_PXA + +#define FB_BACKLIGHT_ON() WRITE_IDP_CONTROL_PORT(IDP_CONTROL_PORT_LCD_BKLEN, IDP_CONTROL_PORT_LCD_BKLEN) +#define FB_BACKLIGHT_OFF() WRITE_IDP_CONTROL_PORT(0, IDP_CONTROL_PORT_LCD_BKLEN) + +#define FB_PWR_ON() WRITE_IDP_CONTROL_PORT(IDP_CONTROL_PORT_LCD_PWR, IDP_CONTROL_PORT_LCD_PWR) +#define FB_PWR_OFF() WRITE_IDP_CONTROL_PORT(0, IDP_CONTROL_PORT_LCD_PWR) + +#define FB_VLCD_ON() WRITE_IDP_CONTROL_PORT(IDP_CONTROL_PORT_LCD_ENAVLCD, IDP_CONTROL_PORT_LCD_ENAVLCD) +#define FB_VLCD_OFF() WRITE_IDP_CONTROL_PORT(0, IDP_CONTROL_PORT_LCD_ENAVLCD) + +#endif + + +/* + * Macros for LED Driver + */ + +/* leds 0 = ON */ +#define IDP_HB_LED 0x1 +#define IDP_BUSY_LED 0x2 + +#define IDP_LEDS_MASK (IDP_HB_LED | IDP_BUSY_LED) + +#define IDP_WRITE_LEDS(value) WRITE_IDP_CPLD_LED_CONTROL(value, IDP_LEDS_MASK) + +/* + * macros for MTD driver + */ + +#define FLASH_WRITE_PROTECT_DISABLE() WRITE_IDP_CONTROL_PORT(0, IDP_CONTROL_PORT_FLASH_WP) +#define FLASH_WRITE_PROTECT_ENABLE() WRITE_IDP_CONTROL_PORT(IDP_CONTROL_PORT_FLASH_WP, IDP_CONTROL_PORT_FLASH_WP) + +#endif diff --git a/include/asm-arm/arch-pxa/io.h b/include/asm-arm/arch-pxa/io.h new file mode 100644 index 000000000000..d58fb7be5cb6 --- /dev/null +++ b/include/asm-arm/arch-pxa/io.h @@ -0,0 +1,19 @@ +/* + * linux/include/asm-arm/arch-pxa/io.h + * + * Copied from asm/arch/sa1100/io.h + */ +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +/* + * We don't actually have real ISA nor PCI buses, but there is so many + * drivers out there that might just work if we fake them... + */ +#define __io(a) (a) +#define __mem_pci(a) ((unsigned long)(a)) +#define __mem_isa(a) ((unsigned long)(a)) + +#endif diff --git a/include/asm-arm/arch-pxa/irq.h b/include/asm-arm/arch-pxa/irq.h new file mode 100644 index 000000000000..d770e4b37ae1 --- /dev/null +++ b/include/asm-arm/arch-pxa/irq.h @@ -0,0 +1,19 @@ +/* + * linux/include/asm-arm/arch-pxa/irq.h + * + * Author: Nicolas Pitre + * Created: Jun 15, 2001 + * Copyright: MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#define fixup_irq(x) (x) + +/* + * This prototype is required for cascading of multiplexed interrupts. + * Since it doesn't exist elsewhere, we'll put it here for now. + */ +extern void do_IRQ(int irq, struct pt_regs *regs); diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h new file mode 100644 index 000000000000..6709d96a665e --- /dev/null +++ b/include/asm-arm/arch-pxa/irqs.h @@ -0,0 +1,132 @@ +/* + * linux/include/asm-arm/arch-pxa/irqs.h + * + * Author: Nicolas Pitre + * Created: Jun 15, 2001 + * Copyright: MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#define PXA_IRQ_SKIP 8 /* The first 8 IRQs are reserved */ +#define PXA_IRQ(x) ((x) - PXA_IRQ_SKIP) + +#define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */ +#define IRQ_GPIO1 PXA_IRQ(9) /* GPIO1 Edge Detect */ +#define IRQ_GPIO_2_80 PXA_IRQ(10) /* GPIO[2-80] Edge Detect */ +#define IRQ_USB PXA_IRQ(11) /* USB Service */ +#define IRQ_PMU PXA_IRQ(12) /* Performance Monitoring Unit */ +#define IRQ_I2S PXA_IRQ(13) /* I2S Interrupt */ +#define IRQ_AC97 PXA_IRQ(14) /* AC97 Interrupt */ +#define IRQ_LCD PXA_IRQ(17) /* LCD Controller Service Request */ +#define IRQ_I2C PXA_IRQ(18) /* I2C Service Request */ +#define IRQ_ICP PXA_IRQ(19) /* ICP Transmit/Receive/Error */ +#define IRQ_STUART PXA_IRQ(20) /* STUART Transmit/Receive/Error */ +#define IRQ_BTUART PXA_IRQ(21) /* BTUART Transmit/Receive/Error */ +#define IRQ_FFUART PXA_IRQ(22) /* FFUART Transmit/Receive/Error*/ +#define IRQ_MMC PXA_IRQ(23) /* MMC Status/Error Detection */ +#define IRQ_SSP PXA_IRQ(24) /* SSP Service Request */ +#define IRQ_DMA PXA_IRQ(25) /* DMA Channel Service Request */ +#define IRQ_OST0 PXA_IRQ(26) /* OS Timer match 0 */ +#define IRQ_OST1 PXA_IRQ(27) /* OS Timer match 1 */ +#define IRQ_OST2 PXA_IRQ(28) /* OS Timer match 2 */ +#define IRQ_OST3 PXA_IRQ(29) /* OS Timer match 3 */ +#define IRQ_RTC1Hz PXA_IRQ(30) /* RTC HZ Clock Tick */ +#define IRQ_RTCAlrm PXA_IRQ(31) /* RTC Alarm */ + +#define GPIO_2_80_TO_IRQ(x) \ + PXA_IRQ((x) - 2 + 32) +#define IRQ_GPIO(x) (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_80_TO_IRQ(x)) + +#define IRQ_TO_GPIO_2_80(i) \ + ((i) - PXA_IRQ(32) + 2) +#define IRQ_TO_GPIO(i) ((i) - (((i) > IRQ_GPIO1) ? IRQ_GPIO(2) : IRQ_GPIO(0))) + +#define NR_IRQS (IRQ_GPIO(80) + 1) + +#if defined(CONFIG_SA1111) + +#define IRQ_SA1111_START (IRQ_GPIO(80) + 1) +#define SA1111_IRQ(x) (IRQ_SA1111_START + (x)) + +#define IRQ_GPAIN0 SA1111_IRQ(0) +#define IRQ_GPAIN1 SA1111_IRQ(1) +#define IRQ_GPAIN2 SA1111_IRQ(2) +#define IRQ_GPAIN3 SA1111_IRQ(3) +#define IRQ_GPBIN0 SA1111_IRQ(4) +#define IRQ_GPBIN1 SA1111_IRQ(5) +#define IRQ_GPBIN2 SA1111_IRQ(6) +#define IRQ_GPBIN3 SA1111_IRQ(7) +#define IRQ_GPBIN4 SA1111_IRQ(8) +#define IRQ_GPBIN5 SA1111_IRQ(9) +#define IRQ_GPCIN0 SA1111_IRQ(10) +#define IRQ_GPCIN1 SA1111_IRQ(11) +#define IRQ_GPCIN2 SA1111_IRQ(12) +#define IRQ_GPCIN3 SA1111_IRQ(13) +#define IRQ_GPCIN4 SA1111_IRQ(14) +#define IRQ_GPCIN5 SA1111_IRQ(15) +#define IRQ_GPCIN6 SA1111_IRQ(16) +#define IRQ_GPCIN7 SA1111_IRQ(17) +#define IRQ_MSTXINT SA1111_IRQ(18) +#define IRQ_MSRXINT SA1111_IRQ(19) +#define IRQ_MSSTOPERRINT SA1111_IRQ(20) +#define IRQ_TPTXINT SA1111_IRQ(21) +#define IRQ_TPRXINT SA1111_IRQ(22) +#define IRQ_TPSTOPERRINT SA1111_IRQ(23) +#define SSPXMTINT SA1111_IRQ(24) +#define SSPRCVINT SA1111_IRQ(25) +#define SSPROR SA1111_IRQ(26) +#define AUDXMTDMADONEA SA1111_IRQ(32) +#define AUDRCVDMADONEA SA1111_IRQ(33) +#define AUDXMTDMADONEB SA1111_IRQ(34) +#define AUDRCVDMADONEB SA1111_IRQ(35) +#define AUDTFSR SA1111_IRQ(36) +#define AUDRFSR SA1111_IRQ(37) +#define AUDTUR SA1111_IRQ(38) +#define AUDROR SA1111_IRQ(39) +#define AUDDTS SA1111_IRQ(40) +#define AUDRDD SA1111_IRQ(41) +#define AUDSTO SA1111_IRQ(42) +#define USBPWR SA1111_IRQ(43) +#define NIRQHCIM SA1111_IRQ(44) +#define HCIBUFFACC SA1111_IRQ(45) +#define HCIRMTWKP SA1111_IRQ(46) +#define NHCIMFCIR SA1111_IRQ(47) +#define PORT_RESUME SA1111_IRQ(48) +#define S0_READY_NINT SA1111_IRQ(49) +#define S1_READY_NINT SA1111_IRQ(50) +#define S0_CD_VALID SA1111_IRQ(51) +#define S1_CD_VALID SA1111_IRQ(52) +#define S0_BVD1_STSCHG SA1111_IRQ(53) +#define S1_BVD1_STSCHG SA1111_IRQ(54) + +#define SA1111_IRQ_MAX SA1111_IRQ(54) + +#undef NR_IRQS +#define NR_IRQS (SA1111_IRQ_MAX + 1) + +#endif // defined(CONFIG_SA1111) + +#if defined(CONFIG_ARCH_LUBBOCK) || defined(CONFIG_ARCH_PXA_IDP) +#if CONFIG_SA1111 +#define LUBBOCK_IRQ(x) (SA1111_IRQ_MAX + 1 + (x)) +#else +#define LUBBOCK_IRQ(x) (IRQ_GPIO(80) + 1 + (x)) +#endif + +#define LUBBOCK_SD_IRQ LUBBOCK_IRQ(0) +#define LUBBOCK_SA1111_IRQ LUBBOCK_IRQ(1) +#define LUBBOCK_USB_IRQ LUBBOCK_IRQ(2) +#define LUBBOCK_ETH_IRQ LUBBOCK_IRQ(3) +#define LUBBOCK_UCB1400_IRQ LUBBOCK_IRQ(4) +#define LUBBOCK_BB_IRQ LUBBOCK_IRQ(5) + +#undef NR_IRQS +#define NR_IRQS (LUBBOCK_IRQ(5) + 1) + +#endif // CONFIG_ARCH_LUBBOCK + + + diff --git a/include/asm-arm/arch-pxa/keyboard.h b/include/asm-arm/arch-pxa/keyboard.h new file mode 100644 index 000000000000..8cd10f1aa231 --- /dev/null +++ b/include/asm-arm/arch-pxa/keyboard.h @@ -0,0 +1,29 @@ +/* + * linux/include/asm-arm/arch-pxa/keyboard.h + * + * This file contains the architecture specific keyboard definitions + */ + +#ifndef _PXA_KEYBOARD_H +#define _PXA_KEYBOARD_H + +#include <linux/config.h> +#include <asm/mach-types.h> +#include <asm/hardware.h> + +extern struct kbd_ops_struct *kbd_ops; + +#define kbd_disable_irq() do { } while(0); +#define kbd_enable_irq() do { } while(0); + +extern int sa1111_kbd_init_hw(void); + +static inline void kbd_init_hw(void) +{ + if (machine_is_lubbock()) + sa1111_kbd_init_hw(); +} + + +#endif /* _PXA_KEYBOARD_H */ + diff --git a/include/asm-arm/arch-pxa/lubbock.h b/include/asm-arm/arch-pxa/lubbock.h new file mode 100644 index 000000000000..7d3b283e3e02 --- /dev/null +++ b/include/asm-arm/arch-pxa/lubbock.h @@ -0,0 +1,112 @@ +/* + * linux/include/asm-arm/arch-pxa/lubbock.h + * + * Author: Nicolas Pitre + * Created: Jun 15, 2001 + * Copyright: MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#define LUBBOCK_FPGA_PHYS PXA_CS2_PHYS +#define LUBBOCK_FPGA_VIRT (0xf0000000) /* phys 0x08000000 */ +#define LUBBOCK_ETH_BASE (0xf1000000) /* phys 0x0c000000 */ +#define LUBBOCK_SA1111_BASE (0xf4000000) /* phys 0x10000000 */ + +#define LUB_P2V(x) ((x) - LUBBOCK_FPGA_PHYS + LUBBOCK_FPGA_VIRT) +#define LUB_V2P(x) ((x) - LUBBOCK_FPGA_VIRT + LUBBOCK_FPGA_PHYS) + +#ifndef __ASSEMBLY__ +# define __LUB_REG(x) (*((volatile unsigned long *)LUB_P2V(x))) +#else +# define __LUB_REG(x) LUB_P2V(x) +#endif + +/* board level registers in the CPLD: (offsets from CPLD_BASE) */ + +#define WHOAMI 0 // card ID's (see programmers manual) +#define HEX_LED 0x10 // R/W access to 8 7 segment displays +#define DISC_BLNK_LED 0x40 // R/W [15-8] enables for hex leds, [7-0] discrete LEDs +#define CONF_SWITCHES 0x50 // RO [1] flash wrt prot, [0] 0= boot from rom, 1= flash +#define USER_SWITCHES 0x60 // RO [15-8] dip switches, [7-0] 2 hex encoding switches +#define MISC_WR 0x80 // R/W various system controls -see manual +#define MISC_RD 0x90 // RO various system status bits -see manual +//#define LUB_IRQ_MASK_EN 0xC0 // R/W 0= mask, 1= enable of TS, codec, ethernet, USB, SA1111, and card det. irq's +//#define LUB_IRQ_SET_CLR 0xD0 // R/W 1= set, 0 = clear IRQ's from TS, codec, etc... +//#define LUB_GP 0x100 // R/W [15-0] 16 bits of general purpose I/o for hacking + + +/* FPGA register physical addresses */ +#define _LUB_WHOAMI (LUBBOCK_FPGA_PHYS + 0x000) +#define _LUB_HEXLED (LUBBOCK_FPGA_PHYS + 0x010) +#define _LUB_DISC_BLNK_LED (LUBBOCK_FPGA_PHYS + 0x040) +#define _LUB_CONF_SWITCHES (LUBBOCK_FPGA_PHYS + 0x050) +#define _LUB_USER_SWITCHES (LUBBOCK_FPGA_PHYS + 0x060) +#define _LUB_MISC_WR (LUBBOCK_FPGA_PHYS + 0x080) +#define _LUB_MISC_RD (LUBBOCK_FPGA_PHYS + 0x090) +#define _LUB_IRQ_MASK_EN (LUBBOCK_FPGA_PHYS + 0x0C0) +#define _LUB_IRQ_SET_CLR (LUBBOCK_FPGA_PHYS + 0x0D0) +#define _LUB_GP (LUBBOCK_FPGA_PHYS + 0x100) + +/* FPGA register virtual addresses */ +#define LUB_WHOAMI __LUB_REG(_LUB_WHOAMI) +#define LUB_HEXLED __LUB_REG(_LUB_HEXLED) +#define LUB_DISC_BLNK_LED __LUB_REG(_LUB_DISC_BLNK_LED) +#define LUB_CONF_SWITCHES __LUB_REG(_LUB_CONF_SWITCHES) +#define LUB_USER_SWITCHES __LUB_REG(_LUB_USER_SWITCHES) +#define LUB_MISC_WR __LUB_REG(_LUB_MISC_WR) +#define LUB_MISC_RD __LUB_REG(_LUB_MISC_RD) +#define LUB_IRQ_MASK_EN __LUB_REG(_LUB_IRQ_MASK_EN) +#define LUB_IRQ_SET_CLR __LUB_REG(_LUB_IRQ_SET_CLR) +#define LUB_GP __LUB_REG(_LUB_GP) + +/* GPIOs */ + +#define GPIO_LUBBOCK_IRQ 0 +#define IRQ_GPIO_LUBBOCK_IRQ IRQ_GPIO0 + + +/* + * LED macros + */ + +#define LEDS_BASE LUB_DISC_BLNK_LED + +// 8 discrete leds available for general use: + +#define D28 0x1 +#define D27 0x2 +#define D26 0x4 +#define D25 0x8 +#define D24 0x10 +#define D23 0x20 +#define D22 0x40 +#define D21 0x80 + +/* Note: bits [15-8] are used to enable/blank the 8 7 segment hex displays so +* be sure to not monkey with them here. +*/ + +#define HEARTBEAT_LED D28 +#define SYS_BUSY_LED D27 +#define HEXLEDS_BASE LUB_HEXLED + +#define HEARTBEAT_LED_ON (LEDS_BASE &= ~HEARTBEAT_LED) +#define HEARTBEAT_LED_OFF (LEDS_BASE |= HEARTBEAT_LED) +#define SYS_BUSY_LED_OFF (LEDS_BASE |= SYS_BUSY_LED) +#define SYS_BUSY_LED_ON (LEDS_BASE &= ~SYS_BUSY_LED) + +// use x = D26-D21 for these, please... +#define DISCRETE_LED_ON(x) (LEDS_BASE &= ~(x)) +#define DISCRETE_LED_OFF(x) (LEDS_BASE |= (x)) + +#ifndef __ASSEMBLY__ + +//extern int hexled_val = 0; + +#endif + +#define BUMP_COUNTER (HEXLEDS_BASE = hexled_val++) +#define DEC_COUNTER (HEXLEDS_BASE = hexled_val--) diff --git a/include/asm-arm/arch-pxa/memory.h b/include/asm-arm/arch-pxa/memory.h new file mode 100644 index 000000000000..b137f480bab6 --- /dev/null +++ b/include/asm-arm/arch-pxa/memory.h @@ -0,0 +1,59 @@ +/* + * linux/include/asm-arm/arch-pxa/memory.h + * + * Author: Nicolas Pitre + * Copyright: (C) 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + + +/* + * Task size: 3GB + */ +#define TASK_SIZE (0xc0000000UL) +#define TASK_SIZE_26 (0x04000000UL) + +/* + * This decides where the kernel will search for a free chunk of vm + * space during mmap's. + */ +#define TASK_UNMAPPED_BASE (TASK_SIZE / 3) + +/* + * Page offset: 3GB + */ +#define PAGE_OFFSET (0xc0000000UL) + +/* + * Physical DRAM offset. + */ +#define PHYS_OFFSET (0xa0000000UL) +#define PHYS_TO_NID(addr) (0) + +/* + * physical vs virtual ram conversion + */ +#define __virt_to_phys__is_a_macro +#define __phys_to_virt__is_a_macro +#define __virt_to_phys(x) ((x) - PAGE_OFFSET + PHYS_OFFSET) +#define __phys_to_virt(x) ((x) - PHYS_OFFSET + PAGE_OFFSET) + +/* + * Virtual view <-> DMA view memory address translations + * virt_to_bus: Used to translate the virtual address to an + * address suitable to be passed to set_dma_addr + * bus_to_virt: Used to convert an address for DMA operations + * to an address that the kernel can use. + */ +#define __virt_to_bus__is_a_macro +#define __bus_to_virt__is_a_macro +#define __virt_to_bus(x) __virt_to_phys(x) +#define __bus_to_virt(x) __phys_to_virt(x) + +#endif diff --git a/include/asm-arm/arch-pxa/param.h b/include/asm-arm/arch-pxa/param.h new file mode 100644 index 000000000000..3197d82d7573 --- /dev/null +++ b/include/asm-arm/arch-pxa/param.h @@ -0,0 +1,3 @@ +/* + * linux/include/asm-arm/arch-pxa/param.h + */ diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h new file mode 100644 index 000000000000..ad618f0fb63f --- /dev/null +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -0,0 +1,1037 @@ +/* + * linux/include/asm-arm/arch-pxa/pxa-regs.h + * + * Author: Nicolas Pitre + * Created: Jun 15, 2001 + * Copyright: MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + + +// FIXME hack so that SA-1111.h will work [cb] + +#ifndef __ASSEMBLY__ +typedef unsigned short Word16 ; +typedef unsigned int Word32 ; +typedef Word32 Word ; +typedef Word Quad [4] ; +typedef void *Address ; +typedef void (*ExcpHndlr) (void) ; +#endif + +/* + * PXA Chip selects + */ + +#define PXA_CS0_PHYS 0x00000000 +#define PXA_CS1_PHYS 0x04000000 +#define PXA_CS2_PHYS 0x08000000 +#define PXA_CS3_PHYS 0x0C000000 +#define PXA_CS4_PHYS 0x10000000 +#define PXA_CS5_PHYS 0x14000000 + + +/* + * Personal Computer Memory Card International Association (PCMCIA) sockets + */ + +#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ +#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ +#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ +#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ +#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ + +#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ +#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ +#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ +#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ + +#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ +#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ +#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ +#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ + +#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ + (0x20000000 + (Nb)*PCMCIASp) +#define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ +#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ + (_PCMCIA (Nb) + 2*PCMCIAPrtSp) +#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ + (_PCMCIA (Nb) + 3*PCMCIAPrtSp) + +#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ +#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ +#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ +#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ + +#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ +#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ +#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ +#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ + + + +/* + * DMA Controller + */ + +#define DCSR0 __REG(0x40000000) /* DMA Control / Status Register for Channel 0 */ +#define DCSR1 __REG(0x40000004) /* DMA Control / Status Register for Channel 1 */ +#define DCSR2 __REG(0x40000008) /* DMA Control / Status Register for Channel 2 */ +#define DCSR3 __REG(0x4000000c) /* DMA Control / Status Register for Channel 3 */ +#define DCSR4 __REG(0x40000010) /* DMA Control / Status Register for Channel 4 */ +#define DCSR5 __REG(0x40000014) /* DMA Control / Status Register for Channel 5 */ +#define DCSR6 __REG(0x40000018) /* DMA Control / Status Register for Channel 6 */ +#define DCSR7 __REG(0x4000001c) /* DMA Control / Status Register for Channel 7 */ +#define DCSR8 __REG(0x40000020) /* DMA Control / Status Register for Channel 8 */ +#define DCSR9 __REG(0x40000024) /* DMA Control / Status Register for Channel 9 */ +#define DCSR10 __REG(0x40000028) /* DMA Control / Status Register for Channel 10 */ +#define DCSR11 __REG(0x4000002c) /* DMA Control / Status Register for Channel 11 */ +#define DCSR12 __REG(0x40000030) /* DMA Control / Status Register for Channel 12 */ +#define DCSR13 __REG(0x40000034) /* DMA Control / Status Register for Channel 13 */ +#define DCSR14 __REG(0x40000038) /* DMA Control / Status Register for Channel 14 */ +#define DCSR15 __REG(0x4000003c) /* DMA Control / Status Register for Channel 15 */ + +#define DCSR(x) __REG2(0x40000000, (x) << 2) + +#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */ +#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */ +#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ +#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */ +#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */ +#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */ +#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */ +#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */ + +#define DINT __REG(0x400000f0) /* DMA Interrupt Register */ + +#define DRCMR0 __REG(0x40000100) /* Request to Channel Map Register for DREQ 0 */ +#define DRCMR1 __REG(0x40000104) /* Request to Channel Map Register for DREQ 1 */ +#define DRCMR2 __REG(0x40000108) /* Request to Channel Map Register for I2S receive Request */ +#define DRCMR3 __REG(0x4000010c) /* Request to Channel Map Register for I2S transmit Request */ +#define DRCMR4 __REG(0x40000110) /* Request to Channel Map Register for BTUART receive Request */ +#define DRCMR5 __REG(0x40000114) /* Request to Channel Map Register for BTUART transmit Request. */ +#define DRCMR6 __REG(0x40000118) /* Request to Channel Map Register for FFUART receive Request */ +#define DRCMR7 __REG(0x4000011c) /* Request to Channel Map Register for FFUART transmit Request */ +#define DRCMR8 __REG(0x40000120) /* Request to Channel Map Register for AC97 microphone Request */ +#define DRCMR9 __REG(0x40000124) /* Request to Channel Map Register for AC97 modem receive Request */ +#define DRCMR10 __REG(0x40000128) /* Request to Channel Map Register for AC97 modem transmit Request */ +#define DRCMR11 __REG(0x4000012c) /* Request to Channel Map Register for AC97 audio receive Request */ +#define DRCMR12 __REG(0x40000130) /* Request to Channel Map Register for AC97 audio transmit Request */ +#define DRCMR13 __REG(0x40000134) /* Request to Channel Map Register for SSP receive Request */ +#define DRCMR14 __REG(0x40000138) /* Request to Channel Map Register for SSP transmit Request */ +#define DRCMR15 __REG(0x4000013c) /* Reserved */ +#define DRCMR16 __REG(0x40000140) /* Reserved */ +#define DRCMR17 __REG(0x40000144) /* Request to Channel Map Register for ICP receive Request */ +#define DRCMR18 __REG(0x40000148) /* Request to Channel Map Register for ICP transmit Request */ +#define DRCMR19 __REG(0x4000014c) /* Request to Channel Map Register for STUART receive Request */ +#define DRCMR20 __REG(0x40000150) /* Request to Channel Map Register for STUART transmit Request */ +#define DRCMR21 __REG(0x40000154) /* Request to Channel Map Register for MMC receive Request */ +#define DRCMR22 __REG(0x40000158) /* Request to Channel Map Register for MMC transmit Request */ +#define DRCMR23 __REG(0x4000015c) /* Reserved */ +#define DRCMR24 __REG(0x40000160) /* Reserved */ +#define DRCMR25 __REG(0x40000164) /* Request to Channel Map Register for USB endpoint 1 Request */ +#define DRCMR26 __REG(0x40000168) /* Request to Channel Map Register for USB endpoint 2 Request */ +#define DRCMR27 __REG(0x4000016C) /* Request to Channel Map Register for USB endpoint 3 Request */ +#define DRCMR28 __REG(0x40000170) /* Request to Channel Map Register for USB endpoint 4 Request */ +#define DRCMR29 __REG(0x40000174) /* Reserved */ +#define DRCMR30 __REG(0x40000178) /* Request to Channel Map Register for USB endpoint 6 Request */ +#define DRCMR31 __REG(0x4000017C) /* Request to Channel Map Register for USB endpoint 7 Request */ +#define DRCMR32 __REG(0x40000180) /* Request to Channel Map Register for USB endpoint 8 Request */ +#define DRCMR33 __REG(0x40000184) /* Request to Channel Map Register for USB endpoint 9 Request */ +#define DRCMR34 __REG(0x40000188) /* Reserved */ +#define DRCMR35 __REG(0x4000018C) /* Request to Channel Map Register for USB endpoint 11 Request */ +#define DRCMR36 __REG(0x40000190) /* Request to Channel Map Register for USB endpoint 12 Request */ +#define DRCMR37 __REG(0x40000194) /* Request to Channel Map Register for USB endpoint 13 Request */ +#define DRCMR38 __REG(0x40000198) /* Request to Channel Map Register for USB endpoint 14 Request */ +#define DRCMR39 __REG(0x4000019C) /* Reserved */ + +#define DRCMRRXSADR DRCMR2 +#define DRCMRTXSADR DRCMR3 +#define DRCMRRXBTRBR DRCMR4 +#define DRCMRTXBTTHR DRCMR5 +#define DRCMRRXFFRBR DRCMR6 +#define DRCMRTXFFTHR DRCMR7 +#define DRCMRRXMCDR DRCMR8 +#define DRCMRRXMODR DRCMR9 +#define DRCMRTXMODR DRCMR10 +#define DRCMRRXPCDR DRCMR11 +#define DRCMRTXPCDR DRCMR12 +#define DRCMRRXSSDR DRCMR13 +#define DRCMRTXSSDR DRCMR14 +#define DRCMRRXICDR DRCMR17 +#define DRCMRTXICDR DRCMR18 +#define DRCMRRXSTRBR DRCMR19 +#define DRCMRTXSTTHR DRCMR20 +#define DRCMRRXMMC DRCMR21 +#define DRCMRTXMMC DRCMR22 + +#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */ +#define DRCMR_CHLNUM 0x0f /* mask for Channel Number (read / write) */ + +#define DDADR0 __REG(0x40000200) /* DMA Descriptor Address Register Channel 0 */ +#define DSADR0 __REG(0x40000204) /* DMA Source Address Register Channel 0 */ +#define DTADR0 __REG(0x40000208) /* DMA Target Address Register Channel 0 */ +#define DCMD0 __REG(0x4000020c) /* DMA Command Address Register Channel 0 */ +#define DDADR1 __REG(0x40000210) /* DMA Descriptor Address Register Channel 1 */ +#define DSADR1 __REG(0x40000214) /* DMA Source Address Register Channel 1 */ +#define DTADR1 __REG(0x40000218) /* DMA Target Address Register Channel 1 */ +#define DCMD1 __REG(0x4000021c) /* DMA Command Address Register Channel 1 */ +#define DDADR2 __REG(0x40000220) /* DMA Descriptor Address Register Channel 2 */ +#define DSADR2 __REG(0x40000224) /* DMA Source Address Register Channel 2 */ +#define DTADR2 __REG(0x40000228) /* DMA Target Address Register Channel 2 */ +#define DCMD2 __REG(0x4000022c) /* DMA Command Address Register Channel 2 */ +#define DDADR3 __REG(0x40000230) /* DMA Descriptor Address Register Channel 3 */ +#define DSADR3 __REG(0x40000234) /* DMA Source Address Register Channel 3 */ +#define DTADR3 __REG(0x40000238) /* DMA Target Address Register Channel 3 */ +#define DCMD3 __REG(0x4000023c) /* DMA Command Address Register Channel 3 */ +#define DDADR4 __REG(0x40000240) /* DMA Descriptor Address Register Channel 4 */ +#define DSADR4 __REG(0x40000244) /* DMA Source Address Register Channel 4 */ +#define DTADR4 __REG(0x40000248) /* DMA Target Address Register Channel 4 */ +#define DCMD4 __REG(0x4000024c) /* DMA Command Address Register Channel 4 */ +#define DDADR5 __REG(0x40000250) /* DMA Descriptor Address Register Channel 5 */ +#define DSADR5 __REG(0x40000254) /* DMA Source Address Register Channel 5 */ +#define DTADR5 __REG(0x40000258) /* DMA Target Address Register Channel 5 */ +#define DCMD5 __REG(0x4000025c) /* DMA Command Address Register Channel 5 */ +#define DDADR6 __REG(0x40000260) /* DMA Descriptor Address Register Channel 6 */ +#define DSADR6 __REG(0x40000264) /* DMA Source Address Register Channel 6 */ +#define DTADR6 __REG(0x40000268) /* DMA Target Address Register Channel 6 */ +#define DCMD6 __REG(0x4000026c) /* DMA Command Address Register Channel 6 */ +#define DDADR7 __REG(0x40000270) /* DMA Descriptor Address Register Channel 7 */ +#define DSADR7 __REG(0x40000274) /* DMA Source Address Register Channel 7 */ +#define DTADR7 __REG(0x40000278) /* DMA Target Address Register Channel 7 */ +#define DCMD7 __REG(0x4000027c) /* DMA Command Address Register Channel 7 */ +#define DDADR8 __REG(0x40000280) /* DMA Descriptor Address Register Channel 8 */ +#define DSADR8 __REG(0x40000284) /* DMA Source Address Register Channel 8 */ +#define DTADR8 __REG(0x40000288) /* DMA Target Address Register Channel 8 */ +#define DCMD8 __REG(0x4000028c) /* DMA Command Address Register Channel 8 */ +#define DDADR9 __REG(0x40000290) /* DMA Descriptor Address Register Channel 9 */ +#define DSADR9 __REG(0x40000294) /* DMA Source Address Register Channel 9 */ +#define DTADR9 __REG(0x40000298) /* DMA Target Address Register Channel 9 */ +#define DCMD9 __REG(0x4000029c) /* DMA Command Address Register Channel 9 */ +#define DDADR10 __REG(0x400002a0) /* DMA Descriptor Address Register Channel 10 */ +#define DSADR10 __REG(0x400002a4) /* DMA Source Address Register Channel 10 */ +#define DTADR10 __REG(0x400002a8) /* DMA Target Address Register Channel 10 */ +#define DCMD10 __REG(0x400002ac) /* DMA Command Address Register Channel 10 */ +#define DDADR11 __REG(0x400002b0) /* DMA Descriptor Address Register Channel 11 */ +#define DSADR11 __REG(0x400002b4) /* DMA Source Address Register Channel 11 */ +#define DTADR11 __REG(0x400002b8) /* DMA Target Address Register Channel 11 */ +#define DCMD11 __REG(0x400002bc) /* DMA Command Address Register Channel 11 */ +#define DDADR12 __REG(0x400002c0) /* DMA Descriptor Address Register Channel 12 */ +#define DSADR12 __REG(0x400002c4) /* DMA Source Address Register Channel 12 */ +#define DTADR12 __REG(0x400002c8) /* DMA Target Address Register Channel 12 */ +#define DCMD12 __REG(0x400002cc) /* DMA Command Address Register Channel 12 */ +#define DDADR13 __REG(0x400002d0) /* DMA Descriptor Address Register Channel 13 */ +#define DSADR13 __REG(0x400002d4) /* DMA Source Address Register Channel 13 */ +#define DTADR13 __REG(0x400002d8) /* DMA Target Address Register Channel 13 */ +#define DCMD13 __REG(0x400002dc) /* DMA Command Address Register Channel 13 */ +#define DDADR14 __REG(0x400002e0) /* DMA Descriptor Address Register Channel 14 */ +#define DSADR14 __REG(0x400002e4) /* DMA Source Address Register Channel 14 */ +#define DTADR14 __REG(0x400002e8) /* DMA Target Address Register Channel 14 */ +#define DCMD14 __REG(0x400002ec) /* DMA Command Address Register Channel 14 */ +#define DDADR15 __REG(0x400002f0) /* DMA Descriptor Address Register Channel 15 */ +#define DSADR15 __REG(0x400002f4) /* DMA Source Address Register Channel 15 */ +#define DTADR15 __REG(0x400002f8) /* DMA Target Address Register Channel 15 */ +#define DCMD15 __REG(0x400002fc) /* DMA Command Address Register Channel 15 */ + +#define DDADR(x) __REG2(0x40000200, (x) << 4) +#define DSADR(x) __REG2(0x40000204, (x) << 4) +#define DTADR(x) __REG2(0x40000208, (x) << 4) +#define DCMD(x) __REG2(0x4000020c, (x) << 4) + +#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */ +#define DDADR_STOP (1 << 0) /* Stop (read / write) */ + +#define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */ +#define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */ +#define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ +#define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */ +#define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */ +#define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */ +#define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */ +#define DCMD_BURST8 (1 << 16) /* 8 byte burst */ +#define DCMD_BURST16 (2 << 16) /* 16 byte burst */ +#define DCMD_BURST32 (3 << 16) /* 32 byte burst */ +#define DCMD_WIDTH1 (1 << 14) /* 1 byte width */ +#define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */ +#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */ +#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ + +/* default combinations */ +#define DCMD_RXPCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4) +#define DCMD_TXPCDR (DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4) + + +/* + * UARTs + */ + +/* Full Function UART (FFUART) */ +#define FFUART FFRBR +#define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */ +#define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */ +#define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */ +#define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */ +#define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */ +#define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */ +#define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */ +#define FFLSR __REG(0x40100014) /* Line Status Register (read only) */ +#define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */ +#define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */ +#define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */ +#define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ +#define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ + +/* Bluetooth UART (BTUART) */ +#define BTUART BTRBR +#define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */ +#define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */ +#define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */ +#define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */ +#define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */ +#define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */ +#define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */ +#define BTLSR __REG(0x40200014) /* Line Status Register (read only) */ +#define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */ +#define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */ +#define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */ +#define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ +#define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ + +/* Standard UART (STUART) */ +#define STUART STRBR +#define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */ +#define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */ +#define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */ +#define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */ +#define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */ +#define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */ +#define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */ +#define STLSR __REG(0x40700014) /* Line Status Register (read only) */ +#define STMSR __REG(0x40700018) /* Reserved */ +#define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */ +#define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */ +#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ +#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ + +#define IER_DMAE (1 << 7) /* DMA Requests Enable */ +#define IER_UUE (1 << 6) /* UART Unit Enable */ +#define IER_NRZE (1 << 5) /* NRZ coding Enable */ +#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */ +#define IER_MIE (1 << 3) /* Modem Interrupt Enable */ +#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */ +#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */ +#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */ + +#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */ +#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */ +#define IIR_TOD (1 << 3) /* Time Out Detected */ +#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */ +#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */ +#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */ + +#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */ +#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */ +#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */ +#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */ +#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */ +#define FCR_ITL_1 (0) +#define FCR_ITL_8 (FCR_ITL1) +#define FCR_ITL_16 (FCR_ITL2) +#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) + +#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */ +#define LCR_SB (1 << 6) /* Set Break */ +#define LCR_STKYP (1 << 5) /* Sticky Parity */ +#define LCR_EPS (1 << 4) /* Even Parity Select */ +#define LCR_PEN (1 << 3) /* Parity Enable */ +#define LCR_STB (1 << 2) /* Stop Bit */ +#define LCR_WLS1 (1 << 1) /* Word Length Select */ +#define LCR_WLS0 (1 << 0) /* Word Length Select */ + +#define LSR_FIFOE (1 << 7) /* FIFO Error Status */ +#define LSR_TEMT (1 << 6) /* Transmitter Empty */ +#define LSR_TDRQ (1 << 5) /* Transmit Data Request */ +#define LSR_BI (1 << 4) /* Break Interrupt */ +#define LSR_FE (1 << 3) /* Framing Error */ +#define LSR_PE (1 << 2) /* Parity Error */ +#define LSR_OE (1 << 1) /* Overrun Error */ +#define LSR_DR (1 << 0) /* Data Ready */ + +#define MCR_LOOP (1 << 4) */ +#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ +#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ +#define MCR_RTS (1 << 1) /* Request to Send */ +#define MCR_DTR (1 << 0) /* Data Terminal Ready */ + +#define MSR_DCD (1 << 7) /* Data Carrier Detect */ +#define MSR_RI (1 << 6) /* Ring Indicator */ +#define MSR_DSR (1 << 5) /* Data Set Ready */ +#define MSR_CTS (1 << 4) /* Clear To Send */ +#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */ +#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */ +#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ +#define MSR_DCTS (1 << 0) /* Delta Clear To Send */ + + +/* + * I2C registers + */ + +#define IBMR __REG(0x40301680) /* I2C Bus Monitor Register - IBMR */ +#define IDBR __REG(0x40301688) /* I2C Data Buffer Register - IDBR */ +#define ICR __REG(0x40301690) /* I2C Control Register - ICR */ +#define ISR __REG(0x40301698) /* I2C Status Register - ISR */ +#define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */ + + +/* + * Serial Audio Controller + */ + + +/* FIXME the audio defines collide w/ the SA1111 defines. I don't like these + * short defines because there is too much chance of namespace collision */ + +//#define SACR0 __REG(0x40400000) /* Global Control Register */ +//#define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */ +//#define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */ +//#define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */ +//#define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */ +//#define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */ +//#define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */ + + +/* + * AC97 Controller registers + */ + +#define POCR __REG(0x40500000) /* PCM Out Control Register */ +#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ + +#define PICR __REG(0x40500004) /* PCM In Control Register */ +#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ + +#define MCCR __REG(0x40500008) /* Mic In Control Register */ +#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ + +#define GCR __REG(0x4050000C) /* Global Control Register */ +#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */ +#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */ +#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */ +#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */ +#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */ +#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */ +#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */ +#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */ +#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */ +#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */ + +#define POSR __REG(0x40500010) /* PCM Out Status Register */ +#define POSR_FIFOE (1 << 4) /* FIFO error */ + +#define PISR __REG(0x40500014) /* PCM In Status Register */ +#define PISR_FIFOE (1 << 4) /* FIFO error */ + +#define MCSR __REG(0x40500018) /* Mic In Status Register */ +#define MCSR_FIFOE (1 << 4) /* FIFO error */ + +#define GSR __REG(0x4050001C) /* Global Status Register */ +#define GSR_CDONE (1 << 19) /* Command Done */ +#define GSR_SDONE (1 << 18) /* Status Done */ +#define GSR_RDCS (1 << 15) /* Read Completion Status */ +#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */ +#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */ +#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */ +#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */ +#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */ +#define GSR_SCR (1 << 9) /* Secondary Codec Ready */ +#define GSR_PCR (1 << 8) /* Primary Codec Ready */ +#define GSR_MINT (1 << 7) /* Mic In Interrupt */ +#define GSR_POINT (1 << 6) /* PCM Out Interrupt */ +#define GSR_PIINT (1 << 5) /* PCM In Interrupt */ +#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */ +#define GSR_MIINT (1 << 1) /* Modem In Interrupt */ +#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */ + +#define CAR __REG(0x40500020) /* CODEC Access Register */ +#define CAR_CAIP (1 << 0) /* Codec Access In Progress */ + +#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */ +#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */ + +#define MOCR __REG(0x40500100) /* Modem Out Control Register */ +#define MOCR_FEIE (1 << 3) /* FIFO Error */ + +#define MICR __REG(0x40500108) /* Modem In Control Register */ +#define MICR_FEIE (1 << 3) /* FIFO Error */ + +#define MOSR __REG(0x40500110) /* Modem Out Status Register */ +#define MOSR_FIFOE (1 << 4) /* FIFO error */ + +#define MISR __REG(0x40500118) /* Modem In Status Register */ +#define MISR_FIFOE (1 << 4) /* FIFO error */ + +#define MODR __REG(0x40500140) /* Modem FIFO Data Register */ + +#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */ +#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */ +#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */ +#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */ + + +/* + * USB Device Controller + */ + +#define UDCCR __REG(0x40600000) /* UDC Control Register */ +#define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */ +#define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */ +#define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */ +#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */ +#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */ +#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */ +#define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */ +#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */ +#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */ +#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */ +#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */ +#define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */ +#define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */ +#define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */ +#define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */ +#define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */ +#define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */ +#define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */ +#define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */ +#define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */ +#define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */ +#define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */ +#define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */ +#define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */ +#define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */ +#define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */ +#define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */ +#define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */ +#define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */ +#define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */ +#define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */ +#define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */ +#define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */ +#define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */ +#define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */ +#define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */ +#define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */ +#define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */ +#define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */ +#define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */ +#define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */ +#define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */ +#define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */ +#define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */ + + +/* + * Fast Infrared Communication Port + */ + +#define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */ +#define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */ +#define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */ +#define ICDR __REG(0x4080000c) /* ICP Data Register */ +#define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */ +#define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */ + + +/* + * Real Time Clock + */ + +#define RCNR __REG(0x40900000) /* RTC Count Register */ +#define RTAR __REG(0x40900004) /* RTC Alarm Register */ +#define RTSR __REG(0x40900008) /* RTC Status Register */ +#define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */ + +#define RTSR_HZE (1 << 3) /* HZ interrupt enable */ +#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */ +#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */ +#define RTSR_AL (1 << 0) /* RTC alarm detected */ + + +/* + * OS Timer & Match Registers + */ + +#define OSMR0 __REG(0x40A00000) /* */ +#define OSMR1 __REG(0x40A00004) /* */ +#define OSMR2 __REG(0x40A00008) /* */ +#define OSMR3 __REG(0x40A0000C) /* */ +#define OSCR __REG(0x40A00010) /* OS Timer Counter Register */ +#define OSSR __REG(0x40A00014) /* OS Timer Status Register */ +#define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */ +#define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */ + +#define OSSR_M3 (1 << 3) /* Match status channel 3 */ +#define OSSR_M2 (1 << 2) /* Match status channel 2 */ +#define OSSR_M1 (1 << 1) /* Match status channel 1 */ +#define OSSR_M0 (1 << 0) /* Match status channel 0 */ + +#define OWER_WME (1 << 0) /* Watchdog Match Enable */ + +#define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */ +#define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */ +#define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */ +#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */ + + +/* + * Pulse Width Modulator + */ + +#define PWM_CTRL0 __REG(0x40B00000) /* PWM 0 Control Register */ +#define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */ +#define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */ + +#define PWM_CTRL1 __REG(0x40C00000) /* PWM 1Control Register */ +#define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */ +#define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */ + + +/* + * Interrupt Controller + */ + +#define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */ +#define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */ +#define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */ +#define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */ +#define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */ +#define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */ + + +/* + * General Purpose I/O + */ + +#define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */ +#define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */ +#define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */ + +#define GPDR0 __REG(0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */ +#define GPDR1 __REG(0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */ +#define GPDR2 __REG(0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */ + +#define GPSR0 __REG(0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */ +#define GPSR1 __REG(0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */ +#define GPSR2 __REG(0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */ + +#define GPCR0 __REG(0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */ +#define GPCR1 __REG(0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */ +#define GPCR2 __REG(0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */ + +#define GRER0 __REG(0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */ +#define GRER1 __REG(0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */ +#define GRER2 __REG(0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */ + +#define GFER0 __REG(0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */ +#define GFER1 __REG(0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */ +#define GFER2 __REG(0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */ + +#define GEDR0 __REG(0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */ +#define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */ +#define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */ + +#define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */ +#define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */ +#define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */ +#define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */ +#define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */ +#define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO 80 */ + +/* More handy macros. The argument is a literal GPIO number. */ + +#define GPIO_bit(x) (1 << ((x) & 0x1f)) +#define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) +#define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) +#define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) +#define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3) +#define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3) +#define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3) +#define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) +#define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) + +/* GPIO alternate function assignments */ + +#define GPIO1_RST 1 /* reset */ +#define GPIO6_MMCCLK 6 /* MMC Clock */ +#define GPIO8_48MHz 7 /* 48 MHz clock output */ +#define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */ +#define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */ +#define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */ +#define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */ +#define GPIO12_32KHz 12 /* 32 kHz out */ +#define GPIO13_MBGNT 13 /* memory controller grant */ +#define GPIO14_MBREQ 14 /* alternate bus master request */ +#define GPIO15_nCS_1 15 /* chip select 1 */ +#define GPIO16_PWM0 16 /* PWM0 output */ +#define GPIO17_PWM1 17 /* PWM1 output */ +#define GPIO18_RDY 18 /* Ext. Bus Ready */ +#define GPIO19_DREQ1 19 /* External DMA Request */ +#define GPIO20_DREQ0 20 /* External DMA Request */ +#define GPIO23_SCLK 23 /* SSP clock */ +#define GPIO24_SFRM 24 /* SSP Frame */ +#define GPIO25_STXD 25 /* SSP transmit */ +#define GPIO26_SRXD 26 /* SSP receive */ +#define GPIO27_SEXTCLK 27 /* SSP ext_clk */ +#define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */ +#define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */ +#define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */ +#define GPIO31_SYNC 31 /* AC97/I2S sync */ +#define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */ +#define GPIO33_nCS_5 33 /* chip select 5 */ +#define GPIO34_FFRXD 34 /* FFUART receive */ +#define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */ +#define GPIO35_FFCTS 35 /* FFUART Clear to send */ +#define GPIO36_FFDCD 36 /* FFUART Data carrier detect */ +#define GPIO37_FFDSR 37 /* FFUART data set ready */ +#define GPIO38_FFRI 38 /* FFUART Ring Indicator */ +#define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */ +#define GPIO39_FFTXD 39 /* FFUART transmit data */ +#define GPIO40_FFDTR 40 /* FFUART data terminal Ready */ +#define GPIO41_FFRTS 41 /* FFUART request to send */ +#define GPIO42_BTRXD 42 /* BTUART receive data */ +#define GPIO43_BTTXD 43 /* BTUART transmit data */ +#define GPIO44_BTCTS 44 /* BTUART clear to send */ +#define GPIO45_BTRTS 45 /* BTUART request to send */ +#define GPIO46_ICPRXD 46 /* ICP receive data */ +#define GPIO46_STRXD 46 /* STD_UART receive data */ +#define GPIO47_ICPTXD 47 /* ICP transmit data */ +#define GPIO47_STTXD 47 /* STD_UART transmit data */ +#define GPIO48_nPOE 48 /* Output Enable for Card Space */ +#define GPIO49_nPWE 49 /* Write Enable for Card Space */ +#define GPIO50_nPIOR 50 /* I/O Read for Card Space */ +#define GPIO51_nPIOW 51 /* I/O Write for Card Space */ +#define GPIO52_nPCE_1 52 /* Card Enable for Card Space */ +#define GPIO53_nPCE_2 53 /* Card Enable for Card Space */ +#define GPIO53_MMCCLK 53 /* MMC Clock */ +#define GPIO54_MMCCLK 54 /* MMC Clock */ +#define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */ +#define GPIO55_nPREG 55 /* Card Address bit 26 */ +#define GPIO56_nPWAIT 56 /* Wait signal for Card Space */ +#define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */ +#define GPIO58_LDD_0 58 /* LCD data pin 0 */ +#define GPIO59_LDD_1 59 /* LCD data pin 1 */ +#define GPIO60_LDD_2 60 /* LCD data pin 2 */ +#define GPIO61_LDD_3 61 /* LCD data pin 3 */ +#define GPIO62_LDD_4 62 /* LCD data pin 4 */ +#define GPIO63_LDD_5 63 /* LCD data pin 5 */ +#define GPIO64_LDD_6 64 /* LCD data pin 6 */ +#define GPIO65_LDD_7 65 /* LCD data pin 7 */ +#define GPIO66_LDD_8 66 /* LCD data pin 8 */ +#define GPIO66_MBREQ 66 /* alternate bus master req */ +#define GPIO67_LDD_9 67 /* LCD data pin 9 */ +#define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */ +#define GPIO68_LDD_10 68 /* LCD data pin 10 */ +#define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */ +#define GPIO69_LDD_11 69 /* LCD data pin 11 */ +#define GPIO69_MMCCLK 69 /* MMC_CLK */ +#define GPIO70_LDD_12 70 /* LCD data pin 12 */ +#define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */ +#define GPIO71_LDD_13 71 /* LCD data pin 13 */ +#define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */ +#define GPIO72_LDD_14 72 /* LCD data pin 14 */ +#define GPIO72_32kHz 72 /* 32 kHz clock */ +#define GPIO73_LDD_15 73 /* LCD data pin 15 */ +#define GPIO73_MBGNT 73 /* Memory controller grant */ +#define GPIO74_LCD_FCLK 74 /* LCD Frame clock */ +#define GPIO75_LCD_LCLK 75 /* LCD line clock */ +#define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */ +#define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */ +#define GPIO78_nCS_2 78 /* chip select 2 */ +#define GPIO79_nCS_3 79 /* chip select 3 */ +#define GPIO80_nCS_4 80 /* chip select 4 */ + +/* GPIO alternate function mode & direction */ + +#define GPIO_IN 0x000 +#define GPIO_OUT 0x080 +#define GPIO_ALT_FN_1_IN 0x100 +#define GPIO_ALT_FN_1_OUT 0x180 +#define GPIO_ALT_FN_2_IN 0x200 +#define GPIO_ALT_FN_2_OUT 0x280 +#define GPIO_ALT_FN_3_IN 0x300 +#define GPIO_ALT_FN_3_OUT 0x380 +#define GPIO_MD_MASK_NR 0x07f +#define GPIO_MD_MASK_DIR 0x080 +#define GPIO_MD_MASK_FN 0x300 + +#define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN) +#define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT) +#define GPIO8_48MHz_MD ( 8 | GPIO_ALT_FN_1_OUT) +#define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT) +#define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT) +#define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT) +#define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT) +#define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT) +#define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT) +#define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN) +#define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT) +#define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT) +#define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT) +#define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN) +#define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN) +#define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN) +#define GPIO23_SCLK_md (23 | GPIO_ALT_FN_2_OUT) +#define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT) +#define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT) +#define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN) +#define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN) +#define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN) +#define GPIO28_BITCLK_I2S_MD (28 | GPIO_ALT_FN_2_IN) +#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN) +#define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN) +#define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT) +#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT) +#define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT) +#define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT) +#define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN) +#define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT) +#define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN) +#define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT) +#define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN) +#define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN) +#define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN) +#define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN) +#define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT) +#define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT) +#define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT) +#define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT) +#define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN) +#define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT) +#define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN) +#define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT) +#define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN) +#define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN) +#define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT) +#define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT) +#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) +#define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT) +#define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT) +#define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT) +#define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT) +#define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT) +#define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT) +#define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT) +#define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT) +#define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT) +#define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN) +#define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN) +#define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT) +#define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT) +#define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT) +#define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT) +#define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT) +#define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT) +#define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT) +#define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT) +#define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT) +#define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN) +#define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT) +#define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT) +#define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT) +#define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT) +#define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT) +#define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT) +#define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT) +#define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT) +#define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT) +#define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT) +#define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT) +#define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT) +#define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT) +#define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT) +#define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT) +#define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT) +#define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT) +#define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT) +#define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT) +#define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT) +#define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT) + + +/* + * Power Manager + */ + +#define PMCR __REG(0x40F00000) /* Power Manager Control Register */ +#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */ +#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */ +#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */ +#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */ +#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */ +#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */ +#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */ +#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */ +#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */ +#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */ +#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */ + + +/* + * SSP Serial Port Registers + */ + +#define SSCR0 __REG(0x41000000) /* SSP Control Register 0 */ +#define SSCR1 __REG(0x41000004) /* SSP Control Register 1 */ +#define SSSR __REG(0x41000008) /* SSP Status Register */ +#define SSITR __REG(0x4100000C) /* SSP Interrupt Test Register */ +#define SSDR __REG(0x41000010) /* (Write / Read) SSP Data Write Register/SSP Data Read Register */ + + +/* + * MultiMediaCard (MMC) controller + */ + +#define MMC_STRPCL __REG(0x41100000) /* Control to start and stop MMC clock */ +#define MMC_STAT __REG(0x41100004) /* MMC Status Register (read only) */ +#define MMC_CLKRT __REG(0x41100008) /* MMC clock rate */ +#define MMC_SPI __REG(0x4110000c) /* SPI mode control bits */ +#define MMC_CMDAT __REG(0x41100010) /* Command/response/data sequence control */ +#define MMC_RESTO __REG(0x41100014) /* Expected response time out */ +#define MMC_RDTO __REG(0x41100018) /* Expected data read time out */ +#define MMC_BLKLEN __REG(0x4110001c) /* Block length of data transaction */ +#define MMC_NOB __REG(0x41100020) /* Number of blocks, for block mode */ +#define MMC_PRTBUF __REG(0x41100024) /* Partial MMC_TXFIFO FIFO written */ +#define MMC_I_MASK __REG(0x41100028) /* Interrupt Mask */ +#define MMC_I_REG __REG(0x4110002c) /* Interrupt Register (read only) */ +#define MMC_CMD __REG(0x41100030) /* Index of current command */ +#define MMC_ARGH __REG(0x41100034) /* MSW part of the current command argument */ +#define MMC_ARGL __REG(0x41100038) /* LSW part of the current command argument */ +#define MMC_RES __REG(0x4110003c) /* Response FIFO (read only) */ +#define MMC_RXFIFO __REG(0x41100040) /* Receive FIFO (read only) */ +#define MMC_TXFIFO __REG(0x41100044) /* Transmit FIFO (write only) */ + + +/* + * Core Clock + */ + +#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */ +#define CKEN __REG(0x41300004) /* Clock Enable Register */ +#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */ + +#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ +#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ +#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ + +#define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */ +#define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */ +#define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */ +#define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */ +#define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */ +#define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */ +#define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */ +#define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */ +#define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */ +#define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */ +#define CKEN2_AC97 (1 << 2) /* AC97 Unit Clock Enable */ +#define CKEN1_PWM1 (1 << 1) /* PWM1 Clock Enable */ +#define CKEN0_PWM0 (1 << 0) /* PWM0 Clock Enable */ + +#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ +#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ + + +/* + * LCD + */ + +#define LCCR0 __REG(0x44000000) /* LCD Controller Control Register 0 */ +#define LCCR1 __REG(0x44000004) /* LCD Controller Control Register 1 */ +#define LCCR2 __REG(0x44000008) /* LCD Controller Control Register 2 */ +#define LCCR3 __REG(0x4400000C) /* LCD Controller Control Register 3 */ +#define DFBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */ +#define DFBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */ +#define LCSR __REG(0x44000038) /* LCD Controller Status Register */ +#define LIIDR __REG(0x4400003C) /* LCD Controller Interrupt ID Register */ +#define TMEDRGBR __REG(0x44000040) /* TMED RGB Seed Register */ +#define TMEDCR __REG(0x44000044) /* TMED Control Register */ + +#define FDADR0 __REG(0x44000200) /* DMA Channel 0 Frame Descriptor Address Register */ +#define FSADR0 __REG(0x44000204) /* DMA Channel 0 Frame Source Address Register */ +#define FIDR0 __REG(0x44000208) /* DMA Channel 0 Frame ID Register */ +#define LDCMD0 __REG(0x4400020C) /* DMA Channel 0 Command Register */ +#define FDADR1 __REG(0x44000210) /* DMA Channel 1 Frame Descriptor Address Register */ +#define FSADR1 __REG(0x44000214) /* DMA Channel 1 Frame Source Address Register */ +#define FIDR1 __REG(0x44000218) /* DMA Channel 1 Frame ID Register */ +#define LDCMD1 __REG(0x4400021C) /* DMA Channel 1 Command Register */ + +#define LCCR0_ENB (1 << 0) /* LCD Controller enable */ +#define LCCR0_CMS (1 << 1) /* Color = 0, Monochrome = 1 */ +#define LCCR0_SDS (1 << 2) /* Single Panel = 0, Dual Panel = 1 */ +#define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */ +#define LCCR0_SFM (1 << 4) /* Start of frame mask */ +#define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */ +#define LCCR0_EFM (1 << 6) /* End of Frame mask */ +#define LCCR0_PAS (1 << 7) /* Passive = 0, Active = 1 */ +#define LCCR0_BLE (1 << 8) /* Little Endian = 0, Big Endian = 1 */ +#define LCCR0_DPD (1 << 9) /* Double Pixel mode, 4 pixel value = 0, 8 pixle values = 1 */ +#define LCCR0_DIS (1 << 10) /* LCD Disable */ +#define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */ +#define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */ +#define LCCR0_PDD_S 12 +#define LCCR0_BM (1 << 20) /* Branch mask */ +#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ + +#define LCCR3_PCD (0xff) /* Pixel clock divisor */ +#define LCCR3_ACB (0xff << 8) /* AC Bias pin frequency */ +#define LCCR3_ACB_S 8 +#define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */ +#define LCCR3_API_S 16 +#define LCCR3_VSP (1 << 20) /* vertical sync polarity */ +#define LCCR3_HSP (1 << 21) /* horizontal sync polarity */ +#define LCCR3_PCP (1 << 22) /* pixel clock polarity */ +#define LCCR3_OEP (1 << 23) /* output enable polarity */ +#define LCCR3_BPP (7 << 24) /* bits per pixel */ +#define LCCR3_BPP_S 24 +#define LCCR3_DPC (1 << 27) /* double pixel clock mode */ + +#define LCSR_LDD (1 << 0) /* LCD Disable Done */ +#define LCSR_SOF (1 << 1) /* Start of frame */ +#define LCSR_BER (1 << 2) /* Bus error */ +#define LCSR_ABC (1 << 3) /* AC Bias count */ +#define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */ +#define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */ +#define LCSR_OU (1 << 6) /* output FIFO underrun */ +#define LCSR_QD (1 << 7) /* quick disable */ +#define LCSR_EOF (1 << 8) /* end of frame */ +#define LCSR_BS (1 << 9) /* branch status */ +#define LCSR_SINT (1 << 10) /* subsequent interrupt */ + +#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ + +/* + * Memory controller + */ + +#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */ +#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */ +#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */ +#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */ +#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */ +#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ +#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */ +#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */ +#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */ +#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */ +#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */ +#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */ +#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */ +#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */ +#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */ +#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */ +#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ + diff --git a/include/asm-arm/arch-pxa/serial.h b/include/asm-arm/arch-pxa/serial.h new file mode 100644 index 000000000000..1a8423ac6f20 --- /dev/null +++ b/include/asm-arm/arch-pxa/serial.h @@ -0,0 +1,51 @@ +/* + * linux/include/asm-arm/arch-pxa/serial.h + * + * Author: Nicolas Pitre + * Copyright: (C) 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + + +#define BAUD_BASE 921600 + +/* Standard COM flags */ +#define STD_COM_FLAGS (ASYNC_SKIP_TEST) + +#define RS_TABLE_SIZE 5 + +#define STD_SERIAL_PORT_DEFNS \ + { \ + type: PORT_PXA, \ + xmit_fifo_size: 64, \ + baud_base: BAUD_BASE, \ + iomem_base: &FFUART, \ + iomem_reg_shift: 2, \ + io_type: SERIAL_IO_MEM, \ + irq: IRQ_FFUART, \ + flags: STD_COM_FLAGS, \ + }, { \ + type: PORT_PXA, \ + xmit_fifo_size: 64, \ + baud_base: BAUD_BASE, \ + iomem_base: &STUART, \ + iomem_reg_shift: 2, \ + io_type: SERIAL_IO_MEM, \ + irq: IRQ_STUART, \ + flags: STD_COM_FLAGS, \ + }, { \ + type: PORT_PXA, \ + xmit_fifo_size: 64, \ + baud_base: BAUD_BASE, \ + iomem_base: &BTUART, \ + iomem_reg_shift: 2, \ + io_type: SERIAL_IO_MEM, \ + irq: IRQ_BTUART, \ + flags: STD_COM_FLAGS, \ + } + +#define EXTRA_SERIAL_PORT_DEFNS + diff --git a/include/asm-arm/arch-pxa/system.h b/include/asm-arm/arch-pxa/system.h new file mode 100644 index 000000000000..ed8b5edb7aed --- /dev/null +++ b/include/asm-arm/arch-pxa/system.h @@ -0,0 +1,39 @@ +/* + * linux/include/asm-arm/arch-pxa/system.h + * + * Author: Nicolas Pitre + * Created: Jun 15, 2001 + * Copyright: MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "hardware.h" + +static inline void arch_idle(void) +{ + if (!hlt_counter) { + int flags; + local_irq_save(flags); + if(!need_resched()) + cpu_do_idle(0); + local_irq_restore(flags); + } +} + + +static inline void arch_reset(char mode) +{ + if (mode == 's') { + /* Jump into ROM at address 0 */ + cpu_reset(0); + } else { + /* Initialize the watchdog and let it fire */ + OWER = OWER_WME; + OSSR = OSSR_M3; + OSMR3 = OSCR + 36864; /* ... in 10 ms */ + } +} + diff --git a/include/asm-arm/arch-pxa/time.h b/include/asm-arm/arch-pxa/time.h new file mode 100644 index 000000000000..2ac2928f0b2c --- /dev/null +++ b/include/asm-arm/arch-pxa/time.h @@ -0,0 +1,84 @@ +/* + * linux/include/asm-arm/arch-pxa/time.h + * + * Author: Nicolas Pitre + * Created: Jun 15, 2001 + * Copyright: MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + + +static inline unsigned long pxa_get_rtc_time(void) +{ + return RCNR; +} + +static int pxa_set_rtc(void) +{ + unsigned long current_time = xtime.tv_sec; + + if (RTSR & RTSR_ALE) { + /* make sure not to forward the clock over an alarm */ + unsigned long alarm = RTAR; + if (current_time >= alarm && alarm >= RCNR) + return -ERESTARTSYS; + } + RCNR = current_time; + return 0; +} + +/* IRQs are disabled before entering here from do_gettimeofday() */ +static unsigned long pxa_gettimeoffset (void) +{ + unsigned long ticks_to_match, elapsed, usec; + + /* Get ticks before next timer match */ + ticks_to_match = OSMR0 - OSCR; + + /* We need elapsed ticks since last match */ + elapsed = LATCH - ticks_to_match; + + /* Now convert them to usec */ + usec = (unsigned long)(elapsed*tick)/LATCH; + + return usec; +} + +static void pxa_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + long flags; + int next_match; + + /* Loop until we get ahead of the free running timer. + * This ensures an exact clock tick count and time acuracy. + * IRQs are disabled inside the loop to ensure coherence between + * lost_ticks (updated in do_timer()) and the match reg value, so we + * can use do_gettimeofday() from interrupt handlers. + */ + do { + do_leds(); + do_set_rtc(); + local_irq_save( flags ); + do_timer(regs); + OSSR = OSSR_M0; /* Clear match on timer 0 */ + next_match = (OSMR0 += LATCH); + local_irq_restore( flags ); + } while( (signed long)(next_match - OSCR) <= 0 ); +} + +void __init time_init(void) +{ + gettimeoffset = pxa_gettimeoffset; + set_rtc = pxa_set_rtc; + xtime.tv_sec = pxa_get_rtc_time(); + timer_irq.handler = pxa_timer_interrupt; + OSMR0 = 0; /* set initial match at 0 */ + OSSR = 0xf; /* clear status on all timers */ + setup_irq(IRQ_OST0, &timer_irq); + OIER |= OIER_E0; /* enable match on timer 0 to cause interrupts */ + OSCR = 0; /* initialize free-running timer, force first match */ +} + diff --git a/include/asm-arm/arch-pxa/timex.h b/include/asm-arm/arch-pxa/timex.h new file mode 100644 index 000000000000..fab199fc334e --- /dev/null +++ b/include/asm-arm/arch-pxa/timex.h @@ -0,0 +1,17 @@ +/* + * linux/include/asm-arm/arch-pxa/timex.h + * + * Author: Nicolas Pitre + * Created: Jun 15, 2001 + * Copyright: MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * PXA250/210 timer + */ +#define CLOCK_TICK_RATE 3686400 +#define CLOCK_TICK_FACTOR 80 diff --git a/include/asm-arm/arch-pxa/uncompress.h b/include/asm-arm/arch-pxa/uncompress.h new file mode 100644 index 000000000000..c4b906dc8b81 --- /dev/null +++ b/include/asm-arm/arch-pxa/uncompress.h @@ -0,0 +1,42 @@ +/* + * linux/include/asm-arm/arch-pxa/uncompress.h + * + * Author: Nicolas Pitre + * Copyright: (C) 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#define FFUART ((volatile unsigned long *)0x40100000) +#define BTUART ((volatile unsigned long *)0x40200000) +#define STUART ((volatile unsigned long *)0x40700000) + +#define UART FFUART + + +static __inline__ void putc(char c) +{ + while (!(UART[5] & 0x20)); + UART[0] = c; +} + +/* + * This does not append a newline + */ +static void puts(const char *s) +{ + while (*s) { + putc(*s); + if (*s == '\n') + putc('\r'); + s++; + } +} + +/* + * nothing to do + */ +#define arch_decomp_setup() +#define arch_decomp_wdog() diff --git a/include/asm-arm/arch-pxa/vmalloc.h b/include/asm-arm/arch-pxa/vmalloc.h new file mode 100644 index 000000000000..a75e7b7593ea --- /dev/null +++ b/include/asm-arm/arch-pxa/vmalloc.h @@ -0,0 +1,23 @@ +/* + * linux/include/asm-arm/arch-pxa/vmalloc.h + * + * Author: Nicolas Pitre + * Copyright: (C) 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Just any arbitrary offset to the start of the vmalloc VM area: the + * current 8MB value just means that there will be a 8MB "hole" after the + * physical memory until the kernel virtual memory starts. That means that + * any out-of-bounds memory accesses will hopefully be caught. + * The vmalloc() routines leaves a hole of 4kB between each vmalloced + * area for the same reason. ;) + */ +#define VMALLOC_OFFSET (8*1024*1024) +#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) +#define VMALLOC_VMADDR(x) ((unsigned long)(x)) +#define VMALLOC_END (0xe8000000) diff --git a/include/asm-arm/arch-sa1100/keyboard.h b/include/asm-arm/arch-sa1100/keyboard.h index 0207ba65ed6e..aa7f317092e5 100644 --- a/include/asm-arm/arch-sa1100/keyboard.h +++ b/include/asm-arm/arch-sa1100/keyboard.h @@ -10,8 +10,8 @@ #include <asm/mach-types.h> #include <asm/arch/assabet.h> -#define kbd_disable_irq() do { } while(0); -#define kbd_enable_irq() do { } while(0); +#define kbd_disable_irq() do { } while(0) +#define kbd_enable_irq() do { } while(0) extern int sa1111_kbd_init_hw(void); extern void gc_kbd_init_hw(void); diff --git a/include/asm-arm/cpu-multi32.h b/include/asm-arm/cpu-multi32.h index 83425c855102..88c5f44048a3 100644 --- a/include/asm-arm/cpu-multi32.h +++ b/include/asm-arm/cpu-multi32.h @@ -56,10 +56,6 @@ extern struct processor { * flush a specific page or pages */ void (*clean_invalidate_range)(unsigned long address, unsigned long end, int flags); - /* - * flush a page to RAM - */ - void (*_flush_ram_page)(void *virt_page); } cache; struct { /* D-cache */ @@ -121,7 +117,6 @@ extern const struct processor sa110_processor_functions; #define cpu_cache_clean_invalidate_all() processor.cache.clean_invalidate_all() #define cpu_cache_clean_invalidate_range(s,e,f) processor.cache.clean_invalidate_range(s,e,f) -#define cpu_flush_ram_page(vp) processor.cache._flush_ram_page(vp) #define cpu_dcache_clean_page(vp) processor.dcache.clean_page(vp) #define cpu_dcache_clean_entry(addr) processor.dcache.clean_entry(addr) diff --git a/include/asm-arm/cpu-single.h b/include/asm-arm/cpu-single.h index f175c79144ab..16b3d4830830 100644 --- a/include/asm-arm/cpu-single.h +++ b/include/asm-arm/cpu-single.h @@ -29,7 +29,6 @@ #define cpu_do_idle __cpu_fn(CPU_NAME,_do_idle) #define cpu_cache_clean_invalidate_all __cpu_fn(CPU_NAME,_cache_clean_invalidate_all) #define cpu_cache_clean_invalidate_range __cpu_fn(CPU_NAME,_cache_clean_invalidate_range) -#define cpu_flush_ram_page __cpu_fn(CPU_NAME,_flush_ram_page) #define cpu_dcache_invalidate_range __cpu_fn(CPU_NAME,_dcache_invalidate_range) #define cpu_dcache_clean_range __cpu_fn(CPU_NAME,_dcache_clean_range) #define cpu_dcache_clean_page __cpu_fn(CPU_NAME,_dcache_clean_page) @@ -57,7 +56,6 @@ extern int cpu_do_idle(int mode); extern void cpu_cache_clean_invalidate_all(void); extern void cpu_cache_clean_invalidate_range(unsigned long address, unsigned long end, int flags); -extern void cpu_flush_ram_page(void *virt_page); extern void cpu_dcache_invalidate_range(unsigned long start, unsigned long end); extern void cpu_dcache_clean_range(unsigned long start, unsigned long end); diff --git a/include/asm-arm/irq.h b/include/asm-arm/irq.h index 057ec51b2394..037ce952513c 100644 --- a/include/asm-arm/irq.h +++ b/include/asm-arm/irq.h @@ -19,6 +19,8 @@ #define NO_IRQ ((unsigned int)(-1)) #endif +struct irqaction; + #define disable_irq_nosync(i) disable_irq(i) extern void disable_irq(unsigned int); @@ -38,5 +40,7 @@ extern void enable_irq(unsigned int); int set_irq_type(unsigned int irq, unsigned int type); +int setup_irq(unsigned int, struct irqaction *); + #endif diff --git a/include/asm-arm/leds.h b/include/asm-arm/leds.h index 598b5086cbb1..88ce4124f854 100644 --- a/include/asm-arm/leds.h +++ b/include/asm-arm/leds.h @@ -23,12 +23,16 @@ typedef enum { led_stop, led_claim, /* override idle & timer leds */ led_release, /* restore idle & timer leds */ + led_start_timer_mode, + led_stop_timer_mode, led_green_on, led_green_off, led_amber_on, led_amber_off, led_red_on, led_red_off, + led_blue_on, + led_blue_off, /* * I want this between led_timer and led_start, but * someone has decided to export this to user space diff --git a/include/asm-arm/mach/irq.h b/include/asm-arm/mach/irq.h index 2c172b1330f2..d9971858d9cd 100644 --- a/include/asm-arm/mach/irq.h +++ b/include/asm-arm/mach/irq.h @@ -75,7 +75,6 @@ extern void (*init_arch_irq)(void); extern void init_FIQ(void); extern int show_fiq_list(struct seq_file *, void *); void __set_irq_handler(unsigned int irq, irq_handler_t, int); -int setup_irq(unsigned int, struct irqaction *); /* * External stuff. diff --git a/include/asm-arm/mach/pci.h b/include/asm-arm/mach/pci.h index 67f5043bea0c..08c459b25aa5 100644 --- a/include/asm-arm/mach/pci.h +++ b/include/asm-arm/mach/pci.h @@ -61,6 +61,7 @@ u8 pci_std_swizzle(struct pci_dev *dev, u8 *pinp); */ extern int iop310_setup(int nr, struct pci_sys_data *); extern struct pci_bus *iop310_scan_bus(int nr, struct pci_sys_data *); +extern void iop310_init(void); extern int dc21285_setup(int nr, struct pci_sys_data *); extern struct pci_bus *dc21285_scan_bus(int nr, struct pci_sys_data *); @@ -75,4 +76,3 @@ extern int pci_v3_setup(int nr, struct pci_sys_data *); extern struct pci_bus *pci_v3_scan_bus(int nr, struct pci_sys_data *); extern void pci_v3_preinit(void); extern void pci_v3_postinit(void); - diff --git a/include/asm-arm/mach/serial_sa1100.h b/include/asm-arm/mach/serial_sa1100.h index cac52bb7450b..bb91ca6b6bb7 100644 --- a/include/asm-arm/mach/serial_sa1100.h +++ b/include/asm-arm/mach/serial_sa1100.h @@ -26,13 +26,10 @@ struct sa1100_port_fns { void (*close)(struct uart_port *, struct uart_info *); }; -#if defined(CONFIG_SERIAL_SA1100) && !defined(CONFIG_SERIAL_SA1100_OLD) +#ifdef CONFIG_SERIAL_SA1100 void sa1100_register_uart_fns(struct sa1100_port_fns *fns); void sa1100_register_uart(int idx, int port); #else #define sa1100_register_uart_fns(fns) do { } while (0) #define sa1100_register_uart(idx,port) do { } while (0) #endif - -void sa1100_uart1_altgpio(void); - diff --git a/include/asm-arm/mman.h b/include/asm-arm/mman.h index 5b6540779c3d..0c72de97d419 100644 --- a/include/asm-arm/mman.h +++ b/include/asm-arm/mman.h @@ -4,6 +4,7 @@ #define PROT_READ 0x1 /* page can be read */ #define PROT_WRITE 0x2 /* page can be written */ #define PROT_EXEC 0x4 /* page can be executed */ +#define PROT_SEM 0x8 /* page may be used for atomic ops */ #define PROT_NONE 0x0 /* page can not be accessed */ #define MAP_SHARED 0x01 /* Share changes */ diff --git a/include/asm-arm/pgalloc.h b/include/asm-arm/pgalloc.h index 0945e2e4d280..18c0c5354f9c 100644 --- a/include/asm-arm/pgalloc.h +++ b/include/asm-arm/pgalloc.h @@ -30,4 +30,6 @@ extern void free_pgd_slow(pgd_t *pgd); #define pgd_alloc(mm) get_pgd_slow(mm) #define pgd_free(pgd) free_pgd_slow(pgd) +#define check_pgt_cache() do { } while (0) + #endif diff --git a/include/asm-arm/proc-armv/cache.h b/include/asm-arm/proc-armv/cache.h index a35cf1c83313..623e262d4166 100644 --- a/include/asm-arm/proc-armv/cache.h +++ b/include/asm-arm/proc-armv/cache.h @@ -59,74 +59,6 @@ } while (0) /* - * This flushes back any buffered write data. We have to clean the entries - * in the cache for this page. This does not invalidate either I or D caches. - * - * Called from: - * 1. fs/exec.c:put_dirty_page - ok - * - page came from alloc_page(), so page->mapping = NULL. - * - flush_dcache_page called immediately prior. - * - * 2. kernel/ptrace.c:access_one_page - flush_icache_page - * - flush_cache_page takes care of the user space side of the mapping. - * - page is either a page cache page (with page->mapping set, and - * hence page->mapping->i_mmap{,shared} also set) or an anonymous - * page. I think this is ok. - * - * 3. kernel/ptrace.c:access_one_page - bad - * - flush_cache_page takes care of the user space side of the mapping. - * - no apparant cache protection, reading the kernel virtual alias - * - * 4. mm/filemap.c:filemap_no_page - ok - * - add_to_page_cache_* clears PG_arch_1. - * - page->mapping != NULL. - * - i_mmap or i_mmap_shared will be non-null if mmap'd - * - called from (8). - * - * 5. mm/memory.c:break_cow,do_wp_page - {copy,clear}_user_page - * - need to ensure that copy_cow_page has pushed all data from the dcache - * to the page. - * - calls - * - clear_user_highpage -> clear_user_page - * - copy_user_highpage -> copy_user_page - * - * 6. mm/memory.c:do_swap_page - flush_icache_page - * - flush_icache_page called afterwards - if flush_icache_page does the - * same as flush_dcache_page, update_mmu_cache will do the work for us. - * - update_mmu_cache called. - * - * 7. mm/memory.c:do_anonymous_page - {copy,clear}_user_page - * - calls clear_user_highpage. See (5) - * - * 8. mm/memory.c:do_no_page - flush_icache_page - * - flush_icache_page called afterwards - if flush_icache_page does the - * same as flush_dcache_page, update_mmu_cache will do the work for us. - * - update_mmu_cache called. - * - When we place a user mapping, we will call update_mmu_cache, - * which will catch PG_arch_1 set. - * - * 9. mm/shmem.c:shmem_no_page - ok - * - shmem_get_page clears PG_arch_1, as does add_to_page_cache (duplicate) - * - page->mapping != NULL. - * - i_mmap or i_mmap_shared will be non-null if mmap'd - * - called from (8). - * - * 10. mm/swapfile.c:try_to_unuse - bad - * - this looks really dodgy - we're putting pages from the swap cache - * straight into processes, and the only cache handling appears to - * be flush_page_to_ram. - */ -#define flush_page_to_ram_ok -#ifdef flush_page_to_ram_ok -#define flush_page_to_ram(page) do { } while (0) -#else -static __inline__ void flush_page_to_ram(struct page *page) -{ - cpu_flush_ram_page(page_address(page)); -} -#endif - -/* * D cache only */ @@ -134,8 +66,16 @@ static __inline__ void flush_page_to_ram(struct page *page) #define clean_dcache_range(_s,_e) cpu_dcache_clean_range((_s),(_e)) #define flush_dcache_range(_s,_e) cpu_cache_clean_invalidate_range((_s),(_e),0) -#define mapping_mapped(map) (!list_empty(&(map)->i_mmap) || \ - !list_empty(&(map)->i_mmap_shared)) +#define clean_dcache_area(start,size) \ + cpu_cache_clean_invalidate_range((unsigned long)start, \ + ((unsigned long)start) + size, 0); + +/* + * This is an obsolete interface; the functionality that was provided by this + * function is now merged into our flush_dcache_page, flush_icache_page, + * copy_user_page and clear_user_page functions. + */ +#define flush_page_to_ram(page) do { } while (0) /* * flush_dcache_page is used when the kernel has written to the page @@ -150,39 +90,31 @@ static __inline__ void flush_page_to_ram(struct page *page) * about to change to user space. This is the same method as used on SPARC64. * See update_mmu_cache for the user space part. */ +#define mapping_mapped(map) (!list_empty(&(map)->i_mmap) || \ + !list_empty(&(map)->i_mmap_shared)) + +static inline void __flush_dcache_page(struct page *page) +{ + unsigned long virt = (unsigned long)page_address(page); + cpu_cache_clean_invalidate_range(virt, virt + PAGE_SIZE, 0); +} + static inline void flush_dcache_page(struct page *page) { if (page->mapping && !mapping_mapped(page->mapping)) set_bit(PG_dcache_dirty, &page->flags); - else { - unsigned long virt = (unsigned long)page_address(page); - cpu_cache_clean_invalidate_range(virt, virt + PAGE_SIZE, 0); - } + else + __flush_dcache_page(page); } +#define flush_icache_user_range(vma,page,addr,len) \ + flush_dcache_page(page) + /* - * flush_icache_page makes the kernel page address consistent with the - * user space mappings. The functionality is the same as flush_dcache_page, - * except we can do an optimisation and only clean the caches here if - * vma->vm_mm == current->active_mm. - * - * This function is misnamed IMHO. There are three places where it - * is called, each of which is preceded immediately by a call to - * flush_page_to_ram: + * We don't appear to need to do anything here. In fact, if we did, we'd + * duplicate cache flushing elsewhere performed by flush_dcache_page(). */ -#ifdef flush_page_to_ram_ok -static inline void flush_icache_page(struct vm_area_struct *vma, struct page *page) -{ - if (page->mapping && !mapping_mapped(page->mapping)) - set_bit(PG_dcache_dirty, &page->flags); - else if (vma->vm_mm == current->active_mm) { - unsigned long virt = (unsigned long)page_address(page); - cpu_cache_clean_invalidate_range(virt, virt + PAGE_SIZE, 0); - } -} -#else -#define flush_icache_page(vma,pg) do { } while (0) -#endif +#define flush_icache_page(vma,page) do { } while (0) #define clean_dcache_entry(_s) cpu_dcache_clean_entry((unsigned long)(_s)) diff --git a/include/asm-arm/proc-armv/domain.h b/include/asm-arm/proc-armv/domain.h index aadc83187d6b..67f889162c31 100644 --- a/include/asm-arm/proc-armv/domain.h +++ b/include/asm-arm/proc-armv/domain.h @@ -38,13 +38,13 @@ : : "r" (x)); \ } while (0) -#define modify_domain(dom,type) \ - do { \ - unsigned int domain = current->thread.domain; \ - domain &= ~domain_val(dom, DOMAIN_MANAGER); \ - domain |= domain_val(dom, type); \ - current->thread.domain = domain; \ - set_domain(current->thread.domain); \ +#define modify_domain(dom,type) \ + do { \ + struct thread_info *thread = current_thread_info(); \ + unsigned int domain = thread->cpu_domain; \ + domain &= ~domain_val(dom, DOMAIN_MANAGER); \ + thread->cpu_domain = domain | domain_val(dom, type); \ + set_domain(thread->cpu_domain); \ } while (0) #endif diff --git a/include/asm-arm/siginfo.h b/include/asm-arm/siginfo.h index 354b4e23b306..c94386bef4f2 100644 --- a/include/asm-arm/siginfo.h +++ b/include/asm-arm/siginfo.h @@ -107,7 +107,8 @@ typedef struct siginfo { #define SI_MESGQ -3 /* sent by real time mesq state change */ #define SI_ASYNCIO -4 /* sent by AIO completion */ #define SI_SIGIO -5 /* sent by queued SIGIO */ -#define SI_TKILL -6 /* sent by tkill system call */ +#define SI_TKILL -6 /* sent by tkill system call */ +#define SI_DETHREAD -7 /* sent by execve() killing subsidiary threads */ #define SI_FROMUSER(siptr) ((siptr)->si_code <= 0) #define SI_FROMKERNEL(siptr) ((siptr)->si_code > 0) diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h index b317ffcd1ec5..67f15f1be682 100644 --- a/include/asm-arm/system.h +++ b/include/asm-arm/system.h @@ -84,7 +84,6 @@ extern struct task_struct *__switch_to(struct thread_info *, struct thread_info #define stf() __stf() #define save_flags(x) __save_flags(x) #define restore_flags(x) __restore_flags(x) -#define save_flags_cli(x) __save_flags_cli(x) #endif /* CONFIG_SMP */ diff --git a/include/asm-generic/tlb.h b/include/asm-generic/tlb.h index eafce6e44ff3..9f5766d595cf 100644 --- a/include/asm-generic/tlb.h +++ b/include/asm-generic/tlb.h @@ -14,6 +14,7 @@ #define _ASM_GENERIC__TLB_H #include <linux/config.h> +#include <asm/tlbflush.h> #ifdef CONFIG_SMP /* aim for something that fits in the L1 cache */ diff --git a/include/asm-i386/apic.h b/include/asm-i386/apic.h index 89921f9d7843..d36b2f10f731 100644 --- a/include/asm-i386/apic.h +++ b/include/asm-i386/apic.h @@ -3,6 +3,7 @@ #include <linux/config.h> #include <linux/pm.h> +#include <asm/fixmap.h> #include <asm/apicdef.h> #include <asm/system.h> diff --git a/include/asm-i386/apicdef.h b/include/asm-i386/apicdef.h index f855a7d88d82..a91e6ede6b0a 100644 --- a/include/asm-i386/apicdef.h +++ b/include/asm-i386/apicdef.h @@ -71,6 +71,7 @@ #define GET_APIC_DEST_FIELD(x) (((x)>>24)&0xFF) #define SET_APIC_DEST_FIELD(x) ((x)<<24) #define APIC_LVTT 0x320 +#define APIC_LVTTHMR 0x330 #define APIC_LVTPC 0x340 #define APIC_LVT0 0x350 #define APIC_LVT_TIMER_BASE_MASK (0x3<<18) @@ -280,7 +281,16 @@ struct local_apic { u32 __reserved_4[3]; } lvt_timer; -/*330*/ struct { u32 __reserved[4]; } __reserved_15; +/*330*/ struct { /* LVT - Thermal Sensor */ + u32 vector : 8, + delivery_mode : 3, + __reserved_1 : 1, + delivery_status : 1, + __reserved_2 : 3, + mask : 1, + __reserved_3 : 15; + u32 __reserved_4[3]; + } lvt_thermal; /*340*/ struct { /* LVT - Performance Counter */ u32 vector : 8, diff --git a/include/asm-i386/cacheflush.h b/include/asm-i386/cacheflush.h new file mode 100644 index 000000000000..58d027dfc5ff --- /dev/null +++ b/include/asm-i386/cacheflush.h @@ -0,0 +1,18 @@ +#ifndef _I386_CACHEFLUSH_H +#define _I386_CACHEFLUSH_H + +/* Keep includes the same across arches. */ +#include <linux/mm.h> + +/* Caches aren't brain-dead on the intel. */ +#define flush_cache_all() do { } while (0) +#define flush_cache_mm(mm) do { } while (0) +#define flush_cache_range(vma, start, end) do { } while (0) +#define flush_cache_page(vma, vmaddr) do { } while (0) +#define flush_page_to_ram(page) do { } while (0) +#define flush_dcache_page(page) do { } while (0) +#define flush_icache_range(start, end) do { } while (0) +#define flush_icache_page(vma,pg) do { } while (0) +#define flush_icache_user_range(vma,pg,adr,len) do { } while (0) + +#endif /* _I386_CACHEFLUSH_H */ diff --git a/include/asm-i386/checksum.h b/include/asm-i386/checksum.h index 6b9761aa8f37..7c0527f9256b 100644 --- a/include/asm-i386/checksum.h +++ b/include/asm-i386/checksum.h @@ -1,6 +1,7 @@ #ifndef _I386_CHECKSUM_H #define _I386_CHECKSUM_H +#include <linux/in6.h> /* * computes the checksum of a memory block at buff, length len, diff --git a/include/asm-i386/highmem.h b/include/asm-i386/highmem.h index 0361da9b3f72..2f2f4e8eb0cc 100644 --- a/include/asm-i386/highmem.h +++ b/include/asm-i386/highmem.h @@ -24,7 +24,7 @@ #include <linux/init.h> #include <linux/interrupt.h> #include <asm/kmap_types.h> -#include <asm/pgtable.h> +#include <asm/tlbflush.h> /* declarations for highmem.c */ extern unsigned long highstart_pfn, highend_pfn; diff --git a/include/asm-i386/hw_irq.h b/include/asm-i386/hw_irq.h index 1461dab08d90..bf447a1b97b2 100644 --- a/include/asm-i386/hw_irq.h +++ b/include/asm-i386/hw_irq.h @@ -43,6 +43,7 @@ #define RESCHEDULE_VECTOR 0xfc #define CALL_FUNCTION_VECTOR 0xfb +#define THERMAL_APIC_VECTOR 0xf0 /* * Local APIC timer IRQ vector is on a different priority level, * to work around the 'lost local interrupt if more than 2 IRQ diff --git a/include/asm-i386/io.h b/include/asm-i386/io.h index f578b76c40cf..44996d06ecc3 100644 --- a/include/asm-i386/io.h +++ b/include/asm-i386/io.h @@ -57,15 +57,37 @@ #define __io_virt(x) ((void *)(x)) #endif -/* - * Change virtual addresses to physical addresses and vv. - * These are pretty trivial +/** + * virt_to_phys - map virtual addresses to physical + * @address: address to remap + * + * The returned physical address is the physical (CPU) mapping for + * the memory address given. It is only valid to use this function on + * addresses directly mapped or allocated via kmalloc. + * + * This function does not give bus mappings for DMA transfers. In + * almost all conceivable cases a device driver should not be using + * this function */ + static inline unsigned long virt_to_phys(volatile void * address) { return __pa(address); } +/** + * phys_to_virt - map physical address to virtual + * @address: address to remap + * + * The returned virtual address is a current CPU mapping for + * the memory address given. It is only valid to use this function on + * addresses that have a kernel mapping + * + * This function does not handle bus mappings for DMA transfers. In + * almost all conceivable cases a device driver should not be using + * this function + */ + static inline void * phys_to_virt(unsigned long address) { return __va(address); @@ -74,20 +96,51 @@ static inline void * phys_to_virt(unsigned long address) /* * Change "struct page" to physical address. */ +#ifdef CONFIG_HIGHMEM64G +#define page_to_phys(page) ((u64)(page - mem_map) << PAGE_SHIFT) +#else #define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT) +#endif extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags); +/** + * ioremap - map bus memory into CPU space + * @offset: bus address of the memory + * @size: size of the resource to map + * + * ioremap performs a platform specific sequence of operations to + * make bus memory CPU accessible via the readb/readw/readl/writeb/ + * writew/writel functions and the other mmio helpers. The returned + * address is not guaranteed to be usable directly as a virtual + * address. + */ + static inline void * ioremap (unsigned long offset, unsigned long size) { return __ioremap(offset, size, 0); } -/* - * This one maps high address device memory and turns off caching for that area. - * it's useful if some control registers are in such an area and write combining - * or read caching is not desirable: +/** + * ioremap_nocache - map bus memory into CPU space + * @offset: bus address of the memory + * @size: size of the resource to map + * + * ioremap_nocache performs a platform specific sequence of operations to + * make bus memory CPU accessible via the readb/readw/readl/writeb/ + * writew/writel functions and the other mmio helpers. The returned + * address is not guaranteed to be usable directly as a virtual + * address. + * + * This version of ioremap ensures that the memory is marked uncachable + * on the CPU as well as honouring existing caching rules from things like + * the PCI bus. Note that there are other caches and buffers on many + * busses. In paticular driver authors should read up on PCI writes + * + * It's useful if some control registers are in such an area and + * write combining or read caching is not desirable: */ + static inline void * ioremap_nocache (unsigned long offset, unsigned long size) { return __ioremap(offset, size, _PAGE_PCD); @@ -113,11 +166,11 @@ extern void bt_iounmap(void *addr, unsigned long size); /* * However PCI ones are not necessarily 1:1 and therefore these interfaces * are forbidden in portable PCI drivers. + * + * Allow them on x86 for legacy drivers, though. */ -extern unsigned long virt_to_bus_not_defined_use_pci_map(volatile void *addr); -#define virt_to_bus virt_to_bus_not_defined_use_pci_map -extern unsigned long bus_to_virt_not_defined_use_pci_map(volatile void *addr); -#define bus_to_virt bus_to_virt_not_defined_use_pci_map +#define virt_to_bus virt_to_phys +#define bus_to_virt phys_to_virt /* * readX/writeX() are used to access memory mapped devices. On some @@ -172,6 +225,17 @@ extern unsigned long bus_to_virt_not_defined_use_pci_map(volatile void *addr); #define eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),__io_virt(b),(c),(d)) #define isa_eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),__io_virt(__ISA_IO_base + (b)),(c),(d)) +/** + * check_signature - find BIOS signatures + * @io_addr: mmio address to check + * @signature: signature block + * @length: length of signature + * + * Perform a signature comparison with the mmio address io_addr. This + * address should have been obtained by ioremap. + * Returns 1 on a match. + */ + static inline int check_signature(unsigned long io_addr, const unsigned char *signature, int length) { @@ -188,6 +252,20 @@ out: return retval; } +/** + * isa_check_signature - find BIOS signatures + * @io_addr: mmio address to check + * @signature: signature block + * @length: length of signature + * + * Perform a signature comparison with the ISA mmio address io_addr. + * Returns 1 on a match. + * + * This function is deprecated. New drivers should use ioremap and + * check_signature. + */ + + static inline int isa_check_signature(unsigned long io_addr, const unsigned char *signature, int length) { diff --git a/include/asm-i386/irq.h b/include/asm-i386/irq.h index c1bcd739bc7b..269bf3e1aa8b 100644 --- a/include/asm-i386/irq.h +++ b/include/asm-i386/irq.h @@ -11,6 +11,7 @@ */ #include <linux/config.h> +#include <linux/sched.h> #define TIMER_IRQ 0 diff --git a/include/asm-i386/mmu_context.h b/include/asm-i386/mmu_context.h index e44c19374aee..c4aafc0dc009 100644 --- a/include/asm-i386/mmu_context.h +++ b/include/asm-i386/mmu_context.h @@ -5,6 +5,7 @@ #include <asm/desc.h> #include <asm/atomic.h> #include <asm/pgalloc.h> +#include <asm/tlbflush.h> /* * possibly do the LDT unload here? diff --git a/include/asm-i386/msr.h b/include/asm-i386/msr.h index d3f23faa638a..2a57654f0d0f 100644 --- a/include/asm-i386/msr.h +++ b/include/asm-i386/msr.h @@ -48,8 +48,8 @@ #define MSR_IA32_UCODE_WRITE 0x79 #define MSR_IA32_UCODE_REV 0x8b -#define MSR_IA32_PERFCTR0 0xc1 -#define MSR_IA32_PERFCTR1 0xc2 +#define MSR_P6_PERFCTR0 0xc1 +#define MSR_P6_PERFCTR1 0xc2 #define MSR_IA32_BBL_CR_CTL 0x119 @@ -57,8 +57,13 @@ #define MSR_IA32_MCG_STATUS 0x17a #define MSR_IA32_MCG_CTL 0x17b -#define MSR_IA32_EVNTSEL0 0x186 -#define MSR_IA32_EVNTSEL1 0x187 +#define MSR_P6_EVNTSEL0 0x186 +#define MSR_P6_EVNTSEL1 0x187 + +#define MSR_IA32_THERM_CONTROL 0x19a +#define MSR_IA32_THERM_INTERRUPT 0x19b +#define MSR_IA32_THERM_STATUS 0x19c +#define MSR_IA32_MISC_ENABLE 0x1a0 #define MSR_IA32_DEBUGCTLMSR 0x1d9 #define MSR_IA32_LASTBRANCHFROMIP 0x1db diff --git a/include/asm-i386/pgalloc.h b/include/asm-i386/pgalloc.h index 0af21645a1f1..b078cdd4adaa 100644 --- a/include/asm-i386/pgalloc.h +++ b/include/asm-i386/pgalloc.h @@ -5,7 +5,6 @@ #include <asm/processor.h> #include <asm/fixmap.h> #include <linux/threads.h> -#include <linux/highmem.h> #define pmd_populate_kernel(mm, pmd, pte) \ set_pmd(pmd, __pmd(_PAGE_TABLE + __pa(pte))) @@ -20,109 +19,11 @@ static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, struct page *p * Allocate and free page tables. */ -#if defined (CONFIG_X86_PAE) -/* - * We can't include <linux/slab.h> here, thus these uglinesses. - */ -struct kmem_cache_s; - -extern struct kmem_cache_s *pae_pgd_cachep; -extern void *kmem_cache_alloc(struct kmem_cache_s *, int); -extern void kmem_cache_free(struct kmem_cache_s *, void *); - - -static inline pgd_t *pgd_alloc(struct mm_struct *mm) -{ - int i; - pgd_t *pgd = kmem_cache_alloc(pae_pgd_cachep, GFP_KERNEL); - - if (pgd) { - for (i = 0; i < USER_PTRS_PER_PGD; i++) { - unsigned long pmd = __get_free_page(GFP_KERNEL); - if (!pmd) - goto out_oom; - clear_page(pmd); - set_pgd(pgd + i, __pgd(1 + __pa(pmd))); - } - memcpy(pgd + USER_PTRS_PER_PGD, - swapper_pg_dir + USER_PTRS_PER_PGD, - (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t)); - } - return pgd; -out_oom: - for (i--; i >= 0; i--) - free_page((unsigned long)__va(pgd_val(pgd[i])-1)); - kmem_cache_free(pae_pgd_cachep, pgd); - return NULL; -} - -#else +extern pgd_t *pgd_alloc(struct mm_struct *); +extern void pgd_free(pgd_t *pgd); -static inline pgd_t *pgd_alloc(struct mm_struct *mm) -{ - pgd_t *pgd = (pgd_t *)__get_free_page(GFP_KERNEL); - - if (pgd) { - memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t)); - memcpy(pgd + USER_PTRS_PER_PGD, - swapper_pg_dir + USER_PTRS_PER_PGD, - (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t)); - } - return pgd; -} - -#endif /* CONFIG_X86_PAE */ - -static inline void pgd_free(pgd_t *pgd) -{ -#if defined(CONFIG_X86_PAE) - int i; - - for (i = 0; i < USER_PTRS_PER_PGD; i++) - free_page((unsigned long)__va(pgd_val(pgd[i])-1)); - kmem_cache_free(pae_pgd_cachep, pgd); -#else - free_page((unsigned long)pgd); -#endif -} - -static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address) -{ - int count = 0; - pte_t *pte; - - do { - pte = (pte_t *) __get_free_page(GFP_KERNEL); - if (pte) - clear_page(pte); - else { - current->state = TASK_UNINTERRUPTIBLE; - schedule_timeout(HZ); - } - } while (!pte && (count++ < 10)); - return pte; -} - -static inline struct page *pte_alloc_one(struct mm_struct *mm, unsigned long address) -{ - int count = 0; - struct page *pte; - - do { -#if CONFIG_HIGHPTE - pte = alloc_pages(GFP_KERNEL | __GFP_HIGHMEM, 0); -#else - pte = alloc_pages(GFP_KERNEL, 0); -#endif - if (pte) - clear_highpage(pte); - else { - current->state = TASK_UNINTERRUPTIBLE; - schedule_timeout(HZ); - } - } while (!pte && (count++ < 10)); - return pte; -} +extern pte_t *pte_alloc_one_kernel(struct mm_struct *, unsigned long); +extern struct page *pte_alloc_one(struct mm_struct *, unsigned long); static inline void pte_free_kernel(pte_t *pte) { @@ -144,85 +45,6 @@ static inline void pte_free(struct page *pte) #define pmd_free(x) do { } while (0) #define pgd_populate(mm, pmd, pte) BUG() -/* - * TLB flushing: - * - * - flush_tlb() flushes the current mm struct TLBs - * - flush_tlb_all() flushes all processes TLBs - * - flush_tlb_mm(mm) flushes the specified mm context TLB's - * - flush_tlb_page(vma, vmaddr) flushes one page - * - flush_tlb_range(vma, start, end) flushes a range of pages - * - flush_tlb_pgtables(mm, start, end) flushes a range of page tables - * - * ..but the i386 has somewhat limited tlb flushing capabilities, - * and page-granular flushes are available only on i486 and up. - */ - -#ifndef CONFIG_SMP - -#define flush_tlb() __flush_tlb() -#define flush_tlb_all() __flush_tlb_all() -#define local_flush_tlb() __flush_tlb() - -static inline void flush_tlb_mm(struct mm_struct *mm) -{ - if (mm == current->active_mm) - __flush_tlb(); -} - -static inline void flush_tlb_page(struct vm_area_struct *vma, - unsigned long addr) -{ - if (vma->vm_mm == current->active_mm) - __flush_tlb_one(addr); -} - -static inline void flush_tlb_range(struct vm_area_struct *vma, - unsigned long start, unsigned long end) -{ - if (vma->vm_mm == current->active_mm) - __flush_tlb(); -} - -#else - -#include <asm/smp.h> - -#define local_flush_tlb() \ - __flush_tlb() - -extern void flush_tlb_all(void); -extern void flush_tlb_current_task(void); -extern void flush_tlb_mm(struct mm_struct *); -extern void flush_tlb_page(struct vm_area_struct *, unsigned long); - -#define flush_tlb() flush_tlb_current_task() - -static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end) -{ - flush_tlb_mm(vma->vm_mm); -} - -#define TLBSTATE_OK 1 -#define TLBSTATE_LAZY 2 - -struct tlb_state -{ - struct mm_struct *active_mm; - int state; - char __cacheline_padding[24]; -}; -extern struct tlb_state cpu_tlbstate[NR_CPUS]; - - -#endif - -static inline void flush_tlb_pgtables(struct mm_struct *mm, - unsigned long start, unsigned long end) -{ - /* i386 does not keep any page table caches in TLB */ -} - #define check_pgt_cache() do { } while (0) #endif /* _I386_PGALLOC_H */ diff --git a/include/asm-i386/pgtable.h b/include/asm-i386/pgtable.h index 1bf46187be83..354e45ca86af 100644 --- a/include/asm-i386/pgtable.h +++ b/include/asm-i386/pgtable.h @@ -24,71 +24,6 @@ extern pgd_t swapper_pg_dir[1024]; extern void paging_init(void); -/* Caches aren't brain-dead on the intel. */ -#define flush_cache_all() do { } while (0) -#define flush_cache_mm(mm) do { } while (0) -#define flush_cache_range(vma, start, end) do { } while (0) -#define flush_cache_page(vma, vmaddr) do { } while (0) -#define flush_page_to_ram(page) do { } while (0) -#define flush_dcache_page(page) do { } while (0) -#define flush_icache_range(start, end) do { } while (0) -#define flush_icache_page(vma,pg) do { } while (0) -#define flush_icache_user_range(vma,pg,adr,len) do { } while (0) - -#define __flush_tlb() \ - do { \ - unsigned int tmpreg; \ - \ - __asm__ __volatile__( \ - "movl %%cr3, %0; # flush TLB \n" \ - "movl %0, %%cr3; \n" \ - : "=r" (tmpreg) \ - :: "memory"); \ - } while (0) - -/* - * Global pages have to be flushed a bit differently. Not a real - * performance problem because this does not happen often. - */ -#define __flush_tlb_global() \ - do { \ - unsigned int tmpreg; \ - \ - __asm__ __volatile__( \ - "movl %1, %%cr4; # turn off PGE \n" \ - "movl %%cr3, %0; # flush TLB \n" \ - "movl %0, %%cr3; \n" \ - "movl %2, %%cr4; # turn PGE back on \n" \ - : "=&r" (tmpreg) \ - : "r" (mmu_cr4_features & ~X86_CR4_PGE), \ - "r" (mmu_cr4_features) \ - : "memory"); \ - } while (0) - -extern unsigned long pgkern_mask; - -/* - * Do not check the PGE bit unnecesserily if this is a PPro+ kernel. - */ -#ifdef CONFIG_X86_PGE -# define __flush_tlb_all() __flush_tlb_global() -#else -# define __flush_tlb_all() \ - do { \ - if (cpu_has_pge) \ - __flush_tlb_global(); \ - else \ - __flush_tlb(); \ - } while (0) -#endif - -#ifndef CONFIG_X86_INVLPG -#define __flush_tlb_one(addr) __flush_tlb() -#else -#define __flush_tlb_one(addr) \ -__asm__ __volatile__("invlpg %0": :"m" (*(char *) addr)) -#endif - /* * ZERO_PAGE is a global shared page that is always zero: used * for zero-mapped memory areas etc.. diff --git a/include/asm-i386/processor.h b/include/asm-i386/processor.h index 573dac8f51ab..13eec87ba8fd 100644 --- a/include/asm-i386/processor.h +++ b/include/asm-i386/processor.h @@ -59,6 +59,7 @@ struct cpuinfo_x86 { #define X86_VENDOR_CENTAUR 5 #define X86_VENDOR_RISE 6 #define X86_VENDOR_TRANSMETA 7 +#define X86_VENDOR_NSC 8 #define X86_VENDOR_UNKNOWN 0xff /* @@ -216,7 +217,7 @@ static inline void clear_in_cr4 (unsigned long mask) } /* - * Cyrix CPU configuration register indexes + * NSC/Cyrix CPU configuration register indexes */ #define CX86_CCR0 0xc0 #define CX86_CCR1 0xc1 @@ -232,7 +233,7 @@ static inline void clear_in_cr4 (unsigned long mask) #define CX86_RCR_BASE 0xdc /* - * Cyrix CPU indexed register access macros + * NSC/Cyrix CPU indexed register access macros */ #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); }) diff --git a/include/asm-i386/rwsem.h b/include/asm-i386/rwsem.h index 3cac14272380..9caff19cfd2e 100644 --- a/include/asm-i386/rwsem.h +++ b/include/asm-i386/rwsem.h @@ -164,7 +164,7 @@ LOCK_PREFIX " xadd %%edx,(%%eax)\n\t" /* subtracts 1, returns the old valu " jmp 1b\n" LOCK_SECTION_END "# ending __up_read\n" - : "+m"(sem->count), "+d"(tmp) + : /*"+m"(sem->count),*/ "+d"(tmp) : "a"(sem) : "memory", "cc"); } diff --git a/include/asm-i386/string-486.h b/include/asm-i386/string-486.h index 51bfd051bc00..4104ab9bc9f9 100644 --- a/include/asm-i386/string-486.h +++ b/include/asm-i386/string-486.h @@ -5,7 +5,7 @@ * This string-include defines all string functions as inline * functions. Use gcc. It also assumes ds=es=data space, this should be * normal. Most of the string-functions are rather heavily hand-optimized, - * see especially strtok,strstr,str[c]spn. They should work, but are not + * see especially strsep,strstr,str[c]spn. They should work, but are not * very easy to understand. Everything is done entirely within the register * set, making the functions fast and clean. * diff --git a/include/asm-i386/string.h b/include/asm-i386/string.h index d4d7899dc1aa..96f4e52fc7f7 100644 --- a/include/asm-i386/string.h +++ b/include/asm-i386/string.h @@ -20,7 +20,7 @@ * This string-include defines all string functions as inline * functions. Use gcc. It also assumes ds=es=data space, this should be * normal. Most of the string-functions are rather heavily hand-optimized, - * see especially strtok,strstr,str[c]spn. They should work, but are not + * see especially strsep,strstr,str[c]spn. They should work, but are not * very easy to understand. Everything is done entirely within the register * set, making the functions fast and clean. String instructions have been * used through-out, making for "slightly" unclear code :-) diff --git a/include/asm-i386/thread_info.h b/include/asm-i386/thread_info.h index 0359b0948f97..b6948b3c8c26 100644 --- a/include/asm-i386/thread_info.h +++ b/include/asm-i386/thread_info.h @@ -47,6 +47,8 @@ struct thread_info { #endif +#define PREEMPT_ACTIVE 0x4000000 + /* * macros/functions for gaining access to the thread information structure */ diff --git a/include/asm-i386/timex.h b/include/asm-i386/timex.h index 97099dd0d414..6cfc7c9a08fc 100644 --- a/include/asm-i386/timex.h +++ b/include/asm-i386/timex.h @@ -9,7 +9,12 @@ #include <linux/config.h> #include <asm/msr.h> -#define CLOCK_TICK_RATE 1193180 /* Underlying HZ */ +#ifdef CONFIG_MELAN +# define CLOCK_TICK_RATE 1189200 /* AMD Elan has different frequency! */ +#else +# define CLOCK_TICK_RATE 1193180 /* Underlying HZ */ +#endif + #define CLOCK_TICK_FACTOR 20 /* Factor of both 1000000 and CLOCK_TICK_RATE */ #define FINETUNE ((((((long)LATCH * HZ - CLOCK_TICK_RATE) << SHIFT_HZ) * \ (1000000/CLOCK_TICK_FACTOR) / (CLOCK_TICK_RATE/CLOCK_TICK_FACTOR)) \ diff --git a/include/asm-i386/tlbflush.h b/include/asm-i386/tlbflush.h new file mode 100644 index 000000000000..f05abd2f437a --- /dev/null +++ b/include/asm-i386/tlbflush.h @@ -0,0 +1,141 @@ +#ifndef _I386_TLBFLUSH_H +#define _I386_TLBFLUSH_H + +#include <linux/config.h> +#include <linux/mm.h> +#include <asm/processor.h> + +#define __flush_tlb() \ + do { \ + unsigned int tmpreg; \ + \ + __asm__ __volatile__( \ + "movl %%cr3, %0; # flush TLB \n" \ + "movl %0, %%cr3; \n" \ + : "=r" (tmpreg) \ + :: "memory"); \ + } while (0) + +/* + * Global pages have to be flushed a bit differently. Not a real + * performance problem because this does not happen often. + */ +#define __flush_tlb_global() \ + do { \ + unsigned int tmpreg; \ + \ + __asm__ __volatile__( \ + "movl %1, %%cr4; # turn off PGE \n" \ + "movl %%cr3, %0; # flush TLB \n" \ + "movl %0, %%cr3; \n" \ + "movl %2, %%cr4; # turn PGE back on \n" \ + : "=&r" (tmpreg) \ + : "r" (mmu_cr4_features & ~X86_CR4_PGE), \ + "r" (mmu_cr4_features) \ + : "memory"); \ + } while (0) + +extern unsigned long pgkern_mask; + +/* + * Do not check the PGE bit unnecesserily if this is a PPro+ kernel. + */ +#ifdef CONFIG_X86_PGE +# define __flush_tlb_all() __flush_tlb_global() +#else +# define __flush_tlb_all() \ + do { \ + if (cpu_has_pge) \ + __flush_tlb_global(); \ + else \ + __flush_tlb(); \ + } while (0) +#endif + +#ifndef CONFIG_X86_INVLPG +#define __flush_tlb_one(addr) __flush_tlb() +#else +#define __flush_tlb_one(addr) \ +__asm__ __volatile__("invlpg %0": :"m" (*(char *) addr)) +#endif + +/* + * TLB flushing: + * + * - flush_tlb() flushes the current mm struct TLBs + * - flush_tlb_all() flushes all processes TLBs + * - flush_tlb_mm(mm) flushes the specified mm context TLB's + * - flush_tlb_page(vma, vmaddr) flushes one page + * - flush_tlb_range(vma, start, end) flushes a range of pages + * - flush_tlb_pgtables(mm, start, end) flushes a range of page tables + * + * ..but the i386 has somewhat limited tlb flushing capabilities, + * and page-granular flushes are available only on i486 and up. + */ + +#ifndef CONFIG_SMP + +#define flush_tlb() __flush_tlb() +#define flush_tlb_all() __flush_tlb_all() +#define local_flush_tlb() __flush_tlb() + +static inline void flush_tlb_mm(struct mm_struct *mm) +{ + if (mm == current->active_mm) + __flush_tlb(); +} + +static inline void flush_tlb_page(struct vm_area_struct *vma, + unsigned long addr) +{ + if (vma->vm_mm == current->active_mm) + __flush_tlb_one(addr); +} + +static inline void flush_tlb_range(struct vm_area_struct *vma, + unsigned long start, unsigned long end) +{ + if (vma->vm_mm == current->active_mm) + __flush_tlb(); +} + +#else + +#include <asm/smp.h> + +#define local_flush_tlb() \ + __flush_tlb() + +extern void flush_tlb_all(void); +extern void flush_tlb_current_task(void); +extern void flush_tlb_mm(struct mm_struct *); +extern void flush_tlb_page(struct vm_area_struct *, unsigned long); + +#define flush_tlb() flush_tlb_current_task() + +static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end) +{ + flush_tlb_mm(vma->vm_mm); +} + +#define TLBSTATE_OK 1 +#define TLBSTATE_LAZY 2 + +struct tlb_state +{ + struct mm_struct *active_mm; + int state; + char __cacheline_padding[24]; +}; +extern struct tlb_state cpu_tlbstate[NR_CPUS]; + + +#endif + +static inline void flush_tlb_pgtables(struct mm_struct *mm, + unsigned long start, unsigned long end) +{ + /* i386 does not keep any page table caches in TLB */ +} + +#endif /* _I386_TLBFLUSH_H */ diff --git a/include/asm-ia64/efi.h b/include/asm-ia64/efi.h index 3157aaa68c01..189f7bcfd035 100644 --- a/include/asm-ia64/efi.h +++ b/include/asm-ia64/efi.h @@ -32,13 +32,18 @@ typedef unsigned long efi_status_t; typedef u8 efi_bool_t; typedef u16 efi_char16_t; /* UNICODE character */ + typedef struct { - u32 data1; - u16 data2; - u16 data3; - u8 data4[8]; + u8 b[16]; } efi_guid_t; +#define EFI_GUID(a,b,c,d0,d1,d2,d3,d4,d5,d6,d7) \ +((efi_guid_t) \ +{{ (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >> 24) & 0xff, \ + (b) & 0xff, ((b) >> 8) & 0xff, \ + (c) & 0xff, ((c) >> 8) & 0xff, \ + (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }}) + /* * Generic EFI table header */ @@ -165,21 +170,23 @@ typedef void efi_reset_system_t (int reset_type, efi_status_t status, /* * EFI Configuration Table and GUID definitions */ +#define NULL_GUID \ + EFI_GUID( 0x00000000, 0x0000, 0x0000, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ) #define MPS_TABLE_GUID \ - ((efi_guid_t) { 0xeb9d2d2f, 0x2d88, 0x11d3, { 0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d }}) + EFI_GUID( 0xeb9d2d2f, 0x2d88, 0x11d3, 0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d ) #define ACPI_TABLE_GUID \ - ((efi_guid_t) { 0xeb9d2d30, 0x2d88, 0x11d3, { 0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d }}) + EFI_GUID( 0xeb9d2d30, 0x2d88, 0x11d3, 0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d ) #define ACPI_20_TABLE_GUID \ - ((efi_guid_t) { 0x8868e871, 0xe4f1, 0x11d3, { 0xbc, 0x22, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 }}) + EFI_GUID( 0x8868e871, 0xe4f1, 0x11d3, 0xbc, 0x22, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 ) #define SMBIOS_TABLE_GUID \ - ((efi_guid_t) { 0xeb9d2d31, 0x2d88, 0x11d3, { 0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d }}) + EFI_GUID( 0xeb9d2d31, 0x2d88, 0x11d3, 0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d ) #define SAL_SYSTEM_TABLE_GUID \ - ((efi_guid_t) { 0xeb9d2d32, 0x2d88, 0x11d3, { 0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d }}) + EFI_GUID( 0xeb9d2d32, 0x2d88, 0x11d3, 0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d ) typedef struct { efi_guid_t guid; @@ -233,6 +240,17 @@ efi_guidcmp (efi_guid_t left, efi_guid_t right) return memcmp(&left, &right, sizeof (efi_guid_t)); } +static inline char * +efi_guid_unparse(efi_guid_t *guid, char *out) +{ + sprintf(out, "%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x", + guid->b[3], guid->b[2], guid->b[1], guid->b[0], + guid->b[5], guid->b[4], guid->b[7], guid->b[6], + guid->b[8], guid->b[9], guid->b[10], guid->b[11], + guid->b[12], guid->b[13], guid->b[14], guid->b[15]); + return out; +} + extern void efi_init (void); extern void efi_map_pal_code (void); extern void efi_memmap_walk (efi_freemem_callback_t callback, void *arg); diff --git a/include/asm-ia64/sal.h b/include/asm-ia64/sal.h index 570fa428ad7e..a778a84561cf 100644 --- a/include/asm-ia64/sal.h +++ b/include/asm-ia64/sal.h @@ -241,32 +241,32 @@ enum { /* SAL Error Record Section GUID Definitions */ #define SAL_PROC_DEV_ERR_SECT_GUID \ - ((efi_guid_t) { 0xe429faf1, 0x3cb7, 0x11d4, { 0xbc, 0xa7, 0x0, 0x80, \ - 0xc7, 0x3c, 0x88, 0x81 }} ) + EFI_GUID ( 0xe429faf1, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, \ + 0xc7, 0x3c, 0x88, 0x81 ) #define SAL_PLAT_MEM_DEV_ERR_SECT_GUID \ - ((efi_guid_t) { 0xe429faf2, 0x3cb7, 0x11d4, { 0xbc, 0xa7, 0x0, 0x80, \ - 0xc7, 0x3c, 0x88, 0x81 }} ) + EFI_GUID( 0xe429faf2, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, \ + 0xc7, 0x3c, 0x88, 0x81 ) #define SAL_PLAT_SEL_DEV_ERR_SECT_GUID \ - ((efi_guid_t) { 0xe429faf3, 0x3cb7, 0x11d4, { 0xbc, 0xa7, 0x0, 0x80, \ - 0xc7, 0x3c, 0x88, 0x81 }} ) + EFI_GUID( 0xe429faf3, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, \ + 0xc7, 0x3c, 0x88, 0x81 ) #define SAL_PLAT_PCI_BUS_ERR_SECT_GUID \ - ((efi_guid_t) { 0xe429faf4, 0x3cb7, 0x11d4, { 0xbc, 0xa7, 0x0, 0x80, \ - 0xc7, 0x3c, 0x88, 0x81 }} ) + EFI_GUID( 0xe429faf4, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, \ + 0xc7, 0x3c, 0x88, 0x81 ) #define SAL_PLAT_SMBIOS_DEV_ERR_SECT_GUID \ - ((efi_guid_t) { 0xe429faf5, 0x3cb7, 0x11d4, { 0xbc, 0xa7, 0x0, 0x80, \ - 0xc7, 0x3c, 0x88, 0x81 }} ) + EFI_GUID( 0xe429faf5, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, \ + 0xc7, 0x3c, 0x88, 0x81 ) #define SAL_PLAT_PCI_COMP_ERR_SECT_GUID \ - ((efi_guid_t) { 0xe429faf6, 0x3cb7, 0x11d4, { 0xbc, 0xa7, 0x0, 0x80, \ - 0xc7, 0x3c, 0x88, 0x81 }} ) + EFI_GUID( 0xe429faf6, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, \ + 0xc7, 0x3c, 0x88, 0x81 ) #define SAL_PLAT_SPECIFIC_ERR_SECT_GUID \ - ((efi_guid_t) { 0xe429faf7, 0x3cb7, 0x11d4, { 0xbc, 0xa7, 0x0, 0x80, \ - 0xc7, 0x3c, 0x88, 0x81 }} ) + EFI_GUID( 0xe429faf7, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, \ + 0xc7, 0x3c, 0x88, 0x81 ) #define SAL_PLAT_HOST_CTLR_ERR_SECT_GUID \ - ((efi_guid_t) { 0xe429faf8, 0x3cb7, 0x11d4, { 0xbc, 0xa7, 0x0, 0x80, \ - 0xc7, 0x3c, 0x88, 0x81 }} ) + EFI_GUID( 0xe429faf8, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, \ + 0xc7, 0x3c, 0x88, 0x81 ) #define SAL_PLAT_BUS_ERR_SECT_GUID \ - ((efi_guid_t) { 0xe429faf9, 0x3cb7, 0x11d4, { 0xbc, 0xa7, 0x0, 0x80, \ - 0xc7, 0x3c, 0x88, 0x81 }} ) + EFI_GUID( 0xe429faf9, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, \ + 0xc7, 0x3c, 0x88, 0x81 ) #define MAX_CACHE_ERRORS 6 #define MAX_TLB_ERRORS 6 diff --git a/include/asm-m68k/string.h b/include/asm-m68k/string.h index 5183aa0096d8..5604739225b3 100644 --- a/include/asm-m68k/string.h +++ b/include/asm-m68k/string.h @@ -117,29 +117,6 @@ static inline size_t strspn(const char *s, const char *accept) } #endif -#if 0 -#define __HAVE_ARCH_STRTOK -extern inline char * strtok(char * s,const char * ct) -{ - char *sbegin, *send; - - sbegin = s ? s : ___strtok; - if (!sbegin) { - return NULL; - } - sbegin += strspn(sbegin,ct); - if (*sbegin == '\0') { - ___strtok = NULL; - return( NULL ); - } - send = strpbrk( sbegin, ct); - if (send && *send != '\0') - *send++ = '\0'; - ___strtok = send; - return (sbegin); -} -#endif - /* strstr !! */ #define __HAVE_ARCH_STRLEN diff --git a/include/asm-mips/spinlock.h b/include/asm-mips/spinlock.h index 61ebfa6603eb..fb02686f7896 100644 --- a/include/asm-mips/spinlock.h +++ b/include/asm-mips/spinlock.h @@ -19,10 +19,10 @@ typedef struct { #define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 } -#define spin_lock_init(x) do { (x)->lock = 0; } while(0); +#define spin_lock_init(x) do { (x)->lock = 0; } while(0) #define spin_is_locked(x) ((x)->lock != 0) -#define spin_unlock_wait(x) ({ do { barrier(); } while ((x)->lock); }) +#define spin_unlock_wait(x) do { barrier(); } while ((x)->lock) /* * Simple spin lock operations. There are two variants, one clears IRQ's diff --git a/include/asm-mips64/spinlock.h b/include/asm-mips64/spinlock.h index 7e560d4c05a4..9ce6c6c2e13c 100644 --- a/include/asm-mips64/spinlock.h +++ b/include/asm-mips64/spinlock.h @@ -19,10 +19,10 @@ typedef struct { #define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 } -#define spin_lock_init(x) do { (x)->lock = 0; } while(0); +#define spin_lock_init(x) do { (x)->lock = 0; } while(0) #define spin_is_locked(x) ((x)->lock != 0) -#define spin_unlock_wait(x) ({ do { barrier(); } while ((x)->lock); }) +#define spin_unlock_wait(x) do { barrier(); } while ((x)->lock) /* * Simple spin lock operations. There are two variants, one clears IRQ's diff --git a/include/asm-parisc/pgalloc.h b/include/asm-parisc/pgalloc.h index b29fa8aef9be..37e7511bedd7 100644 --- a/include/asm-parisc/pgalloc.h +++ b/include/asm-parisc/pgalloc.h @@ -123,7 +123,7 @@ extern void flush_instruction_tlb(void); #define flush_tlb() do { \ flush_data_tlb(); \ flush_instruction_tlb(); \ -} while(0); +} while(0) #define flush_tlb_all() flush_tlb() /* XXX p[id]tlb */ diff --git a/include/asm-sparc/elf.h b/include/asm-sparc/elf.h index 436d1a9ad56b..d6e8a340495d 100644 --- a/include/asm-sparc/elf.h +++ b/include/asm-sparc/elf.h @@ -41,7 +41,7 @@ do { unsigned long *dest = &(__elf_regs[0]); \ dest[34] = src->npc; \ dest[35] = src->y; \ dest[36] = dest[37] = 0; /* XXX */ \ -} while(0); +} while(0) typedef struct { union { diff --git a/include/asm-sparc/pgtable.h b/include/asm-sparc/pgtable.h index 518f15379394..b73aaa20847e 100644 --- a/include/asm-sparc/pgtable.h +++ b/include/asm-sparc/pgtable.h @@ -293,6 +293,9 @@ BTFIXUPDEF_CALL_CONST(pte_t, pte_mkyoung, pte_t) #define page_pte_prot(page, prot) mk_pte(page, prot) #define page_pte(page) page_pte_prot(page, __pgprot(0)) +/* Permanent address of a page. */ +#define page_address(page) ((page)->virtual) + BTFIXUPDEF_CALL(struct page *, pte_page, pte_t) #define pte_page(pte) BTFIXUP_CALL(pte_page)(pte) diff --git a/include/asm-sparc/sbus.h b/include/asm-sparc/sbus.h index 6a687a465c21..d26fd0326a03 100644 --- a/include/asm-sparc/sbus.h +++ b/include/asm-sparc/sbus.h @@ -94,7 +94,8 @@ sbus_is_slave(struct sbus_dev *dev) for((device) = (bus)->devices; (device); (device)=(device)->next) #define for_all_sbusdev(device, bus) \ - for((bus) = sbus_root, ((device) = (bus) ? (bus)->devices : 0); (bus); (device)=((device)->next ? (device)->next : ((bus) = (bus)->next, (bus) ? (bus)->devices : 0))) + for ((bus) = sbus_root; (bus); (bus) = (bus)->next) \ + for ((device) = (bus)->devices; (device); (device) = (device)->next) /* Driver DVMA interfaces. */ #define sbus_can_dma_64bit(sdev) (0) /* actually, sparc_cpu_model==sun4d */ diff --git a/include/asm-sparc64/pgalloc.h b/include/asm-sparc64/pgalloc.h index d2909390fc6d..7f3f59461552 100644 --- a/include/asm-sparc64/pgalloc.h +++ b/include/asm-sparc64/pgalloc.h @@ -10,13 +10,6 @@ #include <asm/spitfire.h> #include <asm/pgtable.h> -#define VPTE_BASE_SPITFIRE 0xfffffffe00000000 -#if 1 -#define VPTE_BASE_CHEETAH VPTE_BASE_SPITFIRE -#else -#define VPTE_BASE_CHEETAH 0xffe0000000000000 -#endif - static __inline__ void flush_tlb_pgtables(struct mm_struct *mm, unsigned long start, unsigned long end) { @@ -42,8 +35,6 @@ static __inline__ void flush_tlb_pgtables(struct mm_struct *mm, unsigned long st vpte_base + (e >> (PAGE_SHIFT - 3))); } } -#undef VPTE_BASE_SPITFIRE -#undef VPTE_BASE_CHEETAH /* Page table allocation/freeing. */ #ifdef CONFIG_SMP diff --git a/include/asm-sparc64/pgtable.h b/include/asm-sparc64/pgtable.h index e0003653a4f5..50aff488dd95 100644 --- a/include/asm-sparc64/pgtable.h +++ b/include/asm-sparc64/pgtable.h @@ -48,6 +48,8 @@ extern void flush_cache_range(struct vm_area_struct *, unsigned long, unsigned l flush_cache_mm((vma)->vm_mm) +struct page; + /* * On spitfire, the icache doesn't snoop local stores and we don't * use block commit stores (which invalidate icache lines) during diff --git a/include/asm-sparc64/processor.h b/include/asm-sparc64/processor.h index 1815502bf700..2f9061f38856 100644 --- a/include/asm-sparc64/processor.h +++ b/include/asm-sparc64/processor.h @@ -39,9 +39,25 @@ * address that the kernel will allocate out. */ #define VA_BITS 44 +#ifndef __ASSEMBLY__ #define VPTE_SIZE (1UL << (VA_BITS - PAGE_SHIFT + 3)) +#else +#define VPTE_SIZE (1 << (VA_BITS - PAGE_SHIFT + 3)) +#endif #define TASK_SIZE ((unsigned long)-VPTE_SIZE) +/* + * The vpte base must be able to hold the entire vpte, half + * of which lives above, and half below, the base. And it + * is placed as close to the highest address range as possible. + */ +#define VPTE_BASE_SPITFIRE (-(VPTE_SIZE/2)) +#if 1 +#define VPTE_BASE_CHEETAH VPTE_BASE_SPITFIRE +#else +#define VPTE_BASE_CHEETAH 0xffe0000000000000 +#endif + #ifndef __ASSEMBLY__ typedef struct { diff --git a/include/asm-sparc64/sbus.h b/include/asm-sparc64/sbus.h index e9f7344b47cf..5970645950ab 100644 --- a/include/asm-sparc64/sbus.h +++ b/include/asm-sparc64/sbus.h @@ -87,7 +87,8 @@ extern struct sbus_bus *sbus_root; for((device) = (bus)->devices; (device); (device)=(device)->next) #define for_all_sbusdev(device, bus) \ - for((bus) = sbus_root, ((device) = (bus) ? (bus)->devices : 0); (bus); (device)=((device)->next ? (device)->next : ((bus) = (bus)->next, (bus) ? (bus)->devices : 0))) + for ((bus) = sbus_root; (bus); (bus) = (bus)->next) \ + for ((device) = (bus)->devices; (device); (device) = (device)->next) /* Driver DVMA interfaces. */ #define sbus_can_dma_64bit(sdev) (1) diff --git a/include/linux/device.h b/include/linux/device.h index f8234fdff19f..96d9cb108139 100644 --- a/include/linux/device.h +++ b/include/linux/device.h @@ -64,6 +64,7 @@ struct device_driver { }; struct device { + struct list_head g_list; /* node in depth-first order list */ struct list_head node; /* node in sibling list */ struct list_head children; struct device * parent; @@ -83,7 +84,7 @@ struct device { device */ void *driver_data; /* data private to the driver */ void *platform_data; /* Platform specific data (e.g. ACPI, - BIOS data relevant to device */ + BIOS data relevant to device) */ u32 current_state; /* Current operating state. In ACPI-speak, this is D0-D3, D0 @@ -99,6 +100,12 @@ list_to_dev(struct list_head *node) return list_entry(node, struct device, node); } +static inline struct device * +g_list_to_dev(struct list_head *g_list) +{ + return list_entry(g_list, struct device, g_list); +} + /* * High level routines for use by the bus drivers */ @@ -143,4 +150,13 @@ static inline void get_device(struct device * dev) extern void put_device(struct device * dev); +/* drivers/base/sys.c */ +extern int register_sys_device(struct device * dev); +extern void unregister_sys_device(struct device * dev); + +/* drivers/base/power.c */ +extern int device_suspend(u32 state, u32 level); +extern void device_resume(u32 level); +extern void device_shutdown(void); + #endif /* _DEVICE_H_ */ diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h index 192959f7477d..6f8ebf32d744 100644 --- a/include/linux/ethtool.h +++ b/include/linux/ethtool.h @@ -36,7 +36,8 @@ struct ethtool_drvinfo { char bus_info[ETHTOOL_BUSINFO_LEN]; /* Bus info for this IF. */ /* For PCI devices, use pci_dev->slot_name. */ char reserved1[32]; - char reserved2[24]; + char reserved2[20]; + u32 testinfo_len; u32 eedump_len; /* Size of data from ETHTOOL_GEEPROM (bytes) */ u32 regdump_len; /* Size of data from ETHTOOL_GREGS (bytes) */ }; @@ -210,6 +211,34 @@ struct ethtool_pauseparam { u32 tx_pause; }; +#define ETH_GSTRING_LEN 32 +enum ethtool_stringset { + ETH_SS_TEST = 0, + ETH_SS_STATS, +}; + +/* for passing string sets for data tagging */ +struct ethtool_gstrings { + u32 cmd; /* ETHTOOL_GSTRINGS */ + u32 string_set; /* string set id e.c. ETH_SS_TEST, etc*/ + u32 len; /* number of strings in the string set */ + u8 data[0]; +}; + +enum ethtool_test_flags { + ETH_TEST_FL_OFFLINE = (1 << 0), /* online / offline */ + ETH_TEST_FL_FAILED = (1 << 1), /* test passed / failed */ +}; + +/* for requesting NIC test and getting results*/ +struct ethtool_test { + u32 cmd; /* ETHTOOL_TEST */ + u32 flags; /* ETH_TEST_FL_xxx */ + u32 reserved; + u32 len; /* result length, in number of u64 elements */ + u64 data[0]; +}; + /* CMDs currently supported */ #define ETHTOOL_GSET 0x00000001 /* Get settings. */ #define ETHTOOL_SSET 0x00000002 /* Set settings, privileged. */ @@ -222,13 +251,13 @@ struct ethtool_pauseparam { #define ETHTOOL_NWAY_RST 0x00000009 /* Restart autonegotiation, priv. */ #define ETHTOOL_GLINK 0x0000000a /* Get link status (ethtool_value) */ #define ETHTOOL_GEEPROM 0x0000000b /* Get EEPROM data */ -#define ETHTOOL_SEEPROM 0x0000000c /* Set EEPROM data */ +#define ETHTOOL_SEEPROM 0x0000000c /* Set EEPROM data, priv. */ #define ETHTOOL_GCOALESCE 0x0000000e /* Get coalesce config */ -#define ETHTOOL_SCOALESCE 0x0000000f /* Set coalesce config */ +#define ETHTOOL_SCOALESCE 0x0000000f /* Set coalesce config, priv. */ #define ETHTOOL_GRINGPARAM 0x00000010 /* Get ring parameters */ -#define ETHTOOL_SRINGPARAM 0x00000011 /* Set ring parameters */ +#define ETHTOOL_SRINGPARAM 0x00000011 /* Set ring parameters, priv. */ #define ETHTOOL_GPAUSEPARAM 0x00000012 /* Get pause parameters */ -#define ETHTOOL_SPAUSEPARAM 0x00000013 /* Set pause parameters */ +#define ETHTOOL_SPAUSEPARAM 0x00000013 /* Set pause parameters, priv. */ #define ETHTOOL_GRXCSUM 0x00000014 /* Get RX hw csum enable (ethtool_value) */ #define ETHTOOL_SRXCSUM 0x00000015 /* Set RX hw csum enable (ethtool_value) */ #define ETHTOOL_GTXCSUM 0x00000016 /* Get TX hw csum enable (ethtool_value) */ @@ -236,7 +265,9 @@ struct ethtool_pauseparam { #define ETHTOOL_GSG 0x00000018 /* Get scatter-gather enable * (ethtool_value) */ #define ETHTOOL_SSG 0x00000019 /* Set scatter-gather enable - * (ethtool_value) */ + * (ethtool_value), priv. */ +#define ETHTOOL_TEST 0x0000001a /* execute NIC self-test, priv. */ +#define ETHTOOL_GSTRINGS 0x0000001b /* get specified string set */ /* compatibility with older code */ #define SPARC_ETH_GSET ETHTOOL_GSET diff --git a/include/linux/ext3_fs_sb.h b/include/linux/ext3_fs_sb.h index cf248c3aae41..6bda514a7a54 100644 --- a/include/linux/ext3_fs_sb.h +++ b/include/linux/ext3_fs_sb.h @@ -61,6 +61,7 @@ struct ext3_sb_info { int s_desc_per_block_bits; int s_inode_size; int s_first_ino; + u32 s_next_generation; /* Journaling */ struct inode * s_journal_inode; diff --git a/include/linux/fs.h b/include/linux/fs.h index 375d53dd69e9..2031f5cbde19 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -650,7 +650,6 @@ struct quota_mount_options #include <linux/ufs_fs_sb.h> #include <linux/romfs_fs_sb.h> #include <linux/adfs_fs_sb.h> -#include <linux/reiserfs_fs_sb.h> #include <linux/bfs_fs_sb.h> extern struct list_head super_blocks; @@ -663,6 +662,7 @@ struct super_block { kdev_t s_dev; unsigned long s_blocksize; unsigned char s_blocksize_bits; + unsigned long s_old_blocksize; unsigned char s_dirt; unsigned long long s_maxbytes; /* Max file size */ struct file_system_type *s_type; @@ -693,7 +693,6 @@ struct super_block { struct ufs_sb_info ufs_sb; struct romfs_sb_info romfs_sb; struct adfs_sb_info adfs_sb; - struct reiserfs_sb_info reiserfs_sb; struct bfs_sb_info bfs_sb; void *generic_sbp; } u; diff --git a/include/linux/hdreg.h b/include/linux/hdreg.h index 8c847b572601..73de808b4749 100644 --- a/include/linux/hdreg.h +++ b/include/linux/hdreg.h @@ -54,16 +54,9 @@ * HDIO_DRIVE_CMD and HDIO_DRIVE_TASK */ -#if 0 -#include <asm/hdreg.h> -typedef ide_ioreg_t task_ioreg_t; -#else -typedef unsigned char task_ioreg_t; -#endif - -#define HDIO_DRIVE_CMD_HDR_SIZE 4*sizeof(task_ioreg_t) -#define HDIO_DRIVE_TASK_HDR_SIZE 8*sizeof(task_ioreg_t) -#define HDIO_DRIVE_HOB_HDR_SIZE 8*sizeof(task_ioreg_t) +#define HDIO_DRIVE_CMD_HDR_SIZE (4 * sizeof(u8)) +#define HDIO_DRIVE_TASK_HDR_SIZE (8 * sizeof(u8)) +#define HDIO_DRIVE_HOB_HDR_SIZE (8 * sizeof(u8)) #define IDE_DRIVE_TASK_INVALID -1 #define IDE_DRIVE_TASK_NO_DATA 0 @@ -74,57 +67,27 @@ typedef unsigned char task_ioreg_t; #define IDE_DRIVE_TASK_OUT 3 #define IDE_DRIVE_TASK_RAW_WRITE 4 -struct hd_drive_cmd_hdr { - task_ioreg_t command; - task_ioreg_t sector_number; - task_ioreg_t feature; - task_ioreg_t sector_count; -}; - -typedef struct hd_drive_task_hdr { - task_ioreg_t data; - task_ioreg_t feature; - task_ioreg_t sector_count; - task_ioreg_t sector_number; - task_ioreg_t low_cylinder; - task_ioreg_t high_cylinder; - task_ioreg_t device_head; - task_ioreg_t command; -} task_struct_t; - -typedef struct hd_drive_hob_hdr { - task_ioreg_t data; - task_ioreg_t feature; - task_ioreg_t sector_count; - task_ioreg_t sector_number; - task_ioreg_t low_cylinder; - task_ioreg_t high_cylinder; - task_ioreg_t device_head; - task_ioreg_t control; -} hob_struct_t; - -typedef union ide_reg_valid_s { - unsigned all : 16; - struct { - unsigned data : 1; - unsigned error_feature : 1; - unsigned sector : 1; - unsigned nsector : 1; - unsigned lcyl : 1; - unsigned hcyl : 1; - unsigned select : 1; - unsigned status_command : 1; - - unsigned data_hob : 1; - unsigned error_feature_hob : 1; - unsigned sector_hob : 1; - unsigned nsector_hob : 1; - unsigned lcyl_hob : 1; - unsigned hcyl_hob : 1; - unsigned select_hob : 1; - unsigned control_hob : 1; - } b; -} ide_reg_valid_t; +struct hd_drive_task_hdr { + u8 data; + u8 feature; + u8 sector_count; + u8 sector_number; + u8 low_cylinder; + u8 high_cylinder; + u8 device_head; + u8 command; +} __attribute__((packed)); + +struct hd_drive_hob_hdr { + u8 data; + u8 feature; + u8 sector_count; + u8 sector_number; + u8 low_cylinder; + u8 high_cylinder; + u8 device_head; + u8 control; +} __attribute__((packed)); /* * Define standard taskfile in/out register @@ -134,23 +97,6 @@ typedef union ide_reg_valid_s { #define IDE_HOB_STD_OUT_FLAGS 0xC0 #define IDE_HOB_STD_IN_FLAGS 0xC0 -typedef struct ide_task_request_s { - task_ioreg_t io_ports[8]; - task_ioreg_t hob_ports[8]; - ide_reg_valid_t out_flags; - ide_reg_valid_t in_flags; - int data_phase; - int req_cmd; - unsigned long out_size; - unsigned long in_size; -} ide_task_request_t; - -typedef struct ide_ioctl_request_s { - ide_task_request_t *task_request; - unsigned char *out_buffer; - unsigned char *in_buffer; -} ide_ioctl_request_t; - #define TASKFILE_INVALID 0x7fff #define TASKFILE_48 0x8000 @@ -212,7 +158,7 @@ typedef struct ide_ioctl_request_s { #define WIN_PIDENTIFY 0xA1 /* identify ATAPI device */ #define WIN_QUEUED_SERVICE 0xA2 #define WIN_SMART 0xB0 /* self-monitoring and reporting */ -#define CFA_ERASE_SECTORS 0xC0 +#define CFA_ERASE_SECTORS 0xC0 #define WIN_MULTREAD 0xC4 /* read sectors using multiple mode*/ #define WIN_MULTWRITE 0xC5 /* write sectors using multiple mode */ #define WIN_SETMULT 0xC6 /* enable/disable multiple mode */ @@ -221,12 +167,12 @@ typedef struct ide_ioctl_request_s { #define WIN_WRITEDMA 0xCA /* write sectors using DMA transfers */ #define WIN_WRITEDMA_QUEUED 0xCC /* write sectors using Queued DMA transfers */ #define CFA_WRITE_MULTI_WO_ERASE 0xCD /* CFA Write multiple without erase */ -#define WIN_GETMEDIASTATUS 0xDA +#define WIN_GETMEDIASTATUS 0xDA #define WIN_DOORLOCK 0xDE /* lock door on removable drives */ #define WIN_DOORUNLOCK 0xDF /* unlock door on removable drives */ #define WIN_STANDBYNOW1 0xE0 #define WIN_IDLEIMMEDIATE 0xE1 /* force drive to become "ready" */ -#define WIN_STANDBY 0xE2 /* Set device in Standby Mode */ +#define WIN_STANDBY 0xE2 /* Set device in Standby Mode */ #define WIN_SETIDLE1 0xE3 #define WIN_READ_BUFFER 0xE4 /* force read only 1 sector */ #define WIN_CHECKPOWERMODE1 0xE5 @@ -268,7 +214,7 @@ typedef struct ide_ioctl_request_s { #define SMART_LCYL_PASS 0x4F #define SMART_HCYL_PASS 0xC2 - + /* WIN_SETFEATURES sub-commands */ #define SETFEATURES_EN_WCACHE 0x02 /* Enable write cache */ @@ -638,8 +584,5 @@ struct hd_driveid { */ #define IDE_NICE_DSC_OVERLAP (0) /* per the DSC overlap protocol */ #define IDE_NICE_ATAPI_OVERLAP (1) /* not supported yet */ -#define IDE_NICE_0 (2) /* when sure that it won't affect us */ -#define IDE_NICE_1 (3) /* when probably won't affect us much */ -#define IDE_NICE_2 (4) /* when we know it's on our expense */ #endif /* _LINUX_HDREG_H */ diff --git a/include/linux/hiddev.h b/include/linux/hiddev.h index 4f57c1174598..eb948560836d 100644 --- a/include/linux/hiddev.h +++ b/include/linux/hiddev.h @@ -119,13 +119,17 @@ struct hiddev_usage_ref { __s32 value; }; +/* FIELD_INDEX_NONE is returned in read() data from the kernel when flags + * is set to (HIDDEV_FLAG_UREF | HIDDEV_FLAG_REPORT) and a new report has + * been sent by the device + */ #define HID_FIELD_INDEX_NONE 0xffffffff /* * Protocol version. */ -#define HID_VERSION 0x010002 +#define HID_VERSION 0x010003 /* * IOCTLs (0x00 - 0x7f) @@ -139,20 +143,20 @@ struct hiddev_usage_ref { #define HIDIOCGNAME(len) _IOC(_IOC_READ, 'H', 0x06, len) #define HIDIOCGREPORT _IOW('H', 0x07, struct hiddev_report_info) #define HIDIOCSREPORT _IOW('H', 0x08, struct hiddev_report_info) -#define HIDIOCGREPORTINFO _IOWR('H', 0x09, struct hiddev_report_info) -#define HIDIOCGFIELDINFO _IOWR('H', 0x0A, struct hiddev_field_info) -#define HIDIOCGUSAGE _IOWR('H', 0x0B, struct hiddev_usage_ref) -#define HIDIOCSUSAGE _IOW('H', 0x0C, struct hiddev_usage_ref) -#define HIDIOCGUCODE _IOWR('H', 0x0D, struct hiddev_usage_ref) -#define HIDIOCGFLAG _IOR('H', 0x0E, int) -#define HIDIOCSFLAG _IOW('H', 0x0F, int) +#define HIDIOCGREPORTINFO _IOWR('H', 0x09, struct hiddev_report_info) +#define HIDIOCGFIELDINFO _IOWR('H', 0x0A, struct hiddev_field_info) +#define HIDIOCGUSAGE _IOWR('H', 0x0B, struct hiddev_usage_ref) +#define HIDIOCSUSAGE _IOW('H', 0x0C, struct hiddev_usage_ref) +#define HIDIOCGUCODE _IOWR('H', 0x0D, struct hiddev_usage_ref) +#define HIDIOCGFLAG _IOR('H', 0x0E, int) +#define HIDIOCSFLAG _IOW('H', 0x0F, int) /* * Flags to be used in HIDIOCSFLAG */ -#define HIDDEV_FLAG_UREF 0x1 -#define HIDDEV_FLAG_REPORT 0x2 -#define HIDDEV_FLAGS 0x3 +#define HIDDEV_FLAG_UREF 0x1 +#define HIDDEV_FLAG_REPORT 0x2 +#define HIDDEV_FLAGS 0x3 /* To traverse the input report descriptor info for a HID device, perform the * following: diff --git a/include/linux/highmem.h b/include/linux/highmem.h index bffa75c6ee5f..abe6fde56849 100644 --- a/include/linux/highmem.h +++ b/include/linux/highmem.h @@ -4,6 +4,7 @@ #include <linux/config.h> #include <linux/bio.h> #include <linux/fs.h> +#include <asm/cacheflush.h> #ifdef CONFIG_HIGHMEM diff --git a/include/linux/ide.h b/include/linux/ide.h index 6dafc47697ff..6d80160690b2 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -68,8 +68,8 @@ typedef unsigned char byte; /* used everywhere */ */ #define DMA_PIO_RETRY 1 /* retrying in PIO */ -#define HWIF(drive) ((drive)->hwif) -#define HWGROUP(drive) (HWIF(drive)->hwgroup) +#define HWIF(drive) ((drive)->channel) +#define HWGROUP(drive) (drive->channel->hwgroup) /* * Definitions for accessing IDE controller registers @@ -90,37 +90,16 @@ typedef unsigned char byte; /* used everywhere */ #define IDE_FEATURE_OFFSET IDE_ERROR_OFFSET #define IDE_COMMAND_OFFSET IDE_STATUS_OFFSET -#define IDE_DATA_OFFSET_HOB (0) -#define IDE_ERROR_OFFSET_HOB (1) -#define IDE_NSECTOR_OFFSET_HOB (2) -#define IDE_SECTOR_OFFSET_HOB (3) -#define IDE_LCYL_OFFSET_HOB (4) -#define IDE_HCYL_OFFSET_HOB (5) -#define IDE_SELECT_OFFSET_HOB (6) -#define IDE_CONTROL_OFFSET_HOB (7) - -#define IDE_FEATURE_OFFSET_HOB IDE_ERROR_OFFSET_HOB - -#define IDE_DATA_REG (HWIF(drive)->io_ports[IDE_DATA_OFFSET]) -#define IDE_ERROR_REG (HWIF(drive)->io_ports[IDE_ERROR_OFFSET]) -#define IDE_NSECTOR_REG (HWIF(drive)->io_ports[IDE_NSECTOR_OFFSET]) -#define IDE_SECTOR_REG (HWIF(drive)->io_ports[IDE_SECTOR_OFFSET]) -#define IDE_LCYL_REG (HWIF(drive)->io_ports[IDE_LCYL_OFFSET]) -#define IDE_HCYL_REG (HWIF(drive)->io_ports[IDE_HCYL_OFFSET]) -#define IDE_SELECT_REG (HWIF(drive)->io_ports[IDE_SELECT_OFFSET]) -#define IDE_STATUS_REG (HWIF(drive)->io_ports[IDE_STATUS_OFFSET]) -#define IDE_CONTROL_REG (HWIF(drive)->io_ports[IDE_CONTROL_OFFSET]) -#define IDE_IRQ_REG (HWIF(drive)->io_ports[IDE_IRQ_OFFSET]) - -#define IDE_DATA_REG_HOB (HWIF(drive)->io_ports[IDE_DATA_OFFSET]) -#define IDE_ERROR_REG_HOB (HWIF(drive)->io_ports[IDE_ERROR_OFFSET]) -#define IDE_NSECTOR_REG_HOB (HWIF(drive)->io_ports[IDE_NSECTOR_OFFSET]) -#define IDE_SECTOR_REG_HOB (HWIF(drive)->io_ports[IDE_SECTOR_OFFSET]) -#define IDE_LCYL_REG_HOB (HWIF(drive)->io_ports[IDE_LCYL_OFFSET]) -#define IDE_HCYL_REG_HOB (HWIF(drive)->io_ports[IDE_HCYL_OFFSET]) -#define IDE_SELECT_REG_HOB (HWIF(drive)->io_ports[IDE_SELECT_OFFSET]) -#define IDE_STATUS_REG_HOB (HWIF(drive)->io_ports[IDE_STATUS_OFFSET]) -#define IDE_CONTROL_REG_HOB (HWIF(drive)->io_ports[IDE_CONTROL_OFFSET]) +#define IDE_DATA_REG (drive->channel->io_ports[IDE_DATA_OFFSET]) +#define IDE_ERROR_REG (drive->channel->io_ports[IDE_ERROR_OFFSET]) +#define IDE_NSECTOR_REG (drive->channel->io_ports[IDE_NSECTOR_OFFSET]) +#define IDE_SECTOR_REG (drive->channel->io_ports[IDE_SECTOR_OFFSET]) +#define IDE_LCYL_REG (drive->channel->io_ports[IDE_LCYL_OFFSET]) +#define IDE_HCYL_REG (drive->channel->io_ports[IDE_HCYL_OFFSET]) +#define IDE_SELECT_REG (drive->channel->io_ports[IDE_SELECT_OFFSET]) +#define IDE_STATUS_REG (drive->channel->io_ports[IDE_STATUS_OFFSET]) +#define IDE_CONTROL_REG (drive->channel->io_ports[IDE_CONTROL_OFFSET]) +#define IDE_IRQ_REG (drive->channel->io_ports[IDE_IRQ_OFFSET]) #define IDE_FEATURE_REG IDE_ERROR_REG #define IDE_COMMAND_REG IDE_STATUS_REG @@ -175,24 +154,24 @@ typedef unsigned char byte; /* used everywhere */ #define WAIT_CMD (10*HZ) /* 10sec - maximum wait for an IRQ to happen */ #define WAIT_MIN_SLEEP (2*HZ/100) /* 20msec - minimum sleep time */ -#define SELECT_DRIVE(hwif,drive) \ +#define SELECT_DRIVE(channel, drive) \ { \ - if (hwif->selectproc) \ - hwif->selectproc(drive); \ - OUT_BYTE((drive)->select.all, hwif->io_ports[IDE_SELECT_OFFSET]); \ + if (channel->selectproc) \ + channel->selectproc(drive); \ + OUT_BYTE((drive)->select.all, channel->io_ports[IDE_SELECT_OFFSET]); \ } -#define SELECT_MASK(hwif,drive,mask) \ +#define SELECT_MASK(channel, drive, mask) \ { \ - if (hwif->maskproc) \ - hwif->maskproc(drive,mask); \ + if (channel->maskproc) \ + channel->maskproc(drive,mask); \ } /* * Check for an interrupt and acknowledge the interrupt status */ -struct hwif_s; -typedef int (ide_ack_intr_t)(struct hwif_s *); +struct ata_channel; +typedef int (ide_ack_intr_t)(struct ata_channel *); #ifndef NO_DMA # define NO_DMA 255 @@ -235,7 +214,6 @@ typedef struct hw_regs_s { int irq; /* our irq number */ int dma; /* our dma entry */ ide_ack_intr_t *ack_intr; /* acknowledge interrupt */ - void *priv; /* interface specific data */ hwif_chipset_t chipset; } hw_regs_t; @@ -291,20 +269,28 @@ typedef union { struct ide_settings_s; typedef struct ide_drive_s { - unsigned int usage; /* current "open()" count for drive */ + struct ata_channel *channel; /* parent pointer to the channel we are attached to */ + + unsigned int usage; /* current "open()" count for drive */ char type; /* distingiush different devices: disk, cdrom, tape, floppy, ... */ /* NOTE: If we had proper separation between channel and host chip, we * could move this to the chanell and many sync problems would * magically just go away. */ - request_queue_t queue; /* per device request queue */ + request_queue_t queue; /* per device request queue */ struct ide_drive_s *next; /* circular list of hwgroup drives */ - unsigned long sleep; /* sleep until this time */ - unsigned long service_start; /* time we started last request */ - unsigned long service_time; /* service time of last request */ - unsigned long timeout; /* max time to wait for irq */ + + /* Those are directly injected jiffie values. They should go away and + * we should use generic timers instead!!! + */ + + unsigned long PADAM_sleep; /* sleep until this time */ + unsigned long PADAM_service_start; /* time we started last request */ + unsigned long PADAM_service_time; /* service time of last request */ + unsigned long PADAM_timeout; /* max time to wait for irq */ + special_t special; /* special action flags */ byte keep_settings; /* restore settings after drive reset */ byte using_dma; /* disk is using dma for read/write */ @@ -314,11 +300,13 @@ typedef struct ide_drive_s { byte slow; /* flag: slow data port */ byte bswap; /* flag: byte swap data */ byte dsc_overlap; /* flag: DSC overlap */ - byte nice1; /* flag: give potential excess bandwidth */ + unsigned waiting_for_dma: 1; /* dma currently in progress */ + unsigned busy : 1; /* currently doing revalidate_disk() */ + unsigned blocked : 1; /* 1=powermanagment told us not to do anything, so sleep nicely */ + unsigned present : 1; /* drive is physically present */ unsigned noprobe : 1; /* from: hdx=noprobe */ - unsigned busy : 1; /* currently doing revalidate_disk() */ unsigned removable : 1; /* 1 if need to do check_media_change */ unsigned forced_geom : 1; /* 1 if hdx=c,h,s was given at boot */ unsigned no_unmask : 1; /* disallow setting unmask bit */ @@ -326,21 +314,18 @@ typedef struct ide_drive_s { unsigned nobios : 1; /* flag: do not probe bios for drive */ unsigned revalidate : 1; /* request revalidation */ unsigned atapi_overlap : 1; /* flag: ATAPI overlap (not supported) */ - unsigned nice0 : 1; /* flag: give obvious excess bandwidth */ - unsigned nice2 : 1; /* flag: give a share in our own bandwidth */ unsigned doorlocking : 1; /* flag: for removable only: door lock/unlock works */ unsigned autotune : 2; /* 1=autotune, 2=noautotune, 0=default */ unsigned remap_0_to_1 : 2; /* 0=remap if ezdrive, 1=remap, 2=noremap */ unsigned ata_flash : 1; /* 1=present, 0=default */ - unsigned blocked : 1; /* 1=powermanagment told us not to do anything, so sleep nicely */ unsigned addressing; /* : 2; 0=28-bit, 1=48-bit, 2=64-bit */ byte scsi; /* 0=default, 1=skip current ide-subdriver for ide-scsi emulation */ select_t select; /* basic drive/head select reg value */ byte ctl; /* "normal" value for IDE_CONTROL_REG */ byte ready_stat; /* min status value for drive ready */ byte mult_count; /* current multiple sector setting */ - byte mult_req; /* requested multiple sector setting */ - byte tune_req; /* requested drive tuning setting */ + byte mult_req; /* requested multiple sector setting */ + byte tune_req; /* requested drive tuning setting */ byte io_32bit; /* 0=16-bit, 1=32-bit, 2/3=32bit+sync */ byte bad_wstat; /* used for ignoring WRERR_STAT */ byte nowerr; /* used for ignoring WRERR_STAT */ @@ -354,20 +339,25 @@ typedef struct ide_drive_s { unsigned long capacity; /* total number of sectors */ unsigned long long capacity48; /* total number of sectors */ unsigned int drive_data; /* for use by tuneproc/selectproc as needed */ - struct hwif_s *hwif; /* parent pointer to the interface we are attached to */ + wait_queue_head_t wqueue; /* used to wait for drive in open() */ + struct hd_driveid *id; /* drive model identification info */ struct hd_struct *part; /* drive partition table */ + char name[4]; /* drive name, such as "hda" */ struct ata_operations *driver; + void *driver_data; /* extra driver data */ devfs_handle_t de; /* directory for device */ struct proc_dir_entry *proc; /* /proc/ide/ directory entry */ struct ide_settings_s *settings; /* /proc/ide/ drive settings */ char driver_req[10]; /* requests specific driver */ + int last_lun; /* last logical unit */ int forced_lun; /* if hdxlun was given at boot */ int lun; /* logical unit */ + int crc_count; /* crc counter to reduce drive speed */ byte quirk_list; /* drive is considered quirky if set for a specific host */ byte suspend_reset; /* drive suspend mode flag, soft-reset recovers */ @@ -409,7 +399,7 @@ typedef int (ide_dmaproc_t)(ide_dma_action_t, ide_drive_t *); * * If it is not defined for a controller, standard-code is used from ide.c. * - * Controllers which are not memory-mapped in the standard way need to + * Controllers which are not memory-mapped in the standard way need to * override that mechanism using this function to work. * */ @@ -448,11 +438,18 @@ typedef void (ide_rw_proc_t) (ide_drive_t *, ide_dma_action_t); */ typedef int (ide_busproc_t) (ide_drive_t *, int); -typedef struct hwif_s { - struct hwif_s *next; /* for linked-list in ide_hwgroup_t */ +struct ata_channel { + struct device dev; /* device handle */ + int unit; /* channel number */ + + struct ata_channel *next; /* for linked-list in ide_hwgroup_t */ struct hwgroup_s *hwgroup; /* actually (ide_hwgroup_t *) */ + ide_ioreg_t io_ports[IDE_NR_PORTS]; /* task file registers */ hw_regs_t hw; /* Hardware info */ +#ifdef CONFIG_BLK_DEV_IDEPCI + struct pci_dev *pci_dev; /* for pci chipsets */ +#endif ide_drive_t drives[MAX_DRIVES]; /* drive info */ struct gendisk *gd; /* gendisk structure */ ide_tuneproc_t *tuneproc; /* routine to tune PIO mode for drives */ @@ -470,7 +467,7 @@ typedef struct hwif_s { struct scatterlist *sg_table; /* Scatter-gather list used to build the above */ int sg_nents; /* Current number of entries in it */ int sg_dma_direction; /* dma transfer direction */ - struct hwif_s *mate; /* other hwif from same PCI chip */ + struct ata_channel *mate; /* other hwif from same PCI chip */ unsigned long dma_base; /* base addr for dma ports */ unsigned dma_extra; /* extra addr for dma ports */ unsigned long config_data; /* for use by chipset-specific code */ @@ -478,7 +475,7 @@ typedef struct hwif_s { struct proc_dir_entry *proc; /* /proc/ide/ directory entry */ int irq; /* our irq number */ int major; /* our major number */ - char name[80]; /* name of interface */ + char name[8]; /* name of interface */ int index; /* 0 for ide0; 1 for ide1; ... */ hwif_chipset_t chipset; /* sub-module for tuning.. */ unsigned noprobe : 1; /* don't probe for this interface */ @@ -489,24 +486,19 @@ typedef struct hwif_s { unsigned autodma : 1; /* automatically try to enable DMA at boot */ unsigned udma_four : 1; /* 1=ATA-66 capable, 0=default */ unsigned highmem : 1; /* can do full 32-bit dma */ - byte channel; /* for dual-port chips: 0=primary, 1=secondary */ -#ifdef CONFIG_BLK_DEV_IDEPCI - struct pci_dev *pci_dev; /* for pci chipsets */ -#endif #if (DISK_RECOVERY_TIME > 0) unsigned long last_time; /* time when previous rq was done */ #endif byte straight8; /* Alan's straight 8 check */ ide_busproc_t *busproc; /* driver soft-power interface */ byte bus_state; /* power state of the IDE bus */ - struct device device; /* global device tree handle */ -} ide_hwif_t; +}; /* * Register new hardware with ide */ -extern int ide_register_hw(hw_regs_t *hw, struct hwif_s **hwifp); -extern void ide_unregister(ide_hwif_t *hwif); +extern int ide_register_hw(hw_regs_t *hw, struct ata_channel **hwifp); +extern void ide_unregister(struct ata_channel *hwif); /* * Status returned from various ide_ functions @@ -536,7 +528,7 @@ typedef struct hwgroup_s { ide_handler_t *handler;/* irq handler, if active */ unsigned long flags; /* BUSY, SLEEPING */ ide_drive_t *drive; /* current drive */ - ide_hwif_t *hwif; /* ptr to current hwif in linked-list */ + struct ata_channel *hwif; /* ptr to current hwif in linked-list */ struct request *rq; /* current request */ struct timer_list timer; /* failsafe timer */ struct request wrq; /* local copy of current write rq */ @@ -595,7 +587,7 @@ typedef struct { #ifdef CONFIG_PROC_FS void proc_ide_create(void); void proc_ide_destroy(void); -void destroy_proc_ide_drives(ide_hwif_t *); +void destroy_proc_ide_drives(struct ata_channel *); void create_proc_ide_interfaces(void); void ide_add_proc_entries(struct proc_dir_entry *dir, ide_proc_entry_t *p, void *data); void ide_remove_proc_entries(struct proc_dir_entry *dir, ide_proc_entry_t *p); @@ -630,7 +622,6 @@ read_proc_t proc_ide_read_geometry; struct ata_operations { struct module *owner; - unsigned busy: 1; /* FIXME: this will go soon away... */ int (*cleanup)(ide_drive_t *); int (*standby)(ide_drive_t *); ide_startstop_t (*do_request)(ide_drive_t *, struct request *, unsigned long); @@ -645,6 +636,7 @@ struct ata_operations { void (*pre_reset)(ide_drive_t *); unsigned long (*capacity)(ide_drive_t *); ide_startstop_t (*special)(ide_drive_t *); + ide_proc_entry_t *proc; }; @@ -670,15 +662,7 @@ extern int register_ata_driver(unsigned int type, struct ata_operations *driver) #define ata_ops(drive) ((drive)->driver) -/* - * ide_hwifs[] is the master data structure used to keep track - * of just about everything in ide.c. Whenever possible, routines - * should be using pointers to a drive (ide_drive_t *) or - * pointers to a hwif (ide_hwif_t *), rather than indexing this - * structure directly (the allocation/layout may change!). - * - */ -extern struct hwif_s ide_hwifs[]; /* master data repository */ +extern struct ata_channel ide_hwifs[]; /* master data repository */ extern int noautodma; /* @@ -771,35 +755,7 @@ typedef enum { */ #define ide_rq_offset(rq) (((rq)->hard_cur_sectors - (rq)->current_nr_sectors) << 9) -#define task_rq_offset(rq) \ - (((rq)->nr_sectors - (rq)->current_nr_sectors) * SECTOR_SIZE) - -/* - * This function issues a special IDE device request - * onto the request queue. - * - * If action is ide_wait, then the rq is queued at the end of the - * request queue, and the function sleeps until it has been processed. - * This is for use when invoked from an ioctl handler. - * - * If action is ide_preempt, then the rq is queued at the head of - * the request queue, displacing the currently-being-processed - * request and this function returns immediately without waiting - * for the new rq to be completed. This is VERY DANGEROUS, and is - * intended for careful use by the ATAPI tape/cdrom driver code. - * - * If action is ide_next, then the rq is queued immediately after - * the currently-being-processed-request (if any), and the function - * returns without waiting for the new rq to be completed. As above, - * This is VERY DANGEROUS, and is intended for careful use by the - * ATAPI tape/cdrom driver code. - * - * If action is ide_end, then the rq is queued at the end of the - * request queue, and the function returns immediately without waiting - * for the new rq to be completed. This is again intended for careful - * use by the ATAPI tape/cdrom driver code. - */ -int ide_do_drive_cmd (ide_drive_t *drive, struct request *rq, ide_action_t action); +extern int ide_do_drive_cmd(ide_drive_t *drive, struct request *rq, ide_action_t action); /* * Clean up after success/failure of an explicit drive cmd. @@ -807,17 +763,11 @@ int ide_do_drive_cmd (ide_drive_t *drive, struct request *rq, ide_action_t actio void ide_end_drive_cmd (ide_drive_t *drive, byte stat, byte err); typedef struct ide_task_s { - task_ioreg_t tfRegister[8]; - task_ioreg_t hobRegister[8]; - ide_reg_valid_t tf_out_flags; - ide_reg_valid_t tf_in_flags; - int data_phase; + struct hd_drive_task_hdr taskfile; + struct hd_drive_hob_hdr hobfile; int command_type; ide_pre_handler_t *prehandler; ide_handler_t *handler; - void *special; /* valid_t generally */ - struct request *rq; /* copy of request */ - unsigned long block; /* copy of block */ } ide_task_t; void ata_input_data (ide_drive_t *drive, void *buffer, unsigned int wcount); @@ -827,15 +777,12 @@ void atapi_output_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecoun void taskfile_input_data (ide_drive_t *drive, void *buffer, unsigned int wcount); void taskfile_output_data (ide_drive_t *drive, void *buffer, unsigned int wcount); -/* - * taskfile io for disks for now... - */ -ide_startstop_t do_rw_taskfile (ide_drive_t *drive, ide_task_t *task); - -/* - * Builds request from ide_ioctl - */ -void do_taskfile (ide_drive_t *drive, struct hd_drive_task_hdr *taskfile, struct hd_drive_hob_hdr *hobfile, ide_handler_t *handler); +extern ide_startstop_t ata_taskfile(ide_drive_t *drive, + struct hd_drive_task_hdr *taskfile, + struct hd_drive_hob_hdr *hobfile, + ide_handler_t *handler, + ide_pre_handler_t *prehandler, + struct request *rq); /* * Special Flagged Register Validation Caller @@ -871,7 +818,7 @@ extern int system_bus_speed; * idedisk_input_data() is a wrapper around ide_input_data() which copes * with byte-swapping the input data if required. */ -inline void idedisk_input_data (ide_drive_t *drive, void *buffer, unsigned int wcount); +extern void idedisk_input_data(ide_drive_t *drive, void *buffer, unsigned int wcount); /* * ide_stall_queue() can be used by a drive to give excess bandwidth back @@ -939,15 +886,14 @@ extern int ide_unregister_subdriver(ide_drive_t *drive); void __init ide_scan_pcibus(int scan_direction); #endif #ifdef CONFIG_BLK_DEV_IDEDMA -# define BAD_DMA_DRIVE 0 -# define GOOD_DMA_DRIVE 1 int ide_build_dmatable (ide_drive_t *drive, ide_dma_action_t func); void ide_destroy_dmatable (ide_drive_t *drive); ide_startstop_t ide_dma_intr (ide_drive_t *drive); int check_drive_lists (ide_drive_t *drive, int good_bad); int ide_dmaproc (ide_dma_action_t func, ide_drive_t *drive); -extern void ide_release_dma(ide_hwif_t *hwif); -void ide_setup_dma (ide_hwif_t *hwif, unsigned long dmabase, unsigned int num_ports) __init; +extern void ide_release_dma(struct ata_channel *hwif); +extern void ide_setup_dma(struct ata_channel *hwif, + unsigned long dmabase, unsigned int num_ports) __init; #endif extern spinlock_t ide_lock; diff --git a/include/linux/inetdevice.h b/include/linux/inetdevice.h index 47ee810f813c..ddd8e23c1ca5 100644 --- a/include/linux/inetdevice.h +++ b/include/linux/inetdevice.h @@ -18,6 +18,7 @@ struct ipv4_devconf int mc_forwarding; int tag; int arp_filter; + int medium_id; void *sysctl; }; @@ -48,6 +49,7 @@ struct in_device #define IN_DEV_TX_REDIRECTS(in_dev) (ipv4_devconf.send_redirects || (in_dev)->cnf.send_redirects) #define IN_DEV_SEC_REDIRECTS(in_dev) (ipv4_devconf.secure_redirects || (in_dev)->cnf.secure_redirects) #define IN_DEV_IDTAG(in_dev) ((in_dev)->cnf.tag) +#define IN_DEV_MEDIUM_ID(in_dev) ((in_dev)->cnf.medium_id) #define IN_DEV_RX_REDIRECTS(in_dev) \ ((IN_DEV_FORWARD(in_dev) && \ diff --git a/include/linux/iobuf.h b/include/linux/iobuf.h index 869b05dc6b80..fb147b5c48a7 100644 --- a/include/linux/iobuf.h +++ b/include/linux/iobuf.h @@ -80,9 +80,9 @@ extern void free_kiobuf_bhs(struct kiobuf *); /* fs/buffer.c */ int brw_kiovec(int rw, int nr, struct kiobuf *iovec[], - kdev_t dev, sector_t [], int size); + struct block_device *bdev, sector_t [], int size); /* fs/bio.c */ -void ll_rw_kio(int rw, struct kiobuf *kio, kdev_t dev, sector_t block); +void ll_rw_kio(int rw, struct kiobuf *kio, struct block_device *bdev, sector_t block); #endif /* __LINUX_IOBUF_H */ diff --git a/include/linux/minix_fs.h b/include/linux/minix_fs.h index 586b49bb61bd..1ecc3cc8cef5 100644 --- a/include/linux/minix_fs.h +++ b/include/linux/minix_fs.h @@ -29,11 +29,6 @@ #define MINIX_INODES_PER_BLOCK ((BLOCK_SIZE)/(sizeof (struct minix_inode))) #define MINIX2_INODES_PER_BLOCK ((BLOCK_SIZE)/(sizeof (struct minix2_inode))) -#define MINIX_V1 0x0001 /* original minix fs */ -#define MINIX_V2 0x0002 /* minix V2 fs */ - -#define INODE_VERSION(inode) minix_sb(inode->i_sb)->s_version - /* * This is the original minix inode layout on disk. * Note the 8-bit gid and atime and ctime. @@ -87,61 +82,4 @@ struct minix_dir_entry { char name[0]; }; -#ifdef __KERNEL__ - -#include <linux/minix_fs_i.h> -#include <linux/minix_fs_sb.h> - -/* - * change the define below to 0 if you want names > info->s_namelen chars to be - * truncated. Else they will be disallowed (ENAMETOOLONG). - */ -#define NO_TRUNCATE 1 - -extern struct minix_inode * minix_V1_raw_inode(struct super_block *, ino_t, struct buffer_head **); -extern struct minix2_inode * minix_V2_raw_inode(struct super_block *, ino_t, struct buffer_head **); -extern struct inode * minix_new_inode(const struct inode * dir, int * error); -extern void minix_free_inode(struct inode * inode); -extern unsigned long minix_count_free_inodes(struct super_block *sb); -extern int minix_new_block(struct inode * inode); -extern void minix_free_block(struct inode * inode, int block); -extern unsigned long minix_count_free_blocks(struct super_block *sb); - -extern void V1_minix_truncate(struct inode *); -extern void V2_minix_truncate(struct inode *); -extern void minix_truncate(struct inode *); -extern int minix_sync_inode(struct inode *); -extern void minix_set_inode(struct inode *, dev_t); -extern int V1_minix_get_block(struct inode *, long, struct buffer_head *, int); -extern int V2_minix_get_block(struct inode *, long, struct buffer_head *, int); - -extern struct minix_dir_entry *minix_find_entry(struct dentry*, struct page**); -extern int minix_add_link(struct dentry*, struct inode*); -extern int minix_delete_entry(struct minix_dir_entry*, struct page*); -extern int minix_make_empty(struct inode*, struct inode*); -extern int minix_empty_dir(struct inode*); -extern void minix_set_link(struct minix_dir_entry*, struct page*, struct inode*); -extern struct minix_dir_entry *minix_dotdot(struct inode*, struct page**); -extern ino_t minix_inode_by_name(struct dentry*); - -extern int minix_sync_file(struct file *, struct dentry *, int); - -extern struct inode_operations minix_file_inode_operations; -extern struct inode_operations minix_dir_inode_operations; -extern struct file_operations minix_file_operations; -extern struct file_operations minix_dir_operations; -extern struct dentry_operations minix_dentry_operations; - -static inline struct minix_sb_info *minix_sb(struct super_block *sb) -{ - return sb->u.generic_sbp; -} - -static inline struct minix_inode_info *minix_i(struct inode *inode) -{ - return list_entry(inode, struct minix_inode_info, vfs_inode); -} - -#endif /* __KERNEL__ */ - #endif diff --git a/include/linux/minix_fs_i.h b/include/linux/minix_fs_i.h deleted file mode 100644 index 1ffd85ed4070..000000000000 --- a/include/linux/minix_fs_i.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef _MINIX_FS_I -#define _MINIX_FS_I - -/* - * minix fs inode data in memory - */ -struct minix_inode_info { - union { - __u16 i1_data[16]; - __u32 i2_data[16]; - } u; - struct inode vfs_inode; -}; - -#endif diff --git a/include/linux/minix_fs_sb.h b/include/linux/minix_fs_sb.h deleted file mode 100644 index 54c82af99a8f..000000000000 --- a/include/linux/minix_fs_sb.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef _MINIX_FS_SB -#define _MINIX_FS_SB - -/* - * minix super-block data in memory - */ -struct minix_sb_info { - unsigned long s_ninodes; - unsigned long s_nzones; - unsigned long s_imap_blocks; - unsigned long s_zmap_blocks; - unsigned long s_firstdatazone; - unsigned long s_log_zone_size; - unsigned long s_max_size; - int s_dirsize; - int s_namelen; - int s_link_max; - struct buffer_head ** s_imap; - struct buffer_head ** s_zmap; - struct buffer_head * s_sbh; - struct minix_super_block * s_ms; - unsigned short s_mount_state; - unsigned short s_version; -}; - -#endif diff --git a/include/linux/mtd/compatmac.h b/include/linux/mtd/compatmac.h index e6844448c327..9c9a2276f57e 100644 --- a/include/linux/mtd/compatmac.h +++ b/include/linux/mtd/compatmac.h @@ -190,8 +190,8 @@ static inline int try_inc_mod_count(struct module *mod) #if LINUX_VERSION_CODE < 0x20300 #include <linux/interrupt.h> -#define spin_lock_bh(lock) do {start_bh_atomic();spin_lock(lock);}while(0); -#define spin_unlock_bh(lock) do {spin_unlock(lock);end_bh_atomic();}while(0); +#define spin_lock_bh(lock) do {start_bh_atomic();spin_lock(lock);} while(0) +#define spin_unlock_bh(lock) do {spin_unlock(lock);end_bh_atomic();} while(0) #else #include <asm/softirq.h> #include <linux/spinlock.h> diff --git a/include/linux/nbd.h b/include/linux/nbd.h index f1b5135d288e..b6120317731d 100644 --- a/include/linux/nbd.h +++ b/include/linux/nbd.h @@ -70,7 +70,7 @@ struct nbd_device { struct file * file; /* If == NULL, device is not ready, yet */ int magic; /* FIXME: not if debugging is off */ struct list_head queue_head; /* Requests are added here... */ - struct semaphore queue_lock; + struct semaphore tx_lock; }; #endif diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index 32b6db3c7a2c..706c6240ecca 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -246,8 +246,6 @@ struct net_device * I/O specific fields * FIXME: Merge these and struct ifmap into one */ - unsigned long rmem_end; /* shmem "recv" end */ - unsigned long rmem_start; /* shmem "recv" start */ unsigned long mem_end; /* shared mem end */ unsigned long mem_start; /* shared mem start */ unsigned long base_addr; /* device I/O address */ diff --git a/include/linux/netfilter_ipv4/ip_conntrack.h b/include/linux/netfilter_ipv4/ip_conntrack.h index 107cce0c67a3..de76fd298762 100644 --- a/include/linux/netfilter_ipv4/ip_conntrack.h +++ b/include/linux/netfilter_ipv4/ip_conntrack.h @@ -6,6 +6,7 @@ #include <linux/config.h> #include <linux/netfilter_ipv4/ip_conntrack_tuple.h> +#include <asm/atomic.h> enum ip_conntrack_info { @@ -62,27 +63,58 @@ do { \ #define IP_NF_ASSERT(x) #endif +#ifdef CONFIG_IP_NF_NAT_NEEDED +#include <linux/netfilter_ipv4/ip_nat.h> +#endif + +/* Add protocol helper include file here */ +#include <linux/netfilter_ipv4/ip_conntrack_ftp.h> +#include <linux/netfilter_ipv4/ip_conntrack_irc.h> + struct ip_conntrack_expect { - /* Internal linked list */ + /* Internal linked list (global expectation list) */ struct list_head list; + /* expectation list for this master */ + struct list_head expected_list; + + /* The conntrack of the master connection */ + struct ip_conntrack *expectant; + + /* The conntrack of the sibling connection, set after + * expectation arrived */ + struct ip_conntrack *sibling; + + /* Tuple saved for conntrack */ + struct ip_conntrack_tuple ct_tuple; + + /* Timer function; deletes the expectation. */ + struct timer_list timeout; + + /* Data filled out by the conntrack helpers follow: */ + /* We expect this tuple, with the following mask */ struct ip_conntrack_tuple tuple, mask; /* Function to call after setup and insertion */ int (*expectfn)(struct ip_conntrack *new); - /* The conntrack we are part of (set iff we're live) */ - struct ip_conntrack *expectant; -}; - + /* At which sequence number did this expectation occur */ + u_int32_t seq; + + union { + /* insert conntrack helper private data (expect) here */ + struct ip_ct_ftp_expect exp_ftp_info; + struct ip_ct_irc_expect exp_irc_info; + #ifdef CONFIG_IP_NF_NAT_NEEDED -#include <linux/netfilter_ipv4/ip_nat.h> + union { + /* insert nat helper private data (expect) here */ + } nat; #endif - -#include <linux/netfilter_ipv4/ip_conntrack_ftp.h> -#include <linux/netfilter_ipv4/ip_conntrack_irc.h> + } help; +}; struct ip_conntrack { @@ -101,10 +133,13 @@ struct ip_conntrack /* If we're expecting another related connection, this will be in expected linked list */ - struct ip_conntrack_expect expected; + struct list_head sibling_list; + + /* Current number of expected connections */ + unsigned int expecting; - /* If we were expected by another connection, this will be it */ - struct nf_ct_info master; + /* If we were expected by an expectation, this will be it */ + struct ip_conntrack_expect *master; /* Helper, if any. */ struct ip_conntrack_helper *helper; @@ -121,8 +156,9 @@ struct ip_conntrack } proto; union { - struct ip_ct_ftp ct_ftp_info; - struct ip_ct_irc ct_irc_info; + /* insert conntrack helper private data (master) here */ + struct ip_ct_ftp_master ct_ftp_info; + struct ip_ct_irc_master ct_irc_info; } help; #ifdef CONFIG_IP_NF_NAT_NEEDED @@ -140,6 +176,9 @@ struct ip_conntrack }; +/* get master conntrack via master expectation */ +#define master_ct(conntr) (conntr->master ? conntr->master->expectant : NULL) + /* Alter reply tuple (maybe alter helper). If it's already taken, return 0 and don't do alteration. */ extern int diff --git a/include/linux/netfilter_ipv4/ip_conntrack_core.h b/include/linux/netfilter_ipv4/ip_conntrack_core.h index 6ed40793af6a..49f26c463e85 100644 --- a/include/linux/netfilter_ipv4/ip_conntrack_core.h +++ b/include/linux/netfilter_ipv4/ip_conntrack_core.h @@ -15,7 +15,7 @@ extern int ip_conntrack_init(void); extern void ip_conntrack_cleanup(void); struct ip_conntrack_protocol; -extern struct ip_conntrack_protocol *find_proto(u_int8_t protocol); +extern struct ip_conntrack_protocol *ip_ct_find_proto(u_int8_t protocol); /* Like above, but you already have conntrack read lock. */ extern struct ip_conntrack_protocol *__find_proto(u_int8_t protocol); extern struct list_head protocol_list; diff --git a/include/linux/netfilter_ipv4/ip_conntrack_ftp.h b/include/linux/netfilter_ipv4/ip_conntrack_ftp.h index 4b560e237ba3..06f6f588ce37 100644 --- a/include/linux/netfilter_ipv4/ip_conntrack_ftp.h +++ b/include/linux/netfilter_ipv4/ip_conntrack_ftp.h @@ -11,6 +11,8 @@ /* Protects ftp part of conntracks */ DECLARE_LOCK_EXTERN(ip_ftp_lock); +#define FTP_PORT 21 + enum ip_ct_ftp_type { /* PORT command from client */ @@ -23,18 +25,20 @@ enum ip_ct_ftp_type IP_CT_FTP_EPSV, }; -/* We record seq number and length of ftp ip/port text here: all in - host order. */ -struct ip_ct_ftp +/* This structure is per expected connection */ +struct ip_ct_ftp_expect { - /* This tells NAT that this is an ftp connection */ - int is_ftp; - u_int32_t seq; - /* 0 means not found yet */ - u_int32_t len; - enum ip_ct_ftp_type ftptype; - /* Port that was to be used */ - u_int16_t port; + /* We record seq number and length of ftp ip/port text here: all in + * host order. */ + + /* sequence number of IP address in packet is in ip_conntrack_expect */ + u_int32_t len; /* length of IP address */ + enum ip_ct_ftp_type ftptype; /* PORT or PASV ? */ + u_int16_t port; /* TCP port that was to be used */ +}; + +/* This structure exists only once per master */ +struct ip_ct_ftp_master { /* Next valid seq position for cmd matching after newline */ u_int32_t seq_aft_nl[IP_CT_DIR_MAX]; /* 0 means seq_match_aft_nl not set */ diff --git a/include/linux/netfilter_ipv4/ip_conntrack_helper.h b/include/linux/netfilter_ipv4/ip_conntrack_helper.h index 728e7bde6b3f..d092a4fcb33b 100644 --- a/include/linux/netfilter_ipv4/ip_conntrack_helper.h +++ b/include/linux/netfilter_ipv4/ip_conntrack_helper.h @@ -5,10 +5,19 @@ struct module; +/* Reuse expectation when max_expected reached */ +#define IP_CT_HELPER_F_REUSE_EXPECT 0x01 + struct ip_conntrack_helper { - /* Internal use. */ - struct list_head list; + struct list_head list; /* Internal use. */ + + const char *name; /* name of the module */ + unsigned char flags; /* Flags (see above) */ + struct module *me; /* pointer to self */ + unsigned int max_expected; /* Maximum number of concurrent + * expected connections */ + unsigned int timeout; /* timeout for expecteds */ /* Mask of things we will help (compared against server response) */ struct ip_conntrack_tuple tuple; @@ -24,11 +33,13 @@ struct ip_conntrack_helper extern int ip_conntrack_helper_register(struct ip_conntrack_helper *); extern void ip_conntrack_helper_unregister(struct ip_conntrack_helper *); -/* Add an expected connection: can only have one per connection */ +extern struct ip_conntrack_helper *ip_ct_find_helper(const struct ip_conntrack_tuple *tuple); + +/* Add an expected connection: can have more than one per connection */ extern int ip_conntrack_expect_related(struct ip_conntrack *related_to, - const struct ip_conntrack_tuple *tuple, - const struct ip_conntrack_tuple *mask, - int (*expectfn)(struct ip_conntrack *)); -extern void ip_conntrack_unexpect_related(struct ip_conntrack *related_to); + struct ip_conntrack_expect *exp); +extern int ip_conntrack_change_expect(struct ip_conntrack_expect *expect, + struct ip_conntrack_tuple *newtuple); +extern void ip_conntrack_unexpect_related(struct ip_conntrack_expect *exp); #endif /*_IP_CONNTRACK_HELPER_H*/ diff --git a/include/linux/netfilter_ipv4/ip_conntrack_irc.h b/include/linux/netfilter_ipv4/ip_conntrack_irc.h index 8069814530ea..bc96a5df6a4b 100644 --- a/include/linux/netfilter_ipv4/ip_conntrack_irc.h +++ b/include/linux/netfilter_ipv4/ip_conntrack_irc.h @@ -20,7 +20,7 @@ #include <linux/netfilter_ipv4/lockhelp.h> -#define IP_CONNTR_IRC 2 +#define IRC_PORT 6667 struct dccproto { char* match; @@ -32,16 +32,18 @@ DECLARE_LOCK_EXTERN(ip_irc_lock); /* We record seq number and length of irc ip/port text here: all in host order. */ -struct ip_ct_irc + +/* This structure is per expected connection */ +struct ip_ct_irc_expect { - /* This tells NAT that this is an IRC connection */ - int is_irc; - /* sequence number where address part of DCC command begins */ - u_int32_t seq; - /* 0 means not found yet */ + /* length of IP address */ u_int32_t len; /* Port that was to be used */ u_int16_t port; }; +/* This structure exists only once per master */ +struct ip_ct_irc_master { +}; + #endif /* _IP_CONNTRACK_IRC_H */ diff --git a/include/linux/netfilter_ipv4/ip_conntrack_protocol.h b/include/linux/netfilter_ipv4/ip_conntrack_protocol.h index 83076c3c5f25..e99cd7ded26f 100644 --- a/include/linux/netfilter_ipv4/ip_conntrack_protocol.h +++ b/include/linux/netfilter_ipv4/ip_conntrack_protocol.h @@ -42,6 +42,13 @@ struct ip_conntrack_protocol int (*new)(struct ip_conntrack *conntrack, struct iphdr *iph, size_t len); + /* Called when a conntrack entry is destroyed */ + void (*destroy)(struct ip_conntrack *conntrack); + + /* Has to decide if a expectation matches one packet or not */ + int (*exp_matches_pkt)(struct ip_conntrack_expect *exp, + struct sk_buff **pskb); + /* Module (if any) which this is connected to. */ struct module *me; }; diff --git a/include/linux/netfilter_ipv4/ip_nat_helper.h b/include/linux/netfilter_ipv4/ip_nat_helper.h index d85cd0669826..2c1fb8d9bb54 100644 --- a/include/linux/netfilter_ipv4/ip_nat_helper.h +++ b/include/linux/netfilter_ipv4/ip_nat_helper.h @@ -6,23 +6,37 @@ struct sk_buff; +/* Flags */ +/* NAT helper must be called on every packet (for TCP) */ +#define IP_NAT_HELPER_F_ALWAYS 0x01 +/* Standalone NAT helper, without a conntrack part */ +#define IP_NAT_HELPER_F_STANDALONE 0x02 + struct ip_nat_helper { - /* Internal use */ - struct list_head list; + struct list_head list; /* Internal use */ + const char *name; /* name of the module */ + unsigned char flags; /* Flags (see above) */ + struct module *me; /* pointer to self */ + /* Mask of things we will help: vs. tuple from server */ struct ip_conntrack_tuple tuple; struct ip_conntrack_tuple mask; /* Helper function: returns verdict */ unsigned int (*help)(struct ip_conntrack *ct, + struct ip_conntrack_expect *exp, struct ip_nat_info *info, enum ip_conntrack_info ctinfo, unsigned int hooknum, struct sk_buff **pskb); - const char *name; + /* Returns verdict and sets up NAT for this connection */ + unsigned int (*expect)(struct sk_buff **pskb, + unsigned int hooknum, + struct ip_conntrack *ct, + struct ip_nat_info *info); }; extern struct list_head helpers; @@ -39,5 +53,5 @@ extern int ip_nat_mangle_tcp_packet(struct sk_buff **skb, extern int ip_nat_seq_adjust(struct sk_buff *skb, struct ip_conntrack *ct, enum ip_conntrack_info ctinfo); -extern void ip_nat_delete_sack(struct sk_buff *skb, struct tcphdr *tcph); +extern void ip_nat_delete_sack(struct sk_buff *skb); #endif diff --git a/include/linux/netfilter_ipv4/ip_nat_rule.h b/include/linux/netfilter_ipv4/ip_nat_rule.h index 6c92b285d184..488efcee2f3c 100644 --- a/include/linux/netfilter_ipv4/ip_nat_rule.h +++ b/include/linux/netfilter_ipv4/ip_nat_rule.h @@ -5,24 +5,7 @@ #include <linux/netfilter_ipv4/ip_nat.h> #ifdef __KERNEL__ -/* Want to be told when we first NAT an expected packet for a conntrack? */ -struct ip_nat_expect -{ - struct list_head list; - /* Returns 1 (and sets verdict) if it has setup NAT for this - connection */ - int (*expect)(struct sk_buff **pskb, - unsigned int hooknum, - struct ip_conntrack *ct, - struct ip_nat_info *info, - struct ip_conntrack *master, - struct ip_nat_info *masterinfo, - unsigned int *verdict); -}; - -extern int ip_nat_expect_register(struct ip_nat_expect *expect); -extern void ip_nat_expect_unregister(struct ip_nat_expect *expect); extern int ip_nat_rule_init(void) __init; extern void ip_nat_rule_cleanup(void); extern int ip_nat_rule_find(struct sk_buff **pskb, diff --git a/include/linux/nfsd/const.h b/include/linux/nfsd/const.h index f59c6a6ef8c4..bd828fa0314f 100644 --- a/include/linux/nfsd/const.h +++ b/include/linux/nfsd/const.h @@ -19,9 +19,9 @@ #define NFSSVC_MAXVERS 3 /* - * Maximum blocksize supported by daemon currently at 8K + * Maximum blocksize supported by daemon currently at 32K */ -#define NFSSVC_MAXBLKSIZE 8192 +#define NFSSVC_MAXBLKSIZE (32*1024) #ifdef __KERNEL__ diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 41eed9cd438e..13ab68e4c0d5 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -355,6 +355,7 @@ #define PCI_VENDOR_ID_WD 0x101c #define PCI_DEVICE_ID_WD_7197 0x3296 +#define PCI_DEVICE_ID_WD_90C 0xc24a #define PCI_VENDOR_ID_AMI 0x101e #define PCI_DEVICE_ID_AMI_MEGARAID3 0x1960 @@ -445,6 +446,7 @@ #define PCI_DEVICE_ID_NEC_PCX2 0x0046 #define PCI_DEVICE_ID_NEC_NILE4 0x005a #define PCI_DEVICE_ID_NEC_VRC5476 0x009b +#define PCI_DEVICE_ID_NEC_VRC5477_AC97 0x00a6 #define PCI_VENDOR_ID_FD 0x1036 #define PCI_DEVICE_ID_FD_36C70 0x0000 @@ -537,10 +539,6 @@ #define PCI_DEVICE_ID_ELSA_MICROLINK 0x1000 #define PCI_DEVICE_ID_ELSA_QS3000 0x3000 -#define PCI_VENDOR_ID_ELSA 0x1048 -#define PCI_DEVICE_ID_ELSA_MICROLINK 0x1000 -#define PCI_DEVICE_ID_ELSA_QS3000 0x3000 - #define PCI_VENDOR_ID_SGS 0x104a #define PCI_DEVICE_ID_SGS_2000 0x0008 #define PCI_DEVICE_ID_SGS_1764 0x0009 @@ -597,6 +595,7 @@ #define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002 #define PCI_DEVICE_ID_MOTOROLA_RAVEN 0x4801 #define PCI_DEVICE_ID_MOTOROLA_FALCON 0x4802 +#define PCI_DEVICE_ID_MOTOROLA_HAWK 0x4803 #define PCI_DEVICE_ID_MOTOROLA_CPX8216 0x4806 #define PCI_VENDOR_ID_PROMISE 0x105a @@ -608,6 +607,7 @@ #define PCI_DEVICE_ID_PROMISE_20268R 0x6268 #define PCI_DEVICE_ID_PROMISE_20269 0x4d69 #define PCI_DEVICE_ID_PROMISE_20275 0x1275 +#define PCI_DEVICE_ID_PROMISE_20276 0x5275 #define PCI_DEVICE_ID_PROMISE_5300 0x5300 #define PCI_VENDOR_ID_N9 0x105d @@ -649,6 +649,12 @@ #define PCI_DEVICE_ID_APPLE_KL_USB 0x0019 #define PCI_DEVICE_ID_APPLE_UNI_N_AGP 0x0020 #define PCI_DEVICE_ID_APPLE_UNI_N_GMAC 0x0021 +#define PCI_DEVICE_ID_APPLE_KEYLARGO 0x0022 +#define PCI_DEVICE_ID_APPLE_UNI_N_GMACP 0x0024 +#define PCI_DEVICE_ID_APPLE_KEYLARGO_P 0x0025 +#define PCI_DEVICE_ID_APPLE_KL_USB_P 0x0026 +#define PCI_DEVICE_ID_APPLE_UNI_N_AGP_P 0x0027 +#define PCI_DEVICE_ID_APPLE_UNI_N_AGP15 0x002d #define PCI_DEVICE_ID_APPLE_UNI_N_FW2 0x0030 #define PCI_VENDOR_ID_YAMAHA 0x1073 @@ -860,12 +866,18 @@ #define PCI_DEVICE_ID_NVIDIA_QUADRO 0x0103 #define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX 0x0110 #define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2 0x0111 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO 0x0112 #define PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR 0x0113 #define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS 0x0150 #define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2 0x0151 #define PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA 0x0152 #define PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO 0x0153 +#define PCI_DEVICE_ID_NVIDIA_IGEFORCE2 0x01a0 #define PCI_DEVICE_ID_NVIDIA_NFORCE_IDE 0x01bc +#define PCI_DEVICE_ID_NVIDIA_GEFORCE3 0x0200 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_1 0x0201 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_2 0x0202 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_DDC 0x0203 #define PCI_VENDOR_ID_IMS 0x10e0 #define PCI_DEVICE_ID_IMS_8849 0x8849 @@ -1106,6 +1118,11 @@ #define PCI_DEVICE_ID_TOSHIBA_TOPIC95 0x060a #define PCI_DEVICE_ID_TOSHIBA_TOPIC97 0x060f +#define PCI_VENDOR_ID_TOSHIBA_2 0x102f +#define PCI_DEVICE_ID_TOSHIBA_TX3927 0x000a +#define PCI_DEVICE_ID_TOSHIBA_TC35815CF 0x0030 +#define PCI_DEVICE_ID_TOSHIBA_TX4927 0x0180 + #define PCI_VENDOR_ID_RICOH 0x1180 #define PCI_DEVICE_ID_RICOH_RL5C465 0x0465 #define PCI_DEVICE_ID_RICOH_RL5C466 0x0466 @@ -1118,6 +1135,8 @@ #define PCI_DEVICE_ID_ARTOP_ATP850UF 0x0005 #define PCI_DEVICE_ID_ARTOP_ATP860 0x0006 #define PCI_DEVICE_ID_ARTOP_ATP860R 0x0007 +#define PCI_DEVICE_ID_ARTOP_ATP865 0x0008 +#define PCI_DEVICE_ID_ARTOP_ATP865R 0x0009 #define PCI_DEVICE_ID_ARTOP_AEC7610 0x8002 #define PCI_DEVICE_ID_ARTOP_AEC7612UW 0x8010 #define PCI_DEVICE_ID_ARTOP_AEC7612U 0x8020 @@ -1279,13 +1298,8 @@ #define PCI_VENDOR_ID_ITE 0x1283 #define PCI_DEVICE_ID_ITE_IT8172G 0x8172 #define PCI_DEVICE_ID_ITE_IT8172G_AUDIO 0x0801 - -#define PCI_VENDOR_ID_ITE 0x1283 -#define PCI_DEVICE_ID_ITE_IT8172G 0x8172 - -#define PCI_VENDOR_ID_ITE 0x1283 #define PCI_DEVICE_ID_ITE_8872 0x8872 - +#define PCI_DEVICE_ID_ITE_IT8330G_0 0xe886 /* formerly Platform Tech */ #define PCI_VENDOR_ID_ESS_OLD 0x1285 @@ -1450,6 +1464,8 @@ #define PCI_DEVICE_ID_LAVA_DSERIAL 0x0100 /* 2x 16550 */ #define PCI_DEVICE_ID_LAVA_QUATRO_A 0x0101 /* 2x 16550, half of 4 port */ #define PCI_DEVICE_ID_LAVA_QUATRO_B 0x0102 /* 2x 16550, half of 4 port */ +#define PCI_DEVICE_ID_LAVA_OCTO_A 0x0180 /* 4x 16550A, half of 8 port */ +#define PCI_DEVICE_ID_LAVA_OCTO_B 0x0181 /* 4x 16550A, half of 8 port */ #define PCI_DEVICE_ID_LAVA_PORT_PLUS 0x0200 /* 2x 16650 */ #define PCI_DEVICE_ID_LAVA_QUAD_A 0x0201 /* 2x 16650, half of 4 port */ #define PCI_DEVICE_ID_LAVA_QUAD_B 0x0202 /* 2x 16650, half of 4 port */ @@ -1639,16 +1655,6 @@ #define PCI_DEVICE_ID_INTEL_82801BA_2 0x2443 #define PCI_DEVICE_ID_INTEL_82801BA_3 0x2444 #define PCI_DEVICE_ID_INTEL_82801BA_4 0x2445 -#define PCI_DEVICE_ID_INTEL_82801CA_0 0x2480 -#define PCI_DEVICE_ID_INTEL_82801CA_2 0x2482 -#define PCI_DEVICE_ID_INTEL_82801CA_3 0x2483 -#define PCI_DEVICE_ID_INTEL_82801CA_4 0x2484 -#define PCI_DEVICE_ID_INTEL_82801CA_5 0x2485 -#define PCI_DEVICE_ID_INTEL_82801CA_6 0x2486 -#define PCI_DEVICE_ID_INTEL_82801CA_7 0x2487 -#define PCI_DEVICE_ID_INTEL_82801CA_10 0x248a -#define PCI_DEVICE_ID_INTEL_82801CA_11 0x248b -#define PCI_DEVICE_ID_INTEL_82801CA_12 0x248c #define PCI_DEVICE_ID_INTEL_82801BA_5 0x2446 #define PCI_DEVICE_ID_INTEL_82801BA_6 0x2448 #define PCI_DEVICE_ID_INTEL_82801BA_7 0x2449 diff --git a/include/linux/platform.h b/include/linux/platform.h new file mode 100644 index 000000000000..3c33084a6ec2 --- /dev/null +++ b/include/linux/platform.h @@ -0,0 +1,43 @@ +/* + * include/linux/platform.h - platform driver definitions + * + * Because of the prolific consumerism of the average American, + * and the dominant marketing budgets of PC OEMs, we have been + * blessed with frequent updates of the PC architecture. + * + * While most of these calls are singular per architecture, they + * require an extra layer of abstraction on the x86 so the right + * subsystem gets the right call. + * + * Basically, this consolidates the power off and reboot callbacks + * into one structure, as well as adding power management hooks. + * + * When adding a platform driver, please make sure all callbacks are + * filled. There are defaults defined below that do nothing; use those + * if you do not support that callback. + */ + +#ifndef _PLATFORM_H_ +#define _PLATFORM_H_ +#ifdef __KERNEL__ + +#include <linux/types.h> + +struct platform_t { + char * name; + u32 suspend_states; + void (*reboot)(char * cmd); + void (*halt)(void); + void (*power_off)(void); + int (*suspend)(int state, int flags); + void (*idle)(void); +}; + +extern struct platform_t * platform; +extern void default_reboot(char * cmd); +extern void default_halt(void); +extern int default_suspend(int state, int flags); +extern void default_idle(void); + +#endif /* __KERNEL__ */ +#endif /* _PLATFORM_H */ diff --git a/include/linux/pnpbios.h b/include/linux/pnpbios.h index b1b2b6f9e5e6..e1e8542bda0a 100644 --- a/include/linux/pnpbios.h +++ b/include/linux/pnpbios.h @@ -143,20 +143,21 @@ static __inline struct pnpbios_driver *pnpbios_dev_driver(const struct pci_dev * extern int pnpbios_dont_use_current_config; extern void *pnpbios_kmalloc(size_t size, int f); extern int pnpbios_init (void); -extern void pnpbios_proc_init (void); +extern int pnpbios_proc_init (void); +extern void pnpbios_proc_exit (void); extern int pnp_bios_dev_node_info (struct pnp_dev_node_info *data); extern int pnp_bios_get_dev_node (u8 *nodenum, char config, struct pnp_bios_node *data); extern int pnp_bios_set_dev_node (u8 nodenum, char config, struct pnp_bios_node *data); +extern int pnp_bios_get_stat_res (char *info); +extern int pnp_bios_isapnp_config (struct pnp_isa_config_struc *data); +extern int pnp_bios_escd_info (struct escd_info_struc *data); +extern int pnp_bios_read_escd (char *data, u32 nvram_base); #if needed extern int pnp_bios_get_event (u16 *message); extern int pnp_bios_send_message (u16 message); extern int pnp_bios_set_stat_res (char *info); -extern int pnp_bios_get_stat_res (char *info); extern int pnp_bios_apm_id_table (char *table, u16 *size); -extern int pnp_bios_isapnp_config (struct pnp_isa_config_struc *data); -extern int pnp_bios_escd_info (struct escd_info_struc *data); -extern int pnp_bios_read_escd (char *data, u32 nvram_base); extern int pnp_bios_write_escd (char *data, u32 nvram_base); #endif diff --git a/include/linux/quota.h b/include/linux/quota.h index d155eb2bd51a..b2d5de7368f6 100644 --- a/include/linux/quota.h +++ b/include/linux/quota.h @@ -144,7 +144,6 @@ struct dqstats { #ifdef __KERNEL__ -extern int nr_dquots, nr_free_dquots; extern int dquot_root_squash; #define NR_DQHASH 43 /* Just an arbitrary number */ diff --git a/include/linux/raid/md.h b/include/linux/raid/md.h index 233163eb2872..07e24c4dc71e 100644 --- a/include/linux/raid/md.h +++ b/include/linux/raid/md.h @@ -18,8 +18,6 @@ #ifndef _MD_H #define _MD_H -#include <linux/mm.h> -#include <linux/fs.h> #include <linux/blkdev.h> #include <asm/semaphore.h> #include <linux/major.h> diff --git a/include/linux/reiserfs_fs.h b/include/linux/reiserfs_fs.h index f148ef8120c4..b27d98610bd3 100644 --- a/include/linux/reiserfs_fs.h +++ b/include/linux/reiserfs_fs.h @@ -21,6 +21,7 @@ #include <linux/bitops.h> #include <linux/proc_fs.h> #include <linux/reiserfs_fs_i.h> +#include <linux/reiserfs_fs_sb.h> #endif /* @@ -96,7 +97,7 @@ if( !( cond ) ) \ /***************************************************************************/ /* - * Structure of super block on disk, a version of which in RAM is often accessed as s->u.reiserfs_sb.s_rs + * Structure of super block on disk, a version of which in RAM is often accessed as REISERFS_SB(s)->s_rs * the version in RAM is part of a larger structure containing fields never written to disk. */ #define UNSET_HASH 0 // read_super will guess about, what hash names @@ -176,7 +177,7 @@ struct reiserfs_super_block // on-disk super block fields converted to cpu form -#define SB_DISK_SUPER_BLOCK(s) ((s)->u.reiserfs_sb.s_rs) +#define SB_DISK_SUPER_BLOCK(s) (REISERFS_SB(s)->s_rs) #define SB_V1_DISK_SUPER_BLOCK(s) (&(SB_DISK_SUPER_BLOCK(s)->s_v1)) #define SB_BLOCKSIZE(s) \ le32_to_cpu ((SB_V1_DISK_SUPER_BLOCK(s)->s_blocksize)) @@ -287,6 +288,12 @@ static inline struct reiserfs_inode_info *REISERFS_I(struct inode *inode) { return list_entry(inode, struct reiserfs_inode_info, vfs_inode); } + +static inline struct reiserfs_sb_info *REISERFS_SB(const struct super_block *sb) +{ + return sb->u.generic_sbp; +} + /** this says about version of key of all items (but stat data) the object consists of */ #define get_inode_item_key_version( inode ) \ @@ -1284,7 +1291,7 @@ static inline loff_t max_reiserfs_offset (struct inode * inode) #define REISERFS_KERNEL_MEM 0 /* reiserfs kernel memory mode */ #define REISERFS_USER_MEM 1 /* reiserfs user memory mode */ -#define fs_generation(s) ((s)->u.reiserfs_sb.s_generation_counter) +#define fs_generation(s) (REISERFS_SB(s)->s_generation_counter) #define get_generation(s) atomic_read (&fs_generation(s)) #define FILESYSTEM_CHANGED_TB(tb) (get_generation((tb)->tb_sb) != (tb)->fs_gen) #define fs_changed(gen,s) (gen != get_generation (s)) @@ -1884,10 +1891,10 @@ int reiserfs_journal_in_proc( char *buffer, char **start, off_t offset, #define PROC_EXP( e ) e #define MAX( a, b ) ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) ) -#define __PINFO( sb ) ( sb ) -> u.reiserfs_sb.s_proc_info_data +#define __PINFO( sb ) REISERFS_SB(sb) -> s_proc_info_data #define PROC_INFO_MAX( sb, field, value ) \ __PINFO( sb ).field = \ - MAX( ( sb ) -> u.reiserfs_sb.s_proc_info_data.field, value ) + MAX( REISERFS_SB( sb ) -> s_proc_info_data.field, value ) #define PROC_INFO_INC( sb, field ) ( ++ ( __PINFO( sb ).field ) ) #define PROC_INFO_ADD( sb, field, val ) ( __PINFO( sb ).field += ( val ) ) #define PROC_INFO_BH_STAT( sb, bh, level ) \ diff --git a/include/linux/reiserfs_fs_sb.h b/include/linux/reiserfs_fs_sb.h index eb166e790a3f..05addd1e35f8 100644 --- a/include/linux/reiserfs_fs_sb.h +++ b/include/linux/reiserfs_fs_sb.h @@ -412,20 +412,20 @@ struct reiserfs_sb_info #define REISERFS_TEST3 13 #define REISERFS_TEST4 14 -#define reiserfs_r5_hash(s) ((s)->u.reiserfs_sb.s_mount_opt & (1 << FORCE_R5_HASH)) -#define reiserfs_rupasov_hash(s) ((s)->u.reiserfs_sb.s_mount_opt & (1 << FORCE_RUPASOV_HASH)) -#define reiserfs_tea_hash(s) ((s)->u.reiserfs_sb.s_mount_opt & (1 << FORCE_TEA_HASH)) -#define reiserfs_hash_detect(s) ((s)->u.reiserfs_sb.s_mount_opt & (1 << FORCE_HASH_DETECT)) -#define reiserfs_no_border(s) ((s)->u.reiserfs_sb.s_mount_opt & (1 << REISERFS_NO_BORDER)) -#define reiserfs_no_unhashed_relocation(s) ((s)->u.reiserfs_sb.s_mount_opt & (1 << REISERFS_NO_UNHASHED_RELOCATION)) -#define reiserfs_hashed_relocation(s) ((s)->u.reiserfs_sb.s_mount_opt & (1 << REISERFS_HASHED_RELOCATION)) -#define reiserfs_test4(s) ((s)->u.reiserfs_sb.s_mount_opt & (1 << REISERFS_TEST4)) - -#define dont_have_tails(s) ((s)->u.reiserfs_sb.s_mount_opt & (1 << NOTAIL)) -#define replay_only(s) ((s)->u.reiserfs_sb.s_mount_opt & (1 << REPLAYONLY)) -#define reiserfs_dont_log(s) ((s)->u.reiserfs_sb.s_mount_opt & (1 << REISERFS_NOLOG)) -#define old_format_only(s) ((s)->u.reiserfs_sb.s_properties & (1 << REISERFS_3_5)) -#define convert_reiserfs(s) ((s)->u.reiserfs_sb.s_mount_opt & (1 << REISERFS_CONVERT)) +#define reiserfs_r5_hash(s) (REISERFS_SB(s)->s_mount_opt & (1 << FORCE_R5_HASH)) +#define reiserfs_rupasov_hash(s) (REISERFS_SB(s)->s_mount_opt & (1 << FORCE_RUPASOV_HASH)) +#define reiserfs_tea_hash(s) (REISERFS_SB(s)->s_mount_opt & (1 << FORCE_TEA_HASH)) +#define reiserfs_hash_detect(s) (REISERFS_SB(s)->s_mount_opt & (1 << FORCE_HASH_DETECT)) +#define reiserfs_no_border(s) (REISERFS_SB(s)->s_mount_opt & (1 << REISERFS_NO_BORDER)) +#define reiserfs_no_unhashed_relocation(s) (REISERFS_SB(s)->s_mount_opt & (1 << REISERFS_NO_UNHASHED_RELOCATION)) +#define reiserfs_hashed_relocation(s) (REISERFS_SB(s)->s_mount_opt & (1 << REISERFS_HASHED_RELOCATION)) +#define reiserfs_test4(s) (REISERFS_SB(s)->s_mount_opt & (1 << REISERFS_TEST4)) + +#define dont_have_tails(s) (REISERFS_SB(s)->s_mount_opt & (1 << NOTAIL)) +#define replay_only(s) (REISERFS_SB(s)->s_mount_opt & (1 << REPLAYONLY)) +#define reiserfs_dont_log(s) (REISERFS_SB(s)->s_mount_opt & (1 << REISERFS_NOLOG)) +#define old_format_only(s) (REISERFS_SB(s)->s_properties & (1 << REISERFS_3_5)) +#define convert_reiserfs(s) (REISERFS_SB(s)->s_mount_opt & (1 << REISERFS_CONVERT)) void reiserfs_file_buffer (struct buffer_head * bh, int list); @@ -439,13 +439,13 @@ int reiserfs_resize(struct super_block *, unsigned long) ; #define SCHEDULE_OCCURRED 1 -#define SB_BUFFER_WITH_SB(s) ((s)->u.reiserfs_sb.s_sbh) -#define SB_JOURNAL(s) ((s)->u.reiserfs_sb.s_journal) +#define SB_BUFFER_WITH_SB(s) (REISERFS_SB(s)->s_sbh) +#define SB_JOURNAL(s) (REISERFS_SB(s)->s_journal) #define SB_JOURNAL_1st_RESERVED_BLOCK(s) (SB_JOURNAL(s)->j_1st_reserved_block) #define SB_JOURNAL_LIST(s) (SB_JOURNAL(s)->j_journal_list) #define SB_JOURNAL_LIST_INDEX(s) (SB_JOURNAL(s)->j_journal_list_index) #define SB_JOURNAL_LEN_FREE(s) (SB_JOURNAL(s)->j_journal_len_free) -#define SB_AP_BITMAP(s) ((s)->u.reiserfs_sb.s_ap_bitmap) +#define SB_AP_BITMAP(s) (REISERFS_SB(s)->s_ap_bitmap) #define SB_DISK_JOURNAL_HEAD(s) (SB_JOURNAL(s)->j_header_bh->) diff --git a/include/linux/rtnetlink.h b/include/linux/rtnetlink.h index b0778a2d45e7..3854002c7eec 100644 --- a/include/linux/rtnetlink.h +++ b/include/linux/rtnetlink.h @@ -589,7 +589,7 @@ extern void rtnetlink_init(void); #define ASSERT_RTNL() do { if (down_trylock(&rtnl_sem) == 0) { up(&rtnl_sem); \ printk("RTNL: assertion failed at " __FILE__ "(%d)\n", __LINE__); } \ - } while(0); + } while(0) #define BUG_TRAP(x) if (!(x)) { printk("KERNEL: assertion (" #x ") failed at " __FILE__ "(%d)\n", __LINE__); } diff --git a/include/linux/sched.h b/include/linux/sched.h index 205c801bea22..024e34706cc9 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -79,7 +79,6 @@ extern int nr_threads; extern int last_pid; extern unsigned long nr_running(void); -#include <linux/fs.h> #include <linux/time.h> #include <linux/param.h> #include <linux/resource.h> diff --git a/include/linux/securebits.h b/include/linux/securebits.h index 1e10badcbdba..5b0617840fa4 100644 --- a/include/linux/securebits.h +++ b/include/linux/securebits.h @@ -6,7 +6,7 @@ extern unsigned securebits; /* When set UID 0 has no special privileges. When unset, we support - inheritance of root-permissions and suid-root executablew under + inheritance of root-permissions and suid-root executable under compatibility mode. We raise the effective and inheritable bitmasks *of the executable file* if the effective uid of the new process is 0. If the real uid is 0, we raise the inheritable bitmask of the diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h index 2bec5fabc4dc..ddfd7b3b1c75 100644 --- a/include/linux/skbuff.h +++ b/include/linux/skbuff.h @@ -16,7 +16,6 @@ #include <linux/config.h> #include <linux/kernel.h> -#include <linux/sched.h> #include <linux/time.h> #include <linux/cache.h> @@ -590,7 +589,7 @@ static inline struct sk_buff *__skb_dequeue(struct sk_buff_head *list) static inline struct sk_buff *skb_dequeue(struct sk_buff_head *list) { - long flags; + unsigned long flags; struct sk_buff *result; spin_lock_irqsave(&list->lock, flags); @@ -739,7 +738,7 @@ static inline struct sk_buff *__skb_dequeue_tail(struct sk_buff_head *list) static inline struct sk_buff *skb_dequeue_tail(struct sk_buff_head *list) { - long flags; + unsigned long flags; struct sk_buff *result; spin_lock_irqsave(&list->lock, flags); diff --git a/include/linux/smb_fs.h b/include/linux/smb_fs.h index f554cf9057a8..e049feae8dea 100644 --- a/include/linux/smb_fs.h +++ b/include/linux/smb_fs.h @@ -12,6 +12,7 @@ #include <linux/smb.h> #include <linux/smb_fs_i.h> #include <linux/smb_fs_sb.h> +#include <linux/fs.h> /* * ioctl commands diff --git a/include/linux/sonypi.h b/include/linux/sonypi.h index 48aab6f712a3..4a53f5b8852a 100644 --- a/include/linux/sonypi.h +++ b/include/linux/sonypi.h @@ -73,11 +73,28 @@ #define SONYPI_EVENT_BACK_PRESSED 35 #define SONYPI_EVENT_LID_CLOSED 36 #define SONYPI_EVENT_LID_OPENED 37 +#define SONYPI_EVENT_BLUETOOTH_ON 38 +#define SONYPI_EVENT_BLUETOOTH_OFF 39 +/* get/set brightness */ +#define SONYPI_IOCGBRT _IOR('v', 0, __u8) +#define SONYPI_IOCSBRT _IOW('v', 0, __u8) -/* brightness etc. ioctls */ -#define SONYPI_IOCGBRT _IOR('v', 0, __u8) -#define SONYPI_IOCSBRT _IOW('v', 0, __u8) +/* get battery full capacity/remaining capacity */ +#define SONYPI_IOCGBAT1CAP _IOR('v', 2, __u16) +#define SONYPI_IOCGBAT1REM _IOR('v', 3, __u16) +#define SONYPI_IOCGBAT2CAP _IOR('v', 4, __u16) +#define SONYPI_IOCGBAT2REM _IOR('v', 5, __u16) + +/* get battery flags: battery1/battery2/ac adapter present */ +#define SONYPI_BFLAGS_B1 0x01 +#define SONYPI_BFLAGS_B2 0x02 +#define SONYPI_BFLAGS_AC 0x04 +#define SONYPI_IOCGBATFLAGS _IOR('v', 7, __u8) + +/* get/set bluetooth subsystem state on/off */ +#define SONYPI_IOCGBLUE _IOR('v', 8, __u8) +#define SONYPI_IOCSBLUE _IOW('v', 9, __u8) #ifdef __KERNEL__ diff --git a/include/linux/spinlock.h b/include/linux/spinlock.h index cd7428798399..a78cd80f4ab6 100644 --- a/include/linux/spinlock.h +++ b/include/linux/spinlock.h @@ -204,7 +204,7 @@ do { \ #else -#define preempt_get_count() do { } while (0) +#define preempt_get_count() (0) #define preempt_disable() do { } while (0) #define preempt_enable_no_resched() do {} while(0) #define preempt_enable() do { } while (0) diff --git a/include/linux/string.h b/include/linux/string.h index b5497d139d28..3d344c0190d8 100644 --- a/include/linux/string.h +++ b/include/linux/string.h @@ -12,9 +12,7 @@ extern "C" { #endif -extern char * ___strtok; extern char * strpbrk(const char *,const char *); -extern char * strtok(char *,const char *); extern char * strsep(char **,const char *); extern __kernel_size_t strspn(const char *,const char *); diff --git a/include/linux/sunrpc/svc.h b/include/linux/sunrpc/svc.h index 2d2461bb38c8..71054b826df2 100644 --- a/include/linux/sunrpc/svc.h +++ b/include/linux/sunrpc/svc.h @@ -123,6 +123,10 @@ struct svc_rqst { /* Catering to nfsd */ struct svc_client * rq_client; /* RPC peer info */ struct svc_cacherep * rq_cacherep; /* cache info */ + struct knfsd_fh * rq_reffh; /* Referrence filehandle, used to + * determine what device number + * to report (real or virtual) + */ wait_queue_head_t rq_wait; /* synchronozation */ }; diff --git a/include/linux/sysctl.h b/include/linux/sysctl.h index 01829afb8e41..30caa40c26be 100644 --- a/include/linux/sysctl.h +++ b/include/linux/sysctl.h @@ -288,7 +288,8 @@ enum NET_TCP_ADV_WIN_SCALE=87, NET_IPV4_NONLOCAL_BIND=88, NET_IPV4_ICMP_RATELIMIT=89, - NET_IPV4_ICMP_RATEMASK=90 + NET_IPV4_ICMP_RATEMASK=90, + NET_TCP_TW_REUSE=91 }; enum { @@ -333,7 +334,8 @@ enum NET_IPV4_CONF_BOOTP_RELAY=10, NET_IPV4_CONF_LOG_MARTIANS=11, NET_IPV4_CONF_TAG=12, - NET_IPV4_CONF_ARPFILTER=13 + NET_IPV4_CONF_ARPFILTER=13, + NET_IPV4_CONF_MEDIUM_ID=14, }; /* /proc/sys/net/ipv6 */ diff --git a/include/linux/ticable.h b/include/linux/ticable.h new file mode 100644 index 000000000000..5aa24b451fba --- /dev/null +++ b/include/linux/ticable.h @@ -0,0 +1,42 @@ +/* Hey EMACS -*- linux-c -*- + * + * tipar/tiser/tiusb - low level driver for handling link cables + * designed for Texas Instruments graphing calculators. + * + * Copyright (C) 2000-2002, Romain Lievin <roms@lpg.ticalc.org> + * + * Redistribution of this file is permitted under the terms of the GNU + * Public License (GPL) + */ + +#ifndef _TICABLE_H +#define _TICABLE_H 1 + +/* Internal default constants for the kernel module */ +#define TIMAXTIME 15 /* 1.5 seconds */ +#define IO_DELAY 10 /* 10 micro-seconds */ + +/* Major & minor number for character devices */ +#define TIPAR_MAJOR 115 /* 0 to 7 */ +#define TIPAR_MINOR 0 + +#define TISER_MAJOR 115 /* 8 to 15 */ +#define TISER_MINOR 8 + +#define TIUSB_MAJOR 115 /* 16 to 31 */ +#define TIUSB_MINOR 16 + +/* + * Request values for the 'ioctl' function. + */ +#define IOCTL_TIPAR_DELAY _IOW('p', 0xa8, int) /* set delay */ +#define IOCTL_TIPAR_TIMEOUT _IOW('p', 0xa9, int) /* set timeout */ + +#define IOCTL_TISER_DELAY _IOW('p', 0xa0, int) /* set delay */ +#define IOCTL_TISER_TIMEOUT _IOW('p', 0xa1, int) /* set timeout */ + +#define IOCTL_TIUSB_TIMEOUT _IOW('N', 0x20, int) /* set timeout */ +#define IOCTL_TIUSB_RESET_DEVICE _IOW('N', 0x21, int) /* reset device */ +#define IOCTL_TIUSB_RESET_PIPES _IOW('N', 0x22, int) /* reset both pipes*/ + +#endif /* TICABLE_H */ diff --git a/include/linux/udf_fs.h b/include/linux/udf_fs.h index 77a54446df3d..07cbb273974f 100644 --- a/include/linux/udf_fs.h +++ b/include/linux/udf_fs.h @@ -34,6 +34,10 @@ #ifndef _UDF_FS_H #define _UDF_FS_H 1 +#include <linux/config.h> + +#include <linux/config.h> + #define UDF_PREALLOCATE #define UDF_DEFAULT_PREALLOC_BLOCKS 8 diff --git a/include/linux/usb.h b/include/linux/usb.h index 391668010831..3b5c1df0ba46 100644 --- a/include/linux/usb.h +++ b/include/linux/usb.h @@ -588,7 +588,7 @@ typedef void (*usb_complete_t)(struct urb *); /** * struct urb - USB Request Block * @urb_list: For use by current owner of the URB. - * @next: Used primarily to link ISO requests into rings. + * @next: Used to link ISO requests into rings. * @pipe: Holds endpoint number, direction, type, and max packet size. * Create these values with the eight macros available; * usb_{snd,rcv}TYPEpipe(dev,endpoint), where the type is "ctrl" @@ -627,8 +627,9 @@ typedef void (*usb_complete_t)(struct urb *); * @start_frame: Returns the initial frame for interrupt or isochronous * transfers. * @number_of_packets: Lists the number of ISO transfer buffers. - * @interval: Specifies the polling interval for interrupt transfers, in - * milliseconds. + * @interval: Specifies the polling interval for interrupt or isochronous + * transfers. The units are frames (milliseconds) for for full and low + * speed devices, and microframes (1/8 millisecond) for highspeed ones. * @error_count: Returns the number of ISO transfers that reported errors. * @context: For use in completion functions. This normally points to * request-specific driver context. @@ -668,12 +669,16 @@ typedef void (*usb_complete_t)(struct urb *); * * Control URBs must provide a setup_packet. * - * Interupt UBS must provide an interval, saying how often (in milliseconds) + * Interrupt UBS must provide an interval, saying how often (in milliseconds + * or, for highspeed devices, 125 microsecond units) * to poll for transfers. After the URB has been submitted, the interval * and start_frame fields reflect how the transfer was actually scheduled. * The polling interval may be more frequent than requested. * For example, some controllers have a maximum interval of 32 microseconds, * while others support intervals of up to 1024 microseconds. + * Isochronous URBs also have transfer intervals. (Note that for isochronous + * endpoints, as well as high speed interrupt endpoints, the encoding of + * the transfer interval in the endpoint descriptor is logarithmic.) * * Isochronous URBs normally use the USB_ISO_ASAP transfer flag, telling * the host controller to schedule the transfer as soon as bandwidth @@ -682,8 +687,8 @@ typedef void (*usb_complete_t)(struct urb *); * and handle the case where the transfer can't begin then. However, drivers * won't know how bandwidth is currently allocated, and while they can * find the current frame using usb_get_current_frame_number () they can't - * know the range for that frame number. (Common ranges for the frame - * counter include 256, 512, and 1024 frames.) + * know the range for that frame number. (Ranges for frame counter values + * are HC-specific, and can go from 256 to 65536 frames from "now".) * * Isochronous URBs have a different data transfer model, in part because * the quality of service is only "best effort". Callers provide specially @@ -734,7 +739,7 @@ struct urb unsigned char *setup_packet; /* (in) setup packet (control only) */ int start_frame; /* (modify) start frame (INT/ISO) */ int number_of_packets; /* (in) number of ISO packets */ - int interval; /* (in) polling interval (INT only) */ + int interval; /* (in) transfer interval (INT/ISO) */ int error_count; /* (return) number of ISO errors */ int timeout; /* (in) timeout, in jiffies */ void *context; /* (in) context for completion */ diff --git a/include/linux/videodev.h b/include/linux/videodev.h index 542e3ececef4..80966ed8e288 100644 --- a/include/linux/videodev.h +++ b/include/linux/videodev.h @@ -37,8 +37,6 @@ struct video_device * video_generic_ioctl() does the userspace copying of the * ioctl arguments */ struct file_operations *fops; - int (*kernel_ioctl)(struct inode *inode, struct file *file, - unsigned int cmd, void *arg); void *priv; /* Used to be 'private' but that upsets C++ */ /* for videodev.c intenal usage -- don't touch */ @@ -60,8 +58,10 @@ extern struct video_device* video_devdata(struct file*); extern int video_exclusive_open(struct inode *inode, struct file *file); extern int video_exclusive_release(struct inode *inode, struct file *file); -extern int video_generic_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg); +extern int video_usercopy(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg, + int (*func)(struct inode *inode, struct file *file, + unsigned int cmd, void *arg)); #endif /* __KERNEL__ */ #define VID_TYPE_CAPTURE 1 /* Can capture */ diff --git a/include/net/irda/discovery.h b/include/net/irda/discovery.h index dccf1246c8ff..8e22eeab5332 100644 --- a/include/net/irda/discovery.h +++ b/include/net/irda/discovery.h @@ -39,6 +39,14 @@ #define DISCOVERY_EXPIRE_TIMEOUT 6*HZ #define DISCOVERY_DEFAULT_SLOTS 0 +/* Types of discovery */ +typedef enum { + DISCOVERY_LOG, /* What's in our discovery log */ + DISCOVERY_ACTIVE, /* Doing our own discovery on the medium */ + DISCOVERY_PASSIVE, /* Peer doing discovery on the medium */ + EXPIRY_TIMEOUT, /* Entry expired due to timeout */ +} DISCOVERY_MODE; + #define NICKNAME_MAX_LEN 21 /* diff --git a/include/net/irda/ircomm_tty.h b/include/net/irda/ircomm_tty.h index d66686510452..77f7dd0d6001 100644 --- a/include/net/irda/ircomm_tty.h +++ b/include/net/irda/ircomm_tty.h @@ -44,6 +44,11 @@ #define IRCOMM_TTY_MAJOR 161 #define IRCOMM_TTY_MINOR 0 +/* This is used as an initial value to max_header_size before the proper + * value is filled in (5 for ttp, 4 for lmp). This allow us to detect + * the state of the underlying connection. - Jean II */ +#define IRCOMM_TTY_HDR_UNITIALISED 32 + /* * IrCOMM TTY driver state */ diff --git a/include/net/irda/irlan_client.h b/include/net/irda/irlan_client.h index 2aab19e9058d..e42871a09642 100644 --- a/include/net/irda/irlan_client.h +++ b/include/net/irda/irlan_client.h @@ -34,7 +34,7 @@ #include <net/irda/irlan_event.h> void irlan_client_start_kick_timer(struct irlan_cb *self, int timeout); -void irlan_client_discovery_indication(discovery_t *, void *); +void irlan_client_discovery_indication(discovery_t *, DISCOVERY_MODE, void *); void irlan_client_wakeup(struct irlan_cb *self, __u32 saddr, __u32 daddr); void irlan_client_open_ctrl_tsap( struct irlan_cb *self); diff --git a/include/net/irda/irlmp.h b/include/net/irda/irlmp.h index 248c1b881adb..fa87b52db321 100644 --- a/include/net/irda/irlmp.h +++ b/include/net/irda/irlmp.h @@ -72,7 +72,7 @@ typedef enum { S_END, } SERVICE; -typedef void (*DISCOVERY_CALLBACK1) (discovery_t *, void *); +typedef void (*DISCOVERY_CALLBACK1) (discovery_t *, DISCOVERY_MODE, void *); typedef void (*DISCOVERY_CALLBACK2) (hashbin_t *, void *); typedef struct { @@ -214,7 +214,7 @@ void irlmp_disconnect_indication(struct lsap_cb *self, LM_REASON reason, struct sk_buff *userdata); int irlmp_disconnect_request(struct lsap_cb *, struct sk_buff *userdata); -void irlmp_discovery_confirm(hashbin_t *discovery_log); +void irlmp_discovery_confirm(hashbin_t *discovery_log, DISCOVERY_MODE); void irlmp_discovery_request(int nslots); struct irda_device_info *irlmp_get_discoveries(int *pn, __u16 mask, int nslots); void irlmp_do_expiry(void); diff --git a/include/net/ndisc.h b/include/net/ndisc.h index 2c37a36e4aa2..407268c78def 100644 --- a/include/net/ndisc.h +++ b/include/net/ndisc.h @@ -42,11 +42,7 @@ extern struct neigh_table nd_tbl; struct nd_msg { struct icmp6hdr icmph; struct in6_addr target; - struct { - __u8 opt_type; - __u8 opt_len; - __u8 link_addr[MAX_ADDR_LEN]; - } opt; + __u8 opt[0]; }; struct ra_msg { diff --git a/include/net/pkt_sched.h b/include/net/pkt_sched.h index 58aa70d2cf84..84c94256dc65 100644 --- a/include/net/pkt_sched.h +++ b/include/net/pkt_sched.h @@ -358,8 +358,8 @@ extern int psched_tod_diff(int delta_sec, int bound); #define PSCHED_TDIFF(tv1, tv2) (long)((tv1) - (tv2)) #define PSCHED_TDIFF_SAFE(tv1, tv2, bound, guard) \ ({ \ - long __delta = (tv1) - (tv2); \ - if ( __delta > (bound)) { __delta = (bound); guard; } \ + long long __delta = (tv1) - (tv2); \ + if ( __delta > (long long)(bound)) { __delta = (bound); guard; } \ __delta; \ }) diff --git a/include/net/sock.h b/include/net/sock.h index d50815f55ff3..57159c6ce0bd 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -80,7 +80,7 @@ typedef struct { do { spin_lock_init(&((__sk)->lock.slock)); \ (__sk)->lock.users = 0; \ init_waitqueue_head(&((__sk)->lock.wq)); \ -} while(0); +} while(0) struct sock { /* Begin of struct sock/struct tcp_tw_bucket shared layout */ diff --git a/include/net/tcp.h b/include/net/tcp.h index c45fc3e12845..1e7cf2cdce47 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -78,7 +78,7 @@ struct tcp_ehash_bucket { */ struct tcp_bind_bucket { unsigned short port; - unsigned short fastreuse; + signed short fastreuse; struct tcp_bind_bucket *next; struct sock *owners; struct tcp_bind_bucket **pprev; @@ -469,6 +469,7 @@ extern int sysctl_tcp_wmem[3]; extern int sysctl_tcp_rmem[3]; extern int sysctl_tcp_app_win; extern int sysctl_tcp_adv_win_scale; +extern int sysctl_tcp_tw_reuse; extern atomic_t tcp_memory_allocated; extern atomic_t tcp_sockets_allocated; @@ -507,7 +508,7 @@ struct open_request { __u16 rmt_port; __u16 mss; __u8 retrans; - __u8 index; + __u8 __pad; __u16 snd_wscale : 4, rcv_wscale : 4, tstamp_ok : 1, @@ -577,9 +578,7 @@ struct tcp_func { struct sk_buff *skb, struct open_request *req, struct dst_entry *dst); - - int (*hash_connecting) (struct sock *sk); - + int (*remember_stamp) (struct sock *sk); __u16 net_header_len; @@ -781,8 +780,7 @@ extern int tcp_v4_connect(struct sock *sk, struct sockaddr *uaddr, int addr_len); -extern int tcp_connect(struct sock *sk, - struct sk_buff *skb); +extern int tcp_connect(struct sock *sk); extern struct sk_buff * tcp_make_synack(struct sock *sk, struct dst_entry *dst, @@ -1834,6 +1832,6 @@ static inline int tcp_paws_check(struct tcp_opt *tp, int rst) return 1; } -#define TCP_CHECK_TIMER(sk) do { } while (0); +#define TCP_CHECK_TIMER(sk) do { } while (0) #endif /* _TCP_H */ |