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2025-11-14arm64: tegra: Remove OTG ID GPIO from Jetson TX2 NXAaron Kling
The P3509 carrier board does not connect the ID GPIO. Prior to this, the GPIO role switch driver could not detect the mode of the OTG port. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-11-14arm64: tegra: Set USB Micro-B port to OTG mode on P3450Aaron Kling
The USB Micro-B port on p3450 is capable of OTG and doesn't need to be hardcoded to peripheral. No other supported Tegra device is set up like this, so align for consistency. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-11-14arm64: tegra: Add NVJPG node for Tegra210 platformsDiogo Ivo
The Tegra X1 chip contains a NVJPG accelerator capable of encoding/decoding JPEG files in hardware. Complete its DT node and enable it. Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-11-14arm64: tegra: Add Tegra210 NVJPG power-domain nodeDiogo Ivo
Add the NVJPG power-domain node in order to support the NVJPG accelerator in Tegra210 platforms. Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-11-14arm64: tegra: Add interrupts for Tegra234 USB wake eventsHaotien Hsu
Add interrupts for Tegra234 USB wake events to support the USB wake-up function. Signed-off-by: Haotien Hsu <haotienh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-11-14arm64: tegra: Add reserved-memory node for P2180Aaron Kling
The Tegra210 L4T bootloader RAM training will corrupt the in-RAM kernel DT if no reserved-memory node exists. This prevents said bootloader from being able to boot a kernel without this node, unless a chainloaded bootloader loads the DT. Add the node to eliminate the requirement for extra boot stages. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-11-14arm64: tegra: Add reserved-memory node for P3450Aaron Kling
The Tegra210 L4T bootloader RAM training will corrupt the in-RAM kernel DT if no reserved-memory node exists. This prevents said bootloader from being able to boot a kernel without this node, unless a chainloaded bootloader loads the DT. Add the node to eliminate the requirement for extra boot stages. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-11-14arm64: tegra: Enable NVDEC and NVENC on Tegra210Aaron Kling
The other engines are already enabled, finish filling out the media engine nodes and power domains. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-11-14arm64: tegra: Fix APB DMA controller node nameNino Zhang
The APB DMA controller node is currently named "dma@60020000", but according to the DT bindings the node name should be "dma-controller". Update the node name to match the binding and fix dtbs_check warnings. Signed-off-by: Nino Zhang <ninozhang001@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-11-14arm64: tegra: Add default GIC address cells on Tegra210Krzysztof Kozlowski
Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: tegra210.dtsi:31.3-41: Warning (interrupt_map): /pcie@1003000:interrupt-map: Missing property '#address-cells' in node /interrupt-controller@50041000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-11-14arm64: tegra: Add default GIC address cells on Tegra194Krzysztof Kozlowski
Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: tegra194.dtsi:2391.4-42: Warning (interrupt_map): /bus@0/pcie@14100000:interrupt-map: Missing property '#address-cells' in node /bus@0/interrupt-controller@3881000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-11-14arm64: tegra: Add default GIC address cells on Tegra186Krzysztof Kozlowski
Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: tegra186.dtsi:1355.3-41: Warning (interrupt_map): /pcie@10003000:interrupt-map: Missing property '#address-cells' in node /interrupt-controller@3881000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-11-14arm64: tegra: Add default GIC address cells on Tegra132Krzysztof Kozlowski
Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: tegra132.dtsi:32.3-41: Warning (interrupt_map): /pcie@1003000:interrupt-map: Missing property '#address-cells' in node /interrupt-controller@50041000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-11-14arm64: tegra: Add OPP tables on Tegra210Aaron Kling
This adds OPP tables for ACTMON and EMC, enabling dynamic frequency scaling for system memory. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-11-14arm64: tegra: Add interconnect properties for Tegra210Aaron Kling
Add interconnect properties to the Memory Controller, External Memory Controller and the Display Controller nodes in order to describe the hardware interconnection. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-11-14arm64: tegra: Add ACTMON on Tegra210Aaron Kling
This enables the action monitor to facilitate dynamic frequency scaling. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-11-14arm64: tegra: Add device-tree node for NVVRS RTCShubhi Garg
Add NVIDIA VRS (Voltage Regulator Specification) RTC device tree node for Tegra234 P3701 and P3767 platforms. Assign VRS RTC as primary RTC (rtc0). Signed-off-by: Shubhi Garg <shgarg@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-11-14arm64: tegra: Move avdd-dsi-csi-supply into CSI nodeSvyatoslav Ryhel
avdd-dsi-csi-supply belongs in CSI node, not VI. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> # tegra20, parallel camera Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-11-14arm64: tegra: Drop redundant clock and reset names from TSEC nodeSvyatoslav Ryhel
Clock and reset names are not needed if node contains only one clock and one reset. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-11-14arm64: tegra: Move HDA into the correct busThierry Reding
HDA is part of the DISP_USB bus, so move it into that and drop the address prefix accordingly. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-11-05arm64: tegra: Add pinctrl definitions for pcie-ep nodesNiklas Cassel
When the PCIe controller is running in endpoint mode, the controller initialization is triggered by a PERST# (PCIe reset) GPIO deassertion. The driver has configured an IRQ to trigger when the PERST# GPIO changes state. Without the pinctrl definition, we do not get an IRQ when PERST# is deasserted, so the PCIe controller never gets initialized. Add the missing definitions, so that the controller actually gets initialized. Fixes: ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT") Fixes: 0580286d0d22 ("arm64: tegra: Add Tegra234 PCIe C4 EP definition") Signed-off-by: Niklas Cassel <cassel@kernel.org> Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> [treding@nvidia.com: add blank lines to separate blocks] Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-10-30arm64: tegra: Add NVIDIA Jetson Nano 2GB Developer Kit supportAaron Kling
This devkit is very similar to P3450, except it has less RAM, no display port, and only 3 USB host ports. Derive from P3450 and disable the hardware that is unavailable. GPIO PA6 is used to control the HDMI power rail and needs to be on for hotplug detect to work. This is mapped to the 3.3V USB hub on P3450. That USB rail is not used here, so delete the regulator to avoid conflicts. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-10-30arm64: tegra: Add Tegra264 audio supportsheetal
- Add the audio devices for the Tegra264 SoC in the tegra264.dtsi file, which includes sound, HDA and APE(Audio Processing Engine) subsystem nodes. APE subsystem includes, - I/O interfaces such as I2S, DMIC and DSPK (all the available instances). - HW accelerators such as ASRC, OPE, MVC, SFC, AMX, ADX and Mixer (all the available instances). - ADMA controller and Interrupt controllers. - Enable the audio nodes in tegra264-p3971.dtsi platform DT file. Signed-off-by: sheetal <sheetal@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-10-30arm64: tegra: Add Tegra186 pin controllersAaron Kling
Add the device tree nodes for the MAIN and AON pin controllers found on the Tegra186 family of SoCs. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-10-16arm64: tegra: Mark Jetson Xavier NX's PHY as a wakeup sourceRussell King (Oracle)
Mark the RTL8211F PHY as a wakeup source for the Jetson Xavier NX. This allows the reworked RTL8211F driver to know that the PHY is wired to wakeup capable hardware, and thus to expose WoL capabilities. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-09-11arm64: tegra: Add I2C nodes for Tegra264Kartik Rajput
Add I2C nodes for Tegra264. Signed-off-by: Kartik Rajput <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-07-31arm64: tegra: Remove numa-node-id propertiesThierry Reding
These were initially added because some software was checking for their presence. However, the device is not NUMA, so adding these is wrong and hence they should be removed. Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-07-11arm64: tegra: Add p3971-0089+p3834-0008 supportThierry Reding
The P3971-0089+P3834-0008 is an engineering reference platform for the Tegra264 SoC. Link: https://lore.kernel.org/r/20250709231401.3767130-3-thierry.reding@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-07-11arm64: tegra: Add memory controller on Tegra264Thierry Reding
Link: https://lore.kernel.org/r/20250709231401.3767130-4-thierry.reding@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-07-11arm64: tegra: Add Tegra264 supportThierry Reding
Add basic support for the Tegra264 SoC, sufficient for booting into an initial ramdisk. Link: https://lore.kernel.org/r/20250709231401.3767130-2-thierry.reding@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-05-21Merge tag 'dt64-cleanup-6.16' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt Minor improvements in ARM64 DTS for v6.16 Two cleanups which were missed on mailing lists - align GPIO node names with DT bindings for Mediatek mt7622 and Nvidia Tegra210-p2894. * tag 'dt64-cleanup-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt: arm64: tegra: tegra210-p2894: Align GPIO hog node name with preferred style arm64: dts: mediatek: mt7622: Align GPIO hog name with bindings Link: https://lore.kernel.org/r/20250513104216.25803-4-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-05-08arm64: tegra: Wire up CEC to devkitsAaron Kling
This enables HDMI CEC and routes it to the HDMI port on all supported Tegra210, Tegra186, and Tegra194 devkits. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Link: https://lore.kernel.org/r/20250413-tegra-cec-v4-4-b6337b66ccad@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-05-08arm64: tegra: Add CEC controller on Tegra210Aaron Kling
The CEC controller found on Tegra210 can be used to control consumer devices using the HDMI CEC pin. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Link: https://lore.kernel.org/r/20250413-tegra-cec-v4-3-b6337b66ccad@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-05-08arm64: tegra: Add fallback CEC compatiblesAaron Kling
The tegra_cec driver only declares support up to Tegra210 and will not declare support for Tegra186 or Tegra194. Thus list a fallback compatible for these chips to tegra210-cec as they work as-is with the existing driver. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Link: https://lore.kernel.org/r/20250413-tegra-cec-v4-2-b6337b66ccad@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-05-08arm64: tegra: Add uartd serial alias for Jetson TX1 moduleAaron Kling
If a serial-tegra interface does not have an alias, the driver fails to probe with an error: serial-tegra 70006300.serial: failed to get alias id, errno -19 This prevents the bluetooth device from being accessible. Fixes: 6eba6471bbb7 ("arm64: tegra: Wire up Bluetooth on Jetson TX1 module") Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Reviewed-by: Tomasz Maciej Nowak <tmn505@gmail.com> Link: https://lore.kernel.org/r/20250420-tx1-bt-v1-1-153cba105a4e@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-05-08arm64: tegra: Bump #address-cells and #size-cells on Tegra186Aaron Kling
This was done for Tegra194 and Tegra234 in 2838cfd, but Tegra186 was not part of that change. The same reasoning for that commit also applies to Tegra186, plus keeping the archs as close to each other as possible makes it easier to compare between them and support features concurrently. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Link: https://lore.kernel.org/r/20250419-tegra186-host1x-addr-size-v1-1-a7493882248d@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-05-08arm64: tegra: p2180: Explicitly enable GPUAaron Kling
The gpu node originally was explicitly left disabled as it was expected for the bootloader to enable it. However, this is only done in u-boot. If u-boot is not in the boot chain, this will never be enabled. Other Tegra210 devices already explicitly enable the gpu, so make p2180 match. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Link: https://lore.kernel.org/r/20250420-tx1-gpu-v1-1-d500de18e43e@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-05-08arm64: tegra: p3310: Explicitly enable GPUAaron Kling
The gpu node originally was explicitly left disabled as it was expected for the bootloader to enable it. However, this is only done in U-Boot. If U-Boot is not in the boot chain, this will never be enabled. Other Tegra186 devices already explicitly enable the GPU, so make p3310 match. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Link: https://lore.kernel.org/r/20250426-tx2-gpu-v1-1-fa1c78dcdbdc@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-05-08arm64: tegra: Add DMA properties for Tegra186 and Tegra194 UARTsAaron Kling
Adding the missing dmas and dma-names properties which are required for uart when using with the Tegra HSUART driver. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Link: https://lore.kernel.org/r/20250428-tegra-serial-fixes-v1-2-4f47c5d85bf6@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-05-08arm64: tegra: Drop remaining serial clock-names and reset-namesAaron Kling
The referenced commit only removed some of the names, missing all that weren't in use at the time. The commit removes the rest. Fixes: 71de0a054d0e ("arm64: tegra: Drop serial clock-names and reset-names") Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Link: https://lore.kernel.org/r/20250428-tegra-serial-fixes-v1-1-4f47c5d85bf6@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-05-08arm64: tegra: Enable PWM fan on the Jetson TX2 DevkitAaron Kling
This is based on the existing configuration of the Jetson TX2 NX devkit. The fan and thermal characteristics of the two devkits are similar, so using the same configuration. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Link: https://lore.kernel.org/r/20250427-tx2-therm-v1-1-65ddb4314723@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-05-08arm64: tegra: Enable PWM fan on the Jetson TX1 DevkitAaron Kling
This is based on 6f78a94, which enabled added the fan and thermal zones for the Jetson Nano Devkit. The fan and thermal characteristics of the two devkits are similar, so using the same configuration. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Link: https://lore.kernel.org/r/20250501-tx1-therm-v2-1-abdb1922c001@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-05-08arm64: tegra: Add I2C aliases for Tegra234Akhil R
Add aliases for all I2C nodes so that the I2C devnode numbers align with hardware bus number. Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Link: https://lore.kernel.org/r/20250506095936.10687-4-akhilrajeev@nvidia.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-05-08arm64: tegra: Configure QSPI clocks and add DMAVishwaroop A
For Tegra234 devices, set QSPI0_2X_PM to 199.99 MHz and QSPI0_PM to 99.99 MHz using PLLC as the parent clock. These frequencies enable Quad IO reads at up to 99.99 MHz, the maximum achievable given PLL and clock divider limitations. Introduce IOMMU property which is needed for internal DMA transfers. Signed-off-by: Vishwaroop A <va@nvidia.com> Link: https://lore.kernel.org/r/20250506152350.3370291-2-va@nvidia.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-05-05arm64: tegra: tegra210-p2894: Align GPIO hog node name with preferred styleKrzysztof Kozlowski
GPIO hogs device node names can use 'hog' prefix or suffix, but the suffix is preferred. The pattern in DT schema might narrow in the future, so adjust the DTS now. Link: https://lore.kernel.org/r/20250115204603.136997-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-03-14Merge tag 'tegra-for-6.15-arm64-dt-v2' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt arm64: tegra: Device tree changes for v6.15-rc1 This contains a patch to remove an unusable key that was erroneously exposed as well as a fix to support GPUs with a large amount of video memory on IGX Orin. Finally, some additional devices, such as a temperature sensor, are enabled on Jetson TX1, the output voltage of some pins is adjusted and the VDD_LCD_1V8_DIS power supply now uses the correct enable GPIO. * tag 'tegra-for-6.15-arm64-dt-v2' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: p2180: Add TMP451 temperature sensor node arm64: tegra: p2597: Enable TCA9539 as IRQ controllers arm64: tegra: Define pinmuxing for gpio pads on Tegra210 arm64: tegra: p2597: Fix gpio for vdd-1v8-dis regulator arm64: tegra: Resize aperture for the IGX PCIe C5 slot arm64: tegra: Remove the Orin NX/Nano suspend key Link: https://lore.kernel.org/r/20250307174938.3456275-1-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-03-07arm64: tegra: p2180: Add TMP451 temperature sensor nodeDiogo Ivo
The Jetson TX1 module contains a TI TMP451 temperature sensor. Add a DT node for it. Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Link: https://lore.kernel.org/r/20250224-diogo-gpio_exp-v1-4-80fb84ac48c6@tecnico.ulisboa.pt Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-03-07arm64: tegra: p2597: Enable TCA9539 as IRQ controllersDiogo Ivo
Fill out the DT nodes enabling both TCA9539 chips as IRQ controllers. Proper functionality was tested for both instances. Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Link: https://lore.kernel.org/r/20250224-diogo-gpio_exp-v1-3-80fb84ac48c6@tecnico.ulisboa.pt Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-03-07arm64: tegra: Define pinmuxing for gpio pads on Tegra210Diogo Ivo
As the gpio pads are capable of operating at either 1.8V or 3.3V add both options to the pinmuxing so that the appropriate level can be set depending on the voltage of the regulator driving the pads. Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Link: https://lore.kernel.org/r/20250224-diogo-gpio_exp-v1-2-80fb84ac48c6@tecnico.ulisboa.pt Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-03-07arm64: tegra: p2597: Fix gpio for vdd-1v8-dis regulatorDiogo Ivo
According to the board schematics the enable pin of this regulator is connected to gpio line #9 of the first instance of the TCA9539 GPIO expander, so adjust it. Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Link: https://lore.kernel.org/r/20250224-diogo-gpio_exp-v1-1-80fb84ac48c6@tecnico.ulisboa.pt Signed-off-by: Thierry Reding <treding@nvidia.com>
generated by cgit v1.2.3 (git 2.46.0) at 2026-01-06 15:38:40 +0000