user/sven/linux.git - Linux Kernel

Age	Commit message (Expand)	Author
2015-03-02	KVM: MIPS: Enable after disabling interrupt	Tapasweni Pathak
2015-03-02	KVM: MIPS: Fix trace event to save PC directly	James Hogan
2015-02-21	Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus	Linus Torvalds
2015-02-21	Merge tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/...	Linus Torvalds
2015-02-20	MIPS: sead3: Corrected get_c0_perfcount_int	Niklas Cassel
2015-02-20	MIPS: mm: Remove dead macro definitions	Andreas Ruprecht
2015-02-20	MIPS: OCTEON: irq: add CIB and other fixes	David Daney
2015-02-20	MIPS: OCTEON: Don't do acknowledge operations for level triggered irqs.	David Daney
2015-02-20	MIPS: OCTEON: More OCTEONIII support	Chandrakala Chavva
2015-02-20	MIPS: OCTEON: Remove setting of processor specific CVMCTL icache bits.	Chad Reese
2015-02-20	MIPS: OCTEON: Core-15169 Workaround and general CVMSEG cleanup.	David Daney
2015-02-20	MIPS: OCTEON: Update octeon-model.h code for new SoCs.	David Daney
2015-02-20	MIPS: OCTEON: Implement DCache errata workaround for all CN6XXX	David Daney
2015-02-20	MIPS: OCTEON: Add little-endian support to asm/octeon/octeon.h	David Daney
2015-02-20	MIPS: OCTEON: Implement the core-16057 workaround	David Daney
2015-02-20	MIPS: OCTEON: Delete unused COP2 saving code	Aleksey Makarov
2015-02-20	MIPS: OCTEON: Use correct instruction to read 64-bit COP0 register	Chandrakala Chavva
2015-02-20	MIPS: OCTEON: Save and restore CP2 SHA3 state	David Daney
2015-02-20	MIPS: OCTEON: Fix FP context save.	David Daney
2015-02-20	MIPS: OCTEON: Save/Restore wider multiply registers in OCTEON III CPUs	David Daney
2015-02-20	MIPS: boot: Provide more uImage options	Markos Chandras
2015-02-20	MIPS: Remove unneeded #ifdef __KERNEL__ from asm/processor.h	David Daney
2015-02-20	MIPS: ip22-gio: Remove legacy suspend/resume support	Lars-Peter Clausen
2015-02-20	mips: pci: Add ifdef around pci_proc_domain	Zubair Lutfullah Kakakhel
2015-02-20	MIPS: Alchemy: Fix cpu clock calculation	Manuel Lauss
2015-02-20	MIPS: Alchemy: remove declaration for set_cpuspec	Manuel Lauss
2015-02-20	MIPS: Alchemy: preset loops_per_jiffy based on CPU clock	Manuel Lauss
2015-02-20	MIPS: Alchemy: fix Au1000/Au1500 LRCLK calculation	Manuel Lauss
2015-02-20	MIPS: Add set/clear CP0 macros for PageGrain register	Steven J. Hill
2015-02-19	MIPS: Usage and cosmetic cleanups of page table bits.	Steven J. Hill
2015-02-19	Merge branch 'kconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/mmare...	Linus Torvalds
2015-02-19	Merge branch 'mipsr6-for-3.20' of git://git.linux-mips.org/pub/scm/mchandras/...	Ralf Baechle
2015-02-19	MIPS: Export MSA functions used by lose_fpu(1) for KVM	James Hogan
2015-02-19	MIPS: Export FP functions used by lose_fpu(1) for KVM	James Hogan
2015-02-19	MIPS: BCM3384: Fix outdated use of mips_cpu_intc_init()	Kevin Cernekee
2015-02-19	MIPS: Provide correct siginfo_t.si_stime	Petr Malat
2015-02-19	MIPS: Makefile: Move the ASEs checks after setting the core's CFLAGS	Markos Chandras
2015-02-19	MIPS: Makefile: Pass -march option on Loongson3A cores	Ralf Baechle
2015-02-18	MIPS: Alchemy: Remove bogus args from alchemy_clk_fgcs_detr	Tomeu Vizoso
2015-02-18	Merge tag 'for-linus-20150216' of git://git.infradead.org/linux-mtd	Linus Torvalds
2015-02-17	MIPS: Add Malta QEMU 32R6 defconfig	Markos Chandras
2015-02-17	MIPS: Malta: Add support for building MIPS R6 kernel	Markos Chandras
2015-02-17	MIPS: kernel: elf: Improve the overall ABI and FPU mode checks	Markos Chandras
2015-02-17	MIPS: asm: fpu: Allow 64-bit FPU on MIPS32 R6	Markos Chandras
2015-02-17	MIPS: kernel: process: Do not allow FR=0 on MIPS R6	Markos Chandras
2015-02-17	MIPS: Handle MIPS IV, V and R2 FPU instructions on MIPS R6 as well	Markos Chandras
2015-02-17	MIPS: Make use of the ERETNC instruction on MIPS R6	Markos Chandras
2015-02-17	MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6	Leonid Yegoshin
2015-02-17	MIPS: asm: mipsregs: Add support for the LLADDR register	Markos Chandras
2015-02-17	MIPS: Add LLB bit and related feature for the Config 5 CP0 register	Markos Chandras