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path: root/drivers/clk
AgeCommit message (Expand)Author
2021-10-20clk: socfpga: agilex: fix duplicate s2f_user0_clkDinh Nguyen
2021-09-30treewide: Change list_sort to use const pointersSami Tolvanen
2021-09-18clk: at91: clk-generated: Limit the requested rate to our rangeCodrin Ciubotariu
2021-09-18clk: imx8m: fix clock tree update of TF-A managed clocksAhmad Fatoum
2021-09-18clk: rockchip: drop GRF dependency for rk3328/rk3036 pll typesPeter Geis
2021-09-18clk: socfpga: agilex: add the bypass register for s2f_usr0 clockDinh Nguyen
2021-09-18clk: socfpga: agilex: fix up s2f_user0_clk representationDinh Nguyen
2021-09-18clk: socfpga: agilex: fix the parents of the psi_ref_clkDinh Nguyen
2021-09-15clk: kirkwood: Fix a clocking boot regressionLinus Walleij
2021-09-03clk: renesas: rcar-usb2-clock-sel: Fix kernel NULL pointer dereferenceAdam Ford
2021-08-26clk: qcom: gdsc: Ensure regulator init state matches GDSC stateBjorn Andersson
2021-08-26clk: imx6q: fix uart earlycon unworkDong Aisheng
2021-08-12clk: fix leak on devm_clk_bulk_get_all() unwindBrian Norris
2021-08-12clk: tegra: Implement disable_unused() of tegra_clk_sdmmc_mux_opsDmitry Osipenko
2021-08-12clk: stm32f4: fix post divisor setup for I2S/SAI PLLsDario Binacchi
2021-07-19clk: tegra: Ensure that PLLU configuration is applied properlyDmitry Osipenko
2021-07-19clk: tegra: Fix refcounting of gate clocksDmitry Osipenko
2021-07-19clk: renesas: r8a77995: Add ZA2 clockKuninori Morimoto
2021-07-19clk: renesas: rcar-usb2-clock-sel: Fix error handling in .probe()Dinghao Liu
2021-07-14clk: si5341: Update initialization magicRobert Hancock
2021-07-14clk: si5341: Check for input clock presence and PLL lock on startupRobert Hancock
2021-07-14clk: si5341: Avoid divide errors due to bogus register contentsRobert Hancock
2021-07-14clk: si5341: Wait for DEVICE_READY on startupRobert Hancock
2021-07-14clk: qcom: clk-alpha-pll: fix CAL_L write in alpha_pll_fabia_prepareJonathan Marek
2021-07-14clk: actions: Fix AHPPREDIV-H-AHB clock chain on Owl S500 SoCCristian Ciocaltea
2021-07-14clk: actions: Fix bisp_factor_table based clocks on Owl S500 SoCCristian Ciocaltea
2021-07-14clk: actions: Fix SD clocks factor table on Owl S500 SoCCristian Ciocaltea
2021-07-14clk: actions: Fix UART clock dividers on Owl S500 SoCCristian Ciocaltea
2021-07-14clk: imx8mq: remove SYS PLL 1/2 clock gatesLucas Stach
2021-07-14clk: vc5: fix output disabling when enabling a FODLuca Ceresoli
2021-07-14clk: tegra30: Use 300MHz for video decoder by defaultDmitry Osipenko
2021-07-14clk: meson: g12a: fix gp0 and hifi rangesJerome Brunet
2021-07-14clk: agilex/stratix10: fix bypass representationDinh Nguyen
2021-07-14clk: agilex/stratix10: remove noc_clkDinh Nguyen
2021-07-14clk: agilex/stratix10/n5x: fix how the bypass_reg is handledDinh Nguyen
2021-05-19clk: exynos7: Mark aclk_fsys1_200 as criticalPaweł Chmiel
2021-05-14clk: uniphier: Fix potential infinite loopColin Ian King
2021-05-14clk: qcom: apss-ipq-pll: Add missing MODULE_DEVICE_TABLEChen Hui
2021-05-14clk: qcom: a53-pll: Add missing MODULE_DEVICE_TABLEChen Hui
2021-05-14clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enableQuanyang Wang
2021-05-14clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callbackQuanyang Wang
2021-05-14clk: imx: Fix reparenting of UARTs not associated with stdoutAdam Ford
2021-05-14media: aspeed: fix clock handling logicJae Hyun Yoo
2021-05-14clk: mvebu: armada-37xx-periph: Fix workaround for switching from L1 to L0Pali Rohár
2021-05-14clk: mvebu: armada-37xx-periph: Fix switching CPU freq from 250 Mhz to 1 GHzPali Rohár
2021-05-14clk: mvebu: armada-37xx-periph: remove .set_parent method for CPU PM clockMarek Behún
2021-05-11clk: socfpga: arria10: Fix memory leak of socfpga_clk on error returnColin Ian King
2021-04-14clk: socfpga: fix iomem pointer cast on 64-bitKrzysztof Kozlowski
2021-04-14clk: fix invalid usage of list cursor in unregisterLukasz Bartosik
2021-04-14clk: fix invalid usage of list cursor in registerLukasz Bartosik