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path: root/drivers/clk
AgeCommit message (Expand)Author
2021-04-14clk: socfpga: fix iomem pointer cast on 64-bitKrzysztof Kozlowski
2021-04-14clk: fix invalid usage of list cursor in unregisterLukasz Bartosik
2021-04-14clk: fix invalid usage of list cursor in registerLukasz Bartosik
2021-04-14clk: qcom: camcc: Update the clock ops for the SC7180Taniya Das
2021-03-30clk: qcom: gcc-sc7180: Use floor ops for the correct sdcc1 clkDouglas Anderson
2021-03-17clk: qcom: gpucc-msm8998: Add resets, cxc, fix flags on gpu_gx_gdscAngeloGioacchino Del Regno
2021-03-17clk: qcom: gdsc: Implement NO_RET_PERIPH flagAngeloGioacchino Del Regno
2021-03-04clk: aspeed: Fix APLL calculate formula from ast2600-A2Ryan Chen
2021-03-04clk: divider: fix initialization with parent_hwMichael Tretter
2021-03-04clk: qcom: gcc-msm8998: Fix Alpha PLL type for all GPLLsAngeloGioacchino Del Regno
2021-03-04clk: qcom: gcc-sc7180: Mark the MM XO clocks to be always ONTaniya Das
2021-03-04clk: qcom: gfm-mux: fix clk maskSrinivas Kandagatla
2021-03-04clk: sunxi-ng: h6: Fix clock divider range on some clocksAndre Przywara
2021-03-04clk: renesas: r8a779a0: Fix parent of CBFUSA clockGeert Uytterhoeven
2021-03-04clk: renesas: r8a779a0: Remove non-existent S2 clockGeert Uytterhoeven
2021-03-04clk: sunxi-ng: h6: Fix CEC clockAndre Przywara
2021-03-04clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate()Martin Blumenstingl
2021-03-04clk: meson: clk-pll: make "ret" a signed integerMartin Blumenstingl
2021-03-04clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLLMartin Blumenstingl
2021-02-13Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds
2021-02-11clk: sunxi-ng: mp: fix parent rate change flag checkJernej Skrabec
2021-01-28Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds
2021-01-12clk: mmp2: fix build without CONFIG_PMArnd Bergmann
2021-01-12clk: qcom: gcc-sm250: Use floor ops for sdcc clksDmitry Baryshkov
2021-01-12clk: imx: fix Kconfig warning for i.MX SCU clkArnd Bergmann
2021-01-12clk: qcom: gcc-sc7180: Mark the camera abh clock always ONTaniya Das
2021-01-12clk: tegra30: Add hda clock default rates to clock driverPeter Geis
2020-12-21Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds
2020-12-20Merge branches 'clk-ingenic', 'clk-vc5', 'clk-cleanup', 'clk-canaan' and 'clk...Stephen Boyd
2020-12-20Merge branches 'clk-ti', 'clk-analog', 'clk-trace', 'clk-at91' and 'clk-silab...Stephen Boyd
2020-12-20Merge branches 'clk-tegra', 'clk-imx', 'clk-sifive', 'clk-mediatek' and 'clk-...Stephen Boyd
2020-12-20Merge branches 'clk-amlogic', 'clk-rockchip', 'clk-of', 'clk-freescale' and '...Stephen Boyd
2020-12-20Merge branches 'clk-doc', 'clk-qcom', 'clk-simplify', 'clk-hw', 'clk-renesas'...Stephen Boyd
2020-12-19clk: vc5: Use "idt,voltage-microvolt" instead of "idt,voltage-microvolts"Geert Uytterhoeven
2020-12-19clk: ingenic: Fix divider calculation with div tablesPaul Cercueil
2020-12-19clk: sunxi-ng: Make sure divider tables have sentinelJernej Skrabec
2020-12-19clk: s2mps11: Fix a resource leak in error handling paths in the probe functionChristophe JAILLET
2020-12-19clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9Terry Zhou
2020-12-19clk: si5351: Wait for bit clear after PLL resetSascha Hauer
2020-12-19clk: at91: sam9x60: remove atmel,osc-bypass supportAlexandre Belloni
2020-12-19clk: at91: sama7g5: register cpu clockClaudiu Beznea
2020-12-19clk: at91: clk-master: re-factor master clockClaudiu Beznea
2020-12-19clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHzClaudiu Beznea
2020-12-19clk: at91: sama7g5: decrease lower limit for MCK0 rateClaudiu Beznea
2020-12-19clk: at91: sama7g5: remove mck0 from parent list of other clocksClaudiu Beznea
2020-12-19clk: at91: clk-sam9x60-pll: allow runtime changes for pllClaudiu Beznea
2020-12-19clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristicsEugen Hristev
2020-12-19clk: at91: clk-master: add 5th divisor for mck masterEugen Hristev
2020-12-19clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DTEugen Hristev
2020-12-19dt-bindings: clock: at91: add sama7g5 pll definesEugen Hristev