user/sven/linux.git - Linux Kernel

Age	Commit message (Expand)	Author
2021-11-26	clk: qcom: gcc-msm8996: Drop (again) gcc_aggre1_pnoc_ahb_clk	Dmitry Baryshkov
2021-11-26	clk/ast2600: Fix soc revision for AHB	Joel Stanley
2021-11-26	clk: ingenic: Fix bugs with divided dividers	Paul Cercueil
2021-11-26	clk: imx: imx6ul: Move csi_sel mux to correct base register	Stefan Riedmueller
2021-11-17	clk: at91: check pmc node status before registering syscore ops	Clément Léger
2021-11-17	clk: mvebu: ap-cpu-clk: Fix a memory leak in error handling paths	Christophe JAILLET
2021-09-22	clk: at91: clk-generated: Limit the requested rate to our range	Codrin Ciubotariu
2021-09-22	clk: at91: clk-generated: pass the id of changeable parent at registration	Claudiu Beznea
2021-09-22	clk: at91: sam9x60: Don't use audio PLL	Codrin Ciubotariu
2021-09-15	clk: kirkwood: Fix a clocking boot regression	Linus Walleij
2021-08-12	clk: fix leak on devm_clk_bulk_get_all() unwind	Brian Norris
2021-08-12	clk: stm32f4: fix post divisor setup for I2S/SAI PLLs	Dario Binacchi
2021-07-19	clk: tegra: Ensure that PLLU configuration is applied properly	Dmitry Osipenko
2021-07-19	clk: renesas: r8a77995: Add ZA2 clock	Kuninori Morimoto
2021-07-14	clk: si5341: Update initialization magic	Robert Hancock
2021-07-14	clk: si5341: Avoid divide errors due to bogus register contents	Robert Hancock
2021-07-14	clk: actions: Fix bisp_factor_table based clocks on Owl S500 SoC	Cristian Ciocaltea
2021-07-14	clk: actions: Fix SD clocks factor table on Owl S500 SoC	Cristian Ciocaltea
2021-07-14	clk: actions: Fix UART clock dividers on Owl S500 SoC	Cristian Ciocaltea
2021-07-14	clk: meson: g12a: fix gp0 and hifi ranges	Jerome Brunet
2021-06-23	clocksource/drivers/timer-ti-dm: Handle dra7 timer wrap errata i940	Tony Lindgren
2021-05-19	clk: exynos7: Mark aclk_fsys1_200 as critical	Paweł Chmiel
2021-05-14	clk: uniphier: Fix potential infinite loop	Colin Ian King
2021-05-14	clk: qcom: a53-pll: Add missing MODULE_DEVICE_TABLE	Chen Hui
2021-05-14	clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callback	Quanyang Wang
2021-05-14	media: aspeed: fix clock handling logic	Jae Hyun Yoo
2021-05-14	clk: mvebu: armada-37xx-periph: Fix workaround for switching from L1 to L0	Pali Rohár
2021-05-14	clk: mvebu: armada-37xx-periph: Fix switching CPU freq from 250 Mhz to 1 GHz	Pali Rohár
2021-05-14	clk: mvebu: armada-37xx-periph: remove .set_parent method for CPU PM clock	Marek Behún
2021-05-11	clk: socfpga: arria10: Fix memory leak of socfpga_clk on error return	Colin Ian King
2021-04-14	clk: socfpga: fix iomem pointer cast on 64-bit	Krzysztof Kozlowski
2021-04-14	clk: fix invalid usage of list cursor in unregister	Lukasz Bartosik
2021-04-14	clk: fix invalid usage of list cursor in register	Lukasz Bartosik
2021-03-04	clk: aspeed: Fix APLL calculate formula from ast2600-A2	Ryan Chen
2021-03-04	clk: qcom: gcc-msm8998: Fix Alpha PLL type for all GPLLs	AngeloGioacchino Del Regno
2021-03-04	clk: sunxi-ng: h6: Fix clock divider range on some clocks	Andre Przywara
2021-03-04	clk: sunxi-ng: h6: Fix CEC clock	Andre Przywara
2021-03-04	clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate()	Martin Blumenstingl
2021-03-04	clk: meson: clk-pll: make "ret" a signed integer	Martin Blumenstingl
2021-03-04	clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLL	Martin Blumenstingl
2021-02-17	clk: sunxi-ng: mp: fix parent rate change flag check	Jernej Skrabec
2021-01-27	clk: tegra30: Add hda clock default rates to clock driver	Peter Geis
2020-12-30	clk: tegra: Do not return 0 on failure	Nicolin Chen
2020-12-30	clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9	Terry Zhou
2020-12-30	clk: ingenic: Fix divider calculation with div tables	Paul Cercueil
2020-12-30	clk: sunxi-ng: Make sure divider tables have sentinel	Jernej Skrabec
2020-12-30	clk: s2mps11: Fix a resource leak in error handling paths in the probe function	Christophe JAILLET
2020-12-30	clk: at91: sam9x60: remove atmel,osc-bypass support	Alexandre Belloni
2020-12-30	clk: ti: Fix memleak in ti_fapll_synth_setup	Zhang Qilong
2020-12-30	clk: tegra: Fix duplicated SE clock entry	Dmitry Osipenko