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path: root/drivers/pci/controller
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2025-12-03Merge branch 'pci/controller/s32g'Bjorn Helgaas
- Add NXP S32G host controller DT binding and driver (Vincent Guittot) * pci/controller/s32g: MAINTAINERS: Add NXP S32G PCIe controller driver maintainer PCI: s32g: Add NXP S32G PCIe controller driver (RC) PCI: dwc: Add register and bitfield definitions dt-bindings: PCI: s32g: Add NXP S32G PCIe controller
2025-12-03Merge branch 'pci/controller/rzg3s-host'Bjorn Helgaas
- Add Renesas RZ/G3S host controller DT binding and driver (Claudiu Beznea) * pci/controller/rzg3s-host: PCI: Add Renesas RZ/G3S host controller driver dt-bindings: PCI: Add Renesas RZ/G3S PCIe controller binding
2025-12-03Merge branch 'pci/controller/rcar-gen2'Bjorn Helgaas
- Drop ARM dependency so we can build test on other arches (Geert Uytterhoeven) * pci/controller/rcar-gen2: PCI: rcar-gen2: Drop ARM dependency from PCI_RCAR_GEN2
2025-12-03Merge branch 'pci/controller/qcom'Bjorn Helgaas
- Look up OPP using both frequency and data rate (not just frequency) so RPMh votes can account for both (Krishna Chaitanya Chundru) * pci/controller/qcom: PCI: qcom: Use frequency and level based OPP lookup
2025-12-03Merge branch 'pci/controller/meson'Bjorn Helgaas
- Update DT binding to name DBI region "dbi", not "elbi", and update driver to support both (Manivannan Sadhasivam) * pci/controller/meson: PCI: meson: Fix parsing the DBI register region dt-bindings: PCI: amlogic: Fix the register name of the DBI region
2025-12-03Merge branch 'pci/controller/mediatek'Bjorn Helgaas
- Convert DT binding to YAML schema (Christian Marangi) - Add Airoha AN7583 DT compatible and driver support (Christian Marangi) * pci/controller/mediatek: PCI: mediatek: Add support for Airoha AN7583 SoC PCI: mediatek: Use generic MACRO for TPVPERL delay PCI: mediatek: Convert bool to single quirks entry and bitmap dt-bindings: PCI: mediatek: Add support for Airoha AN7583 dt-bindings: PCI: mediatek: Convert to YAML schema
2025-12-03Merge branch 'pci/controller/keystone'Bjorn Helgaas
- Fail the probe instead of silently succeeding if ks_pcie_of_data didn't specify Root Complex or Endpoint mode (Siddharth Vadapalli) - Make keystone buildable as a loadable module, except on ARM32 where hook_fault_code() is __init (Siddharth Vadapalli) * pci/controller/keystone: PCI: keystone: Add support to build as a loadable module PCI: dwc: Export dw_pcie_allocate_domains() and dw_pcie_ep_raise_msix_irq() PCI: Export pci_get_host_bridge_device() for use by pci-keystone PCI: keystone: Exit ks_pcie_probe() for invalid mode
2025-12-03Merge branch 'pci/controller/j721e'Bjorn Helgaas
- Use devm_clk_get_optional_enabled() instead of open-coding devm_clk_get_optional() and clk_prepare_enable() (Anand Moon) * pci/controller/j721e: PCI: j721e: Use 'pcie->reset_gpio' directly and drop the local variable PCI: j721e: Use devm_clk_get_optional_enabled() to get and enable the clock
2025-12-03Merge branch 'pci/controller/ixp4xx'Bjorn Helgaas
- Guard ARM32-specific hook_fault_code() with ifdefs so we can build test on other arches (Bjorn Helgaas) * pci/controller/ixp4xx: PCI: ixp4xx: Guard ARM32-specific hook_fault_code()
2025-12-03Merge branch 'pci/controller/dw-rockchip'Bjorn Helgaas
- Use devm_regulator_get_enable_optional() to simplify probing (Anand Moon) * pci/controller/dw-rockchip: PCI: dw-rockchip: Simplify regulator setup with devm_regulator_get_enable_optional()
2025-12-03Merge branch 'pci/controller/dwc'Bjorn Helgaas
- Update PORT_LOGIC_LTSSM_STATE_MASK to be a 6-bit mask as per spec, not a 5-bit mask (Shawn Lin) - Clear L1 PM Substate Capability 'Supported' bits unless glue driver says it's supported, which prevents users from enabling non-working L1SS. Currently only qcom and tegra194 support L1SS (Bjorn Helgaas) - Remove now-superfluous L1SS disable code from tegra194 (Bjorn Helgaas) - Configure L1SS support in dw-rockchip when DT says 'supports-clkreq' (Shawn Lin) * pci/controller/dwc: PCI: dw-rockchip: Configure L1SS support PCI: tegra194: Remove unnecessary L1SS disable code PCI: dwc: Advertise L1 PM Substates only if driver requests it PCI: dwc: Fix wrong PORT_LOGIC_LTSSM_STATE_MASK definition
2025-12-03Merge branch 'pci/controller/brcmstb'Bjorn Helgaas
- Disable advertising ASPM L0s support correctly (Jim Quinlan) - Add a panic/die handler to print diagnostic info in case PCIe caused an unrecoverable abort (Jim Quinlan) * pci/controller/brcmstb: PCI: brcmstb: Add panic/die handler to driver PCI: brcmstb: Add a way to indicate if PCIe bridge is active PCI: brcmstb: Fix disabling L0s capability
2025-12-03Merge branch 'pci/controller/host-common'Bjorn Helgaas
- Move struct pci_host_bridge allocation from pci_host_common_init() to callers, which significantly simplifies pcie-apple (Marc Zyngier) * pci/controller/host-common: PCI: host-generic: Move bridge allocation outside of pci_host_common_init()
2025-12-02PCI: sky1: Add PCIe host support for CIX Sky1Hans Zhang
Add driver for the CIX Sky1 SoC PCIe Gen4 16 GT/s controller based on the Cadence High Performance Architecture (HPA) PCIe core. The controller supports MSI/MSI-X via GICv3, Single Virtual Channel, and Single Function. Signed-off-by: Hans Zhang <hans.zhang@cixtech.com> [mani: moved the PCI ID definitions and squashed Kconfig change] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> [bhelgaas: sort Kconfig menu entry, squash https://lore.kernel.org/r/aSBqp0cglr-Sc8na@stanley.mountain] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/20251108140305.1120117-8-hans.zhang@cixtech.com
2025-12-02PCI: cadence: Add support for High Perf Architecture (HPA) controllerManikandan K Pillai
Add support for Cadence PCIe RP configuration for High Performance Architecture (HPA) controllers. The Cadence High Performance controllers are the latest PCIe controllers that have support for DMA, optional IDE and updated register set. Add a common library for High Performance Architecture (HPA) PCIe controllers. Signed-off-by: Manikandan K Pillai <mpillai@cadence.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> [bhelgaas: squash https://lore.kernel.org/r/20251120093518.2760492-1-jiapeng.chong@linux.alibaba.com, squash https://lore.kernel.org/all/52abaad8-a43e-4e29-93d7-86a3245692c3@cixtech.com/] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/20251108140305.1120117-5-hans.zhang@cixtech.com
2025-12-02PCI: s32g: Add NXP S32G PCIe controller driver (RC)Vincent Guittot
Add initial support of the PCIe controller for the NXP S32G SoC family. Only host mode is supported. Co-developed-by: Ionut Vicovan <Ionut.Vicovan@nxp.com> Signed-off-by: Ionut Vicovan <Ionut.Vicovan@nxp.com> Co-developed-by: Ciprian Marian Costea <ciprianmarian.costea@nxp.com> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@nxp.com> Co-developed-by: Ghennadi Procopciuc <Ghennadi.Procopciuc@nxp.com> Signed-off-by: Ghennadi Procopciuc <Ghennadi.Procopciuc@nxp.com> Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com> Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org> [mani: replaced memblock_start_of_DRAM with hardcoded boundary addr] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20251121164920.2008569-4-vincent.guittot@linaro.org
2025-12-02PCI: dwc: Add register and bitfield definitionsVincent Guittot
Add register and bitfield definitions: - GEN3_RELATED_OFF_EQ_PHASE_2_3 field of GEN3_RELATED_OFF - Coherency control registers Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20251121164920.2008569-3-vincent.guittot@linaro.org
2025-12-02Merge tag 'irq-msi-2025-11-30' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull MSI updates from Thomas Gleixner: "Updates for [PCI] MSI related code: - Remove one variant of PCI/MSI management as all users have been converted to use per device domains. That reduces the variants to two: The modern and the real archaic legacy variant, which keeps the usual suspects in the museum category alive. - Rework the platform MSI device ID detection mechanism in the ARM GIC world to address resource leaks, duplicated code and other details. This requires a corresponding preparatory step in the PCI/iproc driver. - Trivial core code cleanups" * tag 'irq-msi-2025-11-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip/gic-its: Rework platform MSI deviceID detection PCI: iproc: Implement MSI controller node detection with of_msi_xlate() genirq/msi: Slightly simplify msi_domain_alloc() PCI/MSI: Delete pci_msi_create_irq_domain()
2025-11-25PCI: Add Renesas RZ/G3S host controller driverClaudiu Beznea
The Renesas RZ/G3S features a PCIe IP that complies with the PCI Express Base Specification 4.0 and supports speeds of up to 5 GT/s. It functions only as a root complex, with a single-lane (x1) configuration. The controller includes Type 1 configuration registers, as well as IP specific registers (called AXI registers) required for various adjustments. Hardware manual can be downloaded from the address in the "Link" section. The following steps should be followed to access the manual: 1/ Click the "User Manual" button 2/ Click "Confirm"; this will start downloading an archive 3/ Open the downloaded archive 4/ Navigate to r01uh1014ej*-rzg3s-users-manual-hardware -> Deliverables 5/ Open the file r01uh1014ej*-rzg3s.pdf Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://www.renesas.com/en/products/rz-g3s?queryID=695cc067c2d89e3f271d43656ede4d12 Link: https://patch.msgid.link/20251119143523.977085-3-claudiu.beznea.uj@bp.renesas.com
2025-11-25PCI: host-generic: Move bridge allocation outside of pci_host_common_init()Marc Zyngier
Having the host bridge allocation inside pci_host_common_init() results in a lot of complexity in the pcie-apple driver (the only direct user of this function outside of core PCI code). It forces the allocation of driver-specific tracking structures outside of the bridge allocation, which in turn requires it to use inefficient data structures to match the bridge and the private structure as needed. Instead, let the bridge structure be passed to pci_host_common_init(), allowing the driver to allocate it together with the private data, as it is usually intended. The driver can then retrieve the bridge via the owning device attached to the PCI config window structure. This allows the pcie-apple driver to be significantly simplified. Both core and driver code are changed in one go to avoid going via a transitional interface. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Radu Rendec <rrendec@redhat.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Manivannan Sadhasivam <mani@kernel.org> Cc: Rob Herring <robh@kernel.org> Cc: Krzysztof Wilczyński <kwilczynski@kernel.org> Cc: Lorenzo Pieralisi <lpieralisi@kernel.org> Link: https://lore.kernel.org/r/86jyzms036.wl-maz@kernel.org Link: https://patch.msgid.link/20251125102726.865617-1-maz@kernel.org
2025-11-24PCI: dw-rockchip: Configure L1SS supportShawn Lin
L1 PM Substates for RC mode require support in the dw-rockchip driver including proper handling of the CLKREQ# sideband signal. It is mostly handled by hardware, but software still needs to set the clkreq fields in the PCIE_CLIENT_POWER_CON register to match the hardware implementation. For more details, see section '18.6.6.4 L1 Substate' in the RK3568 TRM 1.1 Part 2, or section '11.6.6.4 L1 Substate' in the RK3588 TRM 1.0 Part2. [bhelgaas: set pci->l1ss_support so DWC core preserves L1SS Capability bits; drop corresponding code here, include updates from https://lore.kernel.org/r/aRRG8wv13HxOCqgA@ryzen] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/1761187883-150120-1-git-send-email-shawn.lin@rock-chips.com Link: https://patch.msgid.link/20251118214312.2598220-4-helgaas@kernel.org
2025-11-24PCI: tegra194: Remove unnecessary L1SS disable codeBjorn Helgaas
The DWC core clears the L1 Substates Supported bits unless the driver sets the "dw_pcie.l1ss_support" flag. The tegra194 init_host_aspm() sets "dw_pcie.l1ss_support" if the platform has the "supports-clkreq" DT property. If "supports-clkreq" is absent, "dw_pcie.l1ss_support" is not set, and the DWC core will clear the L1 Substates Supported bits. The tegra194 code to clear the L1 Substates Supported bits is unnecessary, so remove it. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/20251118214312.2598220-3-helgaas@kernel.org
2025-11-24PCI: dwc: Advertise L1 PM Substates only if driver requests itBjorn Helgaas
L1 PM Substates require the CLKREQ# signal and may also require device-specific support. If CLKREQ# is not supported or driver support is lacking, enabling L1.1 or L1.2 may cause errors when accessing devices, e.g., nvme nvme0: controller is down; will reset: CSTS=0xffffffff, PCI_STATUS=0x10 If the kernel is built with CONFIG_PCIEASPM_POWER_SUPERSAVE=y or users enable L1.x via sysfs, users may trip over these errors even if L1 Substates haven't been enabled by firmware or the driver. To prevent such errors, disable advertising the L1 PM Substates unless the driver sets "dw_pcie.l1ss_support" to indicate that it knows CLKREQ# is present and any device-specific configuration has been done. Set "dw_pcie.l1ss_support" in tegra194 (if DT includes the "supports-clkreq' property) and qcom (for cfg_2_7_0, cfg_1_9_0, cfg_1_34_0, and cfg_sc8280xp controllers) so they can continue to use L1 Substates. Based on Niklas's patch: https://patch.msgid.link/20251017163252.598812-2-cassel@kernel.org [bhelgaas: drop hiding for endpoints] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/20251118214312.2598220-2-helgaas@kernel.org
2025-11-24PCI: dwc: Fix wrong PORT_LOGIC_LTSSM_STATE_MASK definitionShawn Lin
As per DesignWare Cores PCI Express Controller Databook, section 5.50, SII: Debug Signals, cxpl_debug_info[63:0]: [5:0] smlh_ltssm_state: LTSSM current state. Encoding is same as the dedicated smlh_ltssm_state output. The mask should be 6 bits, from 0 to 5. Hence, fix the mask definition. Fixes: 23fe5bd4be90 ("PCI: keystone: Cleanup ks_pcie_link_up()") Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [mani: reworded description] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/1763122140-203068-1-git-send-email-shawn.lin@rock-chips.com
2025-11-22PCI: iproc: Implement MSI controller node detection with of_msi_xlate()Lorenzo Pieralisi
The functionality implemented in the iproc driver in order to detect an OF MSI controller node is now fully implemented in of_msi_xlate(). Replace the current msi-map/msi-parent parsing code with of_msi_xlate(). Since of_msi_xlate() is also a deviceID mapping API, pass in a fictitious 0 as deviceID - the driver only requires detecting the OF MSI controller node not the deviceID mapping per-se (of_msi_xlate() return value is ignored for the same reason). Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Frank Li <Frank.Li@nxp.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/20251021124103.198419-5-lpieralisi@kernel.org
2025-11-18PCI: qcom: Implement .assert_perst()Krishna Chaitanya Chundru
Add support for assert_perst() for switches like TC9563, which require configuration before the PCIe link is established. Such devices use this function op to assert PERST# before configuring the device and once the configuration is done they de-assert PERST#. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/20251101-tc9563-v9-5-de3429f7787a@oss.qualcomm.com
2025-11-18PCI: dwc: Implement .assert_perst() for dwc glue driversKrishna Chaitanya Chundru
Add .assert_perst() hook for dwc glue drivers to register with assert_perst() of pci ops, allowing for better control over the link initialization and shutdown process. Implement assert_perst() function op for dwc drivers. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> [bhelgaas: squash dwc host support] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/20251101-tc9563-v9-3-de3429f7787a@oss.qualcomm.com Link: https://patch.msgid.link/20251101-tc9563-v9-4-de3429f7787a@oss.qualcomm.com
2025-11-17PCI: stm32: Don't use 'proxy' headersAndy Shevchenko
Update header inclusions to follow IWYU (Include What You Use) principle. In particular, replace of_gpio.h, which is subject to removal by the GPIOLIB subsystem, with the respective headers that are being used by the driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/20251114185534.3287497-1-andriy.shevchenko@linux.intel.com
2025-11-17PCI: stm32: Fix EP page_size alignmentChristian Bruel
pci_epc_mem_alloc_addr() allocates a CPU address from the ATU window phys base and a page number. Set the ep->page_size so the resulting CPU address is correctly aligned with the ATU required alignment. Fixes: 151f3d29baf4 ("PCI: stm32-ep: Add PCIe Endpoint support for STM32MP25") Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> [mani: added fixes tag] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/20251114-atu_align_ep-v1-1-88da5366fa04@foss.st.com
2025-11-17PCI: stm32: Fix LTSSM EP race with start linkChristian Bruel
If the host has deasserted PERST# and started link training before the link is started on EP side, enabling LTSSM before the endpoint registers are initialized in the perst_irq handler results in probing incorrect values. Thus, wait for the PERST# level-triggered interrupt to start link training at the end of initialization and cleanup the stm32_pcie_[start stop]_link functions. Fixes: 151f3d29baf4 ("PCI: stm32-ep: Add PCIe Endpoint support for STM32MP25") Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> [mani: added fixes tag] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> [bhelgaas: wrap line] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/20251114-perst_ep-v1-1-e7976317a890@foss.st.com
2025-11-17PCI: spacemit: Add SpacemiT PCIe host driverAlex Elder
Introduce a driver for the PCIe host controller found in the SpacemiT K1 SoC. The hardware is derived from the Synopsys DesignWare PCIe IP. The driver supports up to three PCIe ports operating at PCIe link speed up to 5 GT/s. The first port uses a combo PHY, which may be configured for use for USB3 instead. Signed-off-by: Alex Elder <elder@riscstar.com> [mani: added FIXME to the comment on disabling ASPM L1] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Tested-by: Jason Montleon <jmontleo@redhat.com> Tested-by: Johannes Erdfelt <johannes@erdfelt.com> Tested-by: Aurelien Jarno <aurelien@aurel32.net> Link: https://patch.msgid.link/20251113214540.2623070-6-elder@riscstar.com
2025-11-14PCI: cadence: Move PCIe RP common functions to a separate fileManikandan K Pillai
Move the Cadence PCIe controller RP common functions into a separate file. The common library functions are split from legacy PCIe RP controller functions to a separate file. Signed-off-by: Manikandan K Pillai <mpillai@cadence.com> [mani: removed the unused variable] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/20251108140305.1120117-4-hans.zhang@cixtech.com
2025-11-14PCI: cadence: Split PCIe controller header fileManikandan K Pillai
Split the Cadence PCIe header file by moving the Legacy (LGA) controller register definitions to a separate header file for support of next generation PCIe controller architecture. Signed-off-by: Manikandan K Pillai <mpillai@cadence.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/20251108140305.1120117-3-hans.zhang@cixtech.com
2025-11-14PCI: cadence: Add module support for platform controller driverManikandan K Pillai
Add support for building PCI cadence platforms as a module. Signed-off-by: Manikandan K Pillai <mpillai@cadence.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/20251108140305.1120117-2-hans.zhang@cixtech.com
2025-11-13PCI: j721e: Use 'pcie->reset_gpio' directly and drop the local variableAnand Moon
Assign the result of devm_gpiod_get_optional() directly to pcie->reset_gpio, thereby removing the local variable. Signed-off-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://patch.msgid.link/20251028154229.6774-3-linux.amoon@gmail.com
2025-11-13PCI: j721e: Use devm_clk_get_optional_enabled() to get and enable the clockAnand Moon
Use devm_clk_get_optional_enabled() helper instead of calling devm_clk_get_optional() and then clk_prepare_enable(). Assign the result of devm_clk_get_optional_enabled() directly to pcie->refclk to avoid using a local 'clk' variable. Signed-off-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://patch.msgid.link/20251028154229.6774-2-linux.amoon@gmail.com
2025-11-13PCI: keystone: Add support to build as a loadable moduleSiddharth Vadapalli
The 'pci-keystone.c' driver is the application/glue/wrapper driver for the Designware PCIe Controllers on TI SoCs. Now that all of the helper APIs that the 'pci-keystone.c' driver depends upon have been exported for use, enable support to build the driver as a loadable module. When building the driver as a module, the functions marked by the '__init' keyword may be invoked after the init memory has been freed by the kernel. This results will result in an exception of the form: Unable to handle kernel paging request at virtual address ... Mem abort info: ... pc : ks_pcie_host_init+0x0/0x540 lr : dw_pcie_host_init+0x170/0x498 ... ks_pcie_host_init+0x0/0x540 (P) ks_pcie_probe+0x728/0x84c platform_probe+0x5c/0x98 really_probe+0xbc/0x29c __driver_probe_device+0x78/0x12c driver_probe_device+0xd8/0x15c To address this, introduce a new function namely 'ks_pcie_init()' to register the 'fault handler' while removing the '__init' keyword from existing functions. Note that hook_fault_code() is defined as '__init' function. Since the init functions should never be called during runtime (after init memory freeing stage), the driver is made as a built-in if CONFIG_ARM (where hook_fault_code() is used) is selected. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> [mani: added a note about hook_fault_code()] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/20251029080547.1253757-5-s-vadapalli@ti.com
2025-11-13PCI: dwc: Export dw_pcie_allocate_domains() and dw_pcie_ep_raise_msix_irq()Siddharth Vadapalli
The pci-keystone.c driver uses the functions 'dw_pcie_allocate_domains()' and 'dw_pcie_ep_raise_msix_irq()'. Export them in preparation for enabling the pci-keystone.c driver to be built as a loadable module. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/20251029080547.1253757-3-s-vadapalli@ti.com
2025-11-13PCI: keystone: Exit ks_pcie_probe() for invalid modeSiddharth Vadapalli
Commit under Fixes introduced support for PCIe EP mode on AM654x platforms. When the mode happens to be either "DW_PCIE_RC_TYPE" or "DW_PCIE_EP_TYPE", the PCIe Controller is configured accordingly. However, when the mode is neither of them, an error message is displayed, but the driver probe succeeds. Since this "invalid" mode is not associated with a functional PCIe Controller, the probe should fail. Fix the behavior by exiting "ks_pcie_probe()" with the return value of "-EINVAL" in addition to displaying the existing error message when the mode is invalid. Fixes: 23284ad677a9 ("PCI: keystone: Add support for PCIe EP in AM654x Platforms") Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/20251029080547.1253757-4-s-vadapalli@ti.com
2025-11-13PCI: brcmstb: Add panic/die handler to driverJim Quinlan
Most PCIe HW returns 0xffffffff for failed reads on PCIe, but by default Broadcom's STB PCIe controller effects an abort. Some SoCs -- 7216 and its descendants -- have new HW that identifies error details. Add a simple handler to print diagnostic info in case the PCIe controller was the cause of the abort. Unfortunately, an abort still occurs. Read the error registers only when the PCIe bridge is active and the PCIe registers are accessible. Otherwise, a "die" event caused by something other than PCIe could cause an abort if the PCIe "die" handler tried to access registers when the bridge is off. Example error output: brcm-pcie 8b20000.pcie: Error: Mem Acc: 32bit, read, @0x38000000 brcm-pcie 8b20000.pcie: Type: TO=0 Abt=0 UnspReq=1 AccDsble=0 BadAddr=0 Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://patch.msgid.link/20251029193616.3670003-3-james.quinlan@broadcom.com
2025-11-13PCI: brcmstb: Add a way to indicate if PCIe bridge is activeJim Quinlan
In a future commit, a new handler will be introduced that in part does reads and writes to some of the PCIe registers. When this handler is invoked, it is paramount that it does not do these register accesses when the PCIe bridge is inactive, as this will cause CPU abort errors. To solve this we keep a spinlock that guards a variable which indicates whether the bridge is on or off. When the bridge is on, access of the PCIe HW registers may proceed. Since there are multiple ways to reset the bridge, we introduce a general function to obtain the spinlock, call the specific function that is used for the specific SoC, sets the bridge active indicator variable, and releases the spinlock. Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://patch.msgid.link/20251029193616.3670003-2-james.quinlan@broadcom.com
2025-11-10PCI: meson: Fix parsing the DBI register regionManivannan Sadhasivam
First of all, the driver was parsing the 'dbi' register region as 'elbi'. This was due to DT mistakenly passing 'dbi' as 'elbi'. Since the DT is now fixed to supply 'dbi' region, this driver can rely on the DWC core driver to parse and map it. However, to support the old DTs, if the 'elbi' region is found in DT, parse and map the region as both 'dw_pcie::elbi_base' as 'dw_pcie::dbi_base'. This will allow the driver to work with both broken and fixed DTs. Also, skip parsing the 'elbi' region in DWC core if 'pci->elbi_base' was already populated. Fixes: 9c0ef6d34fdb ("PCI: amlogic: Add the Amlogic Meson PCIe controller driver") Fixes: c96992a24bec ("PCI: dwc: Add support for ELBI resource mapping") Reported-by: Linnaea Lavia <linnaea-von-lavia@live.com> Closes: https://lore.kernel.org/linux-pci/DM4PR05MB102707B8CDF84D776C39F22F2C7F0A@DM4PR05MB10270.namprd05.prod.outlook.com/ Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on Bananapi-M2S Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Cc: stable@vger.kernel.org # 6.2 Link: https://patch.msgid.link/20251101-pci-meson-fix-v1-3-c50dcc56ed6a@oss.qualcomm.com
2025-10-31Merge tag 'pci-v6.18-fixes-4' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci Pull pci fixes from Bjorn Helgaas: - Restore custom qcom ASPM enablement code so L1 PM Substates are enabled as they were in v6.17 even though the PCI core now enables just L0s and L1 by default (Bjorn Helgaas) - Size prefetchable bridge windows only when they actually exist, to avoid a WARN_ON() regression (Ilpo Järvinen) * tag 'pci-v6.18-fixes-4' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: PCI: Do not size non-existing prefetchable window Revert "PCI: qcom: Remove custom ASPM enablement code"
2025-10-31PCI: qcom: Use frequency and level based OPP lookupKrishna Chaitanya Chundru
PCIe link configurations such as 8GT/s x2 and 16GT/s x1 may operate at the same frequency, but differ in other characteristics like RPMh votes. But the existing OPP selection which is solely based on frequency (the 'opp-hz' DT property) cannot distinguish between such cases. Hence, use the newly introduced dev_pm_opp_find_key_exact() API to match both frequency and level (the 'opp-level' property) when selecting an OPP, here level indicates PCIe data rate. To support older device trees where opp-level is not defined, check if opp-level is present or not using dev_pm_opp_find_level_exact(). If not present fallback to frequency only match. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> [mani: zero initialize dev_pm_opp_key struct] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> [bhelgaas: add 'opp-hz' and 'opp-level' in commit log] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/20251013-opp_pcie-v5-5-eb64db2b4bd3@oss.qualcomm.com
2025-10-31Revert "PCI: qcom: Remove custom ASPM enablement code"Bjorn Helgaas
This reverts commit a729c16646198872e345bf6c48dbe540ad8a9753. Prior to a729c1664619 ("PCI: qcom: Remove custom ASPM enablement code"), the qcom controller driver enabled ASPM, including L0s, L1, and L1 PM Substates, for all devices powered on at the time the controller driver enumerates them. ASPM was *not* enabled for devices powered on later by pwrctrl (unless the kernel was built with PCIEASPM_POWERSAVE or PCIEASPM_POWER_SUPERSAVE, or the user enabled ASPM via module parameter or sysfs). After f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for devicetree platforms"), the PCI core enabled all ASPM states for all devices whether powered on initially or by pwrctrl, so a729c1664619 was unnecessary and reverted. But f3ac2ff14834 was too aggressive and broke platforms that didn't support CLKREQ# or required device-specific configuration for L1 Substates, so df5192d9bb0e ("PCI/ASPM: Enable only L0s and L1 for devicetree platforms") enabled only L0s and L1. On Qualcomm platforms, this left L1 Substates disabled, which was a regression. Revert a729c1664619 so L1 Substates will be enabled on devices that are initially powered on. Devices powered on by pwrctrl will be addressed later. Fixes: df5192d9bb0e ("PCI/ASPM: Enable only L0s and L1 for devicetree platforms") Reported-by: Johan Hovold <johan@kernel.org> Closes: https://lore.kernel.org/lkml/aPuXZlaawFmmsLmX@hovoldconsulting.com/ Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Johan Hovold <johan@kernel.org> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/20251024210514.1365996-1-helgaas@kernel.org
2025-10-28PCI: brcmstb: Fix disabling L0s capabilityJim Quinlan
caab002d5069 ("PCI: brcmstb: Disable L0s component of ASPM if requested") set PCI_EXP_LNKCAP_ASPM_L1 and (optionally) PCI_EXP_LNKCAP_ASPM_L0S in PCI_EXP_LNKCAP (aka PCIE_RC_CFG_PRIV1_LINK_CAPABILITY in brcmstb). But instead of using PCI_EXP_LNKCAP_ASPM_L1 and PCI_EXP_LNKCAP_ASPM_L0S directly, it used PCIE_LINK_STATE_L1 and PCIE_LINK_STATE_L0S, which are Linux-created values that only coincidentally matched the PCIe spec. b478e162f227 ("PCI/ASPM: Consolidate link state defines") later changed them so they no longer matched the PCIe spec, so the bits ended up in the wrong place in PCI_EXP_LNKCAP. Use PCI_EXP_LNKCAP_ASPM_L0S to clear L0s support when there's an 'aspm-no-l0s' property. Rely on brcmstb hardware to advertise L0s and/or L1 support otherwise. Fixes: caab002d5069 ("PCI: brcmstb: Disable L0s component of ASPM if requested") Reported-by: Bjorn Helgaas <bhelgaas@google.com> Closes: https://lore.kernel.org/linux-pci/20250925194424.GA2197200@bhelgaas Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> [mani: reworded subject and description, added closes tag and CCed stable] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> [bhelgaas: commit log] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20251003170436.1446030-1-james.quinlan@broadcom.com
2025-10-28PCI: vmd: Switch to pci_bus_find_emul_domain_nr()Dan Williams
The new common domain number allocator can replace the custom allocator in VMD. Beyond some code reuse benefits it does close a potential race whereby vmd_find_free_domain() collides with new PCI buses coming online with a conflicting domain number. Such a race has not been observed in practice, hence not tagging this change as a fix. As VMD uses pci_create_root_bus() rather than pci_alloc_host_bridge() + pci_scan_root_bus_bridge() it has no chance to set ->domain_nr in the bridge so needs to manage freeing the domain number on its own. Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Szymon Durawa <szymon.durawa@linux.intel.com> Cc: Nirmal Patel <nirmal.patel@linux.intel.com> Link: https://patch.msgid.link/20251024224622.1470555-3-dan.j.williams@intel.com
2025-10-28PCI: Enable host bridge emulation for PCI_DOMAINS_GENERIC platformsDan Williams
The ability to emulate a host bridge is useful not only for hardware PCI controllers like CONFIG_VMD, or virtual PCI controllers like CONFIG_PCI_HYPERV, but also for test and development scenarios like CONFIG_SAMPLES_DEVSEC [1]. One stumbling block for defining CONFIG_SAMPLES_DEVSEC, a sample implementation of a platform TSM for PCI Device Security, is the need to accommodate PCI_DOMAINS_GENERIC architectures alongside x86 [2]. In support of supplementing the existing CONFIG_PCI_BRIDGE_EMUL infrastructure for host bridges: * Introduce pci_bus_find_emul_domain_nr() as a common way to find a free PCI domain number whether that is to reuse the existing dynamic allocation code in the !ACPI case, or to assign an unused domain above the last ACPI segment. * Convert pci-hyperv to the new allocator so that the PCI core can unconditionally assume that bridge->domain_nr != PCI_DOMAIN_NR_NOT_SET is the dynamically allocated case. A follow on patch can also convert vmd to the new scheme. Currently vmd is limited to CONFIG_PCI_DOMAINS_GENERIC=n (x86) so, unlike pci-hyperv, it does not immediately conflict with this new pci_bus_find_emul_domain_nr() mechanism. Link: http://lore.kernel.org/174107249038.1288555.12362100502109498455.stgit@dwillia2-xfh.jf.intel.com [1] Reported-by: Suzuki K Poulose <suzuki.poulose@arm.com> Closes: http://lore.kernel.org/20250311144601.145736-3-suzuki.poulose@arm.com [2] Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Suzuki K Poulose <suzuki.poulose@arm.com> Tested-by: Michael Kelley <mhklinux@outlook.com> Reviewed-by: Michael Kelley <mhklinux@outlook.com> Cc: Lorenzo Pieralisi <lpieralisi@kernel.org> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Rob Herring <robh@kernel.org> Cc: K. Y. Srinivasan <kys@microsoft.com> Cc: Haiyang Zhang <haiyangz@microsoft.com> Cc: Wei Liu <wei.liu@kernel.org> Cc: Dexuan Cui <decui@microsoft.com> Link: https://patch.msgid.link/20251024224622.1470555-2-dan.j.williams@intel.com
2025-10-24Merge tag 'pci-v6.18-fixes-3' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci Pull pci fixes from Bjorn Helgaas: - Add DWC custom pci_ops for the root bus instead of overwriting the DBI base address, which broke drivers that rely on the DBI address for iATU programming; fixes an FU740 probe regression (Krishna Chaitanya Chundru) - Revert qcom ECAM enablement, which is rendered unnecessary by the DWC custom pci_ops (Krishna Chaitanya Chundru) - Fix longstanding MIPS Malta resource registration issues to avoid exposing them when the next commit fixes the boot failure (Maciej W. Rozycki) - Use pcibios_align_resource() on MIPS Malta to fix boot failure caused by using the generic pci_enable_resources() (Ilpo Järvinen) - Enable only ASPM L0s and L1, not L1 PM Substates, for devicetree platforms because we lack information required to configure L1 Substates; fixes regressions on powerpc and rockchip. A qcom regression (L1 Substates no longer enabled) remains and will be addressed next (Bjorn Helgaas) * tag 'pci-v6.18-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: PCI/ASPM: Enable only L0s and L1 for devicetree platforms MIPS: Malta: Use pcibios_align_resource() to block io range MIPS: Malta: Fix PCI southbridge legacy resource reservations MIPS: Malta: Fix keyboard resource preventing i8042 driver from registering Revert "PCI: qcom: Prepare for the DWC ECAM enablement" PCI: dwc: Use custom pci_ops for root bus DBI vs ECAM config access
2025-10-21PCI: rcar-gen2: Drop ARM dependency from PCI_RCAR_GEN2Geert Uytterhoeven
Since the reliance on ARM-specific struct pci_sys_data was removed, this driver can be compile-tested on other architectures. While at it, make the help text a bit more generic, as some members of the R-Car Gen2 family have a different number of internal PCI controllers. Fixes: 4a957563fe0231e0 ("PCI: rcar-gen2: Convert to use modern host bridge probe functions") Suggested-by: Ilpo Jarvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> [bhelgaas: add rcar-gen2 to subject] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Link: https://patch.msgid.link/00f75d6732eacce93f04ffaeedc415d2db714cd6.1759480426.git.geert+renesas@glider.be
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