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path: root/drivers/phy/freescale
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2026-02-17Merge tag 'phy-for-7.0' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "Core: - Add suuport for "rx-polarity" and "tx-polarity" device tree properties and phy common properties to manage this New Support: - Qualcomm Glymur PCIe Gen4 2-lanes PCIe phy, DP and edp phy, USB UNI PHY and SMB2370 eUSB2 repeater. SC8280xp QMP UFS PHY, Kaanapali PCIe phy and QMP PHY, QCS615 QMP USB3+DP PHY and driver support for that. - SpacemiT PCIe/combo PHY and K1 USB2 PHY driver. - HDMI 2.1 FRL configuration support and driver enabling for rockchip samsung-hdptx driver - TI TCAN1046 phy - Renesas RZ/V2H(P) and RZ/V2N usb3 - Mediatek MT8188 hdmi-phy - Google Tensor SoC USB PHY driver - Apple Type-C PHY Updates: - Subsystem conversion for clock round_rate() to determine_rate() - TI USB3 DT schema conversion - Samsung ExynosAutov920 usb3, combo hsphy and ssphy support" * tag 'phy-for-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (143 commits) phy: ti: phy-j721e-wiz: convert from divider_round_rate() to divider_determine_rate() dt-bindings: phy: ti,control-phy-otghs: convert to DT schema dt-bindings: phy: ti,phy-usb3: convert to DT schema phy: tegra: xusb: Remove unused powered_on variable phy: renesas: rcar-gen3-usb2: add regulator dependency phy: GOOGLE_USB: add TYPEC dependency phy: enter drivers/phy/Makefile even without CONFIG_GENERIC_PHY phy: renesas: rcar-gen3-usb2: Use mux-state for phyrst management phy: renesas: rcar-gen3-usb2: Add regulator for OTG VBUS control phy: renesas: rcar-gen3-usb2: Use devm_pm_runtime_enable() phy: renesas: rcar-gen3-usb2: Factor out VBUS control logic dt-bindings: phy: renesas,usb2-phy: Document RZ/G3E SoC dt-bindings: phy: renesas,usb2-phy: Document mux-states property dt-bindings: phy: renesas,usb2-phy: Document USB VBUS regulator phy: rockchip: samsung-hdptx: Add HDMI 2.1 FRL support phy: rockchip: samsung-hdptx: Extend rk_hdptx_phy_verify_hdmi_config() helper phy: rockchip: samsung-hdptx: Switch to driver specific HDMI config phy: rockchip: samsung-hdptx: Drop hw_rate driver data phy: rockchip: samsung-hdptx: Compute clk rate from PLL config phy: rockchip: samsung-hdptx: Cleanup *_cmn_init_seq lists ...
2026-01-21phy: freescale: imx8qm-hsio: fix NULL pointer dereferenceThomas Richard
During the probe the refclk_pad pointer is set to NULL if the 'fsl,refclk-pad-mode' property is not defined in the devicetree node. But in imx_hsio_configure_clk_pad() this pointer is unconditionally used which could result in a NULL pointer dereference. So check the pointer before to use it. Fixes: 82c56b6dd24f ("phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY driver support") Signed-off-by: Thomas Richard <thomas.richard@bootlin.com> Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com> Link: https://patch.msgid.link/20260114-phy-fsl-imx8qm-hsio-fix-null-pointer-dereference-v1-1-730e941be464@bootlin.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-21phy: fsl-imx8mq-usb: enable RX Termination overrideXu Yang
This is to resolve the problem of wakeup system by USB3 device insertion if HSIOMIX on, in that case, the USB3 device detects RX term on so the USB3 device doesn't downgrade to high-speed, we can't expect CONN wakeup (for USB3) happen because the 24MHz OSC is required ON to trigger it. Because the device works at Super-speed so DP/DM wakeup can't happen either. Then the entire systen can't be waken up by such device attach event. With this override bit we can force the RX term off when enters system suspend, and disable the override after system resume. Therefore, the USB3 device will always downgrade to High-speed, then DP/DM wakeup can always happen. It will correctly switch to Super-speed later when the host reset it after the system resume back. Signed-off-by: Li Jun <jun.li@nxp.com> Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Link: https://patch.msgid.link/20260116101835.1810675-1-xu.yang_2@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-21phy: fsl-imx8mq-usb: set platform driver dataXu Yang
Add missing platform_set_drvdata() as the data will be used in remove(). Fixes: b58f0f86fd61 ("phy: fsl-imx8mq-usb: add tca function driver for imx95") Cc: stable@vger.kernel.org Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260120111646.3159766-1-xu.yang_2@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-21phy: fsl-imx8mq-usb: disable bind/unbind platform driver featureXu Yang
Disabling PHYs in runtime usually causes the client with external abort exception or similar issue due to lack of API to notify clients about PHY removal. This patch removes the possibility to unbind i.MX PHY drivers in runtime. Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260120111712.3159782-1-xu.yang_2@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-14phy: freescale: imx8m-pcie: assert phy reset during power onRafael Beims
After U-Boot initializes PCIe with "pcie enum", Linux fails to detect an NVMe disk on some boot cycles with: phy phy-32f00000.pcie-phy.0: phy poweron failed --> -110 Discussion with NXP identified that the iMX8MP PCIe PHY PLL may fail to lock when re-initialized without a reset cycle [1]. The issue reproduces on 7% of tested hardware platforms, with a 30-40% failure rate per affected device across boot cycles. Insert a reset cycle in the power-on routine to ensure the PHY is initialized from a known state. [1] https://community.nxp.com/t5/i-MX-Processors/iMX8MP-PCIe-initialization-in-U-Boot/m-p/2248437#M242401 Signed-off-by: Rafael Beims <rafael.beims@toradex.com> Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20251223150254.1075221-1-rafael@beims.me Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-24phy: freescale: phy-fsl-samsung-hdmi: convert from round_rate() to ↵Brian Masney
determine_rate() The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney <bmasney@redhat.com> Link: https://patch.msgid.link/20251212-phy-clk-round-rate-v3-1-beae3962f767@redhat.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23phy: lynx-28g: improve lynx_28g_probe() sequenceVladimir Oltean
dev_set_drvdata() is called twice, it is sufficient to do it only once. devm_of_phy_provider_register() can fail, and if it does, the &priv->cdr_check work item is queued, but not cancelled, and the device probing failed, so it will trigger use after free. This is a minor risk though. Resource initialization should be done a little earlier, in case we need to dereference dev_get_drvdata() in lynx_28g_pll_read_configuration() or in lynx_28g_lane_read_configuration(). Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Link: https://patch.msgid.link/20251125114847.804961-16-vladimir.oltean@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23phy: lynx-28g: use "dev" argument more in lynx_28g_probe()Vladimir Oltean
We have "dev" which holds &pdev->dev, but we still dereference this pointer 4 more times, instead of using the local variable. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Link: https://patch.msgid.link/20251125114847.804961-15-vladimir.oltean@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23phy: lynx-28g: configure more equalization params for 1GbE and 10GbEIoana Ciornei
While adding support for 25GbE, it was noticed that the RCCR0 and TTLCR0 registers have different values for this protocol than the 10GbE and 1GbE modes. Expand the lynx_28g_proto_conf[] array with the expected values for the currently supported protocols. These were dumped from a live system, and are the out-of-reset values. It will ensure that the lane is configured with these values when transitioning from 25GbE back into one of these modes. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Link: https://patch.msgid.link/20251125114847.804961-14-vladimir.oltean@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23phy: lynx-28g: distinguish between 10GBASE-R and USXGMIIVladimir Oltean
The driver does not handle well protocol switching to or from USXGMII, because it conflates it with 10GBase-R. In the expected USXGMII use case, that isn't a problem, because SerDes protocol switching performed by the lynx-28g driver is not necessary, because USXGMII natively supports multiple speeds, as opposed to SFP modules using 1000Base-X or 10GBase-R which require switching between the 2. That being said, let's be explicit, and in case someone requests a protocol change which involves USXGMII, let's do the right thing. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Link: https://patch.msgid.link/20251125114847.804961-13-vladimir.oltean@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23phy: lynx-28g: refactor lane->interface to lane->modeVladimir Oltean
Lynx 28G is a multi-protocol SerDes - it handles serial Ethernet, PCIe, SATA. The driver should not use the phylib-specific phy_interface_t as an internal data representation, but something specific to its internal capabilities, and only convert to phy_interface_t when PHY_MODE_ETHERNET is selected and used. Otherwise it has no way of representing the non-Ethernet lanes (which was not a short-term goal when the driver was introduced, and is not a goal per se right now either, but should nonetheless be possible). Prefer the "enum lynx_lane_mode" name over "lynx_28g_lane_mode", in preparation of future Lynx 10G SerDes support. This SerDes is part of the same IP family and has similar capabilities, and will reuse some code, hence the common data type. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Link: https://patch.msgid.link/20251125114847.804961-12-vladimir.oltean@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23phy: lynx-28g: make lynx_28g_set_lane_mode() more systematicVladimir Oltean
The current approach of transitioning from one SerDes protocol to another in lynx_28g_set_lane_mode() is too poetic. Because the driver only supports 1GbE and 10GbE, it only modifies those registers which it knows are different between these two modes. However, that is hardly extensible for 25GbE, 40GbE, backplane modes, etc. We need something more systematic to make sure that all lane and protocol converter registers are written to consistent values, no matter what was the source lane mode. For that, we need to introduce tables with register field values, for each supported lane mode. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Link: https://patch.msgid.link/20251125114847.804961-11-vladimir.oltean@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23phy: lynx-28g: restructure protocol configuration register accessesVladimir Oltean
Eliminate the need to calculate a lane_offset manually, and generate some macros which access the protocol converter corresponding to the correct lane in the PCC* registers. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Link: https://patch.msgid.link/20251125114847.804961-10-vladimir.oltean@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23phy: lynx-28g: convert iowrite32() calls with magic values to macrosVladimir Oltean
The driver will need to become more careful with the values it writes to the TX and RX equalization registers. As a preliminary step, convert the magic numbers to macros defining the register field meanings. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Link: https://patch.msgid.link/20251125114847.804961-9-vladimir.oltean@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23phy: lynx-28g: use FIELD_GET() and FIELD_PREP()Vladimir Oltean
Reduce the number of bit field definitions required in this driver (in the worst case, a read form and a write form), by defining just the mask, and using the FIELD_GET() and FIELD_PREP() API from <linux/bitfield.h> with that. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Link: https://patch.msgid.link/20251125114847.804961-8-vladimir.oltean@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23phy: lynx-28g: don't concatenate lynx_28g_lane_rmw() argument "reg" with ↵Vladimir Oltean
"val" and "mask" The last step in having lynx_28g_lane_rmw() arguments that fully point to their definitions is the removal of the current concatenation logic, by which e.g. "LNaTGCR0, N_RATE_QUARTER, N_RATE_MSK" is expanded to "LNaTGCR0, LNaTGCR0_N_RATE_QUARTER, LNaTGCR0_N_RATE_MSK". There are pros and cons to the above. An advantage is the impossibility to mix up fields of one register with fields of another. For example both LNaTGCR0 and LNaRGCR0 contain an N_RATE_QUARTER field (one for the lane RX direction, one for the lane TX). But the two notable disadvantages are: 1. the impossibility to write expressions such as logical OR between multiple fields. Practically, this forces us to perform more accesses to hardware registers than would otherwise be needed. See the LNaGCR0 access for example. 2. the necessity to invent fields that don't exist, like SGMIIaCR1_SGPCS_DIS, in order to clear SGMIIaCR1_SGPCS_EN (the real field name). This is confusing, because sometimes, fields that end with _DIS really exist, and it's best to not invent new field names. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Link: https://patch.msgid.link/20251125114847.804961-7-vladimir.oltean@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23phy: lynx-28g: remove LYNX_28G_ prefix from register namesVladimir Oltean
Currently, in macros such as lynx_28g_lane_rmw(), the driver has macros which concatenate the LYNX_28G_ prefix with the "val" and "mask" arguments. This is done to shorten function calls and not have to spell out LYNX_28G_ everywhere. But outside of lynx_28g_lane_rmw(), lynx_28g_lane_read() and lynx_28g_pll_read(), this is not done, leading to an inconsistency in the code. Also, the concatenation itself has the disadvantage that searching the arguments of these functions as full words (like N_RATE_QUARTER) leads us nowhere, since the real macro definition is LNaTGCR0_N_RATE_QUARTER. Some maintainers want register definitions in drivers to contain the driver name as a prefix, but here, this has the disadvantages listed above, so just remove that prefix. The only change made here is the removal of LYNX_28G_. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Link: https://patch.msgid.link/20251125114847.804961-6-vladimir.oltean@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23phy: lynx-28g: avoid memsetting lane already allocated with kzalloc()Vladimir Oltean
"priv" is allocated by lynx_28g_probe() using devm_kzalloc(), and the lane is memory inside that structure (&priv->lane[id]). We don't have to zero-initialize it, it is already filled with zeroes. Suggested-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/linux-phy/aRYMM3ZuyBYH8zEC@vaman/ Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Link: https://patch.msgid.link/20251125114847.804961-5-vladimir.oltean@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23phy: lynx-28g: support individual lanes as OF PHY providersVladimir Oltean
Currently, the bindings of this multi-lane SerDes are such that consumers specify the lane index in the PHY cell, and the lane itself is not described in the device tree. It is desirable to describe individual Lynx 28G SerDes lanes in the device tree, in order to be able to customize electrical properties such as those in Documentation/devicetree/bindings/phy/transmit-amplitude.yaml (or others). If each lane may have an OF node, it appears natural for consumers to have their "phys" phandle point to that OF node. The problem is that transitioning between one format and another is a breaking change. The bindings of the 28G Lynx SerDes can themselves be extended in a backward-compatible way, but the consumers cannot be modified without breaking them. Namely, if we have: &mac { phys = <&serdes1 0>; }; we cannot update the device tree to: &mac { phys = <&serdes1_lane_0>; }; because old kernels cannot resolve this phandle to a valid PHY. The proposal here is to keep tolerating existing device trees, which are not supposed to be changed, but modify lynx_28g_xlate() to also resolve the new format with #phy-cells = <0> in the lanes. This way we support 3 modes: - Legacy device trees, no OF nodes for lanes - New device trees, OF nodes for lanes and "phys" phandle points towards them - Hybrid device trees, OF nodes for lanes (to describe electrical parameters), but "phys" phandle points towards the SerDes top-level provider Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Link: https://patch.msgid.link/20251125114847.804961-4-vladimir.oltean@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23phy: lynx-28g: refactor lane probing to lynx_28g_probe_lane()Vladimir Oltean
This simplifies the main control flow a little bit and makes the logic reusable for probing the lanes with OF nodes if those exist. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Link: https://patch.msgid.link/20251125114847.804961-3-vladimir.oltean@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23phy: fsl-imx8mq-usb: change ssc_range value for i.MX8MQXu Yang
According to IC engineer suggestion, set ssc_range as -4003 ppm will have more tolerance for EMI, and suitable for more boards. Besides, it's confirmed that with this setting the TX SSC test will pass on one customer board. Signed-off-by: Li Jun <jun.li@nxp.com> Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20251219081354.3806806-1-xu.yang_2@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23phy: freescale: Discard pm_runtime_put() return valueRafael J. Wysocki
Printing error messages on pm_runtime_put() returning negative values is not particularly useful. Returning an error code from pm_runtime_put() merely means that it has not queued up a work item to check whether or not the device can be suspended and there are many perfectly valid situations in which that can happen, like after writing "on" to the devices' runtime PM "control" attribute in sysfs for one example. Accordingly, update mixel_lvds_phy_reset() to simply discard the return value of pm_runtime_put(). This will facilitate a planned change of the pm_runtime_put() return type to void in the future. Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/2012926.taCxCBeP46@rafael.j.wysocki Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23phy: fsl-imx8mq-usb: Clear the PCS_TX_SWING_FULL field before using itStefano Radaelli
Clear the PCS_TX_SWING_FULL field mask before setting the new value in PHY_CTRL5 register. Without clearing the mask first, the OR operation could leave previously set bits, resulting in incorrect register configuration. Fixes: 63c85ad0cd81 ("phy: fsl-imx8mp-usb: add support for phy tuning") Suggested-by: Leonid Segal <leonids@variscite.com> Acked-by: Pierluigi Passaro <pierluigi.p@variscite.com> Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Reviewed-by: Xu Yang <xu.yang_2@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://patch.msgid.link/20251219160912.561431-1-stefano.r@variscite.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23phy: fsl-imx8mq-usb: fix typec orientation switch when built as moduleFranz Schnyder
Currently, the PHY only registers the typec orientation switch when it is built in. If the typec driver is built as a module, the switch registration is skipped due to the preprocessor condition, causing orientation detection to fail. With commit 45fe729be9a6 ("usb: typec: Stub out typec_switch APIs when CONFIG_TYPEC=n") the preprocessor condition is not needed anymore and the orientation switch is correctly registered for both built-in and module builds. Fixes: b58f0f86fd61 ("phy: fsl-imx8mq-usb: add tca function driver for imx95") Cc: stable@vger.kernel.org Suggested-by: Xu Yang <xu.yang_2@nxp.com> Signed-off-by: Franz Schnyder <franz.schnyder@toradex.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Xu Yang <xu.yang_2@nxp.com> Link: https://patch.msgid.link/20251126140136.1202241-1-fra.schnyder@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20phy: fsl-imx8mq-usb: support alternate reference clockXu Yang
This phy supports both 24MHz and 100MHz clock inputs. By default it's using XTAL 24MHz and the 100MHz clock is a alternate reference clock. Add supports to use alternate reference clock in case 24MHz clock can't work well. Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Link: https://patch.msgid.link/20251118071947.2504789-2-xu.yang_2@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20phy: freescale: Initialize priv->lockXiaolei Wang
Initialize priv->lock to fix the following warning. WARNING: CPU: 0 PID: 12 at kernel/locking/mutex.c:577 __mutex_lock+0x70c/0x8b8 Modules linked in: Hardware name: Freescale i.MX8QM MEK (DT) Call trace: __mutex_lock+0x70c/0x8b8 (P) mutex_lock_nested+0x24/0x30 imx_hsio_power_on+0x4c/0x764 phy_power_on+0x7c/0x12c imx_pcie_host_init+0x1d0/0x4d4 dw_pcie_host_init+0x188/0x4b0 imx_pcie_probe+0x324/0x6f4 platform_probe+0x5c/0x98 really_probe+0xbc/0x29c __driver_probe_device+0x78/0x12c driver_probe_device+0xd8/0x160 __device_attach_driver+0xb8/0x138 bus_for_each_drv+0x84/0xe4 __device_attach_async_helper+0xb8/0xdc async_run_entry_fn+0x34/0xe0 process_one_work+0x220/0x694 worker_thread+0x1c0/0x36c kthread+0x14c/0x224 Fixes: 82c56b6dd24f ("phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY driver support") Signed-off-by: Xiaolei Wang <xiaolei.wang@windriver.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20250925013806.569658-1-xiaolei.wang@windriver.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-09-01phy: lynx-28g: check return value when calling lynx_28g_pll_getJosua Mayer
The lynx_28g_pll_get function may return NULL when called with an unsupported submode argument. This function is only called from the lynx_28g_lane_set_{10gbaser,sgmii} functions, and lynx_28g_set_mode checks available modes before setting a protocol. NXP vendor kernel based on v6.6.52 however is missing any checks and connecting a 2.5/5gbase-t ethernet phy can cause null pointer dereference [1]. Check return value at every invocation and abort in the unlikely error case. Further print a warning message the first time lynx_28g_pll_get returns null, to catch this case should it occur after future changes. [1] [ 127.019924] fsl_dpaa2_eth dpni.4 eth5: dpmac_set_protocol(2500base-x) = -ENOTSUPP [ 127.027451] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000014 [ 127.036245] Mem abort info: [ 127.039044] ESR = 0x0000000096000004 [ 127.042794] EC = 0x25: DABT (current EL), IL = 32 bits [ 127.048107] SET = 0, FnV = 0 [ 127.051161] EA = 0, S1PTW = 0 [ 127.054301] FSC = 0x04: level 0 translation fault [ 127.059179] Data abort info: [ 127.062059] ISV = 0, ISS = 0x00000004, ISS2 = 0x00000000 [ 127.067547] CM = 0, WnR = 0, TnD = 0, TagAccess = 0 [ 127.072596] GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0 [ 127.077907] user pgtable: 4k pages, 48-bit VAs, pgdp=00000020816c9000 [ 127.084344] [0000000000000014] pgd=0000000000000000, p4d=0000000000000000 [ 127.091133] Internal error: Oops: 0000000096000004 [#1] PREEMPT SMP [ 127.097390] Modules linked in: cfg80211 rfkill fsl_jr_uio caam_jr dpaa2_caam caamkeyblob_desc crypto_engine caamhash_desc onboard_usb_hub caamalg_desc crct10dif_ce libdes caam error at24 rtc_ds1307 rtc_fsl_ftm_alarm nvmem_layerscape_sfp layerscape_edac_mod dm_mod nfnetlink ip_tables [ 127.122436] CPU: 5 PID: 96 Comm: kworker/u35:0 Not tainted 6.6.52-g3578ef896722 #10 [ 127.130083] Hardware name: SolidRun LX2162A Clearfog (DT) [ 127.135470] Workqueue: events_power_efficient phylink_resolve [ 127.141219] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 127.148170] pc : lynx_28g_set_lane_mode+0x300/0x818 [ 127.153041] lr : lynx_28g_set_lane_mode+0x2fc/0x818 [ 127.157909] sp : ffff8000806f3b80 [ 127.161212] x29: ffff8000806f3b80 x28: 0000000000000000 x27: 0000000000000000 [ 127.168340] x26: ffff29d6c11f3098 x25: 0000000000000000 x24: 0000000000000000 [ 127.175467] x23: ffff29d6c11f31f0 x22: ffff29d6c11f3080 x21: 0000000000000001 [ 127.182595] x20: ffff29d6c11f4c00 x19: 0000000000000000 x18: 0000000000000006 [ 127.189722] x17: 4f4e452d203d2029 x16: 782d657361623030 x15: 3532286c6f636f74 [ 127.196849] x14: 6f72705f7465735f x13: ffffd7a8ff991cc0 x12: 0000000000000acb [ 127.203976] x11: 0000000000000399 x10: ffffd7a8ff9e9cc0 x9 : 0000000000000000 [ 127.211104] x8 : 0000000000000000 x7 : 0000000000000000 x6 : ffff29d6c11f3080 [ 127.218231] x5 : 0000000000000000 x4 : 0000000040800030 x3 : 000000000000034c [ 127.225358] x2 : ffff29d6c11f3080 x1 : 000000000000034c x0 : 0000000000000000 [ 127.232486] Call trace: [ 127.234921] lynx_28g_set_lane_mode+0x300/0x818 [ 127.239443] lynx_28g_set_mode+0x12c/0x148 [ 127.243529] phy_set_mode_ext+0x5c/0xa8 [ 127.247356] lynx_pcs_config+0x64/0x294 [ 127.251184] phylink_major_config+0x184/0x49c [ 127.255532] phylink_resolve+0x2a0/0x5d8 [ 127.259446] process_one_work+0x138/0x248 [ 127.263448] worker_thread+0x320/0x438 [ 127.267187] kthread+0x114/0x118 [ 127.270406] ret_from_fork+0x10/0x20 [ 127.273973] Code: 2a1303e1 aa0603e0 97fffd3b aa0003e5 (b9401400) [ 127.280055] ---[ end trace 0000000000000000 ]--- Signed-off-by: Josua Mayer <josua@solid-run.com> Link: https://lore.kernel.org/r/20250826-lynx-28g-nullptr-v1-1-e4de0098f822@solid-run.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14phy: freescale: fsl-samsung-hdmi: Improve LUT search for best clockAdam Ford
Searching the look-up-table runs so long as the frequency in the table is at or below the desired rate. This works well in most cases, but the next entry in the LUT might be closer to the nominal value than the lower one. Add some logic to check the higer value is any closer to the nominal value and use it. Signed-off-by: Adam Ford <aford173@gmail.com> Link: https://lore.kernel.org/r/20250504204043.418924-3-aford173@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14phy: freescale: fsl-samsung-hdmi: Refactor finding PHY settingsAdam Ford
There are two functions, round_rate and set_rate that duplicate a lot of the same work, so simplify the code by creating a helper function that will identify the phy settings for a desired clock rate and return the structure with the corresponding settings. >From this structure, the round_rate and set_rate can both get what they need to achieve the clock setting closest to the desired rate as possible while minimizing the duplicated code. Also rename phy_clk_set_rate to fsl_samsung_hdmi_phy_clk_set_rate. Suggested-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Signed-off-by: Adam Ford <aford173@gmail.com> Link: https://lore.kernel.org/r/20250504204043.418924-2-aford173@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14phy: freescale: fsl-samsung-hdmi: Rename phy_clk_round_rateAdam Ford
phy_clk_round_rate sounds like a generic helper function. In reality, it is unique to the phy-fsl-samsung-hdmi. Rename phy_clk_round_rate to fsl_samsung_hdmi_phy_clk_round_rate. No functional change intended. Suggested-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Signed-off-by: Adam Ford <aford173@gmail.com> Link: https://lore.kernel.org/r/20250504204043.418924-1-aford173@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14phy: fsl-imx8mq-usb: add i.MX95 tuning supportXu Yang
The i.MX8MP and i.MX95 USB3 PHY have different tuning parameter for same tuning field, this will add i.MX95 tuning support. Reviewed-by: Jun Li <jun.li@nxp.com> Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Link: https://lore.kernel.org/r/20250430094502.2723983-4-xu.yang_2@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14phy: fsl-imx8mq-usb: fix phy_tx_vboost_level_from_property()Xu Yang
The description of TX_VBOOST_LVL is wrong in register PHY_CTRL3 bit[31:29]. The updated description as below: 011: Corresponds to a launch amplitude of 0.844 V. 100: Corresponds to a launch amplitude of 1.008 V. 101: Corresponds to a launch amplitude of 1.156 V. This will fix the parsing function phy_tx_vboost_level_from_property() to return correct value. Fixes: 63c85ad0cd81 ("phy: fsl-imx8mp-usb: add support for phy tuning") Cc: stable@vger.kernel.org Reviewed-by: Jun Li <jun.li@nxp.com> Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Link: https://lore.kernel.org/r/20250430094502.2723983-3-xu.yang_2@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14phy: freescale: imx8m-pcie: Simplify with dev_err_probe()Alexander Stein
Error handling in probe() can be a bit simpler with dev_err_probe(). Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Link: https://lore.kernel.org/r/20250429090152.1094243-1-alexander.stein@ew.tq-group.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-04-01Merge tag 'phy-for-6.15' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "A fairly moderate sized request for the generic phy subsystem with some new device and driver support along with driver updates with Samsung and Qualcomm ones being major ones. New HW Support: - Qualcomm X1P42100 PCIe Gen4x4, QCS615 qmp usbc, PCIe UNIPHY 28LP driver, SM8750 QMP UFS PHY - Rockchip rk3576 hdptx, rk3562 naneng-combo support - Samsung MIPI D-/C-PHY driver, ExynosAutov920 ufs phy driver Updates: - Samsung USB3 Type-C lane orientation detection and configuration for Google gs101 - Qualcomm support for dual lane PHY support for QCS8300 SoC" * tag 'phy-for-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (47 commits) phy: rockchip-naneng-combo: Support rk3562 dt-bindings: phy: rockchip: Add rk3562 naneng-combophy compatible phy: rockchip: Add Samsung MIPI D-/C-PHY driver dt-bindings: phy: Add Rockchip MIPI C-/D-PHY schema phy: qcom: uniphy-28lp: add COMMON_CLK dependency phy: rockchip: usbdp: Remove unnecessary bool conversion phy: rockchip: usbdp: Avoid call hpd_event_trigger in dp_phy_init phy: rockchip: usbdp: Only verify link rates/lanes/voltage when the corresponding set flags are set phy: qcom-qmp-pcie: add dual lane PHY support for QCS8300 dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the QCS8300 QMP PCIe PHY Gen4 x2 phy: qcom-qmp-ufs: Add PHY Configuration support for sm8750 dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: document the SM8750 QMP UFS PHY phy: qcom: Introduce PCIe UNIPHY 28LP driver dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy phy: qcom: qmp-usbc: Add qmp configuration for QCS615 phy: freescale: imx8m-pcie: assert phy reset and perst in power off phy: freescale: imx8m-pcie: cleanup reset logic phy: core: Remove unused phy_pm_runtime_(allow|forbid) dt-bindings: phy: document Allwinner A523 USB-2.0 PHY phy: phy-rockchip-samsung-hdptx: Add support for RK3576 ...
2025-03-11phy: freescale: imx8m-pcie: assert phy reset and perst in power offStefan Eichenberger
Ensure the PHY reset and perst is asserted during power-off to guarantee it is in a reset state upon repeated power-on calls. This resolves an issue where the PHY may not properly initialize during subsequent power-on cycles. Power-on will deassert the reset at the appropriate time after tuning the PHY parameters. During suspend/resume cycles, we observed that the PHY PLL failed to lock during resume when the CPU temperature increased from 65C to 75C. The observed errors were: phy phy-32f00000.pcie-phy.3: phy poweron failed --> -110 imx6q-pcie 33800000.pcie: waiting for PHY ready timeout! imx6q-pcie 33800000.pcie: PM: dpm_run_callback(): genpd_resume_noirq+0x0/0x80 returns -110 imx6q-pcie 33800000.pcie: PM: failed to resume noirq: error -110 This resulted in a complete CPU freeze, which is resolved by ensuring the PHY is in reset during power-on, thus preventing PHY PLL failures. Cc: stable@vger.kernel.org Fixes: 1aa97b002258 ("phy: freescale: pcie: Initialize the imx8 pcie standalone phy driver") Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20250305144355.20364-3-eichest@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-03-11phy: freescale: imx8m-pcie: cleanup reset logicStefan Eichenberger
Remove the switch statement and base perst release on whether it is found in the device tree. The probe function fails without the reset property, making it mandatory. Therefore, always release reset independent of the variant. This does not change the behavior of the driver but reduces driver complexity and allows for easier future modifications. Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20250305144355.20364-2-eichest@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-14phy: fsl-imx8mq-usb: add tca function driver for imx95Xu Yang
The i.MX95 USB3 phy has a Type-C Assist block (TCA). This block consists two functional blocks (XBar assist and VBus assist) and one system access interface using APB. The primary functionality of XBar assist is: - switching lane for flip - moving unused lanes into lower power states. This info can be get from: i.MX95 RM Chapter 163.3.8 Type-C assist (TCA) block. This will add support for TCA block to achieve lane switching and tca lower power functionality. Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Reviewed-by: Jun Li <jun.li@nxp.com> Link: https://lore.kernel.org/r/20241204050907.1081781-1-xu.yang_2@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-13phy: freescale: fsl-samsung-hdmi: Use helper function devm_clk_get_enabled()Pei Xiao
Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be replaced by devm_clk_get_enabled() when driver enables the clocks for the whole lifetime of the device. Moreover, it is no longer necessary to unprepare and disable the clocks explicitly. Signed-off-by: Pei Xiao <xiaopei01@kylinos.cn> Link: https://lore.kernel.org/r/tencent_9087BCE04E38E6AA5C4B2252B82FA99C2009@qq.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-13phy: freescale: fsl-samsung-hdmi: Limit PLL lock detection clock divider to ↵Pei Xiao
valid range FIELD_PREP() checks that a value fits into the available bitfield, but the index div equals to 4,is out of range. which gcc complains about: In function ‘fsl_samsung_hdmi_phy_configure_pll_lock_det’, inlined from ‘fsl_samsung_hdmi_phy_configure’ at drivers/phy/freescale/phy-fsl-samsung-hdmi.c :470:2: ././include/linux/compiler_types.h:542:38: error: call to ‘__compiletime_assert_538’ declared with attribute error: FIELD_PREP: value too large for the field 542 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) | ^ ././include/linux/compiler_types.h:523:4: note: in definition of macro ‘__compiletime_assert’ 523 | prefix ## suffix(); | ^~~~~~ ././include/linux/compiler_types.h:542:2: note: in expansion of macro ‘_compiletime_assert’ 542 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) REG12_CK_DIV_MASK only two bit, limit div to range 0~3, so build error will fix. Fixes: d567679f2b6a ("phy: freescale: fsl-samsung-hdmi: Clean up fld_tg_code calculation") Signed-off-by: Pei Xiao <xiaopei01@kylinos.cn> Changlog: Reviewed-by: Adam Ford <aford173@gmail.com> Link: https://lore.kernel.org/r/tencent_6F503D43467AA99DD8CC59B8F645F0725B0A@qq.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-01-29Merge tag 'phy-for-6.14' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "Lots of Qualcomm and Rockchip device support. New Support: - Qualcomm SAR2130P qmp usb, SAR2130P qmp pcie, QCS615 qusb2 and PCIe, IPQ5424 qmp pcie, IPQ5424 QUSB2 and USB3 PHY - Rockchip rk3576 combo phy support Updates: - Drop Shengyang for JH7110 maintainer - Freescale hdmi register calculation optimization - Rockchip pcie phy mutex and regmap updates" * tag 'phy-for-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (37 commits) dt-bindings: phy: qcom,qmp-pcie: document the SM8350 two lanes PCIe PHY phy: rockchip: phy-rockchip-typec: Fix Copyright description dt-bindings: phy: qcom,ipq8074-qmp-pcie: Document the IPQ5424 QMP PCIe PHYs phy: qcom-qusb2: Add support for QCS615 dt-bindings: usb: qcom,dwc3: Add QCS615 to USB DWC3 bindings phy: core: Simplify API of_phy_simple_xlate() implementation phy: sun4i-usb: Remove unused of_gpio.h phy: HiSilicon: Don't use "proxy" headers phy: samsung-ufs: switch back to syscon_regmap_lookup_by_phandle() phy: qualcomm: qmp-pcie: add support for SAR2130P phy: qualcomm: qmp-pcie: define several new registers phy: qualcomm: qmp-pcie: split PCS_LANE1 region phy: qualcomm: qmp-combo: add support for SAR2130P dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add SAR2130P compatible dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp: Add SAR2130P compatible phy: freescale: fsl-samsung-hdmi: Clean up fld_tg_code calculation phy: freescale: fsl-samsung-hdmi: Stop searching when exact match is found phy: freescale: fsl-samsung-hdmi: Expand Integer divider range phy: rockchip-naneng-combo: add rk3576 support dt-bindings: phy: rockchip: add rk3576 compatible ...
2024-12-24phy: freescale: fsl-samsung-hdmi: Fix 64-by-32 division cocci warningsAdam Ford
The Kernel test robot returns the following warning: do_div() does a 64-by-32 division, please consider using div64_ul instead. To prevent the 64-by-32 divsion, consolidate both the multiplication and the do_div into one line which explicitly uses u64 sizes. Fixes: 1951dbb41d1d ("phy: freescale: fsl-samsung-hdmi: Support dynamic integer") Signed-off-by: Adam Ford <aford173@gmail.com> Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202412091243.fSObwwPi-lkp@intel.com/ Link: https://lore.kernel.org/r/20241215220555.99113-1-aford173@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-08phy: freescale: fsl-samsung-hdmi: Clean up fld_tg_code calculationAdam Ford
Currently, the calcuation for fld_tg_code is based on a lookup table, but there are gaps in the lookup table, and frequencies in these gaps may not properly use the correct divider. Based on the description of FLD_CK_DIV, the internal PLL frequency should be less than 50 MHz, so directly calcuate the value of FLD_CK_DIV from pixclk. This allow for proper calcuation of any pixel clock and eliminates a few gaps in the LUT. Since the value of the int_pllclk is in Hz, do the fixed-point math in Hz to achieve a more accurate value and reduces the complexity of the caluation to 24MHz * (256 / int_pllclk). Fixes: 6ad082bee902 ("phy: freescale: add Samsung HDMI PHY") Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Link: https://lore.kernel.org/r/20241026132014.73050-3-aford173@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-08phy: freescale: fsl-samsung-hdmi: Stop searching when exact match is foundAdam Ford
There are a series of for-loops which check various values of P and S for the integer divder PLL. The for loops search all entries and use the one closest to the nominal, but it continues to searches through all for loops even after the nominal is achieved. Ending when the nominal value is found stops wasting time, since it will not find a better value than a deviation of 0 Hz. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Link: https://lore.kernel.org/r/20241026132014.73050-2-aford173@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-08phy: freescale: fsl-samsung-hdmi: Expand Integer divider rangeAdam Ford
The Integer divder uses values of P,M, and S to determine the PLL rate. Currently, the range of M was set based on a series of table entries where the range was limited. Since the ref manual shows it is 8-bit wide, expand the range to be up to 255. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Link: https://lore.kernel.org/r/20241026132014.73050-1-aford173@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-11-27Merge tag 'phy-for-6.13' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "New hardware support: - ST STM32MP25 combophy support - Sparx5 support for lan969x serdes and updates to driver to support this - NXP PTN3222 eUSB2 to USB2 redriver - Qualcomm SAR2130P eusb2 support, QCS8300 USB DW3 and QMP USB2 support, X1E80100 QMP PCIe PHY Gen4 support, QCS615 and QCS8300 QMP UFS PHY support and SA8775P eDP PHY support - Rockchip rk3576 usbdp and rk3576 usb2 phy support - Binding for Microchip ATA6561 can phy Updates: - Freescale driver updates from hdmi support - Conversion of rockchip rk3228 hdmi phy binding to yaml - Broadcom usb2-phy deprecated support dropped and USB init array update for BCM4908 - TI USXGMII mode support in J7200 - Switch back to platform_driver::remove() subsystem update" * tag 'phy-for-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (59 commits) phy: qcom: qmp: Fix lecacy-legacy typo phy: lan969x-serdes: add support for lan969x serdes driver dt-bindings: phy: sparx5: document lan969x phy: sparx5-serdes: add support for branching on chip type phy: sparx5-serdes: add indirection layer to register macros phy: sparx5-serdes: add function for getting the CMU index phy: sparx5-serdes: add ops to match data phy: sparx5-serdes: add constant for the number of CMU's phy: sparx5-serdes: add constants to match data phy: sparx5-serdes: add support for private match data phy: bcm-ns-usb2: drop support for old binding variant dt-bindings: phy: bcm-ns-usb2-phy: drop deprecated variant dt-bindings: phy: Add QMP UFS PHY compatible for QCS8300 dt-bindings: phy: qcom: snps-eusb2: Add SAR2130P compatible dt-bindings: phy: ti,tcan104x-can: Document Microchip ATA6561 phy: airoha: Fix REG_CSR_2L_RX{0,1}_REV0 definitions phy: airoha: Fix REG_CSR_2L_JCPLL_SDM_HREN config in airoha_pcie_phy_init_ssc_jcpll() phy: airoha: Fix REG_PCIE_PMA_TX_RESET config in airoha_pcie_phy_init_csr_2l() phy: airoha: Fix REG_CSR_2L_PLL_CMN_RESERVE0 config in airoha_pcie_phy_init_clk_out() phy: phy-rockchip-samsung-hdptx: Don't request RST_PHY/RST_ROPLL/RST_LCPLL ...
2024-10-21phy: freescale: imx8m-pcie: Do CMN_RST just before PHY PLL lock checkRichard Zhu
When enable initcall_debug together with higher debug level below. CONFIG_CONSOLE_LOGLEVEL_DEFAULT=9 CONFIG_CONSOLE_LOGLEVEL_QUIET=9 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 The initialization of i.MX8MP PCIe PHY might be timeout failed randomly. To fix this issue, adjust the sequence of the resets refer to the power up sequence listed below. i.MX8MP PCIe PHY power up sequence: /--------------------------------------------- 1.8v supply ---------/ /--------------------------------------------------- 0.8v supply ---/ ---\ /-------------------------------------------------- X REFCLK Valid Reference Clock ---/ \-------------------------------------------------- ------------------------------------------- | i_init_restn -------------- ------------------------------------ | i_cmn_rstn --------------------- ------------------------------- | o_pll_lock_done -------------------------- Logs: imx6q-pcie 33800000.pcie: host bridge /soc@0/pcie@33800000 ranges: imx6q-pcie 33800000.pcie: IO 0x001ff80000..0x001ff8ffff -> 0x0000000000 imx6q-pcie 33800000.pcie: MEM 0x0018000000..0x001fefffff -> 0x0018000000 probe of clk_imx8mp_audiomix.reset.0 returned 0 after 1052 usecs probe of 30e20000.clock-controller returned 0 after 32971 usecs phy phy-32f00000.pcie-phy.4: phy poweron failed --> -110 probe of 30e10000.dma-controller returned 0 after 10235 usecs imx6q-pcie 33800000.pcie: waiting for PHY ready timeout! dwhdmi-imx 32fd8000.hdmi: Detected HDMI TX controller v2.13a with HDCP (samsung_dw_hdmi_phy2) imx6q-pcie 33800000.pcie: probe with driver imx6q-pcie failed with error -110 Fixes: dce9edff16ee ("phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY support") Cc: stable@vger.kernel.org Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> v2 changes: - Rebase to latest fixes branch of linux-phy git repo. - Richard's environment have problem and can't sent out patch. So I help post this fix patch. Link: https://lore.kernel.org/r/20241021155241.943665-1-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: Switch back to struct platform_driver::remove()Uwe Kleine-König
After commit 0edb555a65d1 ("platform: Make platform_driver::remove() return void") .remove() is (again) the right callback to implement for platform drivers. Convert all platform drivers below drivers/phy/ to use .remove(), with the eventual goal to drop struct platform_driver::remove_new(). As .remove() and .remove_new() have the same prototypes, conversion is done by just changing the structure member name in the driver initializer. While touching these files, make indention of the struct initializer consistent in several files. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Link: https://lore.kernel.org/r/20241009065307.504930-2-u.kleine-koenig@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: freescale: fsl-samsung-hdmi: Remove unnecessary LUT entriesAdam Ford
The lookup table contains entries which use the integer divider instead of just the fractional divider. Since the set and round functions check both the integer divider values and the LUT values, it's no longer necessary to keep the integer divider values in the lookup table, as can be dynamically calcuated. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Dominique Martinet <dominique.martinet@atmark-techno.com> Tested-by: Dominique Martinet <dominique.martinet@atmark-techno.com> Link: https://lore.kernel.org/r/20240914112816.520224-6-aford173@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: freescale: fsl-samsung-hdmi: Use closest dividerAdam Ford
Currently, if the clock values cannot be set to the exact rate, the round_rate and set_rate functions use the closest value found in the look-up-table. In preparation of removing values from the LUT that can be calculated evenly with the integer calculator, it's necessary to ensure to check both the look-up-table and the integer divider clock values to get the closest values to the requested value. It does this by measuring the difference between the requested clock value and the closest value in both integer divider calucator and the fractional clock look-up-table. Which ever has the smallest difference between them is returned as the closest rate. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Dominique Martinet <dominique.martinet@atmark-techno.com> Tested-by: Dominique Martinet <dominique.martinet@atmark-techno.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Link: https://lore.kernel.org/r/20240914112816.520224-5-aford173@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3 (git 2.46.0) at 2026-03-04 11:00:34 +0000