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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,ufoe.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek display UFOe
maintainers:
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
- Philipp Zabel <p.zabel@pengutronix.de>
description: |
Mediatek display UFOe stands for Unified Frame Optimization engine.
UFOe can cut the data rate for DSI port which may lead to reduce power
consumption.
UFOe device node must be siblings to the central MMSYS_CONFIG node.
For a description of the MMSYS_CONFIG binding, see
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
for details.
properties:
compatible:
oneOf:
- enum:
- mediatek,mt8173-disp-ufoe
- items:
- const: mediatek,mt6795-disp-ufoe
- const: mediatek,mt8173-disp-ufoe
reg:
maxItems: 1
interrupts:
maxItems: 1
power-domains:
description: A phandle and PM domain specifier as defined by bindings of
the power controller specified by phandle. See
Documentation/devicetree/bindings/power/power-domain.yaml for details.
clocks:
items:
- description: UFOe Clock
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Input and output ports can have multiple endpoints, each of those
connects to either the primary, secondary, etc, display pipeline.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: UFOE input, usually from one of the RDMA blocks.
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
UFOE output to the input of the next desired component in the
display pipeline, usually one of the available DSI blocks.
required:
- port@0
- port@1
mediatek,gce-client-reg:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: describes how to locate the GCE client register
items:
- items:
- description: Phandle reference to a Mediatek GCE Mailbox
- description:
GCE subsys id mapping to a client defined in header
include/dt-bindings/gce/<chip>-gce.h.
- description: offset for the GCE register offset
- description: size of the GCE register offset
required:
- compatible
- reg
- interrupts
- power-domains
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/gce/mt8173-gce.h>
#include <dt-bindings/power/mt8173-power.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
ufoe@1401a000 {
compatible = "mediatek,mt8173-disp-ufoe";
reg = <0 0x1401a000 0 0x1000>;
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_UFOE>;
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>;
};
};
|
