1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip FPGA {Q,}SPI Controllers
description:
SPI and QSPI controllers on Microchip PolarFire SoC and the "soft"/
fabric IP cores they are based on
maintainers:
- Conor Dooley <conor.dooley@microchip.com>
properties:
compatible:
oneOf:
- items:
- enum:
- microchip,mpfs-qspi
- microchip,pic64gx-qspi
- const: microchip,coreqspi-rtl-v2
- enum:
- microchip,coreqspi-rtl-v2 # FPGA QSPI
- microchip,corespi-rtl-v5 # FPGA CoreSPI
- microchip,mpfs-spi
- items:
- const: microchip,pic64gx-spi
- const: microchip,mpfs-spi
reg:
maxItems: 1
interrupts:
maxItems: 1
clock-names:
maxItems: 1
clocks:
maxItems: 1
microchip,apb-datawidth:
description: APB bus data width in bits.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [8, 16, 32]
default: 8
microchip,frame-size:
description: |
Number of bits per SPI frame, as configured in Libero.
In Motorola and TI modes, this corresponds directly
to the requested frame size. For NSC mode this is set
to 9 + the required data frame size.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 4
maximum: 32
default: 8
microchip,protocol-configuration:
description: CoreSPI protocol selection. Determines operating mode
$ref: /schemas/types.yaml#/definitions/string
enum:
- motorola
- ti
- nsc
default: motorola
microchip,motorola-mode:
description: Motorola SPI mode selection
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 3
microchip,ssel-active:
description: |
Keep SSEL asserted between frames when using the Motorola protocol.
When present, the controller keeps SSEL active across contiguous
transfers and deasserts only when the overall transfer completes.
type: boolean
required:
- compatible
- reg
- interrupts
- clocks
allOf:
- $ref: spi-controller.yaml#
- if:
properties:
compatible:
contains:
const: microchip,mpfs-spi
then:
properties:
num-cs:
default: 1
- if:
properties:
compatible:
contains:
const: microchip,mpfs-spi
not:
required:
- cs-gpios
then:
properties:
num-cs:
maximum: 1
- if:
properties:
compatible:
contains:
const: microchip,corespi-rtl-v5
then:
properties:
num-cs:
minimum: 1
maximum: 8
default: 8
fifo-depth:
minimum: 1
maximum: 32
default: 4
else:
properties:
microchip,apb-datawidth: false
microchip,frame-size: false
microchip,protocol-configuration: false
microchip,motorola-mode: false
microchip,ssel-active: false
unevaluatedProperties: false
examples:
- |
#include "dt-bindings/clock/microchip,mpfs-clock.h"
spi@20108000 {
compatible = "microchip,mpfs-spi";
reg = <0x20108000 0x1000>;
clocks = <&clkcfg CLK_SPI0>;
interrupt-parent = <&plic>;
interrupts = <54>;
};
...
|