mimxrt/boards: Re-generate MIMXRT1052 clock config files.

These were regenerated by the NXP Config tool for v2.11.

The board_init update was needed to ensure CLOCK_SetMode() is run
at the appropriate time during startup.

Signed-off-by: Andrew Leech <andrew.leech@planetinnovation.com.au>

3 files changed, 132 insertions, 103 deletions

diff --git a/ports/mimxrt/board_init.c b/ports/mimxrt/board_init.c
index 88de27ea7..0643da064 100644
--- a/ports/mimxrt/board_init.c
+++ b/ports/mimxrt/board_init.c
@@ -52,6 +52,9 @@ void board_init(void) {
     SCB_EnableICache();
     // Init clock
     BOARD_BootClockRUN();
+    #if !defined(MIMXRT117x_SERIES)
+    CLOCK_SetMode(kCLOCK_ModeRun);
+    #endif
     SystemCoreClockUpdate();
 
     // Enable IOCON clock
diff --git a/ports/mimxrt/boards/MIMXRT1052_clock_config.c b/ports/mimxrt/boards/MIMXRT1052_clock_config.c
index bff43ae5e..de65a3e58 100644
--- a/ports/mimxrt/boards/MIMXRT1052_clock_config.c
+++ b/ports/mimxrt/boards/MIMXRT1052_clock_config.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2017-2019 NXP
+ * Copyright 2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -22,11 +22,11 @@
 
 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
 !!GlobalInfo
-product: Clocks v5.0
+product: Clocks v10.0
 processor: MIMXRT1052xxxxB
 package_id: MIMXRT1052DVL6B
 mcu_data: ksdk2_0
-processor_version: 0.0.0
+processor_version: 0.12.10
 board: IMXRT1050-EVKB
  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
 
@@ -40,8 +40,6 @@ board: IMXRT1050-EVKB
 /*******************************************************************************
  * Variables
  ******************************************************************************/
-/* System clock frequency. */
-extern uint32_t SystemCoreClock;
 
 /*******************************************************************************
  ************************ BOARD_InitBootClocks function ************************
@@ -64,7 +62,6 @@ outputs:
 - {id: CLK_1M.outFreq, value: 1 MHz}
 - {id: CLK_24M.outFreq, value: 24 MHz}
 - {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
-- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz}
 - {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
 - {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
 - {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
@@ -92,7 +89,7 @@ outputs:
 - {id: SAI3_MCLK3.outFreq, value: 30 MHz}
 - {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
 - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
-- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
 - {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
 - {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
 - {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
@@ -104,7 +101,7 @@ settings:
 - {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
 - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
 - {id: CCM.SEMC_PODF.scale, value: '8'}
-- {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
+- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
 - {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
 - {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
 - {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
@@ -125,31 +122,45 @@ settings:
 - {id: CCM_ANALOG.PLL4.denom, value: '50'}
 - {id: CCM_ANALOG.PLL4.div, value: '47'}
 - {id: CCM_ANALOG.PLL5.denom, value: '1'}
-- {id: CCM_ANALOG.PLL5.div, value: '40'}
+- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
 - {id: CCM_ANALOG.PLL5.num, value: '0'}
+- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
+- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'}
+- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'}
 - {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
 - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
 sources:
-- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
 - {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
 
 /*******************************************************************************
  * Variables for BOARD_BootClockRUN configuration
  ******************************************************************************/
-const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = {
-    .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
-    .src = 0,           /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
+{
+    .loopDivider = 100,                           /* PLL loop divider, Fout = Fin * 50 */
+    .src = 0,                                     /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
 };
-const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = {
-    .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
-    .numerator = 0,   /* 30 bit numerator of fractional loop divider */
-    .denominator = 1, /* 30 bit denominator of fractional loop divider */
-    .src = 0,         /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+{
+    .loopDivider = 1,                             /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+    .numerator = 0,                               /* 30 bit numerator of fractional loop divider */
+    .denominator = 1,                             /* 30 bit denominator of fractional loop divider */
+    .src = 0,                                     /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
 };
-const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = {
-    .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
-    .src = 0,         /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+{
+    .loopDivider = 0,                             /* PLL loop divider, Fout = Fin * 20 */
+    .src = 0,                                     /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+};
+const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
+{
+    .loopDivider = 31,                            /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+    .postDivider = 8,                             /* Divider after PLL */
+    .numerator = 0,                               /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+    .denominator = 1,                             /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+    .src = 0,                                     /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
 };
 /*******************************************************************************
  * Code for BOARD_BootClockRUN configuration
@@ -213,10 +224,9 @@ void BOARD_BootClockRUN(void) {
     CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
     /* Set Usdhc2 clock source. */
     CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
-/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
- * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left
- * unchanged.
- * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
     #ifndef SKIP_SYSCLK_INIT
     /* Disable Semc clock gate. */
     CLOCK_DisableClock(kCLOCK_Semc);
@@ -227,10 +237,9 @@ void BOARD_BootClockRUN(void) {
     /* Set Semc clock source. */
     CLOCK_SetMux(kCLOCK_SemcMux, 0);
     #endif
-/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
- * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
- * unchanged.
- * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
     #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
     /* Disable Flexspi clock gate. */
     CLOCK_DisableClock(kCLOCK_FlexSpi);
@@ -257,9 +266,9 @@ void BOARD_BootClockRUN(void) {
     /* Disable TRACE clock gate. */
     CLOCK_DisableClock(kCLOCK_Trace);
     /* Set TRACE_PODF. */
-    CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
+    CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
     /* Set Trace clock source. */
-    CLOCK_SetMux(kCLOCK_TraceMux, 2);
+    CLOCK_SetMux(kCLOCK_TraceMux, 0);
     /* Disable SAI1 clock gate. */
     CLOCK_DisableClock(kCLOCK_Sai1);
     /* Set SAI1_CLK_PRED. */
@@ -351,10 +360,12 @@ void BOARD_BootClockRUN(void) {
     /* Init ARM PLL. */
     CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
     /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
-     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left
-     * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as
-     * well.*/
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
     #ifndef SKIP_SYSCLK_INIT
+    #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+    #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
+    #endif
     /* Init System PLL. */
     CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
     /* Init System pfd0. */
@@ -365,13 +376,10 @@ void BOARD_BootClockRUN(void) {
     CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
     /* Init System pfd3. */
     CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
-    /* Disable pfd offset. */
-    CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK;
     #endif
     /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
-     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
-     * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
-     * well.*/
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
     #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
     /* Init Usb1 PLL. */
     CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
@@ -395,21 +403,30 @@ void BOARD_BootClockRUN(void) {
     CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
     /* Enable Audio PLL output. */
     CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
-    /* DeInit Video PLL. */
-    CLOCK_DeinitVideoPll();
-    /* Bypass Video PLL. */
-    CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
-    /* Set divider for Video PLL. */
-    CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0);
-    /* Enable Video PLL output. */
-    CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
+    /* Init Video PLL. */
+    uint32_t pllVideo;
+    /* Disable Video PLL output before initial Video PLL. */
+    CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
+    /* Bypass PLL first */
+    CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
+        CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
+    CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
+    CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
+    pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
+        CCM_ANALOG_PLL_VIDEO_ENABLE_MASK | CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
+    pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
+    CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
+    CCM_ANALOG->PLL_VIDEO = pllVideo;
+    while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) {
+    }
+    /* Disable bypass for Video PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
     /* DeInit Enet PLL. */
     CLOCK_DeinitEnetPll();
     /* Bypass Enet PLL. */
     CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
     /* Set Enet output divider. */
-    CCM_ANALOG->PLL_ENET =
-        (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
+    CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
     /* Enable Enet output. */
     CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
     /* Enable Enet25M output. */
@@ -429,8 +446,7 @@ void BOARD_BootClockRUN(void) {
     /* Set per clock source. */
     CLOCK_SetMux(kCLOCK_PerclkMux, 0);
     /* Set lvds1 clock source. */
-    CCM_ANALOG->MISC1 =
-        (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
+    CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
     /* Set clock out1 divider. */
     CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
     /* Set clock out1 source. */
@@ -457,13 +473,19 @@ void BOARD_BootClockRUN(void) {
     IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
     /* Set MQS configuration. */
     IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0);
-    /* Set ENET Tx clock source. */
-    IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false);
+    /* Set ENET Ref clock source. */
+    #if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
+    #elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
+    /* Backward compatibility for original bitfield name */
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+    #else
+    #error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined."
+    #endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */
     /* Set GPT1 High frequency reference clock source. */
     IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
     /* Set GPT2 High frequency reference clock source. */
     IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
     /* Set SystemCoreClock variable. */
     SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
-    CLOCK_SetMode(kCLOCK_ModeRun);
 }
diff --git a/ports/mimxrt/boards/MIMXRT1052_clock_config.h b/ports/mimxrt/boards/MIMXRT1052_clock_config.h
index 358a6f03b..0e7febef3 100644
--- a/ports/mimxrt/boards/MIMXRT1052_clock_config.h
+++ b/ports/mimxrt/boards/MIMXRT1052_clock_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2017-2019 NXP
+ * Copyright 2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -13,9 +13,9 @@
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
-#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
 
-#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
 /*******************************************************************************
  ************************ BOARD_InitBootClocks function ************************
  ******************************************************************************/
@@ -40,54 +40,55 @@ void BOARD_InitBootClocks(void);
 /*******************************************************************************
  * Definitions for BOARD_BootClockRUN configuration
  ******************************************************************************/
-#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             600000000U  /*!< Core clock frequency: 600000000Hz */
 
 /* Clock outputs (values are in Hz): */
-#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
-#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
-#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
-#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
-#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
-#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
-#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
-#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
-#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL
-#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
-#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
-#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
-#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
-#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 160000000UL
-#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
-#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
-#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
-#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 9642857UL
-#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
-#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
-#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
-#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
-#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
-#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL
-#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
-#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
-#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
-#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
-#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
-#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
-#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
-#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
-#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
-#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
-#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
-#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
-#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
-#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
-#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
-#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL
-#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 40000000UL
-#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL
-#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL
-#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
-#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT               600000000UL
+#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT               40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT         32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M                    24000000UL
+#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT               12000000UL
+#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK              2400000UL
+#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK           1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK               0UL
+#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK                0UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT           160000000UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      75000000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      75000000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               150000000UL
+#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT             67500000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             105600000UL
+#define BOARD_BOOTCLOCKRUN_LVDS1_CLK                  1200000000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK                   63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            75000000UL
+#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK              24000000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT              75000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             132000000UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK                0UL
+#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK                0UL
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT            198000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT            198000000UL
 
 /*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
  */
@@ -98,6 +99,9 @@ extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
 /*! @brief Sys PLL for BOARD_BootClockRUN configuration.
  */
 extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
 
 /*******************************************************************************
  * API for BOARD_BootClockRUN configuration