diff options
| author | iabdalkader <i.abdalkader@gmail.com> | 2024-11-30 09:56:23 +0100 |
|---|---|---|
| committer | Damien George <damien@micropython.org> | 2024-12-10 10:49:50 +1100 |
| commit | 17808e7b749b269b58dcee67df599a0c61d455bd (patch) | |
| tree | e41c7a3afc7e45a802617119e3fd4c08725b9a19 | |
| parent | 47d9988df2c7c6a4603f631b02a3f3a5c7e997f4 (diff) | |
stm32/sdram: Make SDRAM refresh count configurable by a board.
Refresh count calculations were using a hard-coded SDRAM frequency and
refresh cycles, so change them to values that can be set by a board.
And set these options to their existing values on STM32F769DISC and
STM32F7DISC boards.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
| -rw-r--r-- | ports/stm32/boards/STM32F769DISC/mpconfigboard.h | 2 | ||||
| -rw-r--r-- | ports/stm32/boards/STM32F7DISC/mpconfigboard.h | 2 | ||||
| -rw-r--r-- | ports/stm32/sdram.c | 6 |
3 files changed, 7 insertions, 3 deletions
diff --git a/ports/stm32/boards/STM32F769DISC/mpconfigboard.h b/ports/stm32/boards/STM32F769DISC/mpconfigboard.h index f899091d2..017de9c06 100644 --- a/ports/stm32/boards/STM32F769DISC/mpconfigboard.h +++ b/ports/stm32/boards/STM32F769DISC/mpconfigboard.h @@ -141,6 +141,7 @@ extern struct _spi_bdev_t spi_bdev; #define MICROPY_HW_SDRAM_BURST_LENGTH 1 #define MICROPY_HW_SDRAM_CAS_LATENCY 2 +#define MICROPY_HW_SDRAM_FREQUENCY_KHZ (90000) // 90 MHz #define MICROPY_HW_SDRAM_COLUMN_BITS_NUM 8 #define MICROPY_HW_SDRAM_ROW_BITS_NUM 12 #define MICROPY_HW_SDRAM_MEM_BUS_WIDTH 32 @@ -150,6 +151,7 @@ extern struct _spi_bdev_t spi_bdev; #define MICROPY_HW_SDRAM_RBURST (1) #define MICROPY_HW_SDRAM_WRITE_PROTECTION (0) #define MICROPY_HW_SDRAM_AUTOREFRESH_NUM (8) +#define MICROPY_HW_SDRAM_REFRESH_CYCLES 8192 // See pins.csv for CPU pin mapping #define MICROPY_HW_FMC_SDCKE0 (pyb_pin_FMC_SDCKE0) diff --git a/ports/stm32/boards/STM32F7DISC/mpconfigboard.h b/ports/stm32/boards/STM32F7DISC/mpconfigboard.h index cf7061902..d4b21484a 100644 --- a/ports/stm32/boards/STM32F7DISC/mpconfigboard.h +++ b/ports/stm32/boards/STM32F7DISC/mpconfigboard.h @@ -111,6 +111,7 @@ void STM32F7DISC_board_early_init(void); #define MICROPY_HW_SDRAM_BURST_LENGTH 1 #define MICROPY_HW_SDRAM_CAS_LATENCY 2 +#define MICROPY_HW_SDRAM_FREQUENCY_KHZ (90000) // 90 MHz #define MICROPY_HW_SDRAM_COLUMN_BITS_NUM 8 #define MICROPY_HW_SDRAM_ROW_BITS_NUM 12 #define MICROPY_HW_SDRAM_MEM_BUS_WIDTH 16 @@ -120,6 +121,7 @@ void STM32F7DISC_board_early_init(void); #define MICROPY_HW_SDRAM_RBURST (1) #define MICROPY_HW_SDRAM_WRITE_PROTECTION (0) #define MICROPY_HW_SDRAM_AUTOREFRESH_NUM (8) +#define MICROPY_HW_SDRAM_REFRESH_CYCLES 8192 #define MICROPY_HW_FMC_SDCKE0 (pin_C3) #define MICROPY_HW_FMC_SDNE0 (pin_H3) diff --git a/ports/stm32/sdram.c b/ports/stm32/sdram.c index e99f34d22..7104eb68e 100644 --- a/ports/stm32/sdram.c +++ b/ports/stm32/sdram.c @@ -245,15 +245,15 @@ static void sdram_init_seq(SDRAM_HandleTypeDef /* Send the command */ HAL_SDRAM_SendCommand(hsdram, command, 0x1000); - /* Step 8: Set the refresh rate counter + /* Step 8: Set the refresh rate counter. + Assuming 90MHz frequency, 8192 refresh cycles and 64ms refresh rate: RefreshRate = 64 ms / 8192 cyc = 7.8125 us/cyc - RefreshCycles = 7.8125 us * 90 MHz = 703 According to the formula on p.1665 of the reference manual, we also need to subtract 20 from the value, so the target refresh rate is 703 - 20 = 683. */ - #define REFRESH_COUNT (MICROPY_HW_SDRAM_REFRESH_RATE * 90000 / 8192 - 20) + #define REFRESH_COUNT (MICROPY_HW_SDRAM_REFRESH_RATE * MICROPY_HW_SDRAM_FREQUENCY_KHZ / MICROPY_HW_SDRAM_REFRESH_CYCLES - 20) HAL_SDRAM_ProgramRefreshRate(hsdram, REFRESH_COUNT); #if defined(STM32F7) || defined(STM32H7) |