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authorMike Causer <mcauser@gmail.com>2020-01-13 17:26:01 +1100
committerDamien George <damien@micropython.org>2021-05-20 23:17:51 +1000
commit1ca66efbf7be4f57ab31df5ecb81d27da4aefd0d (patch)
tree6826bc1009ad6e2c53f5663c2cb4d33b6846799f
parentc24003abec78ee443ddc1bdc375c48513e45a54a (diff)
stm32/boards: Add VCC_GND_F407ZG board.
-rw-r--r--ports/stm32/boards/VCC_GND_F407ZG/bdev.c28
-rw-r--r--ports/stm32/boards/VCC_GND_F407ZG/board_init.c7
-rw-r--r--ports/stm32/boards/VCC_GND_F407ZG/mpconfigboard.h182
-rw-r--r--ports/stm32/boards/VCC_GND_F407ZG/mpconfigboard.mk10
-rw-r--r--ports/stm32/boards/VCC_GND_F407ZG/pins.csv157
-rw-r--r--ports/stm32/boards/VCC_GND_F407ZG/stm32f4xx_hal_conf.h15
6 files changed, 399 insertions, 0 deletions
diff --git a/ports/stm32/boards/VCC_GND_F407ZG/bdev.c b/ports/stm32/boards/VCC_GND_F407ZG/bdev.c
new file mode 100644
index 000000000..18b5b85b1
--- /dev/null
+++ b/ports/stm32/boards/VCC_GND_F407ZG/bdev.c
@@ -0,0 +1,28 @@
+#include "storage.h"
+
+#if !MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE
+
+// External SPI flash uses standard SPI interface
+
+STATIC const mp_soft_spi_obj_t soft_spi_bus = {
+ .delay_half = MICROPY_HW_SOFTSPI_MIN_DELAY,
+ .polarity = 0,
+ .phase = 0,
+ .sck = MICROPY_HW_SPIFLASH_SCK,
+ .mosi = MICROPY_HW_SPIFLASH_MOSI,
+ .miso = MICROPY_HW_SPIFLASH_MISO,
+};
+
+STATIC mp_spiflash_cache_t spi_bdev_cache;
+
+const mp_spiflash_config_t spiflash_config = {
+ .bus_kind = MP_SPIFLASH_BUS_SPI,
+ .bus.u_spi.cs = MICROPY_HW_SPIFLASH_CS,
+ .bus.u_spi.data = (void*)&soft_spi_bus,
+ .bus.u_spi.proto = &mp_soft_spi_proto,
+ .cache = &spi_bdev_cache,
+};
+
+spi_bdev_t spi_bdev;
+
+#endif
diff --git a/ports/stm32/boards/VCC_GND_F407ZG/board_init.c b/ports/stm32/boards/VCC_GND_F407ZG/board_init.c
new file mode 100644
index 000000000..1f4663fdf
--- /dev/null
+++ b/ports/stm32/boards/VCC_GND_F407ZG/board_init.c
@@ -0,0 +1,7 @@
+#include "py/mphal.h"
+
+void VCC_GND_F407ZG_board_early_init(void) {
+ // set SPI flash CS pin high
+ mp_hal_pin_output(pin_C4);
+ mp_hal_pin_write(pin_C4, 1);
+}
diff --git a/ports/stm32/boards/VCC_GND_F407ZG/mpconfigboard.h b/ports/stm32/boards/VCC_GND_F407ZG/mpconfigboard.h
new file mode 100644
index 000000000..bd17ab410
--- /dev/null
+++ b/ports/stm32/boards/VCC_GND_F407ZG/mpconfigboard.h
@@ -0,0 +1,182 @@
+/* This file is part of the MicroPython project, http://micropython.org/
+ * MIT License; Copyright (c) 2021 Damien P. George
+ */
+
+// STM32F407ZGT6 Mini by VCC-GND Studio
+// http://vcc-gnd.com/
+// https://item.taobao.com/item.htm?ft=t&id=523383164199
+// https://www.aliexpress.com/wholesale?SearchText=STM32F407ZGT6+Mini
+
+// DFU mode can be accessed by switching BOOT0 DIP ON (towards USB)
+
+#define MICROPY_HW_BOARD_NAME "VCC-GND STM32F407ZG"
+#define MICROPY_HW_MCU_NAME "STM32F407ZG"
+#define MICROPY_HW_FLASH_FS_LABEL "VCCGNDF407ZG"
+
+// 1 = use internal flash (1 MByte)
+// 0 = use onboard SPI flash (512 KByte) Winbond W25X40
+#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (0)
+
+#define MICROPY_HW_HAS_FLASH (1)
+#define MICROPY_HW_ENABLE_RNG (1)
+#define MICROPY_HW_ENABLE_RTC (1)
+#define MICROPY_HW_ENABLE_DAC (1)
+#define MICROPY_HW_ENABLE_USB (1)
+#define MICROPY_HW_ENABLE_SDCARD (1)
+
+// HSE is 25MHz
+#define MICROPY_HW_CLK_PLLM (25) // divide external clock by this to get 1MHz
+#define MICROPY_HW_CLK_PLLN (336) // PLL clock in MHz
+#define MICROPY_HW_CLK_PLLP (RCC_PLLP_DIV2) // divide PLL clock by this to get core clock
+#define MICROPY_HW_CLK_PLLQ (7) // divide core clock by this to get 48MHz
+
+// The board has a 32kHz crystal for the RTC
+#define MICROPY_HW_RTC_USE_LSE (1)
+#define MICROPY_HW_RTC_USE_US (0)
+// #define MICROPY_HW_RTC_USE_CALOUT (1) // turn on/off PC13 512Hz output
+
+// USART1
+#define MICROPY_HW_UART1_TX (pin_A9) // PA9,PB6
+#define MICROPY_HW_UART1_RX (pin_A10) // PA10,PB7
+#define MICROPY_HW_UART1_RTS (pin_A12)
+#define MICROPY_HW_UART1_CTS (pin_A11)
+// USART1_CK PA8
+
+// USART2
+#define MICROPY_HW_UART2_TX (pin_A2) // PA2,PD5
+#define MICROPY_HW_UART2_RX (pin_A3) // PA3,PD6
+#define MICROPY_HW_UART2_RTS (pin_A1) // PA1,PD4
+#define MICROPY_HW_UART2_CTS (pin_A0) // PA0,PD3
+// USART2_CK PA4,PD7
+
+// USART3
+#define MICROPY_HW_UART3_TX (pin_D8) // PB10,PC10,PD8
+#define MICROPY_HW_UART3_RX (pin_D9) // PB11,PC11,PD9
+#define MICROPY_HW_UART3_RTS (pin_D12) // PB14,PD12
+#define MICROPY_HW_UART3_CTS (pin_D11) // PB13,PD11
+// USART3_CK PB12,PC12,PD10
+
+// UART4
+#define MICROPY_HW_UART4_TX (pin_A0) // PA0,PC10
+#define MICROPY_HW_UART4_RX (pin_A1) // PA1,PC11
+
+// UART5
+#define MICROPY_HW_UART5_TX (pin_C12) // PC12
+#define MICROPY_HW_UART5_RX (pin_D2) // PD2
+
+// USART6
+#define MICROPY_HW_UART6_TX (pin_C6) // PC6,PG14
+#define MICROPY_HW_UART6_RX (pin_C7) // PC7,PG9
+#define MICROPY_HW_UART6_RTS (pin_G8) // PG8,PG12
+#define MICROPY_HW_UART6_CTS (pin_G13) // PG13,PG15
+// USART6_CK PC8,PG7
+
+// I2C buses
+#define MICROPY_HW_I2C1_SCL (pin_B6) // PB8,PB6
+#define MICROPY_HW_I2C1_SDA (pin_B7) // PB9,PB7
+// I2C1_SMBA PB5
+#define MICROPY_HW_I2C2_SCL (pin_B10) // PB10,PF1
+#define MICROPY_HW_I2C2_SDA (pin_B11) // PB11,PF0
+// I2C2_SMBA PB12,PF2
+#define MICROPY_HW_I2C3_SCL (pin_A8) // PA8
+#define MICROPY_HW_I2C3_SDA (pin_C9) // PC9
+// I2C3_SMBA PA9
+
+// AT24C08 EEPROM on I2C1 0x50-0x53
+
+// I2S buses - multiplexed with SPI2 and SPI3
+// I2S2_CK PB10,PB13
+// I2S2_MCK PC6
+// I2S2_SD PB15,PC3
+// I2S2_WS PB9,PB12
+// I2S3_CK PB3,PC10
+// I2S3_MCK PC7
+// I2S3_SD PB5,PC12
+// I2S3_WS PA4,PA15
+
+// SPI buses
+#define MICROPY_HW_SPI1_NSS (pin_A4) // PA4,PA15
+#define MICROPY_HW_SPI1_SCK (pin_A5) // PA5,PB3
+#define MICROPY_HW_SPI1_MISO (pin_A6) // PA6,PB4
+#define MICROPY_HW_SPI1_MOSI (pin_A7) // PA7,PB5
+
+#define MICROPY_HW_SPI2_NSS (pin_B12) // PB12,PB9
+#define MICROPY_HW_SPI2_SCK (pin_B13) // PB13,PB10
+#define MICROPY_HW_SPI2_MISO (pin_B14) // PB14,PC2
+#define MICROPY_HW_SPI2_MOSI (pin_B15) // PB15,PC3
+
+#define MICROPY_HW_SPI3_NSS (pin_A15) // PA15,PA4
+#define MICROPY_HW_SPI3_SCK (pin_B3) // PB3,PC10
+#define MICROPY_HW_SPI3_MISO (pin_B4) // PB4,PC11
+#define MICROPY_HW_SPI3_MOSI (pin_B5) // PB5,PC12
+
+// CAN buses
+#define MICROPY_HW_CAN1_TX (pin_B9) // PB9,PD1,PA12
+#define MICROPY_HW_CAN1_RX (pin_B8) // PB8,PD0,PA11
+#define MICROPY_HW_CAN2_TX (pin_B13) // PB13,PB6
+#define MICROPY_HW_CAN2_RX (pin_B12) // PB12,PB5
+
+// DAC
+// DAC_OUT1 PA4
+// DAC_OUT2 PA5
+
+// LEDs
+#define MICROPY_HW_LED1 (pin_G15) // blue
+#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_low(pin))
+#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_high(pin))
+
+// If using onboard SPI flash
+#if !MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE
+
+// W25X40 SPI Flash = 4 Mbit (512 KByte)
+#define MICROPY_HW_SPIFLASH_SIZE_BITS (4 * 1024 * 1024)
+#define MICROPY_HW_SPIFLASH_CS (pin_C4)
+#define MICROPY_HW_SPIFLASH_SCK (pin_A5)
+#define MICROPY_HW_SPIFLASH_MISO (pin_A6)
+#define MICROPY_HW_SPIFLASH_MOSI (pin_A7)
+
+#define MICROPY_BOARD_EARLY_INIT VCC_GND_F407ZG_board_early_init
+void VCC_GND_F407ZG_board_early_init(void);
+
+extern const struct _mp_spiflash_config_t spiflash_config;
+extern struct _spi_bdev_t spi_bdev;
+#define MICROPY_HW_BDEV_IOCTL(op, arg) ( \
+ (op) == BDEV_IOCTL_NUM_BLOCKS ? (MICROPY_HW_SPIFLASH_SIZE_BITS / 8 / FLASH_BLOCK_SIZE) : \
+ (op) == BDEV_IOCTL_INIT ? spi_bdev_ioctl(&spi_bdev, (op), (uint32_t)&spiflash_config) : \
+ spi_bdev_ioctl(&spi_bdev, (op), (arg)) \
+)
+#define MICROPY_HW_BDEV_READBLOCKS(dest, bl, n) spi_bdev_readblocks(&spi_bdev, (dest), (bl), (n))
+#define MICROPY_HW_BDEV_WRITEBLOCKS(src, bl, n) spi_bdev_writeblocks(&spi_bdev, (src), (bl), (n))
+
+#endif
+
+// SD card detect switch
+#define MICROPY_HW_SDCARD_DETECT_PIN (pin_F10)
+#define MICROPY_HW_SDCARD_DETECT_PULL (GPIO_PULLUP)
+#define MICROPY_HW_SDCARD_DETECT_PRESENT (GPIO_PIN_RESET)
+// 1 - PC10 - DAT2/RES
+// 2 - PC11 - CD/DAT3/CS
+// 3 - PD2 - CMD/DI
+// 4 - VCC - VDD
+// 5 - PC12 - CLK/SCLK
+// 6 - GND - VSS
+// 7 - PC8 - DAT0/D0
+// 8 - PC9 - DAT1/RES
+// 9 SW2 - GND
+// 10 SW1 - PF10
+
+// USB config
+#define MICROPY_HW_USB_FS (1)
+// #define MICROPY_HW_USB_VBUS_DETECT_PIN (pin_A9)
+// #define MICROPY_HW_USB_OTG_ID_PIN (pin_A10)
+
+// Ethernet via RMII
+#define MICROPY_HW_ETH_MDC (pin_C1)
+#define MICROPY_HW_ETH_MDIO (pin_A2)
+#define MICROPY_HW_ETH_RMII_REF_CLK (pin_A1)
+#define MICROPY_HW_ETH_RMII_CRS_DV (pin_A7)
+#define MICROPY_HW_ETH_RMII_RXD0 (pin_C4)
+#define MICROPY_HW_ETH_RMII_RXD1 (pin_C5)
+#define MICROPY_HW_ETH_RMII_TX_EN (pin_B11)
+#define MICROPY_HW_ETH_RMII_TXD0 (pin_B12)
+#define MICROPY_HW_ETH_RMII_TXD1 (pin_B13)
diff --git a/ports/stm32/boards/VCC_GND_F407ZG/mpconfigboard.mk b/ports/stm32/boards/VCC_GND_F407ZG/mpconfigboard.mk
new file mode 100644
index 000000000..c67807867
--- /dev/null
+++ b/ports/stm32/boards/VCC_GND_F407ZG/mpconfigboard.mk
@@ -0,0 +1,10 @@
+MCU_SERIES = f4
+CMSIS_MCU = STM32F407xx
+AF_FILE = boards/stm32f405_af.csv
+LD_FILES = boards/stm32f405.ld boards/common_ifs.ld
+TEXT0_ADDR = 0x08000000
+TEXT1_ADDR = 0x08020000
+
+MICROPY_PY_LWIP = 1
+MICROPY_PY_USSL = 1
+MICROPY_SSL_MBEDTLS = 1
diff --git a/ports/stm32/boards/VCC_GND_F407ZG/pins.csv b/ports/stm32/boards/VCC_GND_F407ZG/pins.csv
new file mode 100644
index 000000000..780523a07
--- /dev/null
+++ b/ports/stm32/boards/VCC_GND_F407ZG/pins.csv
@@ -0,0 +1,157 @@
+P1_1,GND
+P1_2,GND
+P1_3,VBAT
+P1_4,VCC_3V3
+P1_5,VIN_5V
+P1_6,VIN_5V
+P1_7,PF2
+P1_8,PF3
+P1_9,PF4
+P1_10,PF5
+P1_11,PF6
+P1_12,PF7
+P1_13,PF8
+P1_14,PF9
+P1_15,PF10
+P1_16,PC0
+P1_17,PC1
+P1_18,PC2
+P1_19,PC3
+P1_20,PA0
+P1_21,PA1
+P1_22,PA2
+P1_23,PA3
+P1_24,PA4
+P1_25,PA5
+P1_26,PA6
+P1_27,PA7
+P1_28,PC4
+P1_29,PC5
+P1_30,PB0
+P1_31,PB1
+P1_32,PB2
+P1_33,PF11
+P1_34,PF12
+P1_35,PF13
+P1_36,PF14
+P1_37,PF15
+P1_38,PG0
+P1_39,PG1
+P1_40,PE7
+P1_41,PE8
+P1_42,PE9
+P1_43,GND
+P1_44,GND
+P2_1,PG7
+P2_2,PG6
+P2_3,PG5
+P2_4,PG4
+P2_5,PG3
+P2_6,PG2
+P2_7,PD15
+P2_8,PD14
+P2_9,PD13
+P2_10,PD12
+P2_11,PD11
+P2_12,PD10
+P2_13,PD9
+P2_14,PD8
+P2_15,PB15
+P2_16,PB14
+P2_17,PB13
+P2_18,PB12
+P2_19,PB11
+P2_20,PB10
+P2_21,PE15
+P2_22,PE14
+P2_23,PE13
+P2_24,PE12
+P2_25,PE11
+P2_26,PE10
+P3_1,PF1
+P3_2,PF0
+P3_3,PC15
+P3_4,PC14
+P3_5,PC13
+P3_6,PE6
+P3_7,PE5
+P3_8,PE4
+P3_9,PE3
+P3_10,PE2
+P3_11,PE1
+P3_12,PE0
+P4_1,GND
+P4_2,GND
+P4_3,VCC_3V3
+P4_4,VCC_3V3
+P4_5,PB9
+P4_6,PB8
+P4_7,PB7
+P4_8,PB6
+P4_9,PB5
+P4_10,PB4
+P4_11,PB3
+P4_12,PG15
+P4_13,PG14
+P4_14,PG13
+P4_15,PG12
+P4_16,PG11
+P4_17,PG10
+P4_18,PG9
+P4_19,PD7
+P4_20,PD6
+P4_21,PD5
+P4_22,PD4
+P4_23,PD3
+P4_24,PD2
+P4_25,PD1
+P4_26,PD0
+P4_27,PC12
+P4_28,PC11
+P4_29,PC10
+P4_30,PA15
+P4_31,PA14
+P4_32,PA13
+P4_33,PA12
+P4_34,PA11
+P4_35,PA10
+P4_36,PA9
+P4_37,PA8
+P4_38,PC9
+P4_39,PC8
+P4_40,PC7
+P4_41,PC6
+P4_42,PG8
+P4_43,GND
+P4_44,GND
+DAC1,PA4
+DAC2,PA5
+SRAM_CS,PG10
+SF_CS,PB12
+BLUE_LED,PG15
+BOOT1,PB2
+USB_VBUS,PA9
+USB_ID,PA10
+USB_DM,PA11
+USB_DP,PA12
+SWCLK,PA14
+SWDIO,PA13
+OSC32_IN,PC14
+OSC32_OUT,PC15
+SD_D0,PC8
+SD_D1,PC9
+SD_D2,PC10
+SD_D3,PC11
+SD_CK,PC12
+SD_CMD,PD2
+SD,PF10
+SD_SW,PF10
+ETH_MDC,PC1
+ETH_MDIO,PA2
+ETH_RMII_REF_CLK,PA1
+ETH_RMII_CRS_DV,PA7
+ETH_RMII_RXD0,PC4
+ETH_RMII_RXD1,PC5
+ETH_RMII_TX_EN,PB11
+ETH_RMII_TXD0,PB12
+ETH_RMII_TXD1,PB13
diff --git a/ports/stm32/boards/VCC_GND_F407ZG/stm32f4xx_hal_conf.h b/ports/stm32/boards/VCC_GND_F407ZG/stm32f4xx_hal_conf.h
new file mode 100644
index 000000000..fe2069fe1
--- /dev/null
+++ b/ports/stm32/boards/VCC_GND_F407ZG/stm32f4xx_hal_conf.h
@@ -0,0 +1,15 @@
+#ifndef MICROPY_INCLUDED_STM32F4XX_HAL_CONF_H
+#define MICROPY_INCLUDED_STM32F4XX_HAL_CONF_H
+
+#include "boards/stm32f4xx_hal_conf_base.h"
+
+// Oscillator values in Hz
+#define HSE_VALUE (25000000)
+#define LSE_VALUE (32768)
+#define EXTERNAL_CLOCK_VALUE (12288000)
+
+// Oscillator timeouts in ms
+#define HSE_STARTUP_TIMEOUT (100)
+#define LSE_STARTUP_TIMEOUT (5000)
+
+#endif // MICROPY_INCLUDED_STM32F4XX_HAL_CONF_H