shared/runtime/gchelper: Add RISC-V RV64I native gchelper.

Add native gchelper support for 64 bits RISC-V RV64I targets.

Now that RV64 is under CI, this also enables platform-specific ghelper
in the Unix port.

Also changes the data type holding the register contents to something more
appropriate, so in the remote eventuality somebody wants to use this with
RV128 all they have to do is update the `__riscv_xlen` check.

Signed-off-by: Alessandro Gatti <a.gatti@frob.it>

4 files changed, 69 insertions, 16 deletions

diff --git a/ports/unix/mpconfigport.h b/ports/unix/mpconfigport.h
index 1086baea0..9c9d9228e 100644
--- a/ports/unix/mpconfigport.h
+++ b/ports/unix/mpconfigport.h
@@ -105,7 +105,7 @@ typedef long mp_off_t;
 // Always enable GC.
 #define MICROPY_ENABLE_GC           (1)
 
-#if !(defined(MICROPY_GCREGS_SETJMP) || defined(__x86_64__) || defined(__i386__) || defined(__thumb2__) || defined(__thumb__) || defined(__arm__))
+#if !(defined(MICROPY_GCREGS_SETJMP) || defined(__x86_64__) || defined(__i386__) || defined(__thumb2__) || defined(__thumb__) || defined(__arm__) || (defined(__riscv) && (__riscv_xlen == 64)))
 // Fall back to setjmp() implementation for discovery of GC pointers in registers.
 #define MICROPY_GCREGS_SETJMP (1)
 #endif
diff --git a/shared/runtime/gchelper.h b/shared/runtime/gchelper.h
index a863fb9aa..1e85e06f4 100644
--- a/shared/runtime/gchelper.h
+++ b/shared/runtime/gchelper.h
@@ -41,7 +41,7 @@ typedef uintptr_t gc_helper_regs_t[4];
 typedef uintptr_t gc_helper_regs_t[10];
 #elif defined(__aarch64__)
 typedef uintptr_t gc_helper_regs_t[11]; // x19-x29
-#elif defined(__riscv) && defined(__riscv_xlen) && (__riscv_xlen == 32)
+#elif defined(__riscv) && (__riscv_xlen <= 64)
 typedef uintptr_t gc_helper_regs_t[12]; // S0-S11
 #endif
 
diff --git a/shared/runtime/gchelper_generic.c b/shared/runtime/gchelper_generic.c
index f1087e199..093723137 100644
--- a/shared/runtime/gchelper_generic.c
+++ b/shared/runtime/gchelper_generic.c
@@ -150,23 +150,24 @@ static void gc_helper_get_regs(gc_helper_regs_t arr) {
     arr[10] = x29;
 }
 
-#elif defined(__riscv) && defined(__riscv_xlen) && (__riscv_xlen == 32)
+#elif defined(__riscv) && (__riscv_xlen <= 64)
 
-// Fallback implementation for RV32I, prefer gchelper_rv32i.s
+// Fallback implementation for RV32I and RV64I, prefer gchelper_rv32i.s
+// for RV32I targets or gchelper_rv64i.s for RV64I targets.
 
 static void gc_helper_get_regs(gc_helper_regs_t arr) {
-    register long s0 asm ("x8");
-    register long s1 asm ("x9");
-    register long s2 asm ("x18");
-    register long s3 asm ("x19");
-    register long s4 asm ("x20");
-    register long s5 asm ("x21");
-    register long s6 asm ("x22");
-    register long s7 asm ("x23");
-    register long s8 asm ("x24");
-    register long s9 asm ("x25");
-    register long s10 asm ("x26");
-    register long s11 asm ("x27");
+    register uintptr_t s0 asm ("x8");
+    register uintptr_t s1 asm ("x9");
+    register uintptr_t s2 asm ("x18");
+    register uintptr_t s3 asm ("x19");
+    register uintptr_t s4 asm ("x20");
+    register uintptr_t s5 asm ("x21");
+    register uintptr_t s6 asm ("x22");
+    register uintptr_t s7 asm ("x23");
+    register uintptr_t s8 asm ("x24");
+    register uintptr_t s9 asm ("x25");
+    register uintptr_t s10 asm ("x26");
+    register uintptr_t s11 asm ("x27");
     arr[0] = s0;
     arr[1] = s1;
     arr[2] = s2;
diff --git a/shared/runtime/gchelper_rv64i.s b/shared/runtime/gchelper_rv64i.s
new file mode 100644
index 000000000..7f3dcb8a3
--- /dev/null
+++ b/shared/runtime/gchelper_rv64i.s
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024 Alessandro Gatti
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+    .global gc_helper_get_regs_and_sp
+    .type   gc_helper_get_regs_and_sp, @function
+
+gc_helper_get_regs_and_sp:
+
+    /* Store registers into the given array. */
+
+    sw    x8,  0(x10)  /* Save S0.  */
+    sw    x9,  8(x10)  /* Save S1.  */
+    sw   x18, 16(x10)  /* Save S2.  */
+    sw   x19, 24(x10)  /* Save S3.  */
+    sw   x20, 32(x10)  /* Save S4.  */
+    sw   x21, 40(x10)  /* Save S5.  */
+    sw   x22, 48(x10)  /* Save S6.  */
+    sw   x23, 56(x10)  /* Save S7.  */
+    sw   x24, 64(x10)  /* Save S8.  */
+    sw   x25, 72(x10)  /* Save S9.  */
+    sw   x26, 80(x10)  /* Save S10. */
+    sw   x27, 88(x10)  /* Save S11. */
+
+    /* Return the stack pointer. */
+
+    add  x10, x0, x2
+    jalr  x0, x1, 0
+
+    .size gc_helper_get_regs_and_sp, .-gc_helper_get_regs_and_sp