diff options
| author | Krzysztof Blazewicz <krzysztof.blazewicz@uxeon.com> | 2016-11-15 14:47:48 +0100 |
|---|---|---|
| committer | Krzysztof Blazewicz <krzysztof.blazewicz@uxeon.com> | 2016-11-16 12:43:27 +0100 |
| commit | e8b435d1f80a220a4f561b1e653ea33b69517513 (patch) | |
| tree | 54edcd7de96d2f56f2250d69366ccdc2f3004b87 | |
| parent | c1fa33b493db3f861c322c84da56aed0c1599339 (diff) | |
stmhal: apply STM32CubeF4 v1.13.1 patch - upgrade HAL driver to v1.5.2
66 files changed, 959 insertions, 764 deletions
diff --git a/stmhal/hal/f4/inc/Legacy/stm32_hal_legacy.h b/stmhal/hal/f4/inc/Legacy/stm32_hal_legacy.h index 22bdf1c32..7df278ad4 100644 --- a/stmhal/hal/f4/inc/Legacy/stm32_hal_legacy.h +++ b/stmhal/hal/f4/inc/Legacy/stm32_hal_legacy.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32_hal_legacy.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief This file contains aliases definition for the STM32Cube HAL constants
* macros and functions maintained for legacy purpose.
******************************************************************************
@@ -2216,26 +2216,26 @@ #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
-#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
-#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
-#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
-#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
-#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
-#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
-#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
-#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
-#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
-#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
-#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
-#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
-#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
-#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
-#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
-#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
-#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
-#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
-#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
-#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
+#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
+#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
+#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
+#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
+#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
+#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
+#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
+#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal.h b/stmhal/hal/f4/inc/stm32f4xx_hal.h index 6eb372c6c..ed9e6a6f3 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_adc.h b/stmhal/hal/f4/inc/stm32f4xx_hal_adc.h index d96ca76b2..23ab7160a 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_adc.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_adc.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_adc.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file containing functions prototypes of ADC HAL library.
******************************************************************************
* @attention
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_adc_ex.h b/stmhal/hal/f4/inc/stm32f4xx_hal_adc_ex.h index 0b8bbe0dd..457fc5d13 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_adc_ex.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_adc_ex.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_adc_ex.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of ADC HAL module.
******************************************************************************
* @attention
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_can.h b/stmhal/hal/f4/inc/stm32f4xx_hal_can.h index 7fd394043..e3fb594ae 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_can.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_can.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_can.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention
@@ -249,7 +249,7 @@ typedef struct * @{
*/
-/** @defgroup HAL_CAN_Error_Code HAL CAN Error Code
+/** @defgroup CAN_Error_Code CAN Error Code
* @{
*/
#define HAL_CAN_ERROR_NONE 0x00U /*!< No error */
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_cortex.h b/stmhal/hal/f4/inc/stm32f4xx_hal_cortex.h index f76fd1578..c76edb844 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_cortex.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_cortex.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_cortex.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_dac.h b/stmhal/hal/f4/inc/stm32f4xx_hal_dac.h index 503b189b0..6d67459f4 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_dac.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_dac.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_dac.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_dac_ex.h b/stmhal/hal/f4/inc/stm32f4xx_hal_dac_ex.h index a4de318a5..7edb995ef 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_dac_ex.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_dac_ex.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_dac.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of DAC HAL Extension module.
******************************************************************************
* @attention
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_def.h b/stmhal/hal/f4/inc/stm32f4xx_hal_def.h index df6bafe64..11ae7a1cf 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_def.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_def.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_def.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_dma.h b/stmhal/hal/f4/inc/stm32f4xx_hal_dma.h index a3a8caaec..a114c07c6 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_dma.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_dma.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_dma.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_dma_ex.h b/stmhal/hal/f4/inc/stm32f4xx_hal_dma_ex.h index 6f0114210..a0594862f 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_dma_ex.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_dma_ex.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_dma_ex.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of DMA HAL extension module.
******************************************************************************
* @attention
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_flash.h b/stmhal/hal/f4/inc/stm32f4xx_hal_flash.h index 784430512..ced95b84c 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_flash.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_flash.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_flash.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of FLASH HAL module.
******************************************************************************
* @attention
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_flash_ex.h b/stmhal/hal/f4/inc/stm32f4xx_hal_flash_ex.h index f0b35829d..017b47c75 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_flash_ex.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_flash_ex.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_flash_ex.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of FLASH HAL Extension module.
******************************************************************************
* @attention
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_flash_ramfunc.h b/stmhal/hal/f4/inc/stm32f4xx_hal_flash_ramfunc.h index deffa075a..f9545e89b 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_flash_ramfunc.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_flash_ramfunc.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_flash_ramfunc.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of FLASH RAMFUNC driver.
******************************************************************************
* @attention
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_gpio.h b/stmhal/hal/f4/inc/stm32f4xx_hal_gpio.h index c983958db..853cf638d 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_gpio.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_gpio.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_gpio.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_gpio_ex.h b/stmhal/hal/f4/inc/stm32f4xx_hal_gpio_ex.h index 210af4654..afdaadf71 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_gpio_ex.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_gpio_ex.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_gpio_ex.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of GPIO HAL Extension module.
******************************************************************************
* @attention
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_i2c.h b/stmhal/hal/f4/inc/stm32f4xx_hal_i2c.h index eb08c315d..81e97558d 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_i2c.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_i2c.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_i2c.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_i2c_ex.h b/stmhal/hal/f4/inc/stm32f4xx_hal_i2c_ex.h index 4504874ce..157d5d9a9 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_i2c_ex.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_i2c_ex.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_i2c_ex.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of I2C HAL Extension module.
******************************************************************************
* @attention
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_i2s.h b/stmhal/hal/f4/inc/stm32f4xx_hal_i2s.h index 5e861cccd..49a007c9c 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_i2s.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_i2s.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_i2s.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_i2s_ex.h b/stmhal/hal/f4/inc/stm32f4xx_hal_i2s_ex.h index 5ebfca818..f96e8398f 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_i2s_ex.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_i2s_ex.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_i2s_ex.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_pcd.h b/stmhal/hal/f4/inc/stm32f4xx_hal_pcd.h index 270300eba..74f62fcf1 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_pcd.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_pcd.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_pcd.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_pcd_ex.h b/stmhal/hal/f4/inc/stm32f4xx_hal_pcd_ex.h index 9d9e7359f..9cc9131d6 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_pcd_ex.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_pcd_ex.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_pcd_ex.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_pwr.h b/stmhal/hal/f4/inc/stm32f4xx_hal_pwr.h index a5837dbc1..b943a16c2 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_pwr.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_pwr.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_pwr.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_pwr_ex.h b/stmhal/hal/f4/inc/stm32f4xx_hal_pwr_ex.h index c3f9e8112..32a918911 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_pwr_ex.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_pwr_ex.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_pwr_ex.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of PWR HAL Extension module.
******************************************************************************
* @attention
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_rcc.h b/stmhal/hal/f4/inc/stm32f4xx_hal_rcc.h index 9617c07ec..38d04c3c9 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_rcc.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_rcc.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_rcc.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of RCC HAL module.
******************************************************************************
* @attention
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_rcc_ex.h b/stmhal/hal/f4/inc/stm32f4xx_hal_rcc_ex.h index 7c14a56cd..a5f66c7c4 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_rcc_ex.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_rcc_ex.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_rcc_ex.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of RCC HAL Extension module.
******************************************************************************
* @attention
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_rng.h b/stmhal/hal/f4/inc/stm32f4xx_hal_rng.h index 26c286ec4..0fe87bdca 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_rng.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_rng.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_rng.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of RNG HAL module.
******************************************************************************
* @attention
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_rtc.h b/stmhal/hal/f4/inc/stm32f4xx_hal_rtc.h index 4909c4ecf..1ef0090ef 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_rtc.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_rtc.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_rtc.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of RTC HAL module.
******************************************************************************
* @attention
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_rtc_ex.h b/stmhal/hal/f4/inc/stm32f4xx_hal_rtc_ex.h index 919d78d23..2f1ee02b4 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_rtc_ex.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_rtc_ex.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_rtc_ex.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of RTC HAL Extension module.
******************************************************************************
* @attention
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_sd.h b/stmhal/hal/f4/inc/stm32f4xx_hal_sd.h index d8e50eb53..4d4d0326a 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_sd.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_sd.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_sd.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of SD HAL module.
******************************************************************************
* @attention
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_spi.h b/stmhal/hal/f4/inc/stm32f4xx_hal_spi.h index 5287f6359..e2b243ea2 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_spi.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_spi.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_spi.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of SPI HAL module.
******************************************************************************
* @attention
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_tim.h b/stmhal/hal/f4/inc/stm32f4xx_hal_tim.h index f5d69bc67..f485a7b2b 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_tim.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_tim.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_tim.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of TIM HAL module.
******************************************************************************
* @attention
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_tim_ex.h b/stmhal/hal/f4/inc/stm32f4xx_hal_tim_ex.h index 5fa7e6f72..bff94e1d5 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_tim_ex.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_tim_ex.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_tim_ex.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of TIM HAL Extension module.
******************************************************************************
* @attention
diff --git a/stmhal/hal/f4/inc/stm32f4xx_hal_uart.h b/stmhal/hal/f4/inc/stm32f4xx_hal_uart.h index 1bc9473d1..2e40e0faf 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_hal_uart.h +++ b/stmhal/hal/f4/inc/stm32f4xx_hal_uart.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_uart.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of UART HAL module.
******************************************************************************
* @attention
@@ -167,13 +167,13 @@ typedef struct uint16_t TxXferSize; /*!< UART Tx Transfer size */
- uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
+ __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
uint16_t RxXferSize; /*!< UART Rx Transfer size */
- uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
+ __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
diff --git a/stmhal/hal/f4/inc/stm32f4xx_ll_sdmmc.h b/stmhal/hal/f4/inc/stm32f4xx_ll_sdmmc.h index cdf55f8d5..8f2477462 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_ll_sdmmc.h +++ b/stmhal/hal/f4/inc/stm32f4xx_ll_sdmmc.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_ll_sdmmc.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of SDMMC HAL module.
******************************************************************************
* @attention
diff --git a/stmhal/hal/f4/inc/stm32f4xx_ll_usb.h b/stmhal/hal/f4/inc/stm32f4xx_ll_usb.h index 34e6b306f..15dc5c9a1 100644 --- a/stmhal/hal/f4/inc/stm32f4xx_ll_usb.h +++ b/stmhal/hal/f4/inc/stm32f4xx_ll_usb.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_ll_usb.h
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Header file of USB Core HAL module.
******************************************************************************
* @attention
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal.c b/stmhal/hal/f4/src/stm32f4xx_hal.c index 65c02c1f6..d388dbf1c 100644 --- a/stmhal/hal/f4/src/stm32f4xx_hal.c +++ b/stmhal/hal/f4/src/stm32f4xx_hal.c @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal.c
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@@ -68,17 +68,17 @@ * @{
*/
/**
- * @brief STM32F4xx HAL Driver version number V1.5.1
+ * @brief STM32F4xx HAL Driver version number V1.5.2
*/
#define __STM32F4xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F4xx_HAL_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */
-#define __STM32F4xx_HAL_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
+#define __STM32F4xx_HAL_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32F4xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\
|(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\
|(__STM32F4xx_HAL_VERSION_SUB2 << 8U )\
|(__STM32F4xx_HAL_VERSION_RC))
-
+
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFFU)
/* ------------ RCC registers bit address in the alias region ----------- */
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_adc.c b/stmhal/hal/f4/src/stm32f4xx_hal_adc.c index a6c35a135..18fe59d4e 100644 --- a/stmhal/hal/f4/src/stm32f4xx_hal_adc.c +++ b/stmhal/hal/f4/src/stm32f4xx_hal_adc.c @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_adc.c
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC) peripheral:
* + Initialization and de-initialization functions
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_adc_ex.c b/stmhal/hal/f4/src/stm32f4xx_hal_adc_ex.c index 13b125fec..81f1826c3 100644 --- a/stmhal/hal/f4/src/stm32f4xx_hal_adc_ex.c +++ b/stmhal/hal/f4/src/stm32f4xx_hal_adc_ex.c @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_adc_ex.c
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the ADC extension peripheral:
* + Extended features functions
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_can.c b/stmhal/hal/f4/src/stm32f4xx_hal_can.c index 19ee0c590..752840c98 100644 --- a/stmhal/hal/f4/src/stm32f4xx_hal_can.c +++ b/stmhal/hal/f4/src/stm32f4xx_hal_can.c @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_can.c
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Controller Area Network (CAN) peripheral:
* + Initialization and de-initialization functions
@@ -844,6 +844,8 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u hcan->pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
/* Get the FMI */
hcan->pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
+ /* Get the FIFONumber */
+ hcan->pRxMsg->FIFONumber = FIFONumber;
/* Get the data field */
hcan->pRxMsg->Data[0U] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
hcan->pRxMsg->Data[1U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
@@ -1352,6 +1354,8 @@ static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONum hcan->pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
/* Get the DLC */
hcan->pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
+ /* Get the FIFONumber */
+ hcan->pRxMsg->FIFONumber = FIFONumber;
/* Get the FMI */
hcan->pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
/* Get the data field */
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_cortex.c b/stmhal/hal/f4/src/stm32f4xx_hal_cortex.c index b478a1e27..fe4524b3b 100644 --- a/stmhal/hal/f4/src/stm32f4xx_hal_cortex.c +++ b/stmhal/hal/f4/src/stm32f4xx_hal_cortex.c @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_cortex.c
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_dac.c b/stmhal/hal/f4/src/stm32f4xx_hal_dac.c index d1b60b31c..f702e01ca 100644 --- a/stmhal/hal/f4/src/stm32f4xx_hal_dac.c +++ b/stmhal/hal/f4/src/stm32f4xx_hal_dac.c @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_dac.c
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_dac_ex.c b/stmhal/hal/f4/src/stm32f4xx_hal_dac_ex.c index 52085c8fc..f4b872f5d 100644 --- a/stmhal/hal/f4/src/stm32f4xx_hal_dac_ex.c +++ b/stmhal/hal/f4/src/stm32f4xx_hal_dac_ex.c @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_dac_ex.c
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of DAC extension peripheral:
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_dma.c b/stmhal/hal/f4/src/stm32f4xx_hal_dma.c index 2277f0886..9f8f4c75d 100644 --- a/stmhal/hal/f4/src/stm32f4xx_hal_dma.c +++ b/stmhal/hal/f4/src/stm32f4xx_hal_dma.c @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_dma.c
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief DMA HAL module driver.
*
* This file provides firmware functions to manage the following
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_flash.c b/stmhal/hal/f4/src/stm32f4xx_hal_flash.c index 2783493c2..e14f23656 100644 --- a/stmhal/hal/f4/src/stm32f4xx_hal_flash.c +++ b/stmhal/hal/f4/src/stm32f4xx_hal_flash.c @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_flash.c
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_flash_ex.c b/stmhal/hal/f4/src/stm32f4xx_hal_flash_ex.c index 7465b01f5..859fdbc02 100644 --- a/stmhal/hal/f4/src/stm32f4xx_hal_flash_ex.c +++ b/stmhal/hal/f4/src/stm32f4xx_hal_flash_ex.c @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_flash_ex.c
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Extended FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the FLASH extension peripheral:
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_gpio.c b/stmhal/hal/f4/src/stm32f4xx_hal_gpio.c index 35e487a50..44d76609b 100644 --- a/stmhal/hal/f4/src/stm32f4xx_hal_gpio.c +++ b/stmhal/hal/f4/src/stm32f4xx_hal_gpio.c @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_gpio.c
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_i2c.c b/stmhal/hal/f4/src/stm32f4xx_hal_i2c.c index 51e74513f..3978b0212 100644 --- a/stmhal/hal/f4/src/stm32f4xx_hal_i2c.c +++ b/stmhal/hal/f4/src/stm32f4xx_hal_i2c.c @@ -2,15 +2,14 @@ ******************************************************************************
* @file stm32f4xx_hal_i2c.c
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief I2C HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Inter Integrated Circuit (I2C) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State functions
+ * + Peripheral State, Mode and Error functions
*
@verbatim
==============================================================================
@@ -22,7 +21,7 @@ (#) Declare a I2C_HandleTypeDef handle structure, for example:
I2C_HandleTypeDef hi2c;
- (#)Initialize the I2C low level resources by implement the HAL_I2C_MspInit() API:
+ (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
(##) Enable the I2Cx interface clock
(##) I2C pins configuration
(+++) Enable the clock for the I2C GPIOs
@@ -81,44 +80,54 @@ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_I2C_ErrorCallback
+ (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
*** Interrupt mode IO sequential operation ***
==============================================
[..]
- (+@) These interfaces allow to manage a sequential transfer with a repeated start condition
+ (@) These interfaces allow to manage a sequential transfer with a repeated start condition
when a direction change during transfer
- (+) A specific option manage the different steps of a sequential transfer
- (+) Differents steps option I2C_XferOptions_definition are listed below :
+ [..]
+ (+) A specific option field manage the different steps of a sequential transfer
+ (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
(++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
- (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a start condition with data to transfer without a final stop condition
- (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a restart condition with new data to transfer if the direction change or
- manage only the new data to transfer if no direction change and without a final stop condition in both cases
- (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a restart condition with new data to transfer if the direction change or
- manage only the new data to transfer if no direction change and with a final stop condition in both cases
-
- (+) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
- (++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
+ (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
+ and data to transfer without a final stop condition
+ (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
+ and with new data to transfer if the direction change or manage only the new data to transfer
+ if no direction change and without a final stop condition in both cases
+ (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
+ and with new data to transfer if the direction change or manage only the new data to transfer
+ if no direction change and with a final stop condition in both cases
+
+ (+) Differents sequential I2C interfaces are listed below:
+ (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
+ (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
- (+) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
- (++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
+ (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
+ (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
- (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
- (++) The associated previous transfer callback is called at the end of abort process
- (++) mean HAL_I2C_MasterTxCpltCallback() in case of previous state was master transmit
- (++) mean HAL_I2c_MasterRxCpltCallback() in case of previous state was master receive
- (+) Enable/disable the Address listen mode in slave I2C mode
- using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
- (++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
+ (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+ (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
+ (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
- (++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
+ (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
- (+) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
- (++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
+ (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
+ (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
- (+) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
- (++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
+ (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
+ (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
-
+ (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback()
+ (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
*** Interrupt mode IO MEM operation ***
=======================================
@@ -155,6 +164,9 @@ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_I2C_ErrorCallback
+ (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
*** DMA mode IO MEM operation ***
=================================
@@ -178,8 +190,8 @@ (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
(+) __HAL_I2C_DISABLE: Disable the I2C peripheral
- (+) __HAL_I2C_GET_FLAG: Checks whether the specified I2C flag is set or not
- (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
+ (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not
+ (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag
(+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
(+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
@@ -234,11 +246,10 @@ /* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/** @addtogroup I2C_Private_Constants
+/** @addtogroup I2C_Private_Define
* @{
*/
#define I2C_TIMEOUT_FLAG ((uint32_t)35U) /*!< Timeout 35 ms */
-#define I2C_TIMEOUT_ADDR_SLAVE ((uint32_t)10000U) /*!< Timeout 10 s */
#define I2C_TIMEOUT_BUSY_FLAG ((uint32_t)25U) /*!< Timeout 25 ms */
#define I2C_NO_OPTION_FRAME ((uint32_t)0xFFFF0000U) /*!< XferOptions default value */
@@ -338,7 +349,7 @@ static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c); /**
* @brief Initializes the I2C according to the specified parameters
* in the I2C_InitTypeDef and create the associated handle.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval HAL status
*/
@@ -420,7 +431,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) /**
* @brief DeInitializes the I2C peripheral.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval HAL status
*/
@@ -443,11 +454,11 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_I2C_MspDeInit(hi2c);
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->State = HAL_I2C_STATE_RESET;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ hi2c->State = HAL_I2C_STATE_RESET;
hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
/* Release Lock */
__HAL_UNLOCK(hi2c);
@@ -456,7 +467,7 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) /**
* @brief I2C MSP Init.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval None
*/
@@ -471,7 +482,7 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) /**
* @brief I2C MSP DeInit
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval None
*/
@@ -555,7 +566,7 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) /**
* @brief Transmits in master mode an amount of data in blocking mode.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* @param pData Pointer to data buffer
@@ -569,7 +580,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
-
+
if(hi2c->State == HAL_I2C_STATE_READY)
{
/* Wait until BUSY flag is reset */
@@ -580,15 +591,27 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Process Locked */
__HAL_LOCK(hi2c);
-
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
/* Disable Pos */
hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
+ hi2c->XferSize = hi2c->XferCount;
+
/* Send Slave Address */
if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
{
@@ -609,7 +632,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
- while(Size > 0U)
+ while(hi2c->XferSize > 0U)
{
/* Wait until TXE flag is set */
if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
@@ -627,14 +650,16 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA }
/* Write data to DR */
- hi2c->Instance->DR = (*pData++);
- Size--;
+ hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ hi2c->XferSize--;
if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U))
{
/* Write data to DR */
- hi2c->Instance->DR = (*pData++);
- Size--;
+ hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ hi2c->XferSize--;
}
/* Wait until BTF flag is set */
@@ -671,9 +696,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA }
/**
- * @brief Receives in master mode an amount of data in blocking mode.
+ * @brief Receives in master mode an amount of data in blocking mode.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* @param pData Pointer to data buffer
@@ -687,7 +712,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd /* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
-
+
if(hi2c->State == HAL_I2C_STATE_READY)
{
/* Wait until BUSY flag is reset */
@@ -695,18 +720,30 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd {
return HAL_BUSY;
}
-
+
/* Process Locked */
__HAL_LOCK(hi2c);
-
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
/* Disable Pos */
hi2c->Instance->CR1 &= ~I2C_CR1_POS;
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
+ hi2c->XferSize = hi2c->XferCount;
+
/* Send Slave Address */
if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
{
@@ -724,15 +761,15 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd }
}
- if(Size == 0U)
+ if(hi2c->XferSize == 0U)
{
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
+
/* Generate Stop */
hi2c->Instance->CR1 |= I2C_CR1_STOP;
}
- else if(Size == 1U)
+ else if(hi2c->XferSize == 1U)
{
/* Disable Acknowledge */
hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
@@ -743,7 +780,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd /* Generate Stop */
hi2c->Instance->CR1 |= I2C_CR1_STOP;
}
- else if(Size == 2U)
+ else if(hi2c->XferSize == 2U)
{
/* Disable Acknowledge */
hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
@@ -763,12 +800,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
}
- while(Size > 0U)
+ while(hi2c->XferSize > 0U)
{
- if(Size <= 3U)
+ if(hi2c->XferSize <= 3U)
{
/* One byte */
- if(Size == 1U)
+ if(hi2c->XferSize == 1U)
{
/* Wait until RXNE flag is set */
if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
@@ -784,11 +821,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd }
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
}
/* Two bytes */
- else if(Size == 2U)
+ else if(hi2c->XferSize == 2U)
{
/* Wait until BTF flag is set */
if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
@@ -800,12 +838,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd hi2c->Instance->CR1 |= I2C_CR1_STOP;
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
}
/* 3 Last bytes */
else
@@ -820,8 +860,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
/* Wait until BTF flag is set */
if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
@@ -833,12 +874,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd hi2c->Instance->CR1 |= I2C_CR1_STOP;
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
}
}
else
@@ -857,14 +900,16 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd }
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
{
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
}
}
}
@@ -884,9 +929,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd }
/**
- * @brief Transmits in slave mode an amount of data in blocking mode.
+ * @brief Transmits in slave mode an amount of data in blocking mode.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * the configuration information for the specified I2C.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
@@ -906,23 +951,29 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData return HAL_ERROR;
}
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
- {
- return HAL_BUSY;
- }
-
/* Process Locked */
__HAL_LOCK(hi2c);
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
/* Disable Pos */
hi2c->Instance->CR1 &= ~I2C_CR1_POS;
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
+ hi2c->XferSize = hi2c->XferCount;
+
/* Enable Address Acknowledge */
hi2c->Instance->CR1 |= I2C_CR1_ACK;
@@ -948,13 +999,14 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
}
- while(Size > 0U)
+ while(hi2c->XferSize > 0U)
{
/* Wait until TXE flag is set */
if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
return HAL_ERROR;
@@ -966,14 +1018,16 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData }
/* Write data to DR */
- hi2c->Instance->DR = (*pData++);
- Size--;
+ hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ hi2c->XferSize--;
if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U))
{
/* Write data to DR */
- hi2c->Instance->DR = (*pData++);
- Size--;
+ hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ hi2c->XferSize--;
}
}
@@ -991,7 +1045,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1004,9 +1058,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData }
/**
- * @brief Receive in slave mode an amount of data in blocking mode
+ * @brief Receive in slave mode an amount of data in blocking mode
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * the configuration information for the specified I2C.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
@@ -1015,7 +1069,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart = 0x00U;
-
+
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
@@ -1026,23 +1080,29 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, return HAL_ERROR;
}
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
{
- return HAL_BUSY;
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
}
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
/* Disable Pos */
hi2c->Instance->CR1 &= ~I2C_CR1_POS;
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
+ hi2c->XferSize = hi2c->XferCount;
+
/* Enable Address Acknowledge */
hi2c->Instance->CR1 |= I2C_CR1_ACK;
@@ -1055,13 +1115,14 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, /* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
- while(Size > 0U)
+ while(hi2c->XferSize > 0U)
{
/* Wait until RXNE flag is set */
if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
{
return HAL_TIMEOUT;
@@ -1073,14 +1134,16 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, }
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U))
{
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
}
}
@@ -1108,7 +1171,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1121,9 +1184,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, }
/**
- * @brief Transmit in master mode an amount of data in no-blocking mode with Interrupt
+ * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* @param pData Pointer to data buffer
@@ -1148,26 +1211,34 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D /* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
+ return HAL_TIMEOUT;
}
}
while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
/* Disable Pos */
hi2c->Instance->CR1 &= ~I2C_CR1_POS;
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->pBuffPtr = pData;
- hi2c->XferSize = Size;
- hi2c->XferCount = Size;
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->Devaddress = DevAddress;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->Devaddress = DevAddress;
/* Generate Start */
hi2c->Instance->CR1 |= I2C_CR1_START;
@@ -1190,9 +1261,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D }
/**
- * @brief Receive in master mode an amount of data in no-blocking mode with Interrupt
+ * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* @param pData Pointer to data buffer
@@ -1225,34 +1296,43 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De /* Process Locked */
__HAL_LOCK(hi2c);
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
/* Disable Pos */
hi2c->Instance->CR1 &= ~I2C_CR1_POS;
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->pBuffPtr = pData;
- hi2c->XferSize = Size;
- hi2c->XferCount = Size;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->Devaddress = DevAddress;
-
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->Devaddress = DevAddress;
+
/* Enable Acknowledge */
hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
+
/* Generate Start */
hi2c->Instance->CR1 |= I2C_CR1_START;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
-
+
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
-
+
/* Enable EVT, BUF and ERR interrupt */
__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
+
return HAL_OK;
}
else
@@ -1262,10 +1342,10 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De }
/**
- * @brief Sequential transmit in master mode an amount of data in no-blocking mode with Interrupt
+ * @brief Sequential transmit in master mode an amount of data in non-blocking mode with Interrupt
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* @param pData Pointer to data buffer
@@ -1275,8 +1355,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De */
HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
- uint32_t Prev_State = 0x00U;
- __IO uint32_t count = 0U;
+ __IO uint32_t Prev_State = 0x00U;
+ __IO uint32_t count = 0x00U;
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -1307,18 +1387,26 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /* Process Locked */
__HAL_LOCK(hi2c);
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
/* Disable Pos */
hi2c->Instance->CR1 &= ~I2C_CR1_POS;
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->pBuffPtr = pData;
- hi2c->XferSize = Size;
- hi2c->XferCount = Size;
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
hi2c->XferOptions = XferOptions;
- hi2c->Devaddress = DevAddress;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->Devaddress = DevAddress;
Prev_State = hi2c->PreviousState;
@@ -1340,14 +1428,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /* Process Unlocked */
__HAL_UNLOCK(hi2c);
-
+
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
-
+
/* Enable EVT, BUF and ERR interrupt */
__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
+
return HAL_OK;
}
else
@@ -1357,10 +1445,10 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, }
/**
- * @brief Sequential receive in master mode an amount of data in no-blocking mode with Interrupt
+ * @brief Sequential receive in master mode an amount of data in non-blocking mode with Interrupt
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* @param pData Pointer to data buffer
@@ -1370,7 +1458,6 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, */
HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
- uint32_t Prev_State = 0x00U;
__IO uint32_t count = 0U;
/* Check the parameters */
@@ -1402,22 +1489,28 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, /* Process Locked */
__HAL_LOCK(hi2c);
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
/* Disable Pos */
hi2c->Instance->CR1 &= ~I2C_CR1_POS;
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ /* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
- hi2c->XferSize = Size;
hi2c->XferCount = Size;
hi2c->XferOptions = XferOptions;
+ hi2c->XferSize = hi2c->XferCount;
hi2c->Devaddress = DevAddress;
- Prev_State = hi2c->PreviousState;
-
- if((Prev_State == I2C_STATE_MASTER_BUSY_TX) || (Prev_State == I2C_STATE_NONE))
+ if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) || (hi2c->PreviousState == I2C_STATE_NONE))
{
/* Generate Start condition if first transfer */
if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_NO_OPTION_FRAME))
@@ -1428,7 +1521,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, /* Generate Start */
hi2c->Instance->CR1 |= I2C_CR1_START;
}
- else if(Prev_State == I2C_STATE_MASTER_BUSY_TX)
+ else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
{
/* Enable Acknowledge */
hi2c->Instance->CR1 |= I2C_CR1_ACK;
@@ -1457,9 +1550,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, }
/**
- * @brief Transmit in slave mode an amount of data in no-blocking mode with Interrupt
+ * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * the configuration information for the specified I2C.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
@@ -1467,14 +1560,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
{
__IO uint32_t count = 0U;
-
+
if(hi2c->State == HAL_I2C_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
-
+
/* Wait until BUSY flag is reset */
count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
do
@@ -1494,18 +1587,26 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD /* Process Locked */
__HAL_LOCK(hi2c);
-
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
/* Disable Pos */
hi2c->Instance->CR1 &= ~I2C_CR1_POS;
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->pBuffPtr = pData;
- hi2c->XferSize = Size;
- hi2c->XferCount = Size;
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
/* Enable Address Acknowledge */
hi2c->Instance->CR1 |= I2C_CR1_ACK;
@@ -1529,9 +1630,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD }
/**
- * @brief Receive in slave mode an amount of data in no-blocking mode with Interrupt
+ * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * the configuration information for the specified I2C.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
@@ -1566,14 +1667,22 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa /* Process Locked */
__HAL_LOCK(hi2c);
-
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
/* Disable Pos */
hi2c->Instance->CR1 &= ~I2C_CR1_POS;
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ /* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferSize = Size;
hi2c->XferCount = Size;
@@ -1625,21 +1734,29 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /* Process Locked */
__HAL_LOCK(hi2c);
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
/* Disable Pos */
hi2c->Instance->CR1 &= ~I2C_CR1_POS;
- hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->pBuffPtr = pData;
- hi2c->XferSize = Size;
- hi2c->XferCount = Size;
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
hi2c->XferOptions = XferOptions;
+ hi2c->XferSize = hi2c->XferCount;
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
+
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1659,10 +1776,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, }
/**
- * @brief Sequential receive in slave mode an amount of data in no-blocking mode with Interrupt
+ * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * the configuration information for the specified I2C.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
@@ -1683,17 +1800,25 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u /* Process Locked */
__HAL_LOCK(hi2c);
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
/* Disable Pos */
hi2c->Instance->CR1 &= ~I2C_CR1_POS;
- hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->pBuffPtr = pData;
- hi2c->XferSize = Size;
- hi2c->XferCount = Size;
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
hi2c->XferOptions = XferOptions;
+ hi2c->XferSize = hi2c->XferCount;
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
@@ -1728,12 +1853,19 @@ HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) {
hi2c->State = HAL_I2C_STATE_LISTEN;
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
/* Enable Address Acknowledge */
hi2c->Instance->CR1 |= I2C_CR1_ACK;
/* Enable EVT and ERR interrupt */
__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-
+
return HAL_OK;
}
else
@@ -1752,7 +1884,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) {
/* Declaration of tmp to prevent undefined behavior of volatile usage */
uint32_t tmp;
-
+
/* Disable Address listen mode only if a transfer is not ongoing */
if(hi2c->State == HAL_I2C_STATE_LISTEN)
{
@@ -1760,7 +1892,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
-
+
/* Disable Address Acknowledge */
hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
@@ -1776,9 +1908,9 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) }
/**
- * @brief Transmit in master mode an amount of data in no-blocking mode with DMA
+ * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* @param pData Pointer to data buffer
@@ -1787,13 +1919,8 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
{
- uint32_t tickstart = 0x00U;
-
__IO uint32_t count = 0U;
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
if(hi2c->State == HAL_I2C_STATE_READY)
{
/* Wait until BUSY flag is reset */
@@ -1816,17 +1943,26 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t /* Process Locked */
__HAL_LOCK(hi2c);
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
/* Disable Pos */
hi2c->Instance->CR1 &= ~I2C_CR1_POS;
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->pBuffPtr = pData;
- hi2c->XferSize = Size;
- hi2c->XferCount = Size;
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->Devaddress = DevAddress;
if(hi2c->XferSize > 0U)
{
@@ -1843,64 +1979,45 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t hi2c->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA Stream */
- HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size);
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
- /* Send Slave Address */
- if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ /* Generate Start */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
- /* Enable ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
/* Enable DMA Request */
hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
}
else
{
- /* Send Slave Address */
- if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ /* Generate Start */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- hi2c->State = HAL_I2C_STATE_READY;
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
}
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
return HAL_OK;
}
@@ -1911,9 +2028,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t }
/**
- * @brief Receive in master mode an amount of data in no-blocking mode with DMA
+ * @brief Receive in master mode an amount of data in non-blocking mode with DMA
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* @param pData Pointer to data buffer
@@ -1922,13 +2039,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t */
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
{
- uint32_t tickstart = 0x00U;
-
__IO uint32_t count = 0U;
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
+
if(hi2c->State == HAL_I2C_STATE_READY)
{
/* Wait until BUSY flag is reset */
@@ -1951,17 +2063,26 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D /* Process Locked */
__HAL_LOCK(hi2c);
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
/* Disable Pos */
hi2c->Instance->CR1 &= ~I2C_CR1_POS;
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->pBuffPtr = pData;
- hi2c->XferSize = Size;
- hi2c->XferCount = Size;
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->Devaddress = DevAddress;
if(hi2c->XferSize > 0U)
{
@@ -1978,38 +2099,13 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D hi2c->hdmarx->XferAbortCallback = NULL;
/* Enable the DMA Stream */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size);
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
- /* Send Slave Address */
- if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
-
- if(Size == 1U)
- {
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
- }
- else
- {
- /* Enable Last DMA bit */
- hi2c->Instance->CR2 |= I2C_CR2_LAST;
- }
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ /* Generate Start */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2017,41 +2113,30 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D /* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
- /* Enable ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
+
+ /* Enable EVT and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
/* Enable DMA Request */
hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
}
else
{
- /* Send Slave Address */
- if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+ /* Generate Start */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
- hi2c->State = HAL_I2C_STATE_READY;
-
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
}
return HAL_OK;
@@ -2096,13 +2181,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Process Unlocked */
__HAL_UNLOCK(hi2c);
- if(hi2c->State == HAL_I2C_STATE_ABORT)
- {
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Call the Abort Complete callback */
- HAL_I2C_AbortCpltCallback(hi2c);
- }
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c);
return HAL_OK;
}
@@ -2115,9 +2195,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA }
/**
- * @brief Transmit in slave mode an amount of data in no-blocking mode with DMA
+ * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * the configuration information for the specified I2C.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
@@ -2152,18 +2232,26 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p /* Process Locked */
__HAL_LOCK(hi2c);
-
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
/* Disable Pos */
hi2c->Instance->CR1 &= ~I2C_CR1_POS;
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->pBuffPtr = pData;
- hi2c->XferSize = Size;
- hi2c->XferCount = Size;
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
/* Set the I2C DMA transfer complete callback */
hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
@@ -2178,74 +2266,22 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p hi2c->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA Stream */
- HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size);
-
- /* Enable ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
-
- /* Enable DMA Request */
- hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
/* Enable Address Acknowledge */
hi2c->Instance->CR1 |= I2C_CR1_ACK;
- /* Wait until ADDR flag is set */
- count = I2C_TIMEOUT_ADDR_SLAVE * (SystemCoreClock /25U /1000U);
- do
- {
- if(count-- == 0U)
- {
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == RESET);
-
- /* If 7bit addressing mode is selected */
- if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
- {
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
- }
- else
- {
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Wait until ADDR flag is set */
- count = I2C_TIMEOUT_ADDR_SLAVE * (SystemCoreClock /25U /1000U);
- do
- {
- if(count-- == 0U)
- {
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == RESET);
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
- }
-
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
- /* Enable ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
+ /* Enable EVT and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
return HAL_OK;
}
@@ -2256,9 +2292,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p }
/**
- * @brief Receive in slave mode an amount of data in no-blocking mode with DMA
+ * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * the configuration information for the specified I2C.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
@@ -2293,25 +2329,33 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD /* Process Locked */
__HAL_LOCK(hi2c);
-
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
/* Disable Pos */
hi2c->Instance->CR1 &= ~I2C_CR1_POS;
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->pBuffPtr = pData;
- hi2c->XferSize = Size;
- hi2c->XferCount = Size;
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
+ hi2c->XferSize = hi2c->XferCount;
+
/* Set the I2C DMA transfer complete callback */
hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
/* Set the DMA error callback */
hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
+
/* Set the unused DMA callbacks to NULL */
hi2c->hdmarx->XferHalfCpltCallback = NULL;
hi2c->hdmarx->XferM1CpltCallback = NULL;
@@ -2319,45 +2363,22 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD hi2c->hdmarx->XferAbortCallback = NULL;
/* Enable the DMA Stream */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size);
-
- /* Enable ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
-
- /* Enable DMA Request */
- hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
/* Enable Address Acknowledge */
hi2c->Instance->CR1 |= I2C_CR1_ACK;
- /* Wait until ADDR flag is set */
- count = I2C_TIMEOUT_ADDR_SLAVE * (SystemCoreClock /25U /1000U);
- do
- {
- if(count-- == 0U)
- {
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == RESET);
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
- /* Enable ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
+ /* Enable EVT and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
return HAL_OK;
}
@@ -2369,7 +2390,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD /**
* @brief Write an amount of data in blocking mode to a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
@@ -2399,13 +2420,25 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress /* Process Locked */
__HAL_LOCK(hi2c);
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
/* Disable Pos */
hi2c->Instance->CR1 &= ~I2C_CR1_POS;
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
/* Send Slave Address and Memory Address */
if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
@@ -2424,7 +2457,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress }
}
- while(Size > 0U)
+ while(hi2c->XferSize > 0U)
{
/* Wait until TXE flag is set */
if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
@@ -2442,14 +2475,16 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress }
/* Write data to DR */
- hi2c->Instance->DR = (*pData++);
- Size--;
+ hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->XferSize--;
+ hi2c->XferCount--;
- if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0))
+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
{
/* Write data to DR */
- hi2c->Instance->DR = (*pData++);
- Size--;
+ hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->XferSize--;
+ hi2c->XferCount--;
}
}
@@ -2488,7 +2523,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress /**
* @brief Read an amount of data in blocking mode from a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
@@ -2518,14 +2553,26 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Process Locked */
__HAL_LOCK(hi2c);
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
/* Disable Pos */
hi2c->Instance->CR1 &= ~I2C_CR1_POS;
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
+ hi2c->XferSize = hi2c->XferCount;
+
/* Send Slave Address and Memory Address */
if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
{
@@ -2543,7 +2590,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, }
}
- if(Size == 0U)
+ if(hi2c->XferSize == 0U)
{
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
@@ -2551,7 +2598,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Generate Stop */
hi2c->Instance->CR1 |= I2C_CR1_STOP;
}
- else if(Size == 1U)
+ else if(hi2c->XferSize == 1U)
{
/* Disable Acknowledge */
hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
@@ -2562,7 +2609,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Generate Stop */
hi2c->Instance->CR1 |= I2C_CR1_STOP;
}
- else if(Size == 2U)
+ else if(hi2c->XferSize == 2U)
{
/* Disable Acknowledge */
hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
@@ -2579,12 +2626,12 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
}
- while(Size > 0U)
+ while(hi2c->XferSize > 0U)
{
- if(Size <= 3U)
+ if(hi2c->XferSize <= 3U)
{
/* One byte */
- if(Size== 1U)
+ if(hi2c->XferSize== 1U)
{
/* Wait until RXNE flag is set */
if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
@@ -2600,8 +2647,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, }
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
}
/* Two bytes */
else if(Size == 2U)
@@ -2616,12 +2664,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, hi2c->Instance->CR1 |= I2C_CR1_STOP;
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
}
/* 3 Last bytes */
else
@@ -2636,8 +2686,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
/* Wait until BTF flag is set */
if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
@@ -2649,18 +2700,20 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, hi2c->Instance->CR1 |= I2C_CR1_STOP;
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
}
}
else
{
/* Wait until RXNE flag is set */
- if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
{
@@ -2673,14 +2726,16 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, }
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
{
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
}
}
}
@@ -2700,9 +2755,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, }
/**
- * @brief Write an amount of data in no-blocking mode with Interrupt to a specific memory address
+ * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
@@ -2738,7 +2793,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Process Locked */
__HAL_LOCK(hi2c);
-
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
/* Disable Pos */
hi2c->Instance->CR1 &= ~I2C_CR1_POS;
@@ -2746,6 +2808,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ /* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferSize = Size;
hi2c->XferCount = Size;
@@ -2777,9 +2840,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr }
/**
- * @brief Read an amount of data in no-blocking mode with Interrupt from a specific memory address
+ * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
@@ -2816,6 +2879,13 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre /* Process Locked */
__HAL_LOCK(hi2c);
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
/* Disable Pos */
hi2c->Instance->CR1 &= ~I2C_CR1_POS;
@@ -2823,6 +2893,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ /* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferSize = Size;
hi2c->XferCount = Size;
@@ -2859,9 +2930,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre }
/**
- * @brief Write an amount of data in no-blocking mode with DMA to a specific memory address
+ * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
@@ -2871,13 +2942,13 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre */
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
+ __IO uint32_t count = 0U;
+
uint32_t tickstart = 0x00U;
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
- __IO uint32_t count = 0U;
-
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
@@ -2903,13 +2974,21 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Process Locked */
__HAL_LOCK(hi2c);
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
/* Disable Pos */
hi2c->Instance->CR1 &= ~I2C_CR1_POS;
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ /* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferSize = Size;
hi2c->XferCount = Size;
@@ -2930,7 +3009,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd hi2c->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA Stream */
- HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size);
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
/* Send Slave Address and Memory Address */
if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
@@ -2949,40 +3028,21 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd }
}
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
/* Enable ERR interrupt */
__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
/* Enable DMA Request */
hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
}
- else
- {
- /* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
-
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
- hi2c->State = HAL_I2C_STATE_READY;
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
return HAL_OK;
}
else
@@ -2992,9 +3052,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd }
/**
- * @brief Reads an amount of data in no-blocking mode with DMA from a specific memory address.
+ * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
@@ -3036,17 +3096,25 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Process Locked */
__HAL_LOCK(hi2c);
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
/* Disable Pos */
hi2c->Instance->CR1 &= ~I2C_CR1_POS;
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ /* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
- hi2c->XferSize = Size;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
if(hi2c->XferSize > 0U)
{
@@ -3063,7 +3131,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->hdmarx->XferAbortCallback = NULL;
/* Enable the DMA Stream */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size);
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
/* Send Slave Address and Memory Address */
if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
@@ -3151,7 +3219,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr * @brief Checks if target device is ready for communication.
* @note This function is used with Memory devices
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * the configuration information for the specified I2C.
* @param DevAddress Target device address
* @param Trials Number of trials
* @param Timeout Timeout duration
@@ -3175,6 +3243,13 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Process Locked */
__HAL_LOCK(hi2c);
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
/* Disable Pos */
hi2c->Instance->CR1 &= ~I2C_CR1_POS;
@@ -3270,8 +3345,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /**
* @brief This function handles I2C event interrupt request.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @retval HAL status
+ * the configuration information for the specified I2C.
+ * @retval None
*/
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
{
@@ -3376,8 +3451,8 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /**
* @brief This function handles I2C error interrupt request.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @retval HAL status
+ * the configuration information for the specified I2C.
+ * @retval None
*/
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
{
@@ -3420,12 +3495,15 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) {
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- /* Generate Stop */
- SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
+ /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */
+ if(hi2c->Mode == HAL_I2C_MODE_MASTER)
+ {
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
+ }
/* Clear AF flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
}
}
@@ -3445,59 +3523,63 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) }
/**
- * @brief Master Tx Transfer completed callbacks.
+ * @brief Master Tx Transfer completed callback.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MasterTxCpltCallback can be implemented in the user file
*/
}
/**
- * @brief Master Rx Transfer completed callbacks.
+ * @brief Master Rx Transfer completed callback.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MasterRxCpltCallback can be implemented in the user file
*/
}
-/** @brief Slave Tx Transfer completed callbacks.
+/** @brief Slave Tx Transfer completed callback.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_SlaveTxCpltCallback can be implemented in the user file
*/
}
/**
- * @brief Slave Rx Transfer completed callbacks.
+ * @brief Slave Rx Transfer completed callback.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_SlaveRxCpltCallback can be implemented in the user file
*/
@@ -3517,6 +3599,7 @@ __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirect UNUSED(hi2c);
UNUSED(TransferDirection);
UNUSED(AddrMatchCode);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_AddrCallback can be implemented in the user file
*/
@@ -3532,51 +3615,55 @@ __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) {
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_ListenCpltCallback can be implemented in the user file
*/
}
/**
- * @brief Memory Tx Transfer completed callbacks.
+ * @brief Memory Tx Transfer completed callback.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MemTxCpltCallback can be implemented in the user file
*/
}
/**
- * @brief Memory Rx Transfer completed callbacks.
+ * @brief Memory Rx Transfer completed callback.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MemRxCpltCallback can be implemented in the user file
*/
}
/**
- * @brief I2C error callbacks.
+ * @brief I2C error callback.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_ErrorCallback can be implemented in the user file
*/
@@ -3602,12 +3689,12 @@ __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) * @}
*/
-/** @defgroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions
+/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
* @brief Peripheral State and Errors functions
*
@verbatim
===============================================================================
- ##### Peripheral State, Mode and Errors functions #####
+ ##### Peripheral State, Mode and Error functions #####
===============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral
@@ -3618,18 +3705,19 @@ __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) */
/**
- * @brief Returns the I2C state.
+ * @brief Return the I2C handle state.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * the configuration information for the specified I2C.
* @retval HAL state
*/
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
{
+ /* Return I2C handle state */
return hi2c->State;
}
/**
- * @brief Returns the I2C Master, Slave, Memory or no mode.
+ * @brief Return the I2C Master, Slave, Memory or no mode.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval HAL mode
@@ -3666,7 +3754,6 @@ static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c) uint32_t CurrentState = hi2c->State;
uint32_t CurrentMode = hi2c->Mode;
uint32_t CurrentXferOptions = hi2c->XferOptions;
- uint32_t tmp;
if((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
{
@@ -3674,25 +3761,24 @@ static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c) if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
{
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
- tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
- hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
+
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->State = HAL_I2C_STATE_READY;
-
+
HAL_I2C_MasterTxCpltCallback(hi2c);
}
else /* Generate Stop condition then Call TxCpltCallback() */
{
/* Disable EVT, BUF and ERR interrupt */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
+
/* Generate Stop */
hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
+
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State = HAL_I2C_STATE_READY;
-
+
if(hi2c->Mode == HAL_I2C_MODE_MEM)
{
hi2c->Mode = HAL_I2C_MODE_NONE;
@@ -3778,7 +3864,6 @@ static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c) static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
{
/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
- uint32_t tmp;
uint32_t CurrentXferOptions = hi2c->XferOptions;
if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
@@ -3796,8 +3881,7 @@ static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) {
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
- tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
- hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->State = HAL_I2C_STATE_READY;
@@ -3890,17 +3974,17 @@ static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
hi2c->XferCount--;
- tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
- hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
hi2c->State = HAL_I2C_STATE_READY;
if(hi2c->Mode == HAL_I2C_MODE_MEM)
{
+ hi2c->PreviousState = I2C_STATE_NONE;
hi2c->Mode = HAL_I2C_MODE_NONE;
HAL_I2C_MemRxCpltCallback(hi2c);
}
else
{
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
hi2c->Mode = HAL_I2C_MODE_NONE;
HAL_I2C_MasterRxCpltCallback(hi2c);
}
@@ -3918,7 +4002,6 @@ static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
{
/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
- uint32_t tmp;
uint32_t CurrentXferOptions = hi2c->XferOptions;
if(hi2c->XferCount == 3U)
@@ -3948,13 +4031,9 @@ static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) /* Enable Acknowledge */
hi2c->Instance->CR1 |= I2C_CR1_ACK;
}
- tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
- hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
}
else
{
- hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
-
/* Generate Stop */
hi2c->Instance->CR1 |= I2C_CR1_STOP;
}
@@ -3974,12 +4053,14 @@ static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) if(hi2c->Mode == HAL_I2C_MODE_MEM)
{
+ hi2c->PreviousState = I2C_STATE_NONE;
hi2c->Mode = HAL_I2C_MODE_NONE;
HAL_I2C_MemRxCpltCallback(hi2c);
}
else
{
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
hi2c->Mode = HAL_I2C_MODE_NONE;
HAL_I2C_MasterRxCpltCallback(hi2c);
@@ -4000,7 +4081,6 @@ static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) * the configuration information for I2C module
* @retval HAL status
*/
-
static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c)
{
if(hi2c->Mode == HAL_I2C_MODE_MEM)
@@ -4073,7 +4153,7 @@ static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c) uint32_t CurrentMode = hi2c->Mode;
uint32_t CurrentXferOptions = hi2c->XferOptions;
uint32_t Prev_State = hi2c->PreviousState;
-
+
if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
if((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM))
@@ -4103,8 +4183,30 @@ static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c) }
else if(hi2c->XferCount == 1U)
{
+ if(CurrentXferOptions == I2C_NO_OPTION_FRAME)
+ {
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+ {
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ }
+ else
+ {
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ }
+ }
/* Prepare next transfer or stop current transfer */
- if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \
+ else if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \
&& (Prev_State != I2C_STATE_MASTER_BUSY_RX))
{
if(hi2c->XferOptions != I2C_NEXT_FRAME)
@@ -4148,7 +4250,13 @@ static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c) /* Enable Acknowledge */
hi2c->Instance->CR1 |= I2C_CR1_ACK;
}
-
+
+ if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+ {
+ /* Enable Last DMA bit */
+ hi2c->Instance->CR2 |= I2C_CR2_LAST;
+ }
+
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
}
@@ -4156,13 +4264,19 @@ static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c) {
/* Enable Acknowledge */
hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
+
+ if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+ {
+ /* Enable Last DMA bit */
+ hi2c->Instance->CR2 |= I2C_CR2_LAST;
+ }
+
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
}
/* Reset Event counter */
- hi2c->EventCount = 0;
+ hi2c->EventCount = 0U;
}
}
else
@@ -4183,7 +4297,6 @@ static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c) static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
{
/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
- uint32_t tmp;
uint32_t CurrentState = hi2c->State;
if(hi2c->XferCount != 0U)
@@ -4198,8 +4311,7 @@ static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c) __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
/* Set state at HAL_I2C_STATE_LISTEN */
- tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
- hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
hi2c->State = HAL_I2C_STATE_LISTEN;
/* Call the Tx complete callback to inform upper layer of the end of receive process */
@@ -4235,7 +4347,6 @@ static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c) static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
{
/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
- uint32_t tmp;
uint32_t CurrentState = hi2c->State;
if(hi2c->XferCount != 0U)
@@ -4248,12 +4359,11 @@ static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c) {
/* Last Byte is received, disable Interrupt */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
-
+
/* Set state at HAL_I2C_STATE_LISTEN */
- tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
- hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
hi2c->State = HAL_I2C_STATE_LISTEN;
-
+
/* Call the Rx complete callback to inform upper layer of the end of receive process */
HAL_I2C_SlaveRxCpltCallback(hi2c);
}
@@ -4330,29 +4440,72 @@ static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c) /* Disable Acknowledge */
hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
- if((CurrentState == HAL_I2C_STATE_LISTEN ) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) || \
- (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
+ /* If a DMA is ongoing, Update handle size context */
+ if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
{
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
- HAL_I2C_ListenCpltCallback(hi2c);
+ if((hi2c->State == HAL_I2C_STATE_BUSY_RX) || (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ {
+ hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmarx);
+ }
+ else
+ {
+ hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmatx);
+ }
+ }
+
+ /* All data are not transferred, so set error code accordingly */
+ if(hi2c->XferCount != 0U)
+ {
+ /* Store Last receive data if any */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
+ {
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferCount--;
+ }
+
+ /* Store Last receive data if any */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+ {
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferCount--;
+ }
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c);
}
else
{
- if((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX))
+ if((CurrentState == HAL_I2C_STATE_LISTEN ) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) || \
+ (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
{
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
-
- HAL_I2C_SlaveRxCpltCallback(hi2c);
+
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+ HAL_I2C_ListenCpltCallback(hi2c);
}
- }
+ else
+ {
+ if((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX))
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ HAL_I2C_SlaveRxCpltCallback(hi2c);
+ }
+ }
+ }
return HAL_OK;
}
@@ -4366,7 +4519,6 @@ static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c) /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
uint32_t CurrentState = hi2c->State;
uint32_t CurrentXferOptions = hi2c->XferOptions;
- uint32_t tmp;
if(((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \
(CurrentState == HAL_I2C_STATE_LISTEN))
@@ -4392,8 +4544,7 @@ static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c) else if(CurrentState == HAL_I2C_STATE_BUSY_TX)
{
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
- hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
@@ -4438,7 +4589,7 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c) {
/* If state is an abort treatment on going, don't change state */
/* This change will be do later */
- if(hi2c->State != HAL_I2C_STATE_ABORT)
+ if((hi2c->State != HAL_I2C_STATE_ABORT) && ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) != I2C_CR2_DMAEN))
{
hi2c->State = HAL_I2C_STATE_READY;
}
@@ -4450,11 +4601,11 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c) hi2c->Instance->CR1 &= ~I2C_CR1_POS;
/* Abort DMA transfer */
- if((hi2c->Instance->CR1 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+ if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
{
hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
- if(hi2c->hdmatx != NULL)
+ if(hi2c->hdmatx->State != HAL_DMA_STATE_READY)
{
/* Set the DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
@@ -4462,11 +4613,16 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c) if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
{
+ /* Disable I2C peripheral to prevent dummy data in buffer */
+ __HAL_I2C_DISABLE(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
/* Call Directly XferAbortCallback function in case of error */
hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
}
}
- else if(hi2c->hdmarx != NULL)
+ else
{
/* Set the DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
@@ -4474,6 +4630,18 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c) if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
{
+ /* Store Last receive data if any */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+ {
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ }
+
+ /* Disable I2C peripheral to prevent dummy data in buffer */
+ __HAL_I2C_DISABLE(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
/* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
}
@@ -4482,12 +4650,30 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c) else if(hi2c->State == HAL_I2C_STATE_ABORT)
{
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Store Last receive data if any */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+ {
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ }
+
+ /* Disable I2C peripheral to prevent dummy data in buffer */
+ __HAL_I2C_DISABLE(hi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
HAL_I2C_AbortCpltCallback(hi2c);
}
else
{
+ /* Store Last receive data if any */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+ {
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ }
+
/* Call user error callback */
HAL_I2C_ErrorCallback(hi2c);
}
@@ -4596,20 +4782,17 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
uint32_t CurrentXferOptions = hi2c->XferOptions;
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
/* Generate Start condition if first transfer */
if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
{
- /* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
/* Generate Start */
hi2c->Instance->CR1 |= I2C_CR1_START;
}
else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
{
- /* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
/* Generate ReStart */
hi2c->Instance->CR1 |= I2C_CR1_START;
}
@@ -5024,6 +5207,10 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) {
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Disable I2C peripheral to prevent dummy data in buffer */
+ __HAL_I2C_DISABLE(hi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
HAL_I2C_AbortCpltCallback(hi2c);
@@ -5033,6 +5220,9 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
+ /* Disable I2C peripheral to prevent dummy data in buffer */
+ __HAL_I2C_DISABLE(hi2c);
+
/* Call the corresponding callback to inform upper layer of End of Transfer */
HAL_I2C_ErrorCallback(hi2c);
}
@@ -5060,7 +5250,8 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin {
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State= HAL_I2C_STATE_READY;
-
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_i2s.c b/stmhal/hal/f4/src/stm32f4xx_hal_i2s.c index 022560827..f36855709 100644 --- a/stmhal/hal/f4/src/stm32f4xx_hal_i2s.c +++ b/stmhal/hal/f4/src/stm32f4xx_hal_i2s.c @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_i2s.c
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Integrated Interchip Sound (I2S) peripheral:
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_i2s_ex.c b/stmhal/hal/f4/src/stm32f4xx_hal_i2s_ex.c index 4907ab81b..dfc4daf43 100644 --- a/stmhal/hal/f4/src/stm32f4xx_hal_i2s_ex.c +++ b/stmhal/hal/f4/src/stm32f4xx_hal_i2s_ex.c @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_i2s_ex.c
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2S extension peripheral:
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_pcd.c b/stmhal/hal/f4/src/stm32f4xx_hal_pcd.c index b5d2d4db7..b867ff92a 100644 --- a/stmhal/hal/f4/src/stm32f4xx_hal_pcd.c +++ b/stmhal/hal/f4/src/stm32f4xx_hal_pcd.c @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_pcd.c
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_pcd_ex.c b/stmhal/hal/f4/src/stm32f4xx_hal_pcd_ex.c index 2d0a4e8de..9f9b49384 100644 --- a/stmhal/hal/f4/src/stm32f4xx_hal_pcd_ex.c +++ b/stmhal/hal/f4/src/stm32f4xx_hal_pcd_ex.c @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_pcd_ex.c
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_pwr.c b/stmhal/hal/f4/src/stm32f4xx_hal_pwr.c index 8f06a93b3..2cb927eef 100644 --- a/stmhal/hal/f4/src/stm32f4xx_hal_pwr.c +++ b/stmhal/hal/f4/src/stm32f4xx_hal_pwr.c @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_pwr.c
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_pwr_ex.c b/stmhal/hal/f4/src/stm32f4xx_hal_pwr_ex.c index 42cde7e40..06c7e631a 100644 --- a/stmhal/hal/f4/src/stm32f4xx_hal_pwr_ex.c +++ b/stmhal/hal/f4/src/stm32f4xx_hal_pwr_ex.c @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_pwr_ex.c
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Extended PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of PWR extension peripheral:
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_rcc.c b/stmhal/hal/f4/src/stm32f4xx_hal_rcc.c index 10d5e921b..cbefae349 100644 --- a/stmhal/hal/f4/src/stm32f4xx_hal_rcc.c +++ b/stmhal/hal/f4/src/stm32f4xx_hal_rcc.c @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_rcc.c
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Reset and Clock Control (RCC) peripheral:
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_rcc_ex.c b/stmhal/hal/f4/src/stm32f4xx_hal_rcc_ex.c index c8080ee8f..2f36a0e19 100644 --- a/stmhal/hal/f4/src/stm32f4xx_hal_rcc_ex.c +++ b/stmhal/hal/f4/src/stm32f4xx_hal_rcc_ex.c @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_rcc_ex.c
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief Extension RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities RCC extension peripheral:
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_rng.c b/stmhal/hal/f4/src/stm32f4xx_hal_rng.c index 56e4b1bef..7c61096ff 100644 --- a/stmhal/hal/f4/src/stm32f4xx_hal_rng.c +++ b/stmhal/hal/f4/src/stm32f4xx_hal_rng.c @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_rng.c
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief RNG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Random Number Generator (RNG) peripheral:
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_rtc.c b/stmhal/hal/f4/src/stm32f4xx_hal_rtc.c index a6f286e3c..663192b3a 100644 --- a/stmhal/hal/f4/src/stm32f4xx_hal_rtc.c +++ b/stmhal/hal/f4/src/stm32f4xx_hal_rtc.c @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_rtc.c
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) peripheral:
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_rtc_ex.c b/stmhal/hal/f4/src/stm32f4xx_hal_rtc_ex.c index 035f8c3ae..871c87c9e 100644 --- a/stmhal/hal/f4/src/stm32f4xx_hal_rtc_ex.c +++ b/stmhal/hal/f4/src/stm32f4xx_hal_rtc_ex.c @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_rtc_ex.c
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) Extension peripheral:
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_sd.c b/stmhal/hal/f4/src/stm32f4xx_hal_sd.c index fc216ca21..f70a1fbea 100644 --- a/stmhal/hal/f4/src/stm32f4xx_hal_sd.c +++ b/stmhal/hal/f4/src/stm32f4xx_hal_sd.c @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_sd.c
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief SD card HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Secure Digital (SD) peripheral:
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_spi.c b/stmhal/hal/f4/src/stm32f4xx_hal_spi.c index 5d1a139b7..93387d13a 100644 --- a/stmhal/hal/f4/src/stm32f4xx_hal_spi.c +++ b/stmhal/hal/f4/src/stm32f4xx_hal_spi.c @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_spi.c
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief SPI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Serial Peripheral Interface (SPI) peripheral:
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_tim.c b/stmhal/hal/f4/src/stm32f4xx_hal_tim.c index ceedccda9..72d9abb44 100644 --- a/stmhal/hal/f4/src/stm32f4xx_hal_tim.c +++ b/stmhal/hal/f4/src/stm32f4xx_hal_tim.c @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_tim.c
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer (TIM) peripheral:
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_tim_ex.c b/stmhal/hal/f4/src/stm32f4xx_hal_tim_ex.c index 51716eef8..607a96333 100644 --- a/stmhal/hal/f4/src/stm32f4xx_hal_tim_ex.c +++ b/stmhal/hal/f4/src/stm32f4xx_hal_tim_ex.c @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_tim_ex.c
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer extension peripheral:
diff --git a/stmhal/hal/f4/src/stm32f4xx_hal_uart.c b/stmhal/hal/f4/src/stm32f4xx_hal_uart.c index 2a6f24848..350af3b77 100644 --- a/stmhal/hal/f4/src/stm32f4xx_hal_uart.c +++ b/stmhal/hal/f4/src/stm32f4xx_hal_uart.c @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_uart.c
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief UART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
diff --git a/stmhal/hal/f4/src/stm32f4xx_ll_sdmmc.c b/stmhal/hal/f4/src/stm32f4xx_ll_sdmmc.c index 0dbde9c3e..cf5997676 100644 --- a/stmhal/hal/f4/src/stm32f4xx_ll_sdmmc.c +++ b/stmhal/hal/f4/src/stm32f4xx_ll_sdmmc.c @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_ll_sdmmc.c
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief SDMMC Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
diff --git a/stmhal/hal/f4/src/stm32f4xx_ll_usb.c b/stmhal/hal/f4/src/stm32f4xx_ll_usb.c index b57c1cd73..93ba19fcf 100644 --- a/stmhal/hal/f4/src/stm32f4xx_ll_usb.c +++ b/stmhal/hal/f4/src/stm32f4xx_ll_usb.c @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_ll_usb.c
* @author MCD Application Team
- * @version V1.5.1
- * @date 01-July-2016
+ * @version V1.5.2
+ * @date 22-September-2016
* @brief USB Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
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