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| author | Jim Mussared <jim.mussared@gmail.com> | 2022-10-08 23:08:53 +1100 |
|---|---|---|
| committer | Damien George <damien@micropython.org> | 2022-10-11 23:17:41 +1100 |
| commit | 17f2783e4aa4534823e2dc33e77389ad498f2d24 (patch) | |
| tree | 7d35ac04c022084fe516bbb95dd6e353b1e325e7 /docs/develop | |
| parent | 8e912a501a926f59f330f8a71c2ac1bd4af88a9e (diff) | |
all: Use += rather than = everywhere for CFLAGS/LDFLAGS/LIBS.
This avoids a surprise where an = can cancel out an earlier +=.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
Diffstat (limited to 'docs/develop')
| -rw-r--r-- | docs/develop/porting.rst | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/docs/develop/porting.rst b/docs/develop/porting.rst index 0511f5d27..74974a39e 100644 --- a/docs/develop/porting.rst +++ b/docs/develop/porting.rst @@ -98,8 +98,8 @@ We also need a Makefile at this point for the port: include $(TOP)/extmod/extmod.mk # Set CFLAGS and libraries. - CFLAGS = -I. -I$(BUILD) -I$(TOP) - LIBS = -lm + CFLAGS += -I. -I$(BUILD) -I$(TOP) + LIBS += -lm # Define the required source files. SRC_C = \ |