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author | robert-hh <robert@hammelrath.com> | 2024-02-20 18:52:57 +0100 |
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committer | Damien George <damien@micropython.org> | 2024-08-29 16:27:43 +1000 |
commit | 01c046d2a803ead4d320ed533938fcc878a5959e (patch) | |
tree | f2907584725ba9d917b77563a9e69e97ceca91f6 /docs/esp32/tutorial/intro.rst | |
parent | fd03a0587f7303d2b37d69c85a1e079088c3de6c (diff) |
rp2/machine_uart: Implement a Python UART IRQ handler.
Supported trigger names: IRQ_RXIDLE, IRQ_TXIDLE, IRQ_BREAK
- IRQ_RXIDLE: The handler for IRQ_RXIDLE is called reliably 31 UART bit
times after the last incoming data.
- IRQ_TXIDLE: This IRQ is triggered after at least >5 characters are sent
at once. It is triggered when the TX FIFO falls below 4 elements. At
that time, up to 5 bytes may still be in the FIFO and output shift
register.
- IRQ_BREAK: The IRQ triggers if a BREAK state is detected at RX.
Properties & side effects:
- After a BREAK, a valid character must be received before another break
can be detected.
- Each break puts a 0xff character into the input buffer.
The irq.flags() value is cleared only with a new wanted event. Do not
change the flags otherwise.
Signed-off-by: robert-hh <robert@hammelrath.com>
Diffstat (limited to 'docs/esp32/tutorial/intro.rst')
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