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| author | Clayton Mills <clayton.mills@planetinnovation.com.au> | 2022-05-26 17:57:17 +1000 |
|---|---|---|
| committer | Damien George <damien@micropython.org> | 2022-06-07 18:08:02 +1000 |
| commit | 0d8d911950703ea7b2efea7a40a73c942aa84b37 (patch) | |
| tree | e0fa441527d082aeb66a3ca059ede7228f145d1f /docs/esp8266/tutorial/network_basics.rst | |
| parent | 14105ff5b168acdefba4b5f0b9079c7eb757bded (diff) | |
stm32/powerctrl: Disable sys tick interrupt in stop mode on some STM32s.
According to ST Errata ES0206 Rev 18, Section 2.2.1, on STM32F427x,
STM32F437x, STM32F429x and STM32F439x.
If the system tick interrupt is enabled during stop mode while certain
bits are set in the DBGMCU_CR, then the system will immediately wake
from stop mode.
Suggested workaround is to disable system tick timer interrupt when
entering stop mode.
According to ST Errate ES0394 Rev 11, Section 2.2.17, on STM32WB55Cx and
STM32WB35Cx.
If the system tick interrupt is enabled during stop 0, stop 1 or stop 2
while certain bits are set in DBGMCU_CR, then system will immediately
wake from stop mode but the system remains in low power state. The CPU
therefore fetches incorrect data from inactive Flash, which can cause a
hard fault.
Suggested workaround is to disable system tick timer interrupt when
entering stop mode.
Diffstat (limited to 'docs/esp8266/tutorial/network_basics.rst')
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