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| author | Damien George <damien.p.george@gmail.com> | 2019-12-04 15:02:54 +1100 |
|---|---|---|
| committer | Damien George <damien.p.george@gmail.com> | 2019-12-04 15:02:54 +1100 |
| commit | 90c524c1141ed9ad8fa882dba6f36199a7768e32 (patch) | |
| tree | 0ee0799df23cb231c47de6f0b885d6f124e448c6 /docs/reference | |
| parent | 40cc7ec677e962c47db567479e42c27ed8911ff6 (diff) | |
docs: Remove spaces on lines that are empty.
Diffstat (limited to 'docs/reference')
| -rw-r--r-- | docs/reference/asm_thumb2_float.rst | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/docs/reference/asm_thumb2_float.rst b/docs/reference/asm_thumb2_float.rst index 4acb734ee..46560413c 100644 --- a/docs/reference/asm_thumb2_float.rst +++ b/docs/reference/asm_thumb2_float.rst @@ -31,7 +31,7 @@ Arithmetic * vsqrt(Sd, Sm) ``Sd = sqrt(Sm)`` Registers may be identical: ``vmul(S0, S0, S0)`` will execute ``S0 = S0*S0`` - + Move between ARM core and FPU registers --------------------------------------- @@ -40,7 +40,7 @@ Move between ARM core and FPU registers The FPU has a register known as FPSCR, similar to the ARM core's APSR, which stores condition codes plus other data. The following instructions provide access to this. - + * vmrs(APSR\_nzcv, FPSCR) Move the floating-point N, Z, C, and V flags to the APSR N, Z, C, and V flags. |