diff options
| author | Angus Gratton <angus@redyak.com.au> | 2025-08-06 15:57:38 +1000 |
|---|---|---|
| committer | Damien George <damien@micropython.org> | 2025-08-07 16:55:46 +1000 |
| commit | 593ae04eeb06b6fd7c6232eb41912b8d26170ddd (patch) | |
| tree | 1a8cac3a8a553efebe16c1f0bf7f01846cb02880 /ports/esp32/machine_timer.h | |
| parent | ce109af712452474dfe3864f82b5430f4e2a5ff0 (diff) | |
esp32/machine_timer: Fix machine.Timer() tick frequency on ESP32C2,C6.
Also future-proofs this code for other chips. Apart form C6 and C2, all
currently supported chips use APB clock for GPTIMER_CLK_SRC_DEFAULT.
ESP32-C2 uses 40MHz PLL but APB_CLK_FREQ was 26MHz.
ESP32-C6 uses 80MHz PLL but APB_CLK_FREQ was 40MHz.
Implementation now gets the correct frequency from ESP-IDF.
This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>
Diffstat (limited to 'ports/esp32/machine_timer.h')
| -rw-r--r-- | ports/esp32/machine_timer.h | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/ports/esp32/machine_timer.h b/ports/esp32/machine_timer.h index 10fe2f39c..5dd0ce95a 100644 --- a/ports/esp32/machine_timer.h +++ b/ports/esp32/machine_timer.h @@ -34,13 +34,6 @@ #include "hal/timer_ll.h" #include "soc/timer_periph.h" -#define TIMER_DIVIDER 8 - -// TIMER_BASE_CLK is normally 80MHz. TIMER_DIVIDER ought to divide this exactly -#define TIMER_SCALE (APB_CLK_FREQ / TIMER_DIVIDER) - -#define TIMER_FLAGS 0 - typedef struct _machine_timer_obj_t { mp_obj_base_t base; @@ -64,4 +57,6 @@ machine_timer_obj_t *machine_timer_create(mp_uint_t timer); void machine_timer_enable(machine_timer_obj_t *self); void machine_timer_disable(machine_timer_obj_t *self); +uint32_t machine_timer_freq_hz(void); + #endif // MICROPY_INCLUDED_ESP32_MACHINE_TIMER_H |