diff options
| author | Angus Gratton <angus@redyak.com.au> | 2025-08-06 15:57:38 +1000 |
|---|---|---|
| committer | Damien George <damien@micropython.org> | 2025-08-07 16:55:46 +1000 |
| commit | 593ae04eeb06b6fd7c6232eb41912b8d26170ddd (patch) | |
| tree | 1a8cac3a8a553efebe16c1f0bf7f01846cb02880 /ports/esp32/machine_uart.c | |
| parent | ce109af712452474dfe3864f82b5430f4e2a5ff0 (diff) | |
esp32/machine_timer: Fix machine.Timer() tick frequency on ESP32C2,C6.HEADorigin/masterorigin/HEADmaster
Also future-proofs this code for other chips. Apart form C6 and C2, all
currently supported chips use APB clock for GPTIMER_CLK_SRC_DEFAULT.
ESP32-C2 uses 40MHz PLL but APB_CLK_FREQ was 26MHz.
ESP32-C6 uses 80MHz PLL but APB_CLK_FREQ was 40MHz.
Implementation now gets the correct frequency from ESP-IDF.
This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>
Diffstat (limited to 'ports/esp32/machine_uart.c')
| -rw-r--r-- | ports/esp32/machine_uart.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/ports/esp32/machine_uart.c b/ports/esp32/machine_uart.c index 661c07138..c4dab2cae 100644 --- a/ports/esp32/machine_uart.c +++ b/ports/esp32/machine_uart.c @@ -58,7 +58,7 @@ #define UART_IRQ_RXIDLE (0x1000) #define UART_IRQ_BREAK (1 << UART_BREAK) #define MP_UART_ALLOWED_FLAGS (UART_IRQ_RX | UART_IRQ_RXIDLE | UART_IRQ_BREAK) -#define RXIDLE_TIMER_MIN (5000) // 500 us +#define RXIDLE_TIMER_MIN (machine_timer_freq_hz() * 5 / 10000) // 500us minimum rxidle time #define UART_QUEUE_SIZE (3) enum { @@ -535,7 +535,7 @@ static void uart_irq_configure_timer(machine_uart_obj_t *self, mp_uint_t trigger self->mp_irq_obj->ishard = false; uint32_t baudrate; uart_get_baudrate(self->uart_num, &baudrate); - mp_int_t period = TIMER_SCALE * 20 / baudrate + 1; + mp_int_t period = machine_timer_freq_hz() * 20 / baudrate + 1; if (period < RXIDLE_TIMER_MIN) { period = RXIDLE_TIMER_MIN; } |