diff options
| author | Francisco J. Manno <fmanno@gmail.com> | 2019-03-03 23:50:23 +0000 |
|---|---|---|
| committer | Damien George <damien.p.george@gmail.com> | 2019-03-05 15:49:08 +1100 |
| commit | f938e70c6905474b08f7b5e6df3da9c1b0dcf01a (patch) | |
| tree | 964500dbfb82827080a3a3695e31ebb94f599019 /ports/stm32/stm32_it.c | |
| parent | e61862d063b7a19f5baba8e0d1234d648826a616 (diff) | |
stm32: Add compile-time option to use HSI as clock source.
To use HSI instead of HSE define MICROPY_HW_CLK_USE_HSI as 1 in the board
configuration file. The default is to use HSE.
HSI has been made the default for the NUCLEO_F401RE board to serve as an
example, and because early revisions of this board need a hardware
modification to get HSE working.
Diffstat (limited to 'ports/stm32/stm32_it.c')
| -rw-r--r-- | ports/stm32/stm32_it.c | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/ports/stm32/stm32_it.c b/ports/stm32/stm32_it.c index 0f2be4c68..004e0f974 100644 --- a/ports/stm32/stm32_it.c +++ b/ports/stm32/stm32_it.c @@ -329,13 +329,16 @@ STATIC void OTG_CMD_WKUP_Handler(PCD_HandleTypeDef *pcd_handle) { /* Reset SLEEPDEEP bit of Cortex System Control Register */ SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); - /* Configures system clock after wake-up from STOP: enable HSE, PLL and select - PLL as system clock source (HSE and PLL are disabled in STOP mode) */ + /* Configures system clock after wake-up from STOP: enable HSE/HSI, PLL and select + PLL as system clock source (HSE/HSI and PLL are disabled in STOP mode) */ - __HAL_RCC_HSE_CONFIG(MICROPY_HW_CLK_HSE_STATE); + __HAL_RCC_HSE_CONFIG(MICROPY_HW_RCC_HSE_STATE); + #if MICROPY_HW_CLK_USE_HSI + __HAL_RCC_HSI_ENABLE(); + #endif - /* Wait till HSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + /* Wait till HSE/HSI is ready */ + while(__HAL_RCC_GET_FLAG(MICROPY_HW_RCC_FLAG_HSxRDY) == RESET) {} /* Enable the main PLL. */ |