diff options
author | Damien George <damien@micropython.org> | 2021-06-04 01:17:09 +1000 |
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committer | Damien George <damien@micropython.org> | 2021-06-05 11:03:04 +1000 |
commit | a70a4e6688c6b29797b1e314ce2841e8e4fecb7b (patch) | |
tree | e80ecb4c5ded463235da813735ac2a75ec0f324e /py/asmarm.c | |
parent | fad0efdcf277dcc5698d59445074f4ee806d7976 (diff) |
py/emitglue: Always flush caches when assigning native ARM code.
Prior to this commit, cache flushing for ARM native code was done only in
the assembler code asm_thumb_end_pass()/asm_arm_end_pass(), at the last
pass of the assembler. But this misses flushing the cache when loading
native code from an .mpy file, ie in persistentcode.c.
The change here makes sure the cache is always flushed/cleaned/invalidated
when assigning native code on ARM architectures.
This problem was found running tests/micropython/import_mpy_native_gc.py on
the mimxrt port.
Signed-off-by: Damien George <damien@micropython.org>
Diffstat (limited to 'py/asmarm.c')
-rw-r--r-- | py/asmarm.c | 19 |
1 files changed, 0 insertions, 19 deletions
diff --git a/py/asmarm.c b/py/asmarm.c index 5662d75e1..4ba93d080 100644 --- a/py/asmarm.c +++ b/py/asmarm.c @@ -38,25 +38,6 @@ #define SIGNED_FIT24(x) (((x) & 0xff800000) == 0) || (((x) & 0xff000000) == 0xff000000) -void asm_arm_end_pass(asm_arm_t *as) { - if (as->base.pass == MP_ASM_PASS_EMIT) { - #if (defined(__linux__) && defined(__GNUC__)) || __ARM_ARCH == 7 - char *start = mp_asm_base_get_code(&as->base); - char *end = start + mp_asm_base_get_code_size(&as->base); - __builtin___clear_cache(start, end); - #elif defined(__arm__) - // flush I- and D-cache - asm volatile ( - "0:" - "mrc p15, 0, r15, c7, c10, 3\n" // test and clean D-cache - "bne 0b\n" - "mov r0, #0\n" - "mcr p15, 0, r0, c7, c7, 0\n" // invalidate I-cache and D-cache - : : : "r0", "cc"); - #endif - } -} - // Insert word into instruction flow STATIC void emit(asm_arm_t *as, uint op) { uint8_t *c = mp_asm_base_get_cur_to_write_bytes(&as->base, 4); |