py/emitnative: Improve Viper register-indexed code for Arm.

This commit lets the Viper code generator use optimised code sequences
for register-indexed load and store operations when generating Arm code.

The existing code defaulted to generic multi-operations code sequences
for Arm code on most cases.  Now optimised implementations are provided
for register-indexed loads and stores of all data sizes, taking at most
two machine opcodes for each operation.

Signed-off-by: Alessandro Gatti <a.gatti@frob.it>

1 files changed, 6 insertions, 0 deletions

diff --git a/py/asmarm.h b/py/asmarm.h
index 4a4253aef..20b4757d2 100644
--- a/py/asmarm.h
+++ b/py/asmarm.h
@@ -116,6 +116,12 @@ void asm_arm_ldrb_reg_reg(asm_arm_t *as, uint rd, uint rn);
 void asm_arm_str_reg_reg(asm_arm_t *as, uint rd, uint rm, uint byte_offset);
 void asm_arm_strh_reg_reg(asm_arm_t *as, uint rd, uint rm);
 void asm_arm_strb_reg_reg(asm_arm_t *as, uint rd, uint rm);
+
+// load from array
+void asm_arm_ldr_reg_reg_reg(asm_arm_t *as, uint rd, uint rm, uint rn);
+void asm_arm_ldrh_reg_reg_reg(asm_arm_t *as, uint rd, uint rm, uint rn);
+void asm_arm_ldrb_reg_reg_reg(asm_arm_t *as, uint rd, uint rm, uint rn);
+
 // store to array
 void asm_arm_str_reg_reg_reg(asm_arm_t *as, uint rd, uint rm, uint rn);
 void asm_arm_strh_reg_reg_reg(asm_arm_t *as, uint rd, uint rm, uint rn);