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authorChris Mason <c.mason@inchipdesign.com.au>2019-09-27 14:27:51 +1000
committerDamien George <damien.p.george@gmail.com>2019-10-04 21:39:17 +1000
commit0096041c9912d34a6227f647c264325b178c0384 (patch)
tree62204a4f1fb3bb51522d7a5e7320901658fb47e7 /py/nativeglue.c
parenta09fd0475840ae6a24995ab7ab7955c88289817a (diff)
stm32/{adc,machine_adc}: Change ADC clock and sampling time for F0 MCUs.
STM32F0 has PCLK=48MHz and maximum ADC clock is 14MHz so use PCLK/4=12MHz to stay within spec of the ADC peripheral. In pyb.ADC set common sampling time to approx 4uS for internal and external sources. In machine.ADC reduce sample time to approx 1uS for external source, leave internal at maximum sampling time.
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