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| author | Angus Gratton <angus@redyak.com.au> | 2024-08-15 16:06:19 +1000 |
|---|---|---|
| committer | Damien George <damien@micropython.org> | 2024-08-16 14:22:51 +1000 |
| commit | b6a3aa10f5a223a43971ac22e6db7c967916d70a (patch) | |
| tree | e99598acedf517a83ad261fbbcc3151e6ecbc703 /py/objstr.c | |
| parent | 6565b3cb34954737428f98f0306b7e3cad146482 (diff) | |
esp32: Remove the increased stack limit margin for ESP32-C3.
The extra limit for C3 dates from 6823514 which added C3 support.
Measuring the minimum stack margins that can pass the stress tests I
measured 768 bytes for ESP32-S3 and 512 bytes for ESP32-C3 on ESP-IDF
V5.2.2 and similar on V5.0.4. i.e. The ESP32-C3 actually needs less stack
margin not more!
I think the extra margin for ESP32-C3 probably arose from:
1. Some toolchain inefficiency in the IDF V4.x RISC-V compiler codegen,
that has since been improved.
OR
2. The race condition that was fixed in e3955f42 where sometimes the limit
wasn't set correctly at all. This seems to trigger more on C3, presumably
some timing artifact, and I'd believe that some binaries might be more
susceptible than others due to random factors.
OR
3. Commit 6007f3e2062cc65fc8416f241c682e37eb956c11 which enabled custom
NLR handling for ESP32-C3.
This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>
Diffstat (limited to 'py/objstr.c')
0 files changed, 0 insertions, 0 deletions