py/emitnative: Improve Viper register-indexed code for Arm.

This commit lets the Viper code generator use optimised code sequences
for register-indexed load and store operations when generating Arm code.

The existing code defaulted to generic multi-operations code sequences
for Arm code on most cases.  Now optimised implementations are provided
for register-indexed loads and stores of all data sizes, taking at most
two machine opcodes for each operation.

Signed-off-by: Alessandro Gatti <a.gatti@frob.it>

0 files changed, 0 insertions, 0 deletions